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	diff --git a/sys/gnu/dts/arm/am33xx-l4.dtsi b/sys/gnu/dts/arm/am33xx-l4.dtsi
	index 4e2986f0c604..5ed7f3c58c0f 100644
	--- a/sys/gnu/dts/arm/am33xx-l4.dtsi
	+++ b/sys/gnu/dts/arm/am33xx-l4.dtsi
	@@ -1,2106 +1,2121 @@
	&l4_wkup { /* 0x44c00000 */
	compatible = "ti,am33xx-l4-wkup", "simple-bus";
	reg = <0x44c00000 0x800>,
	<0x44c00800 0x800>,
	<0x44c01000 0x400>,
	<0x44c01400 0x400>;
	reg-names = "ap", "la", "ia0", "ia1";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
	<0x00100000 0x44d00000 0x100000>, /* segment 1 */
	<0x00200000 0x44e00000 0x100000>; /* segment 2 */

	segment@0 { /* 0x44c00000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
	<0x00000800 0x00000800 0x000800>, /* ap 1 */
	<0x00001000 0x00001000 0x000400>, /* ap 2 */
	<0x00001400 0x00001400 0x000400>; /* ap 3 */
	};

	segment@100000 { /* 0x44d00000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */
	<0x00004000 0x00104000 0x001000>, /* ap 5 */
	<0x00080000 0x00180000 0x002000>, /* ap 6 */
	<0x00082000 0x00182000 0x001000>; /* ap 7 */

	target-module@0 { /* 0x44d00000, ap 4 28.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x0 0x4>;
	reg-names = "rev";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x4000>;
	status = "disabled";
	};

	target-module@80000 { /* 0x44d80000, ap 6 10.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x80000 0x2000>;
	};
	};

	segment@200000 { /* 0x44e00000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */
	<0x00002000 0x00202000 0x001000>, /* ap 9 */
	<0x00003000 0x00203000 0x001000>, /* ap 10 */
	<0x00004000 0x00204000 0x001000>, /* ap 11 */
	<0x00005000 0x00205000 0x001000>, /* ap 12 */
	<0x00006000 0x00206000 0x001000>, /* ap 13 */
	<0x00007000 0x00207000 0x001000>, /* ap 14 */
	<0x00008000 0x00208000 0x001000>, /* ap 15 */
	<0x00009000 0x00209000 0x001000>, /* ap 16 */
	<0x0000a000 0x0020a000 0x001000>, /* ap 17 */
	<0x0000b000 0x0020b000 0x001000>, /* ap 18 */
	<0x0000c000 0x0020c000 0x001000>, /* ap 19 */
	<0x0000d000 0x0020d000 0x001000>, /* ap 20 */
	<0x0000f000 0x0020f000 0x001000>, /* ap 21 */
	<0x00010000 0x00210000 0x010000>, /* ap 22 */
	<0x00020000 0x00220000 0x010000>, /* ap 23 */
	<0x00030000 0x00230000 0x001000>, /* ap 24 */
	<0x00031000 0x00231000 0x001000>, /* ap 25 */
	<0x00032000 0x00232000 0x001000>, /* ap 26 */
	<0x00033000 0x00233000 0x001000>, /* ap 27 */
	<0x00034000 0x00234000 0x001000>, /* ap 28 */
	<0x00035000 0x00235000 0x001000>, /* ap 29 */
	<0x00036000 0x00236000 0x001000>, /* ap 30 */
	<0x00037000 0x00237000 0x001000>, /* ap 31 */
	<0x00038000 0x00238000 0x001000>, /* ap 32 */
	<0x00039000 0x00239000 0x001000>, /* ap 33 */
	<0x0003a000 0x0023a000 0x001000>, /* ap 34 */
	<0x0003e000 0x0023e000 0x001000>, /* ap 35 */
	<0x0003f000 0x0023f000 0x001000>, /* ap 36 */
	<0x0000e000 0x0020e000 0x001000>, /* ap 37 */
	<0x00040000 0x00240000 0x040000>, /* ap 38 */
	<0x00080000 0x00280000 0x001000>; /* ap 39 */

	target-module@0 { /* 0x44e00000, ap 8 58.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0 0x4>;
	reg-names = "rev";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x2000>;

	prcm: prcm@0 {
	compatible = "ti,am3-prcm", "simple-bus";
	reg = <0 0x2000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x2000>;

	prcm_clocks: clocks {
	#address-cells = <1>;
	#size-cells = <0>;
	};

	prcm_clockdomains: clockdomains {
	};
	};
	};

	target-module@3000 { /* 0x44e03000, ap 10 0a.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x3000 0x1000>;
	};

	target-module@5000 { /* 0x44e05000, ap 12 30.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x5000 0x1000>;
	};

	gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x7000 0x4>,
	<0x7010 0x4>,
	<0x7114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
	clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>,
	<&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>;
	clock-names = "fck", "dbclk";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x7000 0x1000>;

	gpio0: gpio@0 {
	compatible = "ti,omap4-gpio";
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x0 0x1000>;
	interrupts = <96>;
	};
	};

	target-module@9000 { /* 0x44e09000, ap 16 04.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x9050 0x4>,
	<0x9054 0x4>,
	<0x9058 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
	clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x9000 0x1000>;

	uart0: serial@0 {
	compatible = "ti,am3352-uart", "ti,omap3-uart";
	clock-frequency = <48000000>;
	reg = <0x0 0x1000>;
	interrupts = <72>;
	status = "disabled";
	dmas = <&edma 26 0>, <&edma 27 0>;
	dma-names = "tx", "rx";
	};
	};

	target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xb000 0x8>,
	<0xb010 0x8>,
	<0xb090 0x8>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
	clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xb000 0x1000>;

	i2c0: i2c@0 {
	compatible = "ti,omap4-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x1000>;
	interrupts = <70>;
	status = "disabled";
	};
	};

	target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xd000 0x4>,
	<0xd010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
	clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x0000d000 0x00001000>,
	<0x00001000 0x0000e000 0x00001000>;

	tscadc: tscadc@0 {
	compatible = "ti,am3359-tscadc";
	reg = <0x0 0x1000>;
	interrupts = <16>;
	status = "disabled";
	dmas = <&edma 53 0>, <&edma 57 0>;
	dma-names = "fifo0", "fifo1";

	tsc {
	compatible = "ti,am3359-tsc";
	};
	am335x_adc: adc {
	#io-channel-cells = <1>;
	compatible = "ti,am3359-adc";
	};
	};
	};

	target-module@10000 { /* 0x44e10000, ap 22 0c.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x10000 0x4>;
	reg-names = "rev";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00010000 0x00010000>,
	<0x00010000 0x00020000 0x00010000>;

	scm: scm@0 {
	compatible = "ti,am3-scm", "simple-bus";
	reg = <0x0 0x2000>;
	#address-cells = <1>;
	#size-cells = <1>;
	#pinctrl-cells = <1>;
	ranges = <0 0 0x2000>;

	am33xx_pinmux: pinmux@800 {
	compatible = "pinctrl-single";
	reg = <0x800 0x238>;
	#pinctrl-cells = <1>;
	pinctrl-single,register-width = <32>;
	pinctrl-single,function-mask = <0x7f>;
	};

	scm_conf: scm_conf@0 {
	compatible = "syscon", "simple-bus";
	reg = <0x0 0x800>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x800>;

	phy_gmii_sel: phy-gmii-sel {
	compatible = "ti,am3352-phy-gmii-sel";
	reg = <0x650 0x4>;
	#phy-cells = <2>;
	};

	scm_clocks: clocks {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	usb_ctrl_mod: control@620 {
	compatible = "ti,am335x-usb-ctrl-module";
	reg = <0x620 0x10>,
	<0x648 0x4>;
	reg-names = "phy_ctrl", "wakeup";
	};

	wkup_m3_ipc: wkup_m3_ipc@1324 {
	compatible = "ti,am3352-wkup-m3-ipc";
	reg = <0x1324 0x24>;
	interrupts = <78>;
	ti,rproc = <&wkup_m3>;
	mboxes = <&mailbox &mbox_wkupm3>;
	};

	edma_xbar: dma-router@f90 {
	compatible = "ti,am335x-edma-crossbar";
	reg = <0xf90 0x40>;
	#dma-cells = <3>;
	dma-requests = <32>;
	dma-masters = <&edma>;
	};

	scm_clockdomains: clockdomains {
	};
	};
	};

	target-module@31000 { /* 0x44e31000, ap 25 40.0 */
	compatible = "ti,sysc-omap2-timer", "ti,sysc";
	ti,hwmods = "timer1";
	reg = <0x31000 0x4>,
	<0x31010 0x4>,
	<0x31014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
	clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x31000 0x1000>;

	timer1: timer@0 {
	compatible = "ti,am335x-timer-1ms";
	reg = <0x0 0x400>;
	interrupts = <67>;
	ti,timer-alwon;
	clocks = <&timer1_fck>;
	clock-names = "fck";
	};
	};

	target-module@33000 { /* 0x44e33000, ap 27 18.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x33000 0x1000>;
	};

	target-module@35000 { /* 0x44e35000, ap 29 50.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x35000 0x4>,
	<0x35010 0x4>,
	<0x35014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_EMUFREE \|
	SYSC_OMAP2_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
	clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x35000 0x1000>;

	wdt2: wdt@0 {
	compatible = "ti,omap3-wdt";
	reg = <0x0 0x1000>;
	interrupts = <91>;
	};
	};

	target-module@37000 { /* 0x44e37000, ap 31 08.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x37000 0x1000>;
	};

	target-module@39000 { /* 0x44e39000, ap 33 02.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x39000 0x1000>;
	};

	target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */
	compatible = "ti,sysc-omap4-simple", "ti,sysc";
	ti,hwmods = "rtc";
	reg = <0x3e074 0x4>,
	<0x3e078 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */
	clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x3e000 0x1000>;

	rtc: rtc@0 {
	compatible = "ti,am3352-rtc", "ti,da830-rtc";
	reg = <0x0 0x1000>;
	interrupts = <75
	76>;
	};
	};

	target-module@40000 { /* 0x44e40000, ap 38 68.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x40000 0x40000>;
	};
	};
	};

	&l4_fw { /* 0x47c00000 */
	compatible = "ti,am33xx-l4-fw", "simple-bus";
	reg = <0x47c00000 0x800>,
	<0x47c00800 0x800>,
	<0x47c01000 0x400>;
	reg-names = "ap", "la", "ia0";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */

	segment@0 { /* 0x47c00000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
	<0x00000800 0x00000800 0x000800>, /* ap 1 */
	<0x00001000 0x00001000 0x000400>, /* ap 2 */
	<0x0000c000 0x0000c000 0x001000>, /* ap 3 */
	<0x0000d000 0x0000d000 0x001000>, /* ap 4 */
	<0x0000e000 0x0000e000 0x001000>, /* ap 5 */
	<0x0000f000 0x0000f000 0x001000>, /* ap 6 */
	<0x00010000 0x00010000 0x001000>, /* ap 7 */
	<0x00011000 0x00011000 0x001000>, /* ap 8 */
	<0x0001a000 0x0001a000 0x001000>, /* ap 9 */
	<0x0001b000 0x0001b000 0x001000>, /* ap 10 */
	<0x00024000 0x00024000 0x001000>, /* ap 11 */
	<0x00025000 0x00025000 0x001000>, /* ap 12 */
	<0x00026000 0x00026000 0x001000>, /* ap 13 */
	<0x00027000 0x00027000 0x001000>, /* ap 14 */
	<0x00030000 0x00030000 0x001000>, /* ap 15 */
	<0x00031000 0x00031000 0x001000>, /* ap 16 */
	<0x00038000 0x00038000 0x001000>, /* ap 17 */
	<0x00039000 0x00039000 0x001000>, /* ap 18 */
	<0x0003a000 0x0003a000 0x001000>, /* ap 19 */
	<0x0003b000 0x0003b000 0x001000>, /* ap 20 */
	<0x0003e000 0x0003e000 0x001000>, /* ap 21 */
	<0x0003f000 0x0003f000 0x001000>, /* ap 22 */
	<0x0003c000 0x0003c000 0x001000>, /* ap 23 */
	<0x00040000 0x00040000 0x001000>, /* ap 24 */
	<0x00046000 0x00046000 0x001000>, /* ap 25 */
	<0x00047000 0x00047000 0x001000>, /* ap 26 */
	<0x00044000 0x00044000 0x001000>, /* ap 27 */
	<0x00045000 0x00045000 0x001000>, /* ap 28 */
	<0x00028000 0x00028000 0x001000>, /* ap 29 */
	<0x00029000 0x00029000 0x001000>, /* ap 30 */
	<0x00032000 0x00032000 0x001000>, /* ap 31 */
	<0x00033000 0x00033000 0x001000>, /* ap 32 */
	<0x0003d000 0x0003d000 0x001000>, /* ap 33 */
	<0x00041000 0x00041000 0x001000>, /* ap 34 */
	<0x00042000 0x00042000 0x001000>, /* ap 35 */
	<0x00043000 0x00043000 0x001000>, /* ap 36 */
	<0x00014000 0x00014000 0x001000>, /* ap 37 */
	<0x00015000 0x00015000 0x001000>; /* ap 38 */

	target-module@c000 { /* 0x47c0c000, ap 3 04.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xc000 0x1000>;
	};

	target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xe000 0x1000>;
	};

	target-module@10000 { /* 0x47c10000, ap 7 20.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x10000 0x1000>;
	};

	target-module@14000 { /* 0x47c14000, ap 37 3c.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x14000 0x1000>;
	};

	target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x1a000 0x1000>;
	};

	target-module@24000 { /* 0x47c24000, ap 11 28.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x24000 0x1000>;
	};

	target-module@26000 { /* 0x47c26000, ap 13 30.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x26000 0x1000>;
	};

	target-module@28000 { /* 0x47c28000, ap 29 40.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x28000 0x1000>;
	};

	target-module@30000 { /* 0x47c30000, ap 15 14.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x30000 0x1000>;
	};

	target-module@32000 { /* 0x47c32000, ap 31 06.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x32000 0x1000>;
	};

	target-module@38000 { /* 0x47c38000, ap 17 18.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x38000 0x1000>;
	};

	target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x3a000 0x1000>;
	};

	target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x3c000 0x1000>;
	};

	target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x3e000 0x1000>;
	};

	target-module@40000 { /* 0x47c40000, ap 24 02.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x40000 0x1000>;
	};

	target-module@42000 { /* 0x47c42000, ap 35 34.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x42000 0x1000>;
	};

	target-module@44000 { /* 0x47c44000, ap 27 24.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x44000 0x1000>;
	};

	target-module@46000 { /* 0x47c46000, ap 25 2c.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x46000 0x1000>;
	};
	};
	};

	&l4_fast { /* 0x4a000000 */
	compatible = "ti,am33xx-l4-fast", "simple-bus";
	reg = <0x4a000000 0x800>,
	<0x4a000800 0x800>,
	<0x4a001000 0x400>;
	reg-names = "ap", "la", "ia0";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */

	segment@0 { /* 0x4a000000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
	<0x00000800 0x00000800 0x000800>, /* ap 1 */
	<0x00001000 0x00001000 0x000400>, /* ap 2 */
	<0x00100000 0x00100000 0x008000>, /* ap 3 */
	<0x00108000 0x00108000 0x001000>, /* ap 4 */
	<0x00180000 0x00180000 0x020000>, /* ap 5 */
	<0x001a0000 0x001a0000 0x001000>, /* ap 6 */
	<0x00200000 0x00200000 0x080000>, /* ap 7 */
	<0x00280000 0x00280000 0x001000>, /* ap 8 */
	<0x00300000 0x00300000 0x080000>, /* ap 9 */
	<0x00380000 0x00380000 0x001000>; /* ap 10 */

	target-module@100000 { /* 0x4a100000, ap 3 08.0 */
	compatible = "ti,sysc-omap4-simple", "ti,sysc";
	reg = <0x101200 0x4>,
	<0x101208 0x4>,
	<0x101204 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <0>;
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>;
	ti,syss-mask = <1>;
	clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x100000 0x8000>;

	mac: ethernet@0 {
	compatible = "ti,am335x-cpsw","ti,cpsw";
	clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
	clock-names = "fck", "cpts";
	cpdma_channels = <8>;
	ale_entries = <1024>;
	bd_ram_size = <0x2000>;
	mac_control = <0x20>;
	slaves = <2>;
	active_slave = <0>;
	cpts_clock_mult = <0x80000000>;
	cpts_clock_shift = <29>;
	reg = <0x0 0x800
	0x1200 0x100>;
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	* c0_rx_thresh_pend
	* c0_rx_pend
	* c0_tx_pend
	* c0_misc_pend
	*/
	interrupts = <40 41 42 43>;
	ranges = <0 0 0x8000>;
	syscon = <&scm_conf>;
	status = "disabled";

	davinci_mdio: mdio@1000 {
	compatible = "ti,cpsw-mdio","ti,davinci_mdio";
	clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <0>;
	bus_freq = <1000000>;
	reg = <0x1000 0x100>;
	status = "disabled";
	};

	cpsw_emac0: slave@200 {
	/* Filled in by U-Boot */
	mac-address = [ 00 00 00 00 00 00 ];
	phys = <&phy_gmii_sel 1 1>;
	};

	cpsw_emac1: slave@300 {
	/* Filled in by U-Boot */
	mac-address = [ 00 00 00 00 00 00 ];
	phys = <&phy_gmii_sel 2 1>;
	};
	};
	};

	target-module@180000 { /* 0x4a180000, ap 5 10.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x180000 0x20000>;
	};

	target-module@200000 { /* 0x4a200000, ap 7 02.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x200000 0x80000>;
	};

	- target-module@300000 { /* 0x4a300000, ap 9 04.0 */
	- compatible = "ti,sysc";
	- status = "disabled";
	+ pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
	+ compatible = "ti,sysc-pruss", "ti,sysc";
	+ reg = <0x326000 0x4>,
	+ <0x326004 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT \|
	+ SYSC_PRUSS_SUB_MWAIT)>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>;
	+ clock-names = "fck";
	+ resets = <&prm_per 1>;
	+ reset-names = "rstctrl";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x300000 0x80000>;
	+ status = "disabled";
	};
	};
	};

	&l4_mpuss { /* 0x4b140000 */
	compatible = "ti,am33xx-l4-mpuss", "simple-bus";
	reg = <0x4b144400 0x100>,
	<0x4b144800 0x400>;
	reg-names = "la", "ap";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */

	segment@0 { /* 0x4b140000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */
	<0x00001000 0x00001000 0x001000>, /* ap 1 */
	<0x00002000 0x00002000 0x001000>, /* ap 2 */
	<0x00004000 0x00004000 0x000400>, /* ap 3 */
	<0x00005000 0x00005000 0x000400>, /* ap 4 */
	<0x00000000 0x00000000 0x001000>, /* ap 5 */
	<0x00003000 0x00003000 0x001000>, /* ap 6 */
	<0x00000800 0x00000800 0x000800>; /* ap 7 */

	target-module@0 { /* 0x4b140000, ap 5 02.2 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00000000 0x00001000>,
	<0x00001000 0x00001000 0x00001000>,
	<0x00002000 0x00002000 0x00001000>;
	};

	target-module@3000 { /* 0x4b143000, ap 6 04.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x3000 0x1000>;
	};
	};
	};

	&l4_per { /* 0x48000000 */
	compatible = "ti,am33xx-l4-per", "simple-bus";
	reg = <0x48000000 0x800>,
	<0x48000800 0x800>,
	<0x48001000 0x400>,
	<0x48001400 0x400>,
	<0x48001800 0x400>,
	<0x48001c00 0x400>;
	reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */
	<0x00100000 0x48100000 0x100000>, /* segment 1 */
	<0x00200000 0x48200000 0x100000>, /* segment 2 */
	<0x00300000 0x48300000 0x100000>, /* segment 3 */
	<0x46000000 0x46000000 0x400000>, /* l3 data port */
	<0x46400000 0x46400000 0x400000>; /* l3 data port */

	segment@0 { /* 0x48000000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
	<0x00000800 0x00000800 0x000800>, /* ap 1 */
	<0x00001000 0x00001000 0x000400>, /* ap 2 */
	<0x00001400 0x00001400 0x000400>, /* ap 3 */
	<0x00001800 0x00001800 0x000400>, /* ap 4 */
	<0x00001c00 0x00001c00 0x000400>, /* ap 5 */
	<0x00008000 0x00008000 0x001000>, /* ap 6 */
	<0x00009000 0x00009000 0x001000>, /* ap 7 */
	<0x00016000 0x00016000 0x001000>, /* ap 8 */
	<0x00017000 0x00017000 0x001000>, /* ap 9 */
	<0x00022000 0x00022000 0x001000>, /* ap 10 */
	<0x00023000 0x00023000 0x001000>, /* ap 11 */
	<0x00024000 0x00024000 0x001000>, /* ap 12 */
	<0x00025000 0x00025000 0x001000>, /* ap 13 */
	<0x0002a000 0x0002a000 0x001000>, /* ap 14 */
	<0x0002b000 0x0002b000 0x001000>, /* ap 15 */
	<0x00038000 0x00038000 0x002000>, /* ap 16 */
	<0x0003a000 0x0003a000 0x001000>, /* ap 17 */
	<0x00014000 0x00014000 0x001000>, /* ap 18 */
	<0x00015000 0x00015000 0x001000>, /* ap 19 */
	<0x0003c000 0x0003c000 0x002000>, /* ap 20 */
	<0x0003e000 0x0003e000 0x001000>, /* ap 21 */
	<0x00040000 0x00040000 0x001000>, /* ap 22 */
	<0x00041000 0x00041000 0x001000>, /* ap 23 */
	<0x00042000 0x00042000 0x001000>, /* ap 24 */
	<0x00043000 0x00043000 0x001000>, /* ap 25 */
	<0x00044000 0x00044000 0x001000>, /* ap 26 */
	<0x00045000 0x00045000 0x001000>, /* ap 27 */
	<0x00046000 0x00046000 0x001000>, /* ap 28 */
	<0x00047000 0x00047000 0x001000>, /* ap 29 */
	<0x00048000 0x00048000 0x001000>, /* ap 30 */
	<0x00049000 0x00049000 0x001000>, /* ap 31 */
	<0x0004c000 0x0004c000 0x001000>, /* ap 32 */
	<0x0004d000 0x0004d000 0x001000>, /* ap 33 */
	<0x00050000 0x00050000 0x002000>, /* ap 34 */
	<0x00052000 0x00052000 0x001000>, /* ap 35 */
	<0x00060000 0x00060000 0x001000>, /* ap 36 */
	<0x00061000 0x00061000 0x001000>, /* ap 37 */
	<0x00080000 0x00080000 0x010000>, /* ap 38 */
	<0x00090000 0x00090000 0x001000>, /* ap 39 */
	<0x000a0000 0x000a0000 0x010000>, /* ap 40 */
	<0x000b0000 0x000b0000 0x001000>, /* ap 41 */
	<0x00030000 0x00030000 0x001000>, /* ap 77 */
	<0x00031000 0x00031000 0x001000>, /* ap 78 */
	<0x0004a000 0x0004a000 0x001000>, /* ap 85 */
	<0x0004b000 0x0004b000 0x001000>, /* ap 86 */
	<0x000c8000 0x000c8000 0x001000>, /* ap 87 */
	<0x000c9000 0x000c9000 0x001000>, /* ap 88 */
	<0x000cc000 0x000cc000 0x001000>, /* ap 89 */
	<0x000cd000 0x000cd000 0x001000>, /* ap 90 */
	<0x000ca000 0x000ca000 0x001000>, /* ap 91 */
	<0x000cb000 0x000cb000 0x001000>, /* ap 92 */
	<0x46000000 0x46000000 0x400000>, /* l3 data port */
	<0x46400000 0x46400000 0x400000>; /* l3 data port */

	target-module@8000 { /* 0x48008000, ap 6 10.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x8000 0x1000>;
	};

	target-module@14000 { /* 0x48014000, ap 18 58.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x14000 0x1000>;
	};

	target-module@16000 { /* 0x48016000, ap 8 3c.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x16000 0x1000>;
	};

	target-module@22000 { /* 0x48022000, ap 10 12.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x22050 0x4>,
	<0x22054 0x4>,
	<0x22058 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x22000 0x1000>;

	uart1: serial@0 {
	compatible = "ti,am3352-uart", "ti,omap3-uart";
	clock-frequency = <48000000>;
	reg = <0x0 0x1000>;
	interrupts = <73>;
	status = "disabled";
	dmas = <&edma 28 0>, <&edma 29 0>;
	dma-names = "tx", "rx";
	};
	};

	target-module@24000 { /* 0x48024000, ap 12 14.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x24050 0x4>,
	<0x24054 0x4>,
	<0x24058 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x24000 0x1000>;

	uart2: serial@0 {
	compatible = "ti,am3352-uart", "ti,omap3-uart";
	clock-frequency = <48000000>;
	reg = <0x0 0x1000>;
	interrupts = <74>;
	status = "disabled";
	dmas = <&edma 30 0>, <&edma 31 0>;
	dma-names = "tx", "rx";
	};
	};

	target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x2a000 0x8>,
	<0x2a010 0x8>,
	<0x2a090 0x8>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x2a000 0x1000>;

	i2c1: i2c@0 {
	compatible = "ti,omap4-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x1000>;
	interrupts = <71>;
	status = "disabled";
	};
	};

	target-module@30000 { /* 0x48030000, ap 77 08.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x30000 0x4>,
	<0x30110 0x4>,
	<0x30114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x30000 0x1000>;

	spi0: spi@0 {
	compatible = "ti,omap4-mcspi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x400>;
	interrupts = <65>;
	ti,spi-num-cs = <2>;
	dmas = <&edma 16 0
	&edma 17 0
	&edma 18 0
	&edma 19 0>;
	dma-names = "tx0", "rx0", "tx1", "rx1";
	status = "disabled";
	};
	};

	target-module@38000 { /* 0x48038000, ap 16 02.0 */
	compatible = "ti,sysc-omap4-simple", "ti,sysc";
	reg = <0x38000 0x4>,
	<0x38004 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	/* Domains (P, C): per_pwrdm, l3s_clkdm */
	clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x38000 0x2000>,
	<0x46000000 0x46000000 0x400000>;

	mcasp0: mcasp@0 {
	compatible = "ti,am33xx-mcasp-audio";
	reg = <0x0 0x2000>,
	<0x46000000 0x400000>;
	reg-names = "mpu", "dat";
	interrupts = <80>, <81>;
	interrupt-names = "tx", "rx";
	status = "disabled";
	dmas = <&edma 8 2>,
	<&edma 9 2>;
	dma-names = "tx", "rx";
	};
	};

	target-module@3c000 { /* 0x4803c000, ap 20 32.0 */
	compatible = "ti,sysc-omap4-simple", "ti,sysc";
	reg = <0x3c000 0x4>,
	<0x3c004 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	/* Domains (P, C): per_pwrdm, l3s_clkdm */
	clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x3c000 0x2000>,
	<0x46400000 0x46400000 0x400000>;

	mcasp1: mcasp@0 {
	compatible = "ti,am33xx-mcasp-audio";
	reg = <0x0 0x2000>,
	<0x46400000 0x400000>;
	reg-names = "mpu", "dat";
	interrupts = <82>, <83>;
	interrupt-names = "tx", "rx";
	status = "disabled";
	dmas = <&edma 10 2>,
	<&edma 11 2>;
	dma-names = "tx", "rx";
	};
	};

	target-module@40000 { /* 0x48040000, ap 22 1e.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	ti,hwmods = "timer2";
	reg = <0x40000 0x4>,
	<0x40010 0x4>,
	<0x40014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x40000 0x1000>;

	timer2: timer@0 {
	compatible = "ti,am335x-timer";
	reg = <0x0 0x400>;
	interrupts = <68>;
	clocks = <&timer2_fck>;
	clock-names = "fck";
	};
	};

	target-module@42000 { /* 0x48042000, ap 24 1c.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x42000 0x4>,
	<0x42010 0x4>,
	<0x42014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x42000 0x1000>;

	timer3: timer@0 {
	compatible = "ti,am335x-timer";
	reg = <0x0 0x400>;
	interrupts = <69>;
	};
	};

	target-module@44000 { /* 0x48044000, ap 26 26.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x44000 0x4>,
	<0x44010 0x4>,
	<0x44014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x44000 0x1000>;

	timer4: timer@0 {
	compatible = "ti,am335x-timer";
	reg = <0x0 0x400>;
	interrupts = <92>;
	ti,timer-pwm;
	};
	};

	target-module@46000 { /* 0x48046000, ap 28 28.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x46000 0x4>,
	<0x46010 0x4>,
	<0x46014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x46000 0x1000>;

	timer5: timer@0 {
	compatible = "ti,am335x-timer";
	reg = <0x0 0x400>;
	interrupts = <93>;
	ti,timer-pwm;
	};
	};

	target-module@48000 { /* 0x48048000, ap 30 22.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x48000 0x4>,
	<0x48010 0x4>,
	<0x48014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x48000 0x1000>;

	timer6: timer@0 {
	compatible = "ti,am335x-timer";
	reg = <0x0 0x400>;
	interrupts = <94>;
	ti,timer-pwm;
	};
	};

	target-module@4a000 { /* 0x4804a000, ap 85 60.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x4a000 0x4>,
	<0x4a010 0x4>,
	<0x4a014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4a000 0x1000>;

	timer7: timer@0 {
	compatible = "ti,am335x-timer";
	reg = <0x0 0x400>;
	interrupts = <95>;
	ti,timer-pwm;
	};
	};

	target-module@4c000 { /* 0x4804c000, ap 32 36.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x4c000 0x4>,
	<0x4c010 0x4>,
	<0x4c114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>,
	<&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>;
	clock-names = "fck", "dbclk";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4c000 0x1000>;

	gpio1: gpio@0 {
	compatible = "ti,omap4-gpio";
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x0 0x1000>;
	interrupts = <98>;
	};
	};

	target-module@50000 { /* 0x48050000, ap 34 2c.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x50000 0x2000>;
	};

	target-module@60000 { /* 0x48060000, ap 36 0c.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x602fc 0x4>,
	<0x60110 0x4>,
	<0x60114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x60000 0x1000>;

	mmc1: mmc@0 {
	compatible = "ti,omap4-hsmmc";
	ti,dual-volt;
	ti,needs-special-reset;
	ti,needs-special-hs-handling;
	dmas = <&edma_xbar 24 0 0
	&edma_xbar 25 0 0>;
	dma-names = "tx", "rx";
	interrupts = <64>;
	reg = <0x0 0x1000>;
	status = "disabled";
	};
	};

	target-module@80000 { /* 0x48080000, ap 38 18.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x80000 0x4>,
	<0x80010 0x4>,
	<0x80014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x80000 0x10000>;

	elm: elm@0 {
	compatible = "ti,am3352-elm";
	reg = <0x0 0x2000>;
	interrupts = <4>;
	status = "disabled";
	};
	};

	target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa0000 0x10000>;
	};

	target-module@c8000 { /* 0x480c8000, ap 87 06.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xc8000 0x4>,
	<0xc8010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xc8000 0x1000>;

	mailbox: mailbox@0 {
	compatible = "ti,omap4-mailbox";
	reg = <0x0 0x200>;
	interrupts = <77>;
	#mbox-cells = <1>;
	ti,mbox-num-users = <4>;
	ti,mbox-num-fifos = <8>;
	mbox_wkupm3: wkup_m3 {
	ti,mbox-send-noirq;
	ti,mbox-tx = <0 0 0>;
	ti,mbox-rx = <0 0 3>;
	};
	};
	};

	target-module@ca000 { /* 0x480ca000, ap 91 40.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xca000 0x4>,
	<0xca010 0x4>,
	<0xca014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xca000 0x1000>;

	hwspinlock: spinlock@0 {
	compatible = "ti,omap4-hwspinlock";
	reg = <0x0 0x1000>;
	#hwlock-cells = <1>;
	};
	};

	target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xcc000 0x1000>;
	};
	};

	segment@100000 { /* 0x48100000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */
	<0x0008d000 0x0018d000 0x001000>, /* ap 43 */
	<0x0008e000 0x0018e000 0x001000>, /* ap 44 */
	<0x0008f000 0x0018f000 0x001000>, /* ap 45 */
	<0x0009c000 0x0019c000 0x001000>, /* ap 46 */
	<0x0009d000 0x0019d000 0x001000>, /* ap 47 */
	<0x000a6000 0x001a6000 0x001000>, /* ap 48 */
	<0x000a7000 0x001a7000 0x001000>, /* ap 49 */
	<0x000a8000 0x001a8000 0x001000>, /* ap 50 */
	<0x000a9000 0x001a9000 0x001000>, /* ap 51 */
	<0x000aa000 0x001aa000 0x001000>, /* ap 52 */
	<0x000ab000 0x001ab000 0x001000>, /* ap 53 */
	<0x000ac000 0x001ac000 0x001000>, /* ap 54 */
	<0x000ad000 0x001ad000 0x001000>, /* ap 55 */
	<0x000ae000 0x001ae000 0x001000>, /* ap 56 */
	<0x000af000 0x001af000 0x001000>, /* ap 57 */
	<0x000b0000 0x001b0000 0x010000>, /* ap 58 */
	<0x000c0000 0x001c0000 0x001000>, /* ap 59 */
	<0x000cc000 0x001cc000 0x002000>, /* ap 60 */
	<0x000ce000 0x001ce000 0x002000>, /* ap 61 */
	<0x000d0000 0x001d0000 0x002000>, /* ap 62 */
	<0x000d2000 0x001d2000 0x002000>, /* ap 63 */
	<0x000d8000 0x001d8000 0x001000>, /* ap 64 */
	<0x000d9000 0x001d9000 0x001000>, /* ap 65 */
	<0x000a0000 0x001a0000 0x001000>, /* ap 79 */
	<0x000a1000 0x001a1000 0x001000>, /* ap 80 */
	<0x000a2000 0x001a2000 0x001000>, /* ap 81 */
	<0x000a3000 0x001a3000 0x001000>, /* ap 82 */
	<0x000a4000 0x001a4000 0x001000>, /* ap 83 */
	<0x000a5000 0x001a5000 0x001000>; /* ap 84 */

	target-module@8c000 { /* 0x4818c000, ap 42 04.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x8c000 0x1000>;
	};

	target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x8e000 0x1000>;
	};

	target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x9c000 0x8>,
	<0x9c010 0x8>,
	<0x9c090 0x8>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x9c000 0x1000>;

	i2c2: i2c@0 {
	compatible = "ti,omap4-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x1000>;
	interrupts = <30>;
	status = "disabled";
	};
	};

	target-module@a0000 { /* 0x481a0000, ap 79 24.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xa0000 0x4>,
	<0xa0110 0x4>,
	<0xa0114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa0000 0x1000>;

	spi1: spi@0 {
	compatible = "ti,omap4-mcspi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x400>;
	interrupts = <125>;
	ti,spi-num-cs = <2>;
	dmas = <&edma 42 0
	&edma 43 0
	&edma 44 0
	&edma 45 0>;
	dma-names = "tx0", "rx0", "tx1", "rx1";
	status = "disabled";
	};
	};

	target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa2000 0x1000>;
	};

	target-module@a4000 { /* 0x481a4000, ap 83 30.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa4000 0x1000>;
	};

	target-module@a6000 { /* 0x481a6000, ap 48 16.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xa6050 0x4>,
	<0xa6054 0x4>,
	<0xa6058 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa6000 0x1000>;

	uart3: serial@0 {
	compatible = "ti,am3352-uart", "ti,omap3-uart";
	clock-frequency = <48000000>;
	reg = <0x0 0x1000>;
	interrupts = <44>;
	status = "disabled";
	};
	};

	target-module@a8000 { /* 0x481a8000, ap 50 20.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xa8050 0x4>,
	<0xa8054 0x4>,
	<0xa8058 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa8000 0x1000>;

	uart4: serial@0 {
	compatible = "ti,am3352-uart", "ti,omap3-uart";
	clock-frequency = <48000000>;
	reg = <0x0 0x1000>;
	interrupts = <45>;
	status = "disabled";
	};
	};

	target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xaa050 0x4>,
	<0xaa054 0x4>,
	<0xaa058 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xaa000 0x1000>;

	uart5: serial@0 {
	compatible = "ti,am3352-uart", "ti,omap3-uart";
	clock-frequency = <48000000>;
	reg = <0x0 0x1000>;
	interrupts = <46>;
	status = "disabled";
	};
	};

	target-module@ac000 { /* 0x481ac000, ap 54 38.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xac000 0x4>,
	<0xac010 0x4>,
	<0xac114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>,
	<&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>;
	clock-names = "fck", "dbclk";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xac000 0x1000>;

	gpio2: gpio@0 {
	compatible = "ti,omap4-gpio";
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x0 0x1000>;
	interrupts = <32>;
	};
	};

	target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xae000 0x4>,
	<0xae010 0x4>,
	<0xae114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>,
	<&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>;
	clock-names = "fck", "dbclk";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xae000 0x1000>;

	gpio3: gpio@0 {
	compatible = "ti,omap4-gpio";
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x0 0x1000>;
	interrupts = <62>;
	};
	};

	target-module@b0000 { /* 0x481b0000, ap 58 50.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xb0000 0x10000>;
	};

	target-module@cc000 { /* 0x481cc000, ap 60 46.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xcc020 0x4>;
	reg-names = "rev";
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
	<&dcan0_fck>;
	clock-names = "fck", "osc";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xcc000 0x2000>;

	dcan0: can@0 {
	compatible = "ti,am3352-d_can";
	reg = <0x0 0x2000>;
	clocks = <&dcan0_fck>;
	clock-names = "fck";
	syscon-raminit = <&scm_conf 0x644 0>;
	interrupts = <52>;
	status = "disabled";
	};
	};

	target-module@d0000 { /* 0x481d0000, ap 62 42.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xd0020 0x4>;
	reg-names = "rev";
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
	<&dcan1_fck>;
	clock-names = "fck", "osc";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xd0000 0x2000>;

	dcan1: can@0 {
	compatible = "ti,am3352-d_can";
	reg = <0x0 0x2000>;
	clocks = <&dcan1_fck>;
	clock-names = "fck";
	syscon-raminit = <&scm_conf 0x644 1>;
	interrupts = <55>;
	status = "disabled";
	};
	};

	target-module@d8000 { /* 0x481d8000, ap 64 66.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xd82fc 0x4>,
	<0xd8110 0x4>,
	<0xd8114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xd8000 0x1000>;

	mmc2: mmc@0 {
	compatible = "ti,omap4-hsmmc";
	ti,needs-special-reset;
	dmas = <&edma 2 0
	&edma 3 0>;
	dma-names = "tx", "rx";
	interrupts = <28>;
	reg = <0x0 0x1000>;
	status = "disabled";
	};
	};
	};

	segment@200000 { /* 0x48200000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	};

	segment@300000 { /* 0x48300000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */
	<0x00001000 0x00301000 0x001000>, /* ap 67 */
	<0x00002000 0x00302000 0x001000>, /* ap 68 */
	<0x00003000 0x00303000 0x001000>, /* ap 69 */
	<0x00004000 0x00304000 0x001000>, /* ap 70 */
	<0x00005000 0x00305000 0x001000>, /* ap 71 */
	<0x0000e000 0x0030e000 0x001000>, /* ap 72 */
	<0x0000f000 0x0030f000 0x001000>, /* ap 73 */
	<0x00018000 0x00318000 0x004000>, /* ap 74 */
	<0x0001c000 0x0031c000 0x001000>, /* ap 75 */
	<0x00010000 0x00310000 0x002000>, /* ap 76 */
	<0x00012000 0x00312000 0x001000>, /* ap 93 */
	<0x00015000 0x00315000 0x001000>, /* ap 94 */
	<0x00016000 0x00316000 0x001000>, /* ap 95 */
	<0x00017000 0x00317000 0x001000>, /* ap 96 */
	<0x00013000 0x00313000 0x001000>, /* ap 97 */
	<0x00014000 0x00314000 0x001000>, /* ap 98 */
	<0x00020000 0x00320000 0x001000>, /* ap 99 */
	<0x00021000 0x00321000 0x001000>, /* ap 100 */
	<0x00022000 0x00322000 0x001000>, /* ap 101 */
	<0x00023000 0x00323000 0x001000>, /* ap 102 */
	<0x00024000 0x00324000 0x001000>, /* ap 103 */
	<0x00025000 0x00325000 0x001000>; /* ap 104 */

	target-module@0 { /* 0x48300000, ap 66 48.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x0 0x4>,
	<0x4 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x1000>;

	epwmss0: epwmss@0 {
	compatible = "ti,am33xx-pwmss";
	reg = <0x0 0x10>;
	#address-cells = <1>;
	#size-cells = <1>;
	status = "disabled";
	ranges = <0 0 0x1000>;

	ecap0: ecap@100 {
	compatible = "ti,am3352-ecap",
	"ti,am33xx-ecap";
	#pwm-cells = <3>;
	reg = <0x100 0x80>;
	clocks = <&l4ls_gclk>;
	clock-names = "fck";
	interrupts = <31>;
	interrupt-names = "ecap0";
	status = "disabled";
	};

	ehrpwm0: pwm@200 {
	compatible = "ti,am3352-ehrpwm",
	"ti,am33xx-ehrpwm";
	#pwm-cells = <3>;
	reg = <0x200 0x80>;
	clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
	clock-names = "tbclk", "fck";
	status = "disabled";
	};
	};
	};

	target-module@2000 { /* 0x48302000, ap 68 52.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x2000 0x4>,
	<0x2004 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x2000 0x1000>;

	epwmss1: epwmss@0 {
	compatible = "ti,am33xx-pwmss";
	reg = <0x0 0x10>;
	#address-cells = <1>;
	#size-cells = <1>;
	status = "disabled";
	ranges = <0 0 0x1000>;

	ecap1: ecap@100 {
	compatible = "ti,am3352-ecap",
	"ti,am33xx-ecap";
	#pwm-cells = <3>;
	reg = <0x100 0x80>;
	clocks = <&l4ls_gclk>;
	clock-names = "fck";
	interrupts = <47>;
	interrupt-names = "ecap1";
	status = "disabled";
	};

	ehrpwm1: pwm@200 {
	compatible = "ti,am3352-ehrpwm",
	"ti,am33xx-ehrpwm";
	#pwm-cells = <3>;
	reg = <0x200 0x80>;
	clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
	clock-names = "tbclk", "fck";
	status = "disabled";
	};
	};
	};

	target-module@4000 { /* 0x48304000, ap 70 44.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x4000 0x4>,
	<0x4004 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4000 0x1000>;

	epwmss2: epwmss@0 {
	compatible = "ti,am33xx-pwmss";
	reg = <0x0 0x10>;
	#address-cells = <1>;
	#size-cells = <1>;
	status = "disabled";
	ranges = <0 0 0x1000>;

	ecap2: ecap@100 {
	compatible = "ti,am3352-ecap",
	"ti,am33xx-ecap";
	#pwm-cells = <3>;
	reg = <0x100 0x80>;
	clocks = <&l4ls_gclk>;
	clock-names = "fck";
	interrupts = <61>;
	interrupt-names = "ecap2";
	status = "disabled";
	};

	ehrpwm2: pwm@200 {
	compatible = "ti,am3352-ehrpwm",
	"ti,am33xx-ehrpwm";
	#pwm-cells = <3>;
	reg = <0x200 0x80>;
	clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
	clock-names = "tbclk", "fck";
	status = "disabled";
	};
	};
	};

	target-module@e000 { /* 0x4830e000, ap 72 4a.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xe000 0x4>,
	<0xe054 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	/* Domains (P, C): per_pwrdm, lcdc_clkdm */
	clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xe000 0x1000>;

	lcdc: lcdc@0 {
	compatible = "ti,am33xx-tilcdc";
	reg = <0x0 0x1000>;
	interrupts = <36>;
	status = "disabled";
	};
	};

	target-module@10000 { /* 0x48310000, ap 76 4e.1 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x11fe0 0x4>,
	<0x11fe4 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x10000 0x2000>;

	rng: rng@0 {
	compatible = "ti,omap4-rng";
	reg = <0x0 0x2000>;
	interrupts = <111>;
	};
	};

	target-module@13000 { /* 0x48313000, ap 97 62.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x13000 0x1000>;
	};

	target-module@15000 { /* 0x48315000, ap 94 56.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00015000 0x00001000>,
	<0x00001000 0x00016000 0x00001000>;
	};

	target-module@18000 { /* 0x48318000, ap 74 4c.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x18000 0x4000>;
	};

	target-module@20000 { /* 0x48320000, ap 99 34.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x20000 0x1000>;
	};

	target-module@22000 { /* 0x48322000, ap 101 3e.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x22000 0x1000>;
	};

	target-module@24000 { /* 0x48324000, ap 103 68.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x24000 0x1000>;
	};
	};
	};

	diff --git a/sys/gnu/dts/arm/am33xx.dtsi b/sys/gnu/dts/arm/am33xx.dtsi
	index 2b9ca5c609e5..f9bc73d099af 100644
	--- a/sys/gnu/dts/arm/am33xx.dtsi
	+++ b/sys/gnu/dts/arm/am33xx.dtsi
	@@ -1,555 +1,622 @@
	/*
	* Device Tree Source for AM33XX SoC
	*
	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	*
	* This file is licensed under the terms of the GNU General Public License
	* version 2. This program is licensed "as is" without any warranty of any
	* kind, whether express or implied.
	*/

	#include <dt-bindings/bus/ti-sysc.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/pinctrl/am33xx.h>
	#include <dt-bindings/clock/am3.h>

	/ {
	compatible = "ti,am33xx";
	interrupt-parent = <&intc>;
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	serial0 = &uart0;
	serial1 = &uart1;
	serial2 = &uart2;
	serial3 = &uart3;
	serial4 = &uart4;
	serial5 = &uart5;
	d-can0 = &dcan0;
	d-can1 = &dcan1;
	usb0 = &usb0;
	usb1 = &usb1;
	phy0 = &usb0_phy;
	phy1 = &usb1_phy;
	ethernet0 = &cpsw_emac0;
	ethernet1 = &cpsw_emac1;
	spi0 = &spi0;
	spi1 = &spi1;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	cpu@0 {
	compatible = "arm,cortex-a8";
	+ enable-method = "ti,am3352";
	device_type = "cpu";
	reg = <0>;

	operating-points-v2 = <&cpu0_opp_table>;

	clocks = <&dpll_mpu_ck>;
	clock-names = "cpu";

	clock-latency = <300000>; /* From omap-cpufreq driver */
	+ cpu-idle-states = <&mpu_gate>;
	+ };
	+
	+ idle-states {
	+ mpu_gate: mpu_gate {
	+ compatible = "arm,idle-state";
	+ entry-latency-us = <40>;
	+ exit-latency-us = <90>;
	+ min-residency-us = <300>;
	+ ti,idle-wkup-m3;
	+ };
	};
	};

	cpu0_opp_table: opp-table {
	compatible = "operating-points-v2-ti-cpu";
	syscon = <&scm_conf>;

	/*
	* The three following nodes are marked with opp-suspend
	* because the can not be enabled simultaneously on a
	* single SoC.
	*/
	opp50-300000000 {
	opp-hz = /bits/ 64 <300000000>;
	opp-microvolt = <950000 931000 969000>;
	opp-supported-hw = <0x06 0x0010>;
	opp-suspend;
	};

	opp100-275000000 {
	opp-hz = /bits/ 64 <275000000>;
	opp-microvolt = <1100000 1078000 1122000>;
	opp-supported-hw = <0x01 0x00FF>;
	opp-suspend;
	};

	opp100-300000000 {
	opp-hz = /bits/ 64 <300000000>;
	opp-microvolt = <1100000 1078000 1122000>;
	opp-supported-hw = <0x06 0x0020>;
	opp-suspend;
	};

	opp100-500000000 {
	opp-hz = /bits/ 64 <500000000>;
	opp-microvolt = <1100000 1078000 1122000>;
	opp-supported-hw = <0x01 0xFFFF>;
	};

	opp100-600000000 {
	opp-hz = /bits/ 64 <600000000>;
	opp-microvolt = <1100000 1078000 1122000>;
	opp-supported-hw = <0x06 0x0040>;
	};

	opp120-600000000 {
	opp-hz = /bits/ 64 <600000000>;
	opp-microvolt = <1200000 1176000 1224000>;
	opp-supported-hw = <0x01 0xFFFF>;
	};

	opp120-720000000 {
	opp-hz = /bits/ 64 <720000000>;
	opp-microvolt = <1200000 1176000 1224000>;
	opp-supported-hw = <0x06 0x0080>;
	};

	oppturbo-720000000 {
	opp-hz = /bits/ 64 <720000000>;
	opp-microvolt = <1260000 1234800 1285200>;
	opp-supported-hw = <0x01 0xFFFF>;
	};

	oppturbo-800000000 {
	opp-hz = /bits/ 64 <800000000>;
	opp-microvolt = <1260000 1234800 1285200>;
	opp-supported-hw = <0x06 0x0100>;
	};

	oppnitro-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	opp-microvolt = <1325000 1298500 1351500>;
	opp-supported-hw = <0x04 0x0200>;
	};
	};

	pmu@4b000000 {
	compatible = "arm,cortex-a8-pmu";
	interrupts = <3>;
	reg = <0x4b000000 0x1000000>;
	ti,hwmods = "debugss";
	};

	/*
	* The soc node represents the soc top level view. It is used for IPs
	* that are not memory mapped in the MPU view or for the MPU itself.
	*/
	soc {
	compatible = "ti,omap-infra";
	mpu {
	compatible = "ti,omap3-mpu";
	ti,hwmods = "mpu";
	pm-sram = <&pm_sram_code
	&pm_sram_data>;
	};
	};

	/*
	* XXX: Use a flat representation of the AM33XX interconnect.
	* The real AM33XX interconnect network is quite complex. Since
	* it will not bring real advantage to represent that in DT
	* for the moment, just use a fake OCP bus entry to represent
	* the whole bus hierarchy.
	*/
	ocp {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	ti,hwmods = "l3_main";

	l4_wkup: interconnect@44c00000 {
	wkup_m3: wkup_m3@100000 {
	compatible = "ti,am3352-wkup-m3";
	reg = <0x100000 0x4000>,
	<0x180000 0x2000>;
	reg-names = "umem", "dmem";
	ti,hwmods = "wkup_m3";
	ti,pm-firmware = "am335x-pm-firmware.elf";
	};
	};
	l4_per: interconnect@48000000 {
	};
	l4_fw: interconnect@47c00000 {
	};
	l4_fast: interconnect@4a000000 {
	};
	l4_mpuss: interconnect@4b140000 {
	};

	intc: interrupt-controller@48200000 {
	compatible = "ti,am33xx-intc";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x48200000 0x1000>;
	};

	- edma: edma@49000000 {
	- compatible = "ti,edma3-tpcc";
	- ti,hwmods = "tpcc";
	- reg = <0x49000000 0x10000>;
	- reg-names = "edma3_cc";
	- interrupts = <12 13 14>;
	- interrupt-names = "edma3_ccint", "edma3_mperr",
	- "edma3_ccerrint";
	- dma-requests = <64>;
	- #dma-cells = <2>;
	-
	- ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
	- <&edma_tptc2 0>;
	-
	- ti,edma-memcpy-channels = <20 21>;
	+ target-module@49000000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49000000 0x4>;
	+ reg-names = "rev";
	+ clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49000000 0x10000>;
	+
	+ edma: dma@0 {
	+ compatible = "ti,edma3-tpcc";
	+ reg = <0 0x10000>;
	+ reg-names = "edma3_cc";
	+ interrupts = <12 13 14>;
	+ interrupt-names = "edma3_ccint", "edma3_mperr",
	+ "edma3_ccerrint";
	+ dma-requests = <64>;
	+ #dma-cells = <2>;
	+
	+ ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
	+ <&edma_tptc2 0>;
	+
	+ ti,edma-memcpy-channels = <20 21>;
	+ };
	};

	- edma_tptc0: tptc@49800000 {
	- compatible = "ti,edma3-tptc";
	- ti,hwmods = "tptc0";
	- reg = <0x49800000 0x100000>;
	- interrupts = <112>;
	- interrupt-names = "edma3_tcerrint";
	+ target-module@49800000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49800000 0x4>,
	+ <0x49800010 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_SMART>;
	+ clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49800000 0x100000>;
	+
	+ edma_tptc0: dma@0 {
	+ compatible = "ti,edma3-tptc";
	+ reg = <0 0x100000>;
	+ interrupts = <112>;
	+ interrupt-names = "edma3_tcerrint";
	+ };
	};

	- edma_tptc1: tptc@49900000 {
	- compatible = "ti,edma3-tptc";
	- ti,hwmods = "tptc1";
	- reg = <0x49900000 0x100000>;
	- interrupts = <113>;
	- interrupt-names = "edma3_tcerrint";
	+ target-module@49900000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49900000 0x4>,
	+ <0x49900010 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_SMART>;
	+ clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49900000 0x100000>;
	+
	+ edma_tptc1: dma@0 {
	+ compatible = "ti,edma3-tptc";
	+ reg = <0 0x100000>;
	+ interrupts = <113>;
	+ interrupt-names = "edma3_tcerrint";
	+ };
	};

	- edma_tptc2: tptc@49a00000 {
	- compatible = "ti,edma3-tptc";
	- ti,hwmods = "tptc2";
	- reg = <0x49a00000 0x100000>;
	- interrupts = <114>;
	- interrupt-names = "edma3_tcerrint";
	+ target-module@49a00000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49a00000 0x4>,
	+ <0x49a00010 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_SMART>;
	+ clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49a00000 0x100000>;
	+
	+ edma_tptc2: dma@0 {
	+ compatible = "ti,edma3-tptc";
	+ reg = <0 0x100000>;
	+ interrupts = <114>;
	+ interrupt-names = "edma3_tcerrint";
	+ };
	};

	target-module@47810000 {
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x478102fc 0x4>,
	<0x47810110 0x4>,
	<0x47810114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x47810000 0x1000>;

	mmc3: mmc@0 {
	compatible = "ti,omap4-hsmmc";
	ti,needs-special-reset;
	interrupts = <29>;
	reg = <0x0 0x1000>;
	status = "disabled";
	};
	};

	usb: target-module@47400000 {
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x47400000 0x4>,
	<0x47400010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP2_SOFTRESET)>;
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x47400000 0x5000>;

	usb0_phy: usb-phy@1300 {
	compatible = "ti,am335x-usb-phy";
	reg = <0x1300 0x100>;
	reg-names = "phy";
	ti,ctrl_mod = <&usb_ctrl_mod>;
	#phy-cells = <0>;
	};

	usb0: usb@1400 {
	compatible = "ti,musb-am33xx";
	reg = <0x1400 0x400>,
	<0x1000 0x200>;
	reg-names = "mc", "control";

	interrupts = <18>;
	interrupt-names = "mc";
	dr_mode = "otg";
	mentor,multipoint = <1>;
	mentor,num-eps = <16>;
	mentor,ram-bits = <12>;
	mentor,power = <500>;
	phys = <&usb0_phy>;

	dmas = <&cppi41dma 0 0 &cppi41dma 1 0
	&cppi41dma 2 0 &cppi41dma 3 0
	&cppi41dma 4 0 &cppi41dma 5 0
	&cppi41dma 6 0 &cppi41dma 7 0
	&cppi41dma 8 0 &cppi41dma 9 0
	&cppi41dma 10 0 &cppi41dma 11 0
	&cppi41dma 12 0 &cppi41dma 13 0
	&cppi41dma 14 0 &cppi41dma 0 1
	&cppi41dma 1 1 &cppi41dma 2 1
	&cppi41dma 3 1 &cppi41dma 4 1
	&cppi41dma 5 1 &cppi41dma 6 1
	&cppi41dma 7 1 &cppi41dma 8 1
	&cppi41dma 9 1 &cppi41dma 10 1
	&cppi41dma 11 1 &cppi41dma 12 1
	&cppi41dma 13 1 &cppi41dma 14 1>;
	dma-names =
	"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
	"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
	"rx14", "rx15",
	"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
	"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
	"tx14", "tx15";
	};

	usb1_phy: usb-phy@1b00 {
	compatible = "ti,am335x-usb-phy";
	reg = <0x1b00 0x100>;
	reg-names = "phy";
	ti,ctrl_mod = <&usb_ctrl_mod>;
	#phy-cells = <0>;
	};

	usb1: usb@1800 {
	compatible = "ti,musb-am33xx";
	reg = <0x1c00 0x400>,
	<0x1800 0x200>;
	reg-names = "mc", "control";
	interrupts = <19>;
	interrupt-names = "mc";
	dr_mode = "otg";
	mentor,multipoint = <1>;
	mentor,num-eps = <16>;
	mentor,ram-bits = <12>;
	mentor,power = <500>;
	phys = <&usb1_phy>;

	dmas = <&cppi41dma 15 0 &cppi41dma 16 0
	&cppi41dma 17 0 &cppi41dma 18 0
	&cppi41dma 19 0 &cppi41dma 20 0
	&cppi41dma 21 0 &cppi41dma 22 0
	&cppi41dma 23 0 &cppi41dma 24 0
	&cppi41dma 25 0 &cppi41dma 26 0
	&cppi41dma 27 0 &cppi41dma 28 0
	&cppi41dma 29 0 &cppi41dma 15 1
	&cppi41dma 16 1 &cppi41dma 17 1
	&cppi41dma 18 1 &cppi41dma 19 1
	&cppi41dma 20 1 &cppi41dma 21 1
	&cppi41dma 22 1 &cppi41dma 23 1
	&cppi41dma 24 1 &cppi41dma 25 1
	&cppi41dma 26 1 &cppi41dma 27 1
	&cppi41dma 28 1 &cppi41dma 29 1>;
	dma-names =
	"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
	"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
	"rx14", "rx15",
	"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
	"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
	"tx14", "tx15";
	};

	cppi41dma: dma-controller@2000 {
	compatible = "ti,am3359-cppi41";
	reg = <0x0000 0x1000>,
	<0x2000 0x1000>,
	<0x3000 0x1000>,
	<0x4000 0x4000>;
	reg-names = "glue", "controller", "scheduler", "queuemgr";
	interrupts = <17>;
	interrupt-names = "glue";
	#dma-cells = <2>;
	#dma-channels = <30>;
	#dma-requests = <256>;
	};
	};

	ocmcram: sram@40300000 {
	compatible = "mmio-sram";
	reg = <0x40300000 0x10000>; /* 64k */
	ranges = <0x0 0x40300000 0x10000>;
	#address-cells = <1>;
	#size-cells = <1>;

	pm_sram_code: pm-code-sram@0 {
	compatible = "ti,sram";
	reg = <0x0 0x1000>;
	protect-exec;
	};

	pm_sram_data: pm-data-sram@1000 {
	compatible = "ti,sram";
	reg = <0x1000 0x1000>;
	pool;
	};
	};

	emif: emif@4c000000 {
	compatible = "ti,emif-am3352";
	reg = <0x4c000000 0x1000000>;
	ti,hwmods = "emif";
	interrupts = <101>;
	sram = <&pm_sram_code
	&pm_sram_data>;
	ti,no-idle;
	};

	gpmc: gpmc@50000000 {
	compatible = "ti,am3352-gpmc";
	ti,hwmods = "gpmc";
	ti,no-idle-on-init;
	reg = <0x50000000 0x2000>;
	interrupts = <100>;
	dmas = <&edma 52 0>;
	dma-names = "rxtx";
	gpmc,num-cs = <7>;
	gpmc,num-waitpins = <2>;
	#address-cells = <2>;
	#size-cells = <1>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;
	status = "disabled";
	};

	sham_target: target-module@53100000 {
	compatible = "ti,sysc-omap3-sham", "ti,sysc";
	reg = <0x53100100 0x4>,
	<0x53100110 0x4>,
	<0x53100114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l3_clkdm */
	clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x53100000 0x1000>;

	sham: sham@0 {
	compatible = "ti,omap4-sham";
	reg = <0 0x200>;
	interrupts = <109>;
	dmas = <&edma 36 0>;
	dma-names = "rx";
	};
	};

	aes_target: target-module@53500000 {
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x53500080 0x4>,
	<0x53500084 0x4>,
	<0x53500088 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l3_clkdm */
	clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x53500000 0x1000>;

	aes: aes@0 {
	compatible = "ti,omap4-aes";
	reg = <0 0xa0>;
	interrupts = <103>;
	dmas = <&edma 6 0>,
	<&edma 5 0>;
	dma-names = "tx", "rx";
	};
	};

	target-module@56000000 {
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x5600fe00 0x4>,
	<0x5600fe10 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
	clock-names = "fck";
	resets = <&prm_gfx 0>;
	reset-names = "rstctrl";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x56000000 0x1000000>;

	/*
	* Closed source PowerVR driver, no child device
	* binding or driver in mainline
	*/
	};
	};
	};

	#include "am33xx-l4.dtsi"
	#include "am33xx-clocks.dtsi"

	&prcm {
	prm_per: prm@c00 {
	compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
	reg = <0xc00 0x100>;
	#reset-cells = <1>;
	};

	prm_wkup: prm@d00 {
	compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
	reg = <0xd00 0x100>;
	#reset-cells = <1>;
	};

	prm_device: prm@f00 {
	compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
	reg = <0xf00 0x100>;
	#reset-cells = <1>;
	};

	prm_gfx: prm@1100 {
	compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
	reg = <0x1100 0x100>;
	#reset-cells = <1>;
	};
	};
	diff --git a/sys/gnu/dts/arm/am4372.dtsi b/sys/gnu/dts/arm/am4372.dtsi
	index faa14dc0faff..dba87bfaf33e 100644
	--- a/sys/gnu/dts/arm/am4372.dtsi
	+++ b/sys/gnu/dts/arm/am4372.dtsi
	@@ -1,498 +1,555 @@
	/*
	* Device Tree Source for AM4372 SoC
	*
	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
	*
	* This file is licensed under the terms of the GNU General Public License
	* version 2. This program is licensed "as is" without any warranty of any
	* kind, whether express or implied.
	*/

	#include <dt-bindings/bus/ti-sysc.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/am4.h>

	/ {
	compatible = "ti,am4372", "ti,am43";
	interrupt-parent = <&wakeupgen>;
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };

	memory@0 {
	device_type = "memory";
	reg = <0 0>;
	};

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	serial0 = &uart0;
	serial1 = &uart1;
	serial2 = &uart2;
	serial3 = &uart3;
	serial4 = &uart4;
	serial5 = &uart5;
	ethernet0 = &cpsw_emac0;
	ethernet1 = &cpsw_emac1;
	spi0 = &qspi;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	cpu: cpu@0 {
	compatible = "arm,cortex-a9";
	+ enable-method = "ti,am4372";
	device_type = "cpu";
	reg = <0>;

	clocks = <&dpll_mpu_ck>;
	clock-names = "cpu";

	operating-points-v2 = <&cpu0_opp_table>;

	clock-latency = <300000>; /* From omap-cpufreq driver */
	+ cpu-idle-states = <&mpu_gate>;
	+ };
	+
	+ idle-states {
	+ mpu_gate: mpu_gate {
	+ compatible = "arm,idle-state";
	+ entry-latency-us = <40>;
	+ exit-latency-us = <100>;
	+ min-residency-us = <300>;
	+ local-timer-stop;
	+ };
	};
	};

	cpu0_opp_table: opp-table {
	compatible = "operating-points-v2-ti-cpu";
	syscon = <&scm_conf>;

	opp50-300000000 {
	opp-hz = /bits/ 64 <300000000>;
	opp-microvolt = <950000 931000 969000>;
	opp-supported-hw = <0xFF 0x01>;
	opp-suspend;
	};

	opp100-600000000 {
	opp-hz = /bits/ 64 <600000000>;
	opp-microvolt = <1100000 1078000 1122000>;
	opp-supported-hw = <0xFF 0x04>;
	};

	opp120-720000000 {
	opp-hz = /bits/ 64 <720000000>;
	opp-microvolt = <1200000 1176000 1224000>;
	opp-supported-hw = <0xFF 0x08>;
	};

	oppturbo-800000000 {
	opp-hz = /bits/ 64 <800000000>;
	opp-microvolt = <1260000 1234800 1285200>;
	opp-supported-hw = <0xFF 0x10>;
	};

	oppnitro-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	opp-microvolt = <1325000 1298500 1351500>;
	opp-supported-hw = <0xFF 0x20>;
	};
	};

	soc {
	compatible = "ti,omap-infra";
	mpu {
	compatible = "ti,omap4-mpu";
	ti,hwmods = "mpu";
	pm-sram = <&pm_sram_code
	&pm_sram_data>;
	};
	};

	gic: interrupt-controller@48241000 {
	compatible = "arm,cortex-a9-gic";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0x48241000 0x1000>,
	<0x48240100 0x0100>;
	interrupt-parent = <&gic>;
	};

	wakeupgen: interrupt-controller@48281000 {
	compatible = "ti,omap4-wugen-mpu";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0x48281000 0x1000>;
	interrupt-parent = <&gic>;
	};

	scu: scu@48240000 {
	compatible = "arm,cortex-a9-scu";
	reg = <0x48240000 0x100>;
	};

	global_timer: timer@48240200 {
	compatible = "arm,cortex-a9-global-timer";
	reg = <0x48240200 0x100>;
	interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
	interrupt-parent = <&gic>;
	clocks = <&mpu_periphclk>;
	};

	local_timer: timer@48240600 {
	compatible = "arm,cortex-a9-twd-timer";
	reg = <0x48240600 0x100>;
	interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
	interrupt-parent = <&gic>;
	clocks = <&mpu_periphclk>;
	};

	l2-cache-controller@48242000 {
	compatible = "arm,pl310-cache";
	reg = <0x48242000 0x1000>;
	cache-unified;
	cache-level = <2>;
	};

	ocp@44000000 {
	compatible = "ti,am4372-l3-noc", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	ti,hwmods = "l3_main";
	ti,no-idle;
	reg = <0x44000000 0x400000
	0x44800000 0x400000>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

	l4_wkup: interconnect@44c00000 {
	wkup_m3: wkup_m3@100000 {
	compatible = "ti,am4372-wkup-m3";
	reg = <0x100000 0x4000>,
	<0x180000 0x2000>;
	reg-names = "umem", "dmem";
	ti,hwmods = "wkup_m3";
	ti,pm-firmware = "am335x-pm-firmware.elf";
	};
	};
	l4_per: interconnect@48000000 {
	};
	l4_fast: interconnect@4a000000 {
	};

	emif: emif@4c000000 {
	compatible = "ti,emif-am4372";
	reg = <0x4c000000 0x1000000>;
	ti,hwmods = "emif";
	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	ti,no-idle;
	sram = <&pm_sram_code
	&pm_sram_data>;
	};

	- edma: edma@49000000 {
	- compatible = "ti,edma3-tpcc";
	- ti,hwmods = "tpcc";
	- reg = <0x49000000 0x10000>;
	- reg-names = "edma3_cc";
	- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	- interrupt-names = "edma3_ccint", "edma3_mperr",
	- "edma3_ccerrint";
	- dma-requests = <64>;
	- #dma-cells = <2>;
	-
	- ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
	- <&edma_tptc2 0>;
	-
	- ti,edma-memcpy-channels = <58 59>;
	+ target-module@49000000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49000000 0x4>;
	+ reg-names = "rev";
	+ clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49000000 0x10000>;
	+
	+ edma: dma@0 {
	+ compatible = "ti,edma3-tpcc";
	+ reg = <0 0x10000>;
	+ reg-names = "edma3_cc";
	+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	+ interrupt-names = "edma3_ccint", "edma3_mperr",
	+ "edma3_ccerrint";
	+ dma-requests = <64>;
	+ #dma-cells = <2>;
	+
	+ ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
	+ <&edma_tptc2 0>;
	+
	+ ti,edma-memcpy-channels = <58 59>;
	+ };
	};

	- edma_tptc0: tptc@49800000 {
	- compatible = "ti,edma3-tptc";
	- ti,hwmods = "tptc0";
	- reg = <0x49800000 0x100000>;
	- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	- interrupt-names = "edma3_tcerrint";
	+ target-module@49800000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49800000 0x4>,
	+ <0x49800010 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_SMART>;
	+ clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49800000 0x100000>;
	+
	+ edma_tptc0: dma@0 {
	+ compatible = "ti,edma3-tptc";
	+ reg = <0 0x100000>;
	+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	+ interrupt-names = "edma3_tcerrint";
	+ };
	};

	- edma_tptc1: tptc@49900000 {
	- compatible = "ti,edma3-tptc";
	- ti,hwmods = "tptc1";
	- reg = <0x49900000 0x100000>;
	- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	- interrupt-names = "edma3_tcerrint";
	+ target-module@49900000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49900000 0x4>,
	+ <0x49900010 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_SMART>;
	+ clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49900000 0x100000>;
	+
	+ edma_tptc1: dma@0 {
	+ compatible = "ti,edma3-tptc";
	+ reg = <0 0x100000>;
	+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	+ interrupt-names = "edma3_tcerrint";
	+ };
	};

	- edma_tptc2: tptc@49a00000 {
	- compatible = "ti,edma3-tptc";
	- ti,hwmods = "tptc2";
	- reg = <0x49a00000 0x100000>;
	- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	- interrupt-names = "edma3_tcerrint";
	+ target-module@49a00000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49a00000 0x4>,
	+ <0x49a00010 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_SMART>;
	+ clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49a00000 0x100000>;
	+
	+ edma_tptc2: dma@0 {
	+ compatible = "ti,edma3-tptc";
	+ reg = <0 0x100000>;
	+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	+ interrupt-names = "edma3_tcerrint";
	+ };
	};

	target-module@47810000 {
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x478102fc 0x4>,
	<0x47810110 0x4>,
	<0x47810114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x47810000 0x1000>;

	mmc3: mmc@0 {
	compatible = "ti,omap4-hsmmc";
	ti,needs-special-reset;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x0 0x1000>;
	};
	};

	sham_target: target-module@53100000 {
	compatible = "ti,sysc-omap3-sham", "ti,sysc";
	reg = <0x53100100 0x4>,
	<0x53100110 0x4>,
	<0x53100114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l3_clkdm */
	clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x53100000 0x1000>;

	sham: sham@0 {
	compatible = "ti,omap5-sham";
	reg = <0 0x300>;
	dmas = <&edma 36 0>;
	dma-names = "rx";
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	aes_target: target-module@53501000 {
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x53501080 0x4>,
	<0x53501084 0x4>,
	<0x53501088 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l3_clkdm */
	clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x53501000 0x1000>;

	aes: aes@0 {
	compatible = "ti,omap4-aes";
	reg = <0 0xa0>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&edma 6 0>,
	<&edma 5 0>;
	dma-names = "tx", "rx";
	};
	};

	des_target: target-module@53701000 {
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x53701030 0x4>,
	<0x53701034 0x4>,
	<0x53701038 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l3_clkdm */
	clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x53701000 0x1000>;

	des: des@0 {
	compatible = "ti,omap4-des";
	reg = <0 0xa0>;
	interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&edma 34 0>,
	<&edma 33 0>;
	dma-names = "tx", "rx";
	};
	};

	+ pruss_tm: target-module@54400000 {
	+ compatible = "ti,sysc-pruss", "ti,sysc";
	+ reg = <0x54426000 0x4>,
	+ <0x54426004 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT \|
	+ SYSC_PRUSS_SUB_MWAIT)>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
	+ clock-names = "fck";
	+ resets = <&prm_per 1>;
	+ reset-names = "rstctrl";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x54400000 0x80000>;
	+ };
	+
	gpmc: gpmc@50000000 {
	compatible = "ti,am3352-gpmc";
	ti,hwmods = "gpmc";
	dmas = <&edma 52 0>;
	dma-names = "rxtx";
	clocks = <&l3s_gclk>;
	clock-names = "fck";
	reg = <0x50000000 0x2000>;
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	gpmc,num-cs = <7>;
	gpmc,num-waitpins = <2>;
	#address-cells = <2>;
	#size-cells = <1>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;
	status = "disabled";
	};

	target-module@47900000 {
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x47900000 0x4>,
	<0x47900010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x47900000 0x1000>,
	<0x30000000 0x30000000 0x4000000>;

	qspi: spi@0 {
	compatible = "ti,am4372-qspi";
	reg = <0 0x100>,
	<0x30000000 0x4000000>;
	reg-names = "qspi_base", "qspi_mmap";
	clocks = <&dpll_per_m2_div4_ck>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 138 0x4>;
	num-cs = <4>;
	};
	};

	- dss: dss@4832a000 {
	- compatible = "ti,omap3-dss";
	- reg = <0x4832a000 0x200>;
	- status = "disabled";
	- ti,hwmods = "dss_core";
	- clocks = <&disp_clk>;
	- clock-names = "fck";
	- #address-cells = <1>;
	- #size-cells = <1>;
	- ranges;
	-
	- dispc: dispc@4832a400 {
	- compatible = "ti,omap3-dispc";
	- reg = <0x4832a400 0x400>;
	- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	- ti,hwmods = "dss_dispc";
	- clocks = <&disp_clk>;
	- clock-names = "fck";
	-
	- max-memory-bandwidth = <230000000>;
	- };
	-
	- rfbi: rfbi@4832a800 {
	- compatible = "ti,omap3-rfbi";
	- reg = <0x4832a800 0x100>;
	- ti,hwmods = "dss_rfbi";
	- clocks = <&disp_clk>;
	- clock-names = "fck";
	- status = "disabled";
	- };
	- };
	-
	ocmcram: sram@40300000 {
	compatible = "mmio-sram";
	reg = <0x40300000 0x40000>; /* 256k */
	ranges = <0x0 0x40300000 0x40000>;
	#address-cells = <1>;
	#size-cells = <1>;

	pm_sram_code: pm-code-sram@0 {
	compatible = "ti,sram";
	reg = <0x0 0x1000>;
	protect-exec;
	};

	pm_sram_data: pm-data-sram@1000 {
	compatible = "ti,sram";
	reg = <0x1000 0x1000>;
	pool;
	};
	};

	target-module@56000000 {
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x5600fe00 0x4>,
	<0x5600fe10 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
	clock-names = "fck";
	resets = <&prm_gfx 0>;
	reset-names = "rstctrl";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x56000000 0x1000000>;
	};
	};
	};

	#include "am437x-l4.dtsi"
	#include "am43xx-clocks.dtsi"

	&prcm {
	prm_gfx: prm@400 {
	compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
	reg = <0x400 0x100>;
	#reset-cells = <1>;
	};

	prm_per: prm@800 {
	compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
	reg = <0x800 0x100>;
	#reset-cells = <1>;
	};

	prm_wkup: prm@2000 {
	compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
	reg = <0x2000 0x100>;
	#reset-cells = <1>;
	};

	prm_device: prm@4000 {
	compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
	reg = <0x4000 0x100>;
	#reset-cells = <1>;
	};
	};
	diff --git a/sys/gnu/dts/arm/am437x-gp-evm.dts b/sys/gnu/dts/arm/am437x-gp-evm.dts
	index 811c8cae315b..d692e3b2812a 100644
	--- a/sys/gnu/dts/arm/am437x-gp-evm.dts
	+++ b/sys/gnu/dts/arm/am437x-gp-evm.dts
	@@ -1,1130 +1,1130 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
	*/

	/* AM437x GP EVM */

	/dts-v1/;

	#include "am4372.dtsi"
	#include <dt-bindings/pinctrl/am43xx.h>
	#include <dt-bindings/pwm/pwm.h>
	#include <dt-bindings/gpio/gpio.h>

	/ {
	model = "TI AM437x GP EVM";
	compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";

	aliases {
	display0 = &lcd0;
	};

	chosen {
	stdout-path = &uart0;
	};

	evm_v3_3d: fixedregulator-v3_3d {
	compatible = "regulator-fixed";
	regulator-name = "evm_v3_3d";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	enable-active-high;
	};

	vtt_fixed: fixedregulator-vtt {
	compatible = "regulator-fixed";
	regulator-name = "vtt_fixed";
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;
	regulator-boot-on;
	enable-active-high;
	gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
	};

	vmmcwl_fixed: fixedregulator-mmcwl {
	compatible = "regulator-fixed";
	regulator-name = "vmmcwl_fixed";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	lcd_bl: backlight {
	compatible = "pwm-backlight";
	pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
	brightness-levels = <0 51 53 56 62 75 101 152 255>;
	default-brightness-level = <8>;
	};

	matrix_keypad: matrix_keypad0 {
	compatible = "gpio-matrix-keypad";
	debounce-delay-ms = <5>;
	col-scan-delay-us = <2>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&matrix_keypad_default>;
	pinctrl-1 = <&matrix_keypad_sleep>;

	wakeup-source;

	row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */
	&gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
	&gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */

	col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
	&gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */

	linux,keymap = <0x00000201 /* P1 */
	0x00010202 /* P2 */
	0x01000067 /* UP */
	0x0101006a /* RIGHT */
	0x02000069 /* LEFT */
	0x0201006c>; /* DOWN */
	};

	lcd0: display {
	compatible = "osddisplays,osd070t1718-19ts", "panel-dpi";
	label = "lcd";

	backlight = <&lcd_bl>;

	panel-timing {
	clock-frequency = <33000000>;
	hactive = <800>;
	vactive = <480>;
	hfront-porch = <210>;
	hback-porch = <16>;
	hsync-len = <30>;
	vback-porch = <10>;
	vfront-porch = <22>;
	vsync-len = <13>;
	hsync-active = <0>;
	vsync-active = <0>;
	de-active = <1>;
	pixelclk-active = <1>;
	};

	port {
	lcd_in: endpoint {
	remote-endpoint = <&dpi_out>;
	};
	};
	};

	/* fixed 12MHz oscillator */
	refclk: oscillator {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <12000000>;
	};

	/* fixed 32k external oscillator clock */
	clk_32k_rtc: clk_32k_rtc {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	};

	sound0: sound0 {
	compatible = "simple-audio-card";
	simple-audio-card,name = "AM437x-GP-EVM";
	simple-audio-card,widgets =
	"Headphone", "Headphone Jack",
	"Line", "Line In";
	simple-audio-card,routing =
	"Headphone Jack", "HPLOUT",
	"Headphone Jack", "HPROUT",
	"LINE1L", "Line In",
	"LINE1R", "Line In";
	simple-audio-card,format = "dsp_b";
	simple-audio-card,bitclock-master = <&sound0_master>;
	simple-audio-card,frame-master = <&sound0_master>;
	simple-audio-card,bitclock-inversion;

	simple-audio-card,cpu {
	sound-dai = <&mcasp1>;
	system-clock-frequency = <12000000>;
	};

	sound0_master: simple-audio-card,codec {
	sound-dai = <&tlv320aic3106>;
	system-clock-frequency = <12000000>;
	};
	};

	beeper: beeper {
	compatible = "gpio-beeper";
	pinctrl-names = "default";
	pinctrl-0 = <&beeper_pins_default>;
	pinctrl-1 = <&beeper_pins_sleep>;
	gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
	};
	};

	&am43xx_pinmux {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins &debugss_pins>;
	pinctrl-1 = <&wlan_pins_sleep>;

	ddr3_vtt_toggle_default: ddr_vtt_toggle_default {
	pinctrl-single,pins = <
	0x25C (DS0_PULL_UP_DOWN_EN \| PIN_OUTPUT_PULLUP \| DS0_FORCE_OFF_MODE \| MUX_MODE7) /* spi0_cs0.gpio5_7 */
	>;
	};

	i2c0_pins: i2c0_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x988, PIN_INPUT_PULLUP \| SLEWCTRL_FAST \| MUX_MODE0) /* i2c0_sda.i2c0_sda */
	AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP \| SLEWCTRL_FAST \| MUX_MODE0) /* i2c0_scl.i2c0_scl */
	>;
	};

	i2c1_pins: i2c1_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP \| SLEWCTRL_FAST \| MUX_MODE2) /* spi0_cs0.i2c1_scl */
	AM4372_IOPAD(0x958, PIN_INPUT_PULLUP \| SLEWCTRL_FAST \| MUX_MODE2) /* spi0_d1.i2c1_sda */
	>;
	};

	mmc1_pins: pinmux_mmc1_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x960, PIN_INPUT \| MUX_MODE7) /* spi0_cs1.gpio0_6 */
	>;
	};

	ecap0_pins: backlight_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
	>;
	};

	pixcir_ts_pins: pixcir_ts_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP \| MUX_MODE7) /* spi2_d0.gpio3_22 */
	>;
	};

	cpsw_default: cpsw_default {
	pinctrl-single,pins = <
	/* Slave 1 */
	AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN \| MUX_MODE2) /* mii1_txen.rgmii1_txen */
	AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN \| MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
	AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN \| MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
	AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN \| MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
	AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN \| MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
	AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN \| MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
	AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN \| MUX_MODE2) /* mii1_txclk.rmii1_tclk */
	AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN \| MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
	AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN \| MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
	AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN \| MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
	AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN \| MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
	AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN \| MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
	>;
	};

	cpsw_sleep: cpsw_sleep {
	pinctrl-single,pins = <
	/* Slave 1 reset value */
	AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	>;
	};

	davinci_mdio_default: davinci_mdio_default {
	pinctrl-single,pins = <
	/* MDIO */
	AM4372_IOPAD(0x948, PIN_INPUT_PULLUP \| SLEWCTRL_FAST \| MUX_MODE0) /* mdio_data.mdio_data */
	AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP \| MUX_MODE0) /* mdio_clk.mdio_clk */
	>;
	};

	davinci_mdio_sleep: davinci_mdio_sleep {
	pinctrl-single,pins = <
	/* MDIO reset value */
	AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	>;
	};

	nand_flash_x8: nand_flash_x8 {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x800, PIN_INPUT \| MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
	AM4372_IOPAD(0x804, PIN_INPUT \| MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
	AM4372_IOPAD(0x808, PIN_INPUT \| MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
	AM4372_IOPAD(0x80c, PIN_INPUT \| MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
	AM4372_IOPAD(0x810, PIN_INPUT \| MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
	AM4372_IOPAD(0x814, PIN_INPUT \| MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
	AM4372_IOPAD(0x818, PIN_INPUT \| MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
	AM4372_IOPAD(0x81c, PIN_INPUT \| MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
	AM4372_IOPAD(0x870, PIN_INPUT_PULLUP \| MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
	AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP \| MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
	AM4372_IOPAD(0x87c, PIN_OUTPUT \| MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
	AM4372_IOPAD(0x890, PIN_OUTPUT \| MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
	AM4372_IOPAD(0x894, PIN_OUTPUT \| MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
	AM4372_IOPAD(0x898, PIN_OUTPUT \| MUX_MODE0) /* gpmc_wen.gpmc_wen */
	AM4372_IOPAD(0x89c, PIN_OUTPUT \| MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
	>;
	};

	dss_pins: dss_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP \| MUX_MODE1) /gpmc ad 8 -> DSS DATA 23 /
	AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP \| MUX_MODE1)
	AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP \| MUX_MODE1)
	AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP \| MUX_MODE1)
	AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP \| MUX_MODE1)
	AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP \| MUX_MODE1)
	AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP \| MUX_MODE1)
	AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP \| MUX_MODE1) /gpmc ad 15 -> DSS DATA 16 /
	AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP \| MUX_MODE0) /* DSS DATA 0 */
	AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP \| MUX_MODE0)
	AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP \| MUX_MODE0)
	AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP \| MUX_MODE0)
	AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP \| MUX_MODE0)
	AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP \| MUX_MODE0)
	AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP \| MUX_MODE0)
	AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP \| MUX_MODE0)
	AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP \| MUX_MODE0)
	AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP \| MUX_MODE0)
	AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP \| MUX_MODE0)
	AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP \| MUX_MODE0)
	AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP \| MUX_MODE0)
	AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP \| MUX_MODE0)
	AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP \| MUX_MODE0)
	AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP \| MUX_MODE0) /* DSS DATA 15 */
	AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP \| MUX_MODE0) /* DSS VSYNC */
	AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP \| MUX_MODE0) /* DSS HSYNC */
	AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP \| MUX_MODE0) /* DSS PCLK */
	AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP \| MUX_MODE0) /* DSS AC BIAS EN */

	>;
	};

	display_mux_pins: display_mux_pins {
	pinctrl-single,pins = <
	/* GPIO 5_8 to select LCD / HDMI */
	AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP \| MUX_MODE7)
	>;
	};

	dcan0_default: dcan0_default_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x978, PIN_OUTPUT \| MUX_MODE2) /* uart1_ctsn.d_can0_tx */
	AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP \| MUX_MODE2) /* uart1_rtsn.d_can0_rx */
	>;
	};

	dcan0_sleep: dcan0_sleep_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x978, PIN_INPUT_PULLUP \| MUX_MODE7) /* uart1_ctsn.gpio0_12 */
	AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP \| MUX_MODE7) /* uart1_rtsn.gpio0_13 */
	>;
	};

	dcan1_default: dcan1_default_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x980, PIN_OUTPUT \| MUX_MODE2) /* uart1_rxd.d_can1_tx */
	AM4372_IOPAD(0x984, PIN_INPUT_PULLUP \| MUX_MODE2) /* uart1_txd.d_can1_rx */
	>;
	};

	dcan1_sleep: dcan1_sleep_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x980, PIN_INPUT_PULLUP \| MUX_MODE7) /* uart1_rxd.gpio0_14 */
	AM4372_IOPAD(0x984, PIN_INPUT_PULLUP \| MUX_MODE7) /* uart1_txd.gpio0_15 */
	>;
	};

	vpfe0_pins_default: vpfe0_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_hd mode 0*/
	AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_vd mode 0*/
	AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_pclk mode 0*/
	AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data8 mode 0*/
	AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data9 mode 0*/
	AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data0 mode 0*/
	AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data1 mode 0*/
	AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data2 mode 0*/
	AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data3 mode 0*/
	AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data4 mode 0*/
	AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data5 mode 0*/
	AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data6 mode 0*/
	AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data7 mode 0*/
	>;
	};

	vpfe0_pins_sleep: vpfe0_pins_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam0_hd mode 0*/
	AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam0_vd mode 0*/
	AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam0_pclk mode 0*/
	AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam0_data8 mode 0*/
	AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam0_data9 mode 0*/
	AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam0_data0 mode 0*/
	AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam0_data1 mode 0*/
	AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam0_data2 mode 0*/
	AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam0_data3 mode 0*/
	AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam0_data4 mode 0*/
	AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam0_data5 mode 0*/
	AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam0_data6 mode 0*/
	AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam0_data7 mode 0*/
	>;
	};

	vpfe1_pins_default: vpfe1_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam1_data9 mode 0*/
	AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam1_data8 mode 0*/
	AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam1_hd mode 0*/
	AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam1_vd mode 0*/
	AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam1_pclk mode 0*/
	AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam1_data0 mode 0*/
	AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam1_data1 mode 0*/
	AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam1_data2 mode 0*/
	AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam1_data3 mode 0*/
	AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam1_data4 mode 0*/
	AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam1_data5 mode 0*/
	AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam1_data6 mode 0*/
	AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam1_data7 mode 0*/
	>;
	};

	vpfe1_pins_sleep: vpfe1_pins_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam1_data9 mode 0*/
	AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam1_data8 mode 0*/
	AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam1_hd mode 0*/
	AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam1_vd mode 0*/
	AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam1_pclk mode 0*/
	AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam1_data0 mode 0*/
	AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam1_data1 mode 0*/
	AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam1_data2 mode 0*/
	AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam1_data3 mode 0*/
	AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam1_data4 mode 0*/
	AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam1_data5 mode 0*/
	AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam1_data6 mode 0*/
	AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* cam1_data7 mode 0*/
	>;
	};

	mmc3_pins_default: pinmux_mmc3_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP \| MUX_MODE3) /* gpmc_clk.mmc2_clk */
	AM4372_IOPAD(0x888, PIN_INPUT_PULLUP \| MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
	AM4372_IOPAD(0x844, PIN_INPUT_PULLUP \| MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
	AM4372_IOPAD(0x848, PIN_INPUT_PULLUP \| MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
	AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP \| MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
	AM4372_IOPAD(0x878, PIN_INPUT_PULLUP \| MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
	>;
	};

	mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* gpmc_clk.mmc2_clk */
	AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
	AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
	AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
	AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
	AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
	>;
	};

	wlan_pins_default: pinmux_wlan_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN \| MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
	AM4372_IOPAD(0x85c, PIN_INPUT \| WAKEUP_ENABLE \| MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
	AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN \| MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
	>;
	};

	wlan_pins_sleep: pinmux_wlan_pins_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN \| MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
	AM4372_IOPAD(0x85c, PIN_INPUT \| WAKEUP_ENABLE \| MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
	AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP \| MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
	>;
	};

	uart3_pins: uart3_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0xa28, PIN_INPUT \| MUX_MODE0) /* uart3_rxd.uart3_rxd */
	AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* uart3_txd.uart3_txd */
	AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP \| MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
	AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
	>;
	};

	mcasp1_pins: mcasp1_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN \| MUX_MODE4) /* mii1_col.mcasp1_axr2 */
	AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN \| MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
	AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN \| MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
	AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN \| MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
	>;
	};

	mcasp1_sleep_pins: mcasp1_sleep_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	>;
	};

	gpio0_pins: gpio0_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0xa6c, PIN_OUTPUT \| MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */
	>;
	};

	emmc_pins_default: emmc_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x800, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
	AM4372_IOPAD(0x804, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
	AM4372_IOPAD(0x808, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
	AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
	AM4372_IOPAD(0x810, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
	AM4372_IOPAD(0x814, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
	AM4372_IOPAD(0x818, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
	AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
	AM4372_IOPAD(0x880, PIN_INPUT_PULLUP \| MUX_MODE2) /* gpmc_csn1.mmc1_clk */
	AM4372_IOPAD(0x884, PIN_INPUT_PULLUP \| MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
	>;
	};

	emmc_pins_sleep: emmc_pins_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* gpmc_ad0.gpio1_0 */
	AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* gpmc_ad1.gpio1_1 */
	AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* gpmc_ad2.gpio1_2 */
	AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* gpmc_ad3.gpio1_3 */
	AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* gpmc_ad4.gpio1_4 */
	AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* gpmc_ad5.gpio1_5 */
	AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* gpmc_ad6.gpio1_6 */
	AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* gpmc_ad7.gpio1_7 */
	AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* gpmc_csn1.gpio1_30 */
	AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* gpmc_csn2.gpio1_31 */
	>;
	};

	beeper_pins_default: beeper_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP \| MUX_MODE7) /* cam1_field.gpio4_12 */
	>;
	};

	beeper_pins_sleep: beeper_pins_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x9e0, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* cam1_field.gpio4_12 */
	>;
	};

	unused_pins: unused_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x950, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x990, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x994, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x998, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x99c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xa3c, PIN_INPUT \| PULL_DISABLE \| MUX_MODE7)
	AM4372_IOPAD(0xa40, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xa44, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xa48, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xa4c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xa50, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xa54, PIN_INPUT \| PULL_DISABLE \| MUX_MODE7)
	AM4372_IOPAD(0xa58, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xa60, PIN_INPUT \| PULL_DISABLE \| MUX_MODE7)
	AM4372_IOPAD(0xa68, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xa70, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xa78, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xa7c, PIN_INPUT \| PULL_DISABLE)
	AM4372_IOPAD(0xac8, PIN_INPUT_PULLDOWN)
	AM4372_IOPAD(0xad4, PIN_INPUT_PULLDOWN)
	AM4372_IOPAD(0xad8, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xadc, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xae0, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xae4, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xae8, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xaec, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xaf0, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xaf4, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xaf8, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xafc, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xb00, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xb04, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xb08, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xb0c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xb10, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xb14, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0xb18, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	>;
	};

	debugss_pins: pinmux_debugss_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0xa90, PIN_INPUT_PULLDOWN)
	AM4372_IOPAD(0xa94, PIN_INPUT_PULLDOWN)
	AM4372_IOPAD(0xa98, PIN_INPUT_PULLDOWN)
	AM4372_IOPAD(0xa9c, PIN_INPUT_PULLDOWN)
	AM4372_IOPAD(0xaa0, PIN_INPUT_PULLDOWN)
	AM4372_IOPAD(0xaa4, PIN_INPUT_PULLDOWN)
	AM4372_IOPAD(0xaa8, PIN_INPUT_PULLDOWN)
	>;
	};

	uart0_pins_default: uart0_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE0) /* uart0_ctsn.uart0_ctsn */
	AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE0) /* uart0_rtsn.uart0_rtsn */
	AM4372_IOPAD(0x970, PIN_INPUT_PULLUP \| SLEWCTRL_FAST \| DS0_PULL_UP_DOWN_EN \| MUX_MODE0) /* uart0_rxd.uart0_rxd */
	AM4372_IOPAD(0x974, PIN_INPUT \| PULL_DISABLE \| SLEWCTRL_FAST \| DS0_PULL_UP_DOWN_EN \| MUX_MODE0) /* uart0_txd.uart0_txd */
	>;
	};

	uart0_pins_sleep: uart0_pins_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* uart0_ctsn.uart0_ctsn */
	AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7) /* uart0_rtsn.uart0_rtsn */
	AM4372_IOPAD(0x970, PIN_INPUT_PULLUP \| SLEWCTRL_FAST \| DS0_PULL_UP_DOWN_EN \| MUX_MODE0) /* uart0_rxd.uart0_rxd */
	AM4372_IOPAD(0x974, PIN_INPUT_PULLDOWN \| SLEWCTRL_FAST \| DS0_PULL_UP_DOWN_EN \| MUX_MODE0) /* uart0_txd.uart0_txd */
	>;
	};

	matrix_keypad_default: matrix_keypad_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x9a4, PIN_OUTPUT \| MUX_MODE7)
	AM4372_IOPAD(0x9a8, PIN_OUTPUT \| MUX_MODE7)
	AM4372_IOPAD(0x9ac, PIN_INPUT \| PULL_DISABLE \| MUX_MODE9)
	AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN \| MUX_MODE0)
	>;
	};

	matrix_keypad_sleep: matrix_keypad_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x9a4, PULL_UP \| MUX_MODE7)
	AM4372_IOPAD(0x9a8, PULL_UP \| MUX_MODE7)
	AM4372_IOPAD(0x9ac, PIN_INPUT \| PULL_DISABLE \| MUX_MODE9)
	AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN \| MUX_MODE0)
	>;
	};
	};

	&uart0 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&uart0_pins_default>;
	pinctrl-1 = <&uart0_pins_sleep>;
	};

	&i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	clock-frequency = <100000>;

	tps65218: tps65218@24 {
	reg = <0x24>;
	compatible = "ti,tps65218";
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* NMIn */
	interrupt-controller;
	#interrupt-cells = <2>;

	dcdc1: regulator-dcdc1 {
	regulator-name = "vdd_core";
	regulator-min-microvolt = <912000>;
	regulator-max-microvolt = <1144000>;
	regulator-boot-on;
	regulator-always-on;
	};

	dcdc2: regulator-dcdc2 {
	regulator-name = "vdd_mpu";
	regulator-min-microvolt = <912000>;
	regulator-max-microvolt = <1378000>;
	regulator-boot-on;
	regulator-always-on;
	};

	dcdc3: regulator-dcdc3 {
	regulator-name = "vdcdc3";
	regulator-boot-on;
	regulator-always-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	regulator-state-disk {
	regulator-off-in-suspend;
	};
	};

	dcdc5: regulator-dcdc5 {
	regulator-name = "v1_0bat";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	dcdc6: regulator-dcdc6 {
	regulator-name = "v1_8bat";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	ldo1: regulator-ldo1 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};

	ov2659@30 {
	compatible = "ovti,ov2659";
	reg = <0x30>;

	clocks = <&refclk 0>;
	clock-names = "xvclk";

	port {
	ov2659_0: endpoint {
	remote-endpoint = <&vpfe1_ep>;
	link-frequencies = /bits/ 64 <70000000>;
	};
	};
	};
	};

	&i2c1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	pixcir_ts@5c {
	compatible = "pixcir,pixcir_tangoc";
	pinctrl-names = "default";
	pinctrl-0 = <&pixcir_ts_pins>;
	reg = <0x5c>;

	attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;

	/*
	* 0x264 represents the offset of padconf register of
	* gpio3_22 from am43xx_pinmux base.
	*/
	interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>,
	<&am43xx_pinmux 0x264>;
	interrupt-names = "tsc", "wakeup";

	touchscreen-size-x = <1024>;
	touchscreen-size-y = <600>;
	wakeup-source;
	};

	ov2659@30 {
	compatible = "ovti,ov2659";
	reg = <0x30>;

	clocks = <&refclk 0>;
	clock-names = "xvclk";

	port {
	ov2659_1: endpoint {
	remote-endpoint = <&vpfe0_ep>;
	link-frequencies = /bits/ 64 <70000000>;
	};
	};
	};

	tlv320aic3106: tlv320aic3106@1b {
	#sound-dai-cells = <0>;
	compatible = "ti,tlv320aic3106";
	reg = <0x1b>;
	status = "okay";

	/* Regulators */
	IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
	AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
	DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
	DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
	};
	};

	&epwmss0 {
	status = "okay";
	};

	&tscadc {
	status = "okay";

	adc {
	ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
	};

	&ecap0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&ecap0_pins>;
	};

	&gpio0 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpio0_pins>;
	status = "okay";

	p23 {
	gpio-hog;
	gpios = <23 GPIO_ACTIVE_HIGH>;
	/* SelEMMCorNAND selects between eMMC and NAND:
	* Low: NAND
	* High: eMMC
	* When changing this line make sure the newly
	* selected device node is enabled and the previously
	* selected device node is disabled.
	*/
	output-low;
	line-name = "SelEMMCorNAND";
	};
	};

	&gpio1 {
	status = "okay";
	};

	&gpio3 {
	status = "okay";
	};

	&gpio4 {
	status = "okay";
	};

	&gpio5 {
	pinctrl-names = "default";
	pinctrl-0 = <&display_mux_pins>;
	status = "okay";
	ti,no-reset-on-init;

	p8 {
	/*
	* SelLCDorHDMI selects between display and audio paths:
	* Low: HDMI display with audio via HDMI
	* High: LCD display with analog audio via aic3111 codec
	*/
	gpio-hog;
	gpios = <8 GPIO_ACTIVE_HIGH>;
	output-high;
	line-name = "SelLCDorHDMI";
	};
	};

	&mmc1 {
	status = "okay";
	vmmc-supply = <&evm_v3_3d>;
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
	};

	/* eMMC sits on mmc2 */
	&mmc2 {
	/*
	* When enabling eMMC, disable GPMC/NAND and set
	* SelEMMCorNAND to output-high
	*/
	status = "disabled";
	vmmc-supply = <&evm_v3_3d>;
	bus-width = <8>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&emmc_pins_default>;
	pinctrl-1 = <&emmc_pins_sleep>;
	ti,non-removable;
	};

	&mmc3 {
	status = "okay";
	/* these are on the crossbar and are outlined in the
	xbar-event-map element */
	dmas = <&edma_xbar 30 0 1>,
	<&edma_xbar 31 0 2>;
	dma-names = "tx", "rx";
	vmmc-supply = <&vmmcwl_fixed>;
	bus-width = <4>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mmc3_pins_default>;
	pinctrl-1 = <&mmc3_pins_sleep>;
	cap-power-off-card;
	keep-power-in-suspend;
	ti,non-removable;

	#address-cells = <1>;
	#size-cells = <0>;
	wlcore: wlcore@0 {
	compatible = "ti,wl1835";
	reg = <2>;
	interrupt-parent = <&gpio1>;
	interrupts = <23 IRQ_TYPE_EDGE_RISING>;
	};
	};

	&uart3 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_pins>;
	};

	&usb2_phy1 {
	status = "okay";
	};

	&usb1 {
	dr_mode = "otg";
	status = "okay";
	};

	&usb2_phy2 {
	status = "okay";
	};

	&usb2 {
	dr_mode = "host";
	status = "okay";
	};

	&mac {
	slaves = <1>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&cpsw_default>;
	pinctrl-1 = <&cpsw_sleep>;
	status = "okay";
	};

	&davinci_mdio {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_default>;
	pinctrl-1 = <&davinci_mdio_sleep>;
	status = "okay";

	ethphy0: ethernet-phy@0 {
	reg = <0>;
	};
	};

	&cpsw_emac0 {
	phy-handle = <&ethphy0>;
	- phy-mode = "rgmii";
	+ phy-mode = "rgmii-rxid";
	};

	&elm {
	status = "okay";
	};

	&gpmc {
	/*
	* When enabling GPMC, disable eMMC and set
	* SelEMMCorNAND to output-low
	*/
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&nand_flash_x8>;
	ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
	nand@0,0 {
	compatible = "ti,omap2-nand";
	reg = <0 0 4>; /* device IO registers */
	interrupt-parent = <&gpmc>;
	interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
	<1 IRQ_TYPE_NONE>; /* termcount */
	rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
	ti,nand-xfer-type = "prefetch-dma";
	ti,nand-ecc-opt = "bch16";
	ti,elm-id = <&elm>;
	nand-bus-width = <8>;
	gpmc,device-width = <1>;
	gpmc,sync-clk-ps = <0>;
	gpmc,cs-on-ns = <0>;
	gpmc,cs-rd-off-ns = <40>;
	gpmc,cs-wr-off-ns = <40>;
	gpmc,adv-on-ns = <0>;
	gpmc,adv-rd-off-ns = <25>;
	gpmc,adv-wr-off-ns = <25>;
	gpmc,we-on-ns = <0>;
	gpmc,we-off-ns = <20>;
	gpmc,oe-on-ns = <3>;
	gpmc,oe-off-ns = <30>;
	gpmc,access-ns = <30>;
	gpmc,rd-cycle-ns = <40>;
	gpmc,wr-cycle-ns = <40>;
	gpmc,bus-turnaround-ns = <0>;
	gpmc,cycle2cycle-delay-ns = <0>;
	gpmc,clk-activation-ns = <0>;
	gpmc,wr-access-ns = <40>;
	gpmc,wr-data-mux-bus-ns = <0>;
	/* MTD partition table */
	/* All SPL-* partitions are sized to minimal length
	* which can be independently programmable. For
	* NAND flash this is equal to size of erase-block */
	#address-cells = <1>;
	#size-cells = <1>;
	partition@0 {
	label = "NAND.SPL";
	reg = <0x00000000 0x00040000>;
	};
	partition@1 {
	label = "NAND.SPL.backup1";
	reg = <0x00040000 0x00040000>;
	};
	partition@2 {
	label = "NAND.SPL.backup2";
	reg = <0x00080000 0x00040000>;
	};
	partition@3 {
	label = "NAND.SPL.backup3";
	reg = <0x000c0000 0x00040000>;
	};
	partition@4 {
	label = "NAND.u-boot-spl-os";
	reg = <0x00100000 0x00080000>;
	};
	partition@5 {
	label = "NAND.u-boot";
	reg = <0x00180000 0x00100000>;
	};
	partition@6 {
	label = "NAND.u-boot-env";
	reg = <0x00280000 0x00040000>;
	};
	partition@7 {
	label = "NAND.u-boot-env.backup1";
	reg = <0x002c0000 0x00040000>;
	};
	partition@8 {
	label = "NAND.kernel";
	reg = <0x00300000 0x00700000>;
	};
	partition@9 {
	label = "NAND.file-system";
	reg = <0x00a00000 0x1f600000>;
	};
	};
	};

	&dss {
	status = "ok";

	pinctrl-names = "default";
	pinctrl-0 = <&dss_pins>;

	port {
	dpi_out: endpoint {
	remote-endpoint = <&lcd_in>;
	data-lines = <24>;
	};
	};
	};

	&dcan0 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&dcan0_default>;
	pinctrl-1 = <&dcan0_sleep>;
	status = "okay";
	};

	&dcan1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&dcan1_default>;
	pinctrl-1 = <&dcan1_sleep>;
	status = "okay";
	};

	&vpfe0 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&vpfe0_pins_default>;
	pinctrl-1 = <&vpfe0_pins_sleep>;

	port {
	vpfe0_ep: endpoint {
	remote-endpoint = <&ov2659_1>;
	ti,am437x-vpfe-interface = <0>;
	bus-width = <8>;
	hsync-active = <0>;
	vsync-active = <0>;
	};
	};
	};

	&vpfe1 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&vpfe1_pins_default>;
	pinctrl-1 = <&vpfe1_pins_sleep>;

	port {
	vpfe1_ep: endpoint {
	remote-endpoint = <&ov2659_0>;
	ti,am437x-vpfe-interface = <0>;
	bus-width = <8>;
	hsync-active = <0>;
	vsync-active = <0>;
	};
	};
	};

	&mcasp1 {
	#sound-dai-cells = <0>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mcasp1_pins>;
	pinctrl-1 = <&mcasp1_sleep_pins>;

	status = "okay";

	op-mode = <0>; /* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializers */
	serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
	0 0 1 2
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
	};

	&rtc {
	clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
	clock-names = "ext-clk", "int-clk";
	status = "okay";
	};

	&cpu {
	cpu0-supply = <&dcdc2>;
	};
	diff --git a/sys/gnu/dts/arm/am437x-idk-evm.dts b/sys/gnu/dts/arm/am437x-idk-evm.dts
	index 9f66f96d09c9..a958f9ee4a5a 100644
	--- a/sys/gnu/dts/arm/am437x-idk-evm.dts
	+++ b/sys/gnu/dts/arm/am437x-idk-evm.dts
	@@ -1,536 +1,536 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
	*/

	/dts-v1/;

	#include "am4372.dtsi"
	#include <dt-bindings/pinctrl/am43xx.h>
	#include <dt-bindings/pwm/pwm.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>

	/ {
	model = "TI AM437x Industrial Development Kit";
	compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43";

	chosen {
	stdout-path = &uart0;
	};

	v24_0d: fixed-regulator-v24_0d {
	compatible = "regulator-fixed";
	regulator-name = "V24_0D";
	regulator-min-microvolt = <24000000>;
	regulator-max-microvolt = <24000000>;
	regulator-always-on;
	regulator-boot-on;
	};

	v3_3d: fixed-regulator-v3_3d {
	compatible = "regulator-fixed";
	regulator-name = "V3_3D";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&v24_0d>;
	};

	vdd_corereg: fixed-regulator-vdd_corereg {
	compatible = "regulator-fixed";
	regulator-name = "VDD_COREREG";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&v24_0d>;
	};

	vdd_core: fixed-regulator-vdd_core {
	compatible = "regulator-fixed";
	regulator-name = "VDD_CORE";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vdd_corereg>;
	};

	v1_8dreg: fixed-regulator-v1_8dreg{
	compatible = "regulator-fixed";
	regulator-name = "V1_8DREG";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&v24_0d>;
	};

	v1_8d: fixed-regulator-v1_8d{
	compatible = "regulator-fixed";
	regulator-name = "V1_8D";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&v1_8dreg>;
	};

	v1_5dreg: fixed-regulator-v1_5dreg{
	compatible = "regulator-fixed";
	regulator-name = "V1_5DREG";
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&v24_0d>;
	};

	v1_5d: fixed-regulator-v1_5d{
	compatible = "regulator-fixed";
	regulator-name = "V1_5D";
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&v1_5dreg>;
	};

	gpio_keys: gpio_keys {
	compatible = "gpio-keys";
	pinctrl-names = "default";
	pinctrl-0 = <&gpio_keys_pins_default>;
	#address-cells = <1>;
	#size-cells = <0>;

	switch0 {
	label = "power-button";
	linux,code = <KEY_POWER>;
	gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
	};
	};

	/* fixed 32k external oscillator clock */
	clk_32k_rtc: clk_32k_rtc {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	};

	leds-iio {
	status = "disabled";
	compatible = "gpio-leds";
	led-out0 {
	label = "out0";
	gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	led-out1 {
	label = "out1";
	gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	led-out2 {
	label = "out2";
	gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	led-out3 {
	label = "out3";
	gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	led-out4 {
	label = "out4";
	gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	led-out5 {
	label = "out5";
	gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	led-out6 {
	label = "out6";
	gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	led-out7 {
	label = "out7";
	gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};
	};
	};

	&am43xx_pinmux {
	gpio_keys_pins_default: gpio_keys_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x9b8, PIN_INPUT \| MUX_MODE7) /* cam0_field.gpio4_2 */
	>;
	};

	i2c0_pins_default: i2c0_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x988, PIN_INPUT \| SLEWCTRL_FAST \| MUX_MODE0) /* i2c0_sda.i2c0_sda */
	AM4372_IOPAD(0x98c, PIN_INPUT \| SLEWCTRL_FAST \| MUX_MODE0) /* i2c0_scl.i2c0_scl */
	>;
	};

	i2c0_pins_sleep: i2c0_pins_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	>;
	};

	i2c2_pins_default: i2c2_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x9e8, PIN_INPUT \| SLEWCTRL_FAST \| MUX_MODE3) /* cam1_data1.i2c2_scl */
	AM4372_IOPAD(0x9ec, PIN_INPUT \| SLEWCTRL_FAST \| MUX_MODE3) /* cam1_data0.i2c2_sda */
	>;
	};

	i2c2_pins_sleep: i2c2_pins_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x9e8, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x9ec, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	>;
	};

	mmc1_pins_default: pinmux_mmc1_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x900, PIN_INPUT \| MUX_MODE0) /* mmc0_clk.mmc0_clk */
	AM4372_IOPAD(0x904, PIN_INPUT \| MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
	AM4372_IOPAD(0x9f0, PIN_INPUT \| MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
	AM4372_IOPAD(0x9f4, PIN_INPUT \| MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
	AM4372_IOPAD(0x9f8, PIN_INPUT \| MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
	AM4372_IOPAD(0x9fc, PIN_INPUT \| MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
	AM4372_IOPAD(0x960, PIN_INPUT \| MUX_MODE7) /* spi0_cs1.gpio0_6 */
	>;
	};

	mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x900, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x904, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x960, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	>;
	};

	spi1_pins_default: spi1_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x908, PIN_INPUT \| MUX_MODE2) /* mii1_col.spi1_sclk */
	AM4372_IOPAD(0x910, PIN_INPUT \| MUX_MODE2) /* mii1_rx_er.spi1_d1 */
	AM4372_IOPAD(0x944, PIN_OUTPUT \| MUX_MODE2) /* rmii1_ref_clk.spi1_cs0 */
	AM4372_IOPAD(0x90c, PIN_OUTPUT \| MUX_MODE7) /* mii1_crs.gpio3_1 */
	>;
	};

	spi1_pins_sleep: spi1_pins_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	>;
	};

	ecap0_pins_default: backlight_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x964, PIN_OUTPUT \| MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */
	>;
	};

	cpsw_default: cpsw_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN \| MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
	AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN \| MUX_MODE2) /* mii1_txen.rgmii1_tctl */
	AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN \| MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
	AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN \| MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
	AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN \| MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
	AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN \| MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
	AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN \| MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
	AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN \| MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
	AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN \| MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
	AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN \| MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
	AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN \| MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
	AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN \| MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
	>;
	};

	cpsw_sleep: cpsw_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	>;
	};

	davinci_mdio_default: davinci_mdio_default {
	pinctrl-single,pins = <
	/* MDIO */
	AM4372_IOPAD(0x948, PIN_INPUT_PULLUP \| SLEWCTRL_FAST \| MUX_MODE0) /* mdio_data.mdio_data */
	AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP \| MUX_MODE0) /* mdio_clk.mdio_clk */
	>;
	};

	davinci_mdio_sleep: davinci_mdio_sleep {
	pinctrl-single,pins = <
	/* MDIO reset value */
	AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	>;
	};

	qspi_pins_default: qspi_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP \| MUX_MODE3) /* gpmc_csn0.qspi_csn */
	AM4372_IOPAD(0x888, PIN_OUTPUT \| MUX_MODE2) /* gpmc_csn3.qspi_clk */
	AM4372_IOPAD(0x890, PIN_INPUT_PULLUP \| MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
	AM4372_IOPAD(0x894, PIN_INPUT_PULLUP \| MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
	AM4372_IOPAD(0x898, PIN_INPUT_PULLUP \| MUX_MODE3) /* gpmc_wen.qspi_d2 */
	AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP \| MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
	>;
	};

	qspi_pins_sleep: qspi_pins_sleep{
	pinctrl-single,pins = <
	AM4372_IOPAD(0x87c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x890, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x894, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x898, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x89c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	>;
	};
	};

	&i2c0 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c0_pins_default>;
	pinctrl-1 = <&i2c0_pins_sleep>;
	clock-frequency = <400000>;

	at24@50 {
	compatible = "atmel,24c256";
	pagesize = <64>;
	reg = <0x50>;
	};

	tps: tps62362@60 {
	compatible = "ti,tps62362";
	reg = <0x60>;
	regulator-name = "VDD_MPU";
	regulator-min-microvolt = <950000>;
	regulator-max-microvolt = <1330000>;
	regulator-boot-on;
	regulator-always-on;
	ti,vsel0-state-high;
	ti,vsel1-state-high;
	vin-supply = <&v3_3d>;
	};
	};

	&i2c2 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c2_pins_default>;
	pinctrl-1 = <&i2c2_pins_sleep>;
	clock-frequency = <100000>;

	tpic2810: tpic2810@60 {
	compatible = "ti,tpic2810";
	reg = <0x60>;
	gpio-controller;
	#gpio-cells = <2>;
	};
	};

	&spi1 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&spi1_pins_default>;
	pinctrl-1 = <&spi1_pins_sleep>;
	ti,pindir-d0-out-d1-in;

	sn65hvs882: sn65hvs882@0 {
	compatible = "pisosr-gpio";
	gpio-controller;
	#gpio-cells = <2>;

	load-gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;

	reg = <0>;
	spi-max-frequency = <1000000>;
	spi-cpol;
	};
	};

	&epwmss0 {
	status = "okay";
	};

	&ecap0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&ecap0_pins_default>;
	};

	&gpio0 {
	status = "okay";
	};

	&gpio1 {
	status = "okay";
	};

	&gpio3 {
	status = "okay";
	};

	&gpio4 {
	status = "okay";
	};

	&gpio5 {
	status = "okay";
	};

	&mmc1 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_sleep>;
	vmmc-supply = <&v3_3d>;
	bus-width = <4>;
	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
	};

	&qspi {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&qspi_pins_default>;
	pinctrl-1 = <&qspi_pins_sleep>;

	spi-max-frequency = <48000000>;
	m25p80@0 {
	compatible = "mx66l51235l";
	spi-max-frequency = <48000000>;
	reg = <0>;
	spi-cpol;
	spi-cpha;
	spi-tx-bus-width = <1>;
	spi-rx-bus-width = <4>;
	#address-cells = <1>;
	#size-cells = <1>;

	/*
	* MTD partition table. The ROM checks the first 512KiB for a
	* valid file to boot(XIP).
	*/
	partition@0 {
	label = "QSPI.U_BOOT";
	reg = <0x00000000 0x000080000>;
	};
	partition@1 {
	label = "QSPI.U_BOOT.backup";
	reg = <0x00080000 0x00080000>;
	};
	partition@2 {
	label = "QSPI.U-BOOT-SPL_OS";
	reg = <0x00100000 0x00010000>;
	};
	partition@3 {
	label = "QSPI.U_BOOT_ENV";
	reg = <0x00110000 0x00010000>;
	};
	partition@4 {
	label = "QSPI.U-BOOT-ENV.backup";
	reg = <0x00120000 0x00010000>;
	};
	partition@5 {
	label = "QSPI.KERNEL";
	reg = <0x00130000 0x0800000>;
	};
	partition@6 {
	label = "QSPI.FILESYSTEM";
	reg = <0x00930000 0x36D0000>;
	};
	};
	};

	&mac {
	slaves = <1>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&cpsw_default>;
	pinctrl-1 = <&cpsw_sleep>;
	status = "okay";
	};

	&davinci_mdio {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_default>;
	pinctrl-1 = <&davinci_mdio_sleep>;
	status = "okay";

	ethphy0: ethernet-phy@0 {
	reg = <0>;
	};
	};

	&cpsw_emac0 {
	phy-handle = <&ethphy0>;
	- phy-mode = "rgmii";
	+ phy-mode = "rgmii-rxid";
	};

	&rtc {
	clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
	clock-names = "ext-clk", "int-clk";
	status = "okay";
	};

	&wdt {
	status = "okay";
	};

	&cpu {
	cpu0-supply = <&tps>;
	};

	&cpu0_opp_table {
	/*
	* Supply voltage supervisor on board will not allow opp50 so
	* disable it and set opp100 as suspend OPP.
	*/
	opp50-300000000 {
	status = "disabled";
	};

	opp100-600000000 {
	opp-suspend;
	};
	};
	diff --git a/sys/gnu/dts/arm/am437x-l4.dtsi b/sys/gnu/dts/arm/am437x-l4.dtsi
	index e18e17d31272..49c6a872052e 100644
	--- a/sys/gnu/dts/arm/am437x-l4.dtsi
	+++ b/sys/gnu/dts/arm/am437x-l4.dtsi
	@@ -1,2452 +1,2527 @@
	&l4_wkup { /* 0x44c00000 */
	compatible = "ti,am4-l4-wkup", "simple-bus";
	reg = <0x44c00000 0x800>,
	<0x44c00800 0x800>,
	<0x44c01000 0x400>,
	<0x44c01400 0x400>;
	reg-names = "ap", "la", "ia0", "ia1";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
	<0x00100000 0x44d00000 0x100000>, /* segment 1 */
	<0x00200000 0x44e00000 0x100000>; /* segment 2 */

	segment@0 { /* 0x44c00000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
	<0x00000800 0x00000800 0x000800>, /* ap 1 */
	<0x00001000 0x00001000 0x000400>, /* ap 2 */
	<0x00001400 0x00001400 0x000400>; /* ap 3 */
	};

	segment@100000 { /* 0x44d00000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */
	<0x00004000 0x00104000 0x001000>, /* ap 5 */
	<0x00080000 0x00180000 0x002000>, /* ap 6 */
	<0x00082000 0x00182000 0x001000>, /* ap 7 */
	<0x000f0000 0x001f0000 0x010000>; /* ap 8 */

	target-module@0 { /* 0x44d00000, ap 4 28.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x4000>;
	};

	target-module@80000 { /* 0x44d80000, ap 6 10.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x80000 0x2000>;
	};

	target-module@f0000 { /* 0x44df0000, ap 8 58.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xf0000 0x4>;
	reg-names = "rev";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf0000 0x10000>;

	prcm: prcm@0 {
	compatible = "ti,am4-prcm", "simple-bus";
	reg = <0x0 0x11000>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x11000>;

	prcm_clocks: clocks {
	#address-cells = <1>;
	#size-cells = <0>;
	};

	prcm_clockdomains: clockdomains {
	};
	};
	};
	};

	segment@200000 { /* 0x44e00000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00200000 0x001000>, /* ap 9 */
	<0x00003000 0x00203000 0x001000>, /* ap 10 */
	<0x00004000 0x00204000 0x001000>, /* ap 11 */
	<0x00005000 0x00205000 0x001000>, /* ap 12 */
	<0x00006000 0x00206000 0x001000>, /* ap 13 */
	<0x00007000 0x00207000 0x001000>, /* ap 14 */
	<0x00008000 0x00208000 0x001000>, /* ap 15 */
	<0x00009000 0x00209000 0x001000>, /* ap 16 */
	<0x0000a000 0x0020a000 0x001000>, /* ap 17 */
	<0x0000b000 0x0020b000 0x001000>, /* ap 18 */
	<0x0000c000 0x0020c000 0x001000>, /* ap 19 */
	<0x0000d000 0x0020d000 0x001000>, /* ap 20 */
	<0x0000f000 0x0020f000 0x001000>, /* ap 21 */
	<0x00010000 0x00210000 0x010000>, /* ap 22 */
	<0x00030000 0x00230000 0x001000>, /* ap 23 */
	<0x00031000 0x00231000 0x001000>, /* ap 24 */
	<0x00032000 0x00232000 0x001000>, /* ap 25 */
	<0x00033000 0x00233000 0x001000>, /* ap 26 */
	<0x00034000 0x00234000 0x001000>, /* ap 27 */
	<0x00035000 0x00235000 0x001000>, /* ap 28 */
	<0x00036000 0x00236000 0x001000>, /* ap 29 */
	<0x00037000 0x00237000 0x001000>, /* ap 30 */
	<0x00038000 0x00238000 0x001000>, /* ap 31 */
	<0x00039000 0x00239000 0x001000>, /* ap 32 */
	<0x0003a000 0x0023a000 0x001000>, /* ap 33 */
	<0x0003e000 0x0023e000 0x001000>, /* ap 34 */
	<0x0003f000 0x0023f000 0x001000>, /* ap 35 */
	<0x00040000 0x00240000 0x040000>, /* ap 36 */
	<0x00080000 0x00280000 0x001000>, /* ap 37 */
	<0x00088000 0x00288000 0x008000>, /* ap 38 */
	<0x00092000 0x00292000 0x001000>, /* ap 39 */
	<0x00086000 0x00286000 0x001000>, /* ap 40 */
	<0x00087000 0x00287000 0x001000>, /* ap 41 */
	<0x00090000 0x00290000 0x001000>, /* ap 42 */
	<0x00091000 0x00291000 0x001000>; /* ap 43 */

	target-module@3000 { /* 0x44e03000, ap 10 0a.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x3000 0x1000>;
	};

	target-module@5000 { /* 0x44e05000, ap 12 30.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x5000 0x1000>;
	};

	target-module@7000 { /* 0x44e07000, ap 14 20.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x7000 0x4>,
	<0x7010 0x4>,
	<0x7114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
	clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 0>,
	<&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 8>;
	clock-names = "fck", "dbclk";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x7000 0x1000>;

	gpio0: gpio@0 {
	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	reg = <0x0 0x1000>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	status = "disabled";
	};
	};

	target-module@9000 { /* 0x44e09000, ap 16 04.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x9050 0x4>,
	<0x9054 0x4>,
	<0x9058 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
	clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_UART1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x9000 0x1000>;

	uart0: serial@0 {
	compatible = "ti,am4372-uart","ti,omap2-uart";
	reg = <0x0 0x2000>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xb000 0x8>,
	<0xb010 0x8>,
	<0xb090 0x8>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
	clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_I2C1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xb000 0x1000>;

	i2c0: i2c@0 {
	compatible = "ti,am4372-i2c","ti,omap4-i2c";
	reg = <0x0 0x1000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};
	};

	target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xd000 0x4>,
	<0xd010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): wkup_pwrdm, l3s_tsc_clkdm */
	clocks = <&l3s_tsc_clkctrl AM4_L3S_TSC_ADC_TSC_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xd000 0x1000>;

	tscadc: tscadc@0 {
	compatible = "ti,am3359-tscadc";
	reg = <0x0 0x1000>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&adc_tsc_fck>;
	clock-names = "fck";
	status = "disabled";
	dmas = <&edma 53 0>, <&edma 57 0>;
	dma-names = "fifo0", "fifo1";

	tsc {
	compatible = "ti,am3359-tsc";
	};

	adc {
	#io-channel-cells = <1>;
	compatible = "ti,am3359-adc";
	};

	};
	};

	target-module@10000 { /* 0x44e10000, ap 22 0c.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x10000 0x4>;
	reg-names = "rev";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x10000 0x10000>;

	scm: scm@0 {
	compatible = "ti,am4-scm", "simple-bus";
	reg = <0x0 0x4000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x4000>;

	am43xx_pinmux: pinmux@800 {
	compatible = "ti,am437-padconf",
	"pinctrl-single";
	reg = <0x800 0x31c>;
	#address-cells = <1>;
	#size-cells = <0>;
	#pinctrl-cells = <1>;
	#interrupt-cells = <1>;
	interrupt-controller;
	pinctrl-single,register-width = <32>;
	pinctrl-single,function-mask = <0xffffffff>;
	};

	scm_conf: scm_conf@0 {
	compatible = "syscon", "simple-bus";
	reg = <0x0 0x800>;
	#address-cells = <1>;
	#size-cells = <1>;

	phy_gmii_sel: phy-gmii-sel {
	compatible = "ti,am43xx-phy-gmii-sel";
	reg = <0x650 0x4>;
	#phy-cells = <2>;
	};

	scm_clocks: clocks {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	wkup_m3_ipc: wkup_m3_ipc@1324 {
	compatible = "ti,am4372-wkup-m3-ipc";
	reg = <0x1324 0x44>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	ti,rproc = <&wkup_m3>;
	mboxes = <&mailbox &mbox_wkupm3>;
	};

	edma_xbar: dma-router@f90 {
	compatible = "ti,am335x-edma-crossbar";
	reg = <0xf90 0x40>;
	#dma-cells = <3>;
	dma-requests = <64>;
	dma-masters = <&edma>;
	};

	scm_clockdomains: clockdomains {
	};
	};
	};

	target-module@31000 { /* 0x44e31000, ap 24 40.0 */
	compatible = "ti,sysc-omap2-timer", "ti,sysc";
	ti,hwmods = "timer1";
	reg = <0x31000 0x4>,
	<0x31010 0x4>,
	<0x31014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
	clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x31000 0x1000>;

	timer1: timer@0 {
	compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	ti,timer-alwon;
	clocks = <&timer1_fck>;
	clock-names = "fck";
	};
	};

	target-module@33000 { /* 0x44e33000, ap 26 18.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x33000 0x1000>;
	};

	target-module@35000 { /* 0x44e35000, ap 28 50.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x35000 0x4>,
	<0x35010 0x4>,
	<0x35014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_EMUFREE \|
	SYSC_OMAP2_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
	clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_WD_TIMER2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x35000 0x1000>;

	wdt: wdt@0 {
	compatible = "ti,am4372-wdt","ti,omap3-wdt";
	reg = <0x0 0x1000>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	target-module@37000 { /* 0x44e37000, ap 30 08.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x37000 0x1000>;
	};

	target-module@39000 { /* 0x44e39000, ap 32 02.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x39000 0x1000>;
	};

	target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */
	compatible = "ti,sysc-omap4-simple", "ti,sysc";
	ti,hwmods = "rtc";
	reg = <0x3e074 0x4>,
	<0x3e078 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */
	clocks = <&l4_rtc_clkctrl AM4_L4_RTC_RTC_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x3e000 0x1000>;

	rtc: rtc@0 {
	compatible = "ti,am4372-rtc", "ti,am3352-rtc",
	"ti,da830-rtc";
	reg = <0x0 0x1000>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
	GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk_32768_ck>;
	clock-names = "int-clk";
	system-power-controller;
	status = "disabled";
	};
	};

	target-module@40000 { /* 0x44e40000, ap 36 68.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x40000 0x40000>;
	};

	target-module@86000 { /* 0x44e86000, ap 40 70.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	ti,hwmods = "counter_32k";
	reg = <0x86000 0x4>,
	<0x86004 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>;
	/* Domains (P, C): wkup_pwrdm, l4_wkup_aon_clkdm */
	clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x86000 0x1000>;

	counter32k: counter@0 {
	compatible = "ti,am4372-counter32k","ti,omap-counter32k";
	reg = <0x0 0x40>;
	};
	};

	target-module@88000 { /* 0x44e88000, ap 38 12.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00088000 0x00008000>,
	<0x00008000 0x00090000 0x00001000>,
	<0x00009000 0x00091000 0x00001000>;
	};
	};
	};

	&l4_fast { /* 0x4a000000 */
	compatible = "ti,am4-l4-fast", "simple-bus";
	reg = <0x4a000000 0x800>,
	<0x4a000800 0x800>,
	<0x4a001000 0x400>;
	reg-names = "ap", "la", "ia0";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */

	segment@0 { /* 0x4a000000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
	<0x00000800 0x00000800 0x000800>, /* ap 1 */
	<0x00001000 0x00001000 0x000400>, /* ap 2 */
	<0x00100000 0x00100000 0x008000>, /* ap 3 */
	<0x00108000 0x00108000 0x001000>, /* ap 4 */
	<0x00400000 0x00400000 0x002000>, /* ap 5 */
	<0x00402000 0x00402000 0x001000>, /* ap 6 */
	<0x00200000 0x00200000 0x080000>, /* ap 7 */
	<0x00280000 0x00280000 0x001000>; /* ap 8 */

	target-module@100000 { /* 0x4a100000, ap 3 04.0 */
	compatible = "ti,sysc-omap4-simple", "ti,sysc";
	reg = <0x101200 0x4>,
	<0x101208 0x4>,
	<0x101204 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <0>;
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>;
	ti,syss-mask = <1>;
	clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x100000 0x8000>;

	mac: ethernet@0 {
	compatible = "ti,am4372-cpsw","ti,cpsw";
	reg = <0x0 0x800
	0x1200 0x100>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
	GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
	GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
	GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <1>;
	clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
	<&dpll_clksel_mac_clk>;
	clock-names = "fck", "cpts", "50mclk";
	assigned-clocks = <&dpll_clksel_mac_clk>;
	assigned-clock-rates = <50000000>;
	status = "disabled";
	cpdma_channels = <8>;
	ale_entries = <1024>;
	bd_ram_size = <0x2000>;
	mac_control = <0x20>;
	slaves = <2>;
	active_slave = <0>;
	cpts_clock_mult = <0x80000000>;
	cpts_clock_shift = <29>;
	ranges = <0 0 0x8000>;
	syscon = <&scm_conf>;

	davinci_mdio: mdio@1000 {
	compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio";
	reg = <0x1000 0x100>;
	clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <0>;
	bus_freq = <1000000>;
	status = "disabled";
	};

	cpsw_emac0: slave@200 {
	/* Filled in by U-Boot */
	mac-address = [ 00 00 00 00 00 00 ];
	phys = <&phy_gmii_sel 1 0>;
	};

	cpsw_emac1: slave@300 {
	/* Filled in by U-Boot */
	mac-address = [ 00 00 00 00 00 00 ];
	phys = <&phy_gmii_sel 2 0>;
	};
	};
	};

	target-module@200000 { /* 0x4a200000, ap 7 02.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x200000 0x80000>;
	};

	target-module@400000 { /* 0x4a400000, ap 5 08.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x400000 0x2000>;
	};
	};
	};

	&l4_per { /* 0x48000000 */
	compatible = "ti,am4-l4-per", "simple-bus";
	reg = <0x48000000 0x800>,
	<0x48000800 0x800>,
	<0x48001000 0x400>,
	<0x48001400 0x400>,
	<0x48001800 0x400>,
	<0x48001c00 0x400>;
	reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */
	<0x00100000 0x48100000 0x100000>, /* segment 1 */
	<0x00200000 0x48200000 0x100000>, /* segment 2 */
	<0x00300000 0x48300000 0x100000>, /* segment 3 */
	<0x46000000 0x46000000 0x400000>, /* l3 data port */
	<0x46400000 0x46400000 0x400000>; /* l3 data port */

	segment@0 { /* 0x48000000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
	<0x00000800 0x00000800 0x000800>, /* ap 1 */
	<0x00001000 0x00001000 0x000400>, /* ap 2 */
	<0x00001400 0x00001400 0x000400>, /* ap 3 */
	<0x00001800 0x00001800 0x000400>, /* ap 4 */
	<0x00001c00 0x00001c00 0x000400>, /* ap 5 */
	<0x00008000 0x00008000 0x001000>, /* ap 6 */
	<0x00009000 0x00009000 0x001000>, /* ap 7 */
	<0x00022000 0x00022000 0x001000>, /* ap 8 */
	<0x00023000 0x00023000 0x001000>, /* ap 9 */
	<0x00024000 0x00024000 0x001000>, /* ap 10 */
	<0x00025000 0x00025000 0x001000>, /* ap 11 */
	<0x0002a000 0x0002a000 0x001000>, /* ap 12 */
	<0x0002b000 0x0002b000 0x001000>, /* ap 13 */
	<0x00038000 0x00038000 0x002000>, /* ap 14 */
	<0x0003a000 0x0003a000 0x001000>, /* ap 15 */
	<0x0003c000 0x0003c000 0x002000>, /* ap 16 */
	<0x0003e000 0x0003e000 0x001000>, /* ap 17 */
	<0x00040000 0x00040000 0x001000>, /* ap 18 */
	<0x00041000 0x00041000 0x001000>, /* ap 19 */
	<0x00042000 0x00042000 0x001000>, /* ap 20 */
	<0x00043000 0x00043000 0x001000>, /* ap 21 */
	<0x00044000 0x00044000 0x001000>, /* ap 22 */
	<0x00045000 0x00045000 0x001000>, /* ap 23 */
	<0x00046000 0x00046000 0x001000>, /* ap 24 */
	<0x00047000 0x00047000 0x001000>, /* ap 25 */
	<0x00048000 0x00048000 0x001000>, /* ap 26 */
	<0x00049000 0x00049000 0x001000>, /* ap 27 */
	<0x0004c000 0x0004c000 0x001000>, /* ap 28 */
	<0x0004d000 0x0004d000 0x001000>, /* ap 29 */
	<0x00060000 0x00060000 0x001000>, /* ap 30 */
	<0x00061000 0x00061000 0x001000>, /* ap 31 */
	<0x00080000 0x00080000 0x010000>, /* ap 32 */
	<0x00090000 0x00090000 0x001000>, /* ap 33 */
	<0x00030000 0x00030000 0x001000>, /* ap 65 */
	<0x00031000 0x00031000 0x001000>, /* ap 66 */
	<0x0004a000 0x0004a000 0x001000>, /* ap 71 */
	<0x0004b000 0x0004b000 0x001000>, /* ap 72 */
	<0x000c8000 0x000c8000 0x001000>, /* ap 73 */
	<0x000c9000 0x000c9000 0x001000>, /* ap 74 */
	<0x000ca000 0x000ca000 0x001000>, /* ap 77 */
	<0x000cb000 0x000cb000 0x001000>, /* ap 78 */
	<0x00034000 0x00034000 0x001000>, /* ap 80 */
	<0x00035000 0x00035000 0x001000>, /* ap 81 */
	<0x00036000 0x00036000 0x001000>, /* ap 84 */
	<0x00037000 0x00037000 0x001000>, /* ap 85 */
	<0x46000000 0x46000000 0x400000>, /* l3 data port */
	<0x46400000 0x46400000 0x400000>; /* l3 data port */

	target-module@8000 { /* 0x48008000, ap 6 10.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x8000 0x1000>;
	};

	target-module@22000 { /* 0x48022000, ap 8 0a.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x22050 0x4>,
	<0x22054 0x4>,
	<0x22058 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_UART2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x22000 0x1000>;

	uart1: serial@0 {
	compatible = "ti,am4372-uart","ti,omap2-uart";
	reg = <0x0 0x2000>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	target-module@24000 { /* 0x48024000, ap 10 1c.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x24050 0x4>,
	<0x24054 0x4>,
	<0x24058 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_UART3_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x24000 0x1000>;

	uart2: serial@0 {
	compatible = "ti,am4372-uart","ti,omap2-uart";
	reg = <0x0 0x2000>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	target-module@2a000 { /* 0x4802a000, ap 12 22.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x2a000 0x8>,
	<0x2a010 0x8>,
	<0x2a090 0x8>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_I2C2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x2a000 0x1000>;

	i2c1: i2c@0 {
	compatible = "ti,am4372-i2c","ti,omap4-i2c";
	reg = <0x0 0x1000>;
	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};
	};

	target-module@30000 { /* 0x48030000, ap 65 08.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x30000 0x4>,
	<0x30110 0x4>,
	<0x30114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_SPI0_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x30000 0x1000>;

	spi0: spi@0 {
	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};
	};

	target-module@34000 { /* 0x48034000, ap 80 56.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x34000 0x1000>;
	};

	target-module@36000 { /* 0x48036000, ap 84 3e.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x36000 0x1000>;
	};

	target-module@38000 { /* 0x48038000, ap 14 04.0 */
	compatible = "ti,sysc-omap4-simple", "ti,sysc";
	reg = <0x38000 0x4>,
	<0x38004 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	/* Domains (P, C): per_pwrdm, l3s_clkdm */
	clocks = <&l3s_clkctrl AM4_L3S_MCASP0_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x38000 0x2000>,
	<0x46000000 0x46000000 0x400000>;

	mcasp0: mcasp@0 {
	compatible = "ti,am33xx-mcasp-audio";
	reg = <0x0 0x2000>,
	<0x46000000 0x400000>;
	reg-names = "mpu", "dat";
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "tx", "rx";
	status = "disabled";
	dmas = <&edma 8 2>,
	<&edma 9 2>;
	dma-names = "tx", "rx";
	};
	};

	target-module@3c000 { /* 0x4803c000, ap 16 2a.0 */
	compatible = "ti,sysc-omap4-simple", "ti,sysc";
	reg = <0x3c000 0x4>,
	<0x3c004 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	/* Domains (P, C): per_pwrdm, l3s_clkdm */
	clocks = <&l3s_clkctrl AM4_L3S_MCASP1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x3c000 0x2000>,
	<0x46400000 0x46400000 0x400000>;

	mcasp1: mcasp@0 {
	compatible = "ti,am33xx-mcasp-audio";
	reg = <0x0 0x2000>,
	<0x46400000 0x400000>;
	reg-names = "mpu", "dat";
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "tx", "rx";
	status = "disabled";
	dmas = <&edma 10 2>,
	<&edma 11 2>;
	dma-names = "tx", "rx";
	};
	};

	target-module@40000 { /* 0x48040000, ap 18 1e.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	ti,hwmods = "timer2";
	reg = <0x40000 0x4>,
	<0x40010 0x4>,
	<0x40014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x40000 0x1000>;

	timer2: timer@0 {
	compatible = "ti,am4372-timer","ti,am335x-timer";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&timer2_fck>;
	clock-names = "fck";
	};
	};

	target-module@42000 { /* 0x48042000, ap 20 24.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x42000 0x4>,
	<0x42010 0x4>,
	<0x42014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_TIMER3_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x42000 0x1000>;

	timer3: timer@0 {
	compatible = "ti,am4372-timer","ti,am335x-timer";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	target-module@44000 { /* 0x48044000, ap 22 26.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x44000 0x4>,
	<0x44010 0x4>,
	<0x44014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_TIMER4_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x44000 0x1000>;

	timer4: timer@0 {
	compatible = "ti,am4372-timer","ti,am335x-timer";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	ti,timer-pwm;
	status = "disabled";
	};
	};

	target-module@46000 { /* 0x48046000, ap 24 28.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x46000 0x4>,
	<0x46010 0x4>,
	<0x46014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_TIMER5_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x46000 0x1000>;

	timer5: timer@0 {
	compatible = "ti,am4372-timer","ti,am335x-timer";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	ti,timer-pwm;
	status = "disabled";
	};
	};

	target-module@48000 { /* 0x48048000, ap 26 1a.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x48000 0x4>,
	<0x48010 0x4>,
	<0x48014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_TIMER6_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x48000 0x1000>;

	timer6: timer@0 {
	compatible = "ti,am4372-timer","ti,am335x-timer";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	ti,timer-pwm;
	status = "disabled";
	};
	};

	target-module@4a000 { /* 0x4804a000, ap 71 48.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x4a000 0x4>,
	<0x4a010 0x4>,
	<0x4a014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_TIMER7_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4a000 0x1000>;

	timer7: timer@0 {
	compatible = "ti,am4372-timer","ti,am335x-timer";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	ti,timer-pwm;
	status = "disabled";
	};
	};

	target-module@4c000 { /* 0x4804c000, ap 28 36.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x4c000 0x4>,
	<0x4c010 0x4>,
	<0x4c114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 0>,
	<&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 8>;
	clock-names = "fck", "dbclk";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4c000 0x1000>;

	gpio1: gpio@0 {
	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	reg = <0x0 0x1000>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	status = "disabled";
	};
	};

	target-module@60000 { /* 0x48060000, ap 30 14.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x602fc 0x4>,
	<0x60110 0x4>,
	<0x60114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_MMC1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x60000 0x1000>;

	mmc1: mmc@0 {
	compatible = "ti,omap4-hsmmc";
	reg = <0x0 0x1000>;
	ti,dual-volt;
	ti,needs-special-reset;
	dmas = <&edma 24 0>,
	<&edma 25 0>;
	dma-names = "tx", "rx";
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	target-module@80000 { /* 0x48080000, ap 32 18.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x80000 0x4>,
	<0x80010 0x4>,
	<0x80014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_ELM_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x80000 0x10000>;

	elm: elm@0 {
	compatible = "ti,am3352-elm";
	reg = <0x0 0x2000>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&l4ls_gclk>;
	clock-names = "fck";
	status = "disabled";
	};
	};

	target-module@c8000 { /* 0x480c8000, ap 73 06.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xc8000 0x4>,
	<0xc8010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_MAILBOX_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xc8000 0x1000>;

	mailbox: mailbox@0 {
	compatible = "ti,omap4-mailbox";
	reg = <0x0 0x200>;
	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	#mbox-cells = <1>;
	ti,mbox-num-users = <4>;
	ti,mbox-num-fifos = <8>;
	mbox_wkupm3: wkup_m3 {
	ti,mbox-send-noirq;
	ti,mbox-tx = <0 0 0>;
	ti,mbox-rx = <0 0 3>;
	};
	};
	};

	target-module@ca000 { /* 0x480ca000, ap 77 38.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xca000 0x4>,
	<0xca010 0x4>,
	<0xca014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_SPINLOCK_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xca000 0x1000>;

	hwspinlock: spinlock@0 {
	compatible = "ti,omap4-hwspinlock";
	reg = <0x0 0x1000>;
	#hwlock-cells = <1>;
	};
	};
	};

	segment@100000 { /* 0x48100000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 34 */
	<0x0008d000 0x0018d000 0x001000>, /* ap 35 */
	<0x0008e000 0x0018e000 0x001000>, /* ap 36 */
	<0x0008f000 0x0018f000 0x001000>, /* ap 37 */
	<0x0009c000 0x0019c000 0x001000>, /* ap 38 */
	<0x0009d000 0x0019d000 0x001000>, /* ap 39 */
	<0x000a6000 0x001a6000 0x001000>, /* ap 40 */
	<0x000a7000 0x001a7000 0x001000>, /* ap 41 */
	<0x000a8000 0x001a8000 0x001000>, /* ap 42 */
	<0x000a9000 0x001a9000 0x001000>, /* ap 43 */
	<0x000aa000 0x001aa000 0x001000>, /* ap 44 */
	<0x000ab000 0x001ab000 0x001000>, /* ap 45 */
	<0x000ac000 0x001ac000 0x001000>, /* ap 46 */
	<0x000ad000 0x001ad000 0x001000>, /* ap 47 */
	<0x000ae000 0x001ae000 0x001000>, /* ap 48 */
	<0x000af000 0x001af000 0x001000>, /* ap 49 */
	<0x000cc000 0x001cc000 0x002000>, /* ap 50 */
	<0x000ce000 0x001ce000 0x002000>, /* ap 51 */
	<0x000d0000 0x001d0000 0x002000>, /* ap 52 */
	<0x000d2000 0x001d2000 0x002000>, /* ap 53 */
	<0x000d8000 0x001d8000 0x001000>, /* ap 54 */
	<0x000d9000 0x001d9000 0x001000>, /* ap 55 */
	<0x000a0000 0x001a0000 0x001000>, /* ap 67 */
	<0x000a1000 0x001a1000 0x001000>, /* ap 68 */
	<0x000a2000 0x001a2000 0x001000>, /* ap 69 */
	<0x000a3000 0x001a3000 0x001000>, /* ap 70 */
	<0x000a4000 0x001a4000 0x001000>, /* ap 92 */
	<0x000a5000 0x001a5000 0x001000>, /* ap 93 */
	<0x000c1000 0x001c1000 0x001000>, /* ap 94 */
	<0x000c2000 0x001c2000 0x001000>; /* ap 95 */

	target-module@8c000 { /* 0x4818c000, ap 34 0c.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x8c000 0x1000>;
	};

	target-module@8e000 { /* 0x4818e000, ap 36 02.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x8e000 0x1000>;
	};

	target-module@9c000 { /* 0x4819c000, ap 38 52.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x9c000 0x8>,
	<0x9c010 0x8>,
	<0x9c090 0x8>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_I2C3_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x9c000 0x1000>;

	i2c2: i2c@0 {
	compatible = "ti,am4372-i2c","ti,omap4-i2c";
	reg = <0x0 0x1000>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};
	};

	target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xa0000 0x4>,
	<0xa0110 0x4>,
	<0xa0114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_SPI1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa0000 0x1000>;

	spi1: spi@0 {
	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};
	};

	target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xa2000 0x4>,
	<0xa2110 0x4>,
	<0xa2114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_SPI2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa2000 0x1000>;

	spi2: spi@0 {
	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};
	};

	target-module@a4000 { /* 0x481a4000, ap 92 62.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xa4000 0x4>,
	<0xa4110 0x4>,
	<0xa4114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_SPI3_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa4000 0x1000>;

	spi3: spi@0 {
	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};
	};

	target-module@a6000 { /* 0x481a6000, ap 40 16.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xa6050 0x4>,
	<0xa6054 0x4>,
	<0xa6058 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_UART4_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa6000 0x1000>;

	uart3: serial@0 {
	compatible = "ti,am4372-uart","ti,omap2-uart";
	reg = <0x0 0x2000>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	target-module@a8000 { /* 0x481a8000, ap 42 20.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xa8050 0x4>,
	<0xa8054 0x4>,
	<0xa8058 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_UART5_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa8000 0x1000>;

	uart4: serial@0 {
	compatible = "ti,am4372-uart","ti,omap2-uart";
	reg = <0x0 0x2000>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	target-module@aa000 { /* 0x481aa000, ap 44 12.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xaa050 0x4>,
	<0xaa054 0x4>,
	<0xaa058 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_UART6_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xaa000 0x1000>;

	uart5: serial@0 {
	compatible = "ti,am4372-uart","ti,omap2-uart";
	reg = <0x0 0x2000>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	target-module@ac000 { /* 0x481ac000, ap 46 30.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xac000 0x4>,
	<0xac010 0x4>,
	<0xac114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 0>,
	<&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 8>;
	clock-names = "fck", "dbclk";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xac000 0x1000>;

	gpio2: gpio@0 {
	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	reg = <0x0 0x1000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	status = "disabled";
	};
	};

	target-module@ae000 { /* 0x481ae000, ap 48 32.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xae000 0x4>,
	<0xae010 0x4>,
	<0xae114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 0>,
	<&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 8>;
	clock-names = "fck", "dbclk";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xae000 0x1000>;

	gpio3: gpio@0 {
	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	reg = <0x0 0x1000>;
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	status = "disabled";
	};
	};

	target-module@c1000 { /* 0x481c1000, ap 94 68.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0xc1000 0x4>,
	<0xc1010 0x4>,
	<0xc1014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_TIMER8_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xc1000 0x1000>;

	timer8: timer@0 {
	compatible = "ti,am4372-timer","ti,am335x-timer";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	target-module@cc000 { /* 0x481cc000, ap 50 46.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xcc020 0x4>;
	reg-names = "rev";
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xcc000 0x2000>;

	dcan0: can@0 {
	compatible = "ti,am4372-d_can", "ti,am3352-d_can";
	reg = <0x0 0x2000>;
	syscon-raminit = <&scm_conf 0x644 0>;
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xd0020 0x4>;
	reg-names = "rev";
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xd0000 0x2000>;

	dcan1: can@0 {
	compatible = "ti,am4372-d_can", "ti,am3352-d_can";
	reg = <0x0 0x2000>;
	syscon-raminit = <&scm_conf 0x644 1>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	target-module@d8000 { /* 0x481d8000, ap 54 5e.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xd82fc 0x4>,
	<0xd8110 0x4>,
	<0xd8114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_MMC2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xd8000 0x1000>;

	mmc2: mmc@0 {
	compatible = "ti,omap4-hsmmc";
	reg = <0x0 0x1000>;
	ti,needs-special-reset;
	dmas = <&edma 2 0>,
	<&edma 3 0>;
	dma-names = "tx", "rx";
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};
	};

	segment@200000 { /* 0x48200000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	};

	segment@300000 { /* 0x48300000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00300000 0x001000>, /* ap 56 */
	<0x00001000 0x00301000 0x001000>, /* ap 57 */
	<0x00002000 0x00302000 0x001000>, /* ap 58 */
	<0x00003000 0x00303000 0x001000>, /* ap 59 */
	<0x00004000 0x00304000 0x001000>, /* ap 60 */
	<0x00005000 0x00305000 0x001000>, /* ap 61 */
	<0x00018000 0x00318000 0x004000>, /* ap 62 */
	<0x0001c000 0x0031c000 0x001000>, /* ap 63 */
	<0x00010000 0x00310000 0x002000>, /* ap 64 */
	<0x00028000 0x00328000 0x001000>, /* ap 75 */
	<0x00029000 0x00329000 0x001000>, /* ap 76 */
	<0x00012000 0x00312000 0x001000>, /* ap 79 */
	<0x00020000 0x00320000 0x001000>, /* ap 82 */
	<0x00021000 0x00321000 0x001000>, /* ap 83 */
	<0x00026000 0x00326000 0x001000>, /* ap 86 */
	<0x00027000 0x00327000 0x001000>, /* ap 87 */
	<0x0002a000 0x0032a000 0x000400>, /* ap 88 */
	<0x0002c000 0x0032c000 0x001000>, /* ap 89 */
	<0x00013000 0x00313000 0x001000>, /* ap 90 */
	<0x00014000 0x00314000 0x001000>, /* ap 91 */
	<0x00006000 0x00306000 0x001000>, /* ap 96 */
	<0x00007000 0x00307000 0x001000>, /* ap 97 */
	<0x00008000 0x00308000 0x001000>, /* ap 98 */
	<0x00009000 0x00309000 0x001000>, /* ap 99 */
	<0x0000a000 0x0030a000 0x001000>, /* ap 100 */
	<0x0000b000 0x0030b000 0x001000>, /* ap 101 */
	<0x0003d000 0x0033d000 0x001000>, /* ap 102 */
	<0x0003e000 0x0033e000 0x001000>, /* ap 103 */
	<0x0003f000 0x0033f000 0x001000>, /* ap 104 */
	<0x00040000 0x00340000 0x001000>, /* ap 105 */
	<0x00041000 0x00341000 0x001000>, /* ap 106 */
	<0x00042000 0x00342000 0x001000>, /* ap 107 */
	<0x00045000 0x00345000 0x001000>, /* ap 108 */
	<0x00046000 0x00346000 0x001000>, /* ap 109 */
	<0x00047000 0x00347000 0x001000>, /* ap 110 */
	<0x00048000 0x00348000 0x001000>, /* ap 111 */
	<0x000f2000 0x003f2000 0x002000>, /* ap 112 */
	<0x000f4000 0x003f4000 0x001000>, /* ap 113 */
	<0x0004c000 0x0034c000 0x002000>, /* ap 114 */
	<0x0004e000 0x0034e000 0x001000>, /* ap 115 */
	<0x00022000 0x00322000 0x001000>, /* ap 116 */
	<0x00023000 0x00323000 0x001000>, /* ap 117 */
	<0x000f0000 0x003f0000 0x001000>, /* ap 118 */
	<0x0002a400 0x0032a400 0x000400>, /* ap 119 */
	<0x0002a800 0x0032a800 0x000400>, /* ap 120 */
	<0x0002ac00 0x0032ac00 0x000400>, /* ap 121 */
	<0x0002b000 0x0032b000 0x001000>, /* ap 122 */
	<0x00080000 0x00380000 0x020000>, /* ap 123 */
	<0x000a0000 0x003a0000 0x001000>, /* ap 124 */
	<0x000a8000 0x003a8000 0x008000>, /* ap 125 */
	<0x000b0000 0x003b0000 0x001000>, /* ap 126 */
	<0x000c0000 0x003c0000 0x020000>, /* ap 127 */
	<0x000e0000 0x003e0000 0x001000>, /* ap 128 */
	<0x000e8000 0x003e8000 0x008000>; /* ap 129 */

	target-module@0 { /* 0x48300000, ap 56 40.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x0 0x4>,
	<0x4 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS0_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x1000>;

	epwmss0: epwmss@0 {
	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	reg = <0x0 0x10>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x1000>;
	status = "disabled";

	ecap0: ecap@100 {
	compatible = "ti,am4372-ecap",
	"ti,am3352-ecap",
	"ti,am33xx-ecap";
	#pwm-cells = <3>;
	reg = <0x100 0x80>;
	clocks = <&l4ls_gclk>;
	clock-names = "fck";
	status = "disabled";
	};

	ehrpwm0: pwm@200 {
	compatible = "ti,am4372-ehrpwm",
	"ti,am3352-ehrpwm",
	"ti,am33xx-ehrpwm";
	#pwm-cells = <3>;
	reg = <0x200 0x80>;
	clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
	clock-names = "tbclk", "fck";
	status = "disabled";
	};
	};
	};

	target-module@2000 { /* 0x48302000, ap 58 4a.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x2000 0x4>,
	<0x2004 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x2000 0x1000>;

	epwmss1: epwmss@0 {
	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	reg = <0x0 0x10>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x1000>;
	status = "disabled";

	ecap1: ecap@100 {
	compatible = "ti,am4372-ecap",
	"ti,am3352-ecap",
	"ti,am33xx-ecap";
	#pwm-cells = <3>;
	reg = <0x100 0x80>;
	clocks = <&l4ls_gclk>;
	clock-names = "fck";
	status = "disabled";
	};

	ehrpwm1: pwm@200 {
	compatible = "ti,am4372-ehrpwm",
	"ti,am3352-ehrpwm",
	"ti,am33xx-ehrpwm";
	#pwm-cells = <3>;
	reg = <0x200 0x80>;
	clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
	clock-names = "tbclk", "fck";
	status = "disabled";
	};
	};
	};

	target-module@4000 { /* 0x48304000, ap 60 44.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x4000 0x4>,
	<0x4004 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4000 0x1000>;

	epwmss2: epwmss@0 {
	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	reg = <0x0 0x10>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x1000>;
	status = "disabled";

	ecap2: ecap@100 {
	compatible = "ti,am4372-ecap",
	"ti,am3352-ecap",
	"ti,am33xx-ecap";
	#pwm-cells = <3>;
	reg = <0x100 0x80>;
	clocks = <&l4ls_gclk>;
	clock-names = "fck";
	status = "disabled";
	};

	ehrpwm2: pwm@200 {
	compatible = "ti,am4372-ehrpwm",
	"ti,am3352-ehrpwm",
	"ti,am33xx-ehrpwm";
	#pwm-cells = <3>;
	reg = <0x200 0x80>;
	clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
	clock-names = "tbclk", "fck";
	status = "disabled";
	};
	};
	};

	target-module@6000 { /* 0x48306000, ap 96 58.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x6000 0x4>,
	<0x6004 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS3_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x6000 0x1000>;

	epwmss3: epwmss@0 {
	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	reg = <0x0 0x10>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x1000>;
	status = "disabled";

	ehrpwm3: pwm@200 {
	compatible = "ti,am4372-ehrpwm",
	"ti,am3352-ehrpwm",
	"ti,am33xx-ehrpwm";
	#pwm-cells = <3>;
	reg = <0x200 0x80>;
	clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>;
	clock-names = "tbclk", "fck";
	status = "disabled";
	};
	};
	};

	target-module@8000 { /* 0x48308000, ap 98 54.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x8000 0x4>,
	<0x8004 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS4_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x8000 0x1000>;

	epwmss4: epwmss@0 {
	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	reg = <0x0 0x10>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x1000>;
	status = "disabled";

	ehrpwm4: pwm@48308200 {
	compatible = "ti,am4372-ehrpwm",
	"ti,am3352-ehrpwm",
	"ti,am33xx-ehrpwm";
	#pwm-cells = <3>;
	reg = <0x200 0x80>;
	clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>;
	clock-names = "tbclk", "fck";
	status = "disabled";
	};
	};
	};

	target-module@a000 { /* 0x4830a000, ap 100 60.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xa000 0x4>,
	<0xa004 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS5_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa000 0x1000>;

	epwmss5: epwmss@0 {
	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	reg = <0x0 0x10>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x1000>;
	status = "disabled";

	ehrpwm5: pwm@200 {
	compatible = "ti,am4372-ehrpwm",
	"ti,am3352-ehrpwm",
	"ti,am33xx-ehrpwm";
	#pwm-cells = <3>;
	reg = <0x200 0x80>;
	clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>;
	clock-names = "tbclk", "fck";
	status = "disabled";
	};
	};
	};

	target-module@10000 { /* 0x48310000, ap 64 4e.1 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x11fe0 0x4>,
	<0x11fe4 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_RNG_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x10000 0x2000>;

	rng: rng@0 {
	compatible = "ti,omap4-rng";
	reg = <0x0 0x2000>;
	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	target-module@13000 { /* 0x48313000, ap 90 50.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x13000 0x1000>;
	};

	target-module@18000 { /* 0x48318000, ap 62 4c.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x18000 0x4000>;
	};

	target-module@20000 { /* 0x48320000, ap 82 34.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x20000 0x4>,
	<0x20010 0x4>,
	<0x20114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 0>,
	<&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 8>;
	clock-names = "fck", "dbclk";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x20000 0x1000>;

	gpio4: gpio@0 {
	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	reg = <0x0 0x1000>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	status = "disabled";
	};
	};

	target-module@22000 { /* 0x48322000, ap 116 64.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x22000 0x4>,
	<0x22010 0x4>,
	<0x22114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 0>,
	<&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 8>;
	clock-names = "fck", "dbclk";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x22000 0x1000>;

	gpio5: gpio@0 {
	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	reg = <0x0 0x1000>;
	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	status = "disabled";
	};
	};

	target-module@26000 { /* 0x48326000, ap 86 66.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x26000 0x4>,
	<0x26104 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	/* Domains (P, C): per_pwrdm, l3s_clkdm */
	clocks = <&l3s_clkctrl AM4_L3S_VPFE0_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x26000 0x1000>;

	vpfe0: vpfe@0 {
	compatible = "ti,am437x-vpfe";
	reg = <0x0 0x2000>;
	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	target-module@28000 { /* 0x48328000, ap 75 0e.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x28000 0x4>,
	<0x28104 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	/* Domains (P, C): per_pwrdm, l3s_clkdm */
	clocks = <&l3s_clkctrl AM4_L3S_VPFE1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x28000 0x1000>;

	vpfe1: vpfe@0 {
	compatible = "ti,am437x-vpfe";
	reg = <0x0 0x2000>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	- ti,hwmods = "dss_core";
	reg = <0x2a000 0x4>,
	<0x2a010 0x4>,
	<0x2a014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, dss_clkdm */
	clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x0002a000 0x00000400>,
	<0x00000400 0x0002a400 0x00000400>,
	<0x00000800 0x0002a800 0x00000400>,
	<0x00000c00 0x0002ac00 0x00000400>,
	<0x00001000 0x0002b000 0x00001000>;
	+
	+ dss: dss@0 {
	+ compatible = "ti,omap3-dss";
	+ reg = <0 0x200>;
	+ status = "disabled";
	+ clocks = <&disp_clk>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x00000000 0x00000000 0x00000400>,
	+ <0x00000400 0x00000400 0x00000400>,
	+ <0x00000800 0x00000800 0x00000400>,
	+ <0x00000c00 0x00000c00 0x00000400>,
	+ <0x00001000 0x00001000 0x00001000>;
	+
	+ target-module@400 {
	+ compatible = "ti,sysc-omap2", "ti,sysc";
	+ reg = <0x400 0x4>,
	+ <0x410 0x4>,
	+ <0x414 0x4>;
	+ reg-names = "rev", "sysc", "syss";
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	+ SYSC_OMAP2_ENAWAKEUP \|
	+ SYSC_OMAP2_SOFTRESET \|
	+ SYSC_OMAP2_AUTOIDLE)>;
	+ ti,syss-mask = <1>;
	+ clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x400 0x400>;
	+
	+ dispc: dispc@0 {
	+ compatible = "ti,omap3-dispc";
	+ reg = <0 0x400>;
	+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&disp_clk>;
	+ clock-names = "fck";
	+
	+ max-memory-bandwidth = <230000000>;
	+ };
	+ };
	+
	+ target-module@800 {
	+ compatible = "ti,sysc-omap2", "ti,sysc";
	+ reg = <0x800 0x4>,
	+ <0x810 0x4>,
	+ <0x814 0x4>;
	+ reg-names = "rev", "sysc", "syss";
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	+ SYSC_OMAP2_AUTOIDLE)>;
	+ ti,syss-mask = <1>;
	+ clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x800 0x400>;
	+
	+ rfbi: rfbi@0 {
	+ compatible = "ti,omap3-rfbi";
	+ reg = <0 0x100>;
	+ clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
	+ clock-names = "fck";
	+ status = "disabled";
	+ };
	+ };
	+ };
	};

	target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x3d000 0x4>,
	<0x3d010 0x4>,
	<0x3d014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_TIMER9_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x3d000 0x1000>;

	timer9: timer@0 {
	compatible = "ti,am4372-timer","ti,am335x-timer";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x3f000 0x4>,
	<0x3f010 0x4>,
	<0x3f014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_TIMER10_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x3f000 0x1000>;

	timer10: timer@0 {
	compatible = "ti,am4372-timer","ti,am335x-timer";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	target-module@41000 { /* 0x48341000, ap 106 76.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x41000 0x4>,
	<0x41010 0x4>,
	<0x41014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_TIMER11_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x41000 0x1000>;

	timer11: timer@0 {
	compatible = "ti,am4372-timer","ti,am335x-timer";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	target-module@45000 { /* 0x48345000, ap 108 6a.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x45000 0x4>,
	<0x45110 0x4>,
	<0x45114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_SPI4_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x45000 0x1000>;

	spi4: spi@0 {
	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};
	};

	target-module@47000 { /* 0x48347000, ap 110 70.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x47000 0x4>,
	<0x47014 0x4>,
	<0x47018 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_HDQ1W_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x47000 0x1000>;

	hdq: hdq@0 {
	compatible = "ti,am4372-hdq";
	reg = <0x0 0x1000>;
	interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&func_12m_clk>;
	clock-names = "fck";
	status = "disabled";
	};
	};

	target-module@4c000 { /* 0x4834c000, ap 114 72.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4c000 0x2000>;
	};

	target-module@80000 { /* 0x48380000, ap 123 42.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	ti,hwmods = "usb_otg_ss0";
	reg = <0x80000 0x4>,
	<0x80010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l3s_clkdm */
	clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x80000 0x20000>;

	dwc3_1: omap_dwc3@0 {
	compatible = "ti,am437x-dwc3";
	reg = <0x0 0x10000>;
	interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <1>;
	utmi-mode = <1>;
	ranges = <0 0 0x20000>;

	usb1: usb@10000 {
	compatible = "synopsys,dwc3";
	reg = <0x10000 0x10000>;
	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "peripheral",
	"host",
	"otg";
	phys = <&usb2_phy1>;
	phy-names = "usb2-phy";
	maximum-speed = "high-speed";
	dr_mode = "otg";
	status = "disabled";
	snps,dis_u3_susphy_quirk;
	snps,dis_u2_susphy_quirk;
	};
	};
	};

	target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xa8000 0x4>;
	reg-names = "rev";
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP0_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa8000 0x8000>;

	ocp2scp0: ocp2scp@0 {
	compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x8000>;

	usb2_phy1: phy@8000 {
	compatible = "ti,am437x-usb2";
	reg = <0x0 0x8000>;
	syscon-phy-power = <&scm_conf 0x620>;
	clocks = <&usb_phy0_always_on_clk32k>,
	<&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 8>;
	clock-names = "wkupclk", "refclk";
	#phy-cells = <0>;
	status = "disabled";
	};
	};
	};

	target-module@c0000 { /* 0x483c0000, ap 127 7a.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	ti,hwmods = "usb_otg_ss1";
	reg = <0xc0000 0x4>,
	<0xc0010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (P, C): per_pwrdm, l3s_clkdm */
	clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xc0000 0x20000>;

	dwc3_2: omap_dwc3@0 {
	compatible = "ti,am437x-dwc3";
	reg = <0x0 0x10000>;
	interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <1>;
	utmi-mode = <1>;
	ranges = <0 0 0x20000>;

	usb2: usb@10000 {
	compatible = "synopsys,dwc3";
	reg = <0x10000 0x10000>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "peripheral",
	"host",
	"otg";
	phys = <&usb2_phy2>;
	phy-names = "usb2-phy";
	maximum-speed = "high-speed";
	dr_mode = "otg";
	status = "disabled";
	snps,dis_u3_susphy_quirk;
	snps,dis_u2_susphy_quirk;
	};
	};
	};

	target-module@e8000 { /* 0x483e8000, ap 129 78.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xe8000 0x4>;
	reg-names = "rev";
	/* Domains (P, C): per_pwrdm, l4ls_clkdm */
	clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xe8000 0x8000>;

	ocp2scp1: ocp2scp@0 {
	compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x8000>;

	usb2_phy2: phy@8000 {
	compatible = "ti,am437x-usb2";
	reg = <0x0 0x8000>;
	syscon-phy-power = <&scm_conf 0x628>;
	clocks = <&usb_phy1_always_on_clk32k>,
	<&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 8>;
	clock-names = "wkupclk", "refclk";
	#phy-cells = <0>;
	status = "disabled";
	};
	};
	};

	target-module@f2000 { /* 0x483f2000, ap 112 5a.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf2000 0x2000>;
	};
	};
	};

	diff --git a/sys/gnu/dts/arm/am437x-sk-evm.dts b/sys/gnu/dts/arm/am437x-sk-evm.dts
	index 25222497f828..4d5a7ca2e25d 100644
	--- a/sys/gnu/dts/arm/am437x-sk-evm.dts
	+++ b/sys/gnu/dts/arm/am437x-sk-evm.dts
	@@ -1,912 +1,912 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
	*/

	/* AM437x SK EVM */

	/dts-v1/;

	#include "am4372.dtsi"
	#include <dt-bindings/pinctrl/am43xx.h>
	#include <dt-bindings/pwm/pwm.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/irq.h>

	/ {
	model = "TI AM437x SK EVM";
	compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43";

	aliases {
	display0 = &lcd0;
	};

	chosen {
	stdout-path = &uart0;
	};

	/* fixed 32k external oscillator clock */
	clk_32k_rtc: clk_32k_rtc {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	};

	lcd_bl: backlight {
	compatible = "pwm-backlight";
	pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
	brightness-levels = <0 51 53 56 62 75 101 152 255>;
	default-brightness-level = <8>;
	};

	sound {
	compatible = "simple-audio-card";
	simple-audio-card,name = "AM437x-SK-EVM";
	simple-audio-card,widgets =
	"Headphone", "Headphone Jack",
	"Line", "Line In";
	simple-audio-card,routing =
	"Headphone Jack", "HPLOUT",
	"Headphone Jack", "HPROUT",
	"LINE1L", "Line In",
	"LINE1R", "Line In";
	simple-audio-card,format = "dsp_b";
	simple-audio-card,bitclock-master = <&sound_master>;
	simple-audio-card,frame-master = <&sound_master>;
	simple-audio-card,bitclock-inversion;

	simple-audio-card,cpu {
	sound-dai = <&mcasp1>;
	};

	sound_master: simple-audio-card,codec {
	sound-dai = <&tlv320aic3106>;
	system-clock-frequency = <24000000>;
	};
	};

	matrix_keypad: matrix_keypad0 {
	compatible = "gpio-matrix-keypad";

	pinctrl-names = "default";
	pinctrl-0 = <&matrix_keypad_pins>;

	debounce-delay-ms = <5>;
	col-scan-delay-us = <5>;

	row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */
	&gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */

	col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */
	&gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */

	linux,keymap = <
	MATRIX_KEY(0, 0, KEY_DOWN)
	MATRIX_KEY(0, 1, KEY_RIGHT)
	MATRIX_KEY(1, 0, KEY_LEFT)
	MATRIX_KEY(1, 1, KEY_UP)
	>;
	};

	leds {
	compatible = "gpio-leds";

	pinctrl-names = "default";
	pinctrl-0 = <&leds_pins>;

	led0 {
	label = "am437x-sk:red:heartbeat";
	gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */
	linux,default-trigger = "heartbeat";
	default-state = "off";
	};

	led1 {
	label = "am437x-sk:green:mmc1";
	gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */
	linux,default-trigger = "mmc0";
	default-state = "off";
	};

	led2 {
	label = "am437x-sk:blue:cpu0";
	gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */
	linux,default-trigger = "cpu0";
	default-state = "off";
	};

	led3 {
	label = "am437x-sk:blue:usr3";
	gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */
	default-state = "off";
	};
	};

	lcd0: display {
	compatible = "newhaven,nhd-4.3-480272ef-atxl", "panel-dpi";
	label = "lcd";

	pinctrl-names = "default";
	pinctrl-0 = <&lcd_pins>;

	backlight = <&lcd_bl>;

	enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;

	panel-timing {
	clock-frequency = <9000000>;
	hactive = <480>;
	vactive = <272>;
	hfront-porch = <2>;
	hback-porch = <2>;
	hsync-len = <41>;
	vfront-porch = <2>;
	vback-porch = <2>;
	vsync-len = <10>;
	hsync-active = <0>;
	vsync-active = <0>;
	de-active = <1>;
	pixelclk-active = <1>;
	};

	port {
	lcd_in: endpoint {
	remote-endpoint = <&dpi_out>;
	};
	};
	};

	vmmcwl_fixed: fixedregulator-mmcwl {
	/*
	* WL_EN is not SDIO standard compliant. It is an out of band
	* signal and hard to be dealt with in a standard way by the
	* SDIO core driver.
	* So modelling the WL_EN line as a regulator was a natural
	* choice as the MMC core already deals with MMC supplies.
	*/
	compatible = "regulator-fixed";
	regulator-name = "vmmcwl_fixed";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};
	};

	&am43xx_pinmux {
	matrix_keypad_pins: matrix_keypad_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0xa4c, PIN_OUTPUT \| MUX_MODE7) /* gpio5_13.gpio5_13 */
	AM4372_IOPAD(0xa50, PIN_OUTPUT \| MUX_MODE7) /* spi4_sclk.gpio5_4 */
	AM4372_IOPAD(0xa54, PIN_INPUT \| MUX_MODE7) /* spi4_d0.gpio5_5 */
	AM4372_IOPAD(0xa58, PIN_INPUT \| MUX_MODE7) /* spi4_d1.gpio5_5 */
	>;
	};

	leds_pins: leds_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0xa28, PIN_OUTPUT \| MUX_MODE7) /* uart3_rxd.gpio5_2 */
	AM4372_IOPAD(0xa2c, PIN_OUTPUT \| MUX_MODE7) /* uart3_txd.gpio5_3 */
	AM4372_IOPAD(0xa30, PIN_OUTPUT \| MUX_MODE7) /* uart3_ctsn.gpio5_0 */
	AM4372_IOPAD(0xa34, PIN_OUTPUT \| MUX_MODE7) /* uart3_rtsn.gpio5_1 */
	>;
	};

	i2c0_pins: i2c0_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x988, PIN_INPUT \| SLEWCTRL_FAST \| MUX_MODE0) /* i2c0_sda.i2c0_sda */
	AM4372_IOPAD(0x98c, PIN_INPUT \| SLEWCTRL_FAST \| MUX_MODE0) /* i2c0_scl.i2c0_scl */
	>;
	};

	i2c1_pins: i2c1_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x95c, PIN_INPUT \| SLEWCTRL_FAST \| MUX_MODE2) /* spi0_cs0.i2c1_scl */
	AM4372_IOPAD(0x958, PIN_INPUT \| SLEWCTRL_FAST \| MUX_MODE2) /* spi0_d1.i2c1_sda */
	>;
	};

	mmc1_pins: pinmux_mmc1_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x8f0, PIN_INPUT \| MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
	AM4372_IOPAD(0x8f4, PIN_INPUT \| MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
	AM4372_IOPAD(0x8f8, PIN_INPUT \| MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
	AM4372_IOPAD(0x8fc, PIN_INPUT \| MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
	AM4372_IOPAD(0x900, PIN_INPUT \| MUX_MODE0) /* mmc0_clk.mmc0_clk */
	AM4372_IOPAD(0x904, PIN_INPUT \| MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
	AM4372_IOPAD(0x960, PIN_INPUT \| MUX_MODE7) /* spi0_cs1.gpio0_6 */
	>;
	};

	ecap0_pins: backlight_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x964, PIN_OUTPUT \| MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
	>;
	};

	edt_ft5306_ts_pins: edt_ft5306_ts_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x874, PIN_INPUT \| MUX_MODE7) /* gpmc_wpn.gpio0_31 */
	AM4372_IOPAD(0x878, PIN_OUTPUT \| MUX_MODE7) /* gpmc_be1n.gpio1_28 */
	>;
	};

	vpfe0_pins_default: vpfe0_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_hd mode 0*/
	AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_vd mode 0*/
	AM4372_IOPAD(0x9b8, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_field mode 0*/
	AM4372_IOPAD(0x9bc, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_wen mode 0*/
	AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_pclk mode 0*/
	AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data8 mode 0*/
	AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data9 mode 0*/
	AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data0 mode 0*/
	AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data1 mode 0*/
	AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data2 mode 0*/
	AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data3 mode 0*/
	AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data4 mode 0*/
	AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data5 mode 0*/
	AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data6 mode 0*/
	AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP \| MUX_MODE0) /* cam0_data7 mode 0*/
	>;
	};

	vpfe0_pins_sleep: vpfe0_pins_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7)
	AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7)
	AM4372_IOPAD(0x9b8, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7)
	AM4372_IOPAD(0x9bc, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7)
	AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7)
	AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7)
	AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7)
	AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7)
	AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7)
	AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7)
	AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7)
	AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7)
	AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7)
	AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7)
	AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN \| INPUT_EN \| MUX_MODE7)
	>;
	};

	clkout1_pin: pinmux_clkout1_pin {
	pinctrl-single,pins = <
	0x270 (PIN_OUTPUT_PULLDOWN \| MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */
	>;
	};

	cpsw_default: cpsw_default {
	pinctrl-single,pins = <
	/* Slave 1 */
	AM4372_IOPAD(0x92c, PIN_OUTPUT \| MUX_MODE2) /* mii1_txclk.rmii1_tclk */
	AM4372_IOPAD(0x914, PIN_OUTPUT \| MUX_MODE2) /* mii1_txen.rgmii1_tctl */
	AM4372_IOPAD(0x928, PIN_OUTPUT \| MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
	AM4372_IOPAD(0x924, PIN_OUTPUT \| MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
	AM4372_IOPAD(0x920, PIN_OUTPUT \| MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
	AM4372_IOPAD(0x91c, PIN_OUTPUT \| MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
	AM4372_IOPAD(0x930, PIN_INPUT \| MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
	AM4372_IOPAD(0x918, PIN_INPUT \| MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
	AM4372_IOPAD(0x940, PIN_INPUT \| MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
	AM4372_IOPAD(0x93c, PIN_INPUT \| MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
	AM4372_IOPAD(0x938, PIN_INPUT \| MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
	AM4372_IOPAD(0x934, PIN_INPUT \| MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */

	/* Slave 2 */
	AM4372_IOPAD(0x858, PIN_OUTPUT \| MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
	AM4372_IOPAD(0x840, PIN_OUTPUT \| MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
	AM4372_IOPAD(0x854, PIN_OUTPUT \| MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
	AM4372_IOPAD(0x850, PIN_OUTPUT \| MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
	AM4372_IOPAD(0x84c, PIN_OUTPUT \| MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
	AM4372_IOPAD(0x848, PIN_OUTPUT \| MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
	AM4372_IOPAD(0x85c, PIN_INPUT \| MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
	AM4372_IOPAD(0x844, PIN_INPUT \| MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */
	AM4372_IOPAD(0x86c, PIN_INPUT \| MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
	AM4372_IOPAD(0x868, PIN_INPUT \| MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
	AM4372_IOPAD(0x864, PIN_INPUT \| MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
	AM4372_IOPAD(0x860, PIN_INPUT \| MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
	>;
	};

	cpsw_sleep: cpsw_sleep {
	pinctrl-single,pins = <
	/* Slave 1 reset value */
	AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN \| MUX_MODE7)

	/* Slave 2 reset value */
	AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x840, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x850, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	>;
	};

	davinci_mdio_default: davinci_mdio_default {
	pinctrl-single,pins = <
	/* MDIO */
	AM4372_IOPAD(0x948, PIN_INPUT \| SLEWCTRL_FAST \| MUX_MODE0) /* mdio_data.mdio_data */
	AM4372_IOPAD(0x94c, PIN_OUTPUT \| MUX_MODE0) /* mdio_clk.mdio_clk */
	>;
	};

	davinci_mdio_sleep: davinci_mdio_sleep {
	pinctrl-single,pins = <
	/* MDIO reset value */
	AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	>;
	};

	dss_pins: dss_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x820, PIN_OUTPUT \| MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */
	AM4372_IOPAD(0x824, PIN_OUTPUT \| MUX_MODE1)
	AM4372_IOPAD(0x828, PIN_OUTPUT \| MUX_MODE1)
	AM4372_IOPAD(0x82c, PIN_OUTPUT \| MUX_MODE1)
	AM4372_IOPAD(0x830, PIN_OUTPUT \| MUX_MODE1)
	AM4372_IOPAD(0x834, PIN_OUTPUT \| MUX_MODE1)
	AM4372_IOPAD(0x838, PIN_OUTPUT \| MUX_MODE1)
	AM4372_IOPAD(0x83c, PIN_OUTPUT \| MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */
	AM4372_IOPAD(0x8a0, PIN_OUTPUT \| MUX_MODE0) /* DSS DATA 0 */
	AM4372_IOPAD(0x8a4, PIN_OUTPUT \| MUX_MODE0)
	AM4372_IOPAD(0x8a8, PIN_OUTPUT \| MUX_MODE0)
	AM4372_IOPAD(0x8ac, PIN_OUTPUT \| MUX_MODE0)
	AM4372_IOPAD(0x8b0, PIN_OUTPUT \| MUX_MODE0)
	AM4372_IOPAD(0x8b4, PIN_OUTPUT \| MUX_MODE0)
	AM4372_IOPAD(0x8b8, PIN_OUTPUT \| MUX_MODE0)
	AM4372_IOPAD(0x8bc, PIN_OUTPUT \| MUX_MODE0)
	AM4372_IOPAD(0x8c0, PIN_OUTPUT \| MUX_MODE0)
	AM4372_IOPAD(0x8c4, PIN_OUTPUT \| MUX_MODE0)
	AM4372_IOPAD(0x8c8, PIN_OUTPUT \| MUX_MODE0)
	AM4372_IOPAD(0x8cc, PIN_OUTPUT \| MUX_MODE0)
	AM4372_IOPAD(0x8d0, PIN_OUTPUT \| MUX_MODE0)
	AM4372_IOPAD(0x8d4, PIN_OUTPUT \| MUX_MODE0)
	AM4372_IOPAD(0x8d8, PIN_OUTPUT \| MUX_MODE0)
	AM4372_IOPAD(0x8dc, PIN_OUTPUT \| MUX_MODE0) /* DSS DATA 15 */
	AM4372_IOPAD(0x8e0, PIN_OUTPUT \| MUX_MODE0) /* DSS VSYNC */
	AM4372_IOPAD(0x8e4, PIN_OUTPUT \| MUX_MODE0) /* DSS HSYNC */
	AM4372_IOPAD(0x8e8, PIN_OUTPUT \| MUX_MODE0) /* DSS PCLK */
	AM4372_IOPAD(0x8ec, PIN_OUTPUT \| MUX_MODE0) /* DSS AC BIAS EN */

	>;
	};

	qspi_pins: qspi_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x87c, PIN_OUTPUT \| MUX_MODE3) /* gpmc_csn0.qspi_csn */
	AM4372_IOPAD(0x888, PIN_OUTPUT \| MUX_MODE2) /* gpmc_csn3.qspi_clk */
	AM4372_IOPAD(0x890, PIN_INPUT \| MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
	AM4372_IOPAD(0x894, PIN_INPUT \| MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
	AM4372_IOPAD(0x898, PIN_INPUT \| MUX_MODE3) /* gpmc_wen.qspi_d2 */
	AM4372_IOPAD(0x89c, PIN_INPUT \| MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
	>;
	};

	mcasp1_pins: mcasp1_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN \| MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
	AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN \| MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
	AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN \| MUX_MODE4) /* mii1_col.mcasp1_axr2 */
	AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN \| MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
	>;
	};

	mcasp1_pins_sleep: mcasp1_pins_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN \| MUX_MODE7)
	>;
	};

	lcd_pins: lcd_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN \| MUX_MODE7) /* gpcm_ad7.gpio1_7 */
	>;
	};

	usb1_pins: usb1_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0xac0, PIN_OUTPUT \| MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
	>;
	};

	usb2_pins: usb2_pins {
	pinctrl-single,pins = <
	AM4372_IOPAD(0xac4, PIN_OUTPUT \| MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
	>;
	};

	mmc3_pins_default: pinmux_mmc3_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP \| MUX_MODE3) /* (AD21) cam1_data2.mmc2_clk */
	AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP \| MUX_MODE3) /* (AE22) cam1_data3.mmc2_cmd */
	AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP \| MUX_MODE3) /* (AD22) cam1_data4.mmc2_dat0 */
	AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP \| MUX_MODE3) /* (AE23) cam1_data5.mmc2_dat1 */
	AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP \| MUX_MODE3) /* (AD23) cam1_data6.mmc2_dat2 */
	AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP \| MUX_MODE3) /* (AE24) cam1_data7.mmc2_dat3 */
	>;
	};

	mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* (AD21) cam1_data2.mmc2_clk */
	AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* (AE22) cam1_data3.mmc2_cmd */
	AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* (AD22) cam1_data4.mmc2_dat0 */
	AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* (AE23) cam1_data5.mmc2_dat1 */
	AM4372_IOPAD(0xa00, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* (AD23) cam1_data6.mmc2_dat2 */
	AM4372_IOPAD(0xa04, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* (AE24) cam1_data7.mmc2_dat3 */
	>;
	};

	wlan_pins_default: pinmux_wlan_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN \| MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */
	AM4372_IOPAD(0x9e4, PIN_INPUT \| WAKEUP_ENABLE \| MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */
	>;
	};

	wlan_pins_sleep: pinmux_wlan_pins_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN \| MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */
	AM4372_IOPAD(0x9e4, PIN_INPUT \| WAKEUP_ENABLE \| MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */
	>;
	};

	uart1_bt_pins_default: pinmux_uart1_bt_pins_default {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x980, PIN_INPUT \| MUX_MODE0) /* uart1_rxd.uart1_rxd */
	AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* uart1_txd.uart1_txd */
	AM4372_IOPAD(0x978, PIN_INPUT_PULLUP \| MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
	AM4372_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
	AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLDOWN \| MUX_MODE7) /* cam1_data9.gpio4_7 BT_EN */
	>;
	};

	uart1_bt_pins_sleep: pinmux_uart1_bt_pins_sleep {
	pinctrl-single,pins = <
	AM4372_IOPAD(0x980, PIN_OUTPUT_PULLDOWN \| MUX_MODE7) /* uart1_rxd.uart1_rxd */
	AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN \| MUX_MODE7) /* uart1_txd.uart1_txd */
	AM4372_IOPAD(0x978, PIN_OUTPUT_PULLDOWN \| MUX_MODE7) /* uart1_ctsn.uart1_ctsn */
	AM4372_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN \| MUX_MODE7) /* uart1_rtsn.uart1_rtsn */
	AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLUP \| MUX_MODE7) /* cam1_data9.gpio4_7 BT_EN */
	>;
	};
	};

	&i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	clock-frequency = <100000>;

	tps@24 {
	compatible = "ti,tps65218";
	reg = <0x24>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;

	dcdc1: regulator-dcdc1 {
	/* VDD_CORE limits min of OPP50 and max of OPP100 */
	regulator-name = "vdd_core";
	regulator-min-microvolt = <912000>;
	regulator-max-microvolt = <1144000>;
	regulator-boot-on;
	regulator-always-on;
	};

	dcdc2: regulator-dcdc2 {
	/* VDD_MPU limits min of OPP50 and max of OPP_NITRO */
	regulator-name = "vdd_mpu";
	regulator-min-microvolt = <912000>;
	regulator-max-microvolt = <1378000>;
	regulator-boot-on;
	regulator-always-on;
	};

	dcdc3: regulator-dcdc3 {
	regulator-name = "vdds_ddr";
	regulator-boot-on;
	regulator-always-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	regulator-state-disk {
	regulator-off-in-suspend;
	};
	};

	dcdc4: regulator-dcdc4 {
	regulator-name = "v3_3d";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	dcdc5: regulator-dcdc5 {
	compatible = "ti,tps65218-dcdc5";
	regulator-name = "v1_0bat";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	dcdc6: regulator-dcdc6 {
	compatible = "ti,tps65218-dcdc6";
	regulator-name = "v1_8bat";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	ldo1: regulator-ldo1 {
	regulator-name = "v1_8d";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	power-button {
	compatible = "ti,tps65218-pwrbutton";
	status = "okay";
	interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
	};
	};

	at24@50 {
	compatible = "atmel,24c256";
	pagesize = <64>;
	reg = <0x50>;
	};
	};

	&i2c1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	clock-frequency = <400000>;

	ov2659@30 {
	compatible = "ovti,ov2659";
	reg = <0x30>;
	pinctrl-names = "default";
	pinctrl-0 = <&clkout1_pin>;

	clocks = <&clkout1_mux_ck>;
	clock-names = "xvclk";
	assigned-clocks = <&clkout1_mux_ck>;
	assigned-clock-parents = <&clkout1_osc_div_ck>;

	port {
	ov2659_1: endpoint {
	remote-endpoint = <&vpfe0_ep>;
	link-frequencies = /bits/ 64 <70000000>;
	};
	};
	};

	edt-ft5306@38 {
	status = "okay";
	compatible = "edt,edt-ft5306", "edt,edt-ft5x06";
	pinctrl-names = "default";
	pinctrl-0 = <&edt_ft5306_ts_pins>;

	reg = <0x38>;
	interrupt-parent = <&gpio0>;
	interrupts = <31 IRQ_TYPE_EDGE_FALLING>;

	reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;

	touchscreen-size-x = <480>;
	touchscreen-size-y = <272>;

	wakeup-source;
	};

	tlv320aic3106: tlv320aic3106@1b {
	#sound-dai-cells = <0>;
	compatible = "ti,tlv320aic3106";
	reg = <0x1b>;
	status = "okay";

	/* Regulators */
	AVDD-supply = <&dcdc4>;
	IOVDD-supply = <&dcdc4>;
	DRVDD-supply = <&dcdc4>;
	DVDD-supply = <&ldo1>;
	};

	lis331dlh@18 {
	compatible = "st,lis331dlh";
	reg = <0x18>;
	status = "okay";

	Vdd-supply = <&dcdc4>;
	Vdd_IO-supply = <&dcdc4>;
	interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>;
	};
	};

	&epwmss0 {
	status = "okay";
	};

	&ecap0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&ecap0_pins>;
	};

	&gpio0 {
	status = "okay";
	};

	&gpio1 {
	status = "okay";
	};

	&gpio4 {
	status = "okay";
	};

	&gpio5 {
	status = "okay";
	};

	&mmc1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;

	vmmc-supply = <&dcdc4>;
	bus-width = <4>;
	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
	};

	&uart1 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&uart1_bt_pins_default>;
	pinctrl-1 = <&uart1_bt_pins_sleep>;
	};

	&mmc3 {
	status = "okay";
	/*
	* these are on the crossbar and are outlined in the
	* xbar-event-map element
	*/
	dmas = <&edma_xbar 30 0 1>,
	<&edma_xbar 31 0 2>;
	dma-names = "tx", "rx";
	vmmc-supply = <&vmmcwl_fixed>;
	bus-width = <4>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mmc3_pins_default>;
	pinctrl-1 = <&mmc3_pins_sleep>;
	cap-power-off-card;
	keep-power-in-suspend;
	ti,non-removable;

	#address-cells = <1>;
	#size-cells = <0>;
	wlcore: wlcore@2 {
	compatible = "ti,wl1835";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&wlan_pins_default>;
	pinctrl-1 = <&wlan_pins_sleep>;
	reg = <2>;
	interrupt-parent = <&gpio4>;
	interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	&usb2_phy1 {
	status = "okay";
	};

	&usb1 {
	dr_mode = "otg";
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&usb1_pins>;
	};

	&usb2_phy2 {
	status = "okay";
	};

	&usb2 {
	dr_mode = "host";
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&usb2_pins>;
	};

	&qspi {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&qspi_pins>;

	spi-max-frequency = <48000000>;
	m25p80@0 {
	compatible = "mx66l51235l";
	spi-max-frequency = <48000000>;
	reg = <0>;
	spi-cpol;
	spi-cpha;
	spi-tx-bus-width = <1>;
	spi-rx-bus-width = <4>;
	#address-cells = <1>;
	#size-cells = <1>;

	/* MTD partition table.
	* The ROM checks the first 512KiB
	* for a valid file to boot(XIP).
	*/
	partition@0 {
	label = "QSPI.U_BOOT";
	reg = <0x00000000 0x000080000>;
	};
	partition@1 {
	label = "QSPI.U_BOOT.backup";
	reg = <0x00080000 0x00080000>;
	};
	partition@2 {
	label = "QSPI.U-BOOT-SPL_OS";
	reg = <0x00100000 0x00010000>;
	};
	partition@3 {
	label = "QSPI.U_BOOT_ENV";
	reg = <0x00110000 0x00010000>;
	};
	partition@4 {
	label = "QSPI.U-BOOT-ENV.backup";
	reg = <0x00120000 0x00010000>;
	};
	partition@5 {
	label = "QSPI.KERNEL";
	reg = <0x00130000 0x0800000>;
	};
	partition@6 {
	label = "QSPI.FILESYSTEM";
	reg = <0x00930000 0x36D0000>;
	};
	};
	};

	&mac {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&cpsw_default>;
	pinctrl-1 = <&cpsw_sleep>;
	dual_emac = <1>;
	status = "okay";
	};

	&davinci_mdio {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_default>;
	pinctrl-1 = <&davinci_mdio_sleep>;
	status = "okay";

	ethphy0: ethernet-phy@4 {
	reg = <4>;
	};

	ethphy1: ethernet-phy@5 {
	reg = <5>;
	};
	};

	&cpsw_emac0 {
	phy-handle = <&ethphy0>;
	- phy-mode = "rgmii";
	+ phy-mode = "rgmii-rxid";
	dual_emac_res_vlan = <1>;
	};

	&cpsw_emac1 {
	phy-handle = <&ethphy1>;
	- phy-mode = "rgmii";
	+ phy-mode = "rgmii-rxid";
	dual_emac_res_vlan = <2>;
	};

	&elm {
	status = "okay";
	};

	&mcasp1 {
	#sound-dai-cells = <0>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mcasp1_pins>;
	pinctrl-1 = <&mcasp1_pins_sleep>;

	status = "okay";

	op-mode = <0>;
	tdm-slots = <2>;
	serial-dir = <
	0 0 1 2
	>;

	tx-num-evt = <1>;
	rx-num-evt = <1>;
	};

	&dss {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&dss_pins>;

	port {
	dpi_out: endpoint@0 {
	remote-endpoint = <&lcd_in>;
	data-lines = <24>;
	};
	};
	};

	&rtc {
	clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
	clock-names = "ext-clk", "int-clk";
	status = "okay";
	};

	&wdt {
	status = "okay";
	};

	&cpu {
	cpu0-supply = <&dcdc2>;
	};

	&vpfe0 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&vpfe0_pins_default>;
	pinctrl-1 = <&vpfe0_pins_sleep>;

	/* Camera port */
	port {
	vpfe0_ep: endpoint {
	remote-endpoint = <&ov2659_1>;
	ti,am437x-vpfe-interface = <0>;
	bus-width = <8>;
	hsync-active = <0>;
	vsync-active = <0>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/am57-pruss.dtsi b/sys/gnu/dts/arm/am57-pruss.dtsi
	new file mode 100644
	index 000000000000..b1c583dee10b
	--- /dev/null
	+++ b/sys/gnu/dts/arm/am57-pruss.dtsi
	@@ -0,0 +1,50 @@
	+// SPDX-License-Identifier: GPL-2.0-only
	+/*
	+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
	+ *
	+ * Common PRUSS data for TI AM57xx platforms
	+ */
	+
	+&ocp {
	+ pruss1_tm: target-module@4b226000 {
	+ compatible = "ti,sysc-pruss", "ti,sysc";
	+ reg = <0x4b226000 0x4>,
	+ <0x4b226004 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT \|
	+ SYSC_PRUSS_SUB_MWAIT)>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ /* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */
	+ clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x00000000 0x4b200000 0x80000>;
	+ };
	+
	+ pruss2_tm: target-module@4b2a6000 {
	+ compatible = "ti,sysc-pruss", "ti,sysc";
	+ reg = <0x4b2a6000 0x4>,
	+ <0x4b2a6004 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT \|
	+ SYSC_PRUSS_SUB_MWAIT)>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ /* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */
	+ clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS2_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x00000000 0x4b280000 0x80000>;
	+ };
	+};
	diff --git a/sys/gnu/dts/arm/am5718.dtsi b/sys/gnu/dts/arm/am5718.dtsi
	index d51007c3e8c4..a80c2e3eee2e 100644
	--- a/sys/gnu/dts/arm/am5718.dtsi
	+++ b/sys/gnu/dts/arm/am5718.dtsi
	@@ -1,32 +1,33 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
	*/

	#include "dra72x.dtsi"
	+#include "am57-pruss.dtsi"

	/ {
	compatible = "ti,am5718", "ti,dra7";
	};

	/*
	* These modules are not present on AM5718
	*
	* ATL
	* VCP1, VCP2
	* MLB
	* ISS
	* USB3, USB4
	*/

	&usb3_tm {
	status = "disabled";
	};

	&usb4_tm {
	status = "disabled";
	};

	&atl_tm {
	status = "disabled";
	};
	diff --git a/sys/gnu/dts/arm/am571x-idk.dts b/sys/gnu/dts/arm/am571x-idk.dts
	index 669559c9c95b..c13756fa0f55 100644
	--- a/sys/gnu/dts/arm/am571x-idk.dts
	+++ b/sys/gnu/dts/arm/am571x-idk.dts
	@@ -1,211 +1,211 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
	*/
	/dts-v1/;

	#include "am5718.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include "dra7-mmc-iodelay.dtsi"
	#include "dra72x-mmc-iodelay.dtsi"
	#include "am57xx-idk-common.dtsi"

	/ {
	model = "TI AM5718 IDK";
	compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7";

	memory@80000000 {
	device_type = "memory";
	reg = <0x0 0x80000000 0x0 0x40000000>;
	};

	leds {
	compatible = "gpio-leds";
	cpu0-led {
	label = "status0:red:cpu0";
	gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	linux,default-trigger = "cpu0";
	};

	usr0-led {
	label = "status0:green:usr";
	gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	heartbeat-led {
	label = "status0:blue:heartbeat";
	gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	linux,default-trigger = "heartbeat";
	};

	usr1-led {
	label = "status1:red:usr";
	gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	usr2-led {
	label = "status1:green:usr";
	gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	mmc0-led {
	label = "status1:blue:mmc0";
	gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	linux,default-trigger = "mmc0";
	};
	};

	idk-leds {
	status = "disabled";
	compatible = "gpio-leds";
	red0-led {
	label = "idk:red0";
	gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	green0-led {
	label = "idk:green0";
	gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	blue0-led {
	label = "idk:blue0";
	gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	red1-led {
	label = "idk:red1";
	gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	green1-led {
	label = "idk:green1";
	gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	blue1-led {
	label = "idk:blue1";
	gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	red2-led {
	label = "idk:red2";
	gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	green2-led {
	label = "idk:green2";
	gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	blue2-led {
	label = "idk:blue2";
	gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	red3-led {
	label = "idk:red3";
	gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	green3-led {
	label = "idk:green3";
	gpios = <&gpio7 25 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	blue3-led {
	label = "idk:blue3";
	gpios = <&gpio7 24 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};
	};
	};

	&extcon_usb2 {
	id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
	vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>;
	};

	&sn65hvs882 {
	load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
	};

	&mailbox5 {
	status = "okay";
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
	status = "okay";
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
	status = "okay";
	};
	};

	&mailbox6 {
	status = "okay";
	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
	status = "okay";
	};
	};

	&pcie1_rc {
	status = "okay";
	gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
	};

	&mmc1 {
	pinctrl-names = "default", "hs";
	pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
	pinctrl-1 = <&mmc1_pins_hs>;
	};

	&mmc2 {
	pinctrl-names = "default", "hs", "ddr_3_3v";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
	pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
	};

	&mac_sw {
	pinctrl-names = "default", "sleep";
	status = "okay";
	};

	&cpsw_port1 {
	phy-handle = <&ethphy0_sw>;
	- phy-mode = "rgmii";
	+ phy-mode = "rgmii-rxid";
	ti,dual-emac-pvid = <1>;
	};

	&cpsw_port2 {
	phy-handle = <&ethphy1_sw>;
	- phy-mode = "rgmii";
	+ phy-mode = "rgmii-rxid";
	ti,dual-emac-pvid = <2>;
	};

	&davinci_mdio_sw {
	ethphy0_sw: ethernet-phy@0 {
	reg = <0>;
	};

	ethphy1_sw: ethernet-phy@1 {
	reg = <1>;
	};
	};
	diff --git a/sys/gnu/dts/arm/am5728.dtsi b/sys/gnu/dts/arm/am5728.dtsi
	index 82e5427ef6a9..9a3810f5adcc 100644
	--- a/sys/gnu/dts/arm/am5728.dtsi
	+++ b/sys/gnu/dts/arm/am5728.dtsi
	@@ -1,33 +1,34 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
	*/

	#include "dra74x.dtsi"
	+#include "am57-pruss.dtsi"

	/ {
	compatible = "ti,am5728", "ti,dra7";
	};

	/*
	* These modules are not present on AM5728
	*
	* EVE1, EVE2
	* ATL
	* VCP1, VCP2
	* MLB
	* ISS
	* USB3, USB4
	*/

	&usb3_tm {
	status = "disabled";
	};

	&usb4_tm {
	status = "disabled";
	};

	&atl_tm {
	status = "disabled";
	};
	diff --git a/sys/gnu/dts/arm/am5748.dtsi b/sys/gnu/dts/arm/am5748.dtsi
	index 5e129759d04a..2b65317b1513 100644
	--- a/sys/gnu/dts/arm/am5748.dtsi
	+++ b/sys/gnu/dts/arm/am5748.dtsi
	@@ -1,33 +1,34 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
	*/

	#include "dra76x.dtsi"
	+#include "am57-pruss.dtsi"

	/ {
	compatible = "ti,am5748", "ti,dra762", "ti,dra7";
	};

	/*
	* These modules are not present on AM5748
	*
	* EVE1, EVE2
	* ATL
	* VCP1, VCP2
	* MLB
	* ISS
	* USB3, USB4
	*/

	&usb3_tm {
	status = "disabled";
	};

	&usb4_tm {
	status = "disabled";
	};

	&atl_tm {
	status = "disabled";
	};
	diff --git a/sys/gnu/dts/arm/am574x-idk.dts b/sys/gnu/dts/arm/am574x-idk.dts
	index fa0088025b2c..85c95cc551dd 100644
	--- a/sys/gnu/dts/arm/am574x-idk.dts
	+++ b/sys/gnu/dts/arm/am574x-idk.dts
	@@ -1,42 +1,46 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
	*/


	/dts-v1/;

	#include "am5748.dtsi"
	#include "dra7-mmc-iodelay.dtsi"
	#include "dra76x-mmc-iodelay.dtsi"
	#include "am572x-idk-common.dtsi"

	/ {
	model = "TI AM5748 IDK";
	compatible = "ti,am5748-idk", "ti,am5748", "ti,dra762", "ti,dra7";
	};

	&qspi {
	spi-max-frequency = <96000000>;
	m25p80@0 {
	spi-max-frequency = <96000000>;
	};
	};

	&mmc1 {
	pinctrl-names = "default", "hs";
	pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
	pinctrl-1 = <&mmc1_pins_hs>;
	};

	&mmc2 {
	pinctrl-names = "default", "hs", "ddr_3_3v";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_default>;
	pinctrl-2 = <&mmc2_pins_default>;
	};

	&mac {
	status = "okay";
	dual_emac;
	};
	+
	+&m_can0 {
	+ status = "disabled";
	+};
	diff --git a/sys/gnu/dts/arm/am57xx-beagle-x15-common.dtsi b/sys/gnu/dts/arm/am57xx-beagle-x15-common.dtsi
	index a813a0cf3ff3..565675354de4 100644
	--- a/sys/gnu/dts/arm/am57xx-beagle-x15-common.dtsi
	+++ b/sys/gnu/dts/arm/am57xx-beagle-x15-common.dtsi
	@@ -1,605 +1,605 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
	*/
	/dts-v1/;

	#include "am5728.dtsi"
	#include "am57xx-commercial-grade.dtsi"
	#include "dra74x-mmc-iodelay.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/irq.h>

	/ {
	compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";

	aliases {
	rtc0 = &mcp_rtc;
	rtc1 = &tps659038_rtc;
	rtc2 = &rtc;
	display0 = &hdmi0;
	};

	chosen {
	stdout-path = &uart3;
	};

	memory@0 {
	device_type = "memory";
	reg = <0x0 0x80000000 0x0 0x80000000>;
	};

	main_12v0: fixedregulator-main_12v0 {
	/* main supply */
	compatible = "regulator-fixed";
	regulator-name = "main_12v0";
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	regulator-always-on;
	regulator-boot-on;
	};

	evm_5v0: fixedregulator-evm_5v0 {
	/* Output of TPS54531D */
	compatible = "regulator-fixed";
	regulator-name = "evm_5v0";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&main_12v0>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_3v3: fixedregulator-vdd_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "vdd_3v3";
	vin-supply = <&regen1>;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	aic_dvdd: fixedregulator-aic_dvdd {
	compatible = "regulator-fixed";
	regulator-name = "aic_dvdd_fixed";
	vin-supply = <&vdd_3v3>;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	vtt_fixed: fixedregulator-vtt {
	/* TPS51200 */
	compatible = "regulator-fixed";
	regulator-name = "vtt_fixed";
	vin-supply = <&smps3_reg>;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	enable-active-high;
	gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
	};

	leds {
	compatible = "gpio-leds";

	led0 {
	label = "beagle-x15:usr0";
	gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	default-state = "off";
	};

	led1 {
	label = "beagle-x15:usr1";
	gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "cpu0";
	default-state = "off";
	};

	led2 {
	label = "beagle-x15:usr2";
	gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "mmc0";
	default-state = "off";
	};

	led3 {
	label = "beagle-x15:usr3";
	gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "disk-activity";
	default-state = "off";
	};
	};

	gpio_fan: gpio_fan {
	/* Based on 5v 500mA AFB02505HHB */
	compatible = "gpio-fan";
	gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>;
	gpio-fan,speed-map = <0 0>,
	<13000 1>;
	#cooling-cells = <2>;
	};

	hdmi0: connector {
	compatible = "hdmi-connector";
	label = "hdmi";

	type = "a";

	port {
	hdmi_connector_in: endpoint {
	remote-endpoint = <&tpd12s015_out>;
	};
	};
	};

	tpd12s015: encoder {
	compatible = "ti,tpd12s015";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	tpd12s015_in: endpoint {
	remote-endpoint = <&hdmi_out>;
	};
	};

	port@1 {
	reg = <1>;

	tpd12s015_out: endpoint {
	remote-endpoint = <&hdmi_connector_in>;
	};
	};
	};
	};

	sound0: sound0 {
	compatible = "simple-audio-card";
	simple-audio-card,name = "BeagleBoard-X15";
	simple-audio-card,widgets =
	"Line", "Line Out",
	"Line", "Line In";
	simple-audio-card,routing =
	"Line Out", "LLOUT",
	"Line Out", "RLOUT",
	"MIC2L", "Line In",
	"MIC2R", "Line In";
	simple-audio-card,format = "dsp_b";
	simple-audio-card,bitclock-master = <&sound0_master>;
	simple-audio-card,frame-master = <&sound0_master>;
	simple-audio-card,bitclock-inversion;

	simple-audio-card,cpu {
	sound-dai = <&mcasp3>;
	};

	sound0_master: simple-audio-card,codec {
	sound-dai = <&tlv320aic3104>;
	clocks = <&clkout2_clk>;
	};
	};
	};

	&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

	tps659038: tps659038@58 {
	compatible = "ti,tps659038";
	reg = <0x58>;
	interrupt-parent = <&gpio1>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;

	#interrupt-cells = <2>;
	interrupt-controller;

	ti,system-power-controller;
	ti,palmas-override-powerhold;

	tps659038_pmic {
	compatible = "ti,tps659038-pmic";

	regulators {
	smps12_reg: smps12 {
	/* VDD_MPU */
	regulator-name = "smps12";
	regulator-min-microvolt = < 850000>;
	regulator-max-microvolt = <1250000>;
	regulator-always-on;
	regulator-boot-on;
	};

	smps3_reg: smps3 {
	/* VDD_DDR */
	regulator-name = "smps3";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	};

	smps45_reg: smps45 {
	/* VDD_DSPEVE, VDD_IVA, VDD_GPU */
	regulator-name = "smps45";
	regulator-min-microvolt = < 850000>;
	regulator-max-microvolt = <1250000>;
	regulator-always-on;
	regulator-boot-on;
	};

	smps6_reg: smps6 {
	/* VDD_CORE */
	regulator-name = "smps6";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1150000>;
	regulator-always-on;
	regulator-boot-on;
	};

	/* SMPS7 unused */

	smps8_reg: smps8 {
	/* VDD_1V8 */
	regulator-name = "smps8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	/* SMPS9 unused */

	ldo1_reg: ldo1 {
	/* VDD_SD / VDDSHV8 */
	regulator-name = "ldo1";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo2_reg: ldo2 {
	/* VDD_SHV5 */
	regulator-name = "ldo2";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldo3_reg: ldo3 {
	/* VDDA_1V8_PHYA */
	regulator-name = "ldo3";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldo4_reg: ldo4 {
	/* VDDA_1V8_PHYB */
	regulator-name = "ldo4";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldo9_reg: ldo9 {
	/* VDD_RTC */
	regulator-name = "ldo9";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldoln_reg: ldoln {
	/* VDDA_1V8_PLL */
	regulator-name = "ldoln";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldousb_reg: ldousb {
	/* VDDA_3V_USB: VDDA_USBHS33 */
	regulator-name = "ldousb";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	};

	regen1: regen1 {
	/* VDD_3V3_ON */
	regulator-name = "regen1";
	regulator-boot-on;
	regulator-always-on;
	};
	};
	};

	tps659038_rtc: tps659038_rtc {
	compatible = "ti,palmas-rtc";
	interrupt-parent = <&tps659038>;
	interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
	wakeup-source;
	};

	tps659038_pwr_button: tps659038_pwr_button {
	compatible = "ti,palmas-pwrbutton";
	interrupt-parent = <&tps659038>;
	interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
	wakeup-source;
	ti,palmas-long-press-seconds = <12>;
	};

	tps659038_gpio: tps659038_gpio {
	compatible = "ti,palmas-gpio";
	gpio-controller;
	#gpio-cells = <2>;
	};

	extcon_usb2: tps659038_usb {
	compatible = "ti,palmas-usb-vid";
	ti,enable-vbus-detection;
	vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
	};

	};

	tmp102: tmp102@48 {
	compatible = "ti,tmp102";
	reg = <0x48>;
	interrupt-parent = <&gpio7>;
	interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
	#thermal-sensor-cells = <1>;
	};

	tlv320aic3104: tlv320aic3104@18 {
	#sound-dai-cells = <0>;
	compatible = "ti,tlv320aic3104";
	reg = <0x18>;
	assigned-clocks = <&clkoutmux2_clk_mux>;
	assigned-clock-parents = <&sys_clk2_dclk_div>;

	status = "okay";
	adc-settle-ms = <40>;

	AVDD-supply = <&vdd_3v3>;
	IOVDD-supply = <&vdd_3v3>;
	DRVDD-supply = <&vdd_3v3>;
	DVDD-supply = <&aic_dvdd>;
	};

	eeprom: eeprom@50 {
	compatible = "atmel,24c32";
	reg = <0x50>;
	};
	};

	&i2c3 {
	status = "okay";
	clock-frequency = <400000>;

	mcp_rtc: rtc@6f {
	compatible = "microchip,mcp7941x";
	reg = <0x6f>;
	interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
	<&dra7_pmx_core 0x424>;
	interrupt-names = "irq", "wakeup";

	vcc-supply = <&vdd_3v3>;
	wakeup-source;
	};
	};

	&gpio7_target {
	ti,no-reset-on-init;
	ti,no-idle-on-init;
	};

	&cpu0 {
	vdd-supply = <&smps12_reg>;
	voltage-tolerance = <1>;
	};

	&uart3 {
	status = "okay";
	interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
	<&dra7_pmx_core 0x3f8>;
	};

	&davinci_mdio {
	phy0: ethernet-phy@1 {
	reg = <1>;
	};

	phy1: ethernet-phy@2 {
	reg = <2>;
	};
	};

	&mac {
	status = "okay";
	dual_emac;
	};

	&cpsw_emac0 {
	phy-handle = <&phy0>;
	- phy-mode = "rgmii";
	+ phy-mode = "rgmii-rxid";
	dual_emac_res_vlan = <1>;
	};

	&cpsw_emac1 {
	phy-handle = <&phy1>;
	- phy-mode = "rgmii";
	+ phy-mode = "rgmii-rxid";
	dual_emac_res_vlan = <2>;
	};

	&mmc1 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins_default>;

	bus-width = <4>;
	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
	no-1-8-v;
	};

	&mmc2 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_pins_default>;

	vmmc-supply = <&vdd_3v3>;
	vqmmc-supply = <&vdd_3v3>;
	bus-width = <8>;
	non-removable;
	no-1-8-v;
	};

	&sata {
	status = "okay";
	};

	&usb2_phy1 {
	phy-supply = <&ldousb_reg>;
	};

	&usb2_phy2 {
	phy-supply = <&ldousb_reg>;
	};

	&usb1 {
	dr_mode = "host";
	};

	&omap_dwc3_2 {
	extcon = <&extcon_usb2>;
	};

	&usb2 {
	/*
	* Stand alone usage is peripheral only.
	* However, with some resistor modifications
	* this port can be used via expansion connectors
	* as "host" or "dual-role". If so, provide
	* the necessary dr_mode override in the expansion
	* board's DT.
	*/
	dr_mode = "peripheral";
	};

	&cpu_trips {
	cpu_alert1: cpu_alert1 {
	temperature = <50000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "active";
	};
	};

	&cpu_cooling_maps {
	map1 {
	trip = <&cpu_alert1>;
	cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};

	&thermal_zones {
	board_thermal: board_thermal {
	polling-delay-passive = <1250>; /* milliseconds */
	polling-delay = <1500>; /* milliseconds */

	/* sensor ID */
	thermal-sensors = <&tmp102 0>;

	board_trips: trips {
	board_alert0: board_alert {
	temperature = <40000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "active";
	};

	board_crit: board_crit {
	temperature = <105000>; /* millicelsius */
	hysteresis = <0>; /* millicelsius */
	type = "critical";
	};
	};

	board_cooling_maps: cooling-maps {
	map0 {
	trip = <&board_alert0>;
	cooling-device =
	<&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};
	};

	&dss {
	status = "ok";

	vdda_video-supply = <&ldoln_reg>;
	};

	&hdmi {
	status = "ok";
	vdda-supply = <&ldo4_reg>;

	port {
	hdmi_out: endpoint {
	remote-endpoint = <&tpd12s015_in>;
	};
	};
	};

	&pcie1_rc {
	status = "ok";
	gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
	};

	&mcasp3 {
	#sound-dai-cells = <0>;
	assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
	assigned-clock-parents = <&sys_clkin2>;
	status = "okay";

	op-mode = <0>; /* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializers */
	serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
	1 2 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
	};

	&mailbox5 {
	status = "okay";
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
	status = "okay";
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
	status = "okay";
	};
	};

	&mailbox6 {
	status = "okay";
	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
	status = "okay";
	};
	mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
	status = "okay";
	};
	};
	diff --git a/sys/gnu/dts/arm/am57xx-idk-common.dtsi b/sys/gnu/dts/arm/am57xx-idk-common.dtsi
	index aa5e55f98179..a3ff1237d1fa 100644
	--- a/sys/gnu/dts/arm/am57xx-idk-common.dtsi
	+++ b/sys/gnu/dts/arm/am57xx-idk-common.dtsi
	@@ -1,546 +1,546 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
	*/

	#include "am57xx-industrial-grade.dtsi"

	/ {
	aliases {
	rtc0 = &tps659038_rtc;
	rtc1 = &rtc;
	display0 = &hdmi0;
	};

	chosen {
	stdout-path = &uart3;
	};

	vmain: fixedregulator-vmain {
	compatible = "regulator-fixed";
	regulator-name = "VMAIN";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	};

	v3_3d: fixedregulator-v3_3d {
	compatible = "regulator-fixed";
	regulator-name = "V3_3D";
	vin-supply = <&smps9_reg>;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vtt_fixed: fixedregulator-vtt {
	/* TPS51200 */
	compatible = "regulator-fixed";
	regulator-name = "vtt_fixed";
	vin-supply = <&v3_3d>;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	};

	leds-iio {
	status = "disabled";
	compatible = "gpio-leds";
	led-out0 {
	label = "out0";
	gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	led-out1 {
	label = "out1";
	gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	led-out2 {
	label = "out2";
	gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	led-out3 {
	label = "out3";
	gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	led-out4 {
	label = "out4";
	gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	led-out5 {
	label = "out5";
	gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	led-out6 {
	label = "out6";
	gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	led-out7 {
	label = "out7";
	gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};
	};

	hdmi0: connector@0 {
	compatible = "hdmi-connector";
	label = "hdmi";

	type = "a";

	port {
	hdmi_connector_in: endpoint {
	remote-endpoint = <&tpd12s015_out>;
	};
	};
	};

	tpd12s015: encoder@0 {
	compatible = "ti,tpd12s016", "ti,tpd12s015";

	gpios = <0>, /* optional CT_CP_HPD */
	<0>, /* optional LS_OE */
	<&gpio7 12 GPIO_ACTIVE_HIGH>; /* HPD */

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	tpd12s015_in: endpoint@0 {
	remote-endpoint = <&hdmi_out>;
	};
	};

	port@1 {
	reg = <1>;

	tpd12s015_out: endpoint@0 {
	remote-endpoint = <&hdmi_connector_in>;
	};
	};
	};
	};
	};

	&dra7_pmx_core {
	dcan1_pins_default: dcan1_pins_default {
	pinctrl-single,pins = <
	DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP \| MUX_MODE0) /* dcan1_tx */
	DRA7XX_CORE_IOPAD(0x37d4, PIN_INPUT_PULLUP \| MUX_MODE0) /* dcan1_rx */
	>;
	};

	dcan1_pins_sleep: dcan1_pins_sleep {
	pinctrl-single,pins = <
	DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 \| PULL_UP) /* dcan1_tx.off */
	DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 \| PULL_UP) /* dcan1_rx.off */
	>;
	};
	};

	&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

	tps659038: tps659038@58 {
	compatible = "ti,tps659038";
	reg = <0x58>;
	interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_HIGH
	&dra7_pmx_core 0x418>;
	#interrupt-cells = <2>;
	interrupt-controller;
	ti,system-power-controller;
	ti,palmas-override-powerhold;

	tps659038_pmic {
	compatible = "ti,tps659038-pmic";

	smps12-in-supply = <&vmain>;
	smps3-in-supply = <&vmain>;
	smps45-in-supply = <&vmain>;
	smps6-in-supply = <&vmain>;
	smps7-in-supply = <&vmain>;
	smps8-in-supply = <&vmain>;
	smps9-in-supply = <&vmain>;
	ldo1-in-supply = <&vmain>;
	ldo2-in-supply = <&vmain>;
	ldo3-in-supply = <&vmain>;
	ldo4-in-supply = <&vmain>;
	ldo9-in-supply = <&vmain>;
	ldoln-in-supply = <&vmain>;
	ldousb-in-supply = <&vmain>;
	ldortc-in-supply = <&vmain>;

	regulators {
	smps12_reg: smps12 {
	/* VDD_MPU */
	regulator-name = "smps12";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1250000>;
	regulator-always-on;
	regulator-boot-on;
	};

	smps3_reg: smps3 {
	/* VDD_DDR EMIF1 EMIF2 */
	regulator-name = "smps3";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	};

	smps45_reg: smps45 {
	/* VDD_DSPEVE on AM572 */
	/* VDD_IVA + VDD_DSP on AM571 */
	regulator-name = "smps45";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1250000>;
	regulator-always-on;
	regulator-boot-on;
	};

	smps6_reg: smps6 {
	/* VDD_GPU */
	regulator-name = "smps6";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1250000>;
	regulator-always-on;
	regulator-boot-on;
	};

	smps7_reg: smps7 {
	/* VDD_CORE */
	regulator-name = "smps7";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1150000>;
	regulator-always-on;
	regulator-boot-on;
	};

	smps8_reg: smps8 {
	/* 5728 - VDD_IVAHD */
	/* 5718 - N.C. test point */
	regulator-name = "smps8";
	};

	smps9_reg: smps9 {
	/* VDD_3_3D */
	regulator-name = "smps9";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldo1_reg: ldo1 {
	/* VDDSHV8 - VSDMMC */
	/* NOTE: on rev 1.3a, data supply */
	regulator-name = "ldo1";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo2_reg: ldo2 {
	/* VDDSH18V */
	regulator-name = "ldo2";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldo3_reg: ldo3 {
	/* R1.3a 572x V1_8PHY_LDO3: USB, SATA */
	regulator-name = "ldo3";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldo4_reg: ldo4 {
	/* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
	regulator-name = "ldo4";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	/* LDO5-8 unused */

	ldo9_reg: ldo9 {
	/* VDD_RTC */
	regulator-name = "ldo9";
	regulator-min-microvolt = <840000>;
	regulator-max-microvolt = <1160000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldoln_reg: ldoln {
	/* VDDA_1V8_PLL */
	regulator-name = "ldoln";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldousb_reg: ldousb {
	/* VDDA_3V_USB: VDDA_USBHS33 */
	regulator-name = "ldousb";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldortc_reg: ldortc {
	/* VDDA_RTC */
	regulator-name = "ldortc";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	regen1: regen1 {
	/* VDD_3V3_ON */
	regulator-name = "regen1";
	regulator-boot-on;
	regulator-always-on;
	};

	regen2: regen2 {
	/* Needed for PMIC internal resource */
	regulator-name = "regen2";
	regulator-boot-on;
	regulator-always-on;
	};
	};
	};

	tps659038_rtc: tps659038_rtc {
	compatible = "ti,palmas-rtc";
	interrupt-parent = <&tps659038>;
	interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
	wakeup-source;
	};

	tps659038_pwr_button: tps659038_pwr_button {
	compatible = "ti,palmas-pwrbutton";
	interrupt-parent = <&tps659038>;
	interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
	wakeup-source;
	ti,palmas-long-press-seconds = <12>;
	};

	tps659038_gpio: tps659038_gpio {
	compatible = "ti,palmas-gpio";
	gpio-controller;
	#gpio-cells = <2>;
	};

	extcon_usb2: tps659038_usb {
	compatible = "ti,palmas-usb-vid";
	ti,enable-vbus-detection;
	ti,enable-id-detection;
	/* ID & VBUS GPIOs provided in board dts */
	};
	};

	tpic2810: tpic2810@60 {
	compatible = "ti,tpic2810";
	reg = <0x60>;
	gpio-controller;
	#gpio-cells = <2>;
	};
	};

	&mcspi3 {
	status = "okay";
	ti,pindir-d0-out-d1-in;

	sn65hvs882: sn65hvs882@0 {
	compatible = "pisosr-gpio";
	gpio-controller;
	#gpio-cells = <2>;

	reg = <0>;
	spi-max-frequency = <1000000>;
	spi-cpol;
	};
	};

	&uart3 {
	status = "okay";
	interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH
	&dra7_pmx_core 0x248>;
	};

	&rtc {
	status = "okay";
	ext-clk-src;
	};

	&cpsw_emac0 {
	phy-handle = <&ethphy0>;
	- phy-mode = "rgmii";
	+ phy-mode = "rgmii-rxid";
	dual_emac_res_vlan = <1>;
	};

	&cpsw_emac1 {
	phy-handle = <&ethphy1>;
	- phy-mode = "rgmii";
	+ phy-mode = "rgmii-rxid";
	dual_emac_res_vlan = <2>;
	};

	&davinci_mdio {
	ethphy0: ethernet-phy@0 {
	reg = <0>;
	};

	ethphy1: ethernet-phy@1 {
	reg = <1>;
	};
	};

	&usb2_phy1 {
	phy-supply = <&ldousb_reg>;
	};

	&usb2_phy2 {
	phy-supply = <&ldousb_reg>;
	};

	&usb1 {
	dr_mode = "host";
	};

	&omap_dwc3_2 {
	extcon = <&extcon_usb2>;
	};

	&usb2 {
	extcon = <&extcon_usb2>;
	dr_mode = "otg";
	};

	&mmc1 {
	status = "okay";
	vmmc-supply = <&v3_3d>;
	vqmmc-supply = <&ldo1_reg>;
	bus-width = <4>;
	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
	no-1-8-v;
	};

	&mmc2 {
	status = "okay";
	vmmc-supply = <&v3_3d>;
	vqmmc-supply = <&v3_3d>;
	bus-width = <8>;
	non-removable;
	max-frequency = <96000000>;
	no-1-8-v;
	};

	&dcan1 {
	status = "okay";
	pinctrl-names = "default", "sleep", "active";
	pinctrl-0 = <&dcan1_pins_sleep>;
	pinctrl-1 = <&dcan1_pins_sleep>;
	pinctrl-2 = <&dcan1_pins_default>;
	};

	&qspi {
	status = "okay";

	spi-max-frequency = <76800000>;
	m25p80@0 {
	compatible = "s25fl256s1", "jedec,spi-nor";
	spi-max-frequency = <76800000>;
	reg = <0>;
	spi-tx-bus-width = <1>;
	spi-rx-bus-width = <4>;
	#address-cells = <1>;
	#size-cells = <1>;

	/* MTD partition table.
	* The ROM checks the first four physical blocks
	* for a valid file to boot and the flash here is
	* 64KiB block size.
	*/
	partition@0 {
	label = "QSPI.SPL";
	reg = <0x00000000 0x000040000>;
	};
	partition@1 {
	label = "QSPI.u-boot";
	reg = <0x00040000 0x00100000>;
	};
	partition@2 {
	label = "QSPI.u-boot-spl-os";
	reg = <0x00140000 0x00080000>;
	};
	partition@3 {
	label = "QSPI.u-boot-env";
	reg = <0x001c0000 0x00010000>;
	};
	partition@4 {
	label = "QSPI.u-boot-env.backup1";
	reg = <0x001d0000 0x0010000>;
	};
	partition@5 {
	label = "QSPI.kernel";
	reg = <0x001e0000 0x0800000>;
	};
	partition@6 {
	label = "QSPI.file-system";
	reg = <0x009e0000 0x01620000>;
	};
	};
	};

	&cpu0 {
	vdd-supply = <&smps12_reg>;
	};

	&hdmi {
	status = "okay";

	vdda-supply = <&ldo4_reg>;

	port {
	hdmi_out: endpoint {
	remote-endpoint = <&tpd12s015_in>;
	};
	};
	};

	&dss {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/arm-realview-pbx.dtsi b/sys/gnu/dts/arm/arm-realview-pbx.dtsi
	index 09f3f544f3a7..f61bd59ae5ba 100644
	--- a/sys/gnu/dts/arm/arm-realview-pbx.dtsi
	+++ b/sys/gnu/dts/arm/arm-realview-pbx.dtsi
	@@ -1,577 +1,577 @@
	/*
	* Copyright 2016 Linaro Ltd
	*
	* Permission is hereby granted, free of charge, to any person obtaining a copy
	* of this software and associated documentation files (the "Software"), to deal
	* in the Software without restriction, including without limitation the rights
	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	* copies of the Software, and to permit persons to whom the Software is
	* furnished to do so, subject to the following conditions:
	*
	* The above copyright notice and this permission notice shall be included in
	* all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	* THE SOFTWARE.
	*/

	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/gpio/gpio.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "arm,realview-pbx";

	chosen { };

	aliases {
	serial0 = &serial0;
	serial1 = &serial1;
	serial2 = &serial2;
	serial3 = &serial3;
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	};

	memory {
	device_type = "memory";
	/* 128 MiB memory @ 0x0 */
	reg = <0x00000000 0x08000000>;
	};

	/* The voltage to the MMC card is hardwired at 3.3V */
	vmmc: regulator-vmmc {
	compatible = "regulator-fixed";
	regulator-name = "vmmc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	};

	veth: regulator-veth {
	compatible = "regulator-fixed";
	regulator-name = "veth";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	};

	xtal24mhz: xtal24mhz@24M {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	};

	refclk32khz: refclk32khz {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	};

	timclk: timclk@1M {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clock-div = <24>;
	clock-mult = <1>;
	clocks = <&xtal24mhz>;
	};

	mclk: mclk@24M {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clock-div = <1>;
	clock-mult = <1>;
	clocks = <&xtal24mhz>;
	};

	kmiclk: kmiclk@24M {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clock-div = <1>;
	clock-mult = <1>;
	clocks = <&xtal24mhz>;
	};

	sspclk: sspclk@24M {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clock-div = <1>;
	clock-mult = <1>;
	clocks = <&xtal24mhz>;
	};

	uartclk: uartclk@24M {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clock-div = <1>;
	clock-mult = <1>;
	clocks = <&xtal24mhz>;
	};

	wdogclk: wdogclk@24M {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clock-div = <1>;
	clock-mult = <1>;
	clocks = <&xtal24mhz>;
	};

	/* FIXME: this actually hangs off the PLL clocks */
	pclk: pclk@0 {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <0>;
	};

	flash0@40000000 {
	/* 2 * 32MiB NOR Flash memory */
	compatible = "arm,versatile-flash", "cfi-flash";
	reg = <0x40000000 0x04000000>;
	bank-width = <4>;
	partitions {
	compatible = "arm,arm-firmware-suite";
	};
	};

	flash1@44000000 {
	/* 2 * 32MiB NOR Flash memory */
	compatible = "arm,versatile-flash", "cfi-flash";
	reg = <0x44000000 0x04000000>;
	bank-width = <4>;
	partitions {
	compatible = "arm,arm-firmware-suite";
	};
	};

	/* SMSC 9118 ethernet with PHY and EEPROM */
	ethernet: ethernet@4e000000 {
	compatible = "smsc,lan9118", "smsc,lan9115";
	reg = <0x4e000000 0x10000>;
	phy-mode = "mii";
	reg-io-width = <4>;
	smsc,irq-active-high;
	smsc,irq-push-pull;
	vdd33a-supply = <&veth>;
	vddvario-supply = <&veth>;
	};

	usb: usb@4f000000 {
	compatible = "nxp,usb-isp1761";
	reg = <0x4f000000 0x20000>;
	port1-otg;
	};

	bridge {
	compatible = "ti,ths8134a", "ti,ths8134";
	#address-cells = <1>;
	#size-cells = <0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	vga_bridge_in: endpoint {
	remote-endpoint = <&clcd_pads>;
	};
	};

	port@1 {
	reg = <1>;

	vga_bridge_out: endpoint {
	remote-endpoint = <&vga_con_in>;
	};
	};
	};
	};

	vga {
	/*
	* This DDC I2C is connected directly to the DVI portions
	* of the connector, so it's not really working when the
	* monitor is connected to the VGA connector.
	*/
	compatible = "vga-connector";
	ddc-i2c-bus = <&i2c1>;

	port {
	vga_con_in: endpoint {
	remote-endpoint = <&vga_bridge_out>;
	};
	};
	};

	- soc: soc@0 {
	+ soc: soc {
	compatible = "arm,realview-pbx-soc", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	regmap = <&syscon>;
	ranges;

	syscon: syscon@10000000 {
	compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd";
	reg = <0x10000000 0x1000>;

	led@08.0 {
	compatible = "register-bit-led";
	offset = <0x08>;
	mask = <0x01>;
	label = "versatile:0";
	linux,default-trigger = "heartbeat";
	default-state = "on";
	};
	led@08.1 {
	compatible = "register-bit-led";
	offset = <0x08>;
	mask = <0x02>;
	label = "versatile:1";
	linux,default-trigger = "mmc0";
	default-state = "off";
	};
	led@08.2 {
	compatible = "register-bit-led";
	offset = <0x08>;
	mask = <0x04>;
	label = "versatile:2";
	linux,default-trigger = "cpu0";
	default-state = "off";
	};
	led@08.3 {
	compatible = "register-bit-led";
	offset = <0x08>;
	mask = <0x08>;
	label = "versatile:3";
	default-state = "off";
	};
	led@08.4 {
	compatible = "register-bit-led";
	offset = <0x08>;
	mask = <0x10>;
	label = "versatile:4";
	default-state = "off";
	};
	led@08.5 {
	compatible = "register-bit-led";
	offset = <0x08>;
	mask = <0x20>;
	label = "versatile:5";
	default-state = "off";
	};
	led@08.6 {
	compatible = "register-bit-led";
	offset = <0x08>;
	mask = <0x40>;
	label = "versatile:6";
	default-state = "off";
	};
	led@08.7 {
	compatible = "register-bit-led";
	offset = <0x08>;
	mask = <0x80>;
	label = "versatile:7";
	default-state = "off";
	};
	oscclk0: osc0@0c {
	compatible = "arm,syscon-icst307";
	#clock-cells = <0>;
	lock-offset = <0x20>;
	vco-offset = <0x0C>;
	clocks = <&xtal24mhz>;
	};
	oscclk1: osc1@10 {
	compatible = "arm,syscon-icst307";
	#clock-cells = <0>;
	lock-offset = <0x20>;
	vco-offset = <0x10>;
	clocks = <&xtal24mhz>;
	};
	oscclk2: osc2@14 {
	compatible = "arm,syscon-icst307";
	#clock-cells = <0>;
	lock-offset = <0x20>;
	vco-offset = <0x14>;
	clocks = <&xtal24mhz>;
	};
	oscclk3: osc3@18 {
	compatible = "arm,syscon-icst307";
	#clock-cells = <0>;
	lock-offset = <0x20>;
	vco-offset = <0x18>;
	clocks = <&xtal24mhz>;
	};
	oscclk4: osc4@1c {
	compatible = "arm,syscon-icst307";
	#clock-cells = <0>;
	lock-offset = <0x20>;
	vco-offset = <0x1c>;
	clocks = <&xtal24mhz>;
	};
	};

	sp810_syscon0: sysctl@10001000 {
	compatible = "arm,sp810", "arm,primecell";
	reg = <0x10001000 0x1000>;
	clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
	clock-names = "refclk", "timclk", "apb_pclk";
	#clock-cells = <1>;
	clock-output-names = "timerclk0",
	"timerclk1",
	"timerclk2",
	"timerclk3";
	assigned-clocks = <&sp810_syscon0 0>,
	<&sp810_syscon0 1>,
	<&sp810_syscon0 2>,
	<&sp810_syscon0 3>;
	assigned-clock-parents = <&timclk>,
	<&timclk>,
	<&timclk>,
	<&timclk>;
	};

	i2c0: i2c@10002000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "arm,versatile-i2c";
	reg = <0x10002000 0x1000>;

	rtc@68 {
	compatible = "dallas,ds1338";
	reg = <0x68>;
	};
	};

	serial0: serial@10009000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x10009000 0x1000>;
	clocks = <&uartclk>, <&pclk>;
	clock-names = "uartclk", "apb_pclk";
	};

	serial1: serial@1000a000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x1000a000 0x1000>;
	clocks = <&uartclk>, <&pclk>;
	clock-names = "uartclk", "apb_pclk";
	};

	serial2: serial@1000b000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x1000b000 0x1000>;
	clocks = <&uartclk>, <&pclk>;
	clock-names = "uartclk", "apb_pclk";
	};

	ssp: spi@1000d000 {
	compatible = "arm,pl022", "arm,primecell";
	reg = <0x1000d000 0x1000>;
	clocks = <&sspclk>, <&pclk>;
	clock-names = "SSPCLK", "apb_pclk";
	};

	wdog0: watchdog@1000f000 {
	compatible = "arm,sp805", "arm,primecell";
	reg = <0x1000f000 0x1000>;
	clocks = <&wdogclk>, <&pclk>;
	clock-names = "wdogclk", "apb_pclk";
	status = "disabled";
	};

	wdog1: watchdog@10010000 {
	compatible = "arm,sp805", "arm,primecell";
	reg = <0x10010000 0x1000>;
	clocks = <&wdogclk>, <&pclk>;
	clock-names = "wdogclk", "apb_pclk";
	status = "disabled";
	};

	timer01: timer@10011000 {
	compatible = "arm,sp804", "arm,primecell";
	reg = <0x10011000 0x1000>;
	clocks = <&sp810_syscon0 0>,
	<&sp810_syscon0 1>,
	<&pclk>;
	clock-names = "timerclk0",
	"timerclk1",
	"apb_pclk";
	};

	timer23: timer@10012000 {
	compatible = "arm,sp804", "arm,primecell";
	reg = <0x10012000 0x1000>;
	clocks = <&sp810_syscon0 2>,
	<&sp810_syscon0 3>,
	<&pclk>;
	clock-names = "timerclk2",
	"timerclk3",
	"apb_pclk";
	};

	gpio0: gpio@10013000 {
	compatible = "arm,pl061", "arm,primecell";
	reg = <0x10013000 0x1000>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pclk>;
	clock-names = "apb_pclk";
	};

	gpio1: gpio@10014000 {
	compatible = "arm,pl061", "arm,primecell";
	reg = <0x10014000 0x1000>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pclk>;
	clock-names = "apb_pclk";
	};

	gpio2: gpio@10015000 {
	compatible = "arm,pl061", "arm,primecell";
	reg = <0x10015000 0x1000>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pclk>;
	clock-names = "apb_pclk";
	};

	i2c1: i2c@10016000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "arm,versatile-i2c";
	reg = <0x10016000 0x1000>;
	};

	rtc: rtc@10017000 {
	compatible = "arm,pl031", "arm,primecell";
	reg = <0x10017000 0x1000>;
	clocks = <&pclk>;
	clock-names = "apb_pclk";
	};

	timer45: timer@10018000 {
	compatible = "arm,sp804", "arm,primecell";
	reg = <0x10018000 0x1000>;
	clocks = <&timclk>, <&timclk>, <&pclk>;
	clock-names = "timerclk4", "timerclk5", "apb_pclk";
	};

	timer67: timer@10019000 {
	compatible = "arm,sp804", "arm,primecell";
	reg = <0x10019000 0x1000>;
	clocks = <&timclk>, <&timclk>, <&pclk>;
	clock-names = "timerclk6", "timerclk7", "apb_pclk";
	};

	sp810_syscon1: sysctl@1001a000 {
	compatible = "arm,sp810", "arm,primecell";
	reg = <0x1001a000 0x1000>;
	clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
	clock-names = "refclk", "timclk", "apb_pclk";
	#clock-cells = <1>;
	clock-output-names = "timerclk4",
	"timerclk5",
	"timerclk6",
	"timerclk7";
	assigned-clocks = <&sp810_syscon1 0>,
	<&sp810_syscon1 1>,
	<&sp810_syscon1 2>,
	<&sp810_syscon1 3>;
	assigned-clock-parents = <&timclk>,
	<&timclk>,
	<&timclk>,
	<&timclk>;
	};
	};


	/* These peripherals are inside the FPGA */
	fpga {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	ranges;

	aaci: aaci@10004000 {
	compatible = "arm,pl041", "arm,primecell";
	reg = <0x10004000 0x1000>;
	clocks = <&pclk>;
	clock-names = "apb_pclk";
	};

	mmc: mmcsd@10005000 {
	compatible = "arm,pl18x", "arm,primecell";
	reg = <0x10005000 0x1000>;

	/* Due to frequent FIFO overruns, use just 500 kHz */
	max-frequency = <500000>;
	bus-width = <4>;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	clocks = <&mclk>, <&pclk>;
	clock-names = "mclk", "apb_pclk";
	vmmc-supply = <&vmmc>;
	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
	};

	kmi0: kmi@10006000 {
	compatible = "arm,pl050", "arm,primecell";
	reg = <0x10006000 0x1000>;
	clocks = <&kmiclk>, <&pclk>;
	clock-names = "KMIREFCLK", "apb_pclk";
	};

	kmi1: kmi@10007000 {
	compatible = "arm,pl050", "arm,primecell";
	reg = <0x10007000 0x1000>;
	clocks = <&kmiclk>, <&pclk>;
	clock-names = "KMIREFCLK", "apb_pclk";
	};

	serial3: serial@1000c000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x1000c000 0x1000>;
	clocks = <&uartclk>, <&pclk>;
	clock-names = "uartclk", "apb_pclk";
	};
	};

	/* These peripherals are inside the NEC ISSP */
	issp {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	ranges;

	clcd: clcd@10020000 {
	compatible = "arm,pl111", "arm,primecell";
	reg = <0x10020000 0x1000>;
	interrupt-names = "combined";
	clocks = <&oscclk4>, <&pclk>;
	clock-names = "clcdclk", "apb_pclk";
	/* 1024x768 16bpp @65MHz works fine */
	max-memory-bandwidth = <95000000>;

	port {
	clcd_pads: endpoint {
	remote-endpoint = <&vga_bridge_in>;
	arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/aspeed-g4.dtsi b/sys/gnu/dts/arm/aspeed-g4.dtsi
	index 807a0fc20670..8e04303e8514 100644
	--- a/sys/gnu/dts/arm/aspeed-g4.dtsi
	+++ b/sys/gnu/dts/arm/aspeed-g4.dtsi
	@@ -1,1423 +1,1425 @@
	// SPDX-License-Identifier: GPL-2.0+
	#include <dt-bindings/clock/aspeed-clock.h>

	/ {
	model = "Aspeed BMC";
	compatible = "aspeed,ast2400";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&vic>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	i2c6 = &i2c6;
	i2c7 = &i2c7;
	i2c8 = &i2c8;
	i2c9 = &i2c9;
	i2c10 = &i2c10;
	i2c11 = &i2c11;
	i2c12 = &i2c12;
	i2c13 = &i2c13;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	serial4 = &uart5;
	serial5 = &vuart;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	compatible = "arm,arm926ej-s";
	device_type = "cpu";
	reg = <0>;
	};
	};

	memory@40000000 {
	device_type = "memory";
	reg = <0x40000000 0>;
	};

	ahb {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	fmc: spi@1e620000 {
	reg = < 0x1e620000 0x94
	0x20000000 0x10000000 >;
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "aspeed,ast2400-fmc";
	clocks = <&syscon ASPEED_CLK_AHB>;
	status = "disabled";
	interrupts = <19>;
	flash@0 {
	reg = < 0 >;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <50000000>;
	status = "disabled";
	};
	flash@1 {
	reg = < 1 >;
	compatible = "jedec,spi-nor";
	status = "disabled";
	};
	flash@2 {
	reg = < 2 >;
	compatible = "jedec,spi-nor";
	status = "disabled";
	};
	flash@3 {
	reg = < 3 >;
	compatible = "jedec,spi-nor";
	status = "disabled";
	};
	flash@4 {
	reg = < 4 >;
	compatible = "jedec,spi-nor";
	status = "disabled";
	};
	};

	spi: spi@1e630000 {
	reg = < 0x1e630000 0x18
	0x30000000 0x10000000 >;
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "aspeed,ast2400-spi";
	clocks = <&syscon ASPEED_CLK_AHB>;
	status = "disabled";
	flash@0 {
	reg = < 0 >;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <50000000>;
	status = "disabled";
	};
	};

	vic: interrupt-controller@1e6c0080 {
	compatible = "aspeed,ast2400-vic";
	interrupt-controller;
	#interrupt-cells = <1>;
	valid-sources = <0xffffffff 0x0007ffff>;
	reg = <0x1e6c0080 0x80>;
	};

	cvic: copro-interrupt-controller@1e6c2000 {
	compatible = "aspeed,ast2400-cvic", "aspeed-cvic";
	valid-sources = <0x7fffffff>;
	reg = <0x1e6c2000 0x80>;
	};

	mac0: ethernet@1e660000 {
	compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
	reg = <0x1e660000 0x180>;
	interrupts = <2>;
	clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
	status = "disabled";
	};

	mac1: ethernet@1e680000 {
	compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
	reg = <0x1e680000 0x180>;
	interrupts = <3>;
	clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
	status = "disabled";
	};

	ehci0: usb@1e6a1000 {
	compatible = "aspeed,ast2400-ehci", "generic-ehci";
	reg = <0x1e6a1000 0x100>;
	interrupts = <5>;
	clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb2h_default>;
	status = "disabled";
	};

	uhci: usb@1e6b0000 {
	compatible = "aspeed,ast2400-uhci", "generic-uhci";
	reg = <0x1e6b0000 0x100>;
	interrupts = <14>;
	#ports = <3>;
	clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
	status = "disabled";
	/*
	* No default pinmux, it will follow EHCI, use an explicit pinmux
	* override if you don't enable EHCI
	*/
	};

	vhub: usb-vhub@1e6a0000 {
	compatible = "aspeed,ast2400-usb-vhub";
	reg = <0x1e6a0000 0x300>;
	interrupts = <5>;
	clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
	+ aspeed,vhub-downstream-ports = <5>;
	+ aspeed,vhub-generic-endpoints = <15>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb2d_default>;
	status = "disabled";
	};

	apb {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	syscon: syscon@1e6e2000 {
	compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
	reg = <0x1e6e2000 0x1a8>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x1e6e2000 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;

	p2a: p2a-control@2c {
	reg = <0x2c 0x4>;
	compatible = "aspeed,ast2400-p2a-ctrl";
	status = "disabled";
	};

	pinctrl: pinctrl@80 {
	reg = <0x80 0x18>, <0xa0 0x10>;
	compatible = "aspeed,ast2400-pinctrl";
	};
	};

	rng: hwrng@1e6e2078 {
	compatible = "timeriomem_rng";
	reg = <0x1e6e2078 0x4>;
	period = <1>;
	quality = <100>;
	};

	adc: adc@1e6e9000 {
	compatible = "aspeed,ast2400-adc";
	reg = <0x1e6e9000 0xb0>;
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_ADC>;
	#io-channel-cells = <1>;
	status = "disabled";
	};

	sram: sram@1e720000 {
	compatible = "mmio-sram";
	reg = <0x1e720000 0x8000>; // 32K
	};

	sdmmc: sd-controller@1e740000 {
	compatible = "aspeed,ast2400-sd-controller";
	reg = <0x1e740000 0x100>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x1e740000 0x10000>;
	clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
	status = "disabled";

	sdhci0: sdhci@100 {
	compatible = "aspeed,ast2400-sdhci";
	reg = <0x100 0x100>;
	interrupts = <26>;
	sdhci,auto-cmd12;
	clocks = <&syscon ASPEED_CLK_SDIO>;
	status = "disabled";
	};

	sdhci1: sdhci@200 {
	compatible = "aspeed,ast2400-sdhci";
	reg = <0x200 0x100>;
	interrupts = <26>;
	sdhci,auto-cmd12;
	clocks = <&syscon ASPEED_CLK_SDIO>;
	status = "disabled";
	};
	};

	gpio: gpio@1e780000 {
	#gpio-cells = <2>;
	gpio-controller;
	compatible = "aspeed,ast2400-gpio";
	reg = <0x1e780000 0x1000>;
	interrupts = <20>;
	gpio-ranges = <&pinctrl 0 0 220>;
	clocks = <&syscon ASPEED_CLK_APB>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	timer: timer@1e782000 {
	/* This timer is a Faraday FTTMR010 derivative */
	compatible = "aspeed,ast2400-timer";
	reg = <0x1e782000 0x90>;
	interrupts = <16 17 18 35 36 37 38 39>;
	clocks = <&syscon ASPEED_CLK_APB>;
	clock-names = "PCLK";
	};

	rtc: rtc@1e781000 {
	compatible = "aspeed,ast2400-rtc";
	reg = <0x1e781000 0x18>;
	status = "disabled";
	};

	uart1: serial@1e783000 {
	compatible = "ns16550a";
	reg = <0x1e783000 0x20>;
	reg-shift = <2>;
	interrupts = <9>;
	clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
	resets = <&lpc_reset 4>;
	no-loopback-test;
	status = "disabled";
	};

	uart5: serial@1e784000 {
	compatible = "ns16550a";
	reg = <0x1e784000 0x20>;
	reg-shift = <2>;
	interrupts = <10>;
	clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
	no-loopback-test;
	status = "disabled";
	};

	wdt1: watchdog@1e785000 {
	compatible = "aspeed,ast2400-wdt";
	reg = <0x1e785000 0x1c>;
	clocks = <&syscon ASPEED_CLK_APB>;
	};

	wdt2: watchdog@1e785020 {
	compatible = "aspeed,ast2400-wdt";
	reg = <0x1e785020 0x1c>;
	clocks = <&syscon ASPEED_CLK_APB>;
	};

	pwm_tacho: pwm-tacho-controller@1e786000 {
	compatible = "aspeed,ast2400-pwm-tacho";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x1e786000 0x1000>;
	clocks = <&syscon ASPEED_CLK_24M>;
	resets = <&syscon ASPEED_RESET_PWM>;
	status = "disabled";
	};

	vuart: serial@1e787000 {
	compatible = "aspeed,ast2400-vuart";
	reg = <0x1e787000 0x40>;
	reg-shift = <2>;
	interrupts = <8>;
	clocks = <&syscon ASPEED_CLK_APB>;
	no-loopback-test;
	status = "disabled";
	};

	lpc: lpc@1e789000 {
	compatible = "aspeed,ast2400-lpc", "simple-mfd";
	reg = <0x1e789000 0x1000>;

	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x1e789000 0x1000>;

	lpc_bmc: lpc-bmc@0 {
	compatible = "aspeed,ast2400-lpc-bmc";
	reg = <0x0 0x80>;
	};

	lpc_host: lpc-host@80 {
	compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
	reg = <0x80 0x1e0>;
	reg-io-width = <4>;

	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x80 0x1e0>;

	lpc_ctrl: lpc-ctrl@0 {
	compatible = "aspeed,ast2400-lpc-ctrl";
	reg = <0x0 0x10>;
	clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
	status = "disabled";
	};

	lpc_snoop: lpc-snoop@10 {
	compatible = "aspeed,ast2400-lpc-snoop";
	reg = <0x10 0x8>;
	interrupts = <8>;
	status = "disabled";
	};

	lhc: lhc@20 {
	compatible = "aspeed,ast2400-lhc";
	reg = <0x20 0x24 0x48 0x8>;
	};

	lpc_reset: reset-controller@18 {
	compatible = "aspeed,ast2400-lpc-reset";
	reg = <0x18 0x4>;
	#reset-cells = <1>;
	};

	ibt: ibt@c0 {
	compatible = "aspeed,ast2400-ibt-bmc";
	reg = <0xc0 0x18>;
	interrupts = <8>;
	status = "disabled";
	};
	};
	};

	uart2: serial@1e78d000 {
	compatible = "ns16550a";
	reg = <0x1e78d000 0x20>;
	reg-shift = <2>;
	interrupts = <32>;
	clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
	resets = <&lpc_reset 5>;
	no-loopback-test;
	status = "disabled";
	};

	uart3: serial@1e78e000 {
	compatible = "ns16550a";
	reg = <0x1e78e000 0x20>;
	reg-shift = <2>;
	interrupts = <33>;
	clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
	resets = <&lpc_reset 6>;
	no-loopback-test;
	status = "disabled";
	};

	uart4: serial@1e78f000 {
	compatible = "ns16550a";
	reg = <0x1e78f000 0x20>;
	reg-shift = <2>;
	interrupts = <34>;
	clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
	resets = <&lpc_reset 7>;
	no-loopback-test;
	status = "disabled";
	};

	i2c: bus@1e78a000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x1e78a000 0x1000>;
	};
	};
	};
	};

	&i2c {
	i2c_ic: interrupt-controller@0 {
	#interrupt-cells = <1>;
	compatible = "aspeed,ast2400-i2c-ic";
	reg = <0x0 0x40>;
	interrupts = <12>;
	interrupt-controller;
	};

	i2c0: i2c-bus@40 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x40 0x40>;
	compatible = "aspeed,ast2400-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <0>;
	interrupt-parent = <&i2c_ic>;
	status = "disabled";
	/* Does not need pinctrl properties */
	};

	i2c1: i2c-bus@80 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x80 0x40>;
	compatible = "aspeed,ast2400-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <1>;
	interrupt-parent = <&i2c_ic>;
	status = "disabled";
	/* Does not need pinctrl properties */
	};

	i2c2: i2c-bus@c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0xc0 0x40>;
	compatible = "aspeed,ast2400-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <2>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3_default>;
	status = "disabled";
	};

	i2c3: i2c-bus@100 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x100 0x40>;
	compatible = "aspeed,ast2400-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <3>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4_default>;
	status = "disabled";
	};

	i2c4: i2c-bus@140 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x140 0x40>;
	compatible = "aspeed,ast2400-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <4>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c5_default>;
	status = "disabled";
	};

	i2c5: i2c-bus@180 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x180 0x40>;
	compatible = "aspeed,ast2400-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <5>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c6_default>;
	status = "disabled";
	};

	i2c6: i2c-bus@1c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x1c0 0x40>;
	compatible = "aspeed,ast2400-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <6>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c7_default>;
	status = "disabled";
	};

	i2c7: i2c-bus@300 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x300 0x40>;
	compatible = "aspeed,ast2400-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <7>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c8_default>;
	status = "disabled";
	};

	i2c8: i2c-bus@340 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x340 0x40>;
	compatible = "aspeed,ast2400-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <8>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c9_default>;
	status = "disabled";
	};

	i2c9: i2c-bus@380 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x380 0x40>;
	compatible = "aspeed,ast2400-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <9>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c10_default>;
	status = "disabled";
	};

	i2c10: i2c-bus@3c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x3c0 0x40>;
	compatible = "aspeed,ast2400-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <10>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c11_default>;
	status = "disabled";
	};

	i2c11: i2c-bus@400 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x400 0x40>;
	compatible = "aspeed,ast2400-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <11>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c12_default>;
	status = "disabled";
	};

	i2c12: i2c-bus@440 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x440 0x40>;
	compatible = "aspeed,ast2400-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <12>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c13_default>;
	status = "disabled";
	};

	i2c13: i2c-bus@480 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x480 0x40>;
	compatible = "aspeed,ast2400-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <13>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c14_default>;
	status = "disabled";
	};
	};

	&pinctrl {
	pinctrl_acpi_default: acpi_default {
	function = "ACPI";
	groups = "ACPI";
	};

	pinctrl_adc0_default: adc0_default {
	function = "ADC0";
	groups = "ADC0";
	};

	pinctrl_adc1_default: adc1_default {
	function = "ADC1";
	groups = "ADC1";
	};

	pinctrl_adc10_default: adc10_default {
	function = "ADC10";
	groups = "ADC10";
	};

	pinctrl_adc11_default: adc11_default {
	function = "ADC11";
	groups = "ADC11";
	};

	pinctrl_adc12_default: adc12_default {
	function = "ADC12";
	groups = "ADC12";
	};

	pinctrl_adc13_default: adc13_default {
	function = "ADC13";
	groups = "ADC13";
	};

	pinctrl_adc14_default: adc14_default {
	function = "ADC14";
	groups = "ADC14";
	};

	pinctrl_adc15_default: adc15_default {
	function = "ADC15";
	groups = "ADC15";
	};

	pinctrl_adc2_default: adc2_default {
	function = "ADC2";
	groups = "ADC2";
	};

	pinctrl_adc3_default: adc3_default {
	function = "ADC3";
	groups = "ADC3";
	};

	pinctrl_adc4_default: adc4_default {
	function = "ADC4";
	groups = "ADC4";
	};

	pinctrl_adc5_default: adc5_default {
	function = "ADC5";
	groups = "ADC5";
	};

	pinctrl_adc6_default: adc6_default {
	function = "ADC6";
	groups = "ADC6";
	};

	pinctrl_adc7_default: adc7_default {
	function = "ADC7";
	groups = "ADC7";
	};

	pinctrl_adc8_default: adc8_default {
	function = "ADC8";
	groups = "ADC8";
	};

	pinctrl_adc9_default: adc9_default {
	function = "ADC9";
	groups = "ADC9";
	};

	pinctrl_bmcint_default: bmcint_default {
	function = "BMCINT";
	groups = "BMCINT";
	};

	pinctrl_ddcclk_default: ddcclk_default {
	function = "DDCCLK";
	groups = "DDCCLK";
	};

	pinctrl_ddcdat_default: ddcdat_default {
	function = "DDCDAT";
	groups = "DDCDAT";
	};

	pinctrl_extrst_default: extrst_default {
	function = "EXTRST";
	groups = "EXTRST";
	};

	pinctrl_flack_default: flack_default {
	function = "FLACK";
	groups = "FLACK";
	};

	pinctrl_flbusy_default: flbusy_default {
	function = "FLBUSY";
	groups = "FLBUSY";
	};

	pinctrl_flwp_default: flwp_default {
	function = "FLWP";
	groups = "FLWP";
	};

	pinctrl_gpid_default: gpid_default {
	function = "GPID";
	groups = "GPID";
	};

	pinctrl_gpid0_default: gpid0_default {
	function = "GPID0";
	groups = "GPID0";
	};

	pinctrl_gpid2_default: gpid2_default {
	function = "GPID2";
	groups = "GPID2";
	};

	pinctrl_gpid4_default: gpid4_default {
	function = "GPID4";
	groups = "GPID4";
	};

	pinctrl_gpid6_default: gpid6_default {
	function = "GPID6";
	groups = "GPID6";
	};

	pinctrl_gpie0_default: gpie0_default {
	function = "GPIE0";
	groups = "GPIE0";
	};

	pinctrl_gpie2_default: gpie2_default {
	function = "GPIE2";
	groups = "GPIE2";
	};

	pinctrl_gpie4_default: gpie4_default {
	function = "GPIE4";
	groups = "GPIE4";
	};

	pinctrl_gpie6_default: gpie6_default {
	function = "GPIE6";
	groups = "GPIE6";
	};

	pinctrl_i2c10_default: i2c10_default {
	function = "I2C10";
	groups = "I2C10";
	};

	pinctrl_i2c11_default: i2c11_default {
	function = "I2C11";
	groups = "I2C11";
	};

	pinctrl_i2c12_default: i2c12_default {
	function = "I2C12";
	groups = "I2C12";
	};

	pinctrl_i2c13_default: i2c13_default {
	function = "I2C13";
	groups = "I2C13";
	};

	pinctrl_i2c14_default: i2c14_default {
	function = "I2C14";
	groups = "I2C14";
	};

	pinctrl_i2c3_default: i2c3_default {
	function = "I2C3";
	groups = "I2C3";
	};

	pinctrl_i2c4_default: i2c4_default {
	function = "I2C4";
	groups = "I2C4";
	};

	pinctrl_i2c5_default: i2c5_default {
	function = "I2C5";
	groups = "I2C5";
	};

	pinctrl_i2c6_default: i2c6_default {
	function = "I2C6";
	groups = "I2C6";
	};

	pinctrl_i2c7_default: i2c7_default {
	function = "I2C7";
	groups = "I2C7";
	};

	pinctrl_i2c8_default: i2c8_default {
	function = "I2C8";
	groups = "I2C8";
	};

	pinctrl_i2c9_default: i2c9_default {
	function = "I2C9";
	groups = "I2C9";
	};

	pinctrl_lpcpd_default: lpcpd_default {
	function = "LPCPD";
	groups = "LPCPD";
	};

	pinctrl_lpcpme_default: lpcpme_default {
	function = "LPCPME";
	groups = "LPCPME";
	};

	pinctrl_lpcrst_default: lpcrst_default {
	function = "LPCRST";
	groups = "LPCRST";
	};

	pinctrl_lpcsmi_default: lpcsmi_default {
	function = "LPCSMI";
	groups = "LPCSMI";
	};

	pinctrl_mac1link_default: mac1link_default {
	function = "MAC1LINK";
	groups = "MAC1LINK";
	};

	pinctrl_mac2link_default: mac2link_default {
	function = "MAC2LINK";
	groups = "MAC2LINK";
	};

	pinctrl_mdio1_default: mdio1_default {
	function = "MDIO1";
	groups = "MDIO1";
	};

	pinctrl_mdio2_default: mdio2_default {
	function = "MDIO2";
	groups = "MDIO2";
	};

	pinctrl_ncts1_default: ncts1_default {
	function = "NCTS1";
	groups = "NCTS1";
	};

	pinctrl_ncts2_default: ncts2_default {
	function = "NCTS2";
	groups = "NCTS2";
	};

	pinctrl_ncts3_default: ncts3_default {
	function = "NCTS3";
	groups = "NCTS3";
	};

	pinctrl_ncts4_default: ncts4_default {
	function = "NCTS4";
	groups = "NCTS4";
	};

	pinctrl_ndcd1_default: ndcd1_default {
	function = "NDCD1";
	groups = "NDCD1";
	};

	pinctrl_ndcd2_default: ndcd2_default {
	function = "NDCD2";
	groups = "NDCD2";
	};

	pinctrl_ndcd3_default: ndcd3_default {
	function = "NDCD3";
	groups = "NDCD3";
	};

	pinctrl_ndcd4_default: ndcd4_default {
	function = "NDCD4";
	groups = "NDCD4";
	};

	pinctrl_ndsr1_default: ndsr1_default {
	function = "NDSR1";
	groups = "NDSR1";
	};

	pinctrl_ndsr2_default: ndsr2_default {
	function = "NDSR2";
	groups = "NDSR2";
	};

	pinctrl_ndsr3_default: ndsr3_default {
	function = "NDSR3";
	groups = "NDSR3";
	};

	pinctrl_ndsr4_default: ndsr4_default {
	function = "NDSR4";
	groups = "NDSR4";
	};

	pinctrl_ndtr1_default: ndtr1_default {
	function = "NDTR1";
	groups = "NDTR1";
	};

	pinctrl_ndtr2_default: ndtr2_default {
	function = "NDTR2";
	groups = "NDTR2";
	};

	pinctrl_ndtr3_default: ndtr3_default {
	function = "NDTR3";
	groups = "NDTR3";
	};

	pinctrl_ndtr4_default: ndtr4_default {
	function = "NDTR4";
	groups = "NDTR4";
	};

	pinctrl_ndts4_default: ndts4_default {
	function = "NDTS4";
	groups = "NDTS4";
	};

	pinctrl_nri1_default: nri1_default {
	function = "NRI1";
	groups = "NRI1";
	};

	pinctrl_nri2_default: nri2_default {
	function = "NRI2";
	groups = "NRI2";
	};

	pinctrl_nri3_default: nri3_default {
	function = "NRI3";
	groups = "NRI3";
	};

	pinctrl_nri4_default: nri4_default {
	function = "NRI4";
	groups = "NRI4";
	};

	pinctrl_nrts1_default: nrts1_default {
	function = "NRTS1";
	groups = "NRTS1";
	};

	pinctrl_nrts2_default: nrts2_default {
	function = "NRTS2";
	groups = "NRTS2";
	};

	pinctrl_nrts3_default: nrts3_default {
	function = "NRTS3";
	groups = "NRTS3";
	};

	pinctrl_oscclk_default: oscclk_default {
	function = "OSCCLK";
	groups = "OSCCLK";
	};

	pinctrl_pwm0_default: pwm0_default {
	function = "PWM0";
	groups = "PWM0";
	};

	pinctrl_pwm1_default: pwm1_default {
	function = "PWM1";
	groups = "PWM1";
	};

	pinctrl_pwm2_default: pwm2_default {
	function = "PWM2";
	groups = "PWM2";
	};

	pinctrl_pwm3_default: pwm3_default {
	function = "PWM3";
	groups = "PWM3";
	};

	pinctrl_pwm4_default: pwm4_default {
	function = "PWM4";
	groups = "PWM4";
	};

	pinctrl_pwm5_default: pwm5_default {
	function = "PWM5";
	groups = "PWM5";
	};

	pinctrl_pwm6_default: pwm6_default {
	function = "PWM6";
	groups = "PWM6";
	};

	pinctrl_pwm7_default: pwm7_default {
	function = "PWM7";
	groups = "PWM7";
	};

	pinctrl_rgmii1_default: rgmii1_default {
	function = "RGMII1";
	groups = "RGMII1";
	};

	pinctrl_rgmii2_default: rgmii2_default {
	function = "RGMII2";
	groups = "RGMII2";
	};

	pinctrl_rmii1_default: rmii1_default {
	function = "RMII1";
	groups = "RMII1";
	};

	pinctrl_rmii2_default: rmii2_default {
	function = "RMII2";
	groups = "RMII2";
	};

	pinctrl_rom16_default: rom16_default {
	function = "ROM16";
	groups = "ROM16";
	};

	pinctrl_rom8_default: rom8_default {
	function = "ROM8";
	groups = "ROM8";
	};

	pinctrl_romcs1_default: romcs1_default {
	function = "ROMCS1";
	groups = "ROMCS1";
	};

	pinctrl_romcs2_default: romcs2_default {
	function = "ROMCS2";
	groups = "ROMCS2";
	};

	pinctrl_romcs3_default: romcs3_default {
	function = "ROMCS3";
	groups = "ROMCS3";
	};

	pinctrl_romcs4_default: romcs4_default {
	function = "ROMCS4";
	groups = "ROMCS4";
	};

	pinctrl_rxd1_default: rxd1_default {
	function = "RXD1";
	groups = "RXD1";
	};

	pinctrl_rxd2_default: rxd2_default {
	function = "RXD2";
	groups = "RXD2";
	};

	pinctrl_rxd3_default: rxd3_default {
	function = "RXD3";
	groups = "RXD3";
	};

	pinctrl_rxd4_default: rxd4_default {
	function = "RXD4";
	groups = "RXD4";
	};

	pinctrl_salt1_default: salt1_default {
	function = "SALT1";
	groups = "SALT1";
	};

	pinctrl_salt2_default: salt2_default {
	function = "SALT2";
	groups = "SALT2";
	};

	pinctrl_salt3_default: salt3_default {
	function = "SALT3";
	groups = "SALT3";
	};

	pinctrl_salt4_default: salt4_default {
	function = "SALT4";
	groups = "SALT4";
	};

	pinctrl_sd1_default: sd1_default {
	function = "SD1";
	groups = "SD1";
	};

	pinctrl_sd2_default: sd2_default {
	function = "SD2";
	groups = "SD2";
	};

	pinctrl_sgpmck_default: sgpmck_default {
	function = "SGPMCK";
	groups = "SGPMCK";
	};

	pinctrl_sgpmi_default: sgpmi_default {
	function = "SGPMI";
	groups = "SGPMI";
	};

	pinctrl_sgpmld_default: sgpmld_default {
	function = "SGPMLD";
	groups = "SGPMLD";
	};

	pinctrl_sgpmo_default: sgpmo_default {
	function = "SGPMO";
	groups = "SGPMO";
	};

	pinctrl_sgpsck_default: sgpsck_default {
	function = "SGPSCK";
	groups = "SGPSCK";
	};

	pinctrl_sgpsi0_default: sgpsi0_default {
	function = "SGPSI0";
	groups = "SGPSI0";
	};

	pinctrl_sgpsi1_default: sgpsi1_default {
	function = "SGPSI1";
	groups = "SGPSI1";
	};

	pinctrl_sgpsld_default: sgpsld_default {
	function = "SGPSLD";
	groups = "SGPSLD";
	};

	pinctrl_sioonctrl_default: sioonctrl_default {
	function = "SIOONCTRL";
	groups = "SIOONCTRL";
	};

	pinctrl_siopbi_default: siopbi_default {
	function = "SIOPBI";
	groups = "SIOPBI";
	};

	pinctrl_siopbo_default: siopbo_default {
	function = "SIOPBO";
	groups = "SIOPBO";
	};

	pinctrl_siopwreq_default: siopwreq_default {
	function = "SIOPWREQ";
	groups = "SIOPWREQ";
	};

	pinctrl_siopwrgd_default: siopwrgd_default {
	function = "SIOPWRGD";
	groups = "SIOPWRGD";
	};

	pinctrl_sios3_default: sios3_default {
	function = "SIOS3";
	groups = "SIOS3";
	};

	pinctrl_sios5_default: sios5_default {
	function = "SIOS5";
	groups = "SIOS5";
	};

	pinctrl_siosci_default: siosci_default {
	function = "SIOSCI";
	groups = "SIOSCI";
	};

	pinctrl_spi1_default: spi1_default {
	function = "SPI1";
	groups = "SPI1";
	};

	pinctrl_spi1debug_default: spi1debug_default {
	function = "SPI1DEBUG";
	groups = "SPI1DEBUG";
	};

	pinctrl_spi1passthru_default: spi1passthru_default {
	function = "SPI1PASSTHRU";
	groups = "SPI1PASSTHRU";
	};

	pinctrl_spics1_default: spics1_default {
	function = "SPICS1";
	groups = "SPICS1";
	};

	pinctrl_timer3_default: timer3_default {
	function = "TIMER3";
	groups = "TIMER3";
	};

	pinctrl_timer4_default: timer4_default {
	function = "TIMER4";
	groups = "TIMER4";
	};

	pinctrl_timer5_default: timer5_default {
	function = "TIMER5";
	groups = "TIMER5";
	};

	pinctrl_timer6_default: timer6_default {
	function = "TIMER6";
	groups = "TIMER6";
	};

	pinctrl_timer7_default: timer7_default {
	function = "TIMER7";
	groups = "TIMER7";
	};

	pinctrl_timer8_default: timer8_default {
	function = "TIMER8";
	groups = "TIMER8";
	};

	pinctrl_txd1_default: txd1_default {
	function = "TXD1";
	groups = "TXD1";
	};

	pinctrl_txd2_default: txd2_default {
	function = "TXD2";
	groups = "TXD2";
	};

	pinctrl_txd3_default: txd3_default {
	function = "TXD3";
	groups = "TXD3";
	};

	pinctrl_txd4_default: txd4_default {
	function = "TXD4";
	groups = "TXD4";
	};

	pinctrl_uart6_default: uart6_default {
	function = "UART6";
	groups = "UART6";
	};

	pinctrl_usbcki_default: usbcki_default {
	function = "USBCKI";
	groups = "USBCKI";
	};

	pinctrl_usb2h_default: usb2h_default {
	function = "USB2H1";
	groups = "USB2H1";
	};

	pinctrl_usb2d_default: usb2d_default {
	function = "USB2D1";
	groups = "USB2D1";
	};

	pinctrl_vgabios_rom_default: vgabios_rom_default {
	function = "VGABIOS_ROM";
	groups = "VGABIOS_ROM";
	};

	pinctrl_vgahs_default: vgahs_default {
	function = "VGAHS";
	groups = "VGAHS";
	};

	pinctrl_vgavs_default: vgavs_default {
	function = "VGAVS";
	groups = "VGAVS";
	};

	pinctrl_vpi18_default: vpi18_default {
	function = "VPI18";
	groups = "VPI18";
	};

	pinctrl_vpi24_default: vpi24_default {
	function = "VPI24";
	groups = "VPI24";
	};

	pinctrl_vpi30_default: vpi30_default {
	function = "VPI30";
	groups = "VPI30";
	};

	pinctrl_vpo12_default: vpo12_default {
	function = "VPO12";
	groups = "VPO12";
	};

	pinctrl_vpo24_default: vpo24_default {
	function = "VPO24";
	groups = "VPO24";
	};

	pinctrl_wdtrst1_default: wdtrst1_default {
	function = "WDTRST1";
	groups = "WDTRST1";
	};

	pinctrl_wdtrst2_default: wdtrst2_default {
	function = "WDTRST2";
	groups = "WDTRST2";
	};
	};
	diff --git a/sys/gnu/dts/arm/aspeed-g5.dtsi b/sys/gnu/dts/arm/aspeed-g5.dtsi
	index ebec0fa8baa7..f12ec04d3cbc 100644
	--- a/sys/gnu/dts/arm/aspeed-g5.dtsi
	+++ b/sys/gnu/dts/arm/aspeed-g5.dtsi
	@@ -1,1617 +1,1619 @@
	// SPDX-License-Identifier: GPL-2.0+
	#include <dt-bindings/clock/aspeed-clock.h>

	/ {
	model = "Aspeed BMC";
	compatible = "aspeed,ast2500";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&vic>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	i2c6 = &i2c6;
	i2c7 = &i2c7;
	i2c8 = &i2c8;
	i2c9 = &i2c9;
	i2c10 = &i2c10;
	i2c11 = &i2c11;
	i2c12 = &i2c12;
	i2c13 = &i2c13;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	serial4 = &uart5;
	serial5 = &vuart;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	compatible = "arm,arm1176jzf-s";
	device_type = "cpu";
	reg = <0>;
	};
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0>;
	};

	ahb {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	fmc: spi@1e620000 {
	reg = < 0x1e620000 0xc4
	0x20000000 0x10000000 >;
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "aspeed,ast2500-fmc";
	clocks = <&syscon ASPEED_CLK_AHB>;
	status = "disabled";
	interrupts = <19>;
	flash@0 {
	reg = < 0 >;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <50000000>;
	status = "disabled";
	};
	flash@1 {
	reg = < 1 >;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <50000000>;
	status = "disabled";
	};
	flash@2 {
	reg = < 2 >;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <50000000>;
	status = "disabled";
	};
	};

	spi1: spi@1e630000 {
	reg = < 0x1e630000 0xc4
	0x30000000 0x08000000 >;
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "aspeed,ast2500-spi";
	clocks = <&syscon ASPEED_CLK_AHB>;
	status = "disabled";
	flash@0 {
	reg = < 0 >;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <50000000>;
	status = "disabled";
	};
	flash@1 {
	reg = < 1 >;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <50000000>;
	status = "disabled";
	};
	};

	spi2: spi@1e631000 {
	reg = < 0x1e631000 0xc4
	0x38000000 0x08000000 >;
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "aspeed,ast2500-spi";
	clocks = <&syscon ASPEED_CLK_AHB>;
	status = "disabled";
	flash@0 {
	reg = < 0 >;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <50000000>;
	status = "disabled";
	};
	flash@1 {
	reg = < 1 >;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <50000000>;
	status = "disabled";
	};
	};

	vic: interrupt-controller@1e6c0080 {
	compatible = "aspeed,ast2400-vic";
	interrupt-controller;
	#interrupt-cells = <1>;
	valid-sources = <0xfefff7ff 0x0807ffff>;
	reg = <0x1e6c0080 0x80>;
	};

	cvic: copro-interrupt-controller@1e6c2000 {
	compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
	valid-sources = <0xffffffff>;
	copro-sw-interrupts = <1>;
	reg = <0x1e6c2000 0x80>;
	};

	mac0: ethernet@1e660000 {
	compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
	reg = <0x1e660000 0x180>;
	interrupts = <2>;
	clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
	status = "disabled";
	};

	mac1: ethernet@1e680000 {
	compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
	reg = <0x1e680000 0x180>;
	interrupts = <3>;
	clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
	status = "disabled";
	};

	ehci0: usb@1e6a1000 {
	compatible = "aspeed,ast2500-ehci", "generic-ehci";
	reg = <0x1e6a1000 0x100>;
	interrupts = <5>;
	clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb2ah_default>;
	status = "disabled";
	};

	ehci1: usb@1e6a3000 {
	compatible = "aspeed,ast2500-ehci", "generic-ehci";
	reg = <0x1e6a3000 0x100>;
	interrupts = <13>;
	clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb2bh_default>;
	status = "disabled";
	};

	uhci: usb@1e6b0000 {
	compatible = "aspeed,ast2500-uhci", "generic-uhci";
	reg = <0x1e6b0000 0x100>;
	interrupts = <14>;
	#ports = <2>;
	clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
	status = "disabled";
	/*
	* No default pinmux, it will follow EHCI, use an explicit pinmux
	* override if you don't enable EHCI
	*/
	};

	vhub: usb-vhub@1e6a0000 {
	compatible = "aspeed,ast2500-usb-vhub";
	reg = <0x1e6a0000 0x300>;
	interrupts = <5>;
	clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
	+ aspeed,vhub-downstream-ports = <5>;
	+ aspeed,vhub-generic-endpoints = <15>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb2ad_default>;
	status = "disabled";
	};

	apb {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	edac: memory-controller@1e6e0000 {
	compatible = "aspeed,ast2500-sdram-edac";
	reg = <0x1e6e0000 0x174>;
	interrupts = <0>;
	status = "disabled";
	};

	syscon: syscon@1e6e2000 {
	compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
	reg = <0x1e6e2000 0x1a8>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x1e6e2000 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;

	p2a: p2a-control@2c {
	compatible = "aspeed,ast2500-p2a-ctrl";
	reg = <0x2c 0x4>;
	status = "disabled";
	};

	pinctrl: pinctrl@80 {
	compatible = "aspeed,ast2500-pinctrl";
	reg = <0x80 0x18>, <0xa0 0x10>;
	aspeed,external-nodes = <&gfx>, <&lhc>;
	};
	};

	rng: hwrng@1e6e2078 {
	compatible = "timeriomem_rng";
	reg = <0x1e6e2078 0x4>;
	period = <1>;
	quality = <100>;
	};

	gfx: display@1e6e6000 {
	compatible = "aspeed,ast2500-gfx", "syscon";
	reg = <0x1e6e6000 0x1000>;
	reg-io-width = <4>;
	clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
	resets = <&syscon ASPEED_RESET_CRT1>;
	status = "disabled";
	interrupts = <0x19>;
	};

	adc: adc@1e6e9000 {
	compatible = "aspeed,ast2500-adc";
	reg = <0x1e6e9000 0xb0>;
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_ADC>;
	#io-channel-cells = <1>;
	status = "disabled";
	};

	video: video@1e700000 {
	compatible = "aspeed,ast2500-video-engine";
	reg = <0x1e700000 0x1000>;
	clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
	<&syscon ASPEED_CLK_GATE_ECLK>;
	clock-names = "vclk", "eclk";
	interrupts = <7>;
	status = "disabled";
	};

	sram: sram@1e720000 {
	compatible = "mmio-sram";
	reg = <0x1e720000 0x9000>; // 36K
	};

	sdmmc: sd-controller@1e740000 {
	compatible = "aspeed,ast2500-sd-controller";
	reg = <0x1e740000 0x100>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x1e740000 0x10000>;
	clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
	status = "disabled";

	sdhci0: sdhci@100 {
	compatible = "aspeed,ast2500-sdhci";
	reg = <0x100 0x100>;
	interrupts = <26>;
	sdhci,auto-cmd12;
	clocks = <&syscon ASPEED_CLK_SDIO>;
	status = "disabled";
	};

	sdhci1: sdhci@200 {
	compatible = "aspeed,ast2500-sdhci";
	reg = <0x200 0x100>;
	interrupts = <26>;
	sdhci,auto-cmd12;
	clocks = <&syscon ASPEED_CLK_SDIO>;
	status = "disabled";
	};
	};

	gpio: gpio@1e780000 {
	#gpio-cells = <2>;
	gpio-controller;
	compatible = "aspeed,ast2500-gpio";
	reg = <0x1e780000 0x200>;
	interrupts = <20>;
	gpio-ranges = <&pinctrl 0 0 232>;
	clocks = <&syscon ASPEED_CLK_APB>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	sgpio: sgpio@1e780200 {
	#gpio-cells = <2>;
	compatible = "aspeed,ast2500-sgpio";
	gpio-controller;
	interrupts = <40>;
	reg = <0x1e780200 0x0100>;
	clocks = <&syscon ASPEED_CLK_APB>;
	interrupt-controller;
	ngpios = <8>;
	bus-frequency = <12000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sgpm_default>;
	status = "disabled";
	};

	rtc: rtc@1e781000 {
	compatible = "aspeed,ast2500-rtc";
	reg = <0x1e781000 0x18>;
	status = "disabled";
	};

	timer: timer@1e782000 {
	/* This timer is a Faraday FTTMR010 derivative */
	compatible = "aspeed,ast2400-timer";
	reg = <0x1e782000 0x90>;
	interrupts = <16 17 18 35 36 37 38 39>;
	clocks = <&syscon ASPEED_CLK_APB>;
	clock-names = "PCLK";
	};

	uart1: serial@1e783000 {
	compatible = "ns16550a";
	reg = <0x1e783000 0x20>;
	reg-shift = <2>;
	interrupts = <9>;
	clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
	resets = <&lpc_reset 4>;
	no-loopback-test;
	status = "disabled";
	};

	uart5: serial@1e784000 {
	compatible = "ns16550a";
	reg = <0x1e784000 0x20>;
	reg-shift = <2>;
	interrupts = <10>;
	clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
	no-loopback-test;
	status = "disabled";
	};

	wdt1: watchdog@1e785000 {
	compatible = "aspeed,ast2500-wdt";
	reg = <0x1e785000 0x20>;
	clocks = <&syscon ASPEED_CLK_APB>;
	};

	wdt2: watchdog@1e785020 {
	compatible = "aspeed,ast2500-wdt";
	reg = <0x1e785020 0x20>;
	clocks = <&syscon ASPEED_CLK_APB>;
	};

	wdt3: watchdog@1e785040 {
	compatible = "aspeed,ast2500-wdt";
	reg = <0x1e785040 0x20>;
	clocks = <&syscon ASPEED_CLK_APB>;
	status = "disabled";
	};

	pwm_tacho: pwm-tacho-controller@1e786000 {
	compatible = "aspeed,ast2500-pwm-tacho";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x1e786000 0x1000>;
	clocks = <&syscon ASPEED_CLK_24M>;
	resets = <&syscon ASPEED_RESET_PWM>;
	status = "disabled";
	};

	vuart: serial@1e787000 {
	compatible = "aspeed,ast2500-vuart";
	reg = <0x1e787000 0x40>;
	reg-shift = <2>;
	interrupts = <8>;
	clocks = <&syscon ASPEED_CLK_APB>;
	no-loopback-test;
	aspeed,sirq-polarity-sense = <&syscon 0x70 25>;
	status = "disabled";
	};

	lpc: lpc@1e789000 {
	compatible = "aspeed,ast2500-lpc", "simple-mfd";
	reg = <0x1e789000 0x1000>;

	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x1e789000 0x1000>;

	lpc_bmc: lpc-bmc@0 {
	compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon";
	reg = <0x0 0x80>;
	reg-io-width = <4>;

	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x80>;

	kcs1: kcs1@0 {
	compatible = "aspeed,ast2500-kcs-bmc";
	interrupts = <8>;
	kcs_chan = <1>;
	status = "disabled";
	};
	kcs2: kcs2@0 {
	compatible = "aspeed,ast2500-kcs-bmc";
	interrupts = <8>;
	kcs_chan = <2>;
	status = "disabled";
	};
	kcs3: kcs3@0 {
	compatible = "aspeed,ast2500-kcs-bmc";
	interrupts = <8>;
	kcs_chan = <3>;
	status = "disabled";
	};
	};

	lpc_host: lpc-host@80 {
	compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
	reg = <0x80 0x1e0>;
	reg-io-width = <4>;

	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x80 0x1e0>;

	kcs4: kcs4@0 {
	compatible = "aspeed,ast2500-kcs-bmc";
	interrupts = <8>;
	kcs_chan = <4>;
	status = "disabled";
	};

	lpc_ctrl: lpc-ctrl@0 {
	compatible = "aspeed,ast2500-lpc-ctrl";
	reg = <0x0 0x10>;
	clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
	status = "disabled";
	};

	lpc_snoop: lpc-snoop@10 {
	compatible = "aspeed,ast2500-lpc-snoop";
	reg = <0x10 0x8>;
	interrupts = <8>;
	status = "disabled";
	};

	lpc_reset: reset-controller@18 {
	compatible = "aspeed,ast2500-lpc-reset";
	reg = <0x18 0x4>;
	#reset-cells = <1>;
	};

	lhc: lhc@20 {
	compatible = "aspeed,ast2500-lhc";
	reg = <0x20 0x24 0x48 0x8>;
	};


	ibt: ibt@c0 {
	compatible = "aspeed,ast2500-ibt-bmc";
	reg = <0xc0 0x18>;
	interrupts = <8>;
	status = "disabled";
	};
	};
	};

	uart2: serial@1e78d000 {
	compatible = "ns16550a";
	reg = <0x1e78d000 0x20>;
	reg-shift = <2>;
	interrupts = <32>;
	clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
	resets = <&lpc_reset 5>;
	no-loopback-test;
	status = "disabled";
	};

	uart3: serial@1e78e000 {
	compatible = "ns16550a";
	reg = <0x1e78e000 0x20>;
	reg-shift = <2>;
	interrupts = <33>;
	clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
	resets = <&lpc_reset 6>;
	no-loopback-test;
	status = "disabled";
	};

	uart4: serial@1e78f000 {
	compatible = "ns16550a";
	reg = <0x1e78f000 0x20>;
	reg-shift = <2>;
	interrupts = <34>;
	clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
	resets = <&lpc_reset 7>;
	no-loopback-test;
	status = "disabled";
	};

	i2c: bus@1e78a000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x1e78a000 0x1000>;
	};
	};
	};
	};

	&i2c {
	i2c_ic: interrupt-controller@0 {
	#interrupt-cells = <1>;
	compatible = "aspeed,ast2500-i2c-ic";
	reg = <0x0 0x40>;
	interrupts = <12>;
	interrupt-controller;
	};

	i2c0: i2c-bus@40 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x40 0x40>;
	compatible = "aspeed,ast2500-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <0>;
	interrupt-parent = <&i2c_ic>;
	status = "disabled";
	/* Does not need pinctrl properties */
	};

	i2c1: i2c-bus@80 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x80 0x40>;
	compatible = "aspeed,ast2500-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <1>;
	interrupt-parent = <&i2c_ic>;
	status = "disabled";
	/* Does not need pinctrl properties */
	};

	i2c2: i2c-bus@c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0xc0 0x40>;
	compatible = "aspeed,ast2500-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <2>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3_default>;
	status = "disabled";
	};

	i2c3: i2c-bus@100 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x100 0x40>;
	compatible = "aspeed,ast2500-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <3>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4_default>;
	status = "disabled";
	};

	i2c4: i2c-bus@140 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x140 0x40>;
	compatible = "aspeed,ast2500-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <4>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c5_default>;
	status = "disabled";
	};

	i2c5: i2c-bus@180 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x180 0x40>;
	compatible = "aspeed,ast2500-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <5>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c6_default>;
	status = "disabled";
	};

	i2c6: i2c-bus@1c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x1c0 0x40>;
	compatible = "aspeed,ast2500-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <6>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c7_default>;
	status = "disabled";
	};

	i2c7: i2c-bus@300 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x300 0x40>;
	compatible = "aspeed,ast2500-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <7>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c8_default>;
	status = "disabled";
	};

	i2c8: i2c-bus@340 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x340 0x40>;
	compatible = "aspeed,ast2500-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <8>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c9_default>;
	status = "disabled";
	};

	i2c9: i2c-bus@380 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x380 0x40>;
	compatible = "aspeed,ast2500-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <9>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c10_default>;
	status = "disabled";
	};

	i2c10: i2c-bus@3c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x3c0 0x40>;
	compatible = "aspeed,ast2500-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <10>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c11_default>;
	status = "disabled";
	};

	i2c11: i2c-bus@400 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x400 0x40>;
	compatible = "aspeed,ast2500-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <11>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c12_default>;
	status = "disabled";
	};

	i2c12: i2c-bus@440 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x440 0x40>;
	compatible = "aspeed,ast2500-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <12>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c13_default>;
	status = "disabled";
	};

	i2c13: i2c-bus@480 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	reg = <0x480 0x40>;
	compatible = "aspeed,ast2500-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_I2C>;
	bus-frequency = <100000>;
	interrupts = <13>;
	interrupt-parent = <&i2c_ic>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c14_default>;
	status = "disabled";
	};
	};

	&pinctrl {
	pinctrl_acpi_default: acpi_default {
	function = "ACPI";
	groups = "ACPI";
	};

	pinctrl_adc0_default: adc0_default {
	function = "ADC0";
	groups = "ADC0";
	};

	pinctrl_adc1_default: adc1_default {
	function = "ADC1";
	groups = "ADC1";
	};

	pinctrl_adc10_default: adc10_default {
	function = "ADC10";
	groups = "ADC10";
	};

	pinctrl_adc11_default: adc11_default {
	function = "ADC11";
	groups = "ADC11";
	};

	pinctrl_adc12_default: adc12_default {
	function = "ADC12";
	groups = "ADC12";
	};

	pinctrl_adc13_default: adc13_default {
	function = "ADC13";
	groups = "ADC13";
	};

	pinctrl_adc14_default: adc14_default {
	function = "ADC14";
	groups = "ADC14";
	};

	pinctrl_adc15_default: adc15_default {
	function = "ADC15";
	groups = "ADC15";
	};

	pinctrl_adc2_default: adc2_default {
	function = "ADC2";
	groups = "ADC2";
	};

	pinctrl_adc3_default: adc3_default {
	function = "ADC3";
	groups = "ADC3";
	};

	pinctrl_adc4_default: adc4_default {
	function = "ADC4";
	groups = "ADC4";
	};

	pinctrl_adc5_default: adc5_default {
	function = "ADC5";
	groups = "ADC5";
	};

	pinctrl_adc6_default: adc6_default {
	function = "ADC6";
	groups = "ADC6";
	};

	pinctrl_adc7_default: adc7_default {
	function = "ADC7";
	groups = "ADC7";
	};

	pinctrl_adc8_default: adc8_default {
	function = "ADC8";
	groups = "ADC8";
	};

	pinctrl_adc9_default: adc9_default {
	function = "ADC9";
	groups = "ADC9";
	};

	pinctrl_bmcint_default: bmcint_default {
	function = "BMCINT";
	groups = "BMCINT";
	};

	pinctrl_ddcclk_default: ddcclk_default {
	function = "DDCCLK";
	groups = "DDCCLK";
	};

	pinctrl_ddcdat_default: ddcdat_default {
	function = "DDCDAT";
	groups = "DDCDAT";
	};

	pinctrl_espi_default: espi_default {
	function = "ESPI";
	groups = "ESPI";
	};

	pinctrl_fwspics1_default: fwspics1_default {
	function = "FWSPICS1";
	groups = "FWSPICS1";
	};

	pinctrl_fwspics2_default: fwspics2_default {
	function = "FWSPICS2";
	groups = "FWSPICS2";
	};

	pinctrl_gpid0_default: gpid0_default {
	function = "GPID0";
	groups = "GPID0";
	};

	pinctrl_gpid2_default: gpid2_default {
	function = "GPID2";
	groups = "GPID2";
	};

	pinctrl_gpid4_default: gpid4_default {
	function = "GPID4";
	groups = "GPID4";
	};

	pinctrl_gpid6_default: gpid6_default {
	function = "GPID6";
	groups = "GPID6";
	};

	pinctrl_gpie0_default: gpie0_default {
	function = "GPIE0";
	groups = "GPIE0";
	};

	pinctrl_gpie2_default: gpie2_default {
	function = "GPIE2";
	groups = "GPIE2";
	};

	pinctrl_gpie4_default: gpie4_default {
	function = "GPIE4";
	groups = "GPIE4";
	};

	pinctrl_gpie6_default: gpie6_default {
	function = "GPIE6";
	groups = "GPIE6";
	};

	pinctrl_i2c10_default: i2c10_default {
	function = "I2C10";
	groups = "I2C10";
	};

	pinctrl_i2c11_default: i2c11_default {
	function = "I2C11";
	groups = "I2C11";
	};

	pinctrl_i2c12_default: i2c12_default {
	function = "I2C12";
	groups = "I2C12";
	};

	pinctrl_i2c13_default: i2c13_default {
	function = "I2C13";
	groups = "I2C13";
	};

	pinctrl_i2c14_default: i2c14_default {
	function = "I2C14";
	groups = "I2C14";
	};

	pinctrl_i2c3_default: i2c3_default {
	function = "I2C3";
	groups = "I2C3";
	};

	pinctrl_i2c4_default: i2c4_default {
	function = "I2C4";
	groups = "I2C4";
	};

	pinctrl_i2c5_default: i2c5_default {
	function = "I2C5";
	groups = "I2C5";
	};

	pinctrl_i2c6_default: i2c6_default {
	function = "I2C6";
	groups = "I2C6";
	};

	pinctrl_i2c7_default: i2c7_default {
	function = "I2C7";
	groups = "I2C7";
	};

	pinctrl_i2c8_default: i2c8_default {
	function = "I2C8";
	groups = "I2C8";
	};

	pinctrl_i2c9_default: i2c9_default {
	function = "I2C9";
	groups = "I2C9";
	};

	pinctrl_lad0_default: lad0_default {
	function = "LAD0";
	groups = "LAD0";
	};

	pinctrl_lad1_default: lad1_default {
	function = "LAD1";
	groups = "LAD1";
	};

	pinctrl_lad2_default: lad2_default {
	function = "LAD2";
	groups = "LAD2";
	};

	pinctrl_lad3_default: lad3_default {
	function = "LAD3";
	groups = "LAD3";
	};

	pinctrl_lclk_default: lclk_default {
	function = "LCLK";
	groups = "LCLK";
	};

	pinctrl_lframe_default: lframe_default {
	function = "LFRAME";
	groups = "LFRAME";
	};

	pinctrl_lpchc_default: lpchc_default {
	function = "LPCHC";
	groups = "LPCHC";
	};

	pinctrl_lpcpd_default: lpcpd_default {
	function = "LPCPD";
	groups = "LPCPD";
	};

	pinctrl_lpcplus_default: lpcplus_default {
	function = "LPCPLUS";
	groups = "LPCPLUS";
	};

	pinctrl_lpcpme_default: lpcpme_default {
	function = "LPCPME";
	groups = "LPCPME";
	};

	pinctrl_lpcrst_default: lpcrst_default {
	function = "LPCRST";
	groups = "LPCRST";
	};

	pinctrl_lpcsmi_default: lpcsmi_default {
	function = "LPCSMI";
	groups = "LPCSMI";
	};

	pinctrl_lsirq_default: lsirq_default {
	function = "LSIRQ";
	groups = "LSIRQ";
	};

	pinctrl_mac1link_default: mac1link_default {
	function = "MAC1LINK";
	groups = "MAC1LINK";
	};

	pinctrl_mac2link_default: mac2link_default {
	function = "MAC2LINK";
	groups = "MAC2LINK";
	};

	pinctrl_mdio1_default: mdio1_default {
	function = "MDIO1";
	groups = "MDIO1";
	};

	pinctrl_mdio2_default: mdio2_default {
	function = "MDIO2";
	groups = "MDIO2";
	};

	pinctrl_ncts1_default: ncts1_default {
	function = "NCTS1";
	groups = "NCTS1";
	};

	pinctrl_ncts2_default: ncts2_default {
	function = "NCTS2";
	groups = "NCTS2";
	};

	pinctrl_ncts3_default: ncts3_default {
	function = "NCTS3";
	groups = "NCTS3";
	};

	pinctrl_ncts4_default: ncts4_default {
	function = "NCTS4";
	groups = "NCTS4";
	};

	pinctrl_ndcd1_default: ndcd1_default {
	function = "NDCD1";
	groups = "NDCD1";
	};

	pinctrl_ndcd2_default: ndcd2_default {
	function = "NDCD2";
	groups = "NDCD2";
	};

	pinctrl_ndcd3_default: ndcd3_default {
	function = "NDCD3";
	groups = "NDCD3";
	};

	pinctrl_ndcd4_default: ndcd4_default {
	function = "NDCD4";
	groups = "NDCD4";
	};

	pinctrl_ndsr1_default: ndsr1_default {
	function = "NDSR1";
	groups = "NDSR1";
	};

	pinctrl_ndsr2_default: ndsr2_default {
	function = "NDSR2";
	groups = "NDSR2";
	};

	pinctrl_ndsr3_default: ndsr3_default {
	function = "NDSR3";
	groups = "NDSR3";
	};

	pinctrl_ndsr4_default: ndsr4_default {
	function = "NDSR4";
	groups = "NDSR4";
	};

	pinctrl_ndtr1_default: ndtr1_default {
	function = "NDTR1";
	groups = "NDTR1";
	};

	pinctrl_ndtr2_default: ndtr2_default {
	function = "NDTR2";
	groups = "NDTR2";
	};

	pinctrl_ndtr3_default: ndtr3_default {
	function = "NDTR3";
	groups = "NDTR3";
	};

	pinctrl_ndtr4_default: ndtr4_default {
	function = "NDTR4";
	groups = "NDTR4";
	};

	pinctrl_nri1_default: nri1_default {
	function = "NRI1";
	groups = "NRI1";
	};

	pinctrl_nri2_default: nri2_default {
	function = "NRI2";
	groups = "NRI2";
	};

	pinctrl_nri3_default: nri3_default {
	function = "NRI3";
	groups = "NRI3";
	};

	pinctrl_nri4_default: nri4_default {
	function = "NRI4";
	groups = "NRI4";
	};

	pinctrl_nrts1_default: nrts1_default {
	function = "NRTS1";
	groups = "NRTS1";
	};

	pinctrl_nrts2_default: nrts2_default {
	function = "NRTS2";
	groups = "NRTS2";
	};

	pinctrl_nrts3_default: nrts3_default {
	function = "NRTS3";
	groups = "NRTS3";
	};

	pinctrl_nrts4_default: nrts4_default {
	function = "NRTS4";
	groups = "NRTS4";
	};

	pinctrl_oscclk_default: oscclk_default {
	function = "OSCCLK";
	groups = "OSCCLK";
	};

	pinctrl_pewake_default: pewake_default {
	function = "PEWAKE";
	groups = "PEWAKE";
	};

	pinctrl_pnor_default: pnor_default {
	function = "PNOR";
	groups = "PNOR";
	};

	pinctrl_pwm0_default: pwm0_default {
	function = "PWM0";
	groups = "PWM0";
	};

	pinctrl_pwm1_default: pwm1_default {
	function = "PWM1";
	groups = "PWM1";
	};

	pinctrl_pwm2_default: pwm2_default {
	function = "PWM2";
	groups = "PWM2";
	};

	pinctrl_pwm3_default: pwm3_default {
	function = "PWM3";
	groups = "PWM3";
	};

	pinctrl_pwm4_default: pwm4_default {
	function = "PWM4";
	groups = "PWM4";
	};

	pinctrl_pwm5_default: pwm5_default {
	function = "PWM5";
	groups = "PWM5";
	};

	pinctrl_pwm6_default: pwm6_default {
	function = "PWM6";
	groups = "PWM6";
	};

	pinctrl_pwm7_default: pwm7_default {
	function = "PWM7";
	groups = "PWM7";
	};

	pinctrl_rgmii1_default: rgmii1_default {
	function = "RGMII1";
	groups = "RGMII1";
	};

	pinctrl_rgmii2_default: rgmii2_default {
	function = "RGMII2";
	groups = "RGMII2";
	};

	pinctrl_rmii1_default: rmii1_default {
	function = "RMII1";
	groups = "RMII1";
	};

	pinctrl_rmii2_default: rmii2_default {
	function = "RMII2";
	groups = "RMII2";
	};

	pinctrl_rxd1_default: rxd1_default {
	function = "RXD1";
	groups = "RXD1";
	};

	pinctrl_rxd2_default: rxd2_default {
	function = "RXD2";
	groups = "RXD2";
	};

	pinctrl_rxd3_default: rxd3_default {
	function = "RXD3";
	groups = "RXD3";
	};

	pinctrl_rxd4_default: rxd4_default {
	function = "RXD4";
	groups = "RXD4";
	};

	pinctrl_salt1_default: salt1_default {
	function = "SALT1";
	groups = "SALT1";
	};

	pinctrl_salt10_default: salt10_default {
	function = "SALT10";
	groups = "SALT10";
	};

	pinctrl_salt11_default: salt11_default {
	function = "SALT11";
	groups = "SALT11";
	};

	pinctrl_salt12_default: salt12_default {
	function = "SALT12";
	groups = "SALT12";
	};

	pinctrl_salt13_default: salt13_default {
	function = "SALT13";
	groups = "SALT13";
	};

	pinctrl_salt14_default: salt14_default {
	function = "SALT14";
	groups = "SALT14";
	};

	pinctrl_salt2_default: salt2_default {
	function = "SALT2";
	groups = "SALT2";
	};

	pinctrl_salt3_default: salt3_default {
	function = "SALT3";
	groups = "SALT3";
	};

	pinctrl_salt4_default: salt4_default {
	function = "SALT4";
	groups = "SALT4";
	};

	pinctrl_salt5_default: salt5_default {
	function = "SALT5";
	groups = "SALT5";
	};

	pinctrl_salt6_default: salt6_default {
	function = "SALT6";
	groups = "SALT6";
	};

	pinctrl_salt7_default: salt7_default {
	function = "SALT7";
	groups = "SALT7";
	};

	pinctrl_salt8_default: salt8_default {
	function = "SALT8";
	groups = "SALT8";
	};

	pinctrl_salt9_default: salt9_default {
	function = "SALT9";
	groups = "SALT9";
	};

	pinctrl_scl1_default: scl1_default {
	function = "SCL1";
	groups = "SCL1";
	};

	pinctrl_scl2_default: scl2_default {
	function = "SCL2";
	groups = "SCL2";
	};

	pinctrl_sd1_default: sd1_default {
	function = "SD1";
	groups = "SD1";
	};

	pinctrl_sd2_default: sd2_default {
	function = "SD2";
	groups = "SD2";
	};

	pinctrl_sda1_default: sda1_default {
	function = "SDA1";
	groups = "SDA1";
	};

	pinctrl_sda2_default: sda2_default {
	function = "SDA2";
	groups = "SDA2";
	};

	pinctrl_sgpm_default: sgpm_default {
	function = "SGPM";
	groups = "SGPM";
	};

	pinctrl_sgps1_default: sgps1_default {
	function = "SGPS1";
	groups = "SGPS1";
	};

	pinctrl_sgps2_default: sgps2_default {
	function = "SGPS2";
	groups = "SGPS2";
	};

	pinctrl_sioonctrl_default: sioonctrl_default {
	function = "SIOONCTRL";
	groups = "SIOONCTRL";
	};

	pinctrl_siopbi_default: siopbi_default {
	function = "SIOPBI";
	groups = "SIOPBI";
	};

	pinctrl_siopbo_default: siopbo_default {
	function = "SIOPBO";
	groups = "SIOPBO";
	};

	pinctrl_siopwreq_default: siopwreq_default {
	function = "SIOPWREQ";
	groups = "SIOPWREQ";
	};

	pinctrl_siopwrgd_default: siopwrgd_default {
	function = "SIOPWRGD";
	groups = "SIOPWRGD";
	};

	pinctrl_sios3_default: sios3_default {
	function = "SIOS3";
	groups = "SIOS3";
	};

	pinctrl_sios5_default: sios5_default {
	function = "SIOS5";
	groups = "SIOS5";
	};

	pinctrl_siosci_default: siosci_default {
	function = "SIOSCI";
	groups = "SIOSCI";
	};

	pinctrl_spi1_default: spi1_default {
	function = "SPI1";
	groups = "SPI1";
	};

	pinctrl_spi1cs1_default: spi1cs1_default {
	function = "SPI1CS1";
	groups = "SPI1CS1";
	};

	pinctrl_spi1debug_default: spi1debug_default {
	function = "SPI1DEBUG";
	groups = "SPI1DEBUG";
	};

	pinctrl_spi1passthru_default: spi1passthru_default {
	function = "SPI1PASSTHRU";
	groups = "SPI1PASSTHRU";
	};

	pinctrl_spi2ck_default: spi2ck_default {
	function = "SPI2CK";
	groups = "SPI2CK";
	};

	pinctrl_spi2cs0_default: spi2cs0_default {
	function = "SPI2CS0";
	groups = "SPI2CS0";
	};

	pinctrl_spi2cs1_default: spi2cs1_default {
	function = "SPI2CS1";
	groups = "SPI2CS1";
	};

	pinctrl_spi2miso_default: spi2miso_default {
	function = "SPI2MISO";
	groups = "SPI2MISO";
	};

	pinctrl_spi2mosi_default: spi2mosi_default {
	function = "SPI2MOSI";
	groups = "SPI2MOSI";
	};

	pinctrl_timer3_default: timer3_default {
	function = "TIMER3";
	groups = "TIMER3";
	};

	pinctrl_timer4_default: timer4_default {
	function = "TIMER4";
	groups = "TIMER4";
	};

	pinctrl_timer5_default: timer5_default {
	function = "TIMER5";
	groups = "TIMER5";
	};

	pinctrl_timer6_default: timer6_default {
	function = "TIMER6";
	groups = "TIMER6";
	};

	pinctrl_timer7_default: timer7_default {
	function = "TIMER7";
	groups = "TIMER7";
	};

	pinctrl_timer8_default: timer8_default {
	function = "TIMER8";
	groups = "TIMER8";
	};

	pinctrl_txd1_default: txd1_default {
	function = "TXD1";
	groups = "TXD1";
	};

	pinctrl_txd2_default: txd2_default {
	function = "TXD2";
	groups = "TXD2";
	};

	pinctrl_txd3_default: txd3_default {
	function = "TXD3";
	groups = "TXD3";
	};

	pinctrl_txd4_default: txd4_default {
	function = "TXD4";
	groups = "TXD4";
	};

	pinctrl_uart6_default: uart6_default {
	function = "UART6";
	groups = "UART6";
	};

	pinctrl_usbcki_default: usbcki_default {
	function = "USBCKI";
	groups = "USBCKI";
	};

	pinctrl_usb2ah_default: usb2ah_default {
	function = "USB2AH";
	groups = "USB2AH";
	};

	pinctrl_usb2ad_default: usb2ad_default {
	function = "USB2AD";
	groups = "USB2AD";
	};

	pinctrl_usb11bhid_default: usb11bhid_default {
	function = "USB11BHID";
	groups = "USB11BHID";
	};

	pinctrl_usb2bh_default: usb2bh_default {
	function = "USB2BH";
	groups = "USB2BH";
	};

	pinctrl_vgabiosrom_default: vgabiosrom_default {
	function = "VGABIOSROM";
	groups = "VGABIOSROM";
	};

	pinctrl_vgahs_default: vgahs_default {
	function = "VGAHS";
	groups = "VGAHS";
	};

	pinctrl_vgavs_default: vgavs_default {
	function = "VGAVS";
	groups = "VGAVS";
	};

	pinctrl_vpi24_default: vpi24_default {
	function = "VPI24";
	groups = "VPI24";
	};

	pinctrl_vpo_default: vpo_default {
	function = "VPO";
	groups = "VPO";
	};

	pinctrl_wdtrst1_default: wdtrst1_default {
	function = "WDTRST1";
	groups = "WDTRST1";
	};

	pinctrl_wdtrst2_default: wdtrst2_default {
	function = "WDTRST2";
	groups = "WDTRST2";
	};
	};
	diff --git a/sys/gnu/dts/arm/aspeed-g6-pinctrl.dtsi b/sys/gnu/dts/arm/aspeed-g6-pinctrl.dtsi
	index 045ce66ca876..7028e21bdd98 100644
	--- a/sys/gnu/dts/arm/aspeed-g6-pinctrl.dtsi
	+++ b/sys/gnu/dts/arm/aspeed-g6-pinctrl.dtsi
	@@ -1,1149 +1,1174 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	// Copyright 2019 IBM Corp.

	&pinctrl {
	pinctrl_adc0_default: adc0_default {
	function = "ADC0";
	groups = "ADC0";
	};

	pinctrl_adc1_default: adc1_default {
	function = "ADC1";
	groups = "ADC1";
	};

	pinctrl_adc10_default: adc10_default {
	function = "ADC10";
	groups = "ADC10";
	};

	pinctrl_adc11_default: adc11_default {
	function = "ADC11";
	groups = "ADC11";
	};

	pinctrl_adc12_default: adc12_default {
	function = "ADC12";
	groups = "ADC12";
	};

	pinctrl_adc13_default: adc13_default {
	function = "ADC13";
	groups = "ADC13";
	};

	pinctrl_adc14_default: adc14_default {
	function = "ADC14";
	groups = "ADC14";
	};

	pinctrl_adc15_default: adc15_default {
	function = "ADC15";
	groups = "ADC15";
	};

	pinctrl_adc2_default: adc2_default {
	function = "ADC2";
	groups = "ADC2";
	};

	pinctrl_adc3_default: adc3_default {
	function = "ADC3";
	groups = "ADC3";
	};

	pinctrl_adc4_default: adc4_default {
	function = "ADC4";
	groups = "ADC4";
	};

	pinctrl_adc5_default: adc5_default {
	function = "ADC5";
	groups = "ADC5";
	};

	pinctrl_adc6_default: adc6_default {
	function = "ADC6";
	groups = "ADC6";
	};

	pinctrl_adc7_default: adc7_default {
	function = "ADC7";
	groups = "ADC7";
	};

	pinctrl_adc8_default: adc8_default {
	function = "ADC8";
	groups = "ADC8";
	};

	pinctrl_adc9_default: adc9_default {
	function = "ADC9";
	groups = "ADC9";
	};

	pinctrl_bmcint_default: bmcint_default {
	function = "BMCINT";
	groups = "BMCINT";
	};

	pinctrl_espi_default: espi_default {
	function = "ESPI";
	groups = "ESPI";
	};

	pinctrl_espialt_default: espialt_default {
	function = "ESPIALT";
	groups = "ESPIALT";
	};

	pinctrl_fsi1_default: fsi1_default {
	function = "FSI1";
	groups = "FSI1";
	};

	pinctrl_fsi2_default: fsi2_default {
	function = "FSI2";
	groups = "FSI2";
	};

	pinctrl_fwspiabr_default: fwspiabr_default {
	function = "FWSPIABR";
	groups = "FWSPIABR";
	};

	pinctrl_fwspid_default: fwspid_default {
	function = "FWSPID";
	groups = "FWSPID";
	};

	pinctrl_fwqspid_default: fwqspid_default {
	function = "FWQSPID";
	groups = "FWQSPID";
	};

	pinctrl_fwspiwp_default: fwspiwp_default {
	function = "FWSPIWP";
	groups = "FWSPIWP";
	};

	pinctrl_gpit0_default: gpit0_default {
	function = "GPIT0";
	groups = "GPIT0";
	};

	pinctrl_gpit1_default: gpit1_default {
	function = "GPIT1";
	groups = "GPIT1";
	};

	pinctrl_gpit2_default: gpit2_default {
	function = "GPIT2";
	groups = "GPIT2";
	};

	pinctrl_gpit3_default: gpit3_default {
	function = "GPIT3";
	groups = "GPIT3";
	};

	pinctrl_gpit4_default: gpit4_default {
	function = "GPIT4";
	groups = "GPIT4";
	};

	pinctrl_gpit5_default: gpit5_default {
	function = "GPIT5";
	groups = "GPIT5";
	};

	pinctrl_gpit6_default: gpit6_default {
	function = "GPIT6";
	groups = "GPIT6";
	};

	pinctrl_gpit7_default: gpit7_default {
	function = "GPIT7";
	groups = "GPIT7";
	};

	pinctrl_gpiu0_default: gpiu0_default {
	function = "GPIU0";
	groups = "GPIU0";
	};

	pinctrl_gpiu1_default: gpiu1_default {
	function = "GPIU1";
	groups = "GPIU1";
	};

	pinctrl_gpiu2_default: gpiu2_default {
	function = "GPIU2";
	groups = "GPIU2";
	};

	pinctrl_gpiu3_default: gpiu3_default {
	function = "GPIU3";
	groups = "GPIU3";
	};

	pinctrl_gpiu4_default: gpiu4_default {
	function = "GPIU4";
	groups = "GPIU4";
	};

	pinctrl_gpiu5_default: gpiu5_default {
	function = "GPIU5";
	groups = "GPIU5";
	};

	pinctrl_gpiu6_default: gpiu6_default {
	function = "GPIU6";
	groups = "GPIU6";
	};

	pinctrl_gpiu7_default: gpiu7_default {
	function = "GPIU7";
	groups = "GPIU7";
	};

	pinctrl_hvi3c3_default: hvi3c3_default {
	function = "HVI3C3";
	groups = "HVI3C3";
	};

	pinctrl_hvi3c4_default: hvi3c4_default {
	function = "HVI3C4";
	groups = "HVI3C4";
	};

	pinctrl_i2c1_default: i2c1_default {
	function = "I2C1";
	groups = "I2C1";
	};

	pinctrl_i2c10_default: i2c10_default {
	function = "I2C10";
	groups = "I2C10";
	};

	pinctrl_i2c11_default: i2c11_default {
	function = "I2C11";
	groups = "I2C11";
	};

	pinctrl_i2c12_default: i2c12_default {
	function = "I2C12";
	groups = "I2C12";
	};

	pinctrl_i2c13_default: i2c13_default {
	function = "I2C13";
	groups = "I2C13";
	};

	pinctrl_i2c14_default: i2c14_default {
	function = "I2C14";
	groups = "I2C14";
	};

	pinctrl_i2c15_default: i2c15_default {
	function = "I2C15";
	groups = "I2C15";
	};

	pinctrl_i2c16_default: i2c16_default {
	function = "I2C16";
	groups = "I2C16";
	};

	pinctrl_i2c2_default: i2c2_default {
	function = "I2C2";
	groups = "I2C2";
	};

	pinctrl_i2c3_default: i2c3_default {
	function = "I2C3";
	groups = "I2C3";
	};

	pinctrl_i2c4_default: i2c4_default {
	function = "I2C4";
	groups = "I2C4";
	};

	pinctrl_i2c5_default: i2c5_default {
	function = "I2C5";
	groups = "I2C5";
	};

	pinctrl_i2c6_default: i2c6_default {
	function = "I2C6";
	groups = "I2C6";
	};

	pinctrl_i2c7_default: i2c7_default {
	function = "I2C7";
	groups = "I2C7";
	};

	pinctrl_i2c8_default: i2c8_default {
	function = "I2C8";
	groups = "I2C8";
	};

	pinctrl_i2c9_default: i2c9_default {
	function = "I2C9";
	groups = "I2C9";
	};

	pinctrl_i3c3_default: i3c3_default {
	function = "I3C3";
	groups = "I3C3";
	};

	pinctrl_i3c4_default: i3c4_default {
	function = "I3C4";
	groups = "I3C4";
	};

	pinctrl_i3c5_default: i3c5_default {
	function = "I3C5";
	groups = "I3C5";
	};

	pinctrl_i3c6_default: i3c6_default {
	function = "I3C6";
	groups = "I3C6";
	};

	pinctrl_jtagm_default: jtagm_default {
	function = "JTAGM";
	groups = "JTAGM";
	};

	pinctrl_lhpd_default: lhpd_default {
	function = "LHPD";
	groups = "LHPD";
	};

	pinctrl_lhsirq_default: lhsirq_default {
	function = "LHSIRQ";
	groups = "LHSIRQ";
	};

	pinctrl_lpc_default: lpc_default {
	function = "LPC";
	groups = "LPC";
	};

	pinctrl_lpchc_default: lpchc_default {
	function = "LPCHC";
	groups = "LPCHC";
	};

	pinctrl_lpcpd_default: lpcpd_default {
	function = "LPCPD";
	groups = "LPCPD";
	};

	pinctrl_lpcpme_default: lpcpme_default {
	function = "LPCPME";
	groups = "LPCPME";
	};

	pinctrl_lpcsmi_default: lpcsmi_default {
	function = "LPCSMI";
	groups = "LPCSMI";
	};

	pinctrl_lsirq_default: lsirq_default {
	function = "LSIRQ";
	groups = "LSIRQ";
	};

	pinctrl_maclink1_default: maclink1_default {
	function = "MACLINK1";
	groups = "MACLINK1";
	};

	pinctrl_maclink2_default: maclink2_default {
	function = "MACLINK2";
	groups = "MACLINK2";
	};

	pinctrl_maclink3_default: maclink3_default {
	function = "MACLINK3";
	groups = "MACLINK3";
	};

	pinctrl_maclink4_default: maclink4_default {
	function = "MACLINK4";
	groups = "MACLINK4";
	};

	pinctrl_mdio1_default: mdio1_default {
	function = "MDIO1";
	groups = "MDIO1";
	};

	pinctrl_mdio2_default: mdio2_default {
	function = "MDIO2";
	groups = "MDIO2";
	};

	pinctrl_mdio3_default: mdio3_default {
	function = "MDIO3";
	groups = "MDIO3";
	};

	pinctrl_mdio4_default: mdio4_default {
	function = "MDIO4";
	groups = "MDIO4";
	};

	pinctrl_ncts1_default: ncts1_default {
	function = "NCTS1";
	groups = "NCTS1";
	};

	pinctrl_ncts2_default: ncts2_default {
	function = "NCTS2";
	groups = "NCTS2";
	};

	pinctrl_ncts3_default: ncts3_default {
	function = "NCTS3";
	groups = "NCTS3";
	};

	pinctrl_ncts4_default: ncts4_default {
	function = "NCTS4";
	groups = "NCTS4";
	};

	pinctrl_ndcd1_default: ndcd1_default {
	function = "NDCD1";
	groups = "NDCD1";
	};

	pinctrl_ndcd2_default: ndcd2_default {
	function = "NDCD2";
	groups = "NDCD2";
	};

	pinctrl_ndcd3_default: ndcd3_default {
	function = "NDCD3";
	groups = "NDCD3";
	};

	pinctrl_ndcd4_default: ndcd4_default {
	function = "NDCD4";
	groups = "NDCD4";
	};

	pinctrl_ndsr1_default: ndsr1_default {
	function = "NDSR1";
	groups = "NDSR1";
	};

	pinctrl_ndsr2_default: ndsr2_default {
	function = "NDSR2";
	groups = "NDSR2";
	};

	pinctrl_ndsr3_default: ndsr3_default {
	function = "NDSR3";
	groups = "NDSR3";
	};

	pinctrl_ndsr4_default: ndsr4_default {
	function = "NDSR4";
	groups = "NDSR4";
	};

	pinctrl_ndtr1_default: ndtr1_default {
	function = "NDTR1";
	groups = "NDTR1";
	};

	pinctrl_ndtr2_default: ndtr2_default {
	function = "NDTR2";
	groups = "NDTR2";
	};

	pinctrl_ndtr3_default: ndtr3_default {
	function = "NDTR3";
	groups = "NDTR3";
	};

	pinctrl_ndtr4_default: ndtr4_default {
	function = "NDTR4";
	groups = "NDTR4";
	};

	pinctrl_nri1_default: nri1_default {
	function = "NRI1";
	groups = "NRI1";
	};

	pinctrl_nri2_default: nri2_default {
	function = "NRI2";
	groups = "NRI2";
	};

	pinctrl_nri3_default: nri3_default {
	function = "NRI3";
	groups = "NRI3";
	};

	pinctrl_nri4_default: nri4_default {
	function = "NRI4";
	groups = "NRI4";
	};

	pinctrl_nrts1_default: nrts1_default {
	function = "NRTS1";
	groups = "NRTS1";
	};

	pinctrl_nrts2_default: nrts2_default {
	function = "NRTS2";
	groups = "NRTS2";
	};

	pinctrl_nrts3_default: nrts3_default {
	function = "NRTS3";
	groups = "NRTS3";
	};

	pinctrl_nrts4_default: nrts4_default {
	function = "NRTS4";
	groups = "NRTS4";
	};

	pinctrl_oscclk_default: oscclk_default {
	function = "OSCCLK";
	groups = "OSCCLK";
	};

	pinctrl_pewake_default: pewake_default {
	function = "PEWAKE";
	groups = "PEWAKE";
	};

	pinctrl_pwm0_default: pwm0_default {
	function = "PWM0";
	groups = "PWM0";
	};

	pinctrl_pwm1_default: pwm1_default {
	function = "PWM1";
	groups = "PWM1";
	};

	pinctrl_pwm10g0_default: pwm10g0_default {
	function = "PWM10";
	groups = "PWM10G0";
	};

	pinctrl_pwm10g1_default: pwm10g1_default {
	function = "PWM10";
	groups = "PWM10G1";
	};

	pinctrl_pwm11g0_default: pwm11g0_default {
	function = "PWM11";
	groups = "PWM11G0";
	};

	pinctrl_pwm11g1_default: pwm11g1_default {
	function = "PWM11";
	groups = "PWM11G1";
	};

	pinctrl_pwm12g0_default: pwm12g0_default {
	function = "PWM12";
	groups = "PWM12G0";
	};

	pinctrl_pwm12g1_default: pwm12g1_default {
	function = "PWM12";
	groups = "PWM12G1";
	};

	pinctrl_pwm13g0_default: pwm13g0_default {
	function = "PWM13";
	groups = "PWM13G0";
	};

	pinctrl_pwm13g1_default: pwm13g1_default {
	function = "PWM13";
	groups = "PWM13G1";
	};

	pinctrl_pwm14g0_default: pwm14g0_default {
	function = "PWM14";
	groups = "PWM14G0";
	};

	pinctrl_pwm14g1_default: pwm14g1_default {
	function = "PWM14";
	groups = "PWM14G1";
	};

	pinctrl_pwm15g0_default: pwm15g0_default {
	function = "PWM15";
	groups = "PWM15G0";
	};

	pinctrl_pwm15g1_default: pwm15g1_default {
	function = "PWM15";
	groups = "PWM15G1";
	};

	pinctrl_pwm2_default: pwm2_default {
	function = "PWM2";
	groups = "PWM2";
	};

	pinctrl_pwm3_default: pwm3_default {
	function = "PWM3";
	groups = "PWM3";
	};

	pinctrl_pwm4_default: pwm4_default {
	function = "PWM4";
	groups = "PWM4";
	};

	pinctrl_pwm5_default: pwm5_default {
	function = "PWM5";
	groups = "PWM5";
	};

	pinctrl_pwm6_default: pwm6_default {
	function = "PWM6";
	groups = "PWM6";
	};

	pinctrl_pwm7_default: pwm7_default {
	function = "PWM7";
	groups = "PWM7";
	};

	pinctrl_pwm8g0_default: pwm8g0_default {
	function = "PWM8";
	groups = "PWM8G0";
	};

	pinctrl_pwm8g1_default: pwm8g1_default {
	function = "PWM8";
	groups = "PWM8G1";
	};

	pinctrl_pwm9g0_default: pwm9g0_default {
	function = "PWM9";
	groups = "PWM9G0";
	};

	pinctrl_pwm9g1_default: pwm9g1_default {
	function = "PWM9";
	groups = "PWM9G1";
	};

	pinctrl_qspi1_default: qspi1_default {
	function = "QSPI1";
	groups = "QSPI1";
	};

	pinctrl_qspi2_default: qspi2_default {
	function = "QSPI2";
	groups = "QSPI2";
	};

	pinctrl_rgmii1_default: rgmii1_default {
	function = "RGMII1";
	groups = "RGMII1";
	};

	pinctrl_rgmii2_default: rgmii2_default {
	function = "RGMII2";
	groups = "RGMII2";
	};

	pinctrl_rgmii3_default: rgmii3_default {
	function = "RGMII3";
	groups = "RGMII3";
	};

	pinctrl_rgmii4_default: rgmii4_default {
	function = "RGMII4";
	groups = "RGMII4";
	};

	pinctrl_rmii1_default: rmii1_default {
	function = "RMII1";
	groups = "RMII1";
	};

	pinctrl_rmii2_default: rmii2_default {
	function = "RMII2";
	groups = "RMII2";
	};

	pinctrl_rmii3_default: rmii3_default {
	function = "RMII3";
	groups = "RMII3";
	};

	pinctrl_rmii4_default: rmii4_default {
	function = "RMII4";
	groups = "RMII4";
	};

	pinctrl_rxd1_default: rxd1_default {
	function = "RXD1";
	groups = "RXD1";
	};

	pinctrl_rxd2_default: rxd2_default {
	function = "RXD2";
	groups = "RXD2";
	};

	pinctrl_rxd3_default: rxd3_default {
	function = "RXD3";
	groups = "RXD3";
	};

	pinctrl_rxd4_default: rxd4_default {
	function = "RXD4";
	groups = "RXD4";
	};

	pinctrl_salt1_default: salt1_default {
	function = "SALT1";
	groups = "SALT1";
	};

	pinctrl_salt10g0_default: salt10g0_default {
	function = "SALT10";
	groups = "SALT10G0";
	};

	pinctrl_salt10g1_default: salt10g1_default {
	function = "SALT10";
	groups = "SALT10G1";
	};

	pinctrl_salt11g0_default: salt11g0_default {
	function = "SALT11";
	groups = "SALT11G0";
	};

	pinctrl_salt11g1_default: salt11g1_default {
	function = "SALT11";
	groups = "SALT11G1";
	};

	pinctrl_salt12g0_default: salt12g0_default {
	function = "SALT12";
	groups = "SALT12G0";
	};

	pinctrl_salt12g1_default: salt12g1_default {
	function = "SALT12";
	groups = "SALT12G1";
	};

	pinctrl_salt13g0_default: salt13g0_default {
	function = "SALT13";
	groups = "SALT13G0";
	};

	pinctrl_salt13g1_default: salt13g1_default {
	function = "SALT13";
	groups = "SALT13G1";
	};

	pinctrl_salt14g0_default: salt14g0_default {
	function = "SALT14";
	groups = "SALT14G0";
	};

	pinctrl_salt14g1_default: salt14g1_default {
	function = "SALT14";
	groups = "SALT14G1";
	};

	pinctrl_salt15g0_default: salt15g0_default {
	function = "SALT15";
	groups = "SALT15G0";
	};

	pinctrl_salt15g1_default: salt15g1_default {
	function = "SALT15";
	groups = "SALT15G1";
	};

	pinctrl_salt16g0_default: salt16g0_default {
	function = "SALT16";
	groups = "SALT16G0";
	};

	pinctrl_salt16g1_default: salt16g1_default {
	function = "SALT16";
	groups = "SALT16G1";
	};

	pinctrl_salt2_default: salt2_default {
	function = "SALT2";
	groups = "SALT2";
	};

	pinctrl_salt3_default: salt3_default {
	function = "SALT3";
	groups = "SALT3";
	};

	pinctrl_salt4_default: salt4_default {
	function = "SALT4";
	groups = "SALT4";
	};

	pinctrl_salt5_default: salt5_default {
	function = "SALT5";
	groups = "SALT5";
	};

	pinctrl_salt6_default: salt6_default {
	function = "SALT6";
	groups = "SALT6";
	};

	pinctrl_salt7_default: salt7_default {
	function = "SALT7";
	groups = "SALT7";
	};

	pinctrl_salt8_default: salt8_default {
	function = "SALT8";
	groups = "SALT8";
	};

	pinctrl_salt9g0_default: salt9g0_default {
	function = "SALT9";
	groups = "SALT9G0";
	};

	pinctrl_salt9g1_default: salt9g1_default {
	function = "SALT9";
	groups = "SALT9G1";
	};

	pinctrl_sd1_default: sd1_default {
	function = "SD1";
	groups = "SD1";
	};

	pinctrl_sd2_default: sd2_default {
	function = "SD2";
	groups = "SD2";
	};

	pinctrl_emmc_default: emmc_default {
	function = "EMMC";
	groups = "EMMCG4";
	};

	pinctrl_sgpm1_default: sgpm1_default {
	function = "SGPM1";
	groups = "SGPM1";
	};

	pinctrl_sgps1_default: sgps1_default {
	function = "SGPS1";
	groups = "SGPS1";
	};

	pinctrl_sioonctrl_default: sioonctrl_default {
	function = "SIOONCTRL";
	groups = "SIOONCTRL";
	};

	pinctrl_siopbi_default: siopbi_default {
	function = "SIOPBI";
	groups = "SIOPBI";
	};

	pinctrl_siopbo_default: siopbo_default {
	function = "SIOPBO";
	groups = "SIOPBO";
	};

	pinctrl_siopwreq_default: siopwreq_default {
	function = "SIOPWREQ";
	groups = "SIOPWREQ";
	};

	pinctrl_siopwrgd_default: siopwrgd_default {
	function = "SIOPWRGD";
	groups = "SIOPWRGD";
	};

	pinctrl_sios3_default: sios3_default {
	function = "SIOS3";
	groups = "SIOS3";
	};

	pinctrl_sios5_default: sios5_default {
	function = "SIOS5";
	groups = "SIOS5";
	};

	pinctrl_siosci_default: siosci_default {
	function = "SIOSCI";
	groups = "SIOSCI";
	};

	pinctrl_spi1_default: spi1_default {
	function = "SPI1";
	groups = "SPI1";
	};

	pinctrl_spi1abr_default: spi1abr_default {
	function = "SPI1ABR";
	groups = "SPI1ABR";
	};

	pinctrl_spi1cs1_default: spi1cs1_default {
	function = "SPI1CS1";
	groups = "SPI1CS1";
	};

	pinctrl_spi1wp_default: spi1wp_default {
	function = "SPI1WP";
	groups = "SPI1WP";
	};

	pinctrl_spi2_default: spi2_default {
	function = "SPI2";
	groups = "SPI2";
	};

	pinctrl_spi2cs1_default: spi2cs1_default {
	function = "SPI2CS1";
	groups = "SPI2CS1";
	};

	pinctrl_spi2cs2_default: spi2cs2_default {
	function = "SPI2CS2";
	groups = "SPI2CS2";
	};

	pinctrl_tach0_default: tach0_default {
	function = "TACH0";
	groups = "TACH0";
	};

	pinctrl_tach1_default: tach1_default {
	function = "TACH1";
	groups = "TACH1";
	};

	pinctrl_tach10_default: tach10_default {
	function = "TACH10";
	groups = "TACH10";
	};

	pinctrl_tach11_default: tach11_default {
	function = "TACH11";
	groups = "TACH11";
	};

	pinctrl_tach12_default: tach12_default {
	function = "TACH12";
	groups = "TACH12";
	};

	pinctrl_tach13_default: tach13_default {
	function = "TACH13";
	groups = "TACH13";
	};

	pinctrl_tach14_default: tach14_default {
	function = "TACH14";
	groups = "TACH14";
	};

	pinctrl_tach15_default: tach15_default {
	function = "TACH15";
	groups = "TACH15";
	};

	pinctrl_tach2_default: tach2_default {
	function = "TACH2";
	groups = "TACH2";
	};

	pinctrl_tach3_default: tach3_default {
	function = "TACH3";
	groups = "TACH3";
	};

	pinctrl_tach4_default: tach4_default {
	function = "TACH4";
	groups = "TACH4";
	};

	pinctrl_tach5_default: tach5_default {
	function = "TACH5";
	groups = "TACH5";
	};

	pinctrl_tach6_default: tach6_default {
	function = "TACH6";
	groups = "TACH6";
	};

	pinctrl_tach7_default: tach7_default {
	function = "TACH7";
	groups = "TACH7";
	};

	pinctrl_tach8_default: tach8_default {
	function = "TACH8";
	groups = "TACH8";
	};

	pinctrl_tach9_default: tach9_default {
	function = "TACH9";
	groups = "TACH9";
	};

	pinctrl_thru0_default: thru0_default {
	function = "THRU0";
	groups = "THRU0";
	};

	pinctrl_thru1_default: thru1_default {
	function = "THRU1";
	groups = "THRU1";
	};

	pinctrl_thru2_default: thru2_default {
	function = "THRU2";
	groups = "THRU2";
	};

	pinctrl_thru3_default: thru3_default {
	function = "THRU3";
	groups = "THRU3";
	};

	pinctrl_txd1_default: txd1_default {
	function = "TXD1";
	groups = "TXD1";
	};

	pinctrl_txd2_default: txd2_default {
	function = "TXD2";
	groups = "TXD2";
	};

	pinctrl_txd3_default: txd3_default {
	function = "TXD3";
	groups = "TXD3";
	};

	pinctrl_txd4_default: txd4_default {
	function = "TXD4";
	groups = "TXD4";
	};

	pinctrl_uart10_default: uart10_default {
	function = "UART10";
	groups = "UART10";
	};

	pinctrl_uart11_default: uart11_default {
	function = "UART11";
	groups = "UART11";
	};

	pinctrl_uart12g0_default: uart12g0_default {
	function = "UART12";
	groups = "UART12G0";
	};

	pinctrl_uart12g1_default: uart12g1_default {
	function = "UART12";
	groups = "UART12G1";
	};

	pinctrl_uart13g0_default: uart13g0_default {
	function = "UART13";
	groups = "UART13G0";
	};

	pinctrl_uart13g1_default: uart13g1_default {
	function = "UART13";
	groups = "UART13G1";
	};

	pinctrl_uart6_default: uart6_default {
	function = "UART6";
	groups = "UART6";
	};

	pinctrl_uart7_default: uart7_default {
	function = "UART7";
	groups = "UART7";
	};

	pinctrl_uart8_default: uart8_default {
	function = "UART8";
	groups = "UART8";
	};

	pinctrl_uart9_default: uart9_default {
	function = "UART9";
	groups = "UART9";
	};

	+ pinctrl_usb2ah_default: usb2ah_default {
	+ function = "USB2AH";
	+ groups = "USBA";
	+ };
	+
	+ pinctrl_usb2ad_default: usb2ad_default {
	+ function = "USB2AD";
	+ groups = "USBA";
	+ };
	+
	+ pinctrl_usb2bh_default: usb2bh_default {
	+ function = "USB2BH";
	+ groups = "USBB";
	+ };
	+
	+ pinctrl_usb2bd_default: usb2bd_default {
	+ function = "USB2BD";
	+ groups = "USBB";
	+ };
	+
	+ pinctrl_usb11bhid_default: usb11bhid_default {
	+ function = "USB11BHID";
	+ groups = "USBB";
	+ };
	+
	pinctrl_vb_default: vb_default {
	function = "VB";
	groups = "VB";
	};

	pinctrl_vgahs_default: vgahs_default {
	function = "VGAHS";
	groups = "VGAHS";
	};

	pinctrl_vgavs_default: vgavs_default {
	function = "VGAVS";
	groups = "VGAVS";
	};

	pinctrl_wdtrst1_default: wdtrst1_default {
	function = "WDTRST1";
	groups = "WDTRST1";
	};

	pinctrl_wdtrst2_default: wdtrst2_default {
	function = "WDTRST2";
	groups = "WDTRST2";
	};

	pinctrl_wdtrst3_default: wdtrst3_default {
	function = "WDTRST3";
	groups = "WDTRST3";
	};

	pinctrl_wdtrst4_default: wdtrst4_default {
	function = "WDTRST4";
	groups = "WDTRST4";
	};
	};
	diff --git a/sys/gnu/dts/arm/aspeed-g6.dtsi b/sys/gnu/dts/arm/aspeed-g6.dtsi
	index 796976d275e1..0a29b3b57a9d 100644
	--- a/sys/gnu/dts/arm/aspeed-g6.dtsi
	+++ b/sys/gnu/dts/arm/aspeed-g6.dtsi
	@@ -1,843 +1,888 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	// Copyright 2019 IBM Corp.

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/ast2600-clock.h>

	/ {
	model = "Aspeed BMC";
	compatible = "aspeed,ast2600";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	i2c6 = &i2c6;
	i2c7 = &i2c7;
	i2c8 = &i2c8;
	i2c9 = &i2c9;
	i2c10 = &i2c10;
	i2c11 = &i2c11;
	i2c12 = &i2c12;
	i2c13 = &i2c13;
	i2c14 = &i2c14;
	i2c15 = &i2c15;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	serial4 = &uart5;
	serial5 = &vuart1;
	serial6 = &vuart2;
	};


	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "aspeed,ast2600-smp";

	cpu@f00 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <0xf00>;
	};

	cpu@f01 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <0xf01>;
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupt-parent = <&gic>;
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	clocks = <&syscon ASPEED_CLK_HPLL>;
	arm,cpu-registers-not-fw-configured;
	};

	ahb {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	device_type = "soc";
	ranges;

	gic: interrupt-controller@40461000 {
	compatible = "arm,cortex-a7-gic";
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	#interrupt-cells = <3>;
	interrupt-controller;
	interrupt-parent = <&gic>;
	reg = <0x40461000 0x1000>,
	<0x40462000 0x1000>,
	<0x40464000 0x2000>,
	<0x40466000 0x2000>;
	};

	fmc: spi@1e620000 {
	reg = < 0x1e620000 0xc4
	0x20000000 0x10000000 >;
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "aspeed,ast2600-fmc";
	clocks = <&syscon ASPEED_CLK_AHB>;
	status = "disabled";
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	flash@0 {
	reg = < 0 >;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <50000000>;
	status = "disabled";
	};
	flash@1 {
	reg = < 1 >;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <50000000>;
	status = "disabled";
	};
	flash@2 {
	reg = < 2 >;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <50000000>;
	status = "disabled";
	};
	};

	spi1: spi@1e630000 {
	reg = < 0x1e630000 0xc4
	0x30000000 0x10000000 >;
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "aspeed,ast2600-spi";
	clocks = <&syscon ASPEED_CLK_AHB>;
	status = "disabled";
	flash@0 {
	reg = < 0 >;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <50000000>;
	status = "disabled";
	};
	flash@1 {
	reg = < 1 >;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <50000000>;
	status = "disabled";
	};
	};

	spi2: spi@1e631000 {
	reg = < 0x1e631000 0xc4
	0x50000000 0x10000000 >;
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "aspeed,ast2600-spi";
	clocks = <&syscon ASPEED_CLK_AHB>;
	status = "disabled";
	flash@0 {
	reg = < 0 >;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <50000000>;
	status = "disabled";
	};
	flash@1 {
	reg = < 1 >;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <50000000>;
	status = "disabled";
	};
	flash@2 {
	reg = < 2 >;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <50000000>;
	status = "disabled";
	};
	};

	mdio0: mdio@1e650000 {
	compatible = "aspeed,ast2600-mdio";
	reg = <0x1e650000 0x8>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mdio1_default>;
	};

	mdio1: mdio@1e650008 {
	compatible = "aspeed,ast2600-mdio";
	reg = <0x1e650008 0x8>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mdio2_default>;
	};

	mdio2: mdio@1e650010 {
	compatible = "aspeed,ast2600-mdio";
	reg = <0x1e650010 0x8>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mdio3_default>;
	};

	mdio3: mdio@1e650018 {
	compatible = "aspeed,ast2600-mdio";
	reg = <0x1e650018 0x8>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mdio4_default>;
	};

	mac0: ftgmac@1e660000 {
	compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
	reg = <0x1e660000 0x180>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
	status = "disabled";
	};

	mac1: ftgmac@1e680000 {
	compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
	reg = <0x1e680000 0x180>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
	status = "disabled";
	};

	mac2: ftgmac@1e670000 {
	compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
	reg = <0x1e670000 0x180>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>;
	status = "disabled";
	};

	mac3: ftgmac@1e690000 {
	compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
	reg = <0x1e690000 0x180>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>;
	status = "disabled";
	};

	+ ehci0: usb@1e6a1000 {
	+ compatible = "aspeed,ast2600-ehci", "generic-ehci";
	+ reg = <0x1e6a1000 0x100>;
	+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_usb2ah_default>;
	+ status = "disabled";
	+ };
	+
	+ ehci1: usb@1e6a3000 {
	+ compatible = "aspeed,ast2600-ehci", "generic-ehci";
	+ reg = <0x1e6a3000 0x100>;
	+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_usb2bh_default>;
	+ status = "disabled";
	+ };
	+
	+ uhci: usb@1e6b0000 {
	+ compatible = "aspeed,ast2600-uhci", "generic-uhci";
	+ reg = <0x1e6b0000 0x100>;
	+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	+ #ports = <2>;
	+ clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
	+ status = "disabled";
	+ /*
	+ * No default pinmux, it will follow EHCI, use an
	+ * explicit pinmux override if EHCI is not enabled.
	+ */
	+ };
	+
	+ vhub: usb-vhub@1e6a0000 {
	+ compatible = "aspeed,ast2600-usb-vhub";
	+ reg = <0x1e6a0000 0x350>;
	+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
	+ aspeed,vhub-downstream-ports = <7>;
	+ aspeed,vhub-generic-endpoints = <21>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_usb2ad_default>;
	+ status = "disabled";
	+ };
	+
	apb {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	syscon: syscon@1e6e2000 {
	compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd";
	reg = <0x1e6e2000 0x1000>;
	ranges = <0 0x1e6e2000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	#clock-cells = <1>;
	#reset-cells = <1>;

	pinctrl: pinctrl {
	compatible = "aspeed,ast2600-pinctrl";
	};

	smp-memram@180 {
	compatible = "aspeed,ast2600-smpmem";
	reg = <0x180 0x40>;
	};
	};

	rng: hwrng@1e6e2524 {
	compatible = "timeriomem_rng";
	reg = <0x1e6e2524 0x4>;
	period = <1>;
	quality = <100>;
	};

	gpio0: gpio@1e780000 {
	#gpio-cells = <2>;
	gpio-controller;
	compatible = "aspeed,ast2600-gpio";
	reg = <0x1e780000 0x800>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	gpio-ranges = <&pinctrl 0 0 208>;
	ngpios = <208>;
	clocks = <&syscon ASPEED_CLK_APB2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio1: gpio@1e780800 {
	#gpio-cells = <2>;
	gpio-controller;
	compatible = "aspeed,ast2600-gpio";
	reg = <0x1e780800 0x800>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	gpio-ranges = <&pinctrl 0 208 36>;
	ngpios = <36>;
	clocks = <&syscon ASPEED_CLK_APB1>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	rtc: rtc@1e781000 {
	compatible = "aspeed,ast2600-rtc";
	reg = <0x1e781000 0x18>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	timer: timer@1e782000 {
	compatible = "aspeed,ast2600-timer";
	reg = <0x1e782000 0x90>;
	interrupts-extended = <&gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&syscon ASPEED_CLK_APB1>;
	clock-names = "PCLK";
	};

	uart1: serial@1e783000 {
	compatible = "ns16550a";
	reg = <0x1e783000 0x20>;
	reg-shift = <2>;
	reg-io-width = <4>;
	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
	resets = <&lpc_reset 4>;
	no-loopback-test;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>;
	status = "disabled";
	};

	uart5: serial@1e784000 {
	compatible = "ns16550a";
	reg = <0x1e784000 0x1000>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
	no-loopback-test;
	};

	wdt1: watchdog@1e785000 {
	compatible = "aspeed,ast2600-wdt";
	reg = <0x1e785000 0x40>;
	};

	wdt2: watchdog@1e785040 {
	compatible = "aspeed,ast2600-wdt";
	reg = <0x1e785040 0x40>;
	status = "disabled";
	};

	wdt3: watchdog@1e785080 {
	compatible = "aspeed,ast2600-wdt";
	reg = <0x1e785080 0x40>;
	status = "disabled";
	};

	wdt4: watchdog@1e7850c0 {
	compatible = "aspeed,ast2600-wdt";
	reg = <0x1e7850C0 0x40>;
	status = "disabled";
	};

	lpc: lpc@1e789000 {
	compatible = "aspeed,ast2600-lpc", "simple-mfd";
	reg = <0x1e789000 0x1000>;

	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x1e789000 0x1000>;

	lpc_bmc: lpc-bmc@0 {
	compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon";
	reg = <0x0 0x80>;
	reg-io-width = <4>;

	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x80>;

	kcs1: kcs1@0 {
	compatible = "aspeed,ast2600-kcs-bmc";
	interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	kcs_chan = <1>;
	status = "disabled";
	};
	kcs2: kcs2@0 {
	compatible = "aspeed,ast2600-kcs-bmc";
	interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
	kcs_chan = <2>;
	status = "disabled";
	};
	kcs3: kcs3@0 {
	compatible = "aspeed,ast2600-kcs-bmc";
	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
	kcs_chan = <3>;
	status = "disabled";
	};
	};

	lpc_host: lpc-host@80 {
	compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon";
	reg = <0x80 0x1e0>;
	reg-io-width = <4>;

	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x80 0x1e0>;

	kcs4: kcs4@0 {
	compatible = "aspeed,ast2600-kcs-bmc";
	interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
	kcs_chan = <4>;
	status = "disabled";
	};

	lpc_ctrl: lpc-ctrl@0 {
	compatible = "aspeed,ast2600-lpc-ctrl";
	reg = <0x0 0x80>;
	clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
	status = "disabled";
	};

	lpc_snoop: lpc-snoop@0 {
	compatible = "aspeed,ast2600-lpc-snoop";
	reg = <0x0 0x80>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	lhc: lhc@20 {
	compatible = "aspeed,ast2600-lhc";
	reg = <0x20 0x24 0x48 0x8>;
	};

	lpc_reset: reset-controller@18 {
	compatible = "aspeed,ast2600-lpc-reset";
	reg = <0x18 0x4>;
	#reset-cells = <1>;
	};

	ibt: ibt@c0 {
	compatible = "aspeed,ast2600-ibt-bmc";
	reg = <0xc0 0x18>;
	interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};
	};

	sdc: sdc@1e740000 {
	compatible = "aspeed,ast2600-sd-controller";
	reg = <0x1e740000 0x100>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x1e740000 0x10000>;
	clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
	status = "disabled";

	sdhci0: sdhci@1e740100 {
	compatible = "aspeed,ast2600-sdhci", "sdhci";
	reg = <0x100 0x100>;
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	sdhci,auto-cmd12;
	clocks = <&syscon ASPEED_CLK_SDIO>;
	status = "disabled";
	};

	sdhci1: sdhci@1e740200 {
	compatible = "aspeed,ast2600-sdhci", "sdhci";
	reg = <0x200 0x100>;
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	sdhci,auto-cmd12;
	clocks = <&syscon ASPEED_CLK_SDIO>;
	status = "disabled";
	};
	};

	emmc_controller: sdc@1e750000 {
	compatible = "aspeed,ast2600-sd-controller";
	reg = <0x1e750000 0x100>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x1e750000 0x10000>;
	clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>;
	status = "disabled";

	emmc: sdhci@1e750100 {
	compatible = "aspeed,ast2600-sdhci";
	reg = <0x100 0x100>;
	sdhci,auto-cmd12;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&syscon ASPEED_CLK_EMMC>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_emmc_default>;
	};
	};

	vuart1: serial@1e787000 {
	compatible = "aspeed,ast2500-vuart";
	reg = <0x1e787000 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&syscon ASPEED_CLK_APB1>;
	no-loopback-test;
	status = "disabled";
	};

	vuart2: serial@1e788000 {
	compatible = "aspeed,ast2500-vuart";
	reg = <0x1e788000 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&syscon ASPEED_CLK_APB1>;
	no-loopback-test;
	status = "disabled";
	};

	uart2: serial@1e78d000 {
	compatible = "ns16550a";
	reg = <0x1e78d000 0x20>;
	reg-shift = <2>;
	reg-io-width = <4>;
	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
	resets = <&lpc_reset 5>;
	no-loopback-test;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
	status = "disabled";
	};

	uart3: serial@1e78e000 {
	compatible = "ns16550a";
	reg = <0x1e78e000 0x20>;
	reg-shift = <2>;
	reg-io-width = <4>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
	resets = <&lpc_reset 6>;
	no-loopback-test;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>;
	status = "disabled";
	};

	uart4: serial@1e78f000 {
	compatible = "ns16550a";
	reg = <0x1e78f000 0x20>;
	reg-shift = <2>;
	reg-io-width = <4>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
	resets = <&lpc_reset 7>;
	no-loopback-test;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>;
	status = "disabled";
	};

	i2c: bus@1e78a000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x1e78a000 0x1000>;
	};

	fsim0: fsi@1e79b000 {
	compatible = "aspeed,ast2600-fsi-master", "fsi-master";
	reg = <0x1e79b000 0x94>;
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fsi1_default>;
	clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
	status = "disabled";
	};

	fsim1: fsi@1e79b100 {
	compatible = "aspeed,ast2600-fsi-master", "fsi-master";
	reg = <0x1e79b100 0x94>;
	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fsi2_default>;
	clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
	status = "disabled";
	};
	};
	};
	};

	#include "aspeed-g6-pinctrl.dtsi"

	&i2c {
	i2c0: i2c-bus@80 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	reg = <0x80 0x80>;
	compatible = "aspeed,ast2600-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB2>;
	resets = <&syscon ASPEED_RESET_I2C>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	bus-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1_default>;
	status = "disabled";
	};

	i2c1: i2c-bus@100 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	reg = <0x100 0x80>;
	compatible = "aspeed,ast2600-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB2>;
	resets = <&syscon ASPEED_RESET_I2C>;
	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
	bus-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2_default>;
	status = "disabled";
	};

	i2c2: i2c-bus@180 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	reg = <0x180 0x80>;
	compatible = "aspeed,ast2600-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB2>;
	resets = <&syscon ASPEED_RESET_I2C>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	bus-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3_default>;
	status = "disabled";
	};

	i2c3: i2c-bus@200 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	reg = <0x200 0x80>;
	compatible = "aspeed,ast2600-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB2>;
	resets = <&syscon ASPEED_RESET_I2C>;
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	bus-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4_default>;
	status = "disabled";
	};

	i2c4: i2c-bus@280 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	reg = <0x280 0x80>;
	compatible = "aspeed,ast2600-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB2>;
	resets = <&syscon ASPEED_RESET_I2C>;
	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	bus-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c5_default>;
	status = "disabled";
	};

	i2c5: i2c-bus@300 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	reg = <0x300 0x80>;
	compatible = "aspeed,ast2600-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB2>;
	resets = <&syscon ASPEED_RESET_I2C>;
	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
	bus-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c6_default>;
	status = "disabled";
	};

	i2c6: i2c-bus@380 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	reg = <0x380 0x80>;
	compatible = "aspeed,ast2600-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB2>;
	resets = <&syscon ASPEED_RESET_I2C>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	bus-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c7_default>;
	status = "disabled";
	};

	i2c7: i2c-bus@400 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	reg = <0x400 0x80>;
	compatible = "aspeed,ast2600-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB2>;
	resets = <&syscon ASPEED_RESET_I2C>;
	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	bus-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c8_default>;
	status = "disabled";
	};

	i2c8: i2c-bus@480 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	reg = <0x480 0x80>;
	compatible = "aspeed,ast2600-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB2>;
	resets = <&syscon ASPEED_RESET_I2C>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	bus-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c9_default>;
	status = "disabled";
	};

	i2c9: i2c-bus@500 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	reg = <0x500 0x80>;
	compatible = "aspeed,ast2600-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB2>;
	resets = <&syscon ASPEED_RESET_I2C>;
	interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	bus-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c10_default>;
	status = "disabled";
	};

	i2c10: i2c-bus@580 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	reg = <0x580 0x80>;
	compatible = "aspeed,ast2600-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB2>;
	resets = <&syscon ASPEED_RESET_I2C>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	bus-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c11_default>;
	status = "disabled";
	};

	i2c11: i2c-bus@600 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	reg = <0x600 0x80>;
	compatible = "aspeed,ast2600-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB2>;
	resets = <&syscon ASPEED_RESET_I2C>;
	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
	bus-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c12_default>;
	status = "disabled";
	};

	i2c12: i2c-bus@680 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	reg = <0x680 0x80>;
	compatible = "aspeed,ast2600-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB2>;
	resets = <&syscon ASPEED_RESET_I2C>;
	interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
	bus-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c13_default>;
	status = "disabled";
	};

	i2c13: i2c-bus@700 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	reg = <0x700 0x80>;
	compatible = "aspeed,ast2600-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB2>;
	resets = <&syscon ASPEED_RESET_I2C>;
	interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
	bus-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c14_default>;
	status = "disabled";
	};

	i2c14: i2c-bus@780 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	reg = <0x780 0x80>;
	compatible = "aspeed,ast2600-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB2>;
	resets = <&syscon ASPEED_RESET_I2C>;
	interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
	bus-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c15_default>;
	status = "disabled";
	};

	i2c15: i2c-bus@800 {
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	reg = <0x800 0x80>;
	compatible = "aspeed,ast2600-i2c-bus";
	clocks = <&syscon ASPEED_CLK_APB2>;
	resets = <&syscon ASPEED_RESET_I2C>;
	interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
	bus-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c16_default>;
	status = "disabled";
	};
	};
	diff --git a/sys/gnu/dts/arm/at91-dvk_su60_somc_lcm.dtsi b/sys/gnu/dts/arm/at91-dvk_su60_somc_lcm.dtsi
	index df0f0cc575c1..bea920b192b6 100644
	--- a/sys/gnu/dts/arm/at91-dvk_su60_somc_lcm.dtsi
	+++ b/sys/gnu/dts/arm/at91-dvk_su60_somc_lcm.dtsi
	@@ -1,90 +1,90 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* at91-dvk_su60_somc_lcm.dtsi - Device Tree file for the DVK SOM60 LCD board
	*
	* Copyright (C) 2018 Laird,
	* 2018 Ben Whitten <ben.whitten@lairdtech.com>
	*
	*/

	/ {
	backlight: backlight {
	compatible = "pwm-backlight";
	pwms = <&hlcdc_pwm 0 50000 0>;
	brightness-levels = <0 4 8 16 32 64 128 255>;
	default-brightness-level = <6>;
	status = "okay";
	};

	panel: panel {
	- compatible = "winstar,wf70gtiagdng0", "innolux,at070tn92", "simple-panel";
	+ compatible = "winstar,wf70gtiagdng0", "innolux,at070tn92";
	backlight = <&backlight>;
	power-supply = <&vcc_lcd_reg>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	panel_input: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&hlcdc_panel_output>;
	};
	};
	};

	vcc_lcd_reg: fixedregulator_lcd {
	compatible = "regulator-fixed";
	regulator-name = "VCC LCM";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-boot-on;
	regulator-always-on;
	status = "okay";
	};
	};

	&pinctrl {
	board {
	pinctrl_lcd_ctp_int: lcd_ctp_int {
	atmel,pins =
	<AT91_PIOC 28 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
	};
	};
	};

	&i2c1 {
	status = "okay";

	ft5426@38 {
	compatible = "focaltech,ft5426", "edt,edt-ft5406";
	reg = <0x38>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcd_ctp_int>;

	interrupt-parent = <&pioC>;
	interrupts = <28 IRQ_TYPE_EDGE_FALLING>;

	touchscreen-size-x = <800>;
	touchscreen-size-y = <480>;
	};
	};

	&hlcdc {
	status = "okay";

	hlcdc-display-controller {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;

	port@0 {
	hlcdc_panel_output: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&panel_input>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/at91-sam9x60ek.dts b/sys/gnu/dts/arm/at91-sam9x60ek.dts
	index 9f30132d7d7b..b484745bf2d4 100644
	--- a/sys/gnu/dts/arm/at91-sam9x60ek.dts
	+++ b/sys/gnu/dts/arm/at91-sam9x60ek.dts
	@@ -1,647 +1,652 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board
	*
	* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
	*
	* Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
	*/
	/dts-v1/;
	#include "sam9x60.dtsi"

	/ {
	model = "Microchip SAM9X60-EK";
	compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9";

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	serial1 = &uart1;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	clocks {
	slow_xtal {
	clock-frequency = <32768>;
	};

	main_xtal {
	clock-frequency = <24000000>;
	};
	};

	regulators: regulators {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	vdd_1v8: fixed-regulator-vdd_1v8@0 {
	compatible = "regulator-fixed";
	regulator-name = "VDD_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	status = "okay";
	};

	vdd_1v5: fixed-regulator-vdd_1v5@1 {
	compatible = "regulator-fixed";
	regulator-name = "VDD_1V5";
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;
	status = "okay";
	};

	vdd1_3v3: fixed-regulator-vdd1_3v3@2 {
	compatible = "regulator-fixed";
	regulator-name = "VDD1_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	status = "okay";
	};

	vdd2_3v3: regulator-fixed-vdd2_3v3@3 {
	compatible = "regulator-fixed";
	regulator-name = "VDD2_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	status = "okay";
	};
	};

	gpio_keys {
	compatible = "gpio-keys";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_key_gpio_default>;
	status = "okay";

	sw1 {
	label = "SW1";
	gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
	linux,code=<0x104>;
	wakeup-source;
	};
	};

	leds {
	compatible = "gpio-leds";
	status = "okay"; /* Conflict with pwm0. */

	red {
	label = "red";
	gpios = <&pioB 11 GPIO_ACTIVE_HIGH>;
	};

	green {
	label = "green";
	gpios = <&pioB 12 GPIO_ACTIVE_HIGH>;
	};

	blue {
	label = "blue";
	gpios = <&pioB 13 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	};
	};
	};

	&adc {
	vddana-supply = <&vdd1_3v3>;
	vref-supply = <&vdd1_3v3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
	status = "okay";
	};

	&can0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can0_rx_tx>;
	status = "disabled"; /* Conflict with dbgu. */
	};

	&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can1_rx_tx>;
	status = "okay";
	};

	&classd {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_classd_default>;
	atmel,pwm-type = "diff";
	atmel,non-overlap-time = <10>;
	status = "okay";
	};

	&dbgu {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dbgu>;
	status = "okay"; /* Conflict with can0. */
	};

	&ebi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
	status = "okay";

	nand_controller: nand-controller {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
	status = "okay";

	nand@3 {
	reg = <0x3 0x0 0x800000>;
	rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
	cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
	nand-bus-width = <8>;
	nand-ecc-mode = "hw";
	nand-ecc-strength = <8>;
	nand-ecc-step-size = <512>;
	nand-on-flash-bbt;
	label = "atmel_nand";

	partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	at91bootstrap@0 {
	label = "at91bootstrap";
	reg = <0x0 0x40000>;
	};

	uboot@40000 {
	label = "u-boot";
	reg = <0x40000 0xc0000>;
	};

	ubootenvred@100000 {
	label = "U-Boot Env Redundant";
	reg = <0x100000 0x40000>;
	};

	ubootenv@140000 {
	label = "U-Boot Env";
	reg = <0x140000 0x40000>;
	};

	dtb@180000 {
	label = "device tree";
	reg = <0x180000 0x80000>;
	};

	kernel@200000 {
	label = "kernel";
	reg = <0x200000 0x600000>;
	};

	rootfs@800000 {
	label = "rootfs";
	reg = <0x800000 0x1f800000>;
	};
	};
	};
	};
	};

	&flx0 {
	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
	status = "okay";

	i2c0: i2c@600 {
	compatible = "microchip,sam9x60-i2c";
	reg = <0x600 0x200>;
	interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flx0_default>;
	atmel,fifo-size = <16>;
	i2c-analog-filter;
	i2c-digital-filter;
	i2c-digital-filter-width-ns = <35>;
	status = "okay";

	eeprom@53 {
	compatible = "atmel,24c32";
	reg = <0x53>;
	pagesize = <16>;
	size = <128>;
	status = "okay";
	};
	};
	};

	&flx4 {
	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
	status = "disabled";

	spi0: spi@400 {
	compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
	reg = <0x400 0x200>;
	interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
	clock-names = "spi_clk";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flx4_default>;
	atmel,fifo-size = <16>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};
	};

	&flx5 {
	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
	status = "okay";

	uart1: serial@200 {
	compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
	reg = <0x200 0x200>;
	interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(10))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(11))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
	clock-names = "usart";
	pinctrl-0 = <&pinctrl_flx5_default>;
	pinctrl-names = "default";
	atmel,use-dma-rx;
	atmel,use-dma-tx;
	status = "okay";
	};
	};

	&flx6 {
	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
	status = "okay";

	i2c1: i2c@600 {
	compatible = "microchip,sam9x60-i2c";
	reg = <0x600 0x200>;
	interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flx6_default>;
	atmel,fifo-size = <16>;
	i2c-analog-filter;
	i2c-digital-filter;
	i2c-digital-filter-width-ns = <35>;
	status = "okay";

	gpio_exp: mcp23008@20 {
	compatible = "microchip,mcp23008";
	reg = <0x20>;
	};
	};
	};

	&i2s {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2s_default>;
	#sound-dai-cells = <0>;
	status = "disabled"; /* Conflict with QSPI. */
	};

	&macb0 {
	phy-mode = "rmii";
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_macb0_rmii>;
	status = "okay";

	ethernet-phy@0 {
	reg = <0x0>;
	};
	};

	&pinctrl {
	atmel,mux-mask = <
	/* A B C */
	0xFFFFFE7F 0xC0E0397F 0xEF00019D /* pioA */
	0x03FFFFFF 0x02FC7E68 0x00780000 /* pioB */
	0xffffffff 0xF83FFFFF 0xB800F3FC /* pioC */
	0x003FFFFF 0x003F8000 0x00000000 /* pioD */
	>;

	adc {
	pinctrl_adc_default: adc_default {
	atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_adtrg_default: adtrg_default {
	atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
	};
	};

	dbgu {
	pinctrl_dbgu: dbgu-0 {
	atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
	AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};
	};

	i2s {
	pinctrl_i2s_default: i2s {
	atmel,pins =
	<AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SCK */
	AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SWS */
	AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SDIN */
	AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SDOUT */
	AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* I2SMCK */
	};
	};

	qspi {
	pinctrl_qspi: qspi {
	atmel,pins =
	<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
	AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
	AT91_PIOB 21 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP \| AT91_PINCTRL_SLEWRATE_DIS)
	AT91_PIOB 22 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP \| AT91_PINCTRL_SLEWRATE_DIS)
	AT91_PIOB 23 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP \| AT91_PINCTRL_SLEWRATE_DIS)
	AT91_PIOB 24 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP \| AT91_PINCTRL_SLEWRATE_DIS)>;
	};
	};

	nand {
	pinctrl_nand_oe_we: nand-oe-we-0 {
	atmel,pins =
	<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE \| AT91_PINCTRL_SLEWRATE_DIS)
	AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE \| AT91_PINCTRL_SLEWRATE_DIS)>;
	};

	pinctrl_nand_rb: nand-rb-0 {
	atmel,pins =
	<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
	};

	pinctrl_nand_cs: nand-cs-0 {
	atmel,pins =
	<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
	};
	};

	ebi {
	pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
	atmel,pins =
	<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE \| AT91_PINCTRL_SLEWRATE_DIS)
	AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE \| AT91_PINCTRL_SLEWRATE_DIS)
	AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE \| AT91_PINCTRL_SLEWRATE_DIS)
	AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE \| AT91_PINCTRL_SLEWRATE_DIS)
	AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE \| AT91_PINCTRL_SLEWRATE_DIS)
	AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE \| AT91_PINCTRL_SLEWRATE_DIS)
	AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE \| AT91_PINCTRL_SLEWRATE_DIS)
	AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE \| AT91_PINCTRL_SLEWRATE_DIS)>;
	};

	pinctrl_ebi_data_0_15: ebi-data-msb-0 {
	atmel,pins =
	<AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_addr_nand: ebi-addr-0 {
	atmel,pins =
	<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE \| AT91_PINCTRL_SLEWRATE_DIS)
	AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE \| AT91_PINCTRL_SLEWRATE_DIS)>;
	};
	};

	flexcom {
	pinctrl_flx0_default: flx0_twi {
	atmel,pins =
	<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
	AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
	};

	pinctrl_flx4_default: flx4_spi {
	atmel,pins =
	<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_flx5_default: flx_uart {
	atmel,pins =
	<AT91_PIOA 7 AT91_PERIPH_C AT91_PINCTRL_NONE
	AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE
	AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE
	AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
	};

	pinctrl_flx6_default: flx6_twi {
	atmel,pins =
	<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
	AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
	};
	};

	classd {
	pinctrl_classd_default: classd {
	atmel,pins =
	<AT91_PIOA 24 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
	AT91_PIOA 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
	AT91_PIOA 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
	AT91_PIOA 27 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
	};
	};

	can0 {
	pinctrl_can0_rx_tx: can0_rx_tx {
	atmel,pins =
	<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX0 */
	AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANTX0 */
	AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN /* Enable CAN0 mux */
	AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>; /* Enable CAN Transceivers */
	};
	};

	can1 {
	pinctrl_can1_rx_tx: can1_rx_tx {
	atmel,pins =
	<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX1 RXD1 */
	AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANTX1 TXD1 */
	AT91_PIOD 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN /* Enable CAN1 mux */
	AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>; /* Enable CAN Transceivers */
	};
	};

	macb0 {
	pinctrl_macb0_rmii: macb0_rmii-0 {
	atmel,pins =
	<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
	AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
	AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
	AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
	AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
	AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
	AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
	AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
	AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
	AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
	};
	};

	pwm0 {
	pinctrl_pwm0_0: pwm0_0 {
	atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
	};

	pinctrl_pwm0_1: pwm0_1 {
	atmel,pins = <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
	};

	pinctrl_pwm0_2: pwm0_2 {
	atmel,pins = <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
	};

	pinctrl_pwm0_3: pwm0_3 {
	atmel,pins = <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
	};
	};

	sdmmc0 {
	pinctrl_sdmmc0_default: sdmmc0 {
	atmel,pins =
	<AT91_PIOA 17 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA17 CK periph A with pullup */
	AT91_PIOA 16 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP \| AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA16 CMD periph A with pullup */
	AT91_PIOA 15 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP \| AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA15 DAT0 periph A */
	AT91_PIOA 18 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP \| AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA18 DAT1 periph A with pullup */
	AT91_PIOA 19 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP \| AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA19 DAT2 periph A with pullup */
	AT91_PIOA 20 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP \| AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA20 DAT3 periph A with pullup */
	};
	};

	gpio_keys {
	pinctrl_key_gpio_default: pinctrl_key_gpio {
	atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
	};
	};
	}; /* pinctrl */

	&pmc {
	atmel,osc-bypass;
	};

	&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2 &pinctrl_pwm0_3>;
	status = "disabled"; /* Conflict with leds. */
	};

	&sdmmc0 {
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sdmmc0_default>;
	status = "okay";
	cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
	disable-wp;
	};

	&qspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi>;
	status = "okay"; /* Conflict with i2s. */

	flash@0 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <80000000>;
	m25p,fast-read;

	at91bootstrap@0 {
	label = "qspi: at91bootstrap";
	reg = <0x0 0x40000>;
	};

	bootloader@40000 {
	label = "qspi: bootloader";
	reg = <0x40000 0xc0000>;
	};

	bootloaderenvred@100000 {
	label = "qspi: bootloader env redundant";
	reg = <0x100000 0x40000>;
	};

	bootloaderenv@140000 {
	label = "qspi: bootloader env";
	reg = <0x140000 0x40000>;
	};

	dtb@180000 {
	label = "qspi: device tree";
	reg = <0x180000 0x80000>;
	};

	kernel@200000 {
	label = "qspi: kernel";
	reg = <0x200000 0x600000>;
	};
	};
	};

	&shutdown_controller {
	atmel,shdwc-debouncer = <976>;
	status = "okay";

	input@0 {
	reg = <0>;
	};
	};

	&tcb0 {
	timer0: timer@0 {
	compatible = "atmel,tcb-timer";
	reg = <0>;
	};

	timer1: timer@1 {
	compatible = "atmel,tcb-timer";
	reg = <1>;
	};
	};

	&usb1 {
	num-ports = <3>;
	atmel,vbus-gpio = <0
	&pioD 15 GPIO_ACTIVE_HIGH
	&pioD 16 GPIO_ACTIVE_HIGH>;
	status = "okay";
	};

	&usb2 {
	status = "okay";
	};
	+
	+&watchdog {
	+ status = "okay";
	+};
	+
	diff --git a/sys/gnu/dts/arm/at91-sama5d27_wlsom1_ek.dts b/sys/gnu/dts/arm/at91-sama5d27_wlsom1_ek.dts
	index 0b9fa2942dff..6b8461278950 100644
	--- a/sys/gnu/dts/arm/at91-sama5d27_wlsom1_ek.dts
	+++ b/sys/gnu/dts/arm/at91-sama5d27_wlsom1_ek.dts
	@@ -1,270 +1,282 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* at91-sama5d27_wlsom1_ek.dts - Device Tree file for SAMA5D27 WLSOM1 EK
	*
	* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
	*
	* Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
	*/
	/dts-v1/;
	#include "at91-sama5d27_wlsom1.dtsi"

	/ {
	model = "Microchip SAMA5D27 WLSOM1 EK";
	compatible = "microchip,sama5d27-wlsom1-ek", "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";

	aliases {
	serial0 = &uart0; /* DBGU */
	serial1 = &uart6; /* BT */
	serial2 = &uart5; /* mikro BUS 2 */
	serial3 = &uart3; /* mikro BUS 1 */
	i2c1 = &i2c1;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	gpio_keys {
	compatible = "gpio-keys";

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_key_gpio_default>;
	status = "okay";

	sw4 {
	label = "USER BUTTON";
	gpios = <&pioA PIN_PB2 GPIO_ACTIVE_LOW>;
	linux,code = <0x104>;
	wakeup-source;
	};
	};

	leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_led_gpio_default>;
	status = "okay";

	red {
	label = "red";
	gpios = <&pioA PIN_PA6 GPIO_ACTIVE_HIGH>;
	};

	green {
	label = "green";
	gpios = <&pioA PIN_PA7 GPIO_ACTIVE_HIGH>;
	};

	blue {
	label = "blue";
	gpios = <&pioA PIN_PA8 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	};
	};
	};

	&adc {
	vddana-supply = <&vdd_3v3>;
	vref-supply = <&vdd_3v3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc_default>;
	status = "okay";
	};

	&flx0 {
	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
	status = "okay";

	uart5: serial@200 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0x200 0x200>;
	interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(11))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(12))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
	clock-names = "usart";
	pinctrl-0 = <&pinctrl_flx0_default>;
	pinctrl-names = "default";
	atmel,use-dma-rx;
	atmel,use-dma-tx;
	status = "okay";
	};
	};

	&flx1 {
	status = "okay";

	uart6: serial@200 {
	atmel,use-dma-rx;
	atmel,use-dma-tx;
	status = "okay";
	};
	};

	&macb0 {
	status = "okay";
	};

	&pioA {
	/*
	* There is no real pinmux for ADC, if the pin
	* is not requested by another peripheral then
	* the muxing is done when channel is enabled.
	* Requesting pins for ADC is GPIO is
	* encouraged to prevent conflicts and to
	* disable bias in order to be in the same
	* state when the pin is not muxed to the adc.
	*/
	pinctrl_adc_default: adc_default {
	pinmux = <PIN_PD25__GPIO>,
	<PIN_PD26__GPIO>;
	bias-disable;
	};

	pinctrl_flx0_default: flx0_usart_default {
	pinmux = <PIN_PB28__FLEXCOM0_IO0>,
	<PIN_PB29__FLEXCOM0_IO1>;
	bias-disable;
	};

	pinctrl_key_gpio_default: key_gpio_default {
	pinmux = <PIN_PB2__GPIO>;
	bias-pull-up;
	};

	pinctrl_led_gpio_default: led_gpio_default {
	pinmux = <PIN_PA6__GPIO>,
	<PIN_PA7__GPIO>,
	<PIN_PA8__GPIO>;
	bias-pull-down;
	};

	pinctrl_sdmmc0_default: sdmmc0_default {
	cmd_data {
	pinmux = <PIN_PA1__SDMMC0_CMD>,
	<PIN_PA2__SDMMC0_DAT0>,
	<PIN_PA3__SDMMC0_DAT1>,
	<PIN_PA4__SDMMC0_DAT2>,
	<PIN_PA5__SDMMC0_DAT3>;
	bias-disable;
	};

	ck_cd_vddsel {
	pinmux = <PIN_PA0__SDMMC0_CK>,
	<PIN_PA11__SDMMC0_VDDSEL>,
	<PIN_PA12__SDMMC0_WP>,
	<PIN_PA13__SDMMC0_CD>;
	bias-disable;
	};
	};

	pinctrl_uart0_default: uart0_default {
	pinmux = <PIN_PB26__URXD0>,
	<PIN_PB27__UTXD0>;
	bias-disable;
	};

	pinctrl_uart3_default: uart3_default {
	pinmux = <PIN_PB11__URXD3>,
	<PIN_PB12__UTXD3>;
	bias-disable;
	};

	pinctrl_pwm0_default: pwm0_default {
	pinmux = <PIN_PA31__PWML0>,
	<PIN_PA30__PWMH0>;
	bias-disable;
	};

	pinctrl_usb_default: usb_default {
	pinmux = <PIN_PA10__GPIO>;
	bias-disable;
	};
	+
	+ pinctrl_usba_vbus: usba_vbus {
	+ pinmux = <PIN_PA16__GPIO>;
	+ bias-disable;
	+ };
	};

	&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm0_default>;
	status = "okay";
	};

	&qspi1 {
	status = "okay";

	qspi1_flash: spi_flash@0 {
	status = "okay";
	};
	};

	&sdmmc0 {
	bus-width = <4>;
	mmc-ddr-3_3v;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sdmmc0_default>;
	status = "okay";
	};

	&shutdown_controller {
	atmel,shdwc-debouncer = <976>;
	atmel,wakeup-rtc-timer;

	input@0 {
	reg = <0>;
	atmel,wakeup-type = "low";
	};
	};

	&tcb0 {
	timer0: timer@0 {
	compatible = "atmel,tcb-timer";
	reg = <0>;
	};

	timer1: timer@1 {
	compatible = "atmel,tcb-timer";
	reg = <1>;
	};
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0_default>;
	atmel,use-dma-rx;
	atmel,use-dma-tx;
	status = "okay";
	};

	&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3_default>;
	atmel,use-dma-rx;
	atmel,use-dma-tx;
	status = "okay";
	};

	+&usb0 {
	+ atmel,vbus-gpio = <&pioA PIN_PA16 GPIO_ACTIVE_HIGH>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_usba_vbus>;
	+ status = "okay";
	+};
	+
	&usb1 {
	num-ports = <3>;
	atmel,vbus-gpio = <0
	&pioA PIN_PA10 GPIO_ACTIVE_HIGH
	0
	>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_default>;
	status = "okay";
	};

	&usb2 {
	phy_type = "hsic";
	status = "okay";
	};

	&watchdog {
	status = "okay";
	};

	diff --git a/sys/gnu/dts/arm/at91-sama5d2_ptc_ek.dts b/sys/gnu/dts/arm/at91-sama5d2_ptc_ek.dts
	index ba7f3e646c26..1c24ac8019ba 100644
	--- a/sys/gnu/dts/arm/at91-sama5d2_ptc_ek.dts
	+++ b/sys/gnu/dts/arm/at91-sama5d2_ptc_ek.dts
	@@ -1,415 +1,442 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR X11)
	/*
	* at91-sama5d2_ptc_ek.dts - Device Tree file for SAMA5D2 PTC EK board
	*
	* Copyright (C) 2017 Microchip/Atmel,
	* 2017 Wenyou Yang <wenyou.yang@microchip.com>
	* 2017 Ludovic Desroches <ludovic.desroches@microchip.com>
	*/
	/dts-v1/;
	#include "sama5d2.dtsi"
	#include "sama5d2-pinfunc.h"
	#include <dt-bindings/mfd/atmel-flexcom.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/pinctrl/at91.h>

	/ {
	model = "Atmel SAMA5D2 PTC EK";
	compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5";

	aliases {
	serial0 = &uart0;
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	clocks {
	slow_xtal {
	clock-frequency = <32768>;
	};

	main_xtal {
	clock-frequency = <24000000>;
	};
	};

	ahb {
	usb0: gadget@300000 {
	atmel,vbus-gpio = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usba_vbus>;
	status = "okay";
	};

	usb1: ohci@400000 {
	num-ports = <3>;
	atmel,vbus-gpio = <0
	&pioA PIN_PB12 GPIO_ACTIVE_HIGH
	0
	>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_default>;
	status = "okay";
	};

	usb2: ehci@500000 {
	status = "okay";
	};

	ebi: ebi@10000000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nand_default>;
	status = "okay"; /* conflicts with sdmmc1 and qspi0 */

	nand_controller: nand-controller {
	status = "okay";

	nand@3 {
	reg = <0x3 0x0 0x2>;
	atmel,rb = <0>;
	nand-bus-width = <8>;
	nand-ecc-mode = "hw";
	nand-on-flash-bbt;
	label = "atmel_nand";

	partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	at91bootstrap@0 {
	label = "bootstrap";
	reg = <0x0 0x40000>;
	};

	bootloader@40000 {
	label = "bootloader";
	reg = <0x40000 0xc0000>;
	};

	bootloaderenvred@0x100000 {
	label = "bootloader env redundant";
	reg = <0x100000 0x40000>;
	};

	bootloaderenv@0x140000 {
	label = "bootloader env";
	reg = <0x140000 0x40000>;
	};

	dtb@180000 {
	label = "device tree";
	reg = <0x180000 0x80000>;
	};

	kernel@200000 {
	label = "kernel";
	reg = <0x200000 0x600000>;
	};

	rootfs@800000 {
	label = "rootfs";
	reg = <0x800000 0x1f800000>;
	};
	};
	};
	};
	};

	sdmmc0: sdio-host@a0000000 {
	bus-width = <8>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sdmmc0_default>;
	non-removable;
	mmc-ddr-1_8v;
	status = "okay";
	};

	apb {
	spi0: spi@f8000000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi0_default>;
	status = "okay";
	};

	macb0: ethernet@f8008000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>;
	phy-mode = "rmii";
	status = "okay";

	ethernet-phy@1 {
	reg = <0x1>;
	interrupt-parent = <&pioA>;
	interrupts = <56 IRQ_TYPE_LEVEL_LOW>;
	};
	};

	tcb0: timer@f800c000 {
	timer0: timer@0 {
	compatible = "atmel,tcb-timer";
	reg = <0>;
	};

	timer1: timer@1 {
	compatible = "atmel,tcb-timer";
	reg = <1>;
	};
	};

	uart0: serial@f801c000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0_default>;
	atmel,use-dma-rx;
	atmel,use-dma-tx;
	status = "okay";
	};

	uart2: serial@f8024000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2_default>;
	atmel,use-dma-rx;
	atmel,use-dma-tx;
	status = "okay";
	};

	i2c0: i2c@f8028000 {
	dmas = <0>, <0>;
	- pinctrl-names = "default";
	+ pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c0_default>;
	+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
	+ sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
	+ scl-gpios = <&pioA PIN_PD22 GPIO_ACTIVE_HIGH>;
	status = "okay";
	};

	flx0: flexcom@f8034000 {
	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
	status = "okay";

	i2c2: i2c@600 {
	compatible = "atmel,sama5d2-i2c";
	reg = <0x600 0x200>;
	interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <0>, <0>;
	dma-names = "tx", "rx";
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
	- pinctrl-names = "default";
	+ pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_flx0_default>;
	+ pinctrl-1 = <&pinctrl_flx0_gpio>;
	+ sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>;
	+ scl-gpios = <&pioA PIN_PB29 GPIO_ACTIVE_HIGH>;
	atmel,fifo-size = <16>;
	status = "okay";
	};
	};

	shdwc@f8048010 {
	atmel,shdwc-debouncer = <976>;

	input@0 {
	reg = <0>;
	atmel,wakeup-type = "low";
	};
	};

	watchdog@f8048040 {
	status = "okay";
	};

	spi1: spi@fc000000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi1_default>;
	status = "okay";
	};

	i2c1: i2c@fc028000 {
	dmas = <0>, <0>;
	- pinctrl-names = "default";
	+ pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1_default>;
	+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
	+ sda-gpios = <&pioA PIN_PC6 GPIO_ACTIVE_HIGH>;
	+ scl-gpios = <&pioA PIN_PC7 GPIO_ACTIVE_HIGH>;
	status = "okay";

	at24@50 {
	compatible = "atmel,24c02";
	reg = <0x50>;
	pagesize = <8>;
	};
	};

	pinctrl@fc038000 {
	pinctrl_flx0_default: flx0_default {
	pinmux = <PIN_PB28__FLEXCOM0_IO0>,
	<PIN_PB29__FLEXCOM0_IO1>;
	bias-disable;
	};

	+ pinctrl_flx0_gpio: flx0_gpio {
	+ pinmux = <PIN_PB28__GPIO>,
	+ <PIN_PB29__GPIO>;
	+ bias-disable;
	+ };
	+
	pinctrl_i2c0_default: i2c0_default {
	pinmux = <PIN_PD21__TWD0>,
	<PIN_PD22__TWCK0>;
	bias-disable;
	};

	+ pinctrl_i2c0_gpio: i2c0_gpio {
	+ pinmux = <PIN_PD21__GPIO>,
	+ <PIN_PD22__GPIO>;
	+ bias-disable;
	+ };
	+
	pinctrl_i2c1_default: i2c1_default {
	pinmux = <PIN_PC6__TWD1>,
	<PIN_PC7__TWCK1>;
	bias-disable;
	};

	+ pinctrl_i2c1_gpio: i2c1_gpio {
	+ pinmux = <PIN_PC6__GPIO>,
	+ <PIN_PC7__GPIO>;
	+ bias-disable;
	+ };
	+
	pinctrl_key_gpio_default: key_gpio_default {
	pinmux = <PIN_PA10__GPIO>;
	bias-pull-up;
	};

	pinctrl_led_gpio_default: led_gpio_default {
	pinmux = <PIN_PB6__GPIO>,
	<PIN_PB8__GPIO>,
	<PIN_PB10__GPIO>;
	bias-pull-up;
	};

	pinctrl_macb0_default: macb0_default {
	pinmux = <PIN_PB14__GTXCK>,
	<PIN_PB15__GTXEN>,
	<PIN_PB16__GRXDV>,
	<PIN_PB17__GRXER>,
	<PIN_PB18__GRX0>,
	<PIN_PB19__GRX1>,
	<PIN_PB20__GTX0>,
	<PIN_PB21__GTX1>,
	<PIN_PB22__GMDC>,
	<PIN_PB23__GMDIO>;
	bias-disable;
	};

	pinctrl_macb0_phy_irq: macb0_phy_irq {
	pinmux = <PIN_PB24__GPIO>;
	bias-disable;
	};

	pinctrl_nand_default: nand_default {
	re_we_data {
	pinmux = <PIN_PA22__D0>,
	<PIN_PA23__D1>,
	<PIN_PA24__D2>,
	<PIN_PA25__D3>,
	<PIN_PA26__D4>,
	<PIN_PA27__D5>,
	<PIN_PA28__D6>,
	<PIN_PA29__D7>,
	<PIN_PA30__NWE_NANDWE>,
	<PIN_PB2__NRD_NANDOE>;
	bias-pull-up;
	atmel,drive-strength = <ATMEL_PIO_DRVSTR_ME>;
	};

	ale_cle_rdy_cs {
	pinmux = <PIN_PB0__A21_NANDALE>,
	<PIN_PB1__A22_NANDCLE>,
	<PIN_PC8__NANDRDY>,
	<PIN_PA31__NCS3>;
	bias-pull-up;
	};
	};

	pinctrl_sdmmc0_default: sdmmc0_default {
	cmd_data {
	pinmux = <PIN_PA1__SDMMC0_CMD>,
	<PIN_PA2__SDMMC0_DAT0>,
	<PIN_PA3__SDMMC0_DAT1>,
	<PIN_PA4__SDMMC0_DAT2>,
	<PIN_PA5__SDMMC0_DAT3>,
	<PIN_PA6__SDMMC0_DAT4>,
	<PIN_PA7__SDMMC0_DAT5>,
	<PIN_PA8__SDMMC0_DAT6>,
	<PIN_PA9__SDMMC0_DAT7>;
	bias-pull-up;
	};

	ck_cd_vddsel {
	pinmux = <PIN_PA0__SDMMC0_CK>,
	<PIN_PA11__SDMMC0_VDDSEL>,
	<PIN_PA13__SDMMC0_CD>;
	bias-disable;
	};
	};

	pinctrl_spi0_default: spi0_default {
	pinmux = <PIN_PA14__SPI0_SPCK>,
	<PIN_PA15__SPI0_MOSI>,
	<PIN_PA16__SPI0_MISO>,
	<PIN_PA17__SPI0_NPCS0>;
	bias-disable;
	};

	pinctrl_spi1_default: spi1_default {
	pinmux = <PIN_PC1__SPI1_SPCK>,
	<PIN_PC2__SPI1_MOSI>,
	<PIN_PC3__SPI1_MISO>,
	<PIN_PC4__SPI1_NPCS0>;
	bias-disable;
	};

	pinctrl_uart0_default: uart0_default {
	pinmux = <PIN_PB26__URXD0>,
	<PIN_PB27__UTXD0>;
	bias-disable;
	};

	pinctrl_uart2_default: uart2_default {
	pinmux = <PIN_PD23__URXD2>,
	<PIN_PD24__UTXD2>;
	bias-disable;
	};

	pinctrl_usb_default: usb_default {
	pinmux = <PIN_PB12__GPIO>;
	bias-disable;
	};

	pinctrl_usba_vbus: usba_vbus {
	pinmux = <PIN_PB11__GPIO>;
	bias-disable;
	};

	};

	};
	};

	gpio_keys {
	compatible = "gpio-keys";

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_key_gpio_default>;

	bp1 {
	label = "PB_USER";
	gpios = <&pioA PIN_PA10 GPIO_ACTIVE_LOW>;
	linux,code = <0x104>;
	};
	};

	leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_led_gpio_default>;
	status = "okay";

	red {
	label = "red";
	gpios = <&pioA PIN_PB10 GPIO_ACTIVE_HIGH>;
	};

	green {
	label = "green";
	gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>;
	};

	blue {
	label = "blue";
	gpios = <&pioA PIN_PB6 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/at91-sama5d2_xplained.dts b/sys/gnu/dts/arm/at91-sama5d2_xplained.dts
	index 9d0a7fbea725..055ee53e4773 100644
	--- a/sys/gnu/dts/arm/at91-sama5d2_xplained.dts
	+++ b/sys/gnu/dts/arm/at91-sama5d2_xplained.dts
	@@ -1,647 +1,674 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* at91-sama5d2_xplained.dts - Device Tree file for SAMA5D2 Xplained board
	*
	* Copyright (C) 2015 Atmel,
	* 2015 Nicolas Ferre <nicolas.ferre@atmel.com>
	*/
	/dts-v1/;
	#include "sama5d2.dtsi"
	#include "sama5d2-pinfunc.h"
	#include <dt-bindings/mfd/atmel-flexcom.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/regulator/active-semi,8945a-regulator.h>

	/ {
	model = "Atmel SAMA5D2 Xplained";
	compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5";

	chosen {
	stdout-path = "serial0:115200n8";
	};

	clocks {
	slow_xtal {
	clock-frequency = <32768>;
	};

	main_xtal {
	clock-frequency = <12000000>;
	};
	};

	ahb {
	usb0: gadget@300000 {
	atmel,vbus-gpio = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usba_vbus>;
	status = "okay";
	};

	usb1: ohci@400000 {
	num-ports = <3>;
	atmel,vbus-gpio = <0 /* &pioA PIN_PB9 GPIO_ACTIVE_HIGH */
	&pioA PIN_PB10 GPIO_ACTIVE_HIGH
	0
	>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_default>;
	status = "okay";
	};

	usb2: ehci@500000 {
	status = "okay";
	};

	sdmmc0: sdio-host@a0000000 {
	bus-width = <8>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sdmmc0_default>;
	non-removable;
	mmc-ddr-1_8v;
	status = "okay";
	};

	sdmmc1: sdio-host@b0000000 {
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sdmmc1_default>;
	status = "okay"; /* conflict with qspi0 */
	vqmmc-supply = <&vdd_3v3_reg>;
	vmmc-supply = <&vdd_3v3_reg>;
	};

	apb {
	spi0: spi@f8000000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi0_default>;
	status = "okay";

	m25p80@0 {
	compatible = "atmel,at25df321a";
	reg = <0>;
	spi-max-frequency = <50000000>;
	};
	};

	macb0: ethernet@f8008000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>;
	phy-mode = "rmii";
	status = "okay";

	ethernet-phy@1 {
	reg = <0x1>;
	interrupt-parent = <&pioA>;
	interrupts = <PIN_PC9 IRQ_TYPE_LEVEL_LOW>;
	};
	};

	tcb0: timer@f800c000 {
	timer0: timer@0 {
	compatible = "atmel,tcb-timer";
	reg = <0>;
	};

	timer1: timer@1 {
	compatible = "atmel,tcb-timer";
	reg = <1>;
	};
	};

	pdmic@f8018000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pdmic_default>;
	atmel,model = "PDMIC @ sama5d2_xplained";
	atmel,mic-min-freq = <1000000>;
	atmel,mic-max-freq = <3246000>;
	atmel,mic-offset = <0x0>;
	status = "okay";
	};

	uart1: serial@f8020000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1_default>;
	atmel,use-dma-rx;
	atmel,use-dma-tx;
	status = "okay";
	};

	i2c0: i2c@f8028000 {
	dmas = <0>, <0>;
	- pinctrl-names = "default";
	+ pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c0_default>;
	+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
	+ sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
	+ scl-gpios = <&pioA PIN_PD22 GPIO_ACTIVE_HIGH>;
	i2c-sda-hold-time-ns = <350>;
	status = "okay";

	pmic@5b {
	compatible = "active-semi,act8945a";
	reg = <0x5b>;
	active-semi,vsel-high;
	status = "okay";

	regulators {
	vdd_1v35_reg: REG_DCDC1 {
	regulator-name = "VDD_1V35";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_FIXED>,
	<ACT8945A_REGULATOR_MODE_LOWPOWER>;
	regulator-initial-mode = <ACT8945A_REGULATOR_MODE_FIXED>;
	regulator-always-on;

	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-min-microvolt=<1400000>;
	regulator-suspend-max-microvolt=<1400000>;
	regulator-changeable-in-suspend;
	regulator-mode=<ACT8945A_REGULATOR_MODE_LOWPOWER>;
	};
	};

	vdd_1v2_reg: REG_DCDC2 {
	regulator-name = "VDD_1V2";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1300000>;
	regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_FIXED>,
	<ACT8945A_REGULATOR_MODE_LOWPOWER>;
	regulator-initial-mode = <ACT8945A_REGULATOR_MODE_FIXED>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_3v3_reg: REG_DCDC3 {
	regulator-name = "VDD_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_FIXED>,
	<ACT8945A_REGULATOR_MODE_LOWPOWER>;
	regulator-initial-mode = <ACT8945A_REGULATOR_MODE_FIXED>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_fuse_reg: REG_LDO1 {
	regulator-name = "VDD_FUSE";
	regulator-min-microvolt = <2500000>;
	regulator-max-microvolt = <2500000>;
	regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>,
	<ACT8945A_REGULATOR_MODE_LOWPOWER>;
	regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_3v3_lp_reg: REG_LDO2 {
	regulator-name = "VDD_3V3_LP";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>,
	<ACT8945A_REGULATOR_MODE_LOWPOWER>;
	regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_led_reg: REG_LDO3 {
	regulator-name = "VDD_LED";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>,
	<ACT8945A_REGULATOR_MODE_LOWPOWER>;
	regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_sdhc_1v8_reg: REG_LDO4 {
	regulator-name = "VDD_SDHC_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>,
	<ACT8945A_REGULATOR_MODE_LOWPOWER>;
	regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};
	};

	charger {
	compatible = "active-semi,act8945a-charger";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>;
	interrupt-parent = <&pioA>;
	interrupts = <PIN_PB13 IRQ_TYPE_EDGE_RISING>;

	active-semi,chglev-gpios = <&pioA PIN_PA12 GPIO_ACTIVE_HIGH>;
	active-semi,lbo-gpios = <&pioA PIN_PC8 GPIO_ACTIVE_LOW>;
	active-semi,input-voltage-threshold-microvolt = <6600>;
	active-semi,precondition-timeout = <40>;
	active-semi,total-timeout = <3>;
	status = "okay";
	};
	};
	};

	pwm0: pwm@f802c000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm0_pwm2_default>;
	status = "disabled"; /* conflict with leds */
	};

	flx0: flexcom@f8034000 {
	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
	status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */

	uart5: serial@200 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0x200 0x200>;
	interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
	clock-names = "usart";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flx0_default>;
	atmel,fifo-size = <32>;
	status = "okay";
	};
	};

	shdwc@f8048010 {
	atmel,shdwc-debouncer = <976>;
	atmel,wakeup-rtc-timer;

	input@0 {
	reg = <0>;
	atmel,wakeup-type = "low";
	};
	};

	watchdog@f8048040 {
	status = "okay";
	};

	i2s0: i2s@f8050000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2s0_default>;
	status = "disabled"; /* conflict with can0 */
	};

	can0: can@f8054000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can0_default>;
	status = "okay";
	};

	uart3: serial@fc008000 {
	atmel,use-dma-rx;
	atmel,use-dma-tx;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3_default>;
	status = "okay";
	};

	flx4: flexcom@fc018000 {
	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
	status = "okay";

	i2c2: i2c@600 {
	compatible = "atmel,sama5d2-i2c";
	reg = <0x600 0x200>;
	interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <0>, <0>;
	dma-names = "tx", "rx";
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
	- pinctrl-names = "default";
	+ pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_flx4_default>;
	+ pinctrl-1 = <&pinctrl_flx4_gpio>;
	+ sda-gpios = <&pioA PIN_PD12 GPIO_ACTIVE_HIGH>;
	+ scl-gpios = <&pioA PIN_PD13 GPIO_ACTIVE_HIGH>;
	atmel,fifo-size = <16>;
	i2c-analog-filter;
	i2c-digital-filter;
	i2c-digital-filter-width-ns = <35>;
	status = "okay";
	};
	};

	i2c1: i2c@fc028000 {
	dmas = <0>, <0>;
	- pinctrl-names = "default";
	+ pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1_default>;
	i2c-analog-filter;
	i2c-digital-filter;
	i2c-digital-filter-width-ns = <35>;
	+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
	+ sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>;
	+ scl-gpios = <&pioA PIN_PD5 GPIO_ACTIVE_HIGH>;
	status = "okay";

	at24@54 {
	compatible = "atmel,24c02";
	reg = <0x54>;
	pagesize = <16>;
	};
	};

	adc: adc@fc030000 {
	vddana-supply = <&vdd_3v3_lp_reg>;
	vref-supply = <&vdd_3v3_lp_reg>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
	status = "okay";
	};

	pinctrl@fc038000 {
	/*
	* There is no real pinmux for ADC, if the pin
	* is not requested by another peripheral then
	* the muxing is done when channel is enabled.
	* Requesting pins for ADC is GPIO is
	* encouraged to prevent conflicts and to
	* disable bias in order to be in the same
	* state when the pin is not muxed to the adc.
	*/
	pinctrl_adc_default: adc_default {
	pinmux = <PIN_PD23__GPIO>;
	bias-disable;
	};

	pinctrl_can0_default: can0_default {
	pinmux = <PIN_PC10__CANTX0>,
	<PIN_PC11__CANRX0>;
	bias-disable;
	};

	pinctrl_can1_default: can1_default {
	pinmux = <PIN_PC26__CANTX1>,
	<PIN_PC27__CANRX1>;
	bias-disable;
	};

	/*
	* The ADTRG pin can work on any edge type.
	* In here it's being pulled up, so need to
	* connect it to ground to get an edge e.g.
	* Trigger can be configured on falling, rise
	* or any edge, and the pull-up can be changed
	* to pull-down or left floating according to
	* needs.
	*/
	pinctrl_adtrg_default: adtrg_default {
	pinmux = <PIN_PD31__ADTRG>;
	bias-pull-up;
	};

	pinctrl_charger_chglev: charger_chglev {
	pinmux = <PIN_PA12__GPIO>;
	bias-disable;
	};

	pinctrl_charger_irq: charger_irq {
	pinmux = <PIN_PB13__GPIO>;
	bias-disable;
	};

	pinctrl_charger_lbo: charger_lbo {
	pinmux = <PIN_PC8__GPIO>;
	bias-pull-up;
	};

	pinctrl_classd_default: classd_default {
	pinmux = <PIN_PB1__CLASSD_R0>,
	<PIN_PB2__CLASSD_R1>,
	<PIN_PB3__CLASSD_R2>,
	<PIN_PB4__CLASSD_R3>;
	bias-pull-up;
	};

	pinctrl_flx0_default: flx0_default {
	pinmux = <PIN_PB28__FLEXCOM0_IO0>,
	<PIN_PB29__FLEXCOM0_IO1>;
	bias-disable;
	};

	pinctrl_flx4_default: flx4_default {
	pinmux = <PIN_PD12__FLEXCOM4_IO0>,
	<PIN_PD13__FLEXCOM4_IO1>;
	bias-disable;
	};

	+ pinctrl_flx4_gpio: flx4_gpio {
	+ pinmux = <PIN_PD12__GPIO>,
	+ <PIN_PD13__GPIO>;
	+ bias-disable;
	+ };
	+
	pinctrl_i2c0_default: i2c0_default {
	pinmux = <PIN_PD21__TWD0>,
	<PIN_PD22__TWCK0>;
	bias-disable;
	};

	+ pinctrl_i2c0_gpio: i2c0_gpio {
	+ pinmux = <PIN_PD21__GPIO>,
	+ <PIN_PD22__GPIO>;
	+ bias-disable;
	+ };
	+
	pinctrl_i2c1_default: i2c1_default {
	pinmux = <PIN_PD4__TWD1>,
	<PIN_PD5__TWCK1>;
	bias-disable;
	};

	+ pinctrl_i2c1_gpio: i2c1_gpio {
	+ pinmux = <PIN_PD4__GPIO>,
	+ <PIN_PD5__GPIO>;
	+ bias-disable;
	+ };
	+
	pinctrl_i2s0_default: i2s0_default {
	pinmux = <PIN_PC1__I2SC0_CK>,
	<PIN_PC2__I2SC0_MCK>,
	<PIN_PC3__I2SC0_WS>,
	<PIN_PC4__I2SC0_DI0>,
	<PIN_PC5__I2SC0_DO0>;
	bias-disable;
	};

	pinctrl_i2s1_default: i2s1_default {
	pinmux = <PIN_PA15__I2SC1_CK>,
	<PIN_PA14__I2SC1_MCK>,
	<PIN_PA16__I2SC1_WS>,
	<PIN_PA17__I2SC1_DI0>,
	<PIN_PA18__I2SC1_DO0>;
	bias-disable;
	};

	pinctrl_key_gpio_default: key_gpio_default {
	pinmux = <PIN_PB9__GPIO>;
	bias-pull-up;
	};

	pinctrl_led_gpio_default: led_gpio_default {
	pinmux = <PIN_PB0__GPIO>,
	<PIN_PB5__GPIO>,
	<PIN_PB6__GPIO>;
	bias-pull-up;
	};

	pinctrl_macb0_default: macb0_default {
	pinmux = <PIN_PB14__GTXCK>,
	<PIN_PB15__GTXEN>,
	<PIN_PB16__GRXDV>,
	<PIN_PB17__GRXER>,
	<PIN_PB18__GRX0>,
	<PIN_PB19__GRX1>,
	<PIN_PB20__GTX0>,
	<PIN_PB21__GTX1>,
	<PIN_PB22__GMDC>,
	<PIN_PB23__GMDIO>;
	bias-disable;
	};

	pinctrl_macb0_phy_irq: macb0_phy_irq {
	pinmux = <PIN_PC9__GPIO>;
	bias-disable;
	};

	pinctrl_pdmic_default: pdmic_default {
	pinmux = <PIN_PB26__PDMIC_DAT>,
	<PIN_PB27__PDMIC_CLK>;
	bias-disable;
	};

	pinctrl_sdmmc0_default: sdmmc0_default {
	cmd_data {
	pinmux = <PIN_PA1__SDMMC0_CMD>,
	<PIN_PA2__SDMMC0_DAT0>,
	<PIN_PA3__SDMMC0_DAT1>,
	<PIN_PA4__SDMMC0_DAT2>,
	<PIN_PA5__SDMMC0_DAT3>,
	<PIN_PA6__SDMMC0_DAT4>,
	<PIN_PA7__SDMMC0_DAT5>,
	<PIN_PA8__SDMMC0_DAT6>,
	<PIN_PA9__SDMMC0_DAT7>;
	bias-disable;
	};

	ck_cd_rstn_vddsel {
	pinmux = <PIN_PA0__SDMMC0_CK>,
	<PIN_PA10__SDMMC0_RSTN>,
	<PIN_PA11__SDMMC0_VDDSEL>,
	<PIN_PA13__SDMMC0_CD>;
	bias-disable;
	};
	};

	pinctrl_sdmmc1_default: sdmmc1_default {
	cmd_data {
	pinmux = <PIN_PA28__SDMMC1_CMD>,
	<PIN_PA18__SDMMC1_DAT0>,
	<PIN_PA19__SDMMC1_DAT1>,
	<PIN_PA20__SDMMC1_DAT2>,
	<PIN_PA21__SDMMC1_DAT3>;
	bias-disable;
	};

	conf-ck_cd {
	pinmux = <PIN_PA22__SDMMC1_CK>,
	<PIN_PA30__SDMMC1_CD>;
	bias-disable;
	};
	};

	pinctrl_spi0_default: spi0_default {
	pinmux = <PIN_PA14__SPI0_SPCK>,
	<PIN_PA15__SPI0_MOSI>,
	<PIN_PA16__SPI0_MISO>,
	<PIN_PA17__SPI0_NPCS0>;
	bias-disable;
	};

	pinctrl_uart1_default: uart1_default {
	pinmux = <PIN_PD2__URXD1>,
	<PIN_PD3__UTXD1>;
	bias-disable;
	};

	pinctrl_uart3_default: uart3_default {
	pinmux = <PIN_PB11__URXD3>,
	<PIN_PB12__UTXD3>;
	bias-disable;
	};

	pinctrl_usb_default: usb_default {
	pinmux = <PIN_PB10__GPIO>;
	bias-disable;
	};

	pinctrl_usba_vbus: usba_vbus {
	pinmux = <PIN_PA31__GPIO>;
	bias-disable;
	};

	pinctrl_pwm0_pwm2_default: pwm0_pwm2_default {
	pinmux = <PIN_PB5__PWMH2>,
	<PIN_PB6__PWML2>;
	bias-pull-up;
	};
	};

	classd: classd@fc048000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_classd_default>;
	atmel,pwm-type = "diff";
	atmel,non-overlap-time = <10>;
	status = "okay";
	};

	i2s1: i2s@fc04c000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2s1_default>;
	status = "disabled"; /* conflict with spi0, sdmmc1 */
	};

	can1: can@fc050000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can1_default>;
	status = "okay";
	};
	};
	};

	gpio_keys {
	compatible = "gpio-keys";

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_key_gpio_default>;

	bp1 {
	label = "PB_USER";
	gpios = <&pioA PIN_PB9 GPIO_ACTIVE_LOW>;
	linux,code = <0x104>;
	wakeup-source;
	};
	};

	leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_led_gpio_default>;
	status = "okay"; /* conflict with pwm0 */

	red {
	label = "red";
	gpios = <&pioA PIN_PB6 GPIO_ACTIVE_LOW>;
	};


	green {
	label = "green";
	gpios = <&pioA PIN_PB5 GPIO_ACTIVE_LOW>;
	};

	blue {
	label = "blue";
	gpios = <&pioA PIN_PB0 GPIO_ACTIVE_LOW>;
	linux,default-trigger = "heartbeat";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/at91-sama5d4_ma5d4evk.dts b/sys/gnu/dts/arm/at91-sama5d4_ma5d4evk.dts
	index af4969485c88..4d7cee569ff2 100644
	--- a/sys/gnu/dts/arm/at91-sama5d4_ma5d4evk.dts
	+++ b/sys/gnu/dts/arm/at91-sama5d4_ma5d4evk.dts
	@@ -1,164 +1,164 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	/*
	* Copyright (C) 2015 Marek Vasut <marex@denx.de>
	*/

	/dts-v1/;
	#include "at91-sama5d4_ma5d4.dtsi"

	/ {
	model = "Aries/DENX MA5D4EVK";
	compatible = "aries,ma5d4evk", "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5";

	chosen {
	stdout-path = "serial3:115200n8";
	};

	ahb {
	usb0: gadget@400000 {
	atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usba_vbus>;
	status = "okay";
	};

	usb1: ohci@500000 {
	num-ports = <3>;
	atmel,vbus-gpio = <0
	&pioE 11 GPIO_ACTIVE_LOW
	&pioE 14 GPIO_ACTIVE_LOW
	>;
	status = "okay";
	};

	usb2: ehci@600000 {
	status = "okay";
	};

	apb {
	hlcdc: hlcdc@f0000000 {
	status = "okay";

	hlcdc-display-controller {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;

	port@0 {
	hlcdc_panel_output: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&panel_input>;
	};
	};
	};

	};

	macb0: ethernet@f8020000 {
	phy-mode = "rmii";
	status = "okay";

	phy0: ethernet-phy@0 {
	reg = <0>;
	};
	};

	usart0: serial@f802c000 {
	status = "okay";
	};

	usart1: serial@f8030000 {
	status = "okay";
	};

	mmc1: mmc@fc000000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
	vmmc-supply = <&vcc_mmc1_reg>;
	vqmmc-supply = <&vcc_3v3_reg>;
	status = "okay";
	slot@0 {
	reg = <0>;
	bus-width = <4>;
	cd-gpios = <&pioE 5 0>;
	};
	};

	adc0: adc@fc034000 {
	atmel,adc-ts-wires = <4>;
	atmel,adc-ts-pressure-threshold = <10000>;
	};


	pinctrl@fc06a000 {
	board {
	pinctrl_mmc1_cd: mmc1_cd {
	atmel,pins = <AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
	};
	pinctrl_usba_vbus: usba_vbus {
	atmel,pins =
	<AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
	};
	};
	};
	};
	};

	backlight: backlight {
	compatible = "pwm-backlight";
	pwms = <&hlcdc_pwm 0 50000 0>;
	brightness-levels = <0 4 8 16 32 64 128 255>;
	default-brightness-level = <6>;
	status = "okay";
	};

	leds {
	compatible = "gpio-leds";
	status = "okay";

	user1 {
	label = "user1";
	gpios = <&pioD 28 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	};

	user2 {
	label = "user2";
	gpios = <&pioD 29 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	};

	user3 {
	label = "user3";
	gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	};
	};

	panel: panel {
	/* Actually Ampire 800480R2 */
	- compatible = "foxlink,fl500wvr00-a0t", "simple-panel";
	+ compatible = "foxlink,fl500wvr00-a0t";
	backlight = <&backlight>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	port@0 {
	#address-cells = <1>;
	#size-cells = <0>;

	panel_input: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&hlcdc_panel_output>;
	};
	};
	};

	vcc_mmc1_reg: fixedregulator_mmc1 {
	compatible = "regulator-fixed";
	gpio = <&pioE 17 GPIO_ACTIVE_LOW>;
	regulator-name = "VDD MCI1";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vcc_3v3_reg>;
	};
	};
	diff --git a/sys/gnu/dts/arm/at91sam9n12ek.dts b/sys/gnu/dts/arm/at91sam9n12ek.dts
	index ea5cef0b0974..d36e162a8817 100644
	--- a/sys/gnu/dts/arm/at91sam9n12ek.dts
	+++ b/sys/gnu/dts/arm/at91sam9n12ek.dts
	@@ -1,285 +1,285 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	/*
	* at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board
	*
	* Copyright (C) 2012 Atmel,
	* 2012 Hong Xu <hong.xu@atmel.com>
	*/
	/dts-v1/;
	#include "at91sam9n12.dtsi"

	/ {
	model = "Atmel AT91SAM9N12-EK";
	compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9";

	chosen {
	bootargs = "root=/dev/mtdblock1 rw rootfstype=jffs2";
	stdout-path = "serial0:115200n8";
	};

	memory {
	reg = <0x20000000 0x8000000>;
	};

	clocks {
	slow_xtal {
	clock-frequency = <32768>;
	};

	main_xtal {
	clock-frequency = <16000000>;
	};
	};

	ahb {
	apb {
	dbgu: serial@fffff200 {
	status = "okay";
	};

	ssc0: ssc@f0010000 {
	status = "okay";
	};

	tcb0: timer@f8008000 {
	timer@0 {
	compatible = "atmel,tcb-timer";
	reg = <0>;
	};

	timer@1 {
	compatible = "atmel,tcb-timer";
	reg = <1>;
	};
	};

	i2c0: i2c@f8010000 {
	status = "okay";

	wm8904: codec@1a {
	compatible = "wlf,wm8904";
	reg = <0x1a>;
	clocks = <&pck0>;
	clock-names = "mclk";
	};

	qt1070: keyboard@1b {
	compatible = "qt1070";
	reg = <0x1b>;
	interrupt-parent = <&pioA>;
	interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qt1070_irq>;
	};
	};

	mmc0: mmc@f0008000 {
	pinctrl-0 = <
	&pinctrl_board_mmc0
	&pinctrl_mmc0_slot0_clk_cmd_dat0
	&pinctrl_mmc0_slot0_dat1_3>;
	status = "okay";
	slot@0 {
	reg = <0>;
	bus-width = <4>;
	cd-gpios = <&pioA 7 GPIO_ACTIVE_HIGH>;
	};
	};

	pinctrl@fffff400 {
	mmc0 {
	pinctrl_board_mmc0: mmc0-board {
	atmel,pins =
	<AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PA7 gpio CD pin pull up and deglitch */
	};
	};

	qt1070 {
	pinctrl_qt1070_irq: qt1070_irq {
	atmel,pins =
	<AT91_PIOA 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
	};
	};

	sound {
	pinctrl_pck0_as_audio_mck: pck0_as_audio_mck {
	atmel,pins =
	<AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
	};
	};

	usb1 {
	pinctrl_usb1_vbus_sense: usb1_vbus_sense {
	atmel,pins =
	<AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PB16 gpio usb vbus sense, no pull up and deglitch */
	};
	};
	};

	spi0: spi@f0000000 {
	status = "okay";
	cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
	m25p80@0 {
	compatible = "atmel,at25df321a";
	spi-max-frequency = <50000000>;
	reg = <0>;
	};
	};

	hlcdc: hlcdc@f8038000 {
	status = "okay";

	hlcdc-display-controller {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;

	port@0 {
	hlcdc_panel_output: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&panel_input>;
	};
	};
	};
	};

	usb1: gadget@f803c000 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb1_vbus_sense>;
	atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
	status = "okay";
	};

	watchdog@fffffe40 {
	status = "okay";
	};

	rtc@fffffeb0 {
	status = "okay";
	};
	};

	ebi: ebi@10000000 {
	status = "okay";

	nand_controller: nand-controller {
	status = "okay";
	pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
	pinctrl-names = "default";

	nand@3 {
	reg = <0x3 0x0 0x800000>;
	rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
	cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
	nand-bus-width = <8>;
	nand-ecc-mode = "soft";
	nand-ecc-strength = <2>;
	nand-ecc-step-size = <512>;
	nand-on-flash-bbt;
	label = "atmel_nand";
	};
	};
	};

	usb0: ohci@500000 {
	num-ports = <1>;
	atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>;
	status = "okay";
	};
	};

	backlight: backlight {
	compatible = "pwm-backlight";
	pwms = <&hlcdc_pwm 0 50000 0>;
	brightness-levels = <0 4 8 16 32 64 128 255>;
	default-brightness-level = <6>;
	power-supply = <&bl_reg>;
	status = "okay";
	};

	bl_reg: backlight_regulator {
	compatible = "regulator-fixed";
	regulator-name = "backlight-power-supply";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	status = "okay";
	};

	leds {
	compatible = "gpio-leds";

	d8 {
	label = "d8";
	gpios = <&pioB 4 GPIO_ACTIVE_LOW>;
	linux,default-trigger = "mmc0";
	};

	d9 {
	label = "d9";
	gpios = <&pioB 5 GPIO_ACTIVE_LOW>;
	linux,default-trigger = "nand-disk";
	};

	d10 {
	label = "d10";
	gpios = <&pioB 6 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	};
	};

	gpio_keys {
	compatible = "gpio-keys";

	enter {
	label = "Enter";
	gpios = <&pioB 3 GPIO_ACTIVE_LOW>;
	linux,code = <28>;
	wakeup-source;
	};
	};

	panel: panel {
	- compatible = "qiaodian,qd43003c0-40", "simple-panel";
	+ compatible = "qiaodian,qd43003c0-40";
	backlight = <&backlight>;
	power-supply = <&panel_reg>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	port@0 {
	reg = <0>;
	#address-cells = <1>;
	#size-cells = <0>;

	panel_input: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&hlcdc_panel_output>;
	};
	};
	};

	panel_reg: panel_regulator {
	compatible = "regulator-fixed";
	regulator-name = "panel-power-supply";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	status = "okay";
	};

	sound {
	compatible = "atmel,asoc-wm8904";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pck0_as_audio_mck>;

	atmel,model = "wm8904 @ AT91SAM9N12";
	atmel,audio-routing =
	"Headphone Jack", "HPOUTL",
	"Headphone Jack", "HPOUTR",
	"IN2L", "Line In Jack",
	"IN2R", "Line In Jack",
	"Mic", "MICBIAS",
	"IN1L", "Mic";

	atmel,ssc-controller = <&ssc0>;
	atmel,audio-codec = <&wm8904>;
	};
	};
	diff --git a/sys/gnu/dts/arm/at91sam9x5dm.dtsi b/sys/gnu/dts/arm/at91sam9x5dm.dtsi
	index 7f00c1f57b90..a9278038af3b 100644
	--- a/sys/gnu/dts/arm/at91sam9x5dm.dtsi
	+++ b/sys/gnu/dts/arm/at91sam9x5dm.dtsi
	@@ -1,96 +1,96 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	/*
	* at91sam9x5dm.dtsi - Device Tree file for SAM9x5 display module
	*
	* Copyright (C) 2014 Atmel,
	* 2014 Free Electrons
	*
	* Author: Boris Brezillon <boris.brezillon@free-electrons.com>
	*/

	/ {
	backlight: backlight {
	compatible = "pwm-backlight";
	pwms = <&hlcdc_pwm 0 50000 0>;
	brightness-levels = <0 4 8 16 32 64 128 255>;
	default-brightness-level = <6>;
	power-supply = <&bl_reg>;
	status = "disabled";
	};

	bl_reg: backlight_regulator {
	compatible = "regulator-fixed";
	regulator-name = "backlight-power-supply";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	status = "disabled";
	};

	panel: panel {
	- compatible = "foxlink,fl500wvr00-a0t", "simple-panel";
	+ compatible = "foxlink,fl500wvr00-a0t";
	backlight = <&backlight>;
	power-supply = <&panel_reg>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";

	port@0 {
	#address-cells = <1>;
	#size-cells = <0>;

	panel_input: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&hlcdc_panel_output>;
	};
	};
	};

	panel_reg: panel_regulator {
	compatible = "regulator-fixed";
	regulator-name = "panel-power-supply";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	status = "disabled";
	};
	};

	&adc0 {
	atmel,adc-ts-wires = <4>;
	atmel,adc-ts-pressure-threshold = <10000>;
	status = "okay";
	};

	&i2c0 {
	keyboard@1b {
	compatible = "qt1070";
	reg = <0x1b>;
	interrupt-parent = <&pioA>;
	interrupts = <7 0x0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qt1070_irq>;
	wakeup-source;
	};
	};

	&hlcdc {
	hlcdc-display-controller {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;

	port@0 {
	hlcdc_panel_output: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&panel_input>;
	};
	};
	};
	};

	&pinctrl {
	board {
	pinctrl_qt1070_irq: qt1070_irq {
	atmel,pins =
	<AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/bcm-hr2.dtsi b/sys/gnu/dts/arm/bcm-hr2.dtsi
	index 6142c672811e..5e5f5ca3c86f 100644
	--- a/sys/gnu/dts/arm/bcm-hr2.dtsi
	+++ b/sys/gnu/dts/arm/bcm-hr2.dtsi
	@@ -1,368 +1,368 @@
	/*
	* BSD LICENSE
	*
	* Copyright(c) 2017 Broadcom. All rights reserved.
	*
	* Redistribution and use in source and binary forms, with or without
	* modification, are permitted provided that the following conditions
	* are met:
	*
	* * Redistributions of source code must retain the above copyright
	* notice, this list of conditions and the following disclaimer.
	* * Redistributions in binary form must reproduce the above copyright
	* notice, this list of conditions and the following disclaimer in
	* the documentation and/or other materials provided with the
	* distribution.
	* * Neither the name of Broadcom Corporation nor the names of its
	* contributors may be used to endorse or promote products derived
	* from this software without specific prior written permission.
	*
	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/interrupt-controller/irq.h>

	/ {
	compatible = "brcm,hr2";
	model = "Broadcom Hurricane 2 SoC";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	next-level-cache = <&L2>;
	reg = <0x0>;
	};
	};

	pmu {
	compatible = "arm,cortex-a9-pmu";
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
	GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>;
	};

	mpcore@19000000 {
	compatible = "simple-bus";
	ranges = <0x00000000 0x19000000 0x00023000>;
	#address-cells = <1>;
	#size-cells = <1>;

	a9pll: arm_clk@0 {
	#clock-cells = <0>;
	compatible = "brcm,hr2-armpll";
	clocks = <&osc>;
	reg = <0x0 0x1000>;
	};

	timer@20200 {
	compatible = "arm,cortex-a9-global-timer";
	reg = <0x20200 0x100>;
	- interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
	+ interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
	clocks = <&periph_clk>;
	};

	twd-timer@20600 {
	compatible = "arm,cortex-a9-twd-timer";
	reg = <0x20600 0x20>;
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) \|
	- IRQ_TYPE_LEVEL_HIGH)>;
	+ IRQ_TYPE_EDGE_RISING)>;
	clocks = <&periph_clk>;
	};

	twd-watchdog@20620 {
	compatible = "arm,cortex-a9-twd-wdt";
	reg = <0x20620 0x20>;
	interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) \|
	- IRQ_TYPE_LEVEL_HIGH)>;
	+ IRQ_TYPE_EDGE_RISING)>;
	clocks = <&periph_clk>;
	};

	gic: interrupt-controller@21000 {
	compatible = "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x21000 0x1000>,
	<0x20100 0x100>;
	};

	L2: l2-cache@22000 {
	compatible = "arm,pl310-cache";
	reg = <0x22000 0x1000>;
	cache-unified;
	cache-level = <2>;
	};
	};

	clocks {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	osc: oscillator {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <25000000>;
	};

	periph_clk: periph_clk {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clocks = <&a9pll>;
	clock-div = <2>;
	clock-mult = <1>;
	};
	};

	axi@18000000 {
	compatible = "simple-bus";
	ranges = <0x00000000 0x18000000 0x0011c40c>;
	#address-cells = <1>;
	#size-cells = <1>;

	uart0: serial@300 {
	compatible = "ns16550a";
	reg = <0x0300 0x100>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc>;
	status = "disabled";
	};

	uart1: serial@400 {
	compatible = "ns16550a";
	reg = <0x0400 0x100>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc>;
	status = "disabled";
	};

	dma@20000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x20000 0x1000>;
	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	status = "disabled";
	};

	amac0: ethernet@22000 {
	compatible = "brcm,nsp-amac";
	reg = <0x22000 0x1000>,
	<0x110000 0x1000>;
	reg-names = "amac_base", "idm_base";
	interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	nand: nand@26000 {
	compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
	reg = <0x26000 0x600>,
	<0x11b408 0x600>,
	<0x026f00 0x20>;
	reg-names = "nand", "iproc-idm", "iproc-ext";
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;

	#address-cells = <1>;
	#size-cells = <0>;

	brcm,nand-has-wp;
	};

	gpiob: gpio@30000 {
	compatible = "brcm,iproc-hr2-gpio", "brcm,iproc-gpio";
	reg = <0x30000 0x50>;
	#gpio-cells = <2>;
	gpio-controller;
	ngpios = <4>;
	interrupt-controller;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	};

	pwm: pwm@31000 {
	compatible = "brcm,iproc-pwm";
	reg = <0x31000 0x28>;
	clocks = <&osc>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	rng: rng@33000 {
	compatible = "brcm,bcm-nsp-rng";
	reg = <0x33000 0x14>;
	};

	qspi: spi@27200 {
	compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
	reg = <0x027200 0x184>,
	<0x027000 0x124>,
	<0x11c408 0x004>,
	<0x0273a0 0x01c>;
	reg-names = "mspi", "bspi", "intr_regs",
	"intr_status_reg";
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "spi_lr_fullness_reached",
	"spi_lr_session_aborted",
	"spi_lr_impatient",
	"spi_lr_session_done",
	"spi_lr_overhead",
	"mspi_done",
	"mspi_halted";
	num-cs = <2>;
	#address-cells = <1>;
	#size-cells = <0>;

	/* partitions defined in board DTS */
	};

	ccbtimer0: timer@34000 {
	compatible = "arm,sp804";
	reg = <0x34000 0x1000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	};

	ccbtimer1: timer@35000 {
	compatible = "arm,sp804";
	reg = <0x35000 0x1000>;
	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	};

	i2c0: i2c@38000 {
	compatible = "brcm,iproc-i2c";
	reg = <0x38000 0x50>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <100000>;
	};

	watchdog: watchdog@39000 {
	compatible = "arm,sp805", "arm,primecell";
	reg = <0x39000 0x1000>;
	interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
	};

	i2c1: i2c@3b000 {
	compatible = "brcm,iproc-i2c";
	reg = <0x3b000 0x50>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <100000>;
	};
	};

	pflash: nor@20000000 {
	compatible = "cfi-flash", "jedec-flash";
	reg = <0x20000000 0x04000000>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;

	/* partitions defined in board DTS */
	};

	pcie0: pcie@18012000 {
	compatible = "brcm,iproc-pcie";
	reg = <0x18012000 0x1000>;

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;

	linux,pci-domain = <0>;

	bus-range = <0x00 0xff>;

	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";

	/* Note: The HW does not support I/O resources. So,
	* only the memory resource range is being specified.
	*/
	ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;

	status = "disabled";

	msi-parent = <&msi0>;
	msi0: msi-controller {
	compatible = "brcm,iproc-msi";
	msi-controller;
	interrupt-parent = <&gic>;
	interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
	brcm,pcie-msi-inten;
	};
	};

	pcie1: pcie@18013000 {
	compatible = "brcm,iproc-pcie";
	reg = <0x18013000 0x1000>;

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;

	linux,pci-domain = <1>;

	bus-range = <0x00 0xff>;

	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";

	/* Note: The HW does not support I/O resources. So,
	* only the memory resource range is being specified.
	*/
	ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;

	status = "disabled";

	msi-parent = <&msi1>;
	msi1: msi-controller {
	compatible = "brcm,iproc-msi";
	msi-controller;
	interrupt-parent = <&gic>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
	brcm,pcie-msi-inten;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/bcm2711-rpi-4-b.dts b/sys/gnu/dts/arm/bcm2711-rpi-4-b.dts
	index efea891b1a76..e26ea9006378 100644
	--- a/sys/gnu/dts/arm/bcm2711-rpi-4-b.dts
	+++ b/sys/gnu/dts/arm/bcm2711-rpi-4-b.dts
	@@ -1,143 +1,217 @@
	// SPDX-License-Identifier: GPL-2.0
	/dts-v1/;
	#include "bcm2711.dtsi"
	#include "bcm2835-rpi.dtsi"
	#include "bcm283x-rpi-usb-peripheral.dtsi"

	/ {
	compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
	model = "Raspberry Pi 4 Model B";

	chosen {
	/* 8250 auxiliary UART instead of pl011 */
	stdout-path = "serial1:115200n8";
	};

	/* Will be filled by the bootloader */
	memory@0 {
	device_type = "memory";
	reg = <0 0 0>;
	};

	aliases {
	+ emmc2bus = &emmc2bus;
	ethernet0 = &genet;
	pcie0 = &pcie0;
	};

	leds {
	act {
	gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
	};

	pwr {
	label = "PWR";
	gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
	default-state = "keep";
	linux,default-trigger = "default-on";
	};
	};

	wifi_pwrseq: wifi-pwrseq {
	compatible = "mmc-pwrseq-simple";
	reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
	};

	sd_io_1v8_reg: sd_io_1v8_reg {
	compatible = "regulator-gpio";
	regulator-name = "vdd-sd-io";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-settling-time-us = <5000>;
	gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;
	states = <1800000 0x1
	3300000 0x0>;
	status = "okay";
	};
	};

	&firmware {
	expgpio: gpio {
	compatible = "raspberrypi,firmware-gpio";
	gpio-controller;
	#gpio-cells = <2>;
	gpio-line-names = "BT_ON",
	"WL_ON",
	"PWR_LED_OFF",
	"GLOBAL_RESET",
	"VDD_SD_IO_SEL",
	"CAM_GPIO",
	"",
	"";
	status = "okay";
	};
	};

	+&gpio {
	+ /*
	+ * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and
	+ * the official GPU firmware DT blob.
	+ *
	+ * Legend:
	+ * "FOO" = GPIO line named "FOO" on the schematic
	+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
	+ */
	+ gpio-line-names = "ID_SDA",
	+ "ID_SCL",
	+ "SDA1",
	+ "SCL1",
	+ "GPIO_GCLK",
	+ "GPIO5",
	+ "GPIO6",
	+ "SPI_CE1_N",
	+ "SPI_CE0_N",
	+ "SPI_MISO",
	+ "SPI_MOSI",
	+ "SPI_SCLK",
	+ "GPIO12",
	+ "GPIO13",
	+ /* Serial port */
	+ "TXD1",
	+ "RXD1",
	+ "GPIO16",
	+ "GPIO17",
	+ "GPIO18",
	+ "GPIO19",
	+ "GPIO20",
	+ "GPIO21",
	+ "GPIO22",
	+ "GPIO23",
	+ "GPIO24",
	+ "GPIO25",
	+ "GPIO26",
	+ "GPIO27",
	+ "RGMII_MDIO",
	+ "RGMIO_MDC",
	+ /* Used by BT module */
	+ "CTS0",
	+ "RTS0",
	+ "TXD0",
	+ "RXD0",
	+ /* Used by Wifi */
	+ "SD1_CLK",
	+ "SD1_CMD",
	+ "SD1_DATA0",
	+ "SD1_DATA1",
	+ "SD1_DATA2",
	+ "SD1_DATA3",
	+ /* Shared with SPI flash */
	+ "PWM0_MISO",
	+ "PWM1_MOSI",
	+ "STATUS_LED_G_CLK",
	+ "SPIFLASH_CE_N",
	+ "SDA0",
	+ "SCL0",
	+ "RGMII_RXCLK",
	+ "RGMII_RXCTL",
	+ "RGMII_RXD0",
	+ "RGMII_RXD1",
	+ "RGMII_RXD2",
	+ "RGMII_RXD3",
	+ "RGMII_TXCLK",
	+ "RGMII_TXCTL",
	+ "RGMII_TXD0",
	+ "RGMII_TXD1",
	+ "RGMII_TXD2",
	+ "RGMII_TXD3";
	+};
	+
	&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;
	status = "okay";
	};

	/* SDHCI is used to control the SDIO for wireless */
	&sdhci {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_gpio34>;
	bus-width = <4>;
	non-removable;
	mmc-pwrseq = <&wifi_pwrseq>;
	status = "okay";

	brcmf: wifi@1 {
	reg = <1>;
	compatible = "brcm,bcm4329-fmac";
	};
	};

	/* EMMC2 is used to drive the SD card */
	&emmc2 {
	vqmmc-supply = <&sd_io_1v8_reg>;
	broken-cd;
	status = "okay";
	};

	&genet {
	phy-handle = <&phy1>;
	phy-mode = "rgmii-rxid";
	status = "okay";
	};

	&genet_mdio {
	phy1: ethernet-phy@1 {
	/* No PHY interrupt */
	reg = <0x1>;
	};
	};

	/* uart0 communicates with the BT module */
	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
	uart-has-rtscts;
	status = "okay";

	bluetooth {
	compatible = "brcm,bcm43438-bt";
	max-speed = <2000000>;
	shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
	};
	};

	/* uart1 is mapped to the pin header */
	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_gpio14>;
	status = "okay";
	};

	&vchiq {
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	};
	diff --git a/sys/gnu/dts/arm/bcm2711.dtsi b/sys/gnu/dts/arm/bcm2711.dtsi
	index d1e684d0acfd..a91cf68e3c4c 100644
	--- a/sys/gnu/dts/arm/bcm2711.dtsi
	+++ b/sys/gnu/dts/arm/bcm2711.dtsi
	@@ -1,922 +1,937 @@
	// SPDX-License-Identifier: GPL-2.0
	#include "bcm283x.dtsi"

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/soc/bcm2835-pm.h>

	/ {
	compatible = "brcm,bcm2711";

	#address-cells = <2>;
	#size-cells = <1>;

	interrupt-parent = <&gicv2>;

	soc {
	/*
	* Defined ranges:
	* Common BCM283x peripherals
	* BCM2711-specific peripherals
	* ARM-local peripherals
	*/
	ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
	<0x7c000000 0x0 0xfc000000 0x02000000>,
	<0x40000000 0x0 0xff800000 0x00800000>;
	/* Emulate a contiguous 30-bit address range for DMA */
	dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;

	/*
	* This node is the provider for the enable-method for
	* bringing up secondary cores.
	*/
	local_intc: local_intc@40000000 {
	compatible = "brcm,bcm2836-l1-intc";
	reg = <0x40000000 0x100>;
	};

	gicv2: interrupt-controller@40041000 {
	interrupt-controller;
	#interrupt-cells = <3>;
	compatible = "arm,gic-400";
	reg = <0x40041000 0x1000>,
	<0x40042000 0x2000>,
	<0x40044000 0x2000>,
	<0x40046000 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \|
	IRQ_TYPE_LEVEL_HIGH)>;
	};

	avs_monitor: avs-monitor@7d5d2000 {
	compatible = "brcm,bcm2711-avs-monitor",
	"syscon", "simple-mfd";
	reg = <0x7d5d2000 0xf00>;

	thermal: thermal {
	compatible = "brcm,bcm2711-thermal";
	#thermal-sensor-cells = <0>;
	};
	};

	dma: dma@7e007000 {
	compatible = "brcm,bcm2835-dma";
	reg = <0x7e007000 0xb00>;
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
	/* DMA lite 7 - 10 */
	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "dma0",
	"dma1",
	"dma2",
	"dma3",
	"dma4",
	"dma5",
	"dma6",
	"dma7",
	"dma8",
	"dma9",
	"dma10";
	#dma-cells = <1>;
	brcm,dma-channel-mask = <0x07f5>;
	};

	pm: watchdog@7e100000 {
	compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
	#power-domain-cells = <1>;
	#reset-cells = <1>;
	reg = <0x7e100000 0x114>,
	<0x7e00a000 0x24>,
	<0x7ec11000 0x20>;
	clocks = <&clocks BCM2835_CLOCK_V3D>,
	<&clocks BCM2835_CLOCK_PERI_IMAGE>,
	<&clocks BCM2835_CLOCK_H264>,
	<&clocks BCM2835_CLOCK_ISP>;
	clock-names = "v3d", "peri_image", "h264", "isp";
	system-power-controller;
	};

	rng@7e104000 {
	compatible = "brcm,bcm2711-rng200";
	reg = <0x7e104000 0x28>;
	};

	uart2: serial@7e201400 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x7e201400 0x200>;
	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clocks BCM2835_CLOCK_UART>,
	<&clocks BCM2835_CLOCK_VPU>;
	clock-names = "uartclk", "apb_pclk";
	arm,primecell-periphid = <0x00241011>;
	status = "disabled";
	};

	uart3: serial@7e201600 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x7e201600 0x200>;
	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clocks BCM2835_CLOCK_UART>,
	<&clocks BCM2835_CLOCK_VPU>;
	clock-names = "uartclk", "apb_pclk";
	arm,primecell-periphid = <0x00241011>;
	status = "disabled";
	};

	uart4: serial@7e201800 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x7e201800 0x200>;
	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clocks BCM2835_CLOCK_UART>,
	<&clocks BCM2835_CLOCK_VPU>;
	clock-names = "uartclk", "apb_pclk";
	arm,primecell-periphid = <0x00241011>;
	status = "disabled";
	};

	uart5: serial@7e201a00 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x7e201a00 0x200>;
	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clocks BCM2835_CLOCK_UART>,
	<&clocks BCM2835_CLOCK_VPU>;
	clock-names = "uartclk", "apb_pclk";
	arm,primecell-periphid = <0x00241011>;
	status = "disabled";
	};

	spi3: spi@7e204600 {
	compatible = "brcm,bcm2835-spi";
	reg = <0x7e204600 0x0200>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clocks BCM2835_CLOCK_VPU>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi4: spi@7e204800 {
	compatible = "brcm,bcm2835-spi";
	reg = <0x7e204800 0x0200>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clocks BCM2835_CLOCK_VPU>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi5: spi@7e204a00 {
	compatible = "brcm,bcm2835-spi";
	reg = <0x7e204a00 0x0200>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clocks BCM2835_CLOCK_VPU>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi6: spi@7e204c00 {
	compatible = "brcm,bcm2835-spi";
	reg = <0x7e204c00 0x0200>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clocks BCM2835_CLOCK_VPU>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c3: i2c@7e205600 {
	compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
	reg = <0x7e205600 0x200>;
	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clocks BCM2835_CLOCK_VPU>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c4: i2c@7e205800 {
	compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
	reg = <0x7e205800 0x200>;
	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clocks BCM2835_CLOCK_VPU>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c5: i2c@7e205a00 {
	compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
	reg = <0x7e205a00 0x200>;
	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clocks BCM2835_CLOCK_VPU>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c6: i2c@7e205c00 {
	compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
	reg = <0x7e205c00 0x200>;
	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clocks BCM2835_CLOCK_VPU>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	pwm1: pwm@7e20c800 {
	compatible = "brcm,bcm2835-pwm";
	reg = <0x7e20c800 0x28>;
	clocks = <&clocks BCM2835_CLOCK_PWM>;
	assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
	assigned-clock-rates = <10000000>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	+ hvs@7e400000 {
	+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	+ };
	+ };
	+
	+ /*
	+ * emmc2 has different DMA constraints based on SoC revisions. It was
	+ * moved into its own bus, so as for RPi4's firmware to update them.
	+ * The firmware will find whether the emmc2bus alias is defined, and if
	+ * so, it'll edit the dma-ranges property below accordingly.
	+ */
	+ emmc2bus: emmc2bus {
	+ compatible = "simple-bus";
	+ #address-cells = <2>;
	+ #size-cells = <1>;
	+
	+ ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
	+ dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
	+
	emmc2: emmc2@7e340000 {
	compatible = "brcm,bcm2711-emmc2";
	- reg = <0x7e340000 0x100>;
	+ reg = <0x0 0x7e340000 0x100>;
	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clocks BCM2711_CLOCK_EMMC2>;
	status = "disabled";
	};
	-
	- hvs@7e400000 {
	- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	- };
	};

	arm-pmu {
	compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \|
	IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \|
	IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \|
	IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \|
	IRQ_TYPE_LEVEL_LOW)>;
	/* This only applies to the ARMv7 stub */
	arm,cpu-registers-not-fw-configured;
	};

	cpus: cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	reg = <0>;
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x000000d8>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	reg = <1>;
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x000000e0>;
	};

	cpu2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	reg = <2>;
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x000000e8>;
	};

	cpu3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	reg = <3>;
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x000000f0>;
	};
	};

	scb {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <1>;

	ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
	<0x6 0x00000000 0x6 0x00000000 0x40000000>;

	pcie0: pcie@7d500000 {
	compatible = "brcm,bcm2711-pcie";
	reg = <0x0 0x7d500000 0x9310>;
	device_type = "pci";
	#address-cells = <3>;
	#interrupt-cells = <1>;
	#size-cells = <2>;
	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "pcie", "msi";
	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
	interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
	IRQ_TYPE_LEVEL_HIGH>;
	msi-controller;
	msi-parent = <&pcie0>;

	ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
	0x0 0x04000000>;
	/*
	* The wrapper around the PCIe block has a bug
	* preventing it from accessing beyond the first 3GB of
	* memory.
	*/
	dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
	0x0 0xc0000000>;
	brcm,enable-ssc;
	};

	genet: ethernet@7d580000 {
	compatible = "brcm,bcm2711-genet-v5";
	reg = <0x0 0x7d580000 0x10000>;
	#address-cells = <0x1>;
	#size-cells = <0x1>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";

	genet_mdio: mdio@e14 {
	compatible = "brcm,genet-mdio-v5";
	reg = <0xe14 0x8>;
	reg-names = "mdio";
	#address-cells = <0x0>;
	#size-cells = <0x1>;
	};
	};
	};
	};

	&clk_osc {
	clock-frequency = <54000000>;
	};

	&clocks {
	compatible = "brcm,bcm2711-cprman";
	};

	&cpu_thermal {
	coefficients = <(-487) 410040>;
	thermal-sensors = <&thermal>;
	};

	&dsi0 {
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	};

	&dsi1 {
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	};

	&gpio {
	compatible = "brcm,bcm2711-gpio";
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;

	gpclk0_gpio49: gpclk0_gpio49 {
	pin-gpclk {
	pins = "gpio49";
	function = "alt1";
	bias-disable;
	};
	};
	gpclk1_gpio50: gpclk1_gpio50 {
	pin-gpclk {
	pins = "gpio50";
	function = "alt1";
	bias-disable;
	};
	};
	gpclk2_gpio51: gpclk2_gpio51 {
	pin-gpclk {
	pins = "gpio51";
	function = "alt1";
	bias-disable;
	};
	};

	i2c0_gpio46: i2c0_gpio46 {
	pin-sda {
	function = "alt0";
	pins = "gpio46";
	bias-pull-up;
	};
	pin-scl {
	function = "alt0";
	pins = "gpio47";
	bias-disable;
	};
	};
	i2c1_gpio46: i2c1_gpio46 {
	pin-sda {
	function = "alt1";
	pins = "gpio46";
	bias-pull-up;
	};
	pin-scl {
	function = "alt1";
	pins = "gpio47";
	bias-disable;
	};
	};
	i2c3_gpio2: i2c3_gpio2 {
	pin-sda {
	function = "alt5";
	pins = "gpio2";
	bias-pull-up;
	};
	pin-scl {
	function = "alt5";
	pins = "gpio3";
	bias-disable;
	};
	};
	i2c3_gpio4: i2c3_gpio4 {
	pin-sda {
	function = "alt5";
	pins = "gpio4";
	bias-pull-up;
	};
	pin-scl {
	function = "alt5";
	pins = "gpio5";
	bias-disable;
	};
	};
	i2c4_gpio6: i2c4_gpio6 {
	pin-sda {
	function = "alt5";
	pins = "gpio6";
	bias-pull-up;
	};
	pin-scl {
	function = "alt5";
	pins = "gpio7";
	bias-disable;
	};
	};
	i2c4_gpio8: i2c4_gpio8 {
	pin-sda {
	function = "alt5";
	pins = "gpio8";
	bias-pull-up;
	};
	pin-scl {
	function = "alt5";
	pins = "gpio9";
	bias-disable;
	};
	};
	i2c5_gpio10: i2c5_gpio10 {
	pin-sda {
	function = "alt5";
	pins = "gpio10";
	bias-pull-up;
	};
	pin-scl {
	function = "alt5";
	pins = "gpio11";
	bias-disable;
	};
	};
	i2c5_gpio12: i2c5_gpio12 {
	pin-sda {
	function = "alt5";
	pins = "gpio12";
	bias-pull-up;
	};
	pin-scl {
	function = "alt5";
	pins = "gpio13";
	bias-disable;
	};
	};
	i2c6_gpio0: i2c6_gpio0 {
	pin-sda {
	function = "alt5";
	pins = "gpio0";
	bias-pull-up;
	};
	pin-scl {
	function = "alt5";
	pins = "gpio1";
	bias-disable;
	};
	};
	i2c6_gpio22: i2c6_gpio22 {
	pin-sda {
	function = "alt5";
	pins = "gpio22";
	bias-pull-up;
	};
	pin-scl {
	function = "alt5";
	pins = "gpio23";
	bias-disable;
	};
	};
	i2c_slave_gpio8: i2c_slave_gpio8 {
	pins-i2c-slave {
	pins = "gpio8",
	"gpio9",
	"gpio10",
	"gpio11";
	function = "alt3";
	};
	};

	jtag_gpio48: jtag_gpio48 {
	pins-jtag {
	pins = "gpio48",
	"gpio49",
	"gpio50",
	"gpio51",
	"gpio52",
	"gpio53";
	function = "alt4";
	};
	};

	mii_gpio28: mii_gpio28 {
	pins-mii {
	pins = "gpio28",
	"gpio29",
	"gpio30",
	"gpio31";
	function = "alt4";
	};
	};
	mii_gpio36: mii_gpio36 {
	pins-mii {
	pins = "gpio36",
	"gpio37",
	"gpio38",
	"gpio39";
	function = "alt5";
	};
	};

	pcm_gpio50: pcm_gpio50 {
	pins-pcm {
	pins = "gpio50",
	"gpio51",
	"gpio52",
	"gpio53";
	function = "alt2";
	};
	};

	pwm0_0_gpio12: pwm0_0_gpio12 {
	pin-pwm {
	pins = "gpio12";
	function = "alt0";
	bias-disable;
	};
	};
	pwm0_0_gpio18: pwm0_0_gpio18 {
	pin-pwm {
	pins = "gpio18";
	function = "alt5";
	bias-disable;
	};
	};
	pwm1_0_gpio40: pwm1_0_gpio40 {
	pin-pwm {
	pins = "gpio40";
	function = "alt0";
	bias-disable;
	};
	};
	pwm0_1_gpio13: pwm0_1_gpio13 {
	pin-pwm {
	pins = "gpio13";
	function = "alt0";
	bias-disable;
	};
	};
	pwm0_1_gpio19: pwm0_1_gpio19 {
	pin-pwm {
	pins = "gpio19";
	function = "alt5";
	bias-disable;
	};
	};
	pwm1_1_gpio41: pwm1_1_gpio41 {
	pin-pwm {
	pins = "gpio41";
	function = "alt0";
	bias-disable;
	};
	};
	pwm0_1_gpio45: pwm0_1_gpio45 {
	pin-pwm {
	pins = "gpio45";
	function = "alt0";
	bias-disable;
	};
	};
	pwm0_0_gpio52: pwm0_0_gpio52 {
	pin-pwm {
	pins = "gpio52";
	function = "alt1";
	bias-disable;
	};
	};
	pwm0_1_gpio53: pwm0_1_gpio53 {
	pin-pwm {
	pins = "gpio53";
	function = "alt1";
	bias-disable;
	};
	};

	rgmii_gpio35: rgmii_gpio35 {
	pin-start-stop {
	pins = "gpio35";
	function = "alt4";
	};
	pin-rx-ok {
	pins = "gpio36";
	function = "alt4";
	};
	};
	rgmii_irq_gpio34: rgmii_irq_gpio34 {
	pin-irq {
	pins = "gpio34";
	function = "alt5";
	};
	};
	rgmii_irq_gpio39: rgmii_irq_gpio39 {
	pin-irq {
	pins = "gpio39";
	function = "alt4";
	};
	};
	rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
	pins-mdio {
	pins = "gpio28",
	"gpio29";
	function = "alt5";
	};
	};
	rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
	pins-mdio {
	pins = "gpio37",
	"gpio38";
	function = "alt4";
	};
	};

	spi0_gpio46: spi0_gpio46 {
	pins-spi {
	pins = "gpio46",
	"gpio47",
	"gpio48",
	"gpio49";
	function = "alt2";
	};
	};
	spi2_gpio46: spi2_gpio46 {
	pins-spi {
	pins = "gpio46",
	"gpio47",
	"gpio48",
	"gpio49",
	"gpio50";
	function = "alt5";
	};
	};
	spi3_gpio0: spi3_gpio0 {
	pins-spi {
	pins = "gpio0",
	"gpio1",
	"gpio2",
	"gpio3";
	function = "alt3";
	};
	};
	spi4_gpio4: spi4_gpio4 {
	pins-spi {
	pins = "gpio4",
	"gpio5",
	"gpio6",
	"gpio7";
	function = "alt3";
	};
	};
	spi5_gpio12: spi5_gpio12 {
	pins-spi {
	pins = "gpio12",
	"gpio13",
	"gpio14",
	"gpio15";
	function = "alt3";
	};
	};
	spi6_gpio18: spi6_gpio18 {
	pins-spi {
	pins = "gpio18",
	"gpio19",
	"gpio20",
	"gpio21";
	function = "alt3";
	};
	};

	uart2_gpio0: uart2_gpio0 {
	pin-tx {
	pins = "gpio0";
	function = "alt4";
	bias-disable;
	};
	pin-rx {
	pins = "gpio1";
	function = "alt4";
	bias-pull-up;
	};
	};
	uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
	pin-cts {
	pins = "gpio2";
	function = "alt4";
	bias-pull-up;
	};
	pin-rts {
	pins = "gpio3";
	function = "alt4";
	bias-disable;
	};
	};
	uart3_gpio4: uart3_gpio4 {
	pin-tx {
	pins = "gpio4";
	function = "alt4";
	bias-disable;
	};
	pin-rx {
	pins = "gpio5";
	function = "alt4";
	bias-pull-up;
	};
	};
	uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
	pin-cts {
	pins = "gpio6";
	function = "alt4";
	bias-pull-up;
	};
	pin-rts {
	pins = "gpio7";
	function = "alt4";
	bias-disable;
	};
	};
	uart4_gpio8: uart4_gpio8 {
	pin-tx {
	pins = "gpio8";
	function = "alt4";
	bias-disable;
	};
	pin-rx {
	pins = "gpio9";
	function = "alt4";
	bias-pull-up;
	};
	};
	uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
	pin-cts {
	pins = "gpio10";
	function = "alt4";
	bias-pull-up;
	};
	pin-rts {
	pins = "gpio11";
	function = "alt4";
	bias-disable;
	};
	};
	uart5_gpio12: uart5_gpio12 {
	pin-tx {
	pins = "gpio12";
	function = "alt4";
	bias-disable;
	};
	pin-rx {
	pins = "gpio13";
	function = "alt4";
	bias-pull-up;
	};
	};
	uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
	pin-cts {
	pins = "gpio14";
	function = "alt4";
	bias-pull-up;
	};
	pin-rts {
	pins = "gpio15";
	function = "alt4";
	bias-disable;
	};
	};
	};

	&rmem {
	#address-cells = <2>;
	};

	&cma {
	/*
	* arm64 reserves the CMA by default somewhere in ZONE_DMA32,
	* that's not good enough for the BCM2711 as some devices can
	* only address the lower 1G of memory (ZONE_DMA).
	*/
	alloc-ranges = <0x0 0x00000000 0x40000000>;
	};

	&i2c0 {
	compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	};

	&i2c1 {
	compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	};

	&mailbox {
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	};

	&sdhci {
	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
	};

	&sdhost {
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	};

	&spi {
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	};

	&spi1 {
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	};

	&spi2 {
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	};

	&system_timer {
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	};

	&txp {
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	};

	&uart0 {
	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
	};

	&uart1 {
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	};

	&usb {
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	};

	&vec {
	interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
	};
	diff --git a/sys/gnu/dts/arm/bcm2835-rpi-zero-w.dts b/sys/gnu/dts/arm/bcm2835-rpi-zero-w.dts
	index 4c3f606e5b8d..f65448c01e31 100644
	--- a/sys/gnu/dts/arm/bcm2835-rpi-zero-w.dts
	+++ b/sys/gnu/dts/arm/bcm2835-rpi-zero-w.dts
	@@ -1,151 +1,151 @@
	// SPDX-License-Identifier: GPL-2.0+
	/*
	* Copyright (C) 2017 Stefan Wahren <stefan.wahren@i2se.com>
	*/

	/dts-v1/;
	#include "bcm2835.dtsi"
	#include "bcm2835-rpi.dtsi"
	#include "bcm283x-rpi-usb-otg.dtsi"

	/ {
	compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
	model = "Raspberry Pi Zero W";

	memory@0 {
	device_type = "memory";
	reg = <0 0x20000000>;
	};

	chosen {
	/* 8250 auxiliary UART instead of pl011 */
	stdout-path = "serial1:115200n8";
	};

	leds {
	act {
	- gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
	+ gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
	};
	};

	wifi_pwrseq: wifi-pwrseq {
	compatible = "mmc-pwrseq-simple";
	reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
	};
	};

	&gpio {
	/*
	* This is based on the official GPU firmware DT blob.
	*
	* Legend:
	* "NC" = not connected (no rail from the SoC)
	* "FOO" = GPIO line named "FOO" on the schematic
	* "FOO_N" = GPIO line named "FOO" on schematic, active low
	*/
	gpio-line-names = "ID_SDA",
	"ID_SCL",
	"SDA1",
	"SCL1",
	"GPIO_GCLK",
	"GPIO5",
	"GPIO6",
	"SPI_CE1_N",
	"SPI_CE0_N",
	"SPI_MISO",
	"SPI_MOSI",
	"SPI_SCLK",
	"GPIO12",
	"GPIO13",
	/* Serial port */
	"TXD0",
	"RXD0",
	"GPIO16",
	"GPIO17",
	"GPIO18",
	"GPIO19",
	"GPIO20",
	"GPIO21",
	"GPIO22",
	"GPIO23",
	"GPIO24",
	"GPIO25",
	"GPIO26",
	"GPIO27",
	"SDA0",
	"SCL0",
	"NC", /* GPIO30 */
	"NC", /* GPIO31 */
	"NC", /* GPIO32 */
	"NC", /* GPIO33 */
	"NC", /* GPIO34 */
	"NC", /* GPIO35 */
	"NC", /* GPIO36 */
	"NC", /* GPIO37 */
	"NC", /* GPIO38 */
	"NC", /* GPIO39 */
	"CAM_GPIO1", /* GPIO40 */
	"WL_ON", /* GPIO41 */
	"NC", /* GPIO42 */
	"WIFI_CLK", /* GPIO43 */
	"CAM_GPIO0", /* GPIO44 */
	"BT_ON", /* GPIO45 */
	"HDMI_HPD_N",
	"STATUS_LED_N",
	/* Used by SD Card */
	"SD_CLK_R",
	"SD_CMD_R",
	"SD_DATA0_R",
	"SD_DATA1_R",
	"SD_DATA2_R",
	"SD_DATA3_R";

	pinctrl-0 = <&gpioout &alt0>;
	};

	&hdmi {
	hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
	power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
	status = "okay";
	};

	&sdhci {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
	bus-width = <4>;
	mmc-pwrseq = <&wifi_pwrseq>;
	non-removable;
	status = "okay";

	brcmf: wifi@1 {
	reg = <1>;
	compatible = "brcm,bcm4329-fmac";
	};
	};

	&sdhost {
	pinctrl-names = "default";
	pinctrl-0 = <&sdhost_gpio48>;
	bus-width = <4>;
	status = "okay";
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>;
	status = "okay";

	bluetooth {
	compatible = "brcm,bcm43438-bt";
	max-speed = <2000000>;
	shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
	};
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_gpio14>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/bcm2835-rpi.dtsi b/sys/gnu/dts/arm/bcm2835-rpi.dtsi
	index fd2c766e0f71..f7ae5a4530b8 100644
	--- a/sys/gnu/dts/arm/bcm2835-rpi.dtsi
	+++ b/sys/gnu/dts/arm/bcm2835-rpi.dtsi
	@@ -1,78 +1,81 @@
	#include <dt-bindings/power/raspberrypi-power.h>

	/ {
	leds {
	compatible = "gpio-leds";

	act {
	label = "ACT";
	default-state = "keep";
	linux,default-trigger = "heartbeat";
	};
	};

	soc {
	firmware: firmware {
	compatible = "raspberrypi,bcm2835-firmware", "simple-bus";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+
	mboxes = <&mailbox>;
	dma-ranges;
	};

	power: power {
	compatible = "raspberrypi,bcm2835-power";
	firmware = <&firmware>;
	#power-domain-cells = <1>;
	};

	vchiq: mailbox@7e00b840 {
	compatible = "brcm,bcm2835-vchiq";
	reg = <0x7e00b840 0x3c>;
	interrupts = <0 2>;
	};
	};
	};

	&gpio {
	pinctrl-names = "default";

	gpioout: gpioout {
	brcm,pins = <6>;
	brcm,function = <BCM2835_FSEL_GPIO_OUT>;
	};

	alt0: alt0 {
	brcm,pins = <4 5 7 8 9 10 11>;
	brcm,function = <BCM2835_FSEL_ALT0>;
	};
	};

	&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_gpio0>;
	status = "okay";
	clock-frequency = <100000>;
	};

	&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_gpio2>;
	status = "okay";
	clock-frequency = <100000>;
	};

	&usb {
	power-domains = <&power RPI_POWER_DOMAIN_USB>;
	};

	&vec {
	power-domains = <&power RPI_POWER_DOMAIN_VEC>;
	status = "okay";
	};

	&dsi0 {
	power-domains = <&power RPI_POWER_DOMAIN_DSI0>;
	};

	&dsi1 {
	power-domains = <&power RPI_POWER_DOMAIN_DSI1>;
	};
	diff --git a/sys/gnu/dts/arm/bcm283x.dtsi b/sys/gnu/dts/arm/bcm283x.dtsi
	index e1abe8c730ce..b83a864e2e8b 100644
	--- a/sys/gnu/dts/arm/bcm283x.dtsi
	+++ b/sys/gnu/dts/arm/bcm283x.dtsi
	@@ -1,508 +1,509 @@
	#include <dt-bindings/pinctrl/bcm2835.h>
	#include <dt-bindings/clock/bcm2835.h>
	#include <dt-bindings/clock/bcm2835-aux.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/soc/bcm2835-pm.h>

	/* firmware-provided startup stubs live here, where the secondary CPUs are
	* spinning.
	*/
	/memreserve/ 0x00000000 0x00001000;

	/* This include file covers the common peripherals and configuration between
	* bcm2835 and bcm2836 implementations, leaving the CPU configuration to
	* bcm2835.dtsi and bcm2836.dtsi.
	*/

	/ {
	compatible = "brcm,bcm2835";
	model = "BCM2835";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
	serial0 = &uart0;
	serial1 = &uart1;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	rmem: reserved-memory {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	cma: linux,cma {
	compatible = "shared-dma-pool";
	size = <0x4000000>; /* 64MB */
	reusable;
	linux,cma-default;
	};
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	polling-delay-passive = <0>;
	polling-delay = <1000>;

	trips {
	cpu-crit {
	temperature = <90000>;
	hysteresis = <0>;
	type = "critical";
	};
	};

	cooling-maps {
	};
	};
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;

	system_timer: timer@7e003000 {
	compatible = "brcm,bcm2835-system-timer";
	reg = <0x7e003000 0x1000>;
	interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
	/* This could be a reference to BCM2835_CLOCK_TIMER,
	* but we don't have the driver using the common clock
	* support yet.
	*/
	clock-frequency = <1000000>;
	};

	txp: txp@7e004000 {
	compatible = "brcm,bcm2835-txp";
	reg = <0x7e004000 0x20>;
	interrupts = <1 11>;
	};

	clocks: cprman@7e101000 {
	compatible = "brcm,bcm2835-cprman";
	#clock-cells = <1>;
	reg = <0x7e101000 0x2000>;

	/* CPRMAN derives almost everything from the
	* platform's oscillator. However, the DSI
	* pixel clocks come from the DSI analog PHY.
	*/
	clocks = <&clk_osc>,
	<&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
	<&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
	};

	mailbox: mailbox@7e00b880 {
	compatible = "brcm,bcm2835-mbox";
	reg = <0x7e00b880 0x40>;
	interrupts = <0 1>;
	#mbox-cells = <0>;
	};

	gpio: gpio@7e200000 {
	compatible = "brcm,bcm2835-gpio";
	reg = <0x7e200000 0xb4>;
	/*
	* The GPIO IP block is designed for 3 banks of GPIOs.
	* Each bank has a GPIO interrupt for itself.
	* There is an overall "any bank" interrupt.
	* In order, these are GIC interrupts 17, 18, 19, 20.
	* Since the BCM2835 only has 2 banks, the 2nd bank
	* interrupt output appears to be mirrored onto the
	* 3rd bank's interrupt signal.
	* So, a bank0 interrupt shows up on 17, 20, and
	* a bank1 interrupt shows up on 18, 19, 20!
	*/
	interrupts = <2 17>, <2 18>, <2 19>, <2 20>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;

	/* Defines common pin muxing groups
	*
	* While each pin can have its mux selected
	* for various functions individually, some
	* groups only make sense to switch to a
	* particular function together.
	*/
	dpi_gpio0: dpi_gpio0 {
	brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
	12 13 14 15 16 17 18 19
	20 21 22 23 24 25 26 27>;
	brcm,function = <BCM2835_FSEL_ALT2>;
	};
	emmc_gpio22: emmc_gpio22 {
	brcm,pins = <22 23 24 25 26 27>;
	brcm,function = <BCM2835_FSEL_ALT3>;
	};
	emmc_gpio34: emmc_gpio34 {
	brcm,pins = <34 35 36 37 38 39>;
	brcm,function = <BCM2835_FSEL_ALT3>;
	brcm,pull = <BCM2835_PUD_OFF
	BCM2835_PUD_UP
	BCM2835_PUD_UP
	BCM2835_PUD_UP
	BCM2835_PUD_UP
	BCM2835_PUD_UP>;
	};
	emmc_gpio48: emmc_gpio48 {
	brcm,pins = <48 49 50 51 52 53>;
	brcm,function = <BCM2835_FSEL_ALT3>;
	};

	gpclk0_gpio4: gpclk0_gpio4 {
	brcm,pins = <4>;
	brcm,function = <BCM2835_FSEL_ALT0>;
	};
	gpclk1_gpio5: gpclk1_gpio5 {
	brcm,pins = <5>;
	brcm,function = <BCM2835_FSEL_ALT0>;
	};
	gpclk1_gpio42: gpclk1_gpio42 {
	brcm,pins = <42>;
	brcm,function = <BCM2835_FSEL_ALT0>;
	};
	gpclk1_gpio44: gpclk1_gpio44 {
	brcm,pins = <44>;
	brcm,function = <BCM2835_FSEL_ALT0>;
	};
	gpclk2_gpio6: gpclk2_gpio6 {
	brcm,pins = <6>;
	brcm,function = <BCM2835_FSEL_ALT0>;
	};
	gpclk2_gpio43: gpclk2_gpio43 {
	brcm,pins = <43>;
	brcm,function = <BCM2835_FSEL_ALT0>;
	brcm,pull = <BCM2835_PUD_OFF>;
	};

	i2c0_gpio0: i2c0_gpio0 {
	brcm,pins = <0 1>;
	brcm,function = <BCM2835_FSEL_ALT0>;
	};
	i2c0_gpio28: i2c0_gpio28 {
	brcm,pins = <28 29>;
	brcm,function = <BCM2835_FSEL_ALT0>;
	};
	i2c0_gpio44: i2c0_gpio44 {
	brcm,pins = <44 45>;
	brcm,function = <BCM2835_FSEL_ALT1>;
	};
	i2c1_gpio2: i2c1_gpio2 {
	brcm,pins = <2 3>;
	brcm,function = <BCM2835_FSEL_ALT0>;
	};
	i2c1_gpio44: i2c1_gpio44 {
	brcm,pins = <44 45>;
	brcm,function = <BCM2835_FSEL_ALT2>;
	};

	jtag_gpio22: jtag_gpio22 {
	brcm,pins = <22 23 24 25 26 27>;
	brcm,function = <BCM2835_FSEL_ALT4>;
	};

	pcm_gpio18: pcm_gpio18 {
	brcm,pins = <18 19 20 21>;
	brcm,function = <BCM2835_FSEL_ALT0>;
	};
	pcm_gpio28: pcm_gpio28 {
	brcm,pins = <28 29 30 31>;
	brcm,function = <BCM2835_FSEL_ALT2>;
	};

	sdhost_gpio48: sdhost_gpio48 {
	brcm,pins = <48 49 50 51 52 53>;
	brcm,function = <BCM2835_FSEL_ALT0>;
	};

	spi0_gpio7: spi0_gpio7 {
	brcm,pins = <7 8 9 10 11>;
	brcm,function = <BCM2835_FSEL_ALT0>;
	};
	spi0_gpio35: spi0_gpio35 {
	brcm,pins = <35 36 37 38 39>;
	brcm,function = <BCM2835_FSEL_ALT0>;
	};
	spi1_gpio16: spi1_gpio16 {
	brcm,pins = <16 17 18 19 20 21>;
	brcm,function = <BCM2835_FSEL_ALT4>;
	};
	spi2_gpio40: spi2_gpio40 {
	brcm,pins = <40 41 42 43 44 45>;
	brcm,function = <BCM2835_FSEL_ALT4>;
	};

	uart0_gpio14: uart0_gpio14 {
	brcm,pins = <14 15>;
	brcm,function = <BCM2835_FSEL_ALT0>;
	};
	/* Separate from the uart0_gpio14 group
	* because it conflicts with spi1_gpio16, and
	* people often run uart0 on the two pins
	* without flow control.
	*/
	uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
	brcm,pins = <16 17>;
	brcm,function = <BCM2835_FSEL_ALT3>;
	};
	uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
	brcm,pins = <30 31>;
	brcm,function = <BCM2835_FSEL_ALT3>;
	brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
	};
	uart0_gpio32: uart0_gpio32 {
	brcm,pins = <32 33>;
	brcm,function = <BCM2835_FSEL_ALT3>;
	brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
	};
	uart0_gpio36: uart0_gpio36 {
	brcm,pins = <36 37>;
	brcm,function = <BCM2835_FSEL_ALT2>;
	};
	uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
	brcm,pins = <38 39>;
	brcm,function = <BCM2835_FSEL_ALT2>;
	};

	uart1_gpio14: uart1_gpio14 {
	brcm,pins = <14 15>;
	brcm,function = <BCM2835_FSEL_ALT5>;
	};
	uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
	brcm,pins = <16 17>;
	brcm,function = <BCM2835_FSEL_ALT5>;
	};
	uart1_gpio32: uart1_gpio32 {
	brcm,pins = <32 33>;
	brcm,function = <BCM2835_FSEL_ALT5>;
	};
	uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
	brcm,pins = <30 31>;
	brcm,function = <BCM2835_FSEL_ALT5>;
	};
	uart1_gpio40: uart1_gpio40 {
	brcm,pins = <40 41>;
	brcm,function = <BCM2835_FSEL_ALT5>;
	};
	uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
	brcm,pins = <42 43>;
	brcm,function = <BCM2835_FSEL_ALT5>;
	};
	};

	uart0: serial@7e201000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x7e201000 0x200>;
	interrupts = <2 25>;
	clocks = <&clocks BCM2835_CLOCK_UART>,
	<&clocks BCM2835_CLOCK_VPU>;
	clock-names = "uartclk", "apb_pclk";
	arm,primecell-periphid = <0x00241011>;
	};

	sdhost: mmc@7e202000 {
	compatible = "brcm,bcm2835-sdhost";
	reg = <0x7e202000 0x100>;
	interrupts = <2 24>;
	clocks = <&clocks BCM2835_CLOCK_VPU>;
	status = "disabled";
	};

	i2s: i2s@7e203000 {
	compatible = "brcm,bcm2835-i2s";
	reg = <0x7e203000 0x24>;
	clocks = <&clocks BCM2835_CLOCK_PCM>;
	status = "disabled";
	};

	spi: spi@7e204000 {
	compatible = "brcm,bcm2835-spi";
	reg = <0x7e204000 0x200>;
	interrupts = <2 22>;
	clocks = <&clocks BCM2835_CLOCK_VPU>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c0: i2c@7e205000 {
	compatible = "brcm,bcm2835-i2c";
	reg = <0x7e205000 0x200>;
	interrupts = <2 21>;
	clocks = <&clocks BCM2835_CLOCK_VPU>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	dpi: dpi@7e208000 {
	compatible = "brcm,bcm2835-dpi";
	reg = <0x7e208000 0x8c>;
	clocks = <&clocks BCM2835_CLOCK_VPU>,
	<&clocks BCM2835_CLOCK_DPI>;
	clock-names = "core", "pixel";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	dsi0: dsi@7e209000 {
	compatible = "brcm,bcm2835-dsi0";
	reg = <0x7e209000 0x78>;
	interrupts = <2 4>;
	#address-cells = <1>;
	#size-cells = <0>;
	#clock-cells = <1>;

	clocks = <&clocks BCM2835_PLLA_DSI0>,
	<&clocks BCM2835_CLOCK_DSI0E>,
	<&clocks BCM2835_CLOCK_DSI0P>;
	clock-names = "phy", "escape", "pixel";

	clock-output-names = "dsi0_byte",
	"dsi0_ddr2",
	"dsi0_ddr";

	+ status = "disabled";
	};

	aux: aux@7e215000 {
	compatible = "brcm,bcm2835-aux";
	#clock-cells = <1>;
	reg = <0x7e215000 0x8>;
	clocks = <&clocks BCM2835_CLOCK_VPU>;
	};

	uart1: serial@7e215040 {
	compatible = "brcm,bcm2835-aux-uart";
	reg = <0x7e215040 0x40>;
	interrupts = <1 29>;
	clocks = <&aux BCM2835_AUX_CLOCK_UART>;
	status = "disabled";
	};

	spi1: spi@7e215080 {
	compatible = "brcm,bcm2835-aux-spi";
	reg = <0x7e215080 0x40>;
	interrupts = <1 29>;
	clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi2: spi@7e2150c0 {
	compatible = "brcm,bcm2835-aux-spi";
	reg = <0x7e2150c0 0x40>;
	interrupts = <1 29>;
	clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	pwm: pwm@7e20c000 {
	compatible = "brcm,bcm2835-pwm";
	reg = <0x7e20c000 0x28>;
	clocks = <&clocks BCM2835_CLOCK_PWM>;
	assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
	assigned-clock-rates = <10000000>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	sdhci: sdhci@7e300000 {
	compatible = "brcm,bcm2835-sdhci";
	reg = <0x7e300000 0x100>;
	interrupts = <2 30>;
	clocks = <&clocks BCM2835_CLOCK_EMMC>;
	status = "disabled";
	};

	hvs@7e400000 {
	compatible = "brcm,bcm2835-hvs";
	reg = <0x7e400000 0x6000>;
	interrupts = <2 1>;
	};

	dsi1: dsi@7e700000 {
	compatible = "brcm,bcm2835-dsi1";
	reg = <0x7e700000 0x8c>;
	interrupts = <2 12>;
	#address-cells = <1>;
	#size-cells = <0>;
	#clock-cells = <1>;

	clocks = <&clocks BCM2835_PLLD_DSI1>,
	<&clocks BCM2835_CLOCK_DSI1E>,
	<&clocks BCM2835_CLOCK_DSI1P>;
	clock-names = "phy", "escape", "pixel";

	clock-output-names = "dsi1_byte",
	"dsi1_ddr2",
	"dsi1_ddr";

	status = "disabled";
	};

	i2c1: i2c@7e804000 {
	compatible = "brcm,bcm2835-i2c";
	reg = <0x7e804000 0x1000>;
	interrupts = <2 21>;
	clocks = <&clocks BCM2835_CLOCK_VPU>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	vec: vec@7e806000 {
	compatible = "brcm,bcm2835-vec";
	reg = <0x7e806000 0x1000>;
	clocks = <&clocks BCM2835_CLOCK_VEC>;
	interrupts = <2 27>;
	status = "disabled";
	};

	usb: usb@7e980000 {
	compatible = "brcm,bcm2835-usb";
	reg = <0x7e980000 0x10000>;
	interrupts = <1 9>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&clk_usb>;
	clock-names = "otg";
	phys = <&usbphy>;
	phy-names = "usb2-phy";
	};
	};

	clocks {
	/* The oscillator is the root of the clock tree. */
	clk_osc: clk-osc {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-output-names = "osc";
	clock-frequency = <19200000>;
	};

	clk_usb: clk-usb {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-output-names = "otg";
	clock-frequency = <480000000>;
	};
	};

	usbphy: phy {
	compatible = "usb-nop-xceiv";
	#phy-cells = <0>;
	};
	};
	diff --git a/sys/gnu/dts/arm/dm814x-clocks.dtsi b/sys/gnu/dts/arm/dm814x-clocks.dtsi
	index e5e4d0affefa..f7939f43413b 100644
	--- a/sys/gnu/dts/arm/dm814x-clocks.dtsi
	+++ b/sys/gnu/dts/arm/dm814x-clocks.dtsi
	@@ -1,365 +1,379 @@
	// SPDX-License-Identifier: GPL-2.0-only

	&pllss {
	/*
	* See TRM "2.6.10 Connected outputso DPLLS" and
	* "2.6.11 Connected Outputs of DPLLJ". Only clkout is
	* connected except for hdmi and usb.
	*/
	adpll_mpu_ck: adpll@40 {
	#clock-cells = <1>;
	compatible = "ti,dm814-adpll-s-clock";
	reg = <0x40 0x40>;
	clocks = <&devosc_ck &devosc_ck &devosc_ck>;
	clock-names = "clkinp", "clkinpulow", "clkinphif";
	clock-output-names = "481c5040.adpll.dcoclkldo",
	"481c5040.adpll.clkout",
	"481c5040.adpll.clkoutx2",
	"481c5040.adpll.clkouthif";
	};

	adpll_dsp_ck: adpll@80 {
	#clock-cells = <1>;
	compatible = "ti,dm814-adpll-lj-clock";
	reg = <0x80 0x30>;
	clocks = <&devosc_ck &devosc_ck>;
	clock-names = "clkinp", "clkinpulow";
	clock-output-names = "481c5080.adpll.dcoclkldo",
	"481c5080.adpll.clkout",
	"481c5080.adpll.clkoutldo";
	};

	adpll_sgx_ck: adpll@b0 {
	#clock-cells = <1>;
	compatible = "ti,dm814-adpll-lj-clock";
	reg = <0xb0 0x30>;
	clocks = <&devosc_ck &devosc_ck>;
	clock-names = "clkinp", "clkinpulow";
	clock-output-names = "481c50b0.adpll.dcoclkldo",
	"481c50b0.adpll.clkout",
	"481c50b0.adpll.clkoutldo";
	};

	adpll_hdvic_ck: adpll@e0 {
	#clock-cells = <1>;
	compatible = "ti,dm814-adpll-lj-clock";
	reg = <0xe0 0x30>;
	clocks = <&devosc_ck &devosc_ck>;
	clock-names = "clkinp", "clkinpulow";
	clock-output-names = "481c50e0.adpll.dcoclkldo",
	"481c50e0.adpll.clkout",
	"481c50e0.adpll.clkoutldo";
	};

	adpll_l3_ck: adpll@110 {
	#clock-cells = <1>;
	compatible = "ti,dm814-adpll-lj-clock";
	reg = <0x110 0x30>;
	clocks = <&devosc_ck &devosc_ck>;
	clock-names = "clkinp", "clkinpulow";
	clock-output-names = "481c5110.adpll.dcoclkldo",
	"481c5110.adpll.clkout",
	"481c5110.adpll.clkoutldo";
	};

	adpll_isp_ck: adpll@140 {
	#clock-cells = <1>;
	compatible = "ti,dm814-adpll-lj-clock";
	reg = <0x140 0x30>;
	clocks = <&devosc_ck &devosc_ck>;
	clock-names = "clkinp", "clkinpulow";
	clock-output-names = "481c5140.adpll.dcoclkldo",
	"481c5140.adpll.clkout",
	"481c5140.adpll.clkoutldo";
	};

	adpll_dss_ck: adpll@170 {
	#clock-cells = <1>;
	compatible = "ti,dm814-adpll-lj-clock";
	reg = <0x170 0x30>;
	clocks = <&devosc_ck &devosc_ck>;
	clock-names = "clkinp", "clkinpulow";
	clock-output-names = "481c5170.adpll.dcoclkldo",
	"481c5170.adpll.clkout",
	"481c5170.adpll.clkoutldo";
	};

	adpll_video0_ck: adpll@1a0 {
	#clock-cells = <1>;
	compatible = "ti,dm814-adpll-lj-clock";
	reg = <0x1a0 0x30>;
	clocks = <&devosc_ck &devosc_ck>;
	clock-names = "clkinp", "clkinpulow";
	clock-output-names = "481c51a0.adpll.dcoclkldo",
	"481c51a0.adpll.clkout",
	"481c51a0.adpll.clkoutldo";
	};

	adpll_video1_ck: adpll@1d0 {
	#clock-cells = <1>;
	compatible = "ti,dm814-adpll-lj-clock";
	reg = <0x1d0 0x30>;
	clocks = <&devosc_ck &devosc_ck>;
	clock-names = "clkinp", "clkinpulow";
	clock-output-names = "481c51d0.adpll.dcoclkldo",
	"481c51d0.adpll.clkout",
	"481c51d0.adpll.clkoutldo";
	};

	adpll_hdmi_ck: adpll@200 {
	#clock-cells = <1>;
	compatible = "ti,dm814-adpll-lj-clock";
	reg = <0x200 0x30>;
	clocks = <&devosc_ck &devosc_ck>;
	clock-names = "clkinp", "clkinpulow";
	clock-output-names = "481c5200.adpll.dcoclkldo",
	"481c5200.adpll.clkout",
	"481c5200.adpll.clkoutldo";
	};

	adpll_audio_ck: adpll@230 {
	#clock-cells = <1>;
	compatible = "ti,dm814-adpll-lj-clock";
	reg = <0x230 0x30>;
	clocks = <&devosc_ck &devosc_ck>;
	clock-names = "clkinp", "clkinpulow";
	clock-output-names = "481c5230.adpll.dcoclkldo",
	"481c5230.adpll.clkout",
	"481c5230.adpll.clkoutldo";
	};

	adpll_usb_ck: adpll@260 {
	#clock-cells = <1>;
	compatible = "ti,dm814-adpll-lj-clock";
	reg = <0x260 0x30>;
	clocks = <&devosc_ck &devosc_ck>;
	clock-names = "clkinp", "clkinpulow";
	clock-output-names = "481c5260.adpll.dcoclkldo",
	"481c5260.adpll.clkout",
	"481c5260.adpll.clkoutldo";
	};

	adpll_ddr_ck: adpll@290 {
	#clock-cells = <1>;
	compatible = "ti,dm814-adpll-lj-clock";
	reg = <0x290 0x30>;
	clocks = <&devosc_ck &devosc_ck>;
	clock-names = "clkinp", "clkinpulow";
	clock-output-names = "481c5290.adpll.dcoclkldo",
	"481c5290.adpll.clkout",
	"481c5290.adpll.clkoutldo";
	};
	};

	&pllss_clocks {
	timer1_fck: timer1_fck@2e0 {
	#clock-cells = <0>;
	compatible = "ti,mux-clock";
	clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
	&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
	ti,bit-shift = <3>;
	reg = <0x2e0>;
	};

	timer2_fck: timer2_fck@2e0 {
	#clock-cells = <0>;
	compatible = "ti,mux-clock";
	clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
	&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
	ti,bit-shift = <6>;
	reg = <0x2e0>;
	};

	/* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */
	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
	#clock-cells = <0>;
	compatible = "ti,mux-clock";
	clocks = <&adpll_video0_ck 1
	&adpll_video1_ck 1
	&adpll_audio_ck 1>;
	ti,bit-shift = <1>;
	reg = <0x2e8>;
	};

	/* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */
	cpsw_125mhz_gclk: cpsw_125mhz_gclk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <125000000>;
	};

	sysclk18_ck: sysclk18_ck@2f0 {
	#clock-cells = <0>;
	compatible = "ti,mux-clock";
	clocks = <&rtcosc_ck>, <&rtcdivider_ck>;
	ti,bit-shift = <0>;
	reg = <0x02f0>;
	};
	};

	&scm_clocks {
	devosc_ck: devosc_ck@40 {
	#clock-cells = <0>;
	compatible = "ti,mux-clock";
	clocks = <&virt_20000000_ck>, <&virt_19200000_ck>;
	ti,bit-shift = <21>;
	reg = <0x0040>;
	};

	/* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */
	auxosc_ck: auxosc_ck {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <22572900>;
	};

	/* Optional 32768Hz crystal or clock on RTCOSC pins */
	rtcosc_ck: rtcosc_ck {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	};

	/* Optional external clock on TCLKIN pin, set rate in baord dts file */
	tclkin_ck: tclkin_ck {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <0>;
	};

	virt_20000000_ck: virt_20000000_ck {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <20000000>;
	};

	virt_19200000_ck: virt_19200000_ck {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <19200000>;
	};

	mpu_ck: mpu_ck {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <1000000000>;
	};
	};

	&prcm_clocks {
	osc_src_ck: osc_src_ck {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clocks = <&devosc_ck>;
	clock-mult = <1>;
	clock-div = <1>;
	};

	mpu_clksrc_ck: mpu_clksrc_ck@40 {
	#clock-cells = <0>;
	compatible = "ti,mux-clock";
	clocks = <&devosc_ck>, <&rtcdivider_ck>;
	ti,bit-shift = <0>;
	reg = <0x0040>;
	};

	/* Fixed divider clock 0.0016384 * devosc */
	rtcdivider_ck: rtcdivider_ck {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clocks = <&devosc_ck>;
	clock-mult = <128>;
	clock-div = <78125>;
	};

	/* L4_HS 220 MHz*/
	sysclk4_ck: sysclk4_ck {
	#clock-cells = <0>;
	compatible = "ti,fixed-factor-clock";
	clocks = <&adpll_l3_ck 1>;
	ti,clock-mult = <1>;
	ti,clock-div = <1>;
	};

	/* L4_FWCFG */
	sysclk5_ck: sysclk5_ck {
	#clock-cells = <0>;
	compatible = "ti,fixed-factor-clock";
	clocks = <&adpll_l3_ck 1>;
	ti,clock-mult = <1>;
	ti,clock-div = <2>;
	};

	/* L4_LS 110 MHz */
	sysclk6_ck: sysclk6_ck {
	#clock-cells = <0>;
	compatible = "ti,fixed-factor-clock";
	clocks = <&adpll_l3_ck 1>;
	ti,clock-mult = <1>;
	ti,clock-div = <2>;
	};

	sysclk8_ck: sysclk8_ck {
	#clock-cells = <0>;
	compatible = "ti,fixed-factor-clock";
	clocks = <&adpll_usb_ck 1>;
	ti,clock-mult = <1>;
	ti,clock-div = <1>;
	};

	sysclk10_ck: sysclk10_ck {
	compatible = "ti,divider-clock";
	reg = <0x324>;
	ti,max-div = <7>;
	#clock-cells = <0>;
	clocks = <&adpll_usb_ck 1>;
	};

	aud_clkin0_ck: aud_clkin0_ck {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <20000000>;
	};

	aud_clkin1_ck: aud_clkin1_ck {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <20000000>;
	};

	aud_clkin2_ck: aud_clkin2_ck {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <20000000>;
	};
	};

	&prcm {
	default_cm: default_cm@500 {
	compatible = "ti,omap4-cm";
	reg = <0x500 0x100>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x500 0x100>;

	default_clkctrl: clk@0 {
	compatible = "ti,clkctrl";
	reg = <0x0 0x5c>;
	#clock-cells = <2>;
	};
	};

	alwon_cm: alwon_cm@1400 {
	compatible = "ti,omap4-cm";
	reg = <0x1400 0x300>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x1400 0x300>;

	alwon_clkctrl: clk@0 {
	compatible = "ti,clkctrl";
	reg = <0x0 0x228>;
	#clock-cells = <2>;
	};
	};
	+
	+ alwon_ethernet_cm: alwon_ethernet_cm@15d4 {
	+ compatible = "ti,omap4-cm";
	+ reg = <0x15d4 0x4>;
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x15d4 0x4>;
	+
	+ alwon_ethernet_clkctrl: clk@0 {
	+ compatible = "ti,clkctrl";
	+ reg = <0 0x4>;
	+ #clock-cells = <2>;
	+ };
	+ };
	};
	diff --git a/sys/gnu/dts/arm/dm814x.dtsi b/sys/gnu/dts/arm/dm814x.dtsi
	index 95de9f214c14..c28ca0540f03 100644
	--- a/sys/gnu/dts/arm/dm814x.dtsi
	+++ b/sys/gnu/dts/arm/dm814x.dtsi
	@@ -1,649 +1,737 @@
	/*
	* This file is licensed under the terms of the GNU General Public License
	* version 2. This program is licensed "as is" without any warranty of any
	* kind, whether express or implied.
	*/

	+#include <dt-bindings/bus/ti-sysc.h>
	+#include <dt-bindings/clock/dm814.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/pinctrl/dm814x.h>

	/ {
	compatible = "ti,dm814";
	interrupt-parent = <&intc>;
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };

	aliases {
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	ethernet0 = &cpsw_emac0;
	ethernet1 = &cpsw_emac1;
	usb0 = &usb0;
	usb1 = &usb1;
	phy0 = &usb0_phy;
	phy1 = &usb1_phy;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	cpu@0 {
	compatible = "arm,cortex-a8";
	device_type = "cpu";
	reg = <0>;
	};
	};

	pmu {
	compatible = "arm,cortex-a8-pmu";
	interrupts = <3>;
	};

	/*
	* The soc node represents the soc top level view. It is used for IPs
	* that are not memory mapped in the MPU view or for the MPU itself.
	*/
	soc {
	compatible = "ti,omap-infra";
	mpu {
	compatible = "ti,omap3-mpu";
	ti,hwmods = "mpu";
	};
	};

	ocp {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	ti,hwmods = "l3_main";

	usb: usb@47400000 {
	compatible = "ti,am33xx-usb";
	reg = <0x47400000 0x1000>;
	ranges;
	#address-cells = <1>;
	#size-cells = <1>;
	ti,hwmods = "usb_otg_hs";

	usb0_phy: usb-phy@47401300 {
	compatible = "ti,am335x-usb-phy";
	reg = <0x47401300 0x100>;
	reg-names = "phy";
	ti,ctrl_mod = <&usb_ctrl_mod>;
	#phy-cells = <0>;
	};

	usb0: usb@47401000 {
	compatible = "ti,musb-am33xx";
	reg = <0x47401400 0x400
	0x47401000 0x200>;
	reg-names = "mc", "control";

	interrupts = <18>;
	interrupt-names = "mc";
	dr_mode = "otg";
	mentor,multipoint = <1>;
	mentor,num-eps = <16>;
	mentor,ram-bits = <12>;
	mentor,power = <500>;
	phys = <&usb0_phy>;

	dmas = <&cppi41dma 0 0 &cppi41dma 1 0
	&cppi41dma 2 0 &cppi41dma 3 0
	&cppi41dma 4 0 &cppi41dma 5 0
	&cppi41dma 6 0 &cppi41dma 7 0
	&cppi41dma 8 0 &cppi41dma 9 0
	&cppi41dma 10 0 &cppi41dma 11 0
	&cppi41dma 12 0 &cppi41dma 13 0
	&cppi41dma 14 0 &cppi41dma 0 1
	&cppi41dma 1 1 &cppi41dma 2 1
	&cppi41dma 3 1 &cppi41dma 4 1
	&cppi41dma 5 1 &cppi41dma 6 1
	&cppi41dma 7 1 &cppi41dma 8 1
	&cppi41dma 9 1 &cppi41dma 10 1
	&cppi41dma 11 1 &cppi41dma 12 1
	&cppi41dma 13 1 &cppi41dma 14 1>;
	dma-names =
	"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
	"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
	"rx14", "rx15",
	"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
	"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
	"tx14", "tx15";
	};

	usb1: usb@47401800 {
	compatible = "ti,musb-am33xx";
	reg = <0x47401c00 0x400
	0x47401800 0x200>;
	reg-names = "mc", "control";
	interrupts = <19>;
	interrupt-names = "mc";
	dr_mode = "otg";
	mentor,multipoint = <1>;
	mentor,num-eps = <16>;
	mentor,ram-bits = <12>;
	mentor,power = <500>;
	phys = <&usb1_phy>;

	dmas = <&cppi41dma 15 0 &cppi41dma 16 0
	&cppi41dma 17 0 &cppi41dma 18 0
	&cppi41dma 19 0 &cppi41dma 20 0
	&cppi41dma 21 0 &cppi41dma 22 0
	&cppi41dma 23 0 &cppi41dma 24 0
	&cppi41dma 25 0 &cppi41dma 26 0
	&cppi41dma 27 0 &cppi41dma 28 0
	&cppi41dma 29 0 &cppi41dma 15 1
	&cppi41dma 16 1 &cppi41dma 17 1
	&cppi41dma 18 1 &cppi41dma 19 1
	&cppi41dma 20 1 &cppi41dma 21 1
	&cppi41dma 22 1 &cppi41dma 23 1
	&cppi41dma 24 1 &cppi41dma 25 1
	&cppi41dma 26 1 &cppi41dma 27 1
	&cppi41dma 28 1 &cppi41dma 29 1>;
	dma-names =
	"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
	"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
	"rx14", "rx15",
	"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
	"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
	"tx14", "tx15";
	};

	cppi41dma: dma-controller@47402000 {
	compatible = "ti,am3359-cppi41";
	reg = <0x47400000 0x1000
	0x47402000 0x1000
	0x47403000 0x1000
	0x47404000 0x4000>;
	reg-names = "glue", "controller", "scheduler", "queuemgr";
	interrupts = <17>;
	interrupt-names = "glue";
	#dma-cells = <2>;
	#dma-channels = <30>;
	#dma-requests = <256>;
	};
	};

	/*
	* See TRM "Table 1-317. L4LS Instance Summary" for hints.
	* It shows the module target agent registers though, so the
	* actual device is typically 0x1000 before the target agent
	* except in cases where the module is larger than 0x1000.
	*/
	l4ls: l4ls@48000000 {
	compatible = "ti,dm814-l4ls", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x48000000 0x2000000>;

	i2c1: i2c@28000 {
	compatible = "ti,omap4-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	ti,hwmods = "i2c1";
	reg = <0x28000 0x1000>;
	interrupts = <70>;
	};

	elm: elm@80000 {
	compatible = "ti,814-elm";
	ti,hwmods = "elm";
	reg = <0x80000 0x2000>;
	interrupts = <4>;
	};

	gpio1: gpio@32000 {
	compatible = "ti,omap4-gpio";
	ti,hwmods = "gpio1";
	ti,gpio-always-on;
	reg = <0x32000 0x2000>;
	interrupts = <96>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio@4c000 {
	compatible = "ti,omap4-gpio";
	ti,hwmods = "gpio2";
	ti,gpio-always-on;
	reg = <0x4c000 0x2000>;
	interrupts = <98>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio@1ac000 {
	compatible = "ti,omap4-gpio";
	ti,hwmods = "gpio3";
	ti,gpio-always-on;
	reg = <0x1ac000 0x2000>;
	interrupts = <32>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio4: gpio@1ae000 {
	compatible = "ti,omap4-gpio";
	ti,hwmods = "gpio4";
	ti,gpio-always-on;
	reg = <0x1ae000 0x2000>;
	interrupts = <62>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	i2c2: i2c@2a000 {
	compatible = "ti,omap4-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	ti,hwmods = "i2c2";
	reg = <0x2a000 0x1000>;
	interrupts = <71>;
	};

	mcspi1: spi@30000 {
	compatible = "ti,omap4-mcspi";
	reg = <0x30000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <65>;
	ti,spi-num-cs = <4>;
	ti,hwmods = "mcspi1";
	dmas = <&edma 16 0 &edma 17 0
	&edma 18 0 &edma 19 0
	&edma 20 0 &edma 21 0
	&edma 22 0 &edma 23 0>;

	dma-names = "tx0", "rx0", "tx1", "rx1",
	"tx2", "rx2", "tx3", "rx3";
	};

	mcspi2: spi@1a0000 {
	compatible = "ti,omap4-mcspi";
	reg = <0x1a0000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <125>;
	ti,spi-num-cs = <4>;
	ti,hwmods = "mcspi2";
	dmas = <&edma 42 0 &edma 43 0
	&edma 44 0 &edma 45 0>;
	dma-names = "tx0", "rx0", "tx1", "rx1";
	};

	/* Board must configure dmas with edma_xbar for EDMA */
	mcspi3: spi@1a2000 {
	compatible = "ti,omap4-mcspi";
	reg = <0x1a2000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <126>;
	ti,spi-num-cs = <4>;
	ti,hwmods = "mcspi3";
	};

	mcspi4: spi@1a4000 {
	compatible = "ti,omap4-mcspi";
	reg = <0x1a4000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <127>;
	ti,spi-num-cs = <4>;
	ti,hwmods = "mcspi4";
	};

	timer1: timer@2e000 {
	compatible = "ti,dm814-timer";
	reg = <0x2e000 0x2000>;
	interrupts = <67>;
	ti,hwmods = "timer1";
	ti,timer-alwon;
	clocks = <&timer1_fck>;
	clock-names = "fck";
	};

	uart1: uart@20000 {
	compatible = "ti,am3352-uart", "ti,omap3-uart";
	ti,hwmods = "uart1";
	reg = <0x20000 0x2000>;
	clock-frequency = <48000000>;
	interrupts = <72>;
	dmas = <&edma 26 0 &edma 27 0>;
	dma-names = "tx", "rx";
	};

	uart2: uart@22000 {
	compatible = "ti,am3352-uart", "ti,omap3-uart";
	ti,hwmods = "uart2";
	reg = <0x22000 0x2000>;
	clock-frequency = <48000000>;
	interrupts = <73>;
	dmas = <&edma 28 0 &edma 29 0>;
	dma-names = "tx", "rx";
	};

	uart3: uart@24000 {
	compatible = "ti,am3352-uart", "ti,omap3-uart";
	ti,hwmods = "uart3";
	reg = <0x24000 0x2000>;
	clock-frequency = <48000000>;
	interrupts = <74>;
	dmas = <&edma 30 0 &edma 31 0>;
	dma-names = "tx", "rx";
	};

	timer2: timer@40000 {
	compatible = "ti,dm814-timer";
	reg = <0x40000 0x2000>;
	interrupts = <68>;
	ti,hwmods = "timer2";
	clocks = <&timer2_fck>;
	clock-names = "fck";
	};

	timer3: timer@42000 {
	compatible = "ti,dm814-timer";
	reg = <0x42000 0x2000>;
	interrupts = <69>;
	ti,hwmods = "timer3";
	};

	mmc1: mmc@60000 {
	compatible = "ti,omap4-hsmmc";
	ti,hwmods = "mmc1";
	dmas = <&edma 24 0
	&edma 25 0>;
	dma-names = "tx", "rx";
	interrupts = <64>;
	interrupt-parent = <&intc>;
	reg = <0x60000 0x1000>;
	};

	rtc: rtc@c0000 {
	compatible = "ti,am3352-rtc", "ti,da830-rtc";
	reg = <0xc0000 0x1000>;
	interrupts = <75 76>;
	ti,hwmods = "rtc";
	};

	mmc2: mmc@1d8000 {
	compatible = "ti,omap4-hsmmc";
	ti,hwmods = "mmc2";
	dmas = <&edma 2 0
	&edma 3 0>;
	dma-names = "tx", "rx";
	interrupts = <28>;
	interrupt-parent = <&intc>;
	reg = <0x1d8000 0x1000>;
	};

	control: control@140000 {
	compatible = "ti,dm814-scm", "simple-bus";
	reg = <0x140000 0x20000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x140000 0x20000>;

	scm_conf: scm_conf@0 {
	compatible = "syscon", "simple-bus";
	reg = <0x0 0x800>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x800>;

	phy_gmii_sel: phy-gmii-sel {
	compatible = "ti,dm814-phy-gmii-sel";
	reg = <0x650 0x4>;
	#phy-cells = <1>;
	};

	scm_clocks: clocks {
	#address-cells = <1>;
	#size-cells = <0>;
	};

	scm_clockdomains: clockdomains {
	};
	};

	usb_ctrl_mod: control@620 {
	compatible = "ti,am335x-usb-ctrl-module";
	reg = <0x620 0x10
	0x648 0x4>;
	reg-names = "phy_ctrl", "wakeup";
	};

	edma_xbar: dma-router@f90 {
	compatible = "ti,am335x-edma-crossbar";
	reg = <0xf90 0x40>;
	#dma-cells = <3>;
	dma-requests = <32>;
	dma-masters = <&edma>;
	};

	/*
	* Note that silicon revision 2.1 and older
	* require input enabled (bit 18 set) for all
	* 3.3V I/Os to avoid cumulative hardware damage.
	* For more info, see errata advisory 2.1.87.
	* We leave bit 18 out of function-mask and rely
	* on the bootloader for it.
	*/
	pincntl: pinmux@800 {
	compatible = "pinctrl-single";
	reg = <0x800 0x438>;
	#address-cells = <1>;
	#size-cells = <0>;
	#pinctrl-cells = <1>;
	pinctrl-single,register-width = <32>;
	pinctrl-single,function-mask = <0x307ff>;
	};

	usb1_phy: usb-phy@1b00 {
	compatible = "ti,am335x-usb-phy";
	reg = <0x1b00 0x100>;
	reg-names = "phy";
	ti,ctrl_mod = <&usb_ctrl_mod>;
	#phy-cells = <0>;
	};
	};

	prcm: prcm@180000 {
	compatible = "ti,dm814-prcm", "simple-bus";
	reg = <0x180000 0x2000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x180000 0x2000>;

	prcm_clocks: clocks {
	#address-cells = <1>;
	#size-cells = <0>;
	};

	prcm_clockdomains: clockdomains {
	};
	};

	/* See TRM PLL_SUBSYS_BASE and "PLLSS Registers" */
	pllss: pllss@1c5000 {
	compatible = "ti,dm814-pllss", "simple-bus";
	reg = <0x1c5000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x1c5000 0x1000>;

	pllss_clocks: clocks {
	#address-cells = <1>;
	#size-cells = <0>;
	};

	pllss_clockdomains: clockdomains {
	};
	};

	wdt1: wdt@1c7000 {
	compatible = "ti,omap3-wdt";
	ti,hwmods = "wd_timer";
	reg = <0x1c7000 0x1000>;
	interrupts = <91>;
	};
	};

	intc: interrupt-controller@48200000 {
	compatible = "ti,dm814-intc";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x48200000 0x1000>;
	};

	/* Board must configure evtmux with edma_xbar for EDMA */
	mmc3: mmc@47810000 {
	compatible = "ti,omap4-hsmmc";
	ti,hwmods = "mmc3";
	interrupts = <29>;
	interrupt-parent = <&intc>;
	reg = <0x47810000 0x1000>;
	};

	- edma: edma@49000000 {
	- compatible = "ti,edma3-tpcc";
	- ti,hwmods = "tpcc";
	- reg = <0x49000000 0x10000>;
	- reg-names = "edma3_cc";
	- interrupts = <12 13 14>;
	- interrupt-names = "edma3_ccint", "edma3_mperr",
	- "edma3_ccerrint";
	- dma-requests = <64>;
	- #dma-cells = <2>;
	-
	- ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
	- <&edma_tptc2 3>, <&edma_tptc3 0>;
	-
	- ti,edma-memcpy-channels = <20 21>;
	+ target-module@49000000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49000000 0x4>;
	+ reg-names = "rev";
	+ clocks = <&alwon_clkctrl DM814_TPCC_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49000000 0x10000>;
	+
	+ edma: dma@0 {
	+ compatible = "ti,edma3-tpcc";
	+ reg = <0 0x10000>;
	+ reg-names = "edma3_cc";
	+ interrupts = <12 13 14>;
	+ interrupt-names = "edma3_ccint", "edma3_mperr",
	+ "edma3_ccerrint";
	+ dma-requests = <64>;
	+ #dma-cells = <2>;
	+
	+ ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
	+ <&edma_tptc2 3>, <&edma_tptc3 0>;
	+
	+ ti,edma-memcpy-channels = <20 21>;
	+ };
	};

	- edma_tptc0: tptc@49800000 {
	- compatible = "ti,edma3-tptc";
	- ti,hwmods = "tptc0";
	- reg = <0x49800000 0x100000>;
	- interrupts = <112>;
	- interrupt-names = "edma3_tcerrint";
	+ target-module@49800000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49800000 0x4>,
	+ <0x49800010 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_SMART>;
	+ clocks = <&alwon_clkctrl DM814_TPTC0_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49800000 0x100000>;
	+
	+ edma_tptc0: dma@0 {
	+ compatible = "ti,edma3-tptc";
	+ reg = <0 0x100000>;
	+ interrupts = <112>;
	+ interrupt-names = "edma3_tcerrint";
	+ };
	};

	- edma_tptc1: tptc@49900000 {
	- compatible = "ti,edma3-tptc";
	- ti,hwmods = "tptc1";
	- reg = <0x49900000 0x100000>;
	- interrupts = <113>;
	- interrupt-names = "edma3_tcerrint";
	+ target-module@49900000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49900000 0x4>,
	+ <0x49900010 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_SMART>;
	+ clocks = <&alwon_clkctrl DM814_TPTC1_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49900000 0x100000>;
	+
	+ edma_tptc1: dma@0 {
	+ compatible = "ti,edma3-tptc";
	+ reg = <0 0x100000>;
	+ interrupts = <113>;
	+ interrupt-names = "edma3_tcerrint";
	+ };
	};

	- edma_tptc2: tptc@49a00000 {
	- compatible = "ti,edma3-tptc";
	- ti,hwmods = "tptc2";
	- reg = <0x49a00000 0x100000>;
	- interrupts = <114>;
	- interrupt-names = "edma3_tcerrint";
	+ target-module@49a00000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49a00000 0x4>,
	+ <0x49a00010 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_SMART>;
	+ clocks = <&alwon_clkctrl DM814_TPTC2_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49a00000 0x100000>;
	+
	+ edma_tptc2: dma@0 {
	+ compatible = "ti,edma3-tptc";
	+ reg = <0 0x100000>;
	+ interrupts = <114>;
	+ interrupt-names = "edma3_tcerrint";
	+ };
	};

	- edma_tptc3: tptc@49b00000 {
	- compatible = "ti,edma3-tptc";
	- ti,hwmods = "tptc3";
	- reg = <0x49b00000 0x100000>;
	- interrupts = <115>;
	- interrupt-names = "edma3_tcerrint";
	+ target-module@49b00000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49b00000 0x4>,
	+ <0x49b00010 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_SMART>;
	+ clocks = <&alwon_clkctrl DM814_TPTC3_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49b00000 0x100000>;
	+
	+ edma_tptc3: dma@0 {
	+ compatible = "ti,edma3-tptc";
	+ reg = <0 0x100000>;
	+ interrupts = <115>;
	+ interrupt-names = "edma3_tcerrint";
	+ };
	};

	/* See TRM "Table 1-318. L4HS Instance Summary" */
	l4hs: l4hs@4a000000 {
	compatible = "ti,dm814-l4hs", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x4a000000 0x1b4040>;
	- };

	- /* REVISIT: Move to live under l4hs once driver is fixed */
	- mac: ethernet@4a100000 {
	- compatible = "ti,cpsw";
	- ti,hwmods = "cpgmac0";
	- clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
	- clock-names = "fck", "cpts";
	- cpdma_channels = <8>;
	- ale_entries = <1024>;
	- bd_ram_size = <0x2000>;
	- mac_control = <0x20>;
	- slaves = <2>;
	- active_slave = <0>;
	- cpts_clock_mult = <0x80000000>;
	- cpts_clock_shift = <29>;
	- reg = <0x4a100000 0x800
	- 0x4a100900 0x100>;
	- #address-cells = <1>;
	- #size-cells = <1>;
	- interrupt-parent = <&intc>;
	- /*
	- * c0_rx_thresh_pend
	- * c0_rx_pend
	- * c0_tx_pend
	- * c0_misc_pend
	- */
	- interrupts = <40 41 42 43>;
	- ranges;
	- syscon = <&scm_conf>;
	-
	- davinci_mdio: mdio@4a100800 {
	- compatible = "ti,davinci_mdio";
	+ target-module@100000 {
	+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
	+ reg = <0x100900 0x4>,
	+ <0x100908 0x4>,
	+ <0x100904 0x4>;
	+ reg-names = "rev", "sysc", "syss";
	+ ti,sysc-mask = <0>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>;
	+ ti,syss-mask = <1>;
	+ clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>;
	+ clock-names = "fck";
	#address-cells = <1>;
	- #size-cells = <0>;
	- ti,hwmods = "davinci_mdio";
	- bus_freq = <1000000>;
	- reg = <0x4a100800 0x100>;
	- };
	-
	- cpsw_emac0: slave@4a100200 {
	- /* Filled in by U-Boot */
	- mac-address = [ 00 00 00 00 00 00 ];
	- phys = <&phy_gmii_sel 1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x100000 0x8000>;
	+
	+ mac: ethernet@0 {
	+ compatible = "ti,cpsw";
	+ clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
	+ clock-names = "fck", "cpts";
	+ cpdma_channels = <8>;
	+ ale_entries = <1024>;
	+ bd_ram_size = <0x2000>;
	+ mac_control = <0x20>;
	+ slaves = <2>;
	+ active_slave = <0>;
	+ cpts_clock_mult = <0x80000000>;
	+ cpts_clock_shift = <29>;
	+ reg = <0 0x800>,
	+ <0x900 0x100>;
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ /*
	+ * c0_rx_thresh_pend
	+ * c0_rx_pend
	+ * c0_tx_pend
	+ * c0_misc_pend
	+ */
	+ interrupts = <40 41 42 43>;
	+ ranges = <0 0 0x8000>;
	+ syscon = <&scm_conf>;
	+
	+ davinci_mdio: mdio@800 {
	+ compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
	+ clocks = <&cpsw_125mhz_gclk>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ bus_freq = <1000000>;
	+ reg = <0x800 0x100>;
	+ };

	- };
	+ cpsw_emac0: slave@200 {
	+ /* Filled in by U-Boot */
	+ mac-address = [ 00 00 00 00 00 00 ];
	+ phys = <&phy_gmii_sel 1>;
	+ };

	- cpsw_emac1: slave@4a100300 {
	- /* Filled in by U-Boot */
	- mac-address = [ 00 00 00 00 00 00 ];
	- phys = <&phy_gmii_sel 2>;
	+ cpsw_emac1: slave@300 {
	+ /* Filled in by U-Boot */
	+ mac-address = [ 00 00 00 00 00 00 ];
	+ phys = <&phy_gmii_sel 2>;
	+ };
	+ };
	};
	};

	gpmc: gpmc@50000000 {
	compatible = "ti,am3352-gpmc";
	ti,hwmods = "gpmc";
	ti,no-idle-on-init;
	reg = <0x50000000 0x2000>;
	interrupts = <100>;
	gpmc,num-cs = <7>;
	gpmc,num-waitpins = <2>;
	#address-cells = <2>;
	#size-cells = <1>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;
	};
	};
	};

	#include "dm814x-clocks.dtsi"
	diff --git a/sys/gnu/dts/arm/dm816x.dtsi b/sys/gnu/dts/arm/dm816x.dtsi
	index 1edc2b48b254..2a4934b60ded 100644
	--- a/sys/gnu/dts/arm/dm816x.dtsi
	+++ b/sys/gnu/dts/arm/dm816x.dtsi
	@@ -1,532 +1,644 @@
	/*
	* This file is licensed under the terms of the GNU General Public License
	* version 2. This program is licensed "as is" without any warranty of any
	* kind, whether express or implied.
	*/

	+#include <dt-bindings/bus/ti-sysc.h>
	+#include <dt-bindings/clock/dm816.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/pinctrl/omap.h>

	/ {
	compatible = "ti,dm816";
	interrupt-parent = <&intc>;
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };

	aliases {
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	ethernet0 = &eth0;
	ethernet1 = &eth1;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	cpu@0 {
	compatible = "arm,cortex-a8";
	device_type = "cpu";
	reg = <0>;
	};
	};

	pmu {
	compatible = "arm,cortex-a8-pmu";
	interrupts = <3>;
	};

	/*
	* The soc node represents the soc top level view. It is used for IPs
	* that are not memory mapped in the MPU view or for the MPU itself.
	*/
	soc {
	compatible = "ti,omap-infra";
	mpu {
	compatible = "ti,omap3-mpu";
	ti,hwmods = "mpu";
	};
	};

	/*
	* XXX: Use a flat representation of the dm816x interconnect.
	* The real dm816x interconnect network is quite complex. Since
	* it will not bring real advantage to represent that in DT
	* for the moment, just use a fake OCP bus entry to represent
	* the whole bus hierarchy.
	*/
	ocp {
	compatible = "simple-bus";
	reg = <0x44000000 0x10000>;
	interrupts = <9 10>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	prcm: prcm@48180000 {
	compatible = "ti,dm816-prcm", "simple-bus";
	reg = <0x48180000 0x4000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x48180000 0x4000>;

	prcm_clocks: clocks {
	#address-cells = <1>;
	#size-cells = <0>;
	};

	prcm_clockdomains: clockdomains {
	};
	};

	scrm: scrm@48140000 {
	compatible = "ti,dm816-scrm", "simple-bus";
	reg = <0x48140000 0x21000>;
	#address-cells = <1>;
	#size-cells = <1>;
	#pinctrl-cells = <1>;
	ranges = <0 0x48140000 0x21000>;

	dm816x_pinmux: pinmux@800 {
	compatible = "pinctrl-single";
	reg = <0x800 0x50a>;
	#address-cells = <1>;
	#size-cells = <0>;
	#pinctrl-cells = <1>;
	pinctrl-single,register-width = <16>;
	pinctrl-single,function-mask = <0xf>;
	};

	/* Device Configuration Registers */
	scm_conf: syscon@600 {
	compatible = "syscon", "simple-bus";
	reg = <0x600 0x110>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x600 0x110>;

	usb_phy0: usb-phy@20 {
	compatible = "ti,dm8168-usb-phy";
	reg = <0x20 0x8>;
	reg-names = "phy";
	clocks = <&main_fapll 6>;
	clock-names = "refclk";
	#phy-cells = <0>;
	syscon = <&scm_conf>;
	};

	usb_phy1: usb-phy@28 {
	compatible = "ti,dm8168-usb-phy";
	reg = <0x28 0x8>;
	reg-names = "phy";
	clocks = <&main_fapll 6>;
	clock-names = "refclk";
	#phy-cells = <0>;
	syscon = <&scm_conf>;
	};
	};

	scrm_clocks: clocks {
	#address-cells = <1>;
	#size-cells = <0>;
	};

	scrm_clockdomains: clockdomains {
	};
	};

	- edma: edma@49000000 {
	- compatible = "ti,edma3";
	- ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
	- reg = <0x49000000 0x10000>,
	- <0x44e10f90 0x40>;
	- interrupts = <12 13 14>;
	- #dma-cells = <1>;
	+ target-module@49000000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49000000 0x4>;
	+ reg-names = "rev";
	+ clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49000000 0x10000>;
	+
	+ edma: dma@0 {
	+ compatible = "ti,edma3-tpcc";
	+ reg = <0 0x10000>;
	+ reg-names = "edma3_cc";
	+ interrupts = <12 13 14>;
	+ interrupt-names = "edma3_ccint", "edma3_mperr",
	+ "edma3_ccerrint";
	+ dma-requests = <64>;
	+ #dma-cells = <2>;
	+
	+ ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
	+ <&edma_tptc2 3>, <&edma_tptc3 0>;
	+
	+ ti,edma-memcpy-channels = <20 21>;
	+ };
	+ };
	+
	+ target-module@49800000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49800000 0x4>,
	+ <0x49800010 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_SMART>;
	+ clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49800000 0x100000>;
	+
	+ edma_tptc0: dma@0 {
	+ compatible = "ti,edma3-tptc";
	+ reg = <0 0x100000>;
	+ interrupts = <112>;
	+ interrupt-names = "edma3_tcerrint";
	+ };
	+ };
	+
	+ target-module@49900000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49900000 0x4>,
	+ <0x49900010 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_SMART>;
	+ clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49900000 0x100000>;
	+
	+ edma_tptc1: dma@0 {
	+ compatible = "ti,edma3-tptc";
	+ reg = <0 0x100000>;
	+ interrupts = <113>;
	+ interrupt-names = "edma3_tcerrint";
	+ };
	+ };
	+
	+ target-module@49a00000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49a00000 0x4>,
	+ <0x49a00010 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_SMART>;
	+ clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49a00000 0x100000>;
	+
	+ edma_tptc2: dma@0 {
	+ compatible = "ti,edma3-tptc";
	+ reg = <0 0x100000>;
	+ interrupts = <114>;
	+ interrupt-names = "edma3_tcerrint";
	+ };
	+ };
	+
	+ target-module@49b00000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x49b00000 0x4>,
	+ <0x49b00010 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_SMART>;
	+ clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x49b00000 0x100000>;
	+
	+ edma_tptc3: dma@0 {
	+ compatible = "ti,edma3-tptc";
	+ reg = <0 0x100000>;
	+ interrupts = <115>;
	+ interrupt-names = "edma3_tcerrint";
	+ };
	};

	elm: elm@48080000 {
	compatible = "ti,am3352-elm";
	ti,hwmods = "elm";
	reg = <0x48080000 0x2000>;
	interrupts = <4>;
	};

	gpio1: gpio@48032000 {
	compatible = "ti,omap4-gpio";
	ti,hwmods = "gpio1";
	ti,gpio-always-on;
	reg = <0x48032000 0x1000>;
	interrupts = <96>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio@4804c000 {
	compatible = "ti,omap4-gpio";
	ti,hwmods = "gpio2";
	ti,gpio-always-on;
	reg = <0x4804c000 0x1000>;
	interrupts = <98>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpmc: gpmc@50000000 {
	compatible = "ti,am3352-gpmc";
	ti,hwmods = "gpmc";
	reg = <0x50000000 0x2000>;
	#address-cells = <2>;
	#size-cells = <1>;
	interrupts = <100>;
	- dmas = <&edma 52>;
	+ dmas = <&edma 52 0>;
	dma-names = "rxtx";
	gpmc,num-cs = <6>;
	gpmc,num-waitpins = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	i2c1: i2c@48028000 {
	compatible = "ti,omap4-i2c";
	ti,hwmods = "i2c1";
	reg = <0x48028000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <70>;
	- dmas = <&edma 58 &edma 59>;
	+ dmas = <&edma 58 0 &edma 59 0>;
	dma-names = "tx", "rx";
	};

	i2c2: i2c@4802a000 {
	compatible = "ti,omap4-i2c";
	ti,hwmods = "i2c2";
	reg = <0x4802a000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <71>;
	- dmas = <&edma 60 &edma 61>;
	+ dmas = <&edma 60 0 &edma 61 0>;
	dma-names = "tx", "rx";
	};

	intc: interrupt-controller@48200000 {
	compatible = "ti,dm816-intc";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x48200000 0x1000>;
	};

	rtc: rtc@480c0000 {
	compatible = "ti,am3352-rtc", "ti,da830-rtc";
	reg = <0x480c0000 0x1000>;
	interrupts = <75 76>;
	ti,hwmods = "rtc";
	};

	mailbox: mailbox@480c8000 {
	compatible = "ti,omap4-mailbox";
	reg = <0x480c8000 0x2000>;
	interrupts = <77>;
	ti,hwmods = "mailbox";
	#mbox-cells = <1>;
	ti,mbox-num-users = <4>;
	ti,mbox-num-fifos = <12>;
	mbox_dsp: mbox_dsp {
	ti,mbox-tx = <3 0 0>;
	ti,mbox-rx = <0 0 0>;
	};
	};

	spinbox: spinbox@480ca000 {
	compatible = "ti,omap4-hwspinlock";
	reg = <0x480ca000 0x2000>;
	ti,hwmods = "spinbox";
	#hwlock-cells = <1>;
	};

	mdio: mdio@4a100800 {
	compatible = "ti,davinci_mdio";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x4a100800 0x100>;
	ti,hwmods = "davinci_mdio";
	bus_freq = <1000000>;
	phy0: ethernet-phy@0 {
	reg = <1>;
	};
	phy1: ethernet-phy@1 {
	reg = <2>;
	};
	};

	eth0: ethernet@4a100000 {
	compatible = "ti,dm816-emac";
	ti,hwmods = "emac0";
	reg = <0x4a100000 0x800
	0x4a100900 0x3700>;
	clocks = <&sysclk24_ck>;
	syscon = <&scm_conf>;
	ti,davinci-ctrl-reg-offset = <0>;
	ti,davinci-ctrl-mod-reg-offset = <0x900>;
	ti,davinci-ctrl-ram-offset = <0x2000>;
	ti,davinci-ctrl-ram-size = <0x2000>;
	interrupts = <40 41 42 43>;
	phy-handle = <&phy0>;
	};

	eth1: ethernet@4a120000 {
	compatible = "ti,dm816-emac";
	ti,hwmods = "emac1";
	reg = <0x4a120000 0x4000>;
	clocks = <&sysclk24_ck>;
	syscon = <&scm_conf>;
	ti,davinci-ctrl-reg-offset = <0>;
	ti,davinci-ctrl-mod-reg-offset = <0x900>;
	ti,davinci-ctrl-ram-offset = <0x2000>;
	ti,davinci-ctrl-ram-size = <0x2000>;
	interrupts = <44 45 46 47>;
	phy-handle = <&phy1>;
	};

	sata: sata@4a140000 {
	compatible = "ti,dm816-ahci";
	reg = <0x4a140000 0x10000>;
	interrupts = <16>;
	ti,hwmods = "sata";
	};

	mcspi1: spi@48030000 {
	compatible = "ti,omap4-mcspi";
	reg = <0x48030000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <65>;
	ti,spi-num-cs = <4>;
	ti,hwmods = "mcspi1";
	- dmas = <&edma 16 &edma 17
	- &edma 18 &edma 19
	- &edma 20 &edma 21
	- &edma 22 &edma 23>;
	+ dmas = <&edma 16 0 &edma 17 0
	+ &edma 18 0 &edma 19 0
	+ &edma 20 0 &edma 21 0
	+ &edma 22 0 &edma 23 0>;
	dma-names = "tx0", "rx0", "tx1", "rx1",
	"tx2", "rx2", "tx3", "rx3";
	};

	mmc1: mmc@48060000 {
	compatible = "ti,omap4-hsmmc";
	reg = <0x48060000 0x11000>;
	ti,hwmods = "mmc1";
	interrupts = <64>;
	- dmas = <&edma 24 &edma 25>;
	+ dmas = <&edma 24 0 &edma 25 0>;
	dma-names = "tx", "rx";
	};

	timer1: timer@4802e000 {
	compatible = "ti,dm816-timer";
	reg = <0x4802e000 0x2000>;
	interrupts = <67>;
	ti,hwmods = "timer1";
	ti,timer-alwon;
	clocks = <&timer1_fck>;
	clock-names = "fck";
	};

	timer2: timer@48040000 {
	compatible = "ti,dm816-timer";
	reg = <0x48040000 0x2000>;
	interrupts = <68>;
	ti,hwmods = "timer2";
	clocks = <&timer2_fck>;
	clock-names = "fck";
	};

	timer3: timer@48042000 {
	compatible = "ti,dm816-timer";
	reg = <0x48042000 0x2000>;
	interrupts = <69>;
	ti,hwmods = "timer3";
	};

	timer4: timer@48044000 {
	compatible = "ti,dm816-timer";
	reg = <0x48044000 0x2000>;
	interrupts = <92>;
	ti,hwmods = "timer4";
	ti,timer-pwm;
	};

	timer5: timer@48046000 {
	compatible = "ti,dm816-timer";
	reg = <0x48046000 0x2000>;
	interrupts = <93>;
	ti,hwmods = "timer5";
	ti,timer-pwm;
	};

	timer6: timer@48048000 {
	compatible = "ti,dm816-timer";
	reg = <0x48048000 0x2000>;
	interrupts = <94>;
	ti,hwmods = "timer6";
	ti,timer-pwm;
	};

	timer7: timer@4804a000 {
	compatible = "ti,dm816-timer";
	reg = <0x4804a000 0x2000>;
	interrupts = <95>;
	ti,hwmods = "timer7";
	ti,timer-pwm;
	};

	uart1: uart@48020000 {
	compatible = "ti,am3352-uart", "ti,omap3-uart";
	ti,hwmods = "uart1";
	reg = <0x48020000 0x2000>;
	clock-frequency = <48000000>;
	interrupts = <72>;
	- dmas = <&edma 26 &edma 27>;
	+ dmas = <&edma 26 0 &edma 27 0>;
	dma-names = "tx", "rx";
	};

	uart2: uart@48022000 {
	compatible = "ti,am3352-uart", "ti,omap3-uart";
	ti,hwmods = "uart2";
	reg = <0x48022000 0x2000>;
	clock-frequency = <48000000>;
	interrupts = <73>;
	- dmas = <&edma 28 &edma 29>;
	+ dmas = <&edma 28 0 &edma 29 0>;
	dma-names = "tx", "rx";
	};

	uart3: uart@48024000 {
	compatible = "ti,am3352-uart", "ti,omap3-uart";
	ti,hwmods = "uart3";
	reg = <0x48024000 0x2000>;
	clock-frequency = <48000000>;
	interrupts = <74>;
	- dmas = <&edma 30 &edma 31>;
	+ dmas = <&edma 30 0 &edma 31 0>;
	dma-names = "tx", "rx";
	};

	/* NOTE: USB needs a transceiver driver for phys to work */
	usb: usb_otg_hs@47401000 {
	compatible = "ti,am33xx-usb";
	reg = <0x47401000 0x400000>;
	ranges;
	#address-cells = <1>;
	#size-cells = <1>;
	ti,hwmods = "usb_otg_hs";

	usb0: usb@47401000 {
	compatible = "ti,musb-dm816";
	reg = <0x47401400 0x400
	0x47401000 0x200>;
	reg-names = "mc", "control";
	interrupts = <18>;
	interrupt-names = "mc";
	dr_mode = "host";
	interface-type = <0>;
	phys = <&usb_phy0>;
	phy-names = "usb2-phy";
	mentor,multipoint = <1>;
	mentor,num-eps = <16>;
	mentor,ram-bits = <12>;
	mentor,power = <500>;

	dmas = <&cppi41dma 0 0 &cppi41dma 1 0
	&cppi41dma 2 0 &cppi41dma 3 0
	&cppi41dma 4 0 &cppi41dma 5 0
	&cppi41dma 6 0 &cppi41dma 7 0
	&cppi41dma 8 0 &cppi41dma 9 0
	&cppi41dma 10 0 &cppi41dma 11 0
	&cppi41dma 12 0 &cppi41dma 13 0
	&cppi41dma 14 0 &cppi41dma 0 1
	&cppi41dma 1 1 &cppi41dma 2 1
	&cppi41dma 3 1 &cppi41dma 4 1
	&cppi41dma 5 1 &cppi41dma 6 1
	&cppi41dma 7 1 &cppi41dma 8 1
	&cppi41dma 9 1 &cppi41dma 10 1
	&cppi41dma 11 1 &cppi41dma 12 1
	&cppi41dma 13 1 &cppi41dma 14 1>;
	dma-names =
	"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
	"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
	"rx14", "rx15",
	"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
	"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
	"tx14", "tx15";
	};

	usb1: usb@47401800 {
	compatible = "ti,musb-dm816";
	reg = <0x47401c00 0x400
	0x47401800 0x200>;
	reg-names = "mc", "control";
	interrupts = <19>;
	interrupt-names = "mc";
	dr_mode = "host";
	interface-type = <0>;
	phys = <&usb_phy1>;
	phy-names = "usb2-phy";
	mentor,multipoint = <1>;
	mentor,num-eps = <16>;
	mentor,ram-bits = <12>;
	mentor,power = <500>;

	dmas = <&cppi41dma 15 0 &cppi41dma 16 0
	&cppi41dma 17 0 &cppi41dma 18 0
	&cppi41dma 19 0 &cppi41dma 20 0
	&cppi41dma 21 0 &cppi41dma 22 0
	&cppi41dma 23 0 &cppi41dma 24 0
	&cppi41dma 25 0 &cppi41dma 26 0
	&cppi41dma 27 0 &cppi41dma 28 0
	&cppi41dma 29 0 &cppi41dma 15 1
	&cppi41dma 16 1 &cppi41dma 17 1
	&cppi41dma 18 1 &cppi41dma 19 1
	&cppi41dma 20 1 &cppi41dma 21 1
	&cppi41dma 22 1 &cppi41dma 23 1
	&cppi41dma 24 1 &cppi41dma 25 1
	&cppi41dma 26 1 &cppi41dma 27 1
	&cppi41dma 28 1 &cppi41dma 29 1>;
	dma-names =
	"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
	"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
	"rx14", "rx15",
	"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
	"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
	"tx14", "tx15";
	};

	cppi41dma: dma-controller@47402000 {
	compatible = "ti,am3359-cppi41";
	reg = <0x47400000 0x1000
	0x47402000 0x1000
	0x47403000 0x1000
	0x47404000 0x4000>;
	reg-names = "glue", "controller", "scheduler", "queuemgr";
	interrupts = <17>;
	interrupt-names = "glue";
	#dma-cells = <2>;
	#dma-channels = <30>;
	#dma-requests = <256>;
	};
	};

	wd_timer2: wd_timer@480c2000 {
	compatible = "ti,omap3-wdt";
	ti,hwmods = "wd_timer";
	reg = <0x480c2000 0x1000>;
	interrupts = <0>;
	};
	};
	};

	#include "dm816x-clocks.dtsi"
	diff --git a/sys/gnu/dts/arm/dra62x.dtsi b/sys/gnu/dts/arm/dra62x.dtsi
	index d3cbb4ea35a8..cc4878aaa8ea 100644
	--- a/sys/gnu/dts/arm/dra62x.dtsi
	+++ b/sys/gnu/dts/arm/dra62x.dtsi
	@@ -1,23 +1,23 @@
	/*
	* This file is licensed under the terms of the GNU General Public License
	* version 2. This program is licensed "as is" without any warranty of any
	* kind, whether express or implied.
	*/

	#include "dm814x.dtsi"

	/ {
	compatible = "ti,dra62x";
	};

	/* Compared to dm814x, dra62x has different offsets for Ethernet */
	&mac {
	- reg = <0x4a100000 0x800
	- 0x4a101200 0x100>;
	+ reg = <0 0x800>,
	+ <0x1200 0x100>;
	};

	&davinci_mdio {
	- reg = <0x4a101000 0x100>;
	+ reg = <0x1000 0x100>;
	};

	#include "dra62x-clocks.dtsi"
	diff --git a/sys/gnu/dts/arm/dra7.dtsi b/sys/gnu/dts/arm/dra7.dtsi
	index 5f5ee16f07a3..7191ee6a1b82 100644
	--- a/sys/gnu/dts/arm/dra7.dtsi
	+++ b/sys/gnu/dts/arm/dra7.dtsi
	@@ -1,961 +1,1046 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
	*
	* Based on "omap4.dtsi"
	*/

	#include <dt-bindings/bus/ti-sysc.h>
	#include <dt-bindings/clock/dra7.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/pinctrl/dra.h>
	#include <dt-bindings/clock/dra7.h>

	#define MAX_SOURCES 400

	/ {
	#address-cells = <2>;
	#size-cells = <2>;

	compatible = "ti,dra7xx";
	interrupt-parent = <&crossbar_mpu>;
	chosen { };

	aliases {
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	i2c2 = &i2c3;
	i2c3 = &i2c4;
	i2c4 = &i2c5;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	serial4 = &uart5;
	serial5 = &uart6;
	serial6 = &uart7;
	serial7 = &uart8;
	serial8 = &uart9;
	serial9 = &uart10;
	ethernet0 = &cpsw_emac0;
	ethernet1 = &cpsw_emac1;
	d_can0 = &dcan1;
	d_can1 = &dcan2;
	spi0 = &qspi;
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	interrupt-parent = <&gic>;
	};

	gic: interrupt-controller@48211000 {
	compatible = "arm,cortex-a15-gic";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0x0 0x48211000 0x0 0x1000>,
	<0x0 0x48212000 0x0 0x2000>,
	<0x0 0x48214000 0x0 0x2000>,
	<0x0 0x48216000 0x0 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	interrupt-parent = <&gic>;
	};

	wakeupgen: interrupt-controller@48281000 {
	compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0x0 0x48281000 0x0 0x1000>;
	interrupt-parent = <&gic>;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0>;

	operating-points-v2 = <&cpu0_opp_table>;

	clocks = <&dpll_mpu_ck>;
	clock-names = "cpu";

	clock-latency = <300000>; /* From omap-cpufreq driver */

	/* cooling options */
	#cooling-cells = <2>; /* min followed by max */

	vbb-supply = <&abb_mpu>;
	};
	};

	cpu0_opp_table: opp-table {
	compatible = "operating-points-v2-ti-cpu";
	syscon = <&scm_wkup>;

	opp_nom-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	opp-microvolt = <1060000 850000 1150000>,
	<1060000 850000 1150000>;
	opp-supported-hw = <0xFF 0x01>;
	opp-suspend;
	};

	opp_od-1176000000 {
	opp-hz = /bits/ 64 <1176000000>;
	opp-microvolt = <1160000 885000 1160000>,
	<1160000 885000 1160000>;

	opp-supported-hw = <0xFF 0x02>;
	};

	opp_high@1500000000 {
	opp-hz = /bits/ 64 <1500000000>;
	opp-microvolt = <1210000 950000 1250000>,
	<1210000 950000 1250000>;
	opp-supported-hw = <0xFF 0x04>;
	};
	};

	/*
	* The soc node represents the soc top level view. It is used for IPs
	* that are not memory mapped in the MPU view or for the MPU itself.
	*/
	soc {
	compatible = "ti,omap-infra";
	mpu {
	compatible = "ti,omap5-mpu";
	ti,hwmods = "mpu";
	};
	};

	/*
	* XXX: Use a flat representation of the SOC interconnect.
	* The real OMAP interconnect network is quite complex.
	* Since it will not bring real advantage to represent that in DT for
	* the moment, just use a fake OCP bus entry to represent the whole bus
	* hierarchy.
	*/
	- ocp {
	+ ocp: ocp {
	compatible = "ti,dra7-l3-noc", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x0 0xc0000000>;
	dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
	ti,hwmods = "l3_main_1", "l3_main_2";
	reg = <0x0 0x44000000 0x0 0x1000000>,
	<0x0 0x45000000 0x0 0x1000>;
	interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	<&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

	l4_cfg: interconnect@4a000000 {
	};
	l4_wkup: interconnect@4ae00000 {
	};
	l4_per1: interconnect@48000000 {
	};
	l4_per2: interconnect@48400000 {
	};
	l4_per3: interconnect@48800000 {
	};

	axi@0 {
	compatible = "simple-bus";
	#size-cells = <1>;
	#address-cells = <1>;
	ranges = <0x51000000 0x51000000 0x3000
	0x0 0x20000000 0x10000000>;
	+ dma-ranges;
	/**
	* To enable PCI endpoint mode, disable the pcie1_rc
	* node and enable pcie1_ep mode.
	*/
	pcie1_rc: pcie@51000000 {
	reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
	reg-names = "rc_dbics", "ti_conf", "config";
	interrupts = <0 232 0x4>, <0 233 0x4>;
	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	ranges = <0x81000000 0 0 0x03000 0 0x00010000
	0x82000000 0 0x20013000 0x13000 0 0xffed000>;
	- dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
	bus-range = <0x00 0xff>;
	#interrupt-cells = <1>;
	num-lanes = <1>;
	linux,pci-domain = <0>;
	ti,hwmods = "pcie1";
	phys = <&pcie1_phy>;
	phy-names = "pcie-phy0";
	ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0 0 0 1 &pcie1_intc 1>,
	<0 0 0 2 &pcie1_intc 2>,
	<0 0 0 3 &pcie1_intc 3>,
	<0 0 0 4 &pcie1_intc 4>;
	ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
	status = "disabled";
	pcie1_intc: interrupt-controller {
	interrupt-controller;
	#address-cells = <0>;
	#interrupt-cells = <1>;
	};
	};

	pcie1_ep: pcie_ep@51000000 {
	reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
	reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
	interrupts = <0 232 0x4>;
	num-lanes = <1>;
	num-ib-windows = <4>;
	num-ob-windows = <16>;
	ti,hwmods = "pcie1";
	phys = <&pcie1_phy>;
	phy-names = "pcie-phy0";
	ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
	ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
	status = "disabled";
	};
	};

	axi@1 {
	compatible = "simple-bus";
	#size-cells = <1>;
	#address-cells = <1>;
	ranges = <0x51800000 0x51800000 0x3000
	0x0 0x30000000 0x10000000>;
	+ dma-ranges;
	status = "disabled";
	pcie2_rc: pcie@51800000 {
	reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
	reg-names = "rc_dbics", "ti_conf", "config";
	interrupts = <0 355 0x4>, <0 356 0x4>;
	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	ranges = <0x81000000 0 0 0x03000 0 0x00010000
	0x82000000 0 0x30013000 0x13000 0 0xffed000>;
	- dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
	bus-range = <0x00 0xff>;
	#interrupt-cells = <1>;
	num-lanes = <1>;
	linux,pci-domain = <1>;
	ti,hwmods = "pcie2";
	phys = <&pcie2_phy>;
	phy-names = "pcie-phy0";
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0 0 0 1 &pcie2_intc 1>,
	<0 0 0 2 &pcie2_intc 2>,
	<0 0 0 3 &pcie2_intc 3>,
	<0 0 0 4 &pcie2_intc 4>;
	ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
	pcie2_intc: interrupt-controller {
	interrupt-controller;
	#address-cells = <0>;
	#interrupt-cells = <1>;
	};
	};
	};

	ocmcram1: ocmcram@40300000 {
	compatible = "mmio-sram";
	reg = <0x40300000 0x80000>;
	ranges = <0x0 0x40300000 0x80000>;
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	* This is a placeholder for an optional reserved
	* region for use by secure software. The size
	* of this region is not known until runtime so it
	* is set as zero to either be updated to reserve
	* space or left unchanged to leave all SRAM for use.
	* On HS parts that that require the reserved region
	* either the bootloader can update the size to
	* the required amount or the node can be overridden
	* from the board dts file for the secure platform.
	*/
	sram-hs@0 {
	compatible = "ti,secure-ram";
	reg = <0x0 0x0>;
	};
	};

	/*
	* NOTE: ocmcram2 and ocmcram3 are not available on all
	* DRA7xx and AM57xx variants. Confirm availability in
	* the data manual for the exact part number in use
	* before enabling these nodes in the board dts file.
	*/
	ocmcram2: ocmcram@40400000 {
	status = "disabled";
	compatible = "mmio-sram";
	reg = <0x40400000 0x100000>;
	ranges = <0x0 0x40400000 0x100000>;
	#address-cells = <1>;
	#size-cells = <1>;
	};

	ocmcram3: ocmcram@40500000 {
	status = "disabled";
	compatible = "mmio-sram";
	reg = <0x40500000 0x100000>;
	ranges = <0x0 0x40500000 0x100000>;
	#address-cells = <1>;
	#size-cells = <1>;
	};

	bandgap: bandgap@4a0021e0 {
	reg = <0x4a0021e0 0xc
	0x4a00232c 0xc
	0x4a002380 0x2c
	0x4a0023C0 0x3c
	0x4a002564 0x8
	0x4a002574 0x50>;
	compatible = "ti,dra752-bandgap";
	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
	#thermal-sensor-cells = <1>;
	};

	dsp1_system: dsp_system@40d00000 {
	compatible = "syscon";
	reg = <0x40d00000 0x100>;
	};

	dra7_iodelay_core: padconf@4844a000 {
	compatible = "ti,dra7-iodelay";
	reg = <0x4844a000 0x0d1c>;
	#address-cells = <1>;
	#size-cells = <0>;
	#pinctrl-cells = <2>;
	};

	- edma: edma@43300000 {
	- compatible = "ti,edma3-tpcc";
	- ti,hwmods = "tpcc";
	- reg = <0x43300000 0x100000>;
	- reg-names = "edma3_cc";
	- interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
	- <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
	- <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	- interrupt-names = "edma3_ccint", "edma3_mperr",
	- "edma3_ccerrint";
	- dma-requests = <64>;
	- #dma-cells = <2>;
	+ target-module@43300000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x43300000 0x4>;
	+ reg-names = "rev";
	+ clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x43300000 0x100000>;
	+
	+ edma: dma@0 {
	+ compatible = "ti,edma3-tpcc";
	+ reg = <0 0x100000>;
	+ reg-names = "edma3_cc";
	+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	+ interrupt-names = "edma3_ccint", "edma3_mperr",
	+ "edma3_ccerrint";
	+ dma-requests = <64>;
	+ #dma-cells = <2>;
	+
	+ ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
	+
	+ /*
	+ * memcpy is disabled, can be enabled with:
	+ * ti,edma-memcpy-channels = <20 21>;
	+ * for example. Note that these channels need to be
	+ * masked in the xbar as well.
	+ */
	+ };
	+ };

	- ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
	+ target-module@43400000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x43400000 0x4>;
	+ reg-names = "rev";
	+ clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x43400000 0x100000>;

	- /*
	- * memcpy is disabled, can be enabled with:
	- * ti,edma-memcpy-channels = <20 21>;
	- * for example. Note that these channels need to be
	- * masked in the xbar as well.
	- */
	+ edma_tptc0: dma@0 {
	+ compatible = "ti,edma3-tptc";
	+ reg = <0 0x100000>;
	+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
	+ interrupt-names = "edma3_tcerrint";
	+ };
	};

	- edma_tptc0: tptc@43400000 {
	- compatible = "ti,edma3-tptc";
	- ti,hwmods = "tptc0";
	- reg = <0x43400000 0x100000>;
	- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
	- interrupt-names = "edma3_tcerrint";
	- };
	+ target-module@43500000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x43500000 0x4>;
	+ reg-names = "rev";
	+ clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x43500000 0x100000>;

	- edma_tptc1: tptc@43500000 {
	- compatible = "ti,edma3-tptc";
	- ti,hwmods = "tptc1";
	- reg = <0x43500000 0x100000>;
	- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
	- interrupt-names = "edma3_tcerrint";
	+ edma_tptc1: dma@0 {
	+ compatible = "ti,edma3-tptc";
	+ reg = <0 0x100000>;
	+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
	+ interrupt-names = "edma3_tcerrint";
	+ };
	};

	dmm@4e000000 {
	compatible = "ti,omap5-dmm";
	reg = <0x4e000000 0x800>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	ti,hwmods = "dmm";
	};

	target-module@40d01000 {
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x40d01000 0x4>,
	<0x40d01010 0x4>,
	<0x40d01014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
	clock-names = "fck";
	resets = <&prm_dsp1 1>;
	reset-names = "rstctrl";
	ranges = <0x0 0x40d01000 0x1000>;
	#size-cells = <1>;
	#address-cells = <1>;

	mmu0_dsp1: mmu@0 {
	compatible = "ti,dra7-dsp-iommu";
	reg = <0x0 0x100>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <0>;
	ti,syscon-mmuconfig = <&dsp1_system 0x0>;
	};
	};

	target-module@40d02000 {
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x40d02000 0x4>,
	<0x40d02010 0x4>,
	<0x40d02014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
	clock-names = "fck";
	resets = <&prm_dsp1 1>;
	reset-names = "rstctrl";
	ranges = <0x0 0x40d02000 0x1000>;
	#size-cells = <1>;
	#address-cells = <1>;

	mmu1_dsp1: mmu@0 {
	compatible = "ti,dra7-dsp-iommu";
	reg = <0x0 0x100>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <0>;
	ti,syscon-mmuconfig = <&dsp1_system 0x1>;
	};
	};

	target-module@58882000 {
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x58882000 0x4>,
	<0x58882010 0x4>,
	<0x58882014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
	clock-names = "fck";
	resets = <&prm_ipu 2>;
	reset-names = "rstctrl";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x58882000 0x100>;

	mmu_ipu1: mmu@0 {
	compatible = "ti,dra7-iommu";
	reg = <0x0 0x100>;
	interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <0>;
	ti,iommu-bus-err-back;
	};
	};

	target-module@55082000 {
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x55082000 0x4>,
	<0x55082010 0x4>,
	<0x55082014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
	clock-names = "fck";
	resets = <&prm_core 2>;
	reset-names = "rstctrl";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x55082000 0x100>;

	mmu_ipu2: mmu@0 {
	compatible = "ti,dra7-iommu";
	reg = <0x0 0x100>;
	interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <0>;
	ti,iommu-bus-err-back;
	};
	};

	abb_mpu: regulator-abb-mpu {
	compatible = "ti,abb-v3";
	regulator-name = "abb_mpu";
	#address-cells = <0>;
	#size-cells = <0>;
	clocks = <&sys_clkin1>;
	ti,settling-time = <50>;
	ti,clock-cycles = <16>;

	reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
	<0x4ae06014 0x4>, <0x4a003b20 0xc>,
	<0x4ae0c158 0x4>;
	reg-names = "setup-address", "control-address",
	"int-address", "efuse-address",
	"ldo-address";
	ti,tranxdone-status-mask = <0x80>;
	/* LDOVBBMPU_FBB_MUX_CTRL */
	ti,ldovbb-override-mask = <0x400>;
	/* LDOVBBMPU_FBB_VSET_OUT */
	ti,ldovbb-vset-mask = <0x1F>;

	/*
	* NOTE: only FBB mode used but actual vset will
	* determine final biasing
	*/
	ti,abb_info = <
	/uV ABB efuse rbb_m fbb_m vset_m/
	1060000 0 0x0 0 0x02000000 0x01F00000
	1160000 0 0x4 0 0x02000000 0x01F00000
	1210000 0 0x8 0 0x02000000 0x01F00000
	>;
	};

	abb_ivahd: regulator-abb-ivahd {
	compatible = "ti,abb-v3";
	regulator-name = "abb_ivahd";
	#address-cells = <0>;
	#size-cells = <0>;
	clocks = <&sys_clkin1>;
	ti,settling-time = <50>;
	ti,clock-cycles = <16>;

	reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
	<0x4ae06010 0x4>, <0x4a0025cc 0xc>,
	<0x4a002470 0x4>;
	reg-names = "setup-address", "control-address",
	"int-address", "efuse-address",
	"ldo-address";
	ti,tranxdone-status-mask = <0x40000000>;
	/* LDOVBBIVA_FBB_MUX_CTRL */
	ti,ldovbb-override-mask = <0x400>;
	/* LDOVBBIVA_FBB_VSET_OUT */
	ti,ldovbb-vset-mask = <0x1F>;

	/*
	* NOTE: only FBB mode used but actual vset will
	* determine final biasing
	*/
	ti,abb_info = <
	/uV ABB efuse rbb_m fbb_m vset_m/
	1055000 0 0x0 0 0x02000000 0x01F00000
	1150000 0 0x4 0 0x02000000 0x01F00000
	1250000 0 0x8 0 0x02000000 0x01F00000
	>;
	};

	abb_dspeve: regulator-abb-dspeve {
	compatible = "ti,abb-v3";
	regulator-name = "abb_dspeve";
	#address-cells = <0>;
	#size-cells = <0>;
	clocks = <&sys_clkin1>;
	ti,settling-time = <50>;
	ti,clock-cycles = <16>;

	reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
	<0x4ae06010 0x4>, <0x4a0025e0 0xc>,
	<0x4a00246c 0x4>;
	reg-names = "setup-address", "control-address",
	"int-address", "efuse-address",
	"ldo-address";
	ti,tranxdone-status-mask = <0x20000000>;
	/* LDOVBBDSPEVE_FBB_MUX_CTRL */
	ti,ldovbb-override-mask = <0x400>;
	/* LDOVBBDSPEVE_FBB_VSET_OUT */
	ti,ldovbb-vset-mask = <0x1F>;

	/*
	* NOTE: only FBB mode used but actual vset will
	* determine final biasing
	*/
	ti,abb_info = <
	/uV ABB efuse rbb_m fbb_m vset_m/
	1055000 0 0x0 0 0x02000000 0x01F00000
	1150000 0 0x4 0 0x02000000 0x01F00000
	1250000 0 0x8 0 0x02000000 0x01F00000
	>;
	};

	abb_gpu: regulator-abb-gpu {
	compatible = "ti,abb-v3";
	regulator-name = "abb_gpu";
	#address-cells = <0>;
	#size-cells = <0>;
	clocks = <&sys_clkin1>;
	ti,settling-time = <50>;
	ti,clock-cycles = <16>;

	reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
	<0x4ae06010 0x4>, <0x4a003b08 0xc>,
	<0x4ae0c154 0x4>;
	reg-names = "setup-address", "control-address",
	"int-address", "efuse-address",
	"ldo-address";
	ti,tranxdone-status-mask = <0x10000000>;
	/* LDOVBBGPU_FBB_MUX_CTRL */
	ti,ldovbb-override-mask = <0x400>;
	/* LDOVBBGPU_FBB_VSET_OUT */
	ti,ldovbb-vset-mask = <0x1F>;

	/*
	* NOTE: only FBB mode used but actual vset will
	* determine final biasing
	*/
	ti,abb_info = <
	/uV ABB efuse rbb_m fbb_m vset_m/
	1090000 0 0x0 0 0x02000000 0x01F00000
	1210000 0 0x4 0 0x02000000 0x01F00000
	1280000 0 0x8 0 0x02000000 0x01F00000
	>;
	};

	qspi: spi@4b300000 {
	compatible = "ti,dra7xxx-qspi";
	reg = <0x4b300000 0x100>,
	<0x5c000000 0x4000000>;
	reg-names = "qspi_base", "qspi_mmap";
	syscon-chipselects = <&scm_conf 0x558>;
	#address-cells = <1>;
	#size-cells = <0>;
	ti,hwmods = "qspi";
	clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
	clock-names = "fck";
	num-cs = <4>;
	interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	/* OCP2SCP3 */
	sata: sata@4a141100 {
	compatible = "snps,dwc-ahci";
	reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	phys = <&sata_phy>;
	phy-names = "sata-phy";
	clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
	ti,hwmods = "sata";
	ports-implemented = <0x1>;
	};

	/* OCP2SCP1 */
	/* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
	gpmc: gpmc@50000000 {
	compatible = "ti,am3352-gpmc";
	ti,hwmods = "gpmc";
	reg = <0x50000000 0x37c>; /* device IO registers */
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&edma_xbar 4 0>;
	dma-names = "rxtx";
	gpmc,num-cs = <8>;
	gpmc,num-waitpins = <2>;
	#address-cells = <2>;
	#size-cells = <1>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;
	status = "disabled";
	};

	target-module@56000000 {
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x5600fe00 0x4>,
	<0x5600fe10 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x56000000 0x2000000>;
	};

	crossbar_mpu: crossbar@4a002a48 {
	compatible = "ti,irq-crossbar";
	reg = <0x4a002a48 0x130>;
	interrupt-controller;
	interrupt-parent = <&wakeupgen>;
	#interrupt-cells = <3>;
	ti,max-irqs = <160>;
	ti,max-crossbar-sources = <MAX_SOURCES>;
	ti,reg-size = <2>;
	ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
	ti,irqs-skip = <10 133 139 140>;
	ti,irqs-safe-map = <0>;
	};

	- dss: dss@58000000 {
	- compatible = "ti,dra7-dss";
	- /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
	- /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
	- status = "disabled";
	- ti,hwmods = "dss_core";
	- /* CTRL_CORE_DSS_PLL_CONTROL */
	- syscon-pll-ctrl = <&scm_conf 0x538>;
	+ target-module@58000000 {
	+ compatible = "ti,sysc-omap2", "ti,sysc";
	+ reg = <0x58000000 4>,
	+ <0x58000014 4>;
	+ reg-names = "rev", "syss";
	+ ti,syss-mask = <1>;
	+ clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>,
	+ <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
	+ <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>,
	+ <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>;
	+ clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
	#address-cells = <1>;
	#size-cells = <1>;
	- ranges;
	-
	- dispc@58001000 {
	- compatible = "ti,dra7-dispc";
	- reg = <0x58001000 0x1000>;
	- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	- ti,hwmods = "dss_dispc";
	- clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
	- clock-names = "fck";
	- /* CTRL_CORE_SMA_SW_1 */
	- syscon-pol = <&scm_conf 0x534>;
	- };
	+ ranges = <0 0x58000000 0x800000>;

	- hdmi: encoder@58060000 {
	- compatible = "ti,dra7-hdmi";
	- reg = <0x58040000 0x200>,
	- <0x58040200 0x80>,
	- <0x58040300 0x80>,
	- <0x58060000 0x19000>;
	- reg-names = "wp", "pll", "phy", "core";
	- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	+ dss: dss@0 {
	+ compatible = "ti,dra7-dss";
	+ /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
	+ /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
	status = "disabled";
	- ti,hwmods = "dss_hdmi";
	- clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
	- <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
	- clock-names = "fck", "sys_clk";
	- dmas = <&sdma_xbar 76>;
	- dma-names = "audio_tx";
	+ /* CTRL_CORE_DSS_PLL_CONTROL */
	+ syscon-pll-ctrl = <&scm_conf 0x538>;
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0 0x800000>;
	+
	+ target-module@1000 {
	+ compatible = "ti,sysc-omap2", "ti,sysc";
	+ reg = <0x1000 0x4>,
	+ <0x1010 0x4>,
	+ <0x1014 0x4>;
	+ reg-names = "rev", "sysc", "syss";
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	+ SYSC_OMAP2_ENAWAKEUP \|
	+ SYSC_OMAP2_SOFTRESET \|
	+ SYSC_OMAP2_AUTOIDLE)>;
	+ ti,syss-mask = <1>;
	+ clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x1000 0x1000>;
	+
	+ dispc@0 {
	+ compatible = "ti,dra7-dispc";
	+ reg = <0 0x1000>;
	+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
	+ clock-names = "fck";
	+ /* CTRL_CORE_SMA_SW_1 */
	+ syscon-pol = <&scm_conf 0x534>;
	+ };
	+ };
	+
	+ target-module@40000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x40000 0x4>,
	+ <0x40010 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>,
	+ <SYSC_IDLE_SMART_WKUP>;
	+ ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
	+ clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
	+ <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
	+ clock-names = "fck", "dss_clk";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x40000 0x40000>;
	+
	+ hdmi: encoder@0 {
	+ compatible = "ti,dra7-hdmi";
	+ reg = <0 0x200>,
	+ <0x200 0x80>,
	+ <0x300 0x80>,
	+ <0x20000 0x19000>;
	+ reg-names = "wp", "pll", "phy", "core";
	+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	+ status = "disabled";
	+ clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
	+ <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
	+ clock-names = "fck", "sys_clk";
	+ dmas = <&sdma_xbar 76>;
	+ dma-names = "audio_tx";
	+ };
	+ };
	};
	};

	aes1_target: target-module@4b500000 {
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x4b500080 0x4>,
	<0x4b500084 0x4>,
	<0x4b500088 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4sec_clkdm */
	clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4b500000 0x1000>;

	aes1: aes@0 {
	compatible = "ti,omap4-aes";
	reg = <0 0xa0>;
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
	dma-names = "tx", "rx";
	clocks = <&l3_iclk_div>;
	clock-names = "fck";
	};
	};

	aes2_target: target-module@4b700000 {
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x4b700080 0x4>,
	<0x4b700084 0x4>,
	<0x4b700088 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): per_pwrdm, l4sec_clkdm */
	clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4b700000 0x1000>;

	aes2: aes@0 {
	compatible = "ti,omap4-aes";
	reg = <0 0xa0>;
	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
	dma-names = "tx", "rx";
	clocks = <&l3_iclk_div>;
	clock-names = "fck";
	};
	};

	sham_target: target-module@4b101000 {
	compatible = "ti,sysc-omap3-sham", "ti,sysc";
	reg = <0x4b101100 0x4>,
	<0x4b101110 0x4>,
	<0x4b101114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
	clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4b101000 0x1000>;

	sham: sham@0 {
	compatible = "ti,omap5-sham";
	reg = <0 0x300>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&edma_xbar 119 0>;
	dma-names = "rx";
	clocks = <&l3_iclk_div>;
	clock-names = "fck";
	};
	};

	opp_supply_mpu: opp-supply@4a003b20 {
	compatible = "ti,omap5-opp-supply";
	reg = <0x4a003b20 0xc>;
	ti,efuse-settings = <
	/* uV offset */
	1060000 0x0
	1160000 0x4
	1210000 0x8
	>;
	ti,absolute-max-voltage-uv = <1500000>;
	};

	};

	thermal_zones: thermal-zones {
	#include "omap4-cpu-thermal.dtsi"
	#include "omap5-gpu-thermal.dtsi"
	#include "omap5-core-thermal.dtsi"
	#include "dra7-dspeve-thermal.dtsi"
	#include "dra7-iva-thermal.dtsi"
	};

	};

	&cpu_thermal {
	polling-delay = <500>; /* milliseconds */
	coefficients = <0 2000>;
	};

	&gpu_thermal {
	coefficients = <0 2000>;
	};

	&core_thermal {
	coefficients = <0 2000>;
	};

	&dspeve_thermal {
	coefficients = <0 2000>;
	};

	&iva_thermal {
	coefficients = <0 2000>;
	};

	&cpu_crit {
	temperature = <120000>; /* milli Celsius */
	};

	&core_crit {
	temperature = <120000>; /* milli Celsius */
	};

	&gpu_crit {
	temperature = <120000>; /* milli Celsius */
	};

	&dspeve_crit {
	temperature = <120000>; /* milli Celsius */
	};

	&iva_crit {
	temperature = <120000>; /* milli Celsius */
	};

	#include "dra7-l4.dtsi"
	#include "dra7xx-clocks.dtsi"

	&prm {
	prm_dsp1: prm@400 {
	compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
	reg = <0x400 0x100>;
	#reset-cells = <1>;
	};

	prm_ipu: prm@500 {
	compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
	reg = <0x500 0x100>;
	#reset-cells = <1>;
	};

	prm_core: prm@700 {
	compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
	reg = <0x700 0x100>;
	#reset-cells = <1>;
	};

	prm_iva: prm@f00 {
	compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
	reg = <0xf00 0x100>;
	};

	prm_dsp2: prm@1b00 {
	compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
	reg = <0x1b00 0x40>;
	#reset-cells = <1>;
	};

	prm_eve1: prm@1b40 {
	compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
	reg = <0x1b40 0x40>;
	};

	prm_eve2: prm@1b80 {
	compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
	reg = <0x1b80 0x40>;
	};

	prm_eve3: prm@1bc0 {
	compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
	reg = <0x1bc0 0x40>;
	};

	prm_eve4: prm@1c00 {
	compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
	reg = <0x1c00 0x60>;
	};
	};
	diff --git a/sys/gnu/dts/arm/dra72x.dtsi b/sys/gnu/dts/arm/dra72x.dtsi
	index 82b57a35abc0..da334489b18f 100644
	--- a/sys/gnu/dts/arm/dra72x.dtsi
	+++ b/sys/gnu/dts/arm/dra72x.dtsi
	@@ -1,108 +1,108 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
	*
	* Based on "omap4.dtsi"
	*/

	#include "dra7.dtsi"

	/ {
	compatible = "ti,dra722", "ti,dra72", "ti,dra7";

	pmu {
	compatible = "arm,cortex-a15-pmu";
	interrupt-parent = <&wakeupgen>;
	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	&l4_per2 {
	target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x5b000 0x4>,
	<0x5b010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>;
	clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x5b000 0x1000>;

	cal: cal@0 {
	compatible = "ti,dra72-cal";
	reg = <0x0000 0x400>,
	<0x0800 0x40>,
	<0x0900 0x40>;
	reg-names = "cal_top",
	"cal_rx_core0",
	"cal_rx_core1";
	interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	ti,camerrx-control = <&scm_conf 0xE94>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	csi2_0: port@0 {
	reg = <0>;
	};
	csi2_1: port@1 {
	reg = <1>;
	};
	};
	};
	};
	};

	&dss {
	- reg = <0x58000000 0x80>,
	- <0x58004054 0x4>,
	- <0x58004300 0x20>;
	+ reg = <0 0x80>,
	+ <0x4054 0x4>,
	+ <0x4300 0x20>;
	reg-names = "dss", "pll1_clkctrl", "pll1";

	clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
	<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>;
	clock-names = "fck", "video1_clk";
	};

	&mailbox5 {
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
	ti,mbox-tx = <6 2 2>;
	ti,mbox-rx = <4 2 2>;
	status = "disabled";
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
	ti,mbox-tx = <5 2 2>;
	ti,mbox-rx = <1 2 2>;
	status = "disabled";
	};
	};

	&mailbox6 {
	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
	ti,mbox-tx = <6 2 2>;
	ti,mbox-rx = <4 2 2>;
	status = "disabled";
	};
	};

	&pcie1_rc {
	compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
	};

	&pcie1_ep {
	compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep";
	};

	&pcie2_rc {
	compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
	};

	&usb4_tm {
	status = "disabled";
	};
	diff --git a/sys/gnu/dts/arm/dra74x.dtsi b/sys/gnu/dts/arm/dra74x.dtsi
	index c5abc436ca1f..7b1c61298253 100644
	--- a/sys/gnu/dts/arm/dra74x.dtsi
	+++ b/sys/gnu/dts/arm/dra74x.dtsi
	@@ -1,185 +1,185 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
	*
	* Based on "omap4.dtsi"
	*/

	#include "dra7.dtsi"

	/ {
	compatible = "ti,dra742", "ti,dra74", "ti,dra7";

	cpus {
	cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <1>;
	operating-points-v2 = <&cpu0_opp_table>;

	clocks = <&dpll_mpu_ck>;
	clock-names = "cpu";

	clock-latency = <300000>; /* From omap-cpufreq driver */

	/* cooling options */
	#cooling-cells = <2>; /* min followed by max */

	vbb-supply = <&abb_mpu>;
	};
	};

	pmu {
	compatible = "arm,cortex-a15-pmu";
	interrupt-parent = <&wakeupgen>;
	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
	};

	ocp {
	dsp2_system: dsp_system@41500000 {
	compatible = "syscon";
	reg = <0x41500000 0x100>;
	};

	omap_dwc3_4: omap_dwc3_4@48940000 {
	compatible = "ti,dwc3";
	ti,hwmods = "usb_otg_ss4";
	reg = <0x48940000 0x10000>;
	interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <1>;
	utmi-mode = <2>;
	ranges;
	status = "disabled";
	usb4: usb@48950000 {
	compatible = "snps,dwc3";
	reg = <0x48950000 0x17000>;
	interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "peripheral",
	"host",
	"otg";
	maximum-speed = "high-speed";
	dr_mode = "otg";
	};
	};

	target-module@41501000 {
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x41501000 0x4>,
	<0x41501010 0x4>,
	<0x41501014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
	clock-names = "fck";
	resets = <&prm_dsp2 1>;
	reset-names = "rstctrl";
	ranges = <0x0 0x41501000 0x1000>;
	#size-cells = <1>;
	#address-cells = <1>;

	mmu0_dsp2: mmu@0 {
	compatible = "ti,dra7-dsp-iommu";
	reg = <0x0 0x100>;
	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <0>;
	ti,syscon-mmuconfig = <&dsp2_system 0x0>;
	};
	};

	target-module@41502000 {
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x41502000 0x4>,
	<0x41502010 0x4>,
	<0x41502014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;

	clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
	clock-names = "fck";
	resets = <&prm_dsp2 1>;
	reset-names = "rstctrl";
	ranges = <0x0 0x41502000 0x1000>;
	#size-cells = <1>;
	#address-cells = <1>;

	mmu1_dsp2: mmu@0 {
	compatible = "ti,dra7-dsp-iommu";
	reg = <0x0 0x100>;
	interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <0>;
	ti,syscon-mmuconfig = <&dsp2_system 0x1>;
	};
	};
	};
	};

	&cpu0_opp_table {
	opp-shared;
	};

	&dss {
	- reg = <0x58000000 0x80>,
	- <0x58004054 0x4>,
	- <0x58004300 0x20>,
	- <0x58009054 0x4>,
	- <0x58009300 0x20>;
	+ reg = <0 0x80>,
	+ <0x4054 0x4>,
	+ <0x4300 0x20>,
	+ <0x9054 0x4>,
	+ <0x9300 0x20>;
	reg-names = "dss", "pll1_clkctrl", "pll1",
	"pll2_clkctrl", "pll2";

	clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
	<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>,
	<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>;
	clock-names = "fck", "video1_clk", "video2_clk";
	};

	&mailbox5 {
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
	ti,mbox-tx = <6 2 2>;
	ti,mbox-rx = <4 2 2>;
	status = "disabled";
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
	ti,mbox-tx = <5 2 2>;
	ti,mbox-rx = <1 2 2>;
	status = "disabled";
	};
	};

	&mailbox6 {
	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
	ti,mbox-tx = <6 2 2>;
	ti,mbox-rx = <4 2 2>;
	status = "disabled";
	};
	mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
	ti,mbox-tx = <5 2 2>;
	ti,mbox-rx = <1 2 2>;
	status = "disabled";
	};
	};

	&pcie1_rc {
	compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
	};

	&pcie1_ep {
	compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
	};

	&pcie2_rc {
	compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
	};
	diff --git a/sys/gnu/dts/arm/ecx-2000.dts b/sys/gnu/dts/arm/ecx-2000.dts
	index 5651ae6dc969..f6eb71553b95 100644
	--- a/sys/gnu/dts/arm/ecx-2000.dts
	+++ b/sys/gnu/dts/arm/ecx-2000.dts
	@@ -1,103 +1,101 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright 2011-2012 Calxeda, Inc.
	*/

	/dts-v1/;

	/* First 4KB has pen for secondary cores. */
	/memreserve/ 0x00000000 0x0001000;

	/ {
	model = "Calxeda ECX-2000";
	compatible = "calxeda,ecx-2000";
	#address-cells = <2>;
	#size-cells = <2>;
	- clock-ranges;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	compatible = "arm,cortex-a15";
	device_type = "cpu";
	reg = <0>;
	clocks = <&a9pll>;
	clock-names = "cpu";
	};

	cpu@1 {
	compatible = "arm,cortex-a15";
	device_type = "cpu";
	reg = <1>;
	clocks = <&a9pll>;
	clock-names = "cpu";
	};

	cpu@2 {
	compatible = "arm,cortex-a15";
	device_type = "cpu";
	reg = <2>;
	clocks = <&a9pll>;
	clock-names = "cpu";
	};

	cpu@3 {
	compatible = "arm,cortex-a15";
	device_type = "cpu";
	reg = <3>;
	clocks = <&a9pll>;
	clock-names = "cpu";
	};
	};

	memory@0 {
	name = "memory";
	device_type = "memory";
	reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
	};

	memory@200000000 {
	name = "memory";
	device_type = "memory";
	reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
	};

	soc {
	ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;

	timer {
	compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
	<1 14 0xf08>,
	<1 11 0xf08>,
	<1 10 0xf08>;
	};

	memory-controller@fff00000 {
	compatible = "calxeda,ecx-2000-ddr-ctrl";
	reg = <0xfff00000 0x1000>;
	interrupts = <0 91 4>;
	};

	intc: interrupt-controller@fff11000 {
	compatible = "arm,cortex-a15-gic";
	#interrupt-cells = <3>;
	- #size-cells = <0>;
	- #address-cells = <1>;
	+ #address-cells = <0>;
	interrupt-controller;
	interrupts = <1 9 0xf04>;
	reg = <0xfff11000 0x1000>,
	<0xfff12000 0x2000>,
	<0xfff14000 0x2000>,
	<0xfff16000 0x2000>;
	};

	pmu {
	compatible = "arm,cortex-a9-pmu";
	- interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
	+ interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>;
	};
	};
	};

	/include/ "ecx-common.dtsi"
	diff --git a/sys/gnu/dts/arm/ecx-common.dtsi b/sys/gnu/dts/arm/ecx-common.dtsi
	index 66ee1d34f72b..57a028a69373 100644
	--- a/sys/gnu/dts/arm/ecx-common.dtsi
	+++ b/sys/gnu/dts/arm/ecx-common.dtsi
	@@ -1,230 +1,231 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright 2011-2012 Calxeda, Inc.
	*/

	/ {
	chosen {
	bootargs = "console=ttyAMA0";
	};

	psci {
	compatible = "arm,psci";
	method = "smc";
	cpu_suspend = <0x84000002>;
	cpu_off = <0x84000004>;
	cpu_on = <0x84000006>;
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&intc>;

	sata@ffe08000 {
	compatible = "calxeda,hb-ahci";
	reg = <0xffe08000 0x10000>;
	interrupts = <0 83 4>;
	dma-coherent;
	- calxeda,port-phys = <&combophy5 0 &combophy0 0
	- &combophy0 1 &combophy0 2
	- &combophy0 3>;
	- calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
	+ calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
	+ <&combophy0 1>, <&combophy0 2>,
	+ <&combophy0 3>;
	+ calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
	+ <&gpioh 7 1>;
	calxeda,led-order = <4 0 1 2 3>;
	};

	sdhci@ffe0e000 {
	compatible = "calxeda,hb-sdhci";
	reg = <0xffe0e000 0x1000>;
	interrupts = <0 90 4>;
	clocks = <&eclk>;
	status = "disabled";
	};

	ipc@fff20000 {
	compatible = "arm,pl320", "arm,primecell";
	reg = <0xfff20000 0x1000>;
	interrupts = <0 7 4>;
	clocks = <&pclk>;
	clock-names = "apb_pclk";
	};

	gpioe: gpio@fff30000 {
	#gpio-cells = <2>;
	compatible = "arm,pl061", "arm,primecell";
	gpio-controller;
	reg = <0xfff30000 0x1000>;
	interrupts = <0 14 4>;
	clocks = <&pclk>;
	clock-names = "apb_pclk";
	status = "disabled";
	};

	gpiof: gpio@fff31000 {
	#gpio-cells = <2>;
	compatible = "arm,pl061", "arm,primecell";
	gpio-controller;
	reg = <0xfff31000 0x1000>;
	interrupts = <0 15 4>;
	clocks = <&pclk>;
	clock-names = "apb_pclk";
	status = "disabled";
	};

	gpiog: gpio@fff32000 {
	#gpio-cells = <2>;
	compatible = "arm,pl061", "arm,primecell";
	gpio-controller;
	reg = <0xfff32000 0x1000>;
	interrupts = <0 16 4>;
	clocks = <&pclk>;
	clock-names = "apb_pclk";
	status = "disabled";
	};

	gpioh: gpio@fff33000 {
	#gpio-cells = <2>;
	compatible = "arm,pl061", "arm,primecell";
	gpio-controller;
	reg = <0xfff33000 0x1000>;
	interrupts = <0 17 4>;
	clocks = <&pclk>;
	clock-names = "apb_pclk";
	status = "disabled";
	};

	timer@fff34000 {
	compatible = "arm,sp804", "arm,primecell";
	reg = <0xfff34000 0x1000>;
	interrupts = <0 18 4>;
	clocks = <&pclk>;
	clock-names = "apb_pclk";
	};

	rtc@fff35000 {
	compatible = "arm,pl031", "arm,primecell";
	reg = <0xfff35000 0x1000>;
	interrupts = <0 19 4>;
	clocks = <&pclk>;
	clock-names = "apb_pclk";
	};

	serial@fff36000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0xfff36000 0x1000>;
	interrupts = <0 20 4>;
	- clocks = <&pclk>;
	- clock-names = "apb_pclk";
	+ clocks = <&pclk>, <&pclk>;
	+ clock-names = "uartclk", "apb_pclk";
	};

	smic@fff3a000 {
	compatible = "ipmi-smic";
	device_type = "ipmi";
	reg = <0xfff3a000 0x1000>;
	interrupts = <0 24 4>;
	reg-size = <4>;
	reg-spacing = <4>;
	};

	sregs@fff3c000 {
	compatible = "calxeda,hb-sregs";
	reg = <0xfff3c000 0x1000>;

	clocks {
	#address-cells = <1>;
	#size-cells = <0>;

	osc: oscillator {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <33333000>;
	};

	ddrpll: ddrpll {
	#clock-cells = <0>;
	compatible = "calxeda,hb-pll-clock";
	clocks = <&osc>;
	reg = <0x108>;
	};

	a9pll: a9pll {
	#clock-cells = <0>;
	compatible = "calxeda,hb-pll-clock";
	clocks = <&osc>;
	reg = <0x100>;
	};

	a9periphclk: a9periphclk {
	#clock-cells = <0>;
	compatible = "calxeda,hb-a9periph-clock";
	clocks = <&a9pll>;
	reg = <0x104>;
	};

	a9bclk: a9bclk {
	#clock-cells = <0>;
	compatible = "calxeda,hb-a9bus-clock";
	clocks = <&a9pll>;
	reg = <0x104>;
	};

	emmcpll: emmcpll {
	#clock-cells = <0>;
	compatible = "calxeda,hb-pll-clock";
	clocks = <&osc>;
	reg = <0x10C>;
	};

	eclk: eclk {
	#clock-cells = <0>;
	compatible = "calxeda,hb-emmc-clock";
	clocks = <&emmcpll>;
	reg = <0x114>;
	};

	pclk: pclk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <150000000>;
	};
	};
	};

	dma@fff3d000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0xfff3d000 0x1000>;
	interrupts = <0 92 4>;
	clocks = <&pclk>;
	clock-names = "apb_pclk";
	};

	ethernet@fff50000 {
	compatible = "calxeda,hb-xgmac";
	reg = <0xfff50000 0x1000>;
	- interrupts = <0 77 4 0 78 4 0 79 4>;
	+ interrupts = <0 77 4>, <0 78 4>, <0 79 4>;
	dma-coherent;
	};

	ethernet@fff51000 {
	compatible = "calxeda,hb-xgmac";
	reg = <0xfff51000 0x1000>;
	- interrupts = <0 80 4 0 81 4 0 82 4>;
	+ interrupts = <0 80 4>, <0 81 4>, <0 82 4>;
	dma-coherent;
	};

	combophy0: combo-phy@fff58000 {
	compatible = "calxeda,hb-combophy";
	#phy-cells = <1>;
	reg = <0xfff58000 0x1000>;
	phydev = <5>;
	};

	combophy5: combo-phy@fff5d000 {
	compatible = "calxeda,hb-combophy";
	#phy-cells = <1>;
	reg = <0xfff5d000 0x1000>;
	phydev = <31>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/exynos3250-artik5.dtsi b/sys/gnu/dts/arm/exynos3250-artik5.dtsi
	index dee35e3a5c4b..b27a82072365 100644
	--- a/sys/gnu/dts/arm/exynos3250-artik5.dtsi
	+++ b/sys/gnu/dts/arm/exynos3250-artik5.dtsi
	@@ -1,381 +1,381 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Samsung's Exynos3250 based ARTIK5 module device tree source
	*
	* Copyright (c) 2016 Samsung Electronics Co., Ltd.
	* http://www.samsung.com
	*
	* Device tree source file for Samsung's ARTIK5 module which is based on
	* Samsung Exynos3250 SoC.
	*/

	#include "exynos3250.dtsi"
	#include <dt-bindings/clock/samsung,s2mps11.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/irq.h>

	/ {
	compatible = "samsung,artik5", "samsung,exynos3250", "samsung,exynos3";

	chosen {
	stdout-path = &serial_2;
	};

	memory@40000000 {
	device_type = "memory";
	- reg = <0x40000000 0x1ff00000>;
	+ reg = <0x40000000 0x1f800000>;
	};

	firmware@205f000 {
	compatible = "samsung,secure-firmware";
	reg = <0x0205f000 0x1000>;
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	cooling-maps {
	map0 {
	/* Corresponds to 500MHz */
	cooling-device = <&cpu0 5 5>,
	<&cpu1 5 5>;
	};
	map1 {
	/* Corresponds to 200MHz */
	cooling-device = <&cpu0 8 8>,
	<&cpu1 8 8>;
	};
	};
	};
	};
	};

	&adc {
	vdd-supply = <&ldo7_reg>;
	assigned-clocks = <&cmu CLK_SCLK_TSADC>;
	assigned-clock-rates = <6000000>;
	};

	&cpu0 {
	cpu0-supply = <&buck2_reg>;
	};

	&gpu {
	mali-supply = <&buck3_reg>;
	status = "okay";
	};

	&i2c_0 {
	#address-cells = <1>;
	#size-cells = <0>;
	samsung,i2c-sda-delay = <100>;
	samsung,i2c-slave-addr = <0x10>;
	samsung,i2c-max-bus-freq = <100000>;
	status = "okay";

	s2mps14_pmic@66 {
	compatible = "samsung,s2mps14-pmic";
	interrupt-parent = <&gpx3>;
	interrupts = <5 IRQ_TYPE_NONE>;
	pinctrl-names = "default";
	pinctrl-0 = <&s2mps14_irq>;
	reg = <0x66>;

	s2mps14_osc: clocks {
	compatible = "samsung,s2mps14-clk";
	#clock-cells = <1>;
	clock-output-names = "s2mps14_ap", "unused",
	"s2mps14_bt";
	};

	regulators {
	ldo1_reg: LDO1 {
	/* VDD_ALIVE15x */
	regulator-name = "VLDO1_1.0V";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	ldo2_reg: LDO2 {
	/* VDDQM176 ~ VDDQM185 */
	regulator-name = "VLDO2_1.2V";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	ldo3_reg: LDO3 {
	/*
	* VDD1_E106 ~ VDD1_E111
	* DVDD_RTC_AP, DVDD_MMC2_AP
	*/
	regulator-name = "VLDO3_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	ldo4_reg: LDO4 {
	/* AVDD_PLL1120 ~ AVDD_PLL11201 */
	regulator-name = "VLDO4_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	ldo5_reg: LDO5 {
	/* VDDI_PLL_ISO141 ~ VDDI_PLL_ISO142 */
	regulator-name = "VLDO5_1.0V";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	ldo6_reg: LDO6 {
	/* VDD_USB, VDD10_HSIC */
	regulator-name = "VLDO6_1.0V";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	ldo7_reg: LDO7 {
	/*
	* VDD18P, AVDD18_TS, AVDD18_HSIC, AVDD_PLL2,
	* AVDD_ADC, AVDD_ABB_0, M4S_VDD18
	*/
	regulator-name = "VLDO7_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	ldo8_reg: LDO8 {
	/* AVDD33_UOTG */
	regulator-name = "VLDO8_3.0V";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;
	};

	ldo9_reg: LDO9 {
	/* VDDQ_E86 ~ VDDQ_E105*/
	regulator-name = "VLDO9_1.2V";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	ldo10_reg: LDO10 {
	regulator-name = "VLDO10_1.0V";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	};

	ldo11_reg: LDO11 {
	/* VDD74 ~ VDD75 */
	regulator-name = "VLDO11_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
	};

	ldo12_reg: LDO12 {
	/* VDD72 ~ VDD73 */
	regulator-name = "VLDO12_2.8V";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
	};

	ldo13_reg: LDO13 {
	regulator-name = "VLDO13_2.8V";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	ldo14_reg: LDO14 {
	regulator-name = "VLDO14_2.7V";
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <2700000>;
	};

	ldo15_reg: LDO15 {
	regulator-name = "VLDO_3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	ldo16_reg: LDO16 {
	regulator-name = "VLDO16_3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	ldo17_reg: LDO17 {
	regulator-name = "VLDO17_3.0V";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	};

	ldo18_reg: LDO18 {
	/* DVDD_MMC2_AP */
	regulator-name = "VLDO18_2.8V";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	ldo19_reg: LDO19 {
	regulator-name = "VLDO19_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo20_reg: LDO20 {
	regulator-name = "VLDO20_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo21_reg: LDO21 {
	regulator-name = "VLDO21_1.25V";
	regulator-min-microvolt = <1250000>;
	regulator-max-microvolt = <1250000>;
	};

	ldo22_reg: LDO22 {
	regulator-name = "VLDO22_1.2V";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	ldo23_reg: LDO23 {
	/* Xi2c3_SDA/SCL, Xi2c7_SDA/SCL, WLAN_SDIO */
	regulator-name = "VLDO23_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	ldo24_reg: LDO24 {
	regulator-name = "VLDO24_3.0V";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	};

	ldo25_reg: LDO25 {
	regulator-name = "VLDO25_3.0V";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	};

	buck1_reg: BUCK1 {
	/* VDD_MIF */
	regulator-name = "VBUCK1_1.0V";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	buck2_reg: BUCK2 {
	/* VDD_CPU */
	regulator-name = "VBUCK2_1.2V";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	buck3_reg: BUCK3 {
	/* VDD_G3D */
	regulator-name = "VBUCK3_1.0V";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	buck4_reg: BUCK4 {
	regulator-name = "VBUCK4_1.95V";
	regulator-min-microvolt = <1950000>;
	regulator-max-microvolt = <1950000>;
	regulator-always-on;
	};

	buck5_reg: BUCK5 {
	regulator-name = "VBUCK5_1.35V";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	};
	};
	};
	};

	&mshc_0 {
	non-removable;
	cap-mmc-highspeed;
	card-detect-delay = <200>;
	vmmc-supply = <&ldo12_reg>;
	clock-frequency = <100000000>;
	max-frequency = <100000000>;
	samsung,dw-mshc-ciu-div = <1>;
	samsung,dw-mshc-sdr-timing = <0 1>;
	samsung,dw-mshc-ddr-timing = <1 2>;
	pinctrl-names = "default";
	pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
	bus-width = <8>;
	status = "okay";
	};

	&mshc_1 {
	cap-sd-highspeed;
	cap-sdio-irq;
	disable-wp;
	non-removable;
	keep-power-in-suspend;
	fifo-depth = <0x40>;
	vqmmc-supply = <&ldo11_reg>;
	/*
	* Voltage negotiation is broken for the SDIO periph so we
	* can't actually set the voltage here.
	* vmmc-supply = <&ldo23_reg>;
	*/
	card-detect-delay = <500>;
	clock-frequency = <100000000>;
	max-frequency = <100000000>;
	samsung,dw-mshc-ciu-div = <3>;
	samsung,dw-mshc-sdr-timing = <0 1>;
	samsung,dw-mshc-ddr-timing = <1 2>;
	pinctrl-names = "default";
	pinctrl-0 = <&sd1_cmd &sd1_clk &sd1_bus1 &sd1_bus4 &wlanen>;
	bus-width = <4>;
	status = "okay";
	};

	&pinctrl_1 {
	wlanen: wlanen {
	samsung,pins = "gpx2-3";
	samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
	samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	samsung,pin-drv = <EXYNOS4_PIN_DRV_LV3>;
	samsung,pin-val = <1>;
	};

	s2mps14_irq: s2mps14-irq {
	samsung,pins = "gpx3-5";
	samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};
	};

	&rtc {
	clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>;
	clock-names = "rtc", "rtc_src";
	status = "okay";
	};

	&tmu {
	status = "okay";
	};

	&xusbxti {
	clock-frequency = <24000000>;
	};
	diff --git a/sys/gnu/dts/arm/exynos4210-universal_c210.dts b/sys/gnu/dts/arm/exynos4210-universal_c210.dts
	index a1bdf7830a87..9dda6bdb9253 100644
	--- a/sys/gnu/dts/arm/exynos4210-universal_c210.dts
	+++ b/sys/gnu/dts/arm/exynos4210-universal_c210.dts
	@@ -1,605 +1,603 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Samsung's Exynos4210 based Universal C210 board device tree source
	*
	* Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
	* http://www.samsung.com
	*
	* Device tree source file for Samsung's Universal C210 board which is based on
	* Samsung's Exynos4210 rev0 SoC.
	*/

	/dts-v1/;
	#include "exynos4210.dtsi"
	#include <dt-bindings/gpio/gpio.h>

	/ {
	model = "Samsung Universal C210 based on Exynos4210 rev0";
	compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4";

	memory@40000000 {
	device_type = "memory";
	reg = <0x40000000 0x10000000
	0x50000000 0x10000000>;
	};

	chosen {
	bootargs = "root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1";
	stdout-path = "serial2:115200n8";
	};


	fixed-rate-clocks {
	xxti {
	compatible = "samsung,clock-xxti";
	clock-frequency = <0>;
	};

	xusbxti {
	compatible = "samsung,clock-xusbxti";
	clock-frequency = <24000000>;
	};
	};

	vemmc_reg: voltage-regulator {
	compatible = "regulator-fixed";
	regulator-name = "VMEM_VDD_2_8V";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	gpio = <&gpe1 3 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	gpio-keys {
	compatible = "gpio-keys";

	vol-up-key {
	gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
	linux,code = <115>;
	label = "volume up";
	debounce-interval = <1>;
	};

	vol-down-key {
	gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
	linux,code = <114>;
	label = "volume down";
	debounce-interval = <1>;
	};

	config-key {
	gpios = <&gpx2 2 GPIO_ACTIVE_LOW>;
	linux,code = <171>;
	label = "config";
	debounce-interval = <1>;
	wakeup-source;
	};

	camera-key {
	gpios = <&gpx2 3 GPIO_ACTIVE_LOW>;
	linux,code = <212>;
	label = "camera";
	debounce-interval = <1>;
	};

	power-key {
	gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
	linux,code = <116>;
	label = "power";
	debounce-interval = <1>;
	wakeup-source;
	};

	ok-key {
	gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
	linux,code = <352>;
	label = "ok";
	debounce-interval = <1>;
	};
	};

	tsp_reg: voltage-regulator {
	compatible = "regulator-fixed";
	regulator-name = "TSP_2_8V";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	gpio = <&gpe2 3 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	spi-lcd {
	compatible = "spi-gpio";
	#address-cells = <1>;
	#size-cells = <0>;

	gpio-sck = <&gpy3 1 GPIO_ACTIVE_HIGH>;
	gpio-mosi = <&gpy3 3 GPIO_ACTIVE_HIGH>;
	num-chipselects = <1>;
	- cs-gpios = <&gpy4 3 GPIO_ACTIVE_HIGH>;
	+ cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>;

	lcd@0 {
	compatible = "samsung,ld9040";
	reg = <0>;
	vdd3-supply = <&ldo7_reg>;
	vci-supply = <&ldo17_reg>;
	reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>;
	spi-max-frequency = <1200000>;
	- spi-cpol;
	- spi-cpha;
	power-on-delay = <10>;
	reset-delay = <10>;
	panel-width-mm = <90>;
	panel-height-mm = <154>;
	display-timings {
	timing {
	clock-frequency = <23492370>;
	hactive = <480>;
	vactive = <800>;
	hback-porch = <16>;
	hfront-porch = <16>;
	vback-porch = <2>;
	vfront-porch = <28>;
	hsync-len = <2>;
	vsync-len = <1>;
	hsync-active = <0>;
	vsync-active = <0>;
	de-active = <0>;
	pixelclk-active = <0>;
	};
	};
	port {
	lcd_ep: endpoint {
	remote-endpoint = <&fimd_dpi_ep>;
	};
	};
	};
	};

	hdmi_en: voltage-regulator-hdmi-5v {
	compatible = "regulator-fixed";
	regulator-name = "HDMI_5V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpe0 1 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	hdmi_ddc: i2c-ddc {
	compatible = "i2c-gpio";
	gpios = <&gpe4 2 GPIO_ACTIVE_HIGH &gpe4 3 GPIO_ACTIVE_HIGH>;
	i2c-gpio,delay-us = <100>;
	#address-cells = <1>;
	#size-cells = <0>;

	pinctrl-0 = <&i2c_ddc_bus>;
	pinctrl-names = "default";
	status = "okay";
	};
	};

	&amba {
	mdma0: mdma@12840000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x12840000 0x1000>;
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clock CLK_MDMA>;
	clock-names = "apb_pclk";
	#dma-cells = <1>;
	#dma-channels = <8>;
	#dma-requests = <1>;
	power-domains = <&pd_lcd0>;
	};
	};

	&camera {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <>;
	};

	&cpu0 {
	cpu0-supply = <&vdd_arm_reg>;
	};

	&ehci {
	status = "okay";
	phys = <&exynos_usbphy 1>;
	phy-names = "host";
	};

	&exynos_usbphy {
	status = "okay";
	vbus-supply = <&safeout1_reg>;
	};

	&fimc_0 {
	status = "okay";
	assigned-clocks = <&clock CLK_MOUT_FIMC0>,
	<&clock CLK_SCLK_FIMC0>;
	assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
	assigned-clock-rates = <0>, <160000000>;
	};

	&fimc_1 {
	status = "okay";
	assigned-clocks = <&clock CLK_MOUT_FIMC1>,
	<&clock CLK_SCLK_FIMC1>;
	assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
	assigned-clock-rates = <0>, <160000000>;
	};

	&fimc_2 {
	status = "okay";
	assigned-clocks = <&clock CLK_MOUT_FIMC2>,
	<&clock CLK_SCLK_FIMC2>;
	assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
	assigned-clock-rates = <0>, <160000000>;
	};

	&fimc_3 {
	status = "okay";
	assigned-clocks = <&clock CLK_MOUT_FIMC3>,
	<&clock CLK_SCLK_FIMC3>;
	assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
	assigned-clock-rates = <0>, <160000000>;
	};

	&fimd {
	pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
	pinctrl-names = "default";
	status = "okay";
	samsung,invert-vden;
	samsung,invert-vclk;
	#address-cells = <1>;
	#size-cells = <0>;
	port@3 {
	reg = <3>;
	fimd_dpi_ep: endpoint {
	remote-endpoint = <&lcd_ep>;
	};
	};
	};

	&gpu {
	mali-supply = <&buck2_reg>;
	status = "okay";
	};

	&hdmi {
	hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_hpd>;
	hdmi-en-supply = <&hdmi_en>;
	vdd-supply = <&ldo3_reg>;
	vdd_osc-supply = <&ldo4_reg>;
	vdd_pll-supply = <&ldo3_reg>;
	ddc = <&hdmi_ddc>;
	status = "okay";
	};

	&hsotg {
	vusb_d-supply = <&ldo3_reg>;
	vusb_a-supply = <&ldo8_reg>;
	dr_mode = "peripheral";
	status = "okay";
	};

	&i2c_3 {
	samsung,i2c-sda-delay = <100>;
	samsung,i2c-slave-addr = <0x10>;
	samsung,i2c-max-bus-freq = <100000>;
	pinctrl-0 = <&i2c3_bus>;
	pinctrl-names = "default";
	status = "okay";

	tsp@4a {
	/* TBD: Atmel maXtouch touchscreen */
	reg = <0x4a>;
	};
	};

	&i2c_5 {
	samsung,i2c-sda-delay = <100>;
	samsung,i2c-slave-addr = <0x10>;
	samsung,i2c-max-bus-freq = <100000>;
	pinctrl-0 = <&i2c5_bus>;
	pinctrl-names = "default";
	status = "okay";

	vdd_arm_reg: pmic@60 {
	compatible = "maxim,max8952";
	reg = <0x60>;

	max8952,vid-gpios = <&gpx0 3 GPIO_ACTIVE_HIGH>,
	<&gpx0 4 GPIO_ACTIVE_HIGH>;
	max8952,default-mode = <0>;
	max8952,dvs-mode-microvolt = <1250000>, <1200000>,
	<1050000>, <950000>;
	max8952,sync-freq = <0>;
	max8952,ramp-speed = <0>;

	regulator-name = "vdd_arm";
	regulator-min-microvolt = <770000>;
	regulator-max-microvolt = <1400000>;
	regulator-always-on;
	regulator-boot-on;
	};

	pmic@66 {
	compatible = "national,lp3974";
	interrupts-extended = <&gpx0 7 0>, <&gpx2 7 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&lp3974_irq>;
	reg = <0x66>;

	max8998,pmic-buck1-default-dvs-idx = <0>;
	max8998,pmic-buck1-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>,
	<&gpx0 6 GPIO_ACTIVE_HIGH>;
	max8998,pmic-buck1-dvs-voltage = <1100000>, <1000000>,
	<1100000>, <1000000>;

	max8998,pmic-buck2-default-dvs-idx = <0>;
	max8998,pmic-buck2-dvs-gpio = <&gpe2 0 GPIO_ACTIVE_HIGH>;
	max8998,pmic-buck2-dvs-voltage = <1200000>, <1100000>;

	regulators {
	ldo2_reg: LDO2 {
	regulator-name = "VALIVE_1.2V";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	ldo3_reg: LDO3 {
	regulator-name = "VUSB+MIPI_1.1V";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;
	};

	ldo4_reg: LDO4 {
	regulator-name = "VADC_3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	ldo5_reg: LDO5 {
	regulator-name = "VTF_2.8V";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	ldo6_reg: LDO6 {
	regulator-name = "LDO6";
	regulator-min-microvolt = <2000000>;
	regulator-max-microvolt = <2000000>;
	};

	ldo7_reg: LDO7 {
	regulator-name = "VLCD+VMIPI_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo8_reg: LDO8 {
	regulator-name = "VUSB+VDAC_3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	ldo9_reg: LDO9 {
	regulator-name = "VCC_2.8V";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-always-on;
	};

	ldo10_reg: LDO10 {
	regulator-name = "VPLL_1.1V";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo11_reg: LDO11 {
	regulator-name = "CAM_AF_3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	ldo12_reg: LDO12 {
	regulator-name = "PS_2.8V";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	ldo13_reg: LDO13 {
	regulator-name = "VHIC_1.2V";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	ldo14_reg: LDO14 {
	regulator-name = "CAM_I_HOST_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo15_reg: LDO15 {
	regulator-name = "CAM_S_DIG+FM33_CORE_1.2V";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	ldo16_reg: LDO16 {
	regulator-name = "CAM_S_ANA_2.8V";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	ldo17_reg: LDO17 {
	regulator-name = "VCC_3.0V_LCD";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	};

	buck1_reg: BUCK1 {
	regulator-name = "VINT_1.1V";
	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <1500000>;
	regulator-boot-on;
	regulator-always-on;
	};

	buck2_reg: BUCK2 {
	regulator-name = "VG3D_1.1V";
	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <1500000>;
	regulator-boot-on;
	};

	buck3_reg: BUCK3 {
	regulator-name = "VCC_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	buck4_reg: BUCK4 {
	regulator-name = "VMEM_1.2V";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	ap32khz_reg: EN32KHz-AP {
	regulator-name = "32KHz AP";
	regulator-always-on;
	};

	cp32khz_reg: EN32KHz-CP {
	regulator-name = "32KHz CP";
	};

	vichg_reg: ENVICHG {
	regulator-name = "VICHG";
	};

	safeout1_reg: ESAFEOUT1 {
	regulator-name = "SAFEOUT1";
	};

	safeout2_reg: ESAFEOUT2 {
	regulator-name = "SAFEOUT2";
	regulator-boot-on;
	};
	};
	};
	};

	&i2c_8 {
	status = "okay";
	};

	&mct {
	compatible = "none";
	};

	&mdma1 {
	/* Use the secure mdma0 */
	status = "disabled";
	};

	&mixer {
	status = "okay";
	};

	&ohci {
	status = "okay";
	};

	&pinctrl_1 {
	lp3974_irq: lp3974-irq {
	samsung,pins = "gpx0-7", "gpx2-7";
	samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};

	hdmi_hpd: hdmi-hpd {
	samsung,pins = "gpx3-7";
	samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};
	};

	&pinctrl_0 {
	i2c_ddc_bus: i2c-ddc-bus {
	samsung,pins = "gpe4-2", "gpe4-3";
	samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
	samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
	samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
	};
	};

	&pwm {
	compatible = "samsung,s5p6440-pwm";
	status = "okay";
	};

	&sdhci_0 {
	bus-width = <8>;
	non-removable;
	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>;
	pinctrl-names = "default";
	vmmc-supply = <&vemmc_reg>;
	status = "okay";
	};

	&sdhci_2 {
	bus-width = <4>;
	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
	pinctrl-names = "default";
	vmmc-supply = <&ldo5_reg>;
	cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&serial_0 {
	status = "okay";
	/delete-property/dmas;
	/delete-property/dma-names;
	};

	&serial_1 {
	status = "okay";
	/delete-property/dmas;
	/delete-property/dma-names;
	};

	&serial_2 {
	status = "okay";
	/delete-property/dmas;
	/delete-property/dma-names;
	};

	&serial_3 {
	status = "okay";
	/delete-property/dmas;
	/delete-property/dma-names;
	};

	&sysram {
	smp-sram@0 {
	status = "disabled";
	};

	smp-sram@5000 {
	compatible = "samsung,exynos4210-sysram";
	reg = <0x5000 0x1000>;
	};

	smp-sram@1f000 {
	status = "disabled";
	};
	};
	diff --git a/sys/gnu/dts/arm/exynos4412-odroid-common.dtsi b/sys/gnu/dts/arm/exynos4412-odroid-common.dtsi
	index 9c39e82e4ecb..73d6a71da88d 100644
	--- a/sys/gnu/dts/arm/exynos4412-odroid-common.dtsi
	+++ b/sys/gnu/dts/arm/exynos4412-odroid-common.dtsi
	@@ -1,564 +1,573 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
	* device tree source
	*/

	#include <dt-bindings/sound/samsung-i2s.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/clock/maxim,max77686.h>
	#include "exynos4412.dtsi"
	#include "exynos4412-ppmu-common.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include "exynos-mfc-reserved-memory.dtsi"

	/ {
	chosen {
	stdout-path = &serial_1;
	};

	firmware@204f000 {
	compatible = "samsung,secure-firmware";
	reg = <0x0204F000 0x1000>;
	};

	gpio_keys {
	compatible = "gpio-keys";
	pinctrl-names = "default";
	pinctrl-0 = <&gpio_power_key>;

	power_key {
	gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_POWER>;
	label = "power key";
	debounce-interval = <10>;
	wakeup-source;
	};
	};

	sound: sound {
	compatible = "hardkernel,odroid-xu4-audio";

	cpu {
	sound-dai = <&i2s0 0>;
	};

	codec {
	sound-dai = <&hdmi>, <&max98090>;
	};
	};

	emmc_pwrseq: pwrseq {
	pinctrl-0 = <&emmc_rstn>;
	pinctrl-names = "default";
	compatible = "mmc-pwrseq-emmc";
	reset-gpios = <&gpk1 2 GPIO_ACTIVE_LOW>;
	};

	fixed-rate-clocks {
	xxti {
	compatible = "samsung,clock-xxti";
	clock-frequency = <0>;
	};

	xusbxti {
	compatible = "samsung,clock-xusbxti";
	clock-frequency = <24000000>;
	};
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	cooling-maps {
	cooling_map0: map0 {
	/* Corresponds to 800MHz at freq_table */
	cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
	<&cpu2 7 7>, <&cpu3 7 7>;
	};
	cooling_map1: map1 {
	/* Corresponds to 200MHz at freq_table */
	cooling-device = <&cpu0 13 13>,
	<&cpu1 13 13>,
	<&cpu2 13 13>,
	<&cpu3 13 13>;
	};
	};
	};
	};
	};

	&bus_dmc {
	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
	vdd-supply = <&buck1_reg>;
	status = "okay";
	};

	&bus_acp {
	devfreq = <&bus_dmc>;
	status = "okay";
	};

	&bus_c2c {
	devfreq = <&bus_dmc>;
	status = "okay";
	};

	&bus_leftbus {
	devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
	vdd-supply = <&buck3_reg>;
	status = "okay";
	};

	&bus_rightbus {
	devfreq = <&bus_leftbus>;
	status = "okay";
	};

	&bus_display {
	devfreq = <&bus_leftbus>;
	status = "okay";
	};

	&bus_fsys {
	devfreq = <&bus_leftbus>;
	status = "okay";
	};

	&bus_peri {
	devfreq = <&bus_leftbus>;
	status = "okay";
	};

	&bus_mfc {
	devfreq = <&bus_leftbus>;
	status = "okay";
	};

	&camera {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <>;
	};

	&clock {
	assigned-clocks = <&clock CLK_FOUT_EPLL>;
	assigned-clock-rates = <45158401>;
	};

	&clock_audss {
	assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
	<&clock_audss EXYNOS_MOUT_I2S>,
	<&clock_audss EXYNOS_DOUT_SRP>,
	<&clock_audss EXYNOS_DOUT_AUD_BUS>,
	<&clock_audss EXYNOS_DOUT_I2S>;

	assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
	<&clock_audss EXYNOS_MOUT_AUDSS>;

	assigned-clock-rates = <0>, <0>,
	<196608001>,
	<(196608001 / 2)>,
	<(196608001 / 8)>;
	};

	&cpu0 {
	cpu0-supply = <&buck2_reg>;
	};

	+&cpu0_opp_table {
	+ opp-1000000000 {
	+ opp-suspend;
	+ };
	+ opp-800000000 {
	+ /delete-property/opp-suspend;
	+ };
	+};
	+
	&pinctrl_1 {
	gpio_power_key: power_key {
	samsung,pins = "gpx1-3";
	samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};

	max77686_irq: max77686-irq {
	samsung,pins = "gpx3-2";
	samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
	samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
	};

	hdmi_hpd: hdmi-hpd {
	samsung,pins = "gpx3-7";
	samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};

	emmc_rstn: emmc-rstn {
	samsung,pins = "gpk1-2";
	samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};
	};

	&ehci {
	status = "okay";
	};

	&exynos_usbphy {
	status = "okay";
	};

	&fimc_0 {
	status = "okay";
	assigned-clocks = <&clock CLK_MOUT_FIMC0>,
	<&clock CLK_SCLK_FIMC0>;
	assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
	assigned-clock-rates = <0>, <176000000>;
	};

	&fimc_1 {
	status = "okay";
	assigned-clocks = <&clock CLK_MOUT_FIMC1>,
	<&clock CLK_SCLK_FIMC1>;
	assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
	assigned-clock-rates = <0>, <176000000>;
	};

	&fimc_2 {
	status = "okay";
	assigned-clocks = <&clock CLK_MOUT_FIMC2>,
	<&clock CLK_SCLK_FIMC2>;
	assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
	assigned-clock-rates = <0>, <176000000>;
	};

	&fimc_3 {
	status = "okay";
	assigned-clocks = <&clock CLK_MOUT_FIMC3>,
	<&clock CLK_SCLK_FIMC3>;
	assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
	assigned-clock-rates = <0>, <176000000>;
	};

	&gpu {
	mali-supply = <&buck4_reg>;
	status = "okay";
	};

	&hdmi {
	hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_hpd>;
	vdd-supply = <&ldo8_reg>;
	vdd_osc-supply = <&ldo10_reg>;
	vdd_pll-supply = <&ldo8_reg>;
	ddc = <&i2c_2>;
	status = "okay";
	};

	&hdmicec {
	status = "okay";
	};

	&hsotg {
	dr_mode = "peripheral";
	status = "okay";
	vusb_d-supply = <&ldo15_reg>;
	vusb_a-supply = <&ldo12_reg>;
	};

	&i2c_0 {
	samsung,i2c-sda-delay = <100>;
	samsung,i2c-max-bus-freq = <400000>;
	status = "okay";

	usb3503: usb3503@8 {
	compatible = "smsc,usb3503";
	reg = <0x08>;

	intn-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>;
	connect-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>;
	reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
	initial-mode = <1>;
	};

	max77686: pmic@9 {
	compatible = "maxim,max77686";
	interrupt-parent = <&gpx3>;
	interrupts = <2 IRQ_TYPE_NONE>;
	pinctrl-names = "default";
	pinctrl-0 = <&max77686_irq>;
	reg = <0x09>;
	#clock-cells = <1>;

	voltage-regulators {
	ldo1_reg: LDO1 {
	regulator-name = "VDD_ALIVE_1.0V";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	ldo2_reg: LDO2 {
	regulator-name = "VDDQ_M1_2_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	ldo3_reg: LDO3 {
	regulator-name = "VDDQ_EXT_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	ldo4_reg: LDO4 {
	regulator-name = "VDDQ_MMC2_2.8V";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-boot-on;
	};

	ldo5_reg: LDO5 {
	regulator-name = "VDDQ_MMC1_3_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldo6_reg: LDO6 {
	regulator-name = "VDD10_MPLL_1.0V";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	ldo7_reg: LDO7 {
	regulator-name = "VDD10_XPLL_1.0V";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	ldo8_reg: LDO8 {
	regulator-name = "VDD10_HDMI_1.0V";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	};

	ldo10_reg: LDO10 {
	regulator-name = "VDDQ_MIPIHSI_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo11_reg: LDO11 {
	regulator-name = "VDD18_ABB1_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	ldo12_reg: LDO12 {
	regulator-name = "VDD33_USB_3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldo13_reg: LDO13 {
	regulator-name = "VDDQ_C2C_W_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldo14_reg: LDO14 {
	regulator-name = "VDD18_ABB0_2_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldo15_reg: LDO15 {
	regulator-name = "VDD10_HSIC_1.0V";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldo16_reg: LDO16 {
	regulator-name = "VDD18_HSIC_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldo20_reg: LDO20 {
	regulator-name = "LDO20_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo21_reg: LDO21 {
	regulator-name = "TFLASH_2.8V";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-boot-on;
	};

	ldo22_reg: LDO22 {
	/*
	* Only U3 uses it, so let it define the
	* constraints
	*/
	regulator-name = "LDO22";
	regulator-boot-on;
	};

	ldo25_reg: LDO25 {
	regulator-name = "VDDQ_LCD_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	buck1_reg: BUCK1 {
	regulator-name = "vdd_mif";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;
	regulator-boot-on;
	};

	buck2_reg: BUCK2 {
	regulator-name = "vdd_arm";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	};

	buck3_reg: BUCK3 {
	regulator-name = "vdd_int";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1050000>;
	regulator-always-on;
	regulator-boot-on;
	};

	buck4_reg: BUCK4 {
	regulator-name = "vdd_g3d";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1100000>;
	regulator-microvolt-offset = <50000>;
	};

	buck5_reg: BUCK5 {
	regulator-name = "VDDQ_CKEM1_2_1.2V";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	regulator-boot-on;
	};

	buck6_reg: BUCK6 {
	regulator-name = "BUCK6_1.35V";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	};

	buck7_reg: BUCK7 {
	regulator-name = "BUCK7_2.0V";
	regulator-min-microvolt = <2000000>;
	regulator-max-microvolt = <2000000>;
	regulator-always-on;
	};

	buck8_reg: BUCK8 {
	/*
	* Constraints set by specific board: X,
	* X2 and U3.
	*/
	regulator-name = "BUCK8_2.8V";
	};
	};
	};
	};

	&i2c_1 {
	status = "okay";
	max98090: max98090@10 {
	compatible = "maxim,max98090";
	reg = <0x10>;
	interrupt-parent = <&gpx0>;
	interrupts = <0 IRQ_TYPE_NONE>;
	clocks = <&i2s0 CLK_I2S_CDCLK>;
	clock-names = "mclk";
	#sound-dai-cells = <0>;
	};
	};

	&i2c_2 {
	status = "okay";
	};

	&i2c_8 {
	status = "okay";
	};

	&i2s0 {
	pinctrl-0 = <&i2s0_bus>;
	pinctrl-names = "default";
	status = "okay";
	assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
	assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
	};

	&mixer {
	status = "okay";
	};

	&mshc_0 {
	pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
	pinctrl-names = "default";
	vmmc-supply = <&ldo20_reg>;
	mmc-pwrseq = <&emmc_pwrseq>;
	status = "okay";

	broken-cd;
	card-detect-delay = <200>;
	samsung,dw-mshc-ciu-div = <3>;
	samsung,dw-mshc-sdr-timing = <2 3>;
	samsung,dw-mshc-ddr-timing = <1 2>;
	bus-width = <8>;
	cap-mmc-highspeed;
	};

	&rtc {
	status = "okay";
	clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
	clock-names = "rtc", "rtc_src";
	};

	&sdhci_2 {
	bus-width = <4>;
	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
	pinctrl-names = "default";
	vmmc-supply = <&ldo21_reg>;
	vqmmc-supply = <&ldo4_reg>;
	cd-gpios = <&gpk2 2 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&serial_0 {
	status = "okay";
	};

	&serial_1 {
	status = "okay";
	};

	&tmu {
	vtmu-supply = <&ldo10_reg>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/exynos5250-arndale.dts b/sys/gnu/dts/arm/exynos5250-arndale.dts
	index f8ebc620f42d..6904091d4837 100644
	--- a/sys/gnu/dts/arm/exynos5250-arndale.dts
	+++ b/sys/gnu/dts/arm/exynos5250-arndale.dts
	@@ -1,647 +1,651 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Samsung's Exynos5250 based Arndale board device tree source
	*
	* Copyright (c) 2013 Samsung Electronics Co., Ltd.
	* http://www.samsung.com
	*/

	/dts-v1/;
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/clock/samsung,s2mps11.h>
	#include <dt-bindings/sound/samsung-i2s.h>
	#include "exynos5250.dtsi"

	/ {
	model = "Insignal Arndale evaluation board based on Exynos5250";
	compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5";

	memory@40000000 {
	device_type = "memory";
	reg = <0x40000000 0x80000000>;
	};

	chosen {
	stdout-path = "serial2:115200n8";
	};

	gpio_keys {
	compatible = "gpio-keys";

	menu {
	label = "SW-TACT2";
	gpios = <&gpx1 4 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_MENU>;
	wakeup-source;
	};

	home {
	label = "SW-TACT3";
	gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_HOME>;
	wakeup-source;
	};

	up {
	label = "SW-TACT4";
	gpios = <&gpx1 6 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_UP>;
	wakeup-source;
	};

	down {
	label = "SW-TACT5";
	gpios = <&gpx1 7 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_DOWN>;
	wakeup-source;
	};

	back {
	label = "SW-TACT6";
	gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_BACK>;
	wakeup-source;
	};

	wakeup {
	label = "SW-TACT7";
	gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_WAKEUP>;
	wakeup-source;
	};
	};

	panel: panel {
	compatible = "boe,hv070wsa-100";
	power-supply = <&vcc_3v3_reg>;
	enable-gpios = <&gpd1 3 GPIO_ACTIVE_HIGH>;
	port {
	panel_ep: endpoint {
	remote-endpoint = <&bridge_out_ep>;
	};
	};
	};

	regulators {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	main_dc_reg: regulator@0 {
	compatible = "regulator-fixed";
	reg = <0>;
	regulator-name = "MAIN_DC";
	+ regulator-always-on;
	};

	mmc_reg: regulator@1 {
	compatible = "regulator-fixed";
	reg = <1>;
	- regulator-name = "VDD_33ON_2.8V";
	+ regulator-name = "VDD_MMC";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	- gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
	- enable-active-high;
	+ regulator-always-on;
	};

	reg_hdmi_en: regulator@2 {
	compatible = "regulator-fixed";
	reg = <2>;
	regulator-name = "hdmi-en";
	+ regulator-always-on;
	};

	vcc_1v2_reg: regulator@3 {
	compatible = "regulator-fixed";
	reg = <3>;
	regulator-name = "VCC_1V2";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	+ regulator-always-on;
	};

	vcc_1v8_reg: regulator@4 {
	compatible = "regulator-fixed";
	reg = <4>;
	regulator-name = "VCC_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	+ regulator-always-on;
	};

	vcc_3v3_reg: regulator@5 {
	compatible = "regulator-fixed";
	reg = <5>;
	regulator-name = "VCC_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	+ regulator-always-on;
	};
	};

	sound {
	compatible = "samsung,arndale-wm1811";
	samsung,audio-cpu = <&i2s0>;
	samsung,audio-codec = <&wm1811>;
	};

	fixed-rate-clocks {
	xxti {
	compatible = "samsung,clock-xxti";
	clock-frequency = <24000000>;
	};
	};

	// SMSC USB3503 connected in hardware only mode as a PHY
	usb_hub: usb-hub {
	compatible = "smsc,usb3503a";

	reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
	connect-gpios = <&gpd1 7 GPIO_ACTIVE_HIGH>;
	};
	};

	&clock {
	assigned-clocks = <&clock CLK_FOUT_EPLL>;
	assigned-clock-rates = <49152000>;
	};

	&clock_audss {
	assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>;
	assigned-clock-parents = <&clock CLK_FOUT_EPLL>;
	};

	&cpu0 {
	cpu0-supply = <&buck2_reg>;
	};

	&dsi_0 {
	vddcore-supply = <&ldo8_reg>;
	vddio-supply = <&ldo10_reg>;
	samsung,pll-clock-frequency = <24000000>;
	samsung,burst-clock-frequency = <320000000>;
	samsung,esc-clock-frequency = <10000000>;
	status = "okay";

	bridge@0 {
	reg = <0>;
	compatible = "toshiba,tc358764";
	vddc-supply = <&vcc_1v2_reg>;
	vddio-supply = <&vcc_1v8_reg>;
	vddlvds-supply = <&vcc_3v3_reg>;
	reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>;
	#address-cells = <1>;
	#size-cells = <0>;
	port@1 {
	reg = <1>;
	bridge_out_ep: endpoint {
	remote-endpoint = <&panel_ep>;
	};
	};
	};
	};

	&fimd {
	status = "okay";
	};

	&hdmi {
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_hpd>;
	status = "okay";
	ddc = <&i2c_ddc>;
	hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
	vdd_osc-supply = <&ldo10_reg>;
	vdd_pll-supply = <&ldo8_reg>;
	vdd-supply = <&ldo8_reg>;
	};

	&i2c_0 {
	status = "okay";
	samsung,i2c-sda-delay = <100>;
	samsung,i2c-max-bus-freq = <20000>;
	samsung,i2c-slave-addr = <0x66>;

	s5m8767_pmic@66 {
	compatible = "samsung,s5m8767-pmic";
	reg = <0x66>;
	interrupt-parent = <&gpx3>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&s5m8767_irq>;

	vinb1-supply = <&main_dc_reg>;
	vinb2-supply = <&main_dc_reg>;
	vinb3-supply = <&main_dc_reg>;
	vinb4-supply = <&main_dc_reg>;
	vinb5-supply = <&main_dc_reg>;
	vinb6-supply = <&main_dc_reg>;
	vinb7-supply = <&main_dc_reg>;
	vinb8-supply = <&main_dc_reg>;
	vinb9-supply = <&main_dc_reg>;

	vinl1-supply = <&buck7_reg>;
	vinl2-supply = <&buck7_reg>;
	vinl3-supply = <&buck7_reg>;
	vinl4-supply = <&main_dc_reg>;
	vinl5-supply = <&main_dc_reg>;
	vinl6-supply = <&main_dc_reg>;
	vinl7-supply = <&main_dc_reg>;
	vinl8-supply = <&buck8_reg>;
	vinl9-supply = <&buck8_reg>;

	s5m8767,pmic-buck2-dvs-voltage = <1300000>;
	s5m8767,pmic-buck3-dvs-voltage = <1100000>;
	s5m8767,pmic-buck4-dvs-voltage = <1200000>;
	s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>,
	<&gpd1 1 GPIO_ACTIVE_HIGH>,
	<&gpd1 2 GPIO_ACTIVE_HIGH>;
	s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>,
	<&gpx2 4 GPIO_ACTIVE_HIGH>,
	<&gpx2 5 GPIO_ACTIVE_HIGH>;

	s5m8767_osc: clocks {
	compatible = "samsung,s5m8767-clk";
	#clock-cells = <1>;
	clock-output-names = "s5m8767_ap", "unused1", "unused2";
	};

	regulators {
	ldo1_reg: LDO1 {
	regulator-name = "VDD_ALIVE_1.0V";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	ldo2_reg: LDO2 {
	regulator-name = "VDD_28IO_DP_1.35V";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	ldo3_reg: LDO3 {
	regulator-name = "VDD_COMMON1_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	ldo4_reg: LDO4 {
	regulator-name = "VDD_IOPERI_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	op_mode = <1>;
	};

	ldo5_reg: LDO5 {
	regulator-name = "VDD_EXT_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	ldo6_reg: LDO6 {
	regulator-name = "VDD_MPLL_1.1V";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	ldo7_reg: LDO7 {
	regulator-name = "VDD_XPLL_1.1V";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	ldo8_reg: LDO8 {
	regulator-name = "VDD_COMMON2_1.0V";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	ldo9_reg: LDO9 {
	regulator-name = "VDD_33ON_3.0V";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	op_mode = <1>;
	};

	ldo10_reg: LDO10 {
	regulator-name = "VDD_COMMON3_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	ldo11_reg: LDO11 {
	regulator-name = "VDD_ABB2_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	ldo12_reg: LDO12 {
	regulator-name = "VDD_USB_3.0V";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	ldo13_reg: LDO13 {
	regulator-name = "VDDQ_C2C_W_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	ldo14_reg: LDO14 {
	regulator-name = "VDD18_ABB0_3_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	ldo15_reg: LDO15 {
	regulator-name = "VDD10_COMMON4_1.0V";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	ldo16_reg: LDO16 {
	regulator-name = "VDD18_HSIC_1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	ldo17_reg: LDO17 {
	regulator-name = "VDDQ_MMC2_3_2.8V";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	ldo18_reg: LDO18 {
	regulator-name = "VDD_33ON_2.8V";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	op_mode = <1>;
	};

	ldo22_reg: LDO22 {
	regulator-name = "EXT_33_OFF";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	op_mode = <1>;
	};

	ldo23_reg: LDO23 {
	regulator-name = "EXT_28_OFF";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	op_mode = <1>;
	};

	ldo25_reg: LDO25 {
	regulator-name = "PVDD_LDO25";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	op_mode = <1>;
	};

	ldo26_reg: LDO26 {
	regulator-name = "EXT_18_OFF";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	op_mode = <1>;
	};

	buck1_reg: BUCK1 {
	regulator-name = "vdd_mif";
	regulator-min-microvolt = <950000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	buck2_reg: BUCK2 {
	regulator-name = "vdd_arm";
	regulator-min-microvolt = <912500>;
	regulator-max-microvolt = <1300000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	buck3_reg: BUCK3 {
	regulator-name = "vdd_int";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	buck4_reg: BUCK4 {
	regulator-name = "vdd_g3d";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1300000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	buck5_reg: BUCK5 {
	regulator-name = "VDD_MEM_1.35V";
	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <1355000>;
	regulator-always-on;
	regulator-boot-on;
	op_mode = <1>;
	};

	buck7_reg: BUCK7 {
	regulator-name = "PVDD_BUCK7";
	regulator-always-on;
	op_mode = <1>;
	};

	buck8_reg: BUCK8 {
	regulator-name = "PVDD_BUCK8";
	regulator-always-on;
	op_mode = <1>;
	};

	buck9_reg: BUCK9 {
	regulator-name = "VDD_33_OFF_EXT1";
	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <3000000>;
	op_mode = <1>;
	};
	};
	};
	};

	&i2c_3 {
	status = "okay";

	wm1811: codec@1a {
	compatible = "wlf,wm1811";
	reg = <0x1a>;
	clocks = <&i2s0 CLK_I2S_CDCLK>;
	clock-names = "MCLK1";

	AVDD2-supply = <&main_dc_reg>;
	CPVDD-supply = <&main_dc_reg>;
	DBVDD1-supply = <&main_dc_reg>;
	DBVDD2-supply = <&main_dc_reg>;
	DBVDD3-supply = <&main_dc_reg>;
	LDO1VDD-supply = <&main_dc_reg>;
	SPKVDD1-supply = <&main_dc_reg>;
	SPKVDD2-supply = <&main_dc_reg>;

	wlf,ldo1ena = <&gpb0 0 GPIO_ACTIVE_HIGH>;
	wlf,ldo2ena = <&gpb0 1 GPIO_ACTIVE_HIGH>;
	};
	};

	&i2c_8 {
	status = "okay";
	/* used by HDMI PHY */
	samsung,i2c-sda-delay = <100>;
	samsung,i2c-max-bus-freq = <66000>;
	};

	&i2c_9 {
	status = "okay";
	samsung,i2c-sda-delay = <100>;
	samsung,i2c-max-bus-freq = <40000>;
	samsung,i2c-slave-addr = <0x38>;

	sata_phy_i2c:sata-phy@38 {
	compatible = "samsung,exynos-sataphy-i2c";
	reg = <0x38>;
	};
	};

	&i2s0 {
	assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
	assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
	status = "okay";
	};

	&i2s0_bus {
	samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
	};

	&mali {
	mali-supply = <&buck4_reg>;
	status = "okay";
	};

	&mixer {
	status = "okay";
	};

	&mmc_0 {
	status = "okay";
	broken-cd;
	card-detect-delay = <200>;
	samsung,dw-mshc-ciu-div = <3>;
	samsung,dw-mshc-sdr-timing = <2 3>;
	samsung,dw-mshc-ddr-timing = <1 2>;
	vmmc-supply = <&mmc_reg>;
	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
	bus-width = <8>;
	cap-mmc-highspeed;
	};

	&mmc_2 {
	status = "okay";
	card-detect-delay = <200>;
	samsung,dw-mshc-ciu-div = <3>;
	samsung,dw-mshc-sdr-timing = <2 3>;
	samsung,dw-mshc-ddr-timing = <1 2>;
	vmmc-supply = <&mmc_reg>;
	pinctrl-names = "default";
	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
	bus-width = <4>;
	disable-wp;
	cap-sd-highspeed;
	};

	&pinctrl_0 {
	s5m8767_irq: s5m8767-irq {
	samsung,pins = "gpx3-2";
	samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};
	};

	&rtc {
	clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>;
	clock-names = "rtc", "rtc_src";
	status = "okay";
	};

	&sata {
	status = "okay";
	};

	&sata_phy {
	status = "okay";
	samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
	};

	&soc {
	/*
	* For unknown reasons HDMI-DDC does not work with Exynos I2C
	* controllers. Lets use software I2C over GPIO pins as a workaround.
	*/
	i2c_ddc: i2c-gpio {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_gpio_bus>;
	status = "okay";
	compatible = "i2c-gpio";
	gpios = <&gpa0 6 0 /* sda */
	&gpa0 7 0 /* scl */
	>;
	i2c-gpio,delay-us = <2>;
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};
	diff --git a/sys/gnu/dts/arm/exynos5420-arndale-octa.dts b/sys/gnu/dts/arm/exynos5420-arndale-octa.dts
	index ee28d30f5476..e9a09dd0a49b 100644
	--- a/sys/gnu/dts/arm/exynos5420-arndale-octa.dts
	+++ b/sys/gnu/dts/arm/exynos5420-arndale-octa.dts
	@@ -1,824 +1,826 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Samsung's Exynos5420 based Arndale Octa board device tree source
	*
	* Copyright (c) 2013 Samsung Electronics Co., Ltd.
	* http://www.samsung.com
	*/

	/dts-v1/;
	#include "exynos5420.dtsi"
	#include "exynos5420-cpus.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/clock/samsung,s2mps11.h>

	/ {
	model = "Insignal Arndale Octa evaluation board based on Exynos5420";
	compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5";

	memory@20000000 {
	device_type = "memory";
	reg = <0x20000000 0x80000000>;
	};

	chosen {
	stdout-path = "serial3:115200n8";
	};

	firmware@2073000 {
	compatible = "samsung,secure-firmware";
	reg = <0x02073000 0x1000>;
	};

	fixed-rate-clocks {
	oscclk {
	compatible = "samsung,exynos5420-oscclk";
	clock-frequency = <24000000>;
	};
	};

	gpio_keys {
	compatible = "gpio-keys";

	wakeup {
	label = "SW-TACT1";
	gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_WAKEUP>;
	wakeup-source;
	};
	};
	};

	&adc {
	vdd-supply = <&ldo4_reg>;
	status = "okay";
	};

	&cci {
	status = "disabled";
	};

	&cpu0 {
	cpu-supply = <&buck2_reg>;
	};

	&cpu4 {
	cpu-supply = <&buck6_reg>;
	};

	&cpu0_thermal {
	trips {
	cpu0_alert0: cpu-alert-0 {
	temperature = <60000>; /* millicelsius */
	hysteresis = <5000>; /* millicelsius */
	type = "passive";
	};
	cpu0_alert1: cpu-alert-1 {
	temperature = <80000>; /* millicelsius */
	hysteresis = <10000>; /* millicelsius */
	type = "passive";
	};
	cpu0_alert2: cpu-alert-2 {
	temperature = <110000>; /* millicelsius */
	hysteresis = <10000>; /* millicelsius */
	type = "passive";
	};
	cpu0_crit0: cpu-crit-0 {
	temperature = <120000>; /* millicelsius */
	hysteresis = <0>; /* millicelsius */
	type = "critical";
	};
	};

	cooling-maps {
	/*
	* Reduce the CPU speed by 2 steps, down to: 1600 MHz
	* and 1100 MHz.
	*/
	map0 {
	trip = <&cpu0_alert0>;
	cooling-device = <&cpu0 0 2>,
	<&cpu1 0 2>,
	<&cpu2 0 2>,
	<&cpu3 0 2>,
	<&cpu4 0 2>,
	<&cpu5 0 2>,
	<&cpu6 0 2>,
	<&cpu7 0 2>;
	};

	/*
	* Reduce the CPU speed down to 1200 MHz big (6 steps)
	* and 800 MHz LITTLE (5 steps).
	*/
	map1 {
	trip = <&cpu0_alert1>;
	cooling-device = <&cpu0 3 6>,
	<&cpu1 3 6>,
	<&cpu2 3 6>,
	<&cpu3 3 6>,
	<&cpu4 3 5>,
	<&cpu5 3 5>,
	<&cpu6 3 5>,
	<&cpu7 3 5>;
	};

	/*
	* Reduce the CPU speed as much as possible, down to 700 MHz
	* big (11 steps) and 600 MHz LITTLE (7 steps).
	*/
	map2 {
	trip = <&cpu0_alert2>;
	cooling-device = <&cpu0 6 11>,
	<&cpu1 6 11>,
	<&cpu2 6 11>,
	<&cpu3 6 11>,
	<&cpu4 5 7>,
	<&cpu5 5 7>,
	<&cpu6 5 7>,
	<&cpu7 5 7>;
	};
	};
	};

	&cpu1_thermal {
	trips {
	cpu1_alert0: cpu-alert-0 {
	temperature = <60000>; /* millicelsius */
	hysteresis = <5000>; /* millicelsius */
	type = "passive";
	};
	cpu1_alert1: cpu-alert-1 {
	temperature = <80000>; /* millicelsius */
	hysteresis = <10000>; /* millicelsius */
	type = "passive";
	};
	cpu1_alert2: cpu-alert-2 {
	temperature = <110000>; /* millicelsius */
	hysteresis = <10000>; /* millicelsius */
	type = "passive";
	};
	cpu1_crit0: cpu-crit-0 {
	temperature = <120000>; /* millicelsius */
	hysteresis = <0>; /* millicelsius */
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu1_alert0>;
	cooling-device = <&cpu0 0 2>,
	<&cpu1 0 2>,
	<&cpu2 0 2>,
	<&cpu3 0 2>,
	<&cpu4 0 2>,
	<&cpu5 0 2>,
	<&cpu6 0 2>,
	<&cpu7 0 2>;
	};

	map1 {
	trip = <&cpu1_alert1>;
	cooling-device = <&cpu0 3 6>,
	<&cpu1 3 6>,
	<&cpu2 3 6>,
	<&cpu3 3 6>,
	<&cpu4 3 5>,
	<&cpu5 3 5>,
	<&cpu6 3 5>,
	<&cpu7 3 5>;
	};

	map2 {
	trip = <&cpu1_alert2>;
	cooling-device = <&cpu0 6 11>,
	<&cpu1 6 11>,
	<&cpu2 6 11>,
	<&cpu3 6 11>,
	<&cpu4 5 7>,
	<&cpu5 5 7>,
	<&cpu6 5 7>,
	<&cpu7 5 7>;
	};
	};
	};

	&cpu2_thermal {
	trips {
	cpu2_alert0: cpu-alert-0 {
	temperature = <60000>; /* millicelsius */
	hysteresis = <5000>; /* millicelsius */
	type = "passive";
	};
	cpu2_alert1: cpu-alert-1 {
	temperature = <80000>; /* millicelsius */
	hysteresis = <10000>; /* millicelsius */
	type = "passive";
	};
	cpu2_alert2: cpu-alert-2 {
	temperature = <110000>; /* millicelsius */
	hysteresis = <10000>; /* millicelsius */
	type = "passive";
	};
	cpu2_crit0: cpu-crit-0 {
	temperature = <120000>; /* millicelsius */
	hysteresis = <0>; /* millicelsius */
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu2_alert0>;
	cooling-device = <&cpu0 0 2>,
	<&cpu1 0 2>,
	<&cpu2 0 2>,
	<&cpu3 0 2>,
	<&cpu4 0 2>,
	<&cpu5 0 2>,
	<&cpu6 0 2>,
	<&cpu7 0 2>;
	};

	map1 {
	trip = <&cpu2_alert1>;
	cooling-device = <&cpu0 3 6>,
	<&cpu1 3 6>,
	<&cpu2 3 6>,
	<&cpu3 3 6>,
	<&cpu4 3 5>,
	<&cpu5 3 5>,
	<&cpu6 3 5>,
	<&cpu7 3 5>;
	};

	map2 {
	trip = <&cpu2_alert2>;
	cooling-device = <&cpu0 6 11>,
	<&cpu1 6 11>,
	<&cpu2 6 11>,
	<&cpu3 6 11>,
	<&cpu4 6 7>,
	<&cpu5 6 7>,
	<&cpu6 6 7>,
	<&cpu7 6 7>;
	};
	};
	};

	&cpu3_thermal {
	trips {
	cpu3_alert0: cpu-alert-0 {
	temperature = <60000>; /* millicelsius */
	hysteresis = <5000>; /* millicelsius */
	type = "passive";
	};
	cpu3_alert1: cpu-alert-1 {
	temperature = <80000>; /* millicelsius */
	hysteresis = <10000>; /* millicelsius */
	type = "passive";
	};
	cpu3_alert2: cpu-alert-2 {
	temperature = <110000>; /* millicelsius */
	hysteresis = <10000>; /* millicelsius */
	type = "passive";
	};
	cpu3_crit0: cpu-crit-0 {
	temperature = <120000>; /* millicelsius */
	hysteresis = <0>; /* millicelsius */
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu3_alert0>;
	cooling-device = <&cpu0 0 2>,
	<&cpu1 0 2>,
	<&cpu2 0 2>,
	<&cpu3 0 2>,
	<&cpu4 0 2>,
	<&cpu5 0 2>,
	<&cpu6 0 2>,
	<&cpu7 0 2>;
	};

	map1 {
	trip = <&cpu3_alert1>;
	cooling-device = <&cpu0 3 6>,
	<&cpu1 3 6>,
	<&cpu2 3 6>,
	<&cpu3 3 6>,
	<&cpu4 3 5>,
	<&cpu5 3 5>,
	<&cpu6 3 5>,
	<&cpu7 3 5>;
	};

	map2 {
	trip = <&cpu3_alert2>;
	cooling-device = <&cpu0 6 11>,
	<&cpu1 6 11>,
	<&cpu2 6 11>,
	<&cpu3 6 11>,
	<&cpu4 5 7>,
	<&cpu5 5 7>,
	<&cpu6 5 7>,
	<&cpu7 5 7>;
	};
	};
	};

	&hdmi {
	hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
	vdd_osc-supply = <&ldo7_reg>;
	vdd_pll-supply = <&ldo6_reg>;
	vdd-supply = <&ldo6_reg>;
	ddc = <&i2c_2>;
	status = "okay";
	};

	&hsi2c_4 {
	status = "okay";

	s2mps11_pmic@66 {
	compatible = "samsung,s2mps11-pmic";
	reg = <0x66>;

	interrupt-parent = <&gpx3>;
	interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
	pinctrl-names = "default";
	pinctrl-0 = <&s2mps11_irq>;

	s2mps11_osc: clocks {
	compatible = "samsung,s2mps11-clk";
	#clock-cells = <1>;
	clock-output-names = "s2mps11_ap",
	"s2mps11_cp", "s2mps11_bt";
	};

	regulators {
	ldo1_reg: LDO1 {
	regulator-name = "PVDD_ALIVE_1V0";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	ldo2_reg: LDO2 {
	regulator-name = "PVDD_APIO_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	ldo3_reg: LDO3 {
	regulator-name = "PVDD_APIO_MMCON_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	/*
	* Must be always on, even though there is
	* a consumer (mmc_0). Otherwise the board
	* does not reboot with vendor U-Boot
	* (Linaro for Arndale Octa, v2012.07).
	*/
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo4_reg: LDO4 {
	regulator-name = "PVDD_ADC_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo5_reg: LDO5 {
	regulator-name = "PVDD_PLL_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	ldo6_reg: LDO6 {
	regulator-name = "PVDD_ANAIP_1V0";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	};

	ldo7_reg: LDO7 {
	regulator-name = "PVDD_ANAIP_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo8_reg: LDO8 {
	regulator-name = "PVDD_ABB_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	ldo9_reg: LDO9 {
	regulator-name = "PVDD_USB_3V3";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;
	};

	ldo10_reg: LDO10 {
	regulator-name = "PVDD_PRE_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	ldo11_reg: LDO11 {
	regulator-name = "PVDD_USB_1V0";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	ldo12_reg: LDO12 {
	regulator-name = "PVDD_HSIC_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo13_reg: LDO13 {
	regulator-name = "PVDD_APIO_MMCOFF_2V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2800000>;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo14_reg: LDO14 {
	/* Unused */
	regulator-name = "PVDD_LDO14";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo15_reg: LDO15 {
	regulator-name = "PVDD_PERI_2V8";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	ldo16_reg: LDO16 {
	regulator-name = "PVDD_PERI_3V3";
	regulator-min-microvolt = <2200000>;
	regulator-max-microvolt = <2200000>;

	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	ldo17_reg: LDO17 {
	/* Unused */
	regulator-name = "PVDD_LDO17";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo18_reg: LDO18 {
	regulator-name = "PVDD_EMMC_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	/*
	* Must stay in "off" mode during shutdown for
	* proper eMMC reset. The "off" mode is in
	* fact controlled by LDO18EN. The eMMC does
	* not have reset pin connected so the reset
	* will be triggered by falling edge of
	* LDO18EN.
	*/

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo19_reg: LDO19 {
	regulator-name = "PVDD_TFLASH_2V8";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo20_reg: LDO20 {
	regulator-name = "PVDD_BTWIFI_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo21_reg: LDO21 {
	regulator-name = "PVDD_CAM1IO_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo22_reg: LDO22 {
	/* Unused */
	regulator-name = "PVDD_LDO22";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <2375000>;
	};

	ldo23_reg: LDO23 {
	regulator-name = "PVDD_MIFS_1V1";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;

	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	ldo24_reg: LDO24 {
	regulator-name = "PVDD_CAM1_AVDD_2V8";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;

	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	ldo25_reg: LDO25 {
	/* Unused */
	regulator-name = "PVDD_LDO25";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo26_reg: LDO26 {
	regulator-name = "PVDD_CAM0_AF_2V8";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	};

	ldo27_reg: LDO27 {
	regulator-name = "PVDD_G3DS_1V0";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1100000>;
	+ regulator-always-on;

	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	ldo28_reg: LDO28 {
	regulator-name = "PVDD_TSP_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	ldo29_reg: LDO29 {
	regulator-name = "PVDD_AUDIO_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo30_reg: LDO30 {
	/* Unused */
	regulator-name = "PVDD_LDO30";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo31_reg: LDO31 {
	regulator-name = "PVDD_PERI_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo32_reg: LDO32 {
	regulator-name = "PVDD_LCD_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo33_reg: LDO33 {
	regulator-name = "PVDD_CAM0IO_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo34_reg: LDO34 {
	/* Unused */
	regulator-name = "PVDD_LDO34";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo35_reg: LDO35 {
	regulator-name = "PVDD_CAM0_DVDD_1V2";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	ldo36_reg: LDO36 {
	/* Unused */
	regulator-name = "PVDD_LDO36";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo37_reg: LDO37 {
	/* Unused */
	regulator-name = "PVDD_LDO37";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo38_reg: LDO38 {
	regulator-name = "PVDD_CAM0_AVDD_2V8";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	buck1_reg: BUCK1 {
	regulator-name = "PVDD_MIF_1V1";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1300000>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	buck2_reg: BUCK2 {
	regulator-name = "vdd_arm";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	buck3_reg: BUCK3 {
	regulator-name = "PVDD_INT_1V0";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1400000>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	buck4_reg: BUCK4 {
	regulator-name = "PVDD_G3D_1V0";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1400000>;
	+ regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	buck5_reg: BUCK5 {
	regulator-name = "PVDD_LPDDR3_1V2";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1400000>;
	regulator-always-on;
	};

	buck6_reg: BUCK6 {
	regulator-name = "PVDD_KFC_1V0";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	buck7_reg: BUCK7 {
	regulator-name = "VIN_LLDO_1V4";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;
	};

	buck8_reg: BUCK8 {
	regulator-name = "VIN_MLDO_2V0";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2100000>;
	regulator-always-on;
	};

	buck9_reg: BUCK9 {
	regulator-name = "VIN_HLDO_3V5";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3500000>;
	regulator-always-on;
	};

	buck10_reg: BUCK10 {
	regulator-name = "PVDD_EMMCF_2V8";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	/*
	* Must stay in "off" mode during shutdown for
	* proper eMMC reset. The "off" mode is in
	* fact controlled by BUCK10EN. The eMMC does
	* not have reset pin connected so the reset
	* will be triggered by falling edge of
	* BUCK10EN.
	*/

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};
	};
	};
	};

	&i2c_2 {
	status = "okay";
	};

	&mixer {
	status = "okay";
	};

	&mmc_0 {
	status = "okay";
	non-removable;
	card-detect-delay = <200>;
	samsung,dw-mshc-ciu-div = <3>;
	samsung,dw-mshc-sdr-timing = <0 4>;
	samsung,dw-mshc-ddr-timing = <0 2>;
	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
	vmmc-supply = <&ldo18_reg>;
	vqmmc-supply = <&ldo3_reg>;
	bus-width = <8>;
	cap-mmc-highspeed;
	mmc-hs200-1_8v;
	};

	&mmc_2 {
	status = "okay";
	card-detect-delay = <200>;
	samsung,dw-mshc-ciu-div = <3>;
	samsung,dw-mshc-sdr-timing = <0 4>;
	samsung,dw-mshc-ddr-timing = <0 2>;
	pinctrl-names = "default";
	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
	vmmc-supply = <&ldo19_reg>;
	vqmmc-supply = <&ldo13_reg>;
	bus-width = <4>;
	cap-sd-highspeed;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	sd-uhs-ddr50;
	};

	&pinctrl_0 {
	s2mps11_irq: s2mps11-irq {
	samsung,pins = "gpx3-2";
	samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
	samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};
	};

	&rtc {
	status = "okay";
	clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
	clock-names = "rtc", "rtc_src";
	};

	&usbdrd_dwc3_1 {
	dr_mode = "host";
	};
	diff --git a/sys/gnu/dts/arm/exynos5422-cpus.dtsi b/sys/gnu/dts/arm/exynos5422-cpus.dtsi
	index 1b8605cf2407..4b641b9b8179 100644
	--- a/sys/gnu/dts/arm/exynos5422-cpus.dtsi
	+++ b/sys/gnu/dts/arm/exynos5422-cpus.dtsi
	@@ -1,130 +1,138 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Samsung Exynos5422 SoC cpu device tree source
	*
	* Copyright (c) 2015 Samsung Electronics Co., Ltd.
	* http://www.samsung.com
	*
	* This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
	*
	* The Exynos5420, 5422 and 5800 actually share the same CPU configuration
	* but particular boards choose different booting order.
	*
	* Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
	* booting cluster (big or LITTLE) is chosen by IROM code by reading
	* the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
	* from the LITTLE: Cortex-A7.
	*/

	/ {
	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@100 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x100>;
	clocks = <&clock CLK_KFC_CLK>;
	clock-frequency = <1000000000>;
	cci-control-port = <&cci_control0>;
	operating-points-v2 = <&cluster_a7_opp_table>;
	#cooling-cells = <2>; /* min followed by max */
	capacity-dmips-mhz = <539>;
	+ dynamic-power-coefficient = <90>;
	};

	cpu1: cpu@101 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x101>;
	clocks = <&clock CLK_KFC_CLK>;
	clock-frequency = <1000000000>;
	cci-control-port = <&cci_control0>;
	operating-points-v2 = <&cluster_a7_opp_table>;
	#cooling-cells = <2>; /* min followed by max */
	capacity-dmips-mhz = <539>;
	+ dynamic-power-coefficient = <90>;
	};

	cpu2: cpu@102 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x102>;
	clocks = <&clock CLK_KFC_CLK>;
	clock-frequency = <1000000000>;
	cci-control-port = <&cci_control0>;
	operating-points-v2 = <&cluster_a7_opp_table>;
	#cooling-cells = <2>; /* min followed by max */
	capacity-dmips-mhz = <539>;
	+ dynamic-power-coefficient = <90>;
	};

	cpu3: cpu@103 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x103>;
	clocks = <&clock CLK_KFC_CLK>;
	clock-frequency = <1000000000>;
	cci-control-port = <&cci_control0>;
	operating-points-v2 = <&cluster_a7_opp_table>;
	#cooling-cells = <2>; /* min followed by max */
	capacity-dmips-mhz = <539>;
	+ dynamic-power-coefficient = <90>;
	};

	cpu4: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0x0>;
	clocks = <&clock CLK_ARM_CLK>;
	clock-frequency = <1800000000>;
	cci-control-port = <&cci_control1>;
	operating-points-v2 = <&cluster_a15_opp_table>;
	#cooling-cells = <2>; /* min followed by max */
	capacity-dmips-mhz = <1024>;
	+ dynamic-power-coefficient = <310>;
	};

	cpu5: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0x1>;
	clocks = <&clock CLK_ARM_CLK>;
	clock-frequency = <1800000000>;
	cci-control-port = <&cci_control1>;
	operating-points-v2 = <&cluster_a15_opp_table>;
	#cooling-cells = <2>; /* min followed by max */
	capacity-dmips-mhz = <1024>;
	+ dynamic-power-coefficient = <310>;
	};

	cpu6: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0x2>;
	clocks = <&clock CLK_ARM_CLK>;
	clock-frequency = <1800000000>;
	cci-control-port = <&cci_control1>;
	operating-points-v2 = <&cluster_a15_opp_table>;
	#cooling-cells = <2>; /* min followed by max */
	capacity-dmips-mhz = <1024>;
	+ dynamic-power-coefficient = <310>;
	};

	cpu7: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0x3>;
	clocks = <&clock CLK_ARM_CLK>;
	clock-frequency = <1800000000>;
	cci-control-port = <&cci_control1>;
	operating-points-v2 = <&cluster_a15_opp_table>;
	#cooling-cells = <2>; /* min followed by max */
	capacity-dmips-mhz = <1024>;
	+ dynamic-power-coefficient = <310>;
	};
	};
	};

	&arm_a7_pmu {
	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	status = "okay";
	};

	&arm_a15_pmu {
	interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/exynos5422-odroid-core.dtsi b/sys/gnu/dts/arm/exynos5422-odroid-core.dtsi
	index 5cf1aed20490..ab27ff8bc3dc 100644
	--- a/sys/gnu/dts/arm/exynos5422-odroid-core.dtsi
	+++ b/sys/gnu/dts/arm/exynos5422-odroid-core.dtsi
	@@ -1,1075 +1,1076 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
	*
	* Copyright (c) 2017 Marek Szyprowski
	* Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
	* http://www.samsung.com
	*/

	#include <dt-bindings/clock/samsung,s2mps11.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/gpio/gpio.h>
	#include "exynos5800.dtsi"
	#include "exynos5422-cpus.dtsi"

	/ {
	memory@40000000 {
	device_type = "memory";
	reg = <0x40000000 0x7EA00000>;
	};

	chosen {
	stdout-path = "serial2:115200n8";
	};

	firmware@2073000 {
	compatible = "samsung,secure-firmware";
	reg = <0x02073000 0x1000>;
	};

	fixed-rate-clocks {
	oscclk {
	compatible = "samsung,exynos5420-oscclk";
	clock-frequency = <24000000>;
	};
	};

	bus_wcore_opp_table: opp_table2 {
	compatible = "operating-points-v2";

	/* derived from 532MHz MPLL */
	opp00 {
	opp-hz = /bits/ 64 <88700000>;
	opp-microvolt = <925000 925000 1400000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <133000000>;
	opp-microvolt = <950000 950000 1400000>;
	};
	opp02 {
	opp-hz = /bits/ 64 <177400000>;
	opp-microvolt = <950000 950000 1400000>;
	};
	opp03 {
	opp-hz = /bits/ 64 <266000000>;
	opp-microvolt = <950000 950000 1400000>;
	};
	opp04 {
	opp-hz = /bits/ 64 <532000000>;
	opp-microvolt = <1000000 1000000 1400000>;
	};
	};

	bus_noc_opp_table: opp_table3 {
	compatible = "operating-points-v2";

	/* derived from 666MHz CPLL */
	opp00 {
	opp-hz = /bits/ 64 <66600000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <74000000>;
	};
	opp02 {
	opp-hz = /bits/ 64 <83250000>;
	};
	opp03 {
	opp-hz = /bits/ 64 <111000000>;
	};
	};

	bus_fsys_apb_opp_table: opp_table4 {
	compatible = "operating-points-v2";

	/* derived from 666MHz CPLL */
	opp00 {
	opp-hz = /bits/ 64 <111000000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <222000000>;
	};
	};

	bus_fsys2_opp_table: opp_table5 {
	compatible = "operating-points-v2";

	/* derived from 600MHz DPLL */
	opp00 {
	opp-hz = /bits/ 64 <75000000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <120000000>;
	};
	opp02 {
	opp-hz = /bits/ 64 <200000000>;
	};
	};

	bus_mfc_opp_table: opp_table6 {
	compatible = "operating-points-v2";

	/* derived from 666MHz CPLL */
	opp00 {
	opp-hz = /bits/ 64 <83250000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <111000000>;
	};
	opp02 {
	opp-hz = /bits/ 64 <166500000>;
	};
	opp03 {
	opp-hz = /bits/ 64 <222000000>;
	};
	opp04 {
	opp-hz = /bits/ 64 <333000000>;
	};
	};

	bus_gen_opp_table: opp_table7 {
	compatible = "operating-points-v2";

	/* derived from 532MHz MPLL */
	opp00 {
	opp-hz = /bits/ 64 <88700000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <133000000>;
	};
	opp02 {
	opp-hz = /bits/ 64 <178000000>;
	};
	opp03 {
	opp-hz = /bits/ 64 <266000000>;
	};
	};

	bus_peri_opp_table: opp_table8 {
	compatible = "operating-points-v2";

	/* derived from 666MHz CPLL */
	opp00 {
	opp-hz = /bits/ 64 <66600000>;
	};
	};

	bus_g2d_opp_table: opp_table9 {
	compatible = "operating-points-v2";

	/* derived from 666MHz CPLL */
	opp00 {
	opp-hz = /bits/ 64 <83250000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <111000000>;
	};
	opp02 {
	opp-hz = /bits/ 64 <166500000>;
	};
	opp03 {
	opp-hz = /bits/ 64 <222000000>;
	};
	opp04 {
	opp-hz = /bits/ 64 <333000000>;
	};
	};

	bus_g2d_acp_opp_table: opp_table10 {
	compatible = "operating-points-v2";

	/* derived from 532MHz MPLL */
	opp00 {
	opp-hz = /bits/ 64 <66500000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <133000000>;
	};
	opp02 {
	opp-hz = /bits/ 64 <178000000>;
	};
	opp03 {
	opp-hz = /bits/ 64 <266000000>;
	};
	};

	bus_jpeg_opp_table: opp_table11 {
	compatible = "operating-points-v2";

	/* derived from 600MHz DPLL */
	opp00 {
	opp-hz = /bits/ 64 <75000000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <150000000>;
	};
	opp02 {
	opp-hz = /bits/ 64 <200000000>;
	};
	opp03 {
	opp-hz = /bits/ 64 <300000000>;
	};
	};

	bus_jpeg_apb_opp_table: opp_table12 {
	compatible = "operating-points-v2";

	/* derived from 666MHz CPLL */
	opp00 {
	opp-hz = /bits/ 64 <83250000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <111000000>;
	};
	opp02 {
	opp-hz = /bits/ 64 <133000000>;
	};
	opp03 {
	opp-hz = /bits/ 64 <166500000>;
	};
	};

	bus_disp1_fimd_opp_table: opp_table13 {
	compatible = "operating-points-v2";

	/* derived from 600MHz DPLL */
	opp00 {
	opp-hz = /bits/ 64 <120000000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <200000000>;
	};
	};

	bus_disp1_opp_table: opp_table14 {
	compatible = "operating-points-v2";

	/* derived from 600MHz DPLL */
	opp00 {
	opp-hz = /bits/ 64 <120000000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <200000000>;
	};
	opp02 {
	opp-hz = /bits/ 64 <300000000>;
	};
	};

	bus_gscl_opp_table: opp_table15 {
	compatible = "operating-points-v2";

	/* derived from 600MHz DPLL */
	opp00 {
	opp-hz = /bits/ 64 <150000000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <200000000>;
	};
	opp02 {
	opp-hz = /bits/ 64 <300000000>;
	};
	};

	bus_mscl_opp_table: opp_table16 {
	compatible = "operating-points-v2";

	/* derived from 666MHz CPLL */
	opp00 {
	opp-hz = /bits/ 64 <84000000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <167000000>;
	};
	opp02 {
	opp-hz = /bits/ 64 <222000000>;
	};
	opp03 {
	opp-hz = /bits/ 64 <333000000>;
	};
	opp04 {
	opp-hz = /bits/ 64 <666000000>;
	};
	};

	dmc_opp_table: opp_table17 {
	compatible = "operating-points-v2";

	opp00 {
	opp-hz = /bits/ 64 <165000000>;
	opp-microvolt = <875000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <206000000>;
	opp-microvolt = <875000>;
	};
	opp02 {
	opp-hz = /bits/ 64 <275000000>;
	opp-microvolt = <875000>;
	};
	opp03 {
	opp-hz = /bits/ 64 <413000000>;
	opp-microvolt = <887500>;
	};
	opp04 {
	opp-hz = /bits/ 64 <543000000>;
	opp-microvolt = <937500>;
	};
	opp05 {
	opp-hz = /bits/ 64 <633000000>;
	opp-microvolt = <1012500>;
	};
	opp06 {
	opp-hz = /bits/ 64 <728000000>;
	opp-microvolt = <1037500>;
	};
	opp07 {
	opp-hz = /bits/ 64 <825000000>;
	opp-microvolt = <1050000>;
	};
	};

	samsung_K3QF2F20DB: lpddr3 {
	compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
	density = <16384>;
	io-width = <32>;
	#address-cells = <1>;
	#size-cells = <0>;

	tRFC-min-tck = <17>;
	tRRD-min-tck = <2>;
	tRPab-min-tck = <2>;
	tRPpb-min-tck = <2>;
	tRCD-min-tck = <3>;
	tRC-min-tck = <6>;
	tRAS-min-tck = <5>;
	tWTR-min-tck = <2>;
	tWR-min-tck = <7>;
	tRTP-min-tck = <2>;
	tW2W-C2C-min-tck = <0>;
	tR2R-C2C-min-tck = <0>;
	tWL-min-tck = <8>;
	tDQSCK-min-tck = <5>;
	tRL-min-tck = <14>;
	tFAW-min-tck = <5>;
	tXSR-min-tck = <12>;
	tXP-min-tck = <2>;
	tCKE-min-tck = <2>;
	tCKESR-min-tck = <2>;
	tMRD-min-tck = <5>;

	timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
	compatible = "jedec,lpddr3-timings";
	/* workaround: 'reg' shows max-freq */
	reg = <800000000>;
	min-freq = <100000000>;
	tRFC = <65000>;
	tRRD = <6000>;
	tRPab = <12000>;
	tRPpb = <12000>;
	tRCD = <10000>;
	tRC = <33750>;
	tRAS = <23000>;
	tWTR = <3750>;
	tWR = <7500>;
	tRTP = <3750>;
	tW2W-C2C = <0>;
	tR2R-C2C = <0>;
	tFAW = <25000>;
	tXSR = <70000>;
	tXP = <3750>;
	tCKE = <3750>;
	tCKESR = <3750>;
	tMRD = <7000>;
	};
	};
	};

	&adc {
	vdd-supply = <&ldo4_reg>;
	status = "okay";
	};

	&bus_wcore {
	operating-points-v2 = <&bus_wcore_opp_table>;
	devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
	<&nocp_mem1_0>, <&nocp_mem1_1>;
	vdd-supply = <&buck3_reg>;
	exynos,saturation-ratio = <100>;
	status = "okay";
	};

	&bus_noc {
	operating-points-v2 = <&bus_noc_opp_table>;
	devfreq = <&bus_wcore>;
	status = "okay";
	};

	&bus_fsys_apb {
	operating-points-v2 = <&bus_fsys_apb_opp_table>;
	devfreq = <&bus_wcore>;
	status = "okay";
	};

	&bus_fsys {
	operating-points-v2 = <&bus_fsys2_opp_table>;
	devfreq = <&bus_wcore>;
	status = "okay";
	};

	&bus_fsys2 {
	operating-points-v2 = <&bus_fsys2_opp_table>;
	devfreq = <&bus_wcore>;
	status = "okay";
	};

	&bus_mfc {
	operating-points-v2 = <&bus_mfc_opp_table>;
	devfreq = <&bus_wcore>;
	status = "okay";
	};

	&bus_gen {
	operating-points-v2 = <&bus_gen_opp_table>;
	devfreq = <&bus_wcore>;
	status = "okay";
	};

	&bus_peri {
	operating-points-v2 = <&bus_peri_opp_table>;
	devfreq = <&bus_wcore>;
	status = "okay";
	};

	&bus_g2d {
	operating-points-v2 = <&bus_g2d_opp_table>;
	devfreq = <&bus_wcore>;
	status = "okay";
	};

	&bus_g2d_acp {
	operating-points-v2 = <&bus_g2d_acp_opp_table>;
	devfreq = <&bus_wcore>;
	status = "okay";
	};

	&bus_jpeg {
	operating-points-v2 = <&bus_jpeg_opp_table>;
	devfreq = <&bus_wcore>;
	status = "okay";
	};

	&bus_jpeg_apb {
	operating-points-v2 = <&bus_jpeg_apb_opp_table>;
	devfreq = <&bus_wcore>;
	status = "okay";
	};

	&bus_disp1_fimd {
	operating-points-v2 = <&bus_disp1_fimd_opp_table>;
	devfreq = <&bus_wcore>;
	status = "okay";
	};

	&bus_disp1 {
	operating-points-v2 = <&bus_disp1_opp_table>;
	devfreq = <&bus_wcore>;
	status = "okay";
	};

	&bus_gscl_scaler {
	operating-points-v2 = <&bus_gscl_opp_table>;
	devfreq = <&bus_wcore>;
	status = "okay";
	};

	&bus_mscl {
	operating-points-v2 = <&bus_mscl_opp_table>;
	devfreq = <&bus_wcore>;
	status = "okay";
	};

	&cpu0 {
	cpu-supply = <&buck6_reg>;
	};

	&cpu4 {
	cpu-supply = <&buck2_reg>;
	};

	&dmc {
	devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
	<&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
	device-handle = <&samsung_K3QF2F20DB>;
	operating-points-v2 = <&dmc_opp_table>;
	vdd-supply = <&buck1_reg>;
	status = "okay";
	};

	&hsi2c_4 {
	status = "okay";

	s2mps11_pmic@66 {
	compatible = "samsung,s2mps11-pmic";
	reg = <0x66>;
	samsung,s2mps11-acokb-ground;

	interrupt-parent = <&gpx0>;
	interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
	pinctrl-names = "default";
	pinctrl-0 = <&s2mps11_irq>;

	s2mps11_osc: clocks {
	compatible = "samsung,s2mps11-clk";
	#clock-cells = <1>;
	clock-output-names = "s2mps11_ap",
	"s2mps11_cp", "s2mps11_bt";
	};

	regulators {
	ldo1_reg: LDO1 {
	regulator-name = "vdd_ldo1";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	ldo2_reg: LDO2 {
	regulator-name = "vdd_ldo2";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	ldo3_reg: LDO3 {
	regulator-name = "vddq_mmc0";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo4_reg: LDO4 {
	regulator-name = "vdd_adc";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo5_reg: LDO5 {
	regulator-name = "vdd_ldo5";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo6_reg: LDO6 {
	regulator-name = "vdd_ldo6";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo7_reg: LDO7 {
	regulator-name = "vdd_ldo7";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo8_reg: LDO8 {
	regulator-name = "vdd_ldo8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo9_reg: LDO9 {
	regulator-name = "vdd_ldo9";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo10_reg: LDO10 {
	regulator-name = "vdd_ldo10";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo11_reg: LDO11 {
	regulator-name = "vdd_ldo11";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo12_reg: LDO12 {
	/* Unused */
	regulator-name = "vdd_ldo12";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <2375000>;
	};

	ldo13_reg: LDO13 {
	regulator-name = "vddq_mmc2";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2800000>;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo14_reg: LDO14 {
	/* Unused */
	regulator-name = "vdd_ldo14";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo15_reg: LDO15 {
	regulator-name = "vdd_ldo15";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo16_reg: LDO16 {
	/* Unused */
	regulator-name = "vdd_ldo16";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo17_reg: LDO17 {
	regulator-name = "vdd_ldo17";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo18_reg: LDO18 {
	regulator-name = "vdd_emmc_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo19_reg: LDO19 {
	regulator-name = "vdd_sd";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo20_reg: LDO20 {
	/* Unused */
	regulator-name = "vdd_ldo20";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo21_reg: LDO21 {
	/* Unused */
	regulator-name = "vdd_ldo21";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo22_reg: LDO22 {
	/* Unused */
	regulator-name = "vdd_ldo22";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <2375000>;
	};

	ldo23_reg: LDO23 {
	regulator-name = "vdd_mifs";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo24_reg: LDO24 {
	/* Unused */
	regulator-name = "vdd_ldo24";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo25_reg: LDO25 {
	/* Unused */
	regulator-name = "vdd_ldo25";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo26_reg: LDO26 {
	/* Used on XU3, XU3-Lite and XU4 */
	regulator-name = "vdd_ldo26";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo27_reg: LDO27 {
	regulator-name = "vdd_g3ds";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo28_reg: LDO28 {
	/* Used on XU3 */
	regulator-name = "vdd_ldo28";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	ldo29_reg: LDO29 {
	/* Unused */
	regulator-name = "vdd_ldo29";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo30_reg: LDO30 {
	/* Unused */
	regulator-name = "vdd_ldo30";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo31_reg: LDO31 {
	/* Unused */
	regulator-name = "vdd_ldo31";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo32_reg: LDO32 {
	/* Unused */
	regulator-name = "vdd_ldo32";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo33_reg: LDO33 {
	/* Unused */
	regulator-name = "vdd_ldo33";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo34_reg: LDO34 {
	/* Unused */
	regulator-name = "vdd_ldo34";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo35_reg: LDO35 {
	/* Unused */
	regulator-name = "vdd_ldo35";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <2375000>;
	};

	ldo36_reg: LDO36 {
	/* Unused */
	regulator-name = "vdd_ldo36";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo37_reg: LDO37 {
	/* Unused */
	regulator-name = "vdd_ldo37";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	ldo38_reg: LDO38 {
	/* Unused */
	regulator-name = "vdd_ldo38";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	};

	buck1_reg: BUCK1 {
	regulator-name = "vdd_mif";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1300000>;
	regulator-always-on;
	regulator-boot-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	buck2_reg: BUCK2 {
	regulator-name = "vdd_arm";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-coupled-with = <&buck3_reg>;
	regulator-coupled-max-spread = <300000>;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	buck3_reg: BUCK3 {
	regulator-name = "vdd_int";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1400000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-coupled-with = <&buck2_reg>;
	regulator-coupled-max-spread = <300000>;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	buck4_reg: BUCK4 {
	regulator-name = "vdd_g3d";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1400000>;
	regulator-boot-on;
	+ regulator-always-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	buck5_reg: BUCK5 {
	regulator-name = "vdd_mem";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1400000>;
	regulator-always-on;
	regulator-boot-on;
	};

	buck6_reg: BUCK6 {
	regulator-name = "vdd_kfc";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;
	regulator-boot-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	buck7_reg: BUCK7 {
	regulator-name = "vdd_1.35v_ldo";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;
	regulator-boot-on;
	};

	buck8_reg: BUCK8 {
	regulator-name = "vdd_2.0v_ldo";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2100000>;
	regulator-always-on;
	regulator-boot-on;
	};

	buck9_reg: BUCK9 {
	regulator-name = "vdd_2.8v_ldo";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3750000>;
	regulator-always-on;
	regulator-boot-on;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	buck10_reg: BUCK10 {
	regulator-name = "vdd_vmem";
	regulator-min-microvolt = <2850000>;
	regulator-max-microvolt = <2850000>;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};
	};
	};
	};

	&mmc_2 {
	status = "okay";
	card-detect-delay = <200>;
	samsung,dw-mshc-ciu-div = <3>;
	samsung,dw-mshc-sdr-timing = <0 4>;
	samsung,dw-mshc-ddr-timing = <0 2>;
	pinctrl-names = "default";
	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
	bus-width = <4>;
	cap-sd-highspeed;
	max-frequency = <200000000>;
	vmmc-supply = <&ldo19_reg>;
	vqmmc-supply = <&ldo13_reg>;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	sd-uhs-ddr50;
	};

	&nocp_mem0_0 {
	status = "okay";
	};

	&nocp_mem0_1 {
	status = "okay";
	};

	&nocp_mem1_0 {
	status = "okay";
	};

	&nocp_mem1_1 {
	status = "okay";
	};

	&pinctrl_0 {
	s2mps11_irq: s2mps11-irq {
	samsung,pins = "gpx0-4";
	samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
	samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};
	};

	&ppmu_dmc0_0 {
	status = "okay";
	};

	&ppmu_dmc0_1 {
	status = "okay";
	};

	&ppmu_dmc1_0 {
	status = "okay";
	};

	&ppmu_dmc1_1 {
	status = "okay";
	};

	&tmu_cpu0 {
	vtmu-supply = <&ldo7_reg>;
	};

	&tmu_cpu1 {
	vtmu-supply = <&ldo7_reg>;
	};

	&tmu_cpu2 {
	vtmu-supply = <&ldo7_reg>;
	};

	&tmu_cpu3 {
	vtmu-supply = <&ldo7_reg>;
	};

	&tmu_gpu {
	vtmu-supply = <&ldo7_reg>;
	};

	&gpu {
	mali-supply = <&buck4_reg>;
	status = "okay";
	};

	&rtc {
	status = "okay";
	clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
	clock-names = "rtc", "rtc_src";
	};

	&usbdrd_dwc3_0 {
	dr_mode = "host";
	};

	/* usbdrd_dwc3_1 mode customized in each board */

	&usbdrd3_0 {
	vdd33-supply = <&ldo9_reg>;
	vdd10-supply = <&ldo11_reg>;
	};

	&usbdrd3_1 {
	vdd33-supply = <&ldo9_reg>;
	vdd10-supply = <&ldo11_reg>;
	};
	diff --git a/sys/gnu/dts/arm/exynos5422-odroidhc1.dts b/sys/gnu/dts/arm/exynos5422-odroidhc1.dts
	index f163206265bb..812659260278 100644
	--- a/sys/gnu/dts/arm/exynos5422-odroidhc1.dts
	+++ b/sys/gnu/dts/arm/exynos5422-odroidhc1.dts
	@@ -1,234 +1,264 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Hardkernel Odroid HC1 board device tree source
	*
	* Copyright (c) 2017 Marek Szyprowski
	* Copyright (c) 2017 Samsung Electronics Co., Ltd.
	* http://www.samsung.com
	*/

	/dts-v1/;
	#include "exynos5422-odroid-core.dtsi"

	/ {
	model = "Hardkernel Odroid HC1";
	compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \
	"samsung,exynos5";

	pwmleds {
	compatible = "pwm-leds";

	blueled {
	label = "blue:heartbeat";
	pwms = <&pwm 2 2000000 0>;
	pwm-names = "pwm2";
	max_brightness = <255>;
	linux,default-trigger = "heartbeat";
	};
	};

	thermal-zones {
	cpu0_thermal: cpu0-thermal {
	thermal-sensors = <&tmu_cpu0 0>;
	trips {
	cpu0_alert0: cpu-alert-0 {
	temperature = <70000>; /* millicelsius */
	hysteresis = <10000>; /* millicelsius */
	type = "active";
	};
	cpu0_alert1: cpu-alert-1 {
	temperature = <85000>; /* millicelsius */
	hysteresis = <10000>; /* millicelsius */
	type = "active";
	};
	cpu0_crit0: cpu-crit-0 {
	temperature = <120000>; /* millicelsius */
	hysteresis = <0>; /* millicelsius */
	type = "critical";
	};
	};

	cooling-maps {
	/*
	* When reaching cpu0_alert0, reduce CPU
	* by 2 steps. On Exynos5422/5800 that would
	* be: 1600 MHz and 1100 MHz.
	*/
	map0 {
	trip = <&cpu0_alert0>;
	cooling-device = <&cpu0 0 2>,
	<&cpu1 0 2>,
	<&cpu2 0 2>,
	<&cpu3 0 2>,
	<&cpu4 0 2>,
	<&cpu5 0 2>,
	<&cpu6 0 2>,
	<&cpu7 0 2>;
	};
	/*
	* When reaching cpu0_alert1, reduce CPU
	* further, down to 600 MHz (12 steps for big,
	* 7 steps for LITTLE).
	*/
	map1 {
	trip = <&cpu0_alert1>;
	cooling-device = <&cpu0 3 8>,
	<&cpu1 3 8>,
	<&cpu2 3 8>,
	<&cpu3 3 8>,
	<&cpu4 3 14>,
	<&cpu5 3 14>,
	<&cpu6 3 14>,
	<&cpu7 3 14>;
	};
	};
	};
	cpu1_thermal: cpu1-thermal {
	thermal-sensors = <&tmu_cpu1 0>;
	trips {
	cpu1_alert0: cpu-alert-0 {
	temperature = <70000>;
	hysteresis = <10000>;
	type = "active";
	};
	cpu1_alert1: cpu-alert-1 {
	temperature = <85000>;
	hysteresis = <10000>;
	type = "active";
	};
	cpu1_crit0: cpu-crit-0 {
	temperature = <120000>;
	hysteresis = <0>;
	type = "critical";
	};
	};
	cooling-maps {
	map0 {
	trip = <&cpu1_alert0>;
	cooling-device = <&cpu0 0 2>,
	<&cpu1 0 2>,
	<&cpu2 0 2>,
	<&cpu3 0 2>,
	<&cpu4 0 2>,
	<&cpu5 0 2>,
	<&cpu6 0 2>,
	<&cpu7 0 2>;
	};
	map1 {
	trip = <&cpu1_alert1>;
	cooling-device = <&cpu0 3 8>,
	<&cpu1 3 8>,
	<&cpu2 3 8>,
	<&cpu3 3 8>,
	<&cpu4 3 14>,
	<&cpu5 3 14>,
	<&cpu6 3 14>,
	<&cpu7 3 14>;
	};
	};
	};
	cpu2_thermal: cpu2-thermal {
	thermal-sensors = <&tmu_cpu2 0>;
	trips {
	cpu2_alert0: cpu-alert-0 {
	temperature = <70000>;
	hysteresis = <10000>;
	type = "active";
	};
	cpu2_alert1: cpu-alert-1 {
	temperature = <85000>;
	hysteresis = <10000>;
	type = "active";
	};
	cpu2_crit0: cpu-crit-0 {
	temperature = <120000>;
	hysteresis = <0>;
	type = "critical";
	};
	};
	cooling-maps {
	map0 {
	trip = <&cpu2_alert0>;
	cooling-device = <&cpu0 0 2>,
	<&cpu1 0 2>,
	<&cpu2 0 2>,
	<&cpu3 0 2>,
	<&cpu4 0 2>,
	<&cpu5 0 2>,
	<&cpu6 0 2>,
	<&cpu7 0 2>;
	};
	map1 {
	trip = <&cpu2_alert1>;
	cooling-device = <&cpu0 3 8>,
	<&cpu1 3 8>,
	<&cpu2 3 8>,
	<&cpu3 3 8>,
	<&cpu4 3 14>,
	<&cpu5 3 14>,
	<&cpu6 3 14>,
	<&cpu7 3 14>;
	};
	};
	};
	cpu3_thermal: cpu3-thermal {
	thermal-sensors = <&tmu_cpu3 0>;
	trips {
	cpu3_alert0: cpu-alert-0 {
	temperature = <70000>;
	hysteresis = <10000>;
	type = "active";
	};
	cpu3_alert1: cpu-alert-1 {
	temperature = <85000>;
	hysteresis = <10000>;
	type = "active";
	};
	cpu3_crit0: cpu-crit-0 {
	temperature = <120000>;
	hysteresis = <0>;
	type = "critical";
	};
	};
	cooling-maps {
	map0 {
	trip = <&cpu3_alert0>;
	cooling-device = <&cpu0 0 2>,
	<&cpu1 0 2>,
	<&cpu2 0 2>,
	<&cpu3 0 2>,
	<&cpu4 0 2>,
	<&cpu5 0 2>,
	<&cpu6 0 2>,
	<&cpu7 0 2>;
	};
	map1 {
	trip = <&cpu3_alert1>;
	cooling-device = <&cpu0 3 8>,
	<&cpu1 3 8>,
	<&cpu2 3 8>,
	<&cpu3 3 8>,
	<&cpu4 3 14>,
	<&cpu5 3 14>,
	<&cpu6 3 14>,
	<&cpu7 3 14>;
	};
	};
	};
	+ gpu_thermal: gpu-thermal {
	+ thermal-sensors = <&tmu_gpu 0>;
	+ trips {
	+ gpu_alert0: gpu-alert-0 {
	+ temperature = <70000>;
	+ hysteresis = <10000>;
	+ type = "active";
	+ };
	+ gpu_alert1: gpu-alert-1 {
	+ temperature = <85000>;
	+ hysteresis = <10000>;
	+ type = "active";
	+ };
	+ gpu_crit0: gpu-crit-0 {
	+ temperature = <120000>;
	+ hysteresis = <0>;
	+ type = "critical";
	+ };
	+ };
	+ cooling-maps {
	+ map0 {
	+ trip = <&gpu_alert0>;
	+ cooling-device = <&gpu 0 2>;
	+ };
	+ map1 {
	+ trip = <&gpu_alert1>;
	+ cooling-device = <&gpu 3 6>;
	+ };
	+ };
	+ };
	};

	};

	&pwm {
	/*
	* PWM 2 -- Blue LED
	*/
	pinctrl-0 = <&pwm2_out>;
	pinctrl-names = "default";
	samsung,pwm-outputs = <2>;
	status = "okay";
	};

	&usbdrd_dwc3_1 {
	dr_mode = "host";
	};
	diff --git a/sys/gnu/dts/arm/exynos5422-odroidxu3-common.dtsi b/sys/gnu/dts/arm/exynos5422-odroidxu3-common.dtsi
	index 1865a708b49f..5da2d81e3be2 100644
	--- a/sys/gnu/dts/arm/exynos5422-odroidxu3-common.dtsi
	+++ b/sys/gnu/dts/arm/exynos5422-odroidxu3-common.dtsi
	@@ -1,446 +1,505 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source
	*
	* Copyright (c) 2013 Samsung Electronics Co., Ltd.
	* http://www.samsung.com
	* Copyright (c) 2014 Collabora Ltd.
	* Copyright (c) 2015 Lukasz Majewski <l.majewski@samsung.com>
	* Anand Moon <linux.amoon@gmail.com>
	*/

	#include <dt-bindings/input/input.h>
	#include "exynos5422-odroid-core.dtsi"

	/ {
	gpio_keys {
	compatible = "gpio-keys";
	pinctrl-names = "default";
	pinctrl-0 = <&power_key>;

	power_key {
	/*
	* The power button (SW2) is connected to the PWRON
	* pin (active high) of the S2MPS11 PMIC, which acts
	* as a 16ms debouce filter and signal inverter with
	* output on ONOB pin (active low). ONOB PMIC pin is
	* then connected to XEINT3 SoC pin.
	*/
	gpios = <&gpx0 3 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_POWER>;
	label = "power key";
	debounce-interval = <0>;
	wakeup-source;
	};
	};

	emmc_pwrseq: pwrseq {
	pinctrl-0 = <&emmc_nrst_pin>;
	pinctrl-names = "default";
	compatible = "mmc-pwrseq-emmc";
	reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>;
	};

	fan0: pwm-fan {
	compatible = "pwm-fan";
	pwms = <&pwm 0 20972 0>;
	#cooling-cells = <2>;
	cooling-levels = <0 130 170 230>;
	};

	thermal-zones {
	cpu0_thermal: cpu0-thermal {
	thermal-sensors = <&tmu_cpu0 0>;
	polling-delay-passive = <250>;
	polling-delay = <0>;
	trips {
	cpu0_alert0: cpu-alert-0 {
	temperature = <50000>; /* millicelsius */
	hysteresis = <5000>; /* millicelsius */
	type = "active";
	};
	cpu0_alert1: cpu-alert-1 {
	temperature = <60000>; /* millicelsius */
	hysteresis = <5000>; /* millicelsius */
	type = "active";
	};
	cpu0_alert2: cpu-alert-2 {
	temperature = <70000>; /* millicelsius */
	hysteresis = <5000>; /* millicelsius */
	type = "active";
	};
	cpu0_crit0: cpu-crit-0 {
	temperature = <120000>; /* millicelsius */
	hysteresis = <0>; /* millicelsius */
	type = "critical";
	};
	/*
	* Exynos542x supports only 4 trip-points
	* so for these polling mode is required.
	* Start polling at temperature level of last
	* interrupt-driven trip: cpu0_alert2
	*/
	cpu0_alert3: cpu-alert-3 {
	temperature = <70000>; /* millicelsius */
	hysteresis = <10000>; /* millicelsius */
	type = "passive";
	};
	cpu0_alert4: cpu-alert-4 {
	temperature = <85000>; /* millicelsius */
	hysteresis = <10000>; /* millicelsius */
	type = "passive";
	};
	};
	cooling-maps {
	map0 {
	trip = <&cpu0_alert0>;
	cooling-device = <&fan0 0 1>;
	};
	map1 {
	trip = <&cpu0_alert1>;
	cooling-device = <&fan0 1 2>;
	};
	map2 {
	trip = <&cpu0_alert2>;
	cooling-device = <&fan0 2 3>;
	};
	/*
	* When reaching cpu0_alert3, reduce CPU
	* by 2 steps. On Exynos5422/5800 that would
	* (usually) be: 1800 MHz and 1200 MHz.
	*/
	map3 {
	trip = <&cpu0_alert3>;
	cooling-device = <&cpu0 0 2>,
	<&cpu1 0 2>,
	<&cpu2 0 2>,
	<&cpu3 0 2>,
	<&cpu4 0 2>,
	<&cpu5 0 2>,
	<&cpu6 0 2>,
	<&cpu7 0 2>;
	};
	/*
	* When reaching cpu0_alert4, reduce CPU
	* further, down to 600 MHz (14 steps for big,
	* 8 steps for LITTLE).
	*/
	cpu0_cooling_map4: map4 {
	trip = <&cpu0_alert4>;
	cooling-device = <&cpu0 3 8>,
	<&cpu1 3 8>,
	<&cpu2 3 8>,
	<&cpu3 3 8>,
	<&cpu4 3 14>,
	<&cpu5 3 14>,
	<&cpu6 3 14>,
	<&cpu7 3 14>;
	};
	};
	};
	cpu1_thermal: cpu1-thermal {
	thermal-sensors = <&tmu_cpu1 0>;
	polling-delay-passive = <250>;
	polling-delay = <0>;
	trips {
	cpu1_alert0: cpu-alert-0 {
	temperature = <50000>;
	hysteresis = <5000>;
	type = "active";
	};
	cpu1_alert1: cpu-alert-1 {
	temperature = <60000>;
	hysteresis = <5000>;
	type = "active";
	};
	cpu1_alert2: cpu-alert-2 {
	temperature = <70000>;
	hysteresis = <5000>;
	type = "active";
	};
	cpu1_crit0: cpu-crit-0 {
	temperature = <120000>;
	hysteresis = <0>;
	type = "critical";
	};
	cpu1_alert3: cpu-alert-3 {
	temperature = <70000>;
	hysteresis = <10000>;
	type = "passive";
	};
	cpu1_alert4: cpu-alert-4 {
	temperature = <85000>;
	hysteresis = <10000>;
	type = "passive";
	};
	};
	cooling-maps {
	map0 {
	trip = <&cpu1_alert0>;
	cooling-device = <&fan0 0 1>;
	};
	map1 {
	trip = <&cpu1_alert1>;
	cooling-device = <&fan0 1 2>;
	};
	map2 {
	trip = <&cpu1_alert2>;
	cooling-device = <&fan0 2 3>;
	};
	map3 {
	trip = <&cpu1_alert3>;
	cooling-device = <&cpu0 0 2>,
	<&cpu1 0 2>,
	<&cpu2 0 2>,
	<&cpu3 0 2>,
	<&cpu4 0 2>,
	<&cpu5 0 2>,
	<&cpu6 0 2>,
	<&cpu7 0 2>;
	};
	cpu1_cooling_map4: map4 {
	trip = <&cpu1_alert4>;
	cooling-device = <&cpu0 3 8>,
	<&cpu1 3 8>,
	<&cpu2 3 8>,
	<&cpu3 3 8>,
	<&cpu4 3 14>,
	<&cpu5 3 14>,
	<&cpu6 3 14>,
	<&cpu7 3 14>;
	};
	};
	};
	cpu2_thermal: cpu2-thermal {
	thermal-sensors = <&tmu_cpu2 0>;
	polling-delay-passive = <250>;
	polling-delay = <0>;
	trips {
	cpu2_alert0: cpu-alert-0 {
	temperature = <50000>;
	hysteresis = <5000>;
	type = "active";
	};
	cpu2_alert1: cpu-alert-1 {
	temperature = <60000>;
	hysteresis = <5000>;
	type = "active";
	};
	cpu2_alert2: cpu-alert-2 {
	temperature = <70000>;
	hysteresis = <5000>;
	type = "active";
	};
	cpu2_crit0: cpu-crit-0 {
	temperature = <120000>;
	hysteresis = <0>;
	type = "critical";
	};
	cpu2_alert3: cpu-alert-3 {
	temperature = <70000>;
	hysteresis = <10000>;
	type = "passive";
	};
	cpu2_alert4: cpu-alert-4 {
	temperature = <85000>;
	hysteresis = <10000>;
	type = "passive";
	};
	};
	cooling-maps {
	map0 {
	trip = <&cpu2_alert0>;
	cooling-device = <&fan0 0 1>;
	};
	map1 {
	trip = <&cpu2_alert1>;
	cooling-device = <&fan0 1 2>;
	};
	map2 {
	trip = <&cpu2_alert2>;
	cooling-device = <&fan0 2 3>;
	};
	map3 {
	trip = <&cpu2_alert3>;
	cooling-device = <&cpu0 0 2>,
	<&cpu1 0 2>,
	<&cpu2 0 2>,
	<&cpu3 0 2>,
	<&cpu4 0 2>,
	<&cpu5 0 2>,
	<&cpu6 0 2>,
	<&cpu7 0 2>;
	};
	cpu2_cooling_map4: map4 {
	trip = <&cpu2_alert4>;
	cooling-device = <&cpu0 3 8>,
	<&cpu1 3 8>,
	<&cpu2 3 8>,
	<&cpu3 3 8>,
	<&cpu4 3 14>,
	<&cpu5 3 14>,
	<&cpu6 3 14>,
	<&cpu7 3 14>;
	};
	};
	};
	cpu3_thermal: cpu3-thermal {
	thermal-sensors = <&tmu_cpu3 0>;
	polling-delay-passive = <250>;
	polling-delay = <0>;
	trips {
	cpu3_alert0: cpu-alert-0 {
	temperature = <50000>;
	hysteresis = <5000>;
	type = "active";
	};
	cpu3_alert1: cpu-alert-1 {
	temperature = <60000>;
	hysteresis = <5000>;
	type = "active";
	};
	cpu3_alert2: cpu-alert-2 {
	temperature = <70000>;
	hysteresis = <5000>;
	type = "active";
	};
	cpu3_crit0: cpu-crit-0 {
	temperature = <120000>;
	hysteresis = <0>;
	type = "critical";
	};
	cpu3_alert3: cpu-alert-3 {
	temperature = <70000>;
	hysteresis = <10000>;
	type = "passive";
	};
	cpu3_alert4: cpu-alert-4 {
	temperature = <85000>;
	hysteresis = <10000>;
	type = "passive";
	};
	};
	cooling-maps {
	map0 {
	trip = <&cpu3_alert0>;
	cooling-device = <&fan0 0 1>;
	};
	map1 {
	trip = <&cpu3_alert1>;
	cooling-device = <&fan0 1 2>;
	};
	map2 {
	trip = <&cpu3_alert2>;
	cooling-device = <&fan0 2 3>;
	};
	map3 {
	trip = <&cpu3_alert3>;
	cooling-device = <&cpu0 0 2>,
	<&cpu1 0 2>,
	<&cpu2 0 2>,
	<&cpu3 0 2>,
	<&cpu4 0 2>,
	<&cpu5 0 2>,
	<&cpu6 0 2>,
	<&cpu7 0 2>;
	};
	cpu3_cooling_map4: map4 {
	trip = <&cpu3_alert4>;
	cooling-device = <&cpu0 3 8>,
	<&cpu1 3 8>,
	<&cpu2 3 8>,
	<&cpu3 3 8>,
	<&cpu4 3 14>,
	<&cpu5 3 14>,
	<&cpu6 3 14>,
	<&cpu7 3 14>;
	};
	};
	};
	+ gpu_thermal: gpu-thermal {
	+ thermal-sensors = <&tmu_gpu 0>;
	+ polling-delay-passive = <250>;
	+ polling-delay = <0>;
	+ trips {
	+ gpu_alert0: gpu-alert-0 {
	+ temperature = <50000>;
	+ hysteresis = <5000>;
	+ type = "active";
	+ };
	+ gpu_alert1: gpu-alert-1 {
	+ temperature = <60000>;
	+ hysteresis = <5000>;
	+ type = "active";
	+ };
	+ gpu_alert2: gpu-alert-2 {
	+ temperature = <70000>;
	+ hysteresis = <5000>;
	+ type = "active";
	+ };
	+ gpu_crit0: gpu-crit-0 {
	+ temperature = <120000>;
	+ hysteresis = <0>;
	+ type = "critical";
	+ };
	+ gpu_alert3: gpu-alert-3 {
	+ temperature = <70000>;
	+ hysteresis = <10000>;
	+ type = "passive";
	+ };
	+ gpu_alert4: gpu-alert-4 {
	+ temperature = <85000>;
	+ hysteresis = <10000>;
	+ type = "passive";
	+ };
	+ };
	+ cooling-maps {
	+ map0 {
	+ trip = <&gpu_alert0>;
	+ cooling-device = <&fan0 0 1>;
	+ };
	+ map1 {
	+ trip = <&gpu_alert1>;
	+ cooling-device = <&fan0 1 2>;
	+ };
	+ map2 {
	+ trip = <&gpu_alert2>;
	+ cooling-device = <&fan0 2 3>;
	+ };
	+ map3 {
	+ trip = <&gpu_alert3>;
	+ cooling-device = <&gpu 0 2>;
	+ };
	+ map4 {
	+ trip = <&gpu_alert4>;
	+ cooling-device = <&gpu 3 6>;
	+ };
	+ };
	+ };
	};
	};

	&buck10_reg {
	/* Supplies vmmc-supply of mmc_0 */
	regulator-always-on;
	regulator-boot-on;
	};

	&hdmi {
	status = "okay";
	ddc = <&i2c_2>;
	hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_hpd_irq>;

	vdd_osc-supply = <&ldo7_reg>;
	vdd_pll-supply = <&ldo6_reg>;
	vdd-supply = <&ldo6_reg>;
	};

	&hdmicec {
	status = "okay";
	needs-hpd;
	};

	&i2c_2 {
	samsung,i2c-sda-delay = <100>;
	samsung,i2c-max-bus-freq = <66000>;
	/* used by HDMI DDC */
	status = "okay";
	};

	&ldo26_reg {
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;
	};

	&mixer {
	status = "okay";
	};

	&mmc_0 {
	status = "okay";
	mmc-pwrseq = <&emmc_pwrseq>;
	card-detect-delay = <200>;
	samsung,dw-mshc-ciu-div = <3>;
	samsung,dw-mshc-sdr-timing = <0 4>;
	samsung,dw-mshc-ddr-timing = <0 2>;
	samsung,dw-mshc-hs400-timing = <0 2>;
	samsung,read-strobe-delay = <90>;
	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>;
	bus-width = <8>;
	cap-mmc-highspeed;
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	max-frequency = <200000000>;
	vmmc-supply = <&ldo18_reg>;
	vqmmc-supply = <&ldo3_reg>;
	};

	&pinctrl_0 {
	power_key: power-key {
	samsung,pins = "gpx0-3";
	samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
	samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	hdmi_hpd_irq: hdmi-hpd-irq {
	samsung,pins = "gpx3-7";
	samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
	samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};
	};

	&pinctrl_1 {
	emmc_nrst_pin: emmc-nrst {
	samsung,pins = "gpd1-0";
	samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
	samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};
	};
	diff --git a/sys/gnu/dts/arm/gemini-dlink-dir-685.dts b/sys/gnu/dts/arm/gemini-dlink-dir-685.dts
	index e2030ba16512..cc39289e99dd 100644
	--- a/sys/gnu/dts/arm/gemini-dlink-dir-685.dts
	+++ b/sys/gnu/dts/arm/gemini-dlink-dir-685.dts
	@@ -1,469 +1,511 @@
	/*
	* Device Tree file for D-Link DIR-685 Xtreme N Storage Router
	*/

	/dts-v1/;

	#include "gemini.dtsi"
	#include <dt-bindings/input/input.h>

	/ {
	model = "D-Link DIR-685 Xtreme N Storage Router";
	compatible = "dlink,dir-685", "cortina,gemini";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
	/* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
	device_type = "memory";
	reg = <0x00000000 0x8000000>;
	};

	chosen {
	bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait consoleblank=300";
	stdout-path = "uart0:19200n8";
	};

	gpio_keys {
	compatible = "gpio-keys";

	button-esc {
	debounce-interval = <100>;
	wakeup-source;
	linux,code = <KEY_ESC>;
	label = "reset";
	/* Collides with LPC_LAD[0], UART DCD, SSP 97RST */
	gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
	};
	button-eject {
	debounce-interval = <100>;
	wakeup-source;
	linux,code = <KEY_EJECTCD>;
	label = "unmount";
	/* Collides with LPC LFRAME, UART RTS, SSP TXD */
	gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
	};
	};

	vdisp: regulator {
	compatible = "regulator-fixed";
	regulator-name = "display-power";
	regulator-min-microvolt = <3600000>;
	regulator-max-microvolt = <3600000>;
	/* Collides with LCD E */
	gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	spi {
	compatible = "spi-gpio";
	#address-cells = <1>;
	#size-cells = <0>;

	/* Collides with IDE pins, that's cool (we do not use them) */
	gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>;
	gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>;
	gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>;
	cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
	num-chipselects = <1>;

	panel: display@0 {
	compatible = "dlink,dir-685-panel", "ilitek,ili9322";
	reg = <0>;
	/* 50 ns min period = 20 MHz */
	spi-max-frequency = <20000000>;
	vcc-supply = <&vdisp>;
	iovcc-supply = <&vdisp>;
	vci-supply = <&vdisp>;

	port {
	panel_in: endpoint {
	remote-endpoint = <&display_out>;
	};
	};
	};
	};

	leds {
	compatible = "gpio-leds";
	led-wps {
	label = "dir685:blue:WPS";
	/* Collides with ICE */
	gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
	default-state = "on";
	linux,default-trigger = "heartbeat";
	};
	/*
	* These two LEDs are on the side of the device.
	* For electrical reasons, both LEDs cannot be active
	* at the same time so only blue or orange can be on at
	* one time. Enabling both makes the LED go dark.
	* The LEDs both sit inside the unmount button and the
	* label on the case says "unmount".
	*/
	led-blue-hd {
	label = "dir685:blue:HD";
	/* Collides with LPC_SERIRQ, UART DTR, SSP FSC pins */
	gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	linux,default-trigger = "disk-read";
	};
	led-orange-hd {
	label = "dir685:orange:HD";
	/* Collides with LPC_LAD[2], UART DSR, SSP ECLK pins */
	gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	linux,default-trigger = "disk-write";
	};
	};

	/*
	* This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM.
	- * Since the platform has no temperature sensor, this is controlled
	- * from userspace by using the hard disks S.M.A.R.T. temperature
	* sensor. It is turned on when the temperature exceeds 46 degrees
	* and turned off when the temperatures goes below 41 degrees
	* (celsius).
	*/
	- gpio-fan {
	+ fan0: gpio-fan {
	compatible = "gpio-fan";
	/* Collides with IDE */
	gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
	gpio-fan,speed-map = <0 0>, <10000 1>;
	#cooling-cells = <2>;
	};

	+ thermal-zones {
	+ chassis-thermal {
	+ /* Poll every 20 seconds */
	+ polling-delay = <20000>;
	+ /* Poll every 2nd second when cooling */
	+ polling-delay-passive = <2000>;
	+ /* Use the thermal sensor in the hard drive */
	+ thermal-sensors = <&drive0>;
	+
	+ /* Tripping points from the fan.script in the rootfs */
	+ trips {
	+ alert: chassis-alert {
	+ /* At 43 degrees turn on the fan */
	+ temperature = <43000>;
	+ hysteresis = <3000>;
	+ type = "active";
	+ };
	+ crit: chassis-crit {
	+ /* Just shut down at 60 degrees */
	+ temperature = <60000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	+ };
	+
	+ cooling-maps {
	+ map0 {
	+ trip = <&alert>;
	+ cooling-device = <&fan0 1 1>;
	+ };
	+ };
	+ };
	+ };
	+
	/*
	* The touchpad input is connected to a GPIO bit-banged
	* I2C bus.
	*/
	gpio-i2c {
	compatible = "i2c-gpio";
	/* Collides with ICE */
	sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH\|GPIO_OPEN_DRAIN)>;
	scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH\|GPIO_OPEN_DRAIN)>;
	#address-cells = <1>;
	#size-cells = <0>;

	touchkeys@26 {
	compatible = "dlink,dir685-touchkeys";
	reg = <0x26>;
	interrupt-parent = <&gpio0>;
	/* Collides with NAND flash */
	interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
	};
	};

	/* This is a RealTek RTL8366RB switch and PHY using SMI over GPIO */
	switch {
	compatible = "realtek,rtl8366rb";
	/* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
	mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
	mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
	reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
	realtek,disable-leds;

	switch_intc: interrupt-controller {
	/* GPIO 15 provides the interrupt */
	interrupt-parent = <&gpio0>;
	interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;
	#address-cells = <0>;
	#interrupt-cells = <1>;
	};

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	label = "lan0";
	phy-handle = <&phy0>;
	};
	port@1 {
	reg = <1>;
	label = "lan1";
	phy-handle = <&phy1>;
	};
	port@2 {
	reg = <2>;
	label = "lan2";
	phy-handle = <&phy2>;
	};
	port@3 {
	reg = <3>;
	label = "lan3";
	phy-handle = <&phy3>;
	};
	port@4 {
	reg = <4>;
	label = "wan";
	phy-handle = <&phy4>;
	};
	rtl8366rb_cpu_port: port@5 {
	reg = <5>;
	label = "cpu";
	ethernet = <&gmac0>;
	phy-mode = "rgmii";
	fixed-link {
	speed = <1000>;
	full-duplex;
	pause;
	};
	};

	};

	mdio {
	compatible = "realtek,smi-mdio";
	#address-cells = <1>;
	#size-cells = <0>;

	phy0: phy@0 {
	reg = <0>;
	interrupt-parent = <&switch_intc>;
	interrupts = <0>;
	};
	phy1: phy@1 {
	reg = <1>;
	interrupt-parent = <&switch_intc>;
	interrupts = <1>;
	};
	phy2: phy@2 {
	reg = <2>;
	interrupt-parent = <&switch_intc>;
	interrupts = <2>;
	};
	phy3: phy@3 {
	reg = <3>;
	interrupt-parent = <&switch_intc>;
	interrupts = <3>;
	};
	phy4: phy@4 {
	reg = <4>;
	interrupt-parent = <&switch_intc>;
	interrupts = <12>;
	};
	};
	};

	soc {
	flash@30000000 {
	/*
	* Flash access collides with the Chip Enable signal for
	* the display panel, that reuse the parallel flash Chip
	* Select 1 (CS1). We switch the pin control state so we
	* enable these pins for flash access only when we need
	* then, and when disabled they can be used for GPIO which
	* is what the display panel needs.
	*/
	status = "okay";
	pinctrl-names = "enabled", "disabled";
	pinctrl-0 = <&pflash_default_pins>;
	pinctrl-1 = <&pflash_disabled_pins>;

	/* 32MB of flash */
	reg = <0x30000000 0x02000000>;

	partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	/*
	* This "RedBoot" is the Storlink derivative.
	*/
	partition@0 {
	label = "RedBoot";
	reg = <0x00000000 0x00040000>;
	read-only;
	};
	/*
	* This firmware image contains the kernel catenated
	* with the squashfs root filesystem. For some reason
	* this is called "upgrade" on the vendor system.
	*/
	partition@40000 {
	label = "upgrade";
	reg = <0x00040000 0x01f40000>;
	read-only;
	};
	/* RGDB, Residental Gateway Database? */
	partition@1f80000 {
	label = "rgdb";
	reg = <0x01f80000 0x00040000>;
	read-only;
	};
	/*
	* This partition contains MAC addresses for WAN,
	* WLAN and LAN, and the country code (for wireless
	* I guess).
	*/
	partition@1fc0000 {
	label = "nvram";
	reg = <0x01fc0000 0x00020000>;
	read-only;
	};
	partition@1fe0000 {
	label = "LangPack";
	reg = <0x01fe0000 0x00020000>;
	read-only;
	};
	};
	};

	syscon: syscon@40000000 {
	pinctrl {
	/*
	* gpio0bgrp cover line 5, 6 used by TK I2C
	* gpio0bgrp cover line 7 used by WPS LED
	* gpio0cgrp cover line 8, 13 used by keys
	* and 11, 12 used by the HD LEDs
	* and line 14, 15 used by RTL8366
	* RESET and phy ready
	* gpio0egrp cover line 16 used by VDISP
	* gpio0fgrp cover line 17 used by TK IRQ
	* gpio0ggrp cover line 20 used by panel CS
	* gpio0hgrp cover line 21,22 used by RTL8366RB MDIO
	*/
	gpio0_default_pins: pinctrl-gpio0 {
	mux {
	function = "gpio0";
	groups = "gpio0bgrp",
	"gpio0cgrp",
	"gpio0egrp",
	"gpio0fgrp",
	"gpio0hgrp";
	};
	};
	/*
	* gpio1bgrp cover line 5,8,7 used by panel SPI
	* also line 6 used by the fan
	*
	*/
	gpio1_default_pins: pinctrl-gpio1 {
	mux {
	function = "gpio1";
	groups = "gpio1bgrp";
	};
	};
	/*
	* These GPIO groups will be mapped in over some
	* of the flash pins when the flash is not in
	* active use.
	*/
	pflash_disabled_pins: pinctrl-pflash-disabled {
	mux {
	function = "gpio0";
	groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp",
	"gpio0kgrp";
	};
	};
	pinctrl-gmii {
	mux {
	function = "gmii";
	groups = "gmii_gmac0_grp";
	};
	conf0 {
	pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV",
	"Y7 GMAC0 RXC", "Y11 GMAC1 RXC",
	"T8 GMAC0 TXEN", "W11 GMAC1 TXEN",
	"U8 GMAC0 TXC", "V11 GMAC1 TXC",
	"W8 GMAC0 RXD0", "V9 GMAC0 RXD1",
	"Y8 GMAC0 RXD2", "U9 GMAC0 RXD3",
	"T7 GMAC0 TXD0", "U6 GMAC0 TXD1",
	"V7 GMAC0 TXD2", "U7 GMAC0 TXD3",
	"Y12 GMAC1 RXD0", "V12 GMAC1 RXD1",
	"T11 GMAC1 RXD2", "W12 GMAC1 RXD3",
	"U10 GMAC1 TXD0", "Y10 GMAC1 TXD1",
	"W10 GMAC1 TXD2", "T9 GMAC1 TXD3";
	skew-delay = <7>;
	};
	/* Set up drive strength on GMAC0 to 16 mA */
	conf1 {
	groups = "gmii_gmac0_grp";
	drive-strength = <16>;
	};
	};
	};
	};

	sata: sata@46000000 {
	cortina,gemini-ata-muxmode = <0>;
	cortina,gemini-enable-sata-bridge;
	status = "okay";
	};

	gpio0: gpio@4d000000 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpio0_default_pins>;
	};

	gpio1: gpio@4e000000 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpio1_default_pins>;
	};

	pci@50000000 {
	status = "okay";
	interrupt-map-mask = <0xf800 0 0 7>;
	interrupt-map =
	<0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
	<0x4800 0 0 2 &pci_intc 1>,
	<0x4800 0 0 3 &pci_intc 2>,
	<0x4800 0 0 4 &pci_intc 3>,
	<0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
	<0x5000 0 0 2 &pci_intc 2>,
	<0x5000 0 0 3 &pci_intc 3>,
	<0x5000 0 0 4 &pci_intc 0>,
	<0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
	<0x5800 0 0 2 &pci_intc 3>,
	<0x5800 0 0 3 &pci_intc 0>,
	<0x5800 0 0 4 &pci_intc 1>,
	<0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
	<0x6000 0 0 2 &pci_intc 0>,
	<0x6000 0 0 3 &pci_intc 1>,
	<0x6000 0 0 4 &pci_intc 2>;
	};

	ethernet@60000000 {
	status = "okay";

	ethernet-port@0 {
	phy-mode = "rgmii";
	fixed-link {
	speed = <1000>;
	full-duplex;
	pause;
	};
	};
	ethernet-port@1 {
	/* Not used in this platform */
	};
	};

	- ata@63000000 {
	+ ide@63000000 {
	status = "okay";
	+
	+ /*
	+ * This drive may have a temperature sensor with a
	+ * thermal zone we can use for thermal control of the
	+ * chassis temperature using the fan.
	+ */
	+ drive0: ide-port@0 {
	+ reg = <0>;
	+ #thermal-sensor-cells = <0>;
	+ };
	};

	display-controller@6a000000 {
	status = "okay";

	port@0 {
	reg = <0>;
	display_out: endpoint {
	remote-endpoint = <&panel_in>;
	};
	};
	};

	usb@68000000 {
	status = "okay";
	};

	usb@69000000 {
	status = "okay";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/gemini-dlink-dns-313.dts b/sys/gnu/dts/arm/gemini-dlink-dns-313.dts
	index 360642a02a48..c6f3d90e3e90 100644
	--- a/sys/gnu/dts/arm/gemini-dlink-dns-313.dts
	+++ b/sys/gnu/dts/arm/gemini-dlink-dns-313.dts
	@@ -1,304 +1,304 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure
	*/

	/dts-v1/;

	#include "gemini.dtsi"
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	model = "D-Link DNS-313 1-Bay Network Storage Enclosure";
	compatible = "dlink,dns-313", "cortina,gemini";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
	/* 64 MB SDRAM in a Nanya NT5DS32M16BS-6K package */
	device_type = "memory";
	reg = <0x00000000 0x4000000>;
	};

	aliases {
	mdio-gpio0 = &mdio0;
	};

	chosen {
	bootargs = "console=ttyS0,19200n8 root=/dev/sda4 rw rootwait";
	stdout-path = "uart0:19200n8";
	};

	gpio_keys {
	compatible = "gpio-keys";

	button-esc {
	debounce-interval = <100>;
	wakeup-source;
	linux,code = <KEY_ESC>;
	label = "reset";
	gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
	};
	};

	leds {
	compatible = "gpio-leds";
	led-power {
	label = "dns313:blue:power";
	gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
	default-state = "on";
	linux,default-trigger = "heartbeat";
	};
	led-disk-blue {
	label = "dns313:blue:disk";
	gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};
	led-disk-green {
	label = "dns313:green:disk";
	gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	linux,default-trigger = "disk-read";
	};
	led-disk-red {
	label = "dns313:red:disk";
	gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	linux,default-trigger = "disk-write";
	};
	};

	/*
	* This is a ADDA AD0405GB-G73 fan @3000 and 6000 RPM.
	*/
	fan0: gpio-fan {
	compatible = "gpio-fan";
	gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
	<&gpio0 12 GPIO_ACTIVE_HIGH>;
	gpio-fan,speed-map = <0 0>, <3000 1>, <6000 2>;
	#cooling-cells = <2>;
	};


	/* Global Mixed-Mode Technology G751 mounted on GPIO I2C */
	gpio-i2c {
	compatible = "i2c-gpio";
	sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH\|GPIO_OPEN_DRAIN)>;
	scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH\|GPIO_OPEN_DRAIN)>;
	#address-cells = <1>;
	#size-cells = <0>;

	g751: temperature-sensor@48 {
	compatible = "gmt,g751";
	reg = <0x48>;
	#thermal-sensor-cells = <0>;
	};
	};

	thermal-zones {
	chassis-thermal {
	/* Poll every 20 seconds */
	polling-delay = <20000>;
	/* Poll every 2nd second when cooling */
	polling-delay-passive = <2000>;

	thermal-sensors = <&g751>;

	/* Tripping points from the fan.script in the rootfs */
	trips {
	chassis_alert0: chassis-alert0 {
	/* At 43 degrees turn on low speed */
	temperature = <43000>;
	hysteresis = <3000>;
	type = "active";
	};
	chassis_alert1: chassis-alert1 {
	/* At 47 degrees turn on high speed */
	temperature = <47000>;
	hysteresis = <3000>;
	type = "active";
	};
	chassis_crit: chassis-crit {
	/* Just shut down at 60 degrees */
	temperature = <60000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&chassis_alert0>;
	cooling-device = <&fan0 1 1>;
	};
	map1 {
	trip = <&chassis_alert1>;
	cooling-device = <&fan0 2 2>;
	};
	};
	};
	};

	mdio0: ethernet-phy {
	compatible = "virtual,mdio-gpio";
	/* Uses MDC and MDIO */
	gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
	<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
	#address-cells = <1>;
	#size-cells = <0>;

	/* This is a Realtek RTL8211B Gigabit ethernet transceiver */
	phy0: ethernet-phy@1 {
	reg = <1>;
	device_type = "ethernet-phy";
	};
	};

	soc {
	flash@30000000 {
	/*
	* This is a Eon EN29LV400AB 512 KiB flash with
	* three partitions.
	*/
	compatible = "cortina,gemini-flash", "jedec-flash";
	status = "okay";
	reg = <0x30000000 0x00080000>;

	/*
	* This "RedBoot" is the Storlink derivative.
	*/
	partition@0 {
	label = "RedBoot";
	reg = <0x00000000 0x00040000>;
	read-only;
	};
	partition@40000 {
	label = "MTD1";
	reg = <0x00040000 0x00020000>;
	read-only;
	};
	partition@60000 {
	label = "MTD2";
	reg = <0x00060000 0x00020000>;
	read-only;
	};
	};

	syscon: syscon@40000000 {
	pinctrl {
	/*
	*/
	gpio0_default_pins: pinctrl-gpio0 {
	mux {
	function = "gpio0";
	groups =
	/* Used by LEDs conflicts ICE */
	"gpio0bgrp",
	/* Used by ? conflicts ICE */
	"gpio0cgrp",
	/*
	* Used by fan & G751, conflicts LPC,
	* UART modem lines, SSP
	*/
	"gpio0egrp",
	/* Used by G751 */
	"gpio0fgrp",
	/* Used by MDIO */
	"gpio0igrp";
	};
	};
	gpio1_default_pins: pinctrl-gpio1 {
	mux {
	function = "gpio1";
	/* Used by "reset" button */
	groups = "gpio1dgrp";
	};
	};
	pinctrl-gmii {
	mux {
	function = "gmii";
	groups = "gmii_gmac0_grp";
	};
	/*
	* In the vendor Linux tree, these values are set for the C3
	* version of the SL3512 ASIC with the comment "benson suggest"
	*/
	conf0 {
	pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV";
	skew-delay = <0>;
	};
	conf1 {
	pins = "T8 GMAC0 RXC";
	skew-delay = <10>;
	};
	conf2 {
	pins = "T11 GMAC1 RXC";
	skew-delay = <15>;
	};
	conf3 {
	pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN";
	skew-delay = <7>;
	};
	conf4 {
	pins = "V7 GMAC0 TXC", "P10 GMAC1 TXC";
	skew-delay = <10>;
	};
	conf5 {
	/* The data lines all have default skew */
	pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1",
	"P9 GMAC0 RXD2", "R9 GMAC0 RXD3",
	"R11 GMAC1 RXD0", "P11 GMAC1 RXD1",
	"V12 GMAC1 RXD2", "U12 GMAC1 RXD3",
	"R10 GMAC1 TXD0", "T10 GMAC1 TXD1",
	"U10 GMAC1 TXD2", "V10 GMAC1 TXD3";
	skew-delay = <7>;
	};
	conf6 {
	pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1",
	"R7 GMAC0 TXD2", "P7 GMAC0 TXD3";
	skew-delay = <5>;
	};
	/* Set up drive strength on GMAC0 to 16 mA */
	conf7 {
	groups = "gmii_gmac0_grp";
	drive-strength = <16>;
	};
	};
	};
	};

	sata: sata@46000000 {
	/* The ROM uses this muxmode */
	cortina,gemini-ata-muxmode = <0>;
	cortina,gemini-enable-sata-bridge;
	status = "okay";
	};

	gpio0: gpio@4d000000 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpio0_default_pins>;
	};

	gpio1: gpio@4e000000 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpio1_default_pins>;
	};

	ethernet@60000000 {
	status = "okay";

	ethernet-port@0 {
	phy-mode = "rgmii";
	phy-handle = <&phy0>;
	};
	ethernet-port@1 {
	/* Not used in this platform */
	};
	};

	- ata@63000000 {
	+ ide@63000000 {
	status = "okay";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/gemini-nas4220b.dts b/sys/gnu/dts/arm/gemini-nas4220b.dts
	index 521714f38eed..43c45f7e1e0a 100644
	--- a/sys/gnu/dts/arm/gemini-nas4220b.dts
	+++ b/sys/gnu/dts/arm/gemini-nas4220b.dts
	@@ -1,189 +1,189 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree file for the Gemini-based Raidsonic NAS IB-4220-B
	*/

	/dts-v1/;

	#include "gemini.dtsi"
	#include <dt-bindings/input/input.h>

	/ {
	model = "Raidsonic NAS IB-4220-B";
	compatible = "raidsonic,ib-4220-b", "cortina,gemini";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 { /* 128 MB */
	device_type = "memory";
	reg = <0x00000000 0x8000000>;
	};

	chosen {
	bootargs = "console=ttyS0,19200n8 root=/dev/mtdblock3 rw rootfstype=squashfs,jffs2 rootwait";
	stdout-path = &uart0;
	};

	gpio_keys {
	compatible = "gpio-keys";

	button-setup {
	debounce-interval = <100>;
	wakeup-source;
	linux,code = <KEY_SETUP>;
	label = "Backup button";
	/* Conflict with TVC */
	gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
	};
	button-restart {
	debounce-interval = <100>;
	wakeup-source;
	linux,code = <KEY_RESTART>;
	label = "Softreset button";
	/* Conflict with TVC */
	gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
	};
	};

	leds {
	compatible = "gpio-leds";
	led-orange-hdd {
	label = "nas4220b:orange:hdd";
	/* Conflict with TVC */
	gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
	default-state = "on";
	};
	led-green-os {
	label = "nas4220b:green:os";
	/* Conflict with TVC */
	gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
	default-state = "on";
	linux,default-trigger = "heartbeat";
	};
	};

	mdio0: ethernet-phy {
	compatible = "virtual,mdio-gpio";
	gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
	<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
	#address-cells = <1>;
	#size-cells = <0>;

	phy0: ethernet-phy@1 {
	reg = <1>;
	device_type = "ethernet-phy";
	};
	};

	soc {
	flash@30000000 {
	status = "okay";
	/* 16MB of flash */
	reg = <0x30000000 0x01000000>;

	partitions {
	compatible = "redboot-fis";
	/* Eraseblock at 0xfe0000 */
	fis-index-block = <0x1fc>;
	};
	};

	syscon: syscon@40000000 {
	pinctrl {
	/*
	* gpio1dgrp cover line 28-31 otherwise used
	* by TVC.
	*/
	gpio1_default_pins: pinctrl-gpio1 {
	mux {
	function = "gpio1";
	groups = "gpio1dgrp";
	};
	};
	pinctrl-gmii {
	mux {
	function = "gmii";
	groups = "gmii_gmac0_grp";
	};
	/* Settings come from OpenWRT, pins on SL3516 */
	conf0 {
	pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV";
	skew-delay = <0>;
	};
	conf1 {
	pins = "Y7 GMAC0 RXC", "Y11 GMAC1 RXC";
	skew-delay = <15>;
	};
	conf2 {
	pins = "T8 GMAC0 TXEN", "W11 GMAC1 TXEN";
	skew-delay = <7>;
	};
	conf3 {
	pins = "U8 GMAC0 TXC";
	skew-delay = <11>;
	};
	conf4 {
	pins = "V11 GMAC1 TXC";
	skew-delay = <10>;
	};
	conf5 {
	/* The data lines all have default skew */
	pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1",
	"Y8 GMAC0 RXD2", "U9 GMAC0 RXD3",
	"T7 GMAC0 TXD0", "U6 GMAC0 TXD1",
	"V7 GMAC0 TXD2", "U7 GMAC0 TXD3",
	"Y12 GMAC1 RXD0", "V12 GMAC1 RXD1",
	"T11 GMAC1 RXD2", "W12 GMAC1 RXD3",
	"U10 GMAC1 TXD0", "Y10 GMAC1 TXD1",
	"W10 GMAC1 TXD2", "T9 GMAC1 TXD3";
	skew-delay = <7>;
	};
	/* Set up drive strength on GMAC0 to 16 mA */
	conf6 {
	groups = "gmii_gmac0_grp";
	drive-strength = <16>;
	};
	};
	};
	};

	sata: sata@46000000 {
	cortina,gemini-ata-muxmode = <0>;
	cortina,gemini-enable-sata-bridge;
	status = "okay";
	};

	gpio1: gpio@4e000000 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpio1_default_pins>;
	};

	ethernet@60000000 {
	status = "okay";

	ethernet-port@0 {
	phy-mode = "rgmii";
	phy-handle = <&phy0>;
	};
	ethernet-port@1 {
	/* Not used in this platform */
	};
	};

	- ata@63000000 {
	+ ide@63000000 {
	status = "okay";
	};

	- ata@63400000 {
	+ ide@63400000 {
	status = "okay";
	};

	usb@68000000 {
	status = "okay";
	};

	usb@69000000 {
	status = "okay";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/gemini-sl93512r.dts b/sys/gnu/dts/arm/gemini-sl93512r.dts
	index a98af0351906..a0916d3c1059 100644
	--- a/sys/gnu/dts/arm/gemini-sl93512r.dts
	+++ b/sys/gnu/dts/arm/gemini-sl93512r.dts
	@@ -1,312 +1,312 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree file for the Storm Semiconductor SL93512R_BRD
	* Gemini reference design, also initially called
	* "Gemini324 EV-Board" before Storm acquired Storlink Semiconductor.
	* The series were later acquired by Cortina Systems.
	*/

	/dts-v1/;

	#include "gemini.dtsi"
	#include <dt-bindings/input/input.h>

	/ {
	model = "Storlink Semiconductor Gemini324 EV-Board / Storm Semiconductor SL93512R_BRD";
	compatible = "storlink,gemini324", "storm,sl93512r", "cortina,gemini";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
	/* 64 MB Samsung K4H511638B */
	device_type = "memory";
	reg = <0x00000000 0x4000000>;
	};

	chosen {
	bootargs = "console=ttyS0,19200n8 root=/dev/mtdblock3 rw rootfstype=squashfs,jffs2 rootwait";
	stdout-path = &uart0;
	};

	gpio_keys {
	compatible = "gpio-keys";

	button-wps {
	debounce-interval = <50>;
	wakeup-source;
	linux,code = <KEY_WPS_BUTTON>;
	label = "WPS";
	/* Conflicts with TVC and extended flash */
	gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
	};

	button-setup {
	debounce-interval = <50>;
	wakeup-source;
	linux,code = <KEY_SETUP>;
	label = "factory reset";
	/* Conflict with NAND flash */
	gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
	};
	};

	leds {
	compatible = "gpio-leds";
	led-green-harddisk {
	label = "sq201:green:harddisk";
	/* Conflict with LCD (no problem) */
	gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
	default-state = "off";
	linux,default-trigger = "disk-activity";
	};
	led-green-wireless {
	label = "sq201:green:wireless";
	/* Conflict with NAND flash CE0 (no problem) */
	gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
	default-state = "on";
	linux,default-trigger = "heartbeat";
	};
	};

	mdio0: mdio {
	compatible = "virtual,mdio-gpio";
	/* Uses MDC and MDIO */
	gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
	<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
	#address-cells = <1>;
	#size-cells = <0>;

	/* This is a Marvell 88E1111 ethernet transciever */
	phy0: ethernet-phy@1 {
	reg = <1>;
	};
	};

	spi {
	compatible = "spi-gpio";
	#address-cells = <1>;
	#size-cells = <0>;
	/* Check pin collisions */
	gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
	gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>;
	gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>;
	cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
	num-chipselects = <1>;

	switch@0 {
	compatible = "vitesse,vsc7385";
	reg = <0>;
	/* Specified for 2.5 MHz or below */
	spi-max-frequency = <2500000>;
	gpio-controller;
	#gpio-cells = <2>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	label = "lan1";
	};
	port@1 {
	reg = <1>;
	label = "lan2";
	};
	port@2 {
	reg = <2>;
	label = "lan3";
	};
	port@3 {
	reg = <3>;
	label = "lan4";
	};
	vsc: port@6 {
	reg = <6>;
	label = "cpu";
	ethernet = <&gmac1>;
	phy-mode = "rgmii";
	fixed-link {
	speed = <1000>;
	full-duplex;
	pause;
	};
	};
	};
	};
	};


	soc {
	flash@30000000 {
	status = "okay";
	/* 16MB of flash */
	reg = <0x30000000 0x01000000>;

	partitions {
	compatible = "redboot-fis";
	/* Eraseblock at 0xfe0000 */
	fis-index-block = <0x1fc>;
	};
	};

	syscon: syscon@40000000 {
	pinctrl {
	/*
	* gpio0agrp cover line 0, used by WPS button
	* gpio0fgrp cover line 16 used by HD LED
	* gpio0ggrp cover line 17, 18 used by wireless LAN LED and
	* reset button OR USB ID select on 17 and USB VBUS select
	* on 18. (Confusing.)
	* gpio0igrp cover line 21, 22 used by MDIO for Marvell PHY
	*/
	gpio0_default_pins: pinctrl-gpio0 {
	mux {
	function = "gpio0";
	groups = "gpio0agrp",
	"gpio0fgrp",
	"gpio0ggrp",
	"gpio0igrp";
	};
	};
	/*
	* gpio1dgrp cover lines used by SPI for
	* the Vitesse chip (28-31)
	*/
	gpio1_default_pins: pinctrl-gpio1 {
	mux {
	function = "gpio1";
	groups = "gpio1dgrp";
	};
	};
	pinctrl-gmii {
	mux {
	function = "gmii";
	groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
	};
	/* Control pad skew comes from sl_switch.c in the vendor code */
	conf0 {
	pins = "P10 GMAC1 TXC";
	skew-delay = <5>;
	};
	conf1 {
	pins = "V11 GMAC1 TXEN";
	skew-delay = <7>;
	};
	conf2 {
	pins = "T11 GMAC1 RXC";
	skew-delay = <8>;
	};
	conf3 {
	pins = "U11 GMAC1 RXDV";
	skew-delay = <7>;
	};
	conf4 {
	pins = "V7 GMAC0 TXC";
	skew-delay = <10>;
	};
	conf5 {
	pins = "P8 GMAC0 TXEN";
	skew-delay = <7>; /* 5 at another place? */
	};
	conf6 {
	pins = "T8 GMAC0 RXC";
	skew-delay = <15>;
	};
	conf7 {
	pins = "R8 GMAC0 RXDV";
	skew-delay = <0>;
	};
	conf8 {
	/* The data lines all have default skew */
	pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1",
	"P9 GMAC0 RXD2", "R9 GMAC0 RXD3",
	"R11 GMAC1 RXD0", "P11 GMAC1 RXD1",
	"V12 GMAC1 RXD2", "U12 GMAC1 RXD3",
	"R10 GMAC1 TXD0", "T10 GMAC1 TXD1",
	"U10 GMAC1 TXD2", "V10 GMAC1 TXD3";
	skew-delay = <7>;
	};
	/* Appears in sl351x_gmac.c in the vendor code */
	conf9 {
	pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1",
	"R7 GMAC0 TXD2", "P7 GMAC0 TXD3";
	skew-delay = <5>;
	};
	};
	};
	};

	/* Both interfaces brought out on SATA connectors */
	sata: sata@46000000 {
	cortina,gemini-ata-muxmode = <0>;
	cortina,gemini-enable-sata-bridge;
	status = "okay";
	};

	gpio0: gpio@4d000000 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpio0_default_pins>;
	};

	gpio1: gpio@4e000000 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpio1_default_pins>;
	};

	pci@50000000 {
	status = "okay";
	interrupt-map-mask = <0xf800 0 0 7>;
	interrupt-map =
	<0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
	<0x4800 0 0 2 &pci_intc 1>,
	<0x4800 0 0 3 &pci_intc 2>,
	<0x4800 0 0 4 &pci_intc 3>,
	<0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
	<0x5000 0 0 2 &pci_intc 2>,
	<0x5000 0 0 3 &pci_intc 3>,
	<0x5000 0 0 4 &pci_intc 0>,
	<0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
	<0x5800 0 0 2 &pci_intc 3>,
	<0x5800 0 0 3 &pci_intc 0>,
	<0x5800 0 0 4 &pci_intc 1>,
	<0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
	<0x6000 0 0 2 &pci_intc 0>,
	<0x6000 0 0 3 &pci_intc 1>,
	<0x6000 0 0 4 &pci_intc 2>;
	};

	ethernet@60000000 {
	status = "okay";

	ethernet-port@0 {
	phy-mode = "rgmii";
	phy-handle = <&phy0>;
	};
	ethernet-port@1 {
	phy-mode = "rgmii";
	fixed-link {
	speed = <1000>;
	full-duplex;
	pause;
	};
	};
	};

	- ata@63000000 {
	+ ide@63000000 {
	status = "okay";
	};

	- ata@63400000 {
	+ ide@63400000 {
	status = "okay";
	};

	usb@68000000 {
	status = "okay";
	};

	usb@69000000 {
	status = "okay";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/gemini-sq201.dts b/sys/gnu/dts/arm/gemini-sq201.dts
	index 239dfacaae4d..0c6e6d35bfaa 100644
	--- a/sys/gnu/dts/arm/gemini-sq201.dts
	+++ b/sys/gnu/dts/arm/gemini-sq201.dts
	@@ -1,304 +1,304 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree file for ITian Square One SQ201 NAS
	*/

	/dts-v1/;

	#include "gemini.dtsi"
	#include <dt-bindings/input/input.h>

	/ {
	model = "ITian Square One SQ201";
	compatible = "itian,sq201", "cortina,gemini";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 { /* 128 MB */
	device_type = "memory";
	reg = <0x00000000 0x8000000>;
	};

	chosen {
	bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
	stdout-path = &uart0;
	};

	gpio_keys {
	compatible = "gpio-keys";

	button-setup {
	debounce-interval = <100>;
	wakeup-source;
	linux,code = <KEY_SETUP>;
	label = "factory reset";
	/* Conflict with NAND flash */
	gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
	};
	};

	leds {
	compatible = "gpio-leds";
	led-green-info {
	label = "sq201:green:info";
	gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
	default-state = "on";
	linux,default-trigger = "heartbeat";
	};
	led-green-usb {
	label = "sq201:green:usb";
	gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	linux,default-trigger = "usb-host";
	};
	};

	mdio0: mdio {
	compatible = "virtual,mdio-gpio";
	/* Uses MDC and MDIO */
	gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
	<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
	#address-cells = <1>;
	#size-cells = <0>;

	/* This is a Marvell 88E1111 ethernet transciever */
	phy0: ethernet-phy@1 {
	reg = <1>;
	};
	};

	spi {
	compatible = "spi-gpio";
	#address-cells = <1>;
	#size-cells = <0>;
	/* Check pin collisions */
	gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
	gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>;
	gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>;
	cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
	num-chipselects = <1>;

	switch@0 {
	compatible = "vitesse,vsc7395";
	reg = <0>;
	/* Specified for 2.5 MHz or below */
	spi-max-frequency = <2500000>;
	gpio-controller;
	#gpio-cells = <2>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	label = "lan1";
	};
	port@1 {
	reg = <1>;
	label = "lan2";
	};
	port@2 {
	reg = <2>;
	label = "lan3";
	};
	port@3 {
	reg = <3>;
	label = "lan4";
	};
	vsc: port@6 {
	reg = <6>;
	label = "cpu";
	ethernet = <&gmac1>;
	phy-mode = "rgmii";
	fixed-link {
	speed = <1000>;
	full-duplex;
	pause;
	};
	};
	};
	};
	};


	soc {
	flash@30000000 {
	status = "okay";
	pinctrl-names = "enabled", "disabled";
	pinctrl-0 = <&pflash_default_pins>;
	pinctrl-1 = <&pflash_disabled_pins>;
	/* 16MB of flash */
	reg = <0x30000000 0x01000000>;

	partitions {
	compatible = "redboot-fis";
	/* Eraseblock at 0xfe0000 */
	fis-index-block = <0x1fc>;
	};
	};

	syscon: syscon@40000000 {
	pinctrl {
	/*
	* gpio0fgrp cover line 18 used by reset button
	* gpio0ggrp cover line 20 used by info LED
	* gpio0hgrp cover line 21, 22 used by MDIO for Marvell PHY
	* gpio0kgrp cover line 31 used by USB LED
	*/
	gpio0_default_pins: pinctrl-gpio0 {
	mux {
	function = "gpio0";
	groups = "gpio0fgrp",
	"gpio0hgrp";
	};
	};
	/*
	* gpio0dgrp cover lines used by the SPI
	* to the Vitesse G5x chip.
	*/
	gpio1_default_pins: pinctrl-gpio1 {
	mux {
	function = "gpio1";
	groups = "gpio1dgrp";
	};
	};
	/*
	* These GPIO groups will be mapped in over some
	* of the flash pins when the flash is not in
	* active use.
	*/
	pflash_disabled_pins: pinctrl-pflash-disabled {
	mux {
	function = "gpio0";
	groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp",
	"gpio0kgrp";
	};
	};
	pinctrl-gmii {
	mux {
	function = "gmii";
	groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
	};
	/* Settings come from memory dump in PLATO */
	conf0 {
	pins = "V8 GMAC0 RXDV";
	skew-delay = <0>;
	};
	conf1 {
	pins = "Y7 GMAC0 RXC";
	skew-delay = <15>;
	};
	conf2 {
	pins = "T8 GMAC0 TXEN";
	skew-delay = <7>;
	};
	conf3 {
	pins = "U8 GMAC0 TXC";
	skew-delay = <10>;
	};
	conf4 {
	pins = "T10 GMAC1 RXDV";
	skew-delay = <7>;
	};
	conf5 {
	pins = "Y11 GMAC1 RXC";
	skew-delay = <8>;
	};
	conf6 {
	pins = "W11 GMAC1 TXEN";
	skew-delay = <7>;
	};
	conf7 {
	pins = "V11 GMAC1 TXC";
	skew-delay = <5>;
	};
	conf8 {
	/* The data lines all have default skew */
	pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1",
	"Y8 GMAC0 RXD2", "U9 GMAC0 RXD3",
	"T7 GMAC0 TXD0", "U6 GMAC0 TXD1",
	"V7 GMAC0 TXD2", "U7 GMAC0 TXD3",
	"Y12 GMAC1 RXD0", "V12 GMAC1 RXD1",
	"T11 GMAC1 RXD2", "W12 GMAC1 RXD3",
	"U10 GMAC1 TXD0", "Y10 GMAC1 TXD1",
	"W10 GMAC1 TXD2", "T9 GMAC1 TXD3";
	skew-delay = <7>;
	};
	/* Set up drive strength on GMAC0 and GMAC1 to 16 mA */
	conf9 {
	groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
	drive-strength = <16>;
	};
	};
	};
	};

	sata: sata@46000000 {
	cortina,gemini-ata-muxmode = <0>;
	cortina,gemini-enable-sata-bridge;
	status = "okay";
	};

	gpio0: gpio@4d000000 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpio0_default_pins>;
	};

	gpio1: gpio@4e000000 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpio1_default_pins>;
	};

	pci@50000000 {
	status = "okay";
	interrupt-map-mask = <0xf800 0 0 7>;
	interrupt-map =
	<0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
	<0x4800 0 0 2 &pci_intc 1>,
	<0x4800 0 0 3 &pci_intc 2>,
	<0x4800 0 0 4 &pci_intc 3>,
	<0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
	<0x5000 0 0 2 &pci_intc 2>,
	<0x5000 0 0 3 &pci_intc 3>,
	<0x5000 0 0 4 &pci_intc 0>,
	<0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
	<0x5800 0 0 2 &pci_intc 3>,
	<0x5800 0 0 3 &pci_intc 0>,
	<0x5800 0 0 4 &pci_intc 1>,
	<0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
	<0x6000 0 0 2 &pci_intc 0>,
	<0x6000 0 0 3 &pci_intc 1>,
	<0x6000 0 0 4 &pci_intc 2>;
	};

	ethernet@60000000 {
	status = "okay";

	ethernet-port@0 {
	phy-mode = "rgmii";
	phy-handle = <&phy0>;
	};
	ethernet-port@1 {
	phy-mode = "rgmii";
	fixed-link {
	speed = <1000>;
	full-duplex;
	pause;
	};
	};
	};

	- ata@63000000 {
	+ ide@63000000 {
	status = "okay";
	};

	usb@68000000 {
	status = "okay";
	};

	usb@69000000 {
	status = "okay";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/gemini.dtsi b/sys/gnu/dts/arm/gemini.dtsi
	index 8cf67b11751f..065ed10a79fa 100644
	--- a/sys/gnu/dts/arm/gemini.dtsi
	+++ b/sys/gnu/dts/arm/gemini.dtsi
	@@ -1,445 +1,449 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree file for Cortina systems Gemini SoC
	*/

	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/clock/cortina,gemini-clock.h>
	#include <dt-bindings/reset/cortina,gemini-reset.h>
	#include <dt-bindings/gpio/gpio.h>

	/ {
	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "simple-bus";
	interrupt-parent = <&intcon>;

	flash@30000000 {
	compatible = "cortina,gemini-flash", "cfi-flash";
	syscon = <&syscon>;
	pinctrl-names = "default";
	pinctrl-0 = <&pflash_default_pins>;
	bank-width = <2>;
	#address-cells = <1>;
	#size-cells = <1>;
	status = "disabled";
	};

	syscon: syscon@40000000 {
	compatible = "cortina,gemini-syscon",
	"syscon", "simple-mfd";
	reg = <0x40000000 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;

	syscon-reboot {
	compatible = "syscon-reboot";
	regmap = <&syscon>;
	/* GLOBAL_RESET register */
	offset = <0x0c>;
	/* RESET_GLOBAL \| RESET_CPU1 */
	mask = <0xC0000000>;
	};

	pinctrl {
	compatible = "cortina,gemini-pinctrl";
	regmap = <&syscon>;
	/* Hog the DRAM pins */
	pinctrl-names = "default";
	pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
	<&vcontrol_default_pins>;

	dram_default_pins: pinctrl-dram {
	mux {
	function = "dram";
	groups = "dramgrp";
	};
	};
	rtc_default_pins: pinctrl-rtc {
	mux {
	function = "rtc";
	groups = "rtcgrp";
	};
	};
	power_default_pins: pinctrl-power {
	mux {
	function = "power";
	groups = "powergrp";
	};
	};
	cir_default_pins: pinctrl-cir {
	mux {
	function = "cir";
	groups = "cirgrp";
	};
	};
	system_default_pins: pinctrl-system {
	mux {
	function = "system";
	groups = "systemgrp";
	};
	};
	vcontrol_default_pins: pinctrl-vcontrol {
	mux {
	function = "vcontrol";
	groups = "vcontrolgrp";
	};
	};
	ice_default_pins: pinctrl-ice {
	mux {
	function = "ice";
	groups = "icegrp";
	};
	};
	uart_default_pins: pinctrl-uart {
	mux {
	function = "uart";
	groups = "uartrxtxgrp";
	};
	};
	pflash_default_pins: pinctrl-pflash {
	mux {
	function = "pflash";
	groups = "pflashgrp";
	};
	};
	usb_default_pins: pinctrl-usb {
	mux {
	function = "usb";
	groups = "usbgrp";
	};
	};
	gmii_default_pins: pinctrl-gmii {
	/*
	* Only activate GMAC0 by default since
	* GMAC1 will overlap with 8 GPIO lines
	* gpio2a, gpio2b. Overlay groups with
	* "gmii_gmac0_grp", "gmii_gmac1_grp" for
	* both ethernet interfaces.
	*/
	mux {
	function = "gmii";
	groups = "gmii_gmac0_grp";
	};
	};
	pci_default_pins: pinctrl-pci {
	mux {
	function = "pci";
	groups = "pcigrp";
	};
	};
	sata_default_pins: pinctrl-sata {
	mux {
	function = "sata";
	groups = "satagrp";
	};
	};
	/* Activate both groups of pins for this state */
	sata_and_ide_pins: pinctrl-sata-ide {
	mux0 {
	function = "sata";
	groups = "satagrp";
	};
	mux1 {
	function = "ide";
	groups = "idegrp";
	};
	};
	tvc_default_pins: pinctrl-tvc {
	mux {
	function = "tvc";
	groups = "tvcgrp";
	};
	};
	};
	};

	watchdog@41000000 {
	compatible = "cortina,gemini-watchdog", "faraday,ftwdt010";
	reg = <0x41000000 0x1000>;
	interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&syscon GEMINI_RESET_WDOG>;
	clocks = <&syscon GEMINI_CLK_APB>;
	clock-names = "PCLK";
	};

	uart0: serial@42000000 {
	compatible = "ns16550a";
	reg = <0x42000000 0x100>;
	resets = <&syscon GEMINI_RESET_UART>;
	clocks = <&syscon GEMINI_CLK_UART>;
	interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart_default_pins>;
	reg-shift = <2>;
	};

	timer@43000000 {
	compatible = "faraday,fttmr010";
	reg = <0x43000000 0x1000>;
	interrupt-parent = <&intcon>;
	interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
	<15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
	<16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
	resets = <&syscon GEMINI_RESET_TIMER>;
	/* APB clock or RTC clock */
	clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
	clock-names = "PCLK", "EXTCLK";
	syscon = <&syscon>;
	};

	rtc@45000000 {
	compatible = "cortina,gemini-rtc";
	reg = <0x45000000 0x100>;
	interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&syscon GEMINI_RESET_RTC>;
	clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
	clock-names = "PCLK", "EXTCLK";
	pinctrl-names = "default";
	pinctrl-0 = <&rtc_default_pins>;
	};

	sata: sata@46000000 {
	compatible = "cortina,gemini-sata-bridge";
	reg = <0x46000000 0x100>;
	resets = <&syscon GEMINI_RESET_SATA0>,
	<&syscon GEMINI_RESET_SATA1>;
	reset-names = "sata0", "sata1";
	clocks = <&syscon GEMINI_CLK_GATE_SATA0>,
	<&syscon GEMINI_CLK_GATE_SATA1>;
	clock-names = "SATA0_PCLK", "SATA1_PCLK";
	/*
	* This defines the special "ide" state that needs
	* to be explicitly enabled to enable the IDE pins,
	* as these pins are normally used for other things.
	*/
	pinctrl-names = "default", "ide";
	pinctrl-0 = <&sata_default_pins>;
	pinctrl-1 = <&sata_and_ide_pins>;
	syscon = <&syscon>;
	status = "disabled";
	};

	intcon: interrupt-controller@48000000 {
	compatible = "faraday,ftintc010";
	reg = <0x48000000 0x1000>;
	resets = <&syscon GEMINI_RESET_INTCON0>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	power-controller@4b000000 {
	compatible = "cortina,gemini-power-controller";
	reg = <0x4b000000 0x100>;
	interrupts = <26 IRQ_TYPE_EDGE_RISING>;
	pinctrl-names = "default";
	pinctrl-0 = <&power_default_pins>;
	};

	gpio0: gpio@4d000000 {
	compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
	reg = <0x4d000000 0x100>;
	interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&syscon GEMINI_RESET_GPIO0>;
	clocks = <&syscon GEMINI_CLK_APB>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio1: gpio@4e000000 {
	compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
	reg = <0x4e000000 0x100>;
	interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&syscon GEMINI_RESET_GPIO1>;
	clocks = <&syscon GEMINI_CLK_APB>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio@4f000000 {
	compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
	reg = <0x4f000000 0x100>;
	interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&syscon GEMINI_RESET_GPIO2>;
	clocks = <&syscon GEMINI_CLK_APB>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	pci@50000000 {
	compatible = "cortina,gemini-pci", "faraday,ftpci100";
	/*
	* The first 256 bytes in the IO range is actually used
	* to configure the host bridge.
	*/
	reg = <0x50000000 0x100>;
	resets = <&syscon GEMINI_RESET_PCI>;
	clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>;
	clock-names = "PCLK", "PCICLK";
	pinctrl-names = "default";
	pinctrl-0 = <&pci_default_pins>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	status = "disabled";

	bus-range = <0x00 0xff>;
	/* PCI ranges mappings */
	ranges =
	/* 1MiB I/O space 0x50000000-0x500fffff */
	<0x01000000 0 0 0x50000000 0 0x00100000>,
	/* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
	<0x02000000 0 0x58000000 0x58000000 0 0x08000000>;

	/* DMA ranges */
	dma-ranges =
	/* 128MiB at 0x00000000-0x07ffffff */
	<0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
	/* 64MiB at 0x00000000-0x03ffffff */
	<0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
	/* 64MiB at 0x00000000-0x03ffffff */
	<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;

	/*
	* This PCI host bridge variant has a cascaded interrupt
	* controller embedded in the host bridge.
	*/
	pci_intc: interrupt-controller {
	interrupt-parent = <&intcon>;
	interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#address-cells = <0>;
	#interrupt-cells = <1>;
	};
	};

	ethernet@60000000 {
	compatible = "cortina,gemini-ethernet";
	reg = <0x60000000 0x4000>, /* Global registers, queue */
	<0x60004000 0x2000>, /* V-bit */
	<0x60006000 0x2000>; /* A-bit */
	pinctrl-names = "default";
	pinctrl-0 = <&gmii_default_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	gmac0: ethernet-port@0 {
	compatible = "cortina,gemini-ethernet-port";
	reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
	<0x6000a000 0x2000>; /* Port 0 GMAC */
	interrupt-parent = <&intcon>;
	interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&syscon GEMINI_RESET_GMAC0>;
	clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
	clock-names = "PCLK";
	};

	gmac1: ethernet-port@1 {
	compatible = "cortina,gemini-ethernet-port";
	reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
	<0x6000e000 0x2000>; /* Port 1 GMAC */
	interrupt-parent = <&intcon>;
	interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&syscon GEMINI_RESET_GMAC1>;
	clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
	clock-names = "PCLK";
	};
	};

	- ata@63000000 {
	+ ide@63000000 {
	compatible = "cortina,gemini-pata", "faraday,ftide010";
	reg = <0x63000000 0x1000>;
	interrupts = <4 IRQ_TYPE_EDGE_RISING>;
	resets = <&syscon GEMINI_RESET_IDE>;
	clocks = <&syscon GEMINI_CLK_GATE_IDE>;
	clock-names = "PCLK";
	sata = <&sata>;
	status = "disabled";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	};

	- ata@63400000 {
	+ ide@63400000 {
	compatible = "cortina,gemini-pata", "faraday,ftide010";
	reg = <0x63400000 0x1000>;
	interrupts = <5 IRQ_TYPE_EDGE_RISING>;
	resets = <&syscon GEMINI_RESET_IDE>;
	clocks = <&syscon GEMINI_CLK_GATE_IDE>;
	clock-names = "PCLK";
	sata = <&sata>;
	status = "disabled";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	};

	dma-controller@67000000 {
	compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
	/* Faraday Technology FTDMAC020 variant */
	arm,primecell-periphid = <0x0003b080>;
	reg = <0x67000000 0x1000>;
	interrupts = <9 IRQ_TYPE_EDGE_RISING>;
	resets = <&syscon GEMINI_RESET_DMAC>;
	clocks = <&syscon GEMINI_CLK_AHB>;
	clock-names = "apb_pclk";
	/* Bus interface AHB1 (AHB0) is totally tilted */
	lli-bus-interface-ahb2;
	mem-bus-interface-ahb2;
	memcpy-burst-size = <256>;
	memcpy-bus-width = <32>;
	#dma-cells = <2>;
	};

	display-controller@6a000000 {
	compatible = "cortina,gemini-tvc", "faraday,tve200";
	reg = <0x6a000000 0x1000>;
	interrupts = <13 IRQ_TYPE_EDGE_RISING>;
	resets = <&syscon GEMINI_RESET_TVC>;
	clocks = <&syscon GEMINI_CLK_GATE_TVC>,
	<&syscon GEMINI_CLK_TVC>;
	clock-names = "PCLK", "TVE";
	pinctrl-names = "default";
	pinctrl-0 = <&tvc_default_pins>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	usb@68000000 {
	compatible = "cortina,gemini-usb", "faraday,fotg210";
	reg = <0x68000000 0x1000>;
	interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&syscon GEMINI_RESET_USB0>;
	clocks = <&syscon GEMINI_CLK_GATE_USB0>;
	clock-names = "PCLK";
	/*
	* This will claim pins for USB0 and USB1 at the same
	* time as they are using some common pins. If you for
	* some reason have a system using USB1 at 96000000 but
	* NOT using USB0 at 68000000 you wll have to add the
	* usb_default_pins to the USB controller at 96000000
	* in your .dts for the board.
	*/
	pinctrl-names = "default";
	pinctrl-0 = <&usb_default_pins>;
	syscon = <&syscon>;
	status = "disabled";
	};

	usb@69000000 {
	compatible = "cortina,gemini-usb", "faraday,fotg210";
	reg = <0x69000000 0x1000>;
	interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&syscon GEMINI_RESET_USB1>;
	clocks = <&syscon GEMINI_CLK_GATE_USB1>;
	clock-names = "PCLK";
	syscon = <&syscon>;
	status = "disabled";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/highbank.dts b/sys/gnu/dts/arm/highbank.dts
	index f4e4dca6f7e7..b6b0225a769e 100644
	--- a/sys/gnu/dts/arm/highbank.dts
	+++ b/sys/gnu/dts/arm/highbank.dts
	@@ -1,161 +1,158 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright 2011-2012 Calxeda, Inc.
	*/

	/dts-v1/;

	/* First 4KB has pen for secondary cores. */
	/memreserve/ 0x00000000 0x0001000;

	/ {
	model = "Calxeda Highbank";
	compatible = "calxeda,highbank";
	#address-cells = <1>;
	#size-cells = <1>;
	- clock-ranges;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@900 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <0x900>;
	next-level-cache = <&L2>;
	clocks = <&a9pll>;
	clock-names = "cpu";
	operating-points = <
	/* kHz ignored */
	1300000 1000000
	1200000 1000000
	1100000 1000000
	800000 1000000
	400000 1000000
	200000 1000000
	>;
	clock-latency = <100000>;
	};

	cpu@901 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <0x901>;
	next-level-cache = <&L2>;
	clocks = <&a9pll>;
	clock-names = "cpu";
	operating-points = <
	/* kHz ignored */
	1300000 1000000
	1200000 1000000
	1100000 1000000
	800000 1000000
	400000 1000000
	200000 1000000
	>;
	clock-latency = <100000>;
	};

	cpu@902 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <0x902>;
	next-level-cache = <&L2>;
	clocks = <&a9pll>;
	clock-names = "cpu";
	operating-points = <
	/* kHz ignored */
	1300000 1000000
	1200000 1000000
	1100000 1000000
	800000 1000000
	400000 1000000
	200000 1000000
	>;
	clock-latency = <100000>;
	};

	cpu@903 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <0x903>;
	next-level-cache = <&L2>;
	clocks = <&a9pll>;
	clock-names = "cpu";
	operating-points = <
	/* kHz ignored */
	1300000 1000000
	1200000 1000000
	1100000 1000000
	800000 1000000
	400000 1000000
	200000 1000000
	>;
	clock-latency = <100000>;
	};
	};

	- memory {
	+ memory@0 {
	name = "memory";
	device_type = "memory";
	reg = <0x00000000 0xff900000>;
	};

	soc {
	ranges = <0x00000000 0x00000000 0xffffffff>;

	memory-controller@fff00000 {
	compatible = "calxeda,hb-ddr-ctrl";
	reg = <0xfff00000 0x1000>;
	interrupts = <0 91 4>;
	};

	timer@fff10600 {
	compatible = "arm,cortex-a9-twd-timer";
	reg = <0xfff10600 0x20>;
	interrupts = <1 13 0xf01>;
	clocks = <&a9periphclk>;
	};

	watchdog@fff10620 {
	compatible = "arm,cortex-a9-twd-wdt";
	reg = <0xfff10620 0x20>;
	interrupts = <1 14 0xf01>;
	clocks = <&a9periphclk>;
	};

	intc: interrupt-controller@fff11000 {
	compatible = "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	- #size-cells = <0>;
	- #address-cells = <1>;
	interrupt-controller;
	reg = <0xfff11000 0x1000>,
	<0xfff10100 0x100>;
	};

	- L2: l2-cache {
	+ L2: cache-controller {
	compatible = "arm,pl310-cache";
	reg = <0xfff12000 0x1000>;
	interrupts = <0 70 4>;
	cache-unified;
	cache-level = <2>;
	};

	pmu {
	compatible = "arm,cortex-a9-pmu";
	- interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
	+ interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>;
	};


	sregs@fff3c200 {
	compatible = "calxeda,hb-sregs-l2-ecc";
	reg = <0xfff3c200 0x100>;
	- interrupts = <0 71 4 0 72 4>;
	+ interrupts = <0 71 4>, <0 72 4>;
	};

	};
	};

	/include/ "ecx-common.dtsi"
	diff --git a/sys/gnu/dts/arm/imx23-olinuxino.dts b/sys/gnu/dts/arm/imx23-olinuxino.dts
	index 4c9aafe00b5d..0729e72f2283 100644
	--- a/sys/gnu/dts/arm/imx23-olinuxino.dts
	+++ b/sys/gnu/dts/arm/imx23-olinuxino.dts
	@@ -1,131 +1,131 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	/*
	* Copyright 2012 Freescale Semiconductor, Inc.
	*
	* Author: Fabio Estevam <fabio.estevam@freescale.com>
	*/

	/dts-v1/;
	#include <dt-bindings/gpio/gpio.h>
	#include "imx23.dtsi"

	/ {
	model = "i.MX23 Olinuxino Low Cost Board";
	compatible = "olimex,imx23-olinuxino", "fsl,imx23";

	memory@40000000 {
	device_type = "memory";
	reg = <0x40000000 0x04000000>;
	};

	apb@80000000 {
	apbh@80000000 {
	ssp0: spi@80010000 {
	compatible = "fsl,imx23-mmc";
	pinctrl-names = "default";
	- pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
	+ pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
	bus-width = <4>;
	broken-cd;
	status = "okay";
	};

	pinctrl@80018000 {
	pinctrl-names = "default";
	pinctrl-0 = <&hog_pins_a>;

	hog_pins_a: hog@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX23_PAD_GPMI_ALE__GPIO_0_17
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	led_pin_gpio2_1: led_gpio2_1@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX23_PAD_SSP1_DETECT__GPIO_2_1
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};
	};

	ssp1: spi@80034000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx23-spi";
	pinctrl-names = "default";
	pinctrl-0 = <&spi2_pins_a>;
	status = "okay";
	};
	};

	apbx@80040000 {
	lradc@80050000 {
	status = "okay";
	};

	i2c: i2c@80058000 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c_pins_b>;
	status = "okay";
	};

	duart: serial@80070000 {
	pinctrl-names = "default";
	pinctrl-0 = <&duart_pins_a>;
	status = "okay";
	};

	auart0: serial@8006c000 {
	pinctrl-names = "default";
	pinctrl-0 = <&auart0_2pins_a>;
	status = "okay";
	};

	usbphy0: usbphy@8007c000 {
	status = "okay";
	};
	};
	};

	ahb@80080000 {
	usb0: usb@80080000 {
	dr_mode = "host";
	vbus-supply = <&reg_usb0_vbus>;
	status = "okay";
	};
	};

	regulators {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	reg_usb0_vbus: regulator@0 {
	compatible = "regulator-fixed";
	reg = <0>;
	regulator-name = "usb0_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	enable-active-high;
	startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */
	gpio = <&gpio0 17 0>;
	};
	};

	leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&led_pin_gpio2_1>;

	user {
	label = "green";
	gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx23.dtsi b/sys/gnu/dts/arm/imx23.dtsi
	index 8257630f7a49..c5edff381213 100644
	--- a/sys/gnu/dts/arm/imx23.dtsi
	+++ b/sys/gnu/dts/arm/imx23.dtsi
	@@ -1,628 +1,636 @@
	// SPDX-License-Identifier: GPL-2.0+
	//
	// Copyright 2012 Freescale Semiconductor, Inc.

	#include "imx23-pinfunc.h"

	/ {
	#address-cells = <1>;
	#size-cells = <1>;

	interrupt-parent = <&icoll>;
	/*
	* The decompressor and also some bootloaders rely on a
	* pre-existing /chosen node to be available to insert the
	* command line and merge other ATAGS info.
	*/
	chosen {};

	aliases {
	gpio0 = &gpio0;
	gpio1 = &gpio1;
	gpio2 = &gpio2;
	serial0 = &auart0;
	serial1 = &auart1;
	spi0 = &ssp0;
	spi1 = &ssp1;
	usbphy0 = &usbphy0;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	compatible = "arm,arm926ej-s";
	device_type = "cpu";
	reg = <0>;
	};
	};

	apb@80000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x80000000 0x80000>;
	ranges;

	apbh@80000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x80000000 0x40000>;
	ranges;

	icoll: interrupt-controller@80000000 {
	compatible = "fsl,imx23-icoll", "fsl,icoll";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x80000000 0x2000>;
	};

	dma_apbh: dma-apbh@80004000 {
	compatible = "fsl,imx23-dma-apbh";
	reg = <0x80004000 0x2000>;
	interrupts = <0 14 20 0
	13 13 13 13>;
	interrupt-names = "empty", "ssp0", "ssp1", "empty",
	"gpmi0", "gpmi1", "gpmi2", "gpmi3";
	#dma-cells = <1>;
	dma-channels = <8>;
	clocks = <&clks 15>;
	};

	ecc@80008000 {
	reg = <0x80008000 0x2000>;
	status = "disabled";
	};

	gpmi-nand@8000c000 {
	compatible = "fsl,imx23-gpmi-nand";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
	reg-names = "gpmi-nand", "bch";
	interrupts = <56>;
	interrupt-names = "bch";
	clocks = <&clks 34>;
	clock-names = "gpmi_io";
	dmas = <&dma_apbh 4>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	ssp0: spi@80010000 {
	reg = <0x80010000 0x2000>;
	interrupts = <15>;
	clocks = <&clks 33>;
	dmas = <&dma_apbh 1>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	etm@80014000 {
	reg = <0x80014000 0x2000>;
	status = "disabled";
	};

	pinctrl@80018000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx23-pinctrl", "simple-bus";
	reg = <0x80018000 0x2000>;

	gpio0: gpio@0 {
	compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
	reg = <0>;
	interrupts = <16>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio1: gpio@1 {
	compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
	reg = <1>;
	interrupts = <17>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio@2 {
	compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
	reg = <2>;
	interrupts = <18>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	duart_pins_a: duart@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX23_PAD_PWM0__DUART_RX
	MX23_PAD_PWM1__DUART_TX
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	auart0_pins_a: auart0@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX23_PAD_AUART1_RX__AUART1_RX
	MX23_PAD_AUART1_TX__AUART1_TX
	MX23_PAD_AUART1_CTS__AUART1_CTS
	MX23_PAD_AUART1_RTS__AUART1_RTS
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	auart0_2pins_a: auart0-2pins@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX23_PAD_I2C_SCL__AUART1_TX
	MX23_PAD_I2C_SDA__AUART1_RX
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	auart1_2pins_a: auart1-2pins@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX23_PAD_GPMI_D14__AUART2_RX
	MX23_PAD_GPMI_D15__AUART2_TX
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	gpmi_pins_a: gpmi-nand@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX23_PAD_GPMI_D00__GPMI_D00
	MX23_PAD_GPMI_D01__GPMI_D01
	MX23_PAD_GPMI_D02__GPMI_D02
	MX23_PAD_GPMI_D03__GPMI_D03
	MX23_PAD_GPMI_D04__GPMI_D04
	MX23_PAD_GPMI_D05__GPMI_D05
	MX23_PAD_GPMI_D06__GPMI_D06
	MX23_PAD_GPMI_D07__GPMI_D07
	MX23_PAD_GPMI_CLE__GPMI_CLE
	MX23_PAD_GPMI_ALE__GPMI_ALE
	MX23_PAD_GPMI_RDY0__GPMI_RDY0
	MX23_PAD_GPMI_RDY1__GPMI_RDY1
	MX23_PAD_GPMI_WPN__GPMI_WPN
	MX23_PAD_GPMI_WRN__GPMI_WRN
	MX23_PAD_GPMI_RDN__GPMI_RDN
	MX23_PAD_GPMI_CE1N__GPMI_CE1N
	MX23_PAD_GPMI_CE0N__GPMI_CE0N
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	gpmi_pins_fixup: gpmi-pins-fixup@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX23_PAD_GPMI_WPN__GPMI_WPN
	MX23_PAD_GPMI_WRN__GPMI_WRN
	MX23_PAD_GPMI_RDN__GPMI_RDN
	>;
	fsl,drive-strength = <MXS_DRIVE_12mA>;
	};

	mmc0_4bit_pins_a: mmc0-4bit@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX23_PAD_SSP1_DATA0__SSP1_DATA0
	MX23_PAD_SSP1_DATA1__SSP1_DATA1
	MX23_PAD_SSP1_DATA2__SSP1_DATA2
	MX23_PAD_SSP1_DATA3__SSP1_DATA3
	MX23_PAD_SSP1_CMD__SSP1_CMD
	MX23_PAD_SSP1_SCK__SSP1_SCK
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	mmc0_8bit_pins_a: mmc0-8bit@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX23_PAD_SSP1_DATA0__SSP1_DATA0
	MX23_PAD_SSP1_DATA1__SSP1_DATA1
	MX23_PAD_SSP1_DATA2__SSP1_DATA2
	MX23_PAD_SSP1_DATA3__SSP1_DATA3
	MX23_PAD_GPMI_D08__SSP1_DATA4
	MX23_PAD_GPMI_D09__SSP1_DATA5
	MX23_PAD_GPMI_D10__SSP1_DATA6
	MX23_PAD_GPMI_D11__SSP1_DATA7
	MX23_PAD_SSP1_CMD__SSP1_CMD
	MX23_PAD_SSP1_DETECT__SSP1_DETECT
	MX23_PAD_SSP1_SCK__SSP1_SCK
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	mmc0_pins_fixup: mmc0-pins-fixup@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX23_PAD_SSP1_DETECT__SSP1_DETECT
	MX23_PAD_SSP1_SCK__SSP1_SCK
	>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	+ mmc0_sck_cfg: mmc0-sck-cfg@0 {
	+ reg = <0>;
	+ fsl,pinmux-ids = <
	+ MX23_PAD_SSP1_SCK__SSP1_SCK
	+ >;
	+ fsl,pull-up = <MXS_PULL_DISABLE>;
	+ };
	+
	mmc1_4bit_pins_a: mmc1-4bit@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX23_PAD_GPMI_D00__SSP2_DATA0
	MX23_PAD_GPMI_D01__SSP2_DATA1
	MX23_PAD_GPMI_D02__SSP2_DATA2
	MX23_PAD_GPMI_D03__SSP2_DATA3
	MX23_PAD_GPMI_RDY1__SSP2_CMD
	MX23_PAD_GPMI_WRN__SSP2_SCK
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	mmc1_8bit_pins_a: mmc1-8bit@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX23_PAD_GPMI_D00__SSP2_DATA0
	MX23_PAD_GPMI_D01__SSP2_DATA1
	MX23_PAD_GPMI_D02__SSP2_DATA2
	MX23_PAD_GPMI_D03__SSP2_DATA3
	MX23_PAD_GPMI_D04__SSP2_DATA4
	MX23_PAD_GPMI_D05__SSP2_DATA5
	MX23_PAD_GPMI_D06__SSP2_DATA6
	MX23_PAD_GPMI_D07__SSP2_DATA7
	MX23_PAD_GPMI_RDY1__SSP2_CMD
	MX23_PAD_GPMI_WRN__SSP2_SCK
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	pwm2_pins_a: pwm2@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX23_PAD_PWM2__PWM2
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	lcdif_24bit_pins_a: lcdif-24bit@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX23_PAD_LCD_D00__LCD_D00
	MX23_PAD_LCD_D01__LCD_D01
	MX23_PAD_LCD_D02__LCD_D02
	MX23_PAD_LCD_D03__LCD_D03
	MX23_PAD_LCD_D04__LCD_D04
	MX23_PAD_LCD_D05__LCD_D05
	MX23_PAD_LCD_D06__LCD_D06
	MX23_PAD_LCD_D07__LCD_D07
	MX23_PAD_LCD_D08__LCD_D08
	MX23_PAD_LCD_D09__LCD_D09
	MX23_PAD_LCD_D10__LCD_D10
	MX23_PAD_LCD_D11__LCD_D11
	MX23_PAD_LCD_D12__LCD_D12
	MX23_PAD_LCD_D13__LCD_D13
	MX23_PAD_LCD_D14__LCD_D14
	MX23_PAD_LCD_D15__LCD_D15
	MX23_PAD_LCD_D16__LCD_D16
	MX23_PAD_LCD_D17__LCD_D17
	MX23_PAD_GPMI_D08__LCD_D18
	MX23_PAD_GPMI_D09__LCD_D19
	MX23_PAD_GPMI_D10__LCD_D20
	MX23_PAD_GPMI_D11__LCD_D21
	MX23_PAD_GPMI_D12__LCD_D22
	MX23_PAD_GPMI_D13__LCD_D23
	MX23_PAD_LCD_DOTCK__LCD_DOTCK
	MX23_PAD_LCD_ENABLE__LCD_ENABLE
	MX23_PAD_LCD_HSYNC__LCD_HSYNC
	MX23_PAD_LCD_VSYNC__LCD_VSYNC
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	spi2_pins_a: spi2@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX23_PAD_GPMI_WRN__SSP2_SCK
	MX23_PAD_GPMI_RDY1__SSP2_CMD
	MX23_PAD_GPMI_D00__SSP2_DATA0
	MX23_PAD_GPMI_D03__SSP2_DATA3
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	i2c_pins_a: i2c@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX23_PAD_I2C_SCL__I2C_SCL
	MX23_PAD_I2C_SDA__I2C_SDA
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	i2c_pins_b: i2c@1 {
	reg = <1>;
	fsl,pinmux-ids = <
	MX23_PAD_LCD_ENABLE__I2C_SCL
	MX23_PAD_LCD_HSYNC__I2C_SDA
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	i2c_pins_c: i2c@2 {
	reg = <2>;
	fsl,pinmux-ids = <
	MX23_PAD_SSP1_DATA1__I2C_SCL
	MX23_PAD_SSP1_DATA2__I2C_SDA
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};
	};

	digctl@8001c000 {
	compatible = "fsl,imx23-digctl";
	reg = <0x8001c000 2000>;
	status = "disabled";
	};

	emi@80020000 {
	reg = <0x80020000 0x2000>;
	status = "disabled";
	};

	dma_apbx: dma-apbx@80024000 {
	compatible = "fsl,imx23-dma-apbx";
	reg = <0x80024000 0x2000>;
	interrupts = <7 5 9 26
	19 0 25 23
	60 58 9 0
	0 0 0 0>;
	interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
	"saif0", "empty", "auart0-rx", "auart0-tx",
	"auart1-rx", "auart1-tx", "saif1", "empty",
	"empty", "empty", "empty", "empty";
	#dma-cells = <1>;
	dma-channels = <16>;
	clocks = <&clks 16>;
	};

	- dcp@80028000 {
	+ dcp: crypto@80028000 {
	compatible = "fsl,imx23-dcp";
	reg = <0x80028000 0x2000>;
	interrupts = <53 54>;
	status = "okay";
	};

	pxp@8002a000 {
	reg = <0x8002a000 0x2000>;
	status = "disabled";
	};

	ocotp@8002c000 {
	compatible = "fsl,imx23-ocotp", "fsl,ocotp";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x8002c000 0x2000>;
	clocks = <&clks 15>;
	};

	axi-ahb@8002e000 {
	reg = <0x8002e000 0x2000>;
	status = "disabled";
	};

	lcdif@80030000 {
	compatible = "fsl,imx23-lcdif";
	reg = <0x80030000 2000>;
	interrupts = <46 45>;
	clocks = <&clks 38>;
	status = "disabled";
	};

	ssp1: spi@80034000 {
	reg = <0x80034000 0x2000>;
	interrupts = <2>;
	clocks = <&clks 33>;
	dmas = <&dma_apbh 2>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	tvenc@80038000 {
	reg = <0x80038000 0x2000>;
	status = "disabled";
	};
	};

	apbx@80040000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x80040000 0x40000>;
	ranges;

	clks: clkctrl@80040000 {
	compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
	reg = <0x80040000 0x2000>;
	#clock-cells = <1>;
	};

	saif0: saif@80042000 {
	reg = <0x80042000 0x2000>;
	dmas = <&dma_apbx 4>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	power@80044000 {
	reg = <0x80044000 0x2000>;
	status = "disabled";
	};

	saif1: saif@80046000 {
	reg = <0x80046000 0x2000>;
	dmas = <&dma_apbx 10>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	audio-out@80048000 {
	reg = <0x80048000 0x2000>;
	dmas = <&dma_apbx 1>;
	dma-names = "tx";
	status = "disabled";
	};

	audio-in@8004c000 {
	reg = <0x8004c000 0x2000>;
	dmas = <&dma_apbx 0>;
	dma-names = "rx";
	status = "disabled";
	};

	lradc: lradc@80050000 {
	compatible = "fsl,imx23-lradc";
	reg = <0x80050000 0x2000>;
	interrupts = <36 37 38 39 40 41 42 43 44>;
	status = "disabled";
	clocks = <&clks 26>;
	#io-channel-cells = <1>;
	};

	spdif@80054000 {
	reg = <0x80054000 2000>;
	dmas = <&dma_apbx 2>;
	dma-names = "tx";
	status = "disabled";
	};

	i2c: i2c@80058000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx23-i2c";
	reg = <0x80058000 0x2000>;
	interrupts = <27>;
	clock-frequency = <100000>;
	dmas = <&dma_apbx 3>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	rtc@8005c000 {
	compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
	reg = <0x8005c000 0x2000>;
	interrupts = <22>;
	};

	pwm: pwm@80064000 {
	compatible = "fsl,imx23-pwm";
	reg = <0x80064000 0x2000>;
	clocks = <&clks 30>;
	#pwm-cells = <2>;
	fsl,pwm-number = <5>;
	status = "disabled";
	};

	timrot@80068000 {
	compatible = "fsl,imx23-timrot", "fsl,timrot";
	reg = <0x80068000 0x2000>;
	interrupts = <28 29 30 31>;
	clocks = <&clks 28>;
	};

	auart0: serial@8006c000 {
	compatible = "fsl,imx23-auart";
	reg = <0x8006c000 0x2000>;
	interrupts = <24>;
	clocks = <&clks 32>;
	dmas = <&dma_apbx 6>, <&dma_apbx 7>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	auart1: serial@8006e000 {
	compatible = "fsl,imx23-auart";
	reg = <0x8006e000 0x2000>;
	interrupts = <59>;
	clocks = <&clks 32>;
	dmas = <&dma_apbx 8>, <&dma_apbx 9>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	duart: serial@80070000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x80070000 0x2000>;
	interrupts = <0>;
	clocks = <&clks 32>, <&clks 16>;
	clock-names = "uart", "apb_pclk";
	status = "disabled";
	};

	usbphy0: usbphy@8007c000 {
	compatible = "fsl,imx23-usbphy";
	reg = <0x8007c000 0x2000>;
	clocks = <&clks 41>;
	status = "disabled";
	};
	};
	};

	ahb@80080000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x80080000 0x80000>;
	ranges;

	usb0: usb@80080000 {
	compatible = "fsl,imx23-usb", "fsl,imx27-usb";
	reg = <0x80080000 0x40000>;
	interrupts = <11>;
	fsl,usbphy = <&usbphy0>;
	clocks = <&clks 40>;
	status = "disabled";
	};
	};

	iio-hwmon {
	compatible = "iio-hwmon";
	io-channels = <&lradc 8>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx25-pinfunc.h b/sys/gnu/dts/arm/imx25-pinfunc.h
	index f4516ccf2c1a..111bfdcbe552 100644
	--- a/sys/gnu/dts/arm/imx25-pinfunc.h
	+++ b/sys/gnu/dts/arm/imx25-pinfunc.h
	@@ -1,628 +1,636 @@
	/* SPDX-License-Identifier: GPL-2.0-only */
	/*
	* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
	* Based on imx35-pinfunc.h in the same directory Which is:
	* Copyright 2013 Freescale Semiconductor, Inc.
	*/

	#ifndef __DTS_IMX25_PINFUNC_H
	#define __DTS_IMX25_PINFUNC_H

	/*
	* The pin function ID is a tuple of
	* <mux_reg conf_reg input_reg mux_mode input_val>
	*/

	#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
	#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000

	#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
	#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
	#define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000

	#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
	#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
	#define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
	#define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000

	#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
	#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x05 0x000
	#define MX25_PAD_A15__SIM1_RST1 0x014 0x234 0x000 0x06 0x000
	#define MX25_PAD_A15__LCDC_PS 0x014 0x234 0x000 0x07 0x000

	#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x00 0x000
	#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x05 0x000
	#define MX25_PAD_A16__SIM1_VEN1 0x018 0x000 0x000 0x06 0x000
	#define MX25_PAD_A16__LCDC_REV 0x018 0x000 0x000 0x07 0x000

	#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x00 0x000
	#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x05 0x000
	#define MX25_PAD_A17__SIM1_TX 0x01c 0x238 0x554 0x06 0x000
	#define MX25_PAD_A17__FEC_TX_ERR 0x01c 0x238 0x000 0x07 0x000

	#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x00 0x000
	#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x05 0x000
	#define MX25_PAD_A18__SIM1_PD1 0x020 0x23c 0x550 0x06 0x000
	#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x07 0x000

	#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x00 0x000
	#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x05 0x000
	#define MX25_PAD_A19__SIM1_RX1 0x024 0x240 0x54c 0x06 0x000
	#define MX25_PAD_A19__FEC_RX_ERR 0x024 0x240 0x518 0x07 0x000

	#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x00 0x000
	#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x05 0x000
	#define MX25_PAD_A20__SIM2_CLK1 0x028 0x244 0x000 0x06 0x000
	#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x07 0x000

	#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x00 0x000
	#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x05 0x000
	#define MX25_PAD_A21__SIM2_RST1 0x02c 0x248 0x000 0x06 0x000
	#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x07 0x000

	#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x00 0x000
	#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x05 0x000
	#define MX25_PAD_A22__SIM2_VEN1 0x030 0x000 0x000 0x06 0x000
	#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x07 0x000

	#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x00 0x000
	#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x05 0x000
	#define MX25_PAD_A23__SIM2_TX1 0x034 0x24c 0x560 0x06 0x000
	#define MX25_PAD_A23__FEC_TDATA3 0x034 0x24c 0x000 0x07 0x000

	#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x00 0x000
	#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x05 0x000
	#define MX25_PAD_A24__SIM2_PD1 0x038 0x250 0x55c 0x06 0x000
	#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x07 0x000

	#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x00 0x000
	#define MX25_PAD_A25__GPIO_2_11 0x03c 0x254 0x000 0x05 0x000
	#define MX25_PAD_A25__FEC_CRS 0x03c 0x254 0x508 0x07 0x000

	#define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x00 0x000
	#define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x04 0x000
	#define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x05 0x000
	+#define MX25_PAD_EB0__CSPI3_SS0 0x040 0x258 0x4bc 0x06 0x000

	#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x00 0x000
	#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x04 0x000
	#define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x05 0x000

	#define MX25_PAD_OE__OE 0x048 0x260 0x000 0x00 0x000
	#define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x04 0x000
	#define MX25_PAD_OE__GPIO_2_14 0x048 0x260 0x000 0x05 0x000

	#define MX25_PAD_CS0__CS0 0x04c 0x000 0x000 0x00 0x000
	#define MX25_PAD_CS0__GPIO_4_2 0x04c 0x000 0x000 0x05 0x000

	#define MX25_PAD_CS1__CS1 0x050 0x000 0x000 0x00 0x000
	#define MX25_PAD_CS1__NF_CE3 0x050 0x000 0x000 0x01 0x000
	#define MX25_PAD_CS1__GPIO_4_3 0x050 0x000 0x000 0x05 0x000

	#define MX25_PAD_CS4__CS4 0x054 0x264 0x000 0x00 0x000
	#define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000
	#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x03 0x000
	#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x05 0x000
	+#define MX25_PAD_CS4__CSPI3_MOSI 0x054 0x264 0x4b8 0x06 0x000

	#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x00 0x000
	#define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000
	#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x03 0x000
	#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x05 0x000
	+#define MX25_PAD_CS5__CSPI3_MISO 0x058 0x268 0x4b4 0x06 0x000

	#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x00 0x000
	#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x05 0x000

	#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x00 0x000
	#define MX25_PAD_ECB__UART5_TXD 0x060 0x270 0x000 0x03 0x000
	#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x05 0x000
	+#define MX25_PAD_ECB__CSPI3_SCLK 0x060 0x270 0x4ac 0x06 0x000

	#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x00 0x000
	#define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x03 0x000
	#define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x05 0x000

	#define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000
	#define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000

	#define MX25_PAD_RW__RW 0x06c 0x278 0x000 0x00 0x000
	#define MX25_PAD_RW__AUD4_TXFS 0x06c 0x278 0x474 0x04 0x000
	#define MX25_PAD_RW__GPIO_3_25 0x06c 0x278 0x000 0x05 0x000

	#define MX25_PAD_NFWE_B__NFWE_B 0x070 0x000 0x000 0x00 0x000
	#define MX25_PAD_NFWE_B__GPIO_3_26 0x070 0x000 0x000 0x05 0x000

	#define MX25_PAD_NFRE_B__NFRE_B 0x074 0x000 0x000 0x00 0x000
	#define MX25_PAD_NFRE_B__GPIO_3_27 0x074 0x000 0x000 0x05 0x000

	#define MX25_PAD_NFALE__NFALE 0x078 0x000 0x000 0x00 0x000
	#define MX25_PAD_NFALE__GPIO_3_28 0x078 0x000 0x000 0x05 0x000

	#define MX25_PAD_NFCLE__NFCLE 0x07c 0x000 0x000 0x00 0x000
	#define MX25_PAD_NFCLE__GPIO_3_29 0x07c 0x000 0x000 0x05 0x000

	#define MX25_PAD_NFWP_B__NFWP_B 0x080 0x000 0x000 0x00 0x000
	#define MX25_PAD_NFWP_B__GPIO_3_30 0x080 0x000 0x000 0x05 0x000

	#define MX25_PAD_NFRB__NFRB 0x084 0x27c 0x000 0x00 0x000
	#define MX25_PAD_NFRB__GPIO_3_31 0x084 0x27c 0x000 0x05 0x000

	#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000
	#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000
	#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000
	#define MX25_PAD_D15__ESDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000

	#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000
	#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000
	#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000
	#define MX25_PAD_D14__ESDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000

	#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000
	#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000
	#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000
	#define MX25_PAD_D13__ESDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000

	#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000
	#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000
	#define MX25_PAD_D12__ESDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000

	#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000
	#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000
	#define MX25_PAD_D11__USBOTG_PWR 0x098 0x290 0x000 0x06 0x000

	#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000
	#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000
	#define MX25_PAD_D10__USBOTG_OC 0x09c 0x294 0x57c 0x06 0x000

	#define MX25_PAD_D9__D9 0x0a0 0x298 0x000 0x00 0x000
	#define MX25_PAD_D9__GPIO_4_11 0x0a0 0x298 0x000 0x05 0x000
	#define MX25_PAD_D9__USBH2_PWR 0x0a0 0x298 0x000 0x06 0x000

	#define MX25_PAD_D8__D8 0x0a4 0x29c 0x000 0x00 0x000
	#define MX25_PAD_D8__GPIO_4_12 0x0a4 0x29c 0x000 0x05 0x000
	#define MX25_PAD_D8__USBH2_OC 0x0a4 0x29c 0x580 0x06 0x000

	#define MX25_PAD_D7__D7 0x0a8 0x2a0 0x000 0x00 0x000
	#define MX25_PAD_D7__GPIO_4_13 0x0a8 0x2a0 0x000 0x05 0x000

	#define MX25_PAD_D6__D6 0x0ac 0x2a4 0x000 0x00 0x000
	#define MX25_PAD_D6__GPIO_4_14 0x0ac 0x2a4 0x000 0x05 0x000

	#define MX25_PAD_D5__D5 0x0b0 0x2a8 0x000 0x00 0x000
	#define MX25_PAD_D5__GPIO_4_15 0x0b0 0x2a8 0x000 0x05 0x000

	#define MX25_PAD_D4__D4 0x0b4 0x2ac 0x000 0x00 0x000
	#define MX25_PAD_D4__GPIO_4_16 0x0b4 0x2ac 0x000 0x05 0x000

	#define MX25_PAD_D3__D3 0x0b8 0x2b0 0x000 0x00 0x000
	#define MX25_PAD_D3__GPIO_4_17 0x0b8 0x2b0 0x000 0x05 0x000

	#define MX25_PAD_D2__D2 0x0bc 0x2b4 0x000 0x00 0x000
	#define MX25_PAD_D2__GPIO_4_18 0x0bc 0x2b4 0x000 0x05 0x000

	#define MX25_PAD_D1__D1 0x0c0 0x2b8 0x000 0x00 0x000
	#define MX25_PAD_D1__GPIO_4_19 0x0c0 0x2b8 0x000 0x05 0x000

	#define MX25_PAD_D0__D0 0x0c4 0x2bc 0x000 0x00 0x000
	#define MX25_PAD_D0__GPIO_4_20 0x0c4 0x2bc 0x000 0x05 0x000

	#define MX25_PAD_LD0__LD0 0x0c8 0x2c0 0x000 0x00 0x000
	#define MX25_PAD_LD0__CSI_D0 0x0c8 0x2c0 0x488 0x02 0x000
	#define MX25_PAD_LD0__GPIO_2_15 0x0c8 0x2c0 0x000 0x05 0x000

	#define MX25_PAD_LD1__LD1 0x0cc 0x2c4 0x000 0x00 0x000
	#define MX25_PAD_LD1__CSI_D1 0x0cc 0x2c4 0x48c 0x02 0x000
	#define MX25_PAD_LD1__GPIO_2_16 0x0cc 0x2c4 0x000 0x05 0x000

	#define MX25_PAD_LD2__LD2 0x0d0 0x2c8 0x000 0x00 0x000
	#define MX25_PAD_LD2__GPIO_2_17 0x0d0 0x2c8 0x000 0x05 0x000

	#define MX25_PAD_LD3__LD3 0x0d4 0x2cc 0x000 0x00 0x000
	#define MX25_PAD_LD3__GPIO_2_18 0x0d4 0x2cc 0x000 0x05 0x000

	#define MX25_PAD_LD4__LD4 0x0d8 0x2d0 0x000 0x00 0x000
	#define MX25_PAD_LD4__GPIO_2_19 0x0d8 0x2d0 0x000 0x05 0x000

	#define MX25_PAD_LD5__LD5 0x0dc 0x2d4 0x000 0x00 0x000
	#define MX25_PAD_LD5__GPIO_1_19 0x0dc 0x2d4 0x000 0x05 0x000

	#define MX25_PAD_LD6__LD6 0x0e0 0x2d8 0x000 0x00 0x000
	#define MX25_PAD_LD6__GPIO_1_20 0x0e0 0x2d8 0x000 0x05 0x000

	#define MX25_PAD_LD7__LD7 0x0e4 0x2dc 0x000 0x00 0x000
	#define MX25_PAD_LD7__GPIO_1_21 0x0e4 0x2dc 0x000 0x05 0x000

	#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x00 0x000
	#define MX25_PAD_LD8__UART4_RXD 0x0e8 0x2e0 0x570 0x02 0x000
	#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x05 0x000
	/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
	#define MX25_PAD_LD8__ESDHC2_CMD 0x0e8 0x2e0 0x4e0 0x16 0x000

	#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x00 0x000
	#define MX25_PAD_LD9__UART4_TXD 0x0ec 0x2e4 0x000 0x02 0x000
	#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x05 0x001
	#define MX25_PAD_LD9__ESDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000

	#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x00 0x000
	#define MX25_PAD_LD10__UART4_RTS 0x0f0 0x2e8 0x56c 0x02 0x000
	#define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x05 0x001

	#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x00 0x000
	#define MX25_PAD_LD11__UART4_CTS 0x0f4 0x2ec 0x000 0x02 0x000
	#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x05 0x001
	#define MX25_PAD_LD11__ESDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000

	#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x00 0x000
	#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000
	+#define MX25_PAD_LD12__KPP_ROW6 0x0f8 0x2f0 0x544 0x04 0x000
	#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x05 0x001

	#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x00 0x000
	#define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000
	+#define MX25_PAD_LD13__KPP_ROW7 0x0fc 0x2f4 0x548 0x04 0x000
	#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x05 0x000

	#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x00 0x000
	#define MX25_PAD_LD14__CSPI2_SCLK 0x100 0x2f8 0x494 0x02 0x000
	#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x05 0x000

	#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x00 0x000
	#define MX25_PAD_LD15__CSPI2_RDY 0x104 0x2fc 0x498 0x02 0x000
	#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x05 0x001

	#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x00 0x000
	#define MX25_PAD_HSYNC__GPIO_1_22 0x108 0x300 0x000 0x05 0x000

	#define MX25_PAD_VSYNC__VSYNC 0x10c 0x304 0x000 0x00 0x000
	#define MX25_PAD_VSYNC__GPIO_1_23 0x10c 0x304 0x000 0x05 0x000

	#define MX25_PAD_LSCLK__LSCLK 0x110 0x308 0x000 0x00 0x000
	#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x05 0x000

	#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x00 0x000
	#define MX25_PAD_OE_ACD__CSPI2_SS0 0x114 0x30c 0x4a4 0x02 0x000
	#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x05 0x000

	#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x00 0x000
	#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x01 0x000
	#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x04 0x000
	#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x05 0x001
	#define MX25_PAD_CONTRAST__USBH2_PWR 0x118 0x310 0x000 0x06 0x000

	#define MX25_PAD_PWM__PWM 0x11c 0x314 0x000 0x00 0x000
	#define MX25_PAD_PWM__GPIO_1_26 0x11c 0x314 0x000 0x05 0x000
	#define MX25_PAD_PWM__USBH2_OC 0x11c 0x314 0x580 0x06 0x001

	#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x00 0x000
	#define MX25_PAD_CSI_D2__UART5_RXD 0x120 0x318 0x578 0x01 0x001
	#define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000
	#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x05 0x000
	#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x07 0x000

	#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x00 0x000
	#define MX25_PAD_CSI_D3__UART5_TXD 0x124 0x31c 0x000 0x01 0x000
	#define MX25_PAD_CSI_D3__SIM1_RST0 0x124 0x31c 0x000 0x04 0x000
	#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x05 0x000
	#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x07 0x001

	#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x00 0x000
	#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x01 0x001
	#define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000
	#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x05 0x000
	#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x07 0x000

	#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x00 0x000
	#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x01 0x000
	#define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000
	#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x05 0x000
	#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x07 0x000

	#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x00 0x000
	/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
	#define MX25_PAD_CSI_D6__ESDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001
	#define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000
	#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x05 0x000

	#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x00 0x000
	#define MX25_PAD_CSI_D7__ESDHC2_CLK 0x134 0x32C 0x4dc 0x02 0x001
	#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x05 0x000

	#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x00 0x000
	#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x02 0x000
	#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x05 0x000
	#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x07 0x000

	#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x00 0x000
	#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x02 0x000
	#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x05 0x000
	#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x07 0x000

	#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x00 0x000
	#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x01 0x000
	#define MX25_PAD_CSI_MCLK__ESDHC2_DAT0 0x140 0x338 0x4e4 0x02 0x001
	#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x05 0x000

	#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x00 0x000
	#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x01 0x000
	#define MX25_PAD_CSI_VSYNC__ESDHC2_DAT1 0x144 0x33c 0x4e8 0x02 0x001
	#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x05 0x000

	#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x00 0x000
	#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x01 0x000
	#define MX25_PAD_CSI_HSYNC__ESDHC2_DAT2 0x148 0x340 0x4ec 0x02 0x001
	#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x05 0x000

	#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x00 0x000
	#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x01 0x000
	#define MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3 0x14c 0x344 0x4f0 0x02 0x001
	#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x05 0x000

	#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x00 0x000
	#define MX25_PAD_I2C1_CLK__GPIO_1_12 0x150 0x348 0x000 0x05 0x000

	#define MX25_PAD_I2C1_DAT__I2C1_DAT 0x154 0x34c 0x000 0x00 0x000
	#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x05 0x000

	#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x00 0x000
	#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x568 0x02 0x000
	#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x05 0x000

	#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x00 0x000
	#define MX25_PAD_CSPI1_MISO__UART3_TXD 0x15c 0x354 0x000 0x02 0x000
	#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x05 0x000

	#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x00 0x000
	#define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x02 0x000
	#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x05 0x000

	#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x00 0x000
	#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x01 0x001
	#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x02 0x000
	#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x05 0x000

	#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x00 0x000
	#define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x02 0x000
	#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x05 0x000

	#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x00 0x000
	#define MX25_PAD_CSPI1_RDY__GPIO_2_22 0x16c 0x364 0x000 0x05 0x000

	#define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x00 0x000
	#define MX25_PAD_UART1_RXD__UART2_DTR 0x170 0x368 0x000 0x03 0x000
	#define MX25_PAD_UART1_RXD__GPIO_4_22 0x170 0x368 0x000 0x05 0x000

	#define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x00 0x000
	#define MX25_PAD_UART1_TXD__UART2_DSR 0x174 0x36c 0x000 0x03 0x000
	#define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x05 0x000

	#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x00 0x000
	#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x01 0x001
	#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x02 0x000
	#define MX25_PAD_UART1_RTS__UART2_DCD 0x178 0x370 0x000 0x03 0x000
	#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x05 0x000

	#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x00 0x000
	#define MX25_PAD_UART1_CTS__CSI_D1 0x17c 0x374 0x48c 0x01 0x001
	#define MX25_PAD_UART1_CTS__UART2_RI 0x17c 0x374 0x000 0x03 0x001
	#define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x05 0x000

	#define MX25_PAD_UART2_RXD__UART2_RXD 0x180 0x378 0x000 0x00 0x000
	#define MX25_PAD_UART2_RXD__GPIO_4_26 0x180 0x378 0x000 0x05 0x000

	#define MX25_PAD_UART2_TXD__UART2_TXD 0x184 0x37c 0x000 0x00 0x000
	#define MX25_PAD_UART2_TXD__GPIO_4_27 0x184 0x37c 0x000 0x05 0x000

	#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x00 0x000
	#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x02 0x002
	#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x03 0x000
	#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x05 0x000

	#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x00 0x000
	#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x02 0x002
	#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x05 0x000

	/*
	* Removing the SION bit from MX25_PAD_*__ESDHCn_CMD breaks detecting an SD
	* card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM
	* Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon
	* bug that configuring the ESDHCn_CMD function doesn't enable the input path
	* for this pin.
	* This might have side effects for other hardware units that are connected to
	* that pin and use the respective function as input.
	*/
	#define MX25_PAD_SD1_CMD__ESDHC1_CMD 0x190 0x388 0x000 0x10 0x000
	#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x01 0x001
	#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x02 0x002
	#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x05 0x000

	#define MX25_PAD_SD1_CLK__ESDHC1_CLK 0x194 0x38c 0x000 0x00 0x000
	#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x01 0x001
	#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x02 0x002
	#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x05 0x000

	#define MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x198 0x390 0x000 0x00 0x000
	#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x01 0x001
	#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x05 0x000

	#define MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x19c 0x394 0x000 0x00 0x000
	#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x03 0x000
	#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x05 0x000

	#define MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x1a0 0x398 0x000 0x00 0x000
	#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x02 0x002
	#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x05 0x000

	#define MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x1a4 0x39c 0x000 0x00 0x000
	#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x02 0x002
	#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x05 0x000

	#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x00 0x000
	#define MX25_PAD_KPP_ROW0__UART3_RXD 0x1a8 0x3a0 0x568 0x01 0x001
	#define MX25_PAD_KPP_ROW0__UART1_DTR 0x1a8 0x3a0 0x000 0x04 0x000
	#define MX25_PAD_KPP_ROW0__GPIO_2_29 0x1a8 0x3a0 0x000 0x05 0x000

	#define MX25_PAD_KPP_ROW1__KPP_ROW1 0x1ac 0x3a4 0x000 0x00 0x000
	#define MX25_PAD_KPP_ROW1__UART3_TXD 0x1ac 0x3a4 0x000 0x01 0x000
	#define MX25_PAD_KPP_ROW1__UART1_DSR 0x1ac 0x3a4 0x000 0x04 0x000
	#define MX25_PAD_KPP_ROW1__GPIO_2_30 0x1ac 0x3a4 0x000 0x05 0x000

	#define MX25_PAD_KPP_ROW2__KPP_ROW2 0x1b0 0x3a8 0x000 0x00 0x000
	#define MX25_PAD_KPP_ROW2__UART3_RTS 0x1b0 0x3a8 0x000 0x01 0x000
	#define MX25_PAD_KPP_ROW2__CSI_D0 0x1b0 0x3a8 0x488 0x03 0x002
	#define MX25_PAD_KPP_ROW2__UART1_DCD 0x1b0 0x3a8 0x000 0x04 0x000
	#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x05 0x000

	#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x00 0x000
	#define MX25_PAD_KPP_ROW3__UART3_CTS 0x1b4 0x3ac 0x000 0x01 0x000
	#define MX25_PAD_KPP_ROW3__CSI_D1 0x1b4 0x3ac 0x48c 0x03 0x002
	#define MX25_PAD_KPP_ROW3__UART1_RI 0x1b4 0x3ac 0x000 0x04 0x000
	#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x05 0x000

	#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x00 0x000
	#define MX25_PAD_KPP_COL0__UART4_RXD 0x1b8 0x3b0 0x570 0x01 0x001
	#define MX25_PAD_KPP_COL0__AUD5_TXD 0x1b8 0x3b0 0x000 0x02 0x000
	#define MX25_PAD_KPP_COL0__GPIO_3_1 0x1b8 0x3b0 0x000 0x05 0x000

	#define MX25_PAD_KPP_COL1__KPP_COL1 0x1bc 0x3b4 0x000 0x00 0x000
	#define MX25_PAD_KPP_COL1__UART4_TXD 0x1bc 0x3b4 0x000 0x01 0x000
	#define MX25_PAD_KPP_COL1__AUD5_RXD 0x1bc 0x3b4 0x000 0x02 0x000
	#define MX25_PAD_KPP_COL1__GPIO_3_2 0x1bc 0x3b4 0x000 0x05 0x000

	#define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x00 0x000
	#define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x56c 0x01 0x001
	#define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x02 0x000
	#define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x05 0x000

	#define MX25_PAD_KPP_COL3__KPP_COL3 0x1c4 0x3bc 0x000 0x00 0x000
	#define MX25_PAD_KPP_COL3__UART4_CTS 0x1c4 0x3bc 0x000 0x01 0x000
	#define MX25_PAD_KPP_COL3__AUD5_TXFS 0x1c4 0x3bc 0x000 0x02 0x000
	#define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x05 0x000

	#define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x00 0x000
	/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
	#define MX25_PAD_FEC_MDC__ESDHC2_CMD 0x1c8 0x3c0 0x4e0 0x11 0x002
	#define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x02 0x001
	#define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x05 0x000

	#define MX25_PAD_FEC_MDIO__FEC_MDIO 0x1cc 0x3c4 0x000 0x00 0x000
	#define MX25_PAD_FEC_MDIO__AUD4_RXD 0x1cc 0x3c4 0x460 0x02 0x001
	#define MX25_PAD_FEC_MDIO__GPIO_3_6 0x1cc 0x3c4 0x000 0x05 0x000

	#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x1d0 0x3c8 0x000 0x00 0x000
	#define MX25_PAD_FEC_TDATA0__GPIO_3_7 0x1d0 0x3c8 0x000 0x05 0x000

	#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x1d4 0x3cc 0x000 0x00 0x000
	#define MX25_PAD_FEC_TDATA1__AUD4_TXFS 0x1d4 0x3cc 0x474 0x02 0x001
	#define MX25_PAD_FEC_TDATA1__GPIO_3_8 0x1d4 0x3cc 0x000 0x05 0x000

	#define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x00 0x000
	#define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x05 0x000
	+#define MX25_PAD_FEC_TX_EN__KPP_ROW4 0x1d8 0x3d0 0x53c 0x06 0x000

	#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x00 0x000
	#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x05 0x000
	+#define MX25_PAD_FEC_RDATA0__KPP_ROW5 0x1dc 0x3d4 0x540 0x06 0x000

	#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x00 0x000
	/*
	* According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
	* 01/2011) this is CAN1_TX but that's wrong.
	*/
	#define MX25_PAD_FEC_RDATA1__CAN2_TX 0x1e0 0x3d8 0x000 0x04 0x000
	#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x05 0x000

	#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x00 0x000
	/*
	* According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
	* 01/2011) this is CAN1_RX but that's wrong.
	*/
	#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x04 0x000
	#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x05 0x000

	#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1e8 0x3e0 0x000 0x00 0x000
	#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 0x1e8 0x3e0 0x000 0x05 0x000

	#define MX25_PAD_RTCK__RTCK 0x1ec 0x3e4 0x000 0x00 0x000
	#define MX25_PAD_RTCK__OWIRE 0x1ec 0x3e4 0x000 0x01 0x000
	#define MX25_PAD_RTCK__GPIO_3_14 0x1ec 0x3e4 0x000 0x05 0x000

	#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000

	#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x00 0x000
	#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x05 0x000

	#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x00 0x000
	#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x06 0x000
	#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x02 0x000

	#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x00 0x000
	#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x02 0x001
	#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x06 0x001

	#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x00 0x000
	#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000
	#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001
	#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001
	#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000

	#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x00 0x000
	#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x02 0x001
	#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x06 0x001

	#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x00 0x000
	#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x01 0x002
	#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000
	#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x04 0x000
	#define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x06 0x002

	#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x00 0x000
	#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000
	#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x04 0x000
	#define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x06 0x000

	#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x00 0x000
	#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x05 0x000

	#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 0x210 0x000 0x000 0x00 0x000
	#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 0x210 0x000 0x000 0x05 0x000

	#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x00 0x000
	#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x04 0x000
	#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x05 0x000
	#define MX25_PAD_VSTBY_REQ__UART4_RTS 0x214 0x408 0x56c 0x06 0x002

	#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x00 0x000
	#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x05 0x000

	#define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x00 0x000
	#define MX25_PAD_POWER_FAIL__AUD7_RXD 0x21c 0x410 0x478 0x04 0x001
	#define MX25_PAD_POWER_FAIL__GPIO_3_19 0x21c 0x410 0x000 0x05 0x000
	#define MX25_PAD_POWER_FAIL__UART4_CTS 0x21c 0x410 0x000 0x06 0x000

	#define MX25_PAD_CLKO__CLKO 0x220 0x414 0x000 0x00 0x000
	#define MX25_PAD_CLKO__GPIO_2_21 0x220 0x414 0x000 0x05 0x000

	#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000
	#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000

	#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000
	#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000

	/*
	* Compatibility defines for out-of-tree users. You should update if you make
	* use of one of them.
	*/
	#define MX25_PAD_D15__SDHC1_DAT7 MX25_PAD_D15__ESDHC1_DAT7
	#define MX25_PAD_D14__SDHC1_DAT6 MX25_PAD_D14__ESDHC1_DAT6
	#define MX25_PAD_D13__SDHC1_DAT5 MX25_PAD_D13__ESDHC1_DAT5
	#define MX25_PAD_D12__SDHC1_DAT4 MX25_PAD_D12__ESDHC1_DAT4
	#define MX25_PAD_LD8__SDHC2_CMD MX25_PAD_LD8__ESDHC2_CMD
	#define MX25_PAD_LD9__SDHC2_CLK MX25_PAD_LD9__ESDHC2_CLK
	#define MX25_PAD_LD11__SDHC2_DAT1 MX25_PAD_LD11__ESDHC2_DAT1
	#define MX25_PAD_CSI_D6__SDHC2_CMD MX25_PAD_CSI_D6__ESDHC2_CMD
	#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK MX25_PAD_CSI_D7__ESDHC2_CLK
	#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 MX25_PAD_CSI_MCLK__ESDHC2_DAT0
	#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 MX25_PAD_CSI_VSYNC__ESDHC2_DAT1
	#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 MX25_PAD_CSI_HSYNC__ESDHC2_DAT2
	#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3
	#define MX25_PAD_SD1_CMD__SD1_CMD MX25_PAD_SD1_CMD__ESDHC1_CMD
	#define MX25_PAD_SD1_CLK__SD1_CLK MX25_PAD_SD1_CLK__ESDHC1_CLK
	#define MX25_PAD_SD1_DATA0__SD1_DATA0 MX25_PAD_SD1_DATA0__ESDHC1_DAT0
	#define MX25_PAD_SD1_DATA1__SD1_DATA1 MX25_PAD_SD1_DATA1__ESDHC1_DAT1
	#define MX25_PAD_SD1_DATA2__SD1_DATA2 MX25_PAD_SD1_DATA2__ESDHC1_DAT2
	#define MX25_PAD_SD1_DATA3__SD1_DATA3 MX25_PAD_SD1_DATA3__ESDHC1_DAT3

	#endif /* __DTS_IMX25_PINFUNC_H */
	diff --git a/sys/gnu/dts/arm/imx25.dtsi b/sys/gnu/dts/arm/imx25.dtsi
	index 40b95a290bd6..1123e683025c 100644
	--- a/sys/gnu/dts/arm/imx25.dtsi
	+++ b/sys/gnu/dts/arm/imx25.dtsi
	@@ -1,637 +1,637 @@
	// SPDX-License-Identifier: GPL-2.0+
	//
	// Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>

	#include <dt-bindings/gpio/gpio.h>
	#include "imx25-pinfunc.h"

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	* The decompressor and also some bootloaders rely on a
	* pre-existing /chosen node to be available to insert the
	* command line and merge other ATAGS info.
	*/
	chosen {};

	aliases {
	ethernet0 = &fec;
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	gpio3 = &gpio4;
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	i2c2 = &i2c3;
	mmc0 = &esdhc1;
	mmc1 = &esdhc2;
	pwm0 = &pwm1;
	pwm1 = &pwm2;
	pwm2 = &pwm3;
	pwm3 = &pwm4;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	serial4 = &uart5;
	spi0 = &spi1;
	spi1 = &spi2;
	spi2 = &spi3;
	usb0 = &usbotg;
	usb1 = &usbhost1;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	compatible = "arm,arm926ej-s";
	device_type = "cpu";
	reg = <0>;
	};
	};

	asic: asic-interrupt-controller@68000000 {
	compatible = "fsl,imx25-asic", "fsl,avic";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x68000000 0x8000000>;
	};

	clocks {
	osc {
	compatible = "fsl,imx-osc", "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	};
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&asic>;
	ranges;

	- aips@43f00000 { /* AIPS1 */
	+ bus@43f00000 { /* AIPS1 */
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x43f00000 0x100000>;
	ranges;

	aips1: bridge@43f00000 {
	compatible = "fsl,imx25-aips";
	reg = <0x43f00000 0x4000>;
	};

	i2c1: i2c@43f80000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
	reg = <0x43f80000 0x4000>;
	clocks = <&clks 48>;
	clock-names = "";
	interrupts = <3>;
	status = "disabled";
	};

	i2c3: i2c@43f84000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
	reg = <0x43f84000 0x4000>;
	clocks = <&clks 48>;
	clock-names = "";
	interrupts = <10>;
	status = "disabled";
	};

	can1: can@43f88000 {
	compatible = "fsl,imx25-flexcan";
	reg = <0x43f88000 0x4000>;
	interrupts = <43>;
	clocks = <&clks 75>, <&clks 75>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	can2: can@43f8c000 {
	compatible = "fsl,imx25-flexcan";
	reg = <0x43f8c000 0x4000>;
	interrupts = <44>;
	clocks = <&clks 76>, <&clks 76>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart1: serial@43f90000 {
	compatible = "fsl,imx25-uart", "fsl,imx21-uart";
	reg = <0x43f90000 0x4000>;
	interrupts = <45>;
	clocks = <&clks 120>, <&clks 57>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart2: serial@43f94000 {
	compatible = "fsl,imx25-uart", "fsl,imx21-uart";
	reg = <0x43f94000 0x4000>;
	interrupts = <32>;
	clocks = <&clks 121>, <&clks 57>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	i2c2: i2c@43f98000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
	reg = <0x43f98000 0x4000>;
	clocks = <&clks 48>;
	clock-names = "";
	interrupts = <4>;
	status = "disabled";
	};

	owire@43f9c000 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x43f9c000 0x4000>;
	clocks = <&clks 51>;
	clock-names = "";
	interrupts = <2>;
	status = "disabled";
	};

	spi1: spi@43fa4000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
	reg = <0x43fa4000 0x4000>;
	clocks = <&clks 78>, <&clks 78>;
	clock-names = "ipg", "per";
	interrupts = <14>;
	status = "disabled";
	};

	kpp: kpp@43fa8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx25-kpp", "fsl,imx21-kpp";
	reg = <0x43fa8000 0x4000>;
	clocks = <&clks 102>;
	clock-names = "";
	interrupts = <24>;
	status = "disabled";
	};

	iomuxc: iomuxc@43fac000 {
	compatible = "fsl,imx25-iomuxc";
	reg = <0x43fac000 0x4000>;
	};

	audmux: audmux@43fb0000 {
	compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
	reg = <0x43fb0000 0x4000>;
	status = "disabled";
	};
	};

	spba@50000000 {
	compatible = "fsl,spba-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x50000000 0x40000>;
	ranges;

	spi3: spi@50004000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
	reg = <0x50004000 0x4000>;
	interrupts = <0>;
	clocks = <&clks 80>, <&clks 80>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart4: serial@50008000 {
	compatible = "fsl,imx25-uart", "fsl,imx21-uart";
	reg = <0x50008000 0x4000>;
	interrupts = <5>;
	clocks = <&clks 123>, <&clks 57>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart3: serial@5000c000 {
	compatible = "fsl,imx25-uart", "fsl,imx21-uart";
	reg = <0x5000c000 0x4000>;
	interrupts = <18>;
	clocks = <&clks 122>, <&clks 57>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	spi2: spi@50010000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
	reg = <0x50010000 0x4000>;
	clocks = <&clks 79>, <&clks 79>;
	clock-names = "ipg", "per";
	interrupts = <13>;
	status = "disabled";
	};

	ssi2: ssi@50014000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
	reg = <0x50014000 0x4000>;
	interrupts = <11>;
	clocks = <&clks 118>;
	clock-names = "ipg";
	dmas = <&sdma 24 1 0>,
	<&sdma 25 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	esai@50018000 {
	reg = <0x50018000 0x4000>;
	interrupts = <7>;
	};

	uart5: serial@5002c000 {
	compatible = "fsl,imx25-uart", "fsl,imx21-uart";
	reg = <0x5002c000 0x4000>;
	interrupts = <40>;
	clocks = <&clks 124>, <&clks 57>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	tscadc: tscadc@50030000 {
	compatible = "fsl,imx25-tsadc";
	reg = <0x50030000 0xc>;
	interrupts = <46>;
	clocks = <&clks 119>;
	clock-names = "ipg";
	interrupt-controller;
	#interrupt-cells = <1>;
	#address-cells = <1>;
	#size-cells = <1>;
	status = "disabled";
	ranges;

	adc: adc@50030800 {
	compatible = "fsl,imx25-gcq";
	reg = <0x50030800 0x60>;
	interrupt-parent = <&tscadc>;
	interrupts = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	tsc: tcq@50030400 {
	compatible = "fsl,imx25-tcq";
	reg = <0x50030400 0x60>;
	interrupt-parent = <&tscadc>;
	interrupts = <0>;
	fsl,wires = <4>;
	status = "disabled";
	};
	};

	ssi1: ssi@50034000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
	reg = <0x50034000 0x4000>;
	interrupts = <12>;
	clocks = <&clks 117>;
	clock-names = "ipg";
	dmas = <&sdma 28 1 0>,
	<&sdma 29 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	fec: ethernet@50038000 {
	compatible = "fsl,imx25-fec";
	reg = <0x50038000 0x4000>;
	interrupts = <57>;
	clocks = <&clks 88>, <&clks 65>;
	clock-names = "ipg", "ahb";
	status = "disabled";
	};
	};

	- aips@53f00000 { /* AIPS2 */
	+ bus@53f00000 { /* AIPS2 */
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x53f00000 0x100000>;
	ranges;

	aips2: bridge@53f00000 {
	compatible = "fsl,imx25-aips";
	reg = <0x53f00000 0x4000>;
	};

	clks: ccm@53f80000 {
	compatible = "fsl,imx25-ccm";
	reg = <0x53f80000 0x4000>;
	interrupts = <31>;
	#clock-cells = <1>;
	};

	gpt4: timer@53f84000 {
	compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
	reg = <0x53f84000 0x4000>;
	clocks = <&clks 95>, <&clks 47>;
	clock-names = "ipg", "per";
	interrupts = <1>;
	};

	gpt3: timer@53f88000 {
	compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
	reg = <0x53f88000 0x4000>;
	clocks = <&clks 94>, <&clks 47>;
	clock-names = "ipg", "per";
	interrupts = <29>;
	};

	gpt2: timer@53f8c000 {
	compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
	reg = <0x53f8c000 0x4000>;
	clocks = <&clks 93>, <&clks 47>;
	clock-names = "ipg", "per";
	interrupts = <53>;
	};

	gpt1: timer@53f90000 {
	compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
	reg = <0x53f90000 0x4000>;
	clocks = <&clks 92>, <&clks 47>;
	clock-names = "ipg", "per";
	interrupts = <54>;
	};

	epit1: timer@53f94000 {
	compatible = "fsl,imx25-epit";
	reg = <0x53f94000 0x4000>;
	clocks = <&clks 83>, <&clks 43>;
	clock-names = "ipg", "per";
	interrupts = <28>;
	};

	epit2: timer@53f98000 {
	compatible = "fsl,imx25-epit";
	reg = <0x53f98000 0x4000>;
	clocks = <&clks 84>, <&clks 43>;
	clock-names = "ipg", "per";
	interrupts = <27>;
	};

	gpio4: gpio@53f9c000 {
	compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
	reg = <0x53f9c000 0x4000>;
	interrupts = <23>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	pwm2: pwm@53fa0000 {
	compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
	#pwm-cells = <2>;
	reg = <0x53fa0000 0x4000>;
	clocks = <&clks 106>, <&clks 52>;
	clock-names = "ipg", "per";
	interrupts = <36>;
	};

	gpio3: gpio@53fa4000 {
	compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
	reg = <0x53fa4000 0x4000>;
	interrupts = <16>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	pwm3: pwm@53fa8000 {
	compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
	#pwm-cells = <2>;
	reg = <0x53fa8000 0x4000>;
	clocks = <&clks 107>, <&clks 52>;
	clock-names = "ipg", "per";
	interrupts = <41>;
	};

	scc: crypto@53fac000 {
	compatible = "fsl,imx25-scc";
	reg = <0x53fac000 0x4000>;
	clocks = <&clks 111>;
	clock-names = "ipg";
	interrupts = <49>, <50>;
	interrupt-names = "scm", "smn";
	};

	rngb: rngb@53fb0000 {
	compatible = "fsl,imx25-rngb";
	reg = <0x53fb0000 0x4000>;
	clocks = <&clks 109>;
	interrupts = <22>;
	};

	esdhc1: esdhc@53fb4000 {
	compatible = "fsl,imx25-esdhc";
	reg = <0x53fb4000 0x4000>;
	interrupts = <9>;
	clocks = <&clks 86>, <&clks 63>, <&clks 45>;
	clock-names = "ipg", "ahb", "per";
	status = "disabled";
	};

	esdhc2: esdhc@53fb8000 {
	compatible = "fsl,imx25-esdhc";
	reg = <0x53fb8000 0x4000>;
	interrupts = <8>;
	clocks = <&clks 87>, <&clks 64>, <&clks 46>;
	clock-names = "ipg", "ahb", "per";
	status = "disabled";
	};

	lcdc: lcdc@53fbc000 {
	compatible = "fsl,imx25-fb", "fsl,imx21-fb";
	reg = <0x53fbc000 0x4000>;
	interrupts = <39>;
	clocks = <&clks 103>, <&clks 66>, <&clks 49>;
	clock-names = "ipg", "ahb", "per";
	status = "disabled";
	};

	slcdc@53fc0000 {
	reg = <0x53fc0000 0x4000>;
	interrupts = <38>;
	status = "disabled";
	};

	pwm4: pwm@53fc8000 {
	compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
	#pwm-cells = <2>;
	reg = <0x53fc8000 0x4000>;
	clocks = <&clks 108>, <&clks 52>;
	clock-names = "ipg", "per";
	interrupts = <42>;
	};

	gpio1: gpio@53fcc000 {
	compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
	reg = <0x53fcc000 0x4000>;
	interrupts = <52>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio@53fd0000 {
	compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
	reg = <0x53fd0000 0x4000>;
	interrupts = <51>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	sdma: sdma@53fd4000 {
	compatible = "fsl,imx25-sdma";
	reg = <0x53fd4000 0x4000>;
	clocks = <&clks 112>, <&clks 68>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	interrupts = <34>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin";
	};

	wdog@53fdc000 {
	compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
	reg = <0x53fdc000 0x4000>;
	clocks = <&clks 126>;
	clock-names = "";
	interrupts = <55>;
	};

	pwm1: pwm@53fe0000 {
	compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
	#pwm-cells = <2>;
	reg = <0x53fe0000 0x4000>;
	clocks = <&clks 105>, <&clks 52>;
	clock-names = "ipg", "per";
	interrupts = <26>;
	};

	iim: iim@53ff0000 {
	compatible = "fsl,imx25-iim", "fsl,imx27-iim";
	reg = <0x53ff0000 0x4000>;
	interrupts = <19>;
	clocks = <&clks 99>;
	};

	usbotg: usb@53ff4000 {
	compatible = "fsl,imx25-usb", "fsl,imx27-usb";
	reg = <0x53ff4000 0x0200>;
	interrupts = <37>;
	clocks = <&clks 9>, <&clks 70>, <&clks 8>;
	clock-names = "ipg", "ahb", "per";
	fsl,usbmisc = <&usbmisc 0>;
	fsl,usbphy = <&usbphy0>;
	phy_type = "utmi";
	dr_mode = "otg";
	status = "disabled";
	};

	usbhost1: usb@53ff4400 {
	compatible = "fsl,imx25-usb", "fsl,imx27-usb";
	reg = <0x53ff4400 0x0200>;
	interrupts = <35>;
	clocks = <&clks 9>, <&clks 70>, <&clks 8>;
	clock-names = "ipg", "ahb", "per";
	fsl,usbmisc = <&usbmisc 1>;
	fsl,usbphy = <&usbphy1>;
	maximum-speed = "full-speed";
	phy_type = "serial";
	dr_mode = "host";
	status = "disabled";
	};

	usbmisc: usbmisc@53ff4600 {
	#index-cells = <1>;
	compatible = "fsl,imx25-usbmisc";
	reg = <0x53ff4600 0x00f>;
	};

	dryice@53ffc000 {
	compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
	reg = <0x53ffc000 0x4000>;
	clocks = <&clks 81>;
	clock-names = "ipg";
	interrupts = <25 56>;
	};
	};

	iram: sram@78000000 {
	compatible = "mmio-sram";
	reg = <0x78000000 0x20000>;
	};

	emi@80000000 {
	compatible = "fsl,emi-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x80000000 0x3b002000>;
	ranges;

	nfc: nand@bb000000 {
	#address-cells = <1>;
	#size-cells = <1>;

	compatible = "fsl,imx25-nand";
	reg = <0xbb000000 0x2000>;
	clocks = <&clks 50>;
	clock-names = "";
	interrupts = <33>;
	status = "disabled";
	};
	};
	};

	usbphy {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	usbphy0: usb-phy@0 {
	reg = <0>;
	compatible = "usb-nop-xceiv";
	#phy-cells = <0>;
	};

	usbphy1: usb-phy@1 {
	reg = <1>;
	compatible = "usb-nop-xceiv";
	#phy-cells = <0>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx27-phytec-phycard-s-rdk.dts b/sys/gnu/dts/arm/imx27-phytec-phycard-s-rdk.dts
	index 0cd75dadf292..188639738dc3 100644
	--- a/sys/gnu/dts/arm/imx27-phytec-phycard-s-rdk.dts
	+++ b/sys/gnu/dts/arm/imx27-phytec-phycard-s-rdk.dts
	@@ -1,162 +1,162 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	/*
	* Copyright 2012 Markus Pargmann, Pengutronix
	*/

	#include "imx27-phytec-phycard-s-som.dtsi"

	/ {
	model = "Phytec pca100 rapid development kit";
	compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27";

	chosen {
	stdout-path = &uart1;
	};

	display: display {
	model = "Primeview-PD050VL1";
	bits-per-pixel = <16>; /* non-standard but required */
	fsl,pcr = <0xf0c88080>; /* non-standard but required */
	display-timings {
	native-mode = <&timing0>;
	timing0: 640x480 {
	hactive = <640>;
	vactive = <480>;
	hback-porch = <112>;
	hfront-porch = <36>;
	hsync-len = <32>;
	vback-porch = <33>;
	vfront-porch = <33>;
	vsync-len = <2>;
	clock-frequency = <25000000>;
	};
	};
	};

	regulators {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	reg_3v3: regulator@0 {
	compatible = "regulator-fixed";
	reg = <0>;
	regulator-name = "3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};
	};
	};

	&fb {
	display = <&display>;
	status = "okay";
	};

	&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	rtc@51 {
	compatible = "nxp,pcf8563";
	reg = <0x51>;
	};

	adc@64 {
	compatible = "maxim,max1037";
	vcc-supply = <&reg_3v3>;
	reg = <0x64>;
	};
	};

	&iomuxc {
	imx27-phycard-s-rdk {
	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	- MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
	- MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
	+ MX27_PAD_I2C_DATA__I2C_DATA 0x0
	+ MX27_PAD_I2C_CLK__I2C_CLK 0x0
	>;
	};

	pinctrl_owire1: owire1grp {
	fsl,pins = <
	MX27_PAD_RTCK__OWIRE 0x0
	>;
	};

	pinctrl_sdhc2: sdhc2grp {
	fsl,pins = <
	MX27_PAD_SD2_CLK__SD2_CLK 0x0
	MX27_PAD_SD2_CMD__SD2_CMD 0x0
	MX27_PAD_SD2_D0__SD2_D0 0x0
	MX27_PAD_SD2_D1__SD2_D1 0x0
	MX27_PAD_SD2_D2__SD2_D2 0x0
	MX27_PAD_SD2_D3__SD2_D3 0x0
	MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	MX27_PAD_UART1_TXD__UART1_TXD 0x0
	MX27_PAD_UART1_RXD__UART1_RXD 0x0
	MX27_PAD_UART1_CTS__UART1_CTS 0x0
	MX27_PAD_UART1_RTS__UART1_RTS 0x0
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	MX27_PAD_UART2_TXD__UART2_TXD 0x0
	MX27_PAD_UART2_RXD__UART2_RXD 0x0
	MX27_PAD_UART2_CTS__UART2_CTS 0x0
	MX27_PAD_UART2_RTS__UART2_RTS 0x0
	>;
	};

	pinctrl_uart3: uart3grp {
	fsl,pins = <
	MX27_PAD_UART3_TXD__UART3_TXD 0x0
	MX27_PAD_UART3_RXD__UART3_RXD 0x0
	MX27_PAD_UART3_CTS__UART3_CTS 0x0
	MX27_PAD_UART3_RTS__UART3_RTS 0x0
	>;
	};
	};
	};

	&owire {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_owire1>;
	status = "okay";
	};

	&sdhci2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sdhc2>;
	cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
	status = "okay";
	};

	&uart1 {
	uart-has-rtscts;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
	};

	&uart2 {
	uart-has-rtscts;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
	};

	&uart3 {
	uart-has-rtscts;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/imx27.dtsi b/sys/gnu/dts/arm/imx27.dtsi
	index f3464cf52e49..002cd223f22d 100644
	--- a/sys/gnu/dts/arm/imx27.dtsi
	+++ b/sys/gnu/dts/arm/imx27.dtsi
	@@ -1,593 +1,593 @@
	// SPDX-License-Identifier: GPL-2.0+
	//
	// Copyright 2012 Sascha Hauer, Pengutronix

	#include "imx27-pinfunc.h"

	#include <dt-bindings/clock/imx27-clock.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/irq.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	* The decompressor and also some bootloaders rely on a
	* pre-existing /chosen node to be available to insert the
	* command line and merge other ATAGS info.
	*/
	chosen {};

	aliases {
	ethernet0 = &fec;
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	gpio3 = &gpio4;
	gpio4 = &gpio5;
	gpio5 = &gpio6;
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	serial4 = &uart5;
	serial5 = &uart6;
	spi0 = &cspi1;
	spi1 = &cspi2;
	spi2 = &cspi3;
	};

	aitc: aitc-interrupt-controller@10040000 {
	compatible = "fsl,imx27-aitc", "fsl,avic";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x10040000 0x1000>;
	};

	clocks {
	clk_osc26m: osc26m {
	compatible = "fsl,imx-osc26m", "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <26000000>;
	};
	};

	cpus {
	#size-cells = <0>;
	#address-cells = <1>;

	cpu: cpu@0 {
	device_type = "cpu";
	reg = <0>;
	compatible = "arm,arm926ej-s";
	operating-points = <
	/* kHz uV */
	266000 1300000
	399000 1450000
	>;
	clock-latency = <62500>;
	clocks = <&clks IMX27_CLK_CPU_DIV>;
	voltage-tolerance = <5>;
	};
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&aitc>;
	ranges;

	aipi@10000000 { /* AIPI1 */
	compatible = "fsl,aipi-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x10000000 0x20000>;
	ranges;

	dma: dma@10001000 {
	compatible = "fsl,imx27-dma";
	reg = <0x10001000 0x1000>;
	interrupts = <32>;
	clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
	<&clks IMX27_CLK_DMA_AHB_GATE>;
	clock-names = "ipg", "ahb";
	#dma-cells = <1>;
	#dma-channels = <16>;
	};

	wdog: wdog@10002000 {
	compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
	reg = <0x10002000 0x1000>;
	interrupts = <27>;
	clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
	};

	gpt1: timer@10003000 {
	compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
	reg = <0x10003000 0x1000>;
	interrupts = <26>;
	clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
	<&clks IMX27_CLK_PER1_GATE>;
	clock-names = "ipg", "per";
	};

	gpt2: timer@10004000 {
	compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
	reg = <0x10004000 0x1000>;
	interrupts = <25>;
	clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
	<&clks IMX27_CLK_PER1_GATE>;
	clock-names = "ipg", "per";
	};

	gpt3: timer@10005000 {
	compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
	reg = <0x10005000 0x1000>;
	interrupts = <24>;
	clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
	<&clks IMX27_CLK_PER1_GATE>;
	clock-names = "ipg", "per";
	};

	pwm: pwm@10006000 {
	#pwm-cells = <2>;
	compatible = "fsl,imx27-pwm";
	reg = <0x10006000 0x1000>;
	interrupts = <23>;
	clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
	<&clks IMX27_CLK_PER1_GATE>;
	clock-names = "ipg", "per";
	};

	rtc: rtc@10007000 {
	compatible = "fsl,imx21-rtc";
	reg = <0x10007000 0x1000>;
	interrupts = <22>;
	clocks = <&clks IMX27_CLK_CKIL>,
	<&clks IMX27_CLK_RTC_IPG_GATE>;
	clock-names = "ref", "ipg";
	};

	kpp: kpp@10008000 {
	compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
	reg = <0x10008000 0x1000>;
	interrupts = <21>;
	clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
	status = "disabled";
	};

	owire: owire@10009000 {
	compatible = "fsl,imx27-owire", "fsl,imx21-owire";
	reg = <0x10009000 0x1000>;
	clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
	status = "disabled";
	};

	uart1: serial@1000a000 {
	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	reg = <0x1000a000 0x1000>;
	interrupts = <20>;
	clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
	<&clks IMX27_CLK_PER1_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart2: serial@1000b000 {
	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	reg = <0x1000b000 0x1000>;
	interrupts = <19>;
	clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
	<&clks IMX27_CLK_PER1_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart3: serial@1000c000 {
	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	reg = <0x1000c000 0x1000>;
	interrupts = <18>;
	clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
	<&clks IMX27_CLK_PER1_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart4: serial@1000d000 {
	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	reg = <0x1000d000 0x1000>;
	interrupts = <17>;
	clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
	<&clks IMX27_CLK_PER1_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	cspi1: spi@1000e000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx27-cspi";
	reg = <0x1000e000 0x1000>;
	interrupts = <16>;
	clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
	<&clks IMX27_CLK_PER2_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	cspi2: spi@1000f000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx27-cspi";
	reg = <0x1000f000 0x1000>;
	interrupts = <15>;
	clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
	<&clks IMX27_CLK_PER2_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ssi1: ssi@10010000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
	reg = <0x10010000 0x1000>;
	interrupts = <14>;
	clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
	dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
	dma-names = "rx0", "tx0", "rx1", "tx1";
	fsl,fifo-depth = <8>;
	status = "disabled";
	};

	ssi2: ssi@10011000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
	reg = <0x10011000 0x1000>;
	interrupts = <13>;
	clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
	dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
	dma-names = "rx0", "tx0", "rx1", "tx1";
	fsl,fifo-depth = <8>;
	status = "disabled";
	};

	i2c1: i2c@10012000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
	reg = <0x10012000 0x1000>;
	interrupts = <12>;
	clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
	status = "disabled";
	};

	sdhci1: sdhci@10013000 {
	compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
	reg = <0x10013000 0x1000>;
	interrupts = <11>;
	clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
	<&clks IMX27_CLK_PER2_GATE>;
	clock-names = "ipg", "per";
	dmas = <&dma 7>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	sdhci2: sdhci@10014000 {
	compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
	reg = <0x10014000 0x1000>;
	interrupts = <10>;
	clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
	<&clks IMX27_CLK_PER2_GATE>;
	clock-names = "ipg", "per";
	dmas = <&dma 6>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	iomuxc: iomuxc@10015000 {
	compatible = "fsl,imx27-iomuxc";
	reg = <0x10015000 0x600>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	gpio1: gpio@10015000 {
	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	reg = <0x10015000 0x100>;
	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
	interrupts = <8>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio@10015100 {
	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	reg = <0x10015100 0x100>;
	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
	interrupts = <8>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio@10015200 {
	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	reg = <0x10015200 0x100>;
	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
	interrupts = <8>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio4: gpio@10015300 {
	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	reg = <0x10015300 0x100>;
	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
	interrupts = <8>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio5: gpio@10015400 {
	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	reg = <0x10015400 0x100>;
	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
	interrupts = <8>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio6: gpio@10015500 {
	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	reg = <0x10015500 0x100>;
	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
	interrupts = <8>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	audmux: audmux@10016000 {
	compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
	reg = <0x10016000 0x1000>;
	clocks = <&clks IMX27_CLK_DUMMY>;
	clock-names = "audmux";
	status = "disabled";
	};

	cspi3: spi@10017000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx27-cspi";
	reg = <0x10017000 0x1000>;
	interrupts = <6>;
	clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
	<&clks IMX27_CLK_PER2_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	gpt4: timer@10019000 {
	compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
	reg = <0x10019000 0x1000>;
	interrupts = <4>;
	clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
	<&clks IMX27_CLK_PER1_GATE>;
	clock-names = "ipg", "per";
	};

	gpt5: timer@1001a000 {
	compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
	reg = <0x1001a000 0x1000>;
	interrupts = <3>;
	clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
	<&clks IMX27_CLK_PER1_GATE>;
	clock-names = "ipg", "per";
	};

	uart5: serial@1001b000 {
	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	reg = <0x1001b000 0x1000>;
	interrupts = <49>;
	clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
	<&clks IMX27_CLK_PER1_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart6: serial@1001c000 {
	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	reg = <0x1001c000 0x1000>;
	interrupts = <48>;
	clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
	<&clks IMX27_CLK_PER1_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	i2c2: i2c@1001d000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
	reg = <0x1001d000 0x1000>;
	interrupts = <1>;
	clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
	status = "disabled";
	};

	sdhci3: sdhci@1001e000 {
	compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
	reg = <0x1001e000 0x1000>;
	interrupts = <9>;
	clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
	<&clks IMX27_CLK_PER2_GATE>;
	clock-names = "ipg", "per";
	dmas = <&dma 36>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	gpt6: timer@1001f000 {
	compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
	reg = <0x1001f000 0x1000>;
	interrupts = <2>;
	clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
	<&clks IMX27_CLK_PER1_GATE>;
	clock-names = "ipg", "per";
	};
	};

	aipi@10020000 { /* AIPI2 */
	compatible = "fsl,aipi-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x10020000 0x20000>;
	ranges;

	fb: fb@10021000 {
	compatible = "fsl,imx27-fb", "fsl,imx21-fb";
	interrupts = <61>;
	reg = <0x10021000 0x1000>;
	clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
	<&clks IMX27_CLK_LCDC_AHB_GATE>,
	<&clks IMX27_CLK_PER3_GATE>;
	clock-names = "ipg", "ahb", "per";
	status = "disabled";
	};

	coda: coda@10023000 {
	compatible = "fsl,imx27-vpu", "cnm,codadx6";
	reg = <0x10023000 0x0200>;
	interrupts = <53>;
	clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
	<&clks IMX27_CLK_VPU_AHB_GATE>;
	clock-names = "per", "ahb";
	iram = <&iram>;
	};

	usbotg: usb@10024000 {
	compatible = "fsl,imx27-usb";
	reg = <0x10024000 0x200>;
	interrupts = <56>;
	clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
	<&clks IMX27_CLK_USB_AHB_GATE>,
	<&clks IMX27_CLK_USB_DIV>;
	clock-names = "ipg", "ahb", "per";
	fsl,usbmisc = <&usbmisc 0>;
	status = "disabled";
	};

	usbh1: usb@10024200 {
	compatible = "fsl,imx27-usb";
	reg = <0x10024200 0x200>;
	interrupts = <54>;
	clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
	<&clks IMX27_CLK_USB_AHB_GATE>,
	<&clks IMX27_CLK_USB_DIV>;
	clock-names = "ipg", "ahb", "per";
	fsl,usbmisc = <&usbmisc 1>;
	dr_mode = "host";
	status = "disabled";
	};

	usbh2: usb@10024400 {
	compatible = "fsl,imx27-usb";
	reg = <0x10024400 0x200>;
	interrupts = <55>;
	clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
	<&clks IMX27_CLK_USB_AHB_GATE>,
	<&clks IMX27_CLK_USB_DIV>;
	clock-names = "ipg", "ahb", "per";
	fsl,usbmisc = <&usbmisc 2>;
	dr_mode = "host";
	status = "disabled";
	};

	usbmisc: usbmisc@10024600 {
	#index-cells = <1>;
	compatible = "fsl,imx27-usbmisc";
	reg = <0x10024600 0x200>;
	};

	- sahara2: sahara@10025000 {
	+ sahara2: crypto@10025000 {
	compatible = "fsl,imx27-sahara";
	reg = <0x10025000 0x1000>;
	interrupts = <59>;
	clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
	<&clks IMX27_CLK_SAHARA_AHB_GATE>;
	clock-names = "ipg", "ahb";
	};

	clks: ccm@10027000{
	compatible = "fsl,imx27-ccm";
	reg = <0x10027000 0x1000>;
	#clock-cells = <1>;
	};

	iim: iim@10028000 {
	compatible = "fsl,imx27-iim";
	reg = <0x10028000 0x1000>;
	interrupts = <62>;
	clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
	};

	fec: ethernet@1002b000 {
	compatible = "fsl,imx27-fec";
	reg = <0x1002b000 0x1000>;
	interrupts = <50>;
	clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
	<&clks IMX27_CLK_FEC_AHB_GATE>;
	clock-names = "ipg", "ahb";
	status = "disabled";
	};
	};

	nfc: nand@d8000000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "fsl,imx27-nand";
	reg = <0xd8000000 0x1000>;
	interrupts = <29>;
	clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
	status = "disabled";
	};

	weim: weim@d8002000 {
	#address-cells = <2>;
	#size-cells = <1>;
	compatible = "fsl,imx27-weim";
	reg = <0xd8002000 0x1000>;
	clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
	ranges = <
	0 0 0xc0000000 0x08000000
	1 0 0xc8000000 0x08000000
	2 0 0xd0000000 0x02000000
	3 0 0xd2000000 0x02000000
	4 0 0xd4000000 0x02000000
	5 0 0xd6000000 0x02000000
	>;
	status = "disabled";
	};

	iram: sram@ffff4c00 {
	compatible = "mmio-sram";
	reg = <0xffff4c00 0xb400>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx28-apx4devkit.dts b/sys/gnu/dts/arm/imx28-apx4devkit.dts
	index 3a184d13887b..c5acc19c982d 100644
	--- a/sys/gnu/dts/arm/imx28-apx4devkit.dts
	+++ b/sys/gnu/dts/arm/imx28-apx4devkit.dts
	@@ -1,230 +1,240 @@
	// SPDX-License-Identifier: GPL-2.0
	/dts-v1/;
	#include "imx28.dtsi"

	/ {
	model = "Bluegiga APX4 Development Kit";
	compatible = "bluegiga,apx4devkit", "fsl,imx28";

	memory@40000000 {
	device_type = "memory";
	reg = <0x40000000 0x04000000>;
	};

	apb@80000000 {
	apbh@80000000 {
	gpmi-nand@8000c000 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
	status = "okay";
	};

	ssp0: spi@80010000 {
	compatible = "fsl,imx28-mmc";
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
	bus-width = <4>;
	status = "okay";
	};

	ssp2: spi@80014000 {
	compatible = "fsl,imx28-mmc";
	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>;
	bus-width = <4>;
	status = "okay";
	};

	pinctrl@80018000 {
	pinctrl-names = "default";
	pinctrl-0 = <&hog_pins_a>;

	hog_pins_a: hog@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_GPMI_CE1N__GPIO_0_17
	MX28_PAD_GPMI_RDY1__GPIO_0_21
	MX28_PAD_SSP2_MISO__GPIO_2_18
	MX28_PAD_SSP2_SS0__AUART3_TX /* was: 0x2131 - MX28_PAD_SSP2_SS0__GPIO_2_19 */
	MX28_PAD_PWM3__GPIO_3_28
	MX28_PAD_LCD_RESET__GPIO_3_30
	MX28_PAD_JTAG_RTCK__GPIO_4_20
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	lcdif_pins_apx4: lcdif-apx4@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_LCD_RD_E__LCD_VSYNC
	MX28_PAD_LCD_WR_RWN__LCD_HSYNC
	MX28_PAD_LCD_RS__LCD_DOTCLK
	MX28_PAD_LCD_CS__LCD_ENABLE
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_SSP0_DATA4__SSP2_D0
	MX28_PAD_SSP0_DATA5__SSP2_D3
	MX28_PAD_SSP0_DATA6__SSP2_CMD
	MX28_PAD_SSP0_DATA7__SSP2_SCK
	MX28_PAD_SSP2_SS1__SSP2_D1
	MX28_PAD_SSP2_SS2__SSP2_D2
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_SSP0_DATA7__SSP2_SCK
	>;
	fsl,drive-strength = <MXS_DRIVE_12mA>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};
	};

	lcdif@80030000 {
	pinctrl-names = "default";
	pinctrl-0 = <&lcdif_24bit_pins_a
	&lcdif_pins_apx4>;
	display = <&display0>;
	status = "okay";

	display0: display0 {
	bits-per-pixel = <32>;
	bus-width = <24>;

	display-timings {
	native-mode = <&timing0>;
	timing0: timing0 {
	clock-frequency = <30000000>;
	hactive = <800>;
	vactive = <480>;
	hback-porch = <88>;
	hfront-porch = <40>;
	vback-porch = <32>;
	vfront-porch = <13>;
	hsync-len = <48>;
	vsync-len = <3>;
	hsync-active = <1>;
	vsync-active = <1>;
	de-active = <1>;
	pixelclk-active = <0>;
	};
	};
	};
	};
	};

	apbx@80040000 {
	saif0: saif@80042000 {
	pinctrl-names = "default";
	pinctrl-0 = <&saif0_pins_a>;
	status = "okay";
	};

	saif1: saif@80046000 {
	pinctrl-names = "default";
	pinctrl-0 = <&saif1_pins_a>;
	fsl,saif-master = <&saif0>;
	status = "okay";
	};

	i2c0: i2c@80058000 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins_a>;
	status = "okay";

	sgtl5000: codec@a {
	compatible = "fsl,sgtl5000";
	reg = <0x0a>;
	#sound-dai-cells = <0>;
	VDDA-supply = <&reg_3p3v>;
	VDDIO-supply = <&reg_3p3v>;
	clocks = <&saif0>;
	};

	pcf8563: rtc@51 {
	compatible = "phg,pcf8563";
	reg = <0x51>;
	};
	};

	duart: serial@80074000 {
	pinctrl-names = "default";
	pinctrl-0 = <&duart_pins_a>;
	status = "okay";
	};

	auart0: serial@8006a000 {
	pinctrl-names = "default";
	pinctrl-0 = <&auart0_pins_a>;
	status = "okay";
	};

	auart1: serial@8006c000 {
	pinctrl-names = "default";
	pinctrl-0 = <&auart1_2pins_a>;
	status = "okay";
	};

	auart2: serial@8006e000 {
	pinctrl-names = "default";
	pinctrl-0 = <&auart2_2pins_a>;
	status = "okay";
	};
	+
	+ usbphy1: usbphy@8007e000 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&usb1_pins_a>;
	+ status = "okay";
	+ };
	};
	};

	ahb@80080000 {
	+ usb1: usb@80090000 {
	+ status = "okay";
	+ };
	+
	mac0: ethernet@800f0000 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&mac0_pins_a>;
	status = "okay";
	};
	};

	regulators {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	reg_3p3v: regulator@0 {
	compatible = "regulator-fixed";
	reg = <0>;
	regulator-name = "3P3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};
	};

	sound {
	compatible = "bluegiga,apx4devkit-sgtl5000",
	"fsl,mxs-audio-sgtl5000";
	model = "apx4devkit-sgtl5000";
	saif-controllers = <&saif0 &saif1>;
	audio-codec = <&sgtl5000>;
	};

	leds {
	compatible = "gpio-leds";

	user {
	label = "Heartbeat";
	gpios = <&gpio3 28 0>;
	linux,default-trigger = "heartbeat";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx28.dtsi b/sys/gnu/dts/arm/imx28.dtsi
	index e14d8ef0158b..a1cbbeb39a4f 100644
	--- a/sys/gnu/dts/arm/imx28.dtsi
	+++ b/sys/gnu/dts/arm/imx28.dtsi
	@@ -1,1330 +1,1330 @@
	// SPDX-License-Identifier: GPL-2.0+
	//
	// Copyright 2012 Freescale Semiconductor, Inc.

	#include <dt-bindings/gpio/gpio.h>
	#include "imx28-pinfunc.h"

	/ {
	#address-cells = <1>;
	#size-cells = <1>;

	interrupt-parent = <&icoll>;
	/*
	* The decompressor and also some bootloaders rely on a
	* pre-existing /chosen node to be available to insert the
	* command line and merge other ATAGS info.
	*/
	chosen {};

	aliases {
	ethernet0 = &mac0;
	ethernet1 = &mac1;
	gpio0 = &gpio0;
	gpio1 = &gpio1;
	gpio2 = &gpio2;
	gpio3 = &gpio3;
	gpio4 = &gpio4;
	saif0 = &saif0;
	saif1 = &saif1;
	serial0 = &auart0;
	serial1 = &auart1;
	serial2 = &auart2;
	serial3 = &auart3;
	serial4 = &auart4;
	spi0 = &ssp1;
	spi1 = &ssp2;
	usbphy0 = &usbphy0;
	usbphy1 = &usbphy1;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	compatible = "arm,arm926ej-s";
	device_type = "cpu";
	reg = <0>;
	};
	};

	apb@80000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x80000000 0x80000>;
	ranges;

	apbh@80000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x80000000 0x3c900>;
	ranges;

	icoll: interrupt-controller@80000000 {
	compatible = "fsl,imx28-icoll", "fsl,icoll";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x80000000 0x2000>;
	};

	hsadc: hsadc@80002000 {
	reg = <0x80002000 0x2000>;
	interrupts = <13>;
	dmas = <&dma_apbh 12>;
	dma-names = "rx";
	status = "disabled";
	};

	dma_apbh: dma-apbh@80004000 {
	compatible = "fsl,imx28-dma-apbh";
	reg = <0x80004000 0x2000>;
	interrupts = <82 83 84 85
	88 88 88 88
	88 88 88 88
	87 86 0 0>;
	interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
	"gpmi0", "gmpi1", "gpmi2", "gmpi3",
	"gpmi4", "gmpi5", "gpmi6", "gmpi7",
	"hsadc", "lcdif", "empty", "empty";
	#dma-cells = <1>;
	dma-channels = <16>;
	clocks = <&clks 25>;
	};

	perfmon: perfmon@80006000 {
	reg = <0x80006000 0x800>;
	interrupts = <27>;
	status = "disabled";
	};

	gpmi: gpmi-nand@8000c000 {
	compatible = "fsl,imx28-gpmi-nand";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
	reg-names = "gpmi-nand", "bch";
	interrupts = <41>;
	interrupt-names = "bch";
	clocks = <&clks 50>;
	clock-names = "gpmi_io";
	dmas = <&dma_apbh 4>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	ssp0: spi@80010000 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x80010000 0x2000>;
	interrupts = <96>;
	clocks = <&clks 46>;
	dmas = <&dma_apbh 0>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	ssp1: spi@80012000 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x80012000 0x2000>;
	interrupts = <97>;
	clocks = <&clks 47>;
	dmas = <&dma_apbh 1>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	ssp2: spi@80014000 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x80014000 0x2000>;
	interrupts = <98>;
	clocks = <&clks 48>;
	dmas = <&dma_apbh 2>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	ssp3: spi@80016000 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x80016000 0x2000>;
	interrupts = <99>;
	clocks = <&clks 49>;
	dmas = <&dma_apbh 3>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	pinctrl: pinctrl@80018000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx28-pinctrl", "simple-bus";
	reg = <0x80018000 0x2000>;

	gpio0: gpio@0 {
	compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
	reg = <0>;
	interrupts = <127>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio1: gpio@1 {
	compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
	reg = <1>;
	interrupts = <126>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio@2 {
	compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
	reg = <2>;
	interrupts = <125>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio@3 {
	compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
	reg = <3>;
	interrupts = <124>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio4: gpio@4 {
	compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
	reg = <4>;
	interrupts = <123>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	duart_pins_a: duart@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_PWM0__DUART_RX
	MX28_PAD_PWM1__DUART_TX
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	duart_pins_b: duart@1 {
	reg = <1>;
	fsl,pinmux-ids = <
	MX28_PAD_AUART0_CTS__DUART_RX
	MX28_PAD_AUART0_RTS__DUART_TX
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	duart_4pins_a: duart-4pins@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_AUART0_CTS__DUART_RX
	MX28_PAD_AUART0_RTS__DUART_TX
	MX28_PAD_AUART0_RX__DUART_CTS
	MX28_PAD_AUART0_TX__DUART_RTS
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	gpmi_pins_a: gpmi-nand@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_GPMI_D00__GPMI_D0
	MX28_PAD_GPMI_D01__GPMI_D1
	MX28_PAD_GPMI_D02__GPMI_D2
	MX28_PAD_GPMI_D03__GPMI_D3
	MX28_PAD_GPMI_D04__GPMI_D4
	MX28_PAD_GPMI_D05__GPMI_D5
	MX28_PAD_GPMI_D06__GPMI_D6
	MX28_PAD_GPMI_D07__GPMI_D7
	MX28_PAD_GPMI_CE0N__GPMI_CE0N
	MX28_PAD_GPMI_RDY0__GPMI_READY0
	MX28_PAD_GPMI_RDN__GPMI_RDN
	MX28_PAD_GPMI_WRN__GPMI_WRN
	MX28_PAD_GPMI_ALE__GPMI_ALE
	MX28_PAD_GPMI_CLE__GPMI_CLE
	MX28_PAD_GPMI_RESETN__GPMI_RESETN
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	gpmi_status_cfg: gpmi-status-cfg@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_GPMI_RDN__GPMI_RDN
	MX28_PAD_GPMI_WRN__GPMI_WRN
	MX28_PAD_GPMI_RESETN__GPMI_RESETN
	>;
	fsl,drive-strength = <MXS_DRIVE_12mA>;
	};

	auart0_pins_a: auart0@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_AUART0_RX__AUART0_RX
	MX28_PAD_AUART0_TX__AUART0_TX
	MX28_PAD_AUART0_CTS__AUART0_CTS
	MX28_PAD_AUART0_RTS__AUART0_RTS
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	auart0_2pins_a: auart0-2pins@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_AUART0_RX__AUART0_RX
	MX28_PAD_AUART0_TX__AUART0_TX
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	auart1_pins_a: auart1@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_AUART1_RX__AUART1_RX
	MX28_PAD_AUART1_TX__AUART1_TX
	MX28_PAD_AUART1_CTS__AUART1_CTS
	MX28_PAD_AUART1_RTS__AUART1_RTS
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	auart1_2pins_a: auart1-2pins@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_AUART1_RX__AUART1_RX
	MX28_PAD_AUART1_TX__AUART1_TX
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	auart2_2pins_a: auart2-2pins@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_SSP2_SCK__AUART2_RX
	MX28_PAD_SSP2_MOSI__AUART2_TX
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	auart2_2pins_b: auart2-2pins@1 {
	reg = <1>;
	fsl,pinmux-ids = <
	MX28_PAD_AUART2_RX__AUART2_RX
	MX28_PAD_AUART2_TX__AUART2_TX
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	auart2_pins_a: auart2-pins@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_AUART2_RX__AUART2_RX
	MX28_PAD_AUART2_TX__AUART2_TX
	MX28_PAD_AUART2_CTS__AUART2_CTS
	MX28_PAD_AUART2_RTS__AUART2_RTS
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	auart3_pins_a: auart3@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_AUART3_RX__AUART3_RX
	MX28_PAD_AUART3_TX__AUART3_TX
	MX28_PAD_AUART3_CTS__AUART3_CTS
	MX28_PAD_AUART3_RTS__AUART3_RTS
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	auart3_2pins_a: auart3-2pins@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_SSP2_MISO__AUART3_RX
	MX28_PAD_SSP2_SS0__AUART3_TX
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	auart3_2pins_b: auart3-2pins@1 {
	reg = <1>;
	fsl,pinmux-ids = <
	MX28_PAD_AUART3_RX__AUART3_RX
	MX28_PAD_AUART3_TX__AUART3_TX
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	auart4_2pins_a: auart4@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_SSP3_SCK__AUART4_TX
	MX28_PAD_SSP3_MOSI__AUART4_RX
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	auart4_2pins_b: auart4@1 {
	reg = <1>;
	fsl,pinmux-ids = <
	MX28_PAD_AUART0_CTS__AUART4_RX
	MX28_PAD_AUART0_RTS__AUART4_TX
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	mac0_pins_a: mac0@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_ENET0_MDC__ENET0_MDC
	MX28_PAD_ENET0_MDIO__ENET0_MDIO
	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
	MX28_PAD_ENET0_RXD0__ENET0_RXD0
	MX28_PAD_ENET0_RXD1__ENET0_RXD1
	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
	MX28_PAD_ENET0_TXD0__ENET0_TXD0
	MX28_PAD_ENET0_TXD1__ENET0_TXD1
	MX28_PAD_ENET_CLK__CLKCTRL_ENET
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	mac0_pins_b: mac0@1 {
	reg = <1>;
	fsl,pinmux-ids = <
	MX28_PAD_ENET0_MDC__ENET0_MDC
	MX28_PAD_ENET0_MDIO__ENET0_MDIO
	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
	MX28_PAD_ENET0_RXD0__ENET0_RXD0
	MX28_PAD_ENET0_RXD1__ENET0_RXD1
	MX28_PAD_ENET0_RXD2__ENET0_RXD2
	MX28_PAD_ENET0_RXD3__ENET0_RXD3
	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
	MX28_PAD_ENET0_TXD0__ENET0_TXD0
	MX28_PAD_ENET0_TXD1__ENET0_TXD1
	MX28_PAD_ENET0_TXD2__ENET0_TXD2
	MX28_PAD_ENET0_TXD3__ENET0_TXD3
	MX28_PAD_ENET_CLK__CLKCTRL_ENET
	MX28_PAD_ENET0_COL__ENET0_COL
	MX28_PAD_ENET0_CRS__ENET0_CRS
	MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
	MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	mac1_pins_a: mac1@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_ENET0_CRS__ENET1_RX_EN
	MX28_PAD_ENET0_RXD2__ENET1_RXD0
	MX28_PAD_ENET0_RXD3__ENET1_RXD1
	MX28_PAD_ENET0_COL__ENET1_TX_EN
	MX28_PAD_ENET0_TXD2__ENET1_TXD0
	MX28_PAD_ENET0_TXD3__ENET1_TXD1
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	mmc0_8bit_pins_a: mmc0-8bit@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_SSP0_DATA0__SSP0_D0
	MX28_PAD_SSP0_DATA1__SSP0_D1
	MX28_PAD_SSP0_DATA2__SSP0_D2
	MX28_PAD_SSP0_DATA3__SSP0_D3
	MX28_PAD_SSP0_DATA4__SSP0_D4
	MX28_PAD_SSP0_DATA5__SSP0_D5
	MX28_PAD_SSP0_DATA6__SSP0_D6
	MX28_PAD_SSP0_DATA7__SSP0_D7
	MX28_PAD_SSP0_CMD__SSP0_CMD
	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
	MX28_PAD_SSP0_SCK__SSP0_SCK
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	mmc0_4bit_pins_a: mmc0-4bit@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_SSP0_DATA0__SSP0_D0
	MX28_PAD_SSP0_DATA1__SSP0_D1
	MX28_PAD_SSP0_DATA2__SSP0_D2
	MX28_PAD_SSP0_DATA3__SSP0_D3
	MX28_PAD_SSP0_CMD__SSP0_CMD
	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
	MX28_PAD_SSP0_SCK__SSP0_SCK
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	mmc0_cd_cfg: mmc0-cd-cfg@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
	>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	mmc0_sck_cfg: mmc0-sck-cfg@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_SSP0_SCK__SSP0_SCK
	>;
	fsl,drive-strength = <MXS_DRIVE_12mA>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	mmc1_4bit_pins_a: mmc1-4bit@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_GPMI_D00__SSP1_D0
	MX28_PAD_GPMI_D01__SSP1_D1
	MX28_PAD_GPMI_D02__SSP1_D2
	MX28_PAD_GPMI_D03__SSP1_D3
	MX28_PAD_GPMI_RDY1__SSP1_CMD
	MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
	MX28_PAD_GPMI_WRN__SSP1_SCK
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	mmc1_cd_cfg: mmc1-cd-cfg@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
	>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	mmc1_sck_cfg: mmc1-sck-cfg@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_GPMI_WRN__SSP1_SCK
	>;
	fsl,drive-strength = <MXS_DRIVE_12mA>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};


	mmc2_4bit_pins_a: mmc2-4bit@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_SSP0_DATA4__SSP2_D0
	MX28_PAD_SSP1_SCK__SSP2_D1
	MX28_PAD_SSP1_CMD__SSP2_D2
	MX28_PAD_SSP0_DATA5__SSP2_D3
	MX28_PAD_SSP0_DATA6__SSP2_CMD
	MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
	MX28_PAD_SSP0_DATA7__SSP2_SCK
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	mmc2_4bit_pins_b: mmc2-4bit@1 {
	reg = <1>;
	fsl,pinmux-ids = <
	MX28_PAD_SSP2_SCK__SSP2_SCK
	MX28_PAD_SSP2_MOSI__SSP2_CMD
	MX28_PAD_SSP2_MISO__SSP2_D0
	MX28_PAD_SSP2_SS0__SSP2_D3
	MX28_PAD_SSP2_SS1__SSP2_D1
	MX28_PAD_SSP2_SS2__SSP2_D2
	MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	mmc2_cd_cfg: mmc2-cd-cfg@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
	>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	mmc2_sck_cfg_a: mmc2-sck-cfg@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_SSP0_DATA7__SSP2_SCK
	>;
	fsl,drive-strength = <MXS_DRIVE_12mA>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	mmc2_sck_cfg_b: mmc2-sck-cfg@1 {
	reg = <1>;
	fsl,pinmux-ids = <
	MX28_PAD_SSP2_SCK__SSP2_SCK
	>;
	fsl,drive-strength = <MXS_DRIVE_12mA>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	i2c0_pins_a: i2c0@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_I2C0_SCL__I2C0_SCL
	MX28_PAD_I2C0_SDA__I2C0_SDA
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	i2c0_pins_b: i2c0@1 {
	reg = <1>;
	fsl,pinmux-ids = <
	MX28_PAD_AUART0_RX__I2C0_SCL
	MX28_PAD_AUART0_TX__I2C0_SDA
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	i2c1_pins_a: i2c1@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_PWM0__I2C1_SCL
	MX28_PAD_PWM1__I2C1_SDA
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	i2c1_pins_b: i2c1@1 {
	reg = <1>;
	fsl,pinmux-ids = <
	MX28_PAD_AUART2_CTS__I2C1_SCL
	MX28_PAD_AUART2_RTS__I2C1_SDA
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	saif0_pins_a: saif0@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
	MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
	MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
	MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
	>;
	fsl,drive-strength = <MXS_DRIVE_12mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	saif0_pins_b: saif0@1 {
	reg = <1>;
	fsl,pinmux-ids = <
	MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
	MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
	MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
	>;
	fsl,drive-strength = <MXS_DRIVE_12mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	saif1_pins_a: saif1@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
	>;
	fsl,drive-strength = <MXS_DRIVE_12mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	pwm0_pins_a: pwm0@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_PWM0__PWM_0
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	pwm2_pins_a: pwm2@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_PWM2__PWM_2
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	pwm3_pins_a: pwm3@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_PWM3__PWM_3
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	pwm3_pins_b: pwm3@1 {
	reg = <1>;
	fsl,pinmux-ids = <
	MX28_PAD_SAIF0_MCLK__PWM_3
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	pwm4_pins_a: pwm4@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_PWM4__PWM_4
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	lcdif_24bit_pins_a: lcdif-24bit@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_LCD_D00__LCD_D0
	MX28_PAD_LCD_D01__LCD_D1
	MX28_PAD_LCD_D02__LCD_D2
	MX28_PAD_LCD_D03__LCD_D3
	MX28_PAD_LCD_D04__LCD_D4
	MX28_PAD_LCD_D05__LCD_D5
	MX28_PAD_LCD_D06__LCD_D6
	MX28_PAD_LCD_D07__LCD_D7
	MX28_PAD_LCD_D08__LCD_D8
	MX28_PAD_LCD_D09__LCD_D9
	MX28_PAD_LCD_D10__LCD_D10
	MX28_PAD_LCD_D11__LCD_D11
	MX28_PAD_LCD_D12__LCD_D12
	MX28_PAD_LCD_D13__LCD_D13
	MX28_PAD_LCD_D14__LCD_D14
	MX28_PAD_LCD_D15__LCD_D15
	MX28_PAD_LCD_D16__LCD_D16
	MX28_PAD_LCD_D17__LCD_D17
	MX28_PAD_LCD_D18__LCD_D18
	MX28_PAD_LCD_D19__LCD_D19
	MX28_PAD_LCD_D20__LCD_D20
	MX28_PAD_LCD_D21__LCD_D21
	MX28_PAD_LCD_D22__LCD_D22
	MX28_PAD_LCD_D23__LCD_D23
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	lcdif_18bit_pins_a: lcdif-18bit@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_LCD_D00__LCD_D0
	MX28_PAD_LCD_D01__LCD_D1
	MX28_PAD_LCD_D02__LCD_D2
	MX28_PAD_LCD_D03__LCD_D3
	MX28_PAD_LCD_D04__LCD_D4
	MX28_PAD_LCD_D05__LCD_D5
	MX28_PAD_LCD_D06__LCD_D6
	MX28_PAD_LCD_D07__LCD_D7
	MX28_PAD_LCD_D08__LCD_D8
	MX28_PAD_LCD_D09__LCD_D9
	MX28_PAD_LCD_D10__LCD_D10
	MX28_PAD_LCD_D11__LCD_D11
	MX28_PAD_LCD_D12__LCD_D12
	MX28_PAD_LCD_D13__LCD_D13
	MX28_PAD_LCD_D14__LCD_D14
	MX28_PAD_LCD_D15__LCD_D15
	MX28_PAD_LCD_D16__LCD_D16
	MX28_PAD_LCD_D17__LCD_D17
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	lcdif_16bit_pins_a: lcdif-16bit@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_LCD_D00__LCD_D0
	MX28_PAD_LCD_D01__LCD_D1
	MX28_PAD_LCD_D02__LCD_D2
	MX28_PAD_LCD_D03__LCD_D3
	MX28_PAD_LCD_D04__LCD_D4
	MX28_PAD_LCD_D05__LCD_D5
	MX28_PAD_LCD_D06__LCD_D6
	MX28_PAD_LCD_D07__LCD_D7
	MX28_PAD_LCD_D08__LCD_D8
	MX28_PAD_LCD_D09__LCD_D9
	MX28_PAD_LCD_D10__LCD_D10
	MX28_PAD_LCD_D11__LCD_D11
	MX28_PAD_LCD_D12__LCD_D12
	MX28_PAD_LCD_D13__LCD_D13
	MX28_PAD_LCD_D14__LCD_D14
	MX28_PAD_LCD_D15__LCD_D15
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	lcdif_sync_pins_a: lcdif-sync@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_LCD_RS__LCD_DOTCLK
	MX28_PAD_LCD_CS__LCD_ENABLE
	MX28_PAD_LCD_RD_E__LCD_VSYNC
	MX28_PAD_LCD_WR_RWN__LCD_HSYNC
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	can0_pins_a: can0@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_GPMI_RDY2__CAN0_TX
	MX28_PAD_GPMI_RDY3__CAN0_RX
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	can1_pins_a: can1@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_GPMI_CE2N__CAN1_TX
	MX28_PAD_GPMI_CE3N__CAN1_RX
	>;
	fsl,drive-strength = <MXS_DRIVE_4mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	spi2_pins_a: spi2@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_SSP2_SCK__SSP2_SCK
	MX28_PAD_SSP2_MOSI__SSP2_CMD
	MX28_PAD_SSP2_MISO__SSP2_D0
	MX28_PAD_SSP2_SS0__SSP2_D3
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	spi3_pins_a: spi3@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_AUART2_RX__SSP3_D4
	MX28_PAD_AUART2_TX__SSP3_D5
	MX28_PAD_SSP3_SCK__SSP3_SCK
	MX28_PAD_SSP3_MOSI__SSP3_CMD
	MX28_PAD_SSP3_MISO__SSP3_D0
	MX28_PAD_SSP3_SS0__SSP3_D3
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	spi3_pins_b: spi3@1 {
	reg = <1>;
	fsl,pinmux-ids = <
	MX28_PAD_SSP3_SCK__SSP3_SCK
	MX28_PAD_SSP3_MOSI__SSP3_CMD
	MX28_PAD_SSP3_MISO__SSP3_D0
	MX28_PAD_SSP3_SS0__SSP3_D3
	>;
	fsl,drive-strength = <MXS_DRIVE_8mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	usb0_pins_a: usb0@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
	>;
	fsl,drive-strength = <MXS_DRIVE_12mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	usb0_pins_b: usb0@1 {
	reg = <1>;
	fsl,pinmux-ids = <
	MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
	>;
	fsl,drive-strength = <MXS_DRIVE_12mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	usb1_pins_a: usb1@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
	>;
	fsl,drive-strength = <MXS_DRIVE_12mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	usb0_id_pins_a: usb0id@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_AUART1_RTS__USB0_ID
	>;
	fsl,drive-strength = <MXS_DRIVE_12mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	usb0_id_pins_b: usb0id1@0 {
	reg = <0>;
	fsl,pinmux-ids = <
	MX28_PAD_PWM2__USB0_ID
	>;
	fsl,drive-strength = <MXS_DRIVE_12mA>;
	fsl,voltage = <MXS_VOLTAGE_HIGH>;
	fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	};

	digctl: digctl@8001c000 {
	compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
	reg = <0x8001c000 0x2000>;
	interrupts = <89>;
	status = "disabled";
	};

	etm: etm@80022000 {
	reg = <0x80022000 0x2000>;
	status = "disabled";
	};

	dma_apbx: dma-apbx@80024000 {
	compatible = "fsl,imx28-dma-apbx";
	reg = <0x80024000 0x2000>;
	interrupts = <78 79 66 0
	80 81 68 69
	70 71 72 73
	74 75 76 77>;
	interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
	"saif0", "saif1", "i2c0", "i2c1",
	"auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
	"auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
	#dma-cells = <1>;
	dma-channels = <16>;
	clocks = <&clks 26>;
	};

	- dcp: dcp@80028000 {
	+ dcp: crypto@80028000 {
	compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
	reg = <0x80028000 0x2000>;
	interrupts = <52 53 54>;
	status = "okay";
	};

	pxp: pxp@8002a000 {
	reg = <0x8002a000 0x2000>;
	interrupts = <39>;
	status = "disabled";
	};

	ocotp: ocotp@8002c000 {
	compatible = "fsl,imx28-ocotp", "fsl,ocotp";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x8002c000 0x2000>;
	clocks = <&clks 25>;
	};

	axi-ahb@8002e000 {
	reg = <0x8002e000 0x2000>;
	status = "disabled";
	};

	lcdif: lcdif@80030000 {
	compatible = "fsl,imx28-lcdif";
	reg = <0x80030000 0x2000>;
	interrupts = <38>;
	clocks = <&clks 55>;
	dmas = <&dma_apbh 13>;
	dma-names = "rx";
	status = "disabled";
	};

	can0: can@80032000 {
	compatible = "fsl,imx28-flexcan";
	reg = <0x80032000 0x2000>;
	interrupts = <8>;
	clocks = <&clks 58>, <&clks 58>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	can1: can@80034000 {
	compatible = "fsl,imx28-flexcan";
	reg = <0x80034000 0x2000>;
	interrupts = <9>;
	clocks = <&clks 59>, <&clks 59>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	simdbg: simdbg@8003c000 {
	reg = <0x8003c000 0x200>;
	status = "disabled";
	};

	simgpmisel: simgpmisel@8003c200 {
	reg = <0x8003c200 0x100>;
	status = "disabled";
	};

	simsspsel: simsspsel@8003c300 {
	reg = <0x8003c300 0x100>;
	status = "disabled";
	};

	simmemsel: simmemsel@8003c400 {
	reg = <0x8003c400 0x100>;
	status = "disabled";
	};

	gpiomon: gpiomon@8003c500 {
	reg = <0x8003c500 0x100>;
	status = "disabled";
	};

	simenet: simenet@8003c700 {
	reg = <0x8003c700 0x100>;
	status = "disabled";
	};

	armjtag: armjtag@8003c800 {
	reg = <0x8003c800 0x100>;
	status = "disabled";
	};
	};

	apbx@80040000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x80040000 0x40000>;
	ranges;

	clks: clkctrl@80040000 {
	compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
	reg = <0x80040000 0x2000>;
	#clock-cells = <1>;
	};

	saif0: saif@80042000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx28-saif";
	reg = <0x80042000 0x2000>;
	interrupts = <59>;
	#clock-cells = <0>;
	clocks = <&clks 53>;
	dmas = <&dma_apbx 4>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	power: power@80044000 {
	reg = <0x80044000 0x2000>;
	status = "disabled";
	};

	saif1: saif@80046000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx28-saif";
	reg = <0x80046000 0x2000>;
	interrupts = <58>;
	clocks = <&clks 54>;
	dmas = <&dma_apbx 5>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	lradc: lradc@80050000 {
	compatible = "fsl,imx28-lradc";
	reg = <0x80050000 0x2000>;
	interrupts = <10 14 15 16 17 18 19
	20 21 22 23 24 25>;
	status = "disabled";
	clocks = <&clks 41>;
	#io-channel-cells = <1>;
	};

	spdif: spdif@80054000 {
	reg = <0x80054000 0x2000>;
	interrupts = <45>;
	dmas = <&dma_apbx 2>;
	dma-names = "tx";
	status = "disabled";
	};

	mxs_rtc: rtc@80056000 {
	compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
	reg = <0x80056000 0x2000>;
	interrupts = <29>;
	};

	i2c0: i2c@80058000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx28-i2c";
	reg = <0x80058000 0x2000>;
	interrupts = <111>;
	clock-frequency = <100000>;
	dmas = <&dma_apbx 6>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	i2c1: i2c@8005a000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx28-i2c";
	reg = <0x8005a000 0x2000>;
	interrupts = <110>;
	clock-frequency = <100000>;
	dmas = <&dma_apbx 7>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	pwm: pwm@80064000 {
	compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
	reg = <0x80064000 0x2000>;
	clocks = <&clks 44>;
	#pwm-cells = <2>;
	fsl,pwm-number = <8>;
	status = "disabled";
	};

	timer: timrot@80068000 {
	compatible = "fsl,imx28-timrot", "fsl,timrot";
	reg = <0x80068000 0x2000>;
	interrupts = <48 49 50 51>;
	clocks = <&clks 26>;
	};

	auart0: serial@8006a000 {
	compatible = "fsl,imx28-auart", "fsl,imx23-auart";
	reg = <0x8006a000 0x2000>;
	interrupts = <112>;
	dmas = <&dma_apbx 8>, <&dma_apbx 9>;
	dma-names = "rx", "tx";
	clocks = <&clks 45>;
	status = "disabled";
	};

	auart1: serial@8006c000 {
	compatible = "fsl,imx28-auart", "fsl,imx23-auart";
	reg = <0x8006c000 0x2000>;
	interrupts = <113>;
	dmas = <&dma_apbx 10>, <&dma_apbx 11>;
	dma-names = "rx", "tx";
	clocks = <&clks 45>;
	status = "disabled";
	};

	auart2: serial@8006e000 {
	compatible = "fsl,imx28-auart", "fsl,imx23-auart";
	reg = <0x8006e000 0x2000>;
	interrupts = <114>;
	dmas = <&dma_apbx 12>, <&dma_apbx 13>;
	dma-names = "rx", "tx";
	clocks = <&clks 45>;
	status = "disabled";
	};

	auart3: serial@80070000 {
	compatible = "fsl,imx28-auart", "fsl,imx23-auart";
	reg = <0x80070000 0x2000>;
	interrupts = <115>;
	dmas = <&dma_apbx 14>, <&dma_apbx 15>;
	dma-names = "rx", "tx";
	clocks = <&clks 45>;
	status = "disabled";
	};

	auart4: serial@80072000 {
	compatible = "fsl,imx28-auart", "fsl,imx23-auart";
	reg = <0x80072000 0x2000>;
	interrupts = <116>;
	dmas = <&dma_apbx 0>, <&dma_apbx 1>;
	dma-names = "rx", "tx";
	clocks = <&clks 45>;
	status = "disabled";
	};

	duart: serial@80074000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x80074000 0x1000>;
	interrupts = <47>;
	clocks = <&clks 45>, <&clks 26>;
	clock-names = "uart", "apb_pclk";
	status = "disabled";
	};

	usbphy0: usbphy@8007c000 {
	compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
	reg = <0x8007c000 0x2000>;
	clocks = <&clks 62>;
	status = "disabled";
	};

	usbphy1: usbphy@8007e000 {
	compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
	reg = <0x8007e000 0x2000>;
	clocks = <&clks 63>;
	status = "disabled";
	};
	};
	};

	ahb@80080000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x80080000 0x80000>;
	ranges;

	usb0: usb@80080000 {
	compatible = "fsl,imx28-usb", "fsl,imx27-usb";
	reg = <0x80080000 0x10000>;
	interrupts = <93>;
	clocks = <&clks 60>;
	fsl,usbphy = <&usbphy0>;
	status = "disabled";
	};

	usb1: usb@80090000 {
	compatible = "fsl,imx28-usb", "fsl,imx27-usb";
	reg = <0x80090000 0x10000>;
	interrupts = <92>;
	clocks = <&clks 61>;
	fsl,usbphy = <&usbphy1>;
	dr_mode = "host";
	status = "disabled";
	};

	dflpt: dflpt@800c0000 {
	reg = <0x800c0000 0x10000>;
	status = "disabled";
	};

	mac0: ethernet@800f0000 {
	compatible = "fsl,imx28-fec";
	reg = <0x800f0000 0x4000>;
	interrupts = <101>;
	clocks = <&clks 57>, <&clks 57>, <&clks 64>;
	clock-names = "ipg", "ahb", "enet_out";
	status = "disabled";
	};

	mac1: ethernet@800f4000 {
	compatible = "fsl,imx28-fec";
	reg = <0x800f4000 0x4000>;
	interrupts = <102>;
	clocks = <&clks 57>, <&clks 57>;
	clock-names = "ipg", "ahb";
	status = "disabled";
	};

	etn_switch: switch@800f8000 {
	reg = <0x800f8000 0x8000>;
	status = "disabled";
	};
	};

	iio-hwmon {
	compatible = "iio-hwmon";
	io-channels = <&lradc 8>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx31.dtsi b/sys/gnu/dts/arm/imx31.dtsi
	index 6b62f0745b82..18270ec648fe 100644
	--- a/sys/gnu/dts/arm/imx31.dtsi
	+++ b/sys/gnu/dts/arm/imx31.dtsi
	@@ -1,370 +1,370 @@
	// SPDX-License-Identifier: GPL-2.0+
	//
	// Copyright 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
	// Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	* The decompressor and also some bootloaders rely on a
	* pre-existing /chosen node to be available to insert the
	* command line and merge other ATAGS info.
	*/
	chosen {};

	aliases {
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	i2c2 = &i2c3;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	serial4 = &uart5;
	spi0 = &spi1;
	spi1 = &spi2;
	spi2 = &spi3;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	compatible = "arm,arm1136jf-s";
	device_type = "cpu";
	reg = <0>;
	};
	};

	avic: interrupt-controller@68000000 {
	compatible = "fsl,imx31-avic", "fsl,avic";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x68000000 0x100000>;
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&avic>;
	ranges;

	iram: sram@1fffc000 {
	compatible = "mmio-sram";
	reg = <0x1fffc000 0x4000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x1fffc000 0x4000>;
	};

	- aips@43f00000 { /* AIPS1 */
	+ bus@43f00000 { /* AIPS1 */
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x43f00000 0x100000>;
	ranges;

	i2c1: i2c@43f80000 {
	compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
	reg = <0x43f80000 0x4000>;
	interrupts = <10>;
	clocks = <&clks 33>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c3: i2c@43f84000 {
	compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
	reg = <0x43f84000 0x4000>;
	interrupts = <3>;
	clocks = <&clks 35>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	ata: ata@43f8c000 {
	compatible = "fsl,imx31-pata", "fsl,imx27-pata";
	reg = <0x43f8c000 0x4000>;
	interrupts = <15>;
	clocks = <&clks 26>;
	status = "disabled";
	};

	uart1: serial@43f90000 {
	compatible = "fsl,imx31-uart", "fsl,imx21-uart";
	reg = <0x43f90000 0x4000>;
	interrupts = <45>;
	clocks = <&clks 10>, <&clks 30>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart2: serial@43f94000 {
	compatible = "fsl,imx31-uart", "fsl,imx21-uart";
	reg = <0x43f94000 0x4000>;
	interrupts = <32>;
	clocks = <&clks 10>, <&clks 31>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	i2c2: i2c@43f98000 {
	compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
	reg = <0x43f98000 0x4000>;
	interrupts = <4>;
	clocks = <&clks 34>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi1: spi@43fa4000 {
	compatible = "fsl,imx31-cspi";
	reg = <0x43fa4000 0x4000>;
	interrupts = <14>;
	clocks = <&clks 10>, <&clks 53>;
	clock-names = "ipg", "per";
	dmas = <&sdma 8 8 0>, <&sdma 9 8 0>;
	dma-names = "rx", "tx";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	kpp: kpp@43fa8000 {
	compatible = "fsl,imx31-kpp", "fsl,imx21-kpp";
	reg = <0x43fa8000 0x4000>;
	interrupts = <24>;
	clocks = <&clks 46>;
	status = "disabled";
	};

	uart4: serial@43fb0000 {
	compatible = "fsl,imx31-uart", "fsl,imx21-uart";
	reg = <0x43fb0000 0x4000>;
	clocks = <&clks 10>, <&clks 49>;
	clock-names = "ipg", "per";
	interrupts = <46>;
	status = "disabled";
	};

	uart5: serial@43fb4000 {
	compatible = "fsl,imx31-uart", "fsl,imx21-uart";
	reg = <0x43fb4000 0x4000>;
	interrupts = <47>;
	clocks = <&clks 10>, <&clks 50>;
	clock-names = "ipg", "per";
	status = "disabled";
	};
	};

	spba@50000000 {
	compatible = "fsl,spba-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x50000000 0x100000>;
	ranges;

	sdhci1: sdhci@50004000 {
	compatible = "fsl,imx31-mmc";
	reg = <0x50004000 0x4000>;
	interrupts = <9>;
	clocks = <&clks 10>, <&clks 20>;
	clock-names = "ipg", "per";
	dmas = <&sdma 20 3 0>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	sdhci2: sdhci@50008000 {
	compatible = "fsl,imx31-mmc";
	reg = <0x50008000 0x4000>;
	interrupts = <8>;
	clocks = <&clks 10>, <&clks 21>;
	clock-names = "ipg", "per";
	dmas = <&sdma 21 3 0>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	uart3: serial@5000c000 {
	compatible = "fsl,imx31-uart", "fsl,imx21-uart";
	reg = <0x5000c000 0x4000>;
	interrupts = <18>;
	clocks = <&clks 10>, <&clks 48>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	spi2: spi@50010000 {
	compatible = "fsl,imx31-cspi";
	reg = <0x50010000 0x4000>;
	interrupts = <13>;
	clocks = <&clks 10>, <&clks 54>;
	clock-names = "ipg", "per";
	dmas = <&sdma 6 8 0>, <&sdma 7 8 0>;
	dma-names = "rx", "tx";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	iim: iim@5001c000 {
	compatible = "fsl,imx31-iim", "fsl,imx27-iim";
	reg = <0x5001c000 0x1000>;
	interrupts = <19>;
	clocks = <&clks 25>;
	};
	};

	- aips@53f00000 { /* AIPS2 */
	+ bus@53f00000 { /* AIPS2 */
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x53f00000 0x100000>;
	ranges;

	clks: ccm@53f80000{
	compatible = "fsl,imx31-ccm";
	reg = <0x53f80000 0x4000>;
	interrupts = <31>, <53>;
	#clock-cells = <1>;
	};

	spi3: spi@53f84000 {
	compatible = "fsl,imx31-cspi";
	reg = <0x53f84000 0x4000>;
	interrupts = <17>;
	clocks = <&clks 10>, <&clks 28>;
	clock-names = "ipg", "per";
	dmas = <&sdma 10 8 0>, <&sdma 11 8 0>;
	dma-names = "rx", "tx";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	gpt: timer@53f90000 {
	compatible = "fsl,imx31-gpt";
	reg = <0x53f90000 0x4000>;
	interrupts = <29>;
	clocks = <&clks 10>, <&clks 22>;
	clock-names = "ipg", "per";
	};

	gpio3: gpio@53fa4000 {
	compatible = "fsl,imx31-gpio";
	reg = <0x53fa4000 0x4000>;
	interrupts = <56>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	rng@53fb0000 {
	compatible = "fsl,imx31-rnga";
	reg = <0x53fb0000 0x4000>;
	interrupts = <22>;
	clocks = <&clks 29>;
	};

	gpio1: gpio@53fcc000 {
	compatible = "fsl,imx31-gpio";
	reg = <0x53fcc000 0x4000>;
	interrupts = <52>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio@53fd0000 {
	compatible = "fsl,imx31-gpio";
	reg = <0x53fd0000 0x4000>;
	interrupts = <51>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	sdma: sdma@53fd4000 {
	compatible = "fsl,imx31-sdma";
	reg = <0x53fd4000 0x4000>;
	interrupts = <34>;
	clocks = <&clks 10>, <&clks 27>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin";
	};

	rtc: rtc@53fd8000 {
	compatible = "fsl,imx31-rtc", "fsl,imx21-rtc";
	reg = <0x53fd8000 0x4000>;
	interrupts = <25>;
	clocks = <&clks 2>, <&clks 40>;
	clock-names = "ref", "ipg";
	};

	wdog: wdog@53fdc000 {
	compatible = "fsl,imx31-wdt", "fsl,imx21-wdt";
	reg = <0x53fdc000 0x4000>;
	clocks = <&clks 41>;
	};

	pwm: pwm@53fe0000 {
	compatible = "fsl,imx31-pwm", "fsl,imx27-pwm";
	reg = <0x53fe0000 0x4000>;
	interrupts = <26>;
	clocks = <&clks 10>, <&clks 42>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};
	};

	emi@b8000000 { /* External Memory Interface */
	compatible = "simple-bus";
	reg = <0xb8000000 0x5000>;
	ranges;
	#address-cells = <1>;
	#size-cells = <1>;

	nfc: nand@b8000000 {
	compatible = "fsl,imx31-nand", "fsl,imx27-nand";
	reg = <0xb8000000 0x1000>;
	interrupts = <33>;
	clocks = <&clks 9>;
	dmas = <&sdma 30 17 0>;
	dma-names = "rx-tx";
	#address-cells = <1>;
	#size-cells = <1>;
	status = "disabled";
	};

	weim: weim@b8002000 {
	compatible = "fsl,imx31-weim", "fsl,imx27-weim";
	reg = <0xb8002000 0x1000>;
	clocks = <&clks 56>;
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0xa0000000 0x08000000
	1 0 0xa8000000 0x08000000
	2 0 0xb0000000 0x02000000
	3 0 0xb2000000 0x02000000
	4 0 0xb4000000 0x02000000
	5 0 0xb6000000 0x02000000>;
	status = "disabled";
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx35.dtsi b/sys/gnu/dts/arm/imx35.dtsi
	index 9cbdc1a15cda..2ebf2c1fa682 100644
	--- a/sys/gnu/dts/arm/imx35.dtsi
	+++ b/sys/gnu/dts/arm/imx35.dtsi
	@@ -1,414 +1,414 @@
	// SPDX-License-Identifier: GPL-2.0
	//
	// Copyright 2012 Steffen Trumtrar, Pengutronix
	//
	// based on imx27.dtsi

	#include "imx35-pinfunc.h"

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	* The decompressor and also some bootloaders rely on a
	* pre-existing /chosen node to be available to insert the
	* command line and merge other ATAGS info.
	*/
	chosen {};

	aliases {
	ethernet0 = &fec;
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	i2c2 = &i2c3;
	mmc0 = &esdhc1;
	mmc1 = &esdhc2;
	mmc2 = &esdhc3;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	spi0 = &spi1;
	spi1 = &spi2;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	compatible = "arm,arm1136jf-s";
	device_type = "cpu";
	reg = <0>;
	};
	};

	avic: avic-interrupt-controller@68000000 {
	compatible = "fsl,imx35-avic", "fsl,avic";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x68000000 0x10000000>;
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&avic>;
	ranges;

	L2: l2-cache@30000000 {
	compatible = "arm,l210-cache";
	reg = <0x30000000 0x1000>;
	cache-unified;
	cache-level = <2>;
	};

	- aips1: aips@43f00000 {
	+ aips1: bus@43f00000 {
	compatible = "fsl,aips", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x43f00000 0x100000>;
	ranges;

	i2c1: i2c@43f80000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
	reg = <0x43f80000 0x4000>;
	clocks = <&clks 51>;
	clock-names = "ipg_per";
	interrupts = <10>;
	status = "disabled";
	};

	i2c3: i2c@43f84000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
	reg = <0x43f84000 0x4000>;
	clocks = <&clks 53>;
	clock-names = "ipg_per";
	interrupts = <3>;
	status = "disabled";
	};

	uart1: serial@43f90000 {
	compatible = "fsl,imx35-uart", "fsl,imx21-uart";
	reg = <0x43f90000 0x4000>;
	clocks = <&clks 9>, <&clks 70>;
	clock-names = "ipg", "per";
	interrupts = <45>;
	status = "disabled";
	};

	uart2: serial@43f94000 {
	compatible = "fsl,imx35-uart", "fsl,imx21-uart";
	reg = <0x43f94000 0x4000>;
	clocks = <&clks 9>, <&clks 71>;
	clock-names = "ipg", "per";
	interrupts = <32>;
	status = "disabled";
	};

	i2c2: i2c@43f98000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
	reg = <0x43f98000 0x4000>;
	clocks = <&clks 52>;
	clock-names = "ipg_per";
	interrupts = <4>;
	status = "disabled";
	};

	ssi1: ssi@43fa0000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx35-ssi", "fsl,imx21-ssi";
	reg = <0x43fa0000 0x4000>;
	interrupts = <11>;
	clocks = <&clks 68>;
	dmas = <&sdma 28 0 0>,
	<&sdma 29 0 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	spi1: spi@43fa4000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx35-cspi";
	reg = <0x43fa4000 0x4000>;
	clocks = <&clks 35 &clks 35>;
	clock-names = "ipg", "per";
	interrupts = <14>;
	status = "disabled";
	};

	kpp: kpp@43fa8000 {
	compatible = "fsl,imx35-kpp", "fsl,imx21-kpp";
	reg = <0x43fa8000 0x4000>;
	interrupts = <24>;
	clocks = <&clks 56>;
	status = "disabled";
	};

	iomuxc: iomuxc@43fac000 {
	compatible = "fsl,imx35-iomuxc";
	reg = <0x43fac000 0x4000>;
	};
	};

	spba: spba-bus@50000000 {
	compatible = "fsl,spba-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x50000000 0x100000>;
	ranges;

	uart3: serial@5000c000 {
	compatible = "fsl,imx35-uart", "fsl,imx21-uart";
	reg = <0x5000c000 0x4000>;
	clocks = <&clks 9>, <&clks 72>;
	clock-names = "ipg", "per";
	interrupts = <18>;
	status = "disabled";
	};

	spi2: spi@50010000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx35-cspi";
	reg = <0x50010000 0x4000>;
	interrupts = <13>;
	clocks = <&clks 36 &clks 36>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	fec: fec@50038000 {
	compatible = "fsl,imx35-fec", "fsl,imx27-fec";
	reg = <0x50038000 0x4000>;
	clocks = <&clks 46>, <&clks 8>;
	clock-names = "ipg", "ahb";
	interrupts = <57>;
	status = "disabled";
	};
	};

	- aips2: aips@53f00000 {
	+ aips2: bus@53f00000 {
	compatible = "fsl,aips", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x53f00000 0x100000>;
	ranges;

	clks: ccm@53f80000 {
	compatible = "fsl,imx35-ccm";
	reg = <0x53f80000 0x4000>;
	interrupts = <31>;
	#clock-cells = <1>;
	};

	gpt: timer@53f90000 {
	compatible = "fsl,imx35-gpt", "fsl,imx31-gpt";
	reg = <0x53f90000 0x4000>;
	interrupts = <29>;
	clocks = <&clks 9>, <&clks 50>;
	clock-names = "ipg", "per";
	};

	gpio3: gpio@53fa4000 {
	compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
	reg = <0x53fa4000 0x4000>;
	interrupts = <56>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	esdhc1: esdhc@53fb4000 {
	compatible = "fsl,imx35-esdhc";
	reg = <0x53fb4000 0x4000>;
	interrupts = <7>;
	clocks = <&clks 9>, <&clks 8>, <&clks 43>;
	clock-names = "ipg", "ahb", "per";
	status = "disabled";
	};

	esdhc2: esdhc@53fb8000 {
	compatible = "fsl,imx35-esdhc";
	reg = <0x53fb8000 0x4000>;
	interrupts = <8>;
	clocks = <&clks 9>, <&clks 8>, <&clks 44>;
	clock-names = "ipg", "ahb", "per";
	status = "disabled";
	};

	esdhc3: esdhc@53fbc000 {
	compatible = "fsl,imx35-esdhc";
	reg = <0x53fbc000 0x4000>;
	interrupts = <9>;
	clocks = <&clks 9>, <&clks 8>, <&clks 45>;
	clock-names = "ipg", "ahb", "per";
	status = "disabled";
	};

	audmux: audmux@53fc4000 {
	compatible = "fsl,imx35-audmux", "fsl,imx31-audmux";
	reg = <0x53fc4000 0x4000>;
	status = "disabled";
	};

	gpio1: gpio@53fcc000 {
	compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
	reg = <0x53fcc000 0x4000>;
	interrupts = <52>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio@53fd0000 {
	compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
	reg = <0x53fd0000 0x4000>;
	interrupts = <51>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	sdma: sdma@53fd4000 {
	compatible = "fsl,imx35-sdma";
	reg = <0x53fd4000 0x4000>;
	clocks = <&clks 9>, <&clks 65>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	interrupts = <34>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx35.bin";
	};

	wdog: wdog@53fdc000 {
	compatible = "fsl,imx35-wdt", "fsl,imx21-wdt";
	reg = <0x53fdc000 0x4000>;
	clocks = <&clks 74>;
	clock-names = "";
	interrupts = <55>;
	};

	can1: can@53fe4000 {
	compatible = "fsl,imx35-flexcan", "fsl,imx25-flexcan";
	reg = <0x53fe4000 0x1000>;
	clocks = <&clks 33>, <&clks 33>;
	clock-names = "ipg", "per";
	interrupts = <43>;
	status = "disabled";
	};

	can2: can@53fe8000 {
	compatible = "fsl,imx35-flexcan", "fsl,imx25-flexcan";
	reg = <0x53fe8000 0x1000>;
	clocks = <&clks 34>, <&clks 34>;
	clock-names = "ipg", "per";
	interrupts = <44>;
	status = "disabled";
	};

	iim@53ff0000 {
	compatible = "fsl,imx35-iim";
	reg = <0x53ff0000 0x4000>;
	interrupts = <19>;
	clocks = <&clks 80>;
	};

	usbotg: usb@53ff4000 {
	compatible = "fsl,imx35-usb", "fsl,imx27-usb";
	reg = <0x53ff4000 0x0200>;
	interrupts = <37>;
	clocks = <&clks 9>, <&clks 73>, <&clks 28>;
	clock-names = "ipg", "ahb", "per";
	fsl,usbmisc = <&usbmisc 0>;
	fsl,usbphy = <&usbphy0>;
	status = "disabled";
	};

	usbhost1: usb@53ff4400 {
	compatible = "fsl,imx35-usb", "fsl,imx27-usb";
	reg = <0x53ff4400 0x0200>;
	interrupts = <35>;
	clocks = <&clks 9>, <&clks 73>, <&clks 28>;
	clock-names = "ipg", "ahb", "per";
	fsl,usbmisc = <&usbmisc 1>;
	fsl,usbphy = <&usbphy1>;
	dr_mode = "host";
	status = "disabled";
	};

	usbmisc: usbmisc@53ff4600 {
	#index-cells = <1>;
	compatible = "fsl,imx35-usbmisc";
	reg = <0x53ff4600 0x00f>;
	};
	};

	emi@80000000 { /* External Memory Interface */
	compatible = "fsl,emi", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x80000000 0x40000000>;
	ranges;

	nfc: nand@bb000000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "fsl,imx35-nand", "fsl,imx25-nand";
	reg = <0xbb000000 0x2000>;
	clocks = <&clks 29>;
	clock-names = "";
	interrupts = <33>;
	status = "disabled";
	};

	weim: weim@b8002000 {
	#address-cells = <2>;
	#size-cells = <1>;
	clocks = <&clks 0>;
	compatible = "fsl,imx35-weim", "fsl,imx27-weim";
	reg = <0xb8002000 0x1000>;
	ranges = <
	0 0 0xa0000000 0x8000000
	1 0 0xa8000000 0x8000000
	2 0 0xb0000000 0x2000000
	3 0 0xb2000000 0x2000000
	4 0 0xb4000000 0x2000000
	5 0 0xb6000000 0x2000000
	>;
	status = "disabled";
	};
	};
	};

	usbphy {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	usbphy0: usb-phy@0 {
	reg = <0>;
	compatible = "usb-nop-xceiv";
	#phy-cells = <0>;
	};

	usbphy1: usb-phy@1 {
	reg = <1>;
	compatible = "usb-nop-xceiv";
	#phy-cells = <0>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx50.dtsi b/sys/gnu/dts/arm/imx50.dtsi
	index 0bfe7c91d0eb..d325658901c5 100644
	--- a/sys/gnu/dts/arm/imx50.dtsi
	+++ b/sys/gnu/dts/arm/imx50.dtsi
	@@ -1,503 +1,503 @@
	// SPDX-License-Identifier: GPL-2.0+
	//
	// Copyright 2013 Greg Ungerer <gerg@uclinux.org>
	// Copyright 2011 Freescale Semiconductor, Inc.
	// Copyright 2011 Linaro Ltd.

	#include "imx50-pinfunc.h"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/clock/imx5-clock.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	* The decompressor and also some bootloaders rely on a
	* pre-existing /chosen node to be available to insert the
	* command line and merge other ATAGS info.
	*/
	chosen {};

	aliases {
	ethernet0 = &fec;
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	gpio3 = &gpio4;
	gpio4 = &gpio5;
	gpio5 = &gpio6;
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	i2c2 = &i2c3;
	mmc0 = &esdhc1;
	mmc1 = &esdhc2;
	mmc2 = &esdhc3;
	mmc3 = &esdhc4;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	serial4 = &uart5;
	spi0 = &ecspi1;
	spi1 = &ecspi2;
	spi2 = &cspi;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a8";
	reg = <0x0>;
	};
	};

	tzic: tz-interrupt-controller@fffc000 {
	compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x0fffc000 0x4000>;
	};

	clocks {
	ckil {
	compatible = "fsl,imx-ckil", "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};

	ckih1 {
	compatible = "fsl,imx-ckih1", "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <22579200>;
	};

	ckih2 {
	compatible = "fsl,imx-ckih2", "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	osc {
	compatible = "fsl,imx-osc", "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	};
	};

	usbphy0: usbphy-0 {
	compatible = "usb-nop-xceiv";
	clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
	clock-names = "main_clk";
	#phy-cells = <0>;
	status = "okay";
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&tzic>;
	ranges;

	- aips@50000000 { /* AIPS1 */
	+ bus@50000000 { /* AIPS1 */
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x50000000 0x10000000>;
	ranges;

	spba@50000000 {
	compatible = "fsl,spba-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x50000000 0x40000>;
	ranges;

	esdhc1: esdhc@50004000 {
	compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
	reg = <0x50004000 0x4000>;
	interrupts = <1>;
	clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
	<&clks IMX5_CLK_DUMMY>,
	<&clks IMX5_CLK_ESDHC1_PER_GATE>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	esdhc2: esdhc@50008000 {
	compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
	reg = <0x50008000 0x4000>;
	interrupts = <2>;
	clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
	<&clks IMX5_CLK_DUMMY>,
	<&clks IMX5_CLK_ESDHC2_PER_GATE>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	uart3: serial@5000c000 {
	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	reg = <0x5000c000 0x4000>;
	interrupts = <33>;
	clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
	<&clks IMX5_CLK_UART3_PER_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ecspi1: spi@50010000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
	reg = <0x50010000 0x4000>;
	interrupts = <36>;
	clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
	<&clks IMX5_CLK_ECSPI1_PER_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ssi2: ssi@50014000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx50-ssi",
	"fsl,imx51-ssi",
	"fsl,imx21-ssi";
	reg = <0x50014000 0x4000>;
	interrupts = <30>;
	clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
	dmas = <&sdma 24 1 0>,
	<&sdma 25 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	esdhc3: esdhc@50020000 {
	compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
	reg = <0x50020000 0x4000>;
	interrupts = <3>;
	clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
	<&clks IMX5_CLK_DUMMY>,
	<&clks IMX5_CLK_ESDHC3_PER_GATE>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	esdhc4: esdhc@50024000 {
	compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
	reg = <0x50024000 0x4000>;
	interrupts = <4>;
	clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
	<&clks IMX5_CLK_DUMMY>,
	<&clks IMX5_CLK_ESDHC4_PER_GATE>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};
	};

	usbotg: usb@53f80000 {
	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	reg = <0x53f80000 0x0200>;
	interrupts = <18>;
	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
	fsl,usbphy = <&usbphy0>;
	status = "disabled";
	};

	usbh1: usb@53f80200 {
	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	reg = <0x53f80200 0x0200>;
	interrupts = <14>;
	clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
	dr_mode = "host";
	status = "disabled";
	};

	gpio1: gpio@53f84000 {
	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	reg = <0x53f84000 0x4000>;
	interrupts = <50 51>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 151 28>;
	};

	gpio2: gpio@53f88000 {
	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	reg = <0x53f88000 0x4000>;
	interrupts = <52 53>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>,
	<&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
	<&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
	<&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
	};

	gpio3: gpio@53f8c000 {
	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	reg = <0x53f8c000 0x4000>;
	interrupts = <54 55>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 108 32>;
	};

	gpio4: gpio@53f90000 {
	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	reg = <0x53f90000 0x4000>;
	interrupts = <56 57>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>,
	<&iomuxc 20 140 11>;
	};

	wdog1: wdog@53f98000 {
	compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
	reg = <0x53f98000 0x4000>;
	interrupts = <58>;
	clocks = <&clks IMX5_CLK_DUMMY>;
	};

	gpt: timer@53fa0000 {
	compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
	reg = <0x53fa0000 0x4000>;
	interrupts = <39>;
	clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
	<&clks IMX5_CLK_GPT_HF_GATE>;
	clock-names = "ipg", "per";
	};

	iomuxc: iomuxc@53fa8000 {
	compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
	reg = <0x53fa8000 0x4000>;
	};

	gpr: iomuxc-gpr@53fa8000 {
	compatible = "fsl,imx50-iomuxc-gpr", "syscon";
	reg = <0x53fa8000 0xc>;
	};

	pwm1: pwm@53fb4000 {
	#pwm-cells = <2>;
	compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
	reg = <0x53fb4000 0x4000>;
	clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
	<&clks IMX5_CLK_PWM1_HF_GATE>;
	clock-names = "ipg", "per";
	interrupts = <61>;
	};

	pwm2: pwm@53fb8000 {
	#pwm-cells = <2>;
	compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
	reg = <0x53fb8000 0x4000>;
	clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
	<&clks IMX5_CLK_PWM2_HF_GATE>;
	clock-names = "ipg", "per";
	interrupts = <94>;
	};

	uart1: serial@53fbc000 {
	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	reg = <0x53fbc000 0x4000>;
	interrupts = <31>;
	clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
	<&clks IMX5_CLK_UART1_PER_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart2: serial@53fc0000 {
	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	reg = <0x53fc0000 0x4000>;
	interrupts = <32>;
	clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
	<&clks IMX5_CLK_UART2_PER_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	src: src@53fd0000 {
	compatible = "fsl,imx50-src", "fsl,imx51-src";
	reg = <0x53fd0000 0x4000>;
	#reset-cells = <1>;
	};

	clks: ccm@53fd4000{
	compatible = "fsl,imx50-ccm";
	reg = <0x53fd4000 0x4000>;
	interrupts = <0 71 0x04 0 72 0x04>;
	#clock-cells = <1>;
	};

	gpio5: gpio@53fdc000 {
	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	reg = <0x53fdc000 0x4000>;
	interrupts = <103 104>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
	};

	gpio6: gpio@53fe0000 {
	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	reg = <0x53fe0000 0x4000>;
	interrupts = <105 106>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
	};

	i2c3: i2c@53fec000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	reg = <0x53fec000 0x4000>;
	interrupts = <64>;
	clocks = <&clks IMX5_CLK_I2C3_GATE>;
	status = "disabled";
	};

	uart4: serial@53ff0000 {
	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	reg = <0x53ff0000 0x4000>;
	interrupts = <13>;
	clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
	<&clks IMX5_CLK_UART4_PER_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};
	};

	- aips@60000000 { /* AIPS2 */
	+ bus@60000000 { /* AIPS2 */
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x60000000 0x10000000>;
	ranges;

	uart5: serial@63f90000 {
	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	reg = <0x63f90000 0x4000>;
	interrupts = <86>;
	clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
	<&clks IMX5_CLK_UART5_PER_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	owire: owire@63fa4000 {
	compatible = "fsl,imx50-owire", "fsl,imx21-owire";
	reg = <0x63fa4000 0x4000>;
	clocks = <&clks IMX5_CLK_OWIRE_GATE>;
	status = "disabled";
	};

	ecspi2: spi@63fac000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
	reg = <0x63fac000 0x4000>;
	interrupts = <37>;
	clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
	<&clks IMX5_CLK_ECSPI2_PER_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	sdma: sdma@63fb0000 {
	compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
	reg = <0x63fb0000 0x4000>;
	interrupts = <6>;
	clocks = <&clks IMX5_CLK_SDMA_GATE>,
	<&clks IMX5_CLK_AHB>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
	};

	cspi: spi@63fc0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
	reg = <0x63fc0000 0x4000>;
	interrupts = <38>;
	clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
	<&clks IMX5_CLK_CSPI_IPG_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	i2c2: i2c@63fc4000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	reg = <0x63fc4000 0x4000>;
	interrupts = <63>;
	clocks = <&clks IMX5_CLK_I2C2_GATE>;
	status = "disabled";
	};

	i2c1: i2c@63fc8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	reg = <0x63fc8000 0x4000>;
	interrupts = <62>;
	clocks = <&clks IMX5_CLK_I2C1_GATE>;
	status = "disabled";
	};

	ssi1: ssi@63fcc000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
	"fsl,imx21-ssi";
	reg = <0x63fcc000 0x4000>;
	interrupts = <29>;
	clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
	dmas = <&sdma 28 0 0>,
	<&sdma 29 0 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	audmux: audmux@63fd0000 {
	compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
	reg = <0x63fd0000 0x4000>;
	status = "disabled";
	};

	fec: ethernet@63fec000 {
	compatible = "fsl,imx53-fec", "fsl,imx25-fec";
	reg = <0x63fec000 0x4000>;
	interrupts = <87>;
	clocks = <&clks IMX5_CLK_FEC_GATE>,
	<&clks IMX5_CLK_FEC_GATE>,
	<&clks IMX5_CLK_FEC_GATE>;
	clock-names = "ipg", "ahb", "ptp";
	status = "disabled";
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx51-zii-rdu1.dts b/sys/gnu/dts/arm/imx51-zii-rdu1.dts
	index 3596060f52e7..e559ab0c3645 100644
	--- a/sys/gnu/dts/arm/imx51-zii-rdu1.dts
	+++ b/sys/gnu/dts/arm/imx51-zii-rdu1.dts
	@@ -1,893 +1,894 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	/*
	* Copyright (C) 2017 Zodiac Inflight Innovations
	*/

	/dts-v1/;
	#include "imx51.dtsi"
	#include <dt-bindings/sound/fsl-imx-audmux.h>

	/ {
	model = "ZII RDU1 Board";
	compatible = "zii,imx51-rdu1", "fsl,imx51";

	chosen {
	stdout-path = &uart1;
	};

	/* Will be filled by the bootloader */
	memory@90000000 {
	device_type = "memory";
	reg = <0x90000000 0>;
	};

	aliases {
	mdio-gpio0 = &mdio_gpio;
	rtc0 = &ds1341;
	};

	clk_26M_osc: 26M_osc {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <26000000>;
	};

	clk_26M_osc_gate: 26M_gate {
	compatible = "gpio-gate-clock";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_clk26mhz>;
	clocks = <&clk_26M_osc>;
	#clock-cells = <0>;
	enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
	};

	clk_26M_usb: usbhost_gate {
	compatible = "gpio-gate-clock";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbgate26mhz>;
	clocks = <&clk_26M_osc_gate>;
	#clock-cells = <0>;
	enable-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	};

	clk_26M_snd: snd_gate {
	compatible = "gpio-gate-clock";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sndgate26mhz>;
	clocks = <&clk_26M_osc_gate>;
	#clock-cells = <0>;
	enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
	};

	reg_5p0v_main: regulator-5p0v-main {
	compatible = "regulator-fixed";
	regulator-name = "5V_MAIN";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
	compatible = "regulator-fixed";
	regulator-name = "3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	disp0 {
	compatible = "fsl,imx-parallel-display";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ipu_disp1>;

	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	display_in: endpoint {
	remote-endpoint = <&ipu_di0_disp1>;
	};
	};

	port@1 {
	reg = <1>;

	display_out: endpoint {
	remote-endpoint = <&panel_in>;
	};
	};
	};

	panel {
	/* no compatible here, bootloader will patch in correct one */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_panel>;
	power-supply = <&reg_3p3v>;
	enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
	status = "disabled";

	port {
	panel_in: endpoint {
	remote-endpoint = <&display_out>;
	};
	};
	};

	i2c_gpio: i2c-gpio {
	compatible = "i2c-gpio";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_swi2c>;
	gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */
	<&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */
	i2c-gpio,delay-us = <50>;
	status = "okay";

	#address-cells = <1>;
	#size-cells = <0>;

	sgtl5000: codec@a {
	compatible = "fsl,sgtl5000";
	reg = <0x0a>;
	clocks = <&clk_26M_snd>;
	VDDA-supply = <&vdig_reg>;
	VDDIO-supply = <&vvideo_reg>;
	#sound-dai-cells = <0>;
	};
	};

	spi_gpio: spi-gpio {
	compatible = "spi-gpio";
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpiospi0>;
	status = "okay";

	gpio-sck = <&gpio4 15 GPIO_ACTIVE_HIGH>;
	gpio-mosi = <&gpio4 12 GPIO_ACTIVE_HIGH>;
	gpio-miso = <&gpio4 11 GPIO_ACTIVE_HIGH>;
	num-chipselects = <1>;
	cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;

	eeprom@0 {
	compatible = "eeprom-93xx46";
	reg = <0>;
	spi-max-frequency = <1000000>;
	spi-cs-high;
	data-size = <8>;
	};
	};

	mdio_gpio: mdio-gpio {
	compatible = "virtual,mdio-gpio";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_swmdio>;
	gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>, /* mdc */
	<&gpio3 25 GPIO_ACTIVE_HIGH>; /* mdio */

	#address-cells = <1>;
	#size-cells = <0>;

	switch@0 {
	compatible = "marvell,mv88e6085";
	reg = <0>;
	dsa,member = <0 0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	label = "cpu";
	ethernet = <&fec>;

	fixed-link {
	speed = <100>;
	full-duplex;
	};
	};

	port@1 {
	reg = <1>;
	label = "netaux";
	};

	port@3 {
	reg = <3>;
	label = "netright";
	};

	port@4 {
	reg = <4>;
	label = "netleft";
	};
	};
	};
	};

	sound {
	compatible = "simple-audio-card";
	simple-audio-card,name = "Front";
	simple-audio-card,format = "i2s";
	simple-audio-card,bitclock-master = <&sound_codec>;
	simple-audio-card,frame-master = <&sound_codec>;
	simple-audio-card,widgets =
	"Headphone", "Headphone Jack";
	simple-audio-card,routing =
	- "Headphone Jack", "HPLEFT",
	- "Headphone Jack", "HPRIGHT";
	+ "Headphone Jack", "TPA6130A2 HPLEFT",
	+ "Headphone Jack", "TPA6130A2 HPRIGHT";
	simple-audio-card,aux-devs = <&hpa1>;

	sound_cpu: simple-audio-card,cpu {
	sound-dai = <&ssi2>;
	};

	sound_codec: simple-audio-card,codec {
	sound-dai = <&sgtl5000>;
	clocks = <&clk_26M_snd>;
	};
	};

	usbh1phy: usbphy1 {
	compatible = "usb-nop-xceiv";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbh1phy>;
	clocks = <&clk_26M_usb>;
	clock-names = "main_clk";
	reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
	vcc-supply = <&vusb_reg>;
	#phy-cells = <0>;
	};

	usbh2phy: usbphy2 {
	compatible = "usb-nop-xceiv";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbh2phy>;
	clocks = <&clk_26M_usb>;
	clock-names = "main_clk";
	reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
	vcc-supply = <&vusb_reg>;
	#phy-cells = <0>;
	};
	};

	&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";

	ssi2 {
	fsl,audmux-port = <1>;
	fsl,port-config = <
	(IMX_AUDMUX_V2_PTCR_SYN \|
	IMX_AUDMUX_V2_PTCR_TFSEL(2) \|
	IMX_AUDMUX_V2_PTCR_TCSEL(2) \|
	IMX_AUDMUX_V2_PTCR_TFSDIR \|
	IMX_AUDMUX_V2_PTCR_TCLKDIR)
	IMX_AUDMUX_V2_PDCR_RXDSEL(2)
	>;
	};

	aud3 {
	fsl,audmux-port = <2>;
	fsl,port-config = <
	IMX_AUDMUX_V2_PTCR_SYN
	IMX_AUDMUX_V2_PDCR_RXDSEL(1)
	>;
	};
	};

	&cpu {
	cpu-supply = <&sw1_reg>;
	};

	&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
	<&gpio4 25 GPIO_ACTIVE_LOW>;
	status = "okay";

	pmic@0 {
	compatible = "fsl,mc13892";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pmic>;
	spi-max-frequency = <6000000>;
	spi-cs-high;
	reg = <0>;
	interrupt-parent = <&gpio1>;
	interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
	fsl,mc13xxx-uses-adc;

	regulators {
	sw1_reg: sw1 {
	regulator-min-microvolt = <600000>;
	regulator-max-microvolt = <1375000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw2_reg: sw2 {
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1850000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw3_reg: sw3 {
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1850000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw4_reg: sw4 {
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1850000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vpll_reg: vpll {
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vdig_reg: vdig {
	regulator-min-microvolt = <1650000>;
	regulator-max-microvolt = <1650000>;
	regulator-boot-on;
	};

	vsd_reg: vsd {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3150000>;
	};

	vusb_reg: vusb {
	regulator-always-on;
	};

	vusb2_reg: vusb2 {
	regulator-min-microvolt = <2400000>;
	regulator-max-microvolt = <2775000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vvideo_reg: vvideo {
	regulator-min-microvolt = <2775000>;
	regulator-max-microvolt = <2775000>;
	};

	vaudio_reg: vaudio {
	regulator-min-microvolt = <2300000>;
	regulator-max-microvolt = <3000000>;
	};

	vcam_reg: vcam {
	regulator-min-microvolt = <2500000>;
	regulator-max-microvolt = <3000000>;
	};

	vgen1_reg: vgen1 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	vgen2_reg: vgen2 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <3150000>;
	regulator-always-on;
	};

	vgen3_reg: vgen3 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2900000>;
	regulator-always-on;
	};
	};

	leds {
	#address-cells = <1>;
	#size-cells = <0>;
	led-control = <0x0 0x0 0x3f83f8 0x0>;

	sysled0@3 {
	reg = <3>;
	label = "system:green:status";
	linux,default-trigger = "default-on";
	};

	sysled1@4 {
	reg = <4>;
	label = "system:green:act";
	linux,default-trigger = "heartbeat";
	};
	};
	};

	flash@1 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "atmel,at45db642d", "atmel,at45", "atmel,dataflash";
	spi-max-frequency = <25000000>;
	reg = <1>;
	};
	};

	&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	no-1-8-v;
	non-removable;
	no-sdio;
	no-sd;
	status = "okay";
	};

	&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "mii";
	phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
	phy-supply = <&vgen3_reg>;
	status = "okay";
	};

	&gpio1 {
	gpio-line-names = "", "", "", "",
	"", "", "", "",
	"", "hp-amp-shutdown-b", "", "",
	"", "", "", "",
	"", "", "", "",
	"", "", "", "",
	"", "", "", "",
	"", "", "", "";

	unused-sd3-wp-gpio {
	/*
	* See pinctrl_esdhc1 below for more details on this
	*/
	gpio-hog;
	gpios = <1 GPIO_ACTIVE_HIGH>;
	output-high;
	};
	};

	&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	hpa1: amp@60 {
	compatible = "ti,tpa6130a2";
	reg = <0x60>;
	Vdd-supply = <&reg_3p3v>;
	+ sound-name-prefix = "TPA6130A2";
	};

	ds1341: rtc@68 {
	compatible = "dallas,ds1341";
	reg = <0x68>;
	};

	/* touch nodes default disabled, bootloader will enable the right one */

	touchscreen@4b {
	compatible = "atmel,maxtouch";
	reg = <0x4b>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ts>;
	interrupt-parent = <&gpio3>;
	interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
	status = "disabled";
	};

	touchscreen@4c {
	compatible = "atmel,maxtouch";
	reg = <0x4c>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ts>;
	interrupt-parent = <&gpio3>;
	interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
	status = "disabled";
	};

	touchscreen@20 {
	compatible = "syna,rmi4-i2c";
	reg = <0x20>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ts>;
	interrupt-parent = <&gpio3>;
	interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
	status = "disabled";

	#address-cells = <1>;
	#size-cells = <0>;

	rmi4-f01@1 {
	reg = <0x1>;
	syna,nosleep-mode = <2>;
	};

	rmi4-f11@11 {
	reg = <0x11>;
	touchscreen-inverted-x;
	touchscreen-swapped-x-y;
	syna,sensor-type = <1>;
	};
	};

	};

	&ipu_di0_disp1 {
	remote-endpoint = <&display_in>;
	};

	&pmu {
	secure-reg-access;
	};

	&ssi2 {
	status = "okay";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
	};

	&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";

	rave-sp {
	compatible = "zii,rave-sp-rdu1";
	current-speed = <38400>;
	#address-cells = <1>;
	#size-cells = <1>;

	watchdog {
	compatible = "zii,rave-sp-watchdog";
	};

	backlight {
	compatible = "zii,rave-sp-backlight";
	};

	pwrbutton {
	compatible = "zii,rave-sp-pwrbutton";
	};

	eeprom@a3 {
	compatible = "zii,rave-sp-eeprom";
	reg = <0xa3 0x2000>;
	#address-cells = <1>;
	#size-cells = <1>;
	zii,eeprom-name = "dds-eeprom";
	};

	eeprom@a4 {
	compatible = "zii,rave-sp-eeprom";
	reg = <0xa4 0x4000>;
	#address-cells = <1>;
	#size-cells = <1>;
	zii,eeprom-name = "main-eeprom";
	};

	eeprom@ae {
	compatible = "zii,rave-sp-eeprom";
	reg = <0xae 0x200>;
	zii,eeprom-name = "switch-eeprom";
	/*
	* Not all RDU1s have this functionality, so we
	* rely on the bootloader to enable this
	*/
	status = "disabled";
	};
	};
	};

	&usbh1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbh1>;
	dr_mode = "host";
	phy_type = "ulpi";
	fsl,usbphy = <&usbh1phy>;
	disable-over-current;
	maximum-speed = "full-speed";
	vbus-supply = <&reg_5p0v_main>;
	status = "okay";
	};

	&usbh2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbh2>;
	dr_mode = "host";
	phy_type = "ulpi";
	fsl,usbphy = <&usbh2phy>;
	disable-over-current;
	vbus-supply = <&reg_5p0v_main>;
	status = "okay";
	};

	&usbphy0 {
	vcc-supply = <&vusb_reg>;
	};

	&usbotg {
	dr_mode = "host";
	disable-over-current;
	phy_type = "utmi_wide";
	vbus-supply = <&reg_5p0v_main>;
	status = "okay";
	};

	&wdog1 {
	status = "disabled";
	};

	&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
	fsl,pins = <
	MX51_PAD_GPIO1_9__GPIO1_9 0x5e
	>;
	};

	pinctrl_audmux: audmuxgrp {
	fsl,pins = <
	MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0xa5
	MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x85
	MX51_PAD_AUD3_BB_CK__AUD3_TXC 0xa5
	MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x85
	>;
	};

	pinctrl_clk26mhz: clk26mhzgrp {
	fsl,pins = <
	MX51_PAD_DI1_PIN12__GPIO3_1 0x85
	>;
	};

	pinctrl_ecspi1: ecspi1grp {
	fsl,pins = <
	MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
	MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
	MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
	>;
	};

	pinctrl_esdhc1: esdhc1grp {
	fsl,pins = <
	MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
	MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
	MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
	MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
	MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
	MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
	/*
	* GPIO1_1 is not directly used by eSDHC1 in
	* any capacity, but earlier versions of RDU1
	* used that pin as WP GPIO for eSDHC3 and
	* because of that that pad has an external
	* pull-up resistor. This is problematic
	* because out of reset the pad is configured
	* as ALT0 which serves as SD1_WP, which, when
	* pulled high by and external pull-up, will
	* inhibit execution of any write request to
	* attached eMMC device.
	*
	* To avoid this problem we configure the pad
	* to ALT1/GPIO and avoid driving SD1_WP
	* signal high.
	*/
	MX51_PAD_GPIO1_1__GPIO1_1 0x0000
	>;
	};

	pinctrl_fec: fecgrp {
	fsl,pins = <
	MX51_PAD_EIM_EB2__FEC_MDIO 0x1f5
	MX51_PAD_NANDF_D9__FEC_RDATA0 0x2180
	MX51_PAD_EIM_EB3__FEC_RDATA1 0x180
	MX51_PAD_EIM_CS2__FEC_RDATA2 0x180
	MX51_PAD_EIM_CS3__FEC_RDATA3 0x180
	MX51_PAD_EIM_CS4__FEC_RX_ER 0x180
	MX51_PAD_NANDF_D11__FEC_RX_DV 0x2084
	MX51_PAD_EIM_CS5__FEC_CRS 0x180
	MX51_PAD_NANDF_RB2__FEC_COL 0x2180
	MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x2180
	MX51_PAD_NANDF_CS2__FEC_TX_ER 0x2004
	MX51_PAD_NANDF_CS3__FEC_MDC 0x2004
	MX51_PAD_NANDF_D8__FEC_TDATA0 0x2180
	MX51_PAD_NANDF_CS4__FEC_TDATA1 0x2004
	MX51_PAD_NANDF_CS5__FEC_TDATA2 0x2004
	MX51_PAD_NANDF_CS6__FEC_TDATA3 0x2004
	MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004
	MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180
	MX51_PAD_EIM_A20__GPIO2_14 0x85
	>;
	};

	pinctrl_gpiospi0: gpiospi0grp {
	fsl,pins = <
	MX51_PAD_CSI2_D18__GPIO4_11 0x85
	MX51_PAD_CSI2_D19__GPIO4_12 0x85
	MX51_PAD_CSI2_HSYNC__GPIO4_14 0x85
	MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x85
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
	MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
	>;
	};

	pinctrl_ipu_disp1: ipudisp1grp {
	fsl,pins = <
	MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
	MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
	MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
	MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
	MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
	MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
	MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
	MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
	MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
	MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
	MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
	MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
	MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
	MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
	MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
	MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
	MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
	MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
	MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
	MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
	MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
	MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
	MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
	MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
	MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
	MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
	MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
	>;
	};

	pinctrl_panel: panelgrp {
	fsl,pins = <
	MX51_PAD_DI1_D0_CS__GPIO3_3 0x85
	>;
	};

	pinctrl_pmic: pmicgrp {
	fsl,pins = <
	MX51_PAD_GPIO1_4__GPIO1_4 0x1e0
	MX51_PAD_GPIO1_8__GPIO1_8 0x21e2
	>;
	};

	pinctrl_sndgate26mhz: sndgate26mhzgrp {
	fsl,pins = <
	MX51_PAD_CSPI1_RDY__GPIO4_26 0x85
	>;
	};

	pinctrl_swi2c: swi2cgrp {
	fsl,pins = <
	MX51_PAD_GPIO1_2__GPIO1_2 0xc5
	MX51_PAD_DI1_D1_CS__GPIO3_4 0x400001f5
	>;
	};

	pinctrl_swmdio: swmdiogrp {
	fsl,pins = <
	MX51_PAD_NANDF_D14__GPIO3_26 0x21e6
	MX51_PAD_NANDF_D15__GPIO3_25 0x21e6
	>;
	};

	pinctrl_ts: tsgrp {
	fsl,pins = <
	MX51_PAD_CSI1_D8__GPIO3_12 0x04
	MX51_PAD_CSI1_D9__GPIO3_13 0x85
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
	MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
	MX51_PAD_UART1_RTS__UART1_RTS 0x1c4
	MX51_PAD_UART1_CTS__UART1_CTS 0x1c4
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	MX51_PAD_UART2_RXD__UART2_RXD 0xc5
	MX51_PAD_UART2_TXD__UART2_TXD 0xc5
	>;
	};

	pinctrl_uart3: uart3grp {
	fsl,pins = <
	MX51_PAD_EIM_D25__UART3_RXD 0x1c5
	MX51_PAD_EIM_D26__UART3_TXD 0x1c5
	>;
	};

	pinctrl_usbgate26mhz: usbgate26mhzgrp {
	fsl,pins = <
	MX51_PAD_DISP2_DAT6__GPIO1_19 0x85
	>;
	};

	pinctrl_usbh1: usbh1grp {
	fsl,pins = <
	MX51_PAD_USBH1_STP__USBH1_STP 0x0
	MX51_PAD_USBH1_CLK__USBH1_CLK 0x0
	MX51_PAD_USBH1_DIR__USBH1_DIR 0x0
	MX51_PAD_USBH1_NXT__USBH1_NXT 0x0
	MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x0
	MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x0
	MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x0
	MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x0
	MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x0
	MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x0
	MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x0
	MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x0
	>;
	};

	pinctrl_usbh1phy: usbh1phygrp {
	fsl,pins = <
	MX51_PAD_NANDF_D0__GPIO4_8 0x85
	>;
	};

	pinctrl_usbh2: usbh2grp {
	fsl,pins = <
	MX51_PAD_EIM_A26__USBH2_STP 0x0
	MX51_PAD_EIM_A24__USBH2_CLK 0x0
	MX51_PAD_EIM_A25__USBH2_DIR 0x0
	MX51_PAD_EIM_A27__USBH2_NXT 0x0
	MX51_PAD_EIM_D16__USBH2_DATA0 0x0
	MX51_PAD_EIM_D17__USBH2_DATA1 0x0
	MX51_PAD_EIM_D18__USBH2_DATA2 0x0
	MX51_PAD_EIM_D19__USBH2_DATA3 0x0
	MX51_PAD_EIM_D20__USBH2_DATA4 0x0
	MX51_PAD_EIM_D21__USBH2_DATA5 0x0
	MX51_PAD_EIM_D22__USBH2_DATA6 0x0
	MX51_PAD_EIM_D23__USBH2_DATA7 0x0
	>;
	};

	pinctrl_usbh2phy: usbh2phygrp {
	fsl,pins = <
	MX51_PAD_NANDF_D1__GPIO4_7 0x85
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx51.dtsi b/sys/gnu/dts/arm/imx51.dtsi
	index dea86b98e9c3..92fbb90bec57 100644
	--- a/sys/gnu/dts/arm/imx51.dtsi
	+++ b/sys/gnu/dts/arm/imx51.dtsi
	@@ -1,640 +1,653 @@
	// SPDX-License-Identifier: GPL-2.0+
	//
	// Copyright 2011 Freescale Semiconductor, Inc.
	// Copyright 2011 Linaro Ltd.

	#include "imx51-pinfunc.h"
	#include <dt-bindings/clock/imx5-clock.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/irq.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	* The decompressor and also some bootloaders rely on a
	* pre-existing /chosen node to be available to insert the
	* command line and merge other ATAGS info.
	*/
	chosen {};

	aliases {
	ethernet0 = &fec;
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	gpio3 = &gpio4;
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	mmc0 = &esdhc1;
	mmc1 = &esdhc2;
	mmc2 = &esdhc3;
	mmc3 = &esdhc4;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	spi0 = &ecspi1;
	spi1 = &ecspi2;
	spi2 = &cspi;
	};

	tzic: tz-interrupt-controller@e0000000 {
	compatible = "fsl,imx51-tzic", "fsl,tzic";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0xe0000000 0x4000>;
	};

	clocks {
	ckil {
	compatible = "fsl,imx-ckil", "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};

	ckih1 {
	compatible = "fsl,imx-ckih1", "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	ckih2 {
	compatible = "fsl,imx-ckih2", "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	osc {
	compatible = "fsl,imx-osc", "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	cpu: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a8";
	reg = <0>;
	clock-latency = <62500>;
	clocks = <&clks IMX5_CLK_CPU_PODF>;
	clock-names = "cpu";
	operating-points = <
	166000 1000000
	600000 1050000
	800000 1100000
	>;
	voltage-tolerance = <5>;
	};
	};

	pmu: pmu {
	compatible = "arm,cortex-a8-pmu";
	interrupt-parent = <&tzic>;
	interrupts = <77>;
	};

	usbphy0: usbphy0 {
	compatible = "usb-nop-xceiv";
	clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
	clock-names = "main_clk";
	#phy-cells = <0>;
	};

	+ capture-subsystem {
	+ compatible = "fsl,imx-capture-subsystem";
	+ ports = <&ipu_csi0>, <&ipu_csi1>;
	+ };
	+
	display-subsystem {
	compatible = "fsl,imx-display-subsystem";
	ports = <&ipu_di0>, <&ipu_di1>;
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&tzic>;
	ranges;

	iram: sram@1ffe0000 {
	compatible = "mmio-sram";
	reg = <0x1ffe0000 0x20000>;
	};

	gpu: gpu@30000000 {
	compatible = "amd,imageon-200.1", "amd,imageon";
	reg = <0x30000000 0x20000>;
	reg-names = "kgsl_3d0_reg_memory";
	interrupts = <12>;
	interrupt-names = "kgsl_3d0_irq";
	clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
	clock-names = "core_clk", "mem_iface_clk";
	};

	ipu: ipu@40000000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx51-ipu";
	reg = <0x40000000 0x20000000>;
	interrupts = <11 10>;
	clocks = <&clks IMX5_CLK_IPU_GATE>,
	<&clks IMX5_CLK_IPU_DI0_GATE>,
	<&clks IMX5_CLK_IPU_DI1_GATE>;
	clock-names = "bus", "di0", "di1";
	resets = <&src 2>;

	+ ipu_csi0: port@0 {
	+ reg = <0>;
	+ };
	+
	+ ipu_csi1: port@1 {
	+ reg = <1>;
	+ };
	+
	ipu_di0: port@2 {
	reg = <2>;

	ipu_di0_disp1: endpoint {
	};
	};

	ipu_di1: port@3 {
	reg = <3>;

	ipu_di1_disp2: endpoint {
	};
	};
	};

	- aips@70000000 { /* AIPS1 */
	+ bus@70000000 { /* AIPS1 */
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x70000000 0x10000000>;
	ranges;

	spba@70000000 {
	compatible = "fsl,spba-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x70000000 0x40000>;
	ranges;

	esdhc1: esdhc@70004000 {
	compatible = "fsl,imx51-esdhc";
	reg = <0x70004000 0x4000>;
	interrupts = <1>;
	clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
	<&clks IMX5_CLK_DUMMY>,
	<&clks IMX5_CLK_ESDHC1_PER_GATE>;
	clock-names = "ipg", "ahb", "per";
	status = "disabled";
	};

	esdhc2: esdhc@70008000 {
	compatible = "fsl,imx51-esdhc";
	reg = <0x70008000 0x4000>;
	interrupts = <2>;
	clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
	<&clks IMX5_CLK_DUMMY>,
	<&clks IMX5_CLK_ESDHC2_PER_GATE>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	uart3: serial@7000c000 {
	compatible = "fsl,imx51-uart", "fsl,imx21-uart";
	reg = <0x7000c000 0x4000>;
	interrupts = <33>;
	clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
	<&clks IMX5_CLK_UART3_PER_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ecspi1: spi@70010000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx51-ecspi";
	reg = <0x70010000 0x4000>;
	interrupts = <36>;
	clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
	<&clks IMX5_CLK_ECSPI1_PER_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ssi2: ssi@70014000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
	reg = <0x70014000 0x4000>;
	interrupts = <30>;
	clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
	<&clks IMX5_CLK_SSI2_ROOT_GATE>;
	clock-names = "ipg", "baud";
	dmas = <&sdma 24 1 0>,
	<&sdma 25 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	esdhc3: esdhc@70020000 {
	compatible = "fsl,imx51-esdhc";
	reg = <0x70020000 0x4000>;
	interrupts = <3>;
	clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
	<&clks IMX5_CLK_DUMMY>,
	<&clks IMX5_CLK_ESDHC3_PER_GATE>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	esdhc4: esdhc@70024000 {
	compatible = "fsl,imx51-esdhc";
	reg = <0x70024000 0x4000>;
	interrupts = <4>;
	clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
	<&clks IMX5_CLK_DUMMY>,
	<&clks IMX5_CLK_ESDHC4_PER_GATE>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};
	};

	aipstz1: bridge@73f00000 {
	compatible = "fsl,imx51-aipstz";
	reg = <0x73f00000 0x60>;
	};

	usbotg: usb@73f80000 {
	compatible = "fsl,imx51-usb", "fsl,imx27-usb";
	reg = <0x73f80000 0x0200>;
	interrupts = <18>;
	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
	fsl,usbmisc = <&usbmisc 0>;
	fsl,usbphy = <&usbphy0>;
	status = "disabled";
	};

	usbh1: usb@73f80200 {
	compatible = "fsl,imx51-usb", "fsl,imx27-usb";
	reg = <0x73f80200 0x0200>;
	interrupts = <14>;
	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
	fsl,usbmisc = <&usbmisc 1>;
	dr_mode = "host";
	status = "disabled";
	};

	usbh2: usb@73f80400 {
	compatible = "fsl,imx51-usb", "fsl,imx27-usb";
	reg = <0x73f80400 0x0200>;
	interrupts = <16>;
	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
	fsl,usbmisc = <&usbmisc 2>;
	dr_mode = "host";
	status = "disabled";
	};

	usbh3: usb@73f80600 {
	compatible = "fsl,imx51-usb", "fsl,imx27-usb";
	reg = <0x73f80600 0x0200>;
	interrupts = <17>;
	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
	fsl,usbmisc = <&usbmisc 3>;
	dr_mode = "host";
	status = "disabled";
	};

	usbmisc: usbmisc@73f80800 {
	#index-cells = <1>;
	compatible = "fsl,imx51-usbmisc";
	reg = <0x73f80800 0x200>;
	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
	};

	gpio1: gpio@73f84000 {
	compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
	reg = <0x73f84000 0x4000>;
	interrupts = <50 51>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio@73f88000 {
	compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
	reg = <0x73f88000 0x4000>;
	interrupts = <52 53>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio@73f8c000 {
	compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
	reg = <0x73f8c000 0x4000>;
	interrupts = <54 55>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio4: gpio@73f90000 {
	compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
	reg = <0x73f90000 0x4000>;
	interrupts = <56 57>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	kpp: kpp@73f94000 {
	compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
	reg = <0x73f94000 0x4000>;
	interrupts = <60>;
	clocks = <&clks IMX5_CLK_DUMMY>;
	status = "disabled";
	};

	wdog1: wdog@73f98000 {
	compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
	reg = <0x73f98000 0x4000>;
	interrupts = <58>;
	clocks = <&clks IMX5_CLK_DUMMY>;
	};

	wdog2: wdog@73f9c000 {
	compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
	reg = <0x73f9c000 0x4000>;
	interrupts = <59>;
	clocks = <&clks IMX5_CLK_DUMMY>;
	status = "disabled";
	};

	gpt: timer@73fa0000 {
	compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
	reg = <0x73fa0000 0x4000>;
	interrupts = <39>;
	clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
	<&clks IMX5_CLK_GPT_HF_GATE>;
	clock-names = "ipg", "per";
	};

	iomuxc: iomuxc@73fa8000 {
	compatible = "fsl,imx51-iomuxc";
	reg = <0x73fa8000 0x4000>;
	};

	pwm1: pwm@73fb4000 {
	#pwm-cells = <2>;
	compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
	reg = <0x73fb4000 0x4000>;
	clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
	<&clks IMX5_CLK_PWM1_HF_GATE>;
	clock-names = "ipg", "per";
	interrupts = <61>;
	};

	pwm2: pwm@73fb8000 {
	#pwm-cells = <2>;
	compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
	reg = <0x73fb8000 0x4000>;
	clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
	<&clks IMX5_CLK_PWM2_HF_GATE>;
	clock-names = "ipg", "per";
	interrupts = <94>;
	};

	uart1: serial@73fbc000 {
	compatible = "fsl,imx51-uart", "fsl,imx21-uart";
	reg = <0x73fbc000 0x4000>;
	interrupts = <31>;
	clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
	<&clks IMX5_CLK_UART1_PER_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart2: serial@73fc0000 {
	compatible = "fsl,imx51-uart", "fsl,imx21-uart";
	reg = <0x73fc0000 0x4000>;
	interrupts = <32>;
	clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
	<&clks IMX5_CLK_UART2_PER_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	src: src@73fd0000 {
	compatible = "fsl,imx51-src";
	reg = <0x73fd0000 0x4000>;
	#reset-cells = <1>;
	};

	clks: ccm@73fd4000{
	compatible = "fsl,imx51-ccm";
	reg = <0x73fd4000 0x4000>;
	interrupts = <0 71 0x04 0 72 0x04>;
	#clock-cells = <1>;
	};
	};

	- aips@80000000 { /* AIPS2 */
	+ bus@80000000 { /* AIPS2 */
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x80000000 0x10000000>;
	ranges;

	aipstz2: bridge@83f00000 {
	compatible = "fsl,imx51-aipstz";
	reg = <0x83f00000 0x60>;
	};

	iim: iim@83f98000 {
	compatible = "fsl,imx51-iim", "fsl,imx27-iim";
	reg = <0x83f98000 0x4000>;
	interrupts = <69>;
	clocks = <&clks IMX5_CLK_IIM_GATE>;
	};

	tigerp: tigerp@83fa0000 {
	compatible = "fsl,imx51-tigerp";
	reg = <0x83fa0000 0x28>;
	};

	owire: owire@83fa4000 {
	compatible = "fsl,imx51-owire", "fsl,imx21-owire";
	reg = <0x83fa4000 0x4000>;
	interrupts = <88>;
	clocks = <&clks IMX5_CLK_OWIRE_GATE>;
	status = "disabled";
	};

	ecspi2: spi@83fac000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx51-ecspi";
	reg = <0x83fac000 0x4000>;
	interrupts = <37>;
	clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
	<&clks IMX5_CLK_ECSPI2_PER_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	sdma: sdma@83fb0000 {
	compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
	reg = <0x83fb0000 0x4000>;
	interrupts = <6>;
	clocks = <&clks IMX5_CLK_SDMA_GATE>,
	<&clks IMX5_CLK_AHB>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
	};

	cspi: spi@83fc0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
	reg = <0x83fc0000 0x4000>;
	interrupts = <38>;
	clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
	<&clks IMX5_CLK_CSPI_IPG_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	i2c2: i2c@83fc4000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
	reg = <0x83fc4000 0x4000>;
	interrupts = <63>;
	clocks = <&clks IMX5_CLK_I2C2_GATE>;
	status = "disabled";
	};

	i2c1: i2c@83fc8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
	reg = <0x83fc8000 0x4000>;
	interrupts = <62>;
	clocks = <&clks IMX5_CLK_I2C1_GATE>;
	status = "disabled";
	};

	ssi1: ssi@83fcc000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
	reg = <0x83fcc000 0x4000>;
	interrupts = <29>;
	clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
	<&clks IMX5_CLK_SSI1_ROOT_GATE>;
	clock-names = "ipg", "baud";
	dmas = <&sdma 28 0 0>,
	<&sdma 29 0 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	audmux: audmux@83fd0000 {
	compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
	reg = <0x83fd0000 0x4000>;
	clocks = <&clks IMX5_CLK_DUMMY>;
	clock-names = "audmux";
	status = "disabled";
	};

	m4if: m4if@83fd8000 {
	compatible = "fsl,imx51-m4if";
	reg = <0x83fd8000 0x1000>;
	};

	weim: weim@83fda000 {
	#address-cells = <2>;
	#size-cells = <1>;
	compatible = "fsl,imx51-weim";
	reg = <0x83fda000 0x1000>;
	clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
	ranges = <
	0 0 0xb0000000 0x08000000
	1 0 0xb8000000 0x08000000
	2 0 0xc0000000 0x08000000
	3 0 0xc8000000 0x04000000
	4 0 0xcc000000 0x02000000
	5 0 0xce000000 0x02000000
	>;
	status = "disabled";
	};

	nfc: nand@83fdb000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "fsl,imx51-nand";
	reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
	interrupts = <8>;
	clocks = <&clks IMX5_CLK_NFC_GATE>;
	status = "disabled";
	};

	pata: pata@83fe0000 {
	compatible = "fsl,imx51-pata", "fsl,imx27-pata";
	reg = <0x83fe0000 0x4000>;
	interrupts = <70>;
	clocks = <&clks IMX5_CLK_PATA_GATE>;
	status = "disabled";
	};

	ssi3: ssi@83fe8000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
	reg = <0x83fe8000 0x4000>;
	interrupts = <96>;
	clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
	<&clks IMX5_CLK_SSI3_ROOT_GATE>;
	clock-names = "ipg", "baud";
	dmas = <&sdma 46 0 0>,
	<&sdma 47 0 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	fec: ethernet@83fec000 {
	compatible = "fsl,imx51-fec", "fsl,imx27-fec";
	reg = <0x83fec000 0x4000>;
	interrupts = <87>;
	clocks = <&clks IMX5_CLK_FEC_GATE>,
	<&clks IMX5_CLK_FEC_GATE>,
	<&clks IMX5_CLK_FEC_GATE>;
	clock-names = "ipg", "ahb", "ptp";
	status = "disabled";
	};

	vpu: vpu@83ff4000 {
	compatible = "fsl,imx51-vpu", "cnm,codahx4";
	reg = <0x83ff4000 0x1000>;
	interrupts = <9>;
	clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
	<&clks IMX5_CLK_VPU_GATE>;
	clock-names = "per", "ahb";
	resets = <&src 1>;
	iram = <&iram>;
	};

	sahara: crypto@83ff8000 {
	compatible = "fsl,imx53-sahara", "fsl,imx51-sahara";
	reg = <0x83ff8000 0x4000>;
	interrupts = <19 20>;
	clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
	<&clks IMX5_CLK_SAHARA_IPG_GATE>;
	clock-names = "ipg", "ahb";
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx53.dtsi b/sys/gnu/dts/arm/imx53.dtsi
	index ed341cfd9d09..8536f59f59e6 100644
	--- a/sys/gnu/dts/arm/imx53.dtsi
	+++ b/sys/gnu/dts/arm/imx53.dtsi
	@@ -1,855 +1,855 @@
	// SPDX-License-Identifier: GPL-2.0+
	//
	// Copyright 2011 Freescale Semiconductor, Inc.
	// Copyright 2011 Linaro Ltd.

	#include "imx53-pinfunc.h"
	#include <dt-bindings/clock/imx5-clock.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/irq.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	* The decompressor and also some bootloaders rely on a
	* pre-existing /chosen node to be available to insert the
	* command line and merge other ATAGS info.
	*/
	chosen {};

	aliases {
	ethernet0 = &fec;
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	gpio3 = &gpio4;
	gpio4 = &gpio5;
	gpio5 = &gpio6;
	gpio6 = &gpio7;
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	i2c2 = &i2c3;
	ipu0 = &ipu;
	mmc0 = &esdhc1;
	mmc1 = &esdhc2;
	mmc2 = &esdhc3;
	mmc3 = &esdhc4;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	serial4 = &uart5;
	spi0 = &ecspi1;
	spi1 = &ecspi2;
	spi2 = &cspi;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a8";
	reg = <0x0>;
	clocks = <&clks IMX5_CLK_ARM>;
	clock-latency = <61036>;
	voltage-tolerance = <5>;
	operating-points = <
	/* kHz */
	166666 850000
	400000 900000
	800000 1050000
	1000000 1200000
	1200000 1300000
	>;
	};
	};

	display-subsystem {
	compatible = "fsl,imx-display-subsystem";
	ports = <&ipu_di0>, <&ipu_di1>;
	};

	capture_subsystem {
	compatible = "fsl,imx-capture-subsystem";
	ports = <&ipu_csi0>, <&ipu_csi1>;
	};

	tzic: tz-interrupt-controller@fffc000 {
	compatible = "fsl,imx53-tzic", "fsl,tzic";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x0fffc000 0x4000>;
	};

	clocks {
	ckil {
	compatible = "fsl,imx-ckil", "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};

	ckih1 {
	compatible = "fsl,imx-ckih1", "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <22579200>;
	};

	ckih2 {
	compatible = "fsl,imx-ckih2", "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	osc {
	compatible = "fsl,imx-osc", "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	};
	};

	pmu: pmu {
	compatible = "arm,cortex-a8-pmu";
	interrupt-parent = <&tzic>;
	interrupts = <77>;
	};

	usbphy0: usbphy-0 {
	compatible = "usb-nop-xceiv";
	clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
	clock-names = "main_clk";
	#phy-cells = <0>;
	status = "okay";
	};

	usbphy1: usbphy-1 {
	compatible = "usb-nop-xceiv";
	clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
	clock-names = "main_clk";
	#phy-cells = <0>;
	status = "okay";
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&tzic>;
	ranges;

	sata: sata@10000000 {
	compatible = "fsl,imx53-ahci";
	reg = <0x10000000 0x1000>;
	interrupts = <28>;
	clocks = <&clks IMX5_CLK_SATA_GATE>,
	<&clks IMX5_CLK_SATA_REF>,
	<&clks IMX5_CLK_AHB>;
	clock-names = "sata", "sata_ref", "ahb";
	status = "disabled";
	};

	ipu: ipu@18000000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx53-ipu";
	reg = <0x18000000 0x08000000>;
	interrupts = <11 10>;
	clocks = <&clks IMX5_CLK_IPU_GATE>,
	<&clks IMX5_CLK_IPU_DI0_GATE>,
	<&clks IMX5_CLK_IPU_DI1_GATE>;
	clock-names = "bus", "di0", "di1";
	resets = <&src 2>;

	ipu_csi0: port@0 {
	reg = <0>;

	ipu_csi0_from_parallel_sensor: endpoint {
	};
	};

	ipu_csi1: port@1 {
	reg = <1>;

	ipu_csi1_from_parallel_sensor: endpoint {
	};
	};

	ipu_di0: port@2 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <2>;

	ipu_di0_disp0: endpoint@0 {
	reg = <0>;
	};

	ipu_di0_lvds0: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&lvds0_in>;
	};
	};

	ipu_di1: port@3 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <3>;

	ipu_di1_disp1: endpoint@0 {
	reg = <0>;
	};

	ipu_di1_lvds1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&lvds1_in>;
	};

	ipu_di1_tve: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&tve_in>;
	};
	};
	};

	gpu: gpu@30000000 {
	compatible = "amd,imageon-200.0", "amd,imageon";
	reg = <0x30000000 0x20000>;
	reg-names = "kgsl_3d0_reg_memory";
	interrupts = <12>;
	interrupt-names = "kgsl_3d0_irq";
	clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
	clock-names = "core_clk", "mem_iface_clk";
	};

	- aips@50000000 { /* AIPS1 */
	+ bus@50000000 { /* AIPS1 */
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x50000000 0x10000000>;
	ranges;

	spba@50000000 {
	compatible = "fsl,spba-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x50000000 0x40000>;
	ranges;

	esdhc1: esdhc@50004000 {
	compatible = "fsl,imx53-esdhc";
	reg = <0x50004000 0x4000>;
	interrupts = <1>;
	clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
	<&clks IMX5_CLK_DUMMY>,
	<&clks IMX5_CLK_ESDHC1_PER_GATE>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	esdhc2: esdhc@50008000 {
	compatible = "fsl,imx53-esdhc";
	reg = <0x50008000 0x4000>;
	interrupts = <2>;
	clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
	<&clks IMX5_CLK_DUMMY>,
	<&clks IMX5_CLK_ESDHC2_PER_GATE>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	uart3: serial@5000c000 {
	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	reg = <0x5000c000 0x4000>;
	interrupts = <33>;
	clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
	<&clks IMX5_CLK_UART3_PER_GATE>;
	clock-names = "ipg", "per";
	dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	ecspi1: spi@50010000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
	reg = <0x50010000 0x4000>;
	interrupts = <36>;
	clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
	<&clks IMX5_CLK_ECSPI1_PER_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ssi2: ssi@50014000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx53-ssi",
	"fsl,imx51-ssi",
	"fsl,imx21-ssi";
	reg = <0x50014000 0x4000>;
	interrupts = <30>;
	clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
	<&clks IMX5_CLK_SSI2_ROOT_GATE>;
	clock-names = "ipg", "baud";
	dmas = <&sdma 24 1 0>,
	<&sdma 25 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	esdhc3: esdhc@50020000 {
	compatible = "fsl,imx53-esdhc";
	reg = <0x50020000 0x4000>;
	interrupts = <3>;
	clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
	<&clks IMX5_CLK_DUMMY>,
	<&clks IMX5_CLK_ESDHC3_PER_GATE>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	esdhc4: esdhc@50024000 {
	compatible = "fsl,imx53-esdhc";
	reg = <0x50024000 0x4000>;
	interrupts = <4>;
	clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
	<&clks IMX5_CLK_DUMMY>,
	<&clks IMX5_CLK_ESDHC4_PER_GATE>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};
	};

	aipstz1: bridge@53f00000 {
	compatible = "fsl,imx53-aipstz";
	reg = <0x53f00000 0x60>;
	};

	usbotg: usb@53f80000 {
	compatible = "fsl,imx53-usb", "fsl,imx27-usb";
	reg = <0x53f80000 0x0200>;
	interrupts = <18>;
	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
	fsl,usbmisc = <&usbmisc 0>;
	fsl,usbphy = <&usbphy0>;
	status = "disabled";
	};

	usbh1: usb@53f80200 {
	compatible = "fsl,imx53-usb", "fsl,imx27-usb";
	reg = <0x53f80200 0x0200>;
	interrupts = <14>;
	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
	fsl,usbmisc = <&usbmisc 1>;
	fsl,usbphy = <&usbphy1>;
	dr_mode = "host";
	status = "disabled";
	};

	usbh2: usb@53f80400 {
	compatible = "fsl,imx53-usb", "fsl,imx27-usb";
	reg = <0x53f80400 0x0200>;
	interrupts = <16>;
	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
	fsl,usbmisc = <&usbmisc 2>;
	dr_mode = "host";
	status = "disabled";
	};

	usbh3: usb@53f80600 {
	compatible = "fsl,imx53-usb", "fsl,imx27-usb";
	reg = <0x53f80600 0x0200>;
	interrupts = <17>;
	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
	fsl,usbmisc = <&usbmisc 3>;
	dr_mode = "host";
	status = "disabled";
	};

	usbmisc: usbmisc@53f80800 {
	#index-cells = <1>;
	compatible = "fsl,imx53-usbmisc";
	reg = <0x53f80800 0x200>;
	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
	};

	gpio1: gpio@53f84000 {
	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
	reg = <0x53f84000 0x4000>;
	interrupts = <50 51>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio@53f88000 {
	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
	reg = <0x53f88000 0x4000>;
	interrupts = <52 53>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio@53f8c000 {
	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
	reg = <0x53f8c000 0x4000>;
	interrupts = <54 55>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio4: gpio@53f90000 {
	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
	reg = <0x53f90000 0x4000>;
	interrupts = <56 57>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	kpp: kpp@53f94000 {
	compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
	reg = <0x53f94000 0x4000>;
	interrupts = <60>;
	clocks = <&clks IMX5_CLK_DUMMY>;
	status = "disabled";
	};

	wdog1: wdog@53f98000 {
	compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
	reg = <0x53f98000 0x4000>;
	interrupts = <58>;
	clocks = <&clks IMX5_CLK_DUMMY>;
	};

	wdog2: wdog@53f9c000 {
	compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
	reg = <0x53f9c000 0x4000>;
	interrupts = <59>;
	clocks = <&clks IMX5_CLK_DUMMY>;
	status = "disabled";
	};

	gpt: timer@53fa0000 {
	compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
	reg = <0x53fa0000 0x4000>;
	interrupts = <39>;
	clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
	<&clks IMX5_CLK_GPT_HF_GATE>;
	clock-names = "ipg", "per";
	};

	srtc: rtc@53fa4000 {
	compatible = "fsl,imx53-rtc";
	reg = <0x53fa4000 0x4000>;
	interrupts = <24>;
	clocks = <&clks IMX5_CLK_SRTC_GATE>;
	};

	iomuxc: iomuxc@53fa8000 {
	compatible = "fsl,imx53-iomuxc";
	reg = <0x53fa8000 0x4000>;
	};

	gpr: iomuxc-gpr@53fa8000 {
	compatible = "fsl,imx53-iomuxc-gpr", "syscon";
	reg = <0x53fa8000 0xc>;
	};

	ldb: ldb@53fa8008 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx53-ldb";
	reg = <0x53fa8008 0x4>;
	gpr = <&gpr>;
	clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
	<&clks IMX5_CLK_LDB_DI1_SEL>,
	<&clks IMX5_CLK_IPU_DI0_SEL>,
	<&clks IMX5_CLK_IPU_DI1_SEL>,
	<&clks IMX5_CLK_LDB_DI0_GATE>,
	<&clks IMX5_CLK_LDB_DI1_GATE>;
	clock-names = "di0_pll", "di1_pll",
	"di0_sel", "di1_sel",
	"di0", "di1";
	status = "disabled";

	lvds-channel@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;
	status = "disabled";

	port@0 {
	reg = <0>;

	lvds0_in: endpoint {
	remote-endpoint = <&ipu_di0_lvds0>;
	};
	};

	port@2 {
	reg = <2>;
	};
	};

	lvds-channel@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;
	status = "disabled";

	port@1 {
	reg = <1>;

	lvds1_in: endpoint {
	remote-endpoint = <&ipu_di1_lvds1>;
	};
	};

	port@2 {
	reg = <2>;
	};
	};
	};

	pwm1: pwm@53fb4000 {
	#pwm-cells = <2>;
	compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
	reg = <0x53fb4000 0x4000>;
	clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
	<&clks IMX5_CLK_PWM1_HF_GATE>;
	clock-names = "ipg", "per";
	interrupts = <61>;
	};

	pwm2: pwm@53fb8000 {
	#pwm-cells = <2>;
	compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
	reg = <0x53fb8000 0x4000>;
	clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
	<&clks IMX5_CLK_PWM2_HF_GATE>;
	clock-names = "ipg", "per";
	interrupts = <94>;
	};

	uart1: serial@53fbc000 {
	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	reg = <0x53fbc000 0x4000>;
	interrupts = <31>;
	clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
	<&clks IMX5_CLK_UART1_PER_GATE>;
	clock-names = "ipg", "per";
	dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart2: serial@53fc0000 {
	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	reg = <0x53fc0000 0x4000>;
	interrupts = <32>;
	clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
	<&clks IMX5_CLK_UART2_PER_GATE>;
	clock-names = "ipg", "per";
	dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	can1: can@53fc8000 {
	compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
	reg = <0x53fc8000 0x4000>;
	interrupts = <82>;
	clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
	<&clks IMX5_CLK_CAN1_SERIAL_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	can2: can@53fcc000 {
	compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
	reg = <0x53fcc000 0x4000>;
	interrupts = <83>;
	clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
	<&clks IMX5_CLK_CAN2_SERIAL_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	src: src@53fd0000 {
	compatible = "fsl,imx53-src", "fsl,imx51-src";
	reg = <0x53fd0000 0x4000>;
	#reset-cells = <1>;
	};

	clks: ccm@53fd4000{
	compatible = "fsl,imx53-ccm";
	reg = <0x53fd4000 0x4000>;
	interrupts = <0 71 0x04 0 72 0x04>;
	#clock-cells = <1>;
	};

	gpio5: gpio@53fdc000 {
	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
	reg = <0x53fdc000 0x4000>;
	interrupts = <103 104>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio6: gpio@53fe0000 {
	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
	reg = <0x53fe0000 0x4000>;
	interrupts = <105 106>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio7: gpio@53fe4000 {
	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
	reg = <0x53fe4000 0x4000>;
	interrupts = <107 108>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	i2c3: i2c@53fec000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
	reg = <0x53fec000 0x4000>;
	interrupts = <64>;
	clocks = <&clks IMX5_CLK_I2C3_GATE>;
	status = "disabled";
	};

	uart4: serial@53ff0000 {
	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	reg = <0x53ff0000 0x4000>;
	interrupts = <13>;
	clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
	<&clks IMX5_CLK_UART4_PER_GATE>;
	clock-names = "ipg", "per";
	dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};
	};

	- aips@60000000 { /* AIPS2 */
	+ bus@60000000 { /* AIPS2 */
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x60000000 0x10000000>;
	ranges;

	aipstz2: bridge@63f00000 {
	compatible = "fsl,imx53-aipstz";
	reg = <0x63f00000 0x60>;
	};

	iim: iim@63f98000 {
	compatible = "fsl,imx53-iim", "fsl,imx27-iim";
	reg = <0x63f98000 0x4000>;
	interrupts = <69>;
	clocks = <&clks IMX5_CLK_IIM_GATE>;
	};

	uart5: serial@63f90000 {
	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	reg = <0x63f90000 0x4000>;
	interrupts = <86>;
	clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
	<&clks IMX5_CLK_UART5_PER_GATE>;
	clock-names = "ipg", "per";
	dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	tigerp: tigerp@63fa0000 {
	compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp";
	reg = <0x63fa0000 0x28>;
	};

	owire: owire@63fa4000 {
	compatible = "fsl,imx53-owire", "fsl,imx21-owire";
	reg = <0x63fa4000 0x4000>;
	clocks = <&clks IMX5_CLK_OWIRE_GATE>;
	status = "disabled";
	};

	ecspi2: spi@63fac000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
	reg = <0x63fac000 0x4000>;
	interrupts = <37>;
	clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
	<&clks IMX5_CLK_ECSPI2_PER_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	sdma: sdma@63fb0000 {
	compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
	reg = <0x63fb0000 0x4000>;
	interrupts = <6>;
	clocks = <&clks IMX5_CLK_SDMA_GATE>,
	<&clks IMX5_CLK_AHB>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
	};

	cspi: spi@63fc0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
	reg = <0x63fc0000 0x4000>;
	interrupts = <38>;
	clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
	<&clks IMX5_CLK_CSPI_IPG_GATE>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	i2c2: i2c@63fc4000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
	reg = <0x63fc4000 0x4000>;
	interrupts = <63>;
	clocks = <&clks IMX5_CLK_I2C2_GATE>;
	status = "disabled";
	};

	i2c1: i2c@63fc8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
	reg = <0x63fc8000 0x4000>;
	interrupts = <62>;
	clocks = <&clks IMX5_CLK_I2C1_GATE>;
	status = "disabled";
	};

	ssi1: ssi@63fcc000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
	"fsl,imx21-ssi";
	reg = <0x63fcc000 0x4000>;
	interrupts = <29>;
	clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
	<&clks IMX5_CLK_SSI1_ROOT_GATE>;
	clock-names = "ipg", "baud";
	dmas = <&sdma 28 0 0>,
	<&sdma 29 0 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	audmux: audmux@63fd0000 {
	compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
	reg = <0x63fd0000 0x4000>;
	status = "disabled";
	};

	nfc: nand@63fdb000 {
	compatible = "fsl,imx53-nand";
	reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
	interrupts = <8>;
	clocks = <&clks IMX5_CLK_NFC_GATE>;
	status = "disabled";
	};

	ssi3: ssi@63fe8000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
	"fsl,imx21-ssi";
	reg = <0x63fe8000 0x4000>;
	interrupts = <96>;
	clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
	<&clks IMX5_CLK_SSI3_ROOT_GATE>;
	clock-names = "ipg", "baud";
	dmas = <&sdma 46 0 0>,
	<&sdma 47 0 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	fec: ethernet@63fec000 {
	compatible = "fsl,imx53-fec", "fsl,imx25-fec";
	reg = <0x63fec000 0x4000>;
	interrupts = <87>;
	clocks = <&clks IMX5_CLK_FEC_GATE>,
	<&clks IMX5_CLK_FEC_GATE>,
	<&clks IMX5_CLK_FEC_GATE>;
	clock-names = "ipg", "ahb", "ptp";
	status = "disabled";
	};

	tve: tve@63ff0000 {
	compatible = "fsl,imx53-tve";
	reg = <0x63ff0000 0x1000>;
	interrupts = <92>;
	clocks = <&clks IMX5_CLK_TVE_GATE>,
	<&clks IMX5_CLK_IPU_DI1_SEL>;
	clock-names = "tve", "di_sel";
	status = "disabled";

	port {
	tve_in: endpoint {
	remote-endpoint = <&ipu_di1_tve>;
	};
	};
	};

	vpu: vpu@63ff4000 {
	compatible = "fsl,imx53-vpu", "cnm,coda7541";
	reg = <0x63ff4000 0x1000>;
	interrupts = <9>;
	clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
	<&clks IMX5_CLK_VPU_GATE>;
	clock-names = "per", "ahb";
	resets = <&src 1>;
	iram = <&ocram>;
	};

	sahara: crypto@63ff8000 {
	compatible = "fsl,imx53-sahara";
	reg = <0x63ff8000 0x4000>;
	interrupts = <19 20>;
	clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
	<&clks IMX5_CLK_SAHARA_IPG_GATE>;
	clock-names = "ipg", "ahb";
	};
	};

	ocram: sram@f8000000 {
	compatible = "mmio-sram";
	reg = <0xf8000000 0x20000>;
	clocks = <&clks IMX5_CLK_OCRAM>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6dl-colibri-eval-v3.dts b/sys/gnu/dts/arm/imx6dl-colibri-eval-v3.dts
	index 84fcc203a2e4..65359aece950 100644
	--- a/sys/gnu/dts/arm/imx6dl-colibri-eval-v3.dts
	+++ b/sys/gnu/dts/arm/imx6dl-colibri-eval-v3.dts
	@@ -1,297 +1,261 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2014-2016 Toradex AG
	+ * Copyright 2014-2020 Toradex
	* Copyright 2012 Freescale Semiconductor, Inc.
	* Copyright 2011 Linaro Ltd.
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License
	- * version 2 as published by the Free Software Foundation.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	*/

	/dts-v1/;

	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include "imx6dl.dtsi"
	#include "imx6qdl-colibri.dtsi"

	/ {
	model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3";
	compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl",
	"fsl,imx6dl";

	/* Will be filled by the bootloader */
	memory@10000000 {
	device_type = "memory";
	reg = <0x10000000 0>;
	};

	aliases {
	i2c0 = &i2c2;
	i2c1 = &i2c3;
	};

	aliases {
	rtc0 = &rtc_i2c;
	rtc1 = &snvs_rtc;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	/* Fixed crystal dedicated to mcp251x */
	clk16m: clock-16m {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <16000000>;
	clock-output-names = "clk16m";
	};

	gpio-keys {
	compatible = "gpio-keys";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_keys>;

	wakeup {
	label = "Wake-Up";
	gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
	linux,code = <KEY_WAKEUP>;
	debounce-interval = <10>;
	wakeup-source;
	};
	};

	lcd_display: disp0 {
	compatible = "fsl,imx-parallel-display";
	#address-cells = <1>;
	#size-cells = <0>;
	interface-pix-fmt = "bgr666";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ipu1_lcdif>;
	status = "okay";

	port@0 {
	reg = <0>;

	lcd_display_in: endpoint {
	remote-endpoint = <&ipu1_di0_disp0>;
	};
	};

	port@1 {
	reg = <1>;

	lcd_display_out: endpoint {
	remote-endpoint = <&lcd_panel_in>;
	};
	};
	};

	panel: panel {
	/*
	* edt,et057090dhu: EDT 5.7" LCD TFT
	* edt,et070080dh6: EDT 7.0" LCD TFT
	*/
	compatible = "edt,et057090dhu";
	backlight = <&backlight>;

	port {
	lcd_panel_in: endpoint {
	remote-endpoint = <&lcd_display_out>;
	};
	};
	};
	};

	&backlight {
	brightness-levels = <0 127 191 223 239 247 251 255>;
	default-brightness-level = <1>;
	status = "okay";
	};

	/* Colibri SSP */
	&ecspi4 {
	status = "okay";

	mcp251x0: mcp251x@0 {
	compatible = "microchip,mcp2515";
	reg = <0>;
	clocks = <&clk16m>;
	interrupt-parent = <&gpio3>;
	interrupts = <27 0x2>;
	spi-max-frequency = <10000000>;
	status = "okay";
	};
	};

	&hdmi {
	status = "okay";
	};

	/*
	* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
	*/
	&i2c3 {
	status = "okay";

	/*
	* Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
	* aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
	*/
	touchscreen@4a {
	compatible = "atmel,maxtouch";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcap_1>;
	reg = <0x4a>;
	interrupt-parent = <&gpio1>;
	interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
	reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */
	status = "disabled";
	};

	/* M41T0M6 real time clock on carrier board */
	rtc_i2c: rtc@68 {
	compatible = "st,m41t0";
	reg = <0x68>;
	};
	};

	&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <
	&pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2
	&pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4
	&pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6
	&pinctrl_usbh_oc_1 &pinctrl_usbc_id_1
	>;

	pinctrl_pcap_1: pcap1grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* SODIMM 28 */
	MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */
	>;
	};

	pinctrl_mxt_ts: mxttsgrp {
	fsl,pins = <
	MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */
	MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */
	>;
	};
	};

	&ipu1_di0_disp0 {
	remote-endpoint = <&lcd_display_in>;
	};

	&pwm1 {
	status = "okay";
	};

	&pwm2 {
	status = "okay";
	};

	&pwm3 {
	status = "okay";
	};

	&pwm4 {
	status = "okay";
	};

	&reg_usb_host_vbus {
	status = "okay";
	};

	&uart1 {
	status = "okay";
	};

	&uart2 {
	status = "okay";
	};

	&uart3 {
	status = "okay";
	};

	&usbh1 {
	vbus-supply = <&reg_usb_host_vbus>;
	status = "okay";
	};

	&usbotg {
	status = "okay";
	};

	/* Colibri MMC */
	&usdhc1 {
	status = "okay";
	};

	&weim {
	status = "okay";

	/* weim memory map: 32MB on CS0, CS1, CS2 and CS3 */
	ranges = <0 0 0x08000000 0x02000000
	1 0 0x0a000000 0x02000000
	2 0 0x0c000000 0x02000000
	3 0 0x0e000000 0x02000000>;

	/* SRAM on Colibri nEXT_CS0 */
	sram@0,0 {
	compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram";
	reg = <0 0 0x00010000>;
	#address-cells = <1>;
	#size-cells = <1>;
	bank-width = <2>;
	fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
	0x00000000 0x04000040 0x00000000>;
	};

	/* SRAM on Colibri nEXT_CS1 */
	sram@1,0 {
	compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram";
	reg = <1 0 0x00010000>;
	#address-cells = <1>;
	#size-cells = <1>;
	bank-width = <2>;
	fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
	0x00000000 0x04000040 0x00000000>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6dl-pico-dwarf.dts b/sys/gnu/dts/arm/imx6dl-pico-dwarf.dts
	new file mode 100644
	index 000000000000..659a8e8714ea
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx6dl-pico-dwarf.dts
	@@ -0,0 +1,17 @@
	+// SPDX-License-Identifier: GPL-2.0 OR MIT
	+//
	+// Copyright 2018 Technexion Ltd.
	+//
	+// Author: Wig Cheng <wig.cheng@technexion.com>
	+// Richard Hu <richard.hu@technexion.com>
	+// Tapani Utriainen <tapani@technexion.com>
	+
	+/dts-v1/;
	+
	+#include "imx6dl.dtsi"
	+#include "imx6qdl-pico-pi.dtsi"
	+
	+/ {
	+ model = "TechNexion PICO-IMX6 DualLite/Solo Board and Dwarf baseboard";
	+ compatible = "technexion,imx6dl-pico", "fsl,imx6dl";
	+};
	diff --git a/sys/gnu/dts/arm/imx6dl-pico-hobbit.dts b/sys/gnu/dts/arm/imx6dl-pico-hobbit.dts
	new file mode 100644
	index 000000000000..d7403c5c4337
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx6dl-pico-hobbit.dts
	@@ -0,0 +1,17 @@
	+// SPDX-License-Identifier: GPL-2.0 OR MIT
	+//
	+// Copyright 2018 Technexion Ltd.
	+//
	+// Author: Wig Cheng <wig.cheng@technexion.com>
	+// Richard Hu <richard.hu@technexion.com>
	+// Tapani Utriainen <tapani@technexion.com>
	+
	+/dts-v1/;
	+
	+#include "imx6dl.dtsi"
	+#include "imx6qdl-pico-hobbit.dtsi"
	+
	+/ {
	+ model = "TechNexion PICO-IMX6 DualLite/Solo Board and Hobbit baseboard";
	+ compatible = "technexion,imx6dl-pico", "fsl,imx6dl";
	+};
	diff --git a/sys/gnu/dts/arm/imx6dl-pico-nymph.dts b/sys/gnu/dts/arm/imx6dl-pico-nymph.dts
	new file mode 100644
	index 000000000000..b282dbf953aa
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx6dl-pico-nymph.dts
	@@ -0,0 +1,17 @@
	+// SPDX-License-Identifier: GPL-2.0 OR MIT
	+//
	+// Copyright 2018 Technexion Ltd.
	+//
	+// Author: Wig Cheng <wig.cheng@technexion.com>
	+// Richard Hu <richard.hu@technexion.com>
	+// Tapani Utriainen <tapani@technexion.com>
	+
	+/dts-v1/;
	+
	+#include "imx6dl.dtsi"
	+#include "imx6qdl-pico-pi.dtsi"
	+
	+/ {
	+ model = "TechNexion PICO-IMX6 DualLite/Solo Board and Nymph baseboard";
	+ compatible = "technexion,imx6dl-pico", "fsl,imx6dl";
	+};
	diff --git a/sys/gnu/dts/arm/imx6dl-pico-pi.dts b/sys/gnu/dts/arm/imx6dl-pico-pi.dts
	new file mode 100644
	index 000000000000..b7b1c07f96f3
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx6dl-pico-pi.dts
	@@ -0,0 +1,17 @@
	+// SPDX-License-Identifier: GPL-2.0 OR MIT
	+//
	+// Copyright 2018 Technexion Ltd.
	+//
	+// Author: Wig Cheng <wig.cheng@technexion.com>
	+// Richard Hu <richard.hu@technexion.com>
	+// Tapani Utriainen <tapani@technexion.com>
	+
	+/dts-v1/;
	+
	+#include "imx6dl.dtsi"
	+#include "imx6qdl-pico-pi.dtsi"
	+
	+/ {
	+ model = "TechNexion PICO-IMX6 DualLite/Solo Board and PI baseboard";
	+ compatible = "technexion,imx6dl-pico", "fsl,imx6dl";
	+};
	diff --git a/sys/gnu/dts/arm/imx6dl-riotboard.dts b/sys/gnu/dts/arm/imx6dl-riotboard.dts
	index 829654e1835a..065d3ab0f50a 100644
	--- a/sys/gnu/dts/arm/imx6dl-riotboard.dts
	+++ b/sys/gnu/dts/arm/imx6dl-riotboard.dts
	@@ -1,580 +1,594 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright 2014 Iain Paton <ipaton0@gmail.com>
	*/

	/dts-v1/;
	#include "imx6dl.dtsi"
	#include <dt-bindings/gpio/gpio.h>

	/ {
	model = "RIoTboard i.MX6S";
	compatible = "riot,imx6s-riotboard", "fsl,imx6dl";

	memory@10000000 {
	device_type = "memory";
	reg = <0x10000000 0x40000000>;
	};

	chosen {
	stdout-path = "serial1:115200n8";
	};

	leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_led>;

	led0: user1 {
	label = "user1";
	gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
	default-state = "on";
	linux,default-trigger = "heartbeat";
	};

	led1: user2 {
	label = "user2";
	gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
	default-state = "off";
	};
	};

	sound {
	compatible = "fsl,imx-audio-sgtl5000";
	model = "imx6-riotboard-sgtl5000";
	ssi-controller = <&ssi1>;
	audio-codec = <&codec>;
	audio-routing =
	"MIC_IN", "Mic Jack",
	"Mic Jack", "Mic Bias",
	"Headphone Jack", "HP_OUT";
	mux-int-port = <1>;
	mux-ext-port = <3>;
	};

	reg_2p5v: regulator-2p5v {
	compatible = "regulator-fixed";
	regulator-name = "2P5V";
	regulator-min-microvolt = <2500000>;
	regulator-max-microvolt = <2500000>;
	};

	reg_3p3v: regulator-3p3v {
	compatible = "regulator-fixed";
	regulator-name = "3P3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	reg_usb_otg_vbus: regulator-usbotgvbus {
	compatible = "regulator-fixed";
	regulator-name = "usb_otg_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
	};
	};

	&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
	};

	&clks {
	fsl,pmic-stby-poweroff;
	};

	&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii-id";
	- phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
	+ phy-handle = <&rgmii_phy>;
	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
	<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
	fsl,err006687-workaround-present;
	status = "okay";
	+
	+ mdio {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ /* Atheros AR8035 PHY */
	+ rgmii_phy: ethernet-phy@4 {
	+ reg = <4>;
	+ interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
	+ reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
	+ reset-assert-us = <10000>;
	+ reset-deassert-us = <1000>;
	+ };
	+ };
	};

	&gpio1 {
	gpio-line-names =
	"", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL",
	"I2C3_SDA", "I2C4_SCL",
	"I2C4_SDA", "", "", "", "", "", "", "",
	"", "PWM3", "", "", "", "", "", "",
	"", "", "", "", "", "", "", "";
	};

	&gpio3 {
	gpio-line-names =
	"", "", "", "", "", "", "", "",
	"", "", "", "", "", "", "", "",
	"", "", "", "", "", "", "USB_OTG_VBUS", "",
	"UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", "";
	};

	&gpio4 {
	gpio-line-names =
	"", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
	"UART5_TXD", "UART5_RXD", "", "", "", "", "", "",
	"GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "",
	"CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO",
	"CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27",
	"CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31";
	};

	&gpio5 {
	gpio-line-names =
	"", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06",
	"GPIO5_07",
	"GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO",
	"CSPI2_CS0", "CSPI2_CLK", "", "",
	"", "", "", "", "", "", "", "",
	"", "", "", "", "", "", "", "";
	};

	&gpio7 {
	gpio-line-names =
	"SD3_CD", "SD3_WP", "", "", "", "", "", "",
	"", "", "", "", "", "", "", "",
	"", "", "", "", "", "", "", "",
	"", "", "", "", "", "", "", "";
	};

	&hdmi {
	ddc-i2c-bus = <&i2c2>;
	status = "okay";
	};

	&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	codec: sgtl5000@a {
	compatible = "fsl,sgtl5000";
	reg = <0x0a>;
	clocks = <&clks IMX6QDL_CLK_CKO>;
	VDDA-supply = <&reg_2p5v>;
	VDDIO-supply = <&reg_3p3v>;
	};

	pmic: pf0100@8 {
	compatible = "fsl,pfuze100";
	reg = <0x08>;
	interrupt-parent = <&gpio5>;
	interrupts = <16 8>;
	fsl,pmic-stby-poweroff;

	regulators {
	reg_vddcore: sw1ab { /* VDDARM_IN */
	regulator-min-microvolt = <300000>;
	regulator-max-microvolt = <1875000>;
	regulator-always-on;
	};

	reg_vddsoc: sw1c { /* VDDSOC_IN */
	regulator-min-microvolt = <300000>;
	regulator-max-microvolt = <1875000>;
	regulator-always-on;
	};

	reg_gen_3v3: sw2 { /* VDDHIGH_IN */
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <1975000>;
	regulator-always-on;
	};

	reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <1975000>;
	regulator-always-on;
	};

	reg_ddr_vtt: sw4 { /* MIPI conn */
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <1975000>;
	regulator-always-on;
	};

	reg_5v_600mA: swbst { /* not used */
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5150000>;
	};

	reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;
	};

	vref_reg: vrefddr { /* VREF_DDR */
	regulator-boot-on;
	regulator-always-on;
	};

	reg_vgen1_1v5: vgen1 { /* not used */
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	};

	reg_vgen2_1v2_eth: vgen2 { /* pcie ? */
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	regulator-always-on;
	};

	reg_vgen3_2v8: vgen3 { /* not used */
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	};
	reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};
	};
	};
	};

	&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
	};

	&i2c4 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	clocks = <&clks 116>;
	status = "okay";
	};

	&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "okay";
	};

	&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	status = "okay";
	};

	&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "okay";
	};

	&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
	status = "okay";
	};

	&ssi1 {
	status = "okay";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
	};

	&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
	};

	&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
	};

	&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	status = "okay";
	};

	&usbh1 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
	};

	&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	disable-over-current;
	dr_mode = "otg";
	status = "okay";
	};

	&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
	vmmc-supply = <&reg_3p3v>;
	status = "okay";
	};

	&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
	vmmc-supply = <&reg_3p3v>;
	status = "okay";
	};

	&usdhc4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4>;
	vmmc-supply = <&reg_3p3v>;
	non-removable;
	status = "okay";
	};

	&iomuxc {
	pinctrl-names = "default";

	imx6-riotboard {
	pinctrl_audmux: audmuxgrp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
	MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
	MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
	MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
	MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */
	>;
	};

	pinctrl_ecspi1: ecspi1grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
	MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
	MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
	MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */
	>;
	};

	pinctrl_ecspi2: ecspi2grp {
	fsl,pins = <
	MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */
	MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1
	MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1
	MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */
	MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1
	>;
	};

	pinctrl_ecspi3: ecspi3grp {
	fsl,pins = <
	MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
	MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
	MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
	MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */
	MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */
	>;
	};

	pinctrl_enet: enetgrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */
	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */
	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */
	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */
	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */
	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */
	MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */
	MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
	MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */
	MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
	MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
	MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c4: i2c4grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
	MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
	>;
	};

	pinctrl_led: ledgrp {
	fsl,pins = <
	MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */
	MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */
	>;
	};

	pinctrl_pwm1: pwm1grp {
	fsl,pins = <
	MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm2: pwm2grp {
	fsl,pins = <
	MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm3: pwm3grp {
	fsl,pins = <
	MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm4: pwm4grp {
	fsl,pins = <
	MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
	MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
	MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart3: uart3grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
	MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart4: uart4grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
	MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart5: uart5grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
	MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_usbotg: usbotggrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
	MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
	MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
	>;
	};

	pinctrl_usdhc2: usdhc2grp {
	fsl,pins = <
	MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
	MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
	MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
	MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
	MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
	MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
	MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */
	MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */
	MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */
	>;
	};

	pinctrl_usdhc4: usdhc4grp {
	fsl,pins = <
	MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
	MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
	MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
	MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
	MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
	MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
	MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */
	>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6dl-yapp4-common.dtsi b/sys/gnu/dts/arm/imx6dl-yapp4-common.dtsi
	index 80ed5f16a76e..2b9423d55c37 100644
	--- a/sys/gnu/dts/arm/imx6dl-yapp4-common.dtsi
	+++ b/sys/gnu/dts/arm/imx6dl-yapp4-common.dtsi
	@@ -1,621 +1,623 @@
	// SPDX-License-Identifier: GPL-2.0
	//
	// Copyright (C) 2015-2018 Y Soft Corporation, a.s.

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/pwm/pwm.h>

	/ {
	backlight: backlight {
	compatible = "pwm-backlight";
	pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
	brightness-levels = <0 32 64 128 255>;
	default-brightness-level = <32>;
	num-interpolated-steps = <8>;
	power-supply = <&sw2_reg>;
	status = "disabled";
	};

	lcd_display: display {
	compatible = "fsl,imx-parallel-display";
	#address-cells = <1>;
	#size-cells = <0>;
	interface-pix-fmt = "rgb24";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ipu1>;
	status = "disabled";

	port@0 {
	reg = <0>;

	lcd_display_in: endpoint {
	remote-endpoint = <&ipu1_di0_disp0>;
	};
	};

	port@1 {
	reg = <1>;

	lcd_display_out: endpoint {
	remote-endpoint = <&lcd_panel_in>;
	};
	};
	};

	panel: panel {
	compatible = "dataimage,scf0700c48ggu18";
	power-supply = <&sw2_reg>;
	status = "disabled";

	port {
	lcd_panel_in: endpoint {
	remote-endpoint = <&lcd_display_out>;
	};
	};
	};

	reg_pcie: regulator-pcie {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie_reg>;
	regulator-name = "MPCIE_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	status = "disabled";
	};

	reg_usb_h1_vbus: regulator-usb-h1-vbus {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbh1_vbus>;
	regulator-name = "usb_h1_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	status = "disabled";
	};

	reg_usb_otg_vbus: regulator-usb-otg-vbus {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg_vbus>;
	regulator-name = "usb_otg_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	status = "okay";
	};
	};

	&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii-id";
	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <20>;
	phy-supply = <&sw2_reg>;
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	phy_port2: phy@1 {
	reg = <1>;
	};

	phy_port3: phy@2 {
	reg = <2>;
	};

	switch@10 {
	compatible = "qca,qca8334";
	reg = <10>;

	switch_ports: ports {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy0: port@0 {
	reg = <0>;
	label = "cpu";
	phy-mode = "rgmii-id";
	ethernet = <&fec>;

	fixed-link {
	speed = <1000>;
	full-duplex;
	};
	};

	port@2 {
	reg = <2>;
	label = "eth2";
	phy-handle = <&phy_port2>;
	};

	port@3 {
	reg = <3>;
	label = "eth1";
	phy-handle = <&phy_port3>;
	};
	};
	};
	};
	};

	&hdmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hdmi_cec>;
	ddc-i2c-bus = <&i2c2>;
	status = "disabled";
	};

	&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	pmic@8 {
	compatible = "fsl,pfuze200";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pmic>;
	reg = <0x8>;

	regulators {
	sw1a_reg: sw1ab {
	regulator-min-microvolt = <300000>;
	regulator-max-microvolt = <1875000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	sw2_reg: sw2 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw3a_reg: sw3a {
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <1975000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw3b_reg: sw3b {
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <1975000>;
	regulator-boot-on;
	regulator-always-on;
	};

	swbst_reg: swbst {
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5150000>;
	};

	vgen1_reg: vgen1 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	};

	vgen2_reg: vgen2 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	};

	vgen3_reg: vgen3 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen4_reg: vgen4 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen5_reg: vgen5 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen6_reg: vgen6 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vref_reg: vrefddr {
	regulator-boot-on;
	regulator-always-on;
	};

	vsnvs_reg: vsnvs {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <3000000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};
	};

	leds: led-controller@30 {
	compatible = "ti,lp5562";
	reg = <0x30>;
	clock-mode = /bits/ 8 <1>;
	status = "disabled";

	chan0 {
	chan-name = "R";
	led-cur = /bits/ 8 <0x20>;
	max-cur = /bits/ 8 <0x60>;
	};

	chan1 {
	chan-name = "G";
	led-cur = /bits/ 8 <0x20>;
	max-cur = /bits/ 8 <0x60>;
	};

	chan2 {
	chan-name = "B";
	led-cur = /bits/ 8 <0x20>;
	max-cur = /bits/ 8 <0x60>;
	};

	chan3 {
	chan-name = "W";
	led-cur = /bits/ 8 <0x0>;
	max-cur = /bits/ 8 <0x0>;
	};
	};

	eeprom@57 {
	compatible = "atmel,24c128";
	reg = <0x57>;
	pagesize = <64>;
	status = "okay";
	};

	touchscreen: touchscreen@5c {
	compatible = "pixcir,pixcir_tangoc";
	reg = <0x5c>;
	pinctrl-0 = <&pinctrl_touch>;
	interrupt-parent = <&gpio4>;
	interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
	attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;
	reset-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
	touchscreen-size-x = <800>;
	touchscreen-size-y = <480>;
	status = "disabled";
	};
	};

	&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	oled: oled@3d {
	compatible = "solomon,ssd1305fb-i2c";
	reg = <0x3d>;
	solomon,height = <64>;
	solomon,width = <128>;
	solomon,page-offset = <0>;
	solomon,prechargep2 = <15>;
	reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>;
	vbat-supply = <&sw2_reg>;
	status = "disabled";
	};

	gpio_oled: gpio@41 {
	compatible = "nxp,pca9536";
	gpio-controller;
	#gpio-cells = <2>;
	reg = <0x41>;
	vcc-supply = <&sw2_reg>;
	status = "disabled";
	};

	touchkeys: keys@5a {
	compatible = "fsl,mpr121-touchkey";
	reg = <0x5a>;
	vdd-supply = <&sw2_reg>;
	autorepeat;
	linux,keycodes = <KEY_1>, <KEY_2>, <KEY_3>, <KEY_4>, <KEY_5>,
	<KEY_6>, <KEY_7>, <KEY_8>, <KEY_9>,
	<KEY_BACKSPACE>, <KEY_0>, <KEY_ENTER>;
	poll-interval = <50>;
	status = "disabled";
	};
	};

	&iomuxc {
	pinctrl_enet: enetgrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b020
	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b020
	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020
	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b020
	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b020
	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b020
	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b020
	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b020
	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b020
	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b020
	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b020
	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b020
	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b020
	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b020
	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b010
	MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b010
	MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b098
	>;
	};

	pinctrl_hdmi_cec: hdmicecgrp {
	fsl,pins = <
	MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1b898
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899
	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b899
	MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899
	>;
	};

	pinctrl_ipu1: ipu1grp {
	fsl,pins = <
	MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
	MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
	MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
	MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
	MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
	MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
	MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
	MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
	MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
	MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
	MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
	MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
	MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
	MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
	MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
	MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
	MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
	MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
	MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
	MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
	MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
	MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
	MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
	MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
	MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
	MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
	MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
	>;
	};

	pinctrl_pcie: pciegrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b098
	MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b098
	MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b098
	>;
	};

	pinctrl_pcie_reg: pciereggrp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b098
	>;
	};

	pinctrl_pmic: pmicgrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b098
	>;
	};

	pinctrl_pwm1: pwm1grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8
	>;
	};

	pinctrl_touch: touchgrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098
	MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b098
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0a8
	MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0a8
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b098
	MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b098
	>;
	};

	pinctrl_usbh1: usbh1grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098
	>;
	};

	pinctrl_usbh1_vbus: usbh1-vbus {
	fsl,pins = <
	MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98
	>;
	};

	pinctrl_usbotg: usbotggrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b098
	MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b098
	>;
	};

	pinctrl_usbotg_vbus: usbotg-vbus {
	fsl,pins = <
	MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b018
	MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b018
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
	>;
	};

	pinctrl_usdhc4: usdhc4grp {
	fsl,pins = <
	MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1f069
	MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10069
	MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17069
	MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17069
	MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17069
	MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17069
	MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17069
	MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17069
	MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17069
	MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17069
	>;
	};

	pinctrl_wdog: wdoggrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
	>;
	};
	};

	&ipu1_di0_disp0 {
	remote-endpoint = <&lcd_display_in>;
	};

	&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
	vpcie-supply = <&reg_pcie>;
	status = "disabled";
	};

	&pwm1 {
	#pwm-cells = <3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "disabled";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
	};

	&usbh1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbh1>;
	vbus-supply = <&reg_usb_h1_vbus>;
	+ over-current-active-low;
	status = "disabled";
	};

	&usbotg {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	vbus-supply = <&reg_usb_otg_vbus>;
	+ over-current-active-low;
	srp-disable;
	hnp-disable;
	adp-disable;
	status = "okay";
	};

	&usbphy1 {
	fsl,tx-d-cal = <106>;
	status = "okay";
	};

	&usbphy2 {
	fsl,tx-d-cal = <109>;
	status = "disabled";
	};

	&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	bus-width = <4>;
	cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
	no-1-8-v;
	keep-power-in-suspend;
	wakeup-source;
	vmmc-supply = <&sw2_reg>;
	status = "disabled";
	};

	&usdhc4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4>;
	bus-width = <8>;
	non-removable;
	no-1-8-v;
	keep-power-in-suspend;
	vmmc-supply = <&sw2_reg>;
	status = "okay";
	};

	&wdog1 {
	status = "disabled";
	};

	&wdog2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/imx6dl-yapp4-ursa.dts b/sys/gnu/dts/arm/imx6dl-yapp4-ursa.dts
	index 0d594e4bd559..a1173bf5bff5 100644
	--- a/sys/gnu/dts/arm/imx6dl-yapp4-ursa.dts
	+++ b/sys/gnu/dts/arm/imx6dl-yapp4-ursa.dts
	@@ -1,54 +1,54 @@
	// SPDX-License-Identifier: GPL-2.0
	//
	// Copyright (C) 2015-2018 Y Soft Corporation, a.s.

	/dts-v1/;

	#include "imx6dl.dtsi"
	#include "imx6dl-yapp4-common.dtsi"

	/ {
	model = "Y Soft IOTA Ursa i.MX6Solo board";
	compatible = "ysoft,imx6dl-yapp4-ursa", "fsl,imx6dl";

	memory@10000000 {
	device_type = "memory";
	reg = <0x10000000 0x20000000>;
	};
	};

	&backlight {
	status = "okay";
	};

	&lcd_display {
	status = "okay";
	};

	&panel {
	status = "okay";
	};

	&pwm1 {
	status = "okay";
	};

	&reg_usb_h1_vbus {
	status = "okay";
	};

	&switch_ports {
	- /delete-node/ port@2;
	+ /delete-node/ port@3;
	};

	&touchscreen {
	status = "okay";
	};

	&usbh1 {
	status = "okay";
	};

	&usbphy2 {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/imx6dl.dtsi b/sys/gnu/dts/arm/imx6dl.dtsi
	index 008312ee0c31..77b65a402e19 100644
	--- a/sys/gnu/dts/arm/imx6dl.dtsi
	+++ b/sys/gnu/dts/arm/imx6dl.dtsi
	@@ -1,392 +1,394 @@
	// SPDX-License-Identifier: GPL-2.0
	//
	// Copyright 2013 Freescale Semiconductor, Inc.

	#include <dt-bindings/interrupt-controller/irq.h>
	#include "imx6dl-pinfunc.h"
	#include "imx6qdl.dtsi"

	/ {
	aliases {
	i2c3 = &i2c4;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <0>;
	next-level-cache = <&L2>;
	operating-points = <
	/* kHz uV */
	996000 1250000
	792000 1175000
	396000 1150000
	>;
	fsl,soc-operating-points = <
	/* ARM kHz SOC-PU uV */
	996000 1175000
	792000 1175000
	396000 1175000
	>;
	clock-latency = <61036>; /* two CLK32 periods */
	#cooling-cells = <2>;
	clocks = <&clks IMX6QDL_CLK_ARM>,
	<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
	<&clks IMX6QDL_CLK_STEP>,
	<&clks IMX6QDL_CLK_PLL1_SW>,
	<&clks IMX6QDL_CLK_PLL1_SYS>;
	clock-names = "arm", "pll2_pfd2_396m", "step",
	"pll1_sw", "pll1_sys";
	arm-supply = <&reg_arm>;
	pu-supply = <&reg_pu>;
	soc-supply = <&reg_soc>;
	+ nvmem-cells = <&cpu_speed_grade>;
	+ nvmem-cell-names = "speed_grade";
	};

	cpu@1 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <1>;
	next-level-cache = <&L2>;
	operating-points = <
	/* kHz uV */
	996000 1250000
	792000 1175000
	396000 1150000
	>;
	fsl,soc-operating-points = <
	/* ARM kHz SOC-PU uV */
	996000 1175000
	792000 1175000
	396000 1175000
	>;
	clock-latency = <61036>; /* two CLK32 periods */
	#cooling-cells = <2>;
	clocks = <&clks IMX6QDL_CLK_ARM>,
	<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
	<&clks IMX6QDL_CLK_STEP>,
	<&clks IMX6QDL_CLK_PLL1_SW>,
	<&clks IMX6QDL_CLK_PLL1_SYS>;
	clock-names = "arm", "pll2_pfd2_396m", "step",
	"pll1_sw", "pll1_sys";
	arm-supply = <&reg_arm>;
	pu-supply = <&reg_pu>;
	soc-supply = <&reg_soc>;
	};
	};

	soc {
	ocram: sram@900000 {
	compatible = "mmio-sram";
	reg = <0x00900000 0x20000>;
	clocks = <&clks IMX6QDL_CLK_OCRAM>;
	};

	- aips1: aips-bus@2000000 {
	- iomuxc: iomuxc@20e0000 {
	+ aips1: bus@2000000 {
	+ iomuxc: pinctrl@20e0000 {
	compatible = "fsl,imx6dl-iomuxc";
	};

	pxp: pxp@20f0000 {
	reg = <0x020f0000 0x4000>;
	interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
	};

	epdc: epdc@20f4000 {
	reg = <0x020f4000 0x4000>;
	interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	- aips2: aips-bus@2100000 {
	+ aips2: bus@2100000 {
	i2c4: i2c@21f8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
	reg = <0x021f8000 0x4000>;
	interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6DL_CLK_I2C4>;
	status = "disabled";
	};
	};
	};

	capture-subsystem {
	compatible = "fsl,imx-capture-subsystem";
	ports = <&ipu1_csi0>, <&ipu1_csi1>;
	};

	display-subsystem {
	compatible = "fsl,imx-display-subsystem";
	ports = <&ipu1_di0>, <&ipu1_di1>;
	};
	};

	&gpio1 {
	gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>,
	<&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
	<&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
	<&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
	<&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
	<&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
	<&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
	};

	&gpio2 {
	gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>,
	<&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>,
	<&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>,
	<&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
	<&iomuxc 28 113 4>;
	};

	&gpio3 {
	gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
	<&iomuxc 16 81 16>;
	};

	&gpio4 {
	gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>,
	<&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>,
	<&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
	<&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>,
	<&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>;
	};

	&gpio5 {
	gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>,
	<&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
	<&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
	<&iomuxc 22 29 6>, <&iomuxc 28 19 4>;
	};

	&gpio6 {
	gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>,
	<&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>,
	<&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
	<&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
	<&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
	<&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>;
	};

	&gpio7 {
	gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>,
	<&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>,
	<&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
	};

	&gpr {
	ipu1_csi0_mux {
	compatible = "video-mux";
	mux-controls = <&mux 0>;
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	ipu1_csi0_mux_from_mipi_vc0: endpoint {
	remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
	};
	};

	port@1 {
	reg = <1>;

	ipu1_csi0_mux_from_mipi_vc1: endpoint {
	remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
	};
	};

	port@2 {
	reg = <2>;

	ipu1_csi0_mux_from_mipi_vc2: endpoint {
	remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
	};
	};

	port@3 {
	reg = <3>;

	ipu1_csi0_mux_from_mipi_vc3: endpoint {
	remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
	};
	};

	port@4 {
	reg = <4>;

	ipu1_csi0_mux_from_parallel_sensor: endpoint {
	};
	};

	port@5 {
	reg = <5>;

	ipu1_csi0_mux_to_ipu1_csi0: endpoint {
	remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
	};
	};
	};

	ipu1_csi1_mux {
	compatible = "video-mux";
	mux-controls = <&mux 1>;
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	ipu1_csi1_mux_from_mipi_vc0: endpoint {
	remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
	};
	};

	port@1 {
	reg = <1>;

	ipu1_csi1_mux_from_mipi_vc1: endpoint {
	remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
	};
	};

	port@2 {
	reg = <2>;

	ipu1_csi1_mux_from_mipi_vc2: endpoint {
	remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
	};
	};

	port@3 {
	reg = <3>;

	ipu1_csi1_mux_from_mipi_vc3: endpoint {
	remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
	};
	};

	port@4 {
	reg = <4>;

	ipu1_csi1_mux_from_parallel_sensor: endpoint {
	};
	};

	port@5 {
	reg = <5>;

	ipu1_csi1_mux_to_ipu1_csi1: endpoint {
	remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
	};
	};
	};
	};

	&gpt {
	compatible = "fsl,imx6dl-gpt";
	};

	&hdmi {
	compatible = "fsl,imx6dl-hdmi";
	};

	&ipu1_csi1 {
	ipu1_csi1_from_ipu1_csi1_mux: endpoint {
	remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
	};
	};

	&ldb {
	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
	<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
	<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
	clock-names = "di0_pll", "di1_pll",
	"di0_sel", "di1_sel",
	"di0", "di1";
	};

	&mipi_csi {
	port@1 {
	reg = <1>;
	#address-cells = <1>;
	#size-cells = <0>;

	mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
	};

	mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
	};
	};

	port@2 {
	reg = <2>;
	#address-cells = <1>;
	#size-cells = <0>;

	mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
	};

	mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
	};
	};

	port@3 {
	reg = <3>;
	#address-cells = <1>;
	#size-cells = <0>;

	mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
	};

	mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
	};
	};

	port@4 {
	reg = <4>;
	#address-cells = <1>;
	#size-cells = <0>;

	mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
	};

	mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
	};
	};
	};

	&mux {
	mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
	<0x34 0x00000038>, /* IPU_CSI1_MUX */
	<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
	<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
	<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
	<0x28 0x00000003>, /* DCIC1_MUX_CTL */
	<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
	};

	&vpu {
	compatible = "fsl,imx6dl-vpu", "cnm,coda960";
	};
	diff --git a/sys/gnu/dts/arm/imx6q-apalis-eval.dts b/sys/gnu/dts/arm/imx6q-apalis-eval.dts
	index 4665e15b196d..fab83abb6466 100644
	--- a/sys/gnu/dts/arm/imx6q-apalis-eval.dts
	+++ b/sys/gnu/dts/arm/imx6q-apalis-eval.dts
	@@ -1,309 +1,273 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2014-2017 Toradex AG
	+ * Copyright 2014-2020 Toradex
	* Copyright 2012 Freescale Semiconductor, Inc.
	* Copyright 2011 Linaro Ltd.
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License
	- * version 2 as published by the Free Software Foundation.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	*/

	/dts-v1/;

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include "imx6q.dtsi"
	#include "imx6qdl-apalis.dtsi"

	/ {
	model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board";
	compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q",
	"fsl,imx6q";

	aliases {
	i2c0 = &i2c1;
	i2c1 = &i2c3;
	i2c2 = &i2c2;
	rtc0 = &rtc_i2c;
	rtc1 = &snvs_rtc;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	gpio-keys {
	compatible = "gpio-keys";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_keys>;

	wakeup {
	label = "Wake-Up";
	gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_WAKEUP>;
	debounce-interval = <10>;
	wakeup-source;
	};
	};

	lcd_display: disp0 {
	compatible = "fsl,imx-parallel-display";
	#address-cells = <1>;
	#size-cells = <0>;
	interface-pix-fmt = "rgb24";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ipu1_lcdif>;
	status = "okay";

	port@0 {
	reg = <0>;

	lcd_display_in: endpoint {
	remote-endpoint = <&ipu1_di1_disp1>;
	};
	};

	port@1 {
	reg = <1>;

	lcd_display_out: endpoint {
	remote-endpoint = <&lcd_panel_in>;
	};
	};
	};

	panel: panel {
	/*
	* edt,et057090dhu: EDT 5.7" LCD TFT
	* edt,et070080dh6: EDT 7.0" LCD TFT
	*/
	compatible = "edt,et057090dhu";
	backlight = <&backlight>;
	power-supply = <&reg_3v3_sw>;

	port {
	lcd_panel_in: endpoint {
	remote-endpoint = <&lcd_display_out>;
	};
	};
	};

	reg_pcie_switch: regulator-pcie-switch {
	compatible = "regulator-fixed";
	regulator-name = "pcie_switch";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
	startup-delay-us = <100000>;
	enable-active-high;
	status = "okay";
	};

	reg_3v3_sw: regulator-3v3-sw {
	compatible = "regulator-fixed";
	regulator-name = "3.3V_SW";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};
	};

	&backlight {
	brightness-levels = <0 127 191 223 239 247 251 255>;
	default-brightness-level = <1>;
	power-supply = <&reg_3v3_sw>;
	status = "okay";
	};

	&can1 {
	xceiver-supply = <&reg_3v3_sw>;
	status = "okay";
	};

	&can2 {
	xceiver-supply = <&reg_3v3_sw>;
	status = "okay";
	};

	&hdmi {
	status = "okay";
	};

	/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
	&i2c1 {
	status = "okay";

	/*
	* Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
	* aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
	*/
	touchscreen@4a {
	compatible = "atmel,maxtouch";
	reg = <0x4a>;
	interrupt-parent = <&gpio6>;
	interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
	reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
	status = "disabled";
	};

	pcie-switch@58 {
	compatible = "plx,pex8605";
	reg = <0x58>;
	};

	/* M41T0M6 real time clock on carrier board */
	rtc_i2c: rtc@68 {
	compatible = "st,m41t0";
	reg = <0x68>;
	};
	};

	/*
	* I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
	* board)
	*/
	&i2c3 {
	status = "okay";
	};

	&ipu1_di1_disp1 {
	remote-endpoint = <&lcd_display_in>;
	};

	&ldb {
	status = "okay";
	};

	&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_reset_moci>;
	/* active-high meaning opposite of regular PERST# active-low polarity */
	reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
	reset-gpio-active-high;
	vpcie-supply = <&reg_pcie_switch>;
	status = "okay";
	};

	&pwm1 {
	status = "okay";
	};

	&pwm2 {
	status = "okay";
	};

	&pwm3 {
	status = "okay";
	};

	&pwm4 {
	status = "okay";
	};

	&reg_usb_otg_vbus {
	status = "okay";
	};

	&reg_usb_host_vbus {
	status = "okay";
	};

	&sata {
	status = "okay";
	};

	&sound_spdif {
	status = "okay";
	};

	&spdif {
	status = "okay";
	};

	&uart1 {
	status = "okay";
	};

	&uart2 {
	status = "okay";
	};

	&uart4 {
	status = "okay";
	};

	&uart5 {
	status = "okay";
	};

	&usbh1 {
	vbus-supply = <&reg_usb_host_vbus>;
	status = "okay";
	};

	&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	status = "okay";
	};

	/* MMC1 */
	&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>;
	cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	/* SD1 */
	&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&iomuxc {
	/*
	* Mux the Apalis GPIOs
	*/
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
	&pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
	&pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
	&pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
	>;
	};
	diff --git a/sys/gnu/dts/arm/imx6q-apalis-ixora-v1.1.dts b/sys/gnu/dts/arm/imx6q-apalis-ixora-v1.1.dts
	index a3fa04a97d81..1614b1ae501d 100644
	--- a/sys/gnu/dts/arm/imx6q-apalis-ixora-v1.1.dts
	+++ b/sys/gnu/dts/arm/imx6q-apalis-ixora-v1.1.dts
	@@ -1,310 +1,274 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2014-2017 Toradex AG
	+ * Copyright 2014-2020 Toradex
	* Copyright 2012 Freescale Semiconductor, Inc.
	* Copyright 2011 Linaro Ltd.
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License
	- * version 2 as published by the Free Software Foundation.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	*/

	/dts-v1/;

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include "imx6q.dtsi"
	#include "imx6qdl-apalis.dtsi"

	/ {
	model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1";
	compatible = "toradex,apalis_imx6q-ixora-v1.1",
	"toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q",
	"fsl,imx6q";

	aliases {
	i2c0 = &i2c1;
	i2c1 = &i2c3;
	i2c2 = &i2c2;
	rtc0 = &rtc_i2c;
	rtc1 = &snvs_rtc;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	gpio-keys {
	compatible = "gpio-keys";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_keys>;

	wakeup {
	label = "Wake-Up";
	gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_WAKEUP>;
	debounce-interval = <10>;
	wakeup-source;
	};
	};

	lcd_display: disp0 {
	compatible = "fsl,imx-parallel-display";
	#address-cells = <1>;
	#size-cells = <0>;
	interface-pix-fmt = "rgb24";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ipu1_lcdif>;
	status = "okay";

	port@0 {
	reg = <0>;

	lcd_display_in: endpoint {
	remote-endpoint = <&ipu1_di1_disp1>;
	};
	};

	port@1 {
	reg = <1>;

	lcd_display_out: endpoint {
	remote-endpoint = <&lcd_panel_in>;
	};
	};
	};

	panel: panel {
	/*
	* edt,et057090dhu: EDT 5.7" LCD TFT
	* edt,et070080dh6: EDT 7.0" LCD TFT
	*/
	compatible = "edt,et057090dhu";
	backlight = <&backlight>;

	port {
	lcd_panel_in: endpoint {
	remote-endpoint = <&lcd_display_out>;
	};
	};
	};

	leds {
	compatible = "gpio-leds";

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_leds_ixora>;

	led4-green {
	label = "LED_4_GREEN";
	gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
	};

	led4-red {
	label = "LED_4_RED";
	gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
	};

	led5-green {
	label = "LED_5_GREEN";
	gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
	};

	led5-red {
	label = "LED_5_RED";
	gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
	};
	};
	};

	&backlight {
	brightness-levels = <0 127 191 223 239 247 251 255>;
	default-brightness-level = <1>;
	status = "okay";
	};

	&can1 {
	status = "okay";
	};

	&can2 {
	status = "okay";
	};

	&hdmi {
	status = "okay";
	};

	/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
	&i2c1 {
	status = "okay";

	/*
	* Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
	* aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
	*/
	touchscreen@4a {
	compatible = "atmel,maxtouch";
	reg = <0x4a>;
	interrupt-parent = <&gpio6>;
	interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
	reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
	status = "disabled";
	};

	/* M41T0M6 real time clock on carrier board */
	rtc_i2c: rtc@68 {
	compatible = "st,m41t0";
	reg = <0x68>;
	};
	};

	/*
	* I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
	* board)
	*/
	&i2c3 {
	status = "okay";
	};

	&ipu1_di1_disp1 {
	remote-endpoint = <&lcd_display_in>;
	};

	&ldb {
	status = "okay";
	};

	&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_reset_moci>;
	/* active-high meaning opposite of regular PERST# active-low polarity */
	reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
	reset-gpio-active-high;
	status = "okay";
	};

	&pwm1 {
	status = "okay";
	};

	&pwm2 {
	status = "okay";
	};

	&pwm3 {
	status = "okay";
	};

	&pwm4 {
	status = "okay";
	};

	&reg_usb_otg_vbus {
	status = "okay";
	};

	&reg_usb_host_vbus {
	status = "okay";
	};

	&sata {
	status = "okay";
	};

	&sound_spdif {
	status = "okay";
	};

	&spdif {
	status = "okay";
	};

	&uart1 {
	status = "okay";
	};

	&uart2 {
	status = "okay";
	};

	&uart4 {
	status = "okay";
	};

	&uart5 {
	status = "okay";
	};

	&usbh1 {
	vbus-supply = <&reg_usb_host_vbus>;
	status = "okay";
	};

	&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	status = "okay";
	};

	/* MMC1 */
	&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>;
	cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	status = "okay";
	};

	&iomuxc {
	/*
	* Mux the Apalis GPIOs
	*/
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
	&pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
	&pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
	&pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
	>;

	pinctrl_leds_ixora: ledsixoragrp {
	fsl,pins = <
	MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
	MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
	MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
	MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6q-apalis-ixora.dts b/sys/gnu/dts/arm/imx6q-apalis-ixora.dts
	index 5ba49d0f4880..fa9f98dd15ac 100644
	--- a/sys/gnu/dts/arm/imx6q-apalis-ixora.dts
	+++ b/sys/gnu/dts/arm/imx6q-apalis-ixora.dts
	@@ -1,311 +1,275 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2014-2017 Toradex AG
	+ * Copyright 2014-2020 Toradex
	* Copyright 2012 Freescale Semiconductor, Inc.
	* Copyright 2011 Linaro Ltd.
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License
	- * version 2 as published by the Free Software Foundation.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	*/

	/dts-v1/;

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include "imx6q.dtsi"
	#include "imx6qdl-apalis.dtsi"

	/ {
	model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board";
	compatible = "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q",
	"fsl,imx6q";

	aliases {
	i2c0 = &i2c1;
	i2c1 = &i2c3;
	i2c2 = &i2c2;
	rtc0 = &rtc_i2c;
	rtc1 = &snvs_rtc;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	gpio-keys {
	compatible = "gpio-keys";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_keys>;

	wakeup {
	label = "Wake-Up";
	gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_WAKEUP>;
	debounce-interval = <10>;
	wakeup-source;
	};
	};

	lcd_display: disp0 {
	compatible = "fsl,imx-parallel-display";
	#address-cells = <1>;
	#size-cells = <0>;
	interface-pix-fmt = "rgb24";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ipu1_lcdif>;
	status = "okay";

	port@0 {
	reg = <0>;

	lcd_display_in: endpoint {
	remote-endpoint = <&ipu1_di1_disp1>;
	};
	};

	port@1 {
	reg = <1>;

	lcd_display_out: endpoint {
	remote-endpoint = <&lcd_panel_in>;
	};
	};
	};

	panel: panel {
	/*
	* edt,et057090dhu: EDT 5.7" LCD TFT
	* edt,et070080dh6: EDT 7.0" LCD TFT
	*/
	compatible = "edt,et057090dhu";
	backlight = <&backlight>;

	port {
	lcd_panel_in: endpoint {
	remote-endpoint = <&lcd_display_out>;
	};
	};
	};

	leds {
	compatible = "gpio-leds";

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_leds_ixora>;

	led4-green {
	label = "LED_4_GREEN";
	gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
	};

	led4-red {
	label = "LED_4_RED";
	gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
	};

	led5-green {
	label = "LED_5_GREEN";
	gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
	};

	led5-red {
	label = "LED_5_RED";
	gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
	};
	};
	};

	&backlight {
	brightness-levels = <0 127 191 223 239 247 251 255>;
	default-brightness-level = <1>;
	status = "okay";
	};

	&can1 {
	status = "okay";
	};

	&can2 {
	status = "okay";
	};

	&hdmi {
	status = "okay";
	};

	/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
	&i2c1 {
	status = "okay";

	/*
	* Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
	* aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
	*/
	touchscreen@4a {
	compatible = "atmel,maxtouch";
	reg = <0x4a>;
	interrupt-parent = <&gpio6>;
	interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
	reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
	status = "disabled";
	};

	eeprom@50 {
	compatible = "atmel,24c02";
	reg = <0x50>;
	};

	/* M41T0M6 real time clock on carrier board */
	rtc_i2c: rtc@68 {
	compatible = "st,m41t0";
	reg = <0x68>;
	};
	};

	/*
	* I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
	* board)
	*/
	&i2c3 {
	status = "okay";
	};

	&ipu1_di1_disp1 {
	remote-endpoint = <&lcd_display_in>;
	};

	&ldb {
	status = "okay";
	};

	&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_reset_moci>;
	/* active-high meaning opposite of regular PERST# active-low polarity */
	reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
	reset-gpio-active-high;
	status = "okay";
	};

	&pwm1 {
	status = "okay";
	};

	&pwm2 {
	status = "okay";
	};

	&pwm3 {
	status = "okay";
	};

	&pwm4 {
	status = "okay";
	};

	&reg_usb_otg_vbus {
	status = "okay";
	};

	&reg_usb_host_vbus {
	status = "okay";
	};

	&sata {
	status = "okay";
	};

	&sound_spdif {
	status = "okay";
	};

	&spdif {
	status = "okay";
	};

	&uart1 {
	status = "okay";
	};

	&uart2 {
	status = "okay";
	};

	&uart4 {
	status = "okay";
	};

	&uart5 {
	status = "okay";
	};

	&usbh1 {
	vbus-supply = <&reg_usb_host_vbus>;
	status = "okay";
	};

	&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	status = "okay";
	};

	/* SD1 */
	&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&iomuxc {
	/* Mux the Apalis GPIOs */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
	&pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
	&pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
	&pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
	>;

	pinctrl_leds_ixora: ledsixoragrp {
	fsl,pins = <
	MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
	MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0
	MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
	MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6q-b450v3.dts b/sys/gnu/dts/arm/imx6q-b450v3.dts
	index 95b8f2d71821..fb0980190aa0 100644
	--- a/sys/gnu/dts/arm/imx6q-b450v3.dts
	+++ b/sys/gnu/dts/arm/imx6q-b450v3.dts
	@@ -1,159 +1,152 @@
	/*
	* Copyright 2015 Timesys Corporation.
	* Copyright 2015 General Electric Company
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License
	* version 2 as published by the Free Software Foundation.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	/dts-v1/;

	#include "imx6q-bx50v3.dtsi"

	/ {
	model = "General Electric B450v3";
	compatible = "ge,imx6q-b450v3", "advantech,imx6q-ba16", "fsl,imx6q";

	chosen {
	stdout-path = &uart3;
	};

	panel-lvds0 {
	compatible = "innolux,g121x1-l03";
	backlight = <&backlight_lvds>;
	power-supply = <&reg_lvds>;

	port {
	panel_in_lvds0: endpoint {
	remote-endpoint = <&lvds0_out>;
	};
	};
	};
	};

	-&clks {
	- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
	- <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
	- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
	- <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
	-};
	-
	&ldb {
	status = "okay";

	lvds0: lvds-channel@0 {
	fsl,data-mapping = "spwg";
	fsl,data-width = <24>;
	status = "okay";

	port@4 {
	reg = <4>;

	lvds0_out: endpoint {
	remote-endpoint = <&panel_in_lvds0>;
	};
	};
	};
	};

	&pca9539 {
	P04 {
	gpio-hog;
	gpios = <4 0>;
	output-low;
	line-name = "PCA9539-P04";
	};

	P07 {
	gpio-hog;
	gpios = <7 0>;
	output-low;
	line-name = "PCA9539-P07";
	};
	};

	&pci_root {
	/* Intel Corporation I210 Gigabit Network Connection */
	switch_nic: ethernet@3,0 {
	compatible = "pci8086,1533";
	reg = <0x00010000 0 0 0 0>;
	};
	};

	&switch_ports {
	port@0 {
	reg = <0>;
	label = "enacq";
	phy-handle = <&switchphy0>;
	};

	port@1 {
	reg = <1>;
	label = "eneport1";
	phy-handle = <&switchphy1>;
	};

	port@2 {
	reg = <2>;
	label = "enix";
	phy-handle = <&switchphy2>;
	};

	port@3 {
	reg = <3>;
	label = "enid";
	phy-handle = <&switchphy3>;
	};

	port@4 {
	reg = <4>;
	label = "cpu";
	ethernet = <&switch_nic>;
	phy-handle = <&switchphy4>;
	};

	port@5 {
	reg = <5>;
	label = "enembc";

	/* connected to Ethernet MAC of AT91RM9200 in MII mode */
	fixed-link {
	speed = <100>;
	full-duplex;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6q-b650v3.dts b/sys/gnu/dts/arm/imx6q-b650v3.dts
	index 611cb7ae7e55..8f762d9c5ae9 100644
	--- a/sys/gnu/dts/arm/imx6q-b650v3.dts
	+++ b/sys/gnu/dts/arm/imx6q-b650v3.dts
	@@ -1,158 +1,151 @@
	/*
	* Copyright 2015 Timesys Corporation.
	* Copyright 2015 General Electric Company
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License
	* version 2 as published by the Free Software Foundation.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	/dts-v1/;

	#include "imx6q-bx50v3.dtsi"

	/ {
	model = "General Electric B650v3";
	compatible = "ge,imx6q-b650v3", "advantech,imx6q-ba16", "fsl,imx6q";

	chosen {
	stdout-path = &uart3;
	};

	panel-lvds0 {
	compatible = "innolux,g121x1-l03";
	backlight = <&backlight_lvds>;
	power-supply = <&reg_lvds>;

	port {
	panel_in_lvds0: endpoint {
	remote-endpoint = <&lvds0_out>;
	};
	};
	};
	};

	-&clks {
	- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
	- <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
	- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
	- <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
	-};
	-
	&ldb {
	status = "okay";

	lvds0: lvds-channel@0 {
	fsl,data-mapping = "spwg";
	fsl,data-width = <24>;
	status = "okay";

	port@4 {
	reg = <4>;

	lvds0_out: endpoint {
	remote-endpoint = <&panel_in_lvds0>;
	};
	};
	};
	};

	&pca9539 {
	P07 {
	gpio-hog;
	gpios = <7 0>;
	output-low;
	line-name = "PCA9539-P07";
	};
	};

	&usbphy1 {
	fsl,tx-cal-45-dn-ohms = <55>;
	fsl,tx-cal-45-dp-ohms = <55>;
	fsl,tx-d-cal = <100>;
	};

	&pci_root {
	/* Intel Corporation I210 Gigabit Network Connection */
	switch_nic: ethernet@3,0 {
	compatible = "pci8086,1533";
	reg = <0x00010000 0 0 0 0>;
	};
	};

	&switch_ports {
	port@0 {
	reg = <0>;
	label = "enacq";
	phy-handle = <&switchphy0>;
	};

	port@1 {
	reg = <1>;
	label = "eneport1";
	phy-handle = <&switchphy1>;
	};

	port@2 {
	reg = <2>;
	label = "enix";
	phy-handle = <&switchphy2>;
	};

	port@3 {
	reg = <3>;
	label = "enid";
	phy-handle = <&switchphy3>;
	};

	port@4 {
	reg = <4>;
	label = "cpu";
	ethernet = <&switch_nic>;
	phy-handle = <&switchphy4>;
	};

	port@5 {
	reg = <5>;
	label = "enembc";

	/* connected to Ethernet MAC of AT91RM9200 in MII mode */
	fixed-link {
	speed = <100>;
	full-duplex;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6q-b850v3.dts b/sys/gnu/dts/arm/imx6q-b850v3.dts
	index e4cb118f88c6..1ea64ecf4291 100644
	--- a/sys/gnu/dts/arm/imx6q-b850v3.dts
	+++ b/sys/gnu/dts/arm/imx6q-b850v3.dts
	@@ -1,301 +1,290 @@
	/*
	* Copyright 2015 Timesys Corporation.
	* Copyright 2015 General Electric Company
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License
	* version 2 as published by the Free Software Foundation.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	/dts-v1/;

	#include "imx6q-bx50v3.dtsi"

	/ {
	model = "General Electric B850v3";
	compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q";

	chosen {
	stdout-path = &uart3;
	};
	};

	-&clks {
	- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
	- <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
	- <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
	- <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
	- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
	- <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
	- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
	- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
	-};
	-
	&ldb {
	fsl,dual-channel;
	status = "okay";

	lvds0: lvds-channel@0 {
	fsl,data-mapping = "spwg";
	fsl,data-width = <24>;
	status = "okay";

	port@4 {
	reg = <4>;

	lvds0_out: endpoint {
	remote-endpoint = <&stdp4028_in>;
	};
	};
	};
	};

	&i2c2 {
	pca9547_ddc: mux@70 {
	compatible = "nxp,pca9547";
	reg = <0x70>;
	#address-cells = <1>;
	#size-cells = <0>;

	mux2_i2c1: i2c@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0>;
	};

	mux2_i2c2: i2c@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x1>;
	};

	mux2_i2c3: i2c@2 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x2>;
	};

	mux2_i2c4: i2c@3 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x3>;
	};

	mux2_i2c5: i2c@4 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x4>;
	};

	mux2_i2c6: i2c@5 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x5>;
	};

	mux2_i2c7: i2c@6 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x6>;
	};

	mux2_i2c8: i2c@7 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x7>;
	};
	};
	};

	&hdmi {
	ddc-i2c-bus = <&mux2_i2c1>;
	};

	&mux1_i2c1 {
	ads7830@4a {
	compatible = "ti,ads7830";
	reg = <0x4a>;
	};
	};

	&mux2_i2c2 {
	clock-frequency = <100000>;

	stdp2690@72 {
	compatible = "megachips,stdp2690-ge-b850v3-fw";
	reg = <0x72>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	stdp2690_in: endpoint {
	remote-endpoint = <&stdp4028_out>;
	};
	};

	port@1 {
	reg = <1>;

	stdp2690_out: endpoint {
	/* Connector for external display */
	};
	};
	};
	};

	stdp4028@73 {
	compatible = "megachips,stdp4028-ge-b850v3-fw";
	reg = <0x73>;
	interrupt-parent = <&gpio2>;
	interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	stdp4028_in: endpoint {
	remote-endpoint = <&lvds0_out>;
	};
	};

	port@1 {
	reg = <1>;

	stdp4028_out: endpoint {
	remote-endpoint = <&stdp2690_in>;
	};
	};
	};
	};
	};

	&pca9539 {
	P10 {
	gpio-hog;
	gpios = <8 0>;
	output-low;
	line-name = "PCA9539-P10";
	};

	P11 {
	gpio-hog;
	gpios = <9 0>;
	output-low;
	line-name = "PCA9539-P11";
	};
	};

	&pci_root {
	/* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */
	bridge@1,0 {
	compatible = "pci10b5,8605";
	reg = <0x00010000 0 0 0 0>;

	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;

	bridge@2,1 {
	compatible = "pci10b5,8605";
	reg = <0x00020800 0 0 0 0>;

	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;

	/* Intel Corporation I210 Gigabit Network Connection */
	ethernet@3,0 {
	compatible = "pci8086,1533";
	reg = <0x00030000 0 0 0 0>;
	};
	};

	bridge@2,2 {
	compatible = "pci10b5,8605";
	reg = <0x00021000 0 0 0 0>;

	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;

	/* Intel Corporation I210 Gigabit Network Connection */
	switch_nic: ethernet@4,0 {
	compatible = "pci8086,1533";
	reg = <0x00040000 0 0 0 0>;
	};
	};
	};
	};

	&switch_ports {
	port@0 {
	reg = <0>;
	label = "eneport1";
	phy-handle = <&switchphy0>;
	};

	port@1 {
	reg = <1>;
	label = "eneport2";
	phy-handle = <&switchphy1>;
	};

	port@2 {
	reg = <2>;
	label = "enix";
	phy-handle = <&switchphy2>;
	};

	port@3 {
	reg = <3>;
	label = "enid";
	phy-handle = <&switchphy3>;
	};

	port@4 {
	reg = <4>;
	label = "cpu";
	ethernet = <&switch_nic>;
	phy-handle = <&switchphy4>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6q-bx50v3.dtsi b/sys/gnu/dts/arm/imx6q-bx50v3.dtsi
	index fa27dcdf06f1..1938b04199c4 100644
	--- a/sys/gnu/dts/arm/imx6q-bx50v3.dtsi
	+++ b/sys/gnu/dts/arm/imx6q-bx50v3.dtsi
	@@ -1,379 +1,394 @@
	/*
	* Copyright 2015 Timesys Corporation.
	* Copyright 2015 General Electric Company
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License
	* version 2 as published by the Free Software Foundation.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include "imx6q-ba16.dtsi"

	/ {
	mclk: clock-mclk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <22000000>;
	};

	gpio-poweroff {
	compatible = "gpio-poweroff";
	gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	reg_wl18xx_vmmc: regulator-wl18xx {
	compatible = "regulator-fixed";
	regulator-name = "vwl1807";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&pca9539 3 GPIO_ACTIVE_HIGH>;
	startup-delay-us = <70000>;
	enable-active-high;
	};

	reg_wlan: regulator-wlan {
	compatible = "regulator-fixed";
	regulator-name = "3P3V_wlan";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	gpio = <&gpio6 14 GPIO_ACTIVE_HIGH>;
	};

	sound {
	compatible = "fsl,imx6q-ba16-sgtl5000",
	"fsl,imx-audio-sgtl5000";
	model = "imx6q-ba16-sgtl5000";
	ssi-controller = <&ssi1>;
	audio-codec = <&sgtl5000>;
	audio-routing =
	"MIC_IN", "Mic Jack",
	"Mic Jack", "Mic Bias",
	"LINE_IN", "Line In Jack",
	"Headphone Jack", "HP_OUT";
	mux-int-port = <1>;
	mux-ext-port = <4>;
	};

	aliases {
	mdio-gpio0 = &mdio0;
	};

	mdio0: mdio-gpio {
	compatible = "virtual,mdio-gpio";
	gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */
	<&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */

	#address-cells = <1>;
	#size-cells = <0>;

	switch@0 {
	compatible = "marvell,mv88e6085"; /* 88e6240*/
	reg = <0>;

	switch_ports: ports {
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	switchphy0: switchphy@0 {
	reg = <0>;
	};

	switchphy1: switchphy@1 {
	reg = <1>;
	};

	switchphy2: switchphy@2 {
	reg = <2>;
	};

	switchphy3: switchphy@3 {
	reg = <3>;
	};

	switchphy4: switchphy@4 {
	reg = <4>;
	};
	};
	};
	};
	};

	&ecspi5 {
	cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi5>;
	status = "okay";

	m25_eeprom: m25p80@0 {
	compatible = "atmel,at25";
	spi-max-frequency = <10000000>;
	size = <0x8000>;
	pagesize = <64>;
	reg = <0>;
	address-width = <16>;
	};
	};

	&i2c1 {
	pinctrl-names = "default", "gpio";
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	sda-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;
	scl-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;

	pca9547: mux@70 {
	compatible = "nxp,pca9547";
	reg = <0x70>;
	#address-cells = <1>;
	#size-cells = <0>;

	mux1_i2c1: i2c@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0>;

	ads7830: ads7830@48 {
	compatible = "ti,ads7830";
	reg = <0x48>;
	};

	mma8453: mma8453@1c {
	compatible = "fsl,mma8453";
	reg = <0x1c>;
	};
	};

	mux1_i2c2: i2c@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x1>;

	eeprom: eeprom@50 {
	compatible = "atmel,24c08";
	reg = <0x50>;
	};

	mpl3115: mpl3115@60 {
	compatible = "fsl,mpl3115";
	reg = <0x60>;
	};
	};

	mux1_i2c3: i2c@2 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x2>;
	};

	mux1_i2c4: i2c@3 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x3>;

	sgtl5000: codec@a {
	compatible = "fsl,sgtl5000";
	reg = <0x0a>;
	clocks = <&mclk>;
	VDDA-supply = <&reg_1p8v>;
	VDDIO-supply = <&reg_3p3v>;
	};
	};

	mux1_i2c5: i2c@4 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x4>;

	pca9539: pca9539@74 {
	compatible = "nxp,pca9539";
	reg = <0x74>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	interrupt-parent = <&gpio2>;
	interrupts = <3 IRQ_TYPE_LEVEL_LOW>;

	P12 {
	gpio-hog;
	gpios = <10 0>;
	output-low;
	line-name = "PCA9539-P12";
	};

	P13 {
	gpio-hog;
	gpios = <11 0>;
	output-low;
	line-name = "PCA9539-P13";
	};

	P14 {
	gpio-hog;
	gpios = <12 0>;
	output-low;
	line-name = "PCA9539-P14";
	};

	P15 {
	gpio-hog;
	gpios = <13 0>;
	output-low;
	line-name = "PCA9539-P15";
	};

	P16 {
	gpio-hog;
	gpios = <14 0>;
	output-low;
	line-name = "PCA9539-P16";
	};

	P17 {
	gpio-hog;
	gpios = <15 0>;
	output-low;
	line-name = "PCA9539-P17";
	};
	};
	};

	mux1_i2c6: i2c@5 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x5>;
	};

	mux1_i2c7: i2c@6 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x6>;
	};

	mux1_i2c8: i2c@7 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x7>;
	};
	};
	};

	&i2c2 {
	pinctrl-names = "default", "gpio";
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
	scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
	};

	&i2c3 {
	pinctrl-names = "default", "gpio";
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
	scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
	};

	&iomuxc {
	pinctrl_i2c1_gpio: i2c1gpiogrp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0
	MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0
	>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0
	MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0
	>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0
	MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
	>;
	};
	};

	&pmu {
	secure-reg-access;
	};

	&usdhc2 {
	status = "disabled";
	};

	&usdhc4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4>;
	bus-width = <4>;
	vmmc-supply = <&reg_wl18xx_vmmc>;
	no-1-8-v;
	non-removable;
	wakeup-source;
	keep-power-in-suspend;
	cap-power-off-card;
	max-frequency = <25000000>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	wlcore: wlcore@2 {
	compatible = "ti,wl1837";
	reg = <2>;
	interrupt-parent = <&gpio2>;
	interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
	tcxo-clock-frequency = <26000000>;
	};
	};

	&pcie {
	/* Synopsys, Inc. Device */
	pci_root: root@0,0 {
	compatible = "pci16c3,abcd";
	reg = <0x00000000 0 0 0 0>;

	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	};
	};
	+
	+&clks {
	+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
	+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
	+ <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
	+ <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>,
	+ <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>,
	+ <&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>;
	+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
	+ <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
	+ <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
	+ <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
	+ <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
	+ <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
	+};
	diff --git a/sys/gnu/dts/arm/imx6q-marsboard.dts b/sys/gnu/dts/arm/imx6q-marsboard.dts
	index 84b30bd6908f..05ee28388229 100644
	--- a/sys/gnu/dts/arm/imx6q-marsboard.dts
	+++ b/sys/gnu/dts/arm/imx6q-marsboard.dts
	@@ -1,403 +1,417 @@
	/*
	* Copyright (C) 2016 Sergio Prado (sergio.prado@e-labworks.com)
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License
	* version 2 as published by the Free Software Foundation.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	/dts-v1/;
	#include "imx6q.dtsi"
	#include <dt-bindings/gpio/gpio.h>

	/ {
	model = "Embest MarS Board i.MX6Dual";
	compatible = "embest,imx6q-marsboard", "fsl,imx6q";

	memory@10000000 {
	device_type = "memory";
	reg = <0x10000000 0x40000000>;
	};

	reg_3p3v: regulator-3p3v {
	compatible = "regulator-fixed";
	regulator-name = "3P3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	reg_usb_otg_vbus: regulator-usb-otg-vbus {
	compatible = "regulator-fixed";
	regulator-name = "usb_otg_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_led>;

	user1 {
	label = "imx6:green:user1";
	gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
	default-state = "off";
	linux,default-trigger = "heartbeat";
	};

	user2 {
	label = "imx6:green:user2";
	gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
	default-state = "off";
	};
	};
	};

	&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
	};

	&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
	status = "okay";

	m25p80@0 {
	compatible = "microchip,sst25vf016b";
	spi-max-frequency = <20000000>;
	reg = <0>;
	};
	};

	&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii-id";
	- phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
	+ phy-handle = <&rgmii_phy>;
	status = "okay";
	+
	+ mdio {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ /* Atheros AR8035 PHY */
	+ rgmii_phy: ethernet-phy@4 {
	+ reg = <4>;
	+ interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
	+ reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
	+ reset-assert-us = <10000>;
	+ reset-deassert-us = <1000>;
	+ };
	+ };
	};

	&hdmi {
	ddc-i2c-bus = <&i2c2>;
	status = "okay";
	};

	&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
	};

	&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
	};

	&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
	};

	&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "okay";
	};

	&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	status = "okay";
	};

	&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "okay";
	};

	&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
	status = "okay";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
	};

	&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
	};

	&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
	};

	&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	status = "okay";
	};

	&usbh1 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
	};

	&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	dr_mode = "otg";
	disable-over-current;
	status = "okay";
	};

	&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	vmmc-supply = <&reg_3p3v>;
	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
	status = "okay";
	};

	&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	vmmc-supply = <&reg_3p3v>;
	non-removable;
	status = "okay";
	};

	&iomuxc {

	pinctrl_audmux: audmuxgrp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
	MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
	MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
	MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
	MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */
	>;
	};

	pinctrl_ecspi1: ecspi1grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
	MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
	MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
	MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000b1 /* CS0 */
	>;
	};

	pinctrl_enet: enetgrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
	/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
	/* AR8035 pin strapping: IO voltage: pull up */
	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
	/* AR8035 pin strapping: PHYADDR#0: pull down */
	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
	/* AR8035 pin strapping: PHYADDR#1: pull down */
	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
	/* AR8035 pin strapping: MODE#1: pull up */
	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
	/* AR8035 pin strapping: MODE#3: pull up */
	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
	/* AR8035 pin strapping: MODE#0: pull down */
	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
	/* GPIO16 -> AR8035 25MHz */
	MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
	/* RGMII_nRST */
	MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0
	/* AR8035 interrupt */
	MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
	MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
	MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
	>;
	};

	pinctrl_led: ledgrp {
	fsl,pins = <
	MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* LED1 */
	MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* LED2 */
	>;
	};

	pinctrl_pwm1: pwm1grp {
	fsl,pins = <
	MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm2: pwm2grp {
	fsl,pins = <
	MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm3: pwm3grp {
	fsl,pins = <
	MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm4: pwm4grp {
	fsl,pins = <
	MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
	MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
	MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart3: uart3grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
	MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart4: uart4grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
	MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart5: uart5grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
	MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_usbotg: usbotggrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
	MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
	MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* USB OTG POWER ENABLE */
	>;
	};

	pinctrl_usdhc2: usdhc2grp {
	fsl,pins = <
	MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
	MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
	MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
	MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
	MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
	MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
	MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
	MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* WP */
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17009
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10009
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17009
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17009
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17009
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17009
	MX6QDL_PAD_SD3_RST__SD3_RESET 0x17009
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6q-novena.dts b/sys/gnu/dts/arm/imx6q-novena.dts
	index 61347a545d6c..69f170ff31c5 100644
	--- a/sys/gnu/dts/arm/imx6q-novena.dts
	+++ b/sys/gnu/dts/arm/imx6q-novena.dts
	@@ -1,792 +1,792 @@
	/*
	* Copyright 2015 Sutajio Ko-Usagi PTE LTD
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of
	* the License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* You should have received a copy of the GNU General Public
	* License along with this file; if not, write to the Free
	* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
	* MA 02110-1301 USA
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*
	*/

	/dts-v1/;
	#include "imx6q.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>

	/ {
	model = "Kosagi Novena Dual/Quad";
	compatible = "kosagi,imx6q-novena", "fsl,imx6q";

	/* Will be filled by the bootloader */
	memory@10000000 {
	device_type = "memory";
	reg = <0x10000000 0>;
	};

	chosen {
	stdout-path = &uart2;
	};

	backlight: backlight {
	compatible = "pwm-backlight";
	pwms = <&pwm1 0 10000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_backlight_novena>;
	power-supply = <&reg_lvds_lcd>;
	brightness-levels = <0 3 6 12 16 24 32 48 64 96 128 192 255>;
	default-brightness-level = <12>;
	};

	gpio-keys {
	compatible = "gpio-keys";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_keys_novena>;

	user-button {
	label = "User Button";
	gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_POWER>;
	};

	lid {
	label = "Lid";
	gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
	linux,input-type = <5>; /* EV_SW */
	linux,code = <0>; /* SW_LID */
	};
	};

	leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_leds_novena>;

	heartbeat {
	label = "novena:white:panel";
	gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "default-on";
	};
	};

	panel: panel {
	- compatible = "innolux,n133hse-ea1", "simple-panel";
	+ compatible = "innolux,n133hse-ea1";
	backlight = <&backlight>;
	};

	reg_2p5v: regulator-2p5v {
	compatible = "regulator-fixed";
	regulator-name = "2P5V";
	regulator-min-microvolt = <2500000>;
	regulator-max-microvolt = <2500000>;
	regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
	compatible = "regulator-fixed";
	regulator-name = "3P3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_audio_codec: regulator-audio-codec {
	compatible = "regulator-fixed";
	regulator-name = "es8328-power";
	regulator-boot-on;
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	startup-delay-us = <400000>;
	gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_display: regulator-display {
	compatible = "regulator-fixed";
	regulator-name = "lcd-display-power";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	startup-delay-us = <200000>;
	gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_lvds_lcd: regulator-lvds-lcd {
	compatible = "regulator-fixed";
	regulator-name = "lcd-lvds-power";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_pcie: regulator-pcie {
	compatible = "regulator-fixed";
	regulator-name = "pcie-bus-power";
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1500000>;
	gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_sata: regulator-sata {
	compatible = "regulator-fixed";
	regulator-name = "sata-power";
	regulator-boot-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	startup-delay-us = <10000>;
	gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_usb_otg_vbus: regulator-usb-otg-vbus {
	compatible = "regulator-fixed";
	regulator-name = "usb_otg_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	enable-active-high;
	};

	sound {
	compatible = "fsl,imx-audio-es8328";
	model = "imx-audio-es8328";
	ssi-controller = <&ssi1>;
	audio-codec = <&codec>;
	audio-amp-supply = <&reg_audio_codec>;
	jack-gpio = <&gpio5 15 GPIO_ACTIVE_HIGH>;
	audio-routing =
	"Speaker", "LOUT2",
	"Speaker", "ROUT2",
	"Speaker", "audio-amp",
	"Headphone", "ROUT1",
	"Headphone", "LOUT1",
	"LINPUT1", "Mic Jack",
	"RINPUT1", "Mic Jack",
	"Mic Jack", "Mic Bias";
	mux-int-port = <0x1>;
	mux-ext-port = <0x3>;
	};
	};

	&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux_novena>;
	status = "okay";
	};

	&ecspi3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3_novena>;
	status = "okay";
	};

	&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet_novena>;
	phy-mode = "rgmii";
	phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
	rxc-skew-ps = <3000>;
	rxdv-skew-ps = <0>;
	txc-skew-ps = <3000>;
	txen-skew-ps = <0>;
	rxd0-skew-ps = <0>;
	rxd1-skew-ps = <0>;
	rxd2-skew-ps = <0>;
	rxd3-skew-ps = <0>;
	txd0-skew-ps = <3000>;
	txd1-skew-ps = <3000>;
	txd2-skew-ps = <3000>;
	txd3-skew-ps = <3000>;
	status = "okay";
	};

	&hdmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hdmi_novena>;
	ddc-i2c-bus = <&i2c2>;
	status = "okay";
	};

	&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1_novena>;
	status = "okay";

	accel: mma8452@1c {
	compatible = "fsl,mma8452";
	reg = <0x1c>;
	};

	rtc: pcf8523@68 {
	compatible = "nxp,pcf8523";
	reg = <0x68>;
	};

	sbs_battery: bq20z75@b {
	compatible = "sbs,sbs-battery";
	reg = <0x0b>;
	sbs,i2c-retry-count = <50>;
	};

	touch: stmpe811@44 {
	compatible = "st,stmpe811";
	reg = <0x44>;
	irq-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>;
	id = <0>;
	blocks = <0x5>;
	irq-trigger = <0x1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_stmpe_novena>;
	vio-supply = <&reg_3p3v>;
	vcc-supply = <&reg_3p3v>;

	stmpe_touchscreen {
	compatible = "st,stmpe-ts";
	st,sample-time = <4>;
	st,mod-12b = <1>;
	st,ref-sel = <0>;
	st,adc-freq = <1>;
	st,ave-ctrl = <1>;
	st,touch-det-delay = <2>;
	st,settling = <2>;
	st,fraction-z = <7>;
	st,i-drive = <1>;
	};
	};
	};

	&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2_novena>;
	status = "okay";

	pmic: pfuze100@8 {
	compatible = "fsl,pfuze100";
	reg = <0x08>;

	regulators {
	reg_sw1a: sw1a {
	regulator-min-microvolt = <300000>;
	regulator-max-microvolt = <1875000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	reg_sw1c: sw1c {
	regulator-min-microvolt = <300000>;
	regulator-max-microvolt = <1875000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_sw2: sw2 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_sw3a: sw3a {
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <1975000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_sw3b: sw3b {
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <1975000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_sw4: sw4 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3300000>;
	};

	reg_swbst: swbst {
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5150000>;
	regulator-boot-on;
	};

	reg_snvs: vsnvs {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <3000000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_vref: vrefddr {
	regulator-boot-on;
	regulator-always-on;
	};

	reg_vgen1: vgen1 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	};

	reg_vgen2: vgen2 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	};

	reg_vgen3: vgen3 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	};

	reg_vgen4: vgen4 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_vgen5: vgen5 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_vgen6: vgen6 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};
	};
	};
	};

	&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3_novena>;
	status = "okay";

	codec: es8328@11 {
	compatible = "everest,es8328";
	reg = <0x11>;
	DVDD-supply = <&reg_audio_codec>;
	AVDD-supply = <&reg_audio_codec>;
	PVDD-supply = <&reg_audio_codec>;
	HPVDD-supply = <&reg_audio_codec>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sound_novena>;
	clocks = <&clks IMX6QDL_CLK_CKO1>;
	assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
	<&clks IMX6QDL_CLK_CKO1_SEL>,
	<&clks IMX6QDL_CLK_PLL4_AUDIO>,
	<&clks IMX6QDL_CLK_CKO1>;
	assigned-clock-parents = <&clks IMX6QDL_CLK_CKO1>,
	<&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>,
	<&clks IMX6QDL_CLK_OSC>,
	<&clks IMX6QDL_CLK_CKO1_PODF>;
	assigned-clock-rates = <0 0 722534400 22579200>;
	};
	};

	&kpp {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_kpp_novena>;
	linux,keymap = <
	MATRIX_KEY(1, 1, KEY_CONFIG)
	>;
	status = "okay";
	};

	&ldb {
	fsl,dual-channel;
	status = "okay";

	lvds-channel@0 {
	fsl,data-mapping = "jeida";
	fsl,data-width = <24>;
	fsl,panel = <&panel>;
	status = "okay";
	};
	};

	&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie_novena>;
	reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>;
	vpcie-supply = <&reg_pcie>;
	status = "okay";
	};

	&pwm1 {
	status = "okay";
	};

	&sata {
	target-supply = <&reg_sata>;
	fsl,transmit-level-mV = <1025>;
	fsl,transmit-boost-mdB = <0>;
	fsl,transmit-atten-16ths = <8>;
	status = "okay";
	};

	&ssi1 {
	status = "okay";
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2_novena>;
	status = "okay";
	};

	&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3_novena>;
	status = "okay";
	};

	&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4_novena>;
	status = "okay";
	};

	&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	dr_mode = "otg";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg_novena>;
	disable-over-current;
	status = "okay";
	};

	&usbh1 {
	vbus-supply = <&reg_swbst>;
	status = "okay";
	};

	&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2_novena>;
	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	status = "okay";
	};

	&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3_novena>;
	bus-width = <4>;
	non-removable;
	status = "okay";
	};

	&iomuxc {
	pinctrl_audmux_novena: audmuxgrp-novena {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
	MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
	MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
	MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
	>;
	};

	pinctrl_backlight_novena: backlightgrp-novena {
	fsl,pins = <
	MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0
	MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b1
	MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1
	>;
	};

	pinctrl_ecspi3_novena: ecspi3grp-novena {
	fsl,pins = <
	MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
	MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
	MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
	>;
	};

	pinctrl_enet_novena: enetgrp-novena {
	fsl,pins = <
	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020
	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b028
	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b028
	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b028
	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b028
	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b028
	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
	MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
	/* Ethernet reset */
	MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b1
	>;
	};

	pinctrl_fpga_gpio: fpgagpiogrp-novena {
	fsl,pins = <
	/* FPGA power */
	MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1
	/* Reset */
	MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1
	/* FPGA GPIOs */
	MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1
	MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1
	MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1
	MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1
	MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1
	MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1
	MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1
	MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1
	MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1
	MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1
	MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1
	MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1
	MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1
	MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1
	MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1
	MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1
	MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1
	MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1
	MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1
	MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1
	MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1
	MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1
	MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1
	MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1
	MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1
	MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1
	>;
	};

	pinctrl_fpga_eim: fpgaeimgrp-novena {
	fsl,pins = <
	/* FPGA power */
	MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1
	/* Reset */
	MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1
	/* FPGA GPIOs */
	MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0f1
	MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0f1
	MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0f1
	MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0f1
	MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0f1
	MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0f1
	MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0f1
	MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0f1
	MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0f1
	MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0f1
	MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0f1
	MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0f1
	MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0f1
	MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0f1
	MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0f1
	MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0f1
	MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0f1
	MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0f1
	MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0f1
	MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0f1
	MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0f1
	MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0f1
	MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0f1
	MX6QDL_PAD_EIM_RW__EIM_RW 0xb0f1
	MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb0f1
	MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0f1
	>;
	};

	pinctrl_gpio_keys_novena: gpiokeysgrp-novena {
	fsl,pins = <
	/* User button */
	MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
	/* PCIe Wakeup */
	MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1f0e0
	/* Lid switch */
	MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0
	>;
	};

	pinctrl_hdmi_novena: hdmigrp-novena {
	fsl,pins = <
	MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
	MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1
	>;
	};

	pinctrl_i2c1_novena: i2c1grp-novena {
	fsl,pins = <
	MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
	MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c2_novena: i2c2grp-novena {
	fsl,pins = <
	MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
	MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c3_novena: i2c3grp-novena {
	fsl,pins = <
	MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
	MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
	>;
	};

	pinctrl_kpp_novena: kppgrp-novena {
	fsl,pins = <
	/* Front panel button */
	MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x1b0b1
	/* Fake column driver, not connected */
	MX6QDL_PAD_KEY_COL1__KEY_COL1 0x1b0b1
	>;
	};

	pinctrl_leds_novena: ledsgrp-novena {
	fsl,pins = <
	MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b1
	>;
	};

	pinctrl_pcie_novena: pciegrp-novena {
	fsl,pins = <
	/* Reset */
	MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1
	/* Power On */
	MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1
	/* Wifi kill */
	MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1
	>;
	};

	pinctrl_sata_novena: satagrp-novena {
	fsl,pins = <
	MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b1
	>;
	};

	pinctrl_senoko_novena: senokogrp-novena {
	fsl,pins = <
	/* Senoko IRQ line */
	MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x13048
	/* Senoko reset line */
	MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1
	>;
	};

	pinctrl_sound_novena: soundgrp-novena {
	fsl,pins = <
	/* Audio power regulator */
	MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1
	/* Headphone plug */
	MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1
	MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
	>;
	};

	pinctrl_stmpe_novena: stmpegrp-novena {
	fsl,pins = <
	/* Touchscreen interrupt */
	MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1
	>;
	};

	pinctrl_uart2_novena: uart2grp-novena {
	fsl,pins = <
	MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
	MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart3_novena: uart3grp-novena {
	fsl,pins = <
	MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
	MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart4_novena: uart4grp-novena {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
	MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_usbotg_novena: usbotggrp-novena {
	fsl,pins = <
	MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
	>;
	};

	pinctrl_usdhc2_novena: usdhc2grp-novena {
	fsl,pins = <
	MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
	MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
	MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
	MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
	MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
	MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
	/* Write protect */
	MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
	/* Card detect */
	MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1
	>;
	};

	pinctrl_usdhc3_novena: usdhc3grp-novena {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6q-pico-dwarf.dts b/sys/gnu/dts/arm/imx6q-pico-dwarf.dts
	new file mode 100644
	index 000000000000..618d2743e1e9
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx6q-pico-dwarf.dts
	@@ -0,0 +1,17 @@
	+// SPDX-License-Identifier: GPL-2.0 OR MIT
	+//
	+// Copyright 2018 Technexion Ltd.
	+//
	+// Author: Wig Cheng <wig.cheng@technexion.com>
	+// Richard Hu <richard.hu@technexion.com>
	+// Tapani Utriainen <tapani@technexion.com>
	+
	+/dts-v1/;
	+
	+#include "imx6q.dtsi"
	+#include "imx6qdl-pico-pi.dtsi"
	+
	+/ {
	+ model = "TechNexion PICO-IMX6 Quad Board and Dwarf baseboard";
	+ compatible = "technexion,imx6q-pico", "fsl,imx6q";
	+};
	diff --git a/sys/gnu/dts/arm/imx6q-pico-hobbit.dts b/sys/gnu/dts/arm/imx6q-pico-hobbit.dts
	new file mode 100644
	index 000000000000..7a666507b456
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx6q-pico-hobbit.dts
	@@ -0,0 +1,17 @@
	+// SPDX-License-Identifier: GPL-2.0 OR MIT
	+//
	+// Copyright 2018 Technexion Ltd.
	+//
	+// Author: Wig Cheng <wig.cheng@technexion.com>
	+// Richard Hu <richard.hu@technexion.com>
	+// Tapani Utriainen <tapani@technexion.com>
	+
	+/dts-v1/;
	+
	+#include "imx6q.dtsi"
	+#include "imx6qdl-pico-hobbit.dtsi"
	+
	+/ {
	+ model = "TechNexion PICO-IMX6 Quad Board and Hobbit baseboard";
	+ compatible = "technexion,imx6q-pico", "fsl,imx6q";
	+};
	diff --git a/sys/gnu/dts/arm/imx6q-pico-nymph.dts b/sys/gnu/dts/arm/imx6q-pico-nymph.dts
	new file mode 100644
	index 000000000000..fe5a7becc9e5
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx6q-pico-nymph.dts
	@@ -0,0 +1,17 @@
	+// SPDX-License-Identifier: GPL-2.0 OR MIT
	+//
	+// Copyright 2018 Technexion Ltd.
	+//
	+// Author: Wig Cheng <wig.cheng@technexion.com>
	+// Richard Hu <richard.hu@technexion.com>
	+// Tapani Utriainen <tapani@technexion.com>
	+
	+/dts-v1/;
	+
	+#include "imx6q.dtsi"
	+#include "imx6qdl-pico-pi.dtsi"
	+
	+/ {
	+ model = "TechNexion PICO-IMX6 Quad Board and Nymph baseboard";
	+ compatible = "technexion,imx6q-pico", "fsl,imx6q";
	+};
	diff --git a/sys/gnu/dts/arm/imx6q-pico-pi.dts b/sys/gnu/dts/arm/imx6q-pico-pi.dts
	new file mode 100644
	index 000000000000..9413f0a68f54
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx6q-pico-pi.dts
	@@ -0,0 +1,17 @@
	+// SPDX-License-Identifier: GPL-2.0 OR MIT
	+//
	+// Copyright 2018 Technexion Ltd.
	+//
	+// Author: Wig Cheng <wig.cheng@technexion.com>
	+// Richard Hu <richard.hu@technexion.com>
	+// Tapani Utriainen <tapani@technexion.com>
	+
	+/dts-v1/;
	+
	+#include "imx6q.dtsi"
	+#include "imx6qdl-pico-pi.dtsi"
	+
	+/ {
	+ model = "TechNexion PICO-IMX6 Quad Board and PI baseboard";
	+ compatible = "technexion,imx6q-pico", "fsl,imx6q";
	+};
	diff --git a/sys/gnu/dts/arm/imx6q.dtsi b/sys/gnu/dts/arm/imx6q.dtsi
	index 9d3be1cc6b64..78a4d64929f3 100644
	--- a/sys/gnu/dts/arm/imx6q.dtsi
	+++ b/sys/gnu/dts/arm/imx6q.dtsi
	@@ -1,546 +1,548 @@
	// SPDX-License-Identifier: GPL-2.0
	//
	// Copyright 2013 Freescale Semiconductor, Inc.

	#include <dt-bindings/interrupt-controller/irq.h>
	#include "imx6q-pinfunc.h"
	#include "imx6qdl.dtsi"

	/ {
	aliases {
	ipu1 = &ipu2;
	spi4 = &ecspi5;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <0>;
	next-level-cache = <&L2>;
	operating-points = <
	/* kHz uV */
	1200000 1275000
	996000 1250000
	852000 1250000
	792000 1175000
	396000 975000
	>;
	fsl,soc-operating-points = <
	/* ARM kHz SOC-PU uV */
	1200000 1275000
	996000 1250000
	852000 1250000
	792000 1175000
	396000 1175000
	>;
	clock-latency = <61036>; /* two CLK32 periods */
	#cooling-cells = <2>;
	clocks = <&clks IMX6QDL_CLK_ARM>,
	<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
	<&clks IMX6QDL_CLK_STEP>,
	<&clks IMX6QDL_CLK_PLL1_SW>,
	<&clks IMX6QDL_CLK_PLL1_SYS>;
	clock-names = "arm", "pll2_pfd2_396m", "step",
	"pll1_sw", "pll1_sys";
	arm-supply = <&reg_arm>;
	pu-supply = <&reg_pu>;
	soc-supply = <&reg_soc>;
	+ nvmem-cells = <&cpu_speed_grade>;
	+ nvmem-cell-names = "speed_grade";
	};

	cpu1: cpu@1 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <1>;
	next-level-cache = <&L2>;
	operating-points = <
	/* kHz uV */
	1200000 1275000
	996000 1250000
	852000 1250000
	792000 1175000
	396000 975000
	>;
	fsl,soc-operating-points = <
	/* ARM kHz SOC-PU uV */
	1200000 1275000
	996000 1250000
	852000 1250000
	792000 1175000
	396000 1175000
	>;
	clock-latency = <61036>; /* two CLK32 periods */
	#cooling-cells = <2>;
	clocks = <&clks IMX6QDL_CLK_ARM>,
	<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
	<&clks IMX6QDL_CLK_STEP>,
	<&clks IMX6QDL_CLK_PLL1_SW>,
	<&clks IMX6QDL_CLK_PLL1_SYS>;
	clock-names = "arm", "pll2_pfd2_396m", "step",
	"pll1_sw", "pll1_sys";
	arm-supply = <&reg_arm>;
	pu-supply = <&reg_pu>;
	soc-supply = <&reg_soc>;
	};

	cpu2: cpu@2 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <2>;
	next-level-cache = <&L2>;
	operating-points = <
	/* kHz uV */
	1200000 1275000
	996000 1250000
	852000 1250000
	792000 1175000
	396000 975000
	>;
	fsl,soc-operating-points = <
	/* ARM kHz SOC-PU uV */
	1200000 1275000
	996000 1250000
	852000 1250000
	792000 1175000
	396000 1175000
	>;
	clock-latency = <61036>; /* two CLK32 periods */
	#cooling-cells = <2>;
	clocks = <&clks IMX6QDL_CLK_ARM>,
	<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
	<&clks IMX6QDL_CLK_STEP>,
	<&clks IMX6QDL_CLK_PLL1_SW>,
	<&clks IMX6QDL_CLK_PLL1_SYS>;
	clock-names = "arm", "pll2_pfd2_396m", "step",
	"pll1_sw", "pll1_sys";
	arm-supply = <&reg_arm>;
	pu-supply = <&reg_pu>;
	soc-supply = <&reg_soc>;
	};

	cpu3: cpu@3 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <3>;
	next-level-cache = <&L2>;
	operating-points = <
	/* kHz uV */
	1200000 1275000
	996000 1250000
	852000 1250000
	792000 1175000
	396000 975000
	>;
	fsl,soc-operating-points = <
	/* ARM kHz SOC-PU uV */
	1200000 1275000
	996000 1250000
	852000 1250000
	792000 1175000
	396000 1175000
	>;
	clock-latency = <61036>; /* two CLK32 periods */
	#cooling-cells = <2>;
	clocks = <&clks IMX6QDL_CLK_ARM>,
	<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
	<&clks IMX6QDL_CLK_STEP>,
	<&clks IMX6QDL_CLK_PLL1_SW>,
	<&clks IMX6QDL_CLK_PLL1_SYS>;
	clock-names = "arm", "pll2_pfd2_396m", "step",
	"pll1_sw", "pll1_sys";
	arm-supply = <&reg_arm>;
	pu-supply = <&reg_pu>;
	soc-supply = <&reg_soc>;
	};
	};

	soc {
	ocram: sram@900000 {
	compatible = "mmio-sram";
	reg = <0x00900000 0x40000>;
	clocks = <&clks IMX6QDL_CLK_OCRAM>;
	};

	- aips-bus@2000000 { /* AIPS1 */
	+ bus@2000000 { /* AIPS1 */
	spba-bus@2000000 {
	ecspi5: spi@2018000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
	reg = <0x02018000 0x4000>;
	interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6Q_CLK_ECSPI5>,
	<&clks IMX6Q_CLK_ECSPI5>;
	clock-names = "ipg", "per";
	dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};
	};

	- iomuxc: iomuxc@20e0000 {
	+ iomuxc: pinctrl@20e0000 {
	compatible = "fsl,imx6q-iomuxc";
	};
	};

	sata: sata@2200000 {
	compatible = "fsl,imx6q-ahci";
	reg = <0x02200000 0x4000>;
	interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_SATA>,
	<&clks IMX6QDL_CLK_SATA_REF_100M>,
	<&clks IMX6QDL_CLK_AHB>;
	clock-names = "sata", "sata_ref", "ahb";
	status = "disabled";
	};

	gpu_vg: gpu@2204000 {
	compatible = "vivante,gc";
	reg = <0x02204000 0x4000>;
	interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
	<&clks IMX6QDL_CLK_GPU2D_CORE>;
	clock-names = "bus", "core";
	power-domains = <&pd_pu>;
	#cooling-cells = <2>;
	};

	ipu2: ipu@2800000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6q-ipu";
	reg = <0x02800000 0x400000>;
	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
	<0 7 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_IPU2>,
	<&clks IMX6QDL_CLK_IPU2_DI0>,
	<&clks IMX6QDL_CLK_IPU2_DI1>;
	clock-names = "bus", "di0", "di1";
	resets = <&src 4>;

	ipu2_csi0: port@0 {
	reg = <0>;

	ipu2_csi0_from_mipi_vc2: endpoint {
	remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
	};
	};

	ipu2_csi1: port@1 {
	reg = <1>;

	ipu2_csi1_from_ipu2_csi1_mux: endpoint {
	remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
	};
	};

	ipu2_di0: port@2 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <2>;

	ipu2_di0_disp0: endpoint@0 {
	reg = <0>;
	};

	ipu2_di0_hdmi: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&hdmi_mux_2>;
	};

	ipu2_di0_mipi: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&mipi_mux_2>;
	};

	ipu2_di0_lvds0: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&lvds0_mux_2>;
	};

	ipu2_di0_lvds1: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&lvds1_mux_2>;
	};
	};

	ipu2_di1: port@3 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <3>;

	ipu2_di1_hdmi: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&hdmi_mux_3>;
	};

	ipu2_di1_mipi: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&mipi_mux_3>;
	};

	ipu2_di1_lvds0: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&lvds0_mux_3>;
	};

	ipu2_di1_lvds1: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&lvds1_mux_3>;
	};
	};
	};
	};

	capture-subsystem {
	compatible = "fsl,imx-capture-subsystem";
	ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
	};

	display-subsystem {
	compatible = "fsl,imx-display-subsystem";
	ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
	};
	};

	&gpio1 {
	gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
	<&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
	<&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
	<&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
	<&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
	<&iomuxc 22 116 10>;
	};

	&gpio2 {
	gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
	<&iomuxc 31 44 1>;
	};

	&gpio3 {
	gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
	};

	&gpio4 {
	gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
	};

	&gpio5 {
	gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
	<&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
	};

	&gpio6 {
	gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
	<&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
	<&iomuxc 31 86 1>;
	};

	&gpio7 {
	gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
	};

	&gpr {
	ipu1_csi0_mux {
	compatible = "video-mux";
	mux-controls = <&mux 0>;
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	ipu1_csi0_mux_from_mipi_vc0: endpoint {
	remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
	};
	};

	port@1 {
	reg = <1>;

	ipu1_csi0_mux_from_parallel_sensor: endpoint {
	};
	};

	port@2 {
	reg = <2>;

	ipu1_csi0_mux_to_ipu1_csi0: endpoint {
	remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
	};
	};
	};

	ipu2_csi1_mux {
	compatible = "video-mux";
	mux-controls = <&mux 1>;
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	ipu2_csi1_mux_from_mipi_vc3: endpoint {
	remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
	};
	};

	port@1 {
	reg = <1>;

	ipu2_csi1_mux_from_parallel_sensor: endpoint {
	};
	};

	port@2 {
	reg = <2>;

	ipu2_csi1_mux_to_ipu2_csi1: endpoint {
	remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
	};
	};
	};
	};

	&hdmi {
	compatible = "fsl,imx6q-hdmi";

	port@2 {
	reg = <2>;

	hdmi_mux_2: endpoint {
	remote-endpoint = <&ipu2_di0_hdmi>;
	};
	};

	port@3 {
	reg = <3>;

	hdmi_mux_3: endpoint {
	remote-endpoint = <&ipu2_di1_hdmi>;
	};
	};
	};

	&ipu1_csi1 {
	ipu1_csi1_from_mipi_vc1: endpoint {
	remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
	};
	};

	&ldb {
	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
	<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
	<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
	<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
	clock-names = "di0_pll", "di1_pll",
	"di0_sel", "di1_sel", "di2_sel", "di3_sel",
	"di0", "di1";

	lvds-channel@0 {
	port@2 {
	reg = <2>;

	lvds0_mux_2: endpoint {
	remote-endpoint = <&ipu2_di0_lvds0>;
	};
	};

	port@3 {
	reg = <3>;

	lvds0_mux_3: endpoint {
	remote-endpoint = <&ipu2_di1_lvds0>;
	};
	};
	};

	lvds-channel@1 {
	port@2 {
	reg = <2>;

	lvds1_mux_2: endpoint {
	remote-endpoint = <&ipu2_di0_lvds1>;
	};
	};

	port@3 {
	reg = <3>;

	lvds1_mux_3: endpoint {
	remote-endpoint = <&ipu2_di1_lvds1>;
	};
	};
	};
	};

	&mipi_csi {
	port@1 {
	reg = <1>;

	mipi_vc0_to_ipu1_csi0_mux: endpoint {
	remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
	};
	};

	port@2 {
	reg = <2>;

	mipi_vc1_to_ipu1_csi1: endpoint {
	remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
	};
	};

	port@3 {
	reg = <3>;

	mipi_vc2_to_ipu2_csi0: endpoint {
	remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
	};
	};

	port@4 {
	reg = <4>;

	mipi_vc3_to_ipu2_csi1_mux: endpoint {
	remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
	};
	};
	};

	&mipi_dsi {
	ports {
	port@2 {
	reg = <2>;

	mipi_mux_2: endpoint {
	remote-endpoint = <&ipu2_di0_mipi>;
	};
	};

	port@3 {
	reg = <3>;

	mipi_mux_3: endpoint {
	remote-endpoint = <&ipu2_di1_mipi>;
	};
	};
	};
	};

	&mux {
	mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
	<0x04 0x00100000>, /* MIPI_IPU2_MUX */
	<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
	<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
	<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
	<0x28 0x00000003>, /* DCIC1_MUX_CTL */
	<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
	};

	&vpu {
	compatible = "fsl,imx6q-vpu", "cnm,coda960";
	};
	diff --git a/sys/gnu/dts/arm/imx6qdl-apalis.dtsi b/sys/gnu/dts/arm/imx6qdl-apalis.dtsi
	index 1b5bc6b5e806..e34be8fabd93 100644
	--- a/sys/gnu/dts/arm/imx6qdl-apalis.dtsi
	+++ b/sys/gnu/dts/arm/imx6qdl-apalis.dtsi
	@@ -1,988 +1,952 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2014-2017 Toradex AG
	+ * Copyright 2014-2020 Toradex
	* Copyright 2012 Freescale Semiconductor, Inc.
	* Copyright 2011 Linaro Ltd.
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License
	- * version 2 as published by the Free Software Foundation.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include <dt-bindings/gpio/gpio.h>

	/ {
	model = "Toradex Apalis iMX6Q/D Module";
	compatible = "toradex,apalis_imx6q", "fsl,imx6q";

	/* Will be filled by the bootloader */
	memory@10000000 {
	device_type = "memory";
	reg = <0x10000000 0>;
	};

	backlight: backlight {
	compatible = "pwm-backlight";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_bl_on>;
	pwms = <&pwm4 0 5000000>;
	enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
	status = "disabled";
	};

	reg_module_3v3: regulator-module-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_module_3v3_audio: regulator-module-3v3-audio {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3_AUDIO";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_usb_otg_vbus: regulator-usb-otg-vbus {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
	regulator-name = "usb_otg_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	status = "disabled";
	};

	/* on module USB hub */
	reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
	regulator-name = "usb_host_vbus_hub";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
	startup-delay-us = <2000>;
	enable-active-high;
	status = "okay";
	};

	reg_usb_host_vbus: regulator-usb-host-vbus {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
	regulator-name = "usb_host_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&reg_usb_host_vbus_hub>;
	status = "disabled";
	};

	sound {
	compatible = "fsl,imx-audio-sgtl5000";
	model = "imx6q-apalis-sgtl5000";
	ssi-controller = <&ssi1>;
	audio-codec = <&codec>;
	audio-routing =
	"LINE_IN", "Line In Jack",
	"MIC_IN", "Mic Jack",
	"Mic Jack", "Mic Bias",
	"Headphone Jack", "HP_OUT";
	mux-int-port = <1>;
	mux-ext-port = <4>;
	};

	sound_spdif: sound-spdif {
	compatible = "fsl,imx-audio-spdif";
	model = "imx-spdif";
	spdif-controller = <&spdif>;
	spdif-in;
	spdif-out;
	status = "disabled";
	};
	};

	&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
	};

	&can1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_flexcan1_default>;
	pinctrl-1 = <&pinctrl_flexcan1_sleep>;
	status = "disabled";
	};

	&can2 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_flexcan2_default>;
	pinctrl-1 = <&pinctrl_flexcan2_sleep>;
	status = "disabled";
	};

	/* Apalis SPI1 */
	&ecspi1 {
	cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	status = "disabled";
	};

	/* Apalis SPI2 */
	&ecspi2 {
	cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2>;
	status = "disabled";
	};

	&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	- phy-mode = "rgmii";
	+ phy-mode = "rgmii-id";
	phy-handle = <&ethphy>;
	phy-reset-duration = <10>;
	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
	status = "okay";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy: ethernet-phy@7 {
	interrupt-parent = <&gpio1>;
	interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
	reg = <7>;
	};
	};
	};

	&hdmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hdmi_ddc &pinctrl_hdmi_cec>;
	status = "disabled";
	};

	/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
	&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	status = "disabled";
	};

	/*
	* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
	* touch screen controller
	*/
	&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	status = "okay";

	pmic: pfuze100@8 {
	compatible = "fsl,pfuze100";
	reg = <0x08>;

	regulators {
	sw1a_reg: sw1ab {
	regulator-min-microvolt = <300000>;
	regulator-max-microvolt = <1875000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	sw1c_reg: sw1c {
	regulator-min-microvolt = <300000>;
	regulator-max-microvolt = <1875000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	sw3a_reg: sw3a {
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <1975000>;
	regulator-boot-on;
	regulator-always-on;
	};

	swbst_reg: swbst {
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5150000>;
	regulator-boot-on;
	regulator-always-on;
	};

	snvs_reg: vsnvs {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <3000000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vref_reg: vrefddr {
	regulator-boot-on;
	regulator-always-on;
	};

	vgen1_reg: vgen1 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vgen2_reg: vgen2 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vgen3_reg: vgen3 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vgen4_reg: vgen4 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vgen5_reg: vgen5 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vgen6_reg: vgen6 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};
	};

	codec: sgtl5000@a {
	compatible = "fsl,sgtl5000";
	reg = <0x0a>;
	clocks = <&clks IMX6QDL_CLK_CKO>;
	VDDA-supply = <&reg_module_3v3_audio>;
	VDDIO-supply = <&reg_module_3v3>;
	VDDD-supply = <&vgen4_reg>;
	};

	/* STMPE811 touch screen controller */
	stmpe811@41 {
	compatible = "st,stmpe811";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_touch_int>;
	reg = <0x41>;
	interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
	interrupt-parent = <&gpio4>;
	interrupt-controller;
	id = <0>;
	blocks = <0x5>;
	irq-trigger = <0x1>;
	/* 3.25 MHz ADC clock speed */
	st,adc-freq = <1>;
	/* 12-bit ADC */
	st,mod-12b = <1>;
	/* internal ADC reference */
	st,ref-sel = <0>;
	/* ADC converstion time: 80 clocks */
	st,sample-time = <4>;

	stmpe_touchscreen {
	compatible = "st,stmpe-ts";
	/* 8 sample average control */
	st,ave-ctrl = <3>;
	/* 7 length fractional part in z */
	st,fraction-z = <7>;
	/*
	* 50 mA typical 80 mA max touchscreen drivers
	* current limit value
	*/
	st,i-drive = <1>;
	/* 1 ms panel driver settling time */
	st,settling = <3>;
	/* 5 ms touch detect interrupt delay */
	st,touch-det-delay = <5>;
	};

	stmpe_adc {
	compatible = "st,stmpe-adc";
	/* forbid to use ADC channels 3-0 (touch) */
	st,norequest-mask = <0x0F>;
	};
	};
	};

	/*
	* I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
	* board)
	*/
	&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	status = "disabled";
	};

	&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "disabled";
	};

	&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	status = "disabled";
	};

	&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "disabled";
	};

	&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
	status = "disabled";
	};

	&spdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spdif>;
	status = "disabled";
	};

	&ssi1 {
	status = "okay";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
	fsl,dte-mode;
	uart-has-rtscts;
	status = "disabled";
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2_dte>;
	fsl,dte-mode;
	uart-has-rtscts;
	status = "disabled";
	};

	&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4_dte>;
	fsl,dte-mode;
	status = "disabled";
	};

	&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5_dte>;
	fsl,dte-mode;
	status = "disabled";
	};

	&usbotg {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	disable-over-current;
	status = "disabled";
	};

	/* MMC1 */
	&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>;
	vqmmc-supply = <&reg_module_3v3>;
	bus-width = <8>;
	disable-wp;
	no-1-8-v;
	status = "disabled";
	};

	/* SD1 */
	&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	vqmmc-supply = <&reg_module_3v3>;
	bus-width = <4>;
	disable-wp;
	no-1-8-v;
	status = "disabled";
	};

	/* eMMC */
	&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	vqmmc-supply = <&reg_module_3v3>;
	bus-width = <8>;
	no-1-8-v;
	non-removable;
	status = "okay";
	};

	&weim {
	status = "disabled";
	};

	&iomuxc {
	pinctrl_apalis_gpio1: gpio2io04grp {
	fsl,pins = <
	MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
	>;
	};

	pinctrl_apalis_gpio2: gpio2io05grp {
	fsl,pins = <
	MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
	>;
	};

	pinctrl_apalis_gpio3: gpio2io06grp {
	fsl,pins = <
	MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
	>;
	};

	pinctrl_apalis_gpio4: gpio2io07grp {
	fsl,pins = <
	MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
	>;
	};

	pinctrl_apalis_gpio5: gpio6io10grp {
	fsl,pins = <
	MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
	>;
	};

	pinctrl_apalis_gpio6: gpio6io09grp {
	fsl,pins = <
	MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
	>;
	};

	pinctrl_apalis_gpio7: gpio1io02grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
	>;
	};

	pinctrl_apalis_gpio8: gpio1io06grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
	>;
	};

	pinctrl_audmux: audmuxgrp {
	fsl,pins = <
	MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
	MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
	MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
	MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
	/* SGTL5000 sys_mclk */
	MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
	>;
	};

	pinctrl_cam_mclk: cammclkgrp {
	fsl,pins = <
	/* CAM sys_mclk */
	MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
	>;
	};

	pinctrl_ecspi1: ecspi1grp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
	MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
	MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
	/* SPI1 cs */
	MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1
	>;
	};

	pinctrl_ecspi2: ecspi2grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
	MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
	MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
	/* SPI2 cs */
	MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
	>;
	};

	pinctrl_enet: enetgrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
	/* Ethernet PHY reset */
	MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
	/* Ethernet PHY interrupt */
	MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1
	>;
	};

	pinctrl_flexcan1_default: flexcan1defgrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
	MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
	>;
	};

	pinctrl_flexcan1_sleep: flexcan1slpgrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0
	MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0
	>;
	};

	pinctrl_flexcan2_default: flexcan2defgrp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
	MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
	>;
	};
	pinctrl_flexcan2_sleep: flexcan2slpgrp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0
	MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0
	>;
	};

	pinctrl_gpio_bl_on: gpioblon {
	fsl,pins = <
	MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
	>;
	};

	pinctrl_gpio_keys: gpio1io04grp {
	fsl,pins = <
	/* Power button */
	MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
	>;
	};

	pinctrl_hdmi_cec: hdmicecgrp {
	fsl,pins = <
	MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
	>;
	};

	pinctrl_hdmi_ddc: hdmiddcgrp {
	fsl,pins = <
	MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
	MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
	MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
	>;
	};

	pinctrl_i2c1_gpio: i2c1gpiogrp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1
	MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
	MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
	MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
	MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
	>;
	};

	pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1
	MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1
	MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1
	MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1
	MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1
	MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1
	MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1
	MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1
	MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
	MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1
	MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1
	>;
	};

	pinctrl_ipu1_lcdif: ipu1lcdifgrp {
	fsl,pins = <
	MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61
	/* DE */
	MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61
	/* HSync */
	MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61
	/* VSync */
	MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61
	MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61
	MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61
	MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61
	MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61
	MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61
	MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61
	MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61
	MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61
	MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61
	MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61
	MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61
	MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61
	MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61
	MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61
	MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61
	MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61
	MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61
	MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61
	MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61
	MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61
	MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61
	MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61
	MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61
	MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61
	>;
	};

	pinctrl_ipu2_vdac: ipu2vdacgrp {
	fsl,pins = <
	MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1
	MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1
	MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1
	MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1
	MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9
	MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9
	MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9
	MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9
	MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9
	MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9
	MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9
	MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9
	MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9
	MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9
	MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9
	MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9
	MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9
	MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9
	MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9
	MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9
	>;
	};

	pinctrl_mmc_cd: gpiommccdgrp {
	fsl,pins = <
	/* MMC1 CD */
	MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
	>;
	};

	pinctrl_pwm1: pwm1grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm2: pwm2grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm3: pwm3grp {
	fsl,pins = <
	MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm4: pwm4grp {
	fsl,pins = <
	MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
	>;
	};

	pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
	fsl,pins = <
	/* USBH_EN */
	MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
	>;
	};

	pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
	fsl,pins = <
	/* USBH_HUB_EN */
	MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
	>;
	};

	pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
	fsl,pins = <
	/* USBO1 power en */
	MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
	>;
	};

	pinctrl_reset_moci: gpioresetmocigrp {
	fsl,pins = <
	/* RESET_MOCI control */
	MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
	>;
	};

	pinctrl_sd_cd: gpiosdcdgrp {
	fsl,pins = <
	/* SD1 CD */
	MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
	>;
	};

	pinctrl_spdif: spdifgrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
	MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
	>;
	};

	pinctrl_touch_int: gpiotouchintgrp {
	fsl,pins = <
	/* STMPE811 interrupt */
	MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
	>;
	};

	pinctrl_uart1_dce: uart1dcegrp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
	MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
	>;
	};

	/* DTE mode */
	pinctrl_uart1_dte: uart1dtegrp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
	MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
	MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
	MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
	>;
	};

	/* Additional DTR, DSR, DCD */
	pinctrl_uart1_ctrl: uart1ctrlgrp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
	MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
	MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
	>;
	};

	pinctrl_uart2_dce: uart2dcegrp {
	fsl,pins = <
	MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
	MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
	>;
	};

	/* DTE mode */
	pinctrl_uart2_dte: uart2dtegrp {
	fsl,pins = <
	MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
	MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
	MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
	MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
	>;
	};

	pinctrl_uart4_dce: uart4dcegrp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
	MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
	>;
	};

	/* DTE mode */
	pinctrl_uart4_dte: uart4dtegrp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
	MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart5_dce: uart5dcegrp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
	MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
	>;
	};

	/* DTE mode */
	pinctrl_uart5_dte: uart5dtegrp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
	MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
	>;
	};

	pinctrl_usbotg: usbotggrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
	>;
	};

	pinctrl_usdhc1_4bit: usdhc1grp_4bit {
	fsl,pins = <
	MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
	MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
	MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
	MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
	MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
	MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
	>;
	};

	pinctrl_usdhc1_8bit: usdhc1grp_8bit {
	fsl,pins = <
	MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
	MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
	MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
	MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
	>;
	};

	pinctrl_usdhc2: usdhc2grp {
	fsl,pins = <
	MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
	MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
	MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
	MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
	MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
	MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
	MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
	MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
	MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
	MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
	/* eMMC reset */
	MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6qdl-colibri.dtsi b/sys/gnu/dts/arm/imx6qdl-colibri.dtsi
	index d03dff23863d..6e3c6b4925a7 100644
	--- a/sys/gnu/dts/arm/imx6qdl-colibri.dtsi
	+++ b/sys/gnu/dts/arm/imx6qdl-colibri.dtsi
	@@ -1,891 +1,855 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2014-2016 Toradex AG
	+ * Copyright 2014-2020 Toradex
	* Copyright 2012 Freescale Semiconductor, Inc.
	* Copyright 2011 Linaro Ltd.
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License
	- * version 2 as published by the Free Software Foundation.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include <dt-bindings/gpio/gpio.h>

	/ {
	model = "Toradex Colibri iMX6DL/S Module";
	compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";

	backlight: backlight {
	compatible = "pwm-backlight";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_bl_on>;
	pwms = <&pwm3 0 5000000>;
	enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
	status = "disabled";
	};

	reg_module_3v3: regulator-module-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_module_3v3_audio: regulator-module-3v3-audio {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3_AUDIO";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_usb_host_vbus: regulator-usb-host-vbus {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
	regulator-name = "usb_host_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
	status = "disabled";
	};

	sound {
	compatible = "fsl,imx-audio-sgtl5000";
	model = "imx6dl-colibri-sgtl5000";
	ssi-controller = <&ssi1>;
	audio-codec = <&codec>;
	audio-routing =
	"Headphone Jack", "HP_OUT",
	"LINE_IN", "Line In Jack",
	"MIC_IN", "Mic Jack",
	"Mic Jack", "Mic Bias";
	mux-int-port = <1>;
	mux-ext-port = <5>;
	};

	/* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
	sound_spdif: sound-spdif {
	compatible = "fsl,imx-audio-spdif";
	model = "imx-spdif";
	spdif-controller = <&spdif>;
	spdif-in;
	spdif-out;
	status = "disabled";
	};
	};

	&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
	status = "okay";
	};

	/* Optional on SODIMM 55/63 */
	&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "disabled";
	};

	/* Optional on SODIMM 178/188 */
	&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	status = "disabled";
	};

	/* Colibri SSP */
	&ecspi4 {
	cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi4>;
	status = "disabled";
	};

	&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rmii";
	phy-handle = <&ethphy>;
	status = "okay";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy: ethernet-phy@0 {
	reg = <0>;
	micrel,led-mode = <0>;
	};
	};
	};

	&hdmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hdmi_ddc>;
	status = "disabled";
	};

	/*
	* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
	* touch screen controller
	*/
	&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-0 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	status = "okay";

	pmic: pfuze100@8 {
	compatible = "fsl,pfuze100";
	reg = <0x08>;

	regulators {
	sw1a_reg: sw1ab {
	regulator-min-microvolt = <300000>;
	regulator-max-microvolt = <1875000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	sw1c_reg: sw1c {
	regulator-min-microvolt = <300000>;
	regulator-max-microvolt = <1875000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	sw3a_reg: sw3a {
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <1975000>;
	regulator-boot-on;
	regulator-always-on;
	};

	swbst_reg: swbst {
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5150000>;
	regulator-boot-on;
	regulator-always-on;
	};

	snvs_reg: vsnvs {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <3000000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vref_reg: vrefddr {
	regulator-boot-on;
	regulator-always-on;
	};

	/* vgen1: unused */

	vgen2_reg: vgen2 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* vgen3: unused */

	vgen4_reg: vgen4 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vgen5_reg: vgen5 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vgen6_reg: vgen6 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};
	};

	codec: sgtl5000@a {
	compatible = "fsl,sgtl5000";
	reg = <0x0a>;
	clocks = <&clks IMX6QDL_CLK_CKO>;
	VDDA-supply = <&reg_module_3v3_audio>;
	VDDIO-supply = <&reg_module_3v3>;
	VDDD-supply = <&vgen4_reg>;
	lrclk-strength = <3>;
	};

	/* STMPE811 touch screen controller */
	stmpe811@41 {
	compatible = "st,stmpe811";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_touch_int>;
	reg = <0x41>;
	interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
	interrupt-parent = <&gpio6>;
	interrupt-controller;
	id = <0>;
	blocks = <0x5>;
	irq-trigger = <0x1>;
	/* 3.25 MHz ADC clock speed */
	st,adc-freq = <1>;
	/* 12-bit ADC */
	st,mod-12b = <1>;
	/* internal ADC reference */
	st,ref-sel = <0>;
	/* ADC converstion time: 80 clocks */
	st,sample-time = <4>;

	stmpe_touchscreen {
	compatible = "st,stmpe-ts";
	/* 8 sample average control */
	st,ave-ctrl = <3>;
	/* 7 length fractional part in z */
	st,fraction-z = <7>;
	/*
	* 50 mA typical 80 mA max touchscreen drivers
	* current limit value
	*/
	st,i-drive = <1>;
	/* 1 ms panel driver settling time */
	st,settling = <3>;
	/* 5 ms touch detect interrupt delay */
	st,touch-det-delay = <5>;
	};

	stmpe_adc {
	compatible = "st,stmpe-adc";
	/* forbid to use ADC channels 3-0 (touch) */
	st,norequest-mask = <0x0F>;
	};
	};
	};

	/*
	* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
	*/
	&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	status = "disabled";
	};

	/* Colibri PWM<B> */
	&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "disabled";
	};

	/* Colibri PWM<D> */
	&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	status = "disabled";
	};

	/* Colibri PWM<A> */
	&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "disabled";
	};

	/* Colibri PWM<C> */
	&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
	status = "disabled";
	};

	/* Optional S/PDIF out on SODIMM 137 */
	&spdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spdif>;
	status = "disabled";
	};

	&ssi1 {
	status = "okay";
	};

	/* Colibri UART_A */
	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
	fsl,dte-mode;
	uart-has-rtscts;
	status = "disabled";
	};

	/* Colibri UART_B */
	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2_dte>;
	fsl,dte-mode;
	uart-has-rtscts;
	status = "disabled";
	};

	/* Colibri UART_C */
	&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3_dte>;
	fsl,dte-mode;
	status = "disabled";
	};

	&usbotg {
	pinctrl-names = "default";
	disable-over-current;
	dr_mode = "peripheral";
	status = "disabled";
	};

	/* Colibri MMC */
	&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
	cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
	disable-wp;
	vqmmc-supply = <&reg_module_3v3>;
	bus-width = <4>;
	no-1-8-v;
	status = "disabled";
	};

	/* eMMC */
	&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	vqmmc-supply = <&reg_module_3v3>;
	bus-width = <8>;
	no-1-8-v;
	non-removable;
	status = "okay";
	};

	&weim {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0
	&pinctrl_weim_cs1 &pinctrl_weim_cs2
	&pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
	#address-cells = <2>;
	#size-cells = <1>;
	status = "disabled";
	};

	&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbh_oc_1>;

	pinctrl_audmux: audmuxgrp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
	MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
	MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
	MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
	/* SGTL5000 sys_mclk */
	MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
	>;
	};

	pinctrl_cam_mclk: cammclkgrp {
	fsl,pins = <
	/* Parallel Camera CAM sys_mclk */
	MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
	>;
	};

	pinctrl_ecspi4: ecspi4grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
	MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
	MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
	/* SPI CS */
	MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
	>;
	};

	pinctrl_enet: enetgrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
	MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
	MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
	MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
	MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
	MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
	MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
	MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) \| 0x1b0b0)
	>;
	};

	pinctrl_flexcan1: flexcan1grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
	MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
	>;
	};

	pinctrl_flexcan2: flexcan2grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
	MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
	>;
	};

	pinctrl_gpio_bl_on: gpioblon {
	fsl,pins = <
	MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0
	>;
	};

	pinctrl_gpio_keys: gpiokeys {
	fsl,pins = <
	MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
	>;
	};

	pinctrl_hdmi_ddc: hdmiddcgrp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
	MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
	MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c2_gpio: i2c2grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
	MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
	MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
	MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
	>;
	};

	pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
	fsl,pins = <
	MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1
	MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1
	MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1
	MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1
	MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1
	MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1
	MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1
	MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1
	MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1
	MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1
	MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1
	/* Disable PWM pins on camera interface */
	MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
	MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40
	>;
	};

	pinctrl_ipu1_lcdif: ipu1lcdifgrp {
	fsl,pins = <
	MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1
	MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1
	MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1
	MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1
	MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1
	MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1
	MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1
	MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1
	MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1
	MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1
	MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1
	MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1
	MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1
	MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1
	MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1
	MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1
	MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1
	MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1
	MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1
	MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1
	MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1
	MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1
	>;
	};

	pinctrl_mic_gnd: gpiomicgnd {
	fsl,pins = <
	/* Controls Mic GND, PU or '1' pull Mic GND to GND */
	MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
	>;
	};

	pinctrl_mmc_cd: gpiommccd {
	fsl,pins = <
	MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1
	>;
	};

	pinctrl_pwm1: pwm1grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm2: pwm2grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
	MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040
	>;
	};

	pinctrl_pwm3: pwm3grp {
	fsl,pins = <
	MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
	MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040
	>;
	};

	pinctrl_pwm4: pwm4grp {
	fsl,pins = <
	MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
	>;
	};

	pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
	fsl,pins = <
	/* USBH_EN */
	MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058
	>;
	};

	pinctrl_usbh_oc_1: usbhoc1grp {
	fsl,pins = <
	/* USBH_OC */
	MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
	>;
	};

	pinctrl_spdif: spdifgrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
	>;
	};

	pinctrl_touch_int: gpiotouchintgrp {
	fsl,pins = <
	/* STMPE811 interrupt */
	MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
	>;
	};

	pinctrl_uart1_dce: uart1dcegrp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
	MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
	>;
	};

	/* DTE mode */
	pinctrl_uart1_dte: uart1dtegrp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
	MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
	MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
	MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
	>;
	};

	/* Additional DTR, DSR, DCD */
	pinctrl_uart1_ctrl: uart1ctrlgrp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
	MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
	MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
	>;
	};

	pinctrl_uart2_dte: uart2dtegrp {
	fsl,pins = <
	MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
	MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
	MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
	MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
	>;
	};

	pinctrl_uart3_dte: uart3dtegrp {
	fsl,pins = <
	MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
	MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_usbc_det: usbcdetgrp {
	fsl,pins = <
	/* USBC_DET */
	MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
	/* USBC_DET_EN */
	MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
	/* USBC_DET_OVERWRITE */
	MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058
	>;
	};

	pinctrl_usbc_id_1: usbc_id-1 {
	fsl,pins = <
	/* USBC_ID */
	MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
	>;
	};

	pinctrl_usdhc1: usdhc1grp {
	fsl,pins = <
	MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
	MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
	MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
	MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
	MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
	MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
	MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
	MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
	MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
	MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
	/* eMMC reset */
	MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
	>;
	};

	pinctrl_weim_cs0: weimcs0grp {
	fsl,pins = <
	/* nEXT_CS0 */
	MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
	>;
	};

	pinctrl_weim_cs1: weimcs1grp {
	fsl,pins = <
	/* nEXT_CS1 */
	MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
	>;
	};

	pinctrl_weim_cs2: weimcs2grp {
	fsl,pins = <
	/* nEXT_CS2 */
	MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1
	>;
	};

	pinctrl_weim_sram: weimsramgrp {
	fsl,pins = <
	MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
	MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
	/* Data */
	MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
	MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
	MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
	MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
	MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
	MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
	MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
	MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
	MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
	MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
	MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
	MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
	MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
	MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
	MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
	MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
	/* Address */
	MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
	MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
	MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
	MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
	MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
	MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
	MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
	MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
	MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
	MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
	MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
	MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
	MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
	MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
	MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
	MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
	>;
	};

	pinctrl_weim_rdnwr: weimrdnwr {
	fsl,pins = <
	MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
	MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
	>;
	};

	pinctrl_weim_npwe: weimnpwe {
	fsl,pins = <
	MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
	MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
	>;
	};

	/* ADDRESS[16:18] [25] used as GPIO */
	pinctrl_weim_gpio_1: weimgpio-1 {
	fsl,pins = <
	MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
	MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
	MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
	MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
	MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
	MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
	MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
	MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
	MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
	MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
	>;
	};

	/* ADDRESS[19:24] used as GPIO */
	pinctrl_weim_gpio_2: weimgpio-2 {
	fsl,pins = <
	MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
	MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
	MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
	MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
	MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
	MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
	MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
	MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
	MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
	>;
	};

	/* DATA[16:31] used as GPIO */
	pinctrl_weim_gpio_3: weimgpio-3 {
	fsl,pins = <
	MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
	MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
	MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
	MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
	MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
	MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
	MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
	MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
	MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
	MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
	MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
	MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
	MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
	MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
	MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
	>;
	};

	/* DQM[0:3] used as GPIO */
	pinctrl_weim_gpio_4: weimgpio-4 {
	fsl,pins = <
	MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
	MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
	MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
	MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
	>;
	};

	/* RDY used as GPIO */
	pinctrl_weim_gpio_5: weimgpio-5 {
	fsl,pins = <
	MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
	>;
	};

	/* ADDRESS[16] DATA[30] used as GPIO */
	pinctrl_weim_gpio_6: weimgpio-6 {
	fsl,pins = <
	MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
	MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6qdl-gw52xx.dtsi b/sys/gnu/dts/arm/imx6qdl-gw52xx.dtsi
	index 1a9a9d98f284..60563ff0b7ce 100644
	--- a/sys/gnu/dts/arm/imx6qdl-gw52xx.dtsi
	+++ b/sys/gnu/dts/arm/imx6qdl-gw52xx.dtsi
	@@ -1,628 +1,633 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	/*
	* Copyright 2013 Gateworks Corporation
	*/

	#include <dt-bindings/gpio/gpio.h>

	/ {
	/* these are used by bootloader for disabling nodes */
	aliases {
	led0 = &led0;
	led1 = &led1;
	led2 = &led2;
	nand = &gpmi;
	ssi0 = &ssi1;
	usb0 = &usbh1;
	usb1 = &usbotg;
	};

	chosen {
	bootargs = "console=ttymxc1,115200";
	};

	backlight {
	compatible = "pwm-backlight";
	pwms = <&pwm4 0 5000000>;
	brightness-levels = <0 4 8 16 32 64 128 255>;
	default-brightness-level = <7>;
	};

	leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_leds>;

	led0: user1 {
	label = "user1";
	gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
	default-state = "on";
	linux,default-trigger = "heartbeat";
	};

	led1: user2 {
	label = "user2";
	gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
	default-state = "off";
	};

	led2: user3 {
	label = "user3";
	gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
	default-state = "off";
	};
	};

	memory@10000000 {
	device_type = "memory";
	reg = <0x10000000 0x20000000>;
	};

	pps {
	compatible = "pps-gpio";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pps>;
	gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
	status = "okay";
	};

	reg_1p0v: regulator-1p0v {
	compatible = "regulator-fixed";
	regulator-name = "1P0V";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
	compatible = "regulator-fixed";
	regulator-name = "3P3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_5p0v: regulator-5p0v {
	compatible = "regulator-fixed";
	regulator-name = "5P0V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	reg_usb_otg_vbus: regulator-usb-otg-vbus {
	compatible = "regulator-fixed";
	regulator-name = "usb_otg_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	sound {
	compatible = "fsl,imx6q-ventana-sgtl5000",
	"fsl,imx-audio-sgtl5000";
	model = "sgtl5000-audio";
	ssi-controller = <&ssi1>;
	audio-codec = <&codec>;
	audio-routing =
	"MIC_IN", "Mic Jack",
	"Mic Jack", "Mic Bias",
	"Headphone Jack", "HP_OUT";
	mux-int-port = <1>;
	mux-ext-port = <4>;
	};
	};

	&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
	};

	&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "okay";
	};

	&clks {
	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
	<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
	<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
	};

	&ecspi3 {
	cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3>;
	status = "okay";
	};

	&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii-id";
	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	status = "okay";
	};

	&hdmi {
	ddc-i2c-bus = <&i2c3>;
	status = "okay";
	};

	&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	eeprom1: eeprom@50 {
	compatible = "atmel,24c02";
	reg = <0x50>;
	pagesize = <16>;
	};

	eeprom2: eeprom@51 {
	compatible = "atmel,24c02";
	reg = <0x51>;
	pagesize = <16>;
	};

	eeprom3: eeprom@52 {
	compatible = "atmel,24c02";
	reg = <0x52>;
	pagesize = <16>;
	};

	eeprom4: eeprom@53 {
	compatible = "atmel,24c02";
	reg = <0x53>;
	pagesize = <16>;
	};

	gpio: pca9555@23 {
	compatible = "nxp,pca9555";
	reg = <0x23>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	rtc: ds1672@68 {
	compatible = "dallas,ds1672";
	reg = <0x68>;
	};
	};

	&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	ltc3676: pmic@3c {
	compatible = "lltc,ltc3676";
	reg = <0x3c>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pmic>;
	interrupt-parent = <&gpio1>;
	interrupts = <8 IRQ_TYPE_EDGE_FALLING>;

	regulators {
	/* VDD_SOC (1+R1/R2 = 1.635) */
	reg_vdd_soc: sw1 {
	regulator-name = "vddsoc";
	regulator-min-microvolt = <674400>;
	regulator-max-microvolt = <1308000>;
	lltc,fb-voltage-divider = <127000 200000>;
	regulator-ramp-delay = <7000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
	reg_1p8v: sw2 {
	regulator-name = "vdd1p8";
	regulator-min-microvolt = <1033310>;
	regulator-max-microvolt = <2004000>;
	lltc,fb-voltage-divider = <301000 200000>;
	regulator-ramp-delay = <7000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* VDD_ARM (1+R1/R2 = 1.635) */
	reg_vdd_arm: sw3 {
	regulator-name = "vddarm";
	regulator-min-microvolt = <674400>;
	regulator-max-microvolt = <1308000>;
	lltc,fb-voltage-divider = <127000 200000>;
	regulator-ramp-delay = <7000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* VDD_DDR (1+R1/R2 = 2.105) */
	reg_vdd_ddr: sw4 {
	regulator-name = "vddddr";
	regulator-min-microvolt = <868310>;
	regulator-max-microvolt = <1684000>;
	lltc,fb-voltage-divider = <221000 200000>;
	regulator-ramp-delay = <7000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
	reg_2p5v: ldo2 {
	regulator-name = "vdd2p5";
	regulator-min-microvolt = <2490375>;
	regulator-max-microvolt = <2490375>;
	lltc,fb-voltage-divider = <487000 200000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* VDD_AUD_1P8: Audio codec */
	reg_aud_1p8v: ldo3 {
	regulator-name = "vdd1p8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	};

	/* VDD_HIGH (1+R1/R2 = 4.17) */
	reg_3p0v: ldo4 {
	regulator-name = "vdd3p0";
	regulator-min-microvolt = <3023250>;
	regulator-max-microvolt = <3023250>;
	lltc,fb-voltage-divider = <634000 200000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};
	};
	};

	&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	codec: sgtl5000@a {
	compatible = "fsl,sgtl5000";
	reg = <0x0a>;
	clocks = <&clks IMX6QDL_CLK_CKO>;
	VDDA-supply = <&reg_1p8v>;
	VDDIO-supply = <&reg_3p3v>;
	};

	touchscreen: egalax_ts@4 {
	compatible = "eeti,egalax_ts";
	reg = <0x04>;
	interrupt-parent = <&gpio7>;
	interrupts = <12 2>;
	wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
	};
	+
	+ accel@1e {
	+ compatible = "nxp,fxos8700";
	+ reg = <0x1e>;
	+ };
	};

	&ldb {
	status = "okay";

	lvds-channel@0 {
	fsl,data-mapping = "spwg";
	fsl,data-width = <18>;
	status = "okay";

	display-timings {
	native-mode = <&timing0>;
	timing0: hsd100pxn1 {
	clock-frequency = <65000000>;
	hactive = <1024>;
	vactive = <768>;
	hback-porch = <220>;
	hfront-porch = <40>;
	vback-porch = <21>;
	vfront-porch = <7>;
	hsync-len = <60>;
	vsync-len = <10>;
	};
	};
	};
	};

	&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
	status = "disabled";
	};

	&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
	status = "disabled";
	};

	&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
	status = "okay";
	};

	&ssi1 {
	status = "okay";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
	status = "okay";
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
	};

	&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	status = "okay";
	};

	&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	disable-over-current;
	status = "okay";
	};

	&usbh1 {
	status = "okay";
	};

	&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_3p3v>;
	no-1-8-v; /* firmware will remove if board revision supports */
	status = "okay";
	};

	&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	};

	&iomuxc {
	pinctrl_audmux: audmuxgrp {
	fsl,pins = <
	MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
	MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
	MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
	MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
	MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
	>;
	};

	pinctrl_ecspi3: escpi3grp {
	fsl,pins = <
	MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
	MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
	MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
	MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
	>;
	};

	pinctrl_enet: enetgrp {
	fsl,pins = <
	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
	MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
	MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
	>;
	};

	pinctrl_flexcan1: flexcan1grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
	MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
	MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
	>;
	};

	pinctrl_gpio_leds: gpioledsgrp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
	MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
	MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
	>;
	};

	pinctrl_gpmi_nand: gpminandgrp {
	fsl,pins = <
	MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
	MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
	MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
	MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
	MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
	MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
	MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
	MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
	MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
	MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
	MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
	MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
	MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
	MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
	MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
	MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
	MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
	>;
	};

	pinctrl_pcie: pciegrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
	>;
	};

	pinctrl_pmic: pmicgrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
	>;
	};

	pinctrl_pps: ppsgrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
	>;
	};

	pinctrl_pwm2: pwm2grp {
	fsl,pins = <
	MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm3: pwm3grp {
	fsl,pins = <
	MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm4: pwm4grp {
	fsl,pins = <
	MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
	MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
	MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
	MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart5: uart5grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
	MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_usbotg: usbotggrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
	MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
	>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
	>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
	>;
	};

	pinctrl_wdog: wdoggrp {
	fsl,pins = <
	MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6qdl-gw53xx.dtsi b/sys/gnu/dts/arm/imx6qdl-gw53xx.dtsi
	index 54b2beadd7a2..8942bec65c5c 100644
	--- a/sys/gnu/dts/arm/imx6qdl-gw53xx.dtsi
	+++ b/sys/gnu/dts/arm/imx6qdl-gw53xx.dtsi
	@@ -1,612 +1,617 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	/*
	* Copyright 2013 Gateworks Corporation
	*/

	#include <dt-bindings/gpio/gpio.h>

	/ {
	/* these are used by bootloader for disabling nodes */
	aliases {
	led0 = &led0;
	led1 = &led1;
	led2 = &led2;
	nand = &gpmi;
	ssi0 = &ssi1;
	usb0 = &usbh1;
	usb1 = &usbotg;
	};

	chosen {
	bootargs = "console=ttymxc1,115200";
	};

	backlight {
	compatible = "pwm-backlight";
	pwms = <&pwm4 0 5000000>;
	brightness-levels = <0 4 8 16 32 64 128 255>;
	default-brightness-level = <7>;
	};

	leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_leds>;

	led0: user1 {
	label = "user1";
	gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
	default-state = "on";
	linux,default-trigger = "heartbeat";
	};

	led1: user2 {
	label = "user2";
	gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
	default-state = "off";
	};

	led2: user3 {
	label = "user3";
	gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
	default-state = "off";
	};
	};

	memory@10000000 {
	device_type = "memory";
	reg = <0x10000000 0x40000000>;
	};

	pps {
	compatible = "pps-gpio";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pps>;
	gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
	status = "okay";
	};

	reg_1p0v: regulator-1p0v {
	compatible = "regulator-fixed";
	regulator-name = "1P0V";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
	compatible = "regulator-fixed";
	regulator-name = "3P3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_usb_h1_vbus: regulator-usb-h1-vbus {
	compatible = "regulator-fixed";
	regulator-name = "usb_h1_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	reg_usb_otg_vbus: regulator-usb-otg-vbus {
	compatible = "regulator-fixed";
	regulator-name = "usb_otg_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	sound {
	compatible = "fsl,imx6q-ventana-sgtl5000",
	"fsl,imx-audio-sgtl5000";
	model = "sgtl5000-audio";
	ssi-controller = <&ssi1>;
	audio-codec = <&codec>;
	audio-routing =
	"MIC_IN", "Mic Jack",
	"Mic Jack", "Mic Bias",
	"Headphone Jack", "HP_OUT";
	mux-int-port = <1>;
	mux-ext-port = <4>;
	};
	};

	&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
	};

	&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "okay";
	};

	&clks {
	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
	<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
	<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
	};

	&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii-id";
	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	status = "okay";
	};

	&hdmi {
	ddc-i2c-bus = <&i2c3>;
	status = "okay";
	};

	&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	eeprom1: eeprom@50 {
	compatible = "atmel,24c02";
	reg = <0x50>;
	pagesize = <16>;
	};

	eeprom2: eeprom@51 {
	compatible = "atmel,24c02";
	reg = <0x51>;
	pagesize = <16>;
	};

	eeprom3: eeprom@52 {
	compatible = "atmel,24c02";
	reg = <0x52>;
	pagesize = <16>;
	};

	eeprom4: eeprom@53 {
	compatible = "atmel,24c02";
	reg = <0x53>;
	pagesize = <16>;
	};

	gpio: pca9555@23 {
	compatible = "nxp,pca9555";
	reg = <0x23>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	rtc: ds1672@68 {
	compatible = "dallas,ds1672";
	reg = <0x68>;
	};
	};

	&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	ltc3676: pmic@3c {
	compatible = "lltc,ltc3676";
	reg = <0x3c>;
	interrupt-parent = <&gpio1>;
	interrupts = <8 IRQ_TYPE_EDGE_FALLING>;

	regulators {
	/* VDD_SOC (1+R1/R2 = 1.635) */
	reg_vdd_soc: sw1 {
	regulator-name = "vddsoc";
	regulator-min-microvolt = <674400>;
	regulator-max-microvolt = <1308000>;
	lltc,fb-voltage-divider = <127000 200000>;
	regulator-ramp-delay = <7000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
	reg_1p8v: sw2 {
	regulator-name = "vdd1p8";
	regulator-min-microvolt = <1033310>;
	regulator-max-microvolt = <2004000>;
	lltc,fb-voltage-divider = <301000 200000>;
	regulator-ramp-delay = <7000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* VDD_ARM (1+R1/R2 = 1.635) */
	reg_vdd_arm: sw3 {
	regulator-name = "vddarm";
	regulator-min-microvolt = <674400>;
	regulator-max-microvolt = <1308000>;
	lltc,fb-voltage-divider = <127000 200000>;
	regulator-ramp-delay = <7000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* VDD_DDR (1+R1/R2 = 2.105) */
	reg_vdd_ddr: sw4 {
	regulator-name = "vddddr";
	regulator-min-microvolt = <868310>;
	regulator-max-microvolt = <1684000>;
	lltc,fb-voltage-divider = <221000 200000>;
	regulator-ramp-delay = <7000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
	reg_2p5v: ldo2 {
	regulator-name = "vdd2p5";
	regulator-min-microvolt = <2490375>;
	regulator-max-microvolt = <2490375>;
	lltc,fb-voltage-divider = <487000 200000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* VDD_AUD_1P8: Audio codec */
	reg_aud_1p8v: ldo3 {
	regulator-name = "vdd1p8a";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	};

	/* VDD_HIGH (1+R1/R2 = 4.17) */
	reg_3p0v: ldo4 {
	regulator-name = "vdd3p0";
	regulator-min-microvolt = <3023250>;
	regulator-max-microvolt = <3023250>;
	lltc,fb-voltage-divider = <634000 200000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};
	};
	};

	&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	codec: sgtl5000@a {
	compatible = "fsl,sgtl5000";
	reg = <0x0a>;
	clocks = <&clks IMX6QDL_CLK_CKO>;
	VDDA-supply = <&reg_1p8v>;
	VDDIO-supply = <&reg_3p3v>;
	};

	touchscreen: egalax_ts@4 {
	compatible = "eeti,egalax_ts";
	reg = <0x04>;
	interrupt-parent = <&gpio1>;
	interrupts = <11 2>;
	wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
	};
	+
	+ accel@1e {
	+ compatible = "nxp,fxos8700";
	+ reg = <0x1e>;
	+ };
	};

	&ldb {
	status = "okay";

	lvds-channel@0 {
	fsl,data-mapping = "spwg";
	fsl,data-width = <18>;
	status = "okay";

	display-timings {
	native-mode = <&timing0>;
	timing0: hsd100pxn1 {
	clock-frequency = <65000000>;
	hactive = <1024>;
	vactive = <768>;
	hback-porch = <220>;
	hfront-porch = <40>;
	vback-porch = <21>;
	vfront-porch = <7>;
	hsync-len = <60>;
	vsync-len = <10>;
	};
	};
	};
	};

	&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
	status = "disabled";
	};

	&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
	status = "disabled";
	};

	&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
	status = "okay";
	};

	&ssi1 {
	status = "okay";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
	status = "okay";
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
	};

	&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	status = "okay";
	};

	&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	disable-over-current;
	status = "okay";
	};

	&usbh1 {
	vbus-supply = <&reg_usb_h1_vbus>;
	status = "okay";
	};

	&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_3p3v>;
	no-1-8-v; /* firmware will remove if board revision supports */
	status = "okay";
	};

	&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	};

	&iomuxc {
	pinctrl_audmux: audmuxgrp {
	fsl,pins = <
	MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
	MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
	MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
	MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
	MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
	>;
	};

	pinctrl_enet: enetgrp {
	fsl,pins = <
	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
	MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
	>;
	};

	pinctrl_flexcan1: flexcan1grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
	MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
	MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
	>;
	};

	pinctrl_gpio_leds: gpioledsgrp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
	MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
	MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
	>;
	};

	pinctrl_gpmi_nand: gpminandgrp {
	fsl,pins = <
	MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
	MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
	MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
	MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
	MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
	MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
	MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
	MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
	MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
	MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
	MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
	MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
	MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
	MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
	MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
	MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
	MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
	>;
	};

	pinctrl_pcie: pciegrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
	MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
	>;
	};

	pinctrl_pmic: pmicgrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
	>;
	};

	pinctrl_pps: ppsgrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
	>;
	};

	pinctrl_pwm2: pwm2grp {
	fsl,pins = <
	MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm3: pwm3grp {
	fsl,pins = <
	MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm4: pwm4grp {
	fsl,pins = <
	MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
	MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
	MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
	MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart5: uart5grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
	MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_usbotg: usbotggrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
	MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
	MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
	>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
	>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
	>;
	};

	pinctrl_wdog: wdoggrp {
	fsl,pins = <
	MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6qdl-gw54xx.dtsi b/sys/gnu/dts/arm/imx6qdl-gw54xx.dtsi
	index 1b6c1331c220..c40583dbd96d 100644
	--- a/sys/gnu/dts/arm/imx6qdl-gw54xx.dtsi
	+++ b/sys/gnu/dts/arm/imx6qdl-gw54xx.dtsi
	@@ -1,704 +1,709 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	/*
	* Copyright 2013 Gateworks Corporation
	*/

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/sound/fsl-imx-audmux.h>

	/ {
	/* these are used by bootloader for disabling nodes */
	aliases {
	led0 = &led0;
	led1 = &led1;
	led2 = &led2;
	nand = &gpmi;
	ssi0 = &ssi1;
	usb0 = &usbh1;
	usb1 = &usbotg;
	};

	chosen {
	bootargs = "console=ttymxc1,115200";
	};

	backlight {
	compatible = "pwm-backlight";
	pwms = <&pwm4 0 5000000>;
	brightness-levels = <0 4 8 16 32 64 128 255>;
	default-brightness-level = <7>;
	};

	leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_leds>;

	led0: user1 {
	label = "user1";
	gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
	default-state = "on";
	linux,default-trigger = "heartbeat";
	};

	led1: user2 {
	label = "user2";
	gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
	default-state = "off";
	};

	led2: user3 {
	label = "user3";
	gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
	default-state = "off";
	};
	};

	memory@10000000 {
	device_type = "memory";
	reg = <0x10000000 0x40000000>;
	};

	pps {
	compatible = "pps-gpio";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pps>;
	gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
	status = "okay";
	};

	regulators {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	reg_1p0v: regulator@0 {
	compatible = "regulator-fixed";
	reg = <0>;
	regulator-name = "1P0V";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	reg_3p3v: regulator@1 {
	compatible = "regulator-fixed";
	reg = <1>;
	regulator-name = "3P3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_usb_h1_vbus: regulator@2 {
	compatible = "regulator-fixed";
	reg = <2>;
	regulator-name = "usb_h1_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	reg_usb_otg_vbus: regulator@3 {
	compatible = "regulator-fixed";
	reg = <3>;
	regulator-name = "usb_otg_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};
	};

	sound-analog {
	compatible = "fsl,imx6q-ventana-sgtl5000",
	"fsl,imx-audio-sgtl5000";
	model = "sgtl5000-audio";
	ssi-controller = <&ssi1>;
	audio-codec = <&sgtl5000>;
	audio-routing =
	"MIC_IN", "Mic Jack",
	"Mic Jack", "Mic Bias",
	"Headphone Jack", "HP_OUT";
	mux-int-port = <1>;
	mux-ext-port = <4>;
	};
	};

	&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
	status = "okay";

	ssi2 {
	fsl,audmux-port = <1>;
	fsl,port-config = <
	(IMX_AUDMUX_V2_PTCR_TFSDIR \|
	IMX_AUDMUX_V2_PTCR_TFSEL(4+8) \| /* RXFS */
	IMX_AUDMUX_V2_PTCR_TCLKDIR \|
	IMX_AUDMUX_V2_PTCR_TCSEL(4+8) \| /* RXC */
	IMX_AUDMUX_V2_PTCR_SYN)
	IMX_AUDMUX_V2_PDCR_RXDSEL(4)
	>;
	};

	aud5 {
	fsl,audmux-port = <4>;
	fsl,port-config = <
	IMX_AUDMUX_V2_PTCR_SYN
	IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
	};
	};

	&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "okay";
	};

	&clks {
	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
	<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
	<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
	};

	&ecspi2 {
	cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2>;
	status = "okay";
	};

	&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii-id";
	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	status = "okay";
	};

	&hdmi {
	ddc-i2c-bus = <&i2c3>;
	status = "okay";
	};

	&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	eeprom1: eeprom@50 {
	compatible = "atmel,24c02";
	reg = <0x50>;
	pagesize = <16>;
	};

	eeprom2: eeprom@51 {
	compatible = "atmel,24c02";
	reg = <0x51>;
	pagesize = <16>;
	};

	eeprom3: eeprom@52 {
	compatible = "atmel,24c02";
	reg = <0x52>;
	pagesize = <16>;
	};

	eeprom4: eeprom@53 {
	compatible = "atmel,24c02";
	reg = <0x53>;
	pagesize = <16>;
	};

	gpio: pca9555@23 {
	compatible = "nxp,pca9555";
	reg = <0x23>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	rtc: ds1672@68 {
	compatible = "dallas,ds1672";
	reg = <0x68>;
	};
	};

	&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	pmic: pfuze100@8 {
	compatible = "fsl,pfuze100";
	reg = <0x08>;

	regulators {
	sw1a_reg: sw1ab {
	regulator-min-microvolt = <300000>;
	regulator-max-microvolt = <1875000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	sw1c_reg: sw1c {
	regulator-min-microvolt = <300000>;
	regulator-max-microvolt = <1875000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	sw2_reg: sw2 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3950000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw3a_reg: sw3a {
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <1975000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw3b_reg: sw3b {
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <1975000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw4_reg: sw4 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3300000>;
	};

	swbst_reg: swbst {
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5150000>;
	regulator-boot-on;
	regulator-always-on;
	};

	snvs_reg: vsnvs {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <3000000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vref_reg: vrefddr {
	regulator-boot-on;
	regulator-always-on;
	};

	vgen1_reg: vgen1 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	};

	vgen2_reg: vgen2 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	};

	vgen3_reg: vgen3 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	};

	vgen4_reg: vgen4 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen5_reg: vgen5 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen6_reg: vgen6 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};
	};
	};
	};

	&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	sgtl5000: audio-codec@a {
	compatible = "fsl,sgtl5000";
	reg = <0x0a>;
	clocks = <&clks IMX6QDL_CLK_CKO>;
	VDDA-supply = <&sw4_reg>;
	VDDIO-supply = <&reg_3p3v>;
	};

	touchscreen: egalax_ts@4 {
	compatible = "eeti,egalax_ts";
	reg = <0x04>;
	interrupt-parent = <&gpio7>;
	interrupts = <12 2>;
	wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
	};
	+
	+ accel@1e {
	+ compatible = "nxp,fxos8700";
	+ reg = <0x1e>;
	+ };
	};

	&ldb {
	status = "okay";

	lvds-channel@0 {
	fsl,data-mapping = "spwg";
	fsl,data-width = <18>;
	status = "okay";

	display-timings {
	native-mode = <&timing0>;
	timing0: hsd100pxn1 {
	clock-frequency = <65000000>;
	hactive = <1024>;
	vactive = <768>;
	hback-porch = <220>;
	hfront-porch = <40>;
	vback-porch = <21>;
	vfront-porch = <7>;
	hsync-len = <60>;
	vsync-len = <10>;
	};
	};
	};
	};

	&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
	status = "disabled";
	};

	&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
	status = "disabled";
	};

	&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
	status = "disabled";
	};

	&pwm4 {
	pinctrl-names = "default", "state_dio";
	pinctrl-0 = <&pinctrl_pwm4_backlight>;
	pinctrl-1 = <&pinctrl_pwm4_dio>;
	status = "okay";
	};

	&ssi1 {
	status = "okay";
	};

	&ssi2 {
	status = "okay";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
	status = "okay";
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
	};

	&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	status = "okay";
	};

	&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	disable-over-current;
	status = "okay";
	};

	&usbh1 {
	vbus-supply = <&reg_usb_h1_vbus>;
	status = "okay";
	};

	&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_3p3v>;
	no-1-8-v; /* firmware will remove if board revision supports */
	status = "okay";
	};

	&wdog1 {
	status = "disabled";
	};

	&wdog2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
	};

	&iomuxc {
	pinctrl_audmux: audmuxgrp {
	fsl,pins = <
	MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
	MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
	MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
	MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
	MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
	MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0
	MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
	MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0
	>;
	};

	pinctrl_enet: enetgrp {
	fsl,pins = <
	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
	MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
	>;
	};

	pinctrl_ecspi2: escpi2grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
	MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
	MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
	MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
	>;
	};

	pinctrl_flexcan1: flexcan1grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
	MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
	MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
	>;
	};

	pinctrl_gpio_leds: gpioledsgrp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
	MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
	MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
	>;
	};

	pinctrl_gpmi_nand: gpminandgrp {
	fsl,pins = <
	MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
	MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
	MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
	MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
	MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
	MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
	MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
	MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
	MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
	MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
	MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
	MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
	MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
	MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
	MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
	MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
	MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
	>;
	};

	pinctrl_pcie: pciegrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
	MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
	>;
	};

	pinctrl_pps: ppsgrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
	>;
	};

	pinctrl_pwm1: pwm1grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm2: pwm2grp {
	fsl,pins = <
	MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm3: pwm3grp {
	fsl,pins = <
	MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm4_backlight: pwm4grpbacklight {
	fsl,pins = <
	/* LVDS_PWM J6.5 */
	MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm4_dio: pwm4grpdio {
	fsl,pins = <
	/* DIO3 J16.4 */
	MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
	MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
	MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
	MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart5: uart5grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
	MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_usbotg: usbotggrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
	MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
	>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
	>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
	>;
	};

	pinctrl_wdog: wdoggrp {
	fsl,pins = <
	MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6qdl-gw553x.dtsi b/sys/gnu/dts/arm/imx6qdl-gw553x.dtsi
	index a1066897be18..ee85031c3916 100644
	--- a/sys/gnu/dts/arm/imx6qdl-gw553x.dtsi
	+++ b/sys/gnu/dts/arm/imx6qdl-gw553x.dtsi
	@@ -1,568 +1,599 @@
	/*
	* Copyright 2016 Gateworks Corporation
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of
	* the License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* You should have received a copy of the GNU General Public
	* License along with this file; if not, write to the Free
	* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
	* MA 02110-1301 USA
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include <dt-bindings/gpio/gpio.h>

	/ {
	/* these are used by bootloader for disabling nodes */
	aliases {
	led0 = &led0;
	led1 = &led1;
	nand = &gpmi;
	usb0 = &usbh1;
	usb1 = &usbotg;
	};

	chosen {
	stdout-path = &uart2;
	};

	leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_leds>;

	led0: user1 {
	label = "user1";
	gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
	default-state = "on";
	linux,default-trigger = "heartbeat";
	};

	led1: user2 {
	label = "user2";
	gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
	default-state = "off";
	};
	};

	memory@10000000 {
	device_type = "memory";
	reg = <0x10000000 0x20000000>;
	};

	pps {
	compatible = "pps-gpio";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pps>;
	gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
	status = "okay";
	};

	reg_5p0v: regulator-5p0v {
	compatible = "regulator-fixed";
	regulator-name = "5P0V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	reg_usb_otg_vbus: regulator-usb-otg-vbus {
	compatible = "regulator-fixed";
	regulator-name = "usb_otg_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};
	};

	&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	status = "okay";
	};

	&hdmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hdmi>;
	ddc-i2c-bus = <&i2c3>;
	status = "okay";
	};

	&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	gpio: pca9555@23 {
	compatible = "nxp,pca9555";
	reg = <0x23>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	eeprom1: eeprom@50 {
	compatible = "atmel,24c02";
	reg = <0x50>;
	pagesize = <16>;
	};

	eeprom2: eeprom@51 {
	compatible = "atmel,24c02";
	reg = <0x51>;
	pagesize = <16>;
	};

	eeprom3: eeprom@52 {
	compatible = "atmel,24c02";
	reg = <0x52>;
	pagesize = <16>;
	};

	eeprom4: eeprom@53 {
	compatible = "atmel,24c02";
	reg = <0x53>;
	pagesize = <16>;
	};

	rtc: ds1672@68 {
	compatible = "dallas,ds1672";
	reg = <0x68>;
	};
	};

	&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	+ magn@1c {
	+ compatible = "st,lsm9ds1-magn";
	+ reg = <0x1c>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_mag>;
	+ interrupt-parent = <&gpio1>;
	+ interrupts = <2 IRQ_TYPE_EDGE_RISING>;
	+ };
	+
	+ imu@6a {
	+ compatible = "st,lsm9ds1-imu";
	+ reg = <0x6a>;
	+ st,drdy-int-pin = <1>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_imu>;
	+ interrupt-parent = <&gpio7>;
	+ interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
	+ };
	+
	ltc3676: pmic@3c {
	compatible = "lltc,ltc3676";
	reg = <0x3c>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pmic>;
	interrupt-parent = <&gpio1>;
	interrupts = <8 IRQ_TYPE_EDGE_FALLING>;

	regulators {
	/* VDD_SOC (1+R1/R2 = 1.635) */
	reg_vdd_soc: sw1 {
	regulator-name = "vddsoc";
	regulator-min-microvolt = <674400>;
	regulator-max-microvolt = <1308000>;
	lltc,fb-voltage-divider = <127000 200000>;
	regulator-ramp-delay = <7000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* VDD_DDR (1+R1/R2 = 2.105) */
	reg_vdd_ddr: sw2 {
	regulator-name = "vddddr";
	regulator-min-microvolt = <868310>;
	regulator-max-microvolt = <1684000>;
	lltc,fb-voltage-divider = <221000 200000>;
	regulator-ramp-delay = <7000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* VDD_ARM (1+R1/R2 = 1.635) */
	reg_vdd_arm: sw3 {
	regulator-name = "vddarm";
	regulator-min-microvolt = <674400>;
	regulator-max-microvolt = <1308000>;
	lltc,fb-voltage-divider = <127000 200000>;
	regulator-ramp-delay = <7000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* VDD_3P3 (1+R1/R2 = 1.281) */
	reg_3p3v: sw4 {
	regulator-name = "vdd3p3";
	regulator-min-microvolt = <1880000>;
	regulator-max-microvolt = <3647000>;
	lltc,fb-voltage-divider = <200000 56200>;
	regulator-ramp-delay = <7000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */
	reg_1p8a: ldo2 {
	regulator-name = "vdd1p8a";
	regulator-min-microvolt = <1816125>;
	regulator-max-microvolt = <1816125>;
	lltc,fb-voltage-divider = <301000 200000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* VDD_1P8b: microSD VDD_1P8 */
	reg_1p8b: ldo3 {
	regulator-name = "vdd1p8b";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	};

	/* VDD_HIGH (1+R1/R2 = 4.17) */
	reg_3p0v: ldo4 {
	regulator-name = "vdd3p0";
	regulator-min-microvolt = <3023250>;
	regulator-max-microvolt = <3023250>;
	lltc,fb-voltage-divider = <634000 200000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};
	};
	};

	&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	adv7180: camera@20 {
	compatible = "adi,adv7180";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adv7180>;
	reg = <0x20>;
	powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
	interrupt-parent = <&gpio5>;
	interrupts = <23 IRQ_TYPE_LEVEL_LOW>;

	port {
	adv7180_to_ipu1_csi0_mux: endpoint {
	remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
	bus-width = <8>;
	};
	};
	};
	};

	&ipu1_csi0_from_ipu1_csi0_mux {
	bus-width = <8>;
	};

	&ipu1_csi0_mux_from_parallel_sensor {
	remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
	bus-width = <8>;
	};

	&ipu1_csi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ipu1_csi0>;
	};

	&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
	status = "disabled";
	};

	&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
	status = "disabled";
	};

	&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
	status = "disabled";
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
	};

	&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
	};

	&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
	};

	&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	status = "okay";
	};

	&usbh1 {
	status = "okay";
	};

	&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	disable-over-current;
	status = "okay";
	};

	&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	};

	&iomuxc {
	pinctrl_adv7180: adv7180grp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0
	MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0
	>;
	};

	pinctrl_gpmi_nand: gpminandgrp {
	fsl,pins = <
	MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
	MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
	MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
	MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
	MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
	MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
	MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
	MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
	MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
	MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
	MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
	MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
	MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
	MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
	MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
	>;
	};

	pinctrl_hdmi: hdmigrp {
	fsl,pins = <
	MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
	MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
	MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
	>;
	};

	+ pinctrl_imu: imugrp {
	+ fsl,pins = <
	+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
	+ >;
	+ };
	+
	pinctrl_ipu1_csi0: ipu1csi0grp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
	MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
	MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
	MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
	MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
	MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
	MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
	MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
	MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
	MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
	MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
	>;
	};

	pinctrl_gpio_leds: gpioledsgrp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
	MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
	>;
	};

	+ pinctrl_mag: maggrp {
	+ fsl,pins = <
	+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
	+ >;
	+ };
	+
	pinctrl_pcie: pciegrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
	MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */
	>;
	};

	pinctrl_pmic: pmicgrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
	>;
	};

	pinctrl_pps: ppsgrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
	>;
	};

	pinctrl_pwm2: pwm2grp {
	fsl,pins = <
	MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm3: pwm3grp {
	fsl,pins = <
	MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm4: pwm4grp {
	fsl,pins = <
	MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
	MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart3: uart3grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
	MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart4: uart4grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
	MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart5: uart5grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
	MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_usbotg: usbotggrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
	MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
	>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
	>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
	>;
	};

	pinctrl_wdog: wdoggrp {
	fsl,pins = <
	MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6qdl-gw5910.dtsi b/sys/gnu/dts/arm/imx6qdl-gw5910.dtsi
	index be1af7482f89..30fe47ff64a4 100644
	--- a/sys/gnu/dts/arm/imx6qdl-gw5910.dtsi
	+++ b/sys/gnu/dts/arm/imx6qdl-gw5910.dtsi
	@@ -1,491 +1,516 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Copyright 2019 Gateworks Corporation
	*/

	#include <dt-bindings/gpio/gpio.h>

	/ {
	/* these are used by bootloader for disabling nodes */
	aliases {
	led0 = &led0;
	led1 = &led1;
	led2 = &led2;
	};

	chosen {
	stdout-path = &uart2;
	};

	memory@10000000 {
	device_type = "memory";
	reg = <0x10000000 0x20000000>;
	};

	leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_leds>;

	led0: user1 {
	label = "user1";
	gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
	default-state = "on";
	linux,default-trigger = "heartbeat";
	};

	led1: user2 {
	label = "user2";
	gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
	default-state = "off";
	};

	led2: user3 {
	label = "user3";
	gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
	default-state = "off";
	};
	};

	pps {
	compatible = "pps-gpio";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pps>;
	gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
	status = "okay";
	};

	reg_3p3v: regulator-3p3v {
	compatible = "regulator-fixed";
	regulator-name = "3P3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_5p0v: regulator-5p0v {
	compatible = "regulator-fixed";
	regulator-name = "5P0V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	reg_wl: regulator-wl {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_reg_wl>;
	compatible = "regulator-fixed";
	regulator-name = "wl";
	gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
	startup-delay-us = <100>;
	enable-active-high;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_bt: regulator-bt {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_reg_bt>;
	compatible = "regulator-fixed";
	regulator-name = "bt";
	gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
	startup-delay-us = <100>;
	enable-active-high;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};
	};


	&ecspi3 {
	cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3>;
	status = "okay";
	};

	&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii-id";
	status = "okay";
	};

	&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	status = "okay";
	};

	&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	gpio@23 {
	compatible = "nxp,pca9555";
	reg = <0x23>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	eeprom@50 {
	compatible = "atmel,24c02";
	reg = <0x50>;
	pagesize = <16>;
	};

	eeprom@51 {
	compatible = "atmel,24c02";
	reg = <0x51>;
	pagesize = <16>;
	};

	eeprom@52 {
	compatible = "atmel,24c02";
	reg = <0x52>;
	pagesize = <16>;
	};

	eeprom@53 {
	compatible = "atmel,24c02";
	reg = <0x53>;
	pagesize = <16>;
	};

	rtc@68 {
	compatible = "dallas,ds1672";
	reg = <0x68>;
	};
	};

	&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
	};

	&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	accel@19 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_accel>;
	compatible = "st,lis2de12";
	reg = <0x19>;
	st,drdy-int-pin = <1>;
	interrupt-parent = <&gpio7>;
	interrupts = <13 0>;
	interrupt-names = "INT1";
	};
	};

	&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
	status = "disabled";
	};

	&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
	status = "disabled";
	};

	/* off-board RS232 */
	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
	};

	/* serial console */
	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
	};

	+/* cc1352 */
	+&uart3 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_uart3>;
	+ uart-has-rtscts;
	+ status = "okay";
	+};
	+
	/* Sterling-LWB Bluetooth */
	&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	uart-has-rtscts;
	status = "okay";
	};

	/* GPS */
	&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	status = "okay";
	};

	&usbotg {
	vbus-supply = <&reg_5p0v>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	disable-over-current;
	status = "okay";
	};

	&usbh1 {
	status = "okay";
	};

	/* Sterling-LWB SDIO WiFi */
	&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	vmmc-supply = <&reg_3p3v>;
	non-removable;
	bus-width = <4>;
	status = "okay";
	};

	&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_3p3v>;
	status = "okay";
	};

	&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	};

	&iomuxc {
	pinctrl_accel: accelmuxgrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
	>;
	};

	pinctrl_ecspi3: escpi3grp {
	fsl,pins = <
	MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
	MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
	MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
	MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
	>;
	};

	pinctrl_enet: enetgrp {
	fsl,pins = <
	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
	MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
	MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
	>;
	};

	pinctrl_gpio_leds: gpioledsgrp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
	MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
	MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
	>;
	};

	pinctrl_gpmi_nand: gpminandgrp {
	fsl,pins = <
	MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
	MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
	MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
	MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
	MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
	MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
	MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
	MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
	MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
	MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
	MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
	MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
	MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
	MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
	MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
	MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
	MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
	MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
	>;
	};

	pinctrl_pcie: pciegrp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
	>;
	};

	pinctrl_pps: ppsgrp {
	fsl,pins = <
	MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1
	>;
	};

	pinctrl_pwm2: pwm2grp {
	fsl,pins = <
	MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm3: pwm3grp {
	fsl,pins = <
	MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
	>;
	};

	pinctrl_reg_bt: regbtgrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
	>;
	};

	pinctrl_reg_wl: regwlgrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
	MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
	MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
	>;
	};

	+ pinctrl_uart3: uart3grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
	+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
	+ MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1
	+ MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
	+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */
	+ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */
	+ MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */
	+ MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */
	+ MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */
	+ MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */
	+ MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */
	+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */
	+ >;
	+ };
	+
	pinctrl_uart4: uart4grp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
	MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
	MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
	MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
	>;
	};

	pinctrl_uart5: uart5grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
	MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_usbotg: usbotggrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
	>;
	};

	pinctrl_usdhc2: usdhc2grp {
	fsl,pins = <
	MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
	MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
	MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
	MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
	MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
	MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
	>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
	>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
	MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
	MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
	>;
	};

	pinctrl_wdog: wdoggrp {
	fsl,pins = <
	MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6qdl-phytec-phycore-som.dtsi b/sys/gnu/dts/arm/imx6qdl-phytec-phycore-som.dtsi
	index 77d871340eb7..41ebe4599e43 100644
	--- a/sys/gnu/dts/arm/imx6qdl-phytec-phycore-som.dtsi
	+++ b/sys/gnu/dts/arm/imx6qdl-phytec-phycore-som.dtsi
	@@ -1,287 +1,290 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (C) 2018 PHYTEC Messtechnik GmbH
	* Author: Christian Hemp <c.hemp@phytec.de>
	*/

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/regulator/dlg,da9063-regulator.h>

	/ {
	aliases {
	rtc1 = &da9062_rtc;
	rtc2 = &snvs_rtc;
	};

	/*
	* Set the minimum memory size here and
	* let the bootloader set the real size.
	*/
	memory@10000000 {
	device_type = "memory";
	reg = <0x10000000 0x8000000>;
	};

	gpio_leds_som: somleds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpioleds_som>;

	som-led-green {
	label = "phycore:green";
	gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	};
	};
	};

	&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
	status = "okay";

	m25p80: flash@0 {
	compatible = "jedec,spi-nor";
	spi-max-frequency = <20000000>;
	reg = <0>;
	status = "disabled";
	};
	};

	&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-handle = <&ethphy>;
	phy-mode = "rgmii";
	phy-supply = <&vdd_eth_io>;
	phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
	status = "disabled";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy: ethernet-phy@3 {
	reg = <3>;
	txc-skew-ps = <1680>;
	rxc-skew-ps = <1860>;
	};
	};
	};

	&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	nand-on-flash-bbt;
	status = "disabled";
	};

	&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	clock-frequency = <400000>;
	status = "okay";

	eeprom@50 {
	compatible = "atmel,24c32";
	reg = <0x50>;
	};

	- pmic@58 {
	+ pmic: pmic@58 {
	compatible = "dlg,da9062";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pmic>;
	reg = <0x58>;
	interrupt-parent = <&gpio1>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;
	+ gpio-controller;
	+ #gpio-cells = <2>;

	da9062_rtc: rtc {
	compatible = "dlg,da9062-rtc";
	};

	da9062_onkey: onkey {
	compatible = "dlg,da9062-onkey";
	};

	watchdog {
	compatible = "dlg,da9062-watchdog";
	+ dlg,use-sw-pm;
	};

	regulators {
	vdd_arm: buck1 {
	regulator-name = "vdd_arm";
	regulator-min-microvolt = <925000>;
	regulator-max-microvolt = <1380000>;
	regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
	regulator-always-on;
	};

	vdd_soc: buck2 {
	regulator-name = "vdd_soc";
	regulator-min-microvolt = <1150000>;
	regulator-max-microvolt = <1380000>;
	regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
	regulator-always-on;
	};

	vdd_ddr3_1p5: buck3 {
	regulator-name = "vdd_ddr3";
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1500000>;
	regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
	regulator-always-on;
	};

	vdd_eth_1p2: buck4 {
	regulator-name = "vdd_eth";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
	regulator-always-on;
	};

	vdd_snvs: ldo1 {
	regulator-name = "vdd_snvs";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;
	};

	vdd_high: ldo2 {
	regulator-name = "vdd_high";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;
	};

	vdd_eth_io: ldo3 {
	regulator-name = "vdd_eth_io";
	regulator-min-microvolt = <2500000>;
	regulator-max-microvolt = <2500000>;
	};

	vdd_emmc_1p8: ldo4 {
	regulator-name = "vdd_emmc";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	};
	};
	};

	&reg_arm {
	vin-supply = <&vdd_arm>;
	};

	&reg_pu {
	vin-supply = <&vdd_soc>;
	};

	&reg_soc {
	vin-supply = <&vdd_soc>;
	};

	&snvs_poweroff {
	status = "okay";
	};

	&usdhc4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4>;
	bus-width = <8>;
	non-removable;
	status = "disabled";
	};

	&iomuxc {
	pinctrl_enet: enetgrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
	MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
	MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
	>;
	};

	pinctrl_gpioleds_som: gpioledssomgrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
	>;
	};

	pinctrl_gpmi_nand: gpminandgrp {
	fsl,pins = <
	MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
	MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
	MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
	MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
	MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
	MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
	MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
	MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
	MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
	MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
	MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
	MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
	MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
	MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
	MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
	MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
	MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
	MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
	MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
	MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
	>;
	};

	pinctrl_ecspi1: ecspi1grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
	MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
	MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
	MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
	>;
	};

	pinctrl_pmic: pmicgrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
	>;
	};

	pinctrl_usdhc4: usdhc4grp {
	fsl,pins = <
	MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
	MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
	MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
	MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
	MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
	MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
	MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
	MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
	MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
	MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6qdl-pico-dwarf.dtsi b/sys/gnu/dts/arm/imx6qdl-pico-dwarf.dtsi
	new file mode 100644
	index 000000000000..3a968782e854
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx6qdl-pico-dwarf.dtsi
	@@ -0,0 +1,45 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	+//
	+// Copyright 2017 NXP
	+
	+#include "imx6qdl-pico.dtsi"
	+
	+/ {
	+ leds {
	+ compatible = "gpio-leds";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_gpio_leds>;
	+
	+ led {
	+ label = "gpio-led";
	+ gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>;
	+ };
	+ };
	+
	+};
	+
	+&i2c1 {
	+ mpl3115@60 {
	+ compatible = "fsl,mpl3115";
	+ reg = <0x60>;
	+ };
	+};
	+
	+&i2c2 {
	+ io-expander@25 {
	+ compatible = "nxp,pca9554";
	+ reg = <0x25>;
	+ gpio-controller;
	+ #gpio-cells = <2>;
	+ #interrupt-cells = <2>;
	+ };
	+
	+};
	+
	+&iomuxc {
	+ pinctrl_gpio_leds: gpioledsgrp {
	+ fsl,pins = <
	+ MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0
	+ >;
	+ };
	+};
	diff --git a/sys/gnu/dts/arm/imx6qdl-pico-hobbit.dtsi b/sys/gnu/dts/arm/imx6qdl-pico-hobbit.dtsi
	new file mode 100644
	index 000000000000..144c4727fbc7
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx6qdl-pico-hobbit.dtsi
	@@ -0,0 +1,37 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	+//
	+// Copyright 2017 NXP
	+
	+#include "imx6qdl-pico.dtsi"
	+
	+/ {
	+ leds {
	+ compatible = "gpio-leds";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_gpio_leds>;
	+
	+ led {
	+ label = "gpio-led";
	+ gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>;
	+ };
	+ };
	+
	+};
	+
	+&i2c2 {
	+ status = "okay";
	+
	+ adc081c: adc@50 {
	+ compatible = "ti,adc081c";
	+ reg = <0x50>;
	+ vref-supply = <&reg_3p3v>;
	+ };
	+};
	+
	+&iomuxc {
	+ pinctrl_gpio_leds: gpioledsgrp {
	+ fsl,pins = <
	+ MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0
	+ >;
	+ };
	+};
	diff --git a/sys/gnu/dts/arm/imx6qdl-pico-nymph.dtsi b/sys/gnu/dts/arm/imx6qdl-pico-nymph.dtsi
	new file mode 100644
	index 000000000000..3d56a4216448
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx6qdl-pico-nymph.dtsi
	@@ -0,0 +1,54 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	+
	+#include "imx6qdl-pico.dtsi"
	+
	+/ {
	+ leds {
	+ compatible = "gpio-leds";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_gpio_leds>;
	+
	+ led {
	+ label = "gpio-led";
	+ gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>;
	+ };
	+ };
	+
	+};
	+
	+&i2c1 {
	+ adc@52 {
	+ compatible = "ti,adc081c";
	+ reg = <0x52>;
	+ vref-supply = <&reg_2p5v>;
	+ };
	+};
	+
	+&i2c2 {
	+ io-expander@25 {
	+ compatible = "nxp,pca9554";
	+ reg = <0x25>;
	+ gpio-controller;
	+ #gpio-cells = <2>;
	+ #interrupt-cells = <2>;
	+ };
	+};
	+
	+&i2c3 {
	+ rtc@68 {
	+ compatible = "dallas,ds1337";
	+ reg = <0x68>;
	+ };
	+};
	+
	+&pcie {
	+ status = "okay";
	+};
	+
	+&iomuxc {
	+ pinctrl_gpio_leds: gpioledsgrp {
	+ fsl,pins = <
	+ MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0
	+ >;
	+ };
	+};
	diff --git a/sys/gnu/dts/arm/imx6qdl-pico-pi.dtsi b/sys/gnu/dts/arm/imx6qdl-pico-pi.dtsi
	new file mode 100644
	index 000000000000..b823dce62e63
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx6qdl-pico-pi.dtsi
	@@ -0,0 +1,31 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	+//
	+// Copyright 2017 NXP
	+
	+#include "imx6qdl-pico.dtsi"
	+
	+/ {
	+ leds {
	+ compatible = "gpio-leds";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_gpio_leds>;
	+
	+ led {
	+ label = "gpio-led";
	+ gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
	+ };
	+ };
	+
	+};
	+
	+&hdmi {
	+ status = "disabled";
	+};
	+
	+&iomuxc {
	+ pinctrl_gpio_leds: gpioledsgrp {
	+ fsl,pins = <
	+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
	+ >;
	+ };
	+};
	diff --git a/sys/gnu/dts/arm/imx6qdl-pico.dtsi b/sys/gnu/dts/arm/imx6qdl-pico.dtsi
	new file mode 100644
	index 000000000000..39dfd90c2c6b
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx6qdl-pico.dtsi
	@@ -0,0 +1,617 @@
	+// SPDX-License-Identifier: GPL-2.0 OR MIT
	+//
	+// Copyright 2018 Technexion Ltd.
	+//
	+// Author: Wig Cheng <wig.cheng@technexion.com>
	+// Richard Hu <richard.hu@technexion.com>
	+// Tapani Utriainen <tapani@technexion.com>
	+
	+#include <dt-bindings/gpio/gpio.h>
	+
	+/ {
	+ chosen {
	+ stdout-path = &uart1;
	+ };
	+
	+ reg_2p5v: regulator-2p5v {
	+ compatible = "regulator-fixed";
	+ regulator-name = "2P5V";
	+ regulator-min-microvolt = <2500000>;
	+ regulator-max-microvolt = <2500000>;
	+ regulator-always-on;
	+ };
	+
	+ reg_3p3v: regulator-3p3v {
	+ compatible = "regulator-fixed";
	+ regulator-name = "3P3V";
	+ regulator-min-microvolt = <3300000>;
	+ regulator-max-microvolt = <3300000>;
	+ regulator-always-on;
	+ };
	+
	+ reg_1p8v: regulator-1p8v {
	+ compatible = "regulator-fixed";
	+ regulator-name = "1P8V";
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+ regulator-always-on;
	+ };
	+
	+ reg_1p5v: regulator-1p5v {
	+ compatible = "regulator-fixed";
	+ regulator-name = "1P5V";
	+ regulator-min-microvolt = <1500000>;
	+ regulator-max-microvolt = <1500000>;
	+ regulator-always-on;
	+ };
	+
	+ reg_2p8v: regulator-2p8v {
	+ compatible = "regulator-fixed";
	+ regulator-name = "2P8V";
	+ regulator-min-microvolt = <2800000>;
	+ regulator-max-microvolt = <2800000>;
	+ regulator-always-on;
	+ };
	+
	+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_usbotg_vbus>;
	+ compatible = "regulator-fixed";
	+ regulator-name = "usb_otg_vbus";
	+ regulator-min-microvolt = <5000000>;
	+ regulator-max-microvolt = <5000000>;
	+ gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
	+ };
	+
	+ codec_osc: clock {
	+ compatible = "fixed-clock";
	+ #clock-cells = <0>;
	+ clock-frequency = <24576000>;
	+ };
	+
	+ sound {
	+ compatible = "fsl,imx-audio-sgtl5000";
	+ model = "imx6-pico-sgtl5000";
	+ ssi-controller = <&ssi1>;
	+ audio-codec = <&sgtl5000>;
	+ audio-routing =
	+ "MIC_IN", "Mic Jack",
	+ "Mic Jack", "Mic Bias",
	+ "Headphone Jack", "HP_OUT";
	+ mux-int-port = <1>;
	+ mux-ext-port = <3>;
	+ };
	+
	+ backlight: backlight {
	+ compatible = "pwm-backlight";
	+ pwms = <&pwm4 0 50000 0>;
	+ brightness-levels = <0 36 72 108 144 180 216 255>;
	+ default-brightness-level = <6>;
	+ status = "okay";
	+ };
	+
	+ reg_lcd_3v3: regulator-lcd-3v3 {
	+ compatible = "regulator-fixed";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_reg_lcd>;
	+ regulator-name = "lcd-3v3";
	+ regulator-min-microvolt = <3300000>;
	+ regulator-max-microvolt = <3300000>;
	+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
	+ enable-active-high;
	+ };
	+
	+ lcd_display: disp0 {
	+ compatible = "fsl,imx-parallel-display";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_ipu1>;
	+ status = "okay";
	+
	+ port@0 {
	+ reg = <0>;
	+
	+ lcd_display_in: endpoint {
	+ remote-endpoint = <&ipu1_di0_disp0>;
	+ };
	+ };
	+
	+ port@1 {
	+ reg = <1>;
	+
	+ lcd_display_out: endpoint {
	+ remote-endpoint = <&lcd_panel_in>;
	+ };
	+ };
	+ };
	+
	+ panel {
	+ compatible = "vxt,vl050-8048nt-c01";
	+ backlight = <&backlight>;
	+ power-supply = <&reg_lcd_3v3>;
	+
	+ port {
	+ lcd_panel_in: endpoint {
	+ remote-endpoint = <&lcd_display_out>;
	+ };
	+ };
	+ };
	+};
	+
	+&audmux {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_audmux>;
	+ status = "okay";
	+};
	+
	+&can1 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_flexcan1>;
	+ status = "okay";
	+};
	+
	+&can2 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_flexcan2>;
	+ status = "okay";
	+};
	+
	+&clks {
	+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
	+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
	+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
	+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
	+};
	+
	+&ecspi2 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_ecspi2>;
	+ cs-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
	+ status = "okay";
	+};
	+
	+&fec {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_enet>;
	+ phy-mode = "rgmii-id";
	+ phy-reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
	+ status = "okay";
	+};
	+
	+&hdmi {
	+ ddc-i2c-bus = <&i2c2>;
	+ status = "okay";
	+};
	+
	+&i2c1 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_i2c1>;
	+ status = "okay";
	+
	+ sgtl5000: audio-codec@a {
	+ #sound-dai-cells = <0>;
	+ reg = <0x0a>;
	+ compatible = "fsl,sgtl5000";
	+ clocks = <&codec_osc>;
	+ VDDA-supply = <&reg_2p5v>;
	+ VDDIO-supply = <&reg_1p8v>;
	+ };
	+};
	+
	+&i2c2 {
	+ clock-frequency = <100000>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_i2c2>;
	+ status = "okay";
	+
	+ touchscreen@38 {
	+ compatible = "edt,edt-ft5x06";
	+ reg = <0x38>;
	+ interrupt-parent = <&gpio5>;
	+ interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
	+ reset-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
	+ touchscreen-size-x = <800>;
	+ touchscreen-size-y = <480>;
	+ wakeup-source;
	+ };
	+
	+ camera@3c {
	+ compatible = "ovti,ov5645";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_ov5645>;
	+ reg = <0x3c>;
	+ clocks = <&clks IMX6QDL_CLK_CKO2>;
	+ clock-names = "xclk";
	+ clock-frequency = <24000000>;
	+ vdddo-supply = <&reg_1p8v>;
	+ vdda-supply = <&reg_2p8v>;
	+ vddd-supply = <&reg_1p5v>;
	+ enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
	+ reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
	+
	+ port {
	+ ov5645_to_mipi_csi2: endpoint {
	+ remote-endpoint = <&mipi_csi2_in>;
	+ clock-lanes = <0>;
	+ data-lanes = <1 2>;
	+ };
	+ };
	+ };
	+};
	+
	+&i2c3 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_i2c3>;
	+ status = "okay";
	+};
	+
	+&ipu1_di0_disp0 {
	+ remote-endpoint = <&lcd_display_in>;
	+};
	+
	+&mipi_csi {
	+ status = "okay";
	+
	+ port@0 {
	+ reg = <0>;
	+
	+ mipi_csi2_in: endpoint {
	+ remote-endpoint = <&ov5645_to_mipi_csi2>;
	+ clock-lanes = <0>;
	+ data-lanes = <1 2>;
	+ };
	+ };
	+};
	+
	+&pcie {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_pcie_reset>;
	+ reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
	+};
	+
	+&pwm1 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_pwm1>;
	+ status = "okay";
	+};
	+
	+&pwm2 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_pwm2>;
	+ status = "okay";
	+};
	+
	+&pwm3 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_pwm3>;
	+ status = "okay";
	+};
	+
	+&pwm4 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_pwm4>;
	+ status = "okay";
	+};
	+
	+&ssi1 {
	+ status = "okay";
	+};
	+
	+&uart1 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_uart1>;
	+ status = "okay";
	+};
	+
	+&uart2 { /* Bluetooth module */
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_uart2>;
	+ uart-has-rtscts;
	+ status = "okay";
	+};
	+
	+&uart3 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_uart3>;
	+ uart-has-rtscts;
	+ status = "okay";
	+};
	+
	+&usbh1 {
	+ status = "okay";
	+};
	+
	+&usbotg {
	+ vbus-supply = <&reg_usb_otg_vbus>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_usbotg>;
	+ disable-over-current;
	+ dr_mode = "otg";
	+ status = "okay";
	+};
	+
	+&usdhc1 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_usdhc1>;
	+ bus-width = <8>;
	+ cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
	+ status = "okay";
	+};
	+
	+&usdhc2 { /* Wifi/BT */
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_usdhc2>;
	+ bus-width = <4>;
	+ no-1-8-v;
	+ keep-power-in-suspend;
	+ non-removable;
	+ status = "okay";
	+};
	+
	+&usdhc3 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_usdhc3>;
	+ bus-width = <8>;
	+ no-1-8-v;
	+ non-removable;
	+ status = "okay";
	+};
	+
	+&iomuxc {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_hog>;
	+
	+ pinctrl_hog: hoggrp {
	+ fsl,pins = <
	+ MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x4001b0b5 /* PICO_P24 */
	+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x4001b0b5 /* PICO_P26 */
	+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b5 /* PICO_P28 */
	+ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b0b5 /* PICO_P30 */
	+ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b0b5 /* PICO_P32 */
	+ MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x4001b0b5 /* PICO_P34 */
	+ MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x4001b0b5 /* PICO_P42 */
	+ MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x4001b0b5 /* PICO_P44 */
	+ MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x4001b0b5 /* PICO_P48 */
	+ >;
	+ };
	+
	+ pinctrl_audmux: audmuxgrp {
	+ fsl,pins = <
	+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
	+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
	+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
	+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
	+ >;
	+ };
	+
	+ pinctrl_ecspi1: ecspi1grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
	+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
	+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
	+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000f0b0
	+ >;
	+ };
	+
	+ pinctrl_ecspi2: ecspi2grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1b0b1
	+ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x1b0b1
	+ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x1b0b1
	+ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000f0b0
	+ MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x000f0b0
	+ >;
	+ };
	+
	+ pinctrl_enet: enetgrp {
	+ fsl,pins = <
	+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
	+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
	+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
	+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
	+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
	+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
	+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
	+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
	+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
	+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
	+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
	+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
	+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
	+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
	+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
	+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1f0b1
	+ >;
	+ };
	+
	+ pinctrl_flexcan1: flexcan1grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
	+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
	+ >;
	+ };
	+
	+ pinctrl_flexcan2: flexcan2grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
	+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
	+ >;
	+ };
	+
	+ pinctrl_i2c1: i2c1grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
	+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
	+ >;
	+ };
	+
	+ pinctrl_i2c2: i2c2grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
	+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	+ >;
	+ };
	+
	+ pinctrl_i2c3: i2c3grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
	+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
	+ >;
	+ };
	+
	+ pinctrl_ipu1: ipu1grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
	+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
	+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
	+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
	+ MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10
	+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
	+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
	+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
	+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
	+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
	+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
	+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
	+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
	+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
	+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
	+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
	+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
	+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
	+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
	+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
	+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
	+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
	+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
	+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
	+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
	+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
	+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
	+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
	+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
	+ >;
	+ };
	+
	+ pinctrl_ov5645: ov5645grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x0b0b0
	+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0
	+ MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0
	+ >;
	+ };
	+
	+ pinctrl_pcie_reset: pciegrp {
	+ fsl,pins = <
	+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x130b0
	+ >;
	+ };
	+
	+ pinctrl_pwm1: pwm1grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
	+ >;
	+ };
	+
	+ pinctrl_pwm2: pwm2grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
	+ >;
	+ };
	+
	+ pinctrl_pwm3: pwm3grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
	+ >;
	+ };
	+
	+ pinctrl_pwm4: pwm4grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
	+ >;
	+ };
	+
	+ pinctrl_reg_lcd: reglcdgrp {
	+ fsl,pins = <
	+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
	+ >;
	+ };
	+
	+ pinctrl_uart1: uart1grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
	+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
	+ >;
	+ };
	+
	+ pinctrl_uart2: uart2grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
	+ MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
	+ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
	+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
	+ >;
	+ };
	+
	+ pinctrl_uart3: uart3grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
	+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
	+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
	+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
	+ >;
	+ };
	+
	+ pinctrl_usbotg: usbotggrp {
	+ fsl,pins = <
	+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
	+ >;
	+ };
	+
	+ pinctrl_usbotg_vbus: usbotgvbusgrp {
	+ fsl,pins = <
	+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
	+ >;
	+ };
	+
	+ pinctrl_usdhc1: usdhc1grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
	+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x17071
	+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
	+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
	+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
	+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
	+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
	+ >;
	+ };
	+
	+ pinctrl_usdhc2: usdhc2grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
	+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
	+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
	+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
	+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
	+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
	+ >;
	+ };
	+
	+ pinctrl_usdhc3: usdhc3grp {
	+ fsl,pins = <
	+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
	+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
	+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
	+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
	+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
	+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
	+ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1
	+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
	+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
	+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
	+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
	+ >;
	+ };
	+};
	diff --git a/sys/gnu/dts/arm/imx6qdl-sr-som-ti.dtsi b/sys/gnu/dts/arm/imx6qdl-sr-som-ti.dtsi
	index 44a97ba93a95..352ac585ca6b 100644
	--- a/sys/gnu/dts/arm/imx6qdl-sr-som-ti.dtsi
	+++ b/sys/gnu/dts/arm/imx6qdl-sr-som-ti.dtsi
	@@ -1,170 +1,171 @@
	/*
	* Copyright (C) 2013,2014 Russell King
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License
	* version 2 as published by the Free Software Foundation.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/
	#include <dt-bindings/gpio/gpio.h>

	/ {
	nvcc_sd1: regulator-nvcc-sd1 {
	compatible = "regulator-fixed";
	regulator-always-on;
	regulator-name = "nvcc_sd1";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vcc_3v3>;
	};

	clk_ti_wifi: ti-wifi-clock {
	/* This is a hack around the kernel - using "fixed clock"
	* results in the "pinctrl" properties being ignored, and
	* the clock not being output. Instead, use a gated clock
	* and the unrouted WL_XTAL_PU gpio.
	*/
	compatible = "gpio-gate-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_microsom_ti_clk>;
	enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
	};

	pwrseq_ti_wifi: ti-wifi-pwrseq {
	compatible = "mmc-pwrseq-simple";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_microsom_ti_wifi_en>;
	reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
	post-power-on-delay-ms = <200>;
	clocks = <&clk_ti_wifi>;
	clock-names = "ext_clock";
	};
	};

	&iomuxc {
	microsom {
	pinctrl_microsom_ti_bt: microsom-ti-bt {
	fsl,pins = <
	/* BT_EN_SOC */
	MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070
	>;
	};

	pinctrl_microsom_ti_clk: microsom-ti-clk {
	fsl,pins = <
	/* EXT_32K */
	MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0
	/* WL_XTAL_PU (unrouted) */
	MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070
	>;
	};

	pinctrl_microsom_ti_wifi_en: microsom-ti-wifi-en {
	fsl,pins = <
	/* WLAN_EN_SOC */
	MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070
	>;
	};

	pinctrl_microsom_ti_wifi_irq: microsom-ti-wifi-irq {
	fsl,pins = <
	/* WLAN_IRQ */
	MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070
	>;
	};

	pinctrl_microsom_uart4: microsom-uart4 {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
	MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
	MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
	MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
	>;
	};

	pinctrl_microsom_usdhc1: microsom-usdhc1 {
	fsl,pins = <
	MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
	MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
	MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
	MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
	MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
	MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
	>;
	};
	};
	};

	/* UART4 - Connected to optional TI Wi-Fi/BT/FM */
	&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_microsom_uart4>;
	uart-has-rtscts;
	status = "okay";

	bluetooth {
	compatible = "ti,wl1837-st";
	clocks = <&clk_ti_wifi>;
	clock-names = "ext_clock";
	enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_microsom_ti_bt>;
	};
	};

	/* USDHC1 - Connected to optional TI Wi-Fi/BT/FM */
	&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_microsom_usdhc1>;
	bus-width = <4>;
	keep-power-in-suspend;
	mmc-pwrseq = <&pwrseq_ti_wifi>;
	+ cap-power-off-card;
	non-removable;
	vmmc-supply = <&vcc_3v3>;
	/* vqmmc-supply = <&nvcc_sd1>; - MMC layer doesn't like it! */
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	wlcore@2 {
	compatible = "ti,wl1837";
	reg = <2>;
	interrupts-extended = <&gpio6 4 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_microsom_ti_wifi_irq>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6qdl-zii-rdu2.dtsi b/sys/gnu/dts/arm/imx6qdl-zii-rdu2.dtsi
	index 0075637f9b0b..20350e803377 100644
	--- a/sys/gnu/dts/arm/imx6qdl-zii-rdu2.dtsi
	+++ b/sys/gnu/dts/arm/imx6qdl-zii-rdu2.dtsi
	@@ -1,1133 +1,1140 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	/*
	* Copyright (C) 2016-2017 Zodiac Inflight Innovations
	*/

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/sound/fsl-imx-audmux.h>

	/ {
	chosen {
	stdout-path = &uart1;
	};

	aliases {
	mdio-gpio0 = &mdio1;
	rtc0 = &ds1341;
	};

	mdio1: mdio {
	compatible = "virtual,mdio-gpio";
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mdio1>;
	gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
	&gpio6 4 GPIO_ACTIVE_HIGH>;

	phy: ethernet-phy@0 {
	pinctrl-0 = <&pinctrl_rmii_phy_irq>;
	pinctrl-names = "default";
	reg = <0>;
	interrupt-parent = <&gpio3>;
	interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
	};
	};

	reg_28p0v: regulator-28p0v {
	compatible = "regulator-fixed";
	regulator-name = "28V_IN";
	regulator-min-microvolt = <28000000>;
	regulator-max-microvolt = <28000000>;
	regulator-always-on;
	};

	reg_12p0v: regulator-12p0v {
	compatible = "regulator-fixed";
	vin-supply = <&reg_28p0v>;
	regulator-name = "12V_MAIN";
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	regulator-always-on;
	};

	reg_5p0v_main: regulator-5p0v-main {
	compatible = "regulator-fixed";
	vin-supply = <&reg_12p0v>;
	regulator-name = "5V_MAIN";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	reg_3p3v_pmic: regulator-3p3v-pmic {
	compatible = "regulator-fixed";
	vin-supply = <&reg_12p0v>;
	regulator-name = "PMIC_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
	compatible = "regulator-fixed";
	vin-supply = <&reg_3p3v_pmic>;
	regulator-name = "GEN_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_3p3v_sd: regulator-3p3v-sd {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
	vin-supply = <&reg_3p3v>;
	regulator-name = "3V3_SD";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
	startup-delay-us = <1000>;
	enable-active-high;
	regulator-always-on;
	};

	reg_3p3v_display: regulator-3p3v-display {
	compatible = "regulator-fixed";
	vin-supply = <&reg_12p0v>;
	regulator-name = "3V3_DISPLAY";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_3p3v_ssd: regulator-3p3v-ssd {
	compatible = "regulator-fixed";
	vin-supply = <&reg_12p0v>;
	regulator-name = "3V3_SSD";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	sound1 {
	compatible = "simple-audio-card";
	simple-audio-card,name = "Front";
	simple-audio-card,format = "i2s";
	simple-audio-card,bitclock-master = <&sound1_codec>;
	simple-audio-card,frame-master = <&sound1_codec>;
	simple-audio-card,widgets =
	"Headphone", "Headphone Jack";
	simple-audio-card,routing =
	"Headphone Jack", "HPLEFT",
	"Headphone Jack", "HPRIGHT",
	"LEFTIN", "HPL",
	"RIGHTIN", "HPR";
	simple-audio-card,aux-devs = <&hpa1>;

	sound1_cpu: simple-audio-card,cpu {
	sound-dai = <&ssi2>;
	};

	sound1_codec: simple-audio-card,codec {
	sound-dai = <&codec1>;
	clocks = <&cs2000>;
	};
	};

	sound2 {
	compatible = "simple-audio-card";
	simple-audio-card,name = "Back";
	simple-audio-card,format = "i2s";
	simple-audio-card,bitclock-master = <&sound2_codec>;
	simple-audio-card,frame-master = <&sound2_codec>;
	simple-audio-card,widgets =
	"Headphone", "Headphone Jack";
	simple-audio-card,routing =
	"Headphone Jack", "HPLEFT",
	"Headphone Jack", "HPRIGHT",
	"LEFTIN", "HPL",
	"RIGHTIN", "HPR";
	simple-audio-card,aux-devs = <&hpa2>;

	sound2_cpu: simple-audio-card,cpu {
	sound-dai = <&ssi1>;
	};

	sound2_codec: simple-audio-card,codec {
	sound-dai = <&codec2>;
	clocks = <&cs2000>;
	};
	};

	panel {
	power-supply = <&reg_3p3v_display>;
	backlight = <&sp_backlight>;
	status = "disabled";

	port {
	panel_in: endpoint {
	remote-endpoint = <&lvds0_out>;
	};
	};
	};

	disp0: disp0 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx-parallel-display";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_disp0>;
	status = "disabled";

	port@0 {
	reg = <0>;

	disp0_in_0: endpoint {
	remote-endpoint = <&ipu1_di0_disp0>;
	};
	};

	port@1 {
	reg = <1>;

	disp0_out: endpoint {
	remote-endpoint = <&tc358767_in>;
	};
	};
	};

	cs2000_ref: cs2000-ref {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24576000>;
	};

	cs2000_in_dummy: cs2000-in-dummy {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	edp_refclk: edp-refclk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <19200000>;
	};
	};

	+&clks {
	+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
	+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
	+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
	+ <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
	+};
	+
	&cpu0 {
	fsl,soc-operating-points = <
	/* ARM kHz SOC-PU uV */
	1200000 1300000
	996000 1275000
	852000 1275000
	792000 1200000
	396000 1200000
	>;
	};

	&reg_arm {
	vin-supply = <&sw1a_reg>;
	};

	&reg_pu {
	vin-supply = <&sw1c_reg>;
	};

	&reg_soc {
	vin-supply = <&sw1c_reg>;
	};

	&ldb {
	lvds-channel@0 {
	port@4 {
	reg = <4>;

	lvds0_out: endpoint {
	remote-endpoint = <&panel_in>;
	};
	};
	};
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
	};

	&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	uart-has-rtscts;
	linux,rs485-enabled-at-boot-time;
	status = "okay";
	};

	&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";

	rave-sp {
	compatible = "zii,rave-sp-rdu2";
	current-speed = <1000000>;
	#address-cells = <1>;
	#size-cells = <1>;

	watchdog {
	compatible = "zii,rave-sp-watchdog";
	};

	sp_backlight: backlight {
	compatible = "zii,rave-sp-backlight";
	};

	pwrbutton {
	compatible = "zii,rave-sp-pwrbutton";
	};

	eeprom@a3 {
	compatible = "zii,rave-sp-eeprom";
	reg = <0xa3 0x4000>;
	#address-cells = <1>;
	#size-cells = <1>;
	zii,eeprom-name = "dds-eeprom";
	};

	eeprom@a4 {
	compatible = "zii,rave-sp-eeprom";
	reg = <0xa4 0x4000>;
	#address-cells = <1>;
	#size-cells = <1>;
	zii,eeprom-name = "main-eeprom";
	};
	};
	};

	&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
	status = "okay";

	flash@0 {
	compatible = "st,m25p128", "jedec,spi-nor";
	spi-max-frequency = <20000000>;
	reg = <0>;
	};
	};

	&gpio3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio3_hog>;

	usb-emulation {
	gpio-hog;
	gpios = <19 GPIO_ACTIVE_HIGH>;
	output-low;
	line-name = "usb-emulation";
	};

	usb-mode1 {
	gpio-hog;
	gpios = <20 GPIO_ACTIVE_HIGH>;
	output-high;
	line-name = "usb-mode1";
	};

	usb-pwr {
	gpio-hog;
	gpios = <22 GPIO_ACTIVE_LOW>;
	output-high;
	line-name = "usb-pwr-ctrl-en-n";
	};

	usb-mode2 {
	gpio-hog;
	gpios = <23 GPIO_ACTIVE_HIGH>;
	output-high;
	line-name = "usb-mode2";
	};
	};

	&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	clock-frequency = <100000>;
	status = "okay";

	codec2: codec@18 {
	compatible = "ti,tlv320dac3100";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_codec2>;
	reg = <0x18>;
	#sound-dai-cells = <0>;
	HPVDD-supply = <&reg_3p3v>;
	SPRVDD-supply = <&reg_3p3v>;
	SPLVDD-supply = <&reg_3p3v>;
	AVDD-supply = <&reg_3p3v>;
	IOVDD-supply = <&reg_3p3v>;
	DVDD-supply = <&vgen4_reg>;
	reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
	};

	accel@1c {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_accel>;
	compatible = "fsl,mma8451";
	reg = <0x1c>;
	interrupt-parent = <&gpio1>;
	interrupt-names = "INT2";
	interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
	vdd-supply = <&reg_3p3v>;
	vddio-supply = <&reg_3p3v>;
	};

	hpa2: amp@60 {
	compatible = "ti,tpa6130a2";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_tpa2>;
	reg = <0x60>;
	power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
	Vdd-supply = <&reg_5p0v_main>;
	};

	edp-bridge@68 {
	compatible = "toshiba,tc358767";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_tc358767>;
	reg = <0x68>;
	shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
	clock-names = "ref";
	clocks = <&edp_refclk>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	reg = <1>;

	tc358767_in: endpoint {
	remote-endpoint = <&disp0_out>;
	};
	};
	};
	};
	};

	&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	clock-frequency = <100000>;
	status = "okay";

	pmic@8 {
	compatible = "fsl,pfuze100";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pfuze100_irq>;
	reg = <0x08>;
	interrupt-parent = <&gpio7>;
	interrupts = <13 IRQ_TYPE_LEVEL_LOW>;

	regulators {
	sw1a_reg: sw1ab {
	regulator-min-microvolt = <300000>;
	regulator-max-microvolt = <1875000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	sw1c_reg: sw1c {
	regulator-min-microvolt = <300000>;
	regulator-max-microvolt = <1875000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	sw2_reg: sw2 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3000000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw3a_reg: sw3a {
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <1500000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw3b_reg: sw3b {
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <1500000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw4_reg: sw4 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	snvs_reg: vsnvs {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <3000000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vref_reg: vrefddr {
	regulator-boot-on;
	regulator-always-on;
	};

	vgen2_reg: vgen2 {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;
	};

	vgen4_reg: vgen4 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	vgen5_reg: vgen5 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2500000>;
	regulator-always-on;
	};

	vgen6_reg: vgen6 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2800000>;
	regulator-always-on;
	};
	};
	};

	watchdog@38 {
	compatible = "zii,rave-wdt";
	reg = <0x38>;
	};

	temp-sense@48 {
	compatible = "national,lm75";
	reg = <0x48>;
	};

	cs2000: clkgen@4e {
	compatible = "cirrus,cs2000-cp";
	reg = <0x4e>;
	#clock-cells = <0>;
	clock-names = "clk_in", "ref_clk";
	clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
	assigned-clocks = <&cs2000>;
	assigned-clock-rates = <24000000>;
	};

	eeprom@54 {
	compatible = "atmel,24c128";
	reg = <0x54>;
	};

	ds1341: rtc@68 {
	compatible = "dallas,ds1341";
	reg = <0x68>;
	};
	};

	&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	clock-frequency = <400000>;
	status = "okay";

	codec1: codec@18 {
	compatible = "ti,tlv320dac3100";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_codec1>;
	reg = <0x18>;
	#sound-dai-cells = <0>;
	HPVDD-supply = <&reg_3p3v>;
	SPRVDD-supply = <&reg_3p3v>;
	SPLVDD-supply = <&reg_3p3v>;
	AVDD-supply = <&reg_3p3v>;
	IOVDD-supply = <&reg_3p3v>;
	DVDD-supply = <&vgen4_reg>;
	reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
	};

	touchscreen@20 {
	compatible = "syna,rmi4-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ts>;
	reg = <0x20>;
	interrupt-parent = <&gpio1>;
	interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
	vdd-supply = <&reg_5p0v_main>;
	vio-supply = <&reg_3p3v>;

	#address-cells = <1>;
	#size-cells = <0>;

	rmi4-f01@1 {
	reg = <0x1>;
	syna,nosleep-mode = <2>;
	};

	rmi4-f11@11 {
	reg = <0x11>;
	touchscreen-inverted-x;
	touchscreen-swapped-x-y;
	syna,sensor-type = <1>;
	};

	rmi4-f12@12 {
	reg = <0x12>;
	touchscreen-inverted-x;
	touchscreen-swapped-x-y;
	syna,sensor-type = <1>;
	};
	};

	touchscreen@2a {
	compatible = "eeti,exc3000";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ts>;
	reg = <0x2a>;
	interrupt-parent = <&gpio1>;
	interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
	touchscreen-inverted-x;
	touchscreen-swapped-x-y;
	status = "disabled";
	};

	reg_5p0v_user_usb: charger@32 {
	compatible = "microchip,ucs1002";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ucs1002_pins>;
	reg = <0x32>;
	interrupts-extended = <&gpio5 2 IRQ_TYPE_EDGE_BOTH>,
	<&gpio3 21 IRQ_TYPE_EDGE_BOTH>;
	interrupt-names = "a_det", "alert";
	};

	hpa1: amp@60 {
	compatible = "ti,tpa6130a2";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_tpa1>;
	reg = <0x60>;
	power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
	Vdd-supply = <&reg_5p0v_main>;
	};
	};

	&ipu1_di0_disp0 {
	remote-endpoint = <&disp0_in_0>;
	};

	&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
	status = "okay";

	host@0 {
	reg = <0 0 0 0 0>;

	#address-cells = <3>;
	#size-cells = <2>;

	i210: i210@0 {
	reg = <0 0 0 0 0>;
	};
	};
	};

	&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	bus-width = <4>;
	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
	disable-wp;
	vmmc-supply = <&reg_3p3v_sd>;
	vqmmc-supply = <&reg_3p3v>;
	no-1-8-v;
	no-sdio;
	status = "okay";
	};

	&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	bus-width = <4>;
	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
	disable-wp;
	vmmc-supply = <&reg_3p3v_sd>;
	vqmmc-supply = <&reg_3p3v>;
	no-1-8-v;
	no-sdio;
	status = "okay";
	};

	&usdhc4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4>;
	bus-width = <8>;
	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_3p3v>;
	no-1-8-v;
	non-removable;
	no-sdio;
	no-sd;
	status = "okay";
	};

	&sata {
	target-supply = <&reg_3p3v_ssd>;
	status = "okay";
	};

	&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rmii";
	phy-handle = <&phy>;
	phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <100>;
	phy-supply = <&reg_3p3v>;
	status = "okay";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	switch: switch@0 {
	compatible = "marvell,mv88e6085";
	pinctrl-0 = <&pinctrl_switch_irq>;
	pinctrl-names = "default";
	reg = <0>;
	dsa,member = <0 0>;
	eeprom-length = <512>;
	interrupt-parent = <&gpio6>;
	interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;
	#interrupt-cells = <2>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	label = "gigabit_proc";
	phy-handle = <&switchphy0>;
	};

	port@1 {
	reg = <1>;
	label = "netaux";
	phy-handle = <&switchphy1>;
	};

	port@2 {
	reg = <2>;
	label = "cpu";
	ethernet = <&fec>;

	fixed-link {
	speed = <100>;
	full-duplex;
	};
	};

	port@3 {
	reg = <3>;
	label = "netright";
	phy-handle = <&switchphy3>;
	};

	port@4 {
	reg = <4>;
	label = "netleft";
	phy-handle = <&switchphy4>;
	};
	};

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	switchphy0: switchphy@0 {
	reg = <0>;
	interrupt-parent = <&switch>;
	interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
	};

	switchphy1: switchphy@1 {
	reg = <1>;
	interrupt-parent = <&switch>;
	interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
	};

	switchphy2: switchphy@2 {
	reg = <2>;
	interrupt-parent = <&switch>;
	interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
	};

	switchphy3: switchphy@3 {
	reg = <3>;
	interrupt-parent = <&switch>;
	interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
	};

	switchphy4: switchphy@4 {
	reg = <4>;
	interrupt-parent = <&switch>;
	interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
	};
	};
	};
	};
	};

	&usbh1 {
	vbus-supply = <&reg_5p0v_main>;
	disable-over-current;
	maximum-speed = "full-speed";
	status = "okay";
	};

	&usbotg {
	vbus-supply = <&reg_5p0v_user_usb>;
	disable-over-current;
	dr_mode = "host";
	status = "okay";
	};

	&snvs_rtc {
	status = "disabled";
	};

	&ssi1 {
	status = "okay";
	};

	&ssi2 {
	status = "okay";
	};

	&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";

	ssi1 {
	fsl,audmux-port = <0>;
	fsl,port-config = <
	(IMX_AUDMUX_V2_PTCR_SYN \|
	IMX_AUDMUX_V2_PTCR_TFSEL(2) \|
	IMX_AUDMUX_V2_PTCR_TCSEL(2) \|
	IMX_AUDMUX_V2_PTCR_TFSDIR \|
	IMX_AUDMUX_V2_PTCR_TCLKDIR)
	IMX_AUDMUX_V2_PDCR_RXDSEL(2)
	>;
	};

	aud3 {
	fsl,audmux-port = <2>;
	fsl,port-config = <
	IMX_AUDMUX_V2_PTCR_SYN
	IMX_AUDMUX_V2_PDCR_RXDSEL(0)
	>;
	};

	ssi2 {
	fsl,audmux-port = <1>;
	fsl,port-config = <
	(IMX_AUDMUX_V2_PTCR_SYN \|
	IMX_AUDMUX_V2_PTCR_TFSEL(4) \|
	IMX_AUDMUX_V2_PTCR_TCSEL(4) \|
	IMX_AUDMUX_V2_PTCR_TFSDIR \|
	IMX_AUDMUX_V2_PTCR_TCLKDIR)
	IMX_AUDMUX_V2_PDCR_RXDSEL(4)
	>;
	};

	aud5 {
	fsl,audmux-port = <4>;
	fsl,port-config = <
	IMX_AUDMUX_V2_PTCR_SYN
	IMX_AUDMUX_V2_PDCR_RXDSEL(1)
	>;
	};
	};

	&wdog1 {
	status = "disabled";
	};

	&iomuxc {
	pinctrl_accel: accelgrp {
	fsl,pins = <
	MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x4001b000
	>;
	};

	pinctrl_audmux: audmuxgrp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
	MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
	MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
	MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
	MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0
	MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
	>;
	};

	pinctrl_codec1: dac1grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x40000038
	>;
	};

	pinctrl_codec2: dac2grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x40000038
	>;
	};

	pinctrl_disp0: disp0grp {
	fsl,pins = <
	MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9
	MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f9
	MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f9
	MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f9
	MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f9
	MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f9
	MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f9
	MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f9
	MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f9
	MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f9
	MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f9
	MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f9
	MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f9
	MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f9
	MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f9
	MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f9
	MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f9
	MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f9
	MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f9
	MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f9
	MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f9
	MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f9
	MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f9
	MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f9
	MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f9
	MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f9
	MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f9
	MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f9
	>;
	};

	pinctrl_ecspi1: ecspi1grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
	MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
	MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
	MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b1
	>;
	};

	pinctrl_enet: enetgrp {
	fsl,pins = <
	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x000b1
	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b1
	MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100f5
	MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100f5
	MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100c0
	MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100c0
	MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100f5
	MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100f5
	MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x40010040
	MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x100b0
	MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
	>;
	};

	pinctrl_gpio3_hog: gpio3hoggrp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
	MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
	MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
	MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
	MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
	MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
	>;
	};

	pinctrl_mdio1: bitbangmdiogrp {
	fsl,pins = <
	/* Bitbang MDIO for DEB Switch */
	MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x4001b030
	MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40018830
	>;
	};

	pinctrl_pcie: pciegrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x10038
	>;
	};

	pinctrl_pfuze100_irq: pfuze100grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x40010000
	>;
	};

	pinctrl_reg_3p3v_sd: mmcsupply1grp {
	fsl,pins = <
	MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x858
	>;
	};

	pinctrl_rmii_phy_irq: phygrp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x40010000
	>;
	};

	pinctrl_switch_irq: switchgrp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x4001b000
	>;
	};

	pinctrl_tc358767: tc358767grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x10
	>;
	};

	pinctrl_tpa1: tpa6130-1grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x40000038
	>;
	};

	pinctrl_tpa2: tpa6130-2grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x40000038
	>;
	};

	pinctrl_ts: tsgrp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
	MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
	MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_uart3: uart3grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
	MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
	MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
	>;
	};

	pinctrl_uart4: uart4grp {
	fsl,pins = <
	MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
	MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
	>;
	};

	pinctrl_ucs1002_pins: ucs1002grp {
	fsl,pins = <
	MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
	MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0
	>;
	};

	pinctrl_usdhc2: usdhc2grp {
	fsl,pins = <
	MX6QDL_PAD_SD2_CMD__SD2_CMD 0x10059
	MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069
	MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
	MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
	MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
	MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
	MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x40010040
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x10059
	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10069
	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
	MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x40010040

	>;
	};

	pinctrl_usdhc4: usdhc4grp {
	fsl,pins = <
	MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
	MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
	MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
	MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
	MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
	MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
	MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
	MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
	MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
	MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
	MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x1b0b1
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6qdl.dtsi b/sys/gnu/dts/arm/imx6qdl.dtsi
	index e6b4b8525f98..98da446aa0f2 100644
	--- a/sys/gnu/dts/arm/imx6qdl.dtsi
	+++ b/sys/gnu/dts/arm/imx6qdl.dtsi
	@@ -1,1367 +1,1373 @@
	// SPDX-License-Identifier: GPL-2.0+
	//
	// Copyright 2011 Freescale Semiconductor, Inc.
	// Copyright 2011 Linaro Ltd.

	#include <dt-bindings/clock/imx6qdl-clock.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	* The decompressor and also some bootloaders rely on a
	* pre-existing /chosen node to be available to insert the
	* command line and merge other ATAGS info.
	*/
	chosen {};

	aliases {
	ethernet0 = &fec;
	can0 = &can1;
	can1 = &can2;
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	gpio3 = &gpio4;
	gpio4 = &gpio5;
	gpio5 = &gpio6;
	gpio6 = &gpio7;
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	i2c2 = &i2c3;
	ipu0 = &ipu1;
	mmc0 = &usdhc1;
	mmc1 = &usdhc2;
	mmc2 = &usdhc3;
	mmc3 = &usdhc4;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	serial4 = &uart5;
	spi0 = &ecspi1;
	spi1 = &ecspi2;
	spi2 = &ecspi3;
	spi3 = &ecspi4;
	usbphy0 = &usbphy1;
	usbphy1 = &usbphy2;
	};

	clocks {
	ckil {
	compatible = "fsl,imx-ckil", "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};

	ckih1 {
	compatible = "fsl,imx-ckih1", "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	osc {
	compatible = "fsl,imx-osc", "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	};
	};

	tempmon: tempmon {
	compatible = "fsl,imx6q-tempmon";
	interrupt-parent = <&gpc>;
	interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
	fsl,tempmon = <&anatop>;
	fsl,tempmon-data = <&ocotp>;
	clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
	#thermal-sensor-cells = <0>;
	};

	ldb: ldb {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
	gpr = <&gpr>;
	status = "disabled";

	lvds-channel@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;
	status = "disabled";

	port@0 {
	reg = <0>;

	lvds0_mux_0: endpoint {
	remote-endpoint = <&ipu1_di0_lvds0>;
	};
	};

	port@1 {
	reg = <1>;

	lvds0_mux_1: endpoint {
	remote-endpoint = <&ipu1_di1_lvds0>;
	};
	};
	};

	lvds-channel@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;
	status = "disabled";

	port@0 {
	reg = <0>;

	lvds1_mux_0: endpoint {
	remote-endpoint = <&ipu1_di0_lvds1>;
	};
	};

	port@1 {
	reg = <1>;

	lvds1_mux_1: endpoint {
	remote-endpoint = <&ipu1_di1_lvds1>;
	};
	};
	};
	};

	pmu: pmu {
	compatible = "arm,cortex-a9-pmu";
	interrupt-parent = <&gpc>;
	interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
	};

	usbphynop1: usbphynop1 {
	compatible = "usb-nop-xceiv";
	#phy-cells = <0>;
	};

	usbphynop2: usbphynop2 {
	compatible = "usb-nop-xceiv";
	#phy-cells = <0>;
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&gpc>;
	ranges;

	dma_apbh: dma-apbh@110000 {
	compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
	reg = <0x00110000 0x2000>;
	interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
	<0 13 IRQ_TYPE_LEVEL_HIGH>,
	<0 13 IRQ_TYPE_LEVEL_HIGH>,
	<0 13 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
	#dma-cells = <1>;
	dma-channels = <4>;
	clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
	};

	gpmi: gpmi-nand@112000 {
	compatible = "fsl,imx6q-gpmi-nand";
	reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
	reg-names = "gpmi-nand", "bch";
	interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "bch";
	clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
	<&clks IMX6QDL_CLK_GPMI_APB>,
	<&clks IMX6QDL_CLK_GPMI_BCH>,
	<&clks IMX6QDL_CLK_GPMI_BCH_APB>,
	<&clks IMX6QDL_CLK_PER1_BCH>;
	clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
	"gpmi_bch_apb", "per1_bch";
	dmas = <&dma_apbh 0>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	hdmi: hdmi@120000 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x00120000 0x9000>;
	interrupts = <0 115 0x04>;
	gpr = <&gpr>;
	clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
	<&clks IMX6QDL_CLK_HDMI_ISFR>;
	clock-names = "iahb", "isfr";
	status = "disabled";

	port@0 {
	reg = <0>;

	hdmi_mux_0: endpoint {
	remote-endpoint = <&ipu1_di0_hdmi>;
	};
	};

	port@1 {
	reg = <1>;

	hdmi_mux_1: endpoint {
	remote-endpoint = <&ipu1_di1_hdmi>;
	};
	};
	};

	gpu_3d: gpu@130000 {
	compatible = "vivante,gc";
	reg = <0x00130000 0x4000>;
	interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
	<&clks IMX6QDL_CLK_GPU3D_CORE>,
	<&clks IMX6QDL_CLK_GPU3D_SHADER>;
	clock-names = "bus", "core", "shader";
	power-domains = <&pd_pu>;
	#cooling-cells = <2>;
	};

	gpu_2d: gpu@134000 {
	compatible = "vivante,gc";
	reg = <0x00134000 0x4000>;
	interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
	<&clks IMX6QDL_CLK_GPU2D_CORE>;
	clock-names = "bus", "core";
	power-domains = <&pd_pu>;
	#cooling-cells = <2>;
	};

	timer@a00600 {
	compatible = "arm,cortex-a9-twd-timer";
	reg = <0x00a00600 0x20>;
	interrupts = <1 13 0xf01>;
	interrupt-parent = <&intc>;
	clocks = <&clks IMX6QDL_CLK_TWD>;
	};

	intc: interrupt-controller@a01000 {
	compatible = "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x00a01000 0x1000>,
	<0x00a00100 0x100>;
	interrupt-parent = <&intc>;
	};

	L2: l2-cache@a02000 {
	compatible = "arm,pl310-cache";
	reg = <0x00a02000 0x1000>;
	interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
	cache-unified;
	cache-level = <2>;
	arm,tag-latency = <4 2 3>;
	arm,data-latency = <4 2 3>;
	arm,shared-override;
	};

	pcie: pcie@1ffc000 {
	compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
	reg = <0x01ffc000 0x04000>,
	<0x01f00000 0x80000>;
	reg-names = "dbi", "config";
	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	bus-range = <0x00 0xff>;
	ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
	0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
	num-lanes = <1>;
	num-viewport = <4>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
	<&clks IMX6QDL_CLK_LVDS1_GATE>,
	<&clks IMX6QDL_CLK_PCIE_REF_125M>;
	clock-names = "pcie", "pcie_bus", "pcie_phy";
	status = "disabled";
	};

	- aips-bus@2000000 { /* AIPS1 */
	+ bus@2000000 { /* AIPS1 */
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02000000 0x100000>;
	ranges;

	spba-bus@2000000 {
	compatible = "fsl,spba-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02000000 0x40000>;
	ranges;

	spdif: spdif@2004000 {
	compatible = "fsl,imx35-spdif";
	reg = <0x02004000 0x4000>;
	interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 14 18 0>,
	<&sdma 15 18 0>;
	dma-names = "rx", "tx";
	clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
	<&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
	<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
	<&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
	<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
	clock-names = "core", "rxtx0",
	"rxtx1", "rxtx2",
	"rxtx3", "rxtx4",
	"rxtx5", "rxtx6",
	"rxtx7", "spba";
	status = "disabled";
	};

	ecspi1: spi@2008000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
	reg = <0x02008000 0x4000>;
	interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_ECSPI1>,
	<&clks IMX6QDL_CLK_ECSPI1>;
	clock-names = "ipg", "per";
	dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	ecspi2: spi@200c000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
	reg = <0x0200c000 0x4000>;
	interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_ECSPI2>,
	<&clks IMX6QDL_CLK_ECSPI2>;
	clock-names = "ipg", "per";
	dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	ecspi3: spi@2010000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
	reg = <0x02010000 0x4000>;
	interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_ECSPI3>,
	<&clks IMX6QDL_CLK_ECSPI3>;
	clock-names = "ipg", "per";
	dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	ecspi4: spi@2014000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
	reg = <0x02014000 0x4000>;
	interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_ECSPI4>,
	<&clks IMX6QDL_CLK_ECSPI4>;
	clock-names = "ipg", "per";
	dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart1: serial@2020000 {
	compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
	reg = <0x02020000 0x4000>;
	interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_UART_IPG>,
	<&clks IMX6QDL_CLK_UART_SERIAL>;
	clock-names = "ipg", "per";
	dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	esai: esai@2024000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx35-esai";
	reg = <0x02024000 0x4000>;
	interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
	<&clks IMX6QDL_CLK_ESAI_MEM>,
	<&clks IMX6QDL_CLK_ESAI_EXTAL>,
	<&clks IMX6QDL_CLK_ESAI_IPG>,
	<&clks IMX6QDL_CLK_SPBA>;
	clock-names = "core", "mem", "extal", "fsys", "spba";
	dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	ssi1: ssi@2028000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx6q-ssi",
	"fsl,imx51-ssi";
	reg = <0x02028000 0x4000>;
	interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
	<&clks IMX6QDL_CLK_SSI1>;
	clock-names = "ipg", "baud";
	dmas = <&sdma 37 1 0>,
	<&sdma 38 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	ssi2: ssi@202c000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx6q-ssi",
	"fsl,imx51-ssi";
	reg = <0x0202c000 0x4000>;
	interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
	<&clks IMX6QDL_CLK_SSI2>;
	clock-names = "ipg", "baud";
	dmas = <&sdma 41 1 0>,
	<&sdma 42 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	ssi3: ssi@2030000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx6q-ssi",
	"fsl,imx51-ssi";
	reg = <0x02030000 0x4000>;
	interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
	<&clks IMX6QDL_CLK_SSI3>;
	clock-names = "ipg", "baud";
	dmas = <&sdma 45 1 0>,
	<&sdma 46 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	asrc: asrc@2034000 {
	compatible = "fsl,imx53-asrc";
	reg = <0x02034000 0x4000>;
	interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
	<&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
	<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
	<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
	<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
	<&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
	<&clks IMX6QDL_CLK_SPBA>;
	clock-names = "mem", "ipg", "asrck_0",
	"asrck_1", "asrck_2", "asrck_3", "asrck_4",
	"asrck_5", "asrck_6", "asrck_7", "asrck_8",
	"asrck_9", "asrck_a", "asrck_b", "asrck_c",
	"asrck_d", "asrck_e", "asrck_f", "spba";
	dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
	<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
	dma-names = "rxa", "rxb", "rxc",
	"txa", "txb", "txc";
	fsl,asrc-rate = <48000>;
	fsl,asrc-width = <16>;
	status = "okay";
	};

	spba@203c000 {
	reg = <0x0203c000 0x4000>;
	};
	};

	vpu: vpu@2040000 {
	compatible = "cnm,coda960";
	reg = <0x02040000 0x3c000>;
	interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
	<0 3 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "bit", "jpeg";
	clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
	<&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
	clock-names = "per", "ahb";
	power-domains = <&pd_pu>;
	resets = <&src 1>;
	iram = <&ocram>;
	};

	aipstz@207c000 { /* AIPSTZ1 */
	reg = <0x0207c000 0x4000>;
	};

	pwm1: pwm@2080000 {
	#pwm-cells = <2>;
	compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
	reg = <0x02080000 0x4000>;
	interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_IPG>,
	<&clks IMX6QDL_CLK_PWM1>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	pwm2: pwm@2084000 {
	#pwm-cells = <2>;
	compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
	reg = <0x02084000 0x4000>;
	interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_IPG>,
	<&clks IMX6QDL_CLK_PWM2>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	pwm3: pwm@2088000 {
	#pwm-cells = <2>;
	compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
	reg = <0x02088000 0x4000>;
	interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_IPG>,
	<&clks IMX6QDL_CLK_PWM3>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	pwm4: pwm@208c000 {
	#pwm-cells = <2>;
	compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
	reg = <0x0208c000 0x4000>;
	interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_IPG>,
	<&clks IMX6QDL_CLK_PWM4>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	can1: flexcan@2090000 {
	compatible = "fsl,imx6q-flexcan";
	reg = <0x02090000 0x4000>;
	interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
	<&clks IMX6QDL_CLK_CAN1_SERIAL>;
	clock-names = "ipg", "per";
	fsl,stop-mode = <&gpr 0x34 28 0x10 17>;
	status = "disabled";
	};

	can2: flexcan@2094000 {
	compatible = "fsl,imx6q-flexcan";
	reg = <0x02094000 0x4000>;
	interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
	<&clks IMX6QDL_CLK_CAN2_SERIAL>;
	clock-names = "ipg", "per";
	fsl,stop-mode = <&gpr 0x34 29 0x10 18>;
	status = "disabled";
	};

	- gpt: gpt@2098000 {
	+ gpt: timer@2098000 {
	compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
	reg = <0x02098000 0x4000>;
	interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
	<&clks IMX6QDL_CLK_GPT_IPG_PER>,
	<&clks IMX6QDL_CLK_GPT_3M>;
	clock-names = "ipg", "per", "osc_per";
	};

	gpio1: gpio@209c000 {
	compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
	reg = <0x0209c000 0x4000>;
	interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
	<0 67 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio@20a0000 {
	compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
	reg = <0x020a0000 0x4000>;
	interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
	<0 69 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio@20a4000 {
	compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
	reg = <0x020a4000 0x4000>;
	interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
	<0 71 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio4: gpio@20a8000 {
	compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
	reg = <0x020a8000 0x4000>;
	interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
	<0 73 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio5: gpio@20ac000 {
	compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
	reg = <0x020ac000 0x4000>;
	interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
	<0 75 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio6: gpio@20b0000 {
	compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
	reg = <0x020b0000 0x4000>;
	interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
	<0 77 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio7: gpio@20b4000 {
	compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
	reg = <0x020b4000 0x4000>;
	interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
	<0 79 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	- kpp: kpp@20b8000 {
	+ kpp: keypad@20b8000 {
	compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
	reg = <0x020b8000 0x4000>;
	interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_IPG>;
	status = "disabled";
	};

	- wdog1: wdog@20bc000 {
	+ wdog1: watchdog@20bc000 {
	compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
	reg = <0x020bc000 0x4000>;
	interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_IPG>;
	};

	- wdog2: wdog@20c0000 {
	+ wdog2: watchdog@20c0000 {
	compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
	reg = <0x020c0000 0x4000>;
	interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_IPG>;
	status = "disabled";
	};

	- clks: ccm@20c4000 {
	+ clks: clock-controller@20c4000 {
	compatible = "fsl,imx6q-ccm";
	reg = <0x020c4000 0x4000>;
	interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
	<0 88 IRQ_TYPE_LEVEL_HIGH>;
	#clock-cells = <1>;
	};

	anatop: anatop@20c8000 {
	compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
	reg = <0x020c8000 0x1000>;
	interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
	<0 54 IRQ_TYPE_LEVEL_HIGH>,
	<0 127 IRQ_TYPE_LEVEL_HIGH>;

	reg_vdd1p1: regulator-1p1 {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vdd1p1";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	anatop-reg-offset = <0x110>;
	anatop-vol-bit-shift = <8>;
	anatop-vol-bit-width = <5>;
	anatop-min-bit-val = <4>;
	anatop-min-voltage = <800000>;
	anatop-max-voltage = <1375000>;
	anatop-enable-bit = <0>;
	};

	reg_vdd3p0: regulator-3p0 {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vdd3p0";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <3150000>;
	regulator-always-on;
	anatop-reg-offset = <0x120>;
	anatop-vol-bit-shift = <8>;
	anatop-vol-bit-width = <5>;
	anatop-min-bit-val = <0>;
	anatop-min-voltage = <2625000>;
	anatop-max-voltage = <3400000>;
	anatop-enable-bit = <0>;
	};

	reg_vdd2p5: regulator-2p5 {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vdd2p5";
	regulator-min-microvolt = <2250000>;
	regulator-max-microvolt = <2750000>;
	regulator-always-on;
	anatop-reg-offset = <0x130>;
	anatop-vol-bit-shift = <8>;
	anatop-vol-bit-width = <5>;
	anatop-min-bit-val = <0>;
	anatop-min-voltage = <2100000>;
	anatop-max-voltage = <2875000>;
	anatop-enable-bit = <0>;
	};

	reg_arm: regulator-vddcore {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vddarm";
	regulator-min-microvolt = <725000>;
	regulator-max-microvolt = <1450000>;
	regulator-always-on;
	anatop-reg-offset = <0x140>;
	anatop-vol-bit-shift = <0>;
	anatop-vol-bit-width = <5>;
	anatop-delay-reg-offset = <0x170>;
	anatop-delay-bit-shift = <24>;
	anatop-delay-bit-width = <2>;
	anatop-min-bit-val = <1>;
	anatop-min-voltage = <725000>;
	anatop-max-voltage = <1450000>;
	};

	reg_pu: regulator-vddpu {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vddpu";
	regulator-min-microvolt = <725000>;
	regulator-max-microvolt = <1450000>;
	regulator-enable-ramp-delay = <150>;
	anatop-reg-offset = <0x140>;
	anatop-vol-bit-shift = <9>;
	anatop-vol-bit-width = <5>;
	anatop-delay-reg-offset = <0x170>;
	anatop-delay-bit-shift = <26>;
	anatop-delay-bit-width = <2>;
	anatop-min-bit-val = <1>;
	anatop-min-voltage = <725000>;
	anatop-max-voltage = <1450000>;
	};

	reg_soc: regulator-vddsoc {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vddsoc";
	regulator-min-microvolt = <725000>;
	regulator-max-microvolt = <1450000>;
	regulator-always-on;
	anatop-reg-offset = <0x140>;
	anatop-vol-bit-shift = <18>;
	anatop-vol-bit-width = <5>;
	anatop-delay-reg-offset = <0x170>;
	anatop-delay-bit-shift = <28>;
	anatop-delay-bit-width = <2>;
	anatop-min-bit-val = <1>;
	anatop-min-voltage = <725000>;
	anatop-max-voltage = <1450000>;
	};
	};

	usbphy1: usbphy@20c9000 {
	compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
	reg = <0x020c9000 0x1000>;
	interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_USBPHY1>;
	fsl,anatop = <&anatop>;
	};

	usbphy2: usbphy@20ca000 {
	compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
	reg = <0x020ca000 0x1000>;
	interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_USBPHY2>;
	fsl,anatop = <&anatop>;
	};

	snvs: snvs@20cc000 {
	compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
	reg = <0x020cc000 0x4000>;

	snvs_rtc: snvs-rtc-lp {
	compatible = "fsl,sec-v4.0-mon-rtc-lp";
	regmap = <&snvs>;
	offset = <0x34>;
	interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
	<0 20 IRQ_TYPE_LEVEL_HIGH>;
	};

	snvs_poweroff: snvs-poweroff {
	compatible = "syscon-poweroff";
	regmap = <&snvs>;
	offset = <0x38>;
	value = <0x60>;
	mask = <0x60>;
	status = "disabled";
	};

	snvs_pwrkey: snvs-powerkey {
	compatible = "fsl,sec-v4.0-pwrkey";
	regmap = <&snvs>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	linux,keycode = <KEY_POWER>;
	wakeup-source;
	status = "disabled";
	};

	snvs_lpgpr: snvs-lpgpr {
	compatible = "fsl,imx6q-snvs-lpgpr";
	};
	};

	epit1: epit@20d0000 { /* EPIT1 */
	reg = <0x020d0000 0x4000>;
	interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
	};

	epit2: epit@20d4000 { /* EPIT2 */
	reg = <0x020d4000 0x4000>;
	interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
	};

	src: src@20d8000 {
	compatible = "fsl,imx6q-src", "fsl,imx51-src";
	reg = <0x020d8000 0x4000>;
	interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
	<0 96 IRQ_TYPE_LEVEL_HIGH>;
	#reset-cells = <1>;
	};

	gpc: gpc@20dc000 {
	compatible = "fsl,imx6q-gpc";
	reg = <0x020dc000 0x4000>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
	<0 90 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-parent = <&intc>;
	clocks = <&clks IMX6QDL_CLK_IPG>;
	clock-names = "ipg";

	pgc {
	#address-cells = <1>;
	#size-cells = <0>;

	power-domain@0 {
	reg = <0>;
	#power-domain-cells = <0>;
	};
	pd_pu: power-domain@1 {
	reg = <1>;
	#power-domain-cells = <0>;
	power-supply = <&reg_pu>;
	clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
	<&clks IMX6QDL_CLK_GPU3D_SHADER>,
	<&clks IMX6QDL_CLK_GPU2D_CORE>,
	<&clks IMX6QDL_CLK_GPU2D_AXI>,
	<&clks IMX6QDL_CLK_OPENVG_AXI>,
	<&clks IMX6QDL_CLK_VPU_AXI>;
	};
	};
	};

	gpr: iomuxc-gpr@20e0000 {
	compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
	reg = <0x20e0000 0x38>;

	mux: mux-controller {
	compatible = "mmio-mux";
	#mux-control-cells = <1>;
	};
	};

	- iomuxc: iomuxc@20e0000 {
	+ iomuxc: pinctrl@20e0000 {
	compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
	reg = <0x20e0000 0x4000>;
	};

	dcic1: dcic@20e4000 {
	reg = <0x020e4000 0x4000>;
	interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
	};

	dcic2: dcic@20e8000 {
	reg = <0x020e8000 0x4000>;
	interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
	};

	sdma: sdma@20ec000 {
	compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
	reg = <0x020ec000 0x4000>;
	interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_IPG>,
	<&clks IMX6QDL_CLK_SDMA>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
	};
	};

	- aips-bus@2100000 { /* AIPS2 */
	+ bus@2100000 { /* AIPS2 */
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02100000 0x100000>;
	ranges;

	- crypto: caam@2100000 {
	+ crypto: crypto@2100000 {
	compatible = "fsl,sec-v4.0";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x2100000 0x10000>;
	ranges = <0 0x2100000 0x10000>;
	clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
	<&clks IMX6QDL_CLK_CAAM_ACLK>,
	<&clks IMX6QDL_CLK_CAAM_IPG>,
	<&clks IMX6QDL_CLK_EIM_SLOW>;
	clock-names = "mem", "aclk", "ipg", "emi_slow";

	- sec_jr0: jr0@1000 {
	+ sec_jr0: jr@1000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x1000 0x1000>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	};

	- sec_jr1: jr1@2000 {
	+ sec_jr1: jr@2000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x2000 0x1000>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	aipstz@217c000 { /* AIPSTZ2 */
	reg = <0x0217c000 0x4000>;
	};

	usbotg: usb@2184000 {
	compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
	reg = <0x02184000 0x200>;
	interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_USBOH3>;
	fsl,usbphy = <&usbphy1>;
	fsl,usbmisc = <&usbmisc 0>;
	ahb-burst-config = <0x0>;
	tx-burst-size-dword = <0x10>;
	rx-burst-size-dword = <0x10>;
	status = "disabled";
	};

	usbh1: usb@2184200 {
	compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
	reg = <0x02184200 0x200>;
	interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_USBOH3>;
	fsl,usbphy = <&usbphy2>;
	fsl,usbmisc = <&usbmisc 1>;
	dr_mode = "host";
	ahb-burst-config = <0x0>;
	tx-burst-size-dword = <0x10>;
	rx-burst-size-dword = <0x10>;
	status = "disabled";
	};

	usbh2: usb@2184400 {
	compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
	reg = <0x02184400 0x200>;
	interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_USBOH3>;
	fsl,usbphy = <&usbphynop1>;
	phy_type = "hsic";
	fsl,usbmisc = <&usbmisc 2>;
	dr_mode = "host";
	ahb-burst-config = <0x0>;
	tx-burst-size-dword = <0x10>;
	rx-burst-size-dword = <0x10>;
	status = "disabled";
	};

	usbh3: usb@2184600 {
	compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
	reg = <0x02184600 0x200>;
	interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_USBOH3>;
	fsl,usbphy = <&usbphynop2>;
	phy_type = "hsic";
	fsl,usbmisc = <&usbmisc 3>;
	dr_mode = "host";
	ahb-burst-config = <0x0>;
	tx-burst-size-dword = <0x10>;
	rx-burst-size-dword = <0x10>;
	status = "disabled";
	};

	usbmisc: usbmisc@2184800 {
	#index-cells = <1>;
	compatible = "fsl,imx6q-usbmisc";
	reg = <0x02184800 0x200>;
	clocks = <&clks IMX6QDL_CLK_USBOH3>;
	};

	fec: ethernet@2188000 {
	compatible = "fsl,imx6q-fec";
	reg = <0x02188000 0x4000>;
	interrupt-names = "int0", "pps";
	- interrupts-extended =
	- <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
	- <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
	+ interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
	+ <0 119 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_ENET>,
	<&clks IMX6QDL_CLK_ENET>,
	<&clks IMX6QDL_CLK_ENET_REF>;
	clock-names = "ipg", "ahb", "ptp";
	+ gpr = <&gpr>;
	status = "disabled";
	};

	mlb@218c000 {
	reg = <0x0218c000 0x4000>;
	interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
	<0 117 IRQ_TYPE_LEVEL_HIGH>,
	<0 126 IRQ_TYPE_LEVEL_HIGH>;
	};

	usdhc1: usdhc@2190000 {
	compatible = "fsl,imx6q-usdhc";
	reg = <0x02190000 0x4000>;
	interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_USDHC1>,
	<&clks IMX6QDL_CLK_USDHC1>,
	<&clks IMX6QDL_CLK_USDHC1>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	usdhc2: usdhc@2194000 {
	compatible = "fsl,imx6q-usdhc";
	reg = <0x02194000 0x4000>;
	interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_USDHC2>,
	<&clks IMX6QDL_CLK_USDHC2>,
	<&clks IMX6QDL_CLK_USDHC2>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	usdhc3: usdhc@2198000 {
	compatible = "fsl,imx6q-usdhc";
	reg = <0x02198000 0x4000>;
	interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_USDHC3>,
	<&clks IMX6QDL_CLK_USDHC3>,
	<&clks IMX6QDL_CLK_USDHC3>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	usdhc4: usdhc@219c000 {
	compatible = "fsl,imx6q-usdhc";
	reg = <0x0219c000 0x4000>;
	interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_USDHC4>,
	<&clks IMX6QDL_CLK_USDHC4>,
	<&clks IMX6QDL_CLK_USDHC4>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	i2c1: i2c@21a0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
	reg = <0x021a0000 0x4000>;
	interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_I2C1>;
	status = "disabled";
	};

	i2c2: i2c@21a4000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
	reg = <0x021a4000 0x4000>;
	interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_I2C2>;
	status = "disabled";
	};

	i2c3: i2c@21a8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
	reg = <0x021a8000 0x4000>;
	interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_I2C3>;
	status = "disabled";
	};

	romcp@21ac000 {
	reg = <0x021ac000 0x4000>;
	};

	mmdc0: memory-controller@21b0000 { /* MMDC0 */
	compatible = "fsl,imx6q-mmdc";
	reg = <0x021b0000 0x4000>;
	clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
	};

	mmdc1: memory-controller@21b4000 { /* MMDC1 */
	compatible = "fsl,imx6q-mmdc";
	reg = <0x021b4000 0x4000>;
	status = "disabled";
	};

	weim: weim@21b8000 {
	#address-cells = <2>;
	#size-cells = <1>;
	compatible = "fsl,imx6q-weim";
	reg = <0x021b8000 0x4000>;
	interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
	fsl,weim-cs-gpr = <&gpr>;
	status = "disabled";
	};

	- ocotp: ocotp@21bc000 {
	+ ocotp: ocotp-ctrl@21bc000 {
	compatible = "fsl,imx6q-ocotp", "syscon";
	reg = <0x021bc000 0x4000>;
	clocks = <&clks IMX6QDL_CLK_IIM>;
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+
	+ cpu_speed_grade: speed-grade@10 {
	+ reg = <0x10 4>;
	+ };
	};

	tzasc@21d0000 { /* TZASC1 */
	reg = <0x021d0000 0x4000>;
	interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
	};

	tzasc@21d4000 { /* TZASC2 */
	reg = <0x021d4000 0x4000>;
	interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
	};

	audmux: audmux@21d8000 {
	compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
	reg = <0x021d8000 0x4000>;
	status = "disabled";
	};

	mipi_csi: mipi@21dc000 {
	compatible = "fsl,imx6-mipi-csi2";
	reg = <0x021dc000 0x4000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 100 0x04>, <0 101 0x04>;
	clocks = <&clks IMX6QDL_CLK_HSI_TX>,
	<&clks IMX6QDL_CLK_VIDEO_27M>,
	<&clks IMX6QDL_CLK_EIM_PODF>;
	clock-names = "dphy", "ref", "pix";
	status = "disabled";
	};

	mipi_dsi: mipi@21e0000 {
	reg = <0x021e0000 0x4000>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	mipi_mux_0: endpoint {
	remote-endpoint = <&ipu1_di0_mipi>;
	};
	};

	port@1 {
	reg = <1>;

	mipi_mux_1: endpoint {
	remote-endpoint = <&ipu1_di1_mipi>;
	};
	};
	};
	};

	vdoa@21e4000 {
	compatible = "fsl,imx6q-vdoa";
	reg = <0x021e4000 0x4000>;
	interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_VDOA>;
	};

	uart2: serial@21e8000 {
	compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
	reg = <0x021e8000 0x4000>;
	interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_UART_IPG>,
	<&clks IMX6QDL_CLK_UART_SERIAL>;
	clock-names = "ipg", "per";
	dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart3: serial@21ec000 {
	compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
	reg = <0x021ec000 0x4000>;
	interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_UART_IPG>,
	<&clks IMX6QDL_CLK_UART_SERIAL>;
	clock-names = "ipg", "per";
	dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart4: serial@21f0000 {
	compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
	reg = <0x021f0000 0x4000>;
	interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_UART_IPG>,
	<&clks IMX6QDL_CLK_UART_SERIAL>;
	clock-names = "ipg", "per";
	dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart5: serial@21f4000 {
	compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
	reg = <0x021f4000 0x4000>;
	interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_UART_IPG>,
	<&clks IMX6QDL_CLK_UART_SERIAL>;
	clock-names = "ipg", "per";
	dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};
	};

	ipu1: ipu@2400000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6q-ipu";
	reg = <0x02400000 0x400000>;
	interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
	<0 5 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_IPU1>,
	<&clks IMX6QDL_CLK_IPU1_DI0>,
	<&clks IMX6QDL_CLK_IPU1_DI1>;
	clock-names = "bus", "di0", "di1";
	resets = <&src 2>;

	ipu1_csi0: port@0 {
	reg = <0>;

	ipu1_csi0_from_ipu1_csi0_mux: endpoint {
	remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
	};
	};

	ipu1_csi1: port@1 {
	reg = <1>;
	};

	ipu1_di0: port@2 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <2>;

	ipu1_di0_disp0: endpoint@0 {
	reg = <0>;
	};

	ipu1_di0_hdmi: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&hdmi_mux_0>;
	};

	ipu1_di0_mipi: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&mipi_mux_0>;
	};

	ipu1_di0_lvds0: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&lvds0_mux_0>;
	};

	ipu1_di0_lvds1: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&lvds1_mux_0>;
	};
	};

	ipu1_di1: port@3 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <3>;

	ipu1_di1_disp1: endpoint@0 {
	reg = <0>;
	};

	ipu1_di1_hdmi: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&hdmi_mux_1>;
	};

	ipu1_di1_mipi: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&mipi_mux_1>;
	};

	ipu1_di1_lvds0: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&lvds0_mux_1>;
	};

	ipu1_di1_lvds1: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&lvds1_mux_1>;
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6qp.dtsi b/sys/gnu/dts/arm/imx6qp.dtsi
	index 5f51f8e5c1fa..b310f13a53f2 100644
	--- a/sys/gnu/dts/arm/imx6qp.dtsi
	+++ b/sys/gnu/dts/arm/imx6qp.dtsi
	@@ -1,115 +1,114 @@
	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	//
	// Copyright 2016 Freescale Semiconductor, Inc.

	#include "imx6q.dtsi"

	/ {
	soc {
	ocram2: sram@940000 {
	compatible = "mmio-sram";
	reg = <0x00940000 0x20000>;
	clocks = <&clks IMX6QDL_CLK_OCRAM>;
	};

	ocram3: sram@960000 {
	compatible = "mmio-sram";
	reg = <0x00960000 0x20000>;
	clocks = <&clks IMX6QDL_CLK_OCRAM>;
	};

	- aips-bus@2100000 {
	+ bus@2100000 {
	pre1: pre@21c8000 {
	compatible = "fsl,imx6qp-pre";
	reg = <0x021c8000 0x1000>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clks IMX6QDL_CLK_PRE0>;
	clock-names = "axi";
	fsl,iram = <&ocram2>;
	};

	pre2: pre@21c9000 {
	compatible = "fsl,imx6qp-pre";
	reg = <0x021c9000 0x1000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clks IMX6QDL_CLK_PRE1>;
	clock-names = "axi";
	fsl,iram = <&ocram2>;
	};

	pre3: pre@21ca000 {
	compatible = "fsl,imx6qp-pre";
	reg = <0x021ca000 0x1000>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clks IMX6QDL_CLK_PRE2>;
	clock-names = "axi";
	fsl,iram = <&ocram3>;
	};

	pre4: pre@21cb000 {
	compatible = "fsl,imx6qp-pre";
	reg = <0x021cb000 0x1000>;
	interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clks IMX6QDL_CLK_PRE3>;
	clock-names = "axi";
	fsl,iram = <&ocram3>;
	};

	prg1: prg@21cc000 {
	compatible = "fsl,imx6qp-prg";
	reg = <0x021cc000 0x1000>;
	clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
	<&clks IMX6QDL_CLK_PRG0_AXI>;
	clock-names = "ipg", "axi";
	fsl,pres = <&pre1>, <&pre2>, <&pre3>;
	};

	prg2: prg@21cd000 {
	compatible = "fsl,imx6qp-prg";
	reg = <0x021cd000 0x1000>;
	clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
	<&clks IMX6QDL_CLK_PRG1_AXI>;
	clock-names = "ipg", "axi";
	fsl,pres = <&pre4>, <&pre2>, <&pre3>;
	};
	};
	};
	};

	&fec {
	- /delete-property/interrupts-extended;
	interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
	<0 119 IRQ_TYPE_LEVEL_HIGH>;
	};

	&gpc {
	compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
	};

	&ipu1 {
	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
	fsl,prg = <&prg1>;
	};

	&ipu2 {
	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
	fsl,prg = <&prg2>;
	};

	&ldb {
	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
	<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
	<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
	<&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
	clock-names = "di0_pll", "di1_pll",
	"di0_sel", "di1_sel", "di2_sel", "di3_sel",
	"di0", "di1";
	};

	&mmdc0 {
	compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
	};

	&pcie {
	compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
	};
	diff --git a/sys/gnu/dts/arm/imx6sl.dtsi b/sys/gnu/dts/arm/imx6sl.dtsi
	index 59c54e6ad09a..8230b45057a1 100644
	--- a/sys/gnu/dts/arm/imx6sl.dtsi
	+++ b/sys/gnu/dts/arm/imx6sl.dtsi
	@@ -1,985 +1,993 @@
	// SPDX-License-Identifier: GPL-2.0
	//
	// Copyright 2013 Freescale Semiconductor, Inc.

	#include <dt-bindings/interrupt-controller/irq.h>
	#include "imx6sl-pinfunc.h"
	#include <dt-bindings/clock/imx6sl-clock.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	* The decompressor and also some bootloaders rely on a
	* pre-existing /chosen node to be available to insert the
	* command line and merge other ATAGS info.
	*/
	chosen {};

	aliases {
	ethernet0 = &fec;
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	gpio3 = &gpio4;
	gpio4 = &gpio5;
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	i2c2 = &i2c3;
	mmc0 = &usdhc1;
	mmc1 = &usdhc2;
	mmc2 = &usdhc3;
	mmc3 = &usdhc4;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	serial4 = &uart5;
	spi0 = &ecspi1;
	spi1 = &ecspi2;
	spi2 = &ecspi3;
	spi3 = &ecspi4;
	usbphy0 = &usbphy1;
	usbphy1 = &usbphy2;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <0x0>;
	next-level-cache = <&L2>;
	operating-points = <
	/* kHz uV */
	996000 1275000
	792000 1175000
	396000 975000
	>;
	fsl,soc-operating-points = <
	/* ARM kHz SOC-PU uV */
	996000 1225000
	792000 1175000
	396000 1175000
	>;
	clock-latency = <61036>; /* two CLK32 periods */
	#cooling-cells = <2>;
	clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
	<&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
	<&clks IMX6SL_CLK_PLL1_SYS>;
	clock-names = "arm", "pll2_pfd2_396m", "step",
	"pll1_sw", "pll1_sys";
	arm-supply = <&reg_arm>;
	pu-supply = <&reg_pu>;
	soc-supply = <&reg_soc>;
	+ nvmem-cells = <&cpu_speed_grade>;
	+ nvmem-cell-names = "speed_grade";
	};
	};

	clocks {
	ckil {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};

	osc {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	};
	};

	tempmon: tempmon {
	compatible = "fsl,imx6q-tempmon";
	interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-parent = <&gpc>;
	fsl,tempmon = <&anatop>;
	fsl,tempmon-data = <&ocotp>;
	clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
	};

	pmu {
	compatible = "arm,cortex-a9-pmu";
	interrupt-parent = <&gpc>;
	interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
	};

	usbphynop1: usbphynop1 {
	compatible = "usb-nop-xceiv";
	#phy-cells = <0>;
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&gpc>;
	ranges;

	ocram: sram@900000 {
	compatible = "mmio-sram";
	reg = <0x00900000 0x20000>;
	clocks = <&clks IMX6SL_CLK_OCRAM>;
	};

	intc: interrupt-controller@a01000 {
	compatible = "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x00a01000 0x1000>,
	<0x00a00100 0x100>;
	interrupt-parent = <&intc>;
	};

	L2: l2-cache@a02000 {
	compatible = "arm,pl310-cache";
	reg = <0x00a02000 0x1000>;
	interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
	cache-unified;
	cache-level = <2>;
	arm,tag-latency = <4 2 3>;
	arm,data-latency = <4 2 3>;
	};

	- aips1: aips-bus@2000000 {
	+ aips1: bus@2000000 {
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02000000 0x100000>;
	ranges;

	spba: spba-bus@2000000 {
	compatible = "fsl,spba-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02000000 0x40000>;
	ranges;

	spdif: spdif@2004000 {
	compatible = "fsl,imx6sl-spdif",
	"fsl,imx35-spdif";
	reg = <0x02004000 0x4000>;
	interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 14 18 0>,
	<&sdma 15 18 0>;
	dma-names = "rx", "tx";
	clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
	<&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
	<&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
	<&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
	<&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
	clock-names = "core", "rxtx0",
	"rxtx1", "rxtx2",
	"rxtx3", "rxtx4",
	"rxtx5", "rxtx6",
	"rxtx7", "spba";
	status = "disabled";
	};

	ecspi1: spi@2008000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
	reg = <0x02008000 0x4000>;
	interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_ECSPI1>,
	<&clks IMX6SL_CLK_ECSPI1>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ecspi2: spi@200c000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
	reg = <0x0200c000 0x4000>;
	interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_ECSPI2>,
	<&clks IMX6SL_CLK_ECSPI2>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ecspi3: spi@2010000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
	reg = <0x02010000 0x4000>;
	interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_ECSPI3>,
	<&clks IMX6SL_CLK_ECSPI3>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ecspi4: spi@2014000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
	reg = <0x02014000 0x4000>;
	interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_ECSPI4>,
	<&clks IMX6SL_CLK_ECSPI4>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart5: serial@2018000 {
	compatible = "fsl,imx6sl-uart",
	"fsl,imx6q-uart", "fsl,imx21-uart";
	reg = <0x02018000 0x4000>;
	interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_UART>,
	<&clks IMX6SL_CLK_UART_SERIAL>;
	clock-names = "ipg", "per";
	dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart1: serial@2020000 {
	compatible = "fsl,imx6sl-uart",
	"fsl,imx6q-uart", "fsl,imx21-uart";
	reg = <0x02020000 0x4000>;
	interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_UART>,
	<&clks IMX6SL_CLK_UART_SERIAL>;
	clock-names = "ipg", "per";
	dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart2: serial@2024000 {
	compatible = "fsl,imx6sl-uart",
	"fsl,imx6q-uart", "fsl,imx21-uart";
	reg = <0x02024000 0x4000>;
	interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_UART>,
	<&clks IMX6SL_CLK_UART_SERIAL>;
	clock-names = "ipg", "per";
	dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	ssi1: ssi@2028000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx6sl-ssi",
	"fsl,imx51-ssi";
	reg = <0x02028000 0x4000>;
	interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
	<&clks IMX6SL_CLK_SSI1>;
	clock-names = "ipg", "baud";
	dmas = <&sdma 37 1 0>,
	<&sdma 38 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	ssi2: ssi@202c000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx6sl-ssi",
	"fsl,imx51-ssi";
	reg = <0x0202c000 0x4000>;
	interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
	<&clks IMX6SL_CLK_SSI2>;
	clock-names = "ipg", "baud";
	dmas = <&sdma 41 1 0>,
	<&sdma 42 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	ssi3: ssi@2030000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx6sl-ssi",
	"fsl,imx51-ssi";
	reg = <0x02030000 0x4000>;
	interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
	<&clks IMX6SL_CLK_SSI3>;
	clock-names = "ipg", "baud";
	dmas = <&sdma 45 1 0>,
	<&sdma 46 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	uart3: serial@2034000 {
	compatible = "fsl,imx6sl-uart",
	"fsl,imx6q-uart", "fsl,imx21-uart";
	reg = <0x02034000 0x4000>;
	interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_UART>,
	<&clks IMX6SL_CLK_UART_SERIAL>;
	clock-names = "ipg", "per";
	dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart4: serial@2038000 {
	compatible = "fsl,imx6sl-uart",
	"fsl,imx6q-uart", "fsl,imx21-uart";
	reg = <0x02038000 0x4000>;
	interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_UART>,
	<&clks IMX6SL_CLK_UART_SERIAL>;
	clock-names = "ipg", "per";
	dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};
	};

	pwm1: pwm@2080000 {
	#pwm-cells = <2>;
	compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
	reg = <0x02080000 0x4000>;
	interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_PERCLK>,
	<&clks IMX6SL_CLK_PWM1>;
	clock-names = "ipg", "per";
	};

	pwm2: pwm@2084000 {
	#pwm-cells = <2>;
	compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
	reg = <0x02084000 0x4000>;
	interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_PERCLK>,
	<&clks IMX6SL_CLK_PWM2>;
	clock-names = "ipg", "per";
	};

	pwm3: pwm@2088000 {
	#pwm-cells = <2>;
	compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
	reg = <0x02088000 0x4000>;
	interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_PERCLK>,
	<&clks IMX6SL_CLK_PWM3>;
	clock-names = "ipg", "per";
	};

	pwm4: pwm@208c000 {
	#pwm-cells = <2>;
	compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
	reg = <0x0208c000 0x4000>;
	interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_PERCLK>,
	<&clks IMX6SL_CLK_PWM4>;
	clock-names = "ipg", "per";
	};

	- gpt: gpt@2098000 {
	+ gpt: timer@2098000 {
	compatible = "fsl,imx6sl-gpt";
	reg = <0x02098000 0x4000>;
	interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_GPT>,
	<&clks IMX6SL_CLK_GPT_SERIAL>;
	clock-names = "ipg", "per";
	};

	gpio1: gpio@209c000 {
	compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
	reg = <0x0209c000 0x4000>;
	interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
	<0 67 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
	<&iomuxc 3 23 1>, <&iomuxc 4 25 1>,
	<&iomuxc 5 24 1>, <&iomuxc 6 19 1>,
	<&iomuxc 7 36 2>, <&iomuxc 9 44 8>,
	<&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
	<&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
	};

	gpio2: gpio@20a0000 {
	compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
	reg = <0x020a0000 0x4000>;
	interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
	<0 69 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
	<&iomuxc 5 34 2>, <&iomuxc 7 57 4>,
	<&iomuxc 11 56 1>, <&iomuxc 12 61 3>,
	<&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
	<&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
	<&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
	<&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
	};

	gpio3: gpio@20a4000 {
	compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
	reg = <0x020a4000 0x4000>;
	interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
	<0 71 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
	<&iomuxc 12 97 4>, <&iomuxc 16 166 3>,
	<&iomuxc 19 85 2>, <&iomuxc 21 137 2>,
	<&iomuxc 23 136 1>, <&iomuxc 24 91 1>,
	<&iomuxc 25 99 1>, <&iomuxc 26 92 1>,
	<&iomuxc 27 100 1>, <&iomuxc 28 93 1>,
	<&iomuxc 29 101 1>, <&iomuxc 30 94 1>,
	<&iomuxc 31 102 1>;
	};

	gpio4: gpio@20a8000 {
	compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
	reg = <0x020a8000 0x4000>;
	interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
	<0 73 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
	<&iomuxc 2 96 1>, <&iomuxc 3 104 1>,
	<&iomuxc 4 97 1>, <&iomuxc 5 105 1>,
	<&iomuxc 6 98 1>, <&iomuxc 7 106 1>,
	<&iomuxc 8 28 1>, <&iomuxc 9 27 1>,
	<&iomuxc 10 26 1>, <&iomuxc 11 29 1>,
	<&iomuxc 12 32 1>, <&iomuxc 13 31 1>,
	<&iomuxc 14 30 1>, <&iomuxc 15 33 1>,
	<&iomuxc 16 84 1>, <&iomuxc 17 79 2>,
	<&iomuxc 19 78 1>, <&iomuxc 20 76 1>,
	<&iomuxc 21 81 2>, <&iomuxc 23 75 1>,
	<&iomuxc 24 83 1>, <&iomuxc 25 74 1>,
	<&iomuxc 26 77 1>, <&iomuxc 27 159 1>,
	<&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
	<&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
	};

	gpio5: gpio@20ac000 {
	compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
	reg = <0x020ac000 0x4000>;
	interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
	<0 75 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
	<&iomuxc 2 155 1>, <&iomuxc 3 153 1>,
	<&iomuxc 4 150 1>, <&iomuxc 5 149 1>,
	<&iomuxc 6 144 1>, <&iomuxc 7 147 1>,
	<&iomuxc 8 142 1>, <&iomuxc 9 146 1>,
	<&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
	<&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
	<&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
	<&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
	<&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
	<&iomuxc 21 161 1>;
	};

	- kpp: kpp@20b8000 {
	+ kpp: keypad@20b8000 {
	compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
	reg = <0x020b8000 0x4000>;
	interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_IPG>;
	status = "disabled";
	};

	- wdog1: wdog@20bc000 {
	+ wdog1: watchdog@20bc000 {
	compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
	reg = <0x020bc000 0x4000>;
	interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_IPG>;
	};

	- wdog2: wdog@20c0000 {
	+ wdog2: watchdog@20c0000 {
	compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
	reg = <0x020c0000 0x4000>;
	interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_IPG>;
	status = "disabled";
	};

	- clks: ccm@20c4000 {
	+ clks: clock-controller@20c4000 {
	compatible = "fsl,imx6sl-ccm";
	reg = <0x020c4000 0x4000>;
	interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
	<0 88 IRQ_TYPE_LEVEL_HIGH>;
	#clock-cells = <1>;
	};

	anatop: anatop@20c8000 {
	compatible = "fsl,imx6sl-anatop",
	"fsl,imx6q-anatop",
	"syscon", "simple-mfd";
	reg = <0x020c8000 0x1000>;
	interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
	<0 54 IRQ_TYPE_LEVEL_HIGH>,
	<0 127 IRQ_TYPE_LEVEL_HIGH>;

	reg_vdd1p1: regulator-1p1 {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vdd1p1";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	anatop-reg-offset = <0x110>;
	anatop-vol-bit-shift = <8>;
	anatop-vol-bit-width = <5>;
	anatop-min-bit-val = <4>;
	anatop-min-voltage = <800000>;
	anatop-max-voltage = <1375000>;
	anatop-enable-bit = <0>;
	};

	reg_vdd3p0: regulator-3p0 {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vdd3p0";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <3150000>;
	regulator-always-on;
	anatop-reg-offset = <0x120>;
	anatop-vol-bit-shift = <8>;
	anatop-vol-bit-width = <5>;
	anatop-min-bit-val = <0>;
	anatop-min-voltage = <2625000>;
	anatop-max-voltage = <3400000>;
	anatop-enable-bit = <0>;
	};

	reg_vdd2p5: regulator-2p5 {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vdd2p5";
	regulator-min-microvolt = <2250000>;
	regulator-max-microvolt = <2750000>;
	regulator-always-on;
	anatop-reg-offset = <0x130>;
	anatop-vol-bit-shift = <8>;
	anatop-vol-bit-width = <5>;
	anatop-min-bit-val = <0>;
	anatop-min-voltage = <2100000>;
	anatop-max-voltage = <2850000>;
	anatop-enable-bit = <0>;
	};

	reg_arm: regulator-vddcore {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vddarm";
	regulator-min-microvolt = <725000>;
	regulator-max-microvolt = <1450000>;
	regulator-always-on;
	anatop-reg-offset = <0x140>;
	anatop-vol-bit-shift = <0>;
	anatop-vol-bit-width = <5>;
	anatop-delay-reg-offset = <0x170>;
	anatop-delay-bit-shift = <24>;
	anatop-delay-bit-width = <2>;
	anatop-min-bit-val = <1>;
	anatop-min-voltage = <725000>;
	anatop-max-voltage = <1450000>;
	};

	reg_pu: regulator-vddpu {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vddpu";
	regulator-min-microvolt = <725000>;
	regulator-max-microvolt = <1450000>;
	anatop-reg-offset = <0x140>;
	anatop-vol-bit-shift = <9>;
	anatop-vol-bit-width = <5>;
	anatop-delay-reg-offset = <0x170>;
	anatop-delay-bit-shift = <26>;
	anatop-delay-bit-width = <2>;
	anatop-min-bit-val = <1>;
	anatop-min-voltage = <725000>;
	anatop-max-voltage = <1450000>;
	};

	reg_soc: regulator-vddsoc {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vddsoc";
	regulator-min-microvolt = <725000>;
	regulator-max-microvolt = <1450000>;
	regulator-always-on;
	anatop-reg-offset = <0x140>;
	anatop-vol-bit-shift = <18>;
	anatop-vol-bit-width = <5>;
	anatop-delay-reg-offset = <0x170>;
	anatop-delay-bit-shift = <28>;
	anatop-delay-bit-width = <2>;
	anatop-min-bit-val = <1>;
	anatop-min-voltage = <725000>;
	anatop-max-voltage = <1450000>;
	};
	};

	usbphy1: usbphy@20c9000 {
	compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
	reg = <0x020c9000 0x1000>;
	interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_USBPHY1>;
	fsl,anatop = <&anatop>;
	};

	usbphy2: usbphy@20ca000 {
	compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
	reg = <0x020ca000 0x1000>;
	interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_USBPHY2>;
	fsl,anatop = <&anatop>;
	};

	snvs: snvs@20cc000 {
	compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
	reg = <0x020cc000 0x4000>;

	snvs_rtc: snvs-rtc-lp {
	compatible = "fsl,sec-v4.0-mon-rtc-lp";
	regmap = <&snvs>;
	offset = <0x34>;
	interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
	<0 20 IRQ_TYPE_LEVEL_HIGH>;
	};

	snvs_poweroff: snvs-poweroff {
	compatible = "syscon-poweroff";
	regmap = <&snvs>;
	offset = <0x38>;
	value = <0x60>;
	mask = <0x60>;
	status = "disabled";
	};
	};

	epit1: epit@20d0000 {
	reg = <0x020d0000 0x4000>;
	interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
	};

	epit2: epit@20d4000 {
	reg = <0x020d4000 0x4000>;
	interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
	};

	src: src@20d8000 {
	compatible = "fsl,imx6sl-src", "fsl,imx51-src";
	reg = <0x020d8000 0x4000>;
	interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
	<0 96 IRQ_TYPE_LEVEL_HIGH>;
	#reset-cells = <1>;
	};

	gpc: gpc@20dc000 {
	compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
	reg = <0x020dc000 0x4000>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-parent = <&intc>;
	clocks = <&clks IMX6SL_CLK_IPG>;
	clock-names = "ipg";

	pgc {
	#address-cells = <1>;
	#size-cells = <0>;

	power-domain@0 {
	reg = <0>;
	#power-domain-cells = <0>;
	};

	pd_pu: power-domain@1 {
	reg = <1>;
	#power-domain-cells = <0>;
	power-supply = <&reg_pu>;
	clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
	<&clks IMX6SL_CLK_GPU2D_PODF>;
	};

	pd_disp: power-domain@2 {
	reg = <2>;
	#power-domain-cells = <0>;
	clocks = <&clks IMX6SL_CLK_LCDIF_AXI>,
	<&clks IMX6SL_CLK_LCDIF_PIX>,
	<&clks IMX6SL_CLK_EPDC_AXI>,
	<&clks IMX6SL_CLK_EPDC_PIX>,
	<&clks IMX6SL_CLK_PXP_AXI>;
	};
	};
	};

	gpr: iomuxc-gpr@20e0000 {
	compatible = "fsl,imx6sl-iomuxc-gpr",
	"fsl,imx6q-iomuxc-gpr", "syscon";
	reg = <0x020e0000 0x38>;
	};

	- iomuxc: iomuxc@20e0000 {
	+ iomuxc: pinctrl@20e0000 {
	compatible = "fsl,imx6sl-iomuxc";
	reg = <0x020e0000 0x4000>;
	};

	csi: csi@20e4000 {
	reg = <0x020e4000 0x4000>;
	interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	spdc: spdc@20e8000 {
	reg = <0x020e8000 0x4000>;
	interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
	};

	sdma: sdma@20ec000 {
	compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
	reg = <0x020ec000 0x4000>;
	interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_SDMA>,
	<&clks IMX6SL_CLK_AHB>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	/* imx6sl reuses imx6q sdma firmware */
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
	};

	pxp: pxp@20f0000 {
	reg = <0x020f0000 0x4000>;
	interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
	};

	epdc: epdc@20f4000 {
	reg = <0x020f4000 0x4000>;
	interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
	};

	lcdif: lcdif@20f8000 {
	compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
	reg = <0x020f8000 0x4000>;
	interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
	<&clks IMX6SL_CLK_LCDIF_AXI>,
	<&clks IMX6SL_CLK_DUMMY>;
	clock-names = "pix", "axi", "disp_axi";
	status = "disabled";
	power-domains = <&pd_disp>;
	};

	- dcp: dcp@20fc000 {
	+ dcp: crypto@20fc000 {
	compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
	reg = <0x020fc000 0x4000>;
	interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
	<0 100 IRQ_TYPE_LEVEL_HIGH>,
	<0 101 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	- aips2: aips-bus@2100000 {
	+ aips2: bus@2100000 {
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02100000 0x100000>;
	ranges;

	usbotg1: usb@2184000 {
	compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
	reg = <0x02184000 0x200>;
	interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_USBOH3>;
	fsl,usbphy = <&usbphy1>;
	fsl,usbmisc = <&usbmisc 0>;
	ahb-burst-config = <0x0>;
	tx-burst-size-dword = <0x10>;
	rx-burst-size-dword = <0x10>;
	status = "disabled";
	};

	usbotg2: usb@2184200 {
	compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
	reg = <0x02184200 0x200>;
	interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_USBOH3>;
	fsl,usbphy = <&usbphy2>;
	fsl,usbmisc = <&usbmisc 1>;
	ahb-burst-config = <0x0>;
	tx-burst-size-dword = <0x10>;
	rx-burst-size-dword = <0x10>;
	status = "disabled";
	};

	usbh: usb@2184400 {
	compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
	reg = <0x02184400 0x200>;
	interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_USBOH3>;
	fsl,usbphy = <&usbphynop1>;
	phy_type = "hsic";
	fsl,usbmisc = <&usbmisc 2>;
	dr_mode = "host";
	ahb-burst-config = <0x0>;
	tx-burst-size-dword = <0x10>;
	rx-burst-size-dword = <0x10>;
	status = "disabled";
	};

	usbmisc: usbmisc@2184800 {
	#index-cells = <1>;
	compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
	reg = <0x02184800 0x200>;
	clocks = <&clks IMX6SL_CLK_USBOH3>;
	};

	fec: ethernet@2188000 {
	compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
	reg = <0x02188000 0x4000>;
	interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_ENET>,
	<&clks IMX6SL_CLK_ENET_REF>;
	clock-names = "ipg", "ahb";
	status = "disabled";
	};

	usdhc1: usdhc@2190000 {
	compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
	reg = <0x02190000 0x4000>;
	interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_USDHC1>,
	<&clks IMX6SL_CLK_USDHC1>,
	<&clks IMX6SL_CLK_USDHC1>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	usdhc2: usdhc@2194000 {
	compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
	reg = <0x02194000 0x4000>;
	interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_USDHC2>,
	<&clks IMX6SL_CLK_USDHC2>,
	<&clks IMX6SL_CLK_USDHC2>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	usdhc3: usdhc@2198000 {
	compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
	reg = <0x02198000 0x4000>;
	interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_USDHC3>,
	<&clks IMX6SL_CLK_USDHC3>,
	<&clks IMX6SL_CLK_USDHC3>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	usdhc4: usdhc@219c000 {
	compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
	reg = <0x0219c000 0x4000>;
	interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_USDHC4>,
	<&clks IMX6SL_CLK_USDHC4>,
	<&clks IMX6SL_CLK_USDHC4>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	i2c1: i2c@21a0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
	reg = <0x021a0000 0x4000>;
	interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_I2C1>;
	status = "disabled";
	};

	i2c2: i2c@21a4000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
	reg = <0x021a4000 0x4000>;
	interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_I2C2>;
	status = "disabled";
	};

	i2c3: i2c@21a8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
	reg = <0x021a8000 0x4000>;
	interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_I2C3>;
	status = "disabled";
	};

	memory-controller@21b0000 {
	compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
	reg = <0x021b0000 0x4000>;
	clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
	};

	rngb: rngb@21b4000 {
	reg = <0x021b4000 0x4000>;
	interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
	};

	weim: weim@21b8000 {
	#address-cells = <2>;
	#size-cells = <1>;
	reg = <0x021b8000 0x4000>;
	interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
	fsl,weim-cs-gpr = <&gpr>;
	status = "disabled";
	};

	- ocotp: ocotp@21bc000 {
	+ ocotp: ocotp-ctrl@21bc000 {
	compatible = "fsl,imx6sl-ocotp", "syscon";
	reg = <0x021bc000 0x4000>;
	clocks = <&clks IMX6SL_CLK_OCOTP>;
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+
	+ cpu_speed_grade: speed-grade@10 {
	+ reg = <0x10 4>;
	+ };
	};

	audmux: audmux@21d8000 {
	compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
	reg = <0x021d8000 0x4000>;
	status = "disabled";
	};
	};

	gpu_2d: gpu@2200000 {
	compatible = "vivante,gc";
	reg = <0x02200000 0x4000>;
	interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
	<&clks IMX6SL_CLK_GPU2D_OVG>;
	clock-names = "bus", "core";
	power-domains = <&pd_pu>;
	};

	gpu_vg: gpu@2204000 {
	compatible = "vivante,gc";
	reg = <0x02204000 0x4000>;
	interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
	<&clks IMX6SL_CLK_GPU2D_OVG>;
	clock-names = "bus", "core";
	power-domains = <&pd_pu>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6sll.dtsi b/sys/gnu/dts/arm/imx6sll.dtsi
	index a1bc5bb31756..edd3abb9a9f1 100644
	--- a/sys/gnu/dts/arm/imx6sll.dtsi
	+++ b/sys/gnu/dts/arm/imx6sll.dtsi
	@@ -1,823 +1,829 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	/*
	* Copyright 2016 Freescale Semiconductor, Inc.
	* Copyright 2017-2018 NXP.
	*
	*/

	#include <dt-bindings/clock/imx6sll-clock.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include "imx6sll-pinfunc.h"

	/ {
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	gpio3 = &gpio4;
	gpio4 = &gpio5;
	gpio5 = &gpio6;
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	i2c2 = &i2c3;
	mmc0 = &usdhc1;
	mmc1 = &usdhc2;
	mmc2 = &usdhc3;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	serial4 = &uart5;
	spi0 = &ecspi1;
	spi1 = &ecspi2;
	spi3 = &ecspi3;
	spi4 = &ecspi4;
	usbphy0 = &usbphy1;
	usbphy1 = &usbphy2;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <0>;
	next-level-cache = <&L2>;
	operating-points = <
	/* kHz uV */
	996000 1275000
	792000 1175000
	396000 1075000
	198000 975000
	>;
	fsl,soc-operating-points = <
	/* ARM kHz SOC-PU uV */
	996000 1175000
	792000 1175000
	396000 1175000
	198000 1175000
	>;
	clock-latency = <61036>; /* two CLK32 periods */
	#cooling-cells = <2>;
	clocks = <&clks IMX6SLL_CLK_ARM>,
	<&clks IMX6SLL_CLK_PLL2_PFD2>,
	<&clks IMX6SLL_CLK_STEP>,
	<&clks IMX6SLL_CLK_PLL1_SW>,
	<&clks IMX6SLL_CLK_PLL1_SYS>;
	clock-names = "arm", "pll2_pfd2_396m", "step",
	"pll1_sw", "pll1_sys";
	+ nvmem-cells = <&cpu_speed_grade>;
	+ nvmem-cell-names = "speed_grade";
	};
	};

	ckil: clock-ckil {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "ckil";
	};

	osc: clock-osc-24m {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "osc";
	};

	ipp_di0: clock-ipp-di0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	clock-output-names = "ipp_di0";
	};

	ipp_di1: clock-ipp-di1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	clock-output-names = "ipp_di1";
	};

	tempmon: temperature-sensor {
	compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-parent = <&gpc>;
	fsl,tempmon = <&anatop>;
	nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
	nvmem-cell-names = "calib", "temp_grade";
	clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&gpc>;
	ranges;

	ocram: sram@900000 {
	compatible = "mmio-sram";
	reg = <0x00900000 0x20000>;
	};

	intc: interrupt-controller@a01000 {
	compatible = "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x00a01000 0x1000>,
	<0x00a00100 0x100>;
	interrupt-parent = <&intc>;
	};

	L2: l2-cache@a02000 {
	compatible = "arm,pl310-cache";
	reg = <0x00a02000 0x1000>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	cache-unified;
	cache-level = <2>;
	arm,tag-latency = <4 2 3>;
	arm,data-latency = <4 2 3>;
	};

	- aips1: aips-bus@2000000 {
	+ aips1: bus@2000000 {
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02000000 0x100000>;
	ranges;

	spba: spba-bus@2000000 {
	compatible = "fsl,spba-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02000000 0x40000>;
	ranges;

	spdif: spdif@2004000 {
	compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif";
	reg = <0x02004000 0x4000>;
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 14 18 0>, <&sdma 15 18 0>;
	dma-names = "rx", "tx";
	clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
	<&clks IMX6SLL_CLK_OSC>,
	<&clks IMX6SLL_CLK_SPDIF>,
	<&clks IMX6SLL_CLK_DUMMY>,
	<&clks IMX6SLL_CLK_DUMMY>,
	<&clks IMX6SLL_CLK_DUMMY>,
	<&clks IMX6SLL_CLK_IPG>,
	<&clks IMX6SLL_CLK_DUMMY>,
	<&clks IMX6SLL_CLK_DUMMY>,
	<&clks IMX6SLL_CLK_SPBA>;
	clock-names = "core", "rxtx0",
	"rxtx1", "rxtx2",
	"rxtx3", "rxtx4",
	"rxtx5", "rxtx6",
	"rxtx7", "dma";
	status = "disabled";
	};

	ecspi1: spi@2008000 {
	compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
	reg = <0x02008000 0x4000>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
	dma-names = "rx", "tx";
	clocks = <&clks IMX6SLL_CLK_ECSPI1>,
	<&clks IMX6SLL_CLK_ECSPI1>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ecspi2: spi@200c000 {
	compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
	reg = <0x0200c000 0x4000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
	dma-names = "rx", "tx";
	clocks = <&clks IMX6SLL_CLK_ECSPI2>,
	<&clks IMX6SLL_CLK_ECSPI2>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ecspi3: spi@2010000 {
	compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
	reg = <0x02010000 0x4000>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
	dma-names = "rx", "tx";
	clocks = <&clks IMX6SLL_CLK_ECSPI3>,
	<&clks IMX6SLL_CLK_ECSPI3>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ecspi4: spi@2014000 {
	compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
	reg = <0x02014000 0x4000>;
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
	dma-names = "rx", "tx";
	clocks = <&clks IMX6SLL_CLK_ECSPI4>,
	<&clks IMX6SLL_CLK_ECSPI4>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart4: serial@2018000 {
	compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
	"fsl,imx21-uart";
	reg = <0x02018000 0x4000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
	dma-names = "rx", "tx";
	clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
	<&clks IMX6SLL_CLK_UART4_SERIAL>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart1: serial@2020000 {
	compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
	"fsl,imx21-uart";
	reg = <0x02020000 0x4000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
	dma-names = "rx", "tx";
	clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
	<&clks IMX6SLL_CLK_UART1_SERIAL>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart2: serial@2024000 {
	compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
	"fsl,imx21-uart";
	reg = <0x02024000 0x4000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
	dma-names = "rx", "tx";
	clocks = <&clks IMX6SLL_CLK_UART2_IPG>,
	<&clks IMX6SLL_CLK_UART2_SERIAL>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ssi1: ssi-controller@2028000 {
	compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
	reg = <0x02028000 0x4000>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 37 22 0>, <&sdma 38 22 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	clocks = <&clks IMX6SLL_CLK_SSI1_IPG>,
	<&clks IMX6SLL_CLK_SSI1>;
	clock-names = "ipg", "baud";
	status = "disabled";
	};

	ssi2: ssi-controller@202c000 {
	compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
	reg = <0x0202c000 0x4000>;
	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 41 22 0>, <&sdma 42 22 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	clocks = <&clks IMX6SLL_CLK_SSI2_IPG>,
	<&clks IMX6SLL_CLK_SSI2>;
	clock-names = "ipg", "baud";
	status = "disabled";
	};

	ssi3: ssi-controller@2030000 {
	compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
	reg = <0x02030000 0x4000>;
	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 45 22 0>, <&sdma 46 22 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	clocks = <&clks IMX6SLL_CLK_SSI3_IPG>,
	<&clks IMX6SLL_CLK_SSI3>;
	clock-names = "ipg", "baud";
	status = "disabled";
	};

	uart3: serial@2034000 {
	compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
	"fsl,imx21-uart";
	reg = <0x02034000 0x4000>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
	dma-name = "rx", "tx";
	clocks = <&clks IMX6SLL_CLK_UART3_IPG>,
	<&clks IMX6SLL_CLK_UART3_SERIAL>;
	clock-names = "ipg", "per";
	status = "disabled";
	};
	};

	pwm1: pwm@2080000 {
	compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
	reg = <0x02080000 0x4000>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_PWM1>,
	<&clks IMX6SLL_CLK_PWM1>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	};

	pwm2: pwm@2084000 {
	compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
	reg = <0x02084000 0x4000>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_PWM2>,
	<&clks IMX6SLL_CLK_PWM2>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	};

	pwm3: pwm@2088000 {
	compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
	reg = <0x02088000 0x4000>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_PWM3>,
	<&clks IMX6SLL_CLK_PWM3>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	};

	pwm4: pwm@208c000 {
	compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
	reg = <0x0208c000 0x4000>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_PWM4>,
	<&clks IMX6SLL_CLK_PWM4>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	};

	gpt1: timer@2098000 {
	compatible = "fsl,imx6sl-gpt";
	reg = <0x02098000 0x4000>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
	<&clks IMX6SLL_CLK_GPT_SERIAL>;
	clock-names = "ipg", "per";
	};

	gpio1: gpio@209c000 {
	compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
	reg = <0x0209c000 0x4000>;
	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_GPIO1>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
	};

	gpio2: gpio@20a0000 {
	compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
	reg = <0x020a0000 0x4000>;
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_GPIO2>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 50 32>;
	};

	gpio3: gpio@20a4000 {
	compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
	reg = <0x020a4000 0x4000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_GPIO3>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
	<&iomuxc 16 101 2>, <&iomuxc 18 5 1>,
	<&iomuxc 21 6 11>;
	};

	gpio4: gpio@20a8000 {
	compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
	reg = <0x020a8000 0x4000>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_GPIO4>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
	<&iomuxc 16 151 1>, <&iomuxc 17 149 1>,
	<&iomuxc 18 146 1>, <&iomuxc 19 144 1>,
	<&iomuxc 20 142 1>, <&iomuxc 21 143 1>,
	<&iomuxc 22 150 1>, <&iomuxc 23 148 1>,
	<&iomuxc 24 147 1>, <&iomuxc 25 145 1>,
	<&iomuxc 26 152 1>, <&iomuxc 27 125 1>,
	<&iomuxc 28 131 1>, <&iomuxc 29 134 1>,
	<&iomuxc 30 129 1>, <&iomuxc 31 133 1>;
	};

	gpio5: gpio@20ac000 {
	compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
	reg = <0x020ac000 0x4000>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_GPIO5>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
	<&iomuxc 2 132 1>, <&iomuxc 3 130 1>,
	<&iomuxc 4 127 1>, <&iomuxc 5 126 1>,
	<&iomuxc 6 120 1>, <&iomuxc 7 123 1>,
	<&iomuxc 8 118 1>, <&iomuxc 9 122 1>,
	<&iomuxc 10 124 1>, <&iomuxc 11 117 1>,
	<&iomuxc 12 121 1>, <&iomuxc 13 119 1>,
	<&iomuxc 14 116 1>, <&iomuxc 15 115 1>,
	<&iomuxc 16 140 2>, <&iomuxc 18 136 1>,
	<&iomuxc 19 138 1>, <&iomuxc 20 139 1>,
	<&iomuxc 21 137 1>;
	};

	gpio6: gpio@20b0000 {
	compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
	reg = <0x020b0000 0x4000>;
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_GPIO6>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	kpp: keypad@20b8000 {
	compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp";
	reg = <0x020b8000 0x4000>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_KPP>;
	status = "disabled";
	};

	wdog1: watchdog@20bc000 {
	compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
	reg = <0x020bc000 0x4000>;
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_WDOG1>;
	};

	wdog2: watchdog@20c0000 {
	compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
	reg = <0x020c0000 0x4000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_WDOG2>;
	status = "disabled";
	};

	clks: clock-controller@20c4000 {
	compatible = "fsl,imx6sll-ccm";
	reg = <0x020c4000 0x4000>;
	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	#clock-cells = <1>;
	clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
	clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";

	assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
	assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
	};

	anatop: anatop@20c8000 {
	compatible = "fsl,imx6sll-anatop",
	"fsl,imx6q-anatop",
	"syscon", "simple-mfd";
	reg = <0x020c8000 0x4000>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;

	reg_3p0: regulator-3p0@20c8120 {
	compatible = "fsl,anatop-regulator";
	reg = <0x20c8120>;
	regulator-name = "vdd3p0";
	regulator-min-microvolt = <2625000>;
	regulator-max-microvolt = <3400000>;
	anatop-reg-offset = <0x120>;
	anatop-vol-bit-shift = <8>;
	anatop-vol-bit-width = <5>;
	anatop-min-bit-val = <0>;
	anatop-min-voltage = <2625000>;
	anatop-max-voltage = <3400000>;
	anatop-enable-bit = <0>;
	};
	};

	usbphy1: usb-phy@20c9000 {
	compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
	"fsl,imx23-usbphy";
	reg = <0x020c9000 0x1000>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_USBPHY1>;
	phy-3p0-supply = <&reg_3p0>;
	fsl,anatop = <&anatop>;
	};

	usbphy2: usb-phy@20ca000 {
	compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
	"fsl,imx23-usbphy";
	reg = <0x020ca000 0x1000>;
	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_USBPHY2>;
	phy-reg_3p0-supply = <&reg_3p0>;
	fsl,anatop = <&anatop>;
	};

	snvs: snvs@20cc000 {
	compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
	reg = <0x020cc000 0x4000>;

	snvs_rtc: snvs-rtc-lp {
	compatible = "fsl,sec-v4.0-mon-rtc-lp";
	regmap = <&snvs>;
	offset = <0x34>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	};

	snvs_poweroff: snvs-poweroff {
	compatible = "syscon-poweroff";
	regmap = <&snvs>;
	offset = <0x38>;
	mask = <0x61>;
	status = "disabled";
	};

	snvs_pwrkey: snvs-powerkey {
	compatible = "fsl,sec-v4.0-pwrkey";
	regmap = <&snvs>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	linux,keycode = <KEY_POWER>;
	wakeup-source;
	status = "disabled";
	};
	};

	src: reset-controller@20d8000 {
	compatible = "fsl,imx6sll-src", "fsl,imx51-src";
	reg = <0x020d8000 0x4000>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	#reset-cells = <1>;
	};

	gpc: interrupt-controller@20dc000 {
	compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc";
	reg = <0x020dc000 0x4000>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-parent = <&intc>;
	};

	iomuxc: pinctrl@20e0000 {
	compatible = "fsl,imx6sll-iomuxc";
	reg = <0x020e0000 0x4000>;
	};

	gpr: iomuxc-gpr@20e4000 {
	compatible = "fsl,imx6sll-iomuxc-gpr",
	"fsl,imx6q-iomuxc-gpr", "syscon";
	reg = <0x020e4000 0x4000>;
	};

	csi: csi@20e8000 {
	compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
	reg = <0x020e8000 0x4000>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_DUMMY>,
	<&clks IMX6SLL_CLK_CSI>,
	<&clks IMX6SLL_CLK_DUMMY>;
	clock-names = "disp-axi", "csi_mclk", "disp_dcic";
	status = "disabled";
	};

	sdma: dma-controller@20ec000 {
	compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma";
	reg = <0x020ec000 0x4000>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_IPG>,
	<&clks IMX6SLL_CLK_SDMA>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	iram = <&ocram>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
	};

	pxp: pxp@20f0000 {
	compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp";
	reg = <0x20f0000 0x4000>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_PXP>;
	clock-names = "axi";
	};

	lcdif: lcd-controller@20f8000 {
	compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
	reg = <0x020f8000 0x4000>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
	<&clks IMX6SLL_CLK_LCDIF_APB>,
	<&clks IMX6SLL_CLK_DUMMY>;
	clock-names = "pix", "axi", "disp_axi";
	status = "disabled";
	};

	- dcp: dcp@20fc000 {
	+ dcp: crypto@20fc000 {
	compatible = "fsl,imx28-dcp";
	reg = <0x020fc000 0x4000>;
	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_DCP>;
	clock-names = "dcp";
	};
	};

	- aips2: aips-bus@2100000 {
	+ aips2: bus@2100000 {
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02100000 0x100000>;
	ranges;

	usbotg1: usb@2184000 {
	compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
	"fsl,imx27-usb";
	reg = <0x02184000 0x200>;
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_USBOH3>;
	fsl,usbphy = <&usbphy1>;
	fsl,usbmisc = <&usbmisc 0>;
	fsl,anatop = <&anatop>;
	ahb-burst-config = <0x0>;
	tx-burst-size-dword = <0x10>;
	rx-burst-size-dword = <0x10>;
	status = "disabled";
	};

	usbotg2: usb@2184200 {
	compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
	"fsl,imx27-usb";
	reg = <0x02184200 0x200>;
	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_USBOH3>;
	fsl,usbphy = <&usbphy2>;
	fsl,usbmisc = <&usbmisc 1>;
	ahb-burst-config = <0x0>;
	tx-burst-size-dword = <0x10>;
	rx-burst-size-dword = <0x10>;
	status = "disabled";
	};

	usbmisc: usbmisc@2184800 {
	#index-cells = <1>;
	compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc",
	"fsl,imx6q-usbmisc";
	reg = <0x02184800 0x200>;
	};

	usdhc1: mmc@2190000 {
	compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
	reg = <0x02190000 0x4000>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_USDHC1>,
	<&clks IMX6SLL_CLK_USDHC1>,
	<&clks IMX6SLL_CLK_USDHC1>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	fsl,tuning-step = <2>;
	fsl,tuning-start-tap = <20>;
	status = "disabled";
	};

	usdhc2: mmc@2194000 {
	compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
	reg = <0x02194000 0x4000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_USDHC2>,
	<&clks IMX6SLL_CLK_USDHC2>,
	<&clks IMX6SLL_CLK_USDHC2>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	fsl,tuning-step = <2>;
	fsl,tuning-start-tap = <20>;
	status = "disabled";
	};

	usdhc3: mmc@2198000 {
	compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
	reg = <0x02198000 0x4000>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_USDHC3>,
	<&clks IMX6SLL_CLK_USDHC3>,
	<&clks IMX6SLL_CLK_USDHC3>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	fsl,tuning-step = <2>;
	fsl,tuning-start-tap = <20>;
	status = "disabled";
	};

	i2c1: i2c@21a0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
	reg = <0x021a0000 0x4000>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_I2C1>;
	status = "disabled";
	};

	i2c2: i2c@21a4000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
	reg = <0x021a4000 0x4000>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_I2C2>;
	status = "disabled";
	};

	i2c3: i2c@21a8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
	reg = <0x021a8000 0x4000>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SLL_CLK_I2C3>;
	status = "disabled";
	};

	mmdc: memory-controller@21b0000 {
	compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
	reg = <0x021b0000 0x4000>;
	clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
	};

	ocotp: ocotp-ctrl@21bc000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "fsl,imx6sll-ocotp", "syscon";
	reg = <0x021bc000 0x4000>;
	clocks = <&clks IMX6SLL_CLK_OCOTP>;

	+ cpu_speed_grade: speed-grade@10 {
	+ reg = <0x10 4>;
	+ };
	+
	tempmon_calib: calib@38 {
	reg = <0x38 4>;
	};

	tempmon_temp_grade: temp-grade@20 {
	reg = <0x20 4>;
	};
	};

	audmux: audmux@21d8000 {
	compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux";
	reg = <0x021d8000 0x4000>;
	status = "disabled";
	};

	uart5: serial@21f4000 {
	compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart",
	"fsl,imx21-uart";
	reg = <0x021f4000 0x4000>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
	dma-names = "rx", "tx";
	clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
	<&clks IMX6SLL_CLK_UART5_SERIAL>;
	clock-names = "ipg", "per";
	status = "disabled";
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6sx-nitrogen6sx.dts b/sys/gnu/dts/arm/imx6sx-nitrogen6sx.dts
	index 832b5c5d7441..d84ea6999377 100644
	--- a/sys/gnu/dts/arm/imx6sx-nitrogen6sx.dts
	+++ b/sys/gnu/dts/arm/imx6sx-nitrogen6sx.dts
	@@ -1,602 +1,602 @@
	// SPDX-License-Identifier: GPL-2.0 OR X11
	/*
	* Copyright (C) 2016 Boundary Devices, Inc.
	*/

	/dts-v1/;

	#include "imx6sx.dtsi"

	/ {
	model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board";
	compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx";

	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x40000000>;
	};

	backlight-lvds {
	compatible = "pwm-backlight";
	pwms = <&pwm4 0 5000000>;
	brightness-levels = <0 4 8 16 32 64 128 255>;
	default-brightness-level = <6>;
	power-supply = <&reg_3p3v>;
	};

	reg_1p8v: regulator-1p8v {
	compatible = "regulator-fixed";
	regulator-name = "1P8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
	compatible = "regulator-fixed";
	regulator-name = "3P3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_can1_3v3: regulator-can1-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "can1-3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
	};

	reg_can2_3v3: regulator-can2-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "can2-3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio4 24 GPIO_ACTIVE_LOW>;
	};

	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1_vbus>;
	compatible = "regulator-fixed";
	regulator-name = "usb_otg1_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_wlan: regulator-wlan {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_reg_wlan>;
	compatible = "regulator-fixed";
	clocks = <&clks IMX6SX_CLK_CKO>;
	clock-names = "slow";
	regulator-name = "wlan-en";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	startup-delay-us = <70000>;
	gpio = <&gpio7 6 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	sound {
	compatible = "fsl,imx-audio-sgtl5000";
	model = "imx6sx-nitrogen6sx-sgtl5000";
	cpu-dai = <&ssi1>;
	audio-codec = <&codec>;
	audio-routing =
	"MIC_IN", "Mic Jack",
	"Mic Jack", "Mic Bias",
	"Headphone Jack", "HP_OUT";
	mux-int-port = <1>;
	mux-ext-port = <5>;
	};
	};

	&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
	};

	&ecspi1 {
	cs-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	status = "okay";

	flash: m25p80@0 {
	compatible = "microchip,sst25vf016b";
	spi-max-frequency = <20000000>;
	reg = <0>;
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
	label = "U-Boot";
	reg = <0x0 0xc0000>;
	read-only;
	};

	partition@c0000 {
	label = "env";
	reg = <0xc0000 0x2000>;
	read-only;
	};

	partition@c2000 {
	label = "Kernel";
	reg = <0xc2000 0x11e000>;
	};

	partition@1e0000 {
	label = "M4";
	reg = <0x1e0000 0x20000>;
	};
	};
	};

	&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_3p3v>;
	fsl,magic-packet;
	status = "okay";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy1: ethernet-phy@4 {
	reg = <4>;
	};

	ethphy2: ethernet-phy@5 {
	reg = <5>;
	};
	};
	};

	&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy2>;
	phy-supply = <&reg_3p3v>;
	fsl,magic-packet;
	status = "okay";
	};

	&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can1_3v3>;
	status = "okay";
	};

	&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_can2_3v3>;
	status = "okay";
	};

	&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	codec: sgtl5000@a {
	compatible = "fsl,sgtl5000";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sgtl5000>;
	reg = <0x0a>;
	clocks = <&clks IMX6SX_CLK_CKO2>;
	VDDA-supply = <&reg_1p8v>;
	VDDIO-supply = <&reg_1p8v>;
	VDDD-supply = <&reg_1p8v>;
	assigned-clocks = <&clks IMX6SX_CLK_CKO2_SEL>,
	<&clks IMX6SX_CLK_CKO2>;
	assigned-clock-parents = <&clks IMX6SX_CLK_OSC>;
	assigned-clock-rates = <0>, <24000000>;
	};
	};

	&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
	};

	&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
	};

	&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio4 10 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
	status = "okay";
	};

	&ssi1 {
	status = "okay";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
	};

	&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	uart-has-rtscts;
	status = "okay";
	};

	&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	status = "okay";
	};

	&usbotg1 {
	vbus-supply = <&reg_usb_otg1_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1>;
	status = "okay";
	};

	&usbotg2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg2>;
	dr_mode = "host";
	disable-over-current;
	reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	bus-width = <4>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	keep-power-in-suspend;
	wakeup-source;
	status = "okay";
	};

	&usdhc3 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	bus-width = <4>;
	non-removable;
	keep-power-in-suspend;
	vmmc-supply = <&reg_wlan>;
	cap-power-off-card;
	cap-sdio-irq;
	status = "okay";

	brcmf: wifi@1 {
	reg = <1>;
	compatible = "brcm,bcm4329-fmac";
	interrupt-parent = <&gpio7>;
	interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
	};

	wlcore: wlcore@2 {
	compatible = "ti,wl1271";
	reg = <2>;
	interrupt-parent = <&gpio7>;
	interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
	ref-clock-frequency = <38400000>;
	};
	};

	&usdhc4 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc4_50mhz>;
	pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
	bus-width = <8>;
	non-removable;
	vmmc-supply = <&reg_1p8v>;
	keep-power-in-suspend;
	status = "okay";
	};

	&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_audmux: audmuxgrp {
	fsl,pins = <
	MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x1b0b0
	MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x1b0b0
	MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x1b0b0
	MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x1b0b0
	>;
	};

	pinctrl_ecspi1: ecspi1grp {
	fsl,pins = <
	MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
	MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
	MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
	MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x0b0b1
	>;
	};

	pinctrl_enet1: enet1grp {
	fsl,pins = <
	MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x1b0b0
	MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x1b0b0
	MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x30b1
	MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x30b1
	MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x30b1
	MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x30b1
	MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x30b1
	MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x30b1
	MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
	MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
	MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
	MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
	MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
	MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
	MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0xb0b0
	MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0xb0b0
	MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0xb0b0
	>;
	};

	pinctrl_enet2: enet2grp {
	fsl,pins = <
	MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x30b1
	MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x30b1
	MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x30b1
	MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x30b1
	MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x30b1
	MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x30b1
	MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
	MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
	MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
	MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
	MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
	MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
	MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0xb0b0
	MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0xb0b0
	MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0xb0b0
	>;
	};

	pinctrl_flexcan1: flexcan1grp {
	fsl,pins = <
	MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0
	MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0
	MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x1b0b0
	MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x0b0b0
	>;
	};

	pinctrl_flexcan2: flexcan2grp {
	fsl,pins = <
	MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0
	MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0
	MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x0b0b0
	>;
	};

	pinctrl_hog: hoggrp {
	fsl,pins = <
	MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x1b0b0
	MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x1b0b0
	MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x1b0b0
	MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x1b0b0
	MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x1b0b0
	MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x1b0b0
	MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x1b0b0
	MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x1b0b0
	MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x1b0b0
	MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x1b0b0
	MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x000b0
	MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x1b0b0
	/* Test points */
	MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x1b0b0
	MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x1b0b0
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
	MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
	MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
	MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
	>;
	};

	pinctrl_pcie: pciegrp {
	fsl,pins = <
	MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0xb0b0
	MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0xb0b0
	MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0xb0b0
	>;
	};

	pinctrl_pwm4: pwm4grp {
	fsl,pins = <
	MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x110b0
	>;
	};

	pinctrl_reg_wlan: reg-wlangrp {
	fsl,pins = <
	MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x1b0b0
	MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x000b0
	>;
	};

	pinctrl_sgtl5000: sgtl5000grp {
	fsl,pins = <
	MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x000b0
	MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x1b0b0
	MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x1b0b0
	MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0xb0b0
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	- MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
	- MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
	+ MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
	+ MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	- MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
	- MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
	+ MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1
	+ MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1
	>;
	};

	pinctrl_uart3: uart3grp {
	fsl,pins = <
	- MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x1b0b1
	- MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x1b0b1
	+ MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x1b0b1
	+ MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x1b0b1
	>;
	};

	pinctrl_uart5: uart5grp {
	fsl,pins = <
	- MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
	- MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
	- MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x1b0b1
	- MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x1b0b1
	+ MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1
	+ MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1
	+ MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x1b0b1
	+ MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x1b0b1
	>;
	};

	pinctrl_usbotg1: usbotg1grp {
	fsl,pins = <
	MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x1b0b0
	MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x170b1
	>;
	};

	pinctrl_usbotg1_vbus: usbotg1-vbusgrp {
	fsl,pins = <
	MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x1b0b0
	>;
	};

	pinctrl_usbotg2: usbotg2grp {
	fsl,pins = <
	MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0xb0b0
	>;
	};

	pinctrl_usdhc2: usdhc2grp {
	fsl,pins = <
	MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
	MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
	MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
	MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
	MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
	MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
	MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x1b0b0
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071
	MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17071
	MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17071
	MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17071
	MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17071
	MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17071
	>;
	};

	pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp {
	fsl,pins = <
	MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071
	MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071
	MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17071
	MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071
	MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071
	MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071
	MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071
	MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071
	MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071
	MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071
	MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071
	>;
	};

	pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp {
	fsl,pins = <
	MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
	MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
	MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
	MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
	MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
	MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
	MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
	MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
	MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
	MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
	>;
	};

	pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp {
	fsl,pins = <
	MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
	MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
	MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
	MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
	MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
	MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
	MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
	MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
	MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
	MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6sx-pinfunc.h b/sys/gnu/dts/arm/imx6sx-pinfunc.h
	index aa194a2fdd53..0b02c7e60c17 100644
	--- a/sys/gnu/dts/arm/imx6sx-pinfunc.h
	+++ b/sys/gnu/dts/arm/imx6sx-pinfunc.h
	@@ -1,1554 +1,1668 @@
	/* SPDX-License-Identifier: GPL-2.0-only */
	/*
	* Copyright 2014 Freescale Semiconductor, Inc.
	*/

	#ifndef __DTS_IMX6SX_PINFUNC_H
	#define __DTS_IMX6SX_PINFUNC_H

	/*
	* The pin function ID is a tuple of
	* <mux_reg conf_reg input_reg mux_mode input_val>
	*/
	#define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
	#define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
	#define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
	#define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
	#define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
	#define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
	#define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
	#define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
	#define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
	#define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
	#define MX6SX_PAD_GPIO1_IO01__SPDIF_SR_CLK 0x0018 0x0360 0x0000 0x2 0x0
	#define MX6SX_PAD_GPIO1_IO01__CCM_STOP 0x0018 0x0360 0x0000 0x3 0x0
	#define MX6SX_PAD_GPIO1_IO01__WDOG3_WDOG_B 0x0018 0x0360 0x0000 0x4 0x0
	#define MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x0018 0x0360 0x0000 0x5 0x0
	#define MX6SX_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL 0x0018 0x0360 0x0000 0x6 0x0
	#define MX6SX_PAD_GPIO1_IO01__PHY_DTB_0 0x0018 0x0360 0x0000 0x7 0x0
	#define MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x001C 0x0364 0x07B0 0x0 0x1
	#define MX6SX_PAD_GPIO1_IO02__USDHC1_CD_B 0x001C 0x0364 0x0864 0x1 0x1
	#define MX6SX_PAD_GPIO1_IO02__CSI2_MCLK 0x001C 0x0364 0x0000 0x2 0x0
	#define MX6SX_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK 0x001C 0x0364 0x0000 0x3 0x0
	#define MX6SX_PAD_GPIO1_IO02__WDOG1_WDOG_B 0x001C 0x0364 0x0000 0x4 0x0
	#define MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x001C 0x0364 0x0000 0x5 0x0
	#define MX6SX_PAD_GPIO1_IO02__CCM_REF_EN_B 0x001C 0x0364 0x0000 0x6 0x0
	#define MX6SX_PAD_GPIO1_IO02__PHY_TDI 0x001C 0x0364 0x0000 0x7 0x0
	#define MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x0020 0x0368 0x07B4 0x0 0x1
	#define MX6SX_PAD_GPIO1_IO03__USDHC1_WP 0x0020 0x0368 0x0868 0x1 0x1
	#define MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M 0x0020 0x0368 0x0000 0x2 0x0
	#define MX6SX_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK 0x0020 0x0368 0x0000 0x3 0x0
	#define MX6SX_PAD_GPIO1_IO03__WDOG2_WDOG_B 0x0020 0x0368 0x0000 0x4 0x0
	#define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x0020 0x0368 0x0000 0x5 0x0
	#define MX6SX_PAD_GPIO1_IO03__CCM_PLL3_BYP 0x0020 0x0368 0x0000 0x6 0x0
	#define MX6SX_PAD_GPIO1_IO03__PHY_TCK 0x0020 0x0368 0x0000 0x7 0x0
	-#define MX6SX_PAD_GPIO1_IO04__UART1_RX 0x0024 0x036C 0x0830 0x0 0x0
	-#define MX6SX_PAD_GPIO1_IO04__UART1_TX 0x0024 0x036C 0x0000 0x0 0x0
	+#define MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x0024 0x036C 0x0000 0x0 0x0
	+#define MX6SX_PAD_GPIO1_IO04__UART1_DTE_RX 0x0024 0x036C 0x0830 0x0 0x0
	#define MX6SX_PAD_GPIO1_IO04__USDHC2_RESET_B 0x0024 0x036C 0x0000 0x1 0x0
	#define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024 0x036C 0x0000 0x2 0x0
	#define MX6SX_PAD_GPIO1_IO04__OSC32K_32K_OUT 0x0024 0x036C 0x0000 0x3 0x0
	#define MX6SX_PAD_GPIO1_IO04__ENET2_REF_CLK2 0x0024 0x036C 0x076C 0x4 0x0
	#define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4 0x0024 0x036C 0x0000 0x5 0x0
	#define MX6SX_PAD_GPIO1_IO04__CCM_PLL2_BYP 0x0024 0x036C 0x0000 0x6 0x0
	#define MX6SX_PAD_GPIO1_IO04__PHY_TMS 0x0024 0x036C 0x0000 0x7 0x0
	-#define MX6SX_PAD_GPIO1_IO05__UART1_RX 0x0028 0x0370 0x0830 0x0 0x1
	-#define MX6SX_PAD_GPIO1_IO05__UART1_TX 0x0028 0x0370 0x0000 0x0 0x0
	+#define MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x0028 0x0370 0x0830 0x0 0x1
	+#define MX6SX_PAD_GPIO1_IO05__UART1_DTE_TX 0x0028 0x0370 0x0000 0x0 0x0
	#define MX6SX_PAD_GPIO1_IO05__USDHC2_VSELECT 0x0028 0x0370 0x0000 0x1 0x0
	#define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028 0x0370 0x0764 0x2 0x0
	#define MX6SX_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK 0x0028 0x0370 0x0000 0x3 0x0
	#define MX6SX_PAD_GPIO1_IO05__ENET1_REF_CLK1 0x0028 0x0370 0x0760 0x4 0x0
	#define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5 0x0028 0x0370 0x0000 0x5 0x0
	#define MX6SX_PAD_GPIO1_IO05__SRC_TESTER_ACK 0x0028 0x0370 0x0000 0x6 0x0
	#define MX6SX_PAD_GPIO1_IO05__PHY_TDO 0x0028 0x0370 0x0000 0x7 0x0
	-#define MX6SX_PAD_GPIO1_IO06__UART2_RX 0x002C 0x0374 0x0838 0x0 0x0
	-#define MX6SX_PAD_GPIO1_IO06__UART2_TX 0x002C 0x0374 0x0000 0x0 0x0
	+#define MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x002C 0x0374 0x0000 0x0 0x0
	+#define MX6SX_PAD_GPIO1_IO06__UART2_DTE_RX 0x002C 0x0374 0x0838 0x0 0x0
	#define MX6SX_PAD_GPIO1_IO06__USDHC2_CD_B 0x002C 0x0374 0x086C 0x1 0x1
	#define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0
	#define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0
	-#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B 0x002C 0x0374 0x082C 0x4 0x0
	+#define MX6SX_PAD_GPIO1_IO06__UART1_DCE_RTS 0x002C 0x0374 0x082C 0x4 0x0
	+#define MX6SX_PAD_GPIO1_IO06__UART1_DTE_CTS 0x002C 0x0374 0x0000 0x4 0x0
	#define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0
	#define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0
	#define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0
	-#define MX6SX_PAD_GPIO1_IO07__UART2_RX 0x0030 0x0378 0x0838 0x0 0x1
	-#define MX6SX_PAD_GPIO1_IO07__UART2_TX 0x0030 0x0378 0x0000 0x0 0x0
	+#define MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x0030 0x0378 0x0838 0x0 0x1
	+#define MX6SX_PAD_GPIO1_IO07__UART2_DTE_TX 0x0030 0x0378 0x0000 0x0 0x0
	#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1
	#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0
	#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0
	-#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x0000 0x4 0x0
	+#define MX6SX_PAD_GPIO1_IO07__UART1_DCE_CTS 0x0030 0x0378 0x0000 0x4 0x0
	+#define MX6SX_PAD_GPIO1_IO07__UART1_DTE_RTS 0x0030 0x0378 0x082C 0x4 0x1
	#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0
	#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0
	#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0
	#define MX6SX_PAD_GPIO1_IO07__VDEC_DEBUG_44 0x0030 0x0378 0x0000 0x8 0x0
	#define MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x0034 0x037C 0x0860 0x0 0x0
	#define MX6SX_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0034 0x037C 0x0000 0x1 0x0
	#define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0
	#define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1
	-#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B 0x0034 0x037C 0x0834 0x4 0x0
	+#define MX6SX_PAD_GPIO1_IO08__UART2_DCE_RTS 0x0034 0x037C 0x0834 0x4 0x0
	+#define MX6SX_PAD_GPIO1_IO08__UART2_DTE_CTS 0x0034 0x037C 0x0000 0x4 0x0
	#define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0
	#define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0
	#define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0
	#define MX6SX_PAD_GPIO1_IO08__VDEC_DEBUG_43 0x0034 0x037C 0x0000 0x8 0x0
	#define MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR 0x0038 0x0380 0x0000 0x0 0x0
	#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0
	#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0
	#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0
	-#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0000 0x4 0x0
	+#define MX6SX_PAD_GPIO1_IO09__UART2_DCE_CTS 0x0038 0x0380 0x0000 0x4 0x0
	+#define MX6SX_PAD_GPIO1_IO09__UART2_DTE_RTS 0x0038 0x0380 0x0834 0x4 0x1
	#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0
	#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0
	#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0
	#define MX6SX_PAD_GPIO1_IO09__VDEC_DEBUG_42 0x0038 0x0380 0x0000 0x8 0x0
	#define MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x003C 0x0384 0x0624 0x0 0x0
	#define MX6SX_PAD_GPIO1_IO10__SPDIF_EXT_CLK 0x003C 0x0384 0x0828 0x1 0x0
	#define MX6SX_PAD_GPIO1_IO10__PWM1_OUT 0x003C 0x0384 0x0000 0x2 0x0
	#define MX6SX_PAD_GPIO1_IO10__CCM_OUT1 0x003C 0x0384 0x0000 0x3 0x0
	#define MX6SX_PAD_GPIO1_IO10__CSI1_FIELD 0x003C 0x0384 0x070C 0x4 0x1
	#define MX6SX_PAD_GPIO1_IO10__GPIO1_IO_10 0x003C 0x0384 0x0000 0x5 0x0
	#define MX6SX_PAD_GPIO1_IO10__CSU_CSU_INT_DEB 0x003C 0x0384 0x0000 0x6 0x0
	#define MX6SX_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3 0x003C 0x0384 0x0000 0x7 0x0
	#define MX6SX_PAD_GPIO1_IO10__VDEC_DEBUG_41 0x003C 0x0384 0x0000 0x8 0x0
	#define MX6SX_PAD_GPIO1_IO11__USB_OTG2_OC 0x0040 0x0388 0x085C 0x0 0x0
	#define MX6SX_PAD_GPIO1_IO11__SPDIF_IN 0x0040 0x0388 0x0824 0x1 0x2
	#define MX6SX_PAD_GPIO1_IO11__PWM2_OUT 0x0040 0x0388 0x0000 0x2 0x0
	#define MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x0040 0x0388 0x0000 0x3 0x0
	#define MX6SX_PAD_GPIO1_IO11__MLB_DATA 0x0040 0x0388 0x07EC 0x4 0x0
	#define MX6SX_PAD_GPIO1_IO11__GPIO1_IO_11 0x0040 0x0388 0x0000 0x5 0x0
	#define MX6SX_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0 0x0040 0x0388 0x0000 0x6 0x0
	#define MX6SX_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2 0x0040 0x0388 0x0000 0x7 0x0
	#define MX6SX_PAD_GPIO1_IO11__VDEC_DEBUG_40 0x0040 0x0388 0x0000 0x8 0x0
	#define MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR 0x0044 0x038C 0x0000 0x0 0x0
	#define MX6SX_PAD_GPIO1_IO12__SPDIF_OUT 0x0044 0x038C 0x0000 0x1 0x0
	#define MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x0044 0x038C 0x0000 0x2 0x0
	#define MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x0044 0x038C 0x0000 0x3 0x0
	#define MX6SX_PAD_GPIO1_IO12__MLB_CLK 0x0044 0x038C 0x07E8 0x4 0x0
	#define MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x0044 0x038C 0x0000 0x5 0x0
	#define MX6SX_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1 0x0044 0x038C 0x0000 0x6 0x0
	#define MX6SX_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1 0x0044 0x038C 0x0000 0x7 0x0
	#define MX6SX_PAD_GPIO1_IO12__VDEC_DEBUG_39 0x0044 0x038C 0x0000 0x8 0x0
	#define MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x0048 0x0390 0x0000 0x0 0x0
	#define MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x0048 0x0390 0x0628 0x1 0x0
	#define MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x0048 0x0390 0x0000 0x2 0x0
	#define MX6SX_PAD_GPIO1_IO13__CCM_OUT2 0x0048 0x0390 0x0000 0x3 0x0
	#define MX6SX_PAD_GPIO1_IO13__MLB_SIG 0x0048 0x0390 0x07F0 0x4 0x0
	#define MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 0x0048 0x0390 0x0000 0x5 0x0
	#define MX6SX_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2 0x0048 0x0390 0x0000 0x6 0x0
	#define MX6SX_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0 0x0048 0x0390 0x0000 0x7 0x0
	#define MX6SX_PAD_GPIO1_IO13__VDEC_DEBUG_38 0x0048 0x0390 0x0000 0x8 0x0
	#define MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x004C 0x0394 0x06A8 0x0 0x0
	#define MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x004C 0x0394 0x078C 0x1 0x1
	#define MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x004C 0x0394 0x0684 0x2 0x1
	#define MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x004C 0x0394 0x07A8 0x3 0x0
	#define MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x004C 0x0394 0x0000 0x4 0x0
	#define MX6SX_PAD_CSI_DATA00__GPIO1_IO_14 0x004C 0x0394 0x0000 0x5 0x0
	#define MX6SX_PAD_CSI_DATA00__WEIM_DATA_23 0x004C 0x0394 0x0000 0x6 0x0
	#define MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x004C 0x0394 0x0800 0x7 0x0
	#define MX6SX_PAD_CSI_DATA00__VADC_DATA_4 0x004C 0x0394 0x0000 0x8 0x0
	#define MX6SX_PAD_CSI_DATA00__MMDC_DEBUG_37 0x004C 0x0394 0x0000 0x9 0x0
	#define MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x0050 0x0398 0x06AC 0x0 0x0
	#define MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x0050 0x0398 0x077C 0x1 0x1
	#define MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x0050 0x0398 0x0688 0x2 0x1
	#define MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x0050 0x0398 0x07AC 0x3 0x0
	#define MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x0050 0x0398 0x0000 0x4 0x0
	#define MX6SX_PAD_CSI_DATA01__GPIO1_IO_15 0x0050 0x0398 0x0000 0x5 0x0
	#define MX6SX_PAD_CSI_DATA01__WEIM_DATA_22 0x0050 0x0398 0x0000 0x6 0x0
	#define MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x0050 0x0398 0x0804 0x7 0x0
	#define MX6SX_PAD_CSI_DATA01__VADC_DATA_5 0x0050 0x0398 0x0000 0x8 0x0
	#define MX6SX_PAD_CSI_DATA01__MMDC_DEBUG_38 0x0050 0x0398 0x0000 0x9 0x0
	#define MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x0054 0x039C 0x06B0 0x0 0x0
	#define MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x0054 0x039C 0x0788 0x1 0x1
	#define MX6SX_PAD_CSI_DATA02__AUDMUX_AUD6_RXC 0x0054 0x039C 0x067C 0x2 0x1
	#define MX6SX_PAD_CSI_DATA02__KPP_COL_5 0x0054 0x039C 0x07C8 0x3 0x0
	#define MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x0054 0x039C 0x0000 0x4 0x0
	#define MX6SX_PAD_CSI_DATA02__GPIO1_IO_16 0x0054 0x039C 0x0000 0x5 0x0
	#define MX6SX_PAD_CSI_DATA02__WEIM_DATA_21 0x0054 0x039C 0x0000 0x6 0x0
	#define MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x0054 0x039C 0x07F4 0x7 0x0
	#define MX6SX_PAD_CSI_DATA02__VADC_DATA_6 0x0054 0x039C 0x0000 0x8 0x0
	#define MX6SX_PAD_CSI_DATA02__MMDC_DEBUG_39 0x0054 0x039C 0x0000 0x9 0x0
	#define MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x0058 0x03A0 0x06B4 0x0 0x0
	#define MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x0058 0x03A0 0x0778 0x1 0x1
	#define MX6SX_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS 0x0058 0x03A0 0x0680 0x2 0x1
	#define MX6SX_PAD_CSI_DATA03__KPP_ROW_5 0x0058 0x03A0 0x07D4 0x3 0x0
	#define MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x0058 0x03A0 0x0000 0x4 0x0
	#define MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x0058 0x03A0 0x0000 0x5 0x0
	#define MX6SX_PAD_CSI_DATA03__WEIM_DATA_20 0x0058 0x03A0 0x0000 0x6 0x0
	#define MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x0058 0x03A0 0x07FC 0x7 0x0
	#define MX6SX_PAD_CSI_DATA03__VADC_DATA_7 0x0058 0x03A0 0x0000 0x8 0x0
	#define MX6SX_PAD_CSI_DATA03__MMDC_DEBUG_40 0x0058 0x03A0 0x0000 0x9 0x0
	#define MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x005C 0x03A4 0x06B8 0x0 0x0
	#define MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x005C 0x03A4 0x0794 0x1 0x1
	#define MX6SX_PAD_CSI_DATA04__SPDIF_OUT 0x005C 0x03A4 0x0000 0x2 0x0
	#define MX6SX_PAD_CSI_DATA04__KPP_COL_6 0x005C 0x03A4 0x07CC 0x3 0x0
	-#define MX6SX_PAD_CSI_DATA04__UART6_RX 0x005C 0x03A4 0x0858 0x4 0x0
	-#define MX6SX_PAD_CSI_DATA04__UART6_TX 0x005C 0x03A4 0x0000 0x4 0x0
	+#define MX6SX_PAD_CSI_DATA04__UART6_DCE_RX 0x005C 0x03A4 0x0858 0x4 0x0
	+#define MX6SX_PAD_CSI_DATA04__UART6_DTE_TX 0x005C 0x03A4 0x0000 0x4 0x0
	#define MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x005C 0x03A4 0x0000 0x5 0x0
	#define MX6SX_PAD_CSI_DATA04__WEIM_DATA_19 0x005C 0x03A4 0x0000 0x6 0x0
	#define MX6SX_PAD_CSI_DATA04__PWM5_OUT 0x005C 0x03A4 0x0000 0x7 0x0
	#define MX6SX_PAD_CSI_DATA04__VADC_DATA_8 0x005C 0x03A4 0x0000 0x8 0x0
	#define MX6SX_PAD_CSI_DATA04__MMDC_DEBUG_41 0x005C 0x03A4 0x0000 0x9 0x0
	#define MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x0060 0x03A8 0x06BC 0x0 0x0
	#define MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x0060 0x03A8 0x07A0 0x1 0x1
	#define MX6SX_PAD_CSI_DATA05__SPDIF_IN 0x0060 0x03A8 0x0824 0x2 0x1
	#define MX6SX_PAD_CSI_DATA05__KPP_ROW_6 0x0060 0x03A8 0x07D8 0x3 0x0
	-#define MX6SX_PAD_CSI_DATA05__UART6_RX 0x0060 0x03A8 0x0858 0x4 0x1
	-#define MX6SX_PAD_CSI_DATA05__UART6_TX 0x0060 0x03A8 0x0000 0x4 0x0
	+#define MX6SX_PAD_CSI_DATA05__UART6_DCE_TX 0x0060 0x03A8 0x0000 0x4 0x0
	+#define MX6SX_PAD_CSI_DATA05__UART6_DTE_RX 0x0060 0x03A8 0x0858 0x4 0x1
	#define MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x0060 0x03A8 0x0000 0x5 0x0
	#define MX6SX_PAD_CSI_DATA05__WEIM_DATA_18 0x0060 0x03A8 0x0000 0x6 0x0
	#define MX6SX_PAD_CSI_DATA05__PWM6_OUT 0x0060 0x03A8 0x0000 0x7 0x0
	#define MX6SX_PAD_CSI_DATA05__VADC_DATA_9 0x0060 0x03A8 0x0000 0x8 0x0
	#define MX6SX_PAD_CSI_DATA05__MMDC_DEBUG_42 0x0060 0x03A8 0x0000 0x9 0x0
	#define MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x0064 0x03AC 0x06C0 0x0 0x0
	#define MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x0064 0x03AC 0x0798 0x1 0x1
	#define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2
	#define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0
	-#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x0064 0x03AC 0x0854 0x4 0x0
	+#define MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS 0x0064 0x03AC 0x0854 0x4 0x0
	+#define MX6SX_PAD_CSI_DATA06__UART6_DTE_CTS 0x0064 0x03AC 0x0000 0x4 0x0
	#define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0
	#define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0
	#define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0
	#define MX6SX_PAD_CSI_DATA06__VADC_DATA_10 0x0064 0x03AC 0x0000 0x8 0x0
	#define MX6SX_PAD_CSI_DATA06__MMDC_DEBUG_43 0x0064 0x03AC 0x0000 0x9 0x0
	#define MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x0068 0x03B0 0x06C4 0x0 0x0
	#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1
	#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2
	#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0
	-#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0000 0x4 0x0
	+#define MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS 0x0068 0x03B0 0x0000 0x4 0x0
	+#define MX6SX_PAD_CSI_DATA07__UART6_DTE_RTS 0x0068 0x03B0 0x0854 0x4 0x1
	#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0
	#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0
	#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0
	#define MX6SX_PAD_CSI_DATA07__VADC_DATA_11 0x0068 0x03B0 0x0000 0x8 0x0
	#define MX6SX_PAD_CSI_DATA07__MMDC_DEBUG_44 0x0068 0x03B0 0x0000 0x9 0x0
	#define MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x006C 0x03B4 0x0700 0x0 0x0
	#define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1
	#define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1
	-#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C 0x03B4 0x0844 0x3 0x2
	+#define MX6SX_PAD_CSI_HSYNC__UART4_DCE_RTS 0x006C 0x03B4 0x0844 0x3 0x2
	+#define MX6SX_PAD_CSI_HSYNC__UART4_DTE_CTS 0x006C 0x03B4 0x0000 0x3 0x0
	#define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0
	#define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0
	#define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0
	#define MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x006C 0x03B4 0x0000 0x7 0x0
	#define MX6SX_PAD_CSI_HSYNC__VADC_DATA_2 0x006C 0x03B4 0x0000 0x8 0x0
	#define MX6SX_PAD_CSI_HSYNC__MMDC_DEBUG_35 0x006C 0x03B4 0x0000 0x9 0x0
	#define MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x0070 0x03B8 0x0000 0x0 0x0
	#define MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x0070 0x03B8 0x0784 0x1 0x1
	#define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x0070 0x03B8 0x0000 0x2 0x0
	-#define MX6SX_PAD_CSI_MCLK__UART4_RX 0x0070 0x03B8 0x0848 0x3 0x2
	-#define MX6SX_PAD_CSI_MCLK__UART4_TX 0x0070 0x03B8 0x0000 0x3 0x0
	+#define MX6SX_PAD_CSI_MCLK__UART4_DCE_RX 0x0070 0x03B8 0x0848 0x3 0x2
	+#define MX6SX_PAD_CSI_MCLK__UART4_DTE_TX 0x0070 0x03B8 0x0000 0x3 0x0
	#define MX6SX_PAD_CSI_MCLK__ANATOP_32K_OUT 0x0070 0x03B8 0x0000 0x4 0x0
	#define MX6SX_PAD_CSI_MCLK__GPIO1_IO_23 0x0070 0x03B8 0x0000 0x5 0x0
	#define MX6SX_PAD_CSI_MCLK__WEIM_DATA_26 0x0070 0x03B8 0x0000 0x6 0x0
	#define MX6SX_PAD_CSI_MCLK__CSI1_FIELD 0x0070 0x03B8 0x070C 0x7 0x0
	#define MX6SX_PAD_CSI_MCLK__VADC_DATA_1 0x0070 0x03B8 0x0000 0x8 0x0
	#define MX6SX_PAD_CSI_MCLK__MMDC_DEBUG_34 0x0070 0x03B8 0x0000 0x9 0x0
	#define MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x0074 0x03BC 0x0704 0x0 0x0
	#define MX6SX_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK 0x0074 0x03BC 0x0780 0x1 0x1
	#define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x0074 0x03BC 0x0000 0x2 0x0
	-#define MX6SX_PAD_CSI_PIXCLK__UART4_RX 0x0074 0x03BC 0x0848 0x3 0x3
	-#define MX6SX_PAD_CSI_PIXCLK__UART4_TX 0x0074 0x03BC 0x0000 0x3 0x0
	+#define MX6SX_PAD_CSI_PIXCLK__UART4_DCE_TX 0x0074 0x03BC 0x0000 0x3 0x0
	+#define MX6SX_PAD_CSI_PIXCLK__UART4_DTE_RX 0x0074 0x03BC 0x0848 0x3 0x3
	#define MX6SX_PAD_CSI_PIXCLK__ANATOP_24M_OUT 0x0074 0x03BC 0x0000 0x4 0x0
	#define MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x0074 0x03BC 0x0000 0x5 0x0
	#define MX6SX_PAD_CSI_PIXCLK__WEIM_DATA_27 0x0074 0x03BC 0x0000 0x6 0x0
	#define MX6SX_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK 0x0074 0x03BC 0x0784 0x7 0x2
	#define MX6SX_PAD_CSI_PIXCLK__VADC_CLK 0x0074 0x03BC 0x0000 0x8 0x0
	#define MX6SX_PAD_CSI_PIXCLK__MMDC_DEBUG_33 0x0074 0x03BC 0x0000 0x9 0x0
	#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0
	#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1
	#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1
	-#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0000 0x3 0x0
	+#define MX6SX_PAD_CSI_VSYNC__UART4_DCE_CTS 0x0078 0x03C0 0x0000 0x3 0x0
	+#define MX6SX_PAD_CSI_VSYNC__UART4_DTE_RTS 0x0078 0x03C0 0x0844 0x3 0x3
	#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0
	#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0
	#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0
	#define MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x0078 0x03C0 0x07F8 0x7 0x0
	#define MX6SX_PAD_CSI_VSYNC__VADC_DATA_3 0x0078 0x03C0 0x0000 0x8 0x0
	#define MX6SX_PAD_CSI_VSYNC__MMDC_DEBUG_36 0x0078 0x03C0 0x0000 0x9 0x0
	#define MX6SX_PAD_ENET1_COL__ENET1_COL 0x007C 0x03C4 0x0000 0x0 0x0
	#define MX6SX_PAD_ENET1_COL__ENET2_MDC 0x007C 0x03C4 0x0000 0x1 0x0
	#define MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x007C 0x03C4 0x0654 0x2 0x1
	#define MX6SX_PAD_ENET1_COL__UART1_RI_B 0x007C 0x03C4 0x0000 0x3 0x0
	#define MX6SX_PAD_ENET1_COL__SPDIF_EXT_CLK 0x007C 0x03C4 0x0828 0x4 0x1
	#define MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x007C 0x03C4 0x0000 0x5 0x0
	#define MX6SX_PAD_ENET1_COL__CSI2_DATA_23 0x007C 0x03C4 0x0000 0x6 0x0
	#define MX6SX_PAD_ENET1_COL__LCDIF2_DATA_16 0x007C 0x03C4 0x0000 0x7 0x0
	#define MX6SX_PAD_ENET1_COL__VDEC_DEBUG_37 0x007C 0x03C4 0x0000 0x8 0x0
	#define MX6SX_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31 0x007C 0x03C4 0x0000 0x9 0x0
	#define MX6SX_PAD_ENET1_CRS__ENET1_CRS 0x0080 0x03C8 0x0000 0x0 0x0
	#define MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0x0080 0x03C8 0x0770 0x1 0x1
	#define MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x0080 0x03C8 0x0648 0x2 0x1
	#define MX6SX_PAD_ENET1_CRS__UART1_DCD_B 0x0080 0x03C8 0x0000 0x3 0x0
	#define MX6SX_PAD_ENET1_CRS__SPDIF_LOCK 0x0080 0x03C8 0x0000 0x4 0x0
	#define MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x0080 0x03C8 0x0000 0x5 0x0
	#define MX6SX_PAD_ENET1_CRS__CSI2_DATA_22 0x0080 0x03C8 0x0000 0x6 0x0
	#define MX6SX_PAD_ENET1_CRS__LCDIF2_DATA_17 0x0080 0x03C8 0x0000 0x7 0x0
	#define MX6SX_PAD_ENET1_CRS__VDEC_DEBUG_36 0x0080 0x03C8 0x0000 0x8 0x0
	#define MX6SX_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30 0x0080 0x03C8 0x0000 0x9 0x0
	#define MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x0084 0x03CC 0x0000 0x0 0x0
	#define MX6SX_PAD_ENET1_MDC__ENET2_MDC 0x0084 0x03CC 0x0000 0x1 0x0
	#define MX6SX_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS 0x0084 0x03CC 0x0638 0x2 0x1
	#define MX6SX_PAD_ENET1_MDC__ANATOP_24M_OUT 0x0084 0x03CC 0x0000 0x3 0x0
	#define MX6SX_PAD_ENET1_MDC__EPIT2_OUT 0x0084 0x03CC 0x0000 0x4 0x0
	#define MX6SX_PAD_ENET1_MDC__GPIO2_IO_2 0x0084 0x03CC 0x0000 0x5 0x0
	#define MX6SX_PAD_ENET1_MDC__USB_OTG1_PWR 0x0084 0x03CC 0x0000 0x6 0x0
	#define MX6SX_PAD_ENET1_MDC__PWM7_OUT 0x0084 0x03CC 0x0000 0x7 0x0
	#define MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x0088 0x03D0 0x0764 0x0 0x1
	#define MX6SX_PAD_ENET1_MDIO__ENET2_MDIO 0x0088 0x03D0 0x0770 0x1 0x2
	#define MX6SX_PAD_ENET1_MDIO__AUDMUX_MCLK 0x0088 0x03D0 0x0000 0x2 0x0
	#define MX6SX_PAD_ENET1_MDIO__OSC32K_32K_OUT 0x0088 0x03D0 0x0000 0x3 0x0
	#define MX6SX_PAD_ENET1_MDIO__EPIT1_OUT 0x0088 0x03D0 0x0000 0x4 0x0
	#define MX6SX_PAD_ENET1_MDIO__GPIO2_IO_3 0x0088 0x03D0 0x0000 0x5 0x0
	#define MX6SX_PAD_ENET1_MDIO__USB_OTG1_OC 0x0088 0x03D0 0x0860 0x6 0x1
	#define MX6SX_PAD_ENET1_MDIO__PWM8_OUT 0x0088 0x03D0 0x0000 0x7 0x0
	#define MX6SX_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x008C 0x03D4 0x0768 0x0 0x0
	#define MX6SX_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M 0x008C 0x03D4 0x0000 0x1 0x0
	#define MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x008C 0x03D4 0x0658 0x2 0x1
	#define MX6SX_PAD_ENET1_RX_CLK__UART1_DSR_B 0x008C 0x03D4 0x0000 0x3 0x0
	#define MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x008C 0x03D4 0x0000 0x4 0x0
	#define MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0x008C 0x03D4 0x0000 0x5 0x0
	#define MX6SX_PAD_ENET1_RX_CLK__CSI2_DATA_21 0x008C 0x03D4 0x0000 0x6 0x0
	#define MX6SX_PAD_ENET1_RX_CLK__LCDIF2_DATA_18 0x008C 0x03D4 0x0000 0x7 0x0
	#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0
	#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0
	#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0
	/*
	* SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is
	* used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a
	* PHY in RMII mode. This configuration is valid if:
	* - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set
	* - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset
	* It seems to be a silicon bug that in this configuration ENET1_TX reference
	* clock isn't provided automatically. According to i.MX6SX reference manual
	* (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it
	* should be the case.
	* So this might have unwanted side effects for other hardware units that are
	* also connected to that pin and using respective function as input (e.g.
	* UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B).
	*/
	#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1
	#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1
	#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0
	#define MX6SX_PAD_ENET1_TX_CLK__SPDIF_SR_CLK 0x0090 0x03D8 0x0000 0x4 0x0
	#define MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0x0090 0x03D8 0x0000 0x5 0x0
	#define MX6SX_PAD_ENET1_TX_CLK__CSI2_DATA_20 0x0090 0x03D8 0x0000 0x6 0x0
	#define MX6SX_PAD_ENET1_TX_CLK__LCDIF2_DATA_19 0x0090 0x03D8 0x0000 0x7 0x0
	#define MX6SX_PAD_ENET1_TX_CLK__VDEC_DEBUG_34 0x0090 0x03D8 0x0000 0x8 0x0
	#define MX6SX_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28 0x0090 0x03D8 0x0000 0x9 0x0
	#define MX6SX_PAD_ENET2_COL__ENET2_COL 0x0094 0x03DC 0x0000 0x0 0x0
	#define MX6SX_PAD_ENET2_COL__ENET1_MDC 0x0094 0x03DC 0x0000 0x1 0x0
	#define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC 0x0094 0x03DC 0x064C 0x2 0x1
	-#define MX6SX_PAD_ENET2_COL__UART1_RX 0x0094 0x03DC 0x0830 0x3 0x2
	-#define MX6SX_PAD_ENET2_COL__UART1_TX 0x0094 0x03DC 0x0000 0x3 0x0
	+#define MX6SX_PAD_ENET2_COL__UART1_DCE_RX 0x0094 0x03DC 0x0830 0x3 0x2
	+#define MX6SX_PAD_ENET2_COL__UART1_DTE_TX 0x0094 0x03DC 0x0000 0x3 0x0
	#define MX6SX_PAD_ENET2_COL__SPDIF_IN 0x0094 0x03DC 0x0824 0x4 0x3
	#define MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x0094 0x03DC 0x0000 0x5 0x0
	#define MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x0094 0x03DC 0x0624 0x6 0x1
	#define MX6SX_PAD_ENET2_COL__LCDIF2_DATA_20 0x0094 0x03DC 0x0000 0x7 0x0
	#define MX6SX_PAD_ENET2_COL__VDEC_DEBUG_33 0x0094 0x03DC 0x0000 0x8 0x0
	#define MX6SX_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27 0x0094 0x03DC 0x0000 0x9 0x0
	#define MX6SX_PAD_ENET2_CRS__ENET2_CRS 0x0098 0x03E0 0x0000 0x0 0x0
	#define MX6SX_PAD_ENET2_CRS__ENET1_MDIO 0x0098 0x03E0 0x0764 0x1 0x2
	#define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS 0x0098 0x03E0 0x0650 0x2 0x1
	-#define MX6SX_PAD_ENET2_CRS__UART1_RX 0x0098 0x03E0 0x0830 0x3 0x3
	-#define MX6SX_PAD_ENET2_CRS__UART1_TX 0x0098 0x03E0 0x0000 0x3 0x0
	+#define MX6SX_PAD_ENET2_CRS__UART1_DCE_TX 0x0098 0x03E0 0x0000 0x3 0x0
	+#define MX6SX_PAD_ENET2_CRS__UART1_DTE_RX 0x0098 0x03E0 0x0830 0x3 0x3
	#define MX6SX_PAD_ENET2_CRS__MLB_SIG 0x0098 0x03E0 0x07F0 0x4 0x1
	#define MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x0098 0x03E0 0x0000 0x5 0x0
	#define MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x0098 0x03E0 0x0628 0x6 0x1
	#define MX6SX_PAD_ENET2_CRS__LCDIF2_DATA_21 0x0098 0x03E0 0x0000 0x7 0x0
	#define MX6SX_PAD_ENET2_CRS__VDEC_DEBUG_32 0x0098 0x03E0 0x0000 0x8 0x0
	#define MX6SX_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26 0x0098 0x03E0 0x0000 0x9 0x0
	#define MX6SX_PAD_ENET2_RX_CLK__ENET2_RX_CLK 0x009C 0x03E4 0x0774 0x0 0x0
	#define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0
	#define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1
	-#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C 0x03E4 0x082C 0x3 0x2
	+#define MX6SX_PAD_ENET2_RX_CLK__UART1_DCE_RTS 0x009C 0x03E4 0x082C 0x3 0x2
	+#define MX6SX_PAD_ENET2_RX_CLK__UART1_DTE_CTS 0x009C 0x03E4 0x0000 0x3 0x0
	#define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1
	#define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0
	#define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1
	#define MX6SX_PAD_ENET2_RX_CLK__LCDIF2_DATA_22 0x009C 0x03E4 0x0000 0x7 0x0
	#define MX6SX_PAD_ENET2_RX_CLK__VDEC_DEBUG_31 0x009C 0x03E4 0x0000 0x8 0x0
	#define MX6SX_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25 0x009C 0x03E4 0x0000 0x9 0x0
	#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0
	#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1
	#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1
	-#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x0000 0x3 0x0
	+#define MX6SX_PAD_ENET2_TX_CLK__UART1_DCE_CTS 0x00A0 0x03E8 0x0000 0x3 0x0
	+#define MX6SX_PAD_ENET2_TX_CLK__UART1_DTE_RTS 0x00A0 0x03E8 0x082C 0x3 0x3
	#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1
	#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0
	#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0
	#define MX6SX_PAD_ENET2_TX_CLK__LCDIF2_DATA_23 0x00A0 0x03E8 0x0000 0x7 0x0
	#define MX6SX_PAD_ENET2_TX_CLK__VDEC_DEBUG_30 0x00A0 0x03E8 0x0000 0x8 0x0
	#define MX6SX_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 0x00A0 0x03E8 0x0000 0x9 0x0
	#define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0
	#define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0
	-#define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4 0x03EC 0x0854 0x2 0x2
	+#define MX6SX_PAD_KEY_COL0__UART6_DCE_RTS 0x00A4 0x03EC 0x0854 0x2 0x2
	+#define MX6SX_PAD_KEY_COL0__UART6_DTE_CTS 0x00A4 0x03EC 0x0000 0x2 0x0
	#define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0
	#define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0
	#define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0
	#define MX6SX_PAD_KEY_COL0__SDMA_EXT_EVENT_1 0x00A4 0x03EC 0x0820 0x6 0x1
	#define MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x00A4 0x03EC 0x0814 0x7 0x0
	#define MX6SX_PAD_KEY_COL0__VADC_DATA_0 0x00A4 0x03EC 0x0000 0x8 0x0
	#define MX6SX_PAD_KEY_COL1__KPP_COL_1 0x00A8 0x03F0 0x0000 0x0 0x0
	#define MX6SX_PAD_KEY_COL1__USDHC3_RESET_B 0x00A8 0x03F0 0x0000 0x1 0x0
	-#define MX6SX_PAD_KEY_COL1__UART6_RX 0x00A8 0x03F0 0x0858 0x2 0x2
	-#define MX6SX_PAD_KEY_COL1__UART6_TX 0x00A8 0x03F0 0x0000 0x2 0x0
	+#define MX6SX_PAD_KEY_COL1__UART6_DCE_TX 0x00A8 0x03F0 0x0000 0x2 0x0
	+#define MX6SX_PAD_KEY_COL1__UART6_DTE_RX 0x00A8 0x03F0 0x0858 0x2 0x2
	#define MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x00A8 0x03F0 0x0714 0x3 0x0
	#define MX6SX_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x00A8 0x03F0 0x0670 0x4 0x0
	#define MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x00A8 0x03F0 0x0000 0x5 0x0
	#define MX6SX_PAD_KEY_COL1__USDHC3_RESET 0x00A8 0x03F0 0x0000 0x6 0x0
	#define MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x00A8 0x03F0 0x0818 0x7 0x0
	#define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0
	#define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1
	-#define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC 0x03F4 0x084C 0x2 0x2
	+#define MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x00AC 0x03F4 0x084C 0x2 0x2
	+#define MX6SX_PAD_KEY_COL2__UART5_DTE_CTS 0x00AC 0x03F4 0x0000 0x2 0x0
	#define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0
	#define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0
	#define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0
	#define MX6SX_PAD_KEY_COL2__WEIM_DATA_30 0x00AC 0x03F4 0x0000 0x6 0x0
	#define MX6SX_PAD_KEY_COL2__ECSPI1_RDY 0x00AC 0x03F4 0x0000 0x7 0x0
	#define MX6SX_PAD_KEY_COL3__KPP_COL_3 0x00B0 0x03F8 0x0000 0x0 0x0
	#define MX6SX_PAD_KEY_COL3__USDHC4_LCTL 0x00B0 0x03F8 0x0000 0x1 0x0
	-#define MX6SX_PAD_KEY_COL3__UART5_RX 0x00B0 0x03F8 0x0850 0x2 0x2
	-#define MX6SX_PAD_KEY_COL3__UART5_TX 0x00B0 0x03F8 0x0000 0x2 0x0
	+#define MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x00B0 0x03F8 0x0000 0x2 0x0
	+#define MX6SX_PAD_KEY_COL3__UART5_DTE_RX 0x00B0 0x03F8 0x0850 0x2 0x2
	#define MX6SX_PAD_KEY_COL3__CAN2_TX 0x00B0 0x03F8 0x0000 0x3 0x0
	#define MX6SX_PAD_KEY_COL3__CANFD_TX2 0x00B0 0x03F8 0x0000 0x4 0x0
	#define MX6SX_PAD_KEY_COL3__GPIO2_IO_13 0x00B0 0x03F8 0x0000 0x5 0x0
	#define MX6SX_PAD_KEY_COL3__WEIM_DATA_28 0x00B0 0x03F8 0x0000 0x6 0x0
	#define MX6SX_PAD_KEY_COL3__ECSPI1_SS2 0x00B0 0x03F8 0x0000 0x7 0x0
	#define MX6SX_PAD_KEY_COL4__KPP_COL_4 0x00B4 0x03FC 0x0000 0x0 0x0
	#define MX6SX_PAD_KEY_COL4__ENET2_MDC 0x00B4 0x03FC 0x0000 0x1 0x0
	#define MX6SX_PAD_KEY_COL4__I2C3_SCL 0x00B4 0x03FC 0x07B8 0x2 0x2
	#define MX6SX_PAD_KEY_COL4__USDHC2_LCTL 0x00B4 0x03FC 0x0000 0x3 0x0
	#define MX6SX_PAD_KEY_COL4__AUDMUX_AUD5_RXC 0x00B4 0x03FC 0x0664 0x4 0x0
	#define MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x00B4 0x03FC 0x0000 0x5 0x0
	#define MX6SX_PAD_KEY_COL4__WEIM_CRE 0x00B4 0x03FC 0x0000 0x6 0x0
	#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0
	#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0
	#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0
	-#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0
	+#define MX6SX_PAD_KEY_ROW0__UART6_DCE_CTS 0x00B8 0x0400 0x0000 0x2 0x0
	+#define MX6SX_PAD_KEY_ROW0__UART6_DTE_RTS 0x00B8 0x0400 0x0854 0x2 0x3
	#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0
	#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0
	#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0
	#define MX6SX_PAD_KEY_ROW0__SDMA_EXT_EVENT_0 0x00B8 0x0400 0x081C 0x6 0x1
	#define MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x00B8 0x0400 0x0000 0x7 0x0
	#define MX6SX_PAD_KEY_ROW0__GPU_IDLE 0x00B8 0x0400 0x0000 0x8 0x0
	#define MX6SX_PAD_KEY_ROW1__KPP_ROW_1 0x00BC 0x0404 0x0000 0x0 0x0
	#define MX6SX_PAD_KEY_ROW1__USDHC4_VSELECT 0x00BC 0x0404 0x0000 0x1 0x0
	-#define MX6SX_PAD_KEY_ROW1__UART6_RX 0x00BC 0x0404 0x0858 0x2 0x3
	-#define MX6SX_PAD_KEY_ROW1__UART6_TX 0x00BC 0x0404 0x0000 0x2 0x0
	+#define MX6SX_PAD_KEY_ROW1__UART6_DCE_RX 0x00BC 0x0404 0x0858 0x2 0x3
	+#define MX6SX_PAD_KEY_ROW1__UART6_DTE_TX 0x00BC 0x0404 0x0000 0x2 0x0
	#define MX6SX_PAD_KEY_ROW1__ECSPI1_SS0 0x00BC 0x0404 0x071C 0x3 0x0
	#define MX6SX_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x00BC 0x0404 0x065C 0x4 0x0
	#define MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x00BC 0x0404 0x0000 0x5 0x0
	#define MX6SX_PAD_KEY_ROW1__WEIM_DATA_31 0x00BC 0x0404 0x0000 0x6 0x0
	#define MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x00BC 0x0404 0x080C 0x7 0x0
	#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0
	#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0
	#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1
	-#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0
	+#define MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x00C0 0x0408 0x0000 0x2 0x0
	+#define MX6SX_PAD_KEY_ROW2__UART5_DTE_RTS 0x00C0 0x0408 0x084C 0x2 0x3
	#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1
	#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1
	#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0
	#define MX6SX_PAD_KEY_ROW2__WEIM_DATA_29 0x00C0 0x0408 0x0000 0x6 0x0
	#define MX6SX_PAD_KEY_ROW2__ECSPI1_SS3 0x00C0 0x0408 0x0000 0x7 0x0
	#define MX6SX_PAD_KEY_ROW3__KPP_ROW_3 0x00C4 0x040C 0x0000 0x0 0x0
	#define MX6SX_PAD_KEY_ROW3__USDHC3_LCTL 0x00C4 0x040C 0x0000 0x1 0x0
	-#define MX6SX_PAD_KEY_ROW3__UART5_RX 0x00C4 0x040C 0x0850 0x2 0x3
	-#define MX6SX_PAD_KEY_ROW3__UART5_TX 0x00C4 0x040C 0x0000 0x2 0x0
	+#define MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x00C4 0x040C 0x0850 0x2 0x3
	+#define MX6SX_PAD_KEY_ROW3__UART5_DTE_TX 0x00C4 0x040C 0x0000 0x2 0x0
	#define MX6SX_PAD_KEY_ROW3__CAN2_RX 0x00C4 0x040C 0x0690 0x3 0x1
	#define MX6SX_PAD_KEY_ROW3__CANFD_RX2 0x00C4 0x040C 0x0698 0x4 0x1
	#define MX6SX_PAD_KEY_ROW3__GPIO2_IO_18 0x00C4 0x040C 0x0000 0x5 0x0
	#define MX6SX_PAD_KEY_ROW3__WEIM_DTACK_B 0x00C4 0x040C 0x0000 0x6 0x0
	#define MX6SX_PAD_KEY_ROW3__ECSPI1_SS1 0x00C4 0x040C 0x0000 0x7 0x0
	#define MX6SX_PAD_KEY_ROW4__KPP_ROW_4 0x00C8 0x0410 0x0000 0x0 0x0
	#define MX6SX_PAD_KEY_ROW4__ENET2_MDIO 0x00C8 0x0410 0x0770 0x1 0x3
	#define MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x00C8 0x0410 0x07BC 0x2 0x2
	#define MX6SX_PAD_KEY_ROW4__USDHC1_LCTL 0x00C8 0x0410 0x0000 0x3 0x0
	#define MX6SX_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS 0x00C8 0x0410 0x0668 0x4 0x0
	#define MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x00C8 0x0410 0x0000 0x5 0x0
	#define MX6SX_PAD_KEY_ROW4__WEIM_ACLK_FREERUN 0x00C8 0x0410 0x0000 0x6 0x0
	#define MX6SX_PAD_KEY_ROW4__SAI2_RX_SYNC 0x00C8 0x0410 0x0810 0x7 0x0
	#define MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x00CC 0x0414 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_CLK__LCDIF1_WR_RWN 0x00CC 0x0414 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_CLK__AUDMUX_AUD3_RXC 0x00CC 0x0414 0x0634 0x2 0x1
	#define MX6SX_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN 0x00CC 0x0414 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_CLK__CSI1_DATA_16 0x00CC 0x0414 0x06DC 0x4 0x0
	#define MX6SX_PAD_LCD1_CLK__GPIO3_IO_0 0x00CC 0x0414 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_CLK__USDHC1_WP 0x00CC 0x0414 0x0868 0x6 0x0
	#define MX6SX_PAD_LCD1_CLK__SIM_M_HADDR_16 0x00CC 0x0414 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_CLK__VADC_TEST_0 0x00CC 0x0414 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_CLK__MMDC_DEBUG_0 0x00CC 0x0414 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x00D0 0x0418 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA00__WEIM_CS1_B 0x00D0 0x0418 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA00__M4_TRACE_0 0x00D0 0x0418 0x0000 0x2 0x0
	#define MX6SX_PAD_LCD1_DATA00__KITTEN_TRACE_0 0x00D0 0x0418 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA00__CSI1_DATA_20 0x00D0 0x0418 0x06EC 0x4 0x0
	#define MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1 0x00D0 0x0418 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA00__SRC_BT_CFG_0 0x00D0 0x0418 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA00__SIM_M_HADDR_21 0x00D0 0x0418 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA00__VADC_TEST_5 0x00D0 0x0418 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA00__MMDC_DEBUG_5 0x00D0 0x0418 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x00D4 0x041C 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA01__WEIM_CS2_B 0x00D4 0x041C 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA01__M4_TRACE_1 0x00D4 0x041C 0x0000 0x2 0x0
	#define MX6SX_PAD_LCD1_DATA01__KITTEN_TRACE_1 0x00D4 0x041C 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA01__CSI1_DATA_21 0x00D4 0x041C 0x06F0 0x4 0x0
	#define MX6SX_PAD_LCD1_DATA01__GPIO3_IO_2 0x00D4 0x041C 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA01__SRC_BT_CFG_1 0x00D4 0x041C 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA01__SIM_M_HADDR_22 0x00D4 0x041C 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA01__VADC_TEST_6 0x00D4 0x041C 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA01__MMDC_DEBUG_6 0x00D4 0x041C 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x00D8 0x0420 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA02__WEIM_CS3_B 0x00D8 0x0420 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA02__M4_TRACE_2 0x00D8 0x0420 0x0000 0x2 0x0
	#define MX6SX_PAD_LCD1_DATA02__KITTEN_TRACE_2 0x00D8 0x0420 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA02__CSI1_DATA_22 0x00D8 0x0420 0x06F4 0x4 0x0
	#define MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3 0x00D8 0x0420 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA02__SRC_BT_CFG_2 0x00D8 0x0420 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA02__SIM_M_HADDR_23 0x00D8 0x0420 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA02__VADC_TEST_7 0x00D8 0x0420 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA02__MMDC_DEBUG_7 0x00D8 0x0420 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x00DC 0x0424 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0x00DC 0x0424 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA03__M4_TRACE_3 0x00DC 0x0424 0x0000 0x2 0x0
	#define MX6SX_PAD_LCD1_DATA03__KITTEN_TRACE_3 0x00DC 0x0424 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA03__CSI1_DATA_23 0x00DC 0x0424 0x06F8 0x4 0x0
	#define MX6SX_PAD_LCD1_DATA03__GPIO3_IO_4 0x00DC 0x0424 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA03__SRC_BT_CFG_3 0x00DC 0x0424 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA03__SIM_M_HADDR_24 0x00DC 0x0424 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA03__VADC_TEST_8 0x00DC 0x0424 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA03__MMDC_DEBUG_8 0x00DC 0x0424 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x00E0 0x0428 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0x00E0 0x0428 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA04__KITTEN_TRACE_4 0x00E0 0x0428 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x00E0 0x0428 0x0708 0x4 0x1
	#define MX6SX_PAD_LCD1_DATA04__GPIO3_IO_5 0x00E0 0x0428 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA04__SRC_BT_CFG_4 0x00E0 0x0428 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA04__SIM_M_HADDR_25 0x00E0 0x0428 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA04__VADC_TEST_9 0x00E0 0x0428 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA04__MMDC_DEBUG_9 0x00E0 0x0428 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x00E4 0x042C 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0x00E4 0x042C 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA05__KITTEN_TRACE_5 0x00E4 0x042C 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x00E4 0x042C 0x0700 0x4 0x1
	#define MX6SX_PAD_LCD1_DATA05__GPIO3_IO_6 0x00E4 0x042C 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA05__SRC_BT_CFG_5 0x00E4 0x042C 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA05__SIM_M_HADDR_26 0x00E4 0x042C 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA05__VADC_TEST_10 0x00E4 0x042C 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA05__MMDC_DEBUG_10 0x00E4 0x042C 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x00E8 0x0430 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA06__WEIM_EB_B_2 0x00E8 0x0430 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA06__KITTEN_TRACE_6 0x00E8 0x0430 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x00E8 0x0430 0x0704 0x4 0x1
	#define MX6SX_PAD_LCD1_DATA06__GPIO3_IO_7 0x00E8 0x0430 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA06__SRC_BT_CFG_6 0x00E8 0x0430 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA06__SIM_M_HADDR_27 0x00E8 0x0430 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA06__VADC_TEST_11 0x00E8 0x0430 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA06__MMDC_DEBUG_11 0x00E8 0x0430 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x00EC 0x0434 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA07__WEIM_EB_B_3 0x00EC 0x0434 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA07__KITTEN_TRACE_7 0x00EC 0x0434 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x00EC 0x0434 0x0000 0x4 0x0
	#define MX6SX_PAD_LCD1_DATA07__GPIO3_IO_8 0x00EC 0x0434 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA07__SRC_BT_CFG_7 0x00EC 0x0434 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA07__SIM_M_HADDR_28 0x00EC 0x0434 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA07__VADC_TEST_12 0x00EC 0x0434 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA07__MMDC_DEBUG_12 0x00EC 0x0434 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x00F0 0x0438 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0x00F0 0x0438 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA08__KITTEN_TRACE_8 0x00F0 0x0438 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x00F0 0x0438 0x06C4 0x4 0x1
	#define MX6SX_PAD_LCD1_DATA08__GPIO3_IO_9 0x00F0 0x0438 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA08__SRC_BT_CFG_8 0x00F0 0x0438 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA08__SIM_M_HADDR_29 0x00F0 0x0438 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA08__VADC_TEST_13 0x00F0 0x0438 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA08__MMDC_DEBUG_13 0x00F0 0x0438 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x00F4 0x043C 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0x00F4 0x043C 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA09__KITTEN_TRACE_9 0x00F4 0x043C 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x00F4 0x043C 0x06C0 0x4 0x1
	#define MX6SX_PAD_LCD1_DATA09__GPIO3_IO_10 0x00F4 0x043C 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA09__SRC_BT_CFG_9 0x00F4 0x043C 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA09__SIM_M_HADDR_30 0x00F4 0x043C 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA09__VADC_TEST_14 0x00F4 0x043C 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA09__MMDC_DEBUG_14 0x00F4 0x043C 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x00F8 0x0440 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0x00F8 0x0440 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA10__KITTEN_TRACE_10 0x00F8 0x0440 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x00F8 0x0440 0x06BC 0x4 0x1
	#define MX6SX_PAD_LCD1_DATA10__GPIO3_IO_11 0x00F8 0x0440 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA10__SRC_BT_CFG_10 0x00F8 0x0440 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA10__SIM_M_HADDR_31 0x00F8 0x0440 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA10__VADC_TEST_15 0x00F8 0x0440 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA10__MMDC_DEBUG_15 0x00F8 0x0440 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x00FC 0x0444 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0x00FC 0x0444 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA11__KITTEN_TRACE_11 0x00FC 0x0444 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x00FC 0x0444 0x06B8 0x4 0x1
	#define MX6SX_PAD_LCD1_DATA11__GPIO3_IO_12 0x00FC 0x0444 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA11__SRC_BT_CFG_11 0x00FC 0x0444 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA11__SIM_M_HBURST_0 0x00FC 0x0444 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA11__VADC_TEST_16 0x00FC 0x0444 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA11__MMDC_DEBUG_16 0x00FC 0x0444 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x0100 0x0448 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0x0100 0x0448 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA12__KITTEN_TRACE_12 0x0100 0x0448 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x0100 0x0448 0x06B4 0x4 0x1
	#define MX6SX_PAD_LCD1_DATA12__GPIO3_IO_13 0x0100 0x0448 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA12__SRC_BT_CFG_12 0x0100 0x0448 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA12__SIM_M_HBURST_1 0x0100 0x0448 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA12__VADC_TEST_17 0x0100 0x0448 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA12__MMDC_DEBUG_17 0x0100 0x0448 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x0104 0x044C 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0x0104 0x044C 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA13__KITTEN_TRACE_13 0x0104 0x044C 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x0104 0x044C 0x06B0 0x4 0x1
	#define MX6SX_PAD_LCD1_DATA13__GPIO3_IO_14 0x0104 0x044C 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA13__SRC_BT_CFG_13 0x0104 0x044C 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA13__SIM_M_HBURST_2 0x0104 0x044C 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA13__VADC_TEST_18 0x0104 0x044C 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA13__MMDC_DEBUG_18 0x0104 0x044C 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x0108 0x0450 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0x0108 0x0450 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA14__KITTEN_TRACE_14 0x0108 0x0450 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x0108 0x0450 0x06AC 0x4 0x1
	#define MX6SX_PAD_LCD1_DATA14__GPIO3_IO_15 0x0108 0x0450 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA14__SRC_BT_CFG_14 0x0108 0x0450 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA14__SIM_M_HMASTLOCK 0x0108 0x0450 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA14__VADC_TEST_19 0x0108 0x0450 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA14__MMDC_DEBUG_19 0x0108 0x0450 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x010C 0x0454 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0x010C 0x0454 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA15__KITTEN_TRACE_15 0x010C 0x0454 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x010C 0x0454 0x06A8 0x4 0x1
	#define MX6SX_PAD_LCD1_DATA15__GPIO3_IO_16 0x010C 0x0454 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA15__SRC_BT_CFG_15 0x010C 0x0454 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA15__SIM_M_HPROT_0 0x010C 0x0454 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA15__VDEC_DEBUG_0 0x010C 0x0454 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA15__MMDC_DEBUG_20 0x010C 0x0454 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x0110 0x0458 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0x0110 0x0458 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA16__M4_TRACE_CLK 0x0110 0x0458 0x0000 0x2 0x0
	#define MX6SX_PAD_LCD1_DATA16__KITTEN_TRACE_CLK 0x0110 0x0458 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x0110 0x0458 0x06A4 0x4 0x0
	#define MX6SX_PAD_LCD1_DATA16__GPIO3_IO_17 0x0110 0x0458 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA16__SRC_BT_CFG_24 0x0110 0x0458 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA16__SIM_M_HPROT_1 0x0110 0x0458 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA16__VDEC_DEBUG_1 0x0110 0x0458 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA16__MMDC_DEBUG_21 0x0110 0x0458 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x0114 0x045C 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0x0114 0x045C 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA17__KITTEN_TRACE_CTL 0x0114 0x045C 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x0114 0x045C 0x06A0 0x4 0x0
	#define MX6SX_PAD_LCD1_DATA17__GPIO3_IO_18 0x0114 0x045C 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA17__SRC_BT_CFG_25 0x0114 0x045C 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA17__SIM_M_HPROT_2 0x0114 0x045C 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA17__VDEC_DEBUG_2 0x0114 0x045C 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA17__MMDC_DEBUG_22 0x0114 0x045C 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x0118 0x0460 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0x0118 0x0460 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA18__M4_EVENTO 0x0118 0x0460 0x0000 0x2 0x0
	#define MX6SX_PAD_LCD1_DATA18__KITTEN_EVENTO 0x0118 0x0460 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA18__CSI1_DATA_15 0x0118 0x0460 0x06D8 0x4 0x0
	#define MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x0118 0x0460 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA18__SRC_BT_CFG_26 0x0118 0x0460 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA18__SIM_M_HPROT_3 0x0118 0x0460 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA18__VDEC_DEBUG_3 0x0118 0x0460 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA18__MMDC_DEBUG_23 0x0118 0x0460 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x011C 0x0464 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0x011C 0x0464 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA19__M4_TRACE_SWO 0x011C 0x0464 0x0000 0x2 0x0
	#define MX6SX_PAD_LCD1_DATA19__CSI1_DATA_14 0x011C 0x0464 0x06D4 0x4 0x0
	#define MX6SX_PAD_LCD1_DATA19__GPIO3_IO_20 0x011C 0x0464 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA19__SRC_BT_CFG_27 0x011C 0x0464 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA19__SIM_M_HREADYOUT 0x011C 0x0464 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA19__VDEC_DEBUG_4 0x011C 0x0464 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA19__MMDC_DEBUG_24 0x011C 0x0464 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x0120 0x0468 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0x0120 0x0468 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA20__PWM8_OUT 0x0120 0x0468 0x0000 0x2 0x0
	#define MX6SX_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT 0x0120 0x0468 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA20__CSI1_DATA_13 0x0120 0x0468 0x06D0 0x4 0x0
	#define MX6SX_PAD_LCD1_DATA20__GPIO3_IO_21 0x0120 0x0468 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA20__SRC_BT_CFG_28 0x0120 0x0468 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA20__SIM_M_HRESP 0x0120 0x0468 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA20__VDEC_DEBUG_5 0x0120 0x0468 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA20__MMDC_DEBUG_25 0x0120 0x0468 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x0124 0x046C 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0x0124 0x046C 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA21__PWM7_OUT 0x0124 0x046C 0x0000 0x2 0x0
	#define MX6SX_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT 0x0124 0x046C 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA21__CSI1_DATA_12 0x0124 0x046C 0x06CC 0x4 0x0
	#define MX6SX_PAD_LCD1_DATA21__GPIO3_IO_22 0x0124 0x046C 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA21__SRC_BT_CFG_29 0x0124 0x046C 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA21__SIM_M_HSIZE_0 0x0124 0x046C 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA21__VDEC_DEBUG_6 0x0124 0x046C 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA21__MMDC_DEBUG_26 0x0124 0x046C 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x0128 0x0470 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0x0128 0x0470 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA22__PWM6_OUT 0x0128 0x0470 0x0000 0x2 0x0
	#define MX6SX_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT 0x0128 0x0470 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA22__CSI1_DATA_11 0x0128 0x0470 0x06C8 0x4 0x0
	#define MX6SX_PAD_LCD1_DATA22__GPIO3_IO_23 0x0128 0x0470 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA22__SRC_BT_CFG_30 0x0128 0x0470 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA22__SIM_M_HSIZE_1 0x0128 0x0470 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA22__VDEC_DEBUG_7 0x0128 0x0470 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA22__MMDC_DEBUG_27 0x0128 0x0470 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x012C 0x0474 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23 0x012C 0x0474 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_DATA23__PWM5_OUT 0x012C 0x0474 0x0000 0x2 0x0
	#define MX6SX_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT 0x012C 0x0474 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_DATA23__CSI1_DATA_10 0x012C 0x0474 0x06FC 0x4 0x0
	#define MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24 0x012C 0x0474 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_DATA23__SRC_BT_CFG_31 0x012C 0x0474 0x0000 0x6 0x0
	#define MX6SX_PAD_LCD1_DATA23__SIM_M_HSIZE_2 0x012C 0x0474 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_DATA23__VDEC_DEBUG_8 0x012C 0x0474 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_DATA23__MMDC_DEBUG_28 0x012C 0x0474 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x0130 0x0478 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_RD_E 0x0130 0x0478 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC 0x0130 0x0478 0x063C 0x2 0x1
	#define MX6SX_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN 0x0130 0x0478 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_ENABLE__CSI1_DATA_17 0x0130 0x0478 0x06E0 0x4 0x0
	#define MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x0130 0x0478 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_ENABLE__USDHC1_CD_B 0x0130 0x0478 0x0864 0x6 0x0
	#define MX6SX_PAD_LCD1_ENABLE__SIM_M_HADDR_17 0x0130 0x0478 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_ENABLE__VADC_TEST_1 0x0130 0x0478 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_ENABLE__MMDC_DEBUG_1 0x0130 0x0478 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x0134 0x047C 0x07E0 0x0 0x0
	#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_RS 0x0134 0x047C 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD 0x0134 0x047C 0x0630 0x2 0x1
	#define MX6SX_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN 0x0134 0x047C 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_HSYNC__CSI1_DATA_18 0x0134 0x047C 0x06E4 0x4 0x0
	#define MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x0134 0x047C 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_HSYNC__USDHC2_WP 0x0134 0x047C 0x0870 0x6 0x0
	#define MX6SX_PAD_LCD1_HSYNC__SIM_M_HADDR_18 0x0134 0x047C 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_HSYNC__VADC_TEST_2 0x0134 0x047C 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_HSYNC__MMDC_DEBUG_2 0x0134 0x047C 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_RESET__LCDIF1_RESET 0x0138 0x0480 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_RESET__LCDIF1_CS 0x0138 0x0480 0x0000 0x1 0x0
	#define MX6SX_PAD_LCD1_RESET__AUDMUX_AUD3_RXD 0x0138 0x0480 0x062C 0x2 0x1
	#define MX6SX_PAD_LCD1_RESET__KITTEN_EVENTI 0x0138 0x0480 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_RESET__M4_EVENTI 0x0138 0x0480 0x0000 0x4 0x0
	#define MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x0138 0x0480 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_RESET__CCM_PMIC_RDY 0x0138 0x0480 0x069C 0x6 0x0
	#define MX6SX_PAD_LCD1_RESET__SIM_M_HADDR_20 0x0138 0x0480 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_RESET__VADC_TEST_4 0x0138 0x0480 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_RESET__MMDC_DEBUG_4 0x0138 0x0480 0x0000 0x9 0x0
	#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x013C 0x0484 0x0000 0x0 0x0
	#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_BUSY 0x013C 0x0484 0x07E0 0x1 0x1
	#define MX6SX_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS 0x013C 0x0484 0x0640 0x2 0x1
	#define MX6SX_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN 0x013C 0x0484 0x0000 0x3 0x0
	#define MX6SX_PAD_LCD1_VSYNC__CSI1_DATA_19 0x013C 0x0484 0x06E8 0x4 0x0
	#define MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x013C 0x0484 0x0000 0x5 0x0
	#define MX6SX_PAD_LCD1_VSYNC__USDHC2_CD_B 0x013C 0x0484 0x086C 0x6 0x0
	#define MX6SX_PAD_LCD1_VSYNC__SIM_M_HADDR_19 0x013C 0x0484 0x0000 0x7 0x0
	#define MX6SX_PAD_LCD1_VSYNC__VADC_TEST_3 0x013C 0x0484 0x0000 0x8 0x0
	#define MX6SX_PAD_LCD1_VSYNC__MMDC_DEBUG_3 0x013C 0x0484 0x0000 0x9 0x0
	#define MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0x0140 0x0488 0x0000 0x0 0x0
	#define MX6SX_PAD_NAND_ALE__I2C3_SDA 0x0140 0x0488 0x07BC 0x1 0x0
	#define MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x0140 0x0488 0x0000 0x2 0x0
	#define MX6SX_PAD_NAND_ALE__ECSPI2_SS0 0x0140 0x0488 0x072C 0x3 0x0
	#define MX6SX_PAD_NAND_ALE__ESAI_TX3_RX2 0x0140 0x0488 0x079C 0x4 0x0
	#define MX6SX_PAD_NAND_ALE__GPIO4_IO_0 0x0140 0x0488 0x0000 0x5 0x0
	#define MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0x0140 0x0488 0x0000 0x6 0x0
	#define MX6SX_PAD_NAND_ALE__TPSMP_HDATA_0 0x0140 0x0488 0x0000 0x7 0x0
	#define MX6SX_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN 0x0140 0x0488 0x0000 0x8 0x0
	#define MX6SX_PAD_NAND_ALE__SDMA_DEBUG_PC_12 0x0140 0x0488 0x0000 0x9 0x0
	#define MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0144 0x048C 0x0000 0x0 0x0
	#define MX6SX_PAD_NAND_CE0_B__USDHC2_VSELECT 0x0144 0x048C 0x0000 0x1 0x0
	#define MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x0144 0x048C 0x0000 0x2 0x0
	#define MX6SX_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC 0x0144 0x048C 0x0654 0x3 0x0
	#define MX6SX_PAD_NAND_CE0_B__ESAI_TX_CLK 0x0144 0x048C 0x078C 0x4 0x0
	#define MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x0144 0x048C 0x0000 0x5 0x0
	#define MX6SX_PAD_NAND_CE0_B__WEIM_LBA_B 0x0144 0x048C 0x0000 0x6 0x0
	#define MX6SX_PAD_NAND_CE0_B__TPSMP_HDATA_3 0x0144 0x048C 0x0000 0x7 0x0
	#define MX6SX_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ 0x0144 0x048C 0x0000 0x8 0x0
	#define MX6SX_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9 0x0144 0x048C 0x0000 0x9 0x0
	#define MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0148 0x0490 0x0000 0x0 0x0
	#define MX6SX_PAD_NAND_CE1_B__USDHC3_RESET_B 0x0148 0x0490 0x0000 0x1 0x0
	#define MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x0148 0x0490 0x0000 0x2 0x0
	#define MX6SX_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD 0x0148 0x0490 0x0648 0x3 0x0
	#define MX6SX_PAD_NAND_CE1_B__ESAI_TX0 0x0148 0x0490 0x0790 0x4 0x0
	#define MX6SX_PAD_NAND_CE1_B__GPIO4_IO_2 0x0148 0x0490 0x0000 0x5 0x0
	#define MX6SX_PAD_NAND_CE1_B__WEIM_OE 0x0148 0x0490 0x0000 0x6 0x0
	#define MX6SX_PAD_NAND_CE1_B__TPSMP_HDATA_4 0x0148 0x0490 0x0000 0x7 0x0
	#define MX6SX_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE 0x0148 0x0490 0x0000 0x8 0x0
	#define MX6SX_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 0x0148 0x0490 0x0000 0x9 0x0
	#define MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0x014C 0x0494 0x0000 0x0 0x0
	#define MX6SX_PAD_NAND_CLE__I2C3_SCL 0x014C 0x0494 0x07B8 0x1 0x0
	#define MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x014C 0x0494 0x0000 0x2 0x0
	#define MX6SX_PAD_NAND_CLE__ECSPI2_SCLK 0x014C 0x0494 0x0720 0x3 0x0
	#define MX6SX_PAD_NAND_CLE__ESAI_TX2_RX3 0x014C 0x0494 0x0798 0x4 0x0
	#define MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x014C 0x0494 0x0000 0x5 0x0
	#define MX6SX_PAD_NAND_CLE__WEIM_BCLK 0x014C 0x0494 0x0000 0x6 0x0
	#define MX6SX_PAD_NAND_CLE__TPSMP_CLK 0x014C 0x0494 0x0000 0x7 0x0
	#define MX6SX_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP 0x014C 0x0494 0x0000 0x8 0x0
	#define MX6SX_PAD_NAND_CLE__SDMA_DEBUG_PC_13 0x014C 0x0494 0x0000 0x9 0x0
	#define MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0x0150 0x0498 0x0000 0x0 0x0
	#define MX6SX_PAD_NAND_DATA00__USDHC1_DATA4 0x0150 0x0498 0x0000 0x1 0x0
	#define MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x0150 0x0498 0x0000 0x2 0x0
	#define MX6SX_PAD_NAND_DATA00__ECSPI5_MISO 0x0150 0x0498 0x0754 0x3 0x0
	#define MX6SX_PAD_NAND_DATA00__ESAI_RX_CLK 0x0150 0x0498 0x0788 0x4 0x0
	#define MX6SX_PAD_NAND_DATA00__GPIO4_IO_4 0x0150 0x0498 0x0000 0x5 0x0
	#define MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0x0150 0x0498 0x0000 0x6 0x0
	#define MX6SX_PAD_NAND_DATA00__TPSMP_HDATA_7 0x0150 0x0498 0x0000 0x7 0x0
	#define MX6SX_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET 0x0150 0x0498 0x0000 0x8 0x0
	#define MX6SX_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5 0x0150 0x0498 0x0000 0x9 0x0
	#define MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0x0154 0x049C 0x0000 0x0 0x0
	#define MX6SX_PAD_NAND_DATA01__USDHC1_DATA5 0x0154 0x049C 0x0000 0x1 0x0
	#define MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x0154 0x049C 0x0000 0x2 0x0
	#define MX6SX_PAD_NAND_DATA01__ECSPI5_MOSI 0x0154 0x049C 0x0758 0x3 0x0
	#define MX6SX_PAD_NAND_DATA01__ESAI_RX_FS 0x0154 0x049C 0x0778 0x4 0x0
	#define MX6SX_PAD_NAND_DATA01__GPIO4_IO_5 0x0154 0x049C 0x0000 0x5 0x0
	#define MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0x0154 0x049C 0x0000 0x6 0x0
	#define MX6SX_PAD_NAND_DATA01__TPSMP_HDATA_8 0x0154 0x049C 0x0000 0x7 0x0
	#define MX6SX_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD 0x0154 0x049C 0x0000 0x8 0x0
	#define MX6SX_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4 0x0154 0x049C 0x0000 0x9 0x0
	#define MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0x0158 0x04A0 0x0000 0x0 0x0
	#define MX6SX_PAD_NAND_DATA02__USDHC1_DATA6 0x0158 0x04A0 0x0000 0x1 0x0
	#define MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x0158 0x04A0 0x0000 0x2 0x0
	#define MX6SX_PAD_NAND_DATA02__ECSPI5_SCLK 0x0158 0x04A0 0x0750 0x3 0x0
	#define MX6SX_PAD_NAND_DATA02__ESAI_TX_HF_CLK 0x0158 0x04A0 0x0784 0x4 0x0
	#define MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x0158 0x04A0 0x0000 0x5 0x0
	#define MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0x0158 0x04A0 0x0000 0x6 0x0
	#define MX6SX_PAD_NAND_DATA02__TPSMP_HDATA_9 0x0158 0x04A0 0x0000 0x7 0x0
	#define MX6SX_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV 0x0158 0x04A0 0x0000 0x8 0x0
	#define MX6SX_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3 0x0158 0x04A0 0x0000 0x9 0x0
	#define MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0x015C 0x04A4 0x0000 0x0 0x0
	#define MX6SX_PAD_NAND_DATA03__USDHC1_DATA7 0x015C 0x04A4 0x0000 0x1 0x0
	#define MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x015C 0x04A4 0x0000 0x2 0x0
	#define MX6SX_PAD_NAND_DATA03__ECSPI5_SS0 0x015C 0x04A4 0x075C 0x3 0x0
	#define MX6SX_PAD_NAND_DATA03__ESAI_RX_HF_CLK 0x015C 0x04A4 0x0780 0x4 0x0
	#define MX6SX_PAD_NAND_DATA03__GPIO4_IO_7 0x015C 0x04A4 0x0000 0x5 0x0
	#define MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0x015C 0x04A4 0x0000 0x6 0x0
	#define MX6SX_PAD_NAND_DATA03__TPSMP_HDATA_10 0x015C 0x04A4 0x0000 0x7 0x0
	#define MX6SX_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH 0x015C 0x04A4 0x0000 0x8 0x0
	#define MX6SX_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6 0x015C 0x04A4 0x0000 0x9 0x0
	#define MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0x0160 0x04A8 0x0000 0x0 0x0
	#define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0
	#define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0
	-#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x0160 0x04A8 0x083C 0x3 0x0
	+#define MX6SX_PAD_NAND_DATA04__UART3_DCE_RTS 0x0160 0x04A8 0x083C 0x3 0x0
	+#define MX6SX_PAD_NAND_DATA04__UART3_DTE_CTS 0x0160 0x04A8 0x0000 0x3 0x0
	#define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0
	#define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0
	#define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0
	#define MX6SX_PAD_NAND_DATA04__TPSMP_HDATA_11 0x0160 0x04A8 0x0000 0x7 0x0
	#define MX6SX_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH 0x0160 0x04A8 0x0000 0x8 0x0
	#define MX6SX_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0 0x0160 0x04A8 0x0000 0x9 0x0
	#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0
	#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0
	#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0
	-#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x0000 0x3 0x0
	+#define MX6SX_PAD_NAND_DATA05__UART3_DCE_CTS 0x0164 0x04AC 0x0000 0x3 0x0
	+#define MX6SX_PAD_NAND_DATA05__UART3_DTE_RTS 0x0164 0x04AC 0x083C 0x3 0x1
	#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0
	#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0
	#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0
	#define MX6SX_PAD_NAND_DATA05__TPSMP_HDATA_12 0x0164 0x04AC 0x0000 0x7 0x0
	#define MX6SX_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET 0x0164 0x04AC 0x0000 0x8 0x0
	#define MX6SX_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1 0x0164 0x04AC 0x0000 0x9 0x0
	#define MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0x0168 0x04B0 0x0000 0x0 0x0
	#define MX6SX_PAD_NAND_DATA06__USDHC2_DATA6 0x0168 0x04B0 0x0000 0x1 0x0
	#define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B 0x0168 0x04B0 0x0000 0x2 0x0
	-#define MX6SX_PAD_NAND_DATA06__UART3_RX 0x0168 0x04B0 0x0840 0x3 0x0
	-#define MX6SX_PAD_NAND_DATA06__UART3_TX 0x0168 0x04B0 0x0000 0x3 0x0
	+#define MX6SX_PAD_NAND_DATA06__UART3_DCE_RX 0x0168 0x04B0 0x0840 0x3 0x0
	+#define MX6SX_PAD_NAND_DATA06__UART3_DTE_TX 0x0168 0x04B0 0x0000 0x3 0x0
	#define MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x0168 0x04B0 0x0000 0x4 0x0
	#define MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x0168 0x04B0 0x0000 0x5 0x0
	#define MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0x0168 0x04B0 0x0000 0x6 0x0
	#define MX6SX_PAD_NAND_DATA06__TPSMP_HDATA_13 0x0168 0x04B0 0x0000 0x7 0x0
	#define MX6SX_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD 0x0168 0x04B0 0x0000 0x8 0x0
	#define MX6SX_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2 0x0168 0x04B0 0x0000 0x9 0x0
	#define MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0x016C 0x04B4 0x0000 0x0 0x0
	#define MX6SX_PAD_NAND_DATA07__USDHC2_DATA7 0x016C 0x04B4 0x0000 0x1 0x0
	#define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS 0x016C 0x04B4 0x0000 0x2 0x0
	-#define MX6SX_PAD_NAND_DATA07__UART3_RX 0x016C 0x04B4 0x0840 0x3 0x1
	-#define MX6SX_PAD_NAND_DATA07__UART3_TX 0x016C 0x04B4 0x0000 0x3 0x0
	+#define MX6SX_PAD_NAND_DATA07__UART3_DCE_TX 0x016C 0x04B4 0x0000 0x3 0x0
	+#define MX6SX_PAD_NAND_DATA07__UART3_DTE_RX 0x016C 0x04B4 0x0840 0x3 0x1
	#define MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x016C 0x04B4 0x0000 0x4 0x0
	#define MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0x016C 0x04B4 0x0000 0x5 0x0
	#define MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0x016C 0x04B4 0x0000 0x6 0x0
	#define MX6SX_PAD_NAND_DATA07__TPSMP_HDATA_14 0x016C 0x04B4 0x0000 0x7 0x0
	#define MX6SX_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD 0x016C 0x04B4 0x0000 0x8 0x0
	#define MX6SX_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3 0x016C 0x04B4 0x0000 0x9 0x0
	#define MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0x0170 0x04B8 0x0000 0x0 0x0
	#define MX6SX_PAD_NAND_RE_B__USDHC2_RESET_B 0x0170 0x04B8 0x0000 0x1 0x0
	#define MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x0170 0x04B8 0x0000 0x2 0x0
	#define MX6SX_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS 0x0170 0x04B8 0x0658 0x3 0x0
	#define MX6SX_PAD_NAND_RE_B__ESAI_TX_FS 0x0170 0x04B8 0x077C 0x4 0x0
	#define MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x0170 0x04B8 0x0000 0x5 0x0
	#define MX6SX_PAD_NAND_RE_B__WEIM_RW 0x0170 0x04B8 0x0000 0x6 0x0
	#define MX6SX_PAD_NAND_RE_B__TPSMP_HDATA_5 0x0170 0x04B8 0x0000 0x7 0x0
	#define MX6SX_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD 0x0170 0x04B8 0x0000 0x8 0x0
	#define MX6SX_PAD_NAND_RE_B__SDMA_DEBUG_PC_7 0x0170 0x04B8 0x0000 0x9 0x0
	#define MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0x0174 0x04BC 0x0000 0x0 0x0
	#define MX6SX_PAD_NAND_READY_B__USDHC1_VSELECT 0x0174 0x04BC 0x0000 0x1 0x0
	#define MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x0174 0x04BC 0x0000 0x2 0x0
	#define MX6SX_PAD_NAND_READY_B__ECSPI2_MISO 0x0174 0x04BC 0x0724 0x3 0x0
	#define MX6SX_PAD_NAND_READY_B__ESAI_TX1 0x0174 0x04BC 0x0794 0x4 0x0
	#define MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x0174 0x04BC 0x0000 0x5 0x0
	#define MX6SX_PAD_NAND_READY_B__WEIM_EB_B_1 0x0174 0x04BC 0x0000 0x6 0x0
	#define MX6SX_PAD_NAND_READY_B__TPSMP_HDATA_2 0x0174 0x04BC 0x0000 0x7 0x0
	#define MX6SX_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN 0x0174 0x04BC 0x0000 0x8 0x0
	#define MX6SX_PAD_NAND_READY_B__SDMA_DEBUG_PC_10 0x0174 0x04BC 0x0000 0x9 0x0
	#define MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0x0178 0x04C0 0x0000 0x0 0x0
	#define MX6SX_PAD_NAND_WE_B__USDHC4_VSELECT 0x0178 0x04C0 0x0000 0x1 0x0
	#define MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x0178 0x04C0 0x0000 0x2 0x0
	#define MX6SX_PAD_NAND_WE_B__AUDMUX_AUD4_RXD 0x0178 0x04C0 0x0644 0x3 0x0
	#define MX6SX_PAD_NAND_WE_B__ESAI_TX5_RX0 0x0178 0x04C0 0x07A4 0x4 0x0
	#define MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x0178 0x04C0 0x0000 0x5 0x0
	#define MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0x0178 0x04C0 0x0000 0x6 0x0
	#define MX6SX_PAD_NAND_WE_B__TPSMP_HDATA_6 0x0178 0x04C0 0x0000 0x7 0x0
	#define MX6SX_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV 0x0178 0x04C0 0x0000 0x8 0x0
	#define MX6SX_PAD_NAND_WE_B__SDMA_DEBUG_PC_6 0x0178 0x04C0 0x0000 0x9 0x0
	#define MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0x017C 0x04C4 0x0000 0x0 0x0
	#define MX6SX_PAD_NAND_WP_B__USDHC1_RESET_B 0x017C 0x04C4 0x0000 0x1 0x0
	#define MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x017C 0x04C4 0x0000 0x2 0x0
	#define MX6SX_PAD_NAND_WP_B__ECSPI2_MOSI 0x017C 0x04C4 0x0728 0x3 0x0
	#define MX6SX_PAD_NAND_WP_B__ESAI_TX4_RX1 0x017C 0x04C4 0x07A0 0x4 0x0
	#define MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x017C 0x04C4 0x0000 0x5 0x0
	#define MX6SX_PAD_NAND_WP_B__WEIM_EB_B_0 0x017C 0x04C4 0x0000 0x6 0x0
	#define MX6SX_PAD_NAND_WP_B__TPSMP_HDATA_1 0x017C 0x04C4 0x0000 0x7 0x0
	#define MX6SX_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE 0x017C 0x04C4 0x0000 0x8 0x0
	#define MX6SX_PAD_NAND_WP_B__SDMA_DEBUG_PC_11 0x017C 0x04C4 0x0000 0x9 0x0
	#define MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x0180 0x04C8 0x0000 0x0 0x0
	#define MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x0180 0x04C8 0x085C 0x1 0x2
	#define MX6SX_PAD_QSPI1A_DATA0__ECSPI1_MOSI 0x0180 0x04C8 0x0718 0x2 0x1
	#define MX6SX_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 0x0180 0x04C8 0x07A0 0x3 0x2
	#define MX6SX_PAD_QSPI1A_DATA0__CSI1_DATA_14 0x0180 0x04C8 0x06D4 0x4 0x1
	#define MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x0180 0x04C8 0x0000 0x5 0x0
	#define MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x0180 0x04C8 0x0000 0x6 0x0
	#define MX6SX_PAD_QSPI1A_DATA0__SIM_M_HADDR_3 0x0180 0x04C8 0x0000 0x7 0x0
	#define MX6SX_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3 0x0180 0x04C8 0x0000 0x9 0x0
	#define MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x0184 0x04CC 0x0000 0x0 0x0
	#define MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x0184 0x04CC 0x0624 0x1 0x2
	#define MX6SX_PAD_QSPI1A_DATA1__ECSPI1_MISO 0x0184 0x04CC 0x0714 0x2 0x1
	#define MX6SX_PAD_QSPI1A_DATA1__ESAI_TX1 0x0184 0x04CC 0x0794 0x3 0x2
	#define MX6SX_PAD_QSPI1A_DATA1__CSI1_DATA_13 0x0184 0x04CC 0x06D0 0x4 0x1
	#define MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x0184 0x04CC 0x0000 0x5 0x0
	#define MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x0184 0x04CC 0x0000 0x6 0x0
	#define MX6SX_PAD_QSPI1A_DATA1__SIM_M_HADDR_4 0x0184 0x04CC 0x0000 0x7 0x0
	#define MX6SX_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0 0x0184 0x04CC 0x0000 0x9 0x0
	#define MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x0188 0x04D0 0x0000 0x0 0x0
	#define MX6SX_PAD_QSPI1A_DATA2__USB_OTG1_PWR 0x0188 0x04D0 0x0000 0x1 0x0
	#define MX6SX_PAD_QSPI1A_DATA2__ECSPI5_SS1 0x0188 0x04D0 0x0000 0x2 0x0
	#define MX6SX_PAD_QSPI1A_DATA2__ESAI_TX_CLK 0x0188 0x04D0 0x078C 0x3 0x2
	#define MX6SX_PAD_QSPI1A_DATA2__CSI1_DATA_12 0x0188 0x04D0 0x06CC 0x4 0x1
	#define MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x0188 0x04D0 0x0000 0x5 0x0
	#define MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x0188 0x04D0 0x0000 0x6 0x0
	#define MX6SX_PAD_QSPI1A_DATA2__SIM_M_HADDR_6 0x0188 0x04D0 0x0000 0x7 0x0
	#define MX6SX_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1 0x0188 0x04D0 0x0000 0x9 0x0
	#define MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x018C 0x04D4 0x0000 0x0 0x0
	#define MX6SX_PAD_QSPI1A_DATA3__USB_OTG1_OC 0x018C 0x04D4 0x0860 0x1 0x2
	#define MX6SX_PAD_QSPI1A_DATA3__ECSPI5_SS2 0x018C 0x04D4 0x0000 0x2 0x0
	#define MX6SX_PAD_QSPI1A_DATA3__ESAI_TX0 0x018C 0x04D4 0x0790 0x3 0x2
	#define MX6SX_PAD_QSPI1A_DATA3__CSI1_DATA_11 0x018C 0x04D4 0x06C8 0x4 0x1
	#define MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x018C 0x04D4 0x0000 0x5 0x0
	#define MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x018C 0x04D4 0x0000 0x6 0x0
	#define MX6SX_PAD_QSPI1A_DATA3__SIM_M_HADDR_7 0x018C 0x04D4 0x0000 0x7 0x0
	#define MX6SX_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2 0x018C 0x04D4 0x0000 0x9 0x0
	#define MX6SX_PAD_QSPI1A_DQS__QSPI1_A_DQS 0x0190 0x04D8 0x0000 0x0 0x0
	#define MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x0190 0x04D8 0x0000 0x1 0x0
	#define MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x0190 0x04D8 0x0000 0x2 0x0
	#define MX6SX_PAD_QSPI1A_DQS__ECSPI5_MOSI 0x0190 0x04D8 0x0758 0x3 0x1
	#define MX6SX_PAD_QSPI1A_DQS__CSI1_DATA_15 0x0190 0x04D8 0x06D8 0x4 0x1
	#define MX6SX_PAD_QSPI1A_DQS__GPIO4_IO_20 0x0190 0x04D8 0x0000 0x5 0x0
	#define MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x0190 0x04D8 0x0000 0x6 0x0
	#define MX6SX_PAD_QSPI1A_DQS__SIM_M_HADDR_13 0x0190 0x04D8 0x0000 0x7 0x0
	#define MX6SX_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4 0x0190 0x04D8 0x0000 0x9 0x0
	#define MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x0194 0x04DC 0x0000 0x0 0x0
	#define MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x0194 0x04DC 0x0628 0x1 0x2
	#define MX6SX_PAD_QSPI1A_SCLK__ECSPI1_SCLK 0x0194 0x04DC 0x0710 0x2 0x1
	#define MX6SX_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 0x0194 0x04DC 0x0798 0x3 0x2
	#define MX6SX_PAD_QSPI1A_SCLK__CSI1_DATA_1 0x0194 0x04DC 0x06A4 0x4 0x1
	#define MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 0x0194 0x04DC 0x0000 0x5 0x0
	#define MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x0194 0x04DC 0x0000 0x6 0x0
	#define MX6SX_PAD_QSPI1A_SCLK__SIM_M_HADDR_0 0x0194 0x04DC 0x0000 0x7 0x0
	#define MX6SX_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5 0x0194 0x04DC 0x0000 0x9 0x0
	#define MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x0198 0x04E0 0x0000 0x0 0x0
	#define MX6SX_PAD_QSPI1A_SS0_B__USB_OTG2_PWR 0x0198 0x04E0 0x0000 0x1 0x0
	#define MX6SX_PAD_QSPI1A_SS0_B__ECSPI1_SS0 0x0198 0x04E0 0x071C 0x2 0x1
	#define MX6SX_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 0x0198 0x04E0 0x079C 0x3 0x2
	#define MX6SX_PAD_QSPI1A_SS0_B__CSI1_DATA_0 0x0198 0x04E0 0x06A0 0x4 0x1
	#define MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x0198 0x04E0 0x0000 0x5 0x0
	#define MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x0198 0x04E0 0x0000 0x6 0x0
	#define MX6SX_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1 0x0198 0x04E0 0x0000 0x7 0x0
	#define MX6SX_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4 0x0198 0x04E0 0x0000 0x9 0x0
	#define MX6SX_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B 0x019C 0x04E4 0x0000 0x0 0x0
	#define MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x019C 0x04E4 0x068C 0x1 0x2
	#define MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x019C 0x04E4 0x0694 0x2 0x2
	#define MX6SX_PAD_QSPI1A_SS1_B__ECSPI5_MISO 0x019C 0x04E4 0x0754 0x3 0x1
	#define MX6SX_PAD_QSPI1A_SS1_B__CSI1_DATA_10 0x019C 0x04E4 0x06FC 0x4 0x1
	#define MX6SX_PAD_QSPI1A_SS1_B__GPIO4_IO_23 0x019C 0x04E4 0x0000 0x5 0x0
	#define MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x019C 0x04E4 0x0000 0x6 0x0
	#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0
	#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0
	#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0
	-#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x0000 0x1 0x0
	+#define MX6SX_PAD_QSPI1B_DATA0__UART3_DCE_CTS 0x01A0 0x04E8 0x0000 0x1 0x0
	+#define MX6SX_PAD_QSPI1B_DATA0__UART3_DTE_RTS 0x01A0 0x04E8 0x083C 0x1 0x4
	#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1
	#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2
	#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1
	#define MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x01A0 0x04E8 0x0000 0x5 0x0
	#define MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x01A0 0x04E8 0x0000 0x6 0x0
	#define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0
	#define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0
	-#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B 0x01A4 0x04EC 0x083C 0x1 0x5
	+#define MX6SX_PAD_QSPI1B_DATA1__UART3_DCE_RTS 0x01A4 0x04EC 0x083C 0x1 0x5
	+#define MX6SX_PAD_QSPI1B_DATA1__UART3_DTE_CTS 0x01A4 0x04EC 0x0000 0x1 0x0
	#define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1
	#define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2
	#define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1
	#define MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x01A4 0x04EC 0x0000 0x5 0x0
	#define MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x01A4 0x04EC 0x0000 0x6 0x0
	#define MX6SX_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 0x01A4 0x04EC 0x0000 0x7 0x0
	#define MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x01A8 0x04F0 0x0000 0x0 0x0
	#define MX6SX_PAD_QSPI1B_DATA2__I2C2_SDA 0x01A8 0x04F0 0x07B4 0x1 0x2
	#define MX6SX_PAD_QSPI1B_DATA2__ECSPI5_RDY 0x01A8 0x04F0 0x0000 0x2 0x0
	#define MX6SX_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 0x01A8 0x04F0 0x07A4 0x3 0x2
	#define MX6SX_PAD_QSPI1B_DATA2__CSI1_DATA_20 0x01A8 0x04F0 0x06EC 0x4 0x1
	#define MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0x01A8 0x04F0 0x0000 0x5 0x0
	#define MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x01A8 0x04F0 0x0000 0x6 0x0
	#define MX6SX_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 0x01A8 0x04F0 0x0000 0x7 0x0
	#define MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x01AC 0x04F4 0x0000 0x0 0x0
	#define MX6SX_PAD_QSPI1B_DATA3__I2C2_SCL 0x01AC 0x04F4 0x07B0 0x1 0x2
	#define MX6SX_PAD_QSPI1B_DATA3__ECSPI5_SS3 0x01AC 0x04F4 0x0000 0x2 0x0
	#define MX6SX_PAD_QSPI1B_DATA3__ESAI_TX_FS 0x01AC 0x04F4 0x077C 0x3 0x2
	#define MX6SX_PAD_QSPI1B_DATA3__CSI1_DATA_19 0x01AC 0x04F4 0x06E8 0x4 0x1
	#define MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x01AC 0x04F4 0x0000 0x5 0x0
	#define MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x01AC 0x04F4 0x0000 0x6 0x0
	#define MX6SX_PAD_QSPI1B_DATA3__SIM_M_HADDR_2 0x01AC 0x04F4 0x0000 0x7 0x0
	#define MX6SX_PAD_QSPI1B_DQS__QSPI1_B_DQS 0x01B0 0x04F8 0x0000 0x0 0x0
	#define MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x01B0 0x04F8 0x0000 0x1 0x0
	#define MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x01B0 0x04F8 0x0000 0x2 0x0
	#define MX6SX_PAD_QSPI1B_DQS__ECSPI5_SS0 0x01B0 0x04F8 0x075C 0x3 0x1
	#define MX6SX_PAD_QSPI1B_DQS__CSI1_DATA_23 0x01B0 0x04F8 0x06F8 0x4 0x1
	#define MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28 0x01B0 0x04F8 0x0000 0x5 0x0
	#define MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x01B0 0x04F8 0x0000 0x6 0x0
	#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0
	#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0
	-#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x01B4 0x04FC 0x0840 0x1 0x4
	-#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX 0x01B4 0x04FC 0x0000 0x0 0x0
	+#define MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x01B4 0x04FC 0x0840 0x1 0x4
	+#define MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX 0x01B4 0x04FC 0x0000 0x0 0x0
	#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1
	#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2
	#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1
	#define MX6SX_PAD_QSPI1B_SCLK__GPIO4_IO_29 0x01B4 0x04FC 0x0000 0x5 0x0
	#define MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x01B4 0x04FC 0x0000 0x6 0x0
	#define MX6SX_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 0x01B4 0x04FC 0x0000 0x7 0x0
	#define MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x01B8 0x0500 0x0000 0x0 0x0
	-#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX 0x01B8 0x0500 0x0840 0x1 0x5
	-#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x01B8 0x0500 0x0000 0x1 0x0
	+#define MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x01B8 0x0500 0x0000 0x1 0x0
	+#define MX6SX_PAD_QSPI1B_SS0_B__UART3_DTE_RX 0x01B8 0x0500 0x0840 0x1 0x5
	#define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0 0x01B8 0x0500 0x073C 0x2 0x1
	#define MX6SX_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK 0x01B8 0x0500 0x0784 0x3 0x3
	#define MX6SX_PAD_QSPI1B_SS0_B__CSI1_DATA_17 0x01B8 0x0500 0x06E0 0x4 0x1
	#define MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x01B8 0x0500 0x0000 0x5 0x0
	#define MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x01B8 0x0500 0x0000 0x6 0x0
	#define MX6SX_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10 0x01B8 0x0500 0x0000 0x7 0x0
	#define MX6SX_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B 0x01BC 0x0504 0x0000 0x0 0x0
	#define MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x01BC 0x0504 0x0690 0x1 0x2
	#define MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x01BC 0x0504 0x0698 0x2 0x2
	#define MX6SX_PAD_QSPI1B_SS1_B__ECSPI5_SCLK 0x01BC 0x0504 0x0750 0x3 0x1
	#define MX6SX_PAD_QSPI1B_SS1_B__CSI1_DATA_18 0x01BC 0x0504 0x06E4 0x4 0x1
	#define MX6SX_PAD_QSPI1B_SS1_B__GPIO4_IO_31 0x01BC 0x0504 0x0000 0x5 0x0
	#define MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x01BC 0x0504 0x0000 0x6 0x0
	#define MX6SX_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14 0x01BC 0x0504 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x01C0 0x0508 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII1_RD0__GPIO5_IO_0 0x01C0 0x0508 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII1_RD0__CSI2_DATA_10 0x01C0 0x0508 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII1_RD0__ANATOP_TESTI_0 0x01C0 0x0508 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER 0x01C0 0x0508 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0 0x01C0 0x0508 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x01C4 0x050C 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII1_RD1__GPIO5_IO_1 0x01C4 0x050C 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII1_RD1__CSI2_DATA_11 0x01C4 0x050C 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII1_RD1__ANATOP_TESTI_1 0x01C4 0x050C 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER 0x01C4 0x050C 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1 0x01C4 0x050C 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x01C8 0x0510 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII1_RD2__GPIO5_IO_2 0x01C8 0x0510 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII1_RD2__CSI2_DATA_12 0x01C8 0x0510 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII1_RD2__ANATOP_TESTI_2 0x01C8 0x0510 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER 0x01C8 0x0510 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2 0x01C8 0x0510 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x01CC 0x0514 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII1_RD3__GPIO5_IO_3 0x01CC 0x0514 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII1_RD3__CSI2_DATA_13 0x01CC 0x0514 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII1_RD3__ANATOP_TESTI_3 0x01CC 0x0514 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER 0x01CC 0x0514 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3 0x01CC 0x0514 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x01D0 0x0518 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII1_RX_CTL__GPIO5_IO_4 0x01D0 0x0518 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII1_RX_CTL__CSI2_DATA_14 0x01D0 0x0518 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0 0x01D0 0x0518 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER 0x01D0 0x0518 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4 0x01D0 0x0518 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x01D4 0x051C 0x0768 0x0 0x1
	#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x01D4 0x051C 0x0000 0x1 0x0
	#define MX6SX_PAD_RGMII1_RXC__GPIO5_IO_5 0x01D4 0x051C 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII1_RXC__CSI2_DATA_15 0x01D4 0x051C 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII1_RXC__ANATOP_TESTO_1 0x01D4 0x051C 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER 0x01D4 0x051C 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5 0x01D4 0x051C 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x01D8 0x0520 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII1_TD0__SAI2_RX_SYNC 0x01D8 0x0520 0x0810 0x2 0x1
	#define MX6SX_PAD_RGMII1_TD0__GPIO5_IO_6 0x01D8 0x0520 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII1_TD0__CSI2_DATA_16 0x01D8 0x0520 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII1_TD0__ANATOP_TESTO_2 0x01D8 0x0520 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER 0x01D8 0x0520 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6 0x01D8 0x0520 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x01DC 0x0524 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII1_TD1__SAI2_RX_BCLK 0x01DC 0x0524 0x0808 0x2 0x1
	#define MX6SX_PAD_RGMII1_TD1__GPIO5_IO_7 0x01DC 0x0524 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII1_TD1__CSI2_DATA_17 0x01DC 0x0524 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII1_TD1__ANATOP_TESTO_3 0x01DC 0x0524 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER 0x01DC 0x0524 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7 0x01DC 0x0524 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x01E0 0x0528 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII1_TD2__SAI2_TX_SYNC 0x01E0 0x0528 0x0818 0x2 0x1
	#define MX6SX_PAD_RGMII1_TD2__GPIO5_IO_8 0x01E0 0x0528 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII1_TD2__CSI2_DATA_18 0x01E0 0x0528 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII1_TD2__ANATOP_TESTO_4 0x01E0 0x0528 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER 0x01E0 0x0528 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8 0x01E0 0x0528 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x01E4 0x052C 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII1_TD3__SAI2_TX_BCLK 0x01E4 0x052C 0x0814 0x2 0x1
	#define MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x01E4 0x052C 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII1_TD3__CSI2_DATA_19 0x01E4 0x052C 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII1_TD3__ANATOP_TESTO_5 0x01E4 0x052C 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER 0x01E4 0x052C 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9 0x01E4 0x052C 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x01E8 0x0530 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 0x01E8 0x0530 0x080C 0x2 0x1
	#define MX6SX_PAD_RGMII1_TX_CTL__GPIO5_IO_10 0x01E8 0x0530 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII1_TX_CTL__CSI2_DATA_0 0x01E8 0x0530 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6 0x01E8 0x0530 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER 0x01E8 0x0530 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10 0x01E8 0x0530 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x01EC 0x0534 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII1_TXC__ENET1_TX_ER 0x01EC 0x0534 0x0000 0x1 0x0
	#define MX6SX_PAD_RGMII1_TXC__SAI2_TX_DATA_0 0x01EC 0x0534 0x0000 0x2 0x0
	#define MX6SX_PAD_RGMII1_TXC__GPIO5_IO_11 0x01EC 0x0534 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII1_TXC__CSI2_DATA_1 0x01EC 0x0534 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII1_TXC__ANATOP_TESTO_7 0x01EC 0x0534 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER 0x01EC 0x0534 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11 0x01EC 0x0534 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x01F0 0x0538 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII2_RD0__PWM4_OUT 0x01F0 0x0538 0x0000 0x2 0x0
	#define MX6SX_PAD_RGMII2_RD0__GPIO5_IO_12 0x01F0 0x0538 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII2_RD0__CSI2_DATA_2 0x01F0 0x0538 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII2_RD0__ANATOP_TESTO_8 0x01F0 0x0538 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII2_RD0__VDEC_DEBUG_18 0x01F0 0x0538 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12 0x01F0 0x0538 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x01F4 0x053C 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII2_RD1__PWM3_OUT 0x01F4 0x053C 0x0000 0x2 0x0
	#define MX6SX_PAD_RGMII2_RD1__GPIO5_IO_13 0x01F4 0x053C 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII2_RD1__CSI2_DATA_3 0x01F4 0x053C 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII2_RD1__ANATOP_TESTO_9 0x01F4 0x053C 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII2_RD1__VDEC_DEBUG_19 0x01F4 0x053C 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13 0x01F4 0x053C 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x01F8 0x0540 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x01F8 0x0540 0x0000 0x2 0x0
	#define MX6SX_PAD_RGMII2_RD2__GPIO5_IO_14 0x01F8 0x0540 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII2_RD2__CSI2_DATA_4 0x01F8 0x0540 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII2_RD2__ANATOP_TESTO_10 0x01F8 0x0540 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII2_RD2__VDEC_DEBUG_20 0x01F8 0x0540 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14 0x01F8 0x0540 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x01FC 0x0544 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x01FC 0x0544 0x0000 0x2 0x0
	#define MX6SX_PAD_RGMII2_RD3__GPIO5_IO_15 0x01FC 0x0544 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII2_RD3__CSI2_DATA_5 0x01FC 0x0544 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII2_RD3__ANATOP_TESTO_11 0x01FC 0x0544 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII2_RD3__VDEC_DEBUG_21 0x01FC 0x0544 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15 0x01FC 0x0544 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x0200 0x0548 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII2_RX_CTL__GPIO5_IO_16 0x0200 0x0548 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII2_RX_CTL__CSI2_DATA_6 0x0200 0x0548 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12 0x0200 0x0548 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22 0x0200 0x0548 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16 0x0200 0x0548 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x0204 0x054C 0x0774 0x0 0x1
	#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_ER 0x0204 0x054C 0x0000 0x1 0x0
	#define MX6SX_PAD_RGMII2_RXC__GPIO5_IO_17 0x0204 0x054C 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII2_RXC__CSI2_DATA_7 0x0204 0x054C 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII2_RXC__ANATOP_TESTO_13 0x0204 0x054C 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII2_RXC__VDEC_DEBUG_23 0x0204 0x054C 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17 0x0204 0x054C 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x0208 0x0550 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII2_TD0__SAI1_RX_SYNC 0x0208 0x0550 0x07FC 0x2 0x1
	#define MX6SX_PAD_RGMII2_TD0__PWM8_OUT 0x0208 0x0550 0x0000 0x3 0x0
	#define MX6SX_PAD_RGMII2_TD0__GPIO5_IO_18 0x0208 0x0550 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII2_TD0__CSI2_DATA_8 0x0208 0x0550 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII2_TD0__ANATOP_TESTO_14 0x0208 0x0550 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII2_TD0__VDEC_DEBUG_24 0x0208 0x0550 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18 0x0208 0x0550 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x020C 0x0554 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII2_TD1__SAI1_RX_BCLK 0x020C 0x0554 0x07F4 0x2 0x1
	#define MX6SX_PAD_RGMII2_TD1__PWM7_OUT 0x020C 0x0554 0x0000 0x3 0x0
	#define MX6SX_PAD_RGMII2_TD1__GPIO5_IO_19 0x020C 0x0554 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII2_TD1__CSI2_DATA_9 0x020C 0x0554 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII2_TD1__ANATOP_TESTO_15 0x020C 0x0554 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII2_TD1__VDEC_DEBUG_25 0x020C 0x0554 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19 0x020C 0x0554 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x0210 0x0558 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII2_TD2__SAI1_TX_SYNC 0x0210 0x0558 0x0804 0x2 0x1
	#define MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x0210 0x0558 0x0000 0x3 0x0
	#define MX6SX_PAD_RGMII2_TD2__GPIO5_IO_20 0x0210 0x0558 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII2_TD2__CSI2_VSYNC 0x0210 0x0558 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII2_TD2__SJC_FAIL 0x0210 0x0558 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII2_TD2__VDEC_DEBUG_26 0x0210 0x0558 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20 0x0210 0x0558 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x0214 0x055C 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII2_TD3__SAI1_TX_BCLK 0x0214 0x055C 0x0800 0x2 0x1
	#define MX6SX_PAD_RGMII2_TD3__PWM5_OUT 0x0214 0x055C 0x0000 0x3 0x0
	#define MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x0214 0x055C 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII2_TD3__CSI2_HSYNC 0x0214 0x055C 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII2_TD3__SJC_JTAG_ACT 0x0214 0x055C 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII2_TD3__VDEC_DEBUG_27 0x0214 0x055C 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21 0x0214 0x055C 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x0218 0x0560 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 0x0218 0x0560 0x07F8 0x2 0x1
	#define MX6SX_PAD_RGMII2_TX_CTL__GPIO5_IO_22 0x0218 0x0560 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII2_TX_CTL__CSI2_FIELD 0x0218 0x0560 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII2_TX_CTL__SJC_DE_B 0x0218 0x0560 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28 0x0218 0x0560 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22 0x0218 0x0560 0x0000 0x9 0x0
	#define MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x021C 0x0564 0x0000 0x0 0x0
	#define MX6SX_PAD_RGMII2_TXC__ENET2_TX_ER 0x021C 0x0564 0x0000 0x1 0x0
	#define MX6SX_PAD_RGMII2_TXC__SAI1_TX_DATA_0 0x021C 0x0564 0x0000 0x2 0x0
	#define MX6SX_PAD_RGMII2_TXC__GPIO5_IO_23 0x021C 0x0564 0x0000 0x5 0x0
	#define MX6SX_PAD_RGMII2_TXC__CSI2_PIXCLK 0x021C 0x0564 0x0000 0x6 0x0
	#define MX6SX_PAD_RGMII2_TXC__SJC_DONE 0x021C 0x0564 0x0000 0x7 0x0
	#define MX6SX_PAD_RGMII2_TXC__VDEC_DEBUG_29 0x021C 0x0564 0x0000 0x8 0x0
	#define MX6SX_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23 0x021C 0x0564 0x0000 0x9 0x0
	#define MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x0220 0x0568 0x0000 0x0 0x0
	#define MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x0220 0x0568 0x0668 0x1 0x1
	#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_B 0x0220 0x0568 0x0000 0x2 0x0
	#define MX6SX_PAD_SD1_CLK__GPT_CLK 0x0220 0x0568 0x0000 0x3 0x0
	#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB 0x0220 0x0568 0x0000 0x4 0x0
	#define MX6SX_PAD_SD1_CLK__GPIO6_IO_0 0x0220 0x0568 0x0000 0x5 0x0
	#define MX6SX_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT 0x0220 0x0568 0x0000 0x6 0x0
	#define MX6SX_PAD_SD1_CLK__CCM_OUT1 0x0220 0x0568 0x0000 0x7 0x0
	#define MX6SX_PAD_SD1_CLK__VADC_ADC_PROC_CLK 0x0220 0x0568 0x0000 0x8 0x0
	#define MX6SX_PAD_SD1_CLK__MMDC_DEBUG_45 0x0220 0x0568 0x0000 0x9 0x0
	#define MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x0224 0x056C 0x0000 0x0 0x0
	#define MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x0224 0x056C 0x0664 0x1 0x1
	#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_B 0x0224 0x056C 0x0000 0x2 0x0
	#define MX6SX_PAD_SD1_CMD__GPT_COMPARE1 0x0224 0x056C 0x0000 0x3 0x0
	#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB 0x0224 0x056C 0x0000 0x4 0x0
	#define MX6SX_PAD_SD1_CMD__GPIO6_IO_1 0x0224 0x056C 0x0000 0x5 0x0
	#define MX6SX_PAD_SD1_CMD__ENET2_1588_EVENT1_IN 0x0224 0x056C 0x0000 0x6 0x0
	#define MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x0224 0x056C 0x0000 0x7 0x0
	#define MX6SX_PAD_SD1_CMD__VADC_EXT_SYSCLK 0x0224 0x056C 0x0000 0x8 0x0
	#define MX6SX_PAD_SD1_CMD__MMDC_DEBUG_46 0x0224 0x056C 0x0000 0x9 0x0
	#define MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x0228 0x0570 0x0000 0x0 0x0
	#define MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x0228 0x0570 0x065C 0x1 0x1
	#define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS 0x0228 0x0570 0x0000 0x2 0x0
	#define MX6SX_PAD_SD1_DATA0__GPT_CAPTURE1 0x0228 0x0570 0x0000 0x3 0x0
	-#define MX6SX_PAD_SD1_DATA0__UART2_RX 0x0228 0x0570 0x0838 0x4 0x2
	-#define MX6SX_PAD_SD1_DATA0__UART2_TX 0x0228 0x0570 0x0000 0x4 0x0
	+#define MX6SX_PAD_SD1_DATA0__UART2_DCE_RX 0x0228 0x0570 0x0838 0x4 0x2
	+#define MX6SX_PAD_SD1_DATA0__UART2_DTE_TX 0x0228 0x0570 0x0000 0x4 0x0
	#define MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x0228 0x0570 0x0000 0x5 0x0
	#define MX6SX_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN 0x0228 0x0570 0x0000 0x6 0x0
	#define MX6SX_PAD_SD1_DATA0__CCM_OUT2 0x0228 0x0570 0x0000 0x7 0x0
	#define MX6SX_PAD_SD1_DATA0__VADC_CLAMP_UP 0x0228 0x0570 0x0000 0x8 0x0
	#define MX6SX_PAD_SD1_DATA0__MMDC_DEBUG_48 0x0228 0x0570 0x0000 0x9 0x0
	#define MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x022C 0x0574 0x0000 0x0 0x0
	#define MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x022C 0x0574 0x066C 0x1 0x1
	#define MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x022C 0x0574 0x0000 0x2 0x0
	#define MX6SX_PAD_SD1_DATA1__GPT_CAPTURE2 0x022C 0x0574 0x0000 0x3 0x0
	-#define MX6SX_PAD_SD1_DATA1__UART2_RX 0x022C 0x0574 0x0838 0x4 0x3
	-#define MX6SX_PAD_SD1_DATA1__UART2_TX 0x022C 0x0574 0x0000 0x4 0x0
	+#define MX6SX_PAD_SD1_DATA1__UART2_DCE_TX 0x022C 0x0574 0x0000 0x4 0x0
	+#define MX6SX_PAD_SD1_DATA1__UART2_DTE_RX 0x022C 0x0574 0x0838 0x4 0x3
	#define MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 0x022C 0x0574 0x0000 0x5 0x0
	#define MX6SX_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT 0x022C 0x0574 0x0000 0x6 0x0
	#define MX6SX_PAD_SD1_DATA1__CCM_CLKO2 0x022C 0x0574 0x0000 0x7 0x0
	#define MX6SX_PAD_SD1_DATA1__VADC_CLAMP_DOWN 0x022C 0x0574 0x0000 0x8 0x0
	#define MX6SX_PAD_SD1_DATA1__MMDC_DEBUG_47 0x022C 0x0574 0x0000 0x9 0x0
	#define MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x0230 0x0578 0x0000 0x0 0x0
	#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1
	#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0
	#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0
	-#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0000 0x4 0x0
	+#define MX6SX_PAD_SD1_DATA2__UART2_DCE_CTS 0x0230 0x0578 0x0000 0x4 0x0
	+#define MX6SX_PAD_SD1_DATA2__UART2_DTE_RTS 0x0230 0x0578 0x0834 0x4 0x2
	#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0
	#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0
	#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0
	#define MX6SX_PAD_SD1_DATA2__VADC_EXT_PD_N 0x0230 0x0578 0x0000 0x8 0x0
	#define MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x0234 0x057C 0x0000 0x0 0x0
	#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x0234 0x057C 0x0660 0x1 0x1
	#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2
	#define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0
	-#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B 0x0234 0x057C 0x0834 0x4 0x3
	+#define MX6SX_PAD_SD1_DATA3__UART2_DCE_RTS 0x0234 0x057C 0x0834 0x4 0x3
	+#define MX6SX_PAD_SD1_DATA3__UART2_DTE_CTS 0x0234 0x057C 0x0000 0x4 0x0
	#define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0
	#define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0
	#define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2
	#define MX6SX_PAD_SD1_DATA3__VADC_RST_N 0x0234 0x057C 0x0000 0x8 0x0
	#define MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x0238 0x0580 0x0000 0x0 0x0
	#define MX6SX_PAD_SD2_CLK__AUDMUX_AUD6_RXFS 0x0238 0x0580 0x0680 0x1 0x2
	#define MX6SX_PAD_SD2_CLK__KPP_COL_5 0x0238 0x0580 0x07C8 0x2 0x1
	#define MX6SX_PAD_SD2_CLK__ECSPI4_SCLK 0x0238 0x0580 0x0740 0x3 0x1
	#define MX6SX_PAD_SD2_CLK__MLB_SIG 0x0238 0x0580 0x07F0 0x4 0x2
	#define MX6SX_PAD_SD2_CLK__GPIO6_IO_6 0x0238 0x0580 0x0000 0x5 0x0
	#define MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x0238 0x0580 0x0000 0x6 0x0
	#define MX6SX_PAD_SD2_CLK__WDOG1_WDOG_ANY 0x0238 0x0580 0x0000 0x7 0x0
	#define MX6SX_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5 0x0238 0x0580 0x0000 0x8 0x0
	#define MX6SX_PAD_SD2_CLK__MMDC_DEBUG_29 0x0238 0x0580 0x0000 0x9 0x0
	#define MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x023C 0x0584 0x0000 0x0 0x0
	#define MX6SX_PAD_SD2_CMD__AUDMUX_AUD6_RXC 0x023C 0x0584 0x067C 0x1 0x2
	#define MX6SX_PAD_SD2_CMD__KPP_ROW_5 0x023C 0x0584 0x07D4 0x2 0x1
	#define MX6SX_PAD_SD2_CMD__ECSPI4_MOSI 0x023C 0x0584 0x0748 0x3 0x1
	#define MX6SX_PAD_SD2_CMD__MLB_CLK 0x023C 0x0584 0x07E8 0x4 0x2
	#define MX6SX_PAD_SD2_CMD__GPIO6_IO_7 0x023C 0x0584 0x0000 0x5 0x0
	#define MX6SX_PAD_SD2_CMD__MQS_LEFT 0x023C 0x0584 0x0000 0x6 0x0
	#define MX6SX_PAD_SD2_CMD__WDOG3_WDOG_B 0x023C 0x0584 0x0000 0x7 0x0
	#define MX6SX_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4 0x023C 0x0584 0x0000 0x8 0x0
	#define MX6SX_PAD_SD2_CMD__MMDC_DEBUG_30 0x023C 0x0584 0x0000 0x9 0x0
	#define MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x0240 0x0588 0x0000 0x0 0x0
	#define MX6SX_PAD_SD2_DATA0__AUDMUX_AUD6_RXD 0x0240 0x0588 0x0674 0x1 0x2
	#define MX6SX_PAD_SD2_DATA0__KPP_ROW_7 0x0240 0x0588 0x07DC 0x2 0x1
	#define MX6SX_PAD_SD2_DATA0__PWM1_OUT 0x0240 0x0588 0x0000 0x3 0x0
	#define MX6SX_PAD_SD2_DATA0__I2C4_SDA 0x0240 0x0588 0x07C4 0x4 0x3
	#define MX6SX_PAD_SD2_DATA0__GPIO6_IO_8 0x0240 0x0588 0x0000 0x5 0x0
	#define MX6SX_PAD_SD2_DATA0__ECSPI4_SS3 0x0240 0x0588 0x0000 0x6 0x0
	-#define MX6SX_PAD_SD2_DATA0__UART4_RX 0x0240 0x0588 0x0848 0x7 0x4
	-#define MX6SX_PAD_SD2_DATA0__UART4_TX 0x0240 0x0588 0x0000 0x7 0x0
	+#define MX6SX_PAD_SD2_DATA0__UART4_DCE_RX 0x0240 0x0588 0x0848 0x7 0x4
	+#define MX6SX_PAD_SD2_DATA0__UART4_DTE_TX 0x0240 0x0588 0x0000 0x7 0x0
	#define MX6SX_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 0x0240 0x0588 0x0000 0x8 0x0
	#define MX6SX_PAD_SD2_DATA0__MMDC_DEBUG_50 0x0240 0x0588 0x0000 0x9 0x0
	#define MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x0244 0x058C 0x0000 0x0 0x0
	#define MX6SX_PAD_SD2_DATA1__AUDMUX_AUD6_TXC 0x0244 0x058C 0x0684 0x1 0x2
	#define MX6SX_PAD_SD2_DATA1__KPP_COL_7 0x0244 0x058C 0x07D0 0x2 0x1
	#define MX6SX_PAD_SD2_DATA1__PWM2_OUT 0x0244 0x058C 0x0000 0x3 0x0
	#define MX6SX_PAD_SD2_DATA1__I2C4_SCL 0x0244 0x058C 0x07C0 0x4 0x3
	#define MX6SX_PAD_SD2_DATA1__GPIO6_IO_9 0x0244 0x058C 0x0000 0x5 0x0
	#define MX6SX_PAD_SD2_DATA1__ECSPI4_SS2 0x0244 0x058C 0x0000 0x6 0x0
	-#define MX6SX_PAD_SD2_DATA1__UART4_RX 0x0244 0x058C 0x0848 0x7 0x5
	-#define MX6SX_PAD_SD2_DATA1__UART4_TX 0x0244 0x058C 0x0000 0x7 0x0
	+#define MX6SX_PAD_SD2_DATA1__UART4_DCE_TX 0x0244 0x058C 0x0000 0x7 0x0
	+#define MX6SX_PAD_SD2_DATA1__UART4_DTE_RX 0x0244 0x058C 0x0848 0x7 0x5
	#define MX6SX_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 0x0244 0x058C 0x0000 0x8 0x0
	#define MX6SX_PAD_SD2_DATA1__MMDC_DEBUG_49 0x0244 0x058C 0x0000 0x9 0x0
	#define MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x0248 0x0590 0x0000 0x0 0x0
	#define MX6SX_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS 0x0248 0x0590 0x0688 0x1 0x2
	#define MX6SX_PAD_SD2_DATA2__KPP_ROW_6 0x0248 0x0590 0x07D8 0x2 0x1
	#define MX6SX_PAD_SD2_DATA2__ECSPI4_SS0 0x0248 0x0590 0x074C 0x3 0x1
	#define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 0x0248 0x0590 0x081C 0x4 0x2
	#define MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 0x0248 0x0590 0x0000 0x5 0x0
	#define MX6SX_PAD_SD2_DATA2__SPDIF_OUT 0x0248 0x0590 0x0000 0x6 0x0
	-#define MX6SX_PAD_SD2_DATA2__UART6_RX 0x0248 0x0590 0x0858 0x7 0x4
	-#define MX6SX_PAD_SD2_DATA2__UART6_TX 0x0248 0x0590 0x0000 0x7 0x0
	+#define MX6SX_PAD_SD2_DATA2__UART6_DCE_RX 0x0248 0x0590 0x0858 0x7 0x4
	+#define MX6SX_PAD_SD2_DATA2__UART6_DTE_TX 0x0248 0x0590 0x0000 0x7 0x0
	#define MX6SX_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 0x0248 0x0590 0x0000 0x8 0x0
	#define MX6SX_PAD_SD2_DATA2__MMDC_DEBUG_32 0x0248 0x0590 0x0000 0x9 0x0
	#define MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x024C 0x0594 0x0000 0x0 0x0
	#define MX6SX_PAD_SD2_DATA3__AUDMUX_AUD6_TXD 0x024C 0x0594 0x0678 0x1 0x2
	#define MX6SX_PAD_SD2_DATA3__KPP_COL_6 0x024C 0x0594 0x07CC 0x2 0x1
	#define MX6SX_PAD_SD2_DATA3__ECSPI4_MISO 0x024C 0x0594 0x0744 0x3 0x1
	#define MX6SX_PAD_SD2_DATA3__MLB_DATA 0x024C 0x0594 0x07EC 0x4 0x2
	#define MX6SX_PAD_SD2_DATA3__GPIO6_IO_11 0x024C 0x0594 0x0000 0x5 0x0
	#define MX6SX_PAD_SD2_DATA3__SPDIF_IN 0x024C 0x0594 0x0824 0x6 0x4
	-#define MX6SX_PAD_SD2_DATA3__UART6_RX 0x024C 0x0594 0x0858 0x7 0x5
	-#define MX6SX_PAD_SD2_DATA3__UART6_TX 0x024C 0x0594 0x0000 0x7 0x0
	+#define MX6SX_PAD_SD2_DATA3__UART6_DCE_TX 0x024C 0x0594 0x0000 0x7 0x0
	+#define MX6SX_PAD_SD2_DATA3__UART6_DTE_RX 0x024C 0x0594 0x0858 0x7 0x5
	#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0
	#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0
	#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0
	-#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0000 0x1 0x0
	+#define MX6SX_PAD_SD3_CLK__UART4_DCE_CTS 0x0250 0x0598 0x0000 0x1 0x0
	+#define MX6SX_PAD_SD3_CLK__UART4_DTE_RTS 0x0250 0x0598 0x0844 0x1 0x0
	#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0
	#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0
	#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0
	#define MX6SX_PAD_SD3_CLK__GPIO7_IO_0 0x0250 0x0598 0x0000 0x5 0x0
	#define MX6SX_PAD_SD3_CLK__LCDIF2_BUSY 0x0250 0x0598 0x07E4 0x6 0x0
	#define MX6SX_PAD_SD3_CLK__TPSMP_HDATA_29 0x0250 0x0598 0x0000 0x7 0x0
	#define MX6SX_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 0x0250 0x0598 0x0000 0x9 0x0
	#define MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x0254 0x059C 0x0000 0x0 0x0
	-#define MX6SX_PAD_SD3_CMD__UART4_RX 0x0254 0x059C 0x0848 0x1 0x0
	-#define MX6SX_PAD_SD3_CMD__UART4_TX 0x0254 0x059C 0x0000 0x1 0x0
	+#define MX6SX_PAD_SD3_CMD__UART4_DCE_TX 0x0254 0x059C 0x0000 0x1 0x0
	+#define MX6SX_PAD_SD3_CMD__UART4_DTE_RX 0x0254 0x059C 0x0848 0x1 0x0
	#define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x0254 0x059C 0x0748 0x2 0x0
	#define MX6SX_PAD_SD3_CMD__AUDMUX_AUD6_RXC 0x0254 0x059C 0x067C 0x3 0x0
	#define MX6SX_PAD_SD3_CMD__LCDIF2_HSYNC 0x0254 0x059C 0x07E4 0x4 0x1
	#define MX6SX_PAD_SD3_CMD__GPIO7_IO_1 0x0254 0x059C 0x0000 0x5 0x0
	#define MX6SX_PAD_SD3_CMD__LCDIF2_RS 0x0254 0x059C 0x0000 0x6 0x0
	#define MX6SX_PAD_SD3_CMD__TPSMP_HDATA_28 0x0254 0x059C 0x0000 0x7 0x0
	#define MX6SX_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 0x0254 0x059C 0x0000 0x9 0x0
	#define MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x0258 0x05A0 0x0000 0x0 0x0
	#define MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x0258 0x05A0 0x07C0 0x1 0x0
	#define MX6SX_PAD_SD3_DATA0__ECSPI2_SS1 0x0258 0x05A0 0x0000 0x2 0x0
	#define MX6SX_PAD_SD3_DATA0__AUDMUX_AUD6_RXD 0x0258 0x05A0 0x0674 0x3 0x0
	#define MX6SX_PAD_SD3_DATA0__LCDIF2_DATA_1 0x0258 0x05A0 0x0000 0x4 0x0
	#define MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x0258 0x05A0 0x0000 0x5 0x0
	#define MX6SX_PAD_SD3_DATA0__DCIC1_OUT 0x0258 0x05A0 0x0000 0x6 0x0
	#define MX6SX_PAD_SD3_DATA0__TPSMP_HDATA_30 0x0258 0x05A0 0x0000 0x7 0x0
	#define MX6SX_PAD_SD3_DATA0__GPU_DEBUG_0 0x0258 0x05A0 0x0000 0x8 0x0
	#define MX6SX_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 0x0258 0x05A0 0x0000 0x9 0x0
	#define MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x025C 0x05A4 0x0000 0x0 0x0
	#define MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x025C 0x05A4 0x07C4 0x1 0x0
	#define MX6SX_PAD_SD3_DATA1__ECSPI2_SS2 0x025C 0x05A4 0x0000 0x2 0x0
	#define MX6SX_PAD_SD3_DATA1__AUDMUX_AUD6_TXC 0x025C 0x05A4 0x0684 0x3 0x0
	#define MX6SX_PAD_SD3_DATA1__LCDIF2_DATA_0 0x025C 0x05A4 0x0000 0x4 0x0
	#define MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x025C 0x05A4 0x0000 0x5 0x0
	#define MX6SX_PAD_SD3_DATA1__DCIC2_OUT 0x025C 0x05A4 0x0000 0x6 0x0
	#define MX6SX_PAD_SD3_DATA1__TPSMP_HDATA_31 0x025C 0x05A4 0x0000 0x7 0x0
	#define MX6SX_PAD_SD3_DATA1__GPU_DEBUG_1 0x025C 0x05A4 0x0000 0x8 0x0
	#define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0
	#define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0
	-#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B 0x0260 0x05A8 0x0844 0x1 0x1
	+#define MX6SX_PAD_SD3_DATA2__UART4_DCE_RTS 0x0260 0x05A8 0x0844 0x1 0x1
	+#define MX6SX_PAD_SD3_DATA2__UART4_DTE_CTS 0x0260 0x05A8 0x0000 0x1 0x0
	#define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0
	#define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0
	#define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0
	#define MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x0260 0x05A8 0x0000 0x5 0x0
	#define MX6SX_PAD_SD3_DATA2__LCDIF2_WR_RWN 0x0260 0x05A8 0x0000 0x6 0x0
	#define MX6SX_PAD_SD3_DATA2__TPSMP_HDATA_26 0x0260 0x05A8 0x0000 0x7 0x0
	#define MX6SX_PAD_SD3_DATA2__GPU_DEBUG_2 0x0260 0x05A8 0x0000 0x8 0x0
	#define MX6SX_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 0x0260 0x05A8 0x0000 0x9 0x0
	#define MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x0264 0x05AC 0x0000 0x0 0x0
	-#define MX6SX_PAD_SD3_DATA3__UART4_RX 0x0264 0x05AC 0x0848 0x1 0x1
	-#define MX6SX_PAD_SD3_DATA3__UART4_TX 0x0264 0x05AC 0x0000 0x1 0x0
	+#define MX6SX_PAD_SD3_DATA3__UART4_DCE_RX 0x0264 0x05AC 0x0848 0x1 0x1
	+#define MX6SX_PAD_SD3_DATA3__UART4_DTE_TX 0x0264 0x05AC 0x0000 0x1 0x0
	#define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x0264 0x05AC 0x0744 0x2 0x0
	#define MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD 0x0264 0x05AC 0x0678 0x3 0x0
	#define MX6SX_PAD_SD3_DATA3__LCDIF2_ENABLE 0x0264 0x05AC 0x0000 0x4 0x0
	#define MX6SX_PAD_SD3_DATA3__GPIO7_IO_5 0x0264 0x05AC 0x0000 0x5 0x0
	#define MX6SX_PAD_SD3_DATA3__LCDIF2_RD_E 0x0264 0x05AC 0x0000 0x6 0x0
	#define MX6SX_PAD_SD3_DATA3__TPSMP_HDATA_27 0x0264 0x05AC 0x0000 0x7 0x0
	#define MX6SX_PAD_SD3_DATA3__GPU_DEBUG_3 0x0264 0x05AC 0x0000 0x8 0x0
	#define MX6SX_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3 0x0264 0x05AC 0x0000 0x9 0x0
	#define MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x0268 0x05B0 0x0000 0x0 0x0
	#define MX6SX_PAD_SD3_DATA4__CAN2_RX 0x0268 0x05B0 0x0690 0x1 0x0
	#define MX6SX_PAD_SD3_DATA4__CANFD_RX2 0x0268 0x05B0 0x0698 0x2 0x0
	-#define MX6SX_PAD_SD3_DATA4__UART3_RX 0x0268 0x05B0 0x0840 0x3 0x2
	-#define MX6SX_PAD_SD3_DATA4__UART3_TX 0x0268 0x05B0 0x0000 0x3 0x0
	+#define MX6SX_PAD_SD3_DATA4__UART3_DCE_RX 0x0268 0x05B0 0x0840 0x3 0x2
	+#define MX6SX_PAD_SD3_DATA4__UART3_DTE_TX 0x0268 0x05B0 0x0000 0x3 0x0
	#define MX6SX_PAD_SD3_DATA4__LCDIF2_DATA_3 0x0268 0x05B0 0x0000 0x4 0x0
	#define MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x0268 0x05B0 0x0000 0x5 0x0
	#define MX6SX_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN 0x0268 0x05B0 0x0000 0x6 0x0
	#define MX6SX_PAD_SD3_DATA4__TPSMP_HTRANS_1 0x0268 0x05B0 0x0000 0x7 0x0
	#define MX6SX_PAD_SD3_DATA4__GPU_DEBUG_4 0x0268 0x05B0 0x0000 0x8 0x0
	#define MX6SX_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0 0x0268 0x05B0 0x0000 0x9 0x0
	#define MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x026C 0x05B4 0x0000 0x0 0x0
	#define MX6SX_PAD_SD3_DATA5__CAN1_TX 0x026C 0x05B4 0x0000 0x1 0x0
	#define MX6SX_PAD_SD3_DATA5__CANFD_TX1 0x026C 0x05B4 0x0000 0x2 0x0
	-#define MX6SX_PAD_SD3_DATA5__UART3_RX 0x026C 0x05B4 0x0840 0x3 0x3
	-#define MX6SX_PAD_SD3_DATA5__UART3_TX 0x026C 0x05B4 0x0000 0x3 0x0
	+#define MX6SX_PAD_SD3_DATA5__UART3_DCE_TX 0x026C 0x05B4 0x0000 0x3 0x0
	+#define MX6SX_PAD_SD3_DATA5__UART3_DTE_RX 0x026C 0x05B4 0x0840 0x3 0x3
	#define MX6SX_PAD_SD3_DATA5__LCDIF2_DATA_2 0x026C 0x05B4 0x0000 0x4 0x0
	#define MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x026C 0x05B4 0x0000 0x5 0x0
	#define MX6SX_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT 0x026C 0x05B4 0x0000 0x6 0x0
	#define MX6SX_PAD_SD3_DATA5__SIM_M_HWRITE 0x026C 0x05B4 0x0000 0x7 0x0
	#define MX6SX_PAD_SD3_DATA5__GPU_DEBUG_5 0x026C 0x05B4 0x0000 0x8 0x0
	#define MX6SX_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1 0x026C 0x05B4 0x0000 0x9 0x0
	#define MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x0270 0x05B8 0x0000 0x0 0x0
	#define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0
	#define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0
	-#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270 0x05B8 0x083C 0x3 0x2
	+#define MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x0270 0x05B8 0x083C 0x3 0x2
	+#define MX6SX_PAD_SD3_DATA6__UART3_DTE_CTS 0x0270 0x05B8 0x0000 0x3 0x0
	#define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0
	#define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0
	#define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0
	#define MX6SX_PAD_SD3_DATA6__TPSMP_HTRANS_0 0x0270 0x05B8 0x0000 0x7 0x0
	#define MX6SX_PAD_SD3_DATA6__GPU_DEBUG_7 0x0270 0x05B8 0x0000 0x8 0x0
	#define MX6SX_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7 0x0270 0x05B8 0x0000 0x9 0x0
	#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0
	#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0
	#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0
	-#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x0000 0x3 0x0
	+#define MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x0274 0x05BC 0x0000 0x3 0x0
	+#define MX6SX_PAD_SD3_DATA7__UART3_DTE_RTS 0x0274 0x05BC 0x083C 0x3 0x3
	#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0
	#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0
	#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0
	#define MX6SX_PAD_SD3_DATA7__TPSMP_HDATA_DIR 0x0274 0x05BC 0x0000 0x7 0x0
	#define MX6SX_PAD_SD3_DATA7__GPU_DEBUG_6 0x0274 0x05BC 0x0000 0x8 0x0
	#define MX6SX_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2 0x0274 0x05BC 0x0000 0x9 0x0
	#define MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x0278 0x05C0 0x0000 0x0 0x0
	#define MX6SX_PAD_SD4_CLK__RAWNAND_DATA15 0x0278 0x05C0 0x0000 0x1 0x0
	#define MX6SX_PAD_SD4_CLK__ECSPI2_MISO 0x0278 0x05C0 0x0724 0x2 0x1
	#define MX6SX_PAD_SD4_CLK__AUDMUX_AUD3_RXFS 0x0278 0x05C0 0x0638 0x3 0x0
	#define MX6SX_PAD_SD4_CLK__LCDIF2_DATA_13 0x0278 0x05C0 0x0000 0x4 0x0
	#define MX6SX_PAD_SD4_CLK__GPIO6_IO_12 0x0278 0x05C0 0x0000 0x5 0x0
	#define MX6SX_PAD_SD4_CLK__ECSPI3_SS2 0x0278 0x05C0 0x0000 0x6 0x0
	#define MX6SX_PAD_SD4_CLK__TPSMP_HDATA_20 0x0278 0x05C0 0x0000 0x7 0x0
	#define MX6SX_PAD_SD4_CLK__VDEC_DEBUG_12 0x0278 0x05C0 0x0000 0x8 0x0
	#define MX6SX_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x0278 0x05C0 0x0000 0x9 0x0
	#define MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x027C 0x05C4 0x0000 0x0 0x0
	#define MX6SX_PAD_SD4_CMD__RAWNAND_DATA14 0x027C 0x05C4 0x0000 0x1 0x0
	#define MX6SX_PAD_SD4_CMD__ECSPI2_MOSI 0x027C 0x05C4 0x0728 0x2 0x1
	#define MX6SX_PAD_SD4_CMD__AUDMUX_AUD3_RXC 0x027C 0x05C4 0x0634 0x3 0x0
	#define MX6SX_PAD_SD4_CMD__LCDIF2_DATA_14 0x027C 0x05C4 0x0000 0x4 0x0
	#define MX6SX_PAD_SD4_CMD__GPIO6_IO_13 0x027C 0x05C4 0x0000 0x5 0x0
	#define MX6SX_PAD_SD4_CMD__ECSPI3_SS1 0x027C 0x05C4 0x0000 0x6 0x0
	#define MX6SX_PAD_SD4_CMD__TPSMP_HDATA_19 0x027C 0x05C4 0x0000 0x7 0x0
	#define MX6SX_PAD_SD4_CMD__VDEC_DEBUG_11 0x027C 0x05C4 0x0000 0x8 0x0
	#define MX6SX_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN 0x027C 0x05C4 0x0000 0x9 0x0
	#define MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x0280 0x05C8 0x0000 0x0 0x0
	#define MX6SX_PAD_SD4_DATA0__RAWNAND_DATA10 0x0280 0x05C8 0x0000 0x1 0x0
	#define MX6SX_PAD_SD4_DATA0__ECSPI2_SS0 0x0280 0x05C8 0x072C 0x2 0x1
	#define MX6SX_PAD_SD4_DATA0__AUDMUX_AUD3_RXD 0x0280 0x05C8 0x062C 0x3 0x0
	#define MX6SX_PAD_SD4_DATA0__LCDIF2_DATA_12 0x0280 0x05C8 0x0000 0x4 0x0
	#define MX6SX_PAD_SD4_DATA0__GPIO6_IO_14 0x0280 0x05C8 0x0000 0x5 0x0
	#define MX6SX_PAD_SD4_DATA0__ECSPI3_SS3 0x0280 0x05C8 0x0000 0x6 0x0
	#define MX6SX_PAD_SD4_DATA0__TPSMP_HDATA_21 0x0280 0x05C8 0x0000 0x7 0x0
	#define MX6SX_PAD_SD4_DATA0__VDEC_DEBUG_13 0x0280 0x05C8 0x0000 0x8 0x0
	#define MX6SX_PAD_SD4_DATA0__SDMA_DEBUG_MODE 0x0280 0x05C8 0x0000 0x9 0x0
	#define MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x0284 0x05CC 0x0000 0x0 0x0
	#define MX6SX_PAD_SD4_DATA1__RAWNAND_DATA11 0x0284 0x05CC 0x0000 0x1 0x0
	#define MX6SX_PAD_SD4_DATA1__ECSPI2_SCLK 0x0284 0x05CC 0x0720 0x2 0x1
	#define MX6SX_PAD_SD4_DATA1__AUDMUX_AUD3_TXC 0x0284 0x05CC 0x063C 0x3 0x0
	#define MX6SX_PAD_SD4_DATA1__LCDIF2_DATA_11 0x0284 0x05CC 0x0000 0x4 0x0
	#define MX6SX_PAD_SD4_DATA1__GPIO6_IO_15 0x0284 0x05CC 0x0000 0x5 0x0
	#define MX6SX_PAD_SD4_DATA1__ECSPI3_RDY 0x0284 0x05CC 0x0000 0x6 0x0
	#define MX6SX_PAD_SD4_DATA1__TPSMP_HDATA_22 0x0284 0x05CC 0x0000 0x7 0x0
	#define MX6SX_PAD_SD4_DATA1__VDEC_DEBUG_14 0x0284 0x05CC 0x0000 0x8 0x0
	#define MX6SX_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR 0x0284 0x05CC 0x0000 0x9 0x0
	#define MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x0288 0x05D0 0x0000 0x0 0x0
	#define MX6SX_PAD_SD4_DATA2__RAWNAND_DATA12 0x0288 0x05D0 0x0000 0x1 0x0
	#define MX6SX_PAD_SD4_DATA2__I2C2_SDA 0x0288 0x05D0 0x07B4 0x2 0x0
	#define MX6SX_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS 0x0288 0x05D0 0x0640 0x3 0x0
	#define MX6SX_PAD_SD4_DATA2__LCDIF2_DATA_10 0x0288 0x05D0 0x0000 0x4 0x0
	#define MX6SX_PAD_SD4_DATA2__GPIO6_IO_16 0x0288 0x05D0 0x0000 0x5 0x0
	#define MX6SX_PAD_SD4_DATA2__ECSPI2_SS3 0x0288 0x05D0 0x0000 0x6 0x0
	#define MX6SX_PAD_SD4_DATA2__TPSMP_HDATA_23 0x0288 0x05D0 0x0000 0x7 0x0
	#define MX6SX_PAD_SD4_DATA2__VDEC_DEBUG_15 0x0288 0x05D0 0x0000 0x8 0x0
	#define MX6SX_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB 0x0288 0x05D0 0x0000 0x9 0x0
	#define MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x028C 0x05D4 0x0000 0x0 0x0
	#define MX6SX_PAD_SD4_DATA3__RAWNAND_DATA13 0x028C 0x05D4 0x0000 0x1 0x0
	#define MX6SX_PAD_SD4_DATA3__I2C2_SCL 0x028C 0x05D4 0x07B0 0x2 0x0
	#define MX6SX_PAD_SD4_DATA3__AUDMUX_AUD3_TXD 0x028C 0x05D4 0x0630 0x3 0x0
	#define MX6SX_PAD_SD4_DATA3__LCDIF2_DATA_9 0x028C 0x05D4 0x0000 0x4 0x0
	#define MX6SX_PAD_SD4_DATA3__GPIO6_IO_17 0x028C 0x05D4 0x0000 0x5 0x0
	#define MX6SX_PAD_SD4_DATA3__ECSPI2_RDY 0x028C 0x05D4 0x0000 0x6 0x0
	#define MX6SX_PAD_SD4_DATA3__TPSMP_HDATA_24 0x028C 0x05D4 0x0000 0x7 0x0
	#define MX6SX_PAD_SD4_DATA3__VDEC_DEBUG_16 0x028C 0x05D4 0x0000 0x8 0x0
	#define MX6SX_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS 0x028C 0x05D4 0x0000 0x9 0x0
	#define MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x0290 0x05D8 0x0000 0x0 0x0
	#define MX6SX_PAD_SD4_DATA4__RAWNAND_DATA09 0x0290 0x05D8 0x0000 0x1 0x0
	-#define MX6SX_PAD_SD4_DATA4__UART5_RX 0x0290 0x05D8 0x0850 0x2 0x0
	-#define MX6SX_PAD_SD4_DATA4__UART5_TX 0x0290 0x05D8 0x0000 0x2 0x0
	+#define MX6SX_PAD_SD4_DATA4__UART5_DCE_RX 0x0290 0x05D8 0x0850 0x2 0x0
	+#define MX6SX_PAD_SD4_DATA4__UART5_DTE_TX 0x0290 0x05D8 0x0000 0x2 0x0
	#define MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK 0x0290 0x05D8 0x0730 0x3 0x0
	#define MX6SX_PAD_SD4_DATA4__LCDIF2_DATA_8 0x0290 0x05D8 0x0000 0x4 0x0
	#define MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x0290 0x05D8 0x0000 0x5 0x0
	#define MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x0290 0x05D8 0x0000 0x6 0x0
	#define MX6SX_PAD_SD4_DATA4__TPSMP_HDATA_16 0x0290 0x05D8 0x0000 0x7 0x0
	#define MX6SX_PAD_SD4_DATA4__USB_OTG_HOST_MODE 0x0290 0x05D8 0x0000 0x8 0x0
	#define MX6SX_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE 0x0290 0x05D8 0x0000 0x9 0x0
	#define MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x0294 0x05DC 0x0000 0x0 0x0
	#define MX6SX_PAD_SD4_DATA5__RAWNAND_CE2_B 0x0294 0x05DC 0x0000 0x1 0x0
	-#define MX6SX_PAD_SD4_DATA5__UART5_RX 0x0294 0x05DC 0x0850 0x2 0x1
	-#define MX6SX_PAD_SD4_DATA5__UART5_TX 0x0294 0x05DC 0x0000 0x2 0x0
	+#define MX6SX_PAD_SD4_DATA5__UART5_DCE_TX 0x0294 0x05DC 0x0000 0x2 0x0
	+#define MX6SX_PAD_SD4_DATA5__UART5_DTE_RX 0x0294 0x05DC 0x0850 0x2 0x1
	#define MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI 0x0294 0x05DC 0x0738 0x3 0x0
	#define MX6SX_PAD_SD4_DATA5__LCDIF2_DATA_7 0x0294 0x05DC 0x0000 0x4 0x0
	#define MX6SX_PAD_SD4_DATA5__GPIO6_IO_19 0x0294 0x05DC 0x0000 0x5 0x0
	#define MX6SX_PAD_SD4_DATA5__SPDIF_IN 0x0294 0x05DC 0x0824 0x6 0x0
	#define MX6SX_PAD_SD4_DATA5__TPSMP_HDATA_17 0x0294 0x05DC 0x0000 0x7 0x0
	#define MX6SX_PAD_SD4_DATA5__VDEC_DEBUG_9 0x0294 0x05DC 0x0000 0x8 0x0
	#define MX6SX_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 0x0294 0x05DC 0x0000 0x9 0x0
	#define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0
	#define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0
	-#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298 0x05E0 0x084C 0x2 0x0
	+#define MX6SX_PAD_SD4_DATA6__UART5_DCE_RTS 0x0298 0x05E0 0x084C 0x2 0x0
	+#define MX6SX_PAD_SD4_DATA6__UART5_DTE_CTS 0x0298 0x05E0 0x0000 0x2 0x0
	#define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0
	#define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0
	#define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0
	#define MX6SX_PAD_SD4_DATA6__USDHC4_WP 0x0298 0x05E0 0x0878 0x6 0x0
	#define MX6SX_PAD_SD4_DATA6__TPSMP_HDATA_18 0x0298 0x05E0 0x0000 0x7 0x0
	#define MX6SX_PAD_SD4_DATA6__VDEC_DEBUG_10 0x0298 0x05E0 0x0000 0x8 0x0
	#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0
	#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0
	#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0
	-#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0
	+#define MX6SX_PAD_SD4_DATA7__UART5_DCE_CTS 0x029C 0x05E4 0x0000 0x2 0x0
	+#define MX6SX_PAD_SD4_DATA7__UART5_DTE_RTS 0x029C 0x05E4 0x084C 0x2 0x1
	#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0
	#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0
	#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0
	#define MX6SX_PAD_SD4_DATA7__USDHC4_CD_B 0x029C 0x05E4 0x0874 0x6 0x0
	#define MX6SX_PAD_SD4_DATA7__TPSMP_HDATA_15 0x029C 0x05E4 0x0000 0x7 0x0
	#define MX6SX_PAD_SD4_DATA7__USB_OTG_PWR_WAKE 0x029C 0x05E4 0x0000 0x8 0x0
	#define MX6SX_PAD_SD4_DATA7__SDMA_DEBUG_YIELD 0x029C 0x05E4 0x0000 0x9 0x0
	#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x02A0 0x05E8 0x0000 0x0 0x0
	#define MX6SX_PAD_SD4_RESET_B__RAWNAND_DQS 0x02A0 0x05E8 0x0000 0x1 0x0
	#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET 0x02A0 0x05E8 0x0000 0x2 0x0
	#define MX6SX_PAD_SD4_RESET_B__AUDMUX_MCLK 0x02A0 0x05E8 0x0000 0x3 0x0
	#define MX6SX_PAD_SD4_RESET_B__LCDIF2_RESET 0x02A0 0x05E8 0x0000 0x4 0x0
	#define MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x02A0 0x05E8 0x0000 0x5 0x0
	#define MX6SX_PAD_SD4_RESET_B__LCDIF2_CS 0x02A0 0x05E8 0x0000 0x6 0x0
	#define MX6SX_PAD_SD4_RESET_B__TPSMP_HDATA_25 0x02A0 0x05E8 0x0000 0x7 0x0
	#define MX6SX_PAD_SD4_RESET_B__VDEC_DEBUG_17 0x02A0 0x05E8 0x0000 0x8 0x0
	#define MX6SX_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2 0x02A0 0x05E8 0x0000 0x9 0x0
	#define MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x02A4 0x05EC 0x0000 0x0 0x0
	#define MX6SX_PAD_USB_H_DATA__PWM2_OUT 0x02A4 0x05EC 0x0000 0x1 0x0
	#define MX6SX_PAD_USB_H_DATA__ANATOP_24M_OUT 0x02A4 0x05EC 0x0000 0x2 0x0
	#define MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x02A4 0x05EC 0x07C4 0x3 0x1
	#define MX6SX_PAD_USB_H_DATA__WDOG3_WDOG_B 0x02A4 0x05EC 0x0000 0x4 0x0
	#define MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 0x02A4 0x05EC 0x0000 0x5 0x0
	#define MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x02A8 0x05F0 0x0000 0x0 0x0
	#define MX6SX_PAD_USB_H_STROBE__PWM1_OUT 0x02A8 0x05F0 0x0000 0x1 0x0
	#define MX6SX_PAD_USB_H_STROBE__ANATOP_32K_OUT 0x02A8 0x05F0 0x0000 0x2 0x0
	#define MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x02A8 0x05F0 0x07C0 0x3 0x1
	#define MX6SX_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB 0x02A8 0x05F0 0x0000 0x4 0x0
	#define MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x02A8 0x05F0 0x0000 0x5 0x0

	+/* these are not supposed to be used any more and remove them after some time */
	+#define MX6SX_PAD_GPIO1_IO04__UART1_RX MX6SX_PAD_GPIO1_IO04__UART1_DTE_RX
	+#define MX6SX_PAD_GPIO1_IO04__UART1_TX MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX
	+#define MX6SX_PAD_GPIO1_IO05__UART1_RX MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX
	+#define MX6SX_PAD_GPIO1_IO05__UART1_TX MX6SX_PAD_GPIO1_IO05__UART1_DTE_TX
	+#define MX6SX_PAD_GPIO1_IO06__UART2_RX MX6SX_PAD_GPIO1_IO06__UART2_DTE_RX
	+#define MX6SX_PAD_GPIO1_IO06__UART2_TX MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX
	+#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B MX6SX_PAD_GPIO1_IO06__UART1_DCE_RTS
	+#define MX6SX_PAD_GPIO1_IO07__UART2_RX MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX
	+#define MX6SX_PAD_GPIO1_IO07__UART2_TX MX6SX_PAD_GPIO1_IO07__UART2_DTE_TX
	+#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B MX6SX_PAD_GPIO1_IO07__UART1_DCE_CTS
	+#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B MX6SX_PAD_GPIO1_IO08__UART2_DCE_RTS
	+#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B MX6SX_PAD_GPIO1_IO09__UART2_DCE_CTS
	+#define MX6SX_PAD_CSI_DATA04__UART6_RX MX6SX_PAD_CSI_DATA04__UART6_DCE_RX
	+#define MX6SX_PAD_CSI_DATA04__UART6_TX MX6SX_PAD_CSI_DATA04__UART6_DTE_TX
	+#define MX6SX_PAD_CSI_DATA05__UART6_RX MX6SX_PAD_CSI_DATA05__UART6_DTE_RX
	+#define MX6SX_PAD_CSI_DATA05__UART6_TX MX6SX_PAD_CSI_DATA05__UART6_DCE_TX
	+#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS
	+#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS
	+#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B MX6SX_PAD_CSI_HSYNC__UART4_DCE_RTS
	+#define MX6SX_PAD_CSI_MCLK__UART4_RX MX6SX_PAD_CSI_MCLK__UART4_DCE_RX
	+#define MX6SX_PAD_CSI_MCLK__UART4_TX MX6SX_PAD_CSI_MCLK__UART4_DTE_TX
	+#define MX6SX_PAD_CSI_PIXCLK__UART4_RX MX6SX_PAD_CSI_PIXCLK__UART4_DTE_RX
	+#define MX6SX_PAD_CSI_PIXCLK__UART4_TX MX6SX_PAD_CSI_PIXCLK__UART4_DCE_TX
	+#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B MX6SX_PAD_CSI_VSYNC__UART4_DCE_CTS
	+#define MX6SX_PAD_ENET2_COL__UART1_RX MX6SX_PAD_ENET2_COL__UART1_DCE_RX
	+#define MX6SX_PAD_ENET2_COL__UART1_TX MX6SX_PAD_ENET2_COL__UART1_DTE_TX
	+#define MX6SX_PAD_ENET2_CRS__UART1_RX MX6SX_PAD_ENET2_CRS__UART1_DTE_RX
	+#define MX6SX_PAD_ENET2_CRS__UART1_TX MX6SX_PAD_ENET2_CRS__UART1_DCE_TX
	+#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B MX6SX_PAD_ENET2_RX_CLK__UART1_DCE_RTS
	+#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B MX6SX_PAD_ENET2_TX_CLK__UART1_DCE_CTS
	+#define MX6SX_PAD_KEY_COL0__UART6_RTS_B MX6SX_PAD_KEY_COL0__UART6_DCE_RTS
	+#define MX6SX_PAD_KEY_COL1__UART6_RX MX6SX_PAD_KEY_COL1__UART6_DTE_RX
	+#define MX6SX_PAD_KEY_COL1__UART6_TX MX6SX_PAD_KEY_COL1__UART6_DCE_TX
	+#define MX6SX_PAD_KEY_COL2__UART5_RTS_B MX6SX_PAD_KEY_COL2__UART5_DCE_RTS
	+#define MX6SX_PAD_KEY_COL3__UART5_RX MX6SX_PAD_KEY_COL3__UART5_DTE_RX
	+#define MX6SX_PAD_KEY_COL3__UART5_TX MX6SX_PAD_KEY_COL3__UART5_DCE_TX
	+#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B MX6SX_PAD_KEY_ROW0__UART6_DCE_CTS
	+#define MX6SX_PAD_KEY_ROW1__UART6_RX MX6SX_PAD_KEY_ROW1__UART6_DCE_RX
	+#define MX6SX_PAD_KEY_ROW1__UART6_TX MX6SX_PAD_KEY_ROW1__UART6_DTE_TX
	+#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS
	+#define MX6SX_PAD_KEY_ROW3__UART5_RX MX6SX_PAD_KEY_ROW3__UART5_DCE_RX
	+#define MX6SX_PAD_KEY_ROW3__UART5_TX MX6SX_PAD_KEY_ROW3__UART5_DTE_TX
	+#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B MX6SX_PAD_NAND_DATA04__UART3_DCE_RTS
	+#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B MX6SX_PAD_NAND_DATA05__UART3_DCE_CTS
	+#define MX6SX_PAD_NAND_DATA06__UART3_RX MX6SX_PAD_NAND_DATA06__UART3_DCE_RX
	+#define MX6SX_PAD_NAND_DATA06__UART3_TX MX6SX_PAD_NAND_DATA06__UART3_DTE_TX
	+#define MX6SX_PAD_NAND_DATA07__UART3_RX MX6SX_PAD_NAND_DATA07__UART3_DTE_RX
	+#define MX6SX_PAD_NAND_DATA07__UART3_TX MX6SX_PAD_NAND_DATA07__UART3_DCE_TX
	+#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B MX6SX_PAD_QSPI1B_DATA0__UART3_DCE_CTS
	+#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B MX6SX_PAD_QSPI1B_DATA1__UART3_DCE_RTS
	+#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX
	+#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX
	+#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX MX6SX_PAD_QSPI1B_SS0_B__UART3_DTE_RX
	+#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX
	+#define MX6SX_PAD_SD1_DATA0__UART2_RX MX6SX_PAD_SD1_DATA0__UART2_DCE_RX
	+#define MX6SX_PAD_SD1_DATA0__UART2_TX MX6SX_PAD_SD1_DATA0__UART2_DTE_TX
	+#define MX6SX_PAD_SD1_DATA1__UART2_RX MX6SX_PAD_SD1_DATA1__UART2_DTE_RX
	+#define MX6SX_PAD_SD1_DATA1__UART2_TX MX6SX_PAD_SD1_DATA1__UART2_DCE_TX
	+#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B MX6SX_PAD_SD1_DATA2__UART2_DCE_CTS
	+#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B MX6SX_PAD_SD1_DATA3__UART2_DCE_RTS
	+#define MX6SX_PAD_SD2_DATA0__UART4_RX MX6SX_PAD_SD2_DATA0__UART4_DCE_RX
	+#define MX6SX_PAD_SD2_DATA0__UART4_TX MX6SX_PAD_SD2_DATA0__UART4_DTE_TX
	+#define MX6SX_PAD_SD2_DATA1__UART4_RX MX6SX_PAD_SD2_DATA1__UART4_DTE_RX
	+#define MX6SX_PAD_SD2_DATA1__UART4_TX MX6SX_PAD_SD2_DATA1__UART4_DCE_TX
	+#define MX6SX_PAD_SD2_DATA2__UART6_RX MX6SX_PAD_SD2_DATA2__UART6_DCE_RX
	+#define MX6SX_PAD_SD2_DATA2__UART6_TX MX6SX_PAD_SD2_DATA2__UART6_DTE_TX
	+#define MX6SX_PAD_SD2_DATA3__UART6_RX MX6SX_PAD_SD2_DATA3__UART6_DTE_RX
	+#define MX6SX_PAD_SD2_DATA3__UART6_TX MX6SX_PAD_SD2_DATA3__UART6_DCE_TX
	+#define MX6SX_PAD_SD3_CLK__UART4_CTS_B MX6SX_PAD_SD3_CLK__UART4_DCE_CTS
	+#define MX6SX_PAD_SD3_CMD__UART4_RX MX6SX_PAD_SD3_CMD__UART4_DTE_RX
	+#define MX6SX_PAD_SD3_CMD__UART4_TX MX6SX_PAD_SD3_CMD__UART4_DCE_TX
	+#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B MX6SX_PAD_SD3_DATA2__UART4_DCE_RTS
	+#define MX6SX_PAD_SD3_DATA3__UART4_RX MX6SX_PAD_SD3_DATA3__UART4_DCE_RX
	+#define MX6SX_PAD_SD3_DATA3__UART4_TX MX6SX_PAD_SD3_DATA3__UART4_DTE_TX
	+#define MX6SX_PAD_SD3_DATA4__UART3_RX MX6SX_PAD_SD3_DATA4__UART3_DCE_RX
	+#define MX6SX_PAD_SD3_DATA4__UART3_TX MX6SX_PAD_SD3_DATA4__UART3_DTE_TX
	+#define MX6SX_PAD_SD3_DATA5__UART3_RX MX6SX_PAD_SD3_DATA5__UART3_DTE_RX
	+#define MX6SX_PAD_SD3_DATA5__UART3_TX MX6SX_PAD_SD3_DATA5__UART3_DCE_TX
	+#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS
	+#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS
	+#define MX6SX_PAD_SD4_DATA4__UART5_RX MX6SX_PAD_SD4_DATA4__UART5_DCE_RX
	+#define MX6SX_PAD_SD4_DATA4__UART5_TX MX6SX_PAD_SD4_DATA4__UART5_DTE_TX
	+#define MX6SX_PAD_SD4_DATA5__UART5_RX MX6SX_PAD_SD4_DATA5__UART5_DTE_RX
	+#define MX6SX_PAD_SD4_DATA5__UART5_TX MX6SX_PAD_SD4_DATA5__UART5_DCE_TX
	+#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B MX6SX_PAD_SD4_DATA6__UART5_DCE_RTS
	+#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B MX6SX_PAD_SD4_DATA7__UART5_DCE_CTS
	+
	#endif /* __DTS_IMX6SX_PINFUNC_H */
	diff --git a/sys/gnu/dts/arm/imx6sx-sabreauto.dts b/sys/gnu/dts/arm/imx6sx-sabreauto.dts
	index 315044ccd65f..825924448ab4 100644
	--- a/sys/gnu/dts/arm/imx6sx-sabreauto.dts
	+++ b/sys/gnu/dts/arm/imx6sx-sabreauto.dts
	@@ -1,461 +1,461 @@
	// SPDX-License-Identifier: GPL-2.0
	//
	// Copyright (C) 2014 Freescale Semiconductor, Inc.

	/dts-v1/;

	#include "imx6sx.dtsi"

	/ {
	model = "Freescale i.MX6 SoloX Sabre Auto Board";
	compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";

	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x80000000>;
	};

	leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_led>;

	user {
	label = "debug";
	gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	};
	};

	vcc_sd3: regulator-vcc-sd3 {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_vcc_sd3>;
	regulator-name = "VCC_SD3";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_can_wake: regulator-can-wake {
	compatible = "regulator-fixed";
	regulator-name = "can-wake";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_can_en: regulator-can-en {
	compatible = "regulator-fixed";
	regulator-name = "can-en";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&reg_can_wake>;
	};

	reg_can_stby: regulator-can-stby {
	compatible = "regulator-fixed";
	regulator-name = "can-stby";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&reg_can_en>;
	};
	};

	&anaclk2 {
	clock-frequency = <24576000>;
	};

	&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy1>;
	fsl,magic-packet;
	status = "okay";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy0: ethernet-phy@0 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <0>;
	};

	ethphy1: ethernet-phy@1 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <1>;
	};
	};
	};

	&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";
	};

	&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can_stby>;
	status = "okay";
	};

	&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_can_stby>;
	status = "okay";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
	};

	&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
	keep-power-in-suspend;
	wakeup-source;
	vmmc-supply = <&vcc_sd3>;
	status = "okay";
	};

	&usdhc4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4>;
	bus-width = <8>;
	cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
	no-1-8-v;
	keep-power-in-suspend;
	wakeup-source;
	status = "okay";
	};

	&iomuxc {
	pinctrl_egalax_int: egalax-intgrp {
	fsl,pins = <
	MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0
	>;
	};

	pinctrl_enet1: enet1grp {
	fsl,pins = <
	MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
	MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
	MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
	MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
	MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
	MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
	MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
	MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
	MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
	MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
	MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
	MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
	MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
	MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
	>;
	};

	pinctrl_enet2: enet2grp {
	fsl,pins = <
	MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
	MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
	MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
	MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
	MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
	MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
	MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
	MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
	MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
	MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
	MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
	MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
	>;
	};

	pinctrl_flexcan1: flexcan1grp {
	fsl,pins = <
	MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
	MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
	>;
	};

	pinctrl_flexcan2: flexcan2grp {
	fsl,pins = <
	MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
	MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
	MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
	MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
	>;
	};

	pinctrl_led: ledgrp {
	fsl,pins = <
	MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	- MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
	- MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
	+ MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
	+ MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
	MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
	MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
	MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
	MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
	MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
	MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
	MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
	MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
	MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
	MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
	MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
	>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
	fsl,pins = <
	MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
	MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
	MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
	MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
	MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
	MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
	MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
	MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
	MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
	MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
	>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
	fsl,pins = <
	MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
	MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
	MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
	MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
	MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
	MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
	MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
	MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
	MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
	MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
	>;
	};

	pinctrl_usdhc4: usdhc4grp {
	fsl,pins = <
	MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
	MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
	MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
	MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
	MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
	MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
	MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
	MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
	>;
	};

	pinctrl_vcc_sd3: vccsd3grp {
	fsl,pins = <
	MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
	>;
	};

	pinctrl_wdog: wdoggrp {
	fsl,pins = <
	MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
	>;
	};
	};

	&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	touchscreen@4 {
	compatible = "eeti,egalax_ts";
	reg = <0x04>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_egalax_int>;
	interrupt-parent = <&gpio6>;
	interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
	wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>;
	};

	pfuze100: pmic@8 {
	compatible = "fsl,pfuze100";
	reg = <0x08>;

	regulators {
	sw1a_reg: sw1ab {
	regulator-min-microvolt = <300000>;
	regulator-max-microvolt = <1875000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	sw1c_reg: sw1c {
	regulator-min-microvolt = <300000>;
	regulator-max-microvolt = <1875000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	sw2_reg: sw2 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw3a_reg: sw3a {
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <1975000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw3b_reg: sw3b {
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <1975000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw4_reg: sw4 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	swbst_reg: swbst {
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5150000>;
	};

	snvs_reg: vsnvs {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <3000000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vref_reg: vrefddr {
	regulator-boot-on;
	regulator-always-on;
	};

	vgen1_reg: vgen1 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	regulator-always-on;
	};

	vgen2_reg: vgen2 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	};

	vgen3_reg: vgen3 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen4_reg: vgen4 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen5_reg: vgen5 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen6_reg: vgen6 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};
	};
	};

	max7322: gpio@68 {
	compatible = "maxim,max7322";
	reg = <0x68>;
	gpio-controller;
	#gpio-cells = <2>;
	};
	};

	&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	max7310_a: gpio@30 {
	compatible = "maxim,max7310";
	reg = <0x30>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	max7310_b: gpio@32 {
	compatible = "maxim,max7310";
	reg = <0x32>;
	gpio-controller;
	#gpio-cells = <2>;
	};
	};

	&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	};
	diff --git a/sys/gnu/dts/arm/imx6sx-sdb.dtsi b/sys/gnu/dts/arm/imx6sx-sdb.dtsi
	index f6972deb5e39..3e5fb72f21fc 100644
	--- a/sys/gnu/dts/arm/imx6sx-sdb.dtsi
	+++ b/sys/gnu/dts/arm/imx6sx-sdb.dtsi
	@@ -1,676 +1,676 @@
	// SPDX-License-Identifier: GPL-2.0
	//
	// Copyright (C) 2014 Freescale Semiconductor, Inc.

	/dts-v1/;

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include "imx6sx.dtsi"

	/ {
	model = "Freescale i.MX6 SoloX SDB Board";
	compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";

	chosen {
	stdout-path = &uart1;
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x40000000>;
	};

	backlight_display: backlight-display {
	compatible = "pwm-backlight";
	pwms = <&pwm3 0 5000000>;
	brightness-levels = <0 4 8 16 32 64 128 255>;
	default-brightness-level = <6>;
	};

	gpio-keys {
	compatible = "gpio-keys";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_keys>;

	volume-up {
	label = "Volume Up";
	gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_VOLUMEUP>;
	wakeup-source;
	};

	volume-down {
	label = "Volume Down";
	gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_VOLUMEDOWN>;
	wakeup-source;
	};
	};

	vcc_sd3: regulator-vcc-sd3 {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_vcc_sd3>;
	regulator-name = "VCC_SD3";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1>;
	regulator-name = "usb_otg1_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg2>;
	regulator-name = "usb_otg2_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_psu_5v: regulator-psu-5v {
	compatible = "regulator-fixed";
	regulator-name = "PSU-5V0";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	};

	reg_lcd_3v3: regulator-lcd-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "lcd-3v3";
	gpio = <&gpio3 27 0>;
	enable-active-high;
	};

	reg_peri_3v3: regulator-peri-3v3 {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_peri_3v3>;
	regulator-name = "peri_3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	regulator-always-on;
	};

	reg_enet_3v3: regulator-enet-3v3 {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet_3v3>;
	regulator-name = "enet_3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_pcie_gpio: regulator-pcie-gpio {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie_reg>;
	regulator-name = "MPCIE_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_lcd_5v: regulator-lcd-5v {
	compatible = "regulator-fixed";
	regulator-name = "lcd-5v0";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	};

	reg_can_en: regulator-can-en {
	compatible = "regulator-fixed";
	regulator-name = "can-en";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	reg_can_stby: regulator-can-stby {
	compatible = "regulator-fixed";
	regulator-name = "can-stby";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	sound {
	compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
	model = "wm8962-audio";
	ssi-controller = <&ssi2>;
	audio-codec = <&codec>;
	audio-routing =
	"Headphone Jack", "HPOUTL",
	"Headphone Jack", "HPOUTR",
	"Ext Spk", "SPKOUTL",
	"Ext Spk", "SPKOUTR",
	"AMIC", "MICBIAS",
	"IN3R", "AMIC";
	mux-int-port = <2>;
	mux-ext-port = <6>;
	};

	panel {
	compatible = "sii,43wvf1g";
	backlight = <&backlight_display>;
	dvdd-supply = <&reg_lcd_3v3>;
	avdd-supply = <&reg_lcd_5v>;

	port {
	panel_in: endpoint {
	remote-endpoint = <&display_out>;
	};
	};
	};
	};

	&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
	};

	&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-supply = <&reg_enet_3v3>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy1>;
	phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
	status = "okay";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy1: ethernet-phy@1 {
	reg = <1>;
	};

	ethphy2: ethernet-phy@2 {
	reg = <2>;
	};
	};
	};

	&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy2>;
	status = "okay";
	};

	&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can_stby>;
	status = "okay";
	};

	&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_can_stby>;
	status = "okay";
	};

	&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
	};

	&i2c4 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	status = "okay";

	codec: wm8962@1a {
	compatible = "wlf,wm8962";
	reg = <0x1a>;
	clocks = <&clks IMX6SX_CLK_AUDIO>;
	DCVDD-supply = <&vgen4_reg>;
	DBVDD-supply = <&vgen4_reg>;
	AVDD-supply = <&vgen4_reg>;
	CPVDD-supply = <&vgen4_reg>;
	MICVDD-supply = <&vgen3_reg>;
	PLLVDD-supply = <&vgen4_reg>;
	SPKVDD1-supply = <&reg_psu_5v>;
	SPKVDD2-supply = <&reg_psu_5v>;
	};
	};

	&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>;
	vpcie-supply = <&reg_pcie_gpio>;
	status = "okay";
	};

	&lcdif1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcd>;
	status = "okay";

	port {
	display_out: endpoint {
	remote-endpoint = <&panel_in>;
	};
	};
	};

	&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "okay";
	};

	&snvs_poweroff {
	status = "okay";
	};

	&sai1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	status = "disabled";
	};

	&ssi2 {
	status = "okay";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
	};

	&uart5 { /* for bluetooth */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	uart-has-rtscts;
	status = "okay";
	};

	&usbotg1 {
	vbus-supply = <&reg_usb_otg1_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1_id>;
	status = "okay";
	};

	&usbotg2 {
	vbus-supply = <&reg_usb_otg2_vbus>;
	dr_mode = "host";
	status = "okay";
	};

	&usbphy1 {
	fsl,tx-d-cal = <106>;
	};

	&usbphy2 {
	fsl,tx-d-cal = <106>;
	};

	&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	non-removable;
	no-1-8-v;
	keep-power-in-suspend;
	wakeup-source;
	status = "okay";
	};

	&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
	keep-power-in-suspend;
	wakeup-source;
	vmmc-supply = <&vcc_sd3>;
	status = "okay";
	};

	&usdhc4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4>;
	cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
	status = "okay";
	};

	&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	};

	&iomuxc {
	imx6x-sdb {
	pinctrl_audmux: audmuxgrp {
	fsl,pins = <
	MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
	MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
	MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
	MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
	MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
	>;
	};

	pinctrl_enet1: enet1grp {
	fsl,pins = <
	MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
	MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
	MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
	MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
	MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
	MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
	MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
	MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
	MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
	MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
	MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
	MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
	MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
	MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
	MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
	/* phy reset */
	MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x10b0
	>;
	};

	pinctrl_enet_3v3: enet3v3grp {
	fsl,pins = <
	MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
	>;
	};

	pinctrl_enet2: enet2grp {
	fsl,pins = <
	MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
	MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
	MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
	MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
	MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
	MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
	MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
	MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
	MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
	MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
	MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
	MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
	>;
	};

	pinctrl_flexcan1: flexcan1grp {
	fsl,pins = <
	MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
	MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
	>;
	};

	pinctrl_flexcan2: flexcan2grp {
	fsl,pins = <
	MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
	MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020
	>;
	};

	pinctrl_gpio_keys: gpio_keysgrp {
	fsl,pins = <
	MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
	MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
	MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
	MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
	>;
	};

	pinctrl_i2c4: i2c4grp {
	fsl,pins = <
	MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
	MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
	>;
	};

	pinctrl_lcd: lcdgrp {
	fsl,pins = <
	MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
	MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
	MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
	MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
	MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
	MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
	MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
	MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
	MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
	MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
	MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
	MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
	MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
	MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
	MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
	MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
	MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
	MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
	MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
	MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
	MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
	MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
	MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
	MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
	MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
	MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
	MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
	MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
	MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
	>;
	};

	pinctrl_pcie: pciegrp {
	fsl,pins = <
	MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
	>;
	};

	pinctrl_pcie_reg: pciereggrp {
	fsl,pins = <
	MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0
	>;
	};

	pinctrl_peri_3v3: peri3v3grp {
	fsl,pins = <
	MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
	>;
	};

	pinctrl_pwm3: pwm3grp-1 {
	fsl,pins = <
	MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
	>;
	};

	pinctrl_qspi2: qspi2grp {
	fsl,pins = <
	MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
	MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
	MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
	MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
	MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
	MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
	MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
	MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
	MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
	MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
	MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
	MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
	>;
	};

	pinctrl_vcc_sd3: vccsd3grp {
	fsl,pins = <
	MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
	>;
	};

	pinctrl_sai1: sai1grp {
	fsl,pins = <
	MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0
	MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0
	MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0
	MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0
	MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	- MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
	- MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
	+ MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
	+ MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
	>;
	};

	pinctrl_uart5: uart5grp {
	fsl,pins = <
	- MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
	- MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
	- MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
	- MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
	+ MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1
	+ MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1
	+ MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x1b0b1
	+ MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x1b0b1
	>;
	};

	pinctrl_usb_otg1: usbotg1grp {
	fsl,pins = <
	MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
	>;
	};

	pinctrl_usb_otg1_id: usbotg1idgrp {
	fsl,pins = <
	MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
	>;
	};

	pinctrl_usb_otg2: usbot2ggrp {
	fsl,pins = <
	MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
	>;
	};

	pinctrl_usdhc2: usdhc2grp {
	fsl,pins = <
	MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
	MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
	MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
	MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
	MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
	MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
	MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
	MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
	MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
	MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
	MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
	MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
	MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
	MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
	MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
	MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
	MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
	>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
	fsl,pins = <
	MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
	MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
	MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
	MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
	MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
	MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
	MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
	MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
	MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
	MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
	>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
	fsl,pins = <
	MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
	MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
	MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
	MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
	MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
	MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
	MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
	MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
	MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
	MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
	>;
	};

	pinctrl_usdhc4: usdhc4grp {
	fsl,pins = <
	MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
	MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
	MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
	MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
	MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
	MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
	MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
	MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
	>;
	};

	pinctrl_wdog: wdoggrp {
	fsl,pins = <
	MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
	>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6sx-softing-vining-2000.dts b/sys/gnu/dts/arm/imx6sx-softing-vining-2000.dts
	index 28563f21024e..6b728b03f1f2 100644
	--- a/sys/gnu/dts/arm/imx6sx-softing-vining-2000.dts
	+++ b/sys/gnu/dts/arm/imx6sx-softing-vining-2000.dts
	@@ -1,570 +1,584 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2016 Christoph Fritz <chf.fritz@googlemail.com>
	*/

	/dts-v1/;

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include "imx6sx.dtsi"

	/ {
	model = "Softing VIN\|ING 2000";
	compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx";

	chosen {
	stdout-path = &uart1;
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x40000000>;
	};

	reg_usb_otg1_vbus: regulator-usb_otg1_vbus {
	compatible = "regulator-fixed";
	regulator-name = "usb_otg1_vbus";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1>;
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_peri_3v3: regulator-peri_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "peri_3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	pwmleds {
	compatible = "pwm-leds";

	red {
	label = "red";
	max-brightness = <255>;
	pwms = <&pwm6 0 50000>;
	};

	green {
	label = "green";
	max-brightness = <255>;
	pwms = <&pwm2 0 50000>;
	};

	blue {
	label = "blue";
	max-brightness = <255>;
	pwms = <&pwm1 0 50000>;
	};
	};
	};

	&adc1 {
	vref-supply = <&reg_peri_3v3>;
	status = "okay";
	};

	&cpu0 {
	/*
	* This board has a shared rail of reg_arm and reg_soc (supplied by
	* sw1a_reg) which is modeled below, but still this module behaves
	* unstable without higher voltages. Hence, set higher voltages here.
	*/
	operating-points = <
	/* kHz uV */
	996000 1250000
	792000 1175000
	396000 1175000
	198000 1175000
	>;
	fsl,soc-operating-points = <
	/* ARM kHz SOC uV */
	996000 1250000
	792000 1175000
	396000 1175000
	198000 1175000
	>;
	};

	&ecspi4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi4>;
	cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
	status = "okay";
	};

	&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-supply = <&reg_peri_3v3>;
	phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <5>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy0: ethernet0-phy@0 {
	reg = <0>;
	max-speed = <100>;
	interrupt-parent = <&gpio2>;
	interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
	};
	};
	};

	&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	phy-supply = <&reg_peri_3v3>;
	phy-reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <5>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	status = "okay";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy1: ethernet1-phy@0 {
	reg = <0>;
	max-speed = <100>;
	interrupt-parent = <&gpio2>;
	interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
	};
	};
	};

	&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "okay";
	};

	&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	status = "okay";
	};

	&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	proximity: sx9500@28 {
	compatible = "semtech,sx9500";
	reg = <0x28>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sx9500>;
	interrupt-parent = <&gpio2>;
	interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
	reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
	};

	pmic: pfuze100@8 {
	compatible = "fsl,pfuze200";
	reg = <0x08>;

	regulators {
	sw1a_reg: sw1ab {
	regulator-min-microvolt = <300000>;
	regulator-max-microvolt = <1875000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	sw2_reg: sw2 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw3a_reg: sw3a {
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <1975000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw3b_reg: sw3b {
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <1975000>;
	regulator-boot-on;
	regulator-always-on;
	};

	snvs_reg: vsnvs {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <3000000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vref_reg: vrefddr {
	regulator-boot-on;
	regulator-always-on;
	};

	vgen1_reg: vgen1 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	regulator-always-on;
	};

	vgen2_reg: vgen2 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	};

	vgen3_reg: vgen3 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen4_reg: vgen4 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen5_reg: vgen5 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen6_reg: vgen6 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};
	};
	};
	};

	&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
	};

	&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpios>;

	pinctrl_ecspi4: ecspi4grp {
	fsl,pins = <
	MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x130b1
	MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x130b1
	MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x130b1
	MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x30b0
	>;
	};

	pinctrl_enet1: enet1grp {
	fsl,pins = <
	MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x30c1
	MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x30c1
	MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0f9
	MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0f9
	MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x30c1
	MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0f9
	MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4000a038
	/* LAN8720 PHY Reset */
	MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x10b0
	/* MDIO */
	MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0f9
	MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0f9
	/* IRQ from PHY */
	MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x10b0
	>;
	};

	pinctrl_enet2: enet2grp {
	fsl,pins = <
	MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x1b0b0
	MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x1b0b0
	MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x1b0b0
	MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x1b0b0
	MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x1b0b0
	MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x1b0b0
	MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4000a038
	/* LAN8720 PHY Reset */
	MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x10b0
	/* MDIO */
	MX6SX_PAD_ENET1_COL__ENET2_MDC 0xa0f9
	MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0xa0f9
	/* IRQ from PHY */
	MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x10b0
	>;
	};

	pinctrl_flexcan1: flexcan1grp {
	fsl,pins = <
	MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0
	MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0
	>;
	};

	pinctrl_flexcan2: flexcan2grp {
	fsl,pins = <
	MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0
	MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0
	>;
	};

	pinctrl_gpios: gpiosgrp {
	fsl,pins = <
	/* reset external uC */
	MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x10b0
	/* IRQ from external uC */
	MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x10b0
	/* overcurrent detection */
	MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x10b0
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
	MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6SX_PAD_NAND_ALE__I2C3_SDA 0x4001b8b1
	MX6SX_PAD_NAND_CLE__I2C3_SCL 0x4001b8b1
	>;
	};

	+ pinctrl_pcie: pciegrp {
	+ fsl,pins = <
	+ MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x10b0
	+ >;
	+ };
	+
	pinctrl_pwm1: pwm1grp-1 {
	fsl,pins = <
	/* blue LED */
	MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm2: pwm2grp-1 {
	fsl,pins = <
	/* green LED */
	MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x1b0b1
	>;
	};

	pinctrl_pwm6: pwm6grp-1 {
	fsl,pins = <
	/* red LED */
	MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x1b0b1
	>;
	};

	pinctrl_sx9500: sx9500grp {
	fsl,pins = <
	/* Reset */
	MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x838
	/* IRQ */
	MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x70e0
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	- MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
	- MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
	+ MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
	+ MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	- MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
	- MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
	+ MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1
	+ MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1
	>;
	};

	pinctrl_usb_otg1: usbotg1grp {
	fsl,pins = <
	MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
	>;
	};

	pinctrl_usb_otg1_id: usbotg1idgrp {
	fsl,pins = <
	MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
	>;
	};

	pinctrl_usdhc2_50mhz: usdhc2grp-50mhz {
	fsl,pins = <
	MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
	MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
	MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
	MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
	MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
	MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
	MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x1b000
	MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x10b0
	>;
	};

	pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
	fsl,pins = <
	MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100b9
	MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170b9
	MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170b9
	MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170b9
	MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170b9
	MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170b9
	>;
	};

	pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
	fsl,pins = <
	MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100f9
	MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170f9
	MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170f9
	MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170f9
	MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170f9
	MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170f9
	>;
	};

	pinctrl_usdhc4_50mhz: usdhc4grp-50mhz {
	fsl,pins = <
	MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
	MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
	MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
	MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
	MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
	MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
	MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
	MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
	MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
	MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
	MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17068
	>;
	};

	pinctrl_usdhc4_100mhz: usdhc4-100mhz {
	fsl,pins = <
	MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
	MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
	MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
	MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
	MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
	MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
	MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
	MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
	MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
	MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
	>;
	};

	pinctrl_usdhc4_200mhz: usdhc4-200mhz {
	fsl,pins = <
	MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
	MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
	MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
	MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
	MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
	MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
	MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
	MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
	MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
	MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
	>;
	};
	};

	+&pcie {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_pcie>;
	+ reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
	+ reset-gpio-active-high;
	+ status = "okay";
	+};
	+
	&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "okay";
	};

	&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	status = "okay";
	};

	&pwm6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm6>;
	status = "okay";
	};

	&reg_arm {
	vin-supply = <&sw1a_reg>;
	};

	&reg_soc {
	vin-supply = <&sw1a_reg>;
	};

	&snvs_poweroff {
	status = "okay";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
	};

	&usbotg1 {
	vbus-supply = <&reg_usb_otg1_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1_id>;
	status = "okay";
	};

	&usbotg2 {
	dr_mode = "host";
	status = "okay";
	};

	&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2_50mhz>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
	cd-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
	keep-power-in-suspend;
	status = "okay";
	};

	&usdhc4 {
	/* hs200-mode is currently unsupported because Vccq is on 3.1V, but
	* not on necessary 1.8V.
	*/
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc4_50mhz>;
	pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
	bus-width = <8>;
	keep-power-in-suspend;
	non-removable;
	cap-mmc-hw-reset;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/imx6sx-udoo-neo.dtsi b/sys/gnu/dts/arm/imx6sx-udoo-neo.dtsi
	index 25d4aa985a69..ee645655090d 100644
	--- a/sys/gnu/dts/arm/imx6sx-udoo-neo.dtsi
	+++ b/sys/gnu/dts/arm/imx6sx-udoo-neo.dtsi
	@@ -1,410 +1,410 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2016 Andreas Färber
	*/

	#include "imx6sx.dtsi"

	/ {
	compatible = "fsl,imx6sx";

	chosen {
	stdout-path = "serial0:115200n8";
	};

	leds {
	compatible = "gpio-leds";

	red {
	label = "udoo-neo:red:mmc";
	gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	linux,default-trigger = "mmc0";
	};

	orange {
	label = "udoo-neo:orange:user";
	gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
	default-state = "keep";
	};
	};

	reg_sdio_pwr: regulator-sdio-pwr {
	compatible = "regulator-fixed";
	gpio = <&gpio6 1 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	regulator-name = "SDIO_PWR";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	};

	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_otg1_reg>;
	regulator-name = "usb_otg1_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_otg2_reg>;
	regulator-name = "usb_otg2_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_wlan: regulator-wlan {
	compatible = "regulator-fixed";
	regulator-name = "wlan-en-regulator";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
	startup-delay-us = <70000>;
	enable-active-high;
	};
	};

	&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-reset-duration = <10>;
	phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
	};

	&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	clock-frequency = <100000>;
	status = "okay";

	pmic: pmic@8 {
	compatible = "fsl,pfuze3000";
	reg = <0x08>;

	regulators {
	sw1a_reg: sw1a {
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1475000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	sw1c_reg: sw1b {
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1475000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	sw2_reg: sw2 {
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1850000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw3a_reg: sw3 {
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1650000>;
	regulator-boot-on;
	regulator-always-on;
	};

	swbst_reg: swbst {
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5150000>;
	};

	snvs_reg: vsnvs {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <3000000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vref_reg: vrefddr {
	regulator-boot-on;
	regulator-always-on;
	};

	vgen1_reg: vldo1 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen2_reg: vldo2 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	};

	vgen3_reg: vccsd {
	regulator-min-microvolt = <2850000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen4_reg: v33 {
	regulator-min-microvolt = <2850000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen5_reg: vldo3 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen6_reg: vldo4 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};
	};
	};
	};

	&i2c2 { /* Brick snap in sensors connector */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	clock-frequency = <100000>;
	status = "okay";
	};

	&i2c4 { /* Onboard Motion sensors */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	clock-frequency = <100000>;
	status = "disabled";
	};

	&iomuxc {
	pinctrl_bt_reg: btreggrp {
	fsl,pins =
	<MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x15059>;
	};

	pinctrl_enet1: enet1grp {
	fsl,pins =
	<MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0xa0b1>,
	<MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1>,
	<MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1>,
	<MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1>,
	<MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1>,
	<MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1>,

	<MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x3081>,
	<MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x3081>,
	<MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081>,
	<MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081>,
	<MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081>,
	<MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x3081>,

	<MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins =
	<MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1>,
	<MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins =
	<MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1>,
	<MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1>;
	};

	pinctrl_i2c4: i2c4grp {
	fsl,pins =
	<MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x4001b8b1>,
	<MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x4001b8b1>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins =
	- <MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1>,
	- <MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1>;
	+ <MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1>,
	+ <MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins =
	- <MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1>,
	- <MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1>;
	+ <MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1>,
	+ <MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1>;
	};

	pinctrl_uart3: uart3grp {
	fsl,pins =
	- <MX6SX_PAD_SD3_DATA4__UART3_RX 0x13059>,
	- <MX6SX_PAD_SD3_DATA5__UART3_TX 0x13059>,
	- <MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x13059>,
	- <MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x13059>;
	+ <MX6SX_PAD_SD3_DATA4__UART3_DCE_RX 0x13059>,
	+ <MX6SX_PAD_SD3_DATA5__UART3_DCE_TX 0x13059>,
	+ <MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x13059>,
	+ <MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x13059>;
	};

	pinctrl_uart5: uart5grp {
	fsl,pins =
	- <MX6SX_PAD_SD4_DATA4__UART5_RX 0x1b0b1>,
	- <MX6SX_PAD_SD4_DATA5__UART5_TX 0x1b0b1>;
	+ <MX6SX_PAD_SD4_DATA4__UART5_DCE_RX 0x1b0b1>,
	+ <MX6SX_PAD_SD4_DATA5__UART5_DCE_TX 0x1b0b1>;
	};

	pinctrl_uart6: uart6grp {
	fsl,pins =
	<MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x1b0b1>,
	<MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x1b0b1>,
	<MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x1b0b1>,
	<MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x1b0b1>,
	- <MX6SX_PAD_CSI_DATA04__UART6_RX 0x1b0b1>,
	- <MX6SX_PAD_CSI_DATA05__UART6_TX 0x1b0b1>,
	- <MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x1b0b1>,
	- <MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x1b0b1>;
	+ <MX6SX_PAD_CSI_DATA04__UART6_DCE_RX 0x1b0b1>,
	+ <MX6SX_PAD_CSI_DATA05__UART6_DCE_TX 0x1b0b1>,
	+ <MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS 0x1b0b1>,
	+ <MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS 0x1b0b1>;
	};

	pinctrl_otg1_reg: otg1grp {
	fsl,pins =
	<MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0>;
	};


	pinctrl_otg2_reg: otg2grp {
	fsl,pins =
	<MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x10b0>;
	};

	pinctrl_usb_otg1: usbotg1grp {
	fsl,pins =
	<MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059>,
	<MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x10b0>;
	};

	pinctrl_usb_otg2: usbot2ggrp {
	fsl,pins =
	<MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x10b0>;
	};

	pinctrl_usdhc2: usdhc2grp {
	fsl,pins =
	<MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059>,
	<MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059>,
	<MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059>,
	<MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059>,
	<MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059>,
	<MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059>,
	<MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059>; /* CD */
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins =
	<MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x15059>,
	<MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x13059>,
	<MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17069>,
	<MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17069>,
	<MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17069>,
	<MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17069>,
	<MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17069>,
	<MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10069>,
	<MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x10059>;
	};
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
	};

	/* Cortex-M4 serial */
	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "disabled";
	};

	&uart3 { /* Bluetooth - only on Extended/Full versions */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	uart-has-rtscts;
	status = "disabled";

	bluetooth {
	compatible = "ti,wl1831-st";
	enable-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_bt_reg>;
	max-speed = <921600>;
	};
	};

	/* Arduino serial */
	&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	status = "disabled";
	};

	&uart6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart6>;
	uart-has-rtscts;
	status = "disabled";
	};

	&usbotg1 { /* J2 micro USB port */
	vbus-supply = <&reg_usb_otg1_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1>;
	status = "okay";
	};

	&usbotg2 { /* J3 host USB port */
	vbus-supply = <&reg_usb_otg2_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg2>;
	dr_mode = "host";
	status = "okay";
	};

	&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	vmmc-supply = <&reg_sdio_pwr>;
	bus-width = <4>;
	cd-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
	no-1-8-v;
	keep-power-in-suspend;
	wakeup-source;
	status = "okay";
	};

	&usdhc3 { /* Wi-Fi */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	non-removable;
	vmmc-supply = <&reg_wlan>;
	cap-power-off-card;
	wakeup-source;
	keep-power-in-suspend;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	wlcore: wlcore@2 {
	compatible = "ti,wl1831";
	reg = <2>;
	interrupt-parent = <&gpio2>;
	interrupts = <16 IRQ_TYPE_EDGE_RISING>;
	ref-clock-frequency = <38400000>;
	tcxo-clock-frequency = <26000000>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6sx.dtsi b/sys/gnu/dts/arm/imx6sx.dtsi
	index 59bad60a47dc..d6f831731460 100644
	--- a/sys/gnu/dts/arm/imx6sx.dtsi
	+++ b/sys/gnu/dts/arm/imx6sx.dtsi
	@@ -1,1395 +1,1401 @@
	// SPDX-License-Identifier: GPL-2.0
	//
	// Copyright 2014 Freescale Semiconductor, Inc.

	#include <dt-bindings/clock/imx6sx-clock.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include "imx6sx-pinfunc.h"

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	* The decompressor and also some bootloaders rely on a
	* pre-existing /chosen node to be available to insert the
	* command line and merge other ATAGS info.
	*/
	chosen {};

	aliases {
	can0 = &flexcan1;
	can1 = &flexcan2;
	ethernet0 = &fec1;
	ethernet1 = &fec2;
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	gpio3 = &gpio4;
	gpio4 = &gpio5;
	gpio5 = &gpio6;
	gpio6 = &gpio7;
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	i2c2 = &i2c3;
	i2c3 = &i2c4;
	mmc0 = &usdhc1;
	mmc1 = &usdhc2;
	mmc2 = &usdhc3;
	mmc3 = &usdhc4;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	serial4 = &uart5;
	serial5 = &uart6;
	spi0 = &ecspi1;
	spi1 = &ecspi2;
	spi2 = &ecspi3;
	spi3 = &ecspi4;
	spi4 = &ecspi5;
	usbphy0 = &usbphy1;
	usbphy1 = &usbphy2;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <0>;
	next-level-cache = <&L2>;
	operating-points = <
	/* kHz uV */
	996000 1250000
	792000 1175000
	396000 1075000
	198000 975000
	>;
	fsl,soc-operating-points = <
	/* ARM kHz SOC uV */
	996000 1175000
	792000 1175000
	396000 1175000
	198000 1175000
	>;
	clock-latency = <61036>; /* two CLK32 periods */
	#cooling-cells = <2>;
	clocks = <&clks IMX6SX_CLK_ARM>,
	<&clks IMX6SX_CLK_PLL2_PFD2>,
	<&clks IMX6SX_CLK_STEP>,
	<&clks IMX6SX_CLK_PLL1_SW>,
	<&clks IMX6SX_CLK_PLL1_SYS>;
	clock-names = "arm", "pll2_pfd2_396m", "step",
	"pll1_sw", "pll1_sys";
	arm-supply = <&reg_arm>;
	soc-supply = <&reg_soc>;
	+ nvmem-cells = <&cpu_speed_grade>;
	+ nvmem-cell-names = "speed_grade";
	};
	};

	ckil: clock-ckil {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "ckil";
	};

	osc: clock-osc {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "osc";
	};

	ipp_di0: clock-ipp-di0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	clock-output-names = "ipp_di0";
	};

	ipp_di1: clock-ipp-di1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	clock-output-names = "ipp_di1";
	};

	anaclk1: clock-anaclk1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	clock-output-names = "anaclk1";
	};

	anaclk2: clock-anaclk2 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	clock-output-names = "anaclk2";
	};

	tempmon: tempmon {
	compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
	interrupt-parent = <&gpc>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	fsl,tempmon = <&anatop>;
	nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
	nvmem-cell-names = "calib", "temp_grade";
	clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
	};

	pmu {
	compatible = "arm,cortex-a9-pmu";
	interrupt-parent = <&gpc>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	};

	usbphynop1: usbphynop1 {
	compatible = "usb-nop-xceiv";
	#phy-cells = <0>;
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&gpc>;
	ranges;

	ocram_s: sram@8f8000 {
	compatible = "mmio-sram";
	reg = <0x008f8000 0x4000>;
	clocks = <&clks IMX6SX_CLK_OCRAM_S>;
	};

	ocram: sram@900000 {
	compatible = "mmio-sram";
	reg = <0x00900000 0x20000>;
	clocks = <&clks IMX6SX_CLK_OCRAM>;
	};

	intc: interrupt-controller@a01000 {
	compatible = "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x00a01000 0x1000>,
	<0x00a00100 0x100>;
	interrupt-parent = <&intc>;
	};

	L2: l2-cache@a02000 {
	compatible = "arm,pl310-cache";
	reg = <0x00a02000 0x1000>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	cache-unified;
	cache-level = <2>;
	arm,tag-latency = <4 2 3>;
	arm,data-latency = <4 2 3>;
	};

	gpu: gpu@1800000 {
	compatible = "vivante,gc";
	reg = <0x01800000 0x4000>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_GPU>,
	<&clks IMX6SX_CLK_GPU>,
	<&clks IMX6SX_CLK_GPU>;
	clock-names = "bus", "core", "shader";
	power-domains = <&pd_pu>;
	};

	dma_apbh: dma-apbh@1804000 {
	compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
	reg = <0x01804000 0x2000>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
	#dma-cells = <1>;
	dma-channels = <4>;
	clocks = <&clks IMX6SX_CLK_APBH_DMA>;
	};

	gpmi: gpmi-nand@1806000{
	compatible = "fsl,imx6sx-gpmi-nand";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
	reg-names = "gpmi-nand", "bch";
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "bch";
	clocks = <&clks IMX6SX_CLK_GPMI_IO>,
	<&clks IMX6SX_CLK_GPMI_APB>,
	<&clks IMX6SX_CLK_GPMI_BCH>,
	<&clks IMX6SX_CLK_GPMI_BCH_APB>,
	<&clks IMX6SX_CLK_PER1_BCH>;
	clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
	"gpmi_bch_apb", "per1_bch";
	dmas = <&dma_apbh 0>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	- aips1: aips-bus@2000000 {
	+ aips1: bus@2000000 {
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02000000 0x100000>;
	ranges;

	spba-bus@2000000 {
	compatible = "fsl,spba-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02000000 0x40000>;
	ranges;

	spdif: spdif@2004000 {
	compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
	reg = <0x02004000 0x4000>;
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 14 18 0>,
	<&sdma 15 18 0>;
	dma-names = "rx", "tx";
	clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
	<&clks IMX6SX_CLK_OSC>,
	<&clks IMX6SX_CLK_SPDIF>,
	<&clks 0>, <&clks 0>, <&clks 0>,
	<&clks IMX6SX_CLK_IPG>,
	<&clks 0>, <&clks 0>,
	<&clks IMX6SX_CLK_SPBA>;
	clock-names = "core", "rxtx0",
	"rxtx1", "rxtx2",
	"rxtx3", "rxtx4",
	"rxtx5", "rxtx6",
	"rxtx7", "spba";
	status = "disabled";
	};

	ecspi1: spi@2008000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
	reg = <0x02008000 0x4000>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_ECSPI1>,
	<&clks IMX6SX_CLK_ECSPI1>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ecspi2: spi@200c000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
	reg = <0x0200c000 0x4000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_ECSPI2>,
	<&clks IMX6SX_CLK_ECSPI2>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ecspi3: spi@2010000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
	reg = <0x02010000 0x4000>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_ECSPI3>,
	<&clks IMX6SX_CLK_ECSPI3>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ecspi4: spi@2014000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
	reg = <0x02014000 0x4000>;
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_ECSPI4>,
	<&clks IMX6SX_CLK_ECSPI4>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart1: serial@2020000 {
	compatible = "fsl,imx6sx-uart",
	"fsl,imx6q-uart", "fsl,imx21-uart";
	reg = <0x02020000 0x4000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_UART_IPG>,
	<&clks IMX6SX_CLK_UART_SERIAL>;
	clock-names = "ipg", "per";
	dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	esai: esai@2024000 {
	reg = <0x02024000 0x4000>;
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
	<&clks IMX6SX_CLK_ESAI_MEM>,
	<&clks IMX6SX_CLK_ESAI_EXTAL>,
	<&clks IMX6SX_CLK_ESAI_IPG>,
	<&clks IMX6SX_CLK_SPBA>;
	clock-names = "core", "mem", "extal",
	"fsys", "spba";
	status = "disabled";
	};

	ssi1: ssi@2028000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
	reg = <0x02028000 0x4000>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
	<&clks IMX6SX_CLK_SSI1>;
	clock-names = "ipg", "baud";
	dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	ssi2: ssi@202c000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
	reg = <0x0202c000 0x4000>;
	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
	<&clks IMX6SX_CLK_SSI2>;
	clock-names = "ipg", "baud";
	dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	ssi3: ssi@2030000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
	reg = <0x02030000 0x4000>;
	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
	<&clks IMX6SX_CLK_SSI3>;
	clock-names = "ipg", "baud";
	dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
	status = "disabled";
	};

	asrc: asrc@2034000 {
	reg = <0x02034000 0x4000>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
	<&clks IMX6SX_CLK_ASRC_IPG>,
	<&clks IMX6SX_CLK_SPDIF>,
	<&clks IMX6SX_CLK_SPBA>;
	clock-names = "mem", "ipg", "asrck", "spba";
	dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
	<&sdma 19 20 1>, <&sdma 20 20 1>,
	<&sdma 21 20 1>, <&sdma 22 20 1>;
	dma-names = "rxa", "rxb", "rxc",
	"txa", "txb", "txc";
	status = "okay";
	};
	};

	pwm1: pwm@2080000 {
	compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
	reg = <0x02080000 0x4000>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_PWM1>,
	<&clks IMX6SX_CLK_PWM1>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	};

	pwm2: pwm@2084000 {
	compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
	reg = <0x02084000 0x4000>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_PWM2>,
	<&clks IMX6SX_CLK_PWM2>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	};

	pwm3: pwm@2088000 {
	compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
	reg = <0x02088000 0x4000>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_PWM3>,
	<&clks IMX6SX_CLK_PWM3>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	};

	pwm4: pwm@208c000 {
	compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
	reg = <0x0208c000 0x4000>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_PWM4>,
	<&clks IMX6SX_CLK_PWM4>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	};

	flexcan1: can@2090000 {
	compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
	reg = <0x02090000 0x4000>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
	<&clks IMX6SX_CLK_CAN1_SERIAL>;
	clock-names = "ipg", "per";
	fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
	status = "disabled";
	};

	flexcan2: can@2094000 {
	compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
	reg = <0x02094000 0x4000>;
	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
	<&clks IMX6SX_CLK_CAN2_SERIAL>;
	clock-names = "ipg", "per";
	fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
	status = "disabled";
	};

	- gpt: gpt@2098000 {
	+ gpt: timer@2098000 {
	compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
	reg = <0x02098000 0x4000>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_GPT_BUS>,
	<&clks IMX6SX_CLK_GPT_3M>;
	clock-names = "ipg", "per";
	};

	gpio1: gpio@209c000 {
	compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
	reg = <0x0209c000 0x4000>;
	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 5 26>;
	};

	gpio2: gpio@20a0000 {
	compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
	reg = <0x020a0000 0x4000>;
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 31 20>;
	};

	gpio3: gpio@20a4000 {
	compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
	reg = <0x020a4000 0x4000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 51 29>;
	};

	gpio4: gpio@20a8000 {
	compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
	reg = <0x020a8000 0x4000>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 80 32>;
	};

	gpio5: gpio@20ac000 {
	compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
	reg = <0x020ac000 0x4000>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 112 24>;
	};

	gpio6: gpio@20b0000 {
	compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
	reg = <0x020b0000 0x4000>;
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
	};

	gpio7: gpio@20b4000 {
	compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
	reg = <0x020b4000 0x4000>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
	};

	- kpp: kpp@20b8000 {
	+ kpp: keypad@20b8000 {
	compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
	reg = <0x020b8000 0x4000>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_IPG>;
	status = "disabled";
	};

	- wdog1: wdog@20bc000 {
	+ wdog1: watchdog@20bc000 {
	compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
	reg = <0x020bc000 0x4000>;
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_IPG>;
	};

	- wdog2: wdog@20c0000 {
	+ wdog2: watchdog@20c0000 {
	compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
	reg = <0x020c0000 0x4000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_IPG>;
	status = "disabled";
	};

	- clks: ccm@20c4000 {
	+ clks: clock-controller@20c4000 {
	compatible = "fsl,imx6sx-ccm";
	reg = <0x020c4000 0x4000>;
	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	#clock-cells = <1>;
	clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
	clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
	};

	anatop: anatop@20c8000 {
	compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
	"syscon", "simple-mfd";
	reg = <0x020c8000 0x1000>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;

	reg_vdd1p1: regulator-1p1 {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vdd1p1";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	anatop-reg-offset = <0x110>;
	anatop-vol-bit-shift = <8>;
	anatop-vol-bit-width = <5>;
	anatop-min-bit-val = <4>;
	anatop-min-voltage = <800000>;
	anatop-max-voltage = <1375000>;
	anatop-enable-bit = <0>;
	};

	reg_vdd3p0: regulator-3p0 {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vdd3p0";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <3150000>;
	regulator-always-on;
	anatop-reg-offset = <0x120>;
	anatop-vol-bit-shift = <8>;
	anatop-vol-bit-width = <5>;
	anatop-min-bit-val = <0>;
	anatop-min-voltage = <2625000>;
	anatop-max-voltage = <3400000>;
	anatop-enable-bit = <0>;
	};

	reg_vdd2p5: regulator-2p5 {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vdd2p5";
	regulator-min-microvolt = <2250000>;
	regulator-max-microvolt = <2750000>;
	regulator-always-on;
	anatop-reg-offset = <0x130>;
	anatop-vol-bit-shift = <8>;
	anatop-vol-bit-width = <5>;
	anatop-min-bit-val = <0>;
	anatop-min-voltage = <2100000>;
	anatop-max-voltage = <2875000>;
	anatop-enable-bit = <0>;
	};

	reg_arm: regulator-vddcore {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vddarm";
	regulator-min-microvolt = <725000>;
	regulator-max-microvolt = <1450000>;
	regulator-always-on;
	anatop-reg-offset = <0x140>;
	anatop-vol-bit-shift = <0>;
	anatop-vol-bit-width = <5>;
	anatop-delay-reg-offset = <0x170>;
	anatop-delay-bit-shift = <24>;
	anatop-delay-bit-width = <2>;
	anatop-min-bit-val = <1>;
	anatop-min-voltage = <725000>;
	anatop-max-voltage = <1450000>;
	};

	reg_pcie: regulator-vddpcie {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vddpcie";
	regulator-min-microvolt = <725000>;
	regulator-max-microvolt = <1450000>;
	anatop-reg-offset = <0x140>;
	anatop-vol-bit-shift = <9>;
	anatop-vol-bit-width = <5>;
	anatop-delay-reg-offset = <0x170>;
	anatop-delay-bit-shift = <26>;
	anatop-delay-bit-width = <2>;
	anatop-min-bit-val = <1>;
	anatop-min-voltage = <725000>;
	anatop-max-voltage = <1450000>;
	};

	reg_soc: regulator-vddsoc {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vddsoc";
	regulator-min-microvolt = <725000>;
	regulator-max-microvolt = <1450000>;
	regulator-always-on;
	anatop-reg-offset = <0x140>;
	anatop-vol-bit-shift = <18>;
	anatop-vol-bit-width = <5>;
	anatop-delay-reg-offset = <0x170>;
	anatop-delay-bit-shift = <28>;
	anatop-delay-bit-width = <2>;
	anatop-min-bit-val = <1>;
	anatop-min-voltage = <725000>;
	anatop-max-voltage = <1450000>;
	};
	};

	usbphy1: usbphy@20c9000 {
	compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
	reg = <0x020c9000 0x1000>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_USBPHY1>;
	fsl,anatop = <&anatop>;
	};

	usbphy2: usbphy@20ca000 {
	compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
	reg = <0x020ca000 0x1000>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_USBPHY2>;
	fsl,anatop = <&anatop>;
	};

	snvs: snvs@20cc000 {
	compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
	reg = <0x020cc000 0x4000>;

	snvs_rtc: snvs-rtc-lp {
	compatible = "fsl,sec-v4.0-mon-rtc-lp";
	regmap = <&snvs>;
	offset = <0x34>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	};

	snvs_poweroff: snvs-poweroff {
	compatible = "syscon-poweroff";
	regmap = <&snvs>;
	offset = <0x38>;
	value = <0x60>;
	mask = <0x60>;
	status = "disabled";
	};

	snvs_pwrkey: snvs-powerkey {
	compatible = "fsl,sec-v4.0-pwrkey";
	regmap = <&snvs>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	linux,keycode = <KEY_POWER>;
	wakeup-source;
	status = "disabled";
	};
	};

	epit1: epit@20d0000 {
	reg = <0x020d0000 0x4000>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	};

	epit2: epit@20d4000 {
	reg = <0x020d4000 0x4000>;
	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	};

	src: src@20d8000 {
	compatible = "fsl,imx6sx-src", "fsl,imx51-src";
	reg = <0x020d8000 0x4000>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	#reset-cells = <1>;
	};

	gpc: gpc@20dc000 {
	compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
	reg = <0x020dc000 0x4000>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-parent = <&intc>;
	clocks = <&clks IMX6SX_CLK_IPG>;
	clock-names = "ipg";

	pgc {
	#address-cells = <1>;
	#size-cells = <0>;

	power-domain@0 {
	reg = <0>;
	#power-domain-cells = <0>;
	};

	pd_pu: power-domain@1 {
	reg = <1>;
	#power-domain-cells = <0>;
	power-supply = <&reg_soc>;
	clocks = <&clks IMX6SX_CLK_GPU>;
	};

	pd_disp: power-domain@2 {
	reg = <2>;
	#power-domain-cells = <0>;
	clocks = <&clks IMX6SX_CLK_PXP_AXI>,
	<&clks IMX6SX_CLK_DISPLAY_AXI>,
	<&clks IMX6SX_CLK_LCDIF1_PIX>,
	<&clks IMX6SX_CLK_LCDIF_APB>,
	<&clks IMX6SX_CLK_LCDIF2_PIX>,
	<&clks IMX6SX_CLK_CSI>,
	<&clks IMX6SX_CLK_VADC>;
	};

	pd_pci: power-domain@3 {
	reg = <3>;
	#power-domain-cells = <0>;
	power-supply = <&reg_pcie>;
	};
	};
	};

	- iomuxc: iomuxc@20e0000 {
	+ iomuxc: pinctrl@20e0000 {
	compatible = "fsl,imx6sx-iomuxc";
	reg = <0x020e0000 0x4000>;
	};

	gpr: iomuxc-gpr@20e4000 {
	compatible = "fsl,imx6sx-iomuxc-gpr",
	"fsl,imx6q-iomuxc-gpr", "syscon";
	reg = <0x020e4000 0x4000>;
	};

	sdma: sdma@20ec000 {
	compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
	reg = <0x020ec000 0x4000>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_IPG>,
	<&clks IMX6SX_CLK_SDMA>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	/* imx6sx reuses imx6q sdma firmware */
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
	};
	};

	- aips2: aips-bus@2100000 {
	+ aips2: bus@2100000 {
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02100000 0x100000>;
	ranges;

	- crypto: caam@2100000 {
	+ crypto: crypto@2100000 {
	compatible = "fsl,sec-v4.0";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x2100000 0x10000>;
	ranges = <0 0x2100000 0x10000>;
	interrupt-parent = <&intc>;
	clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
	<&clks IMX6SX_CLK_CAAM_ACLK>,
	<&clks IMX6SX_CLK_CAAM_IPG>,
	<&clks IMX6SX_CLK_EIM_SLOW>;
	clock-names = "mem", "aclk", "ipg", "emi_slow";

	- sec_jr0: jr0@1000 {
	+ sec_jr0: jr@1000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x1000 0x1000>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	};

	- sec_jr1: jr1@2000 {
	+ sec_jr1: jr@2000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x2000 0x1000>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	usbotg1: usb@2184000 {
	compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
	reg = <0x02184000 0x200>;
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_USBOH3>;
	fsl,usbphy = <&usbphy1>;
	fsl,usbmisc = <&usbmisc 0>;
	fsl,anatop = <&anatop>;
	ahb-burst-config = <0x0>;
	tx-burst-size-dword = <0x10>;
	rx-burst-size-dword = <0x10>;
	status = "disabled";
	};

	usbotg2: usb@2184200 {
	compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
	reg = <0x02184200 0x200>;
	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_USBOH3>;
	fsl,usbphy = <&usbphy2>;
	fsl,usbmisc = <&usbmisc 1>;
	ahb-burst-config = <0x0>;
	tx-burst-size-dword = <0x10>;
	rx-burst-size-dword = <0x10>;
	status = "disabled";
	};

	usbh: usb@2184400 {
	compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
	reg = <0x02184400 0x200>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_USBOH3>;
	fsl,usbphy = <&usbphynop1>;
	fsl,usbmisc = <&usbmisc 2>;
	phy_type = "hsic";
	fsl,anatop = <&anatop>;
	dr_mode = "host";
	ahb-burst-config = <0x0>;
	tx-burst-size-dword = <0x10>;
	rx-burst-size-dword = <0x10>;
	status = "disabled";
	};

	usbmisc: usbmisc@2184800 {
	#index-cells = <1>;
	compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
	reg = <0x02184800 0x200>;
	clocks = <&clks IMX6SX_CLK_USBOH3>;
	};

	fec1: ethernet@2188000 {
	compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
	reg = <0x02188000 0x4000>;
	interrupt-names = "int0", "pps";
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_ENET>,
	<&clks IMX6SX_CLK_ENET_AHB>,
	<&clks IMX6SX_CLK_ENET_PTP>,
	<&clks IMX6SX_CLK_ENET_REF>,
	<&clks IMX6SX_CLK_ENET_PTP>;
	clock-names = "ipg", "ahb", "ptp",
	"enet_clk_ref", "enet_out";
	fsl,num-tx-queues = <3>;
	fsl,num-rx-queues = <3>;
	status = "disabled";
	};

	mlb: mlb@218c000 {
	reg = <0x0218c000 0x4000>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_MLB>;
	status = "disabled";
	};

	usdhc1: usdhc@2190000 {
	compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
	reg = <0x02190000 0x4000>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_USDHC1>,
	<&clks IMX6SX_CLK_USDHC1>,
	<&clks IMX6SX_CLK_USDHC1>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	usdhc2: usdhc@2194000 {
	compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
	reg = <0x02194000 0x4000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_USDHC2>,
	<&clks IMX6SX_CLK_USDHC2>,
	<&clks IMX6SX_CLK_USDHC2>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	usdhc3: usdhc@2198000 {
	compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
	reg = <0x02198000 0x4000>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_USDHC3>,
	<&clks IMX6SX_CLK_USDHC3>,
	<&clks IMX6SX_CLK_USDHC3>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	usdhc4: usdhc@219c000 {
	compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
	reg = <0x0219c000 0x4000>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_USDHC4>,
	<&clks IMX6SX_CLK_USDHC4>,
	<&clks IMX6SX_CLK_USDHC4>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	i2c1: i2c@21a0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
	reg = <0x021a0000 0x4000>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_I2C1>;
	status = "disabled";
	};

	i2c2: i2c@21a4000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
	reg = <0x021a4000 0x4000>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_I2C2>;
	status = "disabled";
	};

	i2c3: i2c@21a8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
	reg = <0x021a8000 0x4000>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_I2C3>;
	status = "disabled";
	};

	memory-controller@21b0000 {
	compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
	reg = <0x021b0000 0x4000>;
	clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;
	};

	fec2: ethernet@21b4000 {
	compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
	reg = <0x021b4000 0x4000>;
	interrupt-names = "int0", "pps";
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_ENET>,
	<&clks IMX6SX_CLK_ENET_AHB>,
	<&clks IMX6SX_CLK_ENET_PTP>,
	<&clks IMX6SX_CLK_ENET2_REF_125M>,
	<&clks IMX6SX_CLK_ENET_PTP>;
	clock-names = "ipg", "ahb", "ptp",
	"enet_clk_ref", "enet_out";
	status = "disabled";
	};

	weim: weim@21b8000 {
	#address-cells = <2>;
	#size-cells = <1>;
	compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
	reg = <0x021b8000 0x4000>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
	fsl,weim-cs-gpr = <&gpr>;
	status = "disabled";
	};

	- ocotp: ocotp@21bc000 {
	+ ocotp: ocotp-ctrl@21bc000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "fsl,imx6sx-ocotp", "syscon";
	reg = <0x021bc000 0x4000>;
	clocks = <&clks IMX6SX_CLK_OCOTP>;

	+ cpu_speed_grade: speed-grade@10 {
	+ reg = <0x10 4>;
	+ };
	+
	tempmon_calib: calib@38 {
	reg = <0x38 4>;
	};

	tempmon_temp_grade: temp-grade@20 {
	reg = <0x20 4>;
	};
	};

	sai1: sai@21d4000 {
	compatible = "fsl,imx6sx-sai";
	reg = <0x021d4000 0x4000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
	<&clks IMX6SX_CLK_SAI1>,
	<&clks 0>, <&clks 0>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dma-names = "rx", "tx";
	dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
	status = "disabled";
	};

	audmux: audmux@21d8000 {
	compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
	reg = <0x021d8000 0x4000>;
	status = "disabled";
	};

	sai2: sai@21dc000 {
	compatible = "fsl,imx6sx-sai";
	reg = <0x021dc000 0x4000>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
	<&clks IMX6SX_CLK_SAI2>,
	<&clks 0>, <&clks 0>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dma-names = "rx", "tx";
	dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
	status = "disabled";
	};

	qspi1: spi@21e0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sx-qspi";
	reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
	reg-names = "QuadSPI", "QuadSPI-memory";
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_QSPI1>,
	<&clks IMX6SX_CLK_QSPI1>;
	clock-names = "qspi_en", "qspi";
	status = "disabled";
	};

	qspi2: spi@21e4000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sx-qspi";
	reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
	reg-names = "QuadSPI", "QuadSPI-memory";
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_QSPI2>,
	<&clks IMX6SX_CLK_QSPI2>;
	clock-names = "qspi_en", "qspi";
	status = "disabled";
	};

	uart2: serial@21e8000 {
	compatible = "fsl,imx6sx-uart",
	"fsl,imx6q-uart", "fsl,imx21-uart";
	reg = <0x021e8000 0x4000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_UART_IPG>,
	<&clks IMX6SX_CLK_UART_SERIAL>;
	clock-names = "ipg", "per";
	dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart3: serial@21ec000 {
	compatible = "fsl,imx6sx-uart",
	"fsl,imx6q-uart", "fsl,imx21-uart";
	reg = <0x021ec000 0x4000>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_UART_IPG>,
	<&clks IMX6SX_CLK_UART_SERIAL>;
	clock-names = "ipg", "per";
	dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart4: serial@21f0000 {
	compatible = "fsl,imx6sx-uart",
	"fsl,imx6q-uart", "fsl,imx21-uart";
	reg = <0x021f0000 0x4000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_UART_IPG>,
	<&clks IMX6SX_CLK_UART_SERIAL>;
	clock-names = "ipg", "per";
	dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart5: serial@21f4000 {
	compatible = "fsl,imx6sx-uart",
	"fsl,imx6q-uart", "fsl,imx21-uart";
	reg = <0x021f4000 0x4000>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_UART_IPG>,
	<&clks IMX6SX_CLK_UART_SERIAL>;
	clock-names = "ipg", "per";
	dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c4: i2c@21f8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
	reg = <0x021f8000 0x4000>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_I2C4>;
	status = "disabled";
	};
	};

	- aips3: aips-bus@2200000 {
	+ aips3: bus@2200000 {
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02200000 0x100000>;
	ranges;

	spba-bus@2240000 {
	compatible = "fsl,spba-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02240000 0x40000>;
	ranges;

	csi1: csi@2214000 {
	reg = <0x02214000 0x4000>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
	<&clks IMX6SX_CLK_CSI>,
	<&clks IMX6SX_CLK_DCIC1>;
	clock-names = "disp-axi", "csi_mclk", "dcic";
	status = "disabled";
	};

	pxp: pxp@2218000 {
	compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
	reg = <0x02218000 0x4000>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_PXP_AXI>;
	clock-names = "axi";
	power-domains = <&pd_disp>;
	status = "disabled";
	};

	csi2: csi@221c000 {
	reg = <0x0221c000 0x4000>;
	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
	<&clks IMX6SX_CLK_CSI>,
	<&clks IMX6SX_CLK_DCIC2>;
	clock-names = "disp-axi", "csi_mclk", "dcic";
	status = "disabled";
	};

	lcdif1: lcdif@2220000 {
	compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
	reg = <0x02220000 0x4000>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
	<&clks IMX6SX_CLK_LCDIF_APB>,
	<&clks IMX6SX_CLK_DISPLAY_AXI>;
	clock-names = "pix", "axi", "disp_axi";
	power-domains = <&pd_disp>;
	status = "disabled";
	};

	lcdif2: lcdif@2224000 {
	compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
	reg = <0x02224000 0x4000>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
	<&clks IMX6SX_CLK_LCDIF_APB>,
	<&clks IMX6SX_CLK_DISPLAY_AXI>;
	clock-names = "pix", "axi", "disp_axi";
	power-domains = <&pd_disp>;
	status = "disabled";
	};

	vadc: vadc@2228000 {
	reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
	reg-names = "vadc-vafe", "vadc-vdec";
	clocks = <&clks IMX6SX_CLK_VADC>,
	<&clks IMX6SX_CLK_CSI>;
	clock-names = "vadc", "csi";
	power-domains = <&pd_disp>;
	status = "disabled";
	};
	};

	adc1: adc@2280000 {
	compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
	reg = <0x02280000 0x4000>;
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_IPG>;
	clock-names = "adc";
	fsl,adck-max-frequency = <30000000>, <40000000>,
	<20000000>;
	status = "disabled";
	};

	adc2: adc@2284000 {
	compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
	reg = <0x02284000 0x4000>;
	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_IPG>;
	clock-names = "adc";
	fsl,adck-max-frequency = <30000000>, <40000000>,
	<20000000>;
	status = "disabled";
	};

	- wdog3: wdog@2288000 {
	+ wdog3: watchdog@2288000 {
	compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
	reg = <0x02288000 0x4000>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_IPG>;
	status = "disabled";
	};

	ecspi5: spi@228c000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
	reg = <0x0228c000 0x4000>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_ECSPI5>,
	<&clks IMX6SX_CLK_ECSPI5>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart6: serial@22a0000 {
	compatible = "fsl,imx6sx-uart",
	"fsl,imx6q-uart", "fsl,imx21-uart";
	reg = <0x022a0000 0x4000>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_UART_IPG>,
	<&clks IMX6SX_CLK_UART_SERIAL>;
	clock-names = "ipg", "per";
	dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	pwm5: pwm@22a4000 {
	compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
	reg = <0x022a4000 0x4000>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_PWM5>,
	<&clks IMX6SX_CLK_PWM5>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	};

	pwm6: pwm@22a8000 {
	compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
	reg = <0x022a8000 0x4000>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_PWM6>,
	<&clks IMX6SX_CLK_PWM6>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	};

	pwm7: pwm@22ac000 {
	compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
	reg = <0x022ac000 0x4000>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_PWM7>,
	<&clks IMX6SX_CLK_PWM7>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	};

	pwm8: pwm@22b0000 {
	compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
	reg = <0x0022b0000 0x4000>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_PWM8>,
	<&clks IMX6SX_CLK_PWM8>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	};
	};

	pcie: pcie@8ffc000 {
	compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
	reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
	reg-names = "dbi", "config";
	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	bus-range = <0x00 0xff>;
	ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */
	0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
	num-lanes = <1>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
	<&clks IMX6SX_CLK_LVDS1_OUT>,
	<&clks IMX6SX_CLK_PCIE_REF_125M>,
	<&clks IMX6SX_CLK_DISPLAY_AXI>;
	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
	power-domains = <&pd_disp>, <&pd_pci>;
	power-domain-names = "pcie", "pcie_phy";
	status = "disabled";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6ul-ccimx6ulsbcpro.dts b/sys/gnu/dts/arm/imx6ul-ccimx6ulsbcpro.dts
	index 3749fdda3611..5d3805b07032 100644
	--- a/sys/gnu/dts/arm/imx6ul-ccimx6ulsbcpro.dts
	+++ b/sys/gnu/dts/arm/imx6ul-ccimx6ulsbcpro.dts
	@@ -1,427 +1,427 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Digi International's ConnectCore6UL SBC Pro board device tree source
	*
	* Copyright 2018 Digi International, Inc.
	*
	*/

	/dts-v1/;
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include "imx6ul.dtsi"
	#include "imx6ul-ccimx6ulsom.dtsi"

	/ {
	model = "Digi International ConnectCore 6UL SBC Pro.";
	compatible = "digi,ccimx6ulsbcpro", "digi,ccimx6ulsom", "fsl,imx6ul";

	lcd_backlight: backlight {
	compatible = "pwm-backlight";
	pwms = <&pwm5 0 50000>;
	brightness-levels = <0 4 8 16 32 64 128 255>;
	default-brightness-level = <6>;
	status = "okay";
	};

	panel {
	- compatible = "auo,g101evn010", "simple-panel";
	+ compatible = "auo,g101evn010";
	power-supply = <&ldo4_ext>;
	backlight = <&lcd_backlight>;

	port {
	panel_in: endpoint {
	remote-endpoint = <&display_out>;
	};
	};
	};

	reg_usb_otg1_vbus: regulator-usb-otg1 {
	compatible = "regulator-fixed";
	regulator-name = "usb_otg1_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};
	};

	&adc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc1>;
	status = "okay";
	};

	&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&ext_3v3>;
	status = "okay";
	};

	/* CAN2 is multiplexed with UART2 RTS/CTS */
	&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&ext_3v3>;
	status = "disabled";
	};

	&ecspi1 {
	cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1_master>;
	status = "okay";
	};

	&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	status = "okay";
	};

	&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <26>;
	status = "okay";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy0: ethernet-phy@0 {
	compatible = "ethernet-phy-ieee802.3-c22";
	smsc,disable-energy-detect;
	reg = <0>;
	};

	ethphy1: ethernet-phy@1 {
	compatible = "ethernet-phy-ieee802.3-c22";
	smsc,disable-energy-detect;
	reg = <1>;
	};
	};
	};

	&gpio5 {
	emmc-usd-mux {
	gpio-hog;
	gpios = <1 GPIO_ACTIVE_LOW>;
	output-high;
	};
	};

	&i2c1 {
	touchscreen@14 {
	compatible = "goodix,gt911";
	reg = <0x14>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_goodix_touch>;
	interrupt-parent = <&gpio5>;
	interrupts = <2 IRQ_TYPE_EDGE_RISING>;
	irq-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
	status = "okay";
	};
	};

	&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif_dat0_17
	&pinctrl_lcdif_clken
	&pinctrl_lcdif_hvsync>;
	lcd-supply = <&ldo4_ext>; /* BU90T82 LVDS bridge power */
	status = "okay";

	port {
	display_out: endpoint {
	remote-endpoint = <&panel_in>;
	};
	};
	};

	&ldo4_ext {
	regulator-max-microvolt = <1800000>;
	};

	&pwm1 {
	status = "okay";
	};

	&pwm2 {
	status = "okay";
	};

	&pwm3 {
	status = "okay";
	};

	&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
	status = "okay";
	};

	&pwm5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm5>;
	status = "okay";
	};

	&pwm6 {
	status = "okay";
	};

	&pwm7 {
	status = "okay";
	};

	&pwm8 {
	status = "okay";
	};

	&sai2 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_sai2>;
	pinctrl-1 = <&pinctrl_sai2_sleep>;
	assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
	<&clks IMX6UL_CLK_PLL4_AUDIO_DIV>,
	<&clks IMX6UL_CLK_SAI2>;
	assigned-clock-rates = <0>, <786432000>, <12288000>;
	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	status = "okay";
	};

	/* UART2 RTS/CTS muxed with CAN2 */
	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2_4wires>;
	uart-has-rtscts;
	status = "okay";
	};

	/* UART3 RTS/CTS muxed with CAN 1 */
	&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3_2wires>;
	status = "okay";
	};

	&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	status = "okay";
	};

	&usbotg1 {
	dr_mode = "otg";
	vbus-supply = <&reg_usb_otg1_vbus>;
	pinctrl-0 = <&pinctrl_usbotg1>;
	status = "okay";
	};

	&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
	};

	/* USDHC2 (microSD conflicts with eMMC) */
	&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	no-1-8-v;
	broken-cd; /* no carrier detect line (use polling) */
	status = "okay";
	};

	&iomuxc {
	pinctrl_adc1: adc1grp {
	fsl,pins = <
	/* EXP_GPIO_2 -> GPIO1_3/ADC1_IN3 */
	MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
	>;
	};

	pinctrl_ecspi1_master: ecspi1grp1 {
	fsl,pins = <
	MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x10b0
	MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x10b0
	MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x10b0
	MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0
	>;
	};

	pinctrl_enet1: enet1grp {
	fsl,pins = <
	MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
	MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
	MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
	MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
	MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
	MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
	MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
	MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051
	>;
	};

	pinctrl_enet2: enet2grp {
	fsl,pins = <
	MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
	MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
	MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
	MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
	MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
	MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
	MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
	MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x40017051
	>;
	};

	pinctrl_enet2_mdio: mdioenet2grp {
	fsl,pins = <
	MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
	MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
	>;
	};

	pinctrl_flexcan1: flexcan1grp{
	fsl,pins = <
	MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
	MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
	>;
	};
	pinctrl_flexcan2: flexcan2grp{
	fsl,pins = <
	MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
	MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
	>;
	};

	pinctrl_goodix_touch: goodixgrp{
	fsl,pins = <
	MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1020
	>;
	};

	pinctrl_lcdif_dat0_17: lcdifdatgrp0-17 {
	fsl,pins = <
	MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
	MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
	MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
	MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
	MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
	MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
	MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
	MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
	MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
	MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
	MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
	MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
	MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
	MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
	MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
	MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
	MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
	MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
	>;
	};

	pinctrl_lcdif_clken: lcdifctrlgrp1 {
	fsl,pins = <
	MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x17050
	MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
	>;
	};

	pinctrl_lcdif_hvsync: lcdifctrlgrp2 {
	fsl,pins = <
	MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
	MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
	>;
	};

	pinctrl_pwm4: pwm4grp {
	fsl,pins = <
	MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0
	>;
	};

	pinctrl_pwm5: pwm5grp {
	fsl,pins = <
	MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0
	>;
	};

	pinctrl_sai2: sai2grp {
	fsl,pins = <
	MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
	MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
	MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
	MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
	MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
	/* Interrupt */
	MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10b0
	>;
	};

	pinctrl_sai2_sleep: sai2grp-sleep {
	fsl,pins = <
	MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x3000
	MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x3000
	MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x3000
	MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x3000
	/* Interrupt */
	MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x3000
	>;
	};

	pinctrl_uart2_4wires: uart2grp-4wires {
	fsl,pins = <
	MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
	MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
	MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
	MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
	>;
	};

	pinctrl_uart3_2wires: uart3grp-2wires {
	fsl,pins = <
	MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
	MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
	>;
	};

	pinctrl_uart5: uart5grp {
	fsl,pins = <
	MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
	MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
	>;
	};

	pinctrl_usdhc2: usdhc2grp {
	fsl,pins = <
	MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
	MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10039
	MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
	MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
	MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
	MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
	/* Mux selector between eMMC/SD# */
	MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x79
	>;
	};

	pinctrl_usbotg1: usbotg1grp {
	fsl,pins = <
	MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
	MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x17059
	MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x17059
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6ul-pico-dwarf.dts b/sys/gnu/dts/arm/imx6ul-pico-dwarf.dts
	new file mode 100644
	index 000000000000..162dc259edc8
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx6ul-pico-dwarf.dts
	@@ -0,0 +1,52 @@
	+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	+//
	+// Copyright 2015 Technexion Ltd.
	+//
	+// Author: Wig Cheng <wig.cheng@technexion.com>
	+// Richard Hu <richard.hu@technexion.com>
	+// Tapani Utriainen <tapani@technexion.com>
	+/dts-v1/;
	+
	+#include "imx6ul-pico.dtsi"
	+/ {
	+ model = "TechNexion PICO-IMX6UL and DWARF baseboard";
	+ compatible = "technexion,imx6ul-pico-dwarf", "fsl,imx6ul";
	+
	+ sound {
	+ compatible = "fsl,imx-audio-sgtl5000";
	+ model = "imx6ul-sgtl5000";
	+ audio-cpu = <&sai1>;
	+ audio-codec = <&sgtl5000>;
	+ audio-routing =
	+ "LINE_IN", "Line In Jack",
	+ "MIC_IN", "Mic Jack",
	+ "Mic Jack", "Mic Bias",
	+ "Headphone Jack", "HP_OUT";
	+ };
	+
	+ sys_mclk: clock-sys-mclk {
	+ compatible = "fixed-clock";
	+ #clock-cells = <0>;
	+ clock-frequency = <24576000>;
	+ };
	+};
	+
	+&i2c2 {
	+ clock_frequency = <100000>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_i2c2>;
	+ status = "okay";
	+
	+ sgtl5000: audio-codec@a {
	+ reg = <0x0a>;
	+ compatible = "fsl,sgtl5000";
	+ clocks = <&sys_mclk>;
	+ VDDA-supply = <&reg_2p5v>;
	+ VDDIO-supply = <&reg_3p3v>;
	+ };
	+
	+ pressure-sensor@60 {
	+ compatible = "fsl,mpl3115";
	+ reg = <0x60>;
	+ };
	+};
	diff --git a/sys/gnu/dts/arm/imx6ul-pico.dtsi b/sys/gnu/dts/arm/imx6ul-pico.dtsi
	index de9f83189ba8..df1da98ab10f 100644
	--- a/sys/gnu/dts/arm/imx6ul-pico.dtsi
	+++ b/sys/gnu/dts/arm/imx6ul-pico.dtsi
	@@ -1,461 +1,452 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	//
	// Copyright 2015 Technexion Ltd.
	//
	// Author: Wig Cheng <wig.cheng@technexion.com>
	// Richard Hu <richard.hu@technexion.com>
	// Tapani Utriainen <tapani@technexion.com>
	/dts-v1/;

	#include "imx6ul.dtsi"

	/ {
	/* Will be filled by the bootloader */
	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0>;
	};

	chosen {
	stdout-path = &uart6;
	};

	- backlight {
	+ backlight: backlight {
	compatible = "pwm-backlight";
	pwms = <&pwm3 0 5000000>;
	brightness-levels = <0 4 8 16 32 64 128 255>;
	default-brightness-level = <6>;
	status = "okay";
	};

	reg_2p5v: regulator-2p5v {
	compatible = "regulator-fixed";
	regulator-name = "2P5V";
	regulator-min-microvolt = <2500000>;
	regulator-max-microvolt = <2500000>;
	};

	reg_3p3v: regulator-3p3v {
	compatible = "regulator-fixed";
	regulator-name = "3P3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	reg_sd1_vmmc: regulator-sd1-vmmc {
	compatible = "regulator-fixed";
	regulator-name = "VSD_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_usb_otg_vbus: regulator-usb-otg-vbus {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1>;
	regulator-name = "usb_otg_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio1 6 0>;
	};

	reg_brcm: regulator-brcm {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_brcm_reg>;
	regulator-name = "brcm_reg";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	startup-delay-us = <200000>;
	};
	+
	+ panel {
	+ compatible = "vxt,vl050-8048nt-c01";
	+ backlight = <&backlight>;
	+
	+ port {
	+ panel_in: endpoint {
	+ remote-endpoint = <&display_out>;
	+ };
	+ };
	+ };
	};

	&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "okay";
	};

	&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	status = "okay";
	};

	&clks {
	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <786432000>;
	};

	&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	status = "okay";
	phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <1>;

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy1: ethernet-phy@1 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <1>;
	max-speed = <100>;
	interrupt-parent = <&gpio5>;
	interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
	};
	};
	};

	&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic: pfuze3000@8 {
	compatible = "fsl,pfuze3000";
	reg = <0x08>;

	regulators {
	/* VDD_ARM_SOC_IN*/
	sw1b_reg: sw1b {
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1475000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	/* DRAM */
	sw3a_reg: sw3 {
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1650000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* DRAM */
	vref_reg: vrefddr {
	regulator-boot-on;
	regulator-always-on;
	};
	};
	};
	};

	&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
	- display = <&display0>;
	status = "okay";

	- display0: display0 {
	- bits-per-pixel = <32>;
	- bus-width = <24>;
	-
	- display-timings {
	- native-mode = <&timing0>;
	-
	- timing0: timing0 {
	- clock-frequency = <33200000>;
	- hactive = <800>;
	- vactive = <480>;
	- hfront-porch = <210>;
	- hback-porch = <46>;
	- hsync-len = <1>;
	- vback-porch = <22>;
	- vfront-porch = <23>;
	- vsync-len = <1>;
	- hsync-active = <0>;
	- vsync-active = <0>;
	- de-active = <1>;
	- pixelclk-active = <0>;
	- };
	+ port {
	+ display_out: endpoint {
	+ remote-endpoint = <&panel_in>;
	};
	};
	};

	&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "okay";
	};

	&pwm7 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm7>;
	status = "okay";
	};

	&pwm8 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm8>;
	status = "okay";
	};

	&sai1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	status = "okay";
	};

	&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	uart-has-rtscts;
	status = "okay";
	};

	&uart6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart6>;
	status = "okay";
	};

	&usbotg1 {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1_id>;
	dr_mode = "otg";
	disable-over-current;
	status = "okay";
	};

	&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
	};

	&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	bus-width = <8>;
	no-1-8-v;
	non-removable;
	keep-power-in-suspend;
	status = "okay";
	};

	&usdhc2 { /* Wifi SDIO */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	no-1-8-v;
	non-removable;
	keep-power-in-suspend;
	wakeup-source;
	vmmc-supply = <&reg_brcm>;
	status = "okay";
	};

	&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	};

	&iomuxc {
	pinctrl_brcm_reg: brcmreggrp {
	fsl,pins = <
	MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */
	MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */
	>;
	};

	pinctrl_enet2: enet2grp {
	fsl,pins = <
	MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0
	MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0
	MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
	MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
	MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
	MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
	MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
	MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
	MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
	MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
	MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800
	MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79
	>;
	};

	pinctrl_flexcan1: flexcan1grp {
	fsl,pins = <
	MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
	MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
	>;
	};

	pinctrl_flexcan2: flexcan2grp {
	fsl,pins = <
	MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
	MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0
	MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
	MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0
	MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0
	>;
	};

	pinctrl_lcdif_dat: lcdifdatgrp {
	fsl,pins = <
	MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
	MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
	MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
	MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
	MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
	MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
	MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
	MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
	MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
	MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
	MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
	MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
	MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
	MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
	MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
	MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
	MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
	MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
	MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
	MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
	MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
	MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
	MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
	MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
	>;
	};

	pinctrl_lcdif_ctrl: lcdifctrlgrp {
	fsl,pins = <
	MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
	MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
	MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
	MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
	/* LCD reset */
	MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
	>;
	};

	pinctrl_pwm3: pwm3grp {
	fsl,pins = <
	MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0
	>;
	};

	pinctrl_pwm7: pwm7grp {
	fsl,pins = <
	MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0
	>;
	};

	pinctrl_pwm8: pwm8grp {
	fsl,pins = <
	MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
	>;
	};

	pinctrl_sai1: sai1grp {
	fsl,pins = <
	MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0
	MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0
	MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0
	MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
	>;
	};

	pinctrl_uart3: uart3grp {
	fsl,pins = <
	MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0
	MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0
	MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0
	MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0
	>;
	};

	pinctrl_uart5: uart5grp {
	fsl,pins = <
	MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1
	MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1
	MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
	MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
	>;
	};

	pinctrl_uart6: uart6grp {
	fsl,pins = <
	MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
	MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
	>;
	};

	pinctrl_usb_otg1: usbotg1grp {
	fsl,pins = <
	MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0
	>;
	};

	pinctrl_usb_otg1_id: usbotg1idgrp {
	fsl,pins = <
	MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
	>;
	};

	pinctrl_usdhc1: usdhc1grp {
	fsl,pins = <
	MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
	MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
	MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
	MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
	MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
	MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
	MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029
	MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
	MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
	MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
	MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
	>;
	};

	pinctrl_usdhc2: usdhc2grp {
	fsl,pins = <
	MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
	MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
	MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
	MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
	MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
	MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
	>;
	};

	pinctrl_wdog: wdoggrp {
	fsl,pins = <
	MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6ul.dtsi b/sys/gnu/dts/arm/imx6ul.dtsi
	index d9fdca12819b..2ccf67c4ac1a 100644
	--- a/sys/gnu/dts/arm/imx6ul.dtsi
	+++ b/sys/gnu/dts/arm/imx6ul.dtsi
	@@ -1,1084 +1,1084 @@
	// SPDX-License-Identifier: GPL-2.0
	//
	// Copyright 2015 Freescale Semiconductor, Inc.

	#include <dt-bindings/clock/imx6ul-clock.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include "imx6ul-pinfunc.h"

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	* The decompressor and also some bootloaders rely on a
	* pre-existing /chosen node to be available to insert the
	* command line and merge other ATAGS info.
	*/
	chosen {};

	aliases {
	ethernet0 = &fec1;
	ethernet1 = &fec2;
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	gpio3 = &gpio4;
	gpio4 = &gpio5;
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	i2c2 = &i2c3;
	i2c3 = &i2c4;
	mmc0 = &usdhc1;
	mmc1 = &usdhc2;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	serial4 = &uart5;
	serial5 = &uart6;
	serial6 = &uart7;
	serial7 = &uart8;
	sai1 = &sai1;
	sai2 = &sai2;
	sai3 = &sai3;
	spi0 = &ecspi1;
	spi1 = &ecspi2;
	spi2 = &ecspi3;
	spi3 = &ecspi4;
	usbphy0 = &usbphy1;
	usbphy1 = &usbphy2;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <0>;
	clock-frequency = <696000000>;
	clock-latency = <61036>; /* two CLK32 periods */
	#cooling-cells = <2>;
	operating-points = <
	/* kHz uV */
	696000 1275000
	528000 1175000
	396000 1025000
	198000 950000
	>;
	fsl,soc-operating-points = <
	/* KHz uV */
	696000 1275000
	528000 1175000
	396000 1175000
	198000 1175000
	>;
	clocks = <&clks IMX6UL_CLK_ARM>,
	<&clks IMX6UL_CLK_PLL2_BUS>,
	<&clks IMX6UL_CLK_PLL2_PFD2>,
	<&clks IMX6UL_CA7_SECONDARY_SEL>,
	<&clks IMX6UL_CLK_STEP>,
	<&clks IMX6UL_CLK_PLL1_SW>,
	<&clks IMX6UL_CLK_PLL1_SYS>;
	clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
	"secondary_sel", "step", "pll1_sw",
	"pll1_sys";
	arm-supply = <&reg_arm>;
	soc-supply = <&reg_soc>;
	nvmem-cells = <&cpu_speed_grade>;
	nvmem-cell-names = "speed_grade";
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>;
	interrupt-parent = <&intc>;
	status = "disabled";
	};

	ckil: clock-cli {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "ckil";
	};

	osc: clock-osc {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "osc";
	};

	ipp_di0: clock-di0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	clock-output-names = "ipp_di0";
	};

	ipp_di1: clock-di1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	clock-output-names = "ipp_di1";
	};

	tempmon: tempmon {
	compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
	interrupt-parent = <&gpc>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	fsl,tempmon = <&anatop>;
	nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
	nvmem-cell-names = "calib", "temp_grade";
	clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
	};

	pmu {
	compatible = "arm,cortex-a7-pmu";
	interrupt-parent = <&gpc>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&gpc>;
	ranges;

	ocram: sram@900000 {
	compatible = "mmio-sram";
	reg = <0x00900000 0x20000>;
	};

	intc: interrupt-controller@a01000 {
	compatible = "arm,gic-400", "arm,cortex-a7-gic";
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_HIGH)>;
	#interrupt-cells = <3>;
	interrupt-controller;
	interrupt-parent = <&intc>;
	reg = <0x00a01000 0x1000>,
	<0x00a02000 0x2000>,
	<0x00a04000 0x2000>,
	<0x00a06000 0x2000>;
	};

	dma_apbh: dma-apbh@1804000 {
	compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
	reg = <0x01804000 0x2000>;
	interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
	<0 13 IRQ_TYPE_LEVEL_HIGH>,
	<0 13 IRQ_TYPE_LEVEL_HIGH>,
	<0 13 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
	#dma-cells = <1>;
	dma-channels = <4>;
	clocks = <&clks IMX6UL_CLK_APBHDMA>;
	};

	gpmi: gpmi-nand@1806000 {
	compatible = "fsl,imx6q-gpmi-nand";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
	reg-names = "gpmi-nand", "bch";
	interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "bch";
	clocks = <&clks IMX6UL_CLK_GPMI_IO>,
	<&clks IMX6UL_CLK_GPMI_APB>,
	<&clks IMX6UL_CLK_GPMI_BCH>,
	<&clks IMX6UL_CLK_GPMI_BCH_APB>,
	<&clks IMX6UL_CLK_PER_BCH>;
	clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
	"gpmi_bch_apb", "per1_bch";
	dmas = <&dma_apbh 0>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	- aips1: aips-bus@2000000 {
	+ aips1: bus@2000000 {
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02000000 0x100000>;
	ranges;

	spba-bus@2000000 {
	compatible = "fsl,spba-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02000000 0x40000>;
	ranges;

	ecspi1: spi@2008000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
	reg = <0x02008000 0x4000>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_ECSPI1>,
	<&clks IMX6UL_CLK_ECSPI1>;
	clock-names = "ipg", "per";
	dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	ecspi2: spi@200c000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
	reg = <0x0200c000 0x4000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_ECSPI2>,
	<&clks IMX6UL_CLK_ECSPI2>;
	clock-names = "ipg", "per";
	dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	ecspi3: spi@2010000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
	reg = <0x02010000 0x4000>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_ECSPI3>,
	<&clks IMX6UL_CLK_ECSPI3>;
	clock-names = "ipg", "per";
	dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	ecspi4: spi@2014000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
	reg = <0x02014000 0x4000>;
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_ECSPI4>,
	<&clks IMX6UL_CLK_ECSPI4>;
	clock-names = "ipg", "per";
	dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart7: serial@2018000 {
	compatible = "fsl,imx6ul-uart",
	"fsl,imx6q-uart";
	reg = <0x02018000 0x4000>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_UART7_IPG>,
	<&clks IMX6UL_CLK_UART7_SERIAL>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart1: serial@2020000 {
	compatible = "fsl,imx6ul-uart",
	"fsl,imx6q-uart";
	reg = <0x02020000 0x4000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_UART1_IPG>,
	<&clks IMX6UL_CLK_UART1_SERIAL>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart8: serial@2024000 {
	compatible = "fsl,imx6ul-uart",
	"fsl,imx6q-uart";
	reg = <0x02024000 0x4000>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_UART8_IPG>,
	<&clks IMX6UL_CLK_UART8_SERIAL>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	sai1: sai@2028000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
	reg = <0x02028000 0x4000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
	<&clks IMX6UL_CLK_SAI1>,
	<&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dmas = <&sdma 35 24 0>,
	<&sdma 36 24 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	sai2: sai@202c000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
	reg = <0x0202c000 0x4000>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
	<&clks IMX6UL_CLK_SAI2>,
	<&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dmas = <&sdma 37 24 0>,
	<&sdma 38 24 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	sai3: sai@2030000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
	reg = <0x02030000 0x4000>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
	<&clks IMX6UL_CLK_SAI3>,
	<&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dmas = <&sdma 39 24 0>,
	<&sdma 40 24 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};
	};

	tsc: tsc@2040000 {
	compatible = "fsl,imx6ul-tsc";
	reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_IPG>,
	<&clks IMX6UL_CLK_ADC2>;
	clock-names = "tsc", "adc";
	status = "disabled";
	};

	pwm1: pwm@2080000 {
	compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
	reg = <0x02080000 0x4000>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_PWM1>,
	<&clks IMX6UL_CLK_PWM1>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm2: pwm@2084000 {
	compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
	reg = <0x02084000 0x4000>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_PWM2>,
	<&clks IMX6UL_CLK_PWM2>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm3: pwm@2088000 {
	compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
	reg = <0x02088000 0x4000>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_PWM3>,
	<&clks IMX6UL_CLK_PWM3>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm4: pwm@208c000 {
	compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
	reg = <0x0208c000 0x4000>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_PWM4>,
	<&clks IMX6UL_CLK_PWM4>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	can1: flexcan@2090000 {
	compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
	reg = <0x02090000 0x4000>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
	<&clks IMX6UL_CLK_CAN1_SERIAL>;
	clock-names = "ipg", "per";
	fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
	status = "disabled";
	};

	can2: flexcan@2094000 {
	compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
	reg = <0x02094000 0x4000>;
	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
	<&clks IMX6UL_CLK_CAN2_SERIAL>;
	clock-names = "ipg", "per";
	fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
	status = "disabled";
	};

	- gpt1: gpt@2098000 {
	+ gpt1: timer@2098000 {
	compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
	reg = <0x02098000 0x4000>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
	<&clks IMX6UL_CLK_GPT1_SERIAL>;
	clock-names = "ipg", "per";
	};

	gpio1: gpio@209c000 {
	compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
	reg = <0x0209c000 0x4000>;
	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_GPIO1>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
	<&iomuxc 16 33 16>;
	};

	gpio2: gpio@20a0000 {
	compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
	reg = <0x020a0000 0x4000>;
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_GPIO2>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
	};

	gpio3: gpio@20a4000 {
	compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
	reg = <0x020a4000 0x4000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_GPIO3>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 65 29>;
	};

	gpio4: gpio@20a8000 {
	compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
	reg = <0x020a8000 0x4000>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_GPIO4>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
	};

	gpio5: gpio@20ac000 {
	compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
	reg = <0x020ac000 0x4000>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_GPIO5>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
	};

	fec2: ethernet@20b4000 {
	compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
	reg = <0x020b4000 0x4000>;
	interrupt-names = "int0", "pps";
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_ENET>,
	<&clks IMX6UL_CLK_ENET_AHB>,
	<&clks IMX6UL_CLK_ENET_PTP>,
	<&clks IMX6UL_CLK_ENET2_REF_125M>,
	<&clks IMX6UL_CLK_ENET2_REF_125M>;
	clock-names = "ipg", "ahb", "ptp",
	"enet_clk_ref", "enet_out";
	fsl,num-tx-queues = <1>;
	fsl,num-rx-queues = <1>;
	status = "disabled";
	};

	- kpp: kpp@20b8000 {
	+ kpp: keypad@20b8000 {
	compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
	reg = <0x020b8000 0x4000>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_KPP>;
	status = "disabled";
	};

	- wdog1: wdog@20bc000 {
	+ wdog1: watchdog@20bc000 {
	compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
	reg = <0x020bc000 0x4000>;
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_WDOG1>;
	};

	- wdog2: wdog@20c0000 {
	+ wdog2: watchdog@20c0000 {
	compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
	reg = <0x020c0000 0x4000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_WDOG2>;
	status = "disabled";
	};

	- clks: ccm@20c4000 {
	+ clks: clock-controller@20c4000 {
	compatible = "fsl,imx6ul-ccm";
	reg = <0x020c4000 0x4000>;
	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	#clock-cells = <1>;
	clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
	clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
	};

	anatop: anatop@20c8000 {
	compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
	"syscon", "simple-mfd";
	reg = <0x020c8000 0x1000>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;

	reg_3p0: regulator-3p0 {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vdd3p0";
	regulator-min-microvolt = <2625000>;
	regulator-max-microvolt = <3400000>;
	anatop-reg-offset = <0x120>;
	anatop-vol-bit-shift = <8>;
	anatop-vol-bit-width = <5>;
	anatop-min-bit-val = <0>;
	anatop-min-voltage = <2625000>;
	anatop-max-voltage = <3400000>;
	anatop-enable-bit = <0>;
	};

	reg_arm: regulator-vddcore {
	compatible = "fsl,anatop-regulator";
	regulator-name = "cpu";
	regulator-min-microvolt = <725000>;
	regulator-max-microvolt = <1450000>;
	regulator-always-on;
	anatop-reg-offset = <0x140>;
	anatop-vol-bit-shift = <0>;
	anatop-vol-bit-width = <5>;
	anatop-delay-reg-offset = <0x170>;
	anatop-delay-bit-shift = <24>;
	anatop-delay-bit-width = <2>;
	anatop-min-bit-val = <1>;
	anatop-min-voltage = <725000>;
	anatop-max-voltage = <1450000>;
	};

	reg_soc: regulator-vddsoc {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vddsoc";
	regulator-min-microvolt = <725000>;
	regulator-max-microvolt = <1450000>;
	regulator-always-on;
	anatop-reg-offset = <0x140>;
	anatop-vol-bit-shift = <18>;
	anatop-vol-bit-width = <5>;
	anatop-delay-reg-offset = <0x170>;
	anatop-delay-bit-shift = <28>;
	anatop-delay-bit-width = <2>;
	anatop-min-bit-val = <1>;
	anatop-min-voltage = <725000>;
	anatop-max-voltage = <1450000>;
	};
	};

	usbphy1: usbphy@20c9000 {
	compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
	reg = <0x020c9000 0x1000>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_USBPHY1>;
	phy-3p0-supply = <&reg_3p0>;
	fsl,anatop = <&anatop>;
	};

	usbphy2: usbphy@20ca000 {
	compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
	reg = <0x020ca000 0x1000>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_USBPHY2>;
	phy-3p0-supply = <&reg_3p0>;
	fsl,anatop = <&anatop>;
	};

	snvs: snvs@20cc000 {
	compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
	reg = <0x020cc000 0x4000>;

	snvs_rtc: snvs-rtc-lp {
	compatible = "fsl,sec-v4.0-mon-rtc-lp";
	regmap = <&snvs>;
	offset = <0x34>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	};

	snvs_poweroff: snvs-poweroff {
	compatible = "syscon-poweroff";
	regmap = <&snvs>;
	offset = <0x38>;
	value = <0x60>;
	mask = <0x60>;
	status = "disabled";
	};

	snvs_pwrkey: snvs-powerkey {
	compatible = "fsl,sec-v4.0-pwrkey";
	regmap = <&snvs>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	linux,keycode = <KEY_POWER>;
	wakeup-source;
	status = "disabled";
	};

	snvs_lpgpr: snvs-lpgpr {
	compatible = "fsl,imx6ul-snvs-lpgpr";
	};
	};

	epit1: epit@20d0000 {
	reg = <0x020d0000 0x4000>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	};

	epit2: epit@20d4000 {
	reg = <0x020d4000 0x4000>;
	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	};

	src: src@20d8000 {
	compatible = "fsl,imx6ul-src", "fsl,imx51-src";
	reg = <0x020d8000 0x4000>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	#reset-cells = <1>;
	};

	gpc: gpc@20dc000 {
	compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
	reg = <0x020dc000 0x4000>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-parent = <&intc>;
	};

	- iomuxc: iomuxc@20e0000 {
	+ iomuxc: pinctrl@20e0000 {
	compatible = "fsl,imx6ul-iomuxc";
	reg = <0x020e0000 0x4000>;
	};

	gpr: iomuxc-gpr@20e4000 {
	compatible = "fsl,imx6ul-iomuxc-gpr",
	"fsl,imx6q-iomuxc-gpr", "syscon";
	reg = <0x020e4000 0x4000>;
	};

	- gpt2: gpt@20e8000 {
	+ gpt2: timer@20e8000 {
	compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
	reg = <0x020e8000 0x4000>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
	<&clks IMX6UL_CLK_GPT2_SERIAL>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	sdma: sdma@20ec000 {
	compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
	"fsl,imx35-sdma";
	reg = <0x020ec000 0x4000>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_IPG>,
	<&clks IMX6UL_CLK_SDMA>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
	};

	pwm5: pwm@20f0000 {
	compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
	reg = <0x020f0000 0x4000>;
	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_PWM5>,
	<&clks IMX6UL_CLK_PWM5>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm6: pwm@20f4000 {
	compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
	reg = <0x020f4000 0x4000>;
	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_PWM6>,
	<&clks IMX6UL_CLK_PWM6>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm7: pwm@20f8000 {
	compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
	reg = <0x020f8000 0x4000>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_PWM7>,
	<&clks IMX6UL_CLK_PWM7>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm8: pwm@20fc000 {
	compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
	reg = <0x020fc000 0x4000>;
	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_PWM8>,
	<&clks IMX6UL_CLK_PWM8>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};
	};

	- aips2: aips-bus@2100000 {
	+ aips2: bus@2100000 {
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02100000 0x100000>;
	ranges;

	- crypto: caam@2140000 {
	+ crypto: crypto@2140000 {
	compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x2140000 0x3c000>;
	ranges = <0 0x2140000 0x3c000>;
	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
	<&clks IMX6UL_CLK_CAAM_MEM>;
	clock-names = "ipg", "aclk", "mem";

	- sec_jr0: jr0@1000 {
	+ sec_jr0: jr@1000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x1000 0x1000>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	};

	- sec_jr1: jr1@2000 {
	+ sec_jr1: jr@2000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x2000 0x1000>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	};

	- sec_jr2: jr2@3000 {
	+ sec_jr2: jr@3000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x3000 0x1000>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	usbotg1: usb@2184000 {
	compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
	reg = <0x02184000 0x200>;
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_USBOH3>;
	fsl,usbphy = <&usbphy1>;
	fsl,usbmisc = <&usbmisc 0>;
	fsl,anatop = <&anatop>;
	ahb-burst-config = <0x0>;
	tx-burst-size-dword = <0x10>;
	rx-burst-size-dword = <0x10>;
	status = "disabled";
	};

	usbotg2: usb@2184200 {
	compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
	reg = <0x02184200 0x200>;
	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_USBOH3>;
	fsl,usbphy = <&usbphy2>;
	fsl,usbmisc = <&usbmisc 1>;
	ahb-burst-config = <0x0>;
	tx-burst-size-dword = <0x10>;
	rx-burst-size-dword = <0x10>;
	status = "disabled";
	};

	usbmisc: usbmisc@2184800 {
	#index-cells = <1>;
	compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
	reg = <0x02184800 0x200>;
	};

	fec1: ethernet@2188000 {
	compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
	reg = <0x02188000 0x4000>;
	interrupt-names = "int0", "pps";
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_ENET>,
	<&clks IMX6UL_CLK_ENET_AHB>,
	<&clks IMX6UL_CLK_ENET_PTP>,
	<&clks IMX6UL_CLK_ENET_REF>,
	<&clks IMX6UL_CLK_ENET_REF>;
	clock-names = "ipg", "ahb", "ptp",
	"enet_clk_ref", "enet_out";
	fsl,num-tx-queues = <1>;
	fsl,num-rx-queues = <1>;
	status = "disabled";
	};

	usdhc1: usdhc@2190000 {
	compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
	reg = <0x02190000 0x4000>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_USDHC1>,
	<&clks IMX6UL_CLK_USDHC1>,
	<&clks IMX6UL_CLK_USDHC1>;
	clock-names = "ipg", "ahb", "per";
	fsl,tuning-step = <2>;
	fsl,tuning-start-tap = <20>;
	bus-width = <4>;
	status = "disabled";
	};

	usdhc2: usdhc@2194000 {
	compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
	reg = <0x02194000 0x4000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_USDHC2>,
	<&clks IMX6UL_CLK_USDHC2>,
	<&clks IMX6UL_CLK_USDHC2>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	fsl,tuning-step = <2>;
	fsl,tuning-start-tap = <20>;
	status = "disabled";
	};

	adc1: adc@2198000 {
	compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
	reg = <0x02198000 0x4000>;
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_ADC1>;
	num-channels = <2>;
	clock-names = "adc";
	fsl,adck-max-frequency = <30000000>, <40000000>,
	<20000000>;
	status = "disabled";
	};

	i2c1: i2c@21a0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
	reg = <0x021a0000 0x4000>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_I2C1>;
	status = "disabled";
	};

	i2c2: i2c@21a4000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
	reg = <0x021a4000 0x4000>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_I2C2>;
	status = "disabled";
	};

	i2c3: i2c@21a8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
	reg = <0x021a8000 0x4000>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_I2C3>;
	status = "disabled";
	};

	memory-controller@21b0000 {
	compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
	reg = <0x021b0000 0x4000>;
	clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
	};

	weim: weim@21b8000 {
	#address-cells = <2>;
	#size-cells = <1>;
	compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
	reg = <0x021b8000 0x4000>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_EIM>;
	fsl,weim-cs-gpr = <&gpr>;
	status = "disabled";
	};

	ocotp: ocotp-ctrl@21bc000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "fsl,imx6ul-ocotp", "syscon";
	reg = <0x021bc000 0x4000>;
	clocks = <&clks IMX6UL_CLK_OCOTP>;

	tempmon_calib: calib@38 {
	reg = <0x38 4>;
	};

	tempmon_temp_grade: temp-grade@20 {
	reg = <0x20 4>;
	};

	cpu_speed_grade: speed-grade@10 {
	reg = <0x10 4>;
	};
	};

	csi: csi@21c4000 {
	compatible = "fsl,imx6ul-csi", "fsl,imx7-csi";
	reg = <0x021c4000 0x4000>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_CSI>;
	clock-names = "mclk";
	status = "disabled";
	};

	lcdif: lcdif@21c8000 {
	compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
	reg = <0x021c8000 0x4000>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
	<&clks IMX6UL_CLK_LCDIF_APB>,
	<&clks IMX6UL_CLK_DUMMY>;
	clock-names = "pix", "axi", "disp_axi";
	status = "disabled";
	};

	pxp: pxp@21cc000 {
	compatible = "fsl,imx6ul-pxp";
	reg = <0x021cc000 0x4000>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_PXP>;
	clock-names = "axi";
	};

	qspi: spi@21e0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
	reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
	reg-names = "QuadSPI", "QuadSPI-memory";
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_QSPI>,
	<&clks IMX6UL_CLK_QSPI>;
	clock-names = "qspi_en", "qspi";
	status = "disabled";
	};

	- wdog3: wdog@21e4000 {
	+ wdog3: watchdog@21e4000 {
	compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
	reg = <0x021e4000 0x4000>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_WDOG3>;
	status = "disabled";
	};

	uart2: serial@21e8000 {
	compatible = "fsl,imx6ul-uart",
	"fsl,imx6q-uart";
	reg = <0x021e8000 0x4000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_UART2_IPG>,
	<&clks IMX6UL_CLK_UART2_SERIAL>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart3: serial@21ec000 {
	compatible = "fsl,imx6ul-uart",
	"fsl,imx6q-uart";
	reg = <0x021ec000 0x4000>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_UART3_IPG>,
	<&clks IMX6UL_CLK_UART3_SERIAL>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart4: serial@21f0000 {
	compatible = "fsl,imx6ul-uart",
	"fsl,imx6q-uart";
	reg = <0x021f0000 0x4000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_UART4_IPG>,
	<&clks IMX6UL_CLK_UART4_SERIAL>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart5: serial@21f4000 {
	compatible = "fsl,imx6ul-uart",
	"fsl,imx6q-uart";
	reg = <0x021f4000 0x4000>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_UART5_IPG>,
	<&clks IMX6UL_CLK_UART5_SERIAL>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	i2c4: i2c@21f8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
	reg = <0x021f8000 0x4000>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_I2C4>;
	status = "disabled";
	};

	uart6: serial@21fc000 {
	compatible = "fsl,imx6ul-uart",
	"fsl,imx6q-uart";
	reg = <0x021fc000 0x4000>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_UART6_IPG>,
	<&clks IMX6UL_CLK_UART6_SERIAL>;
	clock-names = "ipg", "per";
	status = "disabled";
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx6ull.dtsi b/sys/gnu/dts/arm/imx6ull.dtsi
	index b7e67d121322..fcde7f77ae42 100644
	--- a/sys/gnu/dts/arm/imx6ull.dtsi
	+++ b/sys/gnu/dts/arm/imx6ull.dtsi
	@@ -1,88 +1,88 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	//
	// Copyright 2016 Freescale Semiconductor, Inc.

	#include "imx6ul.dtsi"
	#include "imx6ull-pinfunc.h"
	#include "imx6ull-pinfunc-snvs.h"

	/* Delete UART8 in AIPS-1 (i.MX6UL specific) */
	/delete-node/ &uart8;
	/* Delete CAAM node in AIPS-2 (i.MX6UL specific) */
	/delete-node/ &crypto;

	&cpu0 {
	clock-frequency = <900000000>;
	operating-points = <
	/* kHz uV */
	900000 1275000
	792000 1225000
	528000 1175000
	396000 1025000
	198000 950000
	>;
	fsl,soc-operating-points = <
	/* KHz uV */
	900000 1250000
	792000 1175000
	528000 1175000
	396000 1175000
	198000 1175000
	>;
	};

	&ocotp {
	compatible = "fsl,imx6ull-ocotp", "syscon";
	};

	&pxp {
	compatible = "fsl,imx6ull-pxp";
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	};

	&usdhc1 {
	compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
	};

	&usdhc2 {
	compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
	};

	/ {
	soc {
	- aips3: aips-bus@2200000 {
	+ aips3: bus@2200000 {
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x02200000 0x100000>;
	ranges;

	dcp: crypto@2280000 {
	compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp";
	reg = <0x02280000 0x4000>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6ULL_CLK_DCP_CLK>;
	clock-names = "dcp";
	};

	iomuxc_snvs: iomuxc-snvs@2290000 {
	compatible = "fsl,imx6ull-iomuxc-snvs";
	reg = <0x02290000 0x4000>;
	};

	uart8: serial@2288000 {
	compatible = "fsl,imx6ul-uart",
	"fsl,imx6q-uart";
	reg = <0x02288000 0x4000>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_UART8_IPG>,
	<&clks IMX6UL_CLK_UART8_SERIAL>;
	clock-names = "ipg", "per";
	status = "disabled";
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx7-colibri-aster.dtsi b/sys/gnu/dts/arm/imx7-colibri-aster.dtsi
	new file mode 100644
	index 000000000000..9fa701bec2ec
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx7-colibri-aster.dtsi
	@@ -0,0 +1,169 @@
	+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	+/*
	+ * Copyright 2017-2020 Toradex AG
	+ *
	+ */
	+
	+
	+#include <dt-bindings/input/input.h>
	+#include <dt-bindings/pwm/pwm.h>
	+
	+/ {
	+ chosen {
	+ stdout-path = "serial0:115200n8";
	+ };
	+
	+ gpio-keys {
	+ compatible = "gpio-keys";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_gpiokeys>;
	+
	+ power {
	+ label = "Wake-Up";
	+ gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
	+ linux,code = <KEY_WAKEUP>;
	+ debounce-interval = <10>;
	+ wakeup-source;
	+ };
	+ };
	+
	+ panel: panel {
	+ compatible = "edt,et057090dhu";
	+ backlight = <&bl>;
	+ power-supply = <&reg_3v3>;
	+
	+ port {
	+ panel_in: endpoint {
	+ remote-endpoint = <&lcdif_out>;
	+ };
	+ };
	+ };
	+
	+ reg_3v3: regulator-3v3 {
	+ compatible = "regulator-fixed";
	+ regulator-name = "3.3V";
	+ regulator-min-microvolt = <3300000>;
	+ regulator-max-microvolt = <3300000>;
	+ };
	+
	+ reg_5v0: regulator-5v0 {
	+ compatible = "regulator-fixed";
	+ regulator-name = "5V";
	+ regulator-min-microvolt = <5000000>;
	+ regulator-max-microvolt = <5000000>;
	+ };
	+
	+ reg_usbh_vbus: regulator-usbh-vbus {
	+ compatible = "regulator-fixed";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_usbh_reg>;
	+ regulator-name = "VCC_USB[1-4]";
	+ regulator-min-microvolt = <5000000>;
	+ regulator-max-microvolt = <5000000>;
	+ gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
	+ vin-supply = <&reg_5v0>;
	+ };
	+};
	+
	+&adc1 {
	+ status = "okay";
	+};
	+
	+/*
	+ * ADC2 is not available on the Aster board and
	+ * conflicts with AD7879 resistive touchscreen.
	+ */
	+&adc2 {
	+ status = "disabled";
	+};
	+
	+&bl {
	+ brightness-levels = <0 4 8 16 32 64 128 255>;
	+ default-brightness-level = <6>;
	+ power-supply = <&reg_3v3>;
	+ status = "okay";
	+};
	+
	+&fec1 {
	+ status = "okay";
	+};
	+
	+&i2c4 {
	+ status = "okay";
	+
	+ /* Microchip/Atmel maxtouch controller */
	+ touchscreen@4a {
	+ compatible = "atmel,maxtouch";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_gpiotouch>;
	+ reg = <0x4a>;
	+ interrupt-parent = <&gpio2>;
	+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */
	+ reset-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */
	+ };
	+
	+ /* M41T0M6 real time clock on carrier board */
	+ rtc: m41t0m6@68 {
	+ compatible = "st,m41t0";
	+ reg = <0x68>;
	+ };
	+};
	+
	+&iomuxc {
	+ pinctrl_gpiotouch: touchgpios {
	+ fsl,pins = <
	+ MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74
	+ MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14
	+ >;
	+ };
	+};
	+
	+&lcdif {
	+ status = "okay";
	+
	+ port {
	+ lcdif_out: endpoint {
	+ remote-endpoint = <&panel_in>;
	+ };
	+ };
	+};
	+
	+&pwm1 {
	+ status = "okay";
	+};
	+
	+&pwm2 {
	+ status = "okay";
	+};
	+
	+&pwm3 {
	+ status = "okay";
	+};
	+
	+&pwm4 {
	+ status = "okay";
	+};
	+
	+&uart1 {
	+ status = "okay";
	+};
	+
	+&uart2 {
	+ status = "okay";
	+};
	+
	+&uart3 {
	+ status = "okay";
	+};
	+
	+&usbotg1 {
	+ status = "okay";
	+};
	+
	+&usdhc1 {
	+ keep-power-in-suspend;
	+ no-1-8-v;
	+ wakeup-source;
	+ vmmc-supply = <&reg_3v3>;
	+ status = "okay";
	+};
	diff --git a/sys/gnu/dts/arm/imx7-colibri-eval-v3.dtsi b/sys/gnu/dts/arm/imx7-colibri-eval-v3.dtsi
	index 6aa123cbdadb..97601375f264 100644
	--- a/sys/gnu/dts/arm/imx7-colibri-eval-v3.dtsi
	+++ b/sys/gnu/dts/arm/imx7-colibri-eval-v3.dtsi
	@@ -1,226 +1,194 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2016 Toradex AG
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License as
	- * published by the Free Software Foundation; either version 2 of the
	- * License, or (at your option) any later version.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	+ * Copyright 2016-2020 Toradex
	*/

	/ {
	+ aliases {
	+ rtc0 = &rtc;
	+ rtc1 = &snvs_rtc;
	+ };
	+
	chosen {
	stdout-path = "serial0:115200n8";
	};

	/* fixed crystal dedicated to mpc258x */
	clk16m: clk16m {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <16000000>;
	};

	gpio-keys {
	compatible = "gpio-keys";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpiokeys>;

	power {
	label = "Wake-Up";
	gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
	linux,code = <KEY_WAKEUP>;
	debounce-interval = <10>;
	wakeup-source;
	};
	};

	panel: panel {
	compatible = "edt,et057090dhu";
	backlight = <&bl>;
	power-supply = <&reg_3v3>;

	port {
	panel_in: endpoint {
	remote-endpoint = <&lcdif_out>;
	};
	};
	};

	reg_3v3: regulator-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	reg_5v0: regulator-5v0 {
	compatible = "regulator-fixed";
	regulator-name = "5V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	};

	reg_usbh_vbus: regulator-usbh-vbus {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbh_reg>;
	regulator-name = "VCC_USB[1-4]";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
	vin-supply = <&reg_5v0>;
	};
	};

	&bl {
	brightness-levels = <0 4 8 16 32 64 128 255>;
	default-brightness-level = <6>;
	power-supply = <&reg_3v3>;

	status = "okay";
	};

	&adc1 {
	status = "okay";
	};

	&adc2 {
	status = "okay";
	};

	&ecspi3 {
	status = "okay";

	mcp2515: can@0 {
	compatible = "microchip,mcp2515";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can_int>;
	reg = <0>;
	clocks = <&clk16m>;
	interrupt-parent = <&gpio5>;
	interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
	spi-max-frequency = <10000000>;
	vdd-supply = <&reg_3v3>;
	xceiver-supply = <&reg_5v0>;
	status = "okay";
	};
	};

	&fec1 {
	status = "okay";
	};

	&i2c4 {
	status = "okay";

	/*
	* Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
	* aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
	*/
	touchscreen@4a {
	compatible = "atmel,maxtouch";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpiotouch>;
	reg = <0x4a>;
	interrupt-parent = <&gpio1>;
	interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
	reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */
	status = "disabled";
	};

	/* M41T0M6 real time clock on carrier board */
	rtc: m41t0m6@68 {
	compatible = "st,m41t0";
	reg = <0x68>;
	};
	};

	&lcdif {
	status = "okay";

	port {
	lcdif_out: endpoint {
	remote-endpoint = <&panel_in>;
	};
	};
	};

	&pwm1 {
	status = "okay";
	};

	&pwm2 {
	status = "okay";
	};

	&pwm3 {
	status = "okay";
	};

	&pwm4 {
	status = "okay";
	};

	&uart1 {
	status = "okay";
	};

	&uart2 {
	status = "okay";
	};

	&uart3 {
	status = "okay";
	};

	&usbotg1 {
	status = "okay";
	};

	&usdhc1 {
	keep-power-in-suspend;
	wakeup-source;
	vmmc-supply = <&reg_3v3>;
	status = "okay";
	};

	&iomuxc {
	pinctrl_gpiotouch: touchgpios {
	fsl,pins = <
	MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74
	MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx7-colibri.dtsi b/sys/gnu/dts/arm/imx7-colibri.dtsi
	index 04717cf69db0..e18e89dec879 100644
	--- a/sys/gnu/dts/arm/imx7-colibri.dtsi
	+++ b/sys/gnu/dts/arm/imx7-colibri.dtsi
	@@ -1,797 +1,941 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2016 Toradex AG
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License as
	- * published by the Free Software Foundation; either version 2 of the
	- * License, or (at your option) any later version.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	+ * Copyright 2016-2020 Toradex
	*/

	/ {
	bl: backlight {
	compatible = "pwm-backlight";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_bl_on>;
	pwms = <&pwm1 0 5000000 0>;
	enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
	};

	reg_module_3v3: regulator-module-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_module_3v3_avdd: regulator-module-3v3-avdd {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3_AVDD_AUDIO";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	sound {
	compatible = "simple-audio-card";
	simple-audio-card,name = "imx7-sgtl5000";
	simple-audio-card,format = "i2s";
	simple-audio-card,bitclock-master = <&dailink_master>;
	simple-audio-card,frame-master = <&dailink_master>;
	simple-audio-card,cpu {
	sound-dai = <&sai1>;
	};

	dailink_master: simple-audio-card,codec {
	sound-dai = <&codec>;
	clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
	};
	};
	};

	&adc1 {
	vref-supply = <&reg_DCDC3>;
	};

	&adc2 {
	vref-supply = <&reg_DCDC3>;
	};

	&cpu0 {
	cpu-supply = <&reg_DCDC2>;
	};

	&ecspi3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
	cs-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
	};

	&fec1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_enet1>;
	pinctrl-1 = <&pinctrl_enet1_sleep>;
	clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
	<&clks IMX7D_ENET_AXI_ROOT_CLK>,
	<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
	<&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
	clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
	<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
	assigned-clock-rates = <0>, <100000000>;
	phy-mode = "rmii";
	phy-supply = <&reg_LDO1>;
	fsl,magic-packet;
	};

	&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "disabled";
	};

	&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	status = "disabled";
	};

	+&gpio1 {
	+ gpio-line-names = "SODIMM_43",
	+ "SODIMM_45",
	+ "SODIMM_135",
	+ "SODIMM_22",
	+ "",
	+ "",
	+ "SODIMM_37",
	+ "SODIMM_29",
	+ "SODIMM_59",
	+ "SODIMM_28",
	+ "SODIMM_30",
	+ "SODIMM_67",
	+ "",
	+ "",
	+ "SODIMM_188",
	+ "SODIMM_178";
	+};
	+
	+&gpio2 {
	+ gpio-line-names = "SODIMM_111",
	+ "SODIMM_113",
	+ "SODIMM_115",
	+ "SODIMM_117",
	+ "SODIMM_119",
	+ "SODIMM_121",
	+ "SODIMM_123",
	+ "SODIMM_125",
	+ "SODIMM_91",
	+ "SODIMM_89",
	+ "SODIMM_105",
	+ "SODIMM_152",
	+ "SODIMM_150",
	+ "SODIMM_95",
	+ "SODIMM_126",
	+ "SODIMM_107",
	+ "SODIMM_114",
	+ "SODIMM_116",
	+ "SODIMM_118",
	+ "SODIMM_120",
	+ "SODIMM_122",
	+ "SODIMM_124",
	+ "SODIMM_127",
	+ "SODIMM_130",
	+ "SODIMM_132",
	+ "SODIMM_134",
	+ "SODIMM_133",
	+ "SODIMM_104",
	+ "SODIMM_106",
	+ "SODIMM_110",
	+ "SODIMM_112",
	+ "SODIMM_128";
	+};
	+
	+&gpio3 {
	+ gpio-line-names = "SODIMM_56",
	+ "SODIMM_44",
	+ "SODIMM_68",
	+ "SODIMM_82",
	+ "SODIMM_93",
	+ "SODIMM_76",
	+ "SODIMM_70",
	+ "SODIMM_60",
	+ "SODIMM_58",
	+ "SODIMM_78",
	+ "SODIMM_72",
	+ "SODIMM_80",
	+ "SODIMM_46",
	+ "SODIMM_62",
	+ "SODIMM_48",
	+ "SODIMM_74",
	+ "SODIMM_50",
	+ "SODIMM_52",
	+ "SODIMM_54",
	+ "SODIMM_66",
	+ "SODIMM_64",
	+ "SODIMM_57",
	+ "SODIMM_61",
	+ "SODIMM_136",
	+ "SODIMM_138",
	+ "SODIMM_140",
	+ "SODIMM_142",
	+ "SODIMM_144",
	+ "SODIMM_146";
	+};
	+
	+&gpio4 {
	+ gpio-line-names = "SODIMM_35",
	+ "SODIMM_33",
	+ "SODIMM_38",
	+ "SODIMM_36",
	+ "SODIMM_21",
	+ "SODIMM_19",
	+ "SODIMM_131",
	+ "SODIMM_129",
	+ "SODIMM_90",
	+ "SODIMM_92",
	+ "SODIMM_88",
	+ "SODIMM_86",
	+ "SODIMM_81",
	+ "SODIMM_94",
	+ "SODIMM_96",
	+ "SODIMM_75",
	+ "SODIMM_101",
	+ "SODIMM_103",
	+ "SODIMM_79",
	+ "SODIMM_97",
	+ "SODIMM_67",
	+ "SODIMM_59",
	+ "SODIMM_85",
	+ "SODIMM_65";
	+};
	+
	+&gpio5 {
	+ gpio-line-names = "SODIMM_69",
	+ "SODIMM_71",
	+ "SODIMM_73",
	+ "SODIMM_47",
	+ "SODIMM_190",
	+ "SODIMM_192",
	+ "SODIMM_49",
	+ "SODIMM_51",
	+ "SODIMM_53",
	+ "",
	+ "",
	+ "SODIMM_98",
	+ "SODIMM_184",
	+ "SODIMM_186",
	+ "SODIMM_23",
	+ "SODIMM_31",
	+ "SODIMM_100",
	+ "SODIMM_102";
	+};
	+
	+&gpio6 {
	+ gpio-line-names = "",
	+ "",
	+ "",
	+ "",
	+ "",
	+ "",
	+ "",
	+ "",
	+ "",
	+ "",
	+ "",
	+ "",
	+ "SODIMM_169",
	+ "",
	+ "",
	+ "",
	+ "SODIMM_77",
	+ "SODIMM_24",
	+ "",
	+ "SODIMM_25",
	+ "SODIMM_27",
	+ "SODIMM_32",
	+ "SODIMM_34";
	+};
	+
	+&gpio7 {
	+ gpio-line-names = "",
	+ "",
	+ "SODIMM_63",
	+ "SODIMM_55",
	+ "",
	+ "",
	+ "",
	+ "",
	+ "SODIMM_196",
	+ "SODIMM_194",
	+ "",
	+ "SODIMM_99",
	+ "",
	+ "",
	+ "SODIMM_137";
	+};
	+
	&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	fsl,use-minimum-ecc;
	nand-on-flash-bbt;
	nand-ecc-mode = "hw";
	};

	&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
	pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>;
	scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;

	status = "okay";

	codec: sgtl5000@a {
	compatible = "fsl,sgtl5000";
	#sound-dai-cells = <0>;
	reg = <0x0a>;
	clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1_mclk>;
	VDDA-supply = <&reg_module_3v3_avdd>;
	VDDIO-supply = <&reg_module_3v3>;
	VDDD-supply = <&reg_DCDC3>;
	};

	ad7879@2c {
	compatible = "adi,ad7879-1";
	reg = <0x2c>;
	interrupt-parent = <&gpio1>;
	interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
	touchscreen-max-pressure = <4096>;
	adi,resistance-plate-x = <120>;
	adi,first-conversion-delay = /bits/ 8 <3>;
	adi,acquisition-time = /bits/ 8 <1>;
	adi,median-filter-size = /bits/ 8 <2>;
	adi,averaging = /bits/ 8 <1>;
	adi,conversion-interval = /bits/ 8 <255>;
	};

	pmic@33 {
	compatible = "ricoh,rn5t567";
	reg = <0x33>;

	regulators {
	reg_DCDC1: DCDC1 { /* V1.0_SOC */
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1100000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_DCDC2: DCDC2 { /* V1.1_ARM */
	regulator-min-microvolt = <975000>;
	regulator-max-microvolt = <1100000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_DCDC3: DCDC3 { /* V1.8 */
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_DCDC4: DCDC4 { /* V1.35_DRAM */
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	};

	reg_LDO2: LDO2 { /* +V1.8_SD */
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_LDO4: LDO4 { /* V1.8_LPSR */
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};
	};
	};

	&i2c4 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c4>;
	pinctrl-1 = <&pinctrl_i2c4_recovery>;
	scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	};

	&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif_dat
	&pinctrl_lcdif_ctrl>;
	};

	&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	};

	&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	};

	&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	};

	&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
	};

	&reg_1p0d {
	vin-supply = <&reg_DCDC3>;
	};

	&sai1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	status = "okay";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
	uart-has-rtscts;
	fsl,dte-mode;
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
	uart-has-rtscts;
	fsl,dte-mode;
	};

	&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
	fsl,dte-mode;
	};

	&usbotg1 {
	dr_mode = "host";
	};

	&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
	disable-wp;
	vqmmc-supply = <&reg_LDO2>;
	};

	&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
	assigned-clock-rates = <400000000>;
	bus-width = <8>;
	fsl,tuning-step = <2>;
	vmmc-supply = <&reg_module_3v3>;
	vqmmc-supply = <&reg_DCDC3>;
	non-removable;
	sdhci-caps-mask = <0x80000000 0x0>;
	};

	&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4
	- &pinctrl_gpio7>;
	+ &pinctrl_gpio7 &pinctrl_usbc_det>;

	pinctrl_gpio1: gpio1-grp {
	fsl,pins = <
	MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */
	MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */
	MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */
	MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */
	MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */
	MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */
	MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */
	- MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 */
	MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */
	MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */
	MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */
	MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */
	MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */
	MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */
	MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */
	MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */
	MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */
	MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */
	MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */
	MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */
	MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */
	MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */
	MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */
	MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */
	- MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x74 /* SODIMM 106 */
	MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */
	MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */
	MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */
	MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */
	MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */
	MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */
	MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */
	MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */
	MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */
	MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */
	MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */
	MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */
	MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */
	MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */
	MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */
	MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */
	MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */
	>;
	};

	pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */
	fsl,pins = <
	MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */
	MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */
	MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */
	MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */
	MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */
	MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */
	MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */
	MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */
	MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */
	MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */
	MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */
	MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */
	>;
	};

	pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */
	fsl,pins = <
	MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */
	MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */
	MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */
	MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */
	MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */
	MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */
	>;
	};

	pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */
	fsl,pins = <
	MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */
	MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */
	>;
	};

	pinctrl_gpio7: gpio7-grp { /* Alternatively CAN1 */
	fsl,pins = <
	MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */
	MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
	>;
	};

	pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */
	fsl,pins = <
	MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
	>;
	};

	pinctrl_can_int: can-int-grp {
	fsl,pins = <
	MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */
	>;
	};

	pinctrl_enet1: enet1grp {
	fsl,pins = <
	- MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14
	MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
	MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73
	MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73
	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73

	MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73
	MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73
	MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73
	MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73
	MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
	MX7D_PAD_SD2_WP__ENET1_MDC 0x3
	>;
	};

	pinctrl_enet1_sleep: enet1sleepgrp {
	fsl,pins = <
	MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0
	MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0
	MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0
	MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0

	MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0
	MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0
	MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0
	MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0
	MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x0
	MX7D_PAD_SD2_WP__GPIO5_IO10 0x0
	>;
	};

	pinctrl_ecspi3_cs: ecspi3-cs-grp {
	fsl,pins = <
	MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
	>;
	};

	pinctrl_ecspi3: ecspi3-grp {
	fsl,pins = <
	MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2
	MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2
	MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2
	>;
	};

	pinctrl_flexcan1: flexcan1-grp {
	fsl,pins = <
	MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */
	MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */
	>;
	};

	pinctrl_flexcan2: flexcan2-grp {
	fsl,pins = <
	MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */
	MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */
	>;
	};

	pinctrl_gpio_bl_on: gpio-bl-on {
	fsl,pins = <
	MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */
	>;
	};

	pinctrl_gpmi_nand: gpmi-nand-grp {
	fsl,pins = <
	MX7D_PAD_SD3_CLK__NAND_CLE 0x71
	MX7D_PAD_SD3_CMD__NAND_ALE 0x71
	MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
	MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
	MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
	MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
	MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71
	MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71
	MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71
	MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71
	MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71
	MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71
	MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71
	MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
	>;
	};

	pinctrl_i2c4: i2c4-grp {
	fsl,pins = <
	MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f
	MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f
	>;
	};

	pinctrl_i2c4_recovery: i2c4-recoverygrp {
	fsl,pins = <
	MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f
	MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f
	>;
	};

	pinctrl_lcdif_dat: lcdif-dat-grp {
	fsl,pins = <
	MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
	MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
	MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
	MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
	MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
	MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
	MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
	MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
	MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
	MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
	MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
	MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
	MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
	MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
	MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
	MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
	MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
	MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
	>;
	};

	pinctrl_lcdif_dat_24: lcdif-dat-24-grp {
	fsl,pins = <
	MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
	MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
	MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
	MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
	MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
	MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
	>;
	};

	pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
	fsl,pins = <
	MX7D_PAD_LCD_CLK__LCD_CLK 0x79
	MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
	MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
	MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
	>;
	};

	pinctrl_pwm1: pwm1-grp {
	fsl,pins = <
	MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79
	MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4
	>;
	};

	pinctrl_pwm2: pwm2-grp {
	fsl,pins = <
	MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79
	>;
	};

	pinctrl_pwm3: pwm3-grp {
	fsl,pins = <
	MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79
	>;
	};

	pinctrl_pwm4: pwm4-grp {
	fsl,pins = <
	MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79
	MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4
	>;
	};

	pinctrl_uart1: uart1-grp {
	fsl,pins = <
	MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79
	MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79
	MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79
	MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79
	>;
	};

	pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
	fsl,pins = <
	MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */
	MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */
	>;
	};

	pinctrl_uart2: uart2-grp {
	fsl,pins = <
	MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79
	MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79
	MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79
	MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79
	>;
	};
	pinctrl_uart3: uart3-grp {
	fsl,pins = <
	MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79
	MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79
	>;
	};

	+ pinctrl_usbc_det: gpio-usbc-det {
	+ fsl,pins = <
	+ MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14
	+ >;
	+ };
	+
	pinctrl_usbh_reg: gpio-usbh-vbus {
	fsl,pins = <
	MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */
	>;
	};

	pinctrl_usdhc1: usdhc1-grp {
	fsl,pins = <
	MX7D_PAD_SD1_CMD__SD1_CMD 0x59
	MX7D_PAD_SD1_CLK__SD1_CLK 0x19
	MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
	MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
	MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
	MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
	>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
	fsl,pins = <
	MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
	MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
	MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
	MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
	MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
	MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
	>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
	fsl,pins = <
	MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
	MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
	MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
	MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
	MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
	MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX7D_PAD_SD3_CMD__SD3_CMD 0x59
	MX7D_PAD_SD3_CLK__SD3_CLK 0x19
	MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
	MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
	MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
	MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
	MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
	MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
	MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
	MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
	MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
	>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
	fsl,pins = <
	MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
	MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
	MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
	MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
	MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
	MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
	MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
	MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
	MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
	MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
	MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
	>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
	fsl,pins = <
	MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
	MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
	MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
	MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
	MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
	MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
	MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
	MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
	MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
	MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
	MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
	>;
	};

	pinctrl_sai1: sai1-grp {
	fsl,pins = <
	MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
	MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
	MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
	MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
	>;
	};

	pinctrl_sai1_mclk: sai1grp_mclk {
	fsl,pins = <
	MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
	>;
	};
	};

	&iomuxc_lpsr {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_lpsr>;

	pinctrl_gpio_lpsr: gpio1-grp {
	fsl,pins = <
	MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59
	MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59
	>;
	};

	pinctrl_gpiokeys: gpiokeysgrp {
	fsl,pins = <
	MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19
	>;
	};

	pinctrl_i2c1: i2c1-grp {
	fsl,pins = <
	MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
	MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f
	>;
	};

	pinctrl_i2c1_recovery: i2c1-recoverygrp {
	fsl,pins = <
	MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f
	MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f
	>;
	};

	pinctrl_cd_usdhc1: usdhc1-cd-grp {
	fsl,pins = <
	MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */
	>;
	};

	pinctrl_uart1_ctrl2: uart1-ctrl2-grp {
	fsl,pins = <
	MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* DSR */
	MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* RI */
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx7d-cl-som-imx7.dts b/sys/gnu/dts/arm/imx7d-cl-som-imx7.dts
	index 7646284e13a7..89267cd59037 100644
	--- a/sys/gnu/dts/arm/imx7d-cl-som-imx7.dts
	+++ b/sys/gnu/dts/arm/imx7d-cl-som-imx7.dts
	@@ -1,290 +1,290 @@
	/*
	* Support for CompuLab CL-SOM-iMX7 System-on-Module
	*
	* Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
	* Author: Ilya Ledvich <ilya@compulab.co.il>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*/

	/dts-v1/;

	#include "imx7d.dtsi"

	/ {
	model = "CompuLab CL-SOM-iMX7";
	compatible = "compulab,cl-som-imx7", "fsl,imx7d";

	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */
	};

	reg_usb_otg1_vbus: regulator-vbus {
	compatible = "regulator-fixed";
	regulator-name = "usb_otg1_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};
	};

	&cpu0 {
	cpu-supply = <&sw1a_reg>;
	};

	&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
	<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
	assigned-clock-rates = <0>, <100000000>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy0: ethernet-phy@0 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <0>;
	};

	ethphy1: ethernet-phy@1 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <1>;
	};
	};
	};

	&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
	<&clks IMX7D_ENET2_TIME_ROOT_CLK>;
	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
	assigned-clock-rates = <0>, <100000000>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy1>;
	fsl,magic-packet;
	status = "okay";
	};

	&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	pmic: pmic@8 {
	compatible = "fsl,pfuze3000";
	- reg = <0x08>;
	+ reg = <0x8>;

	regulators {
	sw1a_reg: sw1a {
	regulator-min-microvolt = <700000>;
	- regulator-max-microvolt = <1475000>;
	+ regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	/* use sw1c_reg to align with pfuze100/pfuze200 */
	sw1c_reg: sw1b {
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1475000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <6250>;
	};

	sw2_reg: sw2 {
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1850000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sw3a_reg: sw3 {
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1650000>;
	regulator-boot-on;
	regulator-always-on;
	};

	swbst_reg: swbst {
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5150000>;
	};

	snvs_reg: vsnvs {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <3000000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vref_reg: vrefddr {
	regulator-boot-on;
	regulator-always-on;
	};

	vgen1_reg: vldo1 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen2_reg: vldo2 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	};

	vgen3_reg: vccsd {
	regulator-min-microvolt = <2850000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen4_reg: v33 {
	regulator-min-microvolt = <2850000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen5_reg: vldo3 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vgen6_reg: vldo4 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};
	};
	};

	pca9555: pca9555@20 {
	compatible = "nxp,pca9555";
	gpio-controller;
	#gpio-cells = <2>;
	reg = <0x20>;
	};

	eeprom@50 {
	compatible = "atmel,24c08";
	reg = <0x50>;
	pagesize = <16>;
	};
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
	status = "okay";
	};

	&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1>;
	vbus-supply = <&reg_usb_otg1_vbus>;
	status = "okay";
	};

	&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
	assigned-clock-rates = <400000000>;
	bus-width = <8>;
	fsl,tuning-step = <2>;
	non-removable;
	status = "okay";
	};

	&iomuxc {
	pinctrl_enet1: enet1grp {
	fsl,pins = <
	MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x30
	MX7D_PAD_SD2_WP__ENET1_MDC 0x30
	MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x11
	MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x11
	MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x11
	MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x11
	MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x11
	MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x11
	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x11
	MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11
	MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11
	MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11
	MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x11
	MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
	>;
	};

	pinctrl_enet2: enet2grp {
	fsl,pins = <
	MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x11
	MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x11
	MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x11
	MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x11
	MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x11
	MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x11
	MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x11
	MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x11
	MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x11
	MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x11
	MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x11
	MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x11
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
	MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX7D_PAD_SD3_CMD__SD3_CMD 0x59
	MX7D_PAD_SD3_CLK__SD3_CLK 0x19
	MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
	MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
	MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
	MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
	MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
	MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
	MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
	MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
	MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
	>;
	};
	};

	&iomuxc_lpsr {
	pinctrl_usbotg1: usbotg1grp {
	fsl,pins = <
	MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 /* OTG PWREN */
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx7d-colibri-aster.dts b/sys/gnu/dts/arm/imx7d-colibri-aster.dts
	new file mode 100644
	index 000000000000..f3f0537d5a37
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx7d-colibri-aster.dts
	@@ -0,0 +1,20 @@
	+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	+/*
	+ * Copyright 2017-2020 Toradex AG
	+ *
	+ */
	+
	+/dts-v1/;
	+#include "imx7d-colibri.dtsi"
	+#include "imx7-colibri-aster.dtsi"
	+
	+/ {
	+ model = "Toradex Colibri iMX7D on Aster Carrier Board";
	+ compatible = "toradex,colibri-imx7d-aster", "toradex,colibri-imx7d",
	+ "fsl,imx7d";
	+};
	+
	+&usbotg2 {
	+ vbus-supply = <&reg_usbh_vbus>;
	+ status = "okay";
	+};
	diff --git a/sys/gnu/dts/arm/imx7d-colibri-emmc-aster.dts b/sys/gnu/dts/arm/imx7d-colibri-emmc-aster.dts
	new file mode 100644
	index 000000000000..20480276cb0e
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx7d-colibri-emmc-aster.dts
	@@ -0,0 +1,20 @@
	+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	+/*
	+ * Copyright 2017-2020 Toradex AG
	+ *
	+ */
	+
	+/dts-v1/;
	+#include "imx7d-colibri-emmc.dtsi"
	+#include "imx7-colibri-aster.dtsi"
	+
	+/ {
	+ model = "Toradex Colibri iMX7D 1GB (eMMC) on Aster Carrier Board";
	+ compatible = "toradex,colibri-imx7d-emmc-aster",
	+ "toradex,colibri-imx7d-emmc", "fsl,imx7d";
	+};
	+
	+&usbotg2 {
	+ vbus-supply = <&reg_usbh_vbus>;
	+ status = "okay";
	+};
	diff --git a/sys/gnu/dts/arm/imx7d-colibri-emmc.dtsi b/sys/gnu/dts/arm/imx7d-colibri-emmc.dtsi
	index 898f4b8d7421..af39e5370fa1 100644
	--- a/sys/gnu/dts/arm/imx7d-colibri-emmc.dtsi
	+++ b/sys/gnu/dts/arm/imx7d-colibri-emmc.dtsi
	@@ -1,22 +1,48 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	/*
	* Copyright 2017 Toradex AG
	*/

	#include "imx7d.dtsi"
	#include "imx7-colibri.dtsi"

	/ {
	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x40000000>;
	};
	};

	+&gpio6 {
	+ gpio-line-names = "",
	+ "",
	+ "",
	+ "",
	+ "",
	+ "",
	+ "",
	+ "",
	+ "",
	+ "",
	+ "",
	+ "",
	+ "SODIMM_169",
	+ "SODIMM_157",
	+ "",
	+ "SODIMM_163",
	+ "SODIMM_77",
	+ "SODIMM_24",
	+ "",
	+ "SODIMM_25",
	+ "SODIMM_27",
	+ "SODIMM_32",
	+ "SODIMM_34";
	+};
	+
	&usbotg2 {
	dr_mode = "host";
	};

	&usdhc3 {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/imx7d-colibri-eval-v3.dts b/sys/gnu/dts/arm/imx7d-colibri-eval-v3.dts
	index 136e11ab4893..87b132bcd272 100644
	--- a/sys/gnu/dts/arm/imx7d-colibri-eval-v3.dts
	+++ b/sys/gnu/dts/arm/imx7d-colibri-eval-v3.dts
	@@ -1,56 +1,19 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2016 Toradex AG
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License as
	- * published by the Free Software Foundation; either version 2 of the
	- * License, or (at your option) any later version.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	+ * Copyright 2016-2020 Toradex
	*/

	/dts-v1/;
	#include "imx7d-colibri.dtsi"
	#include "imx7-colibri-eval-v3.dtsi"

	/ {
	model = "Toradex Colibri iMX7D on Colibri Evaluation Board V3";
	compatible = "toradex,colibri-imx7d-eval-v3", "toradex,colibri-imx7d",
	"fsl,imx7d";
	};

	&usbotg2 {
	vbus-supply = <&reg_usbh_vbus>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/imx7d-colibri.dtsi b/sys/gnu/dts/arm/imx7d-colibri.dtsi
	index e2e327f437e3..c59d72e50920 100644
	--- a/sys/gnu/dts/arm/imx7d-colibri.dtsi
	+++ b/sys/gnu/dts/arm/imx7d-colibri.dtsi
	@@ -1,59 +1,22 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2016 Toradex AG
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License as
	- * published by the Free Software Foundation; either version 2 of the
	- * License, or (at your option) any later version.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	+ * Copyright 2016-2020 Toradex
	*/

	#include "imx7d.dtsi"
	#include "imx7-colibri.dtsi"

	/ {
	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x20000000>;
	};
	};

	&gpmi {
	status = "okay";
	};

	&usbotg2 {
	dr_mode = "host";
	};
	diff --git a/sys/gnu/dts/arm/imx7d-pico-dwarf.dts b/sys/gnu/dts/arm/imx7d-pico-dwarf.dts
	new file mode 100644
	index 000000000000..5162fe227d1e
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx7d-pico-dwarf.dts
	@@ -0,0 +1,87 @@
	+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	+//
	+// Copyright 2015 Technexion Ltd.
	+//
	+// Author: Wig Cheng <wig.cheng@technexion.com>
	+// Richard Hu <richard.hu@technexion.com>
	+// Tapani Utriainen <tapani@technexion.com>
	+/dts-v1/;
	+
	+#include "imx7d-pico.dtsi"
	+/ {
	+ model = "TechNexion PICO-IMX7D and DWARF baseboard";
	+ compatible = "technexion,imx7d-pico-dwarf", "fsl,imx7d";
	+
	+ sound {
	+ compatible = "fsl,imx-audio-sgtl5000";
	+ model = "imx7d-sgtl5000";
	+ audio-cpu = <&sai1>;
	+ audio-codec = <&sgtl5000>;
	+ audio-routing =
	+ "LINE_IN", "Line In Jack",
	+ "MIC_IN", "Mic Jack",
	+ "Mic Jack", "Mic Bias",
	+ "Headphone Jack", "HP_OUT";
	+ };
	+
	+ sys_mclk: clock-sys-mclk {
	+ compatible = "fixed-clock";
	+ #clock-cells = <0>;
	+ clock-frequency = <24576000>;
	+ };
	+};
	+
	+&i2c1 {
	+ clock_frequency = <100000>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_i2c1>;
	+ status = "okay";
	+
	+ sgtl5000: audio-codec@a {
	+ reg = <0x0a>;
	+ compatible = "fsl,sgtl5000";
	+ clocks = <&sys_mclk>;
	+ VDDA-supply = <&reg_2p5v>;
	+ VDDIO-supply = <&reg_3p3v>;
	+ };
	+
	+ pressure-sensor@60 {
	+ compatible = "fsl,mpl3115";
	+ reg = <0x60>;
	+ };
	+};
	+
	+&i2c4 {
	+ clock_frequency = <100000>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_i2c1>;
	+ status = "okay";
	+
	+ pca9554: io-expander@25 {
	+ compatible = "nxp,pca9554";
	+ gpio-controller;
	+ #gpio-cells = <2>;
	+ #interrupt-cells = <2>;
	+ reg = <0x25>;
	+ };
	+
	+ touchscreen@38 {
	+ compatible = "edt,edt-ft5x06";
	+ reg = <0x38>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_touchscreen>;
	+ interrupt-parent = <&gpio2>;
	+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
	+ reset-gpios = <&pca9554 4 GPIO_ACTIVE_LOW>;
	+ touchscreen-size-x = <800>;
	+ touchscreen-size-y = <480>;
	+ };
	+};
	+
	+&iomuxc {
	+ pinctrl_touchscreen: touchscreengrp {
	+ fsl,pins = <
	+ MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14
	+ >;
	+ };
	+};
	diff --git a/sys/gnu/dts/arm/imx7d-pico-nymph.dts b/sys/gnu/dts/arm/imx7d-pico-nymph.dts
	new file mode 100644
	index 000000000000..104a85254adb
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx7d-pico-nymph.dts
	@@ -0,0 +1,84 @@
	+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	+//
	+// Copyright 2015 Technexion Ltd.
	+//
	+// Author: Wig Cheng <wig.cheng@technexion.com>
	+// Richard Hu <richard.hu@technexion.com>
	+// Tapani Utriainen <tapani@technexion.com>
	+/dts-v1/;
	+
	+#include "imx7d-pico.dtsi"
	+/ {
	+ model = "TechNexion PICO-IMX7 and NYMPH baseboard";
	+ compatible = "technexion,imx7d-pico-nymph", "fsl,imx7d";
	+
	+ leds {
	+ compatible = "gpio-leds";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_gpio_leds>;
	+
	+ led {
	+ label = "gpio-led";
	+ gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
	+ };
	+ };
	+
	+ sound {
	+ compatible = "fsl,imx-audio-sgtl5000";
	+ model = "imx7d-sgtl5000";
	+ audio-cpu = <&sai1>;
	+ audio-codec = <&sgtl5000>;
	+ audio-routing =
	+ "LINE_IN", "Line In Jack",
	+ "MIC_IN", "Mic Jack",
	+ "Mic Jack", "Mic Bias",
	+ "Headphone Jack", "HP_OUT";
	+ };
	+
	+ sys_mclk: clock-sys-mclk {
	+ compatible = "fixed-clock";
	+ #clock-cells = <0>;
	+ clock-frequency = <24576000>;
	+ };
	+};
	+
	+&i2c1 {
	+ clock_frequency = <100000>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_i2c1>;
	+ status = "okay";
	+
	+ sgtl5000: audio-codec@a {
	+ reg = <0x0a>;
	+ compatible = "fsl,sgtl5000";
	+ clocks = <&sys_mclk>;
	+ VDDA-supply = <&reg_2p5v>;
	+ VDDIO-supply = <&reg_3p3v>;
	+ };
	+
	+ adc@52 {
	+ compatible = "ti,adc081c";
	+ reg = <0x52>;
	+ vref-supply = <&reg_2p5v>;
	+ };
	+};
	+
	+&i2c2 {
	+ clock_frequency = <100000>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_i2c2>;
	+ status = "okay";
	+
	+ rtc@68 {
	+ compatible = "dallas,ds1337";
	+ reg = <0x68>;
	+ };
	+};
	+
	+&iomuxc {
	+ pinctrl_gpio_leds: gpioledsgrp {
	+ fsl,pins = <
	+ MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14
	+ >;
	+ };
	+};
	diff --git a/sys/gnu/dts/arm/imx7s-colibri-aster.dts b/sys/gnu/dts/arm/imx7s-colibri-aster.dts
	new file mode 100644
	index 000000000000..fca4e0a95c1b
	--- /dev/null
	+++ b/sys/gnu/dts/arm/imx7s-colibri-aster.dts
	@@ -0,0 +1,15 @@
	+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	+/*
	+ * Copyright 2017-2020 Toradex AG
	+ *
	+ */
	+
	+/dts-v1/;
	+#include "imx7s-colibri.dtsi"
	+#include "imx7-colibri-aster.dtsi"
	+
	+/ {
	+ model = "Toradex Colibri iMX7S on Aster Carrier Board";
	+ compatible = "toradex,colibri-imx7s-aster", "toradex,colibri-imx7s",
	+ "fsl,imx7s";
	+};
	diff --git a/sys/gnu/dts/arm/imx7s-colibri-eval-v3.dts b/sys/gnu/dts/arm/imx7s-colibri-eval-v3.dts
	index bd2a49c1ade6..aa70d3f2e2e2 100644
	--- a/sys/gnu/dts/arm/imx7s-colibri-eval-v3.dts
	+++ b/sys/gnu/dts/arm/imx7s-colibri-eval-v3.dts
	@@ -1,51 +1,14 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2016 Toradex AG
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License as
	- * published by the Free Software Foundation; either version 2 of the
	- * License, or (at your option) any later version.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	+ * Copyright 2016-2020 Toradex
	*/

	/dts-v1/;
	#include "imx7s-colibri.dtsi"
	#include "imx7-colibri-eval-v3.dtsi"

	/ {
	model = "Toradex Colibri iMX7S on Colibri Evaluation Board V3";
	compatible = "toradex,colibri-imx7s-eval-v3", "toradex,colibri-imx7s",
	"fsl,imx7s";
	};
	diff --git a/sys/gnu/dts/arm/imx7s-colibri.dtsi b/sys/gnu/dts/arm/imx7s-colibri.dtsi
	index 6d16e32aed89..94de220a5965 100644
	--- a/sys/gnu/dts/arm/imx7s-colibri.dtsi
	+++ b/sys/gnu/dts/arm/imx7s-colibri.dtsi
	@@ -1,55 +1,18 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2016 Toradex AG
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License as
	- * published by the Free Software Foundation; either version 2 of the
	- * License, or (at your option) any later version.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	+ * Copyright 2016-2020 Toradex
	*/

	#include "imx7s.dtsi"
	#include "imx7-colibri.dtsi"

	/ {
	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x10000000>;
	};
	};

	&gpmi {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/imx7s.dtsi b/sys/gnu/dts/arm/imx7s.dtsi
	index 568d7a984aa6..76e3ffbbbfbf 100644
	--- a/sys/gnu/dts/arm/imx7s.dtsi
	+++ b/sys/gnu/dts/arm/imx7s.dtsi
	@@ -1,1226 +1,1228 @@
	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	//
	// Copyright 2015 Freescale Semiconductor, Inc.
	// Copyright 2016 Toradex AG

	#include <dt-bindings/clock/imx7d-clock.h>
	#include <dt-bindings/power/imx7-power.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/reset/imx7-reset.h>
	#include "imx7d-pinfunc.h"

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	* The decompressor and also some bootloaders rely on a
	* pre-existing /chosen node to be available to insert the
	* command line and merge other ATAGS info.
	*/
	chosen {};

	aliases {
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	gpio3 = &gpio4;
	gpio4 = &gpio5;
	gpio5 = &gpio6;
	gpio6 = &gpio7;
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	i2c2 = &i2c3;
	i2c3 = &i2c4;
	mmc0 = &usdhc1;
	mmc1 = &usdhc2;
	mmc2 = &usdhc3;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	serial4 = &uart5;
	serial5 = &uart6;
	serial6 = &uart7;
	spi0 = &ecspi1;
	spi1 = &ecspi2;
	spi2 = &ecspi3;
	spi3 = &ecspi4;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	idle-states {
	entry-method = "psci";

	cpu_sleep_wait: cpu-sleep-wait {
	compatible = "arm,idle-state";
	arm,psci-suspend-param = <0x0010000>;
	local-timer-stop;
	entry-latency-us = <100>;
	exit-latency-us = <50>;
	min-residency-us = <1000>;
	};
	};

	cpu0: cpu@0 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <0>;
	clock-frequency = <792000000>;
	clock-latency = <61036>; /* two CLK32 periods */
	clocks = <&clks IMX7D_CLK_ARM>;
	cpu-idle-states = <&cpu_sleep_wait>;
	};
	};

	ckil: clock-cki {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "ckil";
	};

	osc: clock-osc {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "osc";
	};

	usbphynop1: usbphynop1 {
	compatible = "usb-nop-xceiv";
	clocks = <&clks IMX7D_USB_PHY1_CLK>;
	clock-names = "main_clk";
	#phy-cells = <0>;
	};

	usbphynop3: usbphynop3 {
	compatible = "usb-nop-xceiv";
	clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
	clock-names = "main_clk";
	#phy-cells = <0>;
	};

	pmu {
	compatible = "arm,cortex-a7-pmu";
	interrupt-parent = <&gpc>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>;
	};

	replicator {
	/*
	* non-configurable replicators don't show up on the
	* AMBA bus. As such no need to add "arm,primecell"
	*/
	compatible = "arm,coresight-static-replicator";

	out-ports {
	#address-cells = <1>;
	#size-cells = <0>;
	/* replicator output ports */
	port@0 {
	reg = <0>;
	replicator_out_port0: endpoint {
	remote-endpoint = <&tpiu_in_port>;
	};
	};

	port@1 {
	reg = <1>;
	replicator_out_port1: endpoint {
	remote-endpoint = <&etr_in_port>;
	};
	};
	};

	in-ports {
	port {
	replicator_in_port0: endpoint {
	remote-endpoint = <&etf_out_port>;
	};
	};
	};
	};

	tempmon: tempmon {
	compatible = "fsl,imx7d-tempmon";
	interrupt-parent = <&gpc>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	fsl,tempmon = <&anatop>;
	nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
	nvmem-cell-names = "calib", "temp_grade";
	clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupt-parent = <&intc>;
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&gpc>;
	ranges;

	funnel@30041000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0x30041000 0x1000>;
	clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
	clock-names = "apb_pclk";

	ca_funnel_in_ports: in-ports {
	port {
	ca_funnel_in_port0: endpoint {
	remote-endpoint = <&etm0_out_port>;
	};
	};

	/* the other input ports are not connect to anything */
	};

	out-ports {
	port {
	ca_funnel_out_port0: endpoint {
	remote-endpoint = <&hugo_funnel_in_port0>;
	};
	};

	};
	};

	etm@3007c000 {
	compatible = "arm,coresight-etm3x", "arm,primecell";
	reg = <0x3007c000 0x1000>;
	cpu = <&cpu0>;
	clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	etm0_out_port: endpoint {
	remote-endpoint = <&ca_funnel_in_port0>;
	};
	};
	};
	};

	funnel@30083000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0x30083000 0x1000>;
	clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
	clock-names = "apb_pclk";

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	hugo_funnel_in_port0: endpoint {
	remote-endpoint = <&ca_funnel_out_port0>;
	};
	};

	port@1 {
	reg = <1>;
	hugo_funnel_in_port1: endpoint {
	/* M4 input */
	};
	};
	/* the other input ports are not connect to anything */
	};

	out-ports {
	port {
	hugo_funnel_out_port0: endpoint {
	remote-endpoint = <&etf_in_port>;
	};
	};
	};
	};

	etf@30084000 {
	compatible = "arm,coresight-tmc", "arm,primecell";
	reg = <0x30084000 0x1000>;
	clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
	clock-names = "apb_pclk";

	in-ports {
	port {
	etf_in_port: endpoint {
	remote-endpoint = <&hugo_funnel_out_port0>;
	};
	};
	};

	out-ports {
	port {
	etf_out_port: endpoint {
	remote-endpoint = <&replicator_in_port0>;
	};
	};
	};
	};

	etr@30086000 {
	compatible = "arm,coresight-tmc", "arm,primecell";
	reg = <0x30086000 0x1000>;
	clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
	clock-names = "apb_pclk";

	in-ports {
	port {
	etr_in_port: endpoint {
	remote-endpoint = <&replicator_out_port1>;
	};
	};
	};
	};

	tpiu@30087000 {
	compatible = "arm,coresight-tpiu", "arm,primecell";
	reg = <0x30087000 0x1000>;
	clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
	clock-names = "apb_pclk";

	in-ports {
	port {
	tpiu_in_port: endpoint {
	remote-endpoint = <&replicator_out_port0>;
	};
	};
	};
	};

	intc: interrupt-controller@31001000 {
	compatible = "arm,cortex-a7-gic";
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_HIGH)>;
	#interrupt-cells = <3>;
	interrupt-controller;
	interrupt-parent = <&intc>;
	reg = <0x31001000 0x1000>,
	<0x31002000 0x2000>,
	<0x31004000 0x2000>,
	<0x31006000 0x2000>;
	};

	- aips1: aips-bus@30000000 {
	+ aips1: bus@30000000 {
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x30000000 0x400000>;
	ranges;

	gpio1: gpio@30200000 {
	compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
	reg = <0x30200000 0x10000>;
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
	};

	gpio2: gpio@30210000 {
	compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
	reg = <0x30210000 0x10000>;
	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 13 32>;
	};

	gpio3: gpio@30220000 {
	compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
	reg = <0x30220000 0x10000>;
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 45 29>;
	};

	gpio4: gpio@30230000 {
	compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
	reg = <0x30230000 0x10000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 74 24>;
	};

	gpio5: gpio@30240000 {
	compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
	reg = <0x30240000 0x10000>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 98 18>;
	};

	gpio6: gpio@30250000 {
	compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
	reg = <0x30250000 0x10000>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 116 23>;
	};

	gpio7: gpio@30260000 {
	compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
	reg = <0x30260000 0x10000>;
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 139 16>;
	};

	- wdog1: wdog@30280000 {
	+ wdog1: watchdog@30280000 {
	compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
	reg = <0x30280000 0x10000>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
	};

	- wdog2: wdog@30290000 {
	+ wdog2: watchdog@30290000 {
	compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
	reg = <0x30290000 0x10000>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
	status = "disabled";
	};

	- wdog3: wdog@302a0000 {
	+ wdog3: watchdog@302a0000 {
	compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
	reg = <0x302a0000 0x10000>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
	status = "disabled";
	};

	- wdog4: wdog@302b0000 {
	+ wdog4: watchdog@302b0000 {
	compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
	reg = <0x302b0000 0x10000>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
	status = "disabled";
	};

	iomuxc_lpsr: iomuxc-lpsr@302c0000 {
	compatible = "fsl,imx7d-iomuxc-lpsr";
	reg = <0x302c0000 0x10000>;
	fsl,input-sel = <&iomuxc>;
	};

	- gpt1: gpt@302d0000 {
	+ gpt1: timer@302d0000 {
	compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
	reg = <0x302d0000 0x10000>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
	<&clks IMX7D_GPT1_ROOT_CLK>;
	clock-names = "ipg", "per";
	};

	- gpt2: gpt@302e0000 {
	+ gpt2: timer@302e0000 {
	compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
	reg = <0x302e0000 0x10000>;
	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
	<&clks IMX7D_GPT2_ROOT_CLK>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	- gpt3: gpt@302f0000 {
	+ gpt3: timer@302f0000 {
	compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
	reg = <0x302f0000 0x10000>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
	<&clks IMX7D_GPT3_ROOT_CLK>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	- gpt4: gpt@30300000 {
	+ gpt4: timer@30300000 {
	compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
	reg = <0x30300000 0x10000>;
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
	<&clks IMX7D_GPT4_ROOT_CLK>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	- kpp: kpp@30320000 {
	+ kpp: keypad@30320000 {
	compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
	reg = <0x30320000 0x10000>;
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_KPP_ROOT_CLK>;
	status = "disabled";
	};

	- iomuxc: iomuxc@30330000 {
	+ iomuxc: pinctrl@30330000 {
	compatible = "fsl,imx7d-iomuxc";
	reg = <0x30330000 0x10000>;
	};

	gpr: iomuxc-gpr@30340000 {
	compatible = "fsl,imx7d-iomuxc-gpr",
	"fsl,imx6q-iomuxc-gpr", "syscon",
	"simple-mfd";
	reg = <0x30340000 0x10000>;

	mux: mux-controller {
	compatible = "mmio-mux";
	#mux-control-cells = <0>;
	mux-reg-masks = <0x14 0x00000010>;
	};

	video_mux: csi-mux {
	compatible = "video-mux";
	mux-controls = <&mux 0>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";

	port@0 {
	reg = <0>;
	};

	port@1 {
	reg = <1>;

	csi_mux_from_mipi_vc0: endpoint {
	remote-endpoint = <&mipi_vc0_to_csi_mux>;
	};
	};

	port@2 {
	reg = <2>;

	csi_mux_to_csi: endpoint {
	remote-endpoint = <&csi_from_csi_mux>;
	};
	};
	};
	};

	ocotp: ocotp-ctrl@30350000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "fsl,imx7d-ocotp", "syscon";
	reg = <0x30350000 0x10000>;
	clocks = <&clks IMX7D_OCOTP_CLK>;

	tempmon_calib: calib@3c {
	reg = <0x3c 0x4>;
	};

	fuse_grade: fuse-grade@10 {
	reg = <0x10 0x4>;
	};
	};

	anatop: anatop@30360000 {
	compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
	"syscon", "simple-mfd";
	reg = <0x30360000 0x10000>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

	reg_1p0d: regulator-vdd1p0d {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vdd1p0d";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1200000>;
	anatop-reg-offset = <0x210>;
	anatop-vol-bit-shift = <8>;
	anatop-vol-bit-width = <5>;
	anatop-min-bit-val = <8>;
	anatop-min-voltage = <800000>;
	anatop-max-voltage = <1200000>;
	anatop-enable-bit = <0>;
	};

	reg_1p2: regulator-vdd1p2 {
	compatible = "fsl,anatop-regulator";
	regulator-name = "vdd1p2";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1300000>;
	anatop-reg-offset = <0x220>;
	anatop-vol-bit-shift = <8>;
	anatop-vol-bit-width = <5>;
	anatop-min-bit-val = <0x14>;
	anatop-min-voltage = <1100000>;
	anatop-max-voltage = <1300000>;
	anatop-enable-bit = <0>;
	};
	};

	snvs: snvs@30370000 {
	compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
	reg = <0x30370000 0x10000>;

	snvs_rtc: snvs-rtc-lp {
	compatible = "fsl,sec-v4.0-mon-rtc-lp";
	regmap = <&snvs>;
	offset = <0x34>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_SNVS_CLK>;
	clock-names = "snvs-rtc";
	};

	snvs_pwrkey: snvs-powerkey {
	compatible = "fsl,sec-v4.0-pwrkey";
	regmap = <&snvs>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clks IMX7D_SNVS_CLK>;
	+ clock-names = "snvs-pwrkey";
	linux,keycode = <KEY_POWER>;
	wakeup-source;
	status = "disabled";
	};
	};

	- clks: ccm@30380000 {
	+ clks: clock-controller@30380000 {
	compatible = "fsl,imx7d-ccm";
	reg = <0x30380000 0x10000>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	#clock-cells = <1>;
	clocks = <&ckil>, <&osc>;
	clock-names = "ckil", "osc";
	};

	src: src@30390000 {
	compatible = "fsl,imx7d-src", "syscon";
	reg = <0x30390000 0x10000>;
	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	#reset-cells = <1>;
	};

	gpc: gpc@303a0000 {
	compatible = "fsl,imx7d-gpc";
	reg = <0x303a0000 0x10000>;
	interrupt-controller;
	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <3>;
	interrupt-parent = <&intc>;
	#power-domain-cells = <1>;

	pgc {
	#address-cells = <1>;
	#size-cells = <0>;

	pgc_mipi_phy: power-domain@0 {
	#power-domain-cells = <0>;
	reg = <0>;
	power-supply = <&reg_1p0d>;
	};

	pgc_pcie_phy: power-domain@1 {
	#power-domain-cells = <0>;
	reg = <1>;
	power-supply = <&reg_1p0d>;
	};

	pgc_hsic_phy: power-domain@2 {
	#power-domain-cells = <0>;
	reg = <2>;
	power-supply = <&reg_1p2>;
	};
	};
	};
	};

	- aips2: aips-bus@30400000 {
	+ aips2: bus@30400000 {
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x30400000 0x400000>;
	ranges;

	adc1: adc@30610000 {
	compatible = "fsl,imx7d-adc";
	reg = <0x30610000 0x10000>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_ADC_ROOT_CLK>;
	clock-names = "adc";
	#io-channel-cells = <1>;
	status = "disabled";
	};

	adc2: adc@30620000 {
	compatible = "fsl,imx7d-adc";
	reg = <0x30620000 0x10000>;
	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_ADC_ROOT_CLK>;
	clock-names = "adc";
	#io-channel-cells = <1>;
	status = "disabled";
	};

	ecspi4: spi@30630000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
	reg = <0x30630000 0x10000>;
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
	<&clks IMX7D_ECSPI4_ROOT_CLK>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	pwm1: pwm@30660000 {
	compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
	reg = <0x30660000 0x10000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
	<&clks IMX7D_PWM1_ROOT_CLK>;
	clock-names = "ipg", "per";
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm2: pwm@30670000 {
	compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
	reg = <0x30670000 0x10000>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
	<&clks IMX7D_PWM2_ROOT_CLK>;
	clock-names = "ipg", "per";
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm3: pwm@30680000 {
	compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
	reg = <0x30680000 0x10000>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
	<&clks IMX7D_PWM3_ROOT_CLK>;
	clock-names = "ipg", "per";
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm4: pwm@30690000 {
	compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
	reg = <0x30690000 0x10000>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
	<&clks IMX7D_PWM4_ROOT_CLK>;
	clock-names = "ipg", "per";
	#pwm-cells = <3>;
	status = "disabled";
	};

	csi: csi@30710000 {
	compatible = "fsl,imx7-csi";
	reg = <0x30710000 0x10000>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_CLK_DUMMY>,
	<&clks IMX7D_CSI_MCLK_ROOT_CLK>,
	<&clks IMX7D_CLK_DUMMY>;
	clock-names = "axi", "mclk", "dcic";
	status = "disabled";

	port {
	csi_from_csi_mux: endpoint {
	remote-endpoint = <&csi_mux_to_csi>;
	};
	};
	};

	lcdif: lcdif@30730000 {
	compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
	reg = <0x30730000 0x10000>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
	<&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
	clock-names = "pix", "axi";
	status = "disabled";
	};

	mipi_csi: mipi-csi@30750000 {
	compatible = "fsl,imx7-mipi-csi2";
	reg = <0x30750000 0x10000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_IPG_ROOT_CLK>,
	<&clks IMX7D_MIPI_CSI_ROOT_CLK>,
	<&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
	clock-names = "pclk", "wrap", "phy";
	power-domains = <&pgc_mipi_phy>;
	phy-supply = <&reg_1p0d>;
	resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
	reset-names = "mrst";
	status = "disabled";

	port@0 {
	reg = <0>;
	};

	port@1 {
	reg = <1>;

	mipi_vc0_to_csi_mux: endpoint {
	remote-endpoint = <&csi_mux_from_mipi_vc0>;
	};
	};
	};
	};

	- aips3: aips-bus@30800000 {
	+ aips3: bus@30800000 {
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x30800000 0x400000>;
	ranges;

	spba-bus@30800000 {
	compatible = "fsl,spba-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x30800000 0x100000>;
	ranges;

	ecspi1: spi@30820000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
	reg = <0x30820000 0x10000>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
	<&clks IMX7D_ECSPI1_ROOT_CLK>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ecspi2: spi@30830000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
	reg = <0x30830000 0x10000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
	<&clks IMX7D_ECSPI2_ROOT_CLK>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ecspi3: spi@30840000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
	reg = <0x30840000 0x10000>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
	<&clks IMX7D_ECSPI3_ROOT_CLK>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart1: serial@30860000 {
	compatible = "fsl,imx7d-uart",
	"fsl,imx6q-uart";
	reg = <0x30860000 0x10000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_UART1_ROOT_CLK>,
	<&clks IMX7D_UART1_ROOT_CLK>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart2: serial@30890000 {
	compatible = "fsl,imx7d-uart",
	"fsl,imx6q-uart";
	reg = <0x30890000 0x10000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_UART2_ROOT_CLK>,
	<&clks IMX7D_UART2_ROOT_CLK>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart3: serial@30880000 {
	compatible = "fsl,imx7d-uart",
	"fsl,imx6q-uart";
	reg = <0x30880000 0x10000>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_UART3_ROOT_CLK>,
	<&clks IMX7D_UART3_ROOT_CLK>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	sai1: sai@308a0000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
	reg = <0x308a0000 0x10000>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_SAI1_IPG_CLK>,
	<&clks IMX7D_SAI1_ROOT_CLK>,
	<&clks IMX7D_CLK_DUMMY>,
	<&clks IMX7D_CLK_DUMMY>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dma-names = "rx", "tx";
	dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
	status = "disabled";
	};

	sai2: sai@308b0000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
	reg = <0x308b0000 0x10000>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_SAI2_IPG_CLK>,
	<&clks IMX7D_SAI2_ROOT_CLK>,
	<&clks IMX7D_CLK_DUMMY>,
	<&clks IMX7D_CLK_DUMMY>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dma-names = "rx", "tx";
	dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
	status = "disabled";
	};

	sai3: sai@308c0000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
	reg = <0x308c0000 0x10000>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_SAI3_IPG_CLK>,
	<&clks IMX7D_SAI3_ROOT_CLK>,
	<&clks IMX7D_CLK_DUMMY>,
	<&clks IMX7D_CLK_DUMMY>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dma-names = "rx", "tx";
	dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
	status = "disabled";
	};
	};

	- crypto: caam@30900000 {
	+ crypto: crypto@30900000 {
	compatible = "fsl,sec-v4.0";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x30900000 0x40000>;
	ranges = <0 0x30900000 0x40000>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_CAAM_CLK>,
	<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
	clock-names = "ipg", "aclk";

	- sec_jr0: jr0@1000 {
	+ sec_jr0: jr@1000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x1000 0x1000>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	};

	- sec_jr1: jr1@2000 {
	+ sec_jr1: jr@2000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x2000 0x1000>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	};

	- sec_jr2: jr1@3000 {
	+ sec_jr2: jr@3000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x3000 0x1000>;
	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	flexcan1: can@30a00000 {
	compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
	reg = <0x30a00000 0x10000>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_CLK_DUMMY>,
	<&clks IMX7D_CAN1_ROOT_CLK>;
	clock-names = "ipg", "per";
	fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
	status = "disabled";
	};

	flexcan2: can@30a10000 {
	compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
	reg = <0x30a10000 0x10000>;
	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_CLK_DUMMY>,
	<&clks IMX7D_CAN2_ROOT_CLK>;
	clock-names = "ipg", "per";
	fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
	status = "disabled";
	};

	i2c1: i2c@30a20000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
	reg = <0x30a20000 0x10000>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
	status = "disabled";
	};

	i2c2: i2c@30a30000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
	reg = <0x30a30000 0x10000>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
	status = "disabled";
	};

	i2c3: i2c@30a40000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
	reg = <0x30a40000 0x10000>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
	status = "disabled";
	};

	i2c4: i2c@30a50000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
	reg = <0x30a50000 0x10000>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
	status = "disabled";
	};

	uart4: serial@30a60000 {
	compatible = "fsl,imx7d-uart",
	"fsl,imx6q-uart";
	reg = <0x30a60000 0x10000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_UART4_ROOT_CLK>,
	<&clks IMX7D_UART4_ROOT_CLK>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart5: serial@30a70000 {
	compatible = "fsl,imx7d-uart",
	"fsl,imx6q-uart";
	reg = <0x30a70000 0x10000>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_UART5_ROOT_CLK>,
	<&clks IMX7D_UART5_ROOT_CLK>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart6: serial@30a80000 {
	compatible = "fsl,imx7d-uart",
	"fsl,imx6q-uart";
	reg = <0x30a80000 0x10000>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_UART6_ROOT_CLK>,
	<&clks IMX7D_UART6_ROOT_CLK>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart7: serial@30a90000 {
	compatible = "fsl,imx7d-uart",
	"fsl,imx6q-uart";
	reg = <0x30a90000 0x10000>;
	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_UART7_ROOT_CLK>,
	<&clks IMX7D_UART7_ROOT_CLK>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	mu0a: mailbox@30aa0000 {
	compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
	reg = <0x30aa0000 0x10000>;
	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_MU_ROOT_CLK>;
	#mbox-cells = <2>;
	status = "disabled";
	};

	mu0b: mailbox@30ab0000 {
	compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
	reg = <0x30ab0000 0x10000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_MU_ROOT_CLK>;
	#mbox-cells = <2>;
	fsl,mu-side-b;
	status = "disabled";
	};

	usbotg1: usb@30b10000 {
	compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
	reg = <0x30b10000 0x200>;
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_USB_CTRL_CLK>;
	fsl,usbphy = <&usbphynop1>;
	fsl,usbmisc = <&usbmisc1 0>;
	phy-clkgate-delay-us = <400>;
	status = "disabled";
	};

	usbh: usb@30b30000 {
	compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
	reg = <0x30b30000 0x200>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&pgc_hsic_phy>;
	clocks = <&clks IMX7D_USB_CTRL_CLK>;
	fsl,usbphy = <&usbphynop3>;
	fsl,usbmisc = <&usbmisc3 0>;
	phy_type = "hsic";
	dr_mode = "host";
	phy-clkgate-delay-us = <400>;
	status = "disabled";
	};

	usbmisc1: usbmisc@30b10200 {
	#index-cells = <1>;
	compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
	reg = <0x30b10200 0x200>;
	};

	usbmisc3: usbmisc@30b30200 {
	#index-cells = <1>;
	compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
	reg = <0x30b30200 0x200>;
	};

	usdhc1: usdhc@30b40000 {
	compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
	reg = <0x30b40000 0x10000>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_IPG_ROOT_CLK>,
	<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
	<&clks IMX7D_USDHC1_ROOT_CLK>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	usdhc2: usdhc@30b50000 {
	compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
	reg = <0x30b50000 0x10000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_IPG_ROOT_CLK>,
	<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
	<&clks IMX7D_USDHC2_ROOT_CLK>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	usdhc3: usdhc@30b60000 {
	compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
	reg = <0x30b60000 0x10000>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_IPG_ROOT_CLK>,
	<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
	<&clks IMX7D_USDHC3_ROOT_CLK>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	status = "disabled";
	};

	sdma: sdma@30bd0000 {
	compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
	reg = <0x30bd0000 0x10000>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_IPG_ROOT_CLK>,
	<&clks IMX7D_SDMA_CORE_CLK>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
	};

	fec1: ethernet@30be0000 {
	compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
	reg = <0x30be0000 0x10000>;
	interrupt-names = "int0", "int1", "int2", "pps";
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
	<&clks IMX7D_ENET_AXI_ROOT_CLK>,
	<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
	<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
	<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
	clock-names = "ipg", "ahb", "ptp",
	"enet_clk_ref", "enet_out";
	fsl,num-tx-queues = <3>;
	fsl,num-rx-queues = <3>;
	status = "disabled";
	};
	};

	dma_apbh: dma-apbh@33000000 {
	compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
	reg = <0x33000000 0x2000>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
	#dma-cells = <1>;
	dma-channels = <4>;
	clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
	};

	gpmi: gpmi-nand@33002000{
	compatible = "fsl,imx7d-gpmi-nand";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
	reg-names = "gpmi-nand", "bch";
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "bch";
	clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
	<&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
	clock-names = "gpmi_io", "gpmi_bch_apb";
	dmas = <&dma_apbh 0>;
	dma-names = "rx-tx";
	status = "disabled";
	assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/imx7ulp-evk.dts b/sys/gnu/dts/arm/imx7ulp-evk.dts
	index a863a2b337d6..eff51e113db4 100644
	--- a/sys/gnu/dts/arm/imx7ulp-evk.dts
	+++ b/sys/gnu/dts/arm/imx7ulp-evk.dts
	@@ -1,134 +1,133 @@
	// SPDX-License-Identifier: GPL-2.0+
	/*
	* Copyright 2016 Freescale Semiconductor, Inc.
	* Copyright 2017-2018 NXP
	* Dong Aisheng <aisheng.dong@nxp.com>
	*/

	/dts-v1/;

	#include "imx7ulp.dtsi"

	/ {
	model = "NXP i.MX7ULP EVK";
	compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";

	chosen {
	stdout-path = &lpuart4;
	};

	memory@60000000 {
	device_type = "memory";
	reg = <0x60000000 0x40000000>;
	};

	backlight {
	compatible = "pwm-backlight";
	pwms = <&tpm4 1 50000 0>;
	brightness-levels = <0 20 25 30 35 40 100>;
	default-brightness-level = <6>;
	status = "okay";
	};

	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1_vbus>;
	regulator-name = "usb_otg1_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_vsd_3v3: regulator-vsd-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VSD_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc0_rst>;
	gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};
	};

	&lpuart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart4>;
	status = "okay";
	};

	&tpm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm0>;
	status = "okay";
	};

	&usbotg1 {
	vbus-supply = <&reg_usb_otg1_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1_id>;
	srp-disable;
	hnp-disable;
	adp-disable;
	- over-current-active-low;
	+ disable-over-current;
	status = "okay";
	};

	&usdhc0 {
	assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
	assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc0>;
	cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_vsd_3v3>;
	status = "okay";
	};

	&iomuxc1 {
	pinctrl_lpuart4: lpuart4grp {
	fsl,pins = <
	IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
	IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
	>;
	bias-pull-up;
	};

	pinctrl_pwm0: pwm0grp {
	fsl,pins = <
	IMX7ULP_PAD_PTF2__TPM4_CH1 0x2
	>;
	};

	pinctrl_usbotg1_vbus: otg1vbusgrp {
	fsl,pins = <
	IMX7ULP_PAD_PTC0__PTC0 0x20000
	>;
	};

	pinctrl_usbotg1_id: otg1idgrp {
	fsl,pins = <
	IMX7ULP_PAD_PTC13__USB0_ID 0x10003
	- IMX7ULP_PAD_PTC16__USB1_OC2 0x10003
	>;
	};

	pinctrl_usdhc0: usdhc0grp {
	fsl,pins = <
	IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
	IMX7ULP_PAD_PTD2__SDHC0_CLK 0x40
	IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
	IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
	IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
	IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
	IMX7ULP_PAD_PTC10__PTC10 0x3 /* CD */
	>;
	};

	pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp {
	fsl,pins = <
	IMX7ULP_PAD_PTD0__PTD0 0x3
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/imx7ulp.dtsi b/sys/gnu/dts/arm/imx7ulp.dtsi
	index ab91c98f2124..f7c4878534c8 100644
	--- a/sys/gnu/dts/arm/imx7ulp.dtsi
	+++ b/sys/gnu/dts/arm/imx7ulp.dtsi
	@@ -1,461 +1,461 @@
	// SPDX-License-Identifier: GPL-2.0+
	/*
	* Copyright (C) 2016 Freescale Semiconductor, Inc.
	* Copyright 2017-2018 NXP
	* Dong Aisheng <aisheng.dong@nxp.com>
	*/

	#include <dt-bindings/clock/imx7ulp-clock.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>

	#include "imx7ulp-pinfunc.h"

	/ {
	interrupt-parent = <&intc>;

	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
	gpio0 = &gpio_ptc;
	gpio1 = &gpio_ptd;
	gpio2 = &gpio_pte;
	gpio3 = &gpio_ptf;
	i2c0 = &lpi2c6;
	i2c1 = &lpi2c7;
	mmc0 = &usdhc0;
	mmc1 = &usdhc1;
	serial0 = &lpuart4;
	serial1 = &lpuart5;
	serial2 = &lpuart6;
	serial3 = &lpuart7;
	usbphy0 = &usbphy1;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@f00 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <0xf00>;
	};
	};

	intc: interrupt-controller@40021000 {
	compatible = "arm,cortex-a7-gic";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x40021000 0x1000>,
	<0x40022000 0x1000>;
	};

	rosc: clock-rosc {
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	clock-output-names = "rosc";
	#clock-cells = <0>;
	};

	sosc: clock-sosc {
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-output-names = "sosc";
	#clock-cells = <0>;
	};

	sirc: clock-sirc {
	compatible = "fixed-clock";
	clock-frequency = <16000000>;
	clock-output-names = "sirc";
	#clock-cells = <0>;
	};

	firc: clock-firc {
	compatible = "fixed-clock";
	clock-frequency = <48000000>;
	clock-output-names = "firc";
	#clock-cells = <0>;
	};

	upll: clock-upll {
	compatible = "fixed-clock";
	clock-frequency = <480000000>;
	clock-output-names = "upll";
	#clock-cells = <0>;
	};

	ahbbridge0: bus@40000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x40000000 0x800000>;
	ranges;

	edma1: dma-controller@40080000 {
	#dma-cells = <2>;
	compatible = "fsl,imx7ulp-edma";
	reg = <0x40080000 0x2000>,
	<0x40210000 0x1000>;
	dma-channels = <32>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "dma", "dmamux0";
	clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
	<&pcc2 IMX7ULP_CLK_DMA_MUX1>;
	};

	crypto: crypto@40240000 {
	compatible = "fsl,sec-v4.0";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x40240000 0x10000>;
	ranges = <0 0x40240000 0x10000>;
	clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
	<&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
	clock-names = "aclk", "ipg";

	- sec_jr0: jr0@1000 {
	+ sec_jr0: jr@1000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x1000 0x1000>;
	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	};

	- sec_jr1: jr1@2000 {
	+ sec_jr1: jr@2000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x2000 0x1000>;
	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	lpuart4: serial@402d0000 {
	compatible = "fsl,imx7ulp-lpuart";
	reg = <0x402d0000 0x1000>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
	clock-names = "ipg";
	assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
	assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
	assigned-clock-rates = <24000000>;
	status = "disabled";
	};

	lpuart5: serial@402e0000 {
	compatible = "fsl,imx7ulp-lpuart";
	reg = <0x402e0000 0x1000>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
	clock-names = "ipg";
	assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
	assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
	assigned-clock-rates = <48000000>;
	status = "disabled";
	};

	tpm4: pwm@40250000 {
	compatible = "fsl,imx7ulp-pwm";
	reg = <0x40250000 0x1000>;
	assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
	assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
	clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	tpm5: tpm@40260000 {
	compatible = "fsl,imx7ulp-tpm";
	reg = <0x40260000 0x1000>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
	<&pcc2 IMX7ULP_CLK_LPTPM5>;
	clock-names = "ipg", "per";
	};

	usbotg1: usb@40330000 {
	compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
	reg = <0x40330000 0x200>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&pcc2 IMX7ULP_CLK_USB0>;
	phys = <&usbphy1>;
	fsl,usbmisc = <&usbmisc1 0>;
	ahb-burst-config = <0x0>;
	tx-burst-size-dword = <0x8>;
	rx-burst-size-dword = <0x8>;
	status = "disabled";
	};

	usbmisc1: usbmisc@40330200 {
	compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
	#index-cells = <1>;
	reg = <0x40330200 0x200>;
	};

	usbphy1: usb-phy@40350000 {
	compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
	reg = <0x40350000 0x1000>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;
	#phy-cells = <0>;
	};

	usdhc0: mmc@40370000 {
	compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
	reg = <0x40370000 0x10000>;
	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
	<&scg1 IMX7ULP_CLK_NIC1_DIV>,
	<&pcc2 IMX7ULP_CLK_USDHC0>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	fsl,tuning-start-tap = <20>;
	fsl,tuning-step = <2>;
	status = "disabled";
	};

	usdhc1: mmc@40380000 {
	compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
	reg = <0x40380000 0x10000>;
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
	<&scg1 IMX7ULP_CLK_NIC1_DIV>,
	<&pcc2 IMX7ULP_CLK_USDHC1>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <4>;
	fsl,tuning-start-tap = <20>;
	fsl,tuning-step = <2>;
	status = "disabled";
	};

	scg1: clock-controller@403e0000 {
	compatible = "fsl,imx7ulp-scg1";
	reg = <0x403e0000 0x10000>;
	clocks = <&rosc>, <&sosc>, <&sirc>,
	<&firc>, <&upll>;
	clock-names = "rosc", "sosc", "sirc",
	"firc", "upll";
	#clock-cells = <1>;
	};

	wdog1: watchdog@403d0000 {
	compatible = "fsl,imx7ulp-wdt";
	reg = <0x403d0000 0x10000>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
	assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
	assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
	timeout-sec = <40>;
	};

	pcc2: clock-controller@403f0000 {
	compatible = "fsl,imx7ulp-pcc2";
	reg = <0x403f0000 0x10000>;
	#clock-cells = <1>;
	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
	<&scg1 IMX7ULP_CLK_NIC1_DIV>,
	<&scg1 IMX7ULP_CLK_DDR_DIV>,
	<&scg1 IMX7ULP_CLK_APLL_PFD2>,
	<&scg1 IMX7ULP_CLK_APLL_PFD1>,
	<&scg1 IMX7ULP_CLK_APLL_PFD0>,
	<&scg1 IMX7ULP_CLK_UPLL>,
	<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
	<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
	<&scg1 IMX7ULP_CLK_ROSC>,
	<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
	clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
	"apll_pfd2", "apll_pfd1", "apll_pfd0",
	"upll", "sosc_bus_clk",
	"firc_bus_clk", "rosc", "spll_bus_clk";
	assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
	assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
	};

	smc1: clock-controller@40410000 {
	compatible = "fsl,imx7ulp-smc1";
	reg = <0x40410000 0x1000>;
	#clock-cells = <1>;
	clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
	<&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
	clock-names = "divcore", "hsrun_divcore";
	};

	pcc3: clock-controller@40b30000 {
	compatible = "fsl,imx7ulp-pcc3";
	reg = <0x40b30000 0x10000>;
	#clock-cells = <1>;
	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
	<&scg1 IMX7ULP_CLK_NIC1_DIV>,
	<&scg1 IMX7ULP_CLK_DDR_DIV>,
	<&scg1 IMX7ULP_CLK_APLL_PFD2>,
	<&scg1 IMX7ULP_CLK_APLL_PFD1>,
	<&scg1 IMX7ULP_CLK_APLL_PFD0>,
	<&scg1 IMX7ULP_CLK_UPLL>,
	<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
	<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
	<&scg1 IMX7ULP_CLK_ROSC>,
	<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
	clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
	"apll_pfd2", "apll_pfd1", "apll_pfd0",
	"upll", "sosc_bus_clk",
	"firc_bus_clk", "rosc", "spll_bus_clk";
	};
	};

	ahbbridge1: bus@40800000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x40800000 0x800000>;
	ranges;

	lpi2c6: i2c@40a40000 {
	compatible = "fsl,imx7ulp-lpi2c";
	reg = <0x40a40000 0x10000>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
	clock-names = "ipg";
	assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
	assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
	assigned-clock-rates = <48000000>;
	status = "disabled";
	};

	lpi2c7: i2c@40a50000 {
	compatible = "fsl,imx7ulp-lpi2c";
	reg = <0x40a50000 0x10000>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
	clock-names = "ipg";
	assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
	assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
	assigned-clock-rates = <48000000>;
	status = "disabled";
	};

	lpuart6: serial@40a60000 {
	compatible = "fsl,imx7ulp-lpuart";
	reg = <0x40a60000 0x1000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
	clock-names = "ipg";
	assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
	assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
	assigned-clock-rates = <48000000>;
	status = "disabled";
	};

	lpuart7: serial@40a70000 {
	compatible = "fsl,imx7ulp-lpuart";
	reg = <0x40a70000 0x1000>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
	clock-names = "ipg";
	assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
	assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
	assigned-clock-rates = <48000000>;
	status = "disabled";
	};

	memory-controller@40ab0000 {
	compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
	reg = <0x40ab0000 0x1000>;
	clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
	};

	iomuxc1: pinctrl@40ac0000 {
	compatible = "fsl,imx7ulp-iomuxc1";
	reg = <0x40ac0000 0x1000>;
	};

	gpio_ptc: gpio@40ae0000 {
	compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
	reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
	<&pcc3 IMX7ULP_CLK_PCTLC>;
	clock-names = "gpio", "port";
	gpio-ranges = <&iomuxc1 0 0 32>;
	};

	gpio_ptd: gpio@40af0000 {
	compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
	reg = <0x40af0000 0x1000 0x400f0040 0x40>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
	<&pcc3 IMX7ULP_CLK_PCTLD>;
	clock-names = "gpio", "port";
	gpio-ranges = <&iomuxc1 0 32 32>;
	};

	gpio_pte: gpio@40b00000 {
	compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
	reg = <0x40b00000 0x1000 0x400f0080 0x40>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
	<&pcc3 IMX7ULP_CLK_PCTLE>;
	clock-names = "gpio", "port";
	gpio-ranges = <&iomuxc1 0 64 32>;
	};

	gpio_ptf: gpio@40b10000 {
	compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
	reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
	<&pcc3 IMX7ULP_CLK_PCTLF>;
	clock-names = "gpio", "port";
	gpio-ranges = <&iomuxc1 0 96 32>;
	};
	};

	m4aips1: bus@41080000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x41080000 0x80000>;
	ranges;

	sim: sim@410a3000 {
	compatible = "fsl,imx7ulp-sim", "syscon";
	reg = <0x410a3000 0x1000>;
	};

	ocotp: ocotp-ctrl@410a6000 {
	compatible = "fsl,imx7ulp-ocotp", "syscon";
	reg = <0x410a6000 0x4000>;
	clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/integratorap.dts b/sys/gnu/dts/arm/integratorap.dts
	index 94d2ff9836d0..198d66181c50 100644
	--- a/sys/gnu/dts/arm/integratorap.dts
	+++ b/sys/gnu/dts/arm/integratorap.dts
	@@ -1,243 +1,242 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree for the ARM Integrator/AP platform
	*/

	/dts-v1/;
	/include/ "integrator.dtsi"

	/ {
	model = "ARM Integrator/AP";
	compatible = "arm,integrator-ap";
	- dma-ranges = <0x80000000 0x0 0x80000000>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	/*
	* Since the board has pluggable CPU modules, we
	* cannot define a proper compatible here. Let the
	* boot loader fill in the apropriate compatible
	* string if necessary.
	*/
	/* compatible = "arm,arm926ej-s"; */
	reg = <0>;
	/*
	* The documentation in ARM DUI 0138E page 3-12 states
	* that the maximum frequency for this clock is 200 MHz
	* but painful trial-and-error has proved to me that it
	* is actually just hanging the system above 71 MHz.
	* Sad but true.
	*/
	/* kHz uV */
	operating-points = <71000 0
	66000 0
	60000 0
	48000 0
	36000 0
	24000 0
	12000 0>;
	clocks = <&cmosc>;
	clock-names = "cpu";
	clock-latency = <1000000>; /* 1 ms */
	};
	};

	aliases {
	arm,timer-primary = &timer2;
	arm,timer-secondary = &timer1;
	};

	chosen {
	bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
	};

	/* 24 MHz chrystal on the Integrator/AP development board */
	xtal24mhz: xtal24mhz@24M {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	};

	pclk: pclk@0 {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clock-div = <1>;
	clock-mult = <1>;
	clocks = <&xtal24mhz>;
	};

	/* The UART clock is 14.74 MHz divided by an ICS525 */
	uartclk: uartclk@14.74M {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <14745600>;
	clocks = <&xtal24mhz>;
	};

	core-module@10000000 {
	/* 24 MHz chrystal on the core module */
	cm24mhz: cm24mhz@24M {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	};

	/* Oscillator on the core module, clocks the CPU core */
	cmosc: cmosc@24M {
	compatible = "arm,syscon-icst525-integratorap-cm";
	#clock-cells = <0>;
	lock-offset = <0x14>;
	vco-offset = <0x08>;
	clocks = <&cm24mhz>;
	};

	/* Auxilary oscillator on the core module, 32.369MHz at boot */
	auxosc: auxosc@24M {
	compatible = "arm,syscon-icst525";
	#clock-cells = <0>;
	lock-offset = <0x14>;
	vco-offset = <0x1c>;
	clocks = <&cm24mhz>;
	};
	};

	syscon {
	compatible = "arm,integrator-ap-syscon", "syscon";
	reg = <0x11000000 0x100>;
	interrupt-parent = <&pic>;
	/* These are the logical module IRQs */
	interrupts = <9>, <10>, <11>, <12>;

	/*
	* SYSCLK clocks PCIv3 bridge, system controller and the
	* logic modules.
	*/
	sysclk: apsys@24M {
	compatible = "arm,syscon-icst525-integratorap-sys";
	#clock-cells = <0>;
	lock-offset = <0x1c>;
	vco-offset = <0x04>;
	clocks = <&xtal24mhz>;
	};

	/* One-bit control for the PCI bus clock (33 or 25 MHz) */
	pciclk: pciclk@24M {
	compatible = "arm,syscon-icst525-integratorap-pci";
	#clock-cells = <0>;
	lock-offset = <0x1c>;
	vco-offset = <0x04>;
	clocks = <&xtal24mhz>;
	};
	};

	timer0: timer@13000000 {
	compatible = "arm,integrator-timer";
	clocks = <&xtal24mhz>;
	};

	timer1: timer@13000100 {
	compatible = "arm,integrator-timer";
	clocks = <&xtal24mhz>;
	};

	timer2: timer@13000200 {
	compatible = "arm,integrator-timer";
	clocks = <&xtal24mhz>;
	};

	pic: pic@14000000 {
	valid-mask = <0x003fffff>;
	};

	pci: pciv3@62000000 {
	compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
	#interrupt-cells = <1>;
	#size-cells = <2>;
	#address-cells = <3>;
	/* Bridge registers and config access space */
	reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
	interrupt-parent = <&pic>;
	interrupts = <17>; /* Bus error IRQ */
	clocks = <&pciclk>;
	bus-range = <0x00 0xff>;
	ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */
	0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */
	0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
	0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
	0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
	0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
	dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
	0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
	0x02000000 0 0x80000000 /* Core module alias memory */
	0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
	interrupt-map-mask = <0xf800 0 0 0x7>;
	interrupt-map = <
	/* IDSEL 9 */
	0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
	0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
	0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
	0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
	/* IDSEL 10 */
	0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
	0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
	0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
	0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
	/* IDSEL 11 */
	0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
	0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
	0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
	0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
	/* IDSEL 12 */
	0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
	0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
	0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
	0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
	>;
	};

	fpga {
	/*
	* The Integator/AP predates the idea to have magic numbers
	* identifying the PrimeCell in hardware, thus we have to
	* supply these from the device tree.
	*/
	rtc: rtc@15000000 {
	compatible = "arm,pl030", "arm,primecell";
	arm,primecell-periphid = <0x00041030>;
	clocks = <&pclk>;
	clock-names = "apb_pclk";
	};

	uart0: uart@16000000 {
	compatible = "arm,pl010", "arm,primecell";
	arm,primecell-periphid = <0x00041010>;
	clocks = <&uartclk>, <&pclk>;
	clock-names = "uartclk", "apb_pclk";
	};

	uart1: uart@17000000 {
	compatible = "arm,pl010", "arm,primecell";
	arm,primecell-periphid = <0x00041010>;
	clocks = <&uartclk>, <&pclk>;
	clock-names = "uartclk", "apb_pclk";
	};

	kmi0: kmi@18000000 {
	compatible = "arm,pl050", "arm,primecell";
	arm,primecell-periphid = <0x00041050>;
	clocks = <&xtal24mhz>, <&pclk>;
	clock-names = "KMIREFCLK", "apb_pclk";
	};

	kmi1: kmi@19000000 {
	compatible = "arm,pl050", "arm,primecell";
	arm,primecell-periphid = <0x00041050>;
	clocks = <&xtal24mhz>, <&pclk>;
	clock-names = "KMIREFCLK", "apb_pclk";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/iwg20d-q7-dbcm-ca.dtsi b/sys/gnu/dts/arm/iwg20d-q7-dbcm-ca.dtsi
	index ede2e0c999b1..e10f99278c77 100644
	--- a/sys/gnu/dts/arm/iwg20d-q7-dbcm-ca.dtsi
	+++ b/sys/gnu/dts/arm/iwg20d-q7-dbcm-ca.dtsi
	@@ -1,126 +1,124 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the iWave-RZ-G1M/N Daughter Board Camera Module
	*
	* Copyright (C) 2017 Renesas Electronics Corp.
	*/

	/ {
	aliases {
	serial1 = &scif1;
	serial4 = &hscif1;
	};

	cec_clock: cec-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <12000000>;
	};

	hdmi-out {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con_out: endpoint {
	remote-endpoint = <&adv7511_out>;
	};
	};
	};
	};

	&can1 {
	pinctrl-0 = <&can1_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";

	ports {
	port@0 {
	endpoint {
	remote-endpoint = <&adv7511_in>;
	};
	};
	};
	};

	&hscif1 {
	pinctrl-0 = <&hscif1_pins>;
	pinctrl-names = "default";

	uart-has-rtscts;
	status = "okay";
	};

	&i2c5 {
	status = "okay";
	clock-frequency = <400000>;

	hdmi@39 {
	compatible = "adi,adv7511w";
	reg = <0x39>;
	interrupt-parent = <&gpio0>;
	interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&cec_clock>;
	clock-names = "cec";

	adi,input-depth = <8>;
	adi,input-colorspace = "rgb";
	adi,input-clock = "1x";
	- adi,input-style = <1>;
	- adi,input-justification = "evenly";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7511_in: endpoint {
	remote-endpoint = <&du_out_rgb>;
	};
	};

	port@1 {
	reg = <1>;
	adv7511_out: endpoint {
	remote-endpoint = <&hdmi_con_out>;
	};
	};
	};
	};
	};

	&pfc {
	can1_pins: can1 {
	groups = "can1_data_d";
	function = "can1";
	};

	du_pins: du {
	groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0";
	function = "du";
	};

	hscif1_pins: hscif1 {
	groups = "hscif1_data_c", "hscif1_ctrl_c";
	function = "hscif1";
	};

	scif1_pins: scif1 {
	groups = "scif1_data_d";
	function = "scif1";
	};
	};

	&scif1 {
	pinctrl-0 = <&scif1_pins>;
	pinctrl-names = "default";

	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/mmp2-brownstone.dts b/sys/gnu/dts/arm/mmp2-brownstone.dts
	index aaedc4c742ea..04f1ae1382e7 100644
	--- a/sys/gnu/dts/arm/mmp2-brownstone.dts
	+++ b/sys/gnu/dts/arm/mmp2-brownstone.dts
	@@ -1,194 +1,192 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2012 Marvell Technology Group Ltd.
	* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
	*/

	/dts-v1/;
	#include "mmp2.dtsi"

	/ {
	model = "Marvell MMP2 Brownstone Development Board";
	compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";

	chosen {
	bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
	};

	memory {
	device_type = "memory";
	reg = <0x00000000 0x08000000>;
	};
	+};
	+
	+&uart3 {
	+ status = "okay";
	+};

	- soc {
	- apb@d4000000 {
	- uart3: uart@d4018000 {
	- status = "okay";
	- };
	- twsi1: i2c@d4011000 {
	- status = "okay";
	- pmic: max8925@3c {
	- compatible = "maxium,max8925";
	- reg = <0x3c>;
	- interrupts = <1>;
	- interrupt-parent = <&intcmux4>;
	- interrupt-controller;
	- #interrupt-cells = <1>;
	- maxim,tsc-irq = <0>;
	+&twsi1 {
	+ status = "okay";
	+ pmic: max8925@3c {
	+ compatible = "maxium,max8925";
	+ reg = <0x3c>;
	+ interrupts = <1>;
	+ interrupt-parent = <&intcmux4>;
	+ interrupt-controller;
	+ #interrupt-cells = <1>;
	+ maxim,tsc-irq = <0>;

	- regulators {
	- SDV1 {
	- regulator-min-microvolt = <637500>;
	- regulator-max-microvolt = <1425000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- SDV2 {
	- regulator-min-microvolt = <650000>;
	- regulator-max-microvolt = <2225000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- SDV3 {
	- regulator-min-microvolt = <750000>;
	- regulator-max-microvolt = <3900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO1 {
	- regulator-min-microvolt = <750000>;
	- regulator-max-microvolt = <3900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO2 {
	- regulator-min-microvolt = <650000>;
	- regulator-max-microvolt = <2250000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO3 {
	- regulator-min-microvolt = <650000>;
	- regulator-max-microvolt = <2250000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO4 {
	- regulator-min-microvolt = <750000>;
	- regulator-max-microvolt = <3900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO5 {
	- regulator-min-microvolt = <750000>;
	- regulator-max-microvolt = <3900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO6 {
	- regulator-min-microvolt = <750000>;
	- regulator-max-microvolt = <3900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO7 {
	- regulator-min-microvolt = <750000>;
	- regulator-max-microvolt = <3900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO8 {
	- regulator-min-microvolt = <750000>;
	- regulator-max-microvolt = <3900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO9 {
	- regulator-min-microvolt = <750000>;
	- regulator-max-microvolt = <3900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO10 {
	- regulator-min-microvolt = <750000>;
	- regulator-max-microvolt = <3900000>;
	- };
	- LDO11 {
	- regulator-min-microvolt = <750000>;
	- regulator-max-microvolt = <3900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO12 {
	- regulator-min-microvolt = <750000>;
	- regulator-max-microvolt = <3900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO13 {
	- regulator-min-microvolt = <750000>;
	- regulator-max-microvolt = <3900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO14 {
	- regulator-min-microvolt = <750000>;
	- regulator-max-microvolt = <3900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO15 {
	- regulator-min-microvolt = <750000>;
	- regulator-max-microvolt = <3900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO16 {
	- regulator-min-microvolt = <750000>;
	- regulator-max-microvolt = <3900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO17 {
	- regulator-min-microvolt = <650000>;
	- regulator-max-microvolt = <2250000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO18 {
	- regulator-min-microvolt = <650000>;
	- regulator-max-microvolt = <2250000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO19 {
	- regulator-min-microvolt = <750000>;
	- regulator-max-microvolt = <3900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO20 {
	- regulator-min-microvolt = <750000>;
	- regulator-max-microvolt = <3900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- };
	- backlight {
	- maxim,max8925-dual-string = <0>;
	- };
	- charger {
	- batt-detect = <0>;
	- topoff-threshold = <1>;
	- fast-charge = <7>;
	- no-temp-support = <0>;
	- no-insert-detect = <0>;
	- };
	- };
	- };
	- rtc: rtc@d4010000 {
	- status = "okay";
	+ regulators {
	+ SDV1 {
	+ regulator-min-microvolt = <637500>;
	+ regulator-max-microvolt = <1425000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ SDV2 {
	+ regulator-min-microvolt = <650000>;
	+ regulator-max-microvolt = <2225000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ SDV3 {
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <3900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO1 {
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <3900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO2 {
	+ regulator-min-microvolt = <650000>;
	+ regulator-max-microvolt = <2250000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO3 {
	+ regulator-min-microvolt = <650000>;
	+ regulator-max-microvolt = <2250000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO4 {
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <3900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO5 {
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <3900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO6 {
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <3900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO7 {
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <3900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO8 {
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <3900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO9 {
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <3900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO10 {
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <3900000>;
	};
	+ LDO11 {
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <3900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO12 {
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <3900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO13 {
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <3900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO14 {
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <3900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO15 {
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <3900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO16 {
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <3900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO17 {
	+ regulator-min-microvolt = <650000>;
	+ regulator-max-microvolt = <2250000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO18 {
	+ regulator-min-microvolt = <650000>;
	+ regulator-max-microvolt = <2250000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO19 {
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <3900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO20 {
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <3900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ };
	+ backlight {
	+ maxim,max8925-dual-string = <0>;
	+ };
	+ charger {
	+ batt-detect = <0>;
	+ topoff-threshold = <1>;
	+ fast-charge = <7>;
	+ no-temp-support = <0>;
	+ no-insert-detect = <0>;
	};
	};
	};
	+
	+&rtc {
	+ status = "okay";
	+};
	diff --git a/sys/gnu/dts/arm/mmp2.dtsi b/sys/gnu/dts/arm/mmp2.dtsi
	index 6a2f072c1d0a..da10567b5aca 100644
	--- a/sys/gnu/dts/arm/mmp2.dtsi
	+++ b/sys/gnu/dts/arm/mmp2.dtsi
	@@ -1,426 +1,426 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2012 Marvell Technology Group Ltd.
	* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
	*/

	#include <dt-bindings/clock/marvell,mmp2.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	i2c0 = &twsi1;
	i2c1 = &twsi2;
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&intc>;
	ranges;

	L2: l2-cache {
	compatible = "marvell,tauros2-cache";
	marvell,tauros2-cache-features = <0x3>;
	};

	axi@d4200000 { /* AXI */
	compatible = "mrvl,axi-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0xd4200000 0x00200000>;
	ranges;

	intc: interrupt-controller@d4282000 {
	compatible = "mrvl,mmp2-intc";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0xd4282000 0x1000>;
	mrvl,intc-nr-irqs = <64>;
	};

	intcmux4: interrupt-controller@d4282150 {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <4>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x150 0x4>, <0x168 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <2>;
	};

	intcmux5: interrupt-controller@d4282154 {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <5>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x154 0x4>, <0x16c 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <2>;
	mrvl,clr-mfp-irq = <1>;
	};

	intcmux9: interrupt-controller@d4282180 {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <9>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x180 0x4>, <0x17c 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <3>;
	};

	intcmux17: interrupt-controller@d4282158 {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <17>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x158 0x4>, <0x170 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <5>;
	};

	intcmux35: interrupt-controller@d428215c {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <35>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x15c 0x4>, <0x174 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <15>;
	};

	intcmux51: interrupt-controller@d4282160 {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <51>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x160 0x4>, <0x178 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <2>;
	};

	intcmux55: interrupt-controller@d4282188 {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <55>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x188 0x4>, <0x184 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <2>;
	};

	usb_phy0: usb-phy@d4207000 {
	compatible = "marvell,mmp2-usb-phy";
	reg = <0xd4207000 0x40>;
	#phy-cells = <0>;
	status = "disabled";
	};

	usb_otg0: usb-otg@d4208000 {
	compatible = "marvell,pxau2o-ehci";
	reg = <0xd4208000 0x200>;
	interrupts = <44>;
	clocks = <&soc_clocks MMP2_CLK_USB>;
	clock-names = "USBCLK";
	phys = <&usb_phy0>;
	phy-names = "usb";
	status = "disabled";
	};

	mmc1: mmc@d4280000 {
	compatible = "mrvl,pxav3-mmc";
	reg = <0xd4280000 0x120>;
	clocks = <&soc_clocks MMP2_CLK_SDH0>;
	clock-names = "io";
	interrupts = <39>;
	status = "disabled";
	};

	mmc2: mmc@d4280800 {
	compatible = "mrvl,pxav3-mmc";
	reg = <0xd4280800 0x120>;
	clocks = <&soc_clocks MMP2_CLK_SDH1>;
	clock-names = "io";
	interrupts = <52>;
	status = "disabled";
	};

	mmc3: mmc@d4281000 {
	compatible = "mrvl,pxav3-mmc";
	reg = <0xd4281000 0x120>;
	clocks = <&soc_clocks MMP2_CLK_SDH2>;
	clock-names = "io";
	interrupts = <53>;
	status = "disabled";
	};

	mmc4: mmc@d4281800 {
	compatible = "mrvl,pxav3-mmc";
	reg = <0xd4281800 0x120>;
	clocks = <&soc_clocks MMP2_CLK_SDH3>;
	clock-names = "io";
	interrupts = <54>;
	status = "disabled";
	};

	camera0: camera@d420a000 {
	compatible = "marvell,mmp2-ccic";
	reg = <0xd420a000 0x800>;
	interrupts = <42>;
	clocks = <&soc_clocks MMP2_CLK_CCIC0>;
	clock-names = "axi";
	#clock-cells = <0>;
	clock-output-names = "mclk";
	status = "disabled";
	};

	camera1: camera@d420a800 {
	compatible = "marvell,mmp2-ccic";
	reg = <0xd420a800 0x800>;
	interrupts = <30>;
	clocks = <&soc_clocks MMP2_CLK_CCIC1>;
	clock-names = "axi";
	#clock-cells = <0>;
	clock-output-names = "mclk";
	status = "disabled";
	};
	};

	apb@d4000000 { /* APB */
	compatible = "mrvl,apb-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0xd4000000 0x00200000>;
	ranges;

	timer0: timer@d4014000 {
	compatible = "mrvl,mmp-timer";
	reg = <0xd4014000 0x100>;
	interrupts = <13>;
	clocks = <&soc_clocks MMP2_CLK_TIMER>;
	};

	- uart1: uart@d4030000 {
	- compatible = "mrvl,mmp-uart";
	+ uart1: serial@d4030000 {
	+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
	reg = <0xd4030000 0x1000>;
	interrupts = <27>;
	clocks = <&soc_clocks MMP2_CLK_UART0>;
	resets = <&soc_clocks MMP2_CLK_UART0>;
	reg-shift = <2>;
	status = "disabled";
	};

	- uart2: uart@d4017000 {
	- compatible = "mrvl,mmp-uart";
	+ uart2: serial@d4017000 {
	+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
	reg = <0xd4017000 0x1000>;
	interrupts = <28>;
	clocks = <&soc_clocks MMP2_CLK_UART1>;
	resets = <&soc_clocks MMP2_CLK_UART1>;
	reg-shift = <2>;
	status = "disabled";
	};

	- uart3: uart@d4018000 {
	- compatible = "mrvl,mmp-uart";
	+ uart3: serial@d4018000 {
	+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
	reg = <0xd4018000 0x1000>;
	interrupts = <24>;
	clocks = <&soc_clocks MMP2_CLK_UART2>;
	resets = <&soc_clocks MMP2_CLK_UART2>;
	reg-shift = <2>;
	status = "disabled";
	};

	- uart4: uart@d4016000 {
	- compatible = "mrvl,mmp-uart";
	+ uart4: serial@d4016000 {
	+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
	reg = <0xd4016000 0x1000>;
	interrupts = <46>;
	clocks = <&soc_clocks MMP2_CLK_UART3>;
	resets = <&soc_clocks MMP2_CLK_UART3>;
	reg-shift = <2>;
	status = "disabled";
	};

	gpio: gpio@d4019000 {
	compatible = "marvell,mmp2-gpio";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0xd4019000 0x1000>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupts = <49>;
	interrupt-names = "gpio_mux";
	clocks = <&soc_clocks MMP2_CLK_GPIO>;
	resets = <&soc_clocks MMP2_CLK_GPIO>;
	interrupt-controller;
	#interrupt-cells = <2>;
	ranges;

	gcb0: gpio@d4019000 {
	reg = <0xd4019000 0x4>;
	};

	gcb1: gpio@d4019004 {
	reg = <0xd4019004 0x4>;
	};

	gcb2: gpio@d4019008 {
	reg = <0xd4019008 0x4>;
	};

	gcb3: gpio@d4019100 {
	reg = <0xd4019100 0x4>;
	};

	gcb4: gpio@d4019104 {
	reg = <0xd4019104 0x4>;
	};

	gcb5: gpio@d4019108 {
	reg = <0xd4019108 0x4>;
	};
	};

	twsi1: i2c@d4011000 {
	compatible = "mrvl,mmp-twsi";
	reg = <0xd4011000 0x1000>;
	interrupts = <7>;
	clocks = <&soc_clocks MMP2_CLK_TWSI0>;
	resets = <&soc_clocks MMP2_CLK_TWSI0>;
	#address-cells = <1>;
	#size-cells = <0>;
	mrvl,i2c-fast-mode;
	status = "disabled";
	};

	twsi2: i2c@d4031000 {
	compatible = "mrvl,mmp-twsi";
	reg = <0xd4031000 0x1000>;
	interrupt-parent = <&intcmux17>;
	interrupts = <0>;
	clocks = <&soc_clocks MMP2_CLK_TWSI1>;
	resets = <&soc_clocks MMP2_CLK_TWSI1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	twsi3: i2c@d4032000 {
	compatible = "mrvl,mmp-twsi";
	reg = <0xd4032000 0x1000>;
	interrupt-parent = <&intcmux17>;
	interrupts = <1>;
	clocks = <&soc_clocks MMP2_CLK_TWSI2>;
	resets = <&soc_clocks MMP2_CLK_TWSI2>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	twsi4: i2c@d4033000 {
	compatible = "mrvl,mmp-twsi";
	reg = <0xd4033000 0x1000>;
	interrupt-parent = <&intcmux17>;
	interrupts = <2>;
	clocks = <&soc_clocks MMP2_CLK_TWSI3>;
	resets = <&soc_clocks MMP2_CLK_TWSI3>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};


	twsi5: i2c@d4033800 {
	compatible = "mrvl,mmp-twsi";
	reg = <0xd4033800 0x1000>;
	interrupt-parent = <&intcmux17>;
	interrupts = <3>;
	clocks = <&soc_clocks MMP2_CLK_TWSI4>;
	resets = <&soc_clocks MMP2_CLK_TWSI4>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	twsi6: i2c@d4034000 {
	compatible = "mrvl,mmp-twsi";
	reg = <0xd4034000 0x1000>;
	interrupt-parent = <&intcmux17>;
	interrupts = <4>;
	clocks = <&soc_clocks MMP2_CLK_TWSI5>;
	resets = <&soc_clocks MMP2_CLK_TWSI5>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	rtc: rtc@d4010000 {
	compatible = "mrvl,mmp-rtc";
	reg = <0xd4010000 0x1000>;
	interrupts = <1 0>;
	interrupt-names = "rtc 1Hz", "rtc alarm";
	interrupt-parent = <&intcmux5>;
	clocks = <&soc_clocks MMP2_CLK_RTC>;
	resets = <&soc_clocks MMP2_CLK_RTC>;
	status = "disabled";
	};

	ssp1: spi@d4035000 {
	compatible = "marvell,mmp2-ssp";
	reg = <0xd4035000 0x1000>;
	clocks = <&soc_clocks MMP2_CLK_SSP0>;
	interrupts = <0>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	ssp2: spi@d4036000 {
	compatible = "marvell,mmp2-ssp";
	reg = <0xd4036000 0x1000>;
	clocks = <&soc_clocks MMP2_CLK_SSP1>;
	interrupts = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	ssp3: spi@d4037000 {
	compatible = "marvell,mmp2-ssp";
	reg = <0xd4037000 0x1000>;
	clocks = <&soc_clocks MMP2_CLK_SSP2>;
	interrupts = <20>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	ssp4: spi@d4039000 {
	compatible = "marvell,mmp2-ssp";
	reg = <0xd4039000 0x1000>;
	clocks = <&soc_clocks MMP2_CLK_SSP3>;
	interrupts = <21>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};
	};

	soc_clocks: clocks {
	compatible = "marvell,mmp2-clock";
	reg = <0xd4050000 0x1000>,
	<0xd4282800 0x400>,
	<0xd4015000 0x1000>;
	reg-names = "mpmu", "apmu", "apbc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/mmp3-dell-ariel.dts b/sys/gnu/dts/arm/mmp3-dell-ariel.dts
	index 15449c72c042..b0ec14c42164 100644
	--- a/sys/gnu/dts/arm/mmp3-dell-ariel.dts
	+++ b/sys/gnu/dts/arm/mmp3-dell-ariel.dts
	@@ -1,116 +1,116 @@
	// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
	/*
	* Dell Wyse 3020 a.k.a. "Ariel" a.k.a. Tx0D (T00D, T10D)
	*
	* Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
	*/

	/dts-v1/;
	#include "mmp3.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/irq.h>

	/ {
	model = "Dell Ariel";
	compatible = "dell,wyse-ariel", "marvell,mmp3";

	aliases {
	serial2 = &uart3;
	};

	chosen {
	#address-cells = <0x1>;
	#size-cells = <0x1>;
	ranges;
	bootargs = "earlyprintk=ttyS2,115200 console=ttyS2,115200";
	};

	memory@0 {
	linux,usable-memory = <0x0 0x7f600000>;
	available = <0x7f700000 0x7ff00000 0x00000000 0x7f600000>;
	reg = <0x0 0x80000000>;
	device_type = "memory";
	};
	};

	&uart3 {
	status = "okay";
	};

	&rtc {
	status = "okay";
	};

	&usb_otg0 {
	status = "okay";
	};

	&usb_otg_phy0 {
	status = "okay";
	};

	&hsic0 {
	status = "okay";

	usb1@1 {
	compatible = "usb424,2640";
	reg = <0x01>;
	#address-cells = <0x01>;
	#size-cells = <0x00>;

	mass-storage@1 {
	compatible = "usb424,4040";
	reg = <0x01>;
	status = "disabled";
	};
	};
	};

	&hsic_phy0 {
	status = "okay";
	reset-gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
	};

	&mmc3 {
	status = "okay";
	max-frequency = <50000000>;
	status = "okay";
	bus-width = <8>;
	non-removable;
	cap-mmc-highspeed;
	};

	&twsi1 {
	status = "okay";

	rtc@68 {
	compatible = "dallas,ds1338";
	reg = <0x68>;
	status = "okay";
	};
	};

	&twsi3 {
	status = "okay";
	};

	&twsi4 {
	status = "okay";
	};

	-&ssp3 {
	+&ssp1 {
	status = "okay";
	- cs-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
	+ cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;

	firmware-flash@0 {
	- compatible = "st,m25p80", "jedec,spi-nor";
	+ compatible = "winbond,w25q32", "jedec,spi-nor";
	reg = <0>;
	- spi-max-frequency = <40000000>;
	+ spi-max-frequency = <104000000>;
	m25p,fast-read;
	};
	};

	-&ssp4 {
	- cs-gpios = <&gpio 56 GPIO_ACTIVE_HIGH>;
	+&ssp2 {
	+ cs-gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/mmp3.dtsi b/sys/gnu/dts/arm/mmp3.dtsi
	index 59a108e49b41..826f0a577859 100644
	--- a/sys/gnu/dts/arm/mmp3.dtsi
	+++ b/sys/gnu/dts/arm/mmp3.dtsi
	@@ -1,571 +1,569 @@
	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	* Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
	*/

	#include <dt-bindings/clock/marvell,mmp2.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "marvell,mmp3-smp";

	cpu@0 {
	compatible = "marvell,pj4b";
	device_type = "cpu";
	next-level-cache = <&l2>;
	reg = <0>;
	};

	cpu@1 {
	compatible = "marvell,pj4b";
	device_type = "cpu";
	next-level-cache = <&l2>;
	reg = <1>;
	};
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&gic>;
	ranges;

	axi@d4200000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0xd4200000 0x00200000>;
	ranges;

	interrupt-controller@d4282000 {
	compatible = "marvell,mmp3-intc";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0xd4282000 0x1000>,
	<0xd4284000 0x100>;
	mrvl,intc-nr-irqs = <64>;
	};

	pmic_mux: interrupt-controller@d4282150 {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x150 0x4>, <0x168 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <4>;
	};

	rtc_mux: interrupt-controller@d4282154 {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x154 0x4>, <0x16c 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <2>;
	};

	hsi3_mux: interrupt-controller@d42821bc {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x1bc 0x4>, <0x1a4 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <3>;
	};

	gpu_mux: interrupt-controller@d42821c0 {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x1c0 0x4>, <0x1a8 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <3>;
	};

	twsi_mux: interrupt-controller@d4282158 {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x158 0x4>, <0x170 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <5>;
	};

	hsi2_mux: interrupt-controller@d42821c4 {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x1c4 0x4>, <0x1ac 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <2>;
	};

	dxo_mux: interrupt-controller@d42821c8 {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x1c8 0x4>, <0x1b0 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <2>;
	};

	misc1_mux: interrupt-controller@d428215c {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x15c 0x4>, <0x174 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <31>;
	};

	ci_mux: interrupt-controller@d42821cc {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x1cc 0x4>, <0x1b4 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <2>;
	};

	ssp_mux: interrupt-controller@d4282160 {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x160 0x4>, <0x178 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <2>;
	};

	hsi1_mux: interrupt-controller@d4282184 {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x184 0x4>, <0x17c 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <4>;
	};

	misc2_mux: interrupt-controller@d4282188 {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x188 0x4>, <0x180 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <20>;
	};

	hsi0_mux: interrupt-controller@d42821d0 {
	compatible = "mrvl,mmp2-mux-intc";
	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x1d0 0x4>, <0x1b8 0x4>;
	reg-names = "mux status", "mux mask";
	mrvl,intc-nr-irqs = <5>;
	};

	usb_otg_phy0: usb-otg-phy@d4207000 {
	compatible = "marvell,mmp3-usb-phy";
	reg = <0xd4207000 0x40>;
	#phy-cells = <0>;
	status = "disabled";
	};

	usb_otg0: usb-otg@d4208000 {
	compatible = "marvell,pxau2o-ehci";
	reg = <0xd4208000 0x200>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&soc_clocks MMP2_CLK_USB>;
	clock-names = "USBCLK";
	phys = <&usb_otg_phy0>;
	phy-names = "usb";
	status = "disabled";
	};

	hsic_phy0: hsic-phy@f0001800 {
	- compatible = "marvell,mmp3-hsic-phy",
	- "usb-nop-xceiv";
	+ compatible = "marvell,mmp3-hsic-phy";
	reg = <0xf0001800 0x40>;
	#phy-cells = <0>;
	status = "disabled";
	};

	hsic0: hsic@f0001000 {
	compatible = "marvell,pxau2o-ehci";
	reg = <0xf0001000 0x200>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&soc_clocks MMP2_CLK_USBHSIC0>;
	clock-names = "USBCLK";
	phys = <&hsic_phy0>;
	phy-names = "usb";
	phy_type = "hsic";
	#address-cells = <0x01>;
	#size-cells = <0x00>;
	status = "disabled";
	};

	hsic_phy1: hsic-phy@f0002800 {
	- compatible = "marvell,mmp3-hsic-phy",
	- "usb-nop-xceiv";
	+ compatible = "marvell,mmp3-hsic-phy";
	reg = <0xf0002800 0x40>;
	#phy-cells = <0>;
	status = "disabled";
	};

	hsic1: hsic@f0002000 {
	compatible = "marvell,pxau2o-ehci";
	reg = <0xf0002000 0x200>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&soc_clocks MMP2_CLK_USBHSIC1>;
	clock-names = "USBCLK";
	phys = <&hsic_phy1>;
	phy-names = "usb";
	phy_type = "hsic";
	#address-cells = <0x01>;
	#size-cells = <0x00>;
	status = "disabled";
	};

	mmc1: mmc@d4280000 {
	compatible = "mrvl,pxav3-mmc";
	reg = <0xd4280000 0x120>;
	clocks = <&soc_clocks MMP2_CLK_SDH0>;
	clock-names = "io";
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	mmc2: mmc@d4280800 {
	compatible = "mrvl,pxav3-mmc";
	reg = <0xd4280800 0x120>;
	clocks = <&soc_clocks MMP2_CLK_SDH1>;
	clock-names = "io";
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	mmc3: mmc@d4281000 {
	compatible = "mrvl,pxav3-mmc";
	reg = <0xd4281000 0x120>;
	clocks = <&soc_clocks MMP2_CLK_SDH2>;
	clock-names = "io";
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	mmc4: mmc@d4281800 {
	compatible = "mrvl,pxav3-mmc";
	reg = <0xd4281800 0x120>;
	clocks = <&soc_clocks MMP2_CLK_SDH3>;
	clock-names = "io";
	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	camera0: camera@d420a000 {
	compatible = "marvell,mmp2-ccic";
	reg = <0xd420a000 0x800>;
	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&soc_clocks MMP2_CLK_CCIC0>;
	clock-names = "axi";
	#clock-cells = <0>;
	clock-output-names = "mclk";
	status = "disabled";
	};

	camera1: camera@d420a800 {
	compatible = "marvell,mmp2-ccic";
	reg = <0xd420a800 0x800>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&soc_clocks MMP2_CLK_CCIC1>;
	clock-names = "axi";
	#clock-cells = <0>;
	clock-output-names = "mclk";
	status = "disabled";
	};
	};

	apb@d4000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0xd4000000 0x00200000>;
	ranges;

	timer: timer@d4014000 {
	compatible = "mrvl,mmp-timer";
	reg = <0xd4014000 0x100>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&soc_clocks MMP2_CLK_TIMER>;
	};

	- uart1: uart@d4030000 {
	- compatible = "mrvl,mmp-uart";
	+ uart1: serial@d4030000 {
	+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
	reg = <0xd4030000 0x1000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&soc_clocks MMP2_CLK_UART0>;
	resets = <&soc_clocks MMP2_CLK_UART0>;
	reg-shift = <2>;
	status = "disabled";
	};

	- uart2: uart@d4017000 {
	- compatible = "mrvl,mmp-uart";
	+ uart2: serial@d4017000 {
	+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
	reg = <0xd4017000 0x1000>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&soc_clocks MMP2_CLK_UART1>;
	resets = <&soc_clocks MMP2_CLK_UART1>;
	reg-shift = <2>;
	status = "disabled";
	};

	- uart3: uart@d4018000 {
	- compatible = "mrvl,mmp-uart";
	+ uart3: serial@d4018000 {
	+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
	reg = <0xd4018000 0x1000>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&soc_clocks MMP2_CLK_UART2>;
	resets = <&soc_clocks MMP2_CLK_UART2>;
	reg-shift = <2>;
	status = "disabled";
	};

	- uart4: uart@d4016000 {
	- compatible = "mrvl,mmp-uart";
	+ uart4: serial@d4016000 {
	+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
	reg = <0xd4016000 0x1000>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&soc_clocks MMP2_CLK_UART3>;
	resets = <&soc_clocks MMP2_CLK_UART3>;
	reg-shift = <2>;
	status = "disabled";
	};

	gpio: gpio@d4019000 {
	compatible = "marvell,mmp2-gpio";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0xd4019000 0x1000>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gpio_mux";
	clocks = <&soc_clocks MMP2_CLK_GPIO>;
	resets = <&soc_clocks MMP2_CLK_GPIO>;
	interrupt-controller;
	#interrupt-cells = <2>;
	ranges;

	gcb0: gpio@d4019000 {
	reg = <0xd4019000 0x4>;
	};

	gcb1: gpio@d4019004 {
	reg = <0xd4019004 0x4>;
	};

	gcb2: gpio@d4019008 {
	reg = <0xd4019008 0x4>;
	};

	gcb3: gpio@d4019100 {
	reg = <0xd4019100 0x4>;
	};

	gcb4: gpio@d4019104 {
	reg = <0xd4019104 0x4>;
	};

	gcb5: gpio@d4019108 {
	reg = <0xd4019108 0x4>;
	};
	};

	twsi1: i2c@d4011000 {
	compatible = "mrvl,mmp-twsi";
	reg = <0xd4011000 0x70>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&soc_clocks MMP2_CLK_TWSI0>;
	resets = <&soc_clocks MMP2_CLK_TWSI0>;
	#address-cells = <1>;
	#size-cells = <0>;
	mrvl,i2c-fast-mode;
	status = "disabled";
	};

	twsi2: i2c@d4031000 {
	compatible = "mrvl,mmp-twsi";
	reg = <0xd4031000 0x70>;
	interrupt-parent = <&twsi_mux>;
	interrupts = <0>;
	clocks = <&soc_clocks MMP2_CLK_TWSI1>;
	resets = <&soc_clocks MMP2_CLK_TWSI1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	twsi3: i2c@d4032000 {
	compatible = "mrvl,mmp-twsi";
	reg = <0xd4032000 0x70>;
	interrupt-parent = <&twsi_mux>;
	interrupts = <1>;
	clocks = <&soc_clocks MMP2_CLK_TWSI2>;
	resets = <&soc_clocks MMP2_CLK_TWSI2>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	twsi4: i2c@d4033000 {
	compatible = "mrvl,mmp-twsi";
	reg = <0xd4033000 0x70>;
	interrupt-parent = <&twsi_mux>;
	interrupts = <2>;
	clocks = <&soc_clocks MMP2_CLK_TWSI3>;
	resets = <&soc_clocks MMP2_CLK_TWSI3>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};


	twsi5: i2c@d4033800 {
	compatible = "mrvl,mmp-twsi";
	reg = <0xd4033800 0x70>;
	interrupt-parent = <&twsi_mux>;
	interrupts = <3>;
	clocks = <&soc_clocks MMP2_CLK_TWSI4>;
	resets = <&soc_clocks MMP2_CLK_TWSI4>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	twsi6: i2c@d4034000 {
	compatible = "mrvl,mmp-twsi";
	reg = <0xd4034000 0x70>;
	interrupt-parent = <&twsi_mux>;
	interrupts = <4>;
	clocks = <&soc_clocks MMP2_CLK_TWSI5>;
	resets = <&soc_clocks MMP2_CLK_TWSI5>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	rtc: rtc@d4010000 {
	compatible = "mrvl,mmp-rtc";
	reg = <0xd4010000 0x1000>;
	interrupts = <1 0>;
	interrupt-names = "rtc 1Hz", "rtc alarm";
	interrupt-parent = <&rtc_mux>;
	clocks = <&soc_clocks MMP2_CLK_RTC>;
	resets = <&soc_clocks MMP2_CLK_RTC>;
	status = "disabled";
	};

	ssp1: spi@d4035000 {
	compatible = "marvell,mmp2-ssp";
	reg = <0xd4035000 0x1000>;
	clocks = <&soc_clocks MMP2_CLK_SSP0>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	ssp2: spi@d4036000 {
	compatible = "marvell,mmp2-ssp";
	reg = <0xd4036000 0x1000>;
	clocks = <&soc_clocks MMP2_CLK_SSP1>;
	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	ssp3: spi@d4037000 {
	compatible = "marvell,mmp2-ssp";
	reg = <0xd4037000 0x1000>;
	clocks = <&soc_clocks MMP2_CLK_SSP2>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	ssp4: spi@d4039000 {
	compatible = "marvell,mmp2-ssp";
	reg = <0xd4039000 0x1000>;
	clocks = <&soc_clocks MMP2_CLK_SSP3>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};
	};

	l2: l2-cache-controller@d0020000 {
	compatible = "marvell,tauros3-cache", "arm,pl310-cache";
	reg = <0xd0020000 0x1000>;
	cache-unified;
	cache-level = <2>;
	};

	soc_clocks: clocks@d4050000 {
	- compatible = "marvell,mmp2-clock";
	+ compatible = "marvell,mmp3-clock";
	reg = <0xd4050000 0x1000>,
	<0xd4282800 0x400>,
	<0xd4015000 0x1000>;
	reg-names = "mpmu", "apmu", "apbc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;
	};

	snoop-control-unit@e0000000 {
	compatible = "arm,arm11mp-scu";
	reg = <0xe0000000 0x100>;
	};

	gic: interrupt-controller@e0001000 {
	compatible = "arm,arm11mp-gic";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0xe0001000 0x1000>,
	<0xe0000100 0x100>;
	};

	local-timer@e0000600 {
	compatible = "arm,arm11mp-twd-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_EDGE_RISING)>;
	reg = <0xe0000600 0x20>;
	};

	watchdog@e0000620 {
	compatible = "arm,arm11mp-twd-wdt";
	reg = <0xe0000620 0x20>;
	interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_EDGE_RISING)>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/motorola-mapphone-common.dtsi b/sys/gnu/dts/arm/motorola-mapphone-common.dtsi
	index 9067e0ef4240..06fbffa81636 100644
	--- a/sys/gnu/dts/arm/motorola-mapphone-common.dtsi
	+++ b/sys/gnu/dts/arm/motorola-mapphone-common.dtsi
	@@ -1,814 +1,851 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/dts-v1/;

	#include <dt-bindings/input/input.h>
	#include "omap443x.dtsi"
	#include "motorola-cpcap-mapphone.dtsi"

	/ {
	chosen {
	stdout-path = &uart3;
	};

	aliases {
	display0 = &lcd0;
	display1 = &hdmi0;
	};

	/*
	* We seem to have only 1021 MB accessible, 1021 - 1022 is locked,
	* then 1023 - 1024 seems to contain mbm.
	*/
	memory {
	device_type = "memory";
	reg = <0x80000000 0x3fd00000>; /* 1021 MB */
	};

	/* Poweroff GPIO probably connected to CPCAP */
	gpio-poweroff {
	compatible = "gpio-poweroff";
	pinctrl-0 = <&poweroff_gpio>;
	pinctrl-names = "default";
	gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; /* gpio50 */
	};

	hdmi0: connector {
	compatible = "hdmi-connector";
	pinctrl-0 = <&hdmi_hpd_gpio>;
	pinctrl-names = "default";
	label = "hdmi";
	type = "d";

	hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio63 */

	port {
	hdmi_connector_in: endpoint {
	remote-endpoint = <&hdmi_out>;
	};
	};
	};

	/*
	* HDMI 5V regulator probably sourced from battery. Let's keep
	* keep this as always enabled for HDMI to work until we've
	* figured what the encoder chip is.
	*/
	hdmi_regulator: regulator-hdmi {
	compatible = "regulator-fixed";
	regulator-name = "hdmi";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio59 */
	enable-active-high;
	regulator-always-on;
	};

	/* FS USB Host PHY on port 1 for mdm6600 */
	fsusb1_phy: usb-phy@1 {
	compatible = "motorola,mapphone-mdm6600";
	pinctrl-0 = <&usb_mdm6600_pins>;
	pinctrl-names = "default";
	enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; /* gpio_95 */
	power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54 */
	reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; /* gpio_49 */
	/* mode: gpio_148 gpio_149 */
	motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
	<&gpio5 21 GPIO_ACTIVE_HIGH>;
	/* cmd: gpio_103 gpio_104 gpio_142 */
	motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
	<&gpio4 8 GPIO_ACTIVE_HIGH>,
	<&gpio5 14 GPIO_ACTIVE_HIGH>;
	/* status: gpio_52 gpio_53 gpio_55 */
	motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
	<&gpio2 21 GPIO_ACTIVE_HIGH>,
	<&gpio2 23 GPIO_ACTIVE_HIGH>;
	#phy-cells = <0>;
	};

	/* HS USB host TLL nop-phy on port 2 for w3glte */
	hsusb2_phy: usb-phy@2 {
	compatible = "usb-nop-xceiv";
	#phy-cells = <0>;
	};

	/* LCD regulator from sw5 source */
	lcd_regulator: regulator-lcd {
	compatible = "regulator-fixed";
	regulator-name = "lcd";
	regulator-min-microvolt = <5050000>;
	regulator-max-microvolt = <5050000>;
	gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; /* gpio96 */
	enable-active-high;
	vin-supply = <&sw5>;
	};

	/* This is probably coming straight from the battery.. */
	wl12xx_vmmc: regulator-wl12xx {
	compatible = "regulator-fixed";
	regulator-name = "vwl1271";
	regulator-min-microvolt = <1650000>;
	regulator-max-microvolt = <1650000>;
	gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; /* gpio94 */
	startup-delay-us = <70000>;
	enable-active-high;
	};

	gpio_keys {
	compatible = "gpio-keys";

	volume_down {
	label = "Volume Down";
	gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */
	linux,code = <KEY_VOLUMEDOWN>;
	linux,can-disable;
	/* Value above 7.95ms for no GPIO hardware debounce */
	debounce-interval = <10>;
	};

	slider {
	label = "Keypad Slide";
	gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio122 */
	linux,input-type = <EV_SW>;
	linux,code = <SW_KEYPAD_SLIDE>;
	linux,can-disable;
	/* Value above 7.95ms for no GPIO hardware debounce */
	debounce-interval = <10>;
	};
	};

	soundcard {
	compatible = "audio-graph-card";
	label = "Droid 4 Audio";

	simple-graph-card,widgets =
	"Speaker", "Earpiece",
	"Speaker", "Loudspeaker",
	"Headphone", "Headphone Jack",
	"Microphone", "Internal Mic";

	simple-graph-card,routing =
	"Earpiece", "EP",
	"Loudspeaker", "SPKR",
	"Headphone Jack", "HSL",
	"Headphone Jack", "HSR",
	"MICR", "Internal Mic";

	dais = <&mcbsp2_port>, <&mcbsp3_port>;
	};

	pwm8: dmtimer-pwm-8 {
	pinctrl-names = "default";
	pinctrl-0 = <&vibrator_direction_pin>;

	compatible = "ti,omap-dmtimer-pwm";
	#pwm-cells = <3>;
	ti,timers = <&timer8>;
	ti,clock-source = <0x01>;
	};

	pwm9: dmtimer-pwm-9 {
	pinctrl-names = "default";
	pinctrl-0 = <&vibrator_enable_pin>;

	compatible = "ti,omap-dmtimer-pwm";
	#pwm-cells = <3>;
	ti,timers = <&timer9>;
	ti,clock-source = <0x01>;
	};

	vibrator {
	compatible = "pwm-vibrator";
	pwms = <&pwm9 0 10000000 0>, <&pwm8 0 10000000 0>;
	pwm-names = "enable", "direction";
	direction-duty-cycle-ns = <10000000>;
	};

	backlight: backlight {
	compatible = "led-backlight";

	leds = <&backlight_led>;
	brightness-levels = <31 63 95 127 159 191 223 255>;
	default-brightness-level = <6>;
	};
	};

	&dss {
	status = "okay";
	};

	&dsi1 {
	status = "okay";
	vdd-supply = <&vcsi>;

	port {
	dsi1_out_ep: endpoint {
	remote-endpoint = <&lcd0_in>;
	lanes = <0 1 2 3 4 5>;
	};
	};

	lcd0: display {
	compatible = "panel-dsi-cm";
	label = "lcd0";
	vddi-supply = <&lcd_regulator>;
	reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */

	backlight = <&backlight>;

	width-mm = <50>;
	height-mm = <89>;

	panel-timing {
	clock-frequency = <0>; /* Calculated by dsi */

	hback-porch = <2>;
	hactive = <540>;
	hfront-porch = <0>;
	hsync-len = <2>;

	vback-porch = <1>;
	vactive = <960>;
	vfront-porch = <0>;
	vsync-len = <1>;

	hsync-active = <0>;
	vsync-active = <0>;
	de-active = <1>;
	pixelclk-active = <1>;
	};

	port {
	lcd0_in: endpoint {
	remote-endpoint = <&dsi1_out_ep>;
	};
	};
	};
	};

	&hdmi {
	status = "okay";
	pinctrl-0 = <&dss_hdmi_pins>;
	pinctrl-names = "default";
	vdda-supply = <&vdac>;

	port {
	hdmi_out: endpoint {
	remote-endpoint = <&hdmi_connector_in>;
	lanes = <1 0 3 2 5 4 7 6>;
	};
	};
	};

	/* Battery NVRAM on 1-wire handled by w1_ds250x driver */
	&hdqw1w {
	pinctrl-0 = <&hdq_pins>;
	pinctrl-names = "default";
	ti,mode = "1w";
	};

	&i2c1 {
	tmp105@48 {
	compatible = "ti,tmp105";
	reg = <0x48>;
	pinctrl-0 = <&tmp105_irq>;
	pinctrl-names = "default";
	/* kpd_row0.gpio_178 */
	interrupts-extended = <&gpio6 18 IRQ_TYPE_EDGE_FALLING
	&omap4_pmx_core 0x14e>;
	interrupt-names = "irq", "wakeup";
	wakeup-source;
	};
	};

	&keypad {
	keypad,num-rows = <8>;
	keypad,num-columns = <8>;
	linux,keymap = <

	/* Row 1 */
	MATRIX_KEY(0, 2, KEY_1)
	MATRIX_KEY(0, 6, KEY_2)
	MATRIX_KEY(2, 3, KEY_3)
	MATRIX_KEY(0, 7, KEY_4)
	MATRIX_KEY(0, 4, KEY_5)
	MATRIX_KEY(5, 5, KEY_6)
	MATRIX_KEY(0, 1, KEY_7)
	MATRIX_KEY(0, 5, KEY_8)
	MATRIX_KEY(0, 0, KEY_9)
	MATRIX_KEY(1, 6, KEY_0)

	/* Row 2 */
	MATRIX_KEY(3, 4, KEY_APOSTROPHE)
	MATRIX_KEY(7, 6, KEY_Q)
	MATRIX_KEY(7, 7, KEY_W)
	MATRIX_KEY(7, 2, KEY_E)
	MATRIX_KEY(1, 0, KEY_R)
	MATRIX_KEY(4, 4, KEY_T)
	MATRIX_KEY(1, 2, KEY_Y)
	MATRIX_KEY(6, 7, KEY_U)
	MATRIX_KEY(2, 2, KEY_I)
	MATRIX_KEY(5, 6, KEY_O)
	MATRIX_KEY(3, 7, KEY_P)
	MATRIX_KEY(6, 5, KEY_BACKSPACE)

	/* Row 3 */
	MATRIX_KEY(5, 4, KEY_TAB)
	MATRIX_KEY(5, 7, KEY_A)
	MATRIX_KEY(2, 7, KEY_S)
	MATRIX_KEY(7, 0, KEY_D)
	MATRIX_KEY(2, 6, KEY_F)
	MATRIX_KEY(6, 2, KEY_G)
	MATRIX_KEY(6, 6, KEY_H)
	MATRIX_KEY(1, 4, KEY_J)
	MATRIX_KEY(3, 1, KEY_K)
	MATRIX_KEY(2, 1, KEY_L)
	MATRIX_KEY(4, 6, KEY_ENTER)

	/* Row 4 */
	MATRIX_KEY(3, 6, KEY_LEFTSHIFT) /* KEY_CAPSLOCK */
	MATRIX_KEY(6, 1, KEY_Z)
	MATRIX_KEY(7, 4, KEY_X)
	MATRIX_KEY(5, 1, KEY_C)
	MATRIX_KEY(1, 7, KEY_V)
	MATRIX_KEY(2, 4, KEY_B)
	MATRIX_KEY(4, 1, KEY_N)
	MATRIX_KEY(1, 1, KEY_M)
	MATRIX_KEY(3, 5, KEY_COMMA)
	MATRIX_KEY(5, 2, KEY_DOT)
	MATRIX_KEY(6, 3, KEY_UP)
	MATRIX_KEY(7, 3, KEY_OK)

	/* Row 5 */
	MATRIX_KEY(2, 5, KEY_LEFTCTRL) /* KEY_LEFTSHIFT */
	MATRIX_KEY(4, 5, KEY_LEFTALT) /* SYM */
	MATRIX_KEY(6, 0, KEY_MINUS)
	MATRIX_KEY(4, 7, KEY_EQUAL)
	MATRIX_KEY(1, 5, KEY_SPACE)
	MATRIX_KEY(3, 2, KEY_SLASH)
	MATRIX_KEY(4, 3, KEY_LEFT)
	MATRIX_KEY(5, 3, KEY_DOWN)
	MATRIX_KEY(3, 3, KEY_RIGHT)

	/* Side buttons, KEY_VOLUMEDOWN and KEY_PWER are on CPCAP? */
	MATRIX_KEY(5, 0, KEY_VOLUMEUP)
	>;
	};

	&mmc1 {
	vmmc-supply = <&vwlan2>;
	bus-width = <4>;
	cd-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* gpio176 */
	};

	&mmc2 {
	vmmc-supply = <&vsdio>;
	bus-width = <8>;
	ti,non-removable;
	};

	&mmc3 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&mmc3_pins>;
	vmmc-supply = <&wl12xx_vmmc>;
	/* uart2_tx.sdmmc3_dat1 pad as wakeirq */
	interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
	&omap4_pmx_core 0xde>;
	interrupt-names = "irq", "wakeup";
	non-removable;
	bus-width = <4>;
	cap-power-off-card;
	keep-power-in-suspend;

	#address-cells = <1>;
	#size-cells = <0>;
	wlcore: wlcore@2 {
	compatible = "ti,wl1285", "ti,wl1283";
	reg = <2>;
	/* gpio_100 with gpmc_wait2 pad as wakeirq */
	interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>,
	<&omap4_pmx_core 0x4e>;
	interrupt-names = "irq", "wakeup";
	ref-clock-frequency = <26000000>;
	tcxo-clock-frequency = <26000000>;
	};
	};

	&i2c1 {
	led-controller@38 {
	compatible = "ti,lm3532";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x38>;

	enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;

	ramp-up-us = <1024>;
	ramp-down-us = <8193>;

	backlight_led: led@0 {
	reg = <0>;
	led-sources = <2>;
	ti,led-mode = <0>;
	label = ":backlight";
	};

	led@1 {
	reg = <1>;
	led-sources = <1>;
	ti,led-mode = <0>;
	label = ":kbd_backlight";
	};
	};
	};

	&i2c2 {
	touchscreen@4a {
	compatible = "atmel,maxtouch";
	reg = <0x4a>;
	pinctrl-names = "default";
	pinctrl-0 = <&touchscreen_pins>;

	reset-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio173 */

	/* gpio_183 with sys_nirq2 pad as wakeup */
	interrupts-extended = <&gpio6 23 IRQ_TYPE_LEVEL_LOW>,
	<&omap4_pmx_core 0x160>;
	interrupt-names = "irq", "wakeup";
	wakeup-source;
	};

	isl29030@44 {
	compatible = "isil,isl29030";
	reg = <0x44>;

	pinctrl-names = "default";
	pinctrl-0 = <&als_proximity_pins>;

	interrupt-parent = <&gpio6>;
	interrupts = <17 IRQ_TYPE_LEVEL_LOW>; /* gpio177 */
	};
	};

	&omap4_pmx_core {

	/* hdmi_hpd.gpio_63 */
	hdmi_hpd_gpio: pinmux_hdmi_hpd_pins {
	pinctrl-single,pins = <
	OMAP4_IOPAD(0x098, PIN_INPUT \| MUX_MODE3)
	>;
	};

	hdq_pins: pinmux_hdq_pins {
	pinctrl-single,pins = <
	/* 0x4a100120 hdq_sio.hdq_sio aa27 */
	OMAP4_IOPAD(0x120, PIN_INPUT \| MUX_MODE0)
	>;
	};

	/* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */
	dss_hdmi_pins: pinmux_dss_hdmi_pins {
	pinctrl-single,pins = <
	OMAP4_IOPAD(0x09a, PIN_INPUT \| MUX_MODE0)
	OMAP4_IOPAD(0x09c, PIN_INPUT \| MUX_MODE0)
	OMAP4_IOPAD(0x09e, PIN_INPUT \| MUX_MODE0)
	>;
	};

	+ /*
	+ * Android uses PIN_OFF_INPUT_PULLDOWN \| PIN_INPUT_PULLUP \| MUX_MODE3
	+ * for gpio_100, but the internal pull makes wlan flakey on some
	+ * devices. Off mode value should be tested if we have off mode working
	+ * later on.
	+ */
	+ mmc3_pins: pinmux_mmc3_pins {
	+ pinctrl-single,pins = <
	+ /* 0x4a10008e gpmc_wait2.gpio_100 d23 */
	+ OMAP4_IOPAD(0x08e, PIN_INPUT \| MUX_MODE3)
	+
	+ /* 0x4a100102 abe_mcbsp1_dx.sdmmc3_dat2 ab25 */
	+ OMAP4_IOPAD(0x102, PIN_INPUT_PULLUP \| MUX_MODE1)
	+
	+ /* 0x4a100104 abe_mcbsp1_fsx.sdmmc3_dat3 ac27 */
	+ OMAP4_IOPAD(0x104, PIN_INPUT_PULLUP \| MUX_MODE1)
	+
	+ /* 0x4a100118 uart2_cts.sdmmc3_clk ab26 */
	+ OMAP4_IOPAD(0x118, PIN_INPUT \| MUX_MODE1)
	+
	+ /* 0x4a10011a uart2_rts.sdmmc3_cmd ab27 */
	+ OMAP4_IOPAD(0x11a, PIN_INPUT_PULLUP \| MUX_MODE1)
	+
	+ /* 0x4a10011c uart2_rx.sdmmc3_dat0 aa25 */
	+ OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP \| MUX_MODE1)
	+
	+ /* 0x4a10011e uart2_tx.sdmmc3_dat1 aa26 */
	+ OMAP4_IOPAD(0x11e, PIN_INPUT_PULLUP \| MUX_MODE1)
	+ >;
	+ };
	+
	/* gpmc_ncs0.gpio_50 */
	poweroff_gpio: pinmux_poweroff_pins {
	pinctrl-single,pins = <
	OMAP4_IOPAD(0x074, PIN_OUTPUT_PULLUP \| MUX_MODE3)
	>;
	};

	/* kpd_row0.gpio_178 */
	tmp105_irq: pinmux_tmp105_irq {
	pinctrl-single,pins = <
	OMAP4_IOPAD(0x18e, PIN_INPUT_PULLUP \| MUX_MODE3)
	>;
	};

	usb_gpio_mux_sel1: pinmux_usb_gpio_mux_sel1_pins {
	/* gpio_60 */
	pinctrl-single,pins = <
	OMAP4_IOPAD(0x088, PIN_OUTPUT \| MUX_MODE3)
	>;
	};

	touchscreen_pins: pinmux_touchscreen_pins {
	pinctrl-single,pins = <
	OMAP4_IOPAD(0x180, PIN_OUTPUT \| MUX_MODE3)
	OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP \| MUX_MODE3)
	>;
	};

	als_proximity_pins: pinmux_als_proximity_pins {
	pinctrl-single,pins = <
	OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP \| MUX_MODE3)
	>;
	};

	usb_mdm6600_pins: pinmux_usb_mdm6600_pins {
	pinctrl-single,pins = <
	/* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */
	OMAP4_IOPAD(0x0d8, PIN_INPUT \| MUX_MODE3)

	/* power 0x4a10007c gpmc_nwp.gpio_54 c25 */
	OMAP4_IOPAD(0x07c, PIN_OUTPUT \| MUX_MODE3)

	/* reset 0x4a100072 gpmc_a25.gpio_49 d20 */
	OMAP4_IOPAD(0x072, PIN_OUTPUT \| MUX_MODE3)

	/* mode0/bpwake 0x4a10014e sdmmc5_dat1.gpio_148 af4 */
	OMAP4_IOPAD(0x14e, PIN_OUTPUT \| MUX_MODE3)

	/* mode1/apwake 0x4a100150 sdmmc5_dat2.gpio_149 ag3 */
	OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW \| PIN_INPUT \| MUX_MODE3)

	/* status0 0x4a10007e gpmc_clk.gpio_55 b22 */
	OMAP4_IOPAD(0x07e, PIN_INPUT \| MUX_MODE3)

	/* status1 0x4a10007a gpmc_ncs3.gpio_53 c22 */
	OMAP4_IOPAD(0x07a, PIN_INPUT \| MUX_MODE3)

	/* status2 0x4a100078 gpmc_ncs2.gpio_52 d21 */
	OMAP4_IOPAD(0x078, PIN_INPUT \| MUX_MODE3)

	/* cmd0 0x4a100094 gpmc_ncs6.gpio_103 c24 */
	OMAP4_IOPAD(0x094, PIN_OUTPUT \| MUX_MODE3)

	/* cmd1 0x4a100096 gpmc_ncs7.gpio_104 d24 */
	OMAP4_IOPAD(0x096, PIN_OUTPUT \| MUX_MODE3)

	/* cmd2 0x4a100142 uart3_rts_sd.gpio_142 f28 */
	OMAP4_IOPAD(0x142, PIN_OUTPUT \| MUX_MODE3)
	>;
	};

	usb_ulpi_pins: pinmux_usb_ulpi_pins {
	pinctrl-single,pins = <
	OMAP4_IOPAD(0x196, MUX_MODE7)
	OMAP4_IOPAD(0x198, MUX_MODE7)
	OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP \| MUX_MODE0)
	OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP \| MUX_MODE0)
	OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP \| MUX_MODE0)
	OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP \| MUX_MODE0)
	OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP \| MUX_MODE0)
	OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP \| MUX_MODE0)
	OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP \| MUX_MODE0)
	OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP \| MUX_MODE0)
	OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP \| MUX_MODE0)
	OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP \| MUX_MODE0)
	OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP \| MUX_MODE0)
	OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP \| MUX_MODE0)
	>;
	};

	/* usb0_otg_dp and usb0_otg_dm */
	usb_utmi_pins: pinmux_usb_utmi_pins {
	pinctrl-single,pins = <
	OMAP4_IOPAD(0x196, PIN_INPUT \| MUX_MODE0)
	OMAP4_IOPAD(0x198, PIN_INPUT \| MUX_MODE0)
	OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP \| MUX_MODE7)
	>;
	};

	/*
	* Note that the v3.0.8 stock userspace dynamically remuxes uart1
	* rts pin probably for PM purposes to PIN_INPUT_PULLUP \| MUX_MODE7
	* when not used. If needed, we can add rts pin remux later based
	* on power measurements.
	*/
	uart1_pins: pinmux_uart1_pins {
	pinctrl-single,pins = <
	/* 0x4a10013c mcspi1_cs2.uart1_cts ag23 */
	OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP \| MUX_MODE1)

	/* 0x4a10013e mcspi1_cs3.uart1_rts ah23 */
	OMAP4_IOPAD(0x13e, MUX_MODE1)

	/* 0x4a100140 uart3_cts_rctx.uart1_tx f27 */
	OMAP4_IOPAD(0x140, PIN_OUTPUT \| MUX_MODE1)

	/* 0x4a1001ca dpm_emu14.uart1_rx aa3 */
	OMAP4_IOPAD(0x1ca, PIN_INPUT_PULLUP \| MUX_MODE2)
	>;
	};

	/* uart3_tx_irtx and uart3_rx_irrx */
	uart3_pins: pinmux_uart3_pins {
	pinctrl-single,pins = <
	OMAP4_IOPAD(0x196, MUX_MODE7)
	OMAP4_IOPAD(0x198, MUX_MODE7)
	OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1ba, MUX_MODE2)
	OMAP4_IOPAD(0x1bc, PIN_INPUT \| MUX_MODE2)
	OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP \| MUX_MODE7)
	OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP \| MUX_MODE7)
	>;
	};

	uart4_pins: pinmux_uart4_pins {
	pinctrl-single,pins = <
	OMAP4_IOPAD(0x15c, PIN_INPUT \| MUX_MODE0) /* uart4_rx */
	OMAP4_IOPAD(0x15e, PIN_OUTPUT \| MUX_MODE0) /* uart4_tx */
	OMAP4_IOPAD(0x110, PIN_INPUT_PULLUP \| MUX_MODE5) /* uart4_cts */
	OMAP4_IOPAD(0x112, PIN_OUTPUT_PULLUP \| MUX_MODE5) /* uart4_rts */
	>;
	};

	mcbsp2_pins: pinmux_mcbsp2_pins {
	pinctrl-single,pins = <
	OMAP4_IOPAD(0x0f6, PIN_INPUT \| MUX_MODE0) /* abe_mcbsp2_clkx */
	OMAP4_IOPAD(0x0f8, PIN_INPUT \| MUX_MODE0) /* abe_mcbsp2_dr */
	OMAP4_IOPAD(0x0fa, PIN_OUTPUT \| MUX_MODE0) /* abe_mcbsp2_dx */
	OMAP4_IOPAD(0x0fc, PIN_INPUT \| MUX_MODE0) /* abe_mcbsp2_fsx */
	>;
	};

	mcbsp3_pins: pinmux_mcbsp3_pins {
	pinctrl-single,pins = <
	OMAP4_IOPAD(0x106, PIN_INPUT \| MUX_MODE1) /* abe_mcbsp3_dr */
	OMAP4_IOPAD(0x108, PIN_OUTPUT \| MUX_MODE1) /* abe_mcbsp3_dx */
	OMAP4_IOPAD(0x10a, PIN_INPUT \| MUX_MODE1) /* abe_mcbsp3_clkx */
	OMAP4_IOPAD(0x10c, PIN_INPUT \| MUX_MODE1) /* abe_mcbsp3_fsx */
	>;
	};

	vibrator_direction_pin: pinmux_vibrator_direction_pin {
	pinctrl-single,pins = <
	OMAP4_IOPAD(0x1ce, PIN_OUTPUT \| MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */
	>;
	};

	vibrator_enable_pin: pinmux_vibrator_enable_pin {
	pinctrl-single,pins = <
	OMAP4_IOPAD(0X1d0, PIN_OUTPUT \| MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */
	>;
	};
	};

	&omap4_pmx_wkup {
	usb_gpio_mux_sel2: pinmux_usb_gpio_mux_sel2_pins {
	/* gpio_wk0 */
	pinctrl-single,pins = <
	OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN \| MUX_MODE3)
	>;
	};
	};

	/* RNG is used by secure mode and not accessible */
	&rng_target {
	status = "disabled";
	};

	/* Configure pwm clock source for timers 8 & 9 */
	&timer8 {
	assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
	assigned-clock-parents = <&sys_clkin_ck>;
	};

	&timer9 {
	assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
	assigned-clock-parents = <&sys_clkin_ck>;
	};

	/*
	- * As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for
	- * uart1 wakeirq.
	+ * The uart1 port is wired to mdm6600 with rts and cts. The modem uses gpio_149
	+ * for wake-up events for both the USB PHY and the UART. We can use gpio_149
	+ * pad as the shared wakeirq for the UART rather than the RX or CTS pad as we
	+ * have gpio_149 trigger before the UART transfer starts.
	*/
	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
	interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH
	- &omap4_pmx_core 0xfc>;
	+ &omap4_pmx_core 0x110>;
	+ uart-has-rtscts;
	+ current-speed = <115200>;
	};

	&uart3 {
	interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
	&omap4_pmx_core 0x17c>;
	};

	&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_pins>;

	bluetooth {
	compatible = "ti,wl1285-st";
	enable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; /* gpio 174 */
	max-speed = <3686400>;
	};
	};

	&usbhsohci {
	phys = <&fsusb1_phy>;
	phy-names = "usb";
	};

	&usbhsehci {
	phys = <&hsusb2_phy>;
	};

	&usbhshost {
	port1-mode = "ohci-phy-4pin-dpdm";
	port2-mode = "ehci-tll";
	};

	/* Internal UTMI+ PHY used for OTG, CPCAP ULPI PHY for detection and charger */
	&usb_otg_hs {
	interface-type = <1>;
	mode = <3>;

	/*
	* Max 300 mA steps based on similar PMIC MC13783UG.pdf "Table 10-4.
	* VBUS Regulator Main Characteristics". Binding uses 2 mA units.
	*/
	power = <150>;
	};

	&i2c4 {
	ak8975: magnetometer@c {
	compatible = "asahi-kasei,ak8975";
	reg = <0x0c>;

	vdd-supply = <&vhvio>;

	interrupt-parent = <&gpio6>;
	interrupts = <15 IRQ_TYPE_EDGE_RISING>; /* gpio175 */

	rotation-matrix = "-1", "0", "0",
	"0", "1", "0",
	"0", "0", "-1";

	};

	lis3dh: accelerometer@18 {
	compatible = "st,lis3dh-accel";
	reg = <0x18>;

	vdd-supply = <&vhvio>;

	interrupt-parent = <&gpio2>;
	interrupts = <2 IRQ_TYPE_EDGE_BOTH>; /* gpio34 */

	rotation-matrix = "0", "-1", "0",
	"1", "0", "0",
	"0", "0", "1";
	};
	};

	&mcbsp2 {
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&mcbsp2_pins>;
	status = "okay";

	mcbsp2_port: port {
	cpu_dai2: endpoint {
	dai-format = "i2s";
	remote-endpoint = <&cpcap_audio_codec0>;
	frame-master = <&cpcap_audio_codec0>;
	bitclock-master = <&cpcap_audio_codec0>;
	};
	};
	};

	&mcbsp3 {
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&mcbsp3_pins>;
	status = "okay";

	mcbsp3_port: port {
	cpu_dai3: endpoint {
	dai-format = "dsp_a";
	frame-master = <&cpcap_audio_codec1>;
	bitclock-master = <&cpcap_audio_codec1>;
	remote-endpoint = <&cpcap_audio_codec1>;
	};
	};
	};

	&cpcap_audio_codec0 {
	remote-endpoint = <&cpu_dai2>;
	};

	&cpcap_audio_codec1 {
	remote-endpoint = <&cpu_dai3>;
	};
	diff --git a/sys/gnu/dts/arm/mt2701.dtsi b/sys/gnu/dts/arm/mt2701.dtsi
	index 51e1305c6471..2093b38d6e6d 100644
	--- a/sys/gnu/dts/arm/mt2701.dtsi
	+++ b/sys/gnu/dts/arm/mt2701.dtsi
	@@ -1,710 +1,710 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Copyright (c) 2015 MediaTek Inc.
	* Author: Erin.Lo <erin.lo@mediatek.com>
	*
	*/

	#include <dt-bindings/clock/mt2701-clk.h>
	#include <dt-bindings/phy/phy.h>
	#include <dt-bindings/power/mt2701-power.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/memory/mt2701-larb-port.h>
	#include <dt-bindings/reset/mt2701-resets.h>
	#include "mt2701-pinfunc.h"

	/ {
	#address-cells = <2>;
	#size-cells = <2>;
	compatible = "mediatek,mt2701";
	interrupt-parent = <&cirq>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "mediatek,mt81xx-tz-smp";

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x0>;
	};
	cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x1>;
	};
	cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x2>;
	};
	cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x3>;
	};
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	trustzone-bootinfo@80002000 {
	compatible = "mediatek,trustzone-bootinfo";
	reg = <0 0x80002000 0 0x1000>;
	};
	};

	system_clk: dummy13m {
	compatible = "fixed-clock";
	clock-frequency = <13000000>;
	#clock-cells = <0>;
	};

	rtc_clk: dummy32k {
	compatible = "fixed-clock";
	clock-frequency = <32000>;
	#clock-cells = <0>;
	};

	clk26m: oscillator@0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <26000000>;
	clock-output-names = "clk26m";
	};

	rtc32k: oscillator@1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32000>;
	clock-output-names = "rtc32k";
	};

	thermal-zones {
	cpu_thermal: cpu_thermal {
	polling-delay-passive = <1000>; /* milliseconds */
	polling-delay = <1000>; /* milliseconds */

	thermal-sensors = <&thermal 0>;
	sustainable-power = <1000>;

	trips {
	threshold: trip-point@0 {
	temperature = <68000>;
	hysteresis = <2000>;
	type = "passive";
	};

	target: trip-point@1 {
	temperature = <85000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu_crit: cpu_crit@0 {
	temperature = <115000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupt-parent = <&gic>;
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	topckgen: syscon@10000000 {
	compatible = "mediatek,mt2701-topckgen", "syscon";
	reg = <0 0x10000000 0 0x1000>;
	#clock-cells = <1>;
	};

	infracfg: syscon@10001000 {
	compatible = "mediatek,mt2701-infracfg", "syscon";
	reg = <0 0x10001000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pericfg: syscon@10003000 {
	compatible = "mediatek,mt2701-pericfg", "syscon";
	reg = <0 0x10003000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	syscfg_pctl_a: syscfg@10005000 {
	compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
	reg = <0 0x10005000 0 0x1000>;
	};

	- scpsys: scpsys@10006000 {
	+ scpsys: power-controller@10006000 {
	compatible = "mediatek,mt2701-scpsys", "syscon";
	#power-domain-cells = <1>;
	reg = <0 0x10006000 0 0x1000>;
	infracfg = <&infracfg>;
	clocks = <&topckgen CLK_TOP_MM_SEL>,
	<&topckgen CLK_TOP_MFG_SEL>,
	<&topckgen CLK_TOP_ETHIF_SEL>;
	clock-names = "mm", "mfg", "ethif";
	};

	watchdog: watchdog@10007000 {
	compatible = "mediatek,mt2701-wdt",
	"mediatek,mt6589-wdt";
	reg = <0 0x10007000 0 0x100>;
	};

	timer: timer@10008000 {
	compatible = "mediatek,mt2701-timer",
	"mediatek,mt6577-timer";
	reg = <0 0x10008000 0 0x80>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&system_clk>, <&rtc_clk>;
	clock-names = "system-clk", "rtc-clk";
	};

	pio: pinctrl@1000b000 {
	compatible = "mediatek,mt2701-pinctrl";
	reg = <0 0x1000b000 0 0x1000>;
	mediatek,pctl-regmap = <&syscfg_pctl_a>;
	pins-are-numbered;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	};

	smi_common: smi@1000c000 {
	compatible = "mediatek,mt2701-smi-common";
	reg = <0 0x1000c000 0 0x1000>;
	clocks = <&infracfg CLK_INFRA_SMI>,
	<&mmsys CLK_MM_SMI_COMMON>,
	<&infracfg CLK_INFRA_SMI>;
	clock-names = "apb", "smi", "async";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	};

	sysirq: interrupt-controller@10200100 {
	compatible = "mediatek,mt2701-sysirq",
	"mediatek,mt6577-sysirq";
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	reg = <0 0x10200100 0 0x1c>;
	};

	cirq: interrupt-controller@10204000 {
	compatible = "mediatek,mt2701-cirq",
	"mediatek,mtk-cirq";
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&sysirq>;
	reg = <0 0x10204000 0 0x400>;
	mediatek,ext-irq-range = <32 200>;
	};

	iommu: mmsys_iommu@10205000 {
	compatible = "mediatek,mt2701-m4u";
	reg = <0 0x10205000 0 0x1000>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_M4U>;
	clock-names = "bclk";
	mediatek,larbs = <&larb0 &larb1 &larb2>;
	#iommu-cells = <1>;
	};

	apmixedsys: syscon@10209000 {
	compatible = "mediatek,mt2701-apmixedsys", "syscon";
	reg = <0 0x10209000 0 0x1000>;
	#clock-cells = <1>;
	};

	gic: interrupt-controller@10211000 {
	compatible = "arm,cortex-a7-gic";
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	reg = <0 0x10211000 0 0x1000>,
	<0 0x10212000 0 0x2000>,
	<0 0x10214000 0 0x2000>,
	<0 0x10216000 0 0x2000>;
	};

	auxadc: adc@11001000 {
	compatible = "mediatek,mt2701-auxadc";
	reg = <0 0x11001000 0 0x1000>;
	clocks = <&pericfg CLK_PERI_AUXADC>;
	clock-names = "main";
	#io-channel-cells = <1>;
	status = "disabled";
	};

	uart0: serial@11002000 {
	compatible = "mediatek,mt2701-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11002000 0 0x400>;
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart1: serial@11003000 {
	compatible = "mediatek,mt2701-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11003000 0 0x400>;
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart2: serial@11004000 {
	compatible = "mediatek,mt2701-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11004000 0 0x400>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart3: serial@11005000 {
	compatible = "mediatek,mt2701-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11005000 0 0x400>;
	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	i2c0: i2c@11007000 {
	compatible = "mediatek,mt2701-i2c",
	"mediatek,mt6577-i2c";
	reg = <0 0x11007000 0 0x70>,
	<0 0x11000200 0 0x80>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main", "dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c1: i2c@11008000 {
	compatible = "mediatek,mt2701-i2c",
	"mediatek,mt6577-i2c";
	reg = <0 0x11008000 0 0x70>,
	<0 0x11000280 0 0x80>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main", "dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c2: i2c@11009000 {
	compatible = "mediatek,mt2701-i2c",
	"mediatek,mt6577-i2c";
	reg = <0 0x11009000 0 0x70>,
	<0 0x11000300 0 0x80>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main", "dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi0: spi@1100a000 {
	compatible = "mediatek,mt2701-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x1100a000 0 0x100>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	<&topckgen CLK_TOP_SPI0_SEL>,
	<&pericfg CLK_PERI_SPI0>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	thermal: thermal@1100b000 {
	#thermal-sensor-cells = <0>;
	compatible = "mediatek,mt2701-thermal";
	reg = <0 0x1100b000 0 0x1000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
	clock-names = "therm", "auxadc";
	resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
	reset-names = "therm";
	mediatek,auxadc = <&auxadc>;
	mediatek,apmixedsys = <&apmixedsys>;
	};

	nandc: nfi@1100d000 {
	compatible = "mediatek,mt2701-nfc";
	reg = <0 0x1100d000 0 0x1000>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_NFI>,
	<&pericfg CLK_PERI_NFI_PAD>;
	clock-names = "nfi_clk", "pad_clk";
	status = "disabled";
	ecc-engine = <&bch>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	bch: ecc@1100e000 {
	compatible = "mediatek,mt2701-ecc";
	reg = <0 0x1100e000 0 0x1000>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_NFI_ECC>;
	clock-names = "nfiecc_clk";
	status = "disabled";
	};

	nor_flash: spi@11014000 {
	compatible = "mediatek,mt2701-nor",
	"mediatek,mt8173-nor";
	reg = <0 0x11014000 0 0xe0>;
	clocks = <&pericfg CLK_PERI_FLASH>,
	<&topckgen CLK_TOP_FLASH_SEL>;
	clock-names = "spi", "sf";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi1: spi@11016000 {
	compatible = "mediatek,mt2701-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x11016000 0 0x100>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	<&topckgen CLK_TOP_SPI1_SEL>,
	<&pericfg CLK_PERI_SPI1>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	spi2: spi@11017000 {
	compatible = "mediatek,mt2701-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x11017000 0 0x1000>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	<&topckgen CLK_TOP_SPI2_SEL>,
	<&pericfg CLK_PERI_SPI2>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	audsys: clock-controller@11220000 {
	compatible = "mediatek,mt2701-audsys", "syscon";
	reg = <0 0x11220000 0 0x2000>;
	#clock-cells = <1>;

	afe: audio-controller {
	compatible = "mediatek,mt2701-audio";
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
	interrupt-names = "afe", "asys";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;

	clocks = <&infracfg CLK_INFRA_AUDIO>,
	<&topckgen CLK_TOP_AUD_MUX1_SEL>,
	<&topckgen CLK_TOP_AUD_MUX2_SEL>,
	<&topckgen CLK_TOP_AUD_48K_TIMING>,
	<&topckgen CLK_TOP_AUD_44K_TIMING>,
	<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
	<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
	<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
	<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
	<&audsys CLK_AUD_I2SO1>,
	<&audsys CLK_AUD_I2SO2>,
	<&audsys CLK_AUD_I2SO3>,
	<&audsys CLK_AUD_I2SO4>,
	<&audsys CLK_AUD_I2SIN1>,
	<&audsys CLK_AUD_I2SIN2>,
	<&audsys CLK_AUD_I2SIN3>,
	<&audsys CLK_AUD_I2SIN4>,
	<&audsys CLK_AUD_ASRCO1>,
	<&audsys CLK_AUD_ASRCO2>,
	<&audsys CLK_AUD_ASRCO3>,
	<&audsys CLK_AUD_ASRCO4>,
	<&audsys CLK_AUD_AFE>,
	<&audsys CLK_AUD_AFE_CONN>,
	<&audsys CLK_AUD_A1SYS>,
	<&audsys CLK_AUD_A2SYS>,
	<&audsys CLK_AUD_AFE_MRGIF>;

	clock-names = "infra_sys_audio_clk",
	"top_audio_mux1_sel",
	"top_audio_mux2_sel",
	"top_audio_a1sys_hp",
	"top_audio_a2sys_hp",
	"i2s0_src_sel",
	"i2s1_src_sel",
	"i2s2_src_sel",
	"i2s3_src_sel",
	"i2s0_src_div",
	"i2s1_src_div",
	"i2s2_src_div",
	"i2s3_src_div",
	"i2s0_mclk_en",
	"i2s1_mclk_en",
	"i2s2_mclk_en",
	"i2s3_mclk_en",
	"i2so0_hop_ck",
	"i2so1_hop_ck",
	"i2so2_hop_ck",
	"i2so3_hop_ck",
	"i2si0_hop_ck",
	"i2si1_hop_ck",
	"i2si2_hop_ck",
	"i2si3_hop_ck",
	"asrc0_out_ck",
	"asrc1_out_ck",
	"asrc2_out_ck",
	"asrc3_out_ck",
	"audio_afe_pd",
	"audio_afe_conn_pd",
	"audio_a1sys_pd",
	"audio_a2sys_pd",
	"audio_mrgif_pd";

	assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
	<&topckgen CLK_TOP_AUD_MUX2_SEL>,
	<&topckgen CLK_TOP_AUD_MUX1_DIV>,
	<&topckgen CLK_TOP_AUD_MUX2_DIV>;
	assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
	<&topckgen CLK_TOP_AUD2PLL_90M>;
	assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
	};
	};

	mmsys: syscon@14000000 {
	compatible = "mediatek,mt2701-mmsys", "syscon";
	reg = <0 0x14000000 0 0x1000>;
	#clock-cells = <1>;
	};

	bls: pwm@1400a000 {
	compatible = "mediatek,mt2701-disp-pwm";
	reg = <0 0x1400a000 0 0x1000>;
	#pwm-cells = <2>;
	clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>;
	clock-names = "main", "mm";
	status = "disabled";
	};

	larb0: larb@14010000 {
	compatible = "mediatek,mt2701-smi-larb";
	reg = <0 0x14010000 0 0x1000>;
	mediatek,smi = <&smi_common>;
	mediatek,larb-id = <0>;
	clocks = <&mmsys CLK_MM_SMI_LARB0>,
	<&mmsys CLK_MM_SMI_LARB0>;
	clock-names = "apb", "smi";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	};

	imgsys: syscon@15000000 {
	compatible = "mediatek,mt2701-imgsys", "syscon";
	reg = <0 0x15000000 0 0x1000>;
	#clock-cells = <1>;
	};

	larb2: larb@15001000 {
	compatible = "mediatek,mt2701-smi-larb";
	reg = <0 0x15001000 0 0x1000>;
	mediatek,smi = <&smi_common>;
	mediatek,larb-id = <2>;
	clocks = <&imgsys CLK_IMG_SMI_COMM>,
	<&imgsys CLK_IMG_SMI_COMM>;
	clock-names = "apb", "smi";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
	};

	jpegdec: jpegdec@15004000 {
	compatible = "mediatek,mt2701-jpgdec";
	reg = <0 0x15004000 0 0x1000>;
	interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
	<&imgsys CLK_IMG_JPGDEC>;
	clock-names = "jpgdec-smi",
	"jpgdec";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
	mediatek,larb = <&larb2>;
	iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
	<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
	};

	vdecsys: syscon@16000000 {
	compatible = "mediatek,mt2701-vdecsys", "syscon";
	reg = <0 0x16000000 0 0x1000>;
	#clock-cells = <1>;
	};

	larb1: larb@16010000 {
	compatible = "mediatek,mt2701-smi-larb";
	reg = <0 0x16010000 0 0x1000>;
	mediatek,smi = <&smi_common>;
	mediatek,larb-id = <1>;
	clocks = <&vdecsys CLK_VDEC_CKGEN>,
	<&vdecsys CLK_VDEC_LARB>;
	clock-names = "apb", "smi";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
	};

	hifsys: syscon@1a000000 {
	compatible = "mediatek,mt2701-hifsys", "syscon";
	reg = <0 0x1a000000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	usb0: usb@1a1c0000 {
	compatible = "mediatek,mt8173-xhci";
	reg = <0 0x1a1c0000 0 0x1000>,
	<0 0x1a1c4700 0 0x0100>;
	reg-names = "mac", "ippc";
	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
	<&topckgen CLK_TOP_ETHIF_SEL>;
	clock-names = "sys_ck", "ref_ck";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
	phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
	status = "disabled";
	};

	u3phy0: usb-phy@1a1c4000 {
	compatible = "mediatek,mt2701-u3phy";
	reg = <0 0x1a1c4000 0 0x0700>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "disabled";

	u2port0: usb-phy@1a1c4800 {
	reg = <0 0x1a1c4800 0 0x0100>;
	clocks = <&topckgen CLK_TOP_USB_PHY48M>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};

	u3port0: usb-phy@1a1c4900 {
	reg = <0 0x1a1c4900 0 0x0700>;
	clocks = <&clk26m>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};
	};

	usb1: usb@1a240000 {
	compatible = "mediatek,mt8173-xhci";
	reg = <0 0x1a240000 0 0x1000>,
	<0 0x1a244700 0 0x0100>;
	reg-names = "mac", "ippc";
	interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
	<&topckgen CLK_TOP_ETHIF_SEL>;
	clock-names = "sys_ck", "ref_ck";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
	phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
	status = "disabled";
	};

	u3phy1: usb-phy@1a244000 {
	compatible = "mediatek,mt2701-u3phy";
	reg = <0 0x1a244000 0 0x0700>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "disabled";

	u2port1: usb-phy@1a244800 {
	reg = <0 0x1a244800 0 0x0100>;
	clocks = <&topckgen CLK_TOP_USB_PHY48M>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};

	u3port1: usb-phy@1a244900 {
	reg = <0 0x1a244900 0 0x0700>;
	clocks = <&clk26m>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};
	};

	ethsys: syscon@1b000000 {
	compatible = "mediatek,mt2701-ethsys", "syscon";
	reg = <0 0x1b000000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	eth: ethernet@1b100000 {
	compatible = "mediatek,mt2701-eth", "syscon";
	reg = <0 0x1b100000 0 0x20000>;
	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
	<&ethsys CLK_ETHSYS_ESW>,
	<&ethsys CLK_ETHSYS_GP1>,
	<&ethsys CLK_ETHSYS_GP2>,
	<&apmixedsys CLK_APMIXED_TRGPLL>;
	clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
	resets = <&ethsys MT2701_ETHSYS_FE_RST>,
	<&ethsys MT2701_ETHSYS_GMAC_RST>,
	<&ethsys MT2701_ETHSYS_PPE_RST>;
	reset-names = "fe", "gmac", "ppe";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
	mediatek,ethsys = <&ethsys>;
	mediatek,pctl = <&syscfg_pctl_a>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	bdpsys: syscon@1c000000 {
	compatible = "mediatek,mt2701-bdpsys", "syscon";
	reg = <0 0x1c000000 0 0x1000>;
	#clock-cells = <1>;
	};
	};
	diff --git a/sys/gnu/dts/arm/mt7623.dtsi b/sys/gnu/dts/arm/mt7623.dtsi
	index a79f0b6c3429..f76b4a3c34b9 100644
	--- a/sys/gnu/dts/arm/mt7623.dtsi
	+++ b/sys/gnu/dts/arm/mt7623.dtsi
	@@ -1,1365 +1,1365 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Copyright (c) 2017-2018 MediaTek Inc.
	* Author: John Crispin <john@phrozen.org>
	* Sean Wang <sean.wang@mediatek.com>
	*
	*/

	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/mt2701-clk.h>
	#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
	#include <dt-bindings/power/mt2701-power.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/phy/phy.h>
	#include <dt-bindings/memory/mt2701-larb-port.h>
	#include <dt-bindings/reset/mt2701-resets.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	compatible = "mediatek,mt7623";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpu_opp_table: opp-table {
	compatible = "operating-points-v2";
	opp-shared;

	opp-98000000 {
	opp-hz = /bits/ 64 <98000000>;
	opp-microvolt = <1050000>;
	};

	opp-198000000 {
	opp-hz = /bits/ 64 <198000000>;
	opp-microvolt = <1050000>;
	};

	opp-398000000 {
	opp-hz = /bits/ 64 <398000000>;
	opp-microvolt = <1050000>;
	};

	opp-598000000 {
	opp-hz = /bits/ 64 <598000000>;
	opp-microvolt = <1050000>;
	};

	opp-747500000 {
	opp-hz = /bits/ 64 <747500000>;
	opp-microvolt = <1050000>;
	};

	opp-1040000000 {
	opp-hz = /bits/ 64 <1040000000>;
	opp-microvolt = <1150000>;
	};

	opp-1196000000 {
	opp-hz = /bits/ 64 <1196000000>;
	opp-microvolt = <1200000>;
	};

	opp-1300000000 {
	opp-hz = /bits/ 64 <1300000000>;
	opp-microvolt = <1300000>;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "mediatek,mt6589-smp";

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x0>;
	clocks = <&infracfg CLK_INFRA_CPUSEL>,
	<&apmixedsys CLK_APMIXED_MAINPLL>;
	clock-names = "cpu", "intermediate";
	operating-points-v2 = <&cpu_opp_table>;
	#cooling-cells = <2>;
	clock-frequency = <1300000000>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x1>;
	clocks = <&infracfg CLK_INFRA_CPUSEL>,
	<&apmixedsys CLK_APMIXED_MAINPLL>;
	clock-names = "cpu", "intermediate";
	operating-points-v2 = <&cpu_opp_table>;
	#cooling-cells = <2>;
	clock-frequency = <1300000000>;
	};

	cpu2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x2>;
	clocks = <&infracfg CLK_INFRA_CPUSEL>,
	<&apmixedsys CLK_APMIXED_MAINPLL>;
	clock-names = "cpu", "intermediate";
	operating-points-v2 = <&cpu_opp_table>;
	#cooling-cells = <2>;
	clock-frequency = <1300000000>;
	};

	cpu3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x3>;
	clocks = <&infracfg CLK_INFRA_CPUSEL>,
	<&apmixedsys CLK_APMIXED_MAINPLL>;
	clock-names = "cpu", "intermediate";
	operating-points-v2 = <&cpu_opp_table>;
	#cooling-cells = <2>;
	clock-frequency = <1300000000>;
	};
	};

	pmu {
	compatible = "arm,cortex-a7-pmu";
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	system_clk: dummy13m {
	compatible = "fixed-clock";
	clock-frequency = <13000000>;
	#clock-cells = <0>;
	};

	rtc32k: oscillator-1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32000>;
	clock-output-names = "rtc32k";
	};

	clk26m: oscillator-0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <26000000>;
	clock-output-names = "clk26m";
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	polling-delay-passive = <1000>;
	polling-delay = <1000>;

	thermal-sensors = <&thermal 0>;

	trips {
	cpu_passive: cpu-passive {
	temperature = <47000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu_active: cpu-active {
	temperature = <67000>;
	hysteresis = <2000>;
	type = "active";
	};

	cpu_hot: cpu-hot {
	temperature = <87000>;
	hysteresis = <2000>;
	type = "hot";
	};

	cpu-crit {
	temperature = <107000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu_passive>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};

	map1 {
	trip = <&cpu_active>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};

	map2 {
	trip = <&cpu_hot>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupt-parent = <&gic>;
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	clock-frequency = <13000000>;
	arm,cpu-registers-not-fw-configured;
	};

	topckgen: syscon@10000000 {
	compatible = "mediatek,mt7623-topckgen",
	"mediatek,mt2701-topckgen",
	"syscon";
	reg = <0 0x10000000 0 0x1000>;
	#clock-cells = <1>;
	};

	infracfg: syscon@10001000 {
	compatible = "mediatek,mt7623-infracfg",
	"mediatek,mt2701-infracfg",
	"syscon";
	reg = <0 0x10001000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pericfg: syscon@10003000 {
	compatible = "mediatek,mt7623-pericfg",
	"mediatek,mt2701-pericfg",
	"syscon";
	reg = <0 0x10003000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pio: pinctrl@10005000 {
	compatible = "mediatek,mt7623-pinctrl";
	reg = <0 0x1000b000 0 0x1000>;
	mediatek,pctl-regmap = <&syscfg_pctl_a>;
	pins-are-numbered;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	interrupt-parent = <&gic>;
	#interrupt-cells = <2>;
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	};

	syscfg_pctl_a: syscfg@10005000 {
	compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
	reg = <0 0x10005000 0 0x1000>;
	};

	- scpsys: scpsys@10006000 {
	+ scpsys: power-controller@10006000 {
	compatible = "mediatek,mt7623-scpsys",
	"mediatek,mt2701-scpsys",
	"syscon";
	#power-domain-cells = <1>;
	reg = <0 0x10006000 0 0x1000>;
	infracfg = <&infracfg>;
	clocks = <&topckgen CLK_TOP_MM_SEL>,
	<&topckgen CLK_TOP_MFG_SEL>,
	<&topckgen CLK_TOP_ETHIF_SEL>;
	clock-names = "mm", "mfg", "ethif";
	};

	watchdog: watchdog@10007000 {
	compatible = "mediatek,mt7623-wdt",
	"mediatek,mt6589-wdt";
	reg = <0 0x10007000 0 0x100>;
	};

	timer: timer@10008000 {
	compatible = "mediatek,mt7623-timer",
	"mediatek,mt6577-timer";
	reg = <0 0x10008000 0 0x80>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&system_clk>, <&rtc32k>;
	clock-names = "system-clk", "rtc-clk";
	};

	smi_common: smi@1000c000 {
	compatible = "mediatek,mt7623-smi-common",
	"mediatek,mt2701-smi-common";
	reg = <0 0x1000c000 0 0x1000>;
	clocks = <&infracfg CLK_INFRA_SMI>,
	<&mmsys CLK_MM_SMI_COMMON>,
	<&infracfg CLK_INFRA_SMI>;
	clock-names = "apb", "smi", "async";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	};

	pwrap: pwrap@1000d000 {
	compatible = "mediatek,mt7623-pwrap",
	"mediatek,mt2701-pwrap";
	reg = <0 0x1000d000 0 0x1000>;
	reg-names = "pwrap";
	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
	reset-names = "pwrap";
	clocks = <&infracfg CLK_INFRA_PMICSPI>,
	<&infracfg CLK_INFRA_PMICWRAP>;
	clock-names = "spi", "wrap";
	};

	cir: cir@10013000 {
	compatible = "mediatek,mt7623-cir";
	reg = <0 0x10013000 0 0x1000>;
	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_IRRX>;
	clock-names = "clk";
	status = "disabled";
	};

	sysirq: interrupt-controller@10200100 {
	compatible = "mediatek,mt7623-sysirq",
	"mediatek,mt6577-sysirq";
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	reg = <0 0x10200100 0 0x1c>;
	};

	iommu: mmsys_iommu@10205000 {
	compatible = "mediatek,mt7623-m4u",
	"mediatek,mt2701-m4u";
	reg = <0 0x10205000 0 0x1000>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_M4U>;
	clock-names = "bclk";
	mediatek,larbs = <&larb0 &larb1 &larb2>;
	#iommu-cells = <1>;
	};

	efuse: efuse@10206000 {
	compatible = "mediatek,mt7623-efuse",
	"mediatek,mt8173-efuse";
	reg = <0 0x10206000 0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	thermal_calibration_data: calib@424 {
	reg = <0x424 0xc>;
	};
	};

	apmixedsys: syscon@10209000 {
	compatible = "mediatek,mt7623-apmixedsys",
	"mediatek,mt2701-apmixedsys",
	"syscon";
	reg = <0 0x10209000 0 0x1000>;
	#clock-cells = <1>;
	};

	rng: rng@1020f000 {
	compatible = "mediatek,mt7623-rng";
	reg = <0 0x1020f000 0 0x1000>;
	clocks = <&infracfg CLK_INFRA_TRNG>;
	clock-names = "rng";
	};

	gic: interrupt-controller@10211000 {
	compatible = "arm,cortex-a7-gic";
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	reg = <0 0x10211000 0 0x1000>,
	<0 0x10212000 0 0x2000>,
	<0 0x10214000 0 0x2000>,
	<0 0x10216000 0 0x2000>;
	};

	auxadc: adc@11001000 {
	compatible = "mediatek,mt7623-auxadc",
	"mediatek,mt2701-auxadc";
	reg = <0 0x11001000 0 0x1000>;
	clocks = <&pericfg CLK_PERI_AUXADC>;
	clock-names = "main";
	#io-channel-cells = <1>;
	};

	uart0: serial@11002000 {
	compatible = "mediatek,mt7623-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11002000 0 0x400>;
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART0_SEL>,
	<&pericfg CLK_PERI_UART0>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart1: serial@11003000 {
	compatible = "mediatek,mt7623-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11003000 0 0x400>;
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART1_SEL>,
	<&pericfg CLK_PERI_UART1>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart2: serial@11004000 {
	compatible = "mediatek,mt7623-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11004000 0 0x400>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART2_SEL>,
	<&pericfg CLK_PERI_UART2>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart3: serial@11005000 {
	compatible = "mediatek,mt7623-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11005000 0 0x400>;
	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART3_SEL>,
	<&pericfg CLK_PERI_UART3>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	pwm: pwm@11006000 {
	compatible = "mediatek,mt7623-pwm";
	reg = <0 0x11006000 0 0x1000>;
	#pwm-cells = <2>;
	clocks = <&topckgen CLK_TOP_PWM_SEL>,
	<&pericfg CLK_PERI_PWM>,
	<&pericfg CLK_PERI_PWM1>,
	<&pericfg CLK_PERI_PWM2>,
	<&pericfg CLK_PERI_PWM3>,
	<&pericfg CLK_PERI_PWM4>,
	<&pericfg CLK_PERI_PWM5>;
	clock-names = "top", "main", "pwm1", "pwm2",
	"pwm3", "pwm4", "pwm5";
	status = "disabled";
	};

	i2c0: i2c@11007000 {
	compatible = "mediatek,mt7623-i2c",
	"mediatek,mt6577-i2c";
	reg = <0 0x11007000 0 0x70>,
	<0 0x11000200 0 0x80>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C0>,
	<&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main", "dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c1: i2c@11008000 {
	compatible = "mediatek,mt7623-i2c",
	"mediatek,mt6577-i2c";
	reg = <0 0x11008000 0 0x70>,
	<0 0x11000280 0 0x80>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C1>,
	<&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main", "dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c2: i2c@11009000 {
	compatible = "mediatek,mt7623-i2c",
	"mediatek,mt6577-i2c";
	reg = <0 0x11009000 0 0x70>,
	<0 0x11000300 0 0x80>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C2>,
	<&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main", "dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi0: spi@1100a000 {
	compatible = "mediatek,mt7623-spi",
	"mediatek,mt2701-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x1100a000 0 0x100>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	<&topckgen CLK_TOP_SPI0_SEL>,
	<&pericfg CLK_PERI_SPI0>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	thermal: thermal@1100b000 {
	#thermal-sensor-cells = <1>;
	compatible = "mediatek,mt7623-thermal",
	"mediatek,mt2701-thermal";
	reg = <0 0x1100b000 0 0x1000>;
	interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
	clock-names = "therm", "auxadc";
	resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
	reset-names = "therm";
	mediatek,auxadc = <&auxadc>;
	mediatek,apmixedsys = <&apmixedsys>;
	nvmem-cells = <&thermal_calibration_data>;
	nvmem-cell-names = "calibration-data";
	};

	btif: serial@1100c000 {
	compatible = "mediatek,mt7623-btif",
	"mediatek,mtk-btif";
	reg = <0 0x1100c000 0 0x1000>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_BTIF>;
	clock-names = "main";
	reg-shift = <2>;
	reg-io-width = <4>;
	status = "disabled";
	};

	nandc: nfi@1100d000 {
	compatible = "mediatek,mt7623-nfc",
	"mediatek,mt2701-nfc";
	reg = <0 0x1100d000 0 0x1000>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
	clocks = <&pericfg CLK_PERI_NFI>,
	<&pericfg CLK_PERI_NFI_PAD>;
	clock-names = "nfi_clk", "pad_clk";
	status = "disabled";
	ecc-engine = <&bch>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	bch: ecc@1100e000 {
	compatible = "mediatek,mt7623-ecc",
	"mediatek,mt2701-ecc";
	reg = <0 0x1100e000 0 0x1000>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_NFI_ECC>;
	clock-names = "nfiecc_clk";
	status = "disabled";
	};

	nor_flash: spi@11014000 {
	compatible = "mediatek,mt7623-nor",
	"mediatek,mt8173-nor";
	reg = <0 0x11014000 0 0x1000>;
	clocks = <&pericfg CLK_PERI_FLASH>,
	<&topckgen CLK_TOP_FLASH_SEL>;
	clock-names = "spi", "sf";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi1: spi@11016000 {
	compatible = "mediatek,mt7623-spi",
	"mediatek,mt2701-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x11016000 0 0x100>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	<&topckgen CLK_TOP_SPI1_SEL>,
	<&pericfg CLK_PERI_SPI1>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	spi2: spi@11017000 {
	compatible = "mediatek,mt7623-spi",
	"mediatek,mt2701-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x11017000 0 0x1000>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	<&topckgen CLK_TOP_SPI2_SEL>,
	<&pericfg CLK_PERI_SPI2>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	audsys: clock-controller@11220000 {
	compatible = "mediatek,mt7623-audsys",
	"mediatek,mt2701-audsys",
	"syscon";
	reg = <0 0x11220000 0 0x2000>;
	#clock-cells = <1>;

	afe: audio-controller {
	compatible = "mediatek,mt7623-audio",
	"mediatek,mt2701-audio";
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
	interrupt-names = "afe", "asys";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;

	clocks = <&infracfg CLK_INFRA_AUDIO>,
	<&topckgen CLK_TOP_AUD_MUX1_SEL>,
	<&topckgen CLK_TOP_AUD_MUX2_SEL>,
	<&topckgen CLK_TOP_AUD_48K_TIMING>,
	<&topckgen CLK_TOP_AUD_44K_TIMING>,
	<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
	<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
	<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
	<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
	<&audsys CLK_AUD_I2SO1>,
	<&audsys CLK_AUD_I2SO2>,
	<&audsys CLK_AUD_I2SO3>,
	<&audsys CLK_AUD_I2SO4>,
	<&audsys CLK_AUD_I2SIN1>,
	<&audsys CLK_AUD_I2SIN2>,
	<&audsys CLK_AUD_I2SIN3>,
	<&audsys CLK_AUD_I2SIN4>,
	<&audsys CLK_AUD_ASRCO1>,
	<&audsys CLK_AUD_ASRCO2>,
	<&audsys CLK_AUD_ASRCO3>,
	<&audsys CLK_AUD_ASRCO4>,
	<&audsys CLK_AUD_AFE>,
	<&audsys CLK_AUD_AFE_CONN>,
	<&audsys CLK_AUD_A1SYS>,
	<&audsys CLK_AUD_A2SYS>,
	<&audsys CLK_AUD_AFE_MRGIF>;

	clock-names = "infra_sys_audio_clk",
	"top_audio_mux1_sel",
	"top_audio_mux2_sel",
	"top_audio_a1sys_hp",
	"top_audio_a2sys_hp",
	"i2s0_src_sel",
	"i2s1_src_sel",
	"i2s2_src_sel",
	"i2s3_src_sel",
	"i2s0_src_div",
	"i2s1_src_div",
	"i2s2_src_div",
	"i2s3_src_div",
	"i2s0_mclk_en",
	"i2s1_mclk_en",
	"i2s2_mclk_en",
	"i2s3_mclk_en",
	"i2so0_hop_ck",
	"i2so1_hop_ck",
	"i2so2_hop_ck",
	"i2so3_hop_ck",
	"i2si0_hop_ck",
	"i2si1_hop_ck",
	"i2si2_hop_ck",
	"i2si3_hop_ck",
	"asrc0_out_ck",
	"asrc1_out_ck",
	"asrc2_out_ck",
	"asrc3_out_ck",
	"audio_afe_pd",
	"audio_afe_conn_pd",
	"audio_a1sys_pd",
	"audio_a2sys_pd",
	"audio_mrgif_pd";

	assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
	<&topckgen CLK_TOP_AUD_MUX2_SEL>,
	<&topckgen CLK_TOP_AUD_MUX1_DIV>,
	<&topckgen CLK_TOP_AUD_MUX2_DIV>;
	assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
	<&topckgen CLK_TOP_AUD2PLL_90M>;
	assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
	};
	};

	mmc0: mmc@11230000 {
	compatible = "mediatek,mt7623-mmc",
	"mediatek,mt2701-mmc";
	reg = <0 0x11230000 0 0x1000>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_MSDC30_0>,
	<&topckgen CLK_TOP_MSDC30_0_SEL>;
	clock-names = "source", "hclk";
	status = "disabled";
	};

	mmc1: mmc@11240000 {
	compatible = "mediatek,mt7623-mmc",
	"mediatek,mt2701-mmc";
	reg = <0 0x11240000 0 0x1000>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_MSDC30_1>,
	<&topckgen CLK_TOP_MSDC30_1_SEL>;
	clock-names = "source", "hclk";
	status = "disabled";
	};

	g3dsys: syscon@13000000 {
	compatible = "mediatek,mt7623-g3dsys",
	"mediatek,mt2701-g3dsys",
	"syscon";
	reg = <0 0x13000000 0 0x200>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	mmsys: syscon@14000000 {
	compatible = "mediatek,mt7623-mmsys",
	"mediatek,mt2701-mmsys",
	"syscon";
	reg = <0 0x14000000 0 0x1000>;
	#clock-cells = <1>;
	};

	larb0: larb@14010000 {
	compatible = "mediatek,mt7623-smi-larb",
	"mediatek,mt2701-smi-larb";
	reg = <0 0x14010000 0 0x1000>;
	mediatek,smi = <&smi_common>;
	mediatek,larb-id = <0>;
	clocks = <&mmsys CLK_MM_SMI_LARB0>,
	<&mmsys CLK_MM_SMI_LARB0>;
	clock-names = "apb", "smi";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	};

	imgsys: syscon@15000000 {
	compatible = "mediatek,mt7623-imgsys",
	"mediatek,mt2701-imgsys",
	"syscon";
	reg = <0 0x15000000 0 0x1000>;
	#clock-cells = <1>;
	};

	larb2: larb@15001000 {
	compatible = "mediatek,mt7623-smi-larb",
	"mediatek,mt2701-smi-larb";
	reg = <0 0x15001000 0 0x1000>;
	mediatek,smi = <&smi_common>;
	mediatek,larb-id = <2>;
	clocks = <&imgsys CLK_IMG_SMI_COMM>,
	<&imgsys CLK_IMG_SMI_COMM>;
	clock-names = "apb", "smi";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
	};

	jpegdec: jpegdec@15004000 {
	compatible = "mediatek,mt7623-jpgdec",
	"mediatek,mt2701-jpgdec";
	reg = <0 0x15004000 0 0x1000>;
	interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
	<&imgsys CLK_IMG_JPGDEC>;
	clock-names = "jpgdec-smi",
	"jpgdec";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
	mediatek,larb = <&larb2>;
	iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
	<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
	};

	vdecsys: syscon@16000000 {
	compatible = "mediatek,mt7623-vdecsys",
	"mediatek,mt2701-vdecsys",
	"syscon";
	reg = <0 0x16000000 0 0x1000>;
	#clock-cells = <1>;
	};

	larb1: larb@16010000 {
	compatible = "mediatek,mt7623-smi-larb",
	"mediatek,mt2701-smi-larb";
	reg = <0 0x16010000 0 0x1000>;
	mediatek,smi = <&smi_common>;
	mediatek,larb-id = <1>;
	clocks = <&vdecsys CLK_VDEC_CKGEN>,
	<&vdecsys CLK_VDEC_LARB>;
	clock-names = "apb", "smi";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
	};

	hifsys: syscon@1a000000 {
	compatible = "mediatek,mt7623-hifsys",
	"mediatek,mt2701-hifsys",
	"syscon";
	reg = <0 0x1a000000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pcie: pcie@1a140000 {
	compatible = "mediatek,mt7623-pcie";
	device_type = "pci";
	reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
	<0 0x1a142000 0 0x1000>, /* Port0 registers */
	<0 0x1a143000 0 0x1000>, /* Port1 registers */
	<0 0x1a144000 0 0x1000>; /* Port2 registers */
	reg-names = "subsys", "port0", "port1", "port2";
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0xf800 0 0 0>;
	interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
	<0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
	<0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
	<&hifsys CLK_HIFSYS_PCIE0>,
	<&hifsys CLK_HIFSYS_PCIE1>,
	<&hifsys CLK_HIFSYS_PCIE2>;
	clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
	resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
	<&hifsys MT2701_HIFSYS_PCIE1_RST>,
	<&hifsys MT2701_HIFSYS_PCIE2_RST>;
	reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
	phys = <&pcie0_port PHY_TYPE_PCIE>,
	<&pcie1_port PHY_TYPE_PCIE>,
	<&u3port1 PHY_TYPE_PCIE>;
	phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
	bus-range = <0x00 0xff>;
	status = "disabled";
	ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
	0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;

	pcie@0,0 {
	reg = <0x0000 0 0 0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
	ranges;
	status = "disabled";
	};

	pcie@1,0 {
	reg = <0x0800 0 0 0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
	ranges;
	status = "disabled";
	};

	pcie@2,0 {
	reg = <0x1000 0 0 0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
	ranges;
	status = "disabled";
	};
	};

	pcie0_phy: pcie-phy@1a149000 {
	compatible = "mediatek,generic-tphy-v1";
	reg = <0 0x1a149000 0 0x0700>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "disabled";

	pcie0_port: pcie-phy@1a149900 {
	reg = <0 0x1a149900 0 0x0700>;
	clocks = <&clk26m>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};
	};

	pcie1_phy: pcie-phy@1a14a000 {
	compatible = "mediatek,generic-tphy-v1";
	reg = <0 0x1a14a000 0 0x0700>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "disabled";

	pcie1_port: pcie-phy@1a14a900 {
	reg = <0 0x1a14a900 0 0x0700>;
	clocks = <&clk26m>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};
	};

	usb1: usb@1a1c0000 {
	compatible = "mediatek,mt7623-xhci",
	"mediatek,mt8173-xhci";
	reg = <0 0x1a1c0000 0 0x1000>,
	<0 0x1a1c4700 0 0x0100>;
	reg-names = "mac", "ippc";
	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
	<&topckgen CLK_TOP_ETHIF_SEL>;
	clock-names = "sys_ck", "ref_ck";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
	phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
	status = "disabled";
	};

	u3phy1: usb-phy@1a1c4000 {
	compatible = "mediatek,mt7623-u3phy",
	"mediatek,mt2701-u3phy";
	reg = <0 0x1a1c4000 0 0x0700>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "disabled";

	u2port0: usb-phy@1a1c4800 {
	reg = <0 0x1a1c4800 0 0x0100>;
	clocks = <&topckgen CLK_TOP_USB_PHY48M>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};

	u3port0: usb-phy@1a1c4900 {
	reg = <0 0x1a1c4900 0 0x0700>;
	clocks = <&clk26m>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};
	};

	usb2: usb@1a240000 {
	compatible = "mediatek,mt7623-xhci",
	"mediatek,mt8173-xhci";
	reg = <0 0x1a240000 0 0x1000>,
	<0 0x1a244700 0 0x0100>;
	reg-names = "mac", "ippc";
	interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
	<&topckgen CLK_TOP_ETHIF_SEL>;
	clock-names = "sys_ck", "ref_ck";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
	phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
	status = "disabled";
	};

	u3phy2: usb-phy@1a244000 {
	compatible = "mediatek,mt7623-u3phy",
	"mediatek,mt2701-u3phy";
	reg = <0 0x1a244000 0 0x0700>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "disabled";

	u2port1: usb-phy@1a244800 {
	reg = <0 0x1a244800 0 0x0100>;
	clocks = <&topckgen CLK_TOP_USB_PHY48M>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};

	u3port1: usb-phy@1a244900 {
	reg = <0 0x1a244900 0 0x0700>;
	clocks = <&clk26m>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};
	};

	ethsys: syscon@1b000000 {
	compatible = "mediatek,mt7623-ethsys",
	"mediatek,mt2701-ethsys",
	"syscon";
	reg = <0 0x1b000000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	hsdma: dma-controller@1b007000 {
	compatible = "mediatek,mt7623-hsdma";
	reg = <0 0x1b007000 0 0x1000>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&ethsys CLK_ETHSYS_HSDMA>;
	clock-names = "hsdma";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
	#dma-cells = <1>;
	};

	eth: ethernet@1b100000 {
	compatible = "mediatek,mt7623-eth",
	"mediatek,mt2701-eth",
	"syscon";
	reg = <0 0x1b100000 0 0x20000>;
	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
	<&ethsys CLK_ETHSYS_ESW>,
	<&ethsys CLK_ETHSYS_GP1>,
	<&ethsys CLK_ETHSYS_GP2>,
	<&apmixedsys CLK_APMIXED_TRGPLL>;
	clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
	resets = <&ethsys MT2701_ETHSYS_FE_RST>,
	<&ethsys MT2701_ETHSYS_GMAC_RST>,
	<&ethsys MT2701_ETHSYS_PPE_RST>;
	reset-names = "fe", "gmac", "ppe";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
	mediatek,ethsys = <&ethsys>;
	mediatek,pctl = <&syscfg_pctl_a>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	crypto: crypto@1b240000 {
	compatible = "mediatek,eip97-crypto";
	reg = <0 0x1b240000 0 0x20000>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
	clock-names = "cryp";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
	status = "disabled";
	};

	bdpsys: syscon@1c000000 {
	compatible = "mediatek,mt7623-bdpsys",
	"mediatek,mt2701-bdpsys",
	"syscon";
	reg = <0 0x1c000000 0 0x1000>;
	#clock-cells = <1>;
	};
	};

	&pio {
	cir_pins_a:cir-default {
	pins-cir {
	pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
	bias-disable;
	};
	};

	i2c0_pins_a: i2c0-default {
	pins-i2c0 {
	pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
	<MT7623_PIN_76_SCL0_FUNC_SCL0>;
	bias-disable;
	};
	};

	i2c1_pins_a: i2c1-default {
	pin-i2c1 {
	pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
	<MT7623_PIN_58_SCL1_FUNC_SCL1>;
	bias-disable;
	};
	};

	i2c1_pins_b: i2c1-alt {
	pin-i2c1 {
	pinmux = <MT7623_PIN_242_URTS2_FUNC_SCL1>,
	<MT7623_PIN_243_UCTS2_FUNC_SDA1>;
	bias-disable;
	};
	};

	i2c2_pins_a: i2c2-default {
	pin-i2c2 {
	pinmux = <MT7623_PIN_77_SDA2_FUNC_SDA2>,
	<MT7623_PIN_78_SCL2_FUNC_SCL2>;
	bias-disable;
	};
	};

	i2c2_pins_b: i2c2-alt {
	pin-i2c2 {
	pinmux = <MT7623_PIN_122_GPIO122_FUNC_SDA2>,
	<MT7623_PIN_123_HTPLG_FUNC_SCL2>;
	bias-disable;
	};
	};

	i2s0_pins_a: i2s0-default {
	pin-i2s0 {
	pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
	<MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
	<MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
	<MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
	<MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
	drive-strength = <MTK_DRIVE_12mA>;
	bias-pull-down;
	};
	};

	i2s1_pins_a: i2s1-default {
	pin-i2s1 {
	pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
	<MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
	<MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
	<MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
	<MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
	drive-strength = <MTK_DRIVE_12mA>;
	bias-pull-down;
	};
	};

	key_pins_a: keys-alt {
	pins-keys {
	pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
	<MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
	input-enable;
	};
	};

	led_pins_a: leds-alt {
	pins-leds {
	pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
	<MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
	<MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
	};
	};

	mmc0_pins_default: mmc0default {
	pins-cmd-dat {
	pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
	<MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
	<MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
	<MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
	<MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
	<MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
	<MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
	<MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
	<MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
	input-enable;
	bias-pull-up;
	};

	pins-clk {
	pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
	bias-pull-down;
	};

	pins-rst {
	pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
	bias-pull-up;
	};
	};

	mmc0_pins_uhs: mmc0 {
	pins-cmd-dat {
	pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
	<MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
	<MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
	<MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
	<MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
	<MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
	<MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
	<MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
	<MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
	input-enable;
	drive-strength = <MTK_DRIVE_2mA>;
	bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
	};

	pins-clk {
	pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
	drive-strength = <MTK_DRIVE_2mA>;
	bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
	};

	pins-rst {
	pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
	bias-pull-up;
	};
	};

	mmc1_pins_default: mmc1default {
	pins-cmd-dat {
	pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
	<MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
	<MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
	<MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
	<MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
	input-enable;
	drive-strength = <MTK_DRIVE_4mA>;
	bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
	};

	pins-clk {
	pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
	bias-pull-down;
	drive-strength = <MTK_DRIVE_4mA>;
	};

	pins-wp {
	pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
	input-enable;
	bias-pull-up;
	};

	pins-insert {
	pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
	bias-pull-up;
	};
	};

	mmc1_pins_uhs: mmc1 {
	pins-cmd-dat {
	pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
	<MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
	<MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
	<MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
	<MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
	input-enable;
	drive-strength = <MTK_DRIVE_4mA>;
	bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
	};

	pins-clk {
	pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
	drive-strength = <MTK_DRIVE_4mA>;
	bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
	};
	};

	nand_pins_default: nanddefault {
	pins-ale {
	pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
	drive-strength = <MTK_DRIVE_8mA>;
	bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
	};

	pins-dat {
	pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
	<MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
	<MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
	<MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
	<MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
	<MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
	<MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
	<MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
	<MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
	input-enable;
	drive-strength = <MTK_DRIVE_8mA>;
	bias-pull-up;
	};

	pins-we {
	pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
	drive-strength = <MTK_DRIVE_8mA>;
	bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
	};
	};

	pcie_default: pcie_pin_default {
	pins_cmd_dat {
	pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
	<MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
	bias-disable;
	};
	};

	pwm_pins_a: pwm-default {
	pins-pwm {
	pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
	<MT7623_PIN_204_PWM1_FUNC_PWM1>,
	<MT7623_PIN_205_PWM2_FUNC_PWM2>,
	<MT7623_PIN_206_PWM3_FUNC_PWM3>,
	<MT7623_PIN_207_PWM4_FUNC_PWM4>;
	};
	};

	spi0_pins_a: spi0-default {
	pins-spi {
	pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
	<MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
	<MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
	<MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
	bias-disable;
	};
	};

	spi1_pins_a: spi1-default {
	pins-spi {
	pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>,
	<MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>,
	<MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>,
	<MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>;
	};
	};

	spi2_pins_a: spi2-default {
	pins-spi {
	pinmux = <MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS>,
	<MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK>,
	<MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI>,
	<MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO>;
	};
	};

	uart0_pins_a: uart0-default {
	pins-dat {
	pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
	<MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
	};
	};

	uart1_pins_a: uart1-default {
	pins-dat {
	pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
	<MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
	};
	};

	uart2_pins_a: uart2-default {
	pins-dat {
	pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
	<MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
	};
	};

	uart2_pins_b: uart2-alt {
	pins-dat {
	pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
	<MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/mt7629.dtsi b/sys/gnu/dts/arm/mt7629.dtsi
	index 867b88103b9d..5cbb3d244c75 100644
	--- a/sys/gnu/dts/arm/mt7629.dtsi
	+++ b/sys/gnu/dts/arm/mt7629.dtsi
	@@ -1,479 +1,493 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Copyright (c) 2019 MediaTek Inc.
	*
	* Author: Ryder Lee <ryder.lee@mediatek.com>
	*/

	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/mt7629-clk.h>
	#include <dt-bindings/power/mt7622-power.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/phy/phy.h>
	#include <dt-bindings/reset/mt7629-resets.h>

	/ {
	compatible = "mediatek,mt7629";
	interrupt-parent = <&sysirq>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "mediatek,mt6589-smp";

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x0>;
	clock-frequency = <1250000000>;
	cci-control-port = <&cci_control2>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x1>;
	clock-frequency = <1250000000>;
	cci-control-port = <&cci_control2>;
	};
	};

	pmu {
	compatible = "arm,cortex-a7-pmu";
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
	interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	clk20m: oscillator-0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <20000000>;
	clock-output-names = "clk20m";
	};

	clk40m: oscillator-1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <40000000>;
	clock-output-names = "clkxtal";
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupt-parent = <&gic>;
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	clock-frequency = <20000000>;
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	infracfg: syscon@10000000 {
	compatible = "mediatek,mt7629-infracfg", "syscon";
	reg = <0x10000000 0x1000>;
	#clock-cells = <1>;
	};

	pericfg: syscon@10002000 {
	compatible = "mediatek,mt7629-pericfg", "syscon";
	reg = <0x10002000 0x1000>;
	#clock-cells = <1>;
	};

	- scpsys: scpsys@10006000 {
	+ scpsys: power-controller@10006000 {
	compatible = "mediatek,mt7629-scpsys",
	"mediatek,mt7622-scpsys";
	#power-domain-cells = <1>;
	reg = <0x10006000 0x1000>;
	clocks = <&topckgen CLK_TOP_HIF_SEL>;
	clock-names = "hif_sel";
	assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
	infracfg = <&infracfg>;
	};

	timer: timer@10009000 {
	compatible = "mediatek,mt7629-timer",
	"mediatek,mt6765-timer";
	reg = <0x10009000 0x60>;
	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk20m>;
	clock-names = "clk20m";
	};

	sysirq: interrupt-controller@10200a80 {
	compatible = "mediatek,mt7629-sysirq",
	"mediatek,mt6577-sysirq";
	reg = <0x10200a80 0x20>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	};

	apmixedsys: syscon@10209000 {
	compatible = "mediatek,mt7629-apmixedsys", "syscon";
	reg = <0x10209000 0x1000>;
	#clock-cells = <1>;
	};

	rng: rng@1020f000 {
	compatible = "mediatek,mt7629-rng",
	"mediatek,mt7623-rng";
	reg = <0x1020f000 0x100>;
	clocks = <&infracfg CLK_INFRA_TRNG_PD>;
	clock-names = "rng";
	};

	topckgen: syscon@10210000 {
	compatible = "mediatek,mt7629-topckgen", "syscon";
	reg = <0x10210000 0x1000>;
	#clock-cells = <1>;
	};

	watchdog: watchdog@10212000 {
	compatible = "mediatek,mt7629-wdt",
	"mediatek,mt6589-wdt";
	reg = <0x10212000 0x100>;
	};

	pio: pinctrl@10217000 {
	compatible = "mediatek,mt7629-pinctrl";
	reg = <0x10217000 0x8000>,
	<0x10005000 0x1000>;
	reg-names = "base", "eint";
	gpio-controller;
	gpio-ranges = <&pio 0 0 79>;
	#gpio-cells = <2>;
	#interrupt-cells = <2>;
	interrupt-controller;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-parent = <&gic>;
	};

	gic: interrupt-controller@10300000 {
	compatible = "arm,gic-400";
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	reg = <0x10310000 0x1000>,
	<0x10320000 0x1000>,
	<0x10340000 0x2000>,
	<0x10360000 0x2000>;
	};

	cci: cci@10390000 {
	compatible = "arm,cci-400";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x10390000 0x1000>;
	ranges = <0 0x10390000 0x10000>;

	cci_control0: slave-if@1000 {
	compatible = "arm,cci-400-ctrl-if";
	interface-type = "ace-lite";
	reg = <0x1000 0x1000>;
	};

	cci_control1: slave-if@4000 {
	compatible = "arm,cci-400-ctrl-if";
	interface-type = "ace";
	reg = <0x4000 0x1000>;
	};

	cci_control2: slave-if@5000 {
	compatible = "arm,cci-400-ctrl-if";
	interface-type = "ace";
	reg = <0x5000 0x1000>;
	};

	pmu@9000 {
	compatible = "arm,cci-400-pmu,r1";
	reg = <0x9000 0x5000>;
	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	uart0: serial@11002000 {
	compatible = "mediatek,mt7629-uart",
	"mediatek,mt6577-uart";
	reg = <0x11002000 0x400>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_UART_SEL>,
	<&pericfg CLK_PERI_UART0_PD>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart1: serial@11003000 {
	compatible = "mediatek,mt7629-uart",
	"mediatek,mt6577-uart";
	reg = <0x11003000 0x400>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_UART_SEL>,
	<&pericfg CLK_PERI_UART1_PD>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart2: serial@11004000 {
	compatible = "mediatek,mt7629-uart",
	"mediatek,mt6577-uart";
	reg = <0x11004000 0x400>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_UART_SEL>,
	<&pericfg CLK_PERI_UART2_PD>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	+ pwm: pwm@11006000 {
	+ compatible = "mediatek,mt7629-pwm";
	+ reg = <0x11006000 0x1000>;
	+ #pwm-cells = <2>;
	+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
	+ <&pericfg CLK_PERI_PWM_PD>,
	+ <&pericfg CLK_PERI_PWM1_PD>;
	+ clock-names = "top", "main", "pwm1";
	+ assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
	+ assigned-clock-parents =
	+ <&topckgen CLK_TOP_UNIVPLL2_D4>;
	+ status = "disabled";
	+ };
	+
	i2c: i2c@11007000 {
	compatible = "mediatek,mt7629-i2c",
	"mediatek,mt2712-i2c";
	reg = <0x11007000 0x90>,
	<0x11000100 0x80>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <4>;
	clocks = <&pericfg CLK_PERI_I2C0_PD>,
	<&pericfg CLK_PERI_AP_DMA_PD>;
	clock-names = "main", "dma";
	assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi: spi@1100a000 {
	compatible = "mediatek,mt7629-spi",
	"mediatek,mt7622-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x1100a000 0x100>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	<&topckgen CLK_TOP_SPI0_SEL>,
	<&pericfg CLK_PERI_SPI0_PD>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	qspi: spi@11014000 {
	compatible = "mediatek,mt7629-nor",
	"mediatek,mt8173-nor";
	reg = <0x11014000 0xe0>;
	clocks = <&pericfg CLK_PERI_FLASH_PD>,
	<&topckgen CLK_TOP_FLASH_SEL>;
	clock-names = "spi", "sf";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	ssusbsys: syscon@1a000000 {
	compatible = "mediatek,mt7629-ssusbsys", "syscon";
	reg = <0x1a000000 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	ssusb: usb@1a0c0000 {
	compatible = "mediatek,mt7629-xhci",
	"mediatek,mtk-xhci";
	reg = <0x1a0c0000 0x01000>,
	<0x1a0c3e00 0x0100>;
	reg-names = "mac", "ippc";
	interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
	<&ssusbsys CLK_SSUSB_REF_EN>,
	<&ssusbsys CLK_SSUSB_MCU_EN>,
	<&ssusbsys CLK_SSUSB_DMA_EN>;
	clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
	assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
	<&topckgen CLK_TOP_SATA_SEL>,
	<&topckgen CLK_TOP_HIF_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
	<&topckgen CLK_TOP_UNIVPLL2_D4>,
	<&topckgen CLK_TOP_UNIVPLL1_D2>;
	power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
	phys = <&u2port0 PHY_TYPE_USB2>,
	<&u3port0 PHY_TYPE_USB3>;
	status = "disabled";
	};

	u3phy0: usb-phy@1a0c4000 {
	compatible = "mediatek,generic-tphy-v2";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x1a0c4000 0xe00>;
	status = "disabled";

	u2port0: usb-phy@0 {
	reg = <0 0x700>;
	clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};

	u3port0: usb-phy@700 {
	reg = <0x700 0x700>;
	clocks = <&clk20m>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};
	};

	pciesys: syscon@1a100800 {
	compatible = "mediatek,mt7629-pciesys", "syscon";
	reg = <0x1a100800 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pcie: pcie@1a140000 {
	compatible = "mediatek,mt7629-pcie";
	device_type = "pci";
	reg = <0x1a140000 0x1000>,
	<0x1a145000 0x1000>;
	reg-names = "subsys","port1";
	#address-cells = <3>;
	#size-cells = <2>;
	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
	<&pciesys CLK_PCIE_P0_AHB_EN>,
	<&pciesys CLK_PCIE_P1_AUX_EN>,
	<&pciesys CLK_PCIE_P1_AXI_EN>,
	<&pciesys CLK_PCIE_P1_OBFF_EN>,
	<&pciesys CLK_PCIE_P1_PIPE_EN>;
	clock-names = "sys_ck1", "ahb_ck1",
	"aux_ck1", "axi_ck1",
	"obff_ck1", "pipe_ck1";
	assigned-clocks = <&topckgen CLK_TOP_SATA_SEL>,
	<&topckgen CLK_TOP_AXI_SEL>,
	<&topckgen CLK_TOP_HIF_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
	<&topckgen CLK_TOP_SYSPLL1_D2>,
	<&topckgen CLK_TOP_UNIVPLL1_D2>;
	phys = <&pcieport1 PHY_TYPE_PCIE>;
	phy-names = "pcie-phy1";
	power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
	bus-range = <0x00 0xff>;
	ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;

	pcie1: pcie@1,0 {
	device_type = "pci";
	reg = <0x0800 0 0 0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges;
	num-lanes = <1>;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0 0 0 1 &pcie_intc1 0>,
	<0 0 0 2 &pcie_intc1 1>,
	<0 0 0 3 &pcie_intc1 2>,
	<0 0 0 4 &pcie_intc1 3>;

	pcie_intc1: interrupt-controller {
	interrupt-controller;
	#address-cells = <0>;
	#interrupt-cells = <1>;
	};
	};
	};

	pciephy1: pcie-phy@1a14a000 {
	compatible = "mediatek,generic-tphy-v2";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x1a14a000 0x1000>;
	status = "disabled";

	pcieport1: port1phy@0 {
	reg = <0 0x1000>;
	clocks = <&clk20m>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};
	};

	ethsys: syscon@1b000000 {
	compatible = "mediatek,mt7629-ethsys", "syscon";
	reg = <0x1b000000 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	eth: ethernet@1b100000 {
	compatible = "mediatek,mt7629-eth","syscon";
	reg = <0x1b100000 0x20000>;
	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_ETH_SEL>,
	<&topckgen CLK_TOP_F10M_REF_SEL>,
	<&ethsys CLK_ETH_ESW_EN>,
	<&ethsys CLK_ETH_GP0_EN>,
	<&ethsys CLK_ETH_GP1_EN>,
	<&ethsys CLK_ETH_GP2_EN>,
	<&ethsys CLK_ETH_FE_EN>,
	<&sgmiisys0 CLK_SGMII_TX_EN>,
	<&sgmiisys0 CLK_SGMII_RX_EN>,
	<&sgmiisys0 CLK_SGMII_CDR_REF>,
	<&sgmiisys0 CLK_SGMII_CDR_FB>,
	<&sgmiisys1 CLK_SGMII_TX_EN>,
	<&sgmiisys1 CLK_SGMII_RX_EN>,
	<&sgmiisys1 CLK_SGMII_CDR_REF>,
	<&sgmiisys1 CLK_SGMII_CDR_FB>,
	<&apmixedsys CLK_APMIXED_SGMIPLL>,
	<&apmixedsys CLK_APMIXED_ETH2PLL>;
	clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1",
	"gp2", "fe", "sgmii_tx250m", "sgmii_rx250m",
	"sgmii_cdr_ref", "sgmii_cdr_fb",
	"sgmii2_tx250m", "sgmii2_rx250m",
	"sgmii2_cdr_ref", "sgmii2_cdr_fb",
	"sgmii_ck", "eth2pll";
	assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
	<&topckgen CLK_TOP_F10M_REF_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
	<&topckgen CLK_TOP_SGMIIPLL_D2>;
	power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
	mediatek,ethsys = <&ethsys>;
	mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
	mediatek,infracfg = <&infracfg>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	sgmiisys0: syscon@1b128000 {
	compatible = "mediatek,mt7629-sgmiisys", "syscon";
	reg = <0x1b128000 0x3000>;
	#clock-cells = <1>;
	};

	sgmiisys1: syscon@1b130000 {
	compatible = "mediatek,mt7629-sgmiisys", "syscon";
	reg = <0x1b130000 0x3000>;
	#clock-cells = <1>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/omap3-n950-n9.dtsi b/sys/gnu/dts/arm/omap3-n950-n9.dtsi
	index a075b63f3087..11d41e86f814 100644
	--- a/sys/gnu/dts/arm/omap3-n950-n9.dtsi
	+++ b/sys/gnu/dts/arm/omap3-n950-n9.dtsi
	@@ -1,491 +1,496 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff)
	*
	* Written by: Aaro Koskinen <aaro.koskinen@iki.fi>
	*/

	#include "omap36xx.dtsi"

	/ {
	cpus {
	cpu@0 {
	cpu0-supply = <&vcc>;
	};
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x40000000>; /* 1 GB */
	};

	vemmc: fixedregulator0 {
	compatible = "regulator-fixed";
	regulator-name = "VEMMC";
	regulator-min-microvolt = <2900000>;
	regulator-max-microvolt = <2900000>;
	gpio = <&gpio5 29 GPIO_ACTIVE_HIGH>; /* gpio line 157 */
	startup-delay-us = <150>;
	enable-active-high;
	};

	vwlan_fixed: fixedregulator2 {
	compatible = "regulator-fixed";
	regulator-name = "VWLAN";
	gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; /* gpio 35 */
	enable-active-high;
	};

	leds {
	compatible = "gpio-leds";

	heartbeat {
	label = "debug::sleep";
	gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; /* gpio92 */
	linux,default-trigger = "default-on";
	pinctrl-names = "default";
	pinctrl-0 = <&debug_leds>;
	};
	};

	/* controlled (enabled/disabled) directly by wl1271 */
	vctcxo: vctcxo {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <38400000>;
	};
	};

	&omap3_pmx_core {
	accelerator_pins: pinmux_accelerator_pins {
	pinctrl-single,pins = <
	OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT \| MUX_MODE4) /* mcspi2_somi.gpio_180 -> LIS302 INT1 */
	OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT \| MUX_MODE4) /* mcspi2_cs0.gpio_181 -> LIS302 INT2 */
	>;
	};

	debug_leds: pinmux_debug_led_pins {
	pinctrl-single,pins = <
	OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT \| MUX_MODE4) /* dss_data22.gpio_92 */
	>;
	};

	mmc2_pins: pinmux_mmc2_pins {
	pinctrl-single,pins = <
	OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc2_clk */
	OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc2_cmd */
	OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc2_dat0 */
	OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc2_dat1 */
	OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc2_dat2 */
	OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc2_dat3 */
	>;
	};

	wlan_pins: pinmux_wlan_pins {
	pinctrl-single,pins = <
	OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT \| MUX_MODE4) /* gpio 35 - wlan enable */
	OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT \| MUX_MODE4) /* gpio 42 - wlan irq */
	>;
	};

	ssi_pins: pinmux_ssi_pins {
	pinctrl-single,pins = <
	OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT \| MUX_MODE1) /* ssi1_dat_tx */
	OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT \| MUX_MODE1) /* ssi1_flag_tx */
	OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP \| MUX_MODE1) /* ssi1_rdy_tx */
	OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT \| MUX_MODE4) /* ssi1_wake_tx (cawake) */
	OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT \| MUX_MODE1) /* ssi1_dat_rx */
	OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT \| MUX_MODE1) /* ssi1_flag_rx */
	OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT \| MUX_MODE1) /* ssi1_rdy_rx */
	OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT \| MUX_MODE1) /* ssi1_wake */
	>;
	};

	ssi_pins_idle: pinmux_ssi_pins_idle {
	pinctrl-single,pins = <
	OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT \| MUX_MODE7) /* ssi1_dat_tx */
	OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT \| MUX_MODE7) /* ssi1_flag_tx */
	OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN \| MUX_MODE7) /* ssi1_rdy_tx */
	OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT \| MUX_MODE4) /* ssi1_wake_tx (cawake) */
	OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT \| MUX_MODE7) /* ssi1_dat_rx */
	OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT \| MUX_MODE7) /* ssi1_flag_rx */
	OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT \| MUX_MODE4) /* ssi1_rdy_rx */
	OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT \| MUX_MODE7) /* ssi1_wake */
	>;
	};

	modem_pins1: pinmux_modem_core1_pins {
	pinctrl-single,pins = <
	OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT \| MUX_MODE4) /* gpio_34 (ape_rst_rq) */
	OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT \| MUX_MODE4) /* gpio_88 (cmt_rst_rq) */
	OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT \| MUX_MODE4) /* gpio_93 (cmt_apeslpx) */
	>;
	};

	uart2_pins: pinmux_uart2_pins {
	pinctrl-single,pins = <
	OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP \| MUX_MODE0) /* uart2_cts */
	OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT \| MUX_MODE0) /* uart2_rts */
	OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT \| MUX_MODE0) /* uart2_tx */
	OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT \| MUX_MODE0) /* uart2_rx */
	>;
	};
	};

	&omap3_pmx_core2 {
	modem_pins2: pinmux_modem_core2_pins {
	pinctrl-single,pins = <
	OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT \| MUX_MODE4) /* gpio_23 (cmt_en) */
	>;
	};
	};

	&i2c1 {
	clock-frequency = <2900000>;

	twl: twl@48 {
	reg = <0x48>;
	interrupts = <7>; /* SYS_NIRQ cascaded to intc */
	interrupt-parent = <&intc>;
	};
	};

	/include/ "twl4030.dtsi"

	&twl {
	compatible = "ti,twl5031";

	twl_power: power {
	compatible = "ti,twl4030-power";
	ti,use_poweroff;
	};
	};

	&twl_gpio {
	ti,pullups = <0x000001>; /* BIT(0) */
	ti,pulldowns = <0x008106>; /* BIT(1) \| BIT(2) \| BIT(8) \| BIT(15) */
	};

	&vdac {
	regulator-name = "vdac";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	&vpll1 {
	regulator-name = "vpll1";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	&vpll2 {
	regulator-name = "vpll2";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	&vaux1 {
	regulator-name = "vaux1";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	/* CSI-2 receiver */
	&vaux2 {
	regulator-name = "vaux2";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	/* Cameras */
	&vaux3 {
	regulator-name = "vaux3";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	&vaux4 {
	regulator-name = "vaux4";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	&vmmc1 {
	regulator-name = "vmmc1";
	regulator-min-microvolt = <1850000>;
	regulator-max-microvolt = <3150000>;
	};

	&vmmc2 {
	regulator-name = "vmmc2";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	};

	&vintana1 {
	regulator-name = "vintana1";
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1500000>;
	};

	&vintana2 {
	regulator-name = "vintana2";
	regulator-min-microvolt = <2750000>;
	regulator-max-microvolt = <2750000>;
	};

	&vintdig {
	regulator-name = "vintdig";
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1500000>;
	};

	&vsim {
	regulator-name = "vsim";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	&vio {
	regulator-name = "vio";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	&i2c2 {
	clock-frequency = <400000>;

	as3645a@30 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x30>;
	compatible = "ams,as3645a";
	as3645a_flash: flash@0 {
	reg = <0x0>;
	flash-timeout-us = <150000>;
	flash-max-microamp = <320000>;
	led-max-microamp = <60000>;
	ams,input-max-microamp = <1750000>;
	};
	as3645a_indicator: indicator@1 {
	reg = <0x1>;
	led-max-microamp = <10000>;
	};
	};
	};

	&i2c3 {
	clock-frequency = <400000>;

	lis302: lis302@1d {
	compatible = "st,lis3lv02d";
	reg = <0x1d>;

	Vdd-supply = <&vaux1>;
	Vdd_IO-supply = <&vio>;

	pinctrl-names = "default";
	pinctrl-0 = <&accelerator_pins>;

	interrupts-extended = <&gpio6 20 IRQ_TYPE_EDGE_FALLING>, <&gpio6 21 IRQ_TYPE_EDGE_FALLING>; /* 180, 181 */

	/* click flags */
	st,click-single-x;
	st,click-single-y;
	st,click-single-z;

	/* Limits are 0.5g * value */
	st,click-threshold-x = <8>;
	st,click-threshold-y = <8>;
	st,click-threshold-z = <10>;

	/* Click must be longer than time limit */
	st,click-time-limit = <9>;

	/* Kind of debounce filter */
	st,click-latency = <50>;

	st,wakeup-x-hi;
	st,wakeup-y-hi;
	st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */

	st,wakeup2-z-hi;
	st,wakeup2-threshold = <(1000/18)>; /* millig-value / 18 to get HW values */

	st,highpass-cutoff-hz = <2>;

	/* Interrupt line 1 for thresholds */
	st,irq1-ff-wu-1;
	st,irq1-ff-wu-2;
	/* Interrupt line 2 for click detection */
	st,irq2-click;

	st,wu-duration-1 = <8>;
	st,wu-duration-2 = <8>;
	};
	};

	&mmc1 {
	status = "disabled";
	};

	&mmc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_pins>;
	vmmc-supply = <&vemmc>;
	bus-width = <4>;
	ti,non-removable;
	};

	&mmc3 {
	status = "disabled";
	};

	+/* RNG not directly accessible on N950/N9. */
	+&rng_target {
	+ status = "disabled";
	+};
	+
	&usb_otg_hs {
	interface-type = <0>;
	usb-phy = <&usb2_phy>;
	phys = <&usb2_phy>;
	phy-names = "usb2-phy";
	mode = <3>;
	power = <50>;
	};

	&gpmc {
	ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */

	onenand@0,0 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "ti,omap2-onenand";
	reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */

	/*
	* These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported
	* bootloader set values when booted with v4.19 using both N950
	* and N9 devices (OneNAND Manufacturer: Samsung):
	*
	* gpmc cs0 before gpmc_cs_program_settings:
	* cs0 GPMC_CS_CONFIG1: 0xfd001202
	* cs0 GPMC_CS_CONFIG2: 0x00181800
	* cs0 GPMC_CS_CONFIG3: 0x00030300
	* cs0 GPMC_CS_CONFIG4: 0x18001804
	* cs0 GPMC_CS_CONFIG5: 0x03171d1d
	* cs0 GPMC_CS_CONFIG6: 0x97080000
	*/
	gpmc,sync-read;
	gpmc,sync-write;
	gpmc,burst-length = <16>;
	gpmc,burst-read;
	gpmc,burst-wrap;
	gpmc,burst-write;
	gpmc,device-width = <2>;
	gpmc,mux-add-data = <2>;
	gpmc,cs-on-ns = <0>;
	gpmc,cs-rd-off-ns = <122>;
	gpmc,cs-wr-off-ns = <122>;
	gpmc,adv-on-ns = <0>;
	gpmc,adv-rd-off-ns = <15>;
	gpmc,adv-wr-off-ns = <15>;
	gpmc,oe-on-ns = <20>;
	gpmc,oe-off-ns = <122>;
	gpmc,we-on-ns = <0>;
	gpmc,we-off-ns = <122>;
	gpmc,rd-cycle-ns = <148>;
	gpmc,wr-cycle-ns = <148>;
	gpmc,access-ns = <117>;
	gpmc,page-burst-access-ns = <15>;
	gpmc,bus-turnaround-ns = <0>;
	gpmc,cycle2cycle-delay-ns = <0>;
	gpmc,wait-monitoring-ns = <0>;
	gpmc,clk-activation-ns = <10>;
	gpmc,wr-data-mux-bus-ns = <40>;
	gpmc,wr-access-ns = <117>;

	gpmc,sync-clk-ps = <15000>; /* TBC; Where this value came? */

	/*
	* MTD partition table corresponding to Nokia's MeeGo 1.2
	* Harmattan release.
	*/
	partition@0 {
	label = "bootloader";
	reg = <0x00000000 0x00100000>;
	};
	partition@1 {
	label = "config";
	reg = <0x00100000 0x002c0000>;
	};
	partition@2 {
	label = "kernel";
	reg = <0x003c0000 0x01000000>;
	};
	partition@3 {
	label = "log";
	reg = <0x013c0000 0x00200000>;
	};
	partition@4 {
	label = "var";
	reg = <0x015c0000 0x1ca40000>;
	};
	partition@5 {
	label = "moslo";
	reg = <0x1e000000 0x02000000>;
	};
	partition@6 {
	label = "omap2-onenand";
	reg = <0x00000000 0x20000000>;
	};
	};
	};

	&ssi_port1 {
	pinctrl-names = "default", "idle";
	pinctrl-0 = <&ssi_pins>;
	pinctrl-1 = <&ssi_pins_idle>;

	ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */

	modem: hsi-client {
	pinctrl-names = "default";
	pinctrl-0 = <&modem_pins1 &modem_pins2>;

	hsi-channel-ids = <0>, <1>, <2>, <3>;
	hsi-channel-names = "mcsaab-control",
	"speech-control",
	"speech-data",
	"mcsaab-data";
	hsi-speed-kbps = <96000>;
	hsi-mode = "frame";
	hsi-flow = "synchronized";
	hsi-arb-mode = "round-robin";

	interrupts-extended = <&gpio2 2 IRQ_TYPE_EDGE_RISING>; /* gpio 34 */

	gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>, /* gpio 93 */
	<&gpio3 24 GPIO_ACTIVE_HIGH>, /* gpio 88 */
	<&gpio1 23 GPIO_ACTIVE_HIGH>; /* gpio 23 */
	gpio-names = "cmt_apeslpx",
	"cmt_rst_rq",
	"cmt_en";
	};
	};

	&ssi_port2 {
	status = "disabled";
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;

	bluetooth {
	compatible = "ti,wl1271-bluetooth-nokia", "nokia,h4p-bluetooth";

	reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; /* 26 */
	host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */
	bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */

	clocks = <&vctcxo>;
	clock-names = "sysclk";
	};
	};
	diff --git a/sys/gnu/dts/arm/omap4-l4.dtsi b/sys/gnu/dts/arm/omap4-l4.dtsi
	index 459fd7027591..ef59e4e97d7c 100644
	--- a/sys/gnu/dts/arm/omap4-l4.dtsi
	+++ b/sys/gnu/dts/arm/omap4-l4.dtsi
	@@ -1,2473 +1,2474 @@
	// SPDX-License-Identifier: GPL-2.0
	&l4_cfg { /* 0x4a000000 */
	compatible = "ti,omap4-l4-cfg", "simple-bus";
	reg = <0x4a000000 0x800>,
	<0x4a000800 0x800>,
	<0x4a001000 0x1000>;
	reg-names = "ap", "la", "ia0";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
	<0x00080000 0x4a080000 0x080000>, /* segment 1 */
	<0x00100000 0x4a100000 0x080000>, /* segment 2 */
	<0x00180000 0x4a180000 0x080000>, /* segment 3 */
	<0x00200000 0x4a200000 0x080000>, /* segment 4 */
	<0x00280000 0x4a280000 0x080000>, /* segment 5 */
	<0x00300000 0x4a300000 0x080000>; /* segment 6 */

	segment@0 { /* 0x4a000000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
	<0x00001000 0x00001000 0x001000>, /* ap 1 */
	<0x00000800 0x00000800 0x000800>, /* ap 2 */
	<0x00002000 0x00002000 0x001000>, /* ap 3 */
	<0x00003000 0x00003000 0x001000>, /* ap 4 */
	<0x00004000 0x00004000 0x001000>, /* ap 5 */
	<0x00005000 0x00005000 0x001000>, /* ap 6 */
	<0x00056000 0x00056000 0x001000>, /* ap 7 */
	<0x00057000 0x00057000 0x001000>, /* ap 8 */
	<0x0005c000 0x0005c000 0x001000>, /* ap 9 */
	<0x00058000 0x00058000 0x004000>, /* ap 10 */
	<0x00062000 0x00062000 0x001000>, /* ap 11 */
	<0x00063000 0x00063000 0x001000>, /* ap 12 */
	<0x00008000 0x00008000 0x002000>, /* ap 23 */
	<0x0000a000 0x0000a000 0x001000>, /* ap 24 */
	<0x00066000 0x00066000 0x001000>, /* ap 25 */
	<0x00067000 0x00067000 0x001000>, /* ap 26 */
	<0x0005e000 0x0005e000 0x002000>, /* ap 80 */
	<0x00060000 0x00060000 0x001000>, /* ap 81 */
	<0x00064000 0x00064000 0x001000>, /* ap 86 */
	<0x00065000 0x00065000 0x001000>; /* ap 87 */

	target-module@2000 { /* 0x4a002000, ap 3 06.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	ti,hwmods = "ctrl_module_core";
	reg = <0x2000 0x4>,
	<0x2010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x2000 0x1000>;

	omap4_scm_core: scm@0 {
	compatible = "ti,omap4-scm-core", "simple-bus";
	reg = <0x0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x1000>;

	scm_conf: scm_conf@0 {
	compatible = "syscon";
	reg = <0x0 0x800>;
	#address-cells = <1>;
	#size-cells = <1>;
	};

	omap_control_usb2phy: control-phy@300 {
	compatible = "ti,control-phy-usb2";
	reg = <0x300 0x4>;
	reg-names = "power";
	};

	omap_control_usbotg: control-phy@33c {
	compatible = "ti,control-phy-otghs";
	reg = <0x33c 0x4>;
	reg-names = "otghs_control";
	};
	};
	};

	target-module@4000 { /* 0x4a004000, ap 5 02.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x4000 0x4>;
	reg-names = "rev";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4000 0x1000>;

	cm1: cm1@0 {
	compatible = "ti,omap4-cm1", "simple-bus";
	reg = <0x0 0x2000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x2000>;

	cm1_clocks: clocks {
	#address-cells = <1>;
	#size-cells = <0>;
	};

	cm1_clockdomains: clockdomains {
	};
	};
	};

	target-module@8000 { /* 0x4a008000, ap 23 32.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x8000 0x4>;
	reg-names = "rev";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x8000 0x2000>;

	cm2: cm2@0 {
	compatible = "ti,omap4-cm2", "simple-bus";
	reg = <0x0 0x2000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x2000>;

	cm2_clocks: clocks {
	#address-cells = <1>;
	#size-cells = <0>;
	};

	cm2_clockdomains: clockdomains {
	};
	};
	};

	target-module@56000 { /* 0x4a056000, ap 7 0a.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x56000 0x4>,
	<0x5602c 0x4>,
	<0x56028 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_EMUFREE \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */
	clocks = <&l3_dma_clkctrl OMAP4_DMA_SYSTEM_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x56000 0x1000>;

	sdma: dma-controller@0 {
	compatible = "ti,omap4430-sdma", "ti,omap-sdma";
	reg = <0x0 0x1000>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	dma-channels = <32>;
	dma-requests = <127>;
	};
	};

	target-module@58000 { /* 0x4a058000, ap 10 0e.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x58000 0x4>,
	<0x58010 0x4>,
	<0x58014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_EMUFREE \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
	clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x58000 0x5000>;

	hsi: hsi@0 {
	compatible = "ti,omap4-hsi";
	reg = <0x0 0x4000>,
	<0x5000 0x1000>;
	reg-names = "sys", "gdd";

	clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
	clock-names = "hsi_fck";

	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gdd_mpu";

	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x4000>;

	hsi_port1: hsi-port@2000 {
	compatible = "ti,omap4-hsi-port";
	reg = <0x2000 0x800>,
	<0x2800 0x800>;
	reg-names = "tx", "rx";
	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	};

	hsi_port2: hsi-port@3000 {
	compatible = "ti,omap4-hsi-port";
	reg = <0x3000 0x800>,
	<0x3800 0x800>;
	reg-names = "tx", "rx";
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
	};
	};
	};

	target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x5e000 0x2000>;
	};

	target-module@62000 { /* 0x4a062000, ap 11 16.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	ti,hwmods = "usb_tll_hs";
	reg = <0x62000 0x4>,
	<0x62010 0x4>,
	<0x62014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	/* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
	clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x62000 0x1000>;

	usbhstll: usbhstll@0 {
	compatible = "ti,usbhs-tll";
	reg = <0x0 0x1000>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	target-module@64000 { /* 0x4a064000, ap 86 1e.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	ti,hwmods = "usb_host_hs";
	reg = <0x64000 0x4>,
	<0x64010 0x4>,
	<0x64014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
	clocks = <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x64000 0x1000>;

	usbhshost: usbhshost@0 {
	compatible = "ti,usbhs-host";
	reg = <0x0 0x800>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x1000>;
	clocks = <&init_60m_fclk>,
	<&xclk60mhsp1_ck>,
	<&xclk60mhsp2_ck>;
	clock-names = "refclk_60m_int",
	"refclk_60m_ext_p1",
	"refclk_60m_ext_p2";

	usbhsohci: ohci@800 {
	compatible = "ti,ohci-omap3";
	reg = <0x800 0x400>;
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	remote-wakeup-connected;
	};

	usbhsehci: ehci@c00 {
	compatible = "ti,ehci-omap";
	reg = <0xc00 0x400>;
	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	};
	};
	};

	target-module@66000 { /* 0x4a066000, ap 25 26.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x66000 0x4>,
	<0x66010 0x4>,
	<0x66014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	/* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */
	clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
	clock-names = "fck";
	resets = <&prm_tesla 1>;
	reset-names = "rstctrl";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x66000 0x1000>;

	mmu_dsp: mmu@0 {
	compatible = "ti,omap4-iommu";
	reg = <0x0 0x100>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <0>;
	};
	};
	};

	segment@80000 { /* 0x4a080000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
	<0x0005a000 0x000da000 0x001000>, /* ap 14 */
	<0x0005b000 0x000db000 0x001000>, /* ap 15 */
	<0x0005c000 0x000dc000 0x001000>, /* ap 16 */
	<0x0005d000 0x000dd000 0x001000>, /* ap 17 */
	<0x0005e000 0x000de000 0x001000>, /* ap 18 */
	<0x00060000 0x000e0000 0x001000>, /* ap 19 */
	<0x00061000 0x000e1000 0x001000>, /* ap 20 */
	<0x00074000 0x000f4000 0x001000>, /* ap 27 */
	<0x00075000 0x000f5000 0x001000>, /* ap 28 */
	<0x00076000 0x000f6000 0x001000>, /* ap 29 */
	<0x00077000 0x000f7000 0x001000>, /* ap 30 */
	<0x00036000 0x000b6000 0x001000>, /* ap 69 */
	<0x00037000 0x000b7000 0x001000>, /* ap 70 */
	<0x0004d000 0x000cd000 0x001000>, /* ap 78 */
	<0x0004e000 0x000ce000 0x001000>, /* ap 79 */
	<0x00029000 0x000a9000 0x001000>, /* ap 82 */
	<0x0002a000 0x000aa000 0x001000>, /* ap 83 */
	<0x0002b000 0x000ab000 0x001000>, /* ap 84 */
	<0x0002c000 0x000ac000 0x001000>, /* ap 85 */
	<0x0002d000 0x000ad000 0x001000>, /* ap 88 */
	<0x0002e000 0x000ae000 0x001000>; /* ap 89 */

	target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x29000 0x1000>;
	};

	target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x2b400 0x4>,
	<0x2b404 0x4>,
	<0x2b408 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
	clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x2b000 0x1000>;

	usb_otg_hs: usb_otg_hs@0 {
	compatible = "ti,omap4-musb";
	reg = <0x0 0x7ff>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "mc", "dma";
	usb-phy = <&usb2_phy>;
	phys = <&usb2_phy>;
	phy-names = "usb2-phy";
	multipoint = <1>;
	num-eps = <16>;
	ram-bits = <12>;
	ctrl-module = <&omap_control_usbotg>;
	};
	};

	target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x2d000 0x4>,
	<0x2d010 0x4>,
	<0x2d014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
	clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x2d000 0x1000>;

	ocp2scp@0 {
	compatible = "ti,omap-ocp2scp";
	reg = <0x0 0x1f>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x1000>;
	usb2_phy: usb2phy@80 {
	compatible = "ti,omap-usb2";
	reg = <0x80 0x58>;
	ctrl-module = <&omap_control_usb2phy>;
	clocks = <&usb_phy_cm_clk32k>;
	clock-names = "wkupclk";
	#phy-cells = <0>;
	};
	};
	};

	/* d2d mdm */
	target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x36000 0x4>,
	<0x36010 0x4>,
	<0x36014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \| SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
	clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x36000 0x1000>;
	};

	/* d2d mpu */
	target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x4d000 0x4>,
	<0x4d010 0x4>,
	<0x4d014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \| SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
	clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4d000 0x1000>;
	};

	target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */
	compatible = "ti,sysc-omap4-sr", "ti,sysc";
	reg = <0x59038 0x4>;
	reg-names = "sysc";
	ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
	clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x59000 0x1000>;

	smartreflex_mpu: smartreflex@0 {
	compatible = "ti,omap4-smartreflex-mpu";
	reg = <0x0 0x80>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */
	compatible = "ti,sysc-omap4-sr", "ti,sysc";
	reg = <0x5b038 0x4>;
	reg-names = "sysc";
	ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
	clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x5b000 0x1000>;

	smartreflex_iva: smartreflex@0 {
	compatible = "ti,omap4-smartreflex-iva";
	reg = <0x0 0x80>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */
	compatible = "ti,sysc-omap4-sr", "ti,sysc";
	reg = <0x5d038 0x4>;
	reg-names = "sysc";
	ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
	clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x5d000 0x1000>;

	smartreflex_core: smartreflex@0 {
	compatible = "ti,omap4-smartreflex-core";
	reg = <0x0 0x80>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x60000 0x1000>;
	};

	target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x74000 0x4>,
	<0x74010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	/* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
	clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x74000 0x1000>;

	mailbox: mailbox@0 {
	compatible = "ti,omap4-mailbox";
	reg = <0x0 0x200>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	#mbox-cells = <1>;
	ti,mbox-num-users = <3>;
	ti,mbox-num-fifos = <8>;
	mbox_ipu: mbox_ipu {
	ti,mbox-tx = <0 0 0>;
	ti,mbox-rx = <1 0 0>;
	};
	mbox_dsp: mbox_dsp {
	ti,mbox-tx = <3 0 0>;
	ti,mbox-rx = <2 0 0>;
	};
	};
	};

	target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x76000 0x4>,
	<0x76010 0x4>,
	<0x76014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
	clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x76000 0x1000>;

	hwspinlock: spinlock@0 {
	compatible = "ti,omap4-hwspinlock";
	reg = <0x0 0x1000>;
	#hwlock-cells = <1>;
	};
	};
	};

	segment@100000 { /* 0x4a100000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */
	<0x00001000 0x00101000 0x001000>, /* ap 22 */
	<0x00002000 0x00102000 0x001000>, /* ap 61 */
	<0x00003000 0x00103000 0x001000>, /* ap 62 */
	<0x00008000 0x00108000 0x001000>, /* ap 63 */
	<0x00009000 0x00109000 0x001000>, /* ap 64 */
	<0x0000a000 0x0010a000 0x001000>, /* ap 65 */
	<0x0000b000 0x0010b000 0x001000>; /* ap 66 */

	target-module@0 { /* 0x4a100000, ap 21 2a.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	ti,hwmods = "ctrl_module_pad_core";
	reg = <0x0 0x4>,
	<0x10 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x1000>;

	omap4_pmx_core: pinmux@40 {
	compatible = "ti,omap4-padconf",
	"pinctrl-single";
	reg = <0x40 0x0196>;
	#address-cells = <1>;
	#size-cells = <0>;
	#pinctrl-cells = <1>;
	#interrupt-cells = <1>;
	interrupt-controller;
	pinctrl-single,register-width = <16>;
	pinctrl-single,function-mask = <0x7fff>;
	};

	omap4_padconf_global: omap4_padconf_global@5a0 {
	compatible = "syscon",
	"simple-bus";
	reg = <0x5a0 0x170>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x5a0 0x170>;

	pbias_regulator: pbias_regulator@60 {
	compatible = "ti,pbias-omap4", "ti,pbias-omap";
	reg = <0x60 0x4>;
	syscon = <&omap4_padconf_global>;
	pbias_mmc_reg: pbias_mmc_omap4 {
	regulator-name = "pbias_mmc_omap4";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3000000>;
	};
	};
	};
	};

	target-module@2000 { /* 0x4a102000, ap 61 3c.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x2000 0x1000>;
	};

	target-module@8000 { /* 0x4a108000, ap 63 62.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x8000 0x1000>;
	};

	target-module@a000 { /* 0x4a10a000, ap 65 50.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xa000 0x4>,
	<0xa010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-delay-us = <2>;
	/* Domains (V, P, C): core, cam_pwrdm, iss_clkdm */
	clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa000 0x1000>;

	/* No child device binding or driver in mainline */
	};
	};

	segment@180000 { /* 0x4a180000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	};

	segment@200000 { /* 0x4a200000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */
	<0x0001f000 0x0021f000 0x001000>, /* ap 32 */
	<0x0000a000 0x0020a000 0x001000>, /* ap 33 */
	<0x0000b000 0x0020b000 0x001000>, /* ap 34 */
	<0x00004000 0x00204000 0x001000>, /* ap 35 */
	<0x00005000 0x00205000 0x001000>, /* ap 36 */
	<0x00006000 0x00206000 0x001000>, /* ap 37 */
	<0x00007000 0x00207000 0x001000>, /* ap 38 */
	<0x00012000 0x00212000 0x001000>, /* ap 39 */
	<0x00013000 0x00213000 0x001000>, /* ap 40 */
	<0x0000c000 0x0020c000 0x001000>, /* ap 41 */
	<0x0000d000 0x0020d000 0x001000>, /* ap 42 */
	<0x00010000 0x00210000 0x001000>, /* ap 43 */
	<0x00011000 0x00211000 0x001000>, /* ap 44 */
	<0x00016000 0x00216000 0x001000>, /* ap 45 */
	<0x00017000 0x00217000 0x001000>, /* ap 46 */
	<0x00014000 0x00214000 0x001000>, /* ap 47 */
	<0x00015000 0x00215000 0x001000>, /* ap 48 */
	<0x00018000 0x00218000 0x001000>, /* ap 49 */
	<0x00019000 0x00219000 0x001000>, /* ap 50 */
	<0x00020000 0x00220000 0x001000>, /* ap 51 */
	<0x00021000 0x00221000 0x001000>, /* ap 52 */
	<0x00026000 0x00226000 0x001000>, /* ap 53 */
	<0x00027000 0x00227000 0x001000>, /* ap 54 */
	<0x00028000 0x00228000 0x001000>, /* ap 55 */
	<0x00029000 0x00229000 0x001000>, /* ap 56 */
	<0x0002a000 0x0022a000 0x001000>, /* ap 57 */
	<0x0002b000 0x0022b000 0x001000>, /* ap 58 */
	<0x0001c000 0x0021c000 0x001000>, /* ap 59 */
	<0x0001d000 0x0021d000 0x001000>; /* ap 60 */

	target-module@4000 { /* 0x4a204000, ap 35 42.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4000 0x1000>;
	};

	target-module@6000 { /* 0x4a206000, ap 37 4a.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x6000 0x1000>;
	};

	target-module@a000 { /* 0x4a20a000, ap 33 2c.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa000 0x1000>;
	};

	target-module@c000 { /* 0x4a20c000, ap 41 20.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xc000 0x1000>;
	};

	target-module@10000 { /* 0x4a210000, ap 43 52.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x10000 0x1000>;
	};

	target-module@12000 { /* 0x4a212000, ap 39 18.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x12000 0x1000>;
	};

	target-module@14000 { /* 0x4a214000, ap 47 30.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x14000 0x1000>;
	};

	target-module@16000 { /* 0x4a216000, ap 45 28.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x16000 0x1000>;
	};

	target-module@18000 { /* 0x4a218000, ap 49 38.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x18000 0x1000>;
	};

	target-module@1c000 { /* 0x4a21c000, ap 59 5a.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x1c000 0x1000>;
	};

	target-module@1e000 { /* 0x4a21e000, ap 31 10.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x1e000 0x1000>;
	};

	target-module@20000 { /* 0x4a220000, ap 51 40.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x20000 0x1000>;
	};

	target-module@26000 { /* 0x4a226000, ap 53 34.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x26000 0x1000>;
	};

	target-module@28000 { /* 0x4a228000, ap 55 2e.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x28000 0x1000>;
	};

	target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x2a000 0x1000>;
	};
	};

	segment@280000 { /* 0x4a280000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	};

	l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
	<0x00040000 0x00340000 0x001000>, /* ap 68 */
	<0x00020000 0x00320000 0x004000>, /* ap 71 */
	<0x00024000 0x00324000 0x002000>, /* ap 72 */
	<0x00026000 0x00326000 0x001000>, /* ap 73 */
	<0x00027000 0x00327000 0x001000>, /* ap 74 */
	<0x00028000 0x00328000 0x001000>, /* ap 75 */
	<0x00029000 0x00329000 0x001000>, /* ap 76 */
	<0x00030000 0x00330000 0x010000>, /* ap 77 */
	<0x0002a000 0x0032a000 0x002000>, /* ap 90 */
	<0x0002c000 0x0032c000 0x004000>; /* ap 91 */

	l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00000000 0x00020000>,
	<0x00020000 0x00020000 0x00004000>,
	<0x00024000 0x00024000 0x00002000>,
	<0x00026000 0x00026000 0x00001000>,
	<0x00027000 0x00027000 0x00001000>,
	<0x00028000 0x00028000 0x00001000>,
	<0x00029000 0x00029000 0x00001000>,
	<0x0002a000 0x0002a000 0x00002000>,
	<0x0002c000 0x0002c000 0x00004000>,
	<0x00030000 0x00030000 0x00010000>;
	};
	};
	};

	&l4_wkup { /* 0x4a300000 */
	compatible = "ti,omap4-l4-wkup", "simple-bus";
	reg = <0x4a300000 0x800>,
	<0x4a300800 0x800>,
	<0x4a301000 0x1000>;
	reg-names = "ap", "la", "ia0";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x4a300000 0x010000>, /* segment 0 */
	<0x00010000 0x4a310000 0x010000>, /* segment 1 */
	<0x00020000 0x4a320000 0x010000>; /* segment 2 */

	segment@0 { /* 0x4a300000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
	<0x00001000 0x00001000 0x001000>, /* ap 1 */
	<0x00000800 0x00000800 0x000800>, /* ap 2 */
	<0x00006000 0x00006000 0x002000>, /* ap 3 */
	<0x00008000 0x00008000 0x001000>, /* ap 4 */
	<0x0000a000 0x0000a000 0x001000>, /* ap 15 */
	<0x0000b000 0x0000b000 0x001000>, /* ap 16 */
	<0x00004000 0x00004000 0x001000>, /* ap 17 */
	<0x00005000 0x00005000 0x001000>, /* ap 18 */
	<0x0000c000 0x0000c000 0x001000>, /* ap 19 */
	<0x0000d000 0x0000d000 0x001000>; /* ap 20 */

	target-module@4000 { /* 0x4a304000, ap 17 24.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	ti,hwmods = "counter_32k";
	reg = <0x4000 0x4>,
	<0x4004 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>;
	/* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
	clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4000 0x1000>;

	counter32k: counter@0 {
	compatible = "ti,omap-counter32k";
	reg = <0x0 0x20>;
	};
	};

	target-module@6000 { /* 0x4a306000, ap 3 08.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x6000 0x4>;
	reg-names = "rev";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x6000 0x2000>;

	prm: prm@0 {
	compatible = "ti,omap4-prm", "simple-bus";
	reg = <0x0 0x2000>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x2000>;

	prm_clocks: clocks {
	#address-cells = <1>;
	#size-cells = <0>;
	};

	prm_clockdomains: clockdomains {
	};
	};
	};

	target-module@a000 { /* 0x4a30a000, ap 15 34.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xa000 0x4>;
	reg-names = "rev";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa000 0x1000>;

	scrm: scrm@0 {
	compatible = "ti,omap4-scrm";
	reg = <0x0 0x2000>;

	scrm_clocks: clocks {
	#address-cells = <1>;
	#size-cells = <0>;
	};

	scrm_clockdomains: clockdomains {
	};
	};
	};

	target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	ti,hwmods = "ctrl_module_wkup";
	reg = <0xc000 0x4>,
	<0xc010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xc000 0x1000>;

	omap4_scm_wkup: scm@c000 {
	compatible = "ti,omap4-scm-wkup";
	reg = <0xc000 0x1000>;
	};
	};
	};

	segment@10000 { /* 0x4a310000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
	<0x00001000 0x00011000 0x001000>, /* ap 6 */
	<0x00004000 0x00014000 0x001000>, /* ap 7 */
	<0x00005000 0x00015000 0x001000>, /* ap 8 */
	<0x00008000 0x00018000 0x001000>, /* ap 9 */
	<0x00009000 0x00019000 0x001000>, /* ap 10 */
	<0x0000c000 0x0001c000 0x001000>, /* ap 11 */
	<0x0000d000 0x0001d000 0x001000>, /* ap 12 */
	<0x0000e000 0x0001e000 0x001000>, /* ap 21 */
	<0x0000f000 0x0001f000 0x001000>; /* ap 22 */

	gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x0 0x4>,
	<0x10 0x4>,
	<0x114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
	clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>,
	<&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 8>;
	clock-names = "fck", "dbclk";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x1000>;

	gpio1: gpio@0 {
	compatible = "ti,omap4-gpio";
	reg = <0x0 0x200>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	ti,gpio-always-on;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	target-module@4000 { /* 0x4a314000, ap 7 18.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x4000 0x4>,
	<0x4010 0x4>,
	<0x4014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_EMUFREE \|
	SYSC_OMAP2_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
	clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4000 0x1000>;

	wdt2: wdt@0 {
	compatible = "ti,omap4-wdt", "ti,omap3-wdt";
	reg = <0x0 0x80>;
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	target-module@8000 { /* 0x4a318000, ap 9 1c.0 */
	compatible = "ti,sysc-omap2-timer", "ti,sysc";
	ti,hwmods = "timer1";
	reg = <0x8000 0x4>,
	<0x8010 0x4>,
	<0x8014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_EMUFREE \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
	clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x8000 0x1000>;

	timer1: timer@0 {
	compatible = "ti,omap3430-timer";
	reg = <0x0 0x80>;
	clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
	clock-names = "fck";
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	ti,timer-alwon;
	};
	};

	target-module@c000 { /* 0x4a31c000, ap 11 20.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xc000 0x4>,
	<0xc010 0x4>,
	<0xc014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_EMUFREE \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
	clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xc000 0x1000>;

	keypad: keypad@0 {
	compatible = "ti,omap4-keypad";
	reg = <0x0 0x80>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	reg-names = "mpu";
	};
	};

	target-module@e000 { /* 0x4a31e000, ap 21 30.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	ti,hwmods = "ctrl_module_pad_wkup";
	reg = <0xe000 0x4>,
	<0xe010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xe000 0x1000>;

	omap4_pmx_wkup: pinmux@40 {
	compatible = "ti,omap4-padconf",
	"pinctrl-single";
	reg = <0x40 0x0038>;
	#address-cells = <1>;
	#size-cells = <0>;
	#pinctrl-cells = <1>;
	#interrupt-cells = <1>;
	interrupt-controller;
	pinctrl-single,register-width = <16>;
	pinctrl-single,function-mask = <0x7fff>;
	};
	};
	};

	segment@20000 { /* 0x4a320000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
	<0x0000a000 0x0002a000 0x001000>, /* ap 14 */
	<0x00000000 0x00020000 0x001000>, /* ap 23 */
	<0x00001000 0x00021000 0x001000>, /* ap 24 */
	<0x00002000 0x00022000 0x001000>, /* ap 25 */
	<0x00003000 0x00023000 0x001000>, /* ap 26 */
	<0x00004000 0x00024000 0x001000>, /* ap 27 */
	<0x00005000 0x00025000 0x001000>, /* ap 28 */
	<0x00007000 0x00027000 0x000400>, /* ap 29 */
	<0x00008000 0x00028000 0x000800>, /* ap 30 */
	<0x00009000 0x00029000 0x000400>; /* ap 31 */

	target-module@0 { /* 0x4a320000, ap 23 04.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x1000>;
	};

	target-module@2000 { /* 0x4a322000, ap 25 0c.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x2000 0x1000>;
	};

	target-module@4000 { /* 0x4a324000, ap 27 10.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4000 0x1000>;
	};

	target-module@6000 { /* 0x4a326000, ap 13 28.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00006000 0x00001000>,
	<0x00001000 0x00007000 0x00000400>,
	<0x00002000 0x00008000 0x00000800>,
	<0x00003000 0x00009000 0x00000400>;
	};
	};
	};

	&l4_per { /* 0x48000000 */
	compatible = "ti,omap4-l4-per", "simple-bus";
	reg = <0x48000000 0x800>,
	<0x48000800 0x800>,
	<0x48001000 0x400>,
	<0x48001400 0x400>,
	<0x48001800 0x400>,
	<0x48001c00 0x400>;
	reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
	<0x00200000 0x48200000 0x200000>; /* segment 1 */

	segment@0 { /* 0x48000000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
	<0x00001000 0x00001000 0x000400>, /* ap 1 */
	<0x00000800 0x00000800 0x000800>, /* ap 2 */
	<0x00020000 0x00020000 0x001000>, /* ap 3 */
	<0x00021000 0x00021000 0x001000>, /* ap 4 */
	<0x00032000 0x00032000 0x001000>, /* ap 5 */
	<0x00033000 0x00033000 0x001000>, /* ap 6 */
	<0x00034000 0x00034000 0x001000>, /* ap 7 */
	<0x00035000 0x00035000 0x001000>, /* ap 8 */
	<0x00036000 0x00036000 0x001000>, /* ap 9 */
	<0x00037000 0x00037000 0x001000>, /* ap 10 */
	<0x0003e000 0x0003e000 0x001000>, /* ap 11 */
	<0x0003f000 0x0003f000 0x001000>, /* ap 12 */
	<0x00040000 0x00040000 0x010000>, /* ap 13 */
	<0x00050000 0x00050000 0x001000>, /* ap 14 */
	<0x00055000 0x00055000 0x001000>, /* ap 15 */
	<0x00056000 0x00056000 0x001000>, /* ap 16 */
	<0x00057000 0x00057000 0x001000>, /* ap 17 */
	<0x00058000 0x00058000 0x001000>, /* ap 18 */
	<0x00059000 0x00059000 0x001000>, /* ap 19 */
	<0x0005a000 0x0005a000 0x001000>, /* ap 20 */
	<0x0005b000 0x0005b000 0x001000>, /* ap 21 */
	<0x0005c000 0x0005c000 0x001000>, /* ap 22 */
	<0x0005d000 0x0005d000 0x001000>, /* ap 23 */
	<0x0005e000 0x0005e000 0x001000>, /* ap 24 */
	<0x00060000 0x00060000 0x001000>, /* ap 25 */
	<0x0006a000 0x0006a000 0x001000>, /* ap 26 */
	<0x0006b000 0x0006b000 0x001000>, /* ap 27 */
	<0x0006c000 0x0006c000 0x001000>, /* ap 28 */
	<0x0006d000 0x0006d000 0x001000>, /* ap 29 */
	<0x0006e000 0x0006e000 0x001000>, /* ap 30 */
	<0x0006f000 0x0006f000 0x001000>, /* ap 31 */
	<0x00070000 0x00070000 0x001000>, /* ap 32 */
	<0x00071000 0x00071000 0x001000>, /* ap 33 */
	<0x00072000 0x00072000 0x001000>, /* ap 34 */
	<0x00073000 0x00073000 0x001000>, /* ap 35 */
	<0x00061000 0x00061000 0x001000>, /* ap 36 */
	<0x00096000 0x00096000 0x001000>, /* ap 37 */
	<0x00097000 0x00097000 0x001000>, /* ap 38 */
	<0x00076000 0x00076000 0x001000>, /* ap 39 */
	<0x00077000 0x00077000 0x001000>, /* ap 40 */
	<0x00078000 0x00078000 0x001000>, /* ap 41 */
	<0x00079000 0x00079000 0x001000>, /* ap 42 */
	<0x00086000 0x00086000 0x001000>, /* ap 43 */
	<0x00087000 0x00087000 0x001000>, /* ap 44 */
	<0x00088000 0x00088000 0x001000>, /* ap 45 */
	<0x00089000 0x00089000 0x001000>, /* ap 46 */
	<0x000b0000 0x000b0000 0x001000>, /* ap 47 */
	<0x000b1000 0x000b1000 0x001000>, /* ap 48 */
	<0x00098000 0x00098000 0x001000>, /* ap 49 */
	<0x00099000 0x00099000 0x001000>, /* ap 50 */
	<0x0009a000 0x0009a000 0x001000>, /* ap 51 */
	<0x0009b000 0x0009b000 0x001000>, /* ap 52 */
	<0x0009c000 0x0009c000 0x001000>, /* ap 53 */
	<0x0009d000 0x0009d000 0x001000>, /* ap 54 */
	<0x0009e000 0x0009e000 0x001000>, /* ap 55 */
	<0x0009f000 0x0009f000 0x001000>, /* ap 56 */
	<0x00090000 0x00090000 0x002000>, /* ap 57 */
	<0x00092000 0x00092000 0x001000>, /* ap 58 */
	<0x000a4000 0x000a4000 0x001000>, /* ap 59 */
	<0x000a6000 0x000a6000 0x001000>, /* ap 60 */
	<0x000a8000 0x000a8000 0x004000>, /* ap 61 */
	<0x000ac000 0x000ac000 0x001000>, /* ap 62 */
	<0x000ad000 0x000ad000 0x001000>, /* ap 63 */
	<0x000ae000 0x000ae000 0x001000>, /* ap 64 */
	<0x000b2000 0x000b2000 0x001000>, /* ap 65 */
	<0x000b3000 0x000b3000 0x001000>, /* ap 66 */
	<0x000b4000 0x000b4000 0x001000>, /* ap 67 */
	<0x000b5000 0x000b5000 0x001000>, /* ap 68 */
	<0x000b8000 0x000b8000 0x001000>, /* ap 69 */
	<0x000b9000 0x000b9000 0x001000>, /* ap 70 */
	<0x000ba000 0x000ba000 0x001000>, /* ap 71 */
	<0x000bb000 0x000bb000 0x001000>, /* ap 72 */
	<0x000d1000 0x000d1000 0x001000>, /* ap 73 */
	<0x000d2000 0x000d2000 0x001000>, /* ap 74 */
	<0x000d5000 0x000d5000 0x001000>, /* ap 75 */
	<0x000d6000 0x000d6000 0x001000>, /* ap 76 */
	<0x000a2000 0x000a2000 0x001000>, /* ap 79 */
	<0x000a3000 0x000a3000 0x001000>, /* ap 80 */
	<0x00001400 0x00001400 0x000400>, /* ap 81 */
	<0x00001800 0x00001800 0x000400>, /* ap 82 */
	<0x00001c00 0x00001c00 0x000400>, /* ap 83 */
	<0x000a5000 0x000a5000 0x001000>; /* ap 84 */

	target-module@20000 { /* 0x48020000, ap 3 06.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x20050 0x4>,
	<0x20054 0x4>,
	<0x20058 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x20000 0x1000>;

	uart3: serial@0 {
	compatible = "ti,omap4-uart";
	reg = <0x0 0x100>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <48000000>;
	};
	};

	target-module@32000 { /* 0x48032000, ap 5 02.0 */
	compatible = "ti,sysc-omap2-timer", "ti,sysc";
	reg = <0x32000 0x4>,
	<0x32010 0x4>,
	<0x32014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_EMUFREE \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x32000 0x1000>;

	timer2: timer@0 {
	compatible = "ti,omap3430-timer";
	reg = <0x0 0x80>;
	clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>;
	clock-names = "fck";
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	target-module@34000 { /* 0x48034000, ap 7 04.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x34000 0x4>,
	<0x34010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x34000 0x1000>;

	timer3: timer@0 {
	compatible = "ti,omap4430-timer";
	reg = <0x0 0x80>;
	clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>;
	clock-names = "fck";
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	target-module@36000 { /* 0x48036000, ap 9 0e.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x36000 0x4>,
	<0x36010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x36000 0x1000>;

	timer4: timer@0 {
	compatible = "ti,omap4430-timer";
	reg = <0x0 0x80>;
	clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>;
	clock-names = "fck";
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	target-module@3e000 { /* 0x4803e000, ap 11 08.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x3e000 0x4>,
	<0x3e010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x3e000 0x1000>;

	timer9: timer@0 {
	compatible = "ti,omap4430-timer";
	reg = <0x0 0x80>;
	clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
	clock-names = "fck";
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	ti,timer-pwm;
	};
	};

	+ /* Unused DSS L4 access, see L3 instead */
	target-module@40000 { /* 0x48040000, ap 13 0a.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x40000 0x10000>;
	};

	target-module@55000 { /* 0x48055000, ap 15 0c.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x55000 0x4>,
	<0x55010 0x4>,
	<0x55114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>,
	<&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 8>;
	clock-names = "fck", "dbclk";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x55000 0x1000>;

	gpio2: gpio@0 {
	compatible = "ti,omap4-gpio";
	reg = <0x0 0x200>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	target-module@57000 { /* 0x48057000, ap 17 16.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x57000 0x4>,
	<0x57010 0x4>,
	<0x57114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>,
	<&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 8>;
	clock-names = "fck", "dbclk";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x57000 0x1000>;

	gpio3: gpio@0 {
	compatible = "ti,omap4-gpio";
	reg = <0x0 0x200>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	target-module@59000 { /* 0x48059000, ap 19 10.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x59000 0x4>,
	<0x59010 0x4>,
	<0x59114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>,
	<&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 8>;
	clock-names = "fck", "dbclk";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x59000 0x1000>;

	gpio4: gpio@0 {
	compatible = "ti,omap4-gpio";
	reg = <0x0 0x200>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	target-module@5b000 { /* 0x4805b000, ap 21 12.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x5b000 0x4>,
	<0x5b010 0x4>,
	<0x5b114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>,
	<&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 8>;
	clock-names = "fck", "dbclk";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x5b000 0x1000>;

	gpio5: gpio@0 {
	compatible = "ti,omap4-gpio";
	reg = <0x0 0x200>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	target-module@5d000 { /* 0x4805d000, ap 23 14.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x5d000 0x4>,
	<0x5d010 0x4>,
	<0x5d114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>,
	<&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 8>;
	clock-names = "fck", "dbclk";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x5d000 0x1000>;

	gpio6: gpio@0 {
	compatible = "ti,omap4-gpio";
	reg = <0x0 0x200>;
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	target-module@60000 { /* 0x48060000, ap 25 1e.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x60000 0x8>,
	<0x60010 0x8>,
	<0x60090 0x8>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x60000 0x1000>;

	i2c3: i2c@0 {
	compatible = "ti,omap4-i2c";
	reg = <0x0 0x100>;
	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	target-module@6a000 { /* 0x4806a000, ap 26 18.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x6a050 0x4>,
	<0x6a054 0x4>,
	<0x6a058 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x6a000 0x1000>;

	uart1: serial@0 {
	compatible = "ti,omap4-uart";
	reg = <0x0 0x100>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <48000000>;
	};
	};

	target-module@6c000 { /* 0x4806c000, ap 28 20.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x6c050 0x4>,
	<0x6c054 0x4>,
	<0x6c058 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x6c000 0x1000>;

	uart2: serial@0 {
	compatible = "ti,omap4-uart";
	reg = <0x0 0x100>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <48000000>;
	};
	};

	target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x6e050 0x4>,
	<0x6e054 0x4>,
	<0x6e058 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x6e000 0x1000>;

	uart4: serial@0 {
	compatible = "ti,omap4-uart";
	reg = <0x0 0x100>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <48000000>;
	};
	};

	target-module@70000 { /* 0x48070000, ap 32 28.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x70000 0x8>,
	<0x70010 0x8>,
	<0x70090 0x8>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x70000 0x1000>;

	i2c1: i2c@0 {
	compatible = "ti,omap4-i2c";
	reg = <0x0 0x100>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	target-module@72000 { /* 0x48072000, ap 34 30.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x72000 0x8>,
	<0x72010 0x8>,
	<0x72090 0x8>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x72000 0x1000>;

	i2c2: i2c@0 {
	compatible = "ti,omap4-i2c";
	reg = <0x0 0x100>;
	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	target-module@76000 { /* 0x48076000, ap 39 38.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x76000 0x4>,
	<0x76010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x76000 0x1000>;

	/* No child device binding or driver in mainline */
	};

	target-module@78000 { /* 0x48078000, ap 41 1a.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x78000 0x4>,
	<0x78010 0x4>,
	<0x78014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x78000 0x1000>;

	elm: elm@0 {
	compatible = "ti,am3352-elm";
	reg = <0x0 0x2000>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	target-module@86000 { /* 0x48086000, ap 43 24.0 */
	compatible = "ti,sysc-omap2-timer", "ti,sysc";
	reg = <0x86000 0x4>,
	<0x86010 0x4>,
	<0x86014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_EMUFREE \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x86000 0x1000>;

	timer10: timer@0 {
	compatible = "ti,omap3430-timer";
	reg = <0x0 0x80>;
	clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>;
	clock-names = "fck";
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	ti,timer-pwm;
	};
	};

	target-module@88000 { /* 0x48088000, ap 45 2e.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x88000 0x4>,
	<0x88010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x88000 0x1000>;

	timer11: timer@0 {
	compatible = "ti,omap4430-timer";
	reg = <0x0 0x80>;
	clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>;
	clock-names = "fck";
	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	ti,timer-pwm;
	};
	};

	rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x91fe0 0x4>,
	<0x91fe4 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>;
	/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
	clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x90000 0x2000>;

	rng: rng@0 {
	compatible = "ti,omap4-rng";
	reg = <0x0 0x2000>;
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	target-module@96000 { /* 0x48096000, ap 37 26.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x9608c 0x4>;
	reg-names = "sysc";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x96000 0x1000>;

	mcbsp4: mcbsp@0 {
	compatible = "ti,omap4-mcbsp";
	reg = <0x0 0xff>; /* L4 Interconnect */
	reg-names = "mpu";
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "common";
	ti,buffer-size = <128>;
	dmas = <&sdma 31>,
	<&sdma 32>;
	dma-names = "tx", "rx";
	status = "disabled";
	};
	};

	target-module@98000 { /* 0x48098000, ap 49 22.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x98000 0x4>,
	<0x98010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x98000 0x1000>;

	mcspi1: spi@0 {
	compatible = "ti,omap4-mcspi";
	reg = <0x0 0x200>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	ti,spi-num-cs = <4>;
	dmas = <&sdma 35>,
	<&sdma 36>,
	<&sdma 37>,
	<&sdma 38>,
	<&sdma 39>,
	<&sdma 40>,
	<&sdma 41>,
	<&sdma 42>;
	dma-names = "tx0", "rx0", "tx1", "rx1",
	"tx2", "rx2", "tx3", "rx3";
	};
	};

	target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x9a000 0x4>,
	<0x9a010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x9a000 0x1000>;

	mcspi2: spi@0 {
	compatible = "ti,omap4-mcspi";
	reg = <0x0 0x200>;
	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	ti,spi-num-cs = <2>;
	dmas = <&sdma 43>,
	<&sdma 44>,
	<&sdma 45>,
	<&sdma 46>;
	dma-names = "tx0", "rx0", "tx1", "rx1";
	};
	};

	target-module@9c000 { /* 0x4809c000, ap 53 36.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x9c000 0x4>,
	<0x9c010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
	clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x9c000 0x1000>;

	mmc1: mmc@0 {
	compatible = "ti,omap4-hsmmc";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	ti,dual-volt;
	ti,needs-special-reset;
	dmas = <&sdma 61>, <&sdma 62>;
	dma-names = "tx", "rx";
	pbias-supply = <&pbias_mmc_reg>;
	};
	};

	target-module@9e000 { /* 0x4809e000, ap 55 48.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x9e000 0x1000>;
	};

	target-module@a2000 { /* 0x480a2000, ap 79 3a.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa2000 0x1000>;
	};

	target-module@a4000 { /* 0x480a4000, ap 59 34.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x000a4000 0x00001000>,
	<0x00001000 0x000a5000 0x00001000>;
	};

	des_target: target-module@a5000 { /* 0x480a5000 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xa5030 0x4>,
	<0xa5034 0x4>,
	<0xa5038 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
	clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0xa5000 0x00001000>;

	des: des@0 {
	compatible = "ti,omap4-des";
	reg = <0 0xa0>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 117>, <&sdma 116>;
	dma-names = "tx", "rx";
	};
	};

	target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa8000 0x4000>;
	};

	target-module@ad000 { /* 0x480ad000, ap 63 50.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xad000 0x4>,
	<0xad010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xad000 0x1000>;

	mmc3: mmc@0 {
	compatible = "ti,omap4-hsmmc";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	ti,needs-special-reset;
	dmas = <&sdma 77>, <&sdma 78>;
	dma-names = "tx", "rx";
	};
	};

	target-module@b0000 { /* 0x480b0000, ap 47 40.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xb0000 0x1000>;
	};

	target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0xb2000 0x4>,
	<0xb2014 0x4>,
	<0xb2018 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,syss-mask = <1>;
	ti,no-reset-on-init;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_HDQ1W_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xb2000 0x1000>;

	hdqw1w: 1w@0 {
	compatible = "ti,omap3-1w";
	reg = <0x0 0x1000>;
	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	target-module@b4000 { /* 0x480b4000, ap 67 46.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xb4000 0x4>,
	<0xb4010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
	clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xb4000 0x1000>;

	mmc2: mmc@0 {
	compatible = "ti,omap4-hsmmc";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	ti,needs-special-reset;
	dmas = <&sdma 47>, <&sdma 48>;
	dma-names = "tx", "rx";
	};
	};

	target-module@b8000 { /* 0x480b8000, ap 69 58.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xb8000 0x4>,
	<0xb8010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xb8000 0x1000>;

	mcspi3: spi@0 {
	compatible = "ti,omap4-mcspi";
	reg = <0x0 0x200>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	ti,spi-num-cs = <2>;
	dmas = <&sdma 15>, <&sdma 16>;
	dma-names = "tx0", "rx0";
	};
	};

	target-module@ba000 { /* 0x480ba000, ap 71 32.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xba000 0x4>,
	<0xba010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xba000 0x1000>;

	mcspi4: spi@0 {
	compatible = "ti,omap4-mcspi";
	reg = <0x0 0x200>;
	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	ti,spi-num-cs = <1>;
	dmas = <&sdma 70>, <&sdma 71>;
	dma-names = "tx0", "rx0";
	};
	};

	target-module@d1000 { /* 0x480d1000, ap 73 44.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xd1000 0x4>,
	<0xd1010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xd1000 0x1000>;

	mmc4: mmc@0 {
	compatible = "ti,omap4-hsmmc";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	ti,needs-special-reset;
	dmas = <&sdma 57>, <&sdma 58>;
	dma-names = "tx", "rx";
	};
	};

	target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0xd5000 0x4>,
	<0xd5010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xd5000 0x1000>;

	mmc5: mmc@0 {
	compatible = "ti,omap4-hsmmc";
	reg = <0x0 0x400>;
	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
	ti,needs-special-reset;
	dmas = <&sdma 59>, <&sdma 60>;
	dma-names = "tx", "rx";
	};
	};
	};

	segment@200000 { /* 0x48200000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */
	<0x00151000 0x00351000 0x001000>; /* ap 78 */

	target-module@150000 { /* 0x48350000, ap 77 4c.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x150000 0x8>,
	<0x150010 0x8>,
	<0x150090 0x8>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
	clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x150000 0x1000>;

	i2c4: i2c@0 {
	compatible = "ti,omap4-i2c";
	reg = <0x0 0x100>;
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};
	};
	};

	diff --git a/sys/gnu/dts/arm/omap4.dtsi b/sys/gnu/dts/arm/omap4.dtsi
	index 9a87440d0b9d..763bdea8c829 100644
	--- a/sys/gnu/dts/arm/omap4.dtsi
	+++ b/sys/gnu/dts/arm/omap4.dtsi
	@@ -1,532 +1,657 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
	*/

	#include <dt-bindings/bus/ti-sysc.h>
	#include <dt-bindings/clock/omap4.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/pinctrl/omap.h>
	#include <dt-bindings/clock/omap4.h>

	/ {
	compatible = "ti,omap4430", "ti,omap4";
	interrupt-parent = <&wakeupgen>;
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };

	aliases {
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	i2c2 = &i2c3;
	i2c3 = &i2c4;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	next-level-cache = <&L2>;
	reg = <0x0>;

	clocks = <&dpll_mpu_ck>;
	clock-names = "cpu";

	clock-latency = <300000>; /* From omap-cpufreq driver */
	};
	cpu@1 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	next-level-cache = <&L2>;
	reg = <0x1>;
	};
	};

	/*
	* Note that 4430 needs cross trigger interface (CTI) supported
	* before we can configure the interrupts. This means sampling
	* events are not supported for pmu. Note that 4460 does not use
	* CTI, see also 4460.dtsi.
	*/
	pmu {
	compatible = "arm,cortex-a9-pmu";
	ti,hwmods = "debugss";
	};

	gic: interrupt-controller@48241000 {
	compatible = "arm,cortex-a9-gic";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0x48241000 0x1000>,
	<0x48240100 0x0100>;
	interrupt-parent = <&gic>;
	};

	L2: l2-cache-controller@48242000 {
	compatible = "arm,pl310-cache";
	reg = <0x48242000 0x1000>;
	cache-unified;
	cache-level = <2>;
	};

	local-timer@48240600 {
	compatible = "arm,cortex-a9-twd-timer";
	clocks = <&mpu_periphclk>;
	reg = <0x48240600 0x20>;
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) \| IRQ_TYPE_EDGE_RISING)>;
	interrupt-parent = <&gic>;
	};

	wakeupgen: interrupt-controller@48281000 {
	compatible = "ti,omap4-wugen-mpu";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0x48281000 0x1000>;
	interrupt-parent = <&gic>;
	};

	/*
	* The soc node represents the soc top level view. It is used for IPs
	* that are not memory mapped in the MPU view or for the MPU itself.
	*/
	soc {
	compatible = "ti,omap-infra";
	mpu {
	compatible = "ti,omap4-mpu";
	ti,hwmods = "mpu";
	sram = <&ocmcram>;
	};

	dsp {
	compatible = "ti,omap3-c64";
	- ti,hwmods = "dsp";
	};

	iva {
	compatible = "ti,ivahd";
	ti,hwmods = "iva";
	};
	};

	/*
	* XXX: Use a flat representation of the OMAP4 interconnect.
	* The real OMAP interconnect network is quite complex.
	* Since it will not bring real advantage to represent that in DT for
	* the moment, just use a fake OCP bus entry to represent the whole bus
	* hierarchy.
	*/
	ocp {
	compatible = "ti,omap4-l3-noc", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
	reg = <0x44000000 0x1000>,
	<0x44800000 0x2000>,
	<0x45000000 0x1000>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

	l4_wkup: interconnect@4a300000 {
	};

	l4_cfg: interconnect@4a000000 {
	};

	l4_per: interconnect@48000000 {
	};

	l4_abe: interconnect@40100000 {
	};

	ocmcram: sram@40304000 {
	compatible = "mmio-sram";
	reg = <0x40304000 0xa000>; /* 40k */
	};

	gpmc: gpmc@50000000 {
	compatible = "ti,omap4430-gpmc";
	reg = <0x50000000 0x1000>;
	#address-cells = <2>;
	#size-cells = <1>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 4>;
	dma-names = "rxtx";
	gpmc,num-cs = <8>;
	gpmc,num-waitpins = <4>;
	ti,hwmods = "gpmc";
	ti,no-idle-on-init;
	clocks = <&l3_div_ck>;
	clock-names = "fck";
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	target-module@52000000 {
	compatible = "ti,sysc-omap4", "ti,sysc";
	ti,hwmods = "iss";
	reg = <0x52000000 0x4>,
	<0x52000010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-delay-us = <2>;
	clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x52000000 0x1000000>;

	/* No child device binding, driver in staging */
	};

	target-module@55082000 {
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x55082000 0x4>,
	<0x55082010 0x4>,
	<0x55082014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
	clock-names = "fck";
	resets = <&prm_core 2>;
	reset-names = "rstctrl";
	ranges = <0x0 0x55082000 0x100>;
	#size-cells = <1>;
	#address-cells = <1>;

	mmu_ipu: mmu@0 {
	compatible = "ti,omap4-iommu";
	reg = <0x0 0x100>;
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <0>;
	ti,iommu-bus-err-back;
	};
	};

	target-module@4012c000 {
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x4012c000 0x4>,
	<0x4012c010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
	<0x4902c000 0x4902c000 0x1000>; /* L3 */

	/* No child device binding or driver in mainline */
	};

	dmm@4e000000 {
	compatible = "ti,omap4-dmm";
	reg = <0x4e000000 0x800>;
	interrupts = <0 113 0x4>;
	ti,hwmods = "dmm";
	};

	emif1: emif@4c000000 {
	compatible = "ti,emif-4d";
	reg = <0x4c000000 0x100>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	ti,hwmods = "emif1";
	ti,no-idle-on-init;
	phy-type = <1>;
	hw-caps-read-idle-ctrl;
	hw-caps-ll-interface;
	hw-caps-temp-alert;
	};

	emif2: emif@4d000000 {
	compatible = "ti,emif-4d";
	reg = <0x4d000000 0x100>;
	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
	ti,hwmods = "emif2";
	ti,no-idle-on-init;
	phy-type = <1>;
	hw-caps-read-idle-ctrl;
	hw-caps-ll-interface;
	hw-caps-temp-alert;
	};

	aes1_target: target-module@4b501000 {
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x4b501080 0x4>,
	<0x4b501084 0x4>,
	<0x4b501088 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
	clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4b501000 0x1000>;

	aes1: aes@0 {
	compatible = "ti,omap4-aes";
	reg = <0 0xa0>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 111>, <&sdma 110>;
	dma-names = "tx", "rx";
	};
	};

	aes2_target: target-module@4b701000 {
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x4b701080 0x4>,
	<0x4b701084 0x4>,
	<0x4b701088 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,syss-mask = <1>;
	/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
	clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4b701000 0x1000>;

	aes2: aes@0 {
	compatible = "ti,omap4-aes";
	reg = <0 0xa0>;
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 114>, <&sdma 113>;
	dma-names = "tx", "rx";
	};
	};

	sham_target: target-module@4b100000 {
	compatible = "ti,sysc-omap3-sham", "ti,sysc";
	reg = <0x4b100100 0x4>,
	<0x4b100110 0x4>,
	<0x4b100114 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,syss-mask = <1>;
	/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
	clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x4b100000 0x1000>;

	sham: sham@0 {
	compatible = "ti,omap4-sham";
	reg = <0 0x300>;
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 119>;
	dma-names = "rx";
	};
	};

	abb_mpu: regulator-abb-mpu {
	compatible = "ti,abb-v2";
	regulator-name = "abb_mpu";
	#address-cells = <0>;
	#size-cells = <0>;
	ti,tranxdone-status-mask = <0x80>;
	clocks = <&sys_clkin_ck>;
	ti,settling-time = <50>;
	ti,clock-cycles = <16>;

	status = "disabled";
	};

	abb_iva: regulator-abb-iva {
	compatible = "ti,abb-v2";
	regulator-name = "abb_iva";
	#address-cells = <0>;
	#size-cells = <0>;
	ti,tranxdone-status-mask = <0x80000000>;
	clocks = <&sys_clkin_ck>;
	ti,settling-time = <50>;
	ti,clock-cycles = <16>;

	status = "disabled";
	};

	target-module@56000000 {
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x5600fe00 0x4>,
	<0x5600fe10 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x56000000 0x2000000>;

	/*
	* Closed source PowerVR driver, no child device
	* binding or driver in mainline
	*/
	};

	- dss: dss@58000000 {
	- compatible = "ti,omap4-dss";
	- reg = <0x58000000 0x80>;
	- status = "disabled";
	- ti,hwmods = "dss_core";
	- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
	- clock-names = "fck";
	+ /*
	+ * DSS is only using l3 mapping without l4 as noted in the TRM
	+ * "10.1.3 DSS Register Manual" for omap4460.
	+ */
	+ target-module@58000000 {
	+ compatible = "ti,sysc-omap2", "ti,sysc";
	+ reg = <0x58000000 4>,
	+ <0x58000014 4>;
	+ reg-names = "rev", "syss";
	+ ti,syss-mask = <1>;
	+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
	+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
	+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
	+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
	+ clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
	#address-cells = <1>;
	#size-cells = <1>;
	- ranges;
	-
	- dispc@58001000 {
	- compatible = "ti,omap4-dispc";
	- reg = <0x58001000 0x1000>;
	- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	- ti,hwmods = "dss_dispc";
	- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
	- clock-names = "fck";
	- };
	-
	- rfbi: encoder@58002000 {
	- compatible = "ti,omap4-rfbi";
	- reg = <0x58002000 0x1000>;
	- status = "disabled";
	- ti,hwmods = "dss_rfbi";
	- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
	- clock-names = "fck", "ick";
	- };
	+ ranges = <0 0x58000000 0x1000000>;

	- venc: encoder@58003000 {
	- compatible = "ti,omap4-venc";
	- reg = <0x58003000 0x1000>;
	+ dss: dss@0 {
	+ compatible = "ti,omap4-dss";
	+ reg = <0 0x80>;
	status = "disabled";
	- ti,hwmods = "dss_venc";
	- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
	+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
	clock-names = "fck";
	- };
	-
	- dsi1: encoder@58004000 {
	- compatible = "ti,omap4-dsi";
	- reg = <0x58004000 0x200>,
	- <0x58004200 0x40>,
	- <0x58004300 0x20>;
	- reg-names = "proto", "phy", "pll";
	- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	- status = "disabled";
	- ti,hwmods = "dss_dsi1";
	- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
	- <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
	- clock-names = "fck", "sys_clk";
	- };
	-
	- dsi2: encoder@58005000 {
	- compatible = "ti,omap4-dsi";
	- reg = <0x58005000 0x200>,
	- <0x58005200 0x40>,
	- <0x58005300 0x20>;
	- reg-names = "proto", "phy", "pll";
	- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	- status = "disabled";
	- ti,hwmods = "dss_dsi2";
	- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
	- <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
	- clock-names = "fck", "sys_clk";
	- };
	-
	- hdmi: encoder@58006000 {
	- compatible = "ti,omap4-hdmi";
	- reg = <0x58006000 0x200>,
	- <0x58006200 0x100>,
	- <0x58006300 0x100>,
	- <0x58006400 0x1000>;
	- reg-names = "wp", "pll", "phy", "core";
	- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	- status = "disabled";
	- ti,hwmods = "dss_hdmi";
	- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
	- <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
	- clock-names = "fck", "sys_clk";
	- dmas = <&sdma 76>;
	- dma-names = "audio_tx";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0 0x1000000>;
	+
	+ target-module@1000 {
	+ compatible = "ti,sysc-omap2", "ti,sysc";
	+ reg = <0x1000 0x4>,
	+ <0x1010 0x4>,
	+ <0x1014 0x4>;
	+ reg-names = "rev", "sysc", "syss";
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	+ SYSC_OMAP2_ENAWAKEUP \|
	+ SYSC_OMAP2_SOFTRESET \|
	+ SYSC_OMAP2_AUTOIDLE)>;
	+ ti,syss-mask = <1>;
	+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
	+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
	+ clock-names = "fck", "sys_clk";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x1000 0x1000>;
	+
	+ dispc@0 {
	+ compatible = "ti,omap4-dispc";
	+ reg = <0 0x1000>;
	+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
	+ clock-names = "fck";
	+ };
	+ };
	+
	+ target-module@2000 {
	+ compatible = "ti,sysc-omap2", "ti,sysc";
	+ reg = <0x2000 0x4>,
	+ <0x2010 0x4>,
	+ <0x2014 0x4>;
	+ reg-names = "rev", "sysc", "syss";
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	+ SYSC_OMAP2_AUTOIDLE)>;
	+ ti,syss-mask = <1>;
	+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
	+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
	+ clock-names = "fck", "sys_clk";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x2000 0x1000>;
	+
	+ rfbi: encoder@0 {
	+ reg = <0 0x1000>;
	+ status = "disabled";
	+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
	+ clock-names = "fck", "ick";
	+ };
	+ };
	+
	+ target-module@3000 {
	+ compatible = "ti,sysc-omap2", "ti,sysc";
	+ reg = <0x3000 0x4>;
	+ reg-names = "rev";
	+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
	+ clock-names = "sys_clk";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x3000 0x1000>;
	+
	+ venc: encoder@0 {
	+ compatible = "ti,omap4-venc";
	+ reg = <0 0x1000>;
	+ status = "disabled";
	+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
	+ clock-names = "fck";
	+ };
	+ };
	+
	+ target-module@4000 {
	+ compatible = "ti,sysc-omap2", "ti,sysc";
	+ reg = <0x4000 0x4>,
	+ <0x4010 0x4>,
	+ <0x4014 0x4>;
	+ reg-names = "rev", "sysc", "syss";
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	+ SYSC_OMAP2_ENAWAKEUP \|
	+ SYSC_OMAP2_SOFTRESET \|
	+ SYSC_OMAP2_AUTOIDLE)>;
	+ ti,syss-mask = <1>;
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x4000 0x1000>;
	+
	+ dsi1: encoder@0 {
	+ compatible = "ti,omap4-dsi";
	+ reg = <0 0x200>,
	+ <0x200 0x40>,
	+ <0x300 0x20>;
	+ reg-names = "proto", "phy", "pll";
	+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	+ status = "disabled";
	+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
	+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
	+ clock-names = "fck", "sys_clk";
	+ };
	+ };
	+
	+ target-module@5000 {
	+ compatible = "ti,sysc-omap2", "ti,sysc";
	+ reg = <0x5000 0x4>,
	+ <0x5010 0x4>,
	+ <0x5014 0x4>;
	+ reg-names = "rev", "sysc", "syss";
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	+ SYSC_OMAP2_ENAWAKEUP \|
	+ SYSC_OMAP2_SOFTRESET \|
	+ SYSC_OMAP2_AUTOIDLE)>;
	+ ti,syss-mask = <1>;
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x5000 0x1000>;
	+
	+ dsi2: encoder@0 {
	+ compatible = "ti,omap4-dsi";
	+ reg = <0 0x200>,
	+ <0x200 0x40>,
	+ <0x300 0x20>;
	+ reg-names = "proto", "phy", "pll";
	+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	+ status = "disabled";
	+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
	+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
	+ clock-names = "fck", "sys_clk";
	+ };
	+ };
	+
	+ target-module@6000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x6000 0x4>,
	+ <0x6010 0x4>;
	+ reg-names = "rev", "sysc";
	+ /*
	+ * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
	+ * but HDMI audio will fail with them.
	+ */
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>;
	+ ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
	+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
	+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
	+ clock-names = "fck", "dss_clk";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x6000 0x2000>;
	+
	+ hdmi: encoder@0 {
	+ compatible = "ti,omap4-hdmi";
	+ reg = <0 0x200>,
	+ <0x200 0x100>,
	+ <0x300 0x100>,
	+ <0x400 0x1000>;
	+ reg-names = "wp", "pll", "phy", "core";
	+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	+ status = "disabled";
	+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
	+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
	+ clock-names = "fck", "sys_clk";
	+ dmas = <&sdma 76>;
	+ dma-names = "audio_tx";
	+ };
	+ };
	};
	};
	};
	};

	#include "omap4-l4.dtsi"
	#include "omap4-l4-abe.dtsi"
	#include "omap44xx-clocks.dtsi"

	&prm {
	prm_tesla: prm@400 {
	compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
	reg = <0x400 0x100>;
	#reset-cells = <1>;
	};

	prm_core: prm@700 {
	compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
	reg = <0x700 0x100>;
	#reset-cells = <1>;
	};

	prm_ivahd: prm@f00 {
	compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
	reg = <0xf00 0x100>;
	#reset-cells = <1>;
	};

	prm_device: prm@1b00 {
	compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
	reg = <0x1b00 0x40>;
	#reset-cells = <1>;
	};
	};
	diff --git a/sys/gnu/dts/arm/omap5-l4-abe.dtsi b/sys/gnu/dts/arm/omap5-l4-abe.dtsi
	index 4ec7909df78b..bafd6adf9f45 100644
	--- a/sys/gnu/dts/arm/omap5-l4-abe.dtsi
	+++ b/sys/gnu/dts/arm/omap5-l4-abe.dtsi
	@@ -1,438 +1,450 @@
	&l4_abe { /* 0x40100000 */
	compatible = "ti,omap5-l4-abe", "simple-bus";
	reg = <0x40100000 0x400>,
	<0x40100400 0x400>;
	reg-names = "la", "ap";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
	<0x49000000 0x49000000 0x100000>;
	segment@0 { /* 0x40100000 */
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges =
	/* CPU to L4 ABE mapping */
	<0x00000000 0x00000000 0x000400>, /* ap 0 */
	<0x00000400 0x00000400 0x000400>, /* ap 1 */
	<0x00022000 0x00022000 0x001000>, /* ap 2 */
	<0x00023000 0x00023000 0x001000>, /* ap 3 */
	<0x00024000 0x00024000 0x001000>, /* ap 4 */
	<0x00025000 0x00025000 0x001000>, /* ap 5 */
	<0x00026000 0x00026000 0x001000>, /* ap 6 */
	<0x00027000 0x00027000 0x001000>, /* ap 7 */
	<0x00028000 0x00028000 0x001000>, /* ap 8 */
	<0x00029000 0x00029000 0x001000>, /* ap 9 */
	<0x0002a000 0x0002a000 0x001000>, /* ap 10 */
	<0x0002b000 0x0002b000 0x001000>, /* ap 11 */
	<0x0002e000 0x0002e000 0x001000>, /* ap 12 */
	<0x0002f000 0x0002f000 0x001000>, /* ap 13 */
	<0x00030000 0x00030000 0x001000>, /* ap 14 */
	<0x00031000 0x00031000 0x001000>, /* ap 15 */
	<0x00032000 0x00032000 0x001000>, /* ap 16 */
	<0x00033000 0x00033000 0x001000>, /* ap 17 */
	<0x00038000 0x00038000 0x001000>, /* ap 18 */
	<0x00039000 0x00039000 0x001000>, /* ap 19 */
	<0x0003a000 0x0003a000 0x001000>, /* ap 20 */
	<0x0003b000 0x0003b000 0x001000>, /* ap 21 */
	<0x0003c000 0x0003c000 0x001000>, /* ap 22 */
	<0x0003d000 0x0003d000 0x001000>, /* ap 23 */
	<0x0003e000 0x0003e000 0x001000>, /* ap 24 */
	<0x0003f000 0x0003f000 0x001000>, /* ap 25 */
	<0x00080000 0x00080000 0x010000>, /* ap 26 */
	<0x00080000 0x00080000 0x001000>, /* ap 27 */
	<0x000a0000 0x000a0000 0x010000>, /* ap 28 */
	<0x000a0000 0x000a0000 0x001000>, /* ap 29 */
	<0x000c0000 0x000c0000 0x010000>, /* ap 30 */
	<0x000c0000 0x000c0000 0x001000>, /* ap 31 */
	<0x000f1000 0x000f1000 0x001000>, /* ap 32 */
	<0x000f2000 0x000f2000 0x001000>, /* ap 33 */

	/* L3 to L4 ABE mapping */
	<0x49000000 0x49000000 0x000400>, /* ap 0 */
	<0x49000400 0x49000400 0x000400>, /* ap 1 */
	<0x49022000 0x49022000 0x001000>, /* ap 2 */
	<0x49023000 0x49023000 0x001000>, /* ap 3 */
	<0x49024000 0x49024000 0x001000>, /* ap 4 */
	<0x49025000 0x49025000 0x001000>, /* ap 5 */
	<0x49026000 0x49026000 0x001000>, /* ap 6 */
	<0x49027000 0x49027000 0x001000>, /* ap 7 */
	<0x49028000 0x49028000 0x001000>, /* ap 8 */
	<0x49029000 0x49029000 0x001000>, /* ap 9 */
	<0x4902a000 0x4902a000 0x001000>, /* ap 10 */
	<0x4902b000 0x4902b000 0x001000>, /* ap 11 */
	<0x4902e000 0x4902e000 0x001000>, /* ap 12 */
	<0x4902f000 0x4902f000 0x001000>, /* ap 13 */
	<0x49030000 0x49030000 0x001000>, /* ap 14 */
	<0x49031000 0x49031000 0x001000>, /* ap 15 */
	<0x49032000 0x49032000 0x001000>, /* ap 16 */
	<0x49033000 0x49033000 0x001000>, /* ap 17 */
	<0x49038000 0x49038000 0x001000>, /* ap 18 */
	<0x49039000 0x49039000 0x001000>, /* ap 19 */
	<0x4903a000 0x4903a000 0x001000>, /* ap 20 */
	<0x4903b000 0x4903b000 0x001000>, /* ap 21 */
	<0x4903c000 0x4903c000 0x001000>, /* ap 22 */
	<0x4903d000 0x4903d000 0x001000>, /* ap 23 */
	<0x4903e000 0x4903e000 0x001000>, /* ap 24 */
	<0x4903f000 0x4903f000 0x001000>, /* ap 25 */
	<0x49080000 0x49080000 0x010000>, /* ap 26 */
	<0x49080000 0x49080000 0x001000>, /* ap 27 */
	<0x490a0000 0x490a0000 0x010000>, /* ap 28 */
	<0x490a0000 0x490a0000 0x001000>, /* ap 29 */
	<0x490c0000 0x490c0000 0x010000>, /* ap 30 */
	<0x490c0000 0x490c0000 0x001000>, /* ap 31 */
	<0x490f1000 0x490f1000 0x001000>, /* ap 32 */
	<0x490f2000 0x490f2000 0x001000>; /* ap 33 */

	target-module@22000 { /* 0x40122000, ap 2 02.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x2208c 0x4>;
	reg-names = "sysc";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
	clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x22000 0x1000>,
	<0x49022000 0x49022000 0x1000>;

	mcbsp1: mcbsp@0 {
	compatible = "ti,omap4-mcbsp";
	reg = <0x0 0xff>, /* MPU private access */
	<0x49022000 0xff>; /* L3 Interconnect */
	reg-names = "mpu", "dma";
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "common";
	ti,buffer-size = <128>;
	dmas = <&sdma 33>,
	<&sdma 34>;
	dma-names = "tx", "rx";
	status = "disabled";
	};
	};

	target-module@24000 { /* 0x40124000, ap 4 04.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x2408c 0x4>;
	reg-names = "sysc";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
	clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x24000 0x1000>,
	<0x49024000 0x49024000 0x1000>;

	mcbsp2: mcbsp@0 {
	compatible = "ti,omap4-mcbsp";
	reg = <0x0 0xff>, /* MPU private access */
	<0x49024000 0xff>; /* L3 Interconnect */
	reg-names = "mpu", "dma";
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "common";
	ti,buffer-size = <128>;
	dmas = <&sdma 17>,
	<&sdma 18>;
	dma-names = "tx", "rx";
	status = "disabled";
	};
	};

	target-module@26000 { /* 0x40126000, ap 6 06.0 */
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x2608c 0x4>;
	reg-names = "sysc";
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_ENAWAKEUP \|
	SYSC_OMAP2_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
	clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x26000 0x1000>,
	<0x49026000 0x49026000 0x1000>;

	mcbsp3: mcbsp@0 {
	compatible = "ti,omap4-mcbsp";
	reg = <0x0 0xff>, /* MPU private access */
	<0x49026000 0xff>; /* L3 Interconnect */
	reg-names = "mpu", "dma";
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "common";
	ti,buffer-size = <128>;
	dmas = <&sdma 19>,
	<&sdma 20>;
	dma-names = "tx", "rx";
	status = "disabled";
	};
	};

	target-module@28000 { /* 0x40128000, ap 8 08.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x28000 0x1000>,
	<0x49028000 0x49028000 0x1000>;
	};

	target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x2a000 0x1000>,
	<0x4902a000 0x4902a000 0x1000>;
	};

	target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x2e000 0x4>,
	<0x2e010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
	clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x2e000 0x1000>,
	<0x4902e000 0x4902e000 0x1000>;

	dmic: dmic@0 {
	compatible = "ti,omap4-dmic";
	reg = <0x0 0x7f>, /* MPU private access */
	<0x4902e000 0x7f>; /* L3 Interconnect */
	reg-names = "mpu", "dma";
	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 67>;
	dma-names = "up_link";
	status = "disabled";
	};
	};

	target-module@30000 { /* 0x40130000, ap 14 0e.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x30000 0x1000>,
	<0x49030000 0x49030000 0x1000>;
	};

	mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x32000 0x4>,
	<0x32010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
	clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x32000 0x1000>,
	<0x49032000 0x49032000 0x1000>;

	/* Must be only enabled for boards with pdmclk wired */
	status = "disabled";

	mcpdm: mcpdm@0 {
	compatible = "ti,omap4-mcpdm";
	reg = <0x0 0x7f>, /* MPU private access */
	<0x49032000 0x7f>; /* L3 Interconnect */
	reg-names = "mpu", "dma";
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 65>,
	<&sdma 66>;
	dma-names = "up_link", "dn_link";
	};
	};

	target-module@38000 { /* 0x40138000, ap 18 12.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x38000 0x4>,
	<0x38010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
	clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x38000 0x1000>,
	<0x49038000 0x49038000 0x1000>;

	timer5: timer@0 {
	compatible = "ti,omap5430-timer";
	reg = <0x0 0x80>,
	<0x49038000 0x80>;
	clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>;
	clock-names = "fck";
	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	ti,timer-dsp;
	ti,timer-pwm;
	};
	};

	target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x3a000 0x4>,
	<0x3a010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
	clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x3a000 0x1000>,
	<0x4903a000 0x4903a000 0x1000>;

	timer6: timer@0 {
	compatible = "ti,omap5430-timer";
	reg = <0x0 0x80>,
	<0x4903a000 0x80>;
	clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>;
	clock-names = "fck";
	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	ti,timer-dsp;
	ti,timer-pwm;
	};
	};

	target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x3c000 0x4>,
	<0x3c010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
	clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x3c000 0x1000>,
	<0x4903c000 0x4903c000 0x1000>;

	timer7: timer@0 {
	compatible = "ti,omap5430-timer";
	reg = <0x0 0x80>,
	<0x4903c000 0x80>;
	clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>;
	clock-names = "fck";
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	ti,timer-dsp;
	};
	};

	target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
	compatible = "ti,sysc-omap4-timer", "ti,sysc";
	reg = <0x3e000 0x4>,
	<0x3e010 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
	SYSC_OMAP4_SOFTRESET)>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>,
	<SYSC_IDLE_SMART_WKUP>;
	/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
	clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x3e000 0x1000>,
	<0x4903e000 0x4903e000 0x1000>;

	timer8: timer@0 {
	compatible = "ti,omap5430-timer";
	reg = <0x0 0x80>,
	<0x4903e000 0x80>;
	clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>;
	clock-names = "fck";
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	ti,timer-dsp;
	ti,timer-pwm;
	};
	};

	target-module@80000 { /* 0x40180000, ap 26 1a.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x80000 0x10000>,
	<0x49080000 0x49080000 0x10000>;
	};

	target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xa0000 0x10000>,
	<0x490a0000 0x490a0000 0x10000>;
	};

	target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
	compatible = "ti,sysc";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xc0000 0x10000>,
	<0x490c0000 0x490c0000 0x10000>;
	};

	target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
	- compatible = "ti,sysc";
	- status = "disabled";
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0xf1000 0x4>,
	+ <0xf1010 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>,
	+ <SYSC_IDLE_SMART_WKUP>;
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
	+ clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>;
	+ clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf1000 0x1000>,
	<0x490f1000 0x490f1000 0x1000>;
	};
	};
	};

	diff --git a/sys/gnu/dts/arm/omap5.dtsi b/sys/gnu/dts/arm/omap5.dtsi
	index a7562d3deb1a..2ac7f021c284 100644
	--- a/sys/gnu/dts/arm/omap5.dtsi
	+++ b/sys/gnu/dts/arm/omap5.dtsi
	@@ -1,476 +1,583 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	*
	* Based on "omap4.dtsi"
	*/

	#include <dt-bindings/bus/ti-sysc.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/pinctrl/omap.h>
	#include <dt-bindings/clock/omap5.h>

	/ {
	#address-cells = <2>;
	#size-cells = <2>;

	compatible = "ti,omap5";
	interrupt-parent = <&wakeupgen>;
	chosen { };

	aliases {
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	i2c2 = &i2c3;
	i2c3 = &i2c4;
	i2c4 = &i2c5;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	serial4 = &uart5;
	serial5 = &uart6;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0x0>;

	operating-points = <
	/* kHz uV */
	1000000 1060000
	1500000 1250000
	>;

	clocks = <&dpll_mpu_ck>;
	clock-names = "cpu";

	clock-latency = <300000>; /* From omap-cpufreq driver */

	/* cooling options */
	#cooling-cells = <2>; /* min followed by max */
	};
	cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0x1>;

	operating-points = <
	/* kHz uV */
	1000000 1060000
	1500000 1250000
	>;

	clocks = <&dpll_mpu_ck>;
	clock-names = "cpu";

	clock-latency = <300000>; /* From omap-cpufreq driver */

	/* cooling options */
	#cooling-cells = <2>; /* min followed by max */
	};
	};

	thermal-zones {
	#include "omap4-cpu-thermal.dtsi"
	#include "omap5-gpu-thermal.dtsi"
	#include "omap5-core-thermal.dtsi"
	};

	timer {
	compatible = "arm,armv7-timer";
	/* PPI secure/nonsecure IRQ */
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_RAW(3) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_RAW(3) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_RAW(3) \| IRQ_TYPE_LEVEL_LOW)>;
	interrupt-parent = <&gic>;
	};

	pmu {
	compatible = "arm,cortex-a15-pmu";
	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
	};

	gic: interrupt-controller@48211000 {
	compatible = "arm,cortex-a15-gic";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0 0x48211000 0 0x1000>,
	<0 0x48212000 0 0x2000>,
	<0 0x48214000 0 0x2000>,
	<0 0x48216000 0 0x2000>;
	interrupt-parent = <&gic>;
	};

	wakeupgen: interrupt-controller@48281000 {
	compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0 0x48281000 0 0x1000>;
	interrupt-parent = <&gic>;
	};

	/*
	* The soc node represents the soc top level view. It is used for IPs
	* that are not memory mapped in the MPU view or for the MPU itself.
	*/
	soc {
	compatible = "ti,omap-infra";
	mpu {
	compatible = "ti,omap4-mpu";
	ti,hwmods = "mpu";
	sram = <&ocmcram>;
	};
	};

	/*
	* XXX: Use a flat representation of the OMAP3 interconnect.
	* The real OMAP interconnect network is quite complex.
	* Since it will not bring real advantage to represent that in DT for
	* the moment, just use a fake OCP bus entry to represent the whole bus
	* hierarchy.
	*/
	ocp {
	compatible = "ti,omap5-l3-noc", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xc0000000>;
	dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
	ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
	reg = <0 0x44000000 0 0x2000>,
	<0 0x44800000 0 0x3000>,
	<0 0x45000000 0 0x4000>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

	l4_wkup: interconnect@4ae00000 {
	};

	l4_cfg: interconnect@4a000000 {
	};

	l4_per: interconnect@48000000 {
	};

	l4_abe: interconnect@40100000 {
	};

	ocmcram: sram@40300000 {
	compatible = "mmio-sram";
	reg = <0x40300000 0x20000>; /* 128k */
	};

	gpmc: gpmc@50000000 {
	compatible = "ti,omap4430-gpmc";
	reg = <0x50000000 0x1000>;
	#address-cells = <2>;
	#size-cells = <1>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&sdma 4>;
	dma-names = "rxtx";
	gpmc,num-cs = <8>;
	gpmc,num-waitpins = <4>;
	ti,hwmods = "gpmc";
	clocks = <&l3_iclk_div>;
	clock-names = "fck";
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	target-module@55082000 {
	compatible = "ti,sysc-omap2", "ti,sysc";
	reg = <0x55082000 0x4>,
	<0x55082010 0x4>,
	<0x55082014 0x4>;
	reg-names = "rev", "sysc", "syss";
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	SYSC_OMAP2_SOFTRESET \|
	SYSC_OMAP2_AUTOIDLE)>;
	clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
	clock-names = "fck";
	resets = <&prm_core 2>;
	reset-names = "rstctrl";
	ranges = <0x0 0x55082000 0x100>;
	#size-cells = <1>;
	#address-cells = <1>;

	mmu_ipu: mmu@0 {
	compatible = "ti,omap4-iommu";
	reg = <0x0 0x100>;
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <0>;
	ti,iommu-bus-err-back;
	};
	};

	dmm@4e000000 {
	compatible = "ti,omap5-dmm";
	reg = <0x4e000000 0x800>;
	interrupts = <0 113 0x4>;
	ti,hwmods = "dmm";
	};

	emif1: emif@4c000000 {
	compatible = "ti,emif-4d5";
	ti,hwmods = "emif1";
	ti,no-idle-on-init;
	phy-type = <2>; /* DDR PHY type: Intelli PHY */
	reg = <0x4c000000 0x400>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	hw-caps-read-idle-ctrl;
	hw-caps-ll-interface;
	hw-caps-temp-alert;
	};

	emif2: emif@4d000000 {
	compatible = "ti,emif-4d5";
	ti,hwmods = "emif2";
	ti,no-idle-on-init;
	phy-type = <2>; /* DDR PHY type: Intelli PHY */
	reg = <0x4d000000 0x400>;
	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
	hw-caps-read-idle-ctrl;
	hw-caps-ll-interface;
	hw-caps-temp-alert;
	};

	bandgap: bandgap@4a0021e0 {
	reg = <0x4a0021e0 0xc
	0x4a00232c 0xc
	0x4a002380 0x2c
	0x4a0023C0 0x3c>;
	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
	compatible = "ti,omap5430-bandgap";

	#thermal-sensor-cells = <1>;
	};

	/* OCP2SCP3 */
	sata: sata@4a141100 {
	compatible = "snps,dwc-ahci";
	reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	phys = <&sata_phy>;
	phy-names = "sata-phy";
	clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
	ti,hwmods = "sata";
	ports-implemented = <0x1>;
	};

	target-module@56000000 {
	compatible = "ti,sysc-omap4", "ti,sysc";
	reg = <0x5600fe00 0x4>,
	<0x5600fe10 0x4>;
	reg-names = "rev", "sysc";
	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	<SYSC_IDLE_NO>,
	<SYSC_IDLE_SMART>;
	clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x56000000 0x2000000>;

	/*
	* Closed source PowerVR driver, no child device
	* binding or driver in mainline
	*/
	};

	- dss: dss@58000000 {
	- compatible = "ti,omap5-dss";
	- reg = <0x58000000 0x80>;
	- status = "disabled";
	- ti,hwmods = "dss_core";
	- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
	- clock-names = "fck";
	+ target-module@58000000 {
	+ compatible = "ti,sysc-omap2", "ti,sysc";
	+ reg = <0x58000000 4>,
	+ <0x58000014 4>;
	+ reg-names = "rev", "syss";
	+ ti,syss-mask = <1>;
	+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
	+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
	+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
	+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
	+ clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
	#address-cells = <1>;
	#size-cells = <1>;
	- ranges;
	+ ranges = <0 0x58000000 0x1000000>;

	- dispc@58001000 {
	- compatible = "ti,omap5-dispc";
	- reg = <0x58001000 0x1000>;
	- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	- ti,hwmods = "dss_dispc";
	+ dss: dss@0 {
	+ compatible = "ti,omap5-dss";
	+ reg = <0 0x80>;
	+ status = "disabled";
	clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
	clock-names = "fck";
	- };
	-
	- rfbi: encoder@58002000 {
	- compatible = "ti,omap5-rfbi";
	- reg = <0x58002000 0x100>;
	- status = "disabled";
	- ti,hwmods = "dss_rfbi";
	- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
	- clock-names = "fck", "ick";
	- };
	-
	- dsi1: encoder@58004000 {
	- compatible = "ti,omap5-dsi";
	- reg = <0x58004000 0x200>,
	- <0x58004200 0x40>,
	- <0x58004300 0x40>;
	- reg-names = "proto", "phy", "pll";
	- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	- status = "disabled";
	- ti,hwmods = "dss_dsi1";
	- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
	- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
	- clock-names = "fck", "sys_clk";
	- };
	-
	- dsi2: encoder@58005000 {
	- compatible = "ti,omap5-dsi";
	- reg = <0x58009000 0x200>,
	- <0x58009200 0x40>,
	- <0x58009300 0x40>;
	- reg-names = "proto", "phy", "pll";
	- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	- status = "disabled";
	- ti,hwmods = "dss_dsi2";
	- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
	- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
	- clock-names = "fck", "sys_clk";
	- };
	-
	- hdmi: encoder@58060000 {
	- compatible = "ti,omap5-hdmi";
	- reg = <0x58040000 0x200>,
	- <0x58040200 0x80>,
	- <0x58040300 0x80>,
	- <0x58060000 0x19000>;
	- reg-names = "wp", "pll", "phy", "core";
	- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	- status = "disabled";
	- ti,hwmods = "dss_hdmi";
	- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
	- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
	- clock-names = "fck", "sys_clk";
	- dmas = <&sdma 76>;
	- dma-names = "audio_tx";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0 0x1000000>;
	+
	+ target-module@1000 {
	+ compatible = "ti,sysc-omap2", "ti,sysc";
	+ reg = <0x1000 0x4>,
	+ <0x1010 0x4>,
	+ <0x1014 0x4>;
	+ reg-names = "rev", "sysc", "syss";
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	+ SYSC_OMAP2_ENAWAKEUP \|
	+ SYSC_OMAP2_SOFTRESET \|
	+ SYSC_OMAP2_AUTOIDLE)>;
	+ ti,syss-mask = <1>;
	+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x1000 0x1000>;
	+
	+ dispc@0 {
	+ compatible = "ti,omap5-dispc";
	+ reg = <0 0x1000>;
	+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
	+ clock-names = "fck";
	+ };
	+ };
	+
	+ target-module@2000 {
	+ compatible = "ti,sysc-omap2", "ti,sysc";
	+ reg = <0x2000 0x4>,
	+ <0x2010 0x4>,
	+ <0x2014 0x4>;
	+ reg-names = "rev", "sysc", "syss";
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	+ SYSC_OMAP2_AUTOIDLE)>;
	+ ti,syss-mask = <1>;
	+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
	+ clock-names = "fck";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x2000 0x1000>;
	+
	+ rfbi: encoder@0 {
	+ compatible = "ti,omap5-rfbi";
	+ reg = <0 0x100>;
	+ status = "disabled";
	+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
	+ clock-names = "fck", "ick";
	+ };
	+ };
	+
	+ target-module@5000 {
	+ compatible = "ti,sysc-omap2", "ti,sysc";
	+ reg = <0x5000 0x4>,
	+ <0x5010 0x4>,
	+ <0x5014 0x4>;
	+ reg-names = "rev", "sysc", "syss";
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	+ SYSC_OMAP2_ENAWAKEUP \|
	+ SYSC_OMAP2_SOFTRESET \|
	+ SYSC_OMAP2_AUTOIDLE)>;
	+ ti,syss-mask = <1>;
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x5000 0x1000>;
	+
	+ dsi1: encoder@0 {
	+ compatible = "ti,omap5-dsi";
	+ reg = <0 0x200>,
	+ <0x200 0x40>,
	+ <0x300 0x40>;
	+ reg-names = "proto", "phy", "pll";
	+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	+ status = "disabled";
	+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
	+ clock-names = "fck";
	+ };
	+ };
	+
	+ target-module@9000 {
	+ compatible = "ti,sysc-omap2", "ti,sysc";
	+ reg = <0x9000 0x4>,
	+ <0x9010 0x4>,
	+ <0x9014 0x4>;
	+ reg-names = "rev", "sysc", "syss";
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>;
	+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	+ SYSC_OMAP2_ENAWAKEUP \|
	+ SYSC_OMAP2_SOFTRESET \|
	+ SYSC_OMAP2_AUTOIDLE)>;
	+ ti,syss-mask = <1>;
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x9000 0x1000>;
	+
	+ dsi2: encoder@0 {
	+ compatible = "ti,omap5-dsi";
	+ reg = <0 0x200>,
	+ <0x200 0x40>,
	+ <0x300 0x40>;
	+ reg-names = "proto", "phy", "pll";
	+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	+ status = "disabled";
	+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
	+ clock-names = "fck";
	+ };
	+ };
	+
	+ target-module@40000 {
	+ compatible = "ti,sysc-omap4", "ti,sysc";
	+ reg = <0x40000 0x4>,
	+ <0x40010 0x4>;
	+ reg-names = "rev", "sysc";
	+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	+ <SYSC_IDLE_NO>,
	+ <SYSC_IDLE_SMART>,
	+ <SYSC_IDLE_SMART_WKUP>;
	+ ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
	+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
	+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
	+ clock-names = "fck", "dss_clk";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x40000 0x40000>;
	+
	+ hdmi: encoder@0 {
	+ compatible = "ti,omap5-hdmi";
	+ reg = <0 0x200>,
	+ <0x200 0x80>,
	+ <0x300 0x80>,
	+ <0x20000 0x19000>;
	+ reg-names = "wp", "pll", "phy", "core";
	+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	+ status = "disabled";
	+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
	+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
	+ clock-names = "fck", "sys_clk";
	+ dmas = <&sdma 76>;
	+ dma-names = "audio_tx";
	+ };
	+ };
	};
	};

	abb_mpu: regulator-abb-mpu {
	compatible = "ti,abb-v2";
	regulator-name = "abb_mpu";
	#address-cells = <0>;
	#size-cells = <0>;
	clocks = <&sys_clkin>;
	ti,settling-time = <50>;
	ti,clock-cycles = <16>;

	reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
	<0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
	reg-names = "base-address", "int-address",
	"efuse-address", "ldo-address";
	ti,tranxdone-status-mask = <0x80>;
	/* LDOVBBMPU_MUX_CTRL */
	ti,ldovbb-override-mask = <0x400>;
	/* LDOVBBMPU_VSET_OUT */
	ti,ldovbb-vset-mask = <0x1F>;

	/*
	* NOTE: only FBB mode used but actual vset will
	* determine final biasing
	*/
	ti,abb_info = <
	/uV ABB efuse rbb_m fbb_m vset_m/
	1060000 0 0x0 0 0x02000000 0x01F00000
	1250000 0 0x4 0 0x02000000 0x01F00000
	>;
	};

	abb_mm: regulator-abb-mm {
	compatible = "ti,abb-v2";
	regulator-name = "abb_mm";
	#address-cells = <0>;
	#size-cells = <0>;
	clocks = <&sys_clkin>;
	ti,settling-time = <50>;
	ti,clock-cycles = <16>;

	reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
	<0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
	reg-names = "base-address", "int-address",
	"efuse-address", "ldo-address";
	ti,tranxdone-status-mask = <0x80000000>;
	/* LDOVBBMM_MUX_CTRL */
	ti,ldovbb-override-mask = <0x400>;
	/* LDOVBBMM_VSET_OUT */
	ti,ldovbb-vset-mask = <0x1F>;

	/*
	* NOTE: only FBB mode used but actual vset will
	* determine final biasing
	*/
	ti,abb_info = <
	/uV ABB efuse rbb_m fbb_m vset_m/
	1025000 0 0x0 0 0x02000000 0x01F00000
	1120000 0 0x4 0 0x02000000 0x01F00000
	>;
	};
	};
	};

	&cpu_thermal {
	polling-delay = <500>; /* milliseconds */
	coefficients = <65 (-1791)>;
	};

	#include "omap5-l4.dtsi"
	#include "omap54xx-clocks.dtsi"

	&gpu_thermal {
	coefficients = <117 (-2992)>;
	};

	&core_thermal {
	coefficients = <0 2000>;
	};

	#include "omap5-l4-abe.dtsi"
	#include "omap54xx-clocks.dtsi"

	&prm {
	prm_dsp: prm@400 {
	compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
	reg = <0x400 0x100>;
	#reset-cells = <1>;
	};

	prm_core: prm@700 {
	compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
	reg = <0x700 0x100>;
	#reset-cells = <1>;
	};

	prm_iva: prm@1200 {
	compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
	reg = <0x1200 0x100>;
	#reset-cells = <1>;
	};

	prm_device: prm@1c00 {
	compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
	reg = <0x1c00 0x100>;
	#reset-cells = <1>;
	};
	};
	diff --git a/sys/gnu/dts/arm/pxa168-aspenite.dts b/sys/gnu/dts/arm/pxa168-aspenite.dts
	index 2ad40e373194..8bade6bf395b 100644
	--- a/sys/gnu/dts/arm/pxa168-aspenite.dts
	+++ b/sys/gnu/dts/arm/pxa168-aspenite.dts
	@@ -1,35 +1,33 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2012 Marvell Technology Group Ltd.
	* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
	*/

	/dts-v1/;
	#include "pxa168.dtsi"

	/ {
	model = "Marvell PXA168 Aspenite Development Board";
	compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";

	chosen {
	bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
	};

	memory {
	reg = <0x00000000 0x04000000>;
	};
	+};

	- soc {
	- apb@d4000000 {
	- uart1: uart@d4017000 {
	- status = "okay";
	- };
	- twsi1: i2c@d4011000 {
	- status = "okay";
	- };
	- rtc: rtc@d4010000 {
	- status = "okay";
	- };
	- };
	- };
	+&uart1 {
	+ status = "okay";
	+};
	+
	+&twsi1 {
	+ status = "okay";
	+};
	+
	+&rtc {
	+ status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/pxa168.dtsi b/sys/gnu/dts/arm/pxa168.dtsi
	index 72f8cb60cb53..9a9e38245e88 100644
	--- a/sys/gnu/dts/arm/pxa168.dtsi
	+++ b/sys/gnu/dts/arm/pxa168.dtsi
	@@ -1,157 +1,160 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2012 Marvell Technology Group Ltd.
	* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
	*/

	#include <dt-bindings/clock/marvell,pxa168.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	i2c0 = &twsi1;
	i2c1 = &twsi2;
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&intc>;
	ranges;

	axi@d4200000 { /* AXI */
	compatible = "mrvl,axi-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0xd4200000 0x00200000>;
	ranges;

	intc: interrupt-controller@d4282000 {
	compatible = "mrvl,mmp-intc";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0xd4282000 0x1000>;
	mrvl,intc-nr-irqs = <64>;
	};

	};

	apb@d4000000 { /* APB */
	compatible = "mrvl,apb-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0xd4000000 0x00200000>;
	ranges;

	timer0: timer@d4014000 {
	compatible = "mrvl,mmp-timer";
	reg = <0xd4014000 0x100>;
	interrupts = <13>;
	};

	- uart1: uart@d4017000 {
	- compatible = "mrvl,mmp-uart";
	+ uart1: serial@d4017000 {
	+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
	reg = <0xd4017000 0x1000>;
	+ reg-shift = <2>;
	interrupts = <27>;
	clocks = <&soc_clocks PXA168_CLK_UART0>;
	resets = <&soc_clocks PXA168_CLK_UART0>;
	status = "disabled";
	};

	- uart2: uart@d4018000 {
	- compatible = "mrvl,mmp-uart";
	+ uart2: serial@d4018000 {
	+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
	reg = <0xd4018000 0x1000>;
	+ reg-shift = <2>;
	interrupts = <28>;
	clocks = <&soc_clocks PXA168_CLK_UART1>;
	resets = <&soc_clocks PXA168_CLK_UART1>;
	status = "disabled";
	};

	- uart3: uart@d4026000 {
	- compatible = "mrvl,mmp-uart";
	+ uart3: serial@d4026000 {
	+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
	reg = <0xd4026000 0x1000>;
	+ reg-shift = <2>;
	interrupts = <29>;
	clocks = <&soc_clocks PXA168_CLK_UART2>;
	resets = <&soc_clocks PXA168_CLK_UART2>;
	status = "disabled";
	};

	gpio@d4019000 {
	compatible = "marvell,mmp-gpio";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0xd4019000 0x1000>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupts = <49>;
	clocks = <&soc_clocks PXA168_CLK_GPIO>;
	resets = <&soc_clocks PXA168_CLK_GPIO>;
	interrupt-names = "gpio_mux";
	interrupt-controller;
	#interrupt-cells = <1>;
	ranges;

	gcb0: gpio@d4019000 {
	reg = <0xd4019000 0x4>;
	};

	gcb1: gpio@d4019004 {
	reg = <0xd4019004 0x4>;
	};

	gcb2: gpio@d4019008 {
	reg = <0xd4019008 0x4>;
	};

	gcb3: gpio@d4019100 {
	reg = <0xd4019100 0x4>;
	};
	};

	twsi1: i2c@d4011000 {
	compatible = "mrvl,mmp-twsi";
	reg = <0xd4011000 0x1000>;
	interrupts = <7>;
	clocks = <&soc_clocks PXA168_CLK_TWSI0>;
	resets = <&soc_clocks PXA168_CLK_TWSI0>;
	mrvl,i2c-fast-mode;
	status = "disabled";
	};

	twsi2: i2c@d4025000 {
	compatible = "mrvl,mmp-twsi";
	reg = <0xd4025000 0x1000>;
	interrupts = <58>;
	clocks = <&soc_clocks PXA168_CLK_TWSI1>;
	resets = <&soc_clocks PXA168_CLK_TWSI1>;
	status = "disabled";
	};

	rtc: rtc@d4010000 {
	compatible = "mrvl,mmp-rtc";
	reg = <0xd4010000 0x1000>;
	interrupts = <5 6>;
	interrupt-names = "rtc 1Hz", "rtc alarm";
	clocks = <&soc_clocks PXA168_CLK_RTC>;
	resets = <&soc_clocks PXA168_CLK_RTC>;
	status = "disabled";
	};
	};

	soc_clocks: clocks{
	compatible = "marvell,pxa168-clock";
	reg = <0xd4050000 0x1000>,
	<0xd4282800 0x400>,
	<0xd4015000 0x1000>;
	reg-names = "mpmu", "apmu", "apbc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/pxa910-dkb.dts b/sys/gnu/dts/arm/pxa910-dkb.dts
	index 0f899e672e82..ce76158867c7 100644
	--- a/sys/gnu/dts/arm/pxa910-dkb.dts
	+++ b/sys/gnu/dts/arm/pxa910-dkb.dts
	@@ -1,172 +1,170 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2012 Marvell Technology Group Ltd.
	* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
	*/

	/dts-v1/;
	#include "pxa910.dtsi"

	/ {
	model = "Marvell PXA910 DKB Development Board";
	compatible = "mrvl,pxa910-dkb", "mrvl,pxa910";

	chosen {
	bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
	};

	memory {
	reg = <0x00000000 0x10000000>;
	};
	+};

	- soc {
	- apb@d4000000 {
	- uart1: uart@d4017000 {
	- status = "okay";
	- };
	- twsi1: i2c@d4011000 {
	- status = "okay";
	+&uart1 {
	+ status = "okay";
	+};
	+
	+&twsi1 {
	+ status = "okay";

	- pmic: 88pm860x@34 {
	- compatible = "marvell,88pm860x";
	- reg = <0x34>;
	- interrupts = <4>;
	- interrupt-parent = <&intc>;
	- interrupt-controller;
	- #interrupt-cells = <1>;
	+ pmic: 88pm860x@34 {
	+ compatible = "marvell,88pm860x";
	+ reg = <0x34>;
	+ interrupts = <4>;
	+ interrupt-parent = <&intc>;
	+ interrupt-controller;
	+ #interrupt-cells = <1>;

	- marvell,88pm860x-irq-read-clr;
	- marvell,88pm860x-slave-addr = <0x11>;
	+ marvell,88pm860x-irq-read-clr;
	+ marvell,88pm860x-slave-addr = <0x11>;

	- regulators {
	- BUCK1 {
	- regulator-min-microvolt = <1000000>;
	- regulator-max-microvolt = <1500000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- BUCK2 {
	- regulator-min-microvolt = <1000000>;
	- regulator-max-microvolt = <1500000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- BUCK3 {
	- regulator-min-microvolt = <1000000>;
	- regulator-max-microvolt = <3000000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO1 {
	- regulator-min-microvolt = <1200000>;
	- regulator-max-microvolt = <2800000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO2 {
	- regulator-min-microvolt = <1800000>;
	- regulator-max-microvolt = <3300000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO3 {
	- regulator-min-microvolt = <1800000>;
	- regulator-max-microvolt = <3300000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO4 {
	- regulator-min-microvolt = <1800000>;
	- regulator-max-microvolt = <3300000>;
	- regulator-always-on;
	- };
	- LDO5 {
	- regulator-min-microvolt = <2900000>;
	- regulator-max-microvolt = <3300000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO6 {
	- regulator-min-microvolt = <1800000>;
	- regulator-max-microvolt = <3300000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO7 {
	- regulator-min-microvolt = <1800000>;
	- regulator-max-microvolt = <2900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO8 {
	- regulator-min-microvolt = <1800000>;
	- regulator-max-microvolt = <2900000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO9 {
	- regulator-min-microvolt = <1800000>;
	- regulator-max-microvolt = <3300000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO10 {
	- regulator-min-microvolt = <1200000>;
	- regulator-max-microvolt = <3300000>;
	- regulator-boot-on;
	- regulator-always-on;
	- };
	- LDO12 {
	- regulator-min-microvolt = <1200000>;
	- regulator-max-microvolt = <3300000>;
	- regulator-always-on;
	- };
	- LDO13 {
	- regulator-min-microvolt = <1200000>;
	- regulator-max-microvolt = <3300000>;
	- regulator-always-on;
	- };
	- LDO14 {
	- regulator-min-microvolt = <1800000>;
	- regulator-max-microvolt = <3300000>;
	- regulator-always-on;
	- };
	- };
	- rtc {
	- marvell,88pm860x-vrtc = <1>;
	- };
	- touch {
	- marvell,88pm860x-gpadc-prebias = <1>;
	- marvell,88pm860x-gpadc-slot-cycle = <1>;
	- marvell,88pm860x-tsi-prebias = <6>;
	- marvell,88pm860x-pen-prebias = <16>;
	- marvell,88pm860x-pen-prechg = <2>;
	- marvell,88pm860x-resistor-X = <300>;
	- };
	- backlights {
	- backlight-0 {
	- marvell,88pm860x-iset = <4>;
	- marvell,88pm860x-pwm = <3>;
	- };
	- backlight-2 {
	- };
	- };
	- leds {
	- led0-red {
	- marvell,88pm860x-iset = <12>;
	- };
	- led0-green {
	- marvell,88pm860x-iset = <12>;
	- };
	- led0-blue {
	- marvell,88pm860x-iset = <12>;
	- };
	- };
	- };
	- };
	- rtc: rtc@d4010000 {
	- status = "okay";
	+ regulators {
	+ BUCK1 {
	+ regulator-min-microvolt = <1000000>;
	+ regulator-max-microvolt = <1500000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ BUCK2 {
	+ regulator-min-microvolt = <1000000>;
	+ regulator-max-microvolt = <1500000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ BUCK3 {
	+ regulator-min-microvolt = <1000000>;
	+ regulator-max-microvolt = <3000000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO1 {
	+ regulator-min-microvolt = <1200000>;
	+ regulator-max-microvolt = <2800000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO2 {
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <3300000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO3 {
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <3300000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO4 {
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <3300000>;
	+ regulator-always-on;
	+ };
	+ LDO5 {
	+ regulator-min-microvolt = <2900000>;
	+ regulator-max-microvolt = <3300000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO6 {
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <3300000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO7 {
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <2900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO8 {
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <2900000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO9 {
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <3300000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO10 {
	+ regulator-min-microvolt = <1200000>;
	+ regulator-max-microvolt = <3300000>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+ LDO12 {
	+ regulator-min-microvolt = <1200000>;
	+ regulator-max-microvolt = <3300000>;
	+ regulator-always-on;
	+ };
	+ LDO13 {
	+ regulator-min-microvolt = <1200000>;
	+ regulator-max-microvolt = <3300000>;
	+ regulator-always-on;
	+ };
	+ LDO14 {
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <3300000>;
	+ regulator-always-on;
	+ };
	+ };
	+ rtc {
	+ marvell,88pm860x-vrtc = <1>;
	+ };
	+ touch {
	+ marvell,88pm860x-gpadc-prebias = <1>;
	+ marvell,88pm860x-gpadc-slot-cycle = <1>;
	+ marvell,88pm860x-tsi-prebias = <6>;
	+ marvell,88pm860x-pen-prebias = <16>;
	+ marvell,88pm860x-pen-prechg = <2>;
	+ marvell,88pm860x-resistor-X = <300>;
	+ };
	+ backlights {
	+ backlight-0 {
	+ marvell,88pm860x-iset = <4>;
	+ marvell,88pm860x-pwm = <3>;
	+ };
	+ backlight-2 {
	+ };
	+ };
	+ leds {
	+ led0-red {
	+ marvell,88pm860x-iset = <12>;
	+ };
	+ led0-green {
	+ marvell,88pm860x-iset = <12>;
	+ };
	+ led0-blue {
	+ marvell,88pm860x-iset = <12>;
	};
	};
	};
	};
	+
	+&rtc {
	+ status = "okay";
	+};
	diff --git a/sys/gnu/dts/arm/pxa910.dtsi b/sys/gnu/dts/arm/pxa910.dtsi
	index b3d6182d4de4..587a5e7f0702 100644
	--- a/sys/gnu/dts/arm/pxa910.dtsi
	+++ b/sys/gnu/dts/arm/pxa910.dtsi
	@@ -1,174 +1,177 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (C) 2012 Marvell Technology Group Ltd.
	* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
	*/

	#include <dt-bindings/clock/marvell,pxa910.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	i2c0 = &twsi1;
	i2c1 = &twsi2;
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&intc>;
	ranges;

	L2: l2-cache {
	compatible = "marvell,tauros2-cache";
	marvell,tauros2-cache-features = <0x3>;
	};

	axi@d4200000 { /* AXI */
	compatible = "mrvl,axi-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0xd4200000 0x00200000>;
	ranges;

	intc: interrupt-controller@d4282000 {
	compatible = "mrvl,mmp-intc";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0xd4282000 0x1000>;
	mrvl,intc-nr-irqs = <64>;
	};

	};

	apb@d4000000 { /* APB */
	compatible = "mrvl,apb-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0xd4000000 0x00200000>;
	ranges;

	timer0: timer@d4014000 {
	compatible = "mrvl,mmp-timer";
	reg = <0xd4014000 0x100>;
	interrupts = <13>;
	};

	timer1: timer@d4016000 {
	compatible = "mrvl,mmp-timer";
	reg = <0xd4016000 0x100>;
	interrupts = <29>;
	status = "disabled";
	};

	- uart1: uart@d4017000 {
	- compatible = "mrvl,mmp-uart";
	+ uart1: serial@d4017000 {
	+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
	reg = <0xd4017000 0x1000>;
	+ reg-shift = <2>;
	interrupts = <27>;
	clocks = <&soc_clocks PXA910_CLK_UART0>;
	resets = <&soc_clocks PXA910_CLK_UART0>;
	status = "disabled";
	};

	- uart2: uart@d4018000 {
	- compatible = "mrvl,mmp-uart";
	+ uart2: serial@d4018000 {
	+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
	reg = <0xd4018000 0x1000>;
	+ reg-shift = <2>;
	interrupts = <28>;
	clocks = <&soc_clocks PXA910_CLK_UART1>;
	resets = <&soc_clocks PXA910_CLK_UART1>;
	status = "disabled";
	};

	- uart3: uart@d4036000 {
	- compatible = "mrvl,mmp-uart";
	+ uart3: serial@d4036000 {
	+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
	reg = <0xd4036000 0x1000>;
	+ reg-shift = <2>;
	interrupts = <59>;
	clocks = <&soc_clocks PXA910_CLK_UART2>;
	resets = <&soc_clocks PXA910_CLK_UART2>;
	status = "disabled";
	};

	gpio@d4019000 {
	compatible = "marvell,mmp-gpio";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0xd4019000 0x1000>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupts = <49>;
	interrupt-names = "gpio_mux";
	clocks = <&soc_clocks PXA910_CLK_GPIO>;
	resets = <&soc_clocks PXA910_CLK_GPIO>;
	interrupt-controller;
	#interrupt-cells = <1>;
	ranges;

	gcb0: gpio@d4019000 {
	reg = <0xd4019000 0x4>;
	};

	gcb1: gpio@d4019004 {
	reg = <0xd4019004 0x4>;
	};

	gcb2: gpio@d4019008 {
	reg = <0xd4019008 0x4>;
	};

	gcb3: gpio@d4019100 {
	reg = <0xd4019100 0x4>;
	};
	};

	twsi1: i2c@d4011000 {
	compatible = "mrvl,mmp-twsi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xd4011000 0x1000>;
	interrupts = <7>;
	clocks = <&soc_clocks PXA910_CLK_TWSI0>;
	resets = <&soc_clocks PXA910_CLK_TWSI0>;
	mrvl,i2c-fast-mode;
	status = "disabled";
	};

	twsi2: i2c@d4037000 {
	compatible = "mrvl,mmp-twsi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xd4037000 0x1000>;
	interrupts = <54>;
	clocks = <&soc_clocks PXA910_CLK_TWSI1>;
	resets = <&soc_clocks PXA910_CLK_TWSI1>;
	status = "disabled";
	};

	rtc: rtc@d4010000 {
	compatible = "mrvl,mmp-rtc";
	reg = <0xd4010000 0x1000>;
	interrupts = <5 6>;
	interrupt-names = "rtc 1Hz", "rtc alarm";
	clocks = <&soc_clocks PXA910_CLK_RTC>;
	resets = <&soc_clocks PXA910_CLK_RTC>;
	status = "disabled";
	};
	};

	soc_clocks: clocks{
	compatible = "marvell,pxa910-clock";
	reg = <0xd4050000 0x1000>,
	<0xd4282800 0x400>,
	<0xd4015000 0x1000>,
	<0xd403b000 0x1000>;
	reg-names = "mpmu", "apmu", "apbc", "apbcp";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/qcom-apq8064.dtsi b/sys/gnu/dts/arm/qcom-apq8064.dtsi
	index 8b79b4112ee1..2687c4e890ba 100644
	--- a/sys/gnu/dts/arm/qcom-apq8064.dtsi
	+++ b/sys/gnu/dts/arm/qcom-apq8064.dtsi
	@@ -1,1764 +1,1765 @@
	// SPDX-License-Identifier: GPL-2.0
	/dts-v1/;

	#include <dt-bindings/clock/qcom,gcc-msm8960.h>
	#include <dt-bindings/reset/qcom,gcc-msm8960.h>
	#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
	#include <dt-bindings/clock/qcom,rpmcc.h>
	#include <dt-bindings/soc/qcom,gsbi.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Qualcomm APQ8064";
	compatible = "qcom,apq8064";
	interrupt-parent = <&intc>;

	reserved-memory {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	smem_region: smem@80000000 {
	reg = <0x80000000 0x200000>;
	no-map;
	};

	wcnss_mem: wcnss@8f000000 {
	reg = <0x8f000000 0x700000>;
	no-map;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	CPU0: cpu@0 {
	compatible = "qcom,krait";
	enable-method = "qcom,kpss-acc-v1";
	device_type = "cpu";
	reg = <0>;
	next-level-cache = <&L2>;
	qcom,acc = <&acc0>;
	qcom,saw = <&saw0>;
	cpu-idle-states = <&CPU_SPC>;
	};

	CPU1: cpu@1 {
	compatible = "qcom,krait";
	enable-method = "qcom,kpss-acc-v1";
	device_type = "cpu";
	reg = <1>;
	next-level-cache = <&L2>;
	qcom,acc = <&acc1>;
	qcom,saw = <&saw1>;
	cpu-idle-states = <&CPU_SPC>;
	};

	CPU2: cpu@2 {
	compatible = "qcom,krait";
	enable-method = "qcom,kpss-acc-v1";
	device_type = "cpu";
	reg = <2>;
	next-level-cache = <&L2>;
	qcom,acc = <&acc2>;
	qcom,saw = <&saw2>;
	cpu-idle-states = <&CPU_SPC>;
	};

	CPU3: cpu@3 {
	compatible = "qcom,krait";
	enable-method = "qcom,kpss-acc-v1";
	device_type = "cpu";
	reg = <3>;
	next-level-cache = <&L2>;
	qcom,acc = <&acc3>;
	qcom,saw = <&saw3>;
	cpu-idle-states = <&CPU_SPC>;
	};

	L2: l2-cache {
	compatible = "cache";
	cache-level = <2>;
	};

	idle-states {
	CPU_SPC: spc {
	compatible = "qcom,idle-state-spc",
	"arm,idle-state";
	entry-latency-us = <400>;
	exit-latency-us = <900>;
	min-residency-us = <3000>;
	};
	};
	};

	memory {
	device_type = "memory";
	reg = <0x0 0x0>;
	};

	thermal-zones {
	cpu-thermal0 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&gcc 7>;
	coefficients = <1199 0>;

	trips {
	cpu_alert0: trip0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu_crit0: trip1 {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu-thermal1 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&gcc 8>;
	coefficients = <1132 0>;

	trips {
	cpu_alert1: trip0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu_crit1: trip1 {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu-thermal2 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&gcc 9>;
	coefficients = <1199 0>;

	trips {
	cpu_alert2: trip0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu_crit2: trip1 {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu-thermal3 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&gcc 10>;
	coefficients = <1132 0>;

	trips {
	cpu_alert3: trip0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu_crit3: trip1 {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};
	};

	cpu-pmu {
	compatible = "qcom,krait-pmu";
	interrupts = <1 10 0x304>;
	};

	clocks {
	cxo_board: cxo_board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <19200000>;
	};

	pxo_board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <27000000>;
	};

	sleep_clk: sleep_clk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	};

	sfpb_mutex: hwmutex {
	compatible = "qcom,sfpb-mutex";
	syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
	#hwlock-cells = <1>;
	};

	smem {
	compatible = "qcom,smem";
	memory-region = <&smem_region>;

	hwlocks = <&sfpb_mutex 3>;
	};

	smd {
	compatible = "qcom,smd";

	modem@0 {
	interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;

	qcom,ipc = <&l2cc 8 3>;
	qcom,smd-edge = <0>;

	status = "disabled";
	};

	q6@1 {
	interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;

	qcom,ipc = <&l2cc 8 15>;
	qcom,smd-edge = <1>;

	status = "disabled";
	};

	dsps@3 {
	interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;

	qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
	qcom,smd-edge = <3>;

	status = "disabled";
	};

	riva@6 {
	interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;

	qcom,ipc = <&l2cc 8 25>;
	qcom,smd-edge = <6>;

	status = "disabled";
	};
	};

	smsm {
	compatible = "qcom,smsm";

	#address-cells = <1>;
	#size-cells = <0>;

	qcom,ipc-1 = <&l2cc 8 4>;
	qcom,ipc-2 = <&l2cc 8 14>;
	qcom,ipc-3 = <&l2cc 8 23>;
	qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;

	apps_smsm: apps@0 {
	reg = <0>;
	#qcom,smem-state-cells = <1>;
	};

	modem_smsm: modem@1 {
	reg = <1>;
	interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	q6_smsm: q6@2 {
	reg = <2>;
	interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	wcnss_smsm: wcnss@3 {
	reg = <3>;
	interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	dsps_smsm: dsps@4 {
	reg = <4>;
	interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	firmware {
	scm {
	compatible = "qcom,scm-apq8064";

	clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
	clock-names = "core";
	};
	};


	/*
	* These channels from the ADC are simply hardware monitors.
	* That is why the ADC is referred to as "HKADC" - HouseKeeping
	* ADC.
	*/
	iio-hwmon {
	compatible = "iio-hwmon";
	io-channels = <&xoadc 0x00 0x01>, /* Battery */
	<&xoadc 0x00 0x02>, /* DC in (charger) */
	<&xoadc 0x00 0x04>, /* VPH the main system voltage */
	<&xoadc 0x00 0x0b>, /* Die temperature */
	<&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
	<&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
	<&xoadc 0x00 0x0e>; /* Charger temperature */
	};

	soc: soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "simple-bus";

	tlmm_pinmux: pinctrl@800000 {
	compatible = "qcom,apq8064-pinctrl";
	reg = <0x800000 0x4000>;

	gpio-controller;
	+ gpio-ranges = <&tlmm_pinmux 0 0 90>;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;

	pinctrl-names = "default";
	pinctrl-0 = <&ps_hold>;
	};

	sfpb_wrapper_mutex: syscon@1200000 {
	compatible = "syscon";
	reg = <0x01200000 0x8000>;
	};

	intc: interrupt-controller@2000000 {
	compatible = "qcom,msm-qgic2";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0x02000000 0x1000>,
	<0x02002000 0x1000>;
	};

	timer@200a000 {
	compatible = "qcom,kpss-timer",
	"qcom,kpss-wdt-apq8064", "qcom,msm-timer";
	interrupts = <1 1 0x301>,
	<1 2 0x301>,
	<1 3 0x301>;
	reg = <0x0200a000 0x100>;
	clock-frequency = <27000000>,
	<32768>;
	cpu-offset = <0x80000>;
	};

	acc0: clock-controller@2088000 {
	compatible = "qcom,kpss-acc-v1";
	reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
	};

	acc1: clock-controller@2098000 {
	compatible = "qcom,kpss-acc-v1";
	reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
	};

	acc2: clock-controller@20a8000 {
	compatible = "qcom,kpss-acc-v1";
	reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
	};

	acc3: clock-controller@20b8000 {
	compatible = "qcom,kpss-acc-v1";
	reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
	};

	saw0: power-controller@2089000 {
	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
	reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
	regulator;
	};

	saw1: power-controller@2099000 {
	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
	reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
	regulator;
	};

	saw2: power-controller@20a9000 {
	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
	reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
	regulator;
	};

	saw3: power-controller@20b9000 {
	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
	reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
	regulator;
	};

	sps_sic_non_secure: sps-sic-non-secure@12100000 {
	compatible = "syscon";
	reg = <0x12100000 0x10000>;
	};

	gsbi1: gsbi@12440000 {
	status = "disabled";
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <1>;
	reg = <0x12440000 0x100>;
	clocks = <&gcc GSBI1_H_CLK>;
	clock-names = "iface";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	syscon-tcsr = <&tcsr>;

	gsbi1_serial: serial@12450000 {
	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	reg = <0x12450000 0x100>,
	<0x12400000 0x03>;
	interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	gsbi1_i2c: i2c@12460000 {
	compatible = "qcom,i2c-qup-v1.1.1";
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-1 = <&i2c1_pins_sleep>;
	pinctrl-names = "default", "sleep";
	reg = <0x12460000 0x1000>;
	interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
	clock-names = "core", "iface";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	};

	gsbi2: gsbi@12480000 {
	status = "disabled";
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <2>;
	reg = <0x12480000 0x100>;
	clocks = <&gcc GSBI2_H_CLK>;
	clock-names = "iface";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	syscon-tcsr = <&tcsr>;

	gsbi2_i2c: i2c@124a0000 {
	compatible = "qcom,i2c-qup-v1.1.1";
	reg = <0x124a0000 0x1000>;
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-1 = <&i2c2_pins_sleep>;
	pinctrl-names = "default", "sleep";
	interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
	clock-names = "core", "iface";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};
	};

	gsbi3: gsbi@16200000 {
	status = "disabled";
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <3>;
	reg = <0x16200000 0x100>;
	clocks = <&gcc GSBI3_H_CLK>;
	clock-names = "iface";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	gsbi3_i2c: i2c@16280000 {
	compatible = "qcom,i2c-qup-v1.1.1";
	pinctrl-0 = <&i2c3_pins>;
	pinctrl-1 = <&i2c3_pins_sleep>;
	pinctrl-names = "default", "sleep";
	reg = <0x16280000 0x1000>;
	interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI3_QUP_CLK>,
	<&gcc GSBI3_H_CLK>;
	clock-names = "core", "iface";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};
	};

	gsbi4: gsbi@16300000 {
	status = "disabled";
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <4>;
	reg = <0x16300000 0x03>;
	clocks = <&gcc GSBI4_H_CLK>;
	clock-names = "iface";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	gsbi4_i2c: i2c@16380000 {
	compatible = "qcom,i2c-qup-v1.1.1";
	pinctrl-0 = <&i2c4_pins>;
	pinctrl-1 = <&i2c4_pins_sleep>;
	pinctrl-names = "default", "sleep";
	reg = <0x16380000 0x1000>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI4_QUP_CLK>,
	<&gcc GSBI4_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};
	};

	gsbi5: gsbi@1a200000 {
	status = "disabled";
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <5>;
	reg = <0x1a200000 0x03>;
	clocks = <&gcc GSBI5_H_CLK>;
	clock-names = "iface";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	gsbi5_serial: serial@1a240000 {
	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	reg = <0x1a240000 0x100>,
	<0x1a200000 0x03>;
	interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	gsbi5_spi: spi@1a280000 {
	compatible = "qcom,spi-qup-v1.1.1";
	reg = <0x1a280000 0x1000>;
	interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-0 = <&spi5_default>;
	pinctrl-1 = <&spi5_sleep>;
	pinctrl-names = "default", "sleep";
	clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	gsbi6: gsbi@16500000 {
	status = "disabled";
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <6>;
	reg = <0x16500000 0x03>;
	clocks = <&gcc GSBI6_H_CLK>;
	clock-names = "iface";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	gsbi6_serial: serial@16540000 {
	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	reg = <0x16540000 0x100>,
	<0x16500000 0x03>;
	interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	gsbi6_i2c: i2c@16580000 {
	compatible = "qcom,i2c-qup-v1.1.1";
	pinctrl-0 = <&i2c6_pins>;
	pinctrl-1 = <&i2c6_pins_sleep>;
	pinctrl-names = "default", "sleep";
	reg = <0x16580000 0x1000>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI6_QUP_CLK>,
	<&gcc GSBI6_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};
	};

	gsbi7: gsbi@16600000 {
	status = "disabled";
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <7>;
	reg = <0x16600000 0x100>;
	clocks = <&gcc GSBI7_H_CLK>;
	clock-names = "iface";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	syscon-tcsr = <&tcsr>;

	gsbi7_serial: serial@16640000 {
	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	reg = <0x16640000 0x1000>,
	<0x16600000 0x1000>;
	interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	gsbi7_i2c: i2c@16680000 {
	compatible = "qcom,i2c-qup-v1.1.1";
	pinctrl-0 = <&i2c7_pins>;
	pinctrl-1 = <&i2c7_pins_sleep>;
	pinctrl-names = "default", "sleep";
	reg = <0x16680000 0x1000>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI7_QUP_CLK>,
	<&gcc GSBI7_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};
	};

	rng@1a500000 {
	compatible = "qcom,prng";
	reg = <0x1a500000 0x200>;
	clocks = <&gcc PRNG_CLK>;
	clock-names = "core";
	};

	ssbi@c00000 {
	compatible = "qcom,ssbi";
	reg = <0x00c00000 0x1000>;
	qcom,controller-type = "pmic-arbiter";

	pm8821: pmic@1 {
	compatible = "qcom,pm8821";
	interrupt-parent = <&tlmm_pinmux>;
	interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
	#interrupt-cells = <2>;
	interrupt-controller;
	#address-cells = <1>;
	#size-cells = <0>;

	pm8821_mpps: mpps@50 {
	compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
	reg = <0x50>;
	interrupts = <24 IRQ_TYPE_NONE>,
	<25 IRQ_TYPE_NONE>,
	<26 IRQ_TYPE_NONE>,
	<27 IRQ_TYPE_NONE>;
	gpio-controller;
	#gpio-cells = <2>;
	};
	};
	};

	qcom,ssbi@500000 {
	compatible = "qcom,ssbi";
	reg = <0x00500000 0x1000>;
	qcom,controller-type = "pmic-arbiter";

	pmicintc: pmic@0 {
	compatible = "qcom,pm8921";
	interrupt-parent = <&tlmm_pinmux>;
	interrupts = <74 8>;
	#interrupt-cells = <2>;
	interrupt-controller;
	#address-cells = <1>;
	#size-cells = <0>;

	pm8921_gpio: gpio@150 {

	compatible = "qcom,pm8921-gpio",
	"qcom,ssbi-gpio";
	reg = <0x150>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pm8921_gpio 0 0 44>;
	#gpio-cells = <2>;

	};

	pm8921_mpps: mpps@50 {
	compatible = "qcom,pm8921-mpp",
	"qcom,ssbi-mpp";
	reg = <0x50>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupts =
	<128 IRQ_TYPE_NONE>,
	<129 IRQ_TYPE_NONE>,
	<130 IRQ_TYPE_NONE>,
	<131 IRQ_TYPE_NONE>,
	<132 IRQ_TYPE_NONE>,
	<133 IRQ_TYPE_NONE>,
	<134 IRQ_TYPE_NONE>,
	<135 IRQ_TYPE_NONE>,
	<136 IRQ_TYPE_NONE>,
	<137 IRQ_TYPE_NONE>,
	<138 IRQ_TYPE_NONE>,
	<139 IRQ_TYPE_NONE>;
	};

	rtc@11d {
	compatible = "qcom,pm8921-rtc";
	interrupt-parent = <&pmicintc>;
	interrupts = <39 1>;
	reg = <0x11d>;
	allow-set-time;
	};

	pwrkey@1c {
	compatible = "qcom,pm8921-pwrkey";
	reg = <0x1c>;
	interrupt-parent = <&pmicintc>;
	interrupts = <50 1>, <51 1>;
	debounce = <15625>;
	pull-up;
	};

	xoadc: xoadc@197 {
	compatible = "qcom,pm8921-adc";
	reg = <197>;
	interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
	#address-cells = <2>;
	#size-cells = <0>;
	#io-channel-cells = <2>;

	vcoin: adc-channel@00 {
	reg = <0x00 0x00>;
	};
	vbat: adc-channel@01 {
	reg = <0x00 0x01>;
	};
	dcin: adc-channel@02 {
	reg = <0x00 0x02>;
	};
	vph_pwr: adc-channel@04 {
	reg = <0x00 0x04>;
	};
	batt_therm: adc-channel@08 {
	reg = <0x00 0x08>;
	};
	batt_id: adc-channel@09 {
	reg = <0x00 0x09>;
	};
	usb_vbus: adc-channel@0a {
	reg = <0x00 0x0a>;
	};
	die_temp: adc-channel@0b {
	reg = <0x00 0x0b>;
	};
	ref_625mv: adc-channel@0c {
	reg = <0x00 0x0c>;
	};
	ref_1250mv: adc-channel@0d {
	reg = <0x00 0x0d>;
	};
	chg_temp: adc-channel@0e {
	reg = <0x00 0x0e>;
	};
	ref_muxoff: adc-channel@0f {
	reg = <0x00 0x0f>;
	};
	};
	};
	};

	qfprom: qfprom@700000 {
	compatible = "qcom,qfprom";
	reg = <0x00700000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	tsens_calib: calib {
	reg = <0x404 0x10>;
	};
	tsens_backup: backup_calib {
	reg = <0x414 0x10>;
	};
	};

	gcc: clock-controller@900000 {
	compatible = "qcom,gcc-apq8064";
	reg = <0x00900000 0x4000>;
	nvmem-cells = <&tsens_calib>, <&tsens_backup>;
	nvmem-cell-names = "calib", "calib_backup";
	#clock-cells = <1>;
	#reset-cells = <1>;
	#thermal-sensor-cells = <1>;
	};

	lcc: clock-controller@28000000 {
	compatible = "qcom,lcc-apq8064";
	reg = <0x28000000 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	mmcc: clock-controller@4000000 {
	compatible = "qcom,mmcc-apq8064";
	reg = <0x4000000 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	l2cc: clock-controller@2011000 {
	compatible = "syscon";
	reg = <0x2011000 0x1000>;
	};

	rpm@108000 {
	compatible = "qcom,rpm-apq8064";
	reg = <0x108000 0x1000>;
	qcom,ipc = <&l2cc 0x8 2>;

	interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "ack", "err", "wakeup";

	rpmcc: clock-controller {
	compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
	#clock-cells = <1>;
	};

	regulators {
	compatible = "qcom,rpm-pm8921-regulators";

	pm8921_s1: s1 {};
	pm8921_s2: s2 {};
	pm8921_s3: s3 {};
	pm8921_s4: s4 {};
	pm8921_s7: s7 {};
	pm8921_s8: s8 {};

	pm8921_l1: l1 {};
	pm8921_l2: l2 {};
	pm8921_l3: l3 {};
	pm8921_l4: l4 {};
	pm8921_l5: l5 {};
	pm8921_l6: l6 {};
	pm8921_l7: l7 {};
	pm8921_l8: l8 {};
	pm8921_l9: l9 {};
	pm8921_l10: l10 {};
	pm8921_l11: l11 {};
	pm8921_l12: l12 {};
	pm8921_l14: l14 {};
	pm8921_l15: l15 {};
	pm8921_l16: l16 {};
	pm8921_l17: l17 {};
	pm8921_l18: l18 {};
	pm8921_l21: l21 {};
	pm8921_l22: l22 {};
	pm8921_l23: l23 {};
	pm8921_l24: l24 {};
	pm8921_l25: l25 {};
	pm8921_l26: l26 {};
	pm8921_l27: l27 {};
	pm8921_l28: l28 {};
	pm8921_l29: l29 {};

	pm8921_lvs1: lvs1 {};
	pm8921_lvs2: lvs2 {};
	pm8921_lvs3: lvs3 {};
	pm8921_lvs4: lvs4 {};
	pm8921_lvs5: lvs5 {};
	pm8921_lvs6: lvs6 {};
	pm8921_lvs7: lvs7 {};

	pm8921_usb_switch: usb-switch {};

	pm8921_hdmi_switch: hdmi-switch {
	bias-pull-down;
	};

	pm8921_ncp: ncp {};
	};
	};

	usb1: usb@12500000 {
	compatible = "qcom,ci-hdrc";
	reg = <0x12500000 0x200>,
	<0x12500200 0x200>;
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
	clock-names = "core", "iface";
	assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
	assigned-clock-rates = <60000000>;
	resets = <&gcc USB_HS1_RESET>;
	reset-names = "core";
	phy_type = "ulpi";
	ahb-burst-config = <0>;
	phys = <&usb_hs1_phy>;
	phy-names = "usb-phy";
	status = "disabled";
	#reset-cells = <1>;

	ulpi {
	usb_hs1_phy: phy {
	compatible = "qcom,usb-hs-phy-apq8064",
	"qcom,usb-hs-phy";
	clocks = <&sleep_clk>, <&cxo_board>;
	clock-names = "sleep", "ref";
	resets = <&usb1 0>;
	reset-names = "por";
	#phy-cells = <0>;
	};
	};
	};

	usb3: usb@12520000 {
	compatible = "qcom,ci-hdrc";
	reg = <0x12520000 0x200>,
	<0x12520200 0x200>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
	clock-names = "core", "iface";
	assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
	assigned-clock-rates = <60000000>;
	resets = <&gcc USB_HS3_RESET>;
	reset-names = "core";
	phy_type = "ulpi";
	ahb-burst-config = <0>;
	phys = <&usb_hs3_phy>;
	phy-names = "usb-phy";
	status = "disabled";
	#reset-cells = <1>;

	ulpi {
	usb_hs3_phy: phy {
	compatible = "qcom,usb-hs-phy-apq8064",
	"qcom,usb-hs-phy";
	#phy-cells = <0>;
	clocks = <&sleep_clk>, <&cxo_board>;
	clock-names = "sleep", "ref";
	resets = <&usb3 0>;
	reset-names = "por";
	};
	};
	};

	usb4: usb@12530000 {
	compatible = "qcom,ci-hdrc";
	reg = <0x12530000 0x200>,
	<0x12530200 0x200>;
	interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
	clock-names = "core", "iface";
	assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
	assigned-clock-rates = <60000000>;
	resets = <&gcc USB_HS4_RESET>;
	reset-names = "core";
	phy_type = "ulpi";
	ahb-burst-config = <0>;
	phys = <&usb_hs4_phy>;
	phy-names = "usb-phy";
	status = "disabled";
	#reset-cells = <1>;

	ulpi {
	usb_hs4_phy: phy {
	compatible = "qcom,usb-hs-phy-apq8064",
	"qcom,usb-hs-phy";
	#phy-cells = <0>;
	clocks = <&sleep_clk>, <&cxo_board>;
	clock-names = "sleep", "ref";
	resets = <&usb4 0>;
	reset-names = "por";
	};
	};
	};

	sata_phy0: phy@1b400000 {
	compatible = "qcom,apq8064-sata-phy";
	status = "disabled";
	reg = <0x1b400000 0x200>;
	reg-names = "phy_mem";
	clocks = <&gcc SATA_PHY_CFG_CLK>;
	clock-names = "cfg";
	#phy-cells = <0>;
	};

	sata0: sata@29000000 {
	compatible = "qcom,apq8064-ahci", "generic-ahci";
	status = "disabled";
	reg = <0x29000000 0x180>;
	interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc SFAB_SATA_S_H_CLK>,
	<&gcc SATA_H_CLK>,
	<&gcc SATA_A_CLK>,
	<&gcc SATA_RXOOB_CLK>,
	<&gcc SATA_PMALIVE_CLK>;
	clock-names = "slave_iface",
	"iface",
	"bus",
	"rxoob",
	"core_pmalive";

	assigned-clocks = <&gcc SATA_RXOOB_CLK>,
	<&gcc SATA_PMALIVE_CLK>;
	assigned-clock-rates = <100000000>, <100000000>;

	phys = <&sata_phy0>;
	phy-names = "sata-phy";
	ports-implemented = <0x1>;
	};

	/* Temporary fixed regulator */
	sdcc1bam:dma@12402000{
	compatible = "qcom,bam-v1.3.0";
	reg = <0x12402000 0x8000>;
	interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc SDC1_H_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	};

	sdcc3bam:dma@12182000{
	compatible = "qcom,bam-v1.3.0";
	reg = <0x12182000 0x8000>;
	interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc SDC3_H_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	};

	sdcc4bam:dma@121c2000{
	compatible = "qcom,bam-v1.3.0";
	reg = <0x121c2000 0x8000>;
	interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc SDC4_H_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	};

	amba {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	sdcc1: sdcc@12400000 {
	status = "disabled";
	compatible = "arm,pl18x", "arm,primecell";
	pinctrl-names = "default";
	pinctrl-0 = <&sdcc1_pins>;
	arm,primecell-periphid = <0x00051180>;
	reg = <0x12400000 0x2000>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
	clock-names = "mclk", "apb_pclk";
	bus-width = <8>;
	max-frequency = <96000000>;
	non-removable;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
	dma-names = "tx", "rx";
	};

	sdcc3: sdcc@12180000 {
	compatible = "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x00051180>;
	status = "disabled";
	reg = <0x12180000 0x2000>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
	clock-names = "mclk", "apb_pclk";
	bus-width = <4>;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	max-frequency = <192000000>;
	no-1-8-v;
	dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
	dma-names = "tx", "rx";
	};

	sdcc4: sdcc@121c0000 {
	compatible = "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x00051180>;
	status = "disabled";
	reg = <0x121c0000 0x2000>;
	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
	clock-names = "mclk", "apb_pclk";
	bus-width = <4>;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	max-frequency = <48000000>;
	dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&sdc4_gpios>;
	};
	};

	tcsr: syscon@1a400000 {
	compatible = "qcom,tcsr-apq8064", "syscon";
	reg = <0x1a400000 0x100>;
	};

	gpu: adreno-3xx@4300000 {
	compatible = "qcom,adreno-3xx";
	reg = <0x04300000 0x20000>;
	reg-names = "kgsl_3d0_reg_memory";
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "kgsl_3d0_irq";
	clock-names =
	"core_clk",
	"iface_clk",
	"mem_clk",
	"mem_iface_clk";
	clocks =
	<&mmcc GFX3D_CLK>,
	<&mmcc GFX3D_AHB_CLK>,
	<&mmcc GFX3D_AXI_CLK>,
	<&mmcc MMSS_IMEM_AHB_CLK>;
	qcom,chipid = <0x03020002>;

	iommus = <&gfx3d 0
	&gfx3d 1
	&gfx3d 2
	&gfx3d 3
	&gfx3d 4
	&gfx3d 5
	&gfx3d 6
	&gfx3d 7
	&gfx3d 8
	&gfx3d 9
	&gfx3d 10
	&gfx3d 11
	&gfx3d 12
	&gfx3d 13
	&gfx3d 14
	&gfx3d 15
	&gfx3d 16
	&gfx3d 17
	&gfx3d 18
	&gfx3d 19
	&gfx3d 20
	&gfx3d 21
	&gfx3d 22
	&gfx3d 23
	&gfx3d 24
	&gfx3d 25
	&gfx3d 26
	&gfx3d 27
	&gfx3d 28
	&gfx3d 29
	&gfx3d 30
	&gfx3d 31
	&gfx3d1 0
	&gfx3d1 1
	&gfx3d1 2
	&gfx3d1 3
	&gfx3d1 4
	&gfx3d1 5
	&gfx3d1 6
	&gfx3d1 7
	&gfx3d1 8
	&gfx3d1 9
	&gfx3d1 10
	&gfx3d1 11
	&gfx3d1 12
	&gfx3d1 13
	&gfx3d1 14
	&gfx3d1 15
	&gfx3d1 16
	&gfx3d1 17
	&gfx3d1 18
	&gfx3d1 19
	&gfx3d1 20
	&gfx3d1 21
	&gfx3d1 22
	&gfx3d1 23
	&gfx3d1 24
	&gfx3d1 25
	&gfx3d1 26
	&gfx3d1 27
	&gfx3d1 28
	&gfx3d1 29
	&gfx3d1 30
	&gfx3d1 31>;

	qcom,gpu-pwrlevels {
	compatible = "qcom,gpu-pwrlevels";
	qcom,gpu-pwrlevel@0 {
	qcom,gpu-freq = <450000000>;
	};
	qcom,gpu-pwrlevel@1 {
	qcom,gpu-freq = <27000000>;
	};
	};
	};

	mmss_sfpb: syscon@5700000 {
	compatible = "syscon";
	reg = <0x5700000 0x70>;
	};

	dsi0: mdss_dsi@4700000 {
	compatible = "qcom,mdss-dsi-ctrl";
	label = "MDSS DSI CTRL->0";
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x04700000 0x200>;
	reg-names = "dsi_ctrl";

	clocks = <&mmcc DSI_M_AHB_CLK>,
	<&mmcc DSI_S_AHB_CLK>,
	<&mmcc AMP_AHB_CLK>,
	<&mmcc DSI_CLK>,
	<&mmcc DSI1_BYTE_CLK>,
	<&mmcc DSI_PIXEL_CLK>,
	<&mmcc DSI1_ESC_CLK>;
	clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
	"src_clk", "byte_clk", "pixel_clk",
	"core_clk";

	assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
	<&mmcc DSI1_ESC_SRC>,
	<&mmcc DSI_SRC>,
	<&mmcc DSI_PIXEL_SRC>;
	assigned-clock-parents = <&dsi0_phy 0>,
	<&dsi0_phy 0>,
	<&dsi0_phy 1>,
	<&dsi0_phy 1>;
	syscon-sfpb = <&mmss_sfpb>;
	phys = <&dsi0_phy>;
	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	dsi0_in: endpoint {
	};
	};

	port@1 {
	reg = <1>;
	dsi0_out: endpoint {
	};
	};
	};
	};


	dsi0_phy: dsi-phy@4700200 {
	compatible = "qcom,dsi-phy-28nm-8960";
	#clock-cells = <1>;
	#phy-cells = <0>;

	reg = <0x04700200 0x100>,
	<0x04700300 0x200>,
	<0x04700500 0x5c>;
	reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
	clock-names = "iface_clk", "ref";
	clocks = <&mmcc DSI_M_AHB_CLK>,
	<&cxo_board>;
	};


	mdp_port0: iommu@7500000 {
	compatible = "qcom,apq8064-iommu";
	#iommu-cells = <1>;
	clock-names =
	"smmu_pclk",
	"iommu_clk";
	clocks =
	<&mmcc SMMU_AHB_CLK>,
	<&mmcc MDP_AXI_CLK>;
	reg = <0x07500000 0x100000>;
	interrupts =
	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	qcom,ncb = <2>;
	};

	mdp_port1: iommu@7600000 {
	compatible = "qcom,apq8064-iommu";
	#iommu-cells = <1>;
	clock-names =
	"smmu_pclk",
	"iommu_clk";
	clocks =
	<&mmcc SMMU_AHB_CLK>,
	<&mmcc MDP_AXI_CLK>;
	reg = <0x07600000 0x100000>;
	interrupts =
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	qcom,ncb = <2>;
	};

	gfx3d: iommu@7c00000 {
	compatible = "qcom,apq8064-iommu";
	#iommu-cells = <1>;
	clock-names =
	"smmu_pclk",
	"iommu_clk";
	clocks =
	<&mmcc SMMU_AHB_CLK>,
	<&mmcc GFX3D_AXI_CLK>;
	reg = <0x07c00000 0x100000>;
	interrupts =
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	qcom,ncb = <3>;
	};

	gfx3d1: iommu@7d00000 {
	compatible = "qcom,apq8064-iommu";
	#iommu-cells = <1>;
	clock-names =
	"smmu_pclk",
	"iommu_clk";
	clocks =
	<&mmcc SMMU_AHB_CLK>,
	<&mmcc GFX3D_AXI_CLK>;
	reg = <0x07d00000 0x100000>;
	interrupts =
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
	qcom,ncb = <3>;
	};

	pcie: pci@1b500000 {
	compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
	reg = <0x1b500000 0x1000
	0x1b502000 0x80
	0x1b600000 0x100
	0x0ff00000 0x100000>;
	reg-names = "dbi", "elbi", "parf", "config";
	device_type = "pci";
	linux,pci-domain = <0>;
	bus-range = <0x00 0xff>;
	num-lanes = <1>;
	#address-cells = <3>;
	#size-cells = <2>;
	ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
	0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* memory */
	interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
	clocks = <&gcc PCIE_A_CLK>,
	<&gcc PCIE_H_CLK>,
	<&gcc PCIE_PHY_REF_CLK>;
	clock-names = "core", "iface", "phy";
	resets = <&gcc PCIE_ACLK_RESET>,
	<&gcc PCIE_HCLK_RESET>,
	<&gcc PCIE_POR_RESET>,
	<&gcc PCIE_PCI_RESET>,
	<&gcc PCIE_PHY_RESET>;
	reset-names = "axi", "ahb", "por", "pci", "phy";
	status = "disabled";
	};

	hdmi: hdmi-tx@4a00000 {
	compatible = "qcom,hdmi-tx-8960";
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_pinctrl>;
	reg = <0x04a00000 0x2f0>;
	reg-names = "core_physical";
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mmcc HDMI_APP_CLK>,
	<&mmcc HDMI_M_AHB_CLK>,
	<&mmcc HDMI_S_AHB_CLK>;
	clock-names = "core_clk",
	"master_iface_clk",
	"slave_iface_clk";

	phys = <&hdmi_phy>;
	phy-names = "hdmi-phy";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	hdmi_in: endpoint {
	};
	};

	port@1 {
	reg = <1>;
	hdmi_out: endpoint {
	};
	};
	};
	};

	hdmi_phy: hdmi-phy@4a00400 {
	compatible = "qcom,hdmi-phy-8960";
	reg = <0x4a00400 0x60>,
	<0x4a00500 0x100>;
	reg-names = "hdmi_phy",
	"hdmi_pll";

	clocks = <&mmcc HDMI_S_AHB_CLK>;
	clock-names = "slave_iface_clk";
	#phy-cells = <0>;
	};

	mdp: mdp@5100000 {
	compatible = "qcom,mdp4";
	reg = <0x05100000 0xf0000>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mmcc MDP_CLK>,
	<&mmcc MDP_AHB_CLK>,
	<&mmcc MDP_AXI_CLK>,
	<&mmcc MDP_LUT_CLK>,
	<&mmcc HDMI_TV_CLK>,
	<&mmcc MDP_TV_CLK>;
	clock-names = "core_clk",
	"iface_clk",
	"bus_clk",
	"lut_clk",
	"hdmi_clk",
	"tv_clk";

	iommus = <&mdp_port0 0
	&mdp_port0 2
	&mdp_port1 0
	&mdp_port1 2>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	mdp_lvds_out: endpoint {
	};
	};

	port@1 {
	reg = <1>;
	mdp_dsi1_out: endpoint {
	};
	};

	port@2 {
	reg = <2>;
	mdp_dsi2_out: endpoint {
	};
	};

	port@3 {
	reg = <3>;
	mdp_dtv_out: endpoint {
	};
	};
	};
	};

	riva: riva-pil@3204000 {
	compatible = "qcom,riva-pil";

	reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
	reg-names = "ccu", "dxe", "pmu";

	interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
	<&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "wdog", "fatal";

	memory-region = <&wcnss_mem>;

	vddcx-supply = <&pm8921_s3>;
	vddmx-supply = <&pm8921_l24>;
	vddpx-supply = <&pm8921_s4>;

	status = "disabled";

	iris {
	compatible = "qcom,wcn3660";

	clocks = <&cxo_board>;
	clock-names = "xo";

	vddxo-supply = <&pm8921_l4>;
	vddrfa-supply = <&pm8921_s2>;
	vddpa-supply = <&pm8921_l10>;
	vdddig-supply = <&pm8921_lvs2>;
	};

	smd-edge {
	interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;

	qcom,ipc = <&l2cc 8 25>;
	qcom,smd-edge = <6>;

	label = "riva";

	wcnss {
	compatible = "qcom,wcnss";
	qcom,smd-channels = "WCNSS_CTRL";

	qcom,mmio = <&riva>;

	bt {
	compatible = "qcom,wcnss-bt";
	};

	wifi {
	compatible = "qcom,wcnss-wlan";

	interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "tx", "rx";

	qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
	qcom,smem-state-names = "tx-enable", "tx-rings-empty";
	};
	};
	};
	};

	etb@1a01000 {
	compatible = "coresight-etb10", "arm,primecell";
	reg = <0x1a01000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>;
	clock-names = "apb_pclk";

	in-ports {
	port {
	etb_in: endpoint {
	remote-endpoint = <&replicator_out0>;
	};
	};
	};
	};

	tpiu@1a03000 {
	compatible = "arm,coresight-tpiu", "arm,primecell";
	reg = <0x1a03000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>;
	clock-names = "apb_pclk";

	in-ports {
	port {
	tpiu_in: endpoint {
	remote-endpoint = <&replicator_out1>;
	};
	};
	};
	};

	replicator {
	compatible = "arm,coresight-static-replicator";

	clocks = <&rpmcc RPM_QDSS_CLK>;
	clock-names = "apb_pclk";

	out-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	replicator_out0: endpoint {
	remote-endpoint = <&etb_in>;
	};
	};
	port@1 {
	reg = <1>;
	replicator_out1: endpoint {
	remote-endpoint = <&tpiu_in>;
	};
	};
	};

	in-ports {
	port {
	replicator_in: endpoint {
	remote-endpoint = <&funnel_out>;
	};
	};
	};
	};

	funnel@1a04000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0x1a04000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>;
	clock-names = "apb_pclk";

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	/*
	* Not described input ports:
	* 2 - connected to STM component
	* 3 - not-connected
	* 6 - not-connected
	* 7 - not-connected
	*/
	port@0 {
	reg = <0>;
	funnel_in0: endpoint {
	remote-endpoint = <&etm0_out>;
	};
	};
	port@1 {
	reg = <1>;
	funnel_in1: endpoint {
	remote-endpoint = <&etm1_out>;
	};
	};
	port@4 {
	reg = <4>;
	funnel_in4: endpoint {
	remote-endpoint = <&etm2_out>;
	};
	};
	port@5 {
	reg = <5>;
	funnel_in5: endpoint {
	remote-endpoint = <&etm3_out>;
	};
	};
	};

	out-ports {
	port {
	funnel_out: endpoint {
	remote-endpoint = <&replicator_in>;
	};
	};
	};
	};

	etm@1a1c000 {
	compatible = "arm,coresight-etm3x", "arm,primecell";
	reg = <0x1a1c000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>;
	clock-names = "apb_pclk";

	cpu = <&CPU0>;

	out-ports {
	port {
	etm0_out: endpoint {
	remote-endpoint = <&funnel_in0>;
	};
	};
	};
	};

	etm@1a1d000 {
	compatible = "arm,coresight-etm3x", "arm,primecell";
	reg = <0x1a1d000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>;
	clock-names = "apb_pclk";

	cpu = <&CPU1>;

	out-ports {
	port {
	etm1_out: endpoint {
	remote-endpoint = <&funnel_in1>;
	};
	};
	};
	};

	etm@1a1e000 {
	compatible = "arm,coresight-etm3x", "arm,primecell";
	reg = <0x1a1e000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>;
	clock-names = "apb_pclk";

	cpu = <&CPU2>;

	out-ports {
	port {
	etm2_out: endpoint {
	remote-endpoint = <&funnel_in4>;
	};
	};
	};
	};

	etm@1a1f000 {
	compatible = "arm,coresight-etm3x", "arm,primecell";
	reg = <0x1a1f000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>;
	clock-names = "apb_pclk";

	cpu = <&CPU3>;

	out-ports {
	port {
	etm3_out: endpoint {
	remote-endpoint = <&funnel_in5>;
	};
	};
	};
	};
	};
	};
	#include "qcom-apq8064-pins.dtsi"
	diff --git a/sys/gnu/dts/arm/qcom-apq8084.dtsi b/sys/gnu/dts/arm/qcom-apq8084.dtsi
	index fa1852eed37b..bf6a03506b45 100644
	--- a/sys/gnu/dts/arm/qcom-apq8084.dtsi
	+++ b/sys/gnu/dts/arm/qcom-apq8084.dtsi
	@@ -1,530 +1,531 @@
	// SPDX-License-Identifier: GPL-2.0
	/dts-v1/;

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/qcom,gcc-apq8084.h>
	#include <dt-bindings/gpio/gpio.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Qualcomm APQ 8084";
	compatible = "qcom,apq8084";
	interrupt-parent = <&intc>;

	reserved-memory {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	smem_mem: smem_region@fa00000 {
	reg = <0xfa00000 0x200000>;
	no-map;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "qcom,krait";
	reg = <0>;
	enable-method = "qcom,kpss-acc-v2";
	next-level-cache = <&L2>;
	qcom,acc = <&acc0>;
	qcom,saw = <&saw0>;
	cpu-idle-states = <&CPU_SPC>;
	};

	cpu@1 {
	device_type = "cpu";
	compatible = "qcom,krait";
	reg = <1>;
	enable-method = "qcom,kpss-acc-v2";
	next-level-cache = <&L2>;
	qcom,acc = <&acc1>;
	qcom,saw = <&saw1>;
	cpu-idle-states = <&CPU_SPC>;
	};

	cpu@2 {
	device_type = "cpu";
	compatible = "qcom,krait";
	reg = <2>;
	enable-method = "qcom,kpss-acc-v2";
	next-level-cache = <&L2>;
	qcom,acc = <&acc2>;
	qcom,saw = <&saw2>;
	cpu-idle-states = <&CPU_SPC>;
	};

	cpu@3 {
	device_type = "cpu";
	compatible = "qcom,krait";
	reg = <3>;
	enable-method = "qcom,kpss-acc-v2";
	next-level-cache = <&L2>;
	qcom,acc = <&acc3>;
	qcom,saw = <&saw3>;
	cpu-idle-states = <&CPU_SPC>;
	};

	L2: l2-cache {
	compatible = "qcom,arch-cache";
	cache-level = <2>;
	qcom,saw = <&saw_l2>;
	};

	idle-states {
	CPU_SPC: spc {
	compatible = "qcom,idle-state-spc",
	"arm,idle-state";
	entry-latency-us = <150>;
	exit-latency-us = <200>;
	min-residency-us = <2000>;
	};
	};
	};

	memory {
	device_type = "memory";
	reg = <0x0 0x0>;
	};

	firmware {
	scm {
	compatible = "qcom,scm";
	clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
	clock-names = "core", "bus", "iface";
	};
	};

	thermal-zones {
	cpu-thermal0 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 5>;

	trips {
	cpu_alert0: trip0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu_crit0: trip1 {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu-thermal1 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 6>;

	trips {
	cpu_alert1: trip0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu_crit1: trip1 {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu-thermal2 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 7>;

	trips {
	cpu_alert2: trip0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu_crit2: trip1 {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu-thermal3 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 8>;

	trips {
	cpu_alert3: trip0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu_crit3: trip1 {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};
	};

	cpu-pmu {
	compatible = "qcom,krait-pmu";
	interrupts = <GIC_PPI 7 0xf04>;
	};

	clocks {
	xo_board: xo_board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <19200000>;
	};

	sleep_clk: sleep_clk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 2 0xf08>,
	<GIC_PPI 3 0xf08>,
	<GIC_PPI 4 0xf08>,
	<GIC_PPI 1 0xf08>;
	clock-frequency = <19200000>;
	};

	smem {
	compatible = "qcom,smem";

	qcom,rpm-msg-ram = <&rpm_msg_ram>;
	memory-region = <&smem_mem>;

	hwlocks = <&tcsr_mutex 3>;
	};

	soc: soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "simple-bus";

	intc: interrupt-controller@f9000000 {
	compatible = "qcom,msm-qgic2";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0xf9000000 0x1000>,
	<0xf9002000 0x1000>;
	};

	apcs: syscon@f9011000 {
	compatible = "syscon";
	reg = <0xf9011000 0x1000>;
	};

	qfprom: qfprom@fc4bc000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "qcom,qfprom";
	reg = <0xfc4bc000 0x1000>;
	tsens_calib: calib@d0 {
	reg = <0xd0 0x18>;
	};
	tsens_backup: backup@440 {
	reg = <0x440 0x10>;
	};
	};

	tsens: thermal-sensor@fc4a8000 {
	compatible = "qcom,msm8974-tsens";
	reg = <0xfc4a9000 0x1000>, /* TM */
	<0xfc4a8000 0x1000>; /* SROT */
	nvmem-cells = <&tsens_calib>, <&tsens_backup>;
	nvmem-cell-names = "calib", "calib_backup";
	#qcom,sensors = <11>;
	#thermal-sensor-cells = <1>;
	};
	timer@f9020000 {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "arm,armv7-timer-mem";
	reg = <0xf9020000 0x1000>;
	clock-frequency = <19200000>;

	frame@f9021000 {
	frame-number = <0>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9021000 0x1000>,
	<0xf9022000 0x1000>;
	};

	frame@f9023000 {
	frame-number = <1>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9023000 0x1000>;
	status = "disabled";
	};

	frame@f9024000 {
	frame-number = <2>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9024000 0x1000>;
	status = "disabled";
	};

	frame@f9025000 {
	frame-number = <3>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9025000 0x1000>;
	status = "disabled";
	};

	frame@f9026000 {
	frame-number = <4>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9026000 0x1000>;
	status = "disabled";
	};

	frame@f9027000 {
	frame-number = <5>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9027000 0x1000>;
	status = "disabled";
	};

	frame@f9028000 {
	frame-number = <6>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9028000 0x1000>;
	status = "disabled";
	};
	};

	saw0: power-controller@f9089000 {
	compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
	reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
	};

	saw1: power-controller@f9099000 {
	compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
	reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
	};

	saw2: power-controller@f90a9000 {
	compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
	reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
	};

	saw3: power-controller@f90b9000 {
	compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
	reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
	};

	saw_l2: power-controller@f9012000 {
	compatible = "qcom,saw2";
	reg = <0xf9012000 0x1000>;
	regulator;
	};

	acc0: clock-controller@f9088000 {
	compatible = "qcom,kpss-acc-v2";
	reg = <0xf9088000 0x1000>,
	<0xf9008000 0x1000>;
	};

	acc1: clock-controller@f9098000 {
	compatible = "qcom,kpss-acc-v2";
	reg = <0xf9098000 0x1000>,
	<0xf9008000 0x1000>;
	};

	acc2: clock-controller@f90a8000 {
	compatible = "qcom,kpss-acc-v2";
	reg = <0xf90a8000 0x1000>,
	<0xf9008000 0x1000>;
	};

	acc3: clock-controller@f90b8000 {
	compatible = "qcom,kpss-acc-v2";
	reg = <0xf90b8000 0x1000>,
	<0xf9008000 0x1000>;
	};

	restart@fc4ab000 {
	compatible = "qcom,pshold";
	reg = <0xfc4ab000 0x4>;
	};

	gcc: clock-controller@fc400000 {
	compatible = "qcom,gcc-apq8084";
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;
	reg = <0xfc400000 0x4000>;
	};

	tcsr_mutex_regs: syscon@fd484000 {
	compatible = "syscon";
	reg = <0xfd484000 0x2000>;
	};

	tcsr_mutex: hwlock {
	compatible = "qcom,tcsr-mutex";
	syscon = <&tcsr_mutex_regs 0 0x80>;
	#hwlock-cells = <1>;
	};

	rpm_msg_ram: memory@fc428000 {
	compatible = "qcom,rpm-msg-ram";
	reg = <0xfc428000 0x4000>;
	};

	tlmm: pinctrl@fd510000 {
	compatible = "qcom,apq8084-pinctrl";
	reg = <0xfd510000 0x4000>;
	gpio-controller;
	+ gpio-ranges = <&tlmm 0 0 147>;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	};

	blsp2_uart2: serial@f995e000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0xf995e000 0x1000>;
	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	sdhci@f9824900 {
	compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
	reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
	reg-names = "hc_mem", "core_mem";
	interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hc_irq", "pwr_irq";
	clocks = <&gcc GCC_SDCC1_APPS_CLK>,
	<&gcc GCC_SDCC1_AHB_CLK>,
	<&xo_board>;
	clock-names = "core", "iface", "xo";
	status = "disabled";
	};

	sdhci@f98a4900 {
	compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
	reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
	reg-names = "hc_mem", "core_mem";
	interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hc_irq", "pwr_irq";
	clocks = <&gcc GCC_SDCC2_APPS_CLK>,
	<&gcc GCC_SDCC2_AHB_CLK>,
	<&xo_board>;
	clock-names = "core", "iface", "xo";
	status = "disabled";
	};

	spmi_bus: spmi@fc4cf000 {
	compatible = "qcom,spmi-pmic-arb";
	reg-names = "core", "intr", "cnfg";
	reg = <0xfc4cf000 0x1000>,
	<0xfc4cb000 0x1000>,
	<0xfc4ca000 0x1000>;
	interrupt-names = "periph_irq";
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	qcom,ee = <0>;
	qcom,channel = <0>;
	#address-cells = <2>;
	#size-cells = <0>;
	interrupt-controller;
	#interrupt-cells = <4>;
	};
	};

	smd {
	compatible = "qcom,smd";

	rpm {
	interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
	qcom,ipc = <&apcs 8 0>;
	qcom,smd-edge = <15>;

	rpm_requests {
	compatible = "qcom,rpm-apq8084";
	qcom,smd-channels = "rpm_requests";

	pma8084-regulators {
	compatible = "qcom,rpm-pma8084-regulators";

	pma8084_s1: s1 {};
	pma8084_s2: s2 {};
	pma8084_s3: s3 {};
	pma8084_s4: s4 {};
	pma8084_s5: s5 {};
	pma8084_s6: s6 {};
	pma8084_s7: s7 {};
	pma8084_s8: s8 {};
	pma8084_s9: s9 {};
	pma8084_s10: s10 {};
	pma8084_s11: s11 {};
	pma8084_s12: s12 {};

	pma8084_l1: l1 {};
	pma8084_l2: l2 {};
	pma8084_l3: l3 {};
	pma8084_l4: l4 {};
	pma8084_l5: l5 {};
	pma8084_l6: l6 {};
	pma8084_l7: l7 {};
	pma8084_l8: l8 {};
	pma8084_l9: l9 {};
	pma8084_l10: l10 {};
	pma8084_l11: l11 {};
	pma8084_l12: l12 {};
	pma8084_l13: l13 {};
	pma8084_l14: l14 {};
	pma8084_l15: l15 {};
	pma8084_l16: l16 {};
	pma8084_l17: l17 {};
	pma8084_l18: l18 {};
	pma8084_l19: l19 {};
	pma8084_l20: l20 {};
	pma8084_l21: l21 {};
	pma8084_l22: l22 {};
	pma8084_l23: l23 {};
	pma8084_l24: l24 {};
	pma8084_l25: l25 {};
	pma8084_l26: l26 {};
	pma8084_l27: l27 {};

	pma8084_lvs1: lvs1 {};
	pma8084_lvs2: lvs2 {};
	pma8084_lvs3: lvs3 {};
	pma8084_lvs4: lvs4 {};

	pma8084_5vs1: 5vs1 {};
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/qcom-ipq4019.dtsi b/sys/gnu/dts/arm/qcom-ipq4019.dtsi
	index 71bb25a8afc0..bfa9ce4c6e69 100644
	--- a/sys/gnu/dts/arm/qcom-ipq4019.dtsi
	+++ b/sys/gnu/dts/arm/qcom-ipq4019.dtsi
	@@ -1,579 +1,580 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (c) 2015, The Linux Foundation. All rights reserved.
	*/

	/dts-v1/;

	#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/interrupt-controller/irq.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;

	model = "Qualcomm Technologies, Inc. IPQ4019";
	compatible = "qcom,ipq4019";
	interrupt-parent = <&intc>;

	reserved-memory {
	#address-cells = <0x1>;
	#size-cells = <0x1>;
	ranges;

	smem_region: smem@87e00000 {
	reg = <0x87e00000 0x080000>;
	no-map;
	};

	tz@87e80000 {
	reg = <0x87e80000 0x180000>;
	no-map;
	};
	};

	aliases {
	spi0 = &blsp1_spi1;
	spi1 = &blsp1_spi2;
	i2c0 = &blsp1_i2c3;
	i2c1 = &blsp1_i2c4;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	enable-method = "qcom,kpss-acc-v2";
	next-level-cache = <&L2>;
	qcom,acc = <&acc0>;
	qcom,saw = <&saw0>;
	reg = <0x0>;
	clocks = <&gcc GCC_APPS_CLK_SRC>;
	clock-frequency = <0>;
	clock-latency = <256000>;
	operating-points-v2 = <&cpu0_opp_table>;
	};

	cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	enable-method = "qcom,kpss-acc-v2";
	next-level-cache = <&L2>;
	qcom,acc = <&acc1>;
	qcom,saw = <&saw1>;
	reg = <0x1>;
	clocks = <&gcc GCC_APPS_CLK_SRC>;
	clock-frequency = <0>;
	clock-latency = <256000>;
	operating-points-v2 = <&cpu0_opp_table>;
	};

	cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	enable-method = "qcom,kpss-acc-v2";
	next-level-cache = <&L2>;
	qcom,acc = <&acc2>;
	qcom,saw = <&saw2>;
	reg = <0x2>;
	clocks = <&gcc GCC_APPS_CLK_SRC>;
	clock-frequency = <0>;
	clock-latency = <256000>;
	operating-points-v2 = <&cpu0_opp_table>;
	};

	cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	enable-method = "qcom,kpss-acc-v2";
	next-level-cache = <&L2>;
	qcom,acc = <&acc3>;
	qcom,saw = <&saw3>;
	reg = <0x3>;
	clocks = <&gcc GCC_APPS_CLK_SRC>;
	clock-frequency = <0>;
	clock-latency = <256000>;
	operating-points-v2 = <&cpu0_opp_table>;
	};

	L2: l2-cache {
	compatible = "cache";
	cache-level = <2>;
	qcom,saw = <&saw_l2>;
	};
	};

	cpu0_opp_table: opp_table0 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-48000000 {
	opp-hz = /bits/ 64 <48000000>;
	clock-latency-ns = <256000>;
	};
	opp-200000000 {
	opp-hz = /bits/ 64 <200000000>;
	clock-latency-ns = <256000>;
	};
	opp-500000000 {
	opp-hz = /bits/ 64 <500000000>;
	clock-latency-ns = <256000>;
	};
	opp-716000000 {
	opp-hz = /bits/ 64 <716000000>;
	clock-latency-ns = <256000>;
	};
	};

	memory {
	device_type = "memory";
	reg = <0x0 0x0>;
	};

	pmu {
	compatible = "arm,cortex-a7-pmu";
	interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) \|
	IRQ_TYPE_LEVEL_HIGH)>;
	};

	clocks {
	sleep_clk: sleep_clk {
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	#clock-cells = <0>;
	};

	xo: xo {
	compatible = "fixed-clock";
	clock-frequency = <48000000>;
	#clock-cells = <0>;
	};
	};

	firmware {
	scm {
	compatible = "qcom,scm-ipq4019";
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <1 2 0xf08>,
	<1 3 0xf08>,
	<1 4 0xf08>,
	<1 1 0xf08>;
	clock-frequency = <48000000>;
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "simple-bus";

	intc: interrupt-controller@b000000 {
	compatible = "qcom,msm-qgic2";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0x0b000000 0x1000>,
	<0x0b002000 0x1000>;
	};

	gcc: clock-controller@1800000 {
	compatible = "qcom,gcc-ipq4019";
	#clock-cells = <1>;
	#reset-cells = <1>;
	reg = <0x1800000 0x60000>;
	};

	rng@22000 {
	compatible = "qcom,prng";
	reg = <0x22000 0x140>;
	clocks = <&gcc GCC_PRNG_AHB_CLK>;
	clock-names = "core";
	status = "disabled";
	};

	tlmm: pinctrl@1000000 {
	compatible = "qcom,ipq4019-pinctrl";
	reg = <0x01000000 0x300000>;
	gpio-controller;
	+ gpio-ranges = <&tlmm 0 0 100>;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	};

	sdhci: sdhci@7824900 {
	compatible = "qcom,sdhci-msm-v4";
	reg = <0x7824900 0x11c>, <0x7824000 0x800>;
	interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hc_irq", "pwr_irq";
	bus-width = <8>;
	clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
	<&gcc GCC_DCD_XO_CLK>;
	clock-names = "core", "iface", "xo";
	status = "disabled";
	};

	blsp_dma: dma@7884000 {
	compatible = "qcom,bam-v1.7.0";
	reg = <0x07884000 0x23000>;
	interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	status = "disabled";
	};

	blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
	compatible = "qcom,spi-qup-v2.2.1";
	reg = <0x78b5000 0x600>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	#address-cells = <1>;
	#size-cells = <0>;
	dmas = <&blsp_dma 5>, <&blsp_dma 4>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
	compatible = "qcom,spi-qup-v2.2.1";
	reg = <0x78b6000 0x600>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	#address-cells = <1>;
	#size-cells = <0>;
	dmas = <&blsp_dma 7>, <&blsp_dma 6>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x78b7000 0x600>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	#address-cells = <1>;
	#size-cells = <0>;
	dmas = <&blsp_dma 9>, <&blsp_dma 8>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x78b8000 0x600>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	#address-cells = <1>;
	#size-cells = <0>;
	dmas = <&blsp_dma 11>, <&blsp_dma 10>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	cryptobam: dma@8e04000 {
	compatible = "qcom,bam-v1.7.0";
	reg = <0x08e04000 0x20000>;
	interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <1>;
	qcom,controlled-remotely;
	status = "disabled";
	};

	crypto@8e3a000 {
	compatible = "qcom,crypto-v5.1";
	reg = <0x08e3a000 0x6000>;
	clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
	<&gcc GCC_CRYPTO_AXI_CLK>,
	<&gcc GCC_CRYPTO_CLK>;
	clock-names = "iface", "bus", "core";
	dmas = <&cryptobam 2>, <&cryptobam 3>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	acc0: clock-controller@b088000 {
	compatible = "qcom,kpss-acc-v2";
	reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
	};

	acc1: clock-controller@b098000 {
	compatible = "qcom,kpss-acc-v2";
	reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
	};

	acc2: clock-controller@b0a8000 {
	compatible = "qcom,kpss-acc-v2";
	reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
	};

	acc3: clock-controller@b0b8000 {
	compatible = "qcom,kpss-acc-v2";
	reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
	};

	saw0: regulator@b089000 {
	compatible = "qcom,saw2";
	reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
	regulator;
	};

	saw1: regulator@b099000 {
	compatible = "qcom,saw2";
	reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
	regulator;
	};

	saw2: regulator@b0a9000 {
	compatible = "qcom,saw2";
	reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
	regulator;
	};

	saw3: regulator@b0b9000 {
	compatible = "qcom,saw2";
	reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
	regulator;
	};

	saw_l2: regulator@b012000 {
	compatible = "qcom,saw2";
	reg = <0xb012000 0x1000>;
	regulator;
	};

	blsp1_uart1: serial@78af000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x78af000 0x200>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp_dma 1>, <&blsp_dma 0>;
	dma-names = "rx", "tx";
	};

	blsp1_uart2: serial@78b0000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x78b0000 0x200>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp_dma 3>, <&blsp_dma 2>;
	dma-names = "rx", "tx";
	};

	watchdog@b017000 {
	compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
	reg = <0xb017000 0x40>;
	clocks = <&sleep_clk>;
	timeout-sec = <10>;
	status = "disabled";
	};

	restart@4ab000 {
	compatible = "qcom,pshold";
	reg = <0x4ab000 0x4>;
	};

	pcie0: pci@40000000 {
	compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
	reg = <0x40000000 0xf1d
	0x40000f20 0xa8
	0x80000 0x2000
	0x40100000 0x1000>;
	reg-names = "dbi", "elbi", "parf", "config";
	device_type = "pci";
	linux,pci-domain = <0>;
	bus-range = <0x00 0xff>;
	num-lanes = <1>;
	#address-cells = <3>;
	#size-cells = <2>;

	ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
	<0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;

	interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
	clocks = <&gcc GCC_PCIE_AHB_CLK>,
	<&gcc GCC_PCIE_AXI_M_CLK>,
	<&gcc GCC_PCIE_AXI_S_CLK>;
	clock-names = "aux",
	"master_bus",
	"slave_bus";

	resets = <&gcc PCIE_AXI_M_ARES>,
	<&gcc PCIE_AXI_S_ARES>,
	<&gcc PCIE_PIPE_ARES>,
	<&gcc PCIE_AXI_M_VMIDMT_ARES>,
	<&gcc PCIE_AXI_S_XPU_ARES>,
	<&gcc PCIE_PARF_XPU_ARES>,
	<&gcc PCIE_PHY_ARES>,
	<&gcc PCIE_AXI_M_STICKY_ARES>,
	<&gcc PCIE_PIPE_STICKY_ARES>,
	<&gcc PCIE_PWR_ARES>,
	<&gcc PCIE_AHB_ARES>,
	<&gcc PCIE_PHY_AHB_ARES>;
	reset-names = "axi_m",
	"axi_s",
	"pipe",
	"axi_m_vmid",
	"axi_s_xpu",
	"parf",
	"phy",
	"axi_m_sticky",
	"pipe_sticky",
	"pwr",
	"ahb",
	"phy_ahb";

	status = "disabled";
	};

	qpic_bam: dma@7984000 {
	compatible = "qcom,bam-v1.7.0";
	reg = <0x7984000 0x1a000>;
	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_QPIC_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	status = "disabled";
	};

	nand: qpic-nand@79b0000 {
	compatible = "qcom,ipq4019-nand";
	reg = <0x79b0000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&gcc GCC_QPIC_CLK>,
	<&gcc GCC_QPIC_AHB_CLK>;
	clock-names = "core", "aon";

	dmas = <&qpic_bam 0>,
	<&qpic_bam 1>,
	<&qpic_bam 2>;
	dma-names = "tx", "rx", "cmd";
	status = "disabled";

	nand@0 {
	reg = <0>;

	nand-ecc-strength = <4>;
	nand-ecc-step-size = <512>;
	nand-bus-width = <8>;
	};
	};

	wifi0: wifi@a000000 {
	compatible = "qcom,ipq4019-wifi";
	reg = <0xa000000 0x200000>;
	resets = <&gcc WIFI0_CPU_INIT_RESET>,
	<&gcc WIFI0_RADIO_SRIF_RESET>,
	<&gcc WIFI0_RADIO_WARM_RESET>,
	<&gcc WIFI0_RADIO_COLD_RESET>,
	<&gcc WIFI0_CORE_WARM_RESET>,
	<&gcc WIFI0_CORE_COLD_RESET>;
	reset-names = "wifi_cpu_init", "wifi_radio_srif",
	"wifi_radio_warm", "wifi_radio_cold",
	"wifi_core_warm", "wifi_core_cold";
	clocks = <&gcc GCC_WCSS2G_CLK>,
	<&gcc GCC_WCSS2G_REF_CLK>,
	<&gcc GCC_WCSS2G_RTC_CLK>;
	clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
	"wifi_wcss_rtc";
	interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi0", "msi1", "msi2", "msi3",
	"msi4", "msi5", "msi6", "msi7",
	"msi8", "msi9", "msi10", "msi11",
	"msi12", "msi13", "msi14", "msi15",
	"legacy";
	status = "disabled";
	};

	wifi1: wifi@a800000 {
	compatible = "qcom,ipq4019-wifi";
	reg = <0xa800000 0x200000>;
	resets = <&gcc WIFI1_CPU_INIT_RESET>,
	<&gcc WIFI1_RADIO_SRIF_RESET>,
	<&gcc WIFI1_RADIO_WARM_RESET>,
	<&gcc WIFI1_RADIO_COLD_RESET>,
	<&gcc WIFI1_CORE_WARM_RESET>,
	<&gcc WIFI1_CORE_COLD_RESET>;
	reset-names = "wifi_cpu_init", "wifi_radio_srif",
	"wifi_radio_warm", "wifi_radio_cold",
	"wifi_core_warm", "wifi_core_cold";
	clocks = <&gcc GCC_WCSS5G_CLK>,
	<&gcc GCC_WCSS5G_REF_CLK>,
	<&gcc GCC_WCSS5G_RTC_CLK>;
	clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
	"wifi_wcss_rtc";
	interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi0", "msi1", "msi2", "msi3",
	"msi4", "msi5", "msi6", "msi7",
	"msi8", "msi9", "msi10", "msi11",
	"msi12", "msi13", "msi14", "msi15",
	"legacy";
	status = "disabled";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/qcom-ipq8064.dtsi b/sys/gnu/dts/arm/qcom-ipq8064.dtsi
	index 16c0da97932c..4021f661cd11 100644
	--- a/sys/gnu/dts/arm/qcom-ipq8064.dtsi
	+++ b/sys/gnu/dts/arm/qcom-ipq8064.dtsi
	@@ -1,669 +1,670 @@
	// SPDX-License-Identifier: GPL-2.0
	/dts-v1/;

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
	#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
	#include <dt-bindings/soc/qcom,gsbi.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Qualcomm IPQ8064";
	compatible = "qcom,ipq8064";
	interrupt-parent = <&intc>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	compatible = "qcom,krait";
	enable-method = "qcom,kpss-acc-v1";
	device_type = "cpu";
	reg = <0>;
	next-level-cache = <&L2>;
	qcom,acc = <&acc0>;
	qcom,saw = <&saw0>;
	};

	cpu@1 {
	compatible = "qcom,krait";
	enable-method = "qcom,kpss-acc-v1";
	device_type = "cpu";
	reg = <1>;
	next-level-cache = <&L2>;
	qcom,acc = <&acc1>;
	qcom,saw = <&saw1>;
	};

	L2: l2-cache {
	compatible = "cache";
	cache-level = <2>;
	};
	};

	memory {
	device_type = "memory";
	reg = <0x0 0x0>;
	};

	cpu-pmu {
	compatible = "qcom,krait-pmu";
	interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_LEVEL_HIGH)>;
	};

	reserved-memory {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	nss@40000000 {
	reg = <0x40000000 0x1000000>;
	no-map;
	};

	smem@41000000 {
	reg = <0x41000000 0x200000>;
	no-map;
	};
	};

	clocks {
	cxo_board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <25000000>;
	};

	pxo_board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <25000000>;
	};

	sleep_clk: sleep_clk {
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	#clock-cells = <0>;
	};
	};

	soc: soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "simple-bus";

	lpass@28100000 {
	compatible = "qcom,lpass-cpu";
	status = "disabled";
	clocks = <&lcc AHBIX_CLK>,
	<&lcc MI2S_OSR_CLK>,
	<&lcc MI2S_BIT_CLK>;
	clock-names = "ahbix-clk",
	"mi2s-osr-clk",
	"mi2s-bit-clk";
	interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "lpass-irq-lpaif";
	reg = <0x28100000 0x10000>;
	reg-names = "lpass-lpaif";
	};

	qcom_pinmux: pinmux@800000 {
	compatible = "qcom,ipq8064-pinctrl";
	reg = <0x800000 0x4000>;

	gpio-controller;
	+ gpio-ranges = <&qcom_pinmux 0 0 69>;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

	pcie0_pins: pcie0_pinmux {
	mux {
	pins = "gpio3";
	function = "pcie1_rst";
	drive-strength = <12>;
	bias-disable;
	};
	};

	pcie1_pins: pcie1_pinmux {
	mux {
	pins = "gpio48";
	function = "pcie2_rst";
	drive-strength = <12>;
	bias-disable;
	};
	};

	pcie2_pins: pcie2_pinmux {
	mux {
	pins = "gpio63";
	function = "pcie3_rst";
	drive-strength = <12>;
	bias-disable;
	};
	};

	spi_pins: spi_pins {
	mux {
	pins = "gpio18", "gpio19", "gpio21";
	function = "gsbi5";
	drive-strength = <10>;
	bias-none;
	};
	};

	leds_pins: leds_pins {
	mux {
	pins = "gpio7", "gpio8", "gpio9",
	"gpio26", "gpio53";
	function = "gpio";
	drive-strength = <2>;
	bias-pull-down;
	output-low;
	};
	};

	buttons_pins: buttons_pins {
	mux {
	pins = "gpio54";
	drive-strength = <2>;
	bias-pull-up;
	};
	};
	};

	intc: interrupt-controller@2000000 {
	compatible = "qcom,msm-qgic2";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0x02000000 0x1000>,
	<0x02002000 0x1000>;
	};

	timer@200a000 {
	compatible = "qcom,kpss-timer",
	"qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
	interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_EDGE_RISING)>,
	<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_EDGE_RISING)>,
	<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_EDGE_RISING)>,
	<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_EDGE_RISING)>,
	<GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_EDGE_RISING)>;
	reg = <0x0200a000 0x100>;
	clock-frequency = <25000000>,
	<32768>;
	clocks = <&sleep_clk>;
	clock-names = "sleep";
	cpu-offset = <0x80000>;
	};

	acc0: clock-controller@2088000 {
	compatible = "qcom,kpss-acc-v1";
	reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
	};

	acc1: clock-controller@2098000 {
	compatible = "qcom,kpss-acc-v1";
	reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
	};

	saw0: regulator@2089000 {
	compatible = "qcom,saw2";
	reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
	regulator;
	};

	saw1: regulator@2099000 {
	compatible = "qcom,saw2";
	reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
	regulator;
	};

	gsbi2: gsbi@12480000 {
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <2>;
	reg = <0x12480000 0x100>;
	clocks = <&gcc GSBI2_H_CLK>;
	clock-names = "iface";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	status = "disabled";

	syscon-tcsr = <&tcsr>;

	serial@12490000 {
	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	reg = <0x12490000 0x1000>,
	<0x12480000 0x1000>;
	interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	i2c@124a0000 {
	compatible = "qcom,i2c-qup-v1.1.1";
	reg = <0x124a0000 0x1000>;
	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";

	#address-cells = <1>;
	#size-cells = <0>;
	};

	};

	gsbi4: gsbi@16300000 {
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <4>;
	reg = <0x16300000 0x100>;
	clocks = <&gcc GSBI4_H_CLK>;
	clock-names = "iface";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	status = "disabled";

	syscon-tcsr = <&tcsr>;

	gsbi4_serial: serial@16340000 {
	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	reg = <0x16340000 0x1000>,
	<0x16300000 0x1000>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	i2c@16380000 {
	compatible = "qcom,i2c-qup-v1.1.1";
	reg = <0x16380000 0x1000>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";

	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	gsbi5: gsbi@1a200000 {
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <5>;
	reg = <0x1a200000 0x100>;
	clocks = <&gcc GSBI5_H_CLK>;
	clock-names = "iface";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	status = "disabled";

	syscon-tcsr = <&tcsr>;

	serial@1a240000 {
	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	reg = <0x1a240000 0x1000>,
	<0x1a200000 0x1000>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	i2c@1a280000 {
	compatible = "qcom,i2c-qup-v1.1.1";
	reg = <0x1a280000 0x1000>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";

	#address-cells = <1>;
	#size-cells = <0>;
	};

	spi@1a280000 {
	compatible = "qcom,spi-qup-v1.1.1";
	reg = <0x1a280000 0x1000>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";

	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	gsbi7: gsbi@16600000 {
	status = "disabled";
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <7>;
	reg = <0x16600000 0x100>;
	clocks = <&gcc GSBI7_H_CLK>;
	clock-names = "iface";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	syscon-tcsr = <&tcsr>;

	gsbi7_serial: serial@16640000 {
	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	reg = <0x16640000 0x1000>,
	<0x16600000 0x1000>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};
	};

	sata_phy: sata-phy@1b400000 {
	compatible = "qcom,ipq806x-sata-phy";
	reg = <0x1b400000 0x200>;

	clocks = <&gcc SATA_PHY_CFG_CLK>;
	clock-names = "cfg";

	#phy-cells = <0>;
	status = "disabled";
	};

	sata@29000000 {
	compatible = "qcom,ipq806x-ahci", "generic-ahci";
	reg = <0x29000000 0x180>;

	interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc SFAB_SATA_S_H_CLK>,
	<&gcc SATA_H_CLK>,
	<&gcc SATA_A_CLK>,
	<&gcc SATA_RXOOB_CLK>,
	<&gcc SATA_PMALIVE_CLK>;
	clock-names = "slave_face", "iface", "core",
	"rxoob", "pmalive";

	assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
	assigned-clock-rates = <100000000>, <100000000>;

	phys = <&sata_phy>;
	phy-names = "sata-phy";
	status = "disabled";
	};

	qcom,ssbi@500000 {
	compatible = "qcom,ssbi";
	reg = <0x00500000 0x1000>;
	qcom,controller-type = "pmic-arbiter";
	};

	gcc: clock-controller@900000 {
	compatible = "qcom,gcc-ipq8064";
	reg = <0x00900000 0x4000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	tcsr: syscon@1a400000 {
	compatible = "qcom,tcsr-ipq8064", "syscon";
	reg = <0x1a400000 0x100>;
	};

	lcc: clock-controller@28000000 {
	compatible = "qcom,lcc-ipq8064";
	reg = <0x28000000 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pcie0: pci@1b500000 {
	compatible = "qcom,pcie-ipq8064";
	reg = <0x1b500000 0x1000
	0x1b502000 0x80
	0x1b600000 0x100
	0x0ff00000 0x100000>;
	reg-names = "dbi", "elbi", "parf", "config";
	device_type = "pci";
	linux,pci-domain = <0>;
	bus-range = <0x00 0xff>;
	num-lanes = <1>;
	#address-cells = <3>;
	#size-cells = <2>;

	ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
	0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */

	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

	clocks = <&gcc PCIE_A_CLK>,
	<&gcc PCIE_H_CLK>,
	<&gcc PCIE_PHY_CLK>,
	<&gcc PCIE_AUX_CLK>,
	<&gcc PCIE_ALT_REF_CLK>;
	clock-names = "core", "iface", "phy", "aux", "ref";

	assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
	assigned-clock-rates = <100000000>;

	resets = <&gcc PCIE_ACLK_RESET>,
	<&gcc PCIE_HCLK_RESET>,
	<&gcc PCIE_POR_RESET>,
	<&gcc PCIE_PCI_RESET>,
	<&gcc PCIE_PHY_RESET>,
	<&gcc PCIE_EXT_RESET>;
	reset-names = "axi", "ahb", "por", "pci", "phy", "ext";

	pinctrl-0 = <&pcie0_pins>;
	pinctrl-names = "default";

	status = "disabled";
	perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
	};

	pcie1: pci@1b700000 {
	compatible = "qcom,pcie-ipq8064";
	reg = <0x1b700000 0x1000
	0x1b702000 0x80
	0x1b800000 0x100
	0x31f00000 0x100000>;
	reg-names = "dbi", "elbi", "parf", "config";
	device_type = "pci";
	linux,pci-domain = <1>;
	bus-range = <0x00 0xff>;
	num-lanes = <1>;
	#address-cells = <3>;
	#size-cells = <2>;

	ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
	0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */

	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	<0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	<0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	<0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

	clocks = <&gcc PCIE_1_A_CLK>,
	<&gcc PCIE_1_H_CLK>,
	<&gcc PCIE_1_PHY_CLK>,
	<&gcc PCIE_1_AUX_CLK>,
	<&gcc PCIE_1_ALT_REF_CLK>;
	clock-names = "core", "iface", "phy", "aux", "ref";

	assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
	assigned-clock-rates = <100000000>;

	resets = <&gcc PCIE_1_ACLK_RESET>,
	<&gcc PCIE_1_HCLK_RESET>,
	<&gcc PCIE_1_POR_RESET>,
	<&gcc PCIE_1_PCI_RESET>,
	<&gcc PCIE_1_PHY_RESET>,
	<&gcc PCIE_1_EXT_RESET>;
	reset-names = "axi", "ahb", "por", "pci", "phy", "ext";

	pinctrl-0 = <&pcie1_pins>;
	pinctrl-names = "default";

	status = "disabled";
	perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
	};

	pcie2: pci@1b900000 {
	compatible = "qcom,pcie-ipq8064";
	reg = <0x1b900000 0x1000
	0x1b902000 0x80
	0x1ba00000 0x100
	0x35f00000 0x100000>;
	reg-names = "dbi", "elbi", "parf", "config";
	device_type = "pci";
	linux,pci-domain = <2>;
	bus-range = <0x00 0xff>;
	num-lanes = <1>;
	#address-cells = <3>;
	#size-cells = <2>;

	ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
	0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */

	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	<0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	<0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	<0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

	clocks = <&gcc PCIE_2_A_CLK>,
	<&gcc PCIE_2_H_CLK>,
	<&gcc PCIE_2_PHY_CLK>,
	<&gcc PCIE_2_AUX_CLK>,
	<&gcc PCIE_2_ALT_REF_CLK>;
	clock-names = "core", "iface", "phy", "aux", "ref";

	assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
	assigned-clock-rates = <100000000>;

	resets = <&gcc PCIE_2_ACLK_RESET>,
	<&gcc PCIE_2_HCLK_RESET>,
	<&gcc PCIE_2_POR_RESET>,
	<&gcc PCIE_2_PCI_RESET>,
	<&gcc PCIE_2_PHY_RESET>,
	<&gcc PCIE_2_EXT_RESET>;
	reset-names = "axi", "ahb", "por", "pci", "phy", "ext";

	pinctrl-0 = <&pcie2_pins>;
	pinctrl-names = "default";

	status = "disabled";
	perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
	};

	vsdcc_fixed: vsdcc-regulator {
	compatible = "regulator-fixed";
	regulator-name = "SDCC Power";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	sdcc1bam:dma@12402000 {
	compatible = "qcom,bam-v1.3.0";
	reg = <0x12402000 0x8000>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc SDC1_H_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	};

	sdcc3bam:dma@12182000 {
	compatible = "qcom,bam-v1.3.0";
	reg = <0x12182000 0x8000>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc SDC3_H_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	};

	amba {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	sdcc@12400000 {
	status = "disabled";
	compatible = "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x00051180>;
	reg = <0x12400000 0x2000>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
	clock-names = "mclk", "apb_pclk";
	bus-width = <8>;
	max-frequency = <96000000>;
	non-removable;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	vmmc-supply = <&vsdcc_fixed>;
	dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
	dma-names = "tx", "rx";
	};

	sdcc@12180000 {
	compatible = "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x00051180>;
	status = "disabled";
	reg = <0x12180000 0x2000>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
	clock-names = "mclk", "apb_pclk";
	bus-width = <8>;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	max-frequency = <192000000>;
	#mmc-ddr-1_8v;
	sd-uhs-sdr104;
	sd-uhs-ddr50;
	vqmmc-supply = <&vsdcc_fixed>;
	dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
	dma-names = "tx", "rx";
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/qcom-mdm9615.dtsi b/sys/gnu/dts/arm/qcom-mdm9615.dtsi
	index 356e9535f7a6..347b4f7d7889 100644
	--- a/sys/gnu/dts/arm/qcom-mdm9615.dtsi
	+++ b/sys/gnu/dts/arm/qcom-mdm9615.dtsi
	@@ -1,553 +1,554 @@
	/*
	* Device Tree Source for Qualcomm MDM9615 SoC
	*
	* Copyright (C) 2016 BayLibre, SAS.
	* Author : Neil Armstrong <narmstrong@baylibre.com>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	/dts-v1/;

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/qcom,gcc-mdm9615.h>
	#include <dt-bindings/reset/qcom,gcc-mdm9615.h>
	#include <dt-bindings/mfd/qcom-rpm.h>
	#include <dt-bindings/soc/qcom,gsbi.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Qualcomm MDM9615";
	compatible = "qcom,mdm9615";
	interrupt-parent = <&intc>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a5";
	device_type = "cpu";
	next-level-cache = <&L2>;
	};
	};

	cpu-pmu {
	compatible = "arm,cortex-a5-pmu";
	interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	clocks {
	cxo_board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <19200000>;
	};
	};

	regulators {
	vsdcc_fixed: vsdcc-regulator {
	compatible = "regulator-fixed";
	regulator-name = "SDCC Power";
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <2700000>;
	regulator-always-on;
	};
	};

	soc: soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "simple-bus";

	L2: l2-cache@2040000 {
	compatible = "arm,pl310-cache";
	reg = <0x02040000 0x1000>;
	arm,data-latency = <2 2 0>;
	cache-unified;
	cache-level = <2>;
	};

	intc: interrupt-controller@2000000 {
	compatible = "qcom,msm-qgic2";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0x02000000 0x1000>,
	<0x02002000 0x1000>;
	};

	timer@200a000 {
	compatible = "qcom,kpss-timer", "qcom,msm-timer";
	interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_EDGE_RISING)>,
	<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_EDGE_RISING)>,
	<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_EDGE_RISING)>;
	reg = <0x0200a000 0x100>;
	clock-frequency = <27000000>,
	<32768>;
	cpu-offset = <0x80000>;
	};

	msmgpio: pinctrl@800000 {
	compatible = "qcom,mdm9615-pinctrl";
	gpio-controller;
	+ gpio-ranges = <&msmgpio 0 0 88>;
	#gpio-cells = <2>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x800000 0x4000>;
	};

	gcc: clock-controller@900000 {
	compatible = "qcom,gcc-mdm9615";
	#clock-cells = <1>;
	#reset-cells = <1>;
	reg = <0x900000 0x4000>;
	};

	lcc: clock-controller@28000000 {
	compatible = "qcom,lcc-mdm9615";
	reg = <0x28000000 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	l2cc: clock-controller@2011000 {
	compatible = "syscon";
	reg = <0x02011000 0x1000>;
	};

	rng@1a500000 {
	compatible = "qcom,prng";
	reg = <0x1a500000 0x200>;
	clocks = <&gcc PRNG_CLK>;
	clock-names = "core";
	assigned-clocks = <&gcc PRNG_CLK>;
	assigned-clock-rates = <32000000>;
	};

	gsbi2: gsbi@16100000 {
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <2>;
	reg = <0x16100000 0x100>;
	clocks = <&gcc GSBI2_H_CLK>;
	clock-names = "iface";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	gsbi2_i2c: i2c@16180000 {
	compatible = "qcom,i2c-qup-v1.1.1";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x16180000 0x1000>;
	interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};
	};

	gsbi3: gsbi@16200000 {
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <3>;
	reg = <0x16200000 0x100>;
	clocks = <&gcc GSBI3_H_CLK>;
	clock-names = "iface";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	gsbi3_spi: spi@16280000 {
	compatible = "qcom,spi-qup-v1.1.1";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x16280000 0x1000>;
	interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
	spi-max-frequency = <24000000>;

	clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};
	};

	gsbi4: gsbi@16300000 {
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <4>;
	reg = <0x16300000 0x100>;
	clocks = <&gcc GSBI4_H_CLK>;
	clock-names = "iface";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	syscon-tcsr = <&tcsr>;

	gsbi4_serial: serial@16340000 {
	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	reg = <0x16340000 0x1000>,
	<0x16300000 0x1000>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};
	};

	gsbi5: gsbi@16400000 {
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <5>;
	reg = <0x16400000 0x100>;
	clocks = <&gcc GSBI5_H_CLK>;
	clock-names = "iface";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	syscon-tcsr = <&tcsr>;

	gsbi5_i2c: i2c@16480000 {
	compatible = "qcom,i2c-qup-v1.1.1";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x16480000 0x1000>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

	/* QUP clock is not initialized, set rate */
	assigned-clocks = <&gcc GSBI5_QUP_CLK>;
	assigned-clock-rates = <24000000>;

	clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	gsbi5_serial: serial@16440000 {
	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	reg = <0x16440000 0x1000>,
	<0x16400000 0x1000>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};
	};

	qcom,ssbi@500000 {
	compatible = "qcom,ssbi";
	reg = <0x500000 0x1000>;
	qcom,controller-type = "pmic-arbiter";

	pmicintc: pmic@0 {
	compatible = "qcom,pm8018", "qcom,pm8921";
	interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <2>;
	interrupt-controller;
	#address-cells = <1>;
	#size-cells = <0>;

	pwrkey@1c {
	compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey";
	reg = <0x1c>;
	interrupt-parent = <&pmicintc>;
	interrupts = <50 IRQ_TYPE_EDGE_RISING>,
	<51 IRQ_TYPE_EDGE_RISING>;
	debounce = <15625>;
	pull-up;
	};

	pmicmpp: mpp@50 {
	compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
	interrupt-parent = <&pmicintc>;
	interrupts = <24 IRQ_TYPE_NONE>,
	<25 IRQ_TYPE_NONE>,
	<26 IRQ_TYPE_NONE>,
	<27 IRQ_TYPE_NONE>,
	<28 IRQ_TYPE_NONE>,
	<29 IRQ_TYPE_NONE>;
	reg = <0x50>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	rtc@11d {
	compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
	interrupt-parent = <&pmicintc>;
	interrupts = <39 IRQ_TYPE_EDGE_RISING>;
	reg = <0x11d>;
	allow-set-time;
	};

	pmicgpio: gpio@150 {
	compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pmicgpio 0 0 6>;
	#gpio-cells = <2>;
	};
	};
	};

	sdcc1bam: dma@12182000{
	compatible = "qcom,bam-v1.3.0";
	reg = <0x12182000 0x8000>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc SDC1_H_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	};

	sdcc2bam: dma@12142000{
	compatible = "qcom,bam-v1.3.0";
	reg = <0x12142000 0x8000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc SDC2_H_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	};

	amba {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	sdcc1: sdcc@12180000 {
	status = "disabled";
	compatible = "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x00051180>;
	reg = <0x12180000 0x2000>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
	clock-names = "mclk", "apb_pclk";
	bus-width = <8>;
	max-frequency = <48000000>;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	vmmc-supply = <&vsdcc_fixed>;
	dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
	dma-names = "tx", "rx";
	assigned-clocks = <&gcc SDC1_CLK>;
	assigned-clock-rates = <400000>;
	};

	sdcc2: sdcc@12140000 {
	compatible = "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x00051180>;
	status = "disabled";
	reg = <0x12140000 0x2000>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
	clock-names = "mclk", "apb_pclk";
	bus-width = <4>;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	max-frequency = <48000000>;
	no-1-8-v;
	vmmc-supply = <&vsdcc_fixed>;
	dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
	dma-names = "tx", "rx";
	assigned-clocks = <&gcc SDC2_CLK>;
	assigned-clock-rates = <400000>;
	};
	};

	tcsr: syscon@1a400000 {
	compatible = "qcom,tcsr-mdm9615", "syscon";
	reg = <0x1a400000 0x100>;
	};

	rpm: rpm@108000 {
	compatible = "qcom,rpm-mdm9615";
	reg = <0x108000 0x1000>;

	qcom,ipc = <&l2cc 0x8 2>;

	interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "ack", "err", "wakeup";

	regulators {
	compatible = "qcom,rpm-pm8018-regulators";

	vin_lvs1-supply = <&pm8018_s3>;

	vdd_l7-supply = <&pm8018_s4>;
	vdd_l8-supply = <&pm8018_s3>;
	vdd_l9_l10_l11_l12-supply = <&pm8018_s5>;

	/* Buck SMPS */
	pm8018_s1: s1 {
	regulator-min-microvolt = <500000>;
	regulator-max-microvolt = <1150000>;
	qcom,switch-mode-frequency = <1600000>;
	bias-pull-down;
	};

	pm8018_s2: s2 {
	regulator-min-microvolt = <1225000>;
	regulator-max-microvolt = <1300000>;
	qcom,switch-mode-frequency = <1600000>;
	bias-pull-down;
	};

	pm8018_s3: s3 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	qcom,switch-mode-frequency = <1600000>;
	bias-pull-down;
	};

	pm8018_s4: s4 {
	regulator-min-microvolt = <2100000>;
	regulator-max-microvolt = <2200000>;
	qcom,switch-mode-frequency = <1600000>;
	bias-pull-down;
	};

	pm8018_s5: s5 {
	regulator-always-on;
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	qcom,switch-mode-frequency = <1600000>;
	bias-pull-down;
	};

	/* PMOS LDO */
	pm8018_l2: l2 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	bias-pull-down;
	};

	pm8018_l3: l3 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	bias-pull-down;
	};

	pm8018_l4: l4 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	bias-pull-down;
	};

	pm8018_l5: l5 {
	regulator-min-microvolt = <2850000>;
	regulator-max-microvolt = <2850000>;
	bias-pull-down;
	};

	pm8018_l6: l6 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2850000>;
	bias-pull-down;
	};

	pm8018_l7: l7 {
	regulator-min-microvolt = <1850000>;
	regulator-max-microvolt = <1900000>;
	bias-pull-down;
	};

	pm8018_l8: l8 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	bias-pull-down;
	};

	pm8018_l9: l9 {
	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <1150000>;
	bias-pull-down;
	};

	pm8018_l10: l10 {
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	bias-pull-down;
	};

	pm8018_l11: l11 {
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	bias-pull-down;
	};

	pm8018_l12: l12 {
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	bias-pull-down;
	};

	pm8018_l13: l13 {
	regulator-min-microvolt = <1850000>;
	regulator-max-microvolt = <2950000>;
	bias-pull-down;
	};

	pm8018_l14: l14 {
	regulator-min-microvolt = <2850000>;
	regulator-max-microvolt = <2850000>;
	bias-pull-down;
	};

	/* Low Voltage Switch */
	pm8018_lvs1: lvs1 {
	bias-pull-down;
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/qcom-msm8660.dtsi b/sys/gnu/dts/arm/qcom-msm8660.dtsi
	index ec5cbc468bd3..480fc08cbe8e 100644
	--- a/sys/gnu/dts/arm/qcom-msm8660.dtsi
	+++ b/sys/gnu/dts/arm/qcom-msm8660.dtsi
	@@ -1,580 +1,581 @@
	// SPDX-License-Identifier: GPL-2.0
	/dts-v1/;

	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/qcom,gcc-msm8660.h>
	#include <dt-bindings/soc/qcom,gsbi.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Qualcomm MSM8660";
	compatible = "qcom,msm8660";
	interrupt-parent = <&intc>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	compatible = "qcom,scorpion";
	enable-method = "qcom,gcc-msm8660";
	device_type = "cpu";
	reg = <0>;
	next-level-cache = <&L2>;
	};

	cpu@1 {
	compatible = "qcom,scorpion";
	enable-method = "qcom,gcc-msm8660";
	device_type = "cpu";
	reg = <1>;
	next-level-cache = <&L2>;
	};

	L2: l2-cache {
	compatible = "cache";
	cache-level = <2>;
	};
	};

	memory {
	device_type = "memory";
	reg = <0x0 0x0>;
	};

	cpu-pmu {
	compatible = "qcom,scorpion-mp-pmu";
	interrupts = <1 9 0x304>;
	};

	clocks {
	cxo_board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <19200000>;
	};

	pxo_board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <27000000>;
	};

	sleep_clk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	};

	/*
	* These channels from the ADC are simply hardware monitors.
	* That is why the ADC is referred to as "HKADC" - HouseKeeping
	* ADC.
	*/
	iio-hwmon {
	compatible = "iio-hwmon";
	io-channels = <&xoadc 0x00 0x01>, /* Battery */
	<&xoadc 0x00 0x02>, /* DC in (charger) */
	<&xoadc 0x00 0x04>, /* VPH the main system voltage */
	<&xoadc 0x00 0x0b>, /* Die temperature */
	<&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
	<&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
	<&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
	};

	soc: soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "simple-bus";

	intc: interrupt-controller@2080000 {
	compatible = "qcom,msm-8660-qgic";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = < 0x02080000 0x1000 >,
	< 0x02081000 0x1000 >;
	};

	timer@2000000 {
	compatible = "qcom,scss-timer", "qcom,msm-timer";
	interrupts = <1 0 0x301>,
	<1 1 0x301>,
	<1 2 0x301>;
	reg = <0x02000000 0x100>;
	clock-frequency = <27000000>,
	<32768>;
	cpu-offset = <0x40000>;
	};

	tlmm: pinctrl@800000 {
	compatible = "qcom,msm8660-pinctrl";
	reg = <0x800000 0x4000>;

	gpio-controller;
	+ gpio-ranges = <&tlmm 0 0 173>;
	#gpio-cells = <2>;
	interrupts = <0 16 0x4>;
	interrupt-controller;
	#interrupt-cells = <2>;

	};

	gcc: clock-controller@900000 {
	compatible = "qcom,gcc-msm8660";
	#clock-cells = <1>;
	#reset-cells = <1>;
	reg = <0x900000 0x4000>;
	};

	gsbi6: gsbi@16500000 {
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <12>;
	reg = <0x16500000 0x100>;
	clocks = <&gcc GSBI6_H_CLK>;
	clock-names = "iface";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	status = "disabled";

	syscon-tcsr = <&tcsr>;

	gsbi6_serial: serial@16540000 {
	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	reg = <0x16540000 0x1000>,
	<0x16500000 0x1000>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	gsbi6_i2c: i2c@16580000 {
	compatible = "qcom,i2c-qup-v1.1.1";
	reg = <0x16580000 0x1000>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
	clock-names = "core", "iface";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};
	};

	gsbi7: gsbi@16600000 {
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <12>;
	reg = <0x16600000 0x100>;
	clocks = <&gcc GSBI7_H_CLK>;
	clock-names = "iface";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	status = "disabled";

	syscon-tcsr = <&tcsr>;

	gsbi7_serial: serial@16640000 {
	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	reg = <0x16640000 0x1000>,
	<0x16600000 0x1000>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	gsbi7_i2c: i2c@16680000 {
	compatible = "qcom,i2c-qup-v1.1.1";
	reg = <0x16680000 0x1000>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
	clock-names = "core", "iface";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};
	};

	gsbi8: gsbi@19800000 {
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <12>;
	reg = <0x19800000 0x100>;
	clocks = <&gcc GSBI8_H_CLK>;
	clock-names = "iface";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	syscon-tcsr = <&tcsr>;

	gsbi8_i2c: i2c@19880000 {
	compatible = "qcom,i2c-qup-v1.1.1";
	reg = <0x19880000 0x1000>;
	interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
	clock-names = "core", "iface";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};
	};

	gsbi12: gsbi@19c00000 {
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <12>;
	reg = <0x19c00000 0x100>;
	clocks = <&gcc GSBI12_H_CLK>;
	clock-names = "iface";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	syscon-tcsr = <&tcsr>;

	gsbi12_serial: serial@19c40000 {
	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	reg = <0x19c40000 0x1000>,
	<0x19c00000 0x1000>;
	interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	gsbi12_i2c: i2c@19c80000 {
	compatible = "qcom,i2c-qup-v1.1.1";
	reg = <0x19c80000 0x1000>;
	interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
	clock-names = "core", "iface";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};
	};

	external-bus@1a100000 {
	compatible = "qcom,msm8660-ebi2";
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0x0 0x1a800000 0x00800000>,
	<1 0x0 0x1b000000 0x00800000>,
	<2 0x0 0x1b800000 0x00800000>,
	<3 0x0 0x1d000000 0x08000000>,
	<4 0x0 0x1c800000 0x00800000>,
	<5 0x0 0x1c000000 0x00800000>;
	reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
	reg-names = "ebi2", "xmem";
	clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
	clock-names = "ebi2x", "ebi2";
	status = "disabled";
	};

	qcom,ssbi@500000 {
	compatible = "qcom,ssbi";
	reg = <0x500000 0x1000>;
	qcom,controller-type = "pmic-arbiter";

	pm8058: pmic@0 {
	compatible = "qcom,pm8058";
	interrupt-parent = <&tlmm>;
	interrupts = <88 8>;
	#interrupt-cells = <2>;
	interrupt-controller;
	#address-cells = <1>;
	#size-cells = <0>;

	pm8058_gpio: gpio@150 {
	compatible = "qcom,pm8058-gpio",
	"qcom,ssbi-gpio";
	reg = <0x150>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pm8058_gpio 0 0 44>;
	#gpio-cells = <2>;

	};

	pm8058_mpps: mpps@50 {
	compatible = "qcom,pm8058-mpp",
	"qcom,ssbi-mpp";
	reg = <0x50>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-parent = <&pm8058>;
	interrupts =
	<128 IRQ_TYPE_NONE>,
	<129 IRQ_TYPE_NONE>,
	<130 IRQ_TYPE_NONE>,
	<131 IRQ_TYPE_NONE>,
	<132 IRQ_TYPE_NONE>,
	<133 IRQ_TYPE_NONE>,
	<134 IRQ_TYPE_NONE>,
	<135 IRQ_TYPE_NONE>,
	<136 IRQ_TYPE_NONE>,
	<137 IRQ_TYPE_NONE>,
	<138 IRQ_TYPE_NONE>,
	<139 IRQ_TYPE_NONE>;
	};

	pwrkey@1c {
	compatible = "qcom,pm8058-pwrkey";
	reg = <0x1c>;
	interrupt-parent = <&pm8058>;
	interrupts = <50 1>, <51 1>;
	debounce = <15625>;
	pull-up;
	};

	keypad@148 {
	compatible = "qcom,pm8058-keypad";
	reg = <0x148>;
	interrupt-parent = <&pm8058>;
	interrupts = <74 1>, <75 1>;
	debounce = <15>;
	scan-delay = <32>;
	row-hold = <91500>;
	};

	xoadc: xoadc@197 {
	compatible = "qcom,pm8058-adc";
	reg = <0x197>;
	interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
	#address-cells = <2>;
	#size-cells = <0>;
	#io-channel-cells = <2>;

	vcoin: adc-channel@0 {
	reg = <0x00 0x00>;
	};
	vbat: adc-channel@1 {
	reg = <0x00 0x01>;
	};
	dcin: adc-channel@2 {
	reg = <0x00 0x02>;
	};
	ichg: adc-channel@3 {
	reg = <0x00 0x03>;
	};
	vph_pwr: adc-channel@4 {
	reg = <0x00 0x04>;
	};
	usb_vbus: adc-channel@a {
	reg = <0x00 0x0a>;
	};
	die_temp: adc-channel@b {
	reg = <0x00 0x0b>;
	};
	ref_625mv: adc-channel@c {
	reg = <0x00 0x0c>;
	};
	ref_1250mv: adc-channel@d {
	reg = <0x00 0x0d>;
	};
	ref_325mv: adc-channel@e {
	reg = <0x00 0x0e>;
	};
	ref_muxoff: adc-channel@f {
	reg = <0x00 0x0f>;
	};
	};

	rtc@1e8 {
	compatible = "qcom,pm8058-rtc";
	reg = <0x1e8>;
	interrupt-parent = <&pm8058>;
	interrupts = <39 1>;
	allow-set-time;
	};

	vibrator@4a {
	compatible = "qcom,pm8058-vib";
	reg = <0x4a>;
	};
	};
	};

	l2cc: clock-controller@2082000 {
	compatible = "syscon";
	reg = <0x02082000 0x1000>;
	};

	rpm: rpm@104000 {
	compatible = "qcom,rpm-msm8660";
	reg = <0x00104000 0x1000>;
	qcom,ipc = <&l2cc 0x8 2>;

	interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "ack", "err", "wakeup";
	clocks = <&gcc RPM_MSG_RAM_H_CLK>;
	clock-names = "ram";

	rpmcc: clock-controller {
	compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
	#clock-cells = <1>;
	};

	pm8901-regulators {
	compatible = "qcom,rpm-pm8901-regulators";

	pm8901_l0: l0 {};
	pm8901_l1: l1 {};
	pm8901_l2: l2 {};
	pm8901_l3: l3 {};
	pm8901_l4: l4 {};
	pm8901_l5: l5 {};
	pm8901_l6: l6 {};

	/* S0 and S1 Handled as SAW regulators by SPM */
	pm8901_s2: s2 {};
	pm8901_s3: s3 {};
	pm8901_s4: s4 {};

	pm8901_lvs0: lvs0 {};
	pm8901_lvs1: lvs1 {};
	pm8901_lvs2: lvs2 {};
	pm8901_lvs3: lvs3 {};

	pm8901_mvs: mvs {};
	};

	pm8058-regulators {
	compatible = "qcom,rpm-pm8058-regulators";

	pm8058_l0: l0 {};
	pm8058_l1: l1 {};
	pm8058_l2: l2 {};
	pm8058_l3: l3 {};
	pm8058_l4: l4 {};
	pm8058_l5: l5 {};
	pm8058_l6: l6 {};
	pm8058_l7: l7 {};
	pm8058_l8: l8 {};
	pm8058_l9: l9 {};
	pm8058_l10: l10 {};
	pm8058_l11: l11 {};
	pm8058_l12: l12 {};
	pm8058_l13: l13 {};
	pm8058_l14: l14 {};
	pm8058_l15: l15 {};
	pm8058_l16: l16 {};
	pm8058_l17: l17 {};
	pm8058_l18: l18 {};
	pm8058_l19: l19 {};
	pm8058_l20: l20 {};
	pm8058_l21: l21 {};
	pm8058_l22: l22 {};
	pm8058_l23: l23 {};
	pm8058_l24: l24 {};
	pm8058_l25: l25 {};

	pm8058_s0: s0 {};
	pm8058_s1: s1 {};
	pm8058_s2: s2 {};
	pm8058_s3: s3 {};
	pm8058_s4: s4 {};

	pm8058_lvs0: lvs0 {};
	pm8058_lvs1: lvs1 {};

	pm8058_ncp: ncp {};
	};
	};

	amba {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	sdcc1: sdcc@12400000 {
	status = "disabled";
	compatible = "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x00051180>;
	reg = <0x12400000 0x8000>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
	clock-names = "mclk", "apb_pclk";
	bus-width = <8>;
	max-frequency = <48000000>;
	non-removable;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	};

	sdcc2: sdcc@12140000 {
	status = "disabled";
	compatible = "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x00051180>;
	reg = <0x12140000 0x8000>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
	clock-names = "mclk", "apb_pclk";
	bus-width = <8>;
	max-frequency = <48000000>;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	};

	sdcc3: sdcc@12180000 {
	compatible = "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x00051180>;
	status = "disabled";
	reg = <0x12180000 0x8000>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
	clock-names = "mclk", "apb_pclk";
	bus-width = <4>;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	max-frequency = <48000000>;
	no-1-8-v;
	};

	sdcc4: sdcc@121c0000 {
	compatible = "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x00051180>;
	status = "disabled";
	reg = <0x121c0000 0x8000>;
	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
	clock-names = "mclk", "apb_pclk";
	bus-width = <4>;
	max-frequency = <48000000>;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	};

	sdcc5: sdcc@12200000 {
	compatible = "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x00051180>;
	status = "disabled";
	reg = <0x12200000 0x8000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
	clock-names = "mclk", "apb_pclk";
	bus-width = <4>;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	max-frequency = <48000000>;
	};
	};

	tcsr: syscon@1a400000 {
	compatible = "qcom,tcsr-msm8660", "syscon";
	reg = <0x1a400000 0x100>;
	};
	};

	};
	diff --git a/sys/gnu/dts/arm/qcom-msm8960.dtsi b/sys/gnu/dts/arm/qcom-msm8960.dtsi
	index f2aeaccdc1ad..172ea3c70eac 100644
	--- a/sys/gnu/dts/arm/qcom-msm8960.dtsi
	+++ b/sys/gnu/dts/arm/qcom-msm8960.dtsi
	@@ -1,330 +1,331 @@
	// SPDX-License-Identifier: GPL-2.0
	/dts-v1/;

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/qcom,gcc-msm8960.h>
	#include <dt-bindings/mfd/qcom-rpm.h>
	#include <dt-bindings/soc/qcom,gsbi.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Qualcomm MSM8960";
	compatible = "qcom,msm8960";
	interrupt-parent = <&intc>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <1 14 0x304>;

	cpu@0 {
	compatible = "qcom,krait";
	enable-method = "qcom,kpss-acc-v1";
	device_type = "cpu";
	reg = <0>;
	next-level-cache = <&L2>;
	qcom,acc = <&acc0>;
	qcom,saw = <&saw0>;
	};

	cpu@1 {
	compatible = "qcom,krait";
	enable-method = "qcom,kpss-acc-v1";
	device_type = "cpu";
	reg = <1>;
	next-level-cache = <&L2>;
	qcom,acc = <&acc1>;
	qcom,saw = <&saw1>;
	};

	L2: l2-cache {
	compatible = "cache";
	cache-level = <2>;
	};
	};

	memory {
	device_type = "memory";
	reg = <0x0 0x0>;
	};

	cpu-pmu {
	compatible = "qcom,krait-pmu";
	interrupts = <1 10 0x304>;
	qcom,no-pc-write;
	};

	clocks {
	cxo_board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <19200000>;
	clock-output-names = "cxo_board";
	};

	pxo_board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <27000000>;
	clock-output-names = "pxo_board";
	};

	sleep_clk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "sleep_clk";
	};
	};

	soc: soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "simple-bus";

	intc: interrupt-controller@2000000 {
	compatible = "qcom,msm-qgic2";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0x02000000 0x1000>,
	<0x02002000 0x1000>;
	};

	timer@200a000 {
	compatible = "qcom,kpss-timer",
	"qcom,kpss-wdt-msm8960", "qcom,msm-timer";
	interrupts = <1 1 0x301>,
	<1 2 0x301>,
	<1 3 0x301>;
	reg = <0x0200a000 0x100>;
	clock-frequency = <27000000>,
	<32768>;
	cpu-offset = <0x80000>;
	};

	msmgpio: pinctrl@800000 {
	compatible = "qcom,msm8960-pinctrl";
	gpio-controller;
	+ gpio-ranges = <&msmgpio 0 0 152>;
	#gpio-cells = <2>;
	interrupts = <0 16 0x4>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x800000 0x4000>;
	};

	gcc: clock-controller@900000 {
	compatible = "qcom,gcc-msm8960";
	#clock-cells = <1>;
	#reset-cells = <1>;
	reg = <0x900000 0x4000>;
	};

	lcc: clock-controller@28000000 {
	compatible = "qcom,lcc-msm8960";
	reg = <0x28000000 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	clock-controller@4000000 {
	compatible = "qcom,mmcc-msm8960";
	reg = <0x4000000 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	l2cc: clock-controller@2011000 {
	compatible = "syscon";
	reg = <0x2011000 0x1000>;
	};

	rpm@108000 {
	compatible = "qcom,rpm-msm8960";
	reg = <0x108000 0x1000>;
	qcom,ipc = <&l2cc 0x8 2>;

	interrupts = <0 19 0>, <0 21 0>, <0 22 0>;
	interrupt-names = "ack", "err", "wakeup";

	regulators {
	compatible = "qcom,rpm-pm8921-regulators";
	};
	};

	acc0: clock-controller@2088000 {
	compatible = "qcom,kpss-acc-v1";
	reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
	};

	acc1: clock-controller@2098000 {
	compatible = "qcom,kpss-acc-v1";
	reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
	};

	saw0: regulator@2089000 {
	compatible = "qcom,saw2";
	reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
	regulator;
	};

	saw1: regulator@2099000 {
	compatible = "qcom,saw2";
	reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
	regulator;
	};

	gsbi5: gsbi@16400000 {
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <5>;
	reg = <0x16400000 0x100>;
	clocks = <&gcc GSBI5_H_CLK>;
	clock-names = "iface";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	syscon-tcsr = <&tcsr>;

	gsbi5_serial: serial@16440000 {
	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	reg = <0x16440000 0x1000>,
	<0x16400000 0x1000>;
	interrupts = <0 154 0x0>;
	clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};
	};

	qcom,ssbi@500000 {
	compatible = "qcom,ssbi";
	reg = <0x500000 0x1000>;
	qcom,controller-type = "pmic-arbiter";

	pmicintc: pmic@0 {
	compatible = "qcom,pm8921";
	interrupt-parent = <&msmgpio>;
	interrupts = <104 8>;
	#interrupt-cells = <2>;
	interrupt-controller;
	#address-cells = <1>;
	#size-cells = <0>;

	pwrkey@1c {
	compatible = "qcom,pm8921-pwrkey";
	reg = <0x1c>;
	interrupt-parent = <&pmicintc>;
	interrupts = <50 1>, <51 1>;
	debounce = <15625>;
	pull-up;
	};

	keypad@148 {
	compatible = "qcom,pm8921-keypad";
	reg = <0x148>;
	interrupt-parent = <&pmicintc>;
	interrupts = <74 1>, <75 1>;
	debounce = <15>;
	scan-delay = <32>;
	row-hold = <91500>;
	};

	rtc@11d {
	compatible = "qcom,pm8921-rtc";
	interrupt-parent = <&pmicintc>;
	interrupts = <39 1>;
	reg = <0x11d>;
	allow-set-time;
	};
	};
	};

	rng@1a500000 {
	compatible = "qcom,prng";
	reg = <0x1a500000 0x200>;
	clocks = <&gcc PRNG_CLK>;
	clock-names = "core";
	};

	/* Temporary fixed regulator */
	vsdcc_fixed: vsdcc-regulator {
	compatible = "regulator-fixed";
	regulator-name = "SDCC Power";
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <2700000>;
	regulator-always-on;
	};

	amba {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	sdcc1: sdcc@12400000 {
	status = "disabled";
	compatible = "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x00051180>;
	reg = <0x12400000 0x8000>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
	clock-names = "mclk", "apb_pclk";
	bus-width = <8>;
	max-frequency = <96000000>;
	non-removable;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	vmmc-supply = <&vsdcc_fixed>;
	};

	sdcc3: sdcc@12180000 {
	compatible = "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x00051180>;
	status = "disabled";
	reg = <0x12180000 0x8000>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
	clock-names = "mclk", "apb_pclk";
	bus-width = <4>;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	max-frequency = <192000000>;
	no-1-8-v;
	vmmc-supply = <&vsdcc_fixed>;
	};
	};

	tcsr: syscon@1a400000 {
	compatible = "qcom,tcsr-msm8960", "syscon";
	reg = <0x1a400000 0x100>;
	};

	gsbi@16000000 {
	compatible = "qcom,gsbi-v1.0.0";
	cell-index = <1>;
	reg = <0x16000000 0x100>;
	clocks = <&gcc GSBI1_H_CLK>;
	clock-names = "iface";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	spi@16080000 {
	compatible = "qcom,spi-qup-v1.1.1";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x16080000 0x1000>;
	interrupts = <0 147 0>;
	spi-max-frequency = <24000000>;
	cs-gpios = <&msmgpio 8 0>;

	clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/qcom-msm8974-lge-nexus5-hammerhead.dts b/sys/gnu/dts/arm/qcom-msm8974-lge-nexus5-hammerhead.dts
	index 3487daf98e81..32b474bfeec3 100644
	--- a/sys/gnu/dts/arm/qcom-msm8974-lge-nexus5-hammerhead.dts
	+++ b/sys/gnu/dts/arm/qcom-msm8974-lge-nexus5-hammerhead.dts
	@@ -1,662 +1,733 @@
	// SPDX-License-Identifier: GPL-2.0
	#include "qcom-msm8974.dtsi"
	#include "qcom-pm8841.dtsi"
	#include "qcom-pm8941.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>

	/ {
	model = "LGE MSM 8974 HAMMERHEAD";
	compatible = "lge,hammerhead", "qcom,msm8974";

	aliases {
	serial0 = &blsp1_uart1;
	+ serial1 = &blsp2_uart10;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	smd {
	rpm {
	rpm_requests {
	pm8841-regulators {
	s1 {
	regulator-min-microvolt = <675000>;
	regulator-max-microvolt = <1050000>;
	};

	s2 {
	regulator-min-microvolt = <500000>;
	regulator-max-microvolt = <1050000>;
	};

	s3 {
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	};

	s4 {
	regulator-min-microvolt = <815000>;
	regulator-max-microvolt = <900000>;
	};
	};

	pm8941-regulators {
	vdd_l1_l3-supply = <&pm8941_s1>;
	vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
	vdd_l4_l11-supply = <&pm8941_s1>;
	vdd_l5_l7-supply = <&pm8941_s2>;
	vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
	vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>;
	vdd_l9_l10_l17_l22-supply = <&vreg_boost>;
	vdd_l13_l20_l23_l24-supply = <&vreg_boost>;
	vdd_l21-supply = <&vreg_boost>;

	s1 {
	regulator-min-microvolt = <1300000>;
	regulator-max-microvolt = <1300000>;

	regulator-always-on;
	regulator-boot-on;
	};

	s2 {
	regulator-min-microvolt = <2150000>;
	regulator-max-microvolt = <2150000>;

	regulator-boot-on;
	};

	s3 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	regulator-always-on;
	regulator-boot-on;
	};

	l1 {
	regulator-min-microvolt = <1225000>;
	regulator-max-microvolt = <1225000>;

	regulator-always-on;
	regulator-boot-on;
	};

	l2 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	l3 {
	regulator-min-microvolt = <1225000>;
	regulator-max-microvolt = <1225000>;
	};

	l4 {
	regulator-min-microvolt = <1225000>;
	regulator-max-microvolt = <1225000>;
	};

	l5 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	l6 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	regulator-boot-on;
	};

	l7 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	regulator-boot-on;
	};

	l8 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	l9 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2950000>;
	};

	l10 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2950000>;
	};

	l11 {
	regulator-min-microvolt = <1300000>;
	regulator-max-microvolt = <1300000>;
	};

	l12 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	regulator-always-on;
	regulator-boot-on;
	};

	l13 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2950000>;

	regulator-boot-on;
	};

	l14 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	l15 {
	regulator-min-microvolt = <2050000>;
	regulator-max-microvolt = <2050000>;
	};

	l16 {
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <2700000>;
	};

	l17 {
	regulator-min-microvolt = <2850000>;
	regulator-max-microvolt = <2850000>;
	};

	l18 {
	regulator-min-microvolt = <2850000>;
	regulator-max-microvolt = <2850000>;
	};

	l19 {
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3300000>;
	};

	l20 {
	regulator-min-microvolt = <2950000>;
	regulator-max-microvolt = <2950000>;

	regulator-boot-on;
	regulator-system-load = <200000>;
	regulator-allow-set-load;
	};

	l21 {
	regulator-min-microvolt = <2950000>;
	regulator-max-microvolt = <2950000>;

	regulator-boot-on;
	};

	l22 {
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3300000>;
	};

	l23 {
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	};

	l24 {
	regulator-min-microvolt = <3075000>;
	regulator-max-microvolt = <3075000>;

	regulator-boot-on;
	};
	};
	};
	};
	};

	vreg_wlan: wlan-regulator {
	compatible = "regulator-fixed";

	regulator-name = "wl-reg";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&msmgpio 26 GPIO_ACTIVE_HIGH>;
	enable-active-high;

	pinctrl-names = "default";
	pinctrl-0 = <&wlan_regulator_pin>;
	};
	};

	&soc {
	serial@f991d000 {
	status = "ok";
	};

	pinctrl@fd510000 {
	sdhc1_pin_a: sdhc1-pin-active {
	clk {
	pins = "sdc1_clk";
	drive-strength = <16>;
	bias-disable;
	};

	cmd-data {
	pins = "sdc1_cmd", "sdc1_data";
	drive-strength = <10>;
	bias-pull-up;
	};
	};

	sdhc2_pin_a: sdhc2-pin-active {
	clk {
	pins = "sdc2_clk";
	drive-strength = <6>;
	bias-disable;
	};

	cmd-data {
	pins = "sdc2_cmd", "sdc2_data";
	drive-strength = <6>;
	bias-pull-up;
	};
	};

	i2c1_pins: i2c1 {
	mux {
	pins = "gpio2", "gpio3";
	function = "blsp_i2c1";

	drive-strength = <2>;
	bias-disable;
	};
	};

	i2c2_pins: i2c2 {
	mux {
	pins = "gpio6", "gpio7";
	function = "blsp_i2c2";

	drive-strength = <2>;
	bias-disable;
	};
	};

	i2c3_pins: i2c3 {
	mux {
	pins = "gpio10", "gpio11";
	function = "blsp_i2c3";
	drive-strength = <2>;
	bias-disable;
	};
	};

	i2c11_pins: i2c11 {
	mux {
	pins = "gpio83", "gpio84";
	function = "blsp_i2c11";

	drive-strength = <2>;
	bias-disable;
	};
	};

	i2c12_pins: i2c12 {
	mux {
	pins = "gpio87", "gpio88";
	function = "blsp_i2c12";
	drive-strength = <2>;
	bias-disable;
	};
	};

	mpu6515_pin: mpu6515 {
	irq {
	pins = "gpio73";
	function = "gpio";
	bias-disable;
	input-enable;
	};
	};

	touch_pin: touch {
	int {
	pins = "gpio5";
	function = "gpio";

	drive-strength = <2>;
	bias-disable;
	input-enable;
	};

	reset {
	pins = "gpio8";
	function = "gpio";

	drive-strength = <2>;
	bias-pull-up;
	};
	};

	panel_pin: panel {
	te {
	pins = "gpio12";
	function = "mdp_vsync";

	drive-strength = <2>;
	bias-disable;
	};
	};
	+
	+ bt_pin: bt {
	+ hostwake {
	+ pins = "gpio42";
	+ function = "gpio";
	+ };
	+
	+ devwake {
	+ pins = "gpio62";
	+ function = "gpio";
	+ };
	+
	+ shutdown {
	+ pins = "gpio41";
	+ function = "gpio";
	+ };
	+ };
	+
	+ blsp2_uart10_pin_a: blsp2-uart10-pin-active {
	+ tx {
	+ pins = "gpio53";
	+ function = "blsp_uart10";
	+
	+ drive-strength = <2>;
	+ bias-disable;
	+ };
	+
	+ rx {
	+ pins = "gpio54";
	+ function = "blsp_uart10";
	+
	+ drive-strength = <2>;
	+ bias-pull-up;
	+ };
	+
	+ cts {
	+ pins = "gpio55";
	+ function = "blsp_uart10";
	+
	+ drive-strength = <2>;
	+ bias-pull-up;
	+ };
	+
	+ rts {
	+ pins = "gpio56";
	+ function = "blsp_uart10";
	+
	+ drive-strength = <2>;
	+ bias-disable;
	+ };
	+ };
	};

	sdhci@f9824900 {
	status = "ok";

	vmmc-supply = <&pm8941_l20>;
	vqmmc-supply = <&pm8941_s3>;

	bus-width = <8>;
	non-removable;

	pinctrl-names = "default";
	pinctrl-0 = <&sdhc1_pin_a>;
	};

	sdhci@f98a4900 {
	status = "ok";

	max-frequency = <100000000>;
	bus-width = <4>;
	non-removable;
	vmmc-supply = <&vreg_wlan>;
	vqmmc-supply = <&pm8941_s3>;

	pinctrl-names = "default";
	pinctrl-0 = <&sdhc2_pin_a>;

	#address-cells = <1>;
	#size-cells = <0>;

	bcrmf@1 {
	compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac";
	reg = <1>;

	brcm,drive-strength = <10>;

	pinctrl-names = "default";
	pinctrl-0 = <&wlan_sleep_clk_pin>;
	};
	};

	gpio-keys {
	compatible = "gpio-keys";
	input-name = "gpio-keys";

	pinctrl-names = "default";
	pinctrl-0 = <&gpio_keys_pin_a>;

	volume-up {
	label = "volume_up";
	gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
	linux,input-type = <1>;
	linux,code = <KEY_VOLUMEUP>;
	};

	volume-down {
	label = "volume_down";
	gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>;
	linux,input-type = <1>;
	linux,code = <KEY_VOLUMEDOWN>;
	};
	};

	+ serial@f9960000 {
	+ status = "ok";
	+
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&blsp2_uart10_pin_a>;
	+
	+ bluetooth {
	+ compatible = "brcm,bcm43438-bt";
	+ max-speed = <3000000>;
	+
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&bt_pin>;
	+
	+ host-wakeup-gpios = <&msmgpio 42 GPIO_ACTIVE_HIGH>;
	+ device-wakeup-gpios = <&msmgpio 62 GPIO_ACTIVE_HIGH>;
	+ shutdown-gpios = <&msmgpio 41 GPIO_ACTIVE_HIGH>;
	+ };
	+ };
	+
	i2c@f9967000 {
	status = "ok";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c11_pins>;
	clock-frequency = <355000>;
	qcom,src-freq = <50000000>;

	led-controller@38 {
	compatible = "ti,lm3630a";
	status = "ok";
	reg = <0x38>;

	#address-cells = <1>;
	#size-cells = <0>;

	led@0 {
	reg = <0>;
	led-sources = <0 1>;
	label = "lcd-backlight";
	default-brightness = <200>;
	};
	};
	};

	i2c@f9968000 {
	status = "ok";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c12_pins>;
	clock-frequency = <100000>;
	qcom,src-freq = <50000000>;

	mpu6515@68 {
	compatible = "invensense,mpu6515";
	reg = <0x68>;
	interrupts-extended = <&msmgpio 73 IRQ_TYPE_EDGE_FALLING>;
	vddio-supply = <&pm8941_lvs1>;

	pinctrl-names = "default";
	pinctrl-0 = <&mpu6515_pin>;

	i2c-gate {
	#address-cells = <1>;
	#size-cells = <0>;
	ak8963@f {
	compatible = "asahi-kasei,ak8963";
	reg = <0x0f>;
	gpios = <&msmgpio 67 0>;
	vid-supply = <&pm8941_lvs1>;
	vdd-supply = <&pm8941_l17>;
	};

	bmp280@76 {
	compatible = "bosch,bmp280";
	reg = <0x76>;
	vdda-supply = <&pm8941_lvs1>;
	vddd-supply = <&pm8941_l17>;
	};
	};
	};
	};

	i2c@f9923000 {
	status = "ok";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	clock-frequency = <100000>;
	qcom,src-freq = <50000000>;

	charger: bq24192@6b {
	compatible = "ti,bq24192";
	reg = <0x6b>;
	interrupts-extended = <&spmi_bus 0 0xd5 0 IRQ_TYPE_EDGE_FALLING>;

	omit-battery-class;

	usb_otg_vbus: usb-otg-vbus { };
	};
	};

	i2c@f9924000 {
	status = "ok";

	clock-frequency = <355000>;
	qcom,src-freq = <50000000>;

	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;

	synaptics@70 {
	compatible = "syna,rmi4-i2c";
	reg = <0x70>;

	interrupts-extended = <&msmgpio 5 IRQ_TYPE_EDGE_FALLING>;
	vdd-supply = <&pm8941_l22>;
	vio-supply = <&pm8941_lvs3>;

	pinctrl-names = "default";
	pinctrl-0 = <&touch_pin>;

	#address-cells = <1>;
	#size-cells = <0>;

	rmi4-f01@1 {
	reg = <0x1>;
	syna,nosleep-mode = <1>;
	};

	rmi4-f12@12 {
	reg = <0x12>;
	syna,sensor-type = <1>;
	};
	};
	};

	i2c@f9925000 {
	status = "ok";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins>;
	clock-frequency = <100000>;
	qcom,src-freq = <50000000>;

	avago_apds993@39 {
	compatible = "avago,apds9930";
	reg = <0x39>;
	interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>;
	vdd-supply = <&pm8941_l17>;
	vddio-supply = <&pm8941_lvs1>;
	led-max-microamp = <100000>;
	amstaos,proximity-diodes = <0>;
	};
	};

	usb@f9a55000 {
	status = "ok";

	phys = <&usb_hs1_phy>;
	phy-select = <&tcsr 0xb000 0>;

	extcon = <&charger>, <&usb_id>;
	vbus-supply = <&usb_otg_vbus>;

	hnp-disable;
	srp-disable;
	adp-disable;

	ulpi {
	phy@a {
	status = "ok";

	v1p8-supply = <&pm8941_l6>;
	v3p3-supply = <&pm8941_l24>;

	qcom,init-seq = /bits/ 8 <0x1 0x64>;
	};
	};
	};

	mdss@fd900000 {
	status = "ok";

	mdp@fd900000 {
	status = "ok";
	};

	dsi@fd922800 {
	status = "ok";

	vdda-supply = <&pm8941_l2>;
	vdd-supply = <&pm8941_lvs3>;
	vddio-supply = <&pm8941_l12>;

	#address-cells = <1>;
	#size-cells = <0>;

	ports {
	port@1 {
	endpoint {
	remote-endpoint = <&panel_in>;
	data-lanes = <0 1 2 3>;
	};
	};
	};

	panel: panel@0 {
	reg = <0>;
	compatible = "lg,acx467akm-7";

	pinctrl-names = "default";
	pinctrl-0 = <&panel_pin>;

	port {
	panel_in: endpoint {
	remote-endpoint = <&dsi0_out>;
	};
	};
	};
	};

	dsi-phy@fd922a00 {
	status = "ok";

	vddio-supply = <&pm8941_l12>;
	};
	};
	};

	&spmi_bus {
	pm8941@0 {
	gpios@c000 {
	gpio_keys_pin_a: gpio-keys-active {
	pins = "gpio2", "gpio3";
	function = "normal";

	bias-pull-up;
	power-source = <PM8941_GPIO_S3>;
	};

	wlan_sleep_clk_pin: wl-sleep-clk {
	pins = "gpio16";
	function = "func2";

	output-high;
	power-source = <PM8941_GPIO_S3>;
	};

	wlan_regulator_pin: wl-reg-active {
	pins = "gpio17";
	function = "normal";

	bias-disable;
	power-source = <PM8941_GPIO_S3>;
	};

	otg {
	gpio-hog;
	gpios = <35 GPIO_ACTIVE_HIGH>;
	output-high;
	line-name = "otg-gpio";
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/qcom-msm8974-sony-xperia-honami.dts b/sys/gnu/dts/arm/qcom-msm8974-sony-xperia-honami.dts
	index 450b8321e0a6..611bae9fe66b 100644
	--- a/sys/gnu/dts/arm/qcom-msm8974-sony-xperia-honami.dts
	+++ b/sys/gnu/dts/arm/qcom-msm8974-sony-xperia-honami.dts
	@@ -1,460 +1,485 @@
	// SPDX-License-Identifier: GPL-2.0
	#include "qcom-msm8974.dtsi"
	#include "qcom-pm8841.dtsi"
	#include "qcom-pm8941.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>

	/ {
	model = "Sony Xperia Z1";
	compatible = "sony,xperia-honami", "qcom,msm8974";

	aliases {
	serial0 = &blsp1_uart2;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	gpio-keys {
	compatible = "gpio-keys";
	input-name = "gpio-keys";

	pinctrl-names = "default";
	pinctrl-0 = <&gpio_keys_pin_a>;

	volume-down {
	label = "volume_down";
	gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
	linux,input-type = <1>;
	linux,code = <KEY_VOLUMEDOWN>;
	};

	camera-snapshot {
	label = "camera_snapshot";
	gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>;
	linux,input-type = <1>;
	linux,code = <KEY_CAMERA>;
	};

	camera-focus {
	label = "camera_focus";
	gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>;
	linux,input-type = <1>;
	linux,code = <KEY_CAMERA_FOCUS>;
	};

	volume-up {
	label = "volume_up";
	gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>;
	linux,input-type = <1>;
	linux,code = <KEY_VOLUMEUP>;
	};
	};

	memory@0 {
	reg = <0 0x40000000>, <0x40000000 0x40000000>;
	device_type = "memory";
	};

	smd {
	rpm {
	rpm_requests {
	pm8841-regulators {
	s1 {
	regulator-min-microvolt = <675000>;
	regulator-max-microvolt = <1050000>;
	};

	s2 {
	regulator-min-microvolt = <500000>;
	regulator-max-microvolt = <1050000>;
	};

	s3 {
	regulator-min-microvolt = <500000>;
	regulator-max-microvolt = <1050000>;
	};

	s4 {
	regulator-min-microvolt = <500000>;
	regulator-max-microvolt = <1050000>;
	};
	};

	pm8941-regulators {
	vdd_l1_l3-supply = <&pm8941_s1>;
	vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
	vdd_l4_l11-supply = <&pm8941_s1>;
	vdd_l5_l7-supply = <&pm8941_s2>;
	vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
	vdd_l9_l10_l17_l22-supply = <&vreg_boost>;
	vdd_l13_l20_l23_l24-supply = <&vreg_boost>;
	vdd_l21-supply = <&vreg_boost>;

	s1 {
	regulator-min-microvolt = <1300000>;
	regulator-max-microvolt = <1300000>;
	regulator-always-on;
	regulator-boot-on;
	};

	s2 {
	regulator-min-microvolt = <2150000>;
	regulator-max-microvolt = <2150000>;
	regulator-boot-on;
	};

	s3 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	s4 {
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	};

	l1 {
	regulator-min-microvolt = <1225000>;
	regulator-max-microvolt = <1225000>;

	regulator-always-on;
	regulator-boot-on;
	};

	l2 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	l3 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	l4 {
	regulator-min-microvolt = <1225000>;
	regulator-max-microvolt = <1225000>;
	};

	l5 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	l6 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	regulator-boot-on;
	};

	l7 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	regulator-boot-on;
	};

	l8 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	l9 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2950000>;
	};

	l11 {
	regulator-min-microvolt = <1300000>;
	regulator-max-microvolt = <1350000>;
	};

	l12 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	regulator-always-on;
	regulator-boot-on;
	};

	l13 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2950000>;

	regulator-boot-on;
	};

	l14 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	l15 {
	regulator-min-microvolt = <2050000>;
	regulator-max-microvolt = <2050000>;
	};

	l16 {
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <2700000>;
	};

	l17 {
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <2700000>;
	};

	l18 {
	regulator-min-microvolt = <2850000>;
	regulator-max-microvolt = <2850000>;
	};

	l19 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	l20 {
	regulator-min-microvolt = <2950000>;
	regulator-max-microvolt = <2950000>;

	regulator-allow-set-load;
	regulator-boot-on;
	regulator-system-load = <200000>;
	};

	l21 {
	regulator-min-microvolt = <2950000>;
	regulator-max-microvolt = <2950000>;

	regulator-boot-on;
	};

	l22 {
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	};

	l23 {
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	l24 {
	regulator-min-microvolt = <3075000>;
	regulator-max-microvolt = <3075000>;

	regulator-boot-on;
	};
	};
	};
	};
	};
	};

	&soc {
	+ usb@f9a55000 {
	+ status = "ok";
	+
	+ phys = <&usb_hs1_phy>;
	+ phy-select = <&tcsr 0xb000 0>;
	+ extcon = <&smbb>, <&usb_id>;
	+ vbus-supply = <&chg_otg>;
	+
	+ hnp-disable;
	+ srp-disable;
	+ adp-disable;
	+
	+ ulpi {
	+ phy@a {
	+ status = "ok";
	+
	+ v1p8-supply = <&pm8941_l6>;
	+ v3p3-supply = <&pm8941_l24>;
	+
	+ extcon = <&smbb>;
	+ qcom,init-seq = /bits/ 8 <0x1 0x64>;
	+ };
	+ };
	+ };
	+
	sdhci@f9824900 {
	status = "ok";

	vmmc-supply = <&pm8941_l20>;
	vqmmc-supply = <&pm8941_s3>;

	bus-width = <8>;
	non-removable;

	pinctrl-names = "default";
	pinctrl-0 = <&sdhc1_pin_a>;
	};

	sdhci@f98a4900 {
	status = "ok";

	bus-width = <4>;

	vmmc-supply = <&pm8941_l21>;
	vqmmc-supply = <&pm8941_l13>;

	cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>;

	pinctrl-names = "default";
	pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>;
	};

	serial@f991e000 {
	status = "ok";

	pinctrl-names = "default";
	pinctrl-0 = <&blsp1_uart2_pin_a>;
	};

	i2c@f9924000 {
	status = "ok";

	clock-frequency = <355000>;
	qcom,src-freq = <50000000>;

	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;

	synaptics@2c {
	compatible = "syna,rmi4-i2c";
	reg = <0x2c>;

	interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>;

	#address-cells = <1>;
	#size-cells = <0>;

	vdd-supply = <&pm8941_l22>;
	vio-supply = <&pm8941_lvs3>;

	pinctrl-names = "default";
	pinctrl-0 = <&ts_int_pin>;

	syna,startup-delay-ms = <10>;

	rmi4-f01@1 {
	reg = <0x1>;
	syna,nosleep-mode = <1>;
	};

	rmi4-f11@11 {
	reg = <0x11>;
	touchscreen-inverted-x;
	syna,sensor-type = <1>;
	};
	};
	};

	pinctrl@fd510000 {
	blsp1_uart2_pin_a: blsp1-uart2-pin-active {
	rx {
	pins = "gpio5";
	function = "blsp_uart2";

	drive-strength = <2>;
	bias-pull-up;
	};

	tx {
	pins = "gpio4";
	function = "blsp_uart2";

	drive-strength = <4>;
	bias-disable;
	};
	};

	i2c2_pins: i2c2 {
	mux {
	pins = "gpio6", "gpio7";
	function = "blsp_i2c2";

	drive-strength = <2>;
	bias-disable;
	};
	};

	sdhc1_pin_a: sdhc1-pin-active {
	clk {
	pins = "sdc1_clk";
	drive-strength = <16>;
	bias-disable;
	};

	cmd-data {
	pins = "sdc1_cmd", "sdc1_data";
	drive-strength = <10>;
	bias-pull-up;
	};
	};

	sdhc2_cd_pin_a: sdhc2-cd-pin-active {
	pins = "gpio62";
	function = "gpio";

	drive-strength = <2>;
	bias-disable;
	};

	sdhc2_pin_a: sdhc2-pin-active {
	clk {
	pins = "sdc2_clk";
	drive-strength = <10>;
	bias-disable;
	};

	cmd-data {
	pins = "sdc2_cmd", "sdc2_data";
	drive-strength = <6>;
	bias-pull-up;
	};
	};

	ts_int_pin: touch-int {
	pin {
	pins = "gpio61";
	function = "gpio";

	drive-strength = <2>;
	bias-disable;
	input-enable;
	};
	};
	};

	dma-controller@f9944000 {
	qcom,controlled-remotely;
	};
	};

	&spmi_bus {
	pm8941@0 {
	charger@1000 {
	qcom,fast-charge-safe-current = <1500000>;
	qcom,fast-charge-current-limit = <1500000>;
	qcom,dc-current-limit = <1800000>;
	qcom,fast-charge-safe-voltage = <4400000>;
	qcom,fast-charge-high-threshold-voltage = <4350000>;
	qcom,fast-charge-low-threshold-voltage = <3400000>;
	qcom,auto-recharge-threshold-voltage = <4200000>;
	qcom,minimum-input-voltage = <4300000>;
	};

	gpios@c000 {
	gpio_keys_pin_a: gpio-keys-active {
	pins = "gpio2", "gpio3", "gpio4", "gpio5";
	function = "normal";

	bias-pull-up;
	power-source = <PM8941_GPIO_S3>;
	};
	};

	coincell@2800 {
	status = "ok";
	qcom,rset-ohms = <2100>;
	qcom,vset-millivolts = <3000>;
	};
	};

	pm8941@1 {
	wled@d800 {
	status = "ok";

	qcom,cs-out;
	qcom,current-limit = <20>;
	qcom,current-boost-limit = <805>;
	qcom,switching-freq = <1600>;
	qcom,ovp = <29>;
	qcom,num-strings = <2>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/qcom-msm8974.dtsi b/sys/gnu/dts/arm/qcom-msm8974.dtsi
	index 4b161b809dd5..2ea2308d91b3 100644
	--- a/sys/gnu/dts/arm/qcom-msm8974.dtsi
	+++ b/sys/gnu/dts/arm/qcom-msm8974.dtsi
	@@ -1,1622 +1,1632 @@
	// SPDX-License-Identifier: GPL-2.0
	/dts-v1/;

	#include <dt-bindings/interconnect/qcom,msm8974.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/qcom,gcc-msm8974.h>
	#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
	#include <dt-bindings/clock/qcom,rpmcc.h>
	#include <dt-bindings/reset/qcom,gcc-msm8974.h>
	#include <dt-bindings/gpio/gpio.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Qualcomm MSM8974";
	compatible = "qcom,msm8974";
	interrupt-parent = <&intc>;

	reserved-memory {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	mpss_region: mpss@8000000 {
	reg = <0x08000000 0x5100000>;
	no-map;
	};

	mba_region: mba@d100000 {
	reg = <0x0d100000 0x100000>;
	no-map;
	};

	wcnss_region: wcnss@d200000 {
	reg = <0x0d200000 0xa00000>;
	no-map;
	};

	adsp_region: adsp@dc00000 {
	reg = <0x0dc00000 0x1900000>;
	no-map;
	};

	venus@f500000 {
	reg = <0x0f500000 0x500000>;
	no-map;
	};

	smem_region: smem@fa00000 {
	reg = <0xfa00000 0x200000>;
	no-map;
	};

	tz@fc00000 {
	reg = <0x0fc00000 0x160000>;
	no-map;
	};

	rfsa@fd60000 {
	reg = <0x0fd60000 0x20000>;
	no-map;
	};

	rmtfs@fd80000 {
	compatible = "qcom,rmtfs-mem";
	reg = <0x0fd80000 0x180000>;
	no-map;

	qcom,client-id = <1>;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_PPI 9 0xf04>;

	CPU0: cpu@0 {
	compatible = "qcom,krait";
	enable-method = "qcom,kpss-acc-v2";
	device_type = "cpu";
	reg = <0>;
	next-level-cache = <&L2>;
	qcom,acc = <&acc0>;
	qcom,saw = <&saw0>;
	cpu-idle-states = <&CPU_SPC>;
	};

	CPU1: cpu@1 {
	compatible = "qcom,krait";
	enable-method = "qcom,kpss-acc-v2";
	device_type = "cpu";
	reg = <1>;
	next-level-cache = <&L2>;
	qcom,acc = <&acc1>;
	qcom,saw = <&saw1>;
	cpu-idle-states = <&CPU_SPC>;
	};

	CPU2: cpu@2 {
	compatible = "qcom,krait";
	enable-method = "qcom,kpss-acc-v2";
	device_type = "cpu";
	reg = <2>;
	next-level-cache = <&L2>;
	qcom,acc = <&acc2>;
	qcom,saw = <&saw2>;
	cpu-idle-states = <&CPU_SPC>;
	};

	CPU3: cpu@3 {
	compatible = "qcom,krait";
	enable-method = "qcom,kpss-acc-v2";
	device_type = "cpu";
	reg = <3>;
	next-level-cache = <&L2>;
	qcom,acc = <&acc3>;
	qcom,saw = <&saw3>;
	cpu-idle-states = <&CPU_SPC>;
	};

	L2: l2-cache {
	compatible = "cache";
	cache-level = <2>;
	qcom,saw = <&saw_l2>;
	};

	idle-states {
	CPU_SPC: spc {
	compatible = "qcom,idle-state-spc",
	"arm,idle-state";
	entry-latency-us = <150>;
	exit-latency-us = <200>;
	min-residency-us = <2000>;
	};
	};
	};

	memory {
	device_type = "memory";
	reg = <0x0 0x0>;
	};

	thermal-zones {
	cpu-thermal0 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 5>;

	trips {
	cpu_alert0: trip0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu_crit0: trip1 {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu-thermal1 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 6>;

	trips {
	cpu_alert1: trip0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu_crit1: trip1 {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu-thermal2 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 7>;

	trips {
	cpu_alert2: trip0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu_crit2: trip1 {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu-thermal3 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 8>;

	trips {
	cpu_alert3: trip0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu_crit3: trip1 {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	q6-dsp-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 1>;

	trips {
	q6_dsp_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	modemtx-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 2>;

	trips {
	modemtx_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	video-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 3>;

	trips {
	video_alert0: trip-point0 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	wlan-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 4>;

	trips {
	wlan_alert0: trip-point0 {
	temperature = <105000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	gpu-thermal-top {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 9>;

	trips {
	gpu1_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	gpu-thermal-bottom {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 10>;

	trips {
	gpu2_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};
	};

	cpu-pmu {
	compatible = "qcom,krait-pmu";
	interrupts = <GIC_PPI 7 0xf04>;
	};

	clocks {
	xo_board: xo_board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <19200000>;
	};

	sleep_clk: sleep_clk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 2 0xf08>,
	<GIC_PPI 3 0xf08>,
	<GIC_PPI 4 0xf08>,
	<GIC_PPI 1 0xf08>;
	clock-frequency = <19200000>;
	};

	adsp-pil {
	compatible = "qcom,msm8974-adsp-pil";

	interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
	<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";

	cx-supply = <&pm8841_s2>;

	clocks = <&xo_board>;
	clock-names = "xo";

	memory-region = <&adsp_region>;

	qcom,smem-states = <&adsp_smp2p_out 0>;
	qcom,smem-state-names = "stop";

	smd-edge {
	interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;

	qcom,ipc = <&apcs 8 8>;
	qcom,smd-edge = <1>;

	label = "lpass";
	};
	};

	smem {
	compatible = "qcom,smem";

	memory-region = <&smem_region>;
	qcom,rpm-msg-ram = <&rpm_msg_ram>;

	hwlocks = <&tcsr_mutex 3>;
	};

	smp2p-adsp {
	compatible = "qcom,smp2p";
	qcom,smem = <443>, <429>;

	interrupt-parent = <&intc>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;

	qcom,ipc = <&apcs 8 10>;

	qcom,local-pid = <0>;
	qcom,remote-pid = <2>;

	adsp_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};

	adsp_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";

	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	smp2p-modem {
	compatible = "qcom,smp2p";
	qcom,smem = <435>, <428>;

	interrupt-parent = <&intc>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;

	qcom,ipc = <&apcs 8 14>;

	qcom,local-pid = <0>;
	qcom,remote-pid = <1>;

	modem_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};

	modem_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";

	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	smp2p-wcnss {
	compatible = "qcom,smp2p";
	qcom,smem = <451>, <431>;

	interrupt-parent = <&intc>;
	interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;

	qcom,ipc = <&apcs 8 18>;

	qcom,local-pid = <0>;
	qcom,remote-pid = <4>;

	wcnss_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";

	#qcom,smem-state-cells = <1>;
	};

	wcnss_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";

	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	smsm {
	compatible = "qcom,smsm";

	#address-cells = <1>;
	#size-cells = <0>;

	qcom,ipc-1 = <&apcs 8 13>;
	qcom,ipc-2 = <&apcs 8 9>;
	qcom,ipc-3 = <&apcs 8 19>;

	apps_smsm: apps@0 {
	reg = <0>;

	#qcom,smem-state-cells = <1>;
	};

	modem_smsm: modem@1 {
	reg = <1>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	adsp_smsm: adsp@2 {
	reg = <2>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	wcnss_smsm: wcnss@7 {
	reg = <7>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	firmware {
	scm {
	compatible = "qcom,scm";
	clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
	clock-names = "core", "bus", "iface";
	};
	};

	soc: soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "simple-bus";

	intc: interrupt-controller@f9000000 {
	compatible = "qcom,msm-qgic2";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0xf9000000 0x1000>,
	<0xf9002000 0x1000>;
	};

	apcs: syscon@f9011000 {
	compatible = "syscon";
	reg = <0xf9011000 0x1000>;
	};

	qfprom: qfprom@fc4bc000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "qcom,qfprom";
	reg = <0xfc4bc000 0x1000>;
	tsens_calib: calib@d0 {
	reg = <0xd0 0x18>;
	};
	tsens_backup: backup@440 {
	reg = <0x440 0x10>;
	};
	};

	tsens: thermal-sensor@fc4a9000 {
	compatible = "qcom,msm8974-tsens";
	reg = <0xfc4a9000 0x1000>, /* TM */
	<0xfc4a8000 0x1000>; /* SROT */
	nvmem-cells = <&tsens_calib>, <&tsens_backup>;
	nvmem-cell-names = "calib", "calib_backup";
	#qcom,sensors = <11>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "uplow";
	#thermal-sensor-cells = <1>;
	};

	timer@f9020000 {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "arm,armv7-timer-mem";
	reg = <0xf9020000 0x1000>;
	clock-frequency = <19200000>;

	frame@f9021000 {
	frame-number = <0>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9021000 0x1000>,
	<0xf9022000 0x1000>;
	};

	frame@f9023000 {
	frame-number = <1>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9023000 0x1000>;
	status = "disabled";
	};

	frame@f9024000 {
	frame-number = <2>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9024000 0x1000>;
	status = "disabled";
	};

	frame@f9025000 {
	frame-number = <3>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9025000 0x1000>;
	status = "disabled";
	};

	frame@f9026000 {
	frame-number = <4>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9026000 0x1000>;
	status = "disabled";
	};

	frame@f9027000 {
	frame-number = <5>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9027000 0x1000>;
	status = "disabled";
	};

	frame@f9028000 {
	frame-number = <6>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9028000 0x1000>;
	status = "disabled";
	};
	};

	saw0: power-controller@f9089000 {
	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
	};

	saw1: power-controller@f9099000 {
	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
	};

	saw2: power-controller@f90a9000 {
	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
	};

	saw3: power-controller@f90b9000 {
	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
	};

	saw_l2: power-controller@f9012000 {
	compatible = "qcom,saw2";
	reg = <0xf9012000 0x1000>;
	regulator;
	};

	acc0: clock-controller@f9088000 {
	compatible = "qcom,kpss-acc-v2";
	reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
	};

	acc1: clock-controller@f9098000 {
	compatible = "qcom,kpss-acc-v2";
	reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
	};

	acc2: clock-controller@f90a8000 {
	compatible = "qcom,kpss-acc-v2";
	reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
	};

	acc3: clock-controller@f90b8000 {
	compatible = "qcom,kpss-acc-v2";
	reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
	};

	restart@fc4ab000 {
	compatible = "qcom,pshold";
	reg = <0xfc4ab000 0x4>;
	};

	gcc: clock-controller@fc400000 {
	compatible = "qcom,gcc-msm8974";
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;
	reg = <0xfc400000 0x4000>;
	};

	tcsr: syscon@fd4a0000 {
	compatible = "syscon";
	reg = <0xfd4a0000 0x10000>;
	};

	tcsr_mutex_block: syscon@fd484000 {
	compatible = "syscon";
	reg = <0xfd484000 0x2000>;
	};

	mmcc: clock-controller@fd8c0000 {
	compatible = "qcom,mmcc-msm8974";
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;
	reg = <0xfd8c0000 0x6000>;
	};

	tcsr_mutex: tcsr-mutex {
	compatible = "qcom,tcsr-mutex";
	syscon = <&tcsr_mutex_block 0 0x80>;

	#hwlock-cells = <1>;
	};

	rpm_msg_ram: memory@fc428000 {
	compatible = "qcom,rpm-msg-ram";
	reg = <0xfc428000 0x4000>;
	};

	blsp1_uart1: serial@f991d000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0xf991d000 0x1000>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	blsp1_uart2: serial@f991e000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0xf991e000 0x1000>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	+ blsp2_uart10: serial@f9960000 {
	+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	+ reg = <0xf9960000 0x1000>;
	+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
	+ clock-names = "core", "iface";
	+ status = "disabled";
	+ };
	+
	sdhci@f9824900 {
	compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
	reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
	reg-names = "hc_mem", "core_mem";
	interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hc_irq", "pwr_irq";
	clocks = <&gcc GCC_SDCC1_APPS_CLK>,
	<&gcc GCC_SDCC1_AHB_CLK>,
	<&xo_board>;
	clock-names = "core", "iface", "xo";
	status = "disabled";
	};

	sdhci@f9864900 {
	compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
	reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
	reg-names = "hc_mem", "core_mem";
	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hc_irq", "pwr_irq";
	clocks = <&gcc GCC_SDCC3_APPS_CLK>,
	<&gcc GCC_SDCC3_AHB_CLK>,
	<&xo_board>;
	clock-names = "core", "iface", "xo";
	status = "disabled";
	};

	sdhci@f98a4900 {
	compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
	reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
	reg-names = "hc_mem", "core_mem";
	interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hc_irq", "pwr_irq";
	clocks = <&gcc GCC_SDCC2_APPS_CLK>,
	<&gcc GCC_SDCC2_AHB_CLK>,
	<&xo_board>;
	clock-names = "core", "iface", "xo";
	status = "disabled";
	};

	otg: usb@f9a55000 {
	compatible = "qcom,ci-hdrc";
	reg = <0xf9a55000 0x200>,
	<0xf9a55200 0x200>;
	interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_USB_HS_AHB_CLK>,
	<&gcc GCC_USB_HS_SYSTEM_CLK>;
	clock-names = "iface", "core";
	assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
	assigned-clock-rates = <75000000>;
	resets = <&gcc GCC_USB_HS_BCR>;
	reset-names = "core";
	phy_type = "ulpi";
	dr_mode = "otg";
	ahb-burst-config = <0>;
	phy-names = "usb-phy";
	status = "disabled";
	#reset-cells = <1>;

	ulpi {
	usb_hs1_phy: phy@a {
	compatible = "qcom,usb-hs-phy-msm8974",
	"qcom,usb-hs-phy";
	#phy-cells = <0>;
	clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
	clock-names = "ref", "sleep";
	resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
	reset-names = "phy", "por";
	status = "disabled";
	};

	usb_hs2_phy: phy@b {
	compatible = "qcom,usb-hs-phy-msm8974",
	"qcom,usb-hs-phy";
	#phy-cells = <0>;
	clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
	clock-names = "ref", "sleep";
	resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
	reset-names = "phy", "por";
	status = "disabled";
	};
	};
	};

	rng@f9bff000 {
	compatible = "qcom,prng";
	reg = <0xf9bff000 0x200>;
	clocks = <&gcc GCC_PRNG_AHB_CLK>;
	clock-names = "core";
	};

	remoteproc@fc880000 {
	compatible = "qcom,msm8974-mss-pil";
	reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
	reg-names = "qdsp6", "rmb";

	interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
	<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";

	clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
	<&gcc GCC_MSS_CFG_AHB_CLK>,
	<&gcc GCC_BOOT_ROM_AHB_CLK>,
	<&xo_board>;
	clock-names = "iface", "bus", "mem", "xo";

	resets = <&gcc GCC_MSS_RESTART>;
	reset-names = "mss_restart";

	cx-supply = <&pm8841_s2>;
	mss-supply = <&pm8841_s3>;
	mx-supply = <&pm8841_s1>;
	pll-supply = <&pm8941_l12>;

	qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;

	qcom,smem-states = <&modem_smp2p_out 0>;
	qcom,smem-state-names = "stop";

	mba {
	memory-region = <&mba_region>;
	};

	mpss {
	memory-region = <&mpss_region>;
	};

	smd-edge {
	interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;

	qcom,ipc = <&apcs 8 12>;
	qcom,smd-edge = <0>;

	label = "modem";
	};
	};

	pronto: remoteproc@fb21b000 {
	compatible = "qcom,pronto-v2-pil", "qcom,pronto";
	reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
	reg-names = "ccu", "dxe", "pmu";

	memory-region = <&wcnss_region>;

	interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
	<&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	<&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	<&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	<&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";

	vddpx-supply = <&pm8941_s3>;

	qcom,smem-states = <&wcnss_smp2p_out 0>;
	qcom,smem-state-names = "stop";

	status = "disabled";

	iris {
	compatible = "qcom,wcn3680";

	clocks = <&rpmcc RPM_SMD_CXO_A2>;
	clock-names = "xo";

	vddxo-supply = <&pm8941_l6>;
	vddrfa-supply = <&pm8941_l11>;
	vddpa-supply = <&pm8941_l19>;
	vdddig-supply = <&pm8941_s3>;
	};

	smd-edge {
	interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;

	qcom,ipc = <&apcs 8 17>;
	qcom,smd-edge = <6>;

	wcnss {
	compatible = "qcom,wcnss";
	qcom,smd-channels = "WCNSS_CTRL";
	status = "disabled";

	qcom,mmio = <&pronto>;

	bt {
	compatible = "qcom,wcnss-bt";
	};

	wifi {
	compatible = "qcom,wcnss-wlan";

	interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "tx", "rx";

	qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
	qcom,smem-state-names = "tx-enable", "tx-rings-empty";
	};
	};
	};
	};

	msmgpio: pinctrl@fd510000 {
	compatible = "qcom,msm8974-pinctrl";
	reg = <0xfd510000 0x4000>;
	gpio-controller;
	+ gpio-ranges = <&msmgpio 0 0 146>;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	};

	i2c@f9923000 {
	status = "disabled";
	compatible = "qcom,i2c-qup-v2.1.1";
	reg = <0xf9923000 0x1000>;
	interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c@f9924000 {
	status = "disabled";
	compatible = "qcom,i2c-qup-v2.1.1";
	reg = <0xf9924000 0x1000>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	blsp_i2c3: i2c@f9925000 {
	status = "disabled";
	compatible = "qcom,i2c-qup-v2.1.1";
	reg = <0xf9925000 0x1000>;
	interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	blsp_i2c8: i2c@f9964000 {
	status = "disabled";
	compatible = "qcom,i2c-qup-v2.1.1";
	reg = <0xf9964000 0x1000>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
	clock-names = "core", "iface";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	blsp_i2c11: i2c@f9967000 {
	status = "disabled";
	compatible = "qcom,i2c-qup-v2.1.1";
	reg = <0xf9967000 0x1000>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
	clock-names = "core", "iface";
	#address-cells = <1>;
	#size-cells = <0>;
	dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
	dma-names = "tx", "rx";
	};

	blsp_i2c12: i2c@f9968000 {
	status = "disabled";
	compatible = "qcom,i2c-qup-v2.1.1";
	reg = <0xf9968000 0x1000>;
	interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
	clock-names = "core", "iface";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	spmi_bus: spmi@fc4cf000 {
	compatible = "qcom,spmi-pmic-arb";
	reg-names = "core", "intr", "cnfg";
	reg = <0xfc4cf000 0x1000>,
	<0xfc4cb000 0x1000>,
	<0xfc4ca000 0x1000>;
	interrupt-names = "periph_irq";
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	qcom,ee = <0>;
	qcom,channel = <0>;
	#address-cells = <2>;
	#size-cells = <0>;
	interrupt-controller;
	#interrupt-cells = <4>;
	};

	blsp2_dma: dma-controller@f9944000 {
	compatible = "qcom,bam-v1.4.0";
	reg = <0xf9944000 0x19000>;
	interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP2_AHB_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	};

	etr@fc322000 {
	compatible = "arm,coresight-tmc", "arm,primecell";
	reg = <0xfc322000 0x1000>;

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	port {
	etr_in: endpoint {
	remote-endpoint = <&replicator_out0>;
	};
	};
	};
	};

	tpiu@fc318000 {
	compatible = "arm,coresight-tpiu", "arm,primecell";
	reg = <0xfc318000 0x1000>;

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	port {
	tpiu_in: endpoint {
	remote-endpoint = <&replicator_out1>;
	};
	};
	};
	};

	replicator@fc31c000 {
	compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
	reg = <0xfc31c000 0x1000>;

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	out-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	replicator_out0: endpoint {
	remote-endpoint = <&etr_in>;
	};
	};
	port@1 {
	reg = <1>;
	replicator_out1: endpoint {
	remote-endpoint = <&tpiu_in>;
	};
	};
	};

	in-ports {
	port {
	replicator_in: endpoint {
	remote-endpoint = <&etf_out>;
	};
	};
	};
	};

	etf@fc307000 {
	compatible = "arm,coresight-tmc", "arm,primecell";
	reg = <0xfc307000 0x1000>;

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	out-ports {
	port {
	etf_out: endpoint {
	remote-endpoint = <&replicator_in>;
	};
	};
	};

	in-ports {
	port {
	etf_in: endpoint {
	remote-endpoint = <&merger_out>;
	};
	};
	};
	};

	funnel@fc31b000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0xfc31b000 0x1000>;

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	/*
	* Not described input ports:
	* 0 - connected trought funnel to Audio, Modem and
	* Resource and Power Manager CPU's
	* 2...7 - not-connected
	*/
	port@1 {
	reg = <1>;
	merger_in1: endpoint {
	remote-endpoint = <&funnel1_out>;
	};
	};
	};

	out-ports {
	port {
	merger_out: endpoint {
	remote-endpoint = <&etf_in>;
	};
	};
	};
	};

	funnel@fc31a000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0xfc31a000 0x1000>;

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	/*
	* Not described input ports:
	* 0 - not-connected
	* 1 - connected trought funnel to Multimedia CPU
	* 2 - connected to Wireless CPU
	* 3 - not-connected
	* 4 - not-connected
	* 6 - not-connected
	* 7 - connected to STM
	*/
	port@5 {
	reg = <5>;
	funnel1_in5: endpoint {
	remote-endpoint = <&kpss_out>;
	};
	};
	};

	out-ports {
	port {
	funnel1_out: endpoint {
	remote-endpoint = <&merger_in1>;
	};
	};
	};
	};

	funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0xfc345000 0x1000>;

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	kpss_in0: endpoint {
	remote-endpoint = <&etm0_out>;
	};
	};
	port@1 {
	reg = <1>;
	kpss_in1: endpoint {
	remote-endpoint = <&etm1_out>;
	};
	};
	port@2 {
	reg = <2>;
	kpss_in2: endpoint {
	remote-endpoint = <&etm2_out>;
	};
	};
	port@3 {
	reg = <3>;
	kpss_in3: endpoint {
	remote-endpoint = <&etm3_out>;
	};
	};
	};

	out-ports {
	port {
	kpss_out: endpoint {
	remote-endpoint = <&funnel1_in5>;
	};
	};
	};
	};

	etm@fc33c000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0xfc33c000 0x1000>;

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	cpu = <&CPU0>;

	out-ports {
	port {
	etm0_out: endpoint {
	remote-endpoint = <&kpss_in0>;
	};
	};
	};
	};

	etm@fc33d000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0xfc33d000 0x1000>;

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	cpu = <&CPU1>;

	out-ports {
	port {
	etm1_out: endpoint {
	remote-endpoint = <&kpss_in1>;
	};
	};
	};
	};

	etm@fc33e000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0xfc33e000 0x1000>;

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	cpu = <&CPU2>;

	out-ports {
	port {
	etm2_out: endpoint {
	remote-endpoint = <&kpss_in2>;
	};
	};
	};
	};

	etm@fc33f000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0xfc33f000 0x1000>;

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	cpu = <&CPU3>;

	out-ports {
	port {
	etm3_out: endpoint {
	remote-endpoint = <&kpss_in3>;
	};
	};
	};
	};

	ocmem@fdd00000 {
	compatible = "qcom,msm8974-ocmem";
	reg = <0xfdd00000 0x2000>,
	<0xfec00000 0x180000>;
	reg-names = "ctrl",
	"mem";
	clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
	<&mmcc OCMEMCX_OCMEMNOC_CLK>;
	clock-names = "core",
	"iface";

	#address-cells = <1>;
	#size-cells = <1>;

	gmu_sram: gmu-sram@0 {
	reg = <0x0 0x100000>;
	};
	};

	bimc: interconnect@fc380000 {
	reg = <0xfc380000 0x6a000>;
	compatible = "qcom,msm8974-bimc";
	#interconnect-cells = <1>;
	clock-names = "bus", "bus_a";
	clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
	<&rpmcc RPM_SMD_BIMC_A_CLK>;
	};

	snoc: interconnect@fc460000 {
	reg = <0xfc460000 0x4000>;
	compatible = "qcom,msm8974-snoc";
	#interconnect-cells = <1>;
	clock-names = "bus", "bus_a";
	clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
	<&rpmcc RPM_SMD_SNOC_A_CLK>;
	};

	pnoc: interconnect@fc468000 {
	reg = <0xfc468000 0x4000>;
	compatible = "qcom,msm8974-pnoc";
	#interconnect-cells = <1>;
	clock-names = "bus", "bus_a";
	clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
	<&rpmcc RPM_SMD_PNOC_A_CLK>;
	};

	ocmemnoc: interconnect@fc470000 {
	reg = <0xfc470000 0x4000>;
	compatible = "qcom,msm8974-ocmemnoc";
	#interconnect-cells = <1>;
	clock-names = "bus", "bus_a";
	clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
	<&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
	};

	mmssnoc: interconnect@fc478000 {
	reg = <0xfc478000 0x4000>;
	compatible = "qcom,msm8974-mmssnoc";
	#interconnect-cells = <1>;
	clock-names = "bus", "bus_a";
	clocks = <&mmcc MMSS_S0_AXI_CLK>,
	<&mmcc MMSS_S0_AXI_CLK>;
	};

	cnoc: interconnect@fc480000 {
	reg = <0xfc480000 0x4000>;
	compatible = "qcom,msm8974-cnoc";
	#interconnect-cells = <1>;
	clock-names = "bus", "bus_a";
	clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
	<&rpmcc RPM_SMD_CNOC_A_CLK>;
	};

	mdss: mdss@fd900000 {
	status = "disabled";

	compatible = "qcom,mdss";
	reg = <0xfd900000 0x100>,
	<0xfd924000 0x1000>;
	reg-names = "mdss_phys",
	"vbif_phys";

	power-domains = <&mmcc MDSS_GDSC>;

	clocks = <&mmcc MDSS_AHB_CLK>,
	<&mmcc MDSS_AXI_CLK>,
	<&mmcc MDSS_VSYNC_CLK>;
	clock-names = "iface",
	"bus",
	"vsync";

	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;

	interrupt-controller;
	#interrupt-cells = <1>;

	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	mdp: mdp@fd900000 {
	status = "disabled";

	compatible = "qcom,mdp5";
	reg = <0xfd900100 0x22000>;
	reg-names = "mdp_phys";

	interrupt-parent = <&mdss>;
	interrupts = <0 0>;

	clocks = <&mmcc MDSS_AHB_CLK>,
	<&mmcc MDSS_AXI_CLK>,
	<&mmcc MDSS_MDP_CLK>,
	<&mmcc MDSS_VSYNC_CLK>;
	clock-names = "iface",
	"bus",
	"core",
	"vsync";

	interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
	interconnect-names = "mdp0-mem";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	mdp5_intf1_out: endpoint {
	remote-endpoint = <&dsi0_in>;
	};
	};
	};
	};

	dsi0: dsi@fd922800 {
	status = "disabled";

	compatible = "qcom,mdss-dsi-ctrl";
	reg = <0xfd922800 0x1f8>;
	reg-names = "dsi_ctrl";

	interrupt-parent = <&mdss>;
	interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;

	assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
	<&mmcc PCLK0_CLK_SRC>;
	assigned-clock-parents = <&dsi_phy0 0>,
	<&dsi_phy0 1>;

	clocks = <&mmcc MDSS_MDP_CLK>,
	<&mmcc MDSS_AHB_CLK>,
	<&mmcc MDSS_AXI_CLK>,
	<&mmcc MDSS_BYTE0_CLK>,
	<&mmcc MDSS_PCLK0_CLK>,
	<&mmcc MDSS_ESC0_CLK>,
	<&mmcc MMSS_MISC_AHB_CLK>;
	clock-names = "mdp_core",
	"iface",
	"bus",
	"byte",
	"pixel",
	"core",
	"core_mmss";

	phys = <&dsi_phy0>;
	phy-names = "dsi-phy";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	dsi0_in: endpoint {
	remote-endpoint = <&mdp5_intf1_out>;
	};
	};

	port@1 {
	reg = <1>;
	dsi0_out: endpoint {
	};
	};
	};
	};

	dsi_phy0: dsi-phy@fd922a00 {
	status = "disabled";

	compatible = "qcom,dsi-phy-28nm-hpm";
	reg = <0xfd922a00 0xd4>,
	<0xfd922b00 0x280>,
	<0xfd922d80 0x30>;
	reg-names = "dsi_pll",
	"dsi_phy",
	"dsi_phy_regulator";

	#clock-cells = <1>;
	#phy-cells = <0>;
	qcom,dsi-phy-index = <0>;

	clocks = <&mmcc MDSS_AHB_CLK>;
	clock-names = "iface";
	};
	};

	imem@fe805000 {
	status = "disabled";
	compatible = "syscon", "simple-mfd";
	reg = <0xfe805000 0x1000>;

	reboot-mode {
	compatible = "syscon-reboot-mode";
	offset = <0x65c>;
	};
	};
	};

	smd {
	compatible = "qcom,smd";

	rpm {
	interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
	qcom,ipc = <&apcs 8 0>;
	qcom,smd-edge = <15>;

	rpm_requests {
	compatible = "qcom,rpm-msm8974";
	qcom,smd-channels = "rpm_requests";

	rpmcc: clock-controller {
	compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
	#clock-cells = <1>;
	};

	pm8841-regulators {
	compatible = "qcom,rpm-pm8841-regulators";

	pm8841_s1: s1 {};
	pm8841_s2: s2 {};
	pm8841_s3: s3 {};
	pm8841_s4: s4 {};
	pm8841_s5: s5 {};
	pm8841_s6: s6 {};
	pm8841_s7: s7 {};
	pm8841_s8: s8 {};
	};

	pm8941-regulators {
	compatible = "qcom,rpm-pm8941-regulators";

	pm8941_s1: s1 {};
	pm8941_s2: s2 {};
	pm8941_s3: s3 {};

	pm8941_l1: l1 {};
	pm8941_l2: l2 {};
	pm8941_l3: l3 {};
	pm8941_l4: l4 {};
	pm8941_l5: l5 {};
	pm8941_l6: l6 {};
	pm8941_l7: l7 {};
	pm8941_l8: l8 {};
	pm8941_l9: l9 {};
	pm8941_l10: l10 {};
	pm8941_l11: l11 {};
	pm8941_l12: l12 {};
	pm8941_l13: l13 {};
	pm8941_l14: l14 {};
	pm8941_l15: l15 {};
	pm8941_l16: l16 {};
	pm8941_l17: l17 {};
	pm8941_l18: l18 {};
	pm8941_l19: l19 {};
	pm8941_l20: l20 {};
	pm8941_l21: l21 {};
	pm8941_l22: l22 {};
	pm8941_l23: l23 {};
	pm8941_l24: l24 {};

	pm8941_lvs1: lvs1 {};
	pm8941_lvs2: lvs2 {};
	pm8941_lvs3: lvs3 {};
	};
	};
	};
	};

	vreg_boost: vreg-boost {
	compatible = "regulator-fixed";

	regulator-name = "vreg-boost";
	regulator-min-microvolt = <3150000>;
	regulator-max-microvolt = <3150000>;

	regulator-always-on;
	regulator-boot-on;

	gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
	enable-active-high;

	pinctrl-names = "default";
	pinctrl-0 = <&boost_bypass_n_pin>;
	};
	vreg_vph_pwr: vreg-vph-pwr {
	compatible = "regulator-fixed";
	regulator-name = "vph-pwr";

	regulator-min-microvolt = <3600000>;
	regulator-max-microvolt = <3600000>;

	regulator-always-on;
	};
	};
	diff --git a/sys/gnu/dts/arm/r7s72100-gr-peach.dts b/sys/gnu/dts/arm/r7s72100-gr-peach.dts
	index fe1a4aa4d7cb..2562cc9b5356 100644
	--- a/sys/gnu/dts/arm/r7s72100-gr-peach.dts
	+++ b/sys/gnu/dts/arm/r7s72100-gr-peach.dts
	@@ -1,134 +1,137 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the GR-Peach board
	*
	* Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
	* Copyright (C) 2016 Renesas Electronics
	*/

	/dts-v1/;
	#include "r7s72100.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>

	/ {
	model = "GR-Peach";
	compatible = "renesas,gr-peach", "renesas,r7s72100";

	aliases {
	serial0 = &scif2;
	};

	chosen {
	bootargs = "ignore_loglevel rw root=/dev/mtdblock0";
	stdout-path = "serial0:115200n8";
	};

	memory@20000000 {
	device_type = "memory";
	reg = <0x20000000 0x00a00000>;
	};

	lbsc {
	#address-cells = <1>;
	#size-cells = <1>;
	};

	flash@18000000 {
	compatible = "mtd-rom";
	probe-type = "map_rom";
	reg = <0x18000000 0x00800000>;
	bank-width = <4>;
	device-width = <1>;

	+ clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>;
	+ power-domains = <&cpg_clocks>;
	+
	#address-cells = <1>;
	#size-cells = <1>;

	rootfs@600000 {
	label = "rootfs";
	reg = <0x00600000 0x00200000>;
	};
	};

	leds {
	status = "okay";
	compatible = "gpio-leds";

	led1 {
	gpios = <&port6 12 GPIO_ACTIVE_HIGH>;
	};
	};
	};

	&pinctrl {
	scif2_pins: serial2 {
	/* P6_2 as RxD2; P6_3 as TxD2 */
	pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
	};

	ether_pins: ether {
	/* Ethernet on Ports 1,3,5,10 */
	pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */
	<RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */
	<RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
	<RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
	<RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */
	<RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */
	<RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */
	<RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */
	<RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */
	<RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */
	<RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */
	<RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */
	<RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */
	<RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */
	<RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */
	<RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */
	<RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
	<RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
	};
	};

	&extal_clk {
	clock-frequency = <13333000>;
	};

	&usb_x1_clk {
	clock-frequency = <48000000>;
	};

	&mtu2 {
	status = "okay";
	};

	&ostm0 {
	status = "okay";
	};

	&ostm1 {
	status = "okay";
	};

	&scif2 {
	pinctrl-names = "default";
	pinctrl-0 = <&scif2_pins>;

	status = "okay";
	};

	&ether {
	pinctrl-names = "default";
	pinctrl-0 = <&ether_pins>;

	status = "okay";

	renesas,no-ether-link;
	phy-handle = <&phy0>;

	phy0: ethernet-phy@0 {
	reg = <0>;

	reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
	reset-delay-us = <5>;
	};
	};
	diff --git a/sys/gnu/dts/arm/r7s72100.dtsi b/sys/gnu/dts/arm/r7s72100.dtsi
	index 75b2796ebfca..0a567d8ebc66 100644
	--- a/sys/gnu/dts/arm/r7s72100.dtsi
	+++ b/sys/gnu/dts/arm/r7s72100.dtsi
	@@ -1,724 +1,725 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the r7s72100 SoC
	*
	* Copyright (C) 2013-14 Renesas Solutions Corp.
	* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
	*/

	#include <dt-bindings/clock/r7s72100-clock.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/interrupt-controller/irq.h>

	/ {
	compatible = "renesas,r7s72100";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	spi0 = &spi0;
	spi1 = &spi1;
	spi2 = &spi2;
	spi3 = &spi3;
	spi4 = &spi4;
	};

	/* Fixed factor clocks */
	b_clk: b {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clocks = <&cpg_clocks R7S72100_CLK_PLL>;
	clock-mult = <1>;
	clock-div = <3>;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <0>;
	clock-frequency = <400000000>;
	clocks = <&cpg_clocks R7S72100_CLK_I>;
	next-level-cache = <&L2>;
	};
	};

	/* External clocks */
	extal_clk: extal {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	/* If clk present, value must be set by board */
	clock-frequency = <0>;
	};

	p0_clk: p0 {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clocks = <&cpg_clocks R7S72100_CLK_PLL>;
	clock-mult = <1>;
	clock-div = <12>;
	};

	p1_clk: p1 {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clocks = <&cpg_clocks R7S72100_CLK_PLL>;
	clock-mult = <1>;
	clock-div = <6>;
	};

	pmu {
	compatible = "arm,cortex-a9-pmu";
	interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
	};

	rtc_x1_clk: rtc_x1 {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	/* If clk present, value must be set by board to 32678 */
	clock-frequency = <0>;
	};

	rtc_x3_clk: rtc_x3 {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	/* If clk present, value must be set by board to 4000000 */
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;

	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	L2: cache-controller@3ffff000 {
	compatible = "arm,pl310-cache";
	reg = <0x3ffff000 0x1000>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	arm,early-bresp-disable;
	arm,full-line-zero-disable;
	cache-unified;
	cache-level = <2>;
	};

	scif0: serial@e8007000 {
	compatible = "renesas,scif-r7s72100", "renesas,scif";
	reg = <0xe8007000 64>;
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
	clock-names = "fck";
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	scif1: serial@e8007800 {
	compatible = "renesas,scif-r7s72100", "renesas,scif";
	reg = <0xe8007800 64>;
	interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
	clock-names = "fck";
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	scif2: serial@e8008000 {
	compatible = "renesas,scif-r7s72100", "renesas,scif";
	reg = <0xe8008000 64>;
	interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
	clock-names = "fck";
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	scif3: serial@e8008800 {
	compatible = "renesas,scif-r7s72100", "renesas,scif";
	reg = <0xe8008800 64>;
	interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
	clock-names = "fck";
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	scif4: serial@e8009000 {
	compatible = "renesas,scif-r7s72100", "renesas,scif";
	reg = <0xe8009000 64>;
	interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
	clock-names = "fck";
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	scif5: serial@e8009800 {
	compatible = "renesas,scif-r7s72100", "renesas,scif";
	reg = <0xe8009800 64>;
	interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
	clock-names = "fck";
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	scif6: serial@e800a000 {
	compatible = "renesas,scif-r7s72100", "renesas,scif";
	reg = <0xe800a000 64>;
	interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
	clock-names = "fck";
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	scif7: serial@e800a800 {
	compatible = "renesas,scif-r7s72100", "renesas,scif";
	reg = <0xe800a800 64>;
	interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
	clock-names = "fck";
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	spi0: spi@e800c800 {
	compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
	reg = <0xe800c800 0x24>;
	interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error", "rx", "tx";
	clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
	power-domains = <&cpg_clocks>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi1: spi@e800d000 {
	compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
	reg = <0xe800d000 0x24>;
	interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error", "rx", "tx";
	clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
	power-domains = <&cpg_clocks>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi2: spi@e800d800 {
	compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
	reg = <0xe800d800 0x24>;
	interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error", "rx", "tx";
	clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
	power-domains = <&cpg_clocks>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi3: spi@e800e000 {
	compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
	reg = <0xe800e000 0x24>;
	interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error", "rx", "tx";
	clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
	power-domains = <&cpg_clocks>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi4: spi@e800e800 {
	compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
	reg = <0xe800e800 0x24>;
	interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error", "rx", "tx";
	clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
	power-domains = <&cpg_clocks>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	usbhs0: usb@e8010000 {
	compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
	reg = <0xe8010000 0x1a0>;
	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp7_clks R7S72100_CLK_USB0>;
	renesas,buswait = <4>;
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	usbhs1: usb@e8207000 {
	compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
	reg = <0xe8207000 0x1a0>;
	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp7_clks R7S72100_CLK_USB1>;
	renesas,buswait = <4>;
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	mmcif: mmc@e804c800 {
	compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
	reg = <0xe804c800 0x80>;
	interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
	power-domains = <&cpg_clocks>;
	reg-io-width = <4>;
	bus-width = <8>;
	status = "disabled";
	};

	sdhi0: sd@e804e000 {
	compatible = "renesas,sdhi-r7s72100";
	reg = <0xe804e000 0x100>;
	interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
	<&mstp12_clks R7S72100_CLK_SDHI01>;
	clock-names = "core", "cd";
	power-domains = <&cpg_clocks>;
	cap-sd-highspeed;
	cap-sdio-irq;
	status = "disabled";
	};

	sdhi1: sd@e804e800 {
	compatible = "renesas,sdhi-r7s72100";
	reg = <0xe804e800 0x100>;
	interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
	<&mstp12_clks R7S72100_CLK_SDHI11>;
	clock-names = "core", "cd";
	power-domains = <&cpg_clocks>;
	cap-sd-highspeed;
	cap-sdio-irq;
	status = "disabled";
	};

	gic: interrupt-controller@e8201000 {
	compatible = "arm,pl390";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0xe8201000 0x1000>,
	<0xe8202000 0x1000>;
	};

	ether: ethernet@e8203000 {
	compatible = "renesas,ether-r7s72100";
	reg = <0xe8203000 0x800>,
	<0xe8204800 0x200>;
	interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
	power-domains = <&cpg_clocks>;
	phy-mode = "mii";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	ceu: camera@e8210000 {
	reg = <0xe8210000 0x3000>;
	compatible = "renesas,r7s72100-ceu";
	interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp6_clks R7S72100_CLK_CEU>;
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	wdt: watchdog@fcfe0000 {
	compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
	reg = <0xfcfe0000 0x6>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&p0_clk>;
	};

	/* Special CPG clocks */
	cpg_clocks: cpg_clocks@fcfe0000 {
	#clock-cells = <1>;
	compatible = "renesas,r7s72100-cpg-clocks",
	"renesas,rz-cpg-clocks";
	reg = <0xfcfe0000 0x18>;
	clocks = <&extal_clk>, <&usb_x1_clk>;
	clock-output-names = "pll", "i", "g";
	#power-domain-cells = <0>;
	};

	/* MSTP clocks */
	mstp3_clks: mstp3_clks@fcfe0420 {
	#clock-cells = <1>;
	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0xfcfe0420 4>;
	clocks = <&p0_clk>;
	clock-indices = <R7S72100_CLK_MTU2>;
	clock-output-names = "mtu2";
	};

	mstp4_clks: mstp4_clks@fcfe0424 {
	#clock-cells = <1>;
	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0xfcfe0424 4>;
	clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
	<&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
	clock-indices = <
	R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
	R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
	>;
	clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
	};

	mstp5_clks: mstp5_clks@fcfe0428 {
	#clock-cells = <1>;
	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0xfcfe0428 4>;
	clocks = <&p0_clk>, <&p0_clk>;
	clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
	clock-output-names = "ostm0", "ostm1";
	};

	mstp6_clks: mstp6_clks@fcfe042c {
	#clock-cells = <1>;
	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0xfcfe042c 4>;
	clocks = <&b_clk>, <&p0_clk>;
	clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>;
	clock-output-names = "ceu", "rtc";
	};

	mstp7_clks: mstp7_clks@fcfe0430 {
	#clock-cells = <1>;
	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0xfcfe0430 4>;
	clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
	clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
	clock-output-names = "ether", "usb0", "usb1";
	};

	mstp8_clks: mstp8_clks@fcfe0434 {
	#clock-cells = <1>;
	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0xfcfe0434 4>;
	clocks = <&p1_clk>;
	clock-indices = <R7S72100_CLK_MMCIF>;
	clock-output-names = "mmcif";
	};

	mstp9_clks: mstp9_clks@fcfe0438 {
	#clock-cells = <1>;
	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0xfcfe0438 4>;
	- clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
	+ clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>;
	clock-indices = <
	R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
	+ R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1
	>;
	- clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
	+ clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1";
	};

	mstp10_clks: mstp10_clks@fcfe043c {
	#clock-cells = <1>;
	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0xfcfe043c 4>;
	clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
	<&p1_clk>;
	clock-indices = <
	R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
	R7S72100_CLK_SPI4
	>;
	clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
	};
	mstp12_clks: mstp12_clks@fcfe0444 {
	#clock-cells = <1>;
	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0xfcfe0444 4>;
	clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
	clock-indices = <
	R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
	R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
	>;
	clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
	};

	pinctrl: pin-controller@fcfe3000 {
	compatible = "renesas,r7s72100-ports";

	reg = <0xfcfe3000 0x4230>;

	port0: gpio-0 {
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 0 6>;
	};

	port1: gpio-1 {
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 16 16>;
	};

	port2: gpio-2 {
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 32 16>;
	};

	port3: gpio-3 {
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 48 16>;
	};

	port4: gpio-4 {
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 64 16>;
	};

	port5: gpio-5 {
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 80 11>;
	};

	port6: gpio-6 {
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 96 16>;
	};

	port7: gpio-7 {
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 112 16>;
	};

	port8: gpio-8 {
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 128 16>;
	};

	port9: gpio-9 {
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 144 8>;
	};

	port10: gpio-10 {
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 160 16>;
	};

	port11: gpio-11 {
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 176 16>;
	};
	};

	ostm0: timer@fcfec000 {
	compatible = "renesas,r7s72100-ostm", "renesas,ostm";
	reg = <0xfcfec000 0x30>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
	clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	ostm1: timer@fcfec400 {
	compatible = "renesas,r7s72100-ostm", "renesas,ostm";
	reg = <0xfcfec400 0x30>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
	clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	i2c0: i2c@fcfee000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
	reg = <0xfcfee000 0x44>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
	clock-frequency = <100000>;
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	i2c1: i2c@fcfee400 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
	reg = <0xfcfee400 0x44>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
	clock-frequency = <100000>;
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	i2c2: i2c@fcfee800 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
	reg = <0xfcfee800 0x44>;
	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
	clock-frequency = <100000>;
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	i2c3: i2c@fcfeec00 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
	reg = <0xfcfeec00 0x44>;
	interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
	clock-frequency = <100000>;
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	irqc: interrupt-controller@fcfef800 {
	compatible = "renesas,r7s72100-irqc",
	"renesas,rza1-irqc";
	#interrupt-cells = <2>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0xfcfef800 0x6>;
	interrupt-map =
	<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-map-mask = <7 0>;
	};

	mtu2: timer@fcff0000 {
	compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
	reg = <0xfcff0000 0x400>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "tgi0a";
	clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
	clock-names = "fck";
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};

	rtc: rtc@fcff1000 {
	compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
	reg = <0xfcff1000 0x2e>;
	interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "alarm", "period", "carry";
	clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
	<&rtc_x3_clk>, <&extal_clk>;
	clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
	power-domains = <&cpg_clocks>;
	status = "disabled";
	};
	};

	usb_x1_clk: usb_x1 {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	/* If clk present, value must be set by board */
	clock-frequency = <0>;
	};
	};
	diff --git a/sys/gnu/dts/arm/r7s9210.dtsi b/sys/gnu/dts/arm/r7s9210.dtsi
	index 72b79770e336..cace43807497 100644
	--- a/sys/gnu/dts/arm/r7s9210.dtsi
	+++ b/sys/gnu/dts/arm/r7s9210.dtsi
	@@ -1,504 +1,501 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the R7S9210 SoC
	*
	* Copyright (C) 2018 Renesas Electronics Corporation
	*
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/r7s9210-cpg-mssr.h>

	/ {
	compatible = "renesas,r7s9210";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	/* External clocks */
	extal_clk: extal {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	/* Value must be set by board */
	clock-frequency = <0>;
	};

	rtc_x1_clk: rtc_x1 {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	/* If clk present, value (32678) must be set by board */
	clock-frequency = <0>;
	};

	usb_x1_clk: usb_x1 {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	/* If clk present, value (48000000) must be set by board */
	clock-frequency = <0>;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <0>;
	clock-frequency = <528000000>;
	next-level-cache = <&L2>;
	};
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;

	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	L2: cache-controller@1f003000 {
	compatible = "arm,pl310-cache";
	reg = <0x1f003000 0x1000>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	arm,early-bresp-disable;
	arm,full-line-zero-disable;
	cache-unified;
	cache-level = <2>;
	};

	scif0: serial@e8007000 {
	compatible = "renesas,scif-r7s9210";
	reg = <0xe8007000 0x18>;
	interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "eri", "rxi", "txi",
	"bri", "dri", "tei";
	clocks = <&cpg CPG_MOD 47>;
	clock-names = "fck";
	power-domains = <&cpg>;
	status = "disabled";
	};

	scif1: serial@e8007800 {
	compatible = "renesas,scif-r7s9210";
	reg = <0xe8007800 0x18>;
	interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "eri", "rxi", "txi",
	"bri", "dri", "tei";
	clocks = <&cpg CPG_MOD 46>;
	clock-names = "fck";
	power-domains = <&cpg>;
	status = "disabled";
	};

	scif2: serial@e8008000 {
	compatible = "renesas,scif-r7s9210";
	reg = <0xe8008000 0x18>;
	interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "eri", "rxi", "txi",
	"bri", "dri", "tei";
	clocks = <&cpg CPG_MOD 45>;
	clock-names = "fck";
	power-domains = <&cpg>;
	status = "disabled";
	};

	scif3: serial@e8008800 {
	compatible = "renesas,scif-r7s9210";
	reg = <0xe8008800 0x18>;
	interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "eri", "rxi", "txi",
	"bri", "dri", "tei";
	clocks = <&cpg CPG_MOD 44>;
	clock-names = "fck";
	power-domains = <&cpg>;
	status = "disabled";
	};

	scif4: serial@e8009000 {
	compatible = "renesas,scif-r7s9210";
	reg = <0xe8009000 0x18>;
	interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "eri", "rxi", "txi",
	"bri", "dri", "tei";
	clocks = <&cpg CPG_MOD 43>;
	clock-names = "fck";
	power-domains = <&cpg>;
	status = "disabled";
	};

	spi0: spi@e800c800 {
	compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
	reg = <0xe800c800 0x24>;
	interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error", "rx", "tx";
	clocks = <&cpg CPG_MOD 97>;
	power-domains = <&cpg>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi1: spi@e800d000 {
	compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
	reg = <0xe800d000 0x24>;
	interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error", "rx", "tx";
	clocks = <&cpg CPG_MOD 96>;
	power-domains = <&cpg>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi2: spi@e800d800 {
	compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
	reg = <0xe800d800 0x24>;
	interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error", "rx", "tx";
	clocks = <&cpg CPG_MOD 95>;
	power-domains = <&cpg>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	ether0: ethernet@e8204000 {
	compatible = "renesas,ether-r7s9210";
	reg = <0xe8204000 0x200>;
	interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 65>;
	power-domains = <&cpg>;

	phy-mode = "rmii";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	ether1: ethernet@e8204200 {
	compatible = "renesas,ether-r7s9210";
	reg = <0xe8204200 0x200>;
	interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 64>;
	power-domains = <&cpg>;
	phy-mode = "rmii";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c0: i2c@e803a000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
	reg = <0xe803a000 0x44>;
	interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 87>;
	power-domains = <&cpg>;
	clock-frequency = <100000>;
	status = "disabled";
	};

	i2c1: i2c@e803a400 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
	reg = <0xe803a400 0x44>;
	interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 86>;
	power-domains = <&cpg>;
	clock-frequency = <100000>;
	status = "disabled";
	};

	i2c2: i2c@e803a800 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
	reg = <0xe803a800 0x44>;
	interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 85>;
	power-domains = <&cpg>;
	clock-frequency = <100000>;
	status = "disabled";
	};

	i2c3: i2c@e803ac00 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
	reg = <0xe803ac00 0x44>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 257 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 258 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 84>;
	power-domains = <&cpg>;
	clock-frequency = <100000>;
	status = "disabled";
	};

	ostm0: timer@e803b000 {
	compatible = "renesas,r7s9210-ostm", "renesas,ostm";
	reg = <0xe803b000 0x30>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
	clocks = <&cpg CPG_MOD 36>;
	- clock-names = "ostm0";
	power-domains = <&cpg>;
	status = "disabled";
	};

	ostm1: timer@e803c000 {
	compatible = "renesas,r7s9210-ostm", "renesas,ostm";
	reg = <0xe803c000 0x30>;
	interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
	clocks = <&cpg CPG_MOD 35>;
	- clock-names = "ostm1";
	power-domains = <&cpg>;
	status = "disabled";
	};

	ostm2: timer@e803d000 {
	compatible = "renesas,r7s9210-ostm", "renesas,ostm";
	reg = <0xe803d000 0x30>;
	interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>;
	clocks = <&cpg CPG_MOD 34>;
	- clock-names = "ostm2";
	power-domains = <&cpg>;
	status = "disabled";
	};

	ohci0: usb@e8218000 {
	compatible = "generic-ohci";
	reg = <0xe8218000 0x100>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 61>;
	phys = <&usb2_phy0>;
	phy-names = "usb";
	power-domains = <&cpg>;
	status = "disabled";
	};

	ehci0: usb@e8218100 {
	compatible = "generic-ehci";
	reg = <0xe8218100 0x100>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 61>;
	phys = <&usb2_phy0>;
	phy-names = "usb";
	power-domains = <&cpg>;
	status = "disabled";
	};

	usb2_phy0: usb-phy@e8218200 {
	compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy";
	reg = <0xe8218200 0x700>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 61>, <&usb_x1_clk>;
	clock-names = "fck", "usb_x1";
	power-domains = <&cpg>;
	#phy-cells = <0>;
	status = "disabled";
	};

	usbhs0: usb@e8219000 {
	compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs";
	reg = <0xe8219000 0x724>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 61>;
	renesas,buswait = <7>;
	phys = <&usb2_phy0>;
	phy-names = "usb";
	power-domains = <&cpg>;
	status = "disabled";
	};

	ohci1: usb@e821a000 {
	compatible = "generic-ohci";
	reg = <0xe821a000 0x100>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 60>;
	phys = <&usb2_phy1>;
	phy-names = "usb";
	power-domains = <&cpg>;
	status = "disabled";
	};

	ehci1: usb@e821a100 {
	compatible = "generic-ehci";
	reg = <0xe821a100 0x100>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 60>;
	phys = <&usb2_phy1>;
	phy-names = "usb";
	power-domains = <&cpg>;
	status = "disabled";
	};

	usb2_phy1: usb-phy@e821a200 {
	compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy";
	reg = <0xe821a200 0x700>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 60>, <&usb_x1_clk>;
	clock-names = "fck", "usb_x1";
	power-domains = <&cpg>;
	#phy-cells = <0>;
	status = "disabled";
	};

	usbhs1: usb@e821b000 {
	compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs";
	reg = <0xe821b000 0x724>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 60>;
	renesas,buswait = <7>;
	phys = <&usb2_phy1>;
	phy-names = "usb";
	power-domains = <&cpg>;
	status = "disabled";
	};

	sdhi0: sd@e8228000 {
	compatible = "renesas,sdhi-r7s9210";
	reg = <0xe8228000 0x8c0>;
	interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 103>, <&cpg CPG_MOD 102>;
	clock-names = "core", "cd";
	power-domains = <&cpg>;
	cap-sd-highspeed;
	cap-sdio-irq;
	status = "disabled";
	};

	sdhi1: sd@e822a000 {
	compatible = "renesas,sdhi-r7s9210";
	reg = <0xe822a000 0x8c0>;
	interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 101>, <&cpg CPG_MOD 100>;
	clock-names = "core", "cd";
	power-domains = <&cpg>;
	cap-sd-highspeed;
	cap-sdio-irq;
	status = "disabled";
	};

	gic: interrupt-controller@e8221000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0xe8221000 0x1000>,
	<0xe8222000 0x1000>;
	};

	cpg: clock-controller@fcfe0010 {
	compatible = "renesas,r7s9210-cpg-mssr";
	reg = <0xfcfe0010 0x455>;
	clocks = <&extal_clk>;
	clock-names = "extal";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	};

	wdt: watchdog@fcfe7000 {
	compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt";
	reg = <0xfcfe7000 0x26>;
	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_CORE R7S9210_CLK_P0>;
	};

	bsid: chipid@fcfe8004 {
	compatible = "renesas,bsid";
	reg = <0xfcfe8004 4>;
	};

	irqc: interrupt-controller@fcfef800 {
	compatible = "renesas,r7s9210-irqc",
	"renesas,rza1-irqc";
	#interrupt-cells = <2>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0xfcfef800 0x6>;
	interrupt-map =
	<0 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	<1 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	<2 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	<3 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<4 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<5 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	<6 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	<7 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-map-mask = <7 0>;
	};

	pinctrl: pin-controller@fcffe000 {
	compatible = "renesas,r7s9210-pinctrl";
	reg = <0xfcffe000 0x1000>;

	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 0 176>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/r8a73a4-ape6evm.dts b/sys/gnu/dts/arm/r8a73a4-ape6evm.dts
	index a5351ddbf506..b088e8e351d5 100644
	--- a/sys/gnu/dts/arm/r8a73a4-ape6evm.dts
	+++ b/sys/gnu/dts/arm/r8a73a4-ape6evm.dts
	@@ -1,275 +1,272 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the APE6EVM board
	*
	* Copyright (C) 2013 Renesas Solutions Corp.
	*/

	/dts-v1/;
	#include "r8a73a4.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>

	/ {
	model = "APE6EVM";
	compatible = "renesas,ape6evm", "renesas,r8a73a4";

	aliases {
	serial0 = &scifa0;
	};

	chosen {
	bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
	stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
	device_type = "memory";
	reg = <0 0x40000000 0 0x40000000>;
	};

	memory@200000000 {
	device_type = "memory";
	reg = <2 0x00000000 0 0x40000000>;
	};

	vcc_mmc0: regulator-mmc0 {
	compatible = "regulator-fixed";
	regulator-name = "MMC0 Vcc";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-always-on;
	};

	vcc_sdhi0: regulator-sdhi0 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI0 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&pfc 76 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	/* Common 1.8V and 3.3V rails, used by several devices on APE6EVM */
	ape6evm_fixed_1v8: regulator-1v8 {
	compatible = "regulator-fixed";
	regulator-name = "1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	ape6evm_fixed_3v3: regulator-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	leds {
	compatible = "gpio-leds";
	led1 {
	gpios = <&pfc 28 GPIO_ACTIVE_HIGH>;
	label = "GNSS_EN";
	};
	led2 {
	gpios = <&pfc 126 GPIO_ACTIVE_HIGH>;
	label = "NFC_NRST";
	};
	led3 {
	gpios = <&pfc 132 GPIO_ACTIVE_HIGH>;
	label = "GNSS_NRST";
	};
	led4 {
	gpios = <&pfc 232 GPIO_ACTIVE_HIGH>;
	label = "BT_WAKEUP";
	};
	led5 {
	gpios = <&pfc 250 GPIO_ACTIVE_HIGH>;
	label = "STROBE";
	};
	led6 {
	gpios = <&pfc 288 GPIO_ACTIVE_HIGH>;
	label = "BBRESETOUT";
	};
	};

	keyboard {
	compatible = "gpio-keys";

	pinctrl-names = "default";
	pinctrl-0 = <&keyboard_pins>;

	zero-key {
	gpios = <&pfc 324 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_0>;
	label = "S16";
	wakeup-source;
	};

	menu-key {
	gpios = <&pfc 325 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_MENU>;
	label = "S17";
	};

	home-key {
	gpios = <&pfc 326 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_HOME>;
	label = "S18";
	};

	back-key {
	gpios = <&pfc 327 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_BACK>;
	label = "S19";
	};

	volup-key {
	gpios = <&pfc 328 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_VOLUMEUP>;
	label = "S20";
	};

	voldown-key {
	gpios = <&pfc 329 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_VOLUMEDOWN>;
	label = "S21";
	};
	};
	};

	&i2c5 {
	status = "okay";
	vdd_dvfs: regulator@1b {
	compatible = "maxim,max8973";
	reg = <0x1b>;

	regulator-min-microvolt = <935000>;
	regulator-max-microvolt = <1200000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};

	&cpu0 {
	cpu0-supply = <&vdd_dvfs>;
	- operating-points = <
	- /* kHz uV */
	- 1950000 1115000
	- 1462500 995000
	- >;
	+ operating-points = <1950000 1115000>, /* kHz uV */
	+ <1462500 995000>;
	voltage-tolerance = <1>; /* 1% */
	};

	&bsc {
	flash@0 {
	compatible = "cfi-flash", "mtd-rom";
	reg = <0x0 0x08000000>;
	bank-width = <2>;

	partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
	label = "uboot";
	reg = <0x00000000 0x00040000>;
	read-only;
	};
	partition@40000 {
	label = "uboot-env";
	reg = <0x00040000 0x00040000>;
	read-only;
	};
	partition@80000 {
	label = "flash";
	reg = <0x00080000 0x07f80000>;
	};
	};
	};

	ethernet@8000000 {
	compatible = "smsc,lan9220", "smsc,lan9115";
	reg = <0x08000000 0x1000>;
	interrupt-parent = <&irqc1>;
	interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
	phy-mode = "mii";
	reg-io-width = <4>;
	smsc,irq-active-high;
	smsc,irq-push-pull;
	vdd33a-supply = <&ape6evm_fixed_3v3>;
	vddvario-supply = <&ape6evm_fixed_1v8>;
	};
	};

	&cmt1 {
	status = "okay";
	};

	&pfc {
	scifa0_pins: scifa0 {
	groups = "scifa0_data";
	function = "scifa0";
	};

	mmc0_pins: mmc0 {
	groups = "mmc0_data8", "mmc0_ctrl";
	function = "mmc0";
	};

	sdhi0_pins: sd0 {
	groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
	function = "sdhi0";
	};

	sdhi1_pins: sd1 {
	groups = "sdhi1_data4", "sdhi1_ctrl";
	function = "sdhi1";
	};

	keyboard_pins: keyboard {
	pins = "PORT324", "PORT325", "PORT326", "PORT327", "PORT328",
	"PORT329";
	bias-pull-up;
	};
	};

	&mmcif0 {
	vmmc-supply = <&vcc_mmc0>;
	bus-width = <8>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	status = "okay";
	};

	&scifa0 {
	pinctrl-0 = <&scifa0_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&sdhi0 {
	vmmc-supply = <&vcc_sdhi0>;
	bus-width = <4>;
	disable-wp;
	pinctrl-names = "default";
	pinctrl-0 = <&sdhi0_pins>;
	status = "okay";
	};

	&sdhi1 {
	vmmc-supply = <&ape6evm_fixed_3v3>;
	bus-width = <4>;
	broken-cd;
	disable-wp;
	pinctrl-names = "default";
	pinctrl-0 = <&sdhi1_pins>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/r8a73a4.dtsi b/sys/gnu/dts/arm/r8a73a4.dtsi
	index a5cd31229fbd..a3ba722a9d7f 100644
	--- a/sys/gnu/dts/arm/r8a73a4.dtsi
	+++ b/sys/gnu/dts/arm/r8a73a4.dtsi
	@@ -1,898 +1,905 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the r8a73a4 SoC
	*
	* Copyright (C) 2013 Renesas Solutions Corp.
	* Copyright (C) 2013 Magnus Damm
	*/

	#include <dt-bindings/clock/r8a73a4-clock.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/interrupt-controller/irq.h>

	/ {
	compatible = "renesas,r8a73a4";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0>;
	clocks = <&cpg_clocks R8A73A4_CLK_Z>;
	clock-frequency = <1500000000>;
	power-domains = <&pd_a2sl>;
	next-level-cache = <&L2_CA15>;
	};

	L2_CA15: cache-controller-0 {
	compatible = "cache";
	clocks = <&cpg_clocks R8A73A4_CLK_Z>;
	power-domains = <&pd_a3sm>;
	cache-unified;
	cache-level = <2>;
	};

	L2_CA7: cache-controller-1 {
	compatible = "cache";
	clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
	power-domains = <&pd_a3km>;
	cache-unified;
	cache-level = <2>;
	};
	};

	ptm {
	compatible = "arm,coresight-etm3x";
	power-domains = <&pd_d4>;
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	dbsc1: memory-controller@e6790000 {
	compatible = "renesas,dbsc-r8a73a4";
	reg = <0 0xe6790000 0 0x10000>;
	power-domains = <&pd_a3bc>;
	};

	dbsc2: memory-controller@e67a0000 {
	compatible = "renesas,dbsc-r8a73a4";
	reg = <0 0xe67a0000 0 0x10000>;
	power-domains = <&pd_a3bc>;
	};

	dmac: dma-multiplexer {
	compatible = "renesas,shdma-mux";
	#dma-cells = <1>;
	dma-channels = <20>;
	dma-requests = <256>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	dma0: dma-controller@e6700020 {
	compatible = "renesas,shdma-r8a73a4";
	reg = <0 0xe6700020 0 0x89e0>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15",
	"ch16", "ch17", "ch18", "ch19";
	clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
	power-domains = <&pd_a3sp>;
	};
	};

	i2c5: i2c@e60b0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
	reg = <0 0xe60b0000 0 0x428>;
	interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
	power-domains = <&pd_a3sp>;

	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
	clock-names = "fck";
	power-domains = <&pd_c5>;
	status = "disabled";
	};

	irqc0: interrupt-controller@e61c0000 {
	compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
	power-domains = <&pd_c4>;
	};

	irqc1: interrupt-controller@e61c0200 {
	compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0200 0 0x200>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
	power-domains = <&pd_c4>;
	};

	pfc: pin-controller@e6050000 {
	compatible = "renesas,pfc-r8a73a4";
	reg = <0 0xe6050000 0 0x9000>;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges =
	<&pfc 0 0 31>, <&pfc 32 32 9>,
	<&pfc 64 64 22>, <&pfc 96 96 31>,
	<&pfc 128 128 7>, <&pfc 160 160 19>,
	<&pfc 192 192 31>, <&pfc 224 224 27>,
	<&pfc 256 256 28>, <&pfc 288 288 21>,
	<&pfc 320 320 10>;
	interrupts-extended =
	<&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
	<&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
	<&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
	<&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
	<&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
	<&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
	<&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
	<&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
	<&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
	<&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
	<&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
	<&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
	<&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
	<&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
	<&irqc1 24 0>, <&irqc1 25 0>;
	power-domains = <&pd_c5>;
	};

	thermal@e61f0000 {
	compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
	reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
	<0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
	power-domains = <&pd_c5>;
	};

	i2c0: i2c@e6500000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
	reg = <0 0xe6500000 0 0x428>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	i2c1: i2c@e6510000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
	reg = <0 0xe6510000 0 0x428>;
	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	i2c2: i2c@e6520000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
	reg = <0 0xe6520000 0 0x428>;
	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	i2c3: i2c@e6530000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
	reg = <0 0xe6530000 0 0x428>;
	interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	i2c4: i2c@e6540000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
	reg = <0 0xe6540000 0 0x428>;
	interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	i2c6: i2c@e6550000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
	reg = <0 0xe6550000 0 0x428>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	i2c7: i2c@e6560000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
	reg = <0 0xe6560000 0 0x428>;
	interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	i2c8: i2c@e6570000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
	reg = <0 0xe6570000 0 0x428>;
	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	scifb0: serial@e6c20000 {
	compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
	reg = <0 0xe6c20000 0 0x100>;
	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
	clock-names = "fck";
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	scifb1: serial@e6c30000 {
	compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
	reg = <0 0xe6c30000 0 0x100>;
	interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
	clock-names = "fck";
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	scifa0: serial@e6c40000 {
	compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
	reg = <0 0xe6c40000 0 0x100>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
	clock-names = "fck";
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	scifa1: serial@e6c50000 {
	compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
	reg = <0 0xe6c50000 0 0x100>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
	clock-names = "fck";
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	scifb2: serial@e6ce0000 {
	compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
	reg = <0 0xe6ce0000 0 0x100>;
	interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
	clock-names = "fck";
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	scifb3: serial@e6cf0000 {
	compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
	reg = <0 0xe6cf0000 0 0x100>;
	interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
	clock-names = "fck";
	power-domains = <&pd_c4>;
	status = "disabled";
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a73a4";
	reg = <0 0xee100000 0 0x100>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
	power-domains = <&pd_a3sp>;
	cap-sd-highspeed;
	status = "disabled";
	};

	sdhi1: sd@ee120000 {
	compatible = "renesas,sdhi-r8a73a4";
	reg = <0 0xee120000 0 0x100>;
	interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
	power-domains = <&pd_a3sp>;
	cap-sd-highspeed;
	status = "disabled";
	};

	sdhi2: sd@ee140000 {
	compatible = "renesas,sdhi-r8a73a4";
	reg = <0 0xee140000 0 0x100>;
	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
	power-domains = <&pd_a3sp>;
	cap-sd-highspeed;
	status = "disabled";
	};

	mmcif0: mmc@ee200000 {
	compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
	reg = <0 0xee200000 0 0x80>;
	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
	power-domains = <&pd_a3sp>;
	reg-io-width = <4>;
	status = "disabled";
	};

	mmcif1: mmc@ee220000 {
	compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
	reg = <0 0xee220000 0 0x80>;
	interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
	power-domains = <&pd_a3sp>;
	reg-io-width = <4>;
	status = "disabled";
	};

	gic: interrupt-controller@f1001000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0 0xf1001000 0 0x1000>,
	<0 0xf1002000 0 0x2000>,
	<0 0xf1004000 0 0x2000>,
	<0 0xf1006000 0 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
	clock-names = "clk";
	power-domains = <&pd_c4>;
	};

	bsc: bus@fec10000 {
	compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
	"simple-pm-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0x20000000>;
	reg = <0 0xfec10000 0 0x400>;
	clocks = <&zb_clk>;
	power-domains = <&pd_c4>;
	};

	clocks {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	/* External root clocks */
	extalr_clk: extalr {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	extal1_clk: extal1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <25000000>;
	};
	extal2_clk: extal2 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <48000000>;
	};
	fsiack_clk: fsiack {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};
	fsibck_clk: fsibck {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	/* Special CPG clocks */
	cpg_clocks: cpg_clocks@e6150000 {
	compatible = "renesas,r8a73a4-cpg-clocks";
	reg = <0 0xe6150000 0 0x10000>;
	clocks = <&extal1_clk>, <&extal2_clk>;
	#clock-cells = <1>;
	clock-output-names = "main", "pll0", "pll1", "pll2",
	"pll2s", "pll2h", "z", "z2",
	"i", "m3", "b", "m1", "m2",
	"zx", "zs", "hp";
	};

	/* Variable factor clocks (DIV6) */
	zb_clk: zb_clk@e6150010 {
	compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
	reg = <0 0xe6150010 0 4>;
	clocks = <&pll1_div2_clk>, <0>,
	<&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
	#clock-cells = <0>;
	clock-output-names = "zb";
	};
	sdhi0_clk: sdhi0ck@e6150074 {
	compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
	reg = <0 0xe6150074 0 4>;
	clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
	<0>, <&extal2_clk>;
	#clock-cells = <0>;
	};
	sdhi1_clk: sdhi1ck@e6150078 {
	compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
	reg = <0 0xe6150078 0 4>;
	clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
	<0>, <&extal2_clk>;
	#clock-cells = <0>;
	};
	sdhi2_clk: sdhi2ck@e615007c {
	compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
	reg = <0 0xe615007c 0 4>;
	clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
	<0>, <&extal2_clk>;
	#clock-cells = <0>;
	};
	mmc0_clk: mmc0@e6150240 {
	compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
	reg = <0 0xe6150240 0 4>;
	clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
	<0>, <&extal2_clk>;
	#clock-cells = <0>;
	};
	mmc1_clk: mmc1@e6150244 {
	compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
	reg = <0 0xe6150244 0 4>;
	clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
	<0>, <&extal2_clk>;
	#clock-cells = <0>;
	};
	vclk1_clk: vclk1@e6150008 {
	compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
	reg = <0 0xe6150008 0 4>;
	clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
	<0>, <&extal2_clk>, <&main_div2_clk>,
	<&extalr_clk>, <0>, <0>;
	#clock-cells = <0>;
	};
	vclk2_clk: vclk2@e615000c {
	compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
	reg = <0 0xe615000c 0 4>;
	clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
	<0>, <&extal2_clk>, <&main_div2_clk>,
	<&extalr_clk>, <0>, <0>;
	#clock-cells = <0>;
	};
	vclk3_clk: vclk3@e615001c {
	compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
	reg = <0 0xe615001c 0 4>;
	clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
	<0>, <&extal2_clk>, <&main_div2_clk>,
	<&extalr_clk>, <0>, <0>;
	#clock-cells = <0>;
	};
	vclk4_clk: vclk4@e6150014 {
	compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
	reg = <0 0xe6150014 0 4>;
	clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
	<0>, <&extal2_clk>, <&main_div2_clk>,
	<&extalr_clk>, <0>, <0>;
	#clock-cells = <0>;
	};
	vclk5_clk: vclk5@e6150034 {
	compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
	reg = <0 0xe6150034 0 4>;
	clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
	<0>, <&extal2_clk>, <&main_div2_clk>,
	<&extalr_clk>, <0>, <0>;
	#clock-cells = <0>;
	};
	fsia_clk: fsia@e6150018 {
	compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
	reg = <0 0xe6150018 0 4>;
	clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
	<&fsiack_clk>, <0>;
	#clock-cells = <0>;
	};
	fsib_clk: fsib@e6150090 {
	compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
	reg = <0 0xe6150090 0 4>;
	clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
	<&fsibck_clk>, <0>;
	#clock-cells = <0>;
	};
	mp_clk: mp@e6150080 {
	compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
	reg = <0 0xe6150080 0 4>;
	clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
	<&extal2_clk>, <&extal2_clk>;
	#clock-cells = <0>;
	};
	m4_clk: m4@e6150098 {
	compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
	reg = <0 0xe6150098 0 4>;
	clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
	#clock-cells = <0>;
	};
	hsi_clk: hsi@e615026c {
	compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
	reg = <0 0xe615026c 0 4>;
	clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
	<&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
	#clock-cells = <0>;
	};
	spuv_clk: spuv@e6150094 {
	compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
	reg = <0 0xe6150094 0 4>;
	clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
	<&extal2_clk>, <&extal2_clk>;
	#clock-cells = <0>;
	};

	/* Fixed factor clocks */
	main_div2_clk: main_div2 {
	compatible = "fixed-factor-clock";
	clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
	#clock-cells = <0>;
	clock-div = <2>;
	clock-mult = <1>;
	};
	pll0_div2_clk: pll0_div2 {
	compatible = "fixed-factor-clock";
	clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
	#clock-cells = <0>;
	clock-div = <2>;
	clock-mult = <1>;
	};
	pll1_div2_clk: pll1_div2 {
	compatible = "fixed-factor-clock";
	clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
	#clock-cells = <0>;
	clock-div = <2>;
	clock-mult = <1>;
	};
	extal1_div2_clk: extal1_div2 {
	compatible = "fixed-factor-clock";
	clocks = <&extal1_clk>;
	#clock-cells = <0>;
	clock-div = <2>;
	clock-mult = <1>;
	};

	/* Gate clocks */
	mstp2_clks: mstp2_clks@e6150138 {
	compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
	clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
	<&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
	#clock-cells = <1>;
	clock-indices = <
	R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
	R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
	R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
	R8A73A4_CLK_DMAC
	>;
	clock-output-names =
	"scifa0", "scifa1", "scifb0", "scifb1",
	"scifb2", "scifb3", "dmac";
	};
	mstp3_clks: mstp3_clks@e615013c {
	compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
	clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
	<&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
	<&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
	<&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
	R8A73A4_CLK_HP>, <&cpg_clocks
	R8A73A4_CLK_HP>, <&extalr_clk>;
	#clock-cells = <1>;
	clock-indices = <
	R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
	R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
	R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
	R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
	R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
	R8A73A4_CLK_CMT1
	>;
	clock-output-names =
	"iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
	"mmcif0", "iic6", "iic7", "iic0", "iic1",
	"cmt1";
	};
	mstp4_clks: mstp4_clks@e6150140 {
	compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
	clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
	<&main_div2_clk>,
	<&cpg_clocks R8A73A4_CLK_HP>,
	<&cpg_clocks R8A73A4_CLK_HP>;
	#clock-cells = <1>;
	clock-indices = <
	R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS
	R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
	R8A73A4_CLK_IIC3
	>;
	clock-output-names =
	"irqc", "intc-sys", "iic5", "iic4", "iic3";
	};
	mstp5_clks: mstp5_clks@e6150144 {
	compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
	clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
	#clock-cells = <1>;
	clock-indices = <
	R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
	>;
	clock-output-names =
	"thermal", "iic8";
	};
	};

	prr: chipid@ff000044 {
	compatible = "renesas,prr";
	reg = <0 0xff000044 0 4>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
	reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;

	pm-domains {
	pd_c5: c5 {
	#address-cells = <1>;
	#size-cells = <0>;
	#power-domain-cells = <0>;

	pd_c4: c4@0 {
	reg = <0>;
	#address-cells = <1>;
	#size-cells = <0>;
	#power-domain-cells = <0>;

	pd_a3sg: a3sg@16 {
	reg = <16>;
	#power-domain-cells = <0>;
	};

	pd_a3ex: a3ex@17 {
	reg = <17>;
	#power-domain-cells = <0>;
	};

	pd_a3sp: a3sp@18 {
	reg = <18>;
	#address-cells = <1>;
	#size-cells = <0>;
	#power-domain-cells = <0>;

	pd_a2us: a2us@19 {
	reg = <19>;
	#power-domain-cells = <0>;
	};
	};

	pd_a3sm: a3sm@20 {
	reg = <20>;
	#address-cells = <1>;
	#size-cells = <0>;
	#power-domain-cells = <0>;

	pd_a2sl: a2sl@21 {
	reg = <21>;
	#power-domain-cells = <0>;
	};
	};

	pd_a3km: a3km@22 {
	reg = <22>;
	#address-cells = <1>;
	#size-cells = <0>;
	#power-domain-cells = <0>;

	pd_a2kl: a2kl@23 {
	reg = <23>;
	#power-domain-cells = <0>;
	};
	};
	};

	pd_c4ma: c4ma@1 {
	reg = <1>;
	#power-domain-cells = <0>;
	};

	pd_c4cl: c4cl@2 {
	reg = <2>;
	#power-domain-cells = <0>;
	};

	pd_d4: d4@3 {
	reg = <3>;
	#power-domain-cells = <0>;
	};

	pd_a4bc: a4bc@4 {
	reg = <4>;
	#address-cells = <1>;
	#size-cells = <0>;
	#power-domain-cells = <0>;

	pd_a3bc: a3bc@5 {
	reg = <5>;
	#power-domain-cells = <0>;
	};
	};

	pd_a4l: a4l@6 {
	reg = <6>;
	#power-domain-cells = <0>;
	};

	pd_a4lc: a4lc@7 {
	reg = <7>;
	#power-domain-cells = <0>;
	};

	pd_a4mp: a4mp@8 {
	reg = <8>;
	#address-cells = <1>;
	#size-cells = <0>;
	#power-domain-cells = <0>;

	pd_a3mp: a3mp@9 {
	reg = <9>;
	#power-domain-cells = <0>;
	};

	pd_a3vc: a3vc@10 {
	reg = <10>;
	#power-domain-cells = <0>;
	};
	};

	pd_a4sf: a4sf@11 {
	reg = <11>;
	#power-domain-cells = <0>;
	};

	pd_a3r: a3r@12 {
	reg = <12>;
	#address-cells = <1>;
	#size-cells = <0>;
	#power-domain-cells = <0>;

	pd_a2rv: a2rv@13 {
	reg = <13>;
	#power-domain-cells = <0>;
	};

	pd_a2is: a2is@14 {
	reg = <14>;
	#power-domain-cells = <0>;
	};
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/r8a7740.dtsi b/sys/gnu/dts/arm/r8a7740.dtsi
	index ebc1ff64f530..90feb2cf9960 100644
	--- a/sys/gnu/dts/arm/r8a7740.dtsi
	+++ b/sys/gnu/dts/arm/r8a7740.dtsi
	@@ -1,736 +1,736 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the R-Mobile A1 (R8A77400) SoC
	*
	* Copyright (C) 2012 Renesas Solutions Corp.
	*/

	#include <dt-bindings/clock/r8a7740-clock.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/interrupt-controller/irq.h>

	/ {
	compatible = "renesas,r8a7740";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	cpu@0 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <0x0>;
	clock-frequency = <800000000>;
	power-domains = <&pd_a3sm>;
	next-level-cache = <&L2>;
	};
	};

	gic: interrupt-controller@c2800000 {
	compatible = "arm,pl390";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0xc2800000 0x1000>,
	<0xc2000000 0x1000>;
	};

	L2: cache-controller@f0100000 {
	compatible = "arm,pl310-cache";
	reg = <0xf0100000 0x1000>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&pd_a3sm>;
	arm,data-latency = <3 3 3>;
	arm,tag-latency = <2 2 2>;
	arm,shared-override;
	cache-unified;
	cache-level = <2>;
	};

	dbsc3: memory-controller@fe400000 {
	compatible = "renesas,dbsc3-r8a7740";
	reg = <0xfe400000 0x400>;
	power-domains = <&pd_a4s>;
	};

	pmu {
	compatible = "arm,cortex-a9-pmu";
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	};

	ptm {
	compatible = "arm,coresight-etm3x";
	power-domains = <&pd_d4>;
	};

	ceu0: ceu@fe910000 {
	reg = <0xfe910000 0x3000>;
	compatible = "renesas,r8a7740-ceu";
	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp1_clks R8A7740_CLK_CEU20>;
	power-domains = <&pd_a4r>;
	status = "disabled";
	};

	ceu1: ceu@fe914000 {
	reg = <0xfe914000 0x3000>;
	compatible = "renesas,r8a7740-ceu";
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp1_clks R8A7740_CLK_CEU21>;
	power-domains = <&pd_a4r>;
	status = "disabled";
	};

	cmt1: timer@e6138000 {
	compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
	reg = <0xe6138000 0x170>;
	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
	clock-names = "fck";
	power-domains = <&pd_c5>;
	status = "disabled";
	};

	/* irqpin0: IRQ0 - IRQ7 */
	irqpin0: interrupt-controller@e6900000 {
	compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0xe6900000 4>,
	<0xe6900010 4>,
	<0xe6900020 1>,
	<0xe6900040 1>,
	<0xe6900060 1>;
	interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
	power-domains = <&pd_a4s>;
	};

	/* irqpin1: IRQ8 - IRQ15 */
	irqpin1: interrupt-controller@e6900004 {
	compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0xe6900004 4>,
	<0xe6900014 4>,
	<0xe6900024 1>,
	<0xe6900044 1>,
	<0xe6900064 1>;
	interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
	power-domains = <&pd_a4s>;
	};

	/* irqpin2: IRQ16 - IRQ23 */
	irqpin2: interrupt-controller@e6900008 {
	compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0xe6900008 4>,
	<0xe6900018 4>,
	<0xe6900028 1>,
	<0xe6900048 1>,
	<0xe6900068 1>;
	interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
	power-domains = <&pd_a4s>;
	};

	/* irqpin3: IRQ24 - IRQ31 */
	irqpin3: interrupt-controller@e690000c {
	compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0xe690000c 4>,
	<0xe690001c 4>,
	<0xe690002c 1>,
	<0xe690004c 1>,
	<0xe690006c 1>;
	interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
	power-domains = <&pd_a4s>;
	};

	ether: ethernet@e9a00000 {
	compatible = "renesas,gether-r8a7740";
	reg = <0xe9a00000 0x800>,
	<0xe9a01800 0x800>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
	power-domains = <&pd_a4s>;
	phy-mode = "mii";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c0: i2c@fff20000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
	reg = <0xfff20000 0x425>;
	interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
	power-domains = <&pd_a4r>;
	status = "disabled";
	};

	i2c1: i2c@e6c20000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
	reg = <0xe6c20000 0x425>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	scifa0: serial@e6c40000 {
	compatible = "renesas,scifa-r8a7740", "renesas,scifa";
	reg = <0xe6c40000 0x100>;
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
	clock-names = "fck";
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	scifa1: serial@e6c50000 {
	compatible = "renesas,scifa-r8a7740", "renesas,scifa";
	reg = <0xe6c50000 0x100>;
	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
	clock-names = "fck";
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	scifa2: serial@e6c60000 {
	compatible = "renesas,scifa-r8a7740", "renesas,scifa";
	reg = <0xe6c60000 0x100>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
	clock-names = "fck";
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	scifa3: serial@e6c70000 {
	compatible = "renesas,scifa-r8a7740", "renesas,scifa";
	reg = <0xe6c70000 0x100>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
	clock-names = "fck";
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	scifa4: serial@e6c80000 {
	compatible = "renesas,scifa-r8a7740", "renesas,scifa";
	reg = <0xe6c80000 0x100>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
	clock-names = "fck";
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	scifa5: serial@e6cb0000 {
	compatible = "renesas,scifa-r8a7740", "renesas,scifa";
	reg = <0xe6cb0000 0x100>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
	clock-names = "fck";
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	scifa6: serial@e6cc0000 {
	compatible = "renesas,scifa-r8a7740", "renesas,scifa";
	reg = <0xe6cc0000 0x100>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
	clock-names = "fck";
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	scifa7: serial@e6cd0000 {
	compatible = "renesas,scifa-r8a7740", "renesas,scifa";
	reg = <0xe6cd0000 0x100>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
	clock-names = "fck";
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	scifb: serial@e6c30000 {
	compatible = "renesas,scifb-r8a7740", "renesas,scifb";
	reg = <0xe6c30000 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
	clock-names = "fck";
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	pfc: pin-controller@e6050000 {
	compatible = "renesas,pfc-r8a7740";
	reg = <0xe6050000 0x8000>,
	<0xe605800c 0x20>;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pfc 0 0 212>;
	interrupts-extended =
	<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
	<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
	<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
	<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
	<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
	<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
	<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
	<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
	power-domains = <&pd_c5>;
	};

	tpu: pwm@e6600000 {
	compatible = "renesas,tpu-r8a7740", "renesas,tpu";
	reg = <0xe6600000 0x148>;
	clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
	power-domains = <&pd_a3sp>;
	status = "disabled";
	#pwm-cells = <3>;
	};

	mmcif0: mmc@e6bd0000 {
	compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
	reg = <0xe6bd0000 0x100>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp3_clks R8A7740_CLK_MMC>;
	power-domains = <&pd_a3sp>;
	status = "disabled";
	};

	sdhi0: sd@e6850000 {
	compatible = "renesas,sdhi-r8a7740";
	reg = <0xe6850000 0x100>;
	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
	power-domains = <&pd_a3sp>;
	cap-sd-highspeed;
	cap-sdio-irq;
	status = "disabled";
	};

	sdhi1: sd@e6860000 {
	compatible = "renesas,sdhi-r8a7740";
	reg = <0xe6860000 0x100>;
	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
	power-domains = <&pd_a3sp>;
	cap-sd-highspeed;
	cap-sdio-irq;
	status = "disabled";
	};

	sdhi2: sd@e6870000 {
	compatible = "renesas,sdhi-r8a7740";
	reg = <0xe6870000 0x100>;
	interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
	power-domains = <&pd_a3sp>;
	cap-sd-highspeed;
	cap-sdio-irq;
	status = "disabled";
	};

	sh_fsi2: sound@fe1f0000 {
	#sound-dai-cells = <1>;
	compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
	reg = <0xfe1f0000 0x400>;
	interrupts = <GIC_SPI 9 0x4>;
	clocks = <&mstp3_clks R8A7740_CLK_FSI>;
	power-domains = <&pd_a4mp>;
	status = "disabled";
	};

	tmu0: timer@fff80000 {
	compatible = "renesas,tmu-r8a7740", "renesas,tmu";
	reg = <0xfff80000 0x2c>;
	interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
	clock-names = "fck";
	power-domains = <&pd_a4r>;

	#renesas,channels = <3>;

	status = "disabled";
	};

	tmu1: timer@fff90000 {
	compatible = "renesas,tmu-r8a7740", "renesas,tmu";
	reg = <0xfff90000 0x2c>;
	interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
	clock-names = "fck";
	power-domains = <&pd_a4r>;

	#renesas,channels = <3>;

	status = "disabled";
	};

	clocks {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	/* External root clock */
	extalr_clk: extalr {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	extal1_clk: extal1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	extal2_clk: extal2 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	dv_clk: dv {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <27000000>;
	};
	fmsick_clk: fmsick {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	fmsock_clk: fmsock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	fsiack_clk: fsiack {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	fsibck_clk: fsibck {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	/* Special CPG clocks */
	cpg_clocks: cpg_clocks@e6150000 {
	compatible = "renesas,r8a7740-cpg-clocks";
	reg = <0xe6150000 0x10000>;
	- clocks = <&extal1_clk>, <&extalr_clk>;
	+ clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
	#clock-cells = <1>;
	clock-output-names = "system", "pllc0", "pllc1",
	"pllc2", "r",
	"usb24s",
	"i", "zg", "b", "m1", "hp",
	"hpp", "usbp", "s", "zb", "m3",
	"cp";
	};

	/* Variable factor clocks (DIV6) */
	vclk1_clk: vclk1@e6150008 {
	compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
	reg = <0xe6150008 4>;
	clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
	<&cpg_clocks R8A7740_CLK_USB24S>,
	<&extal1_div2_clk>, <&extalr_clk>, <0>,
	<0>;
	#clock-cells = <0>;
	};
	vclk2_clk: vclk2@e615000c {
	compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
	reg = <0xe615000c 4>;
	clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
	<&cpg_clocks R8A7740_CLK_USB24S>,
	<&extal1_div2_clk>, <&extalr_clk>, <0>,
	<0>;
	#clock-cells = <0>;
	};
	fmsi_clk: fmsi@e6150010 {
	compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
	reg = <0xe6150010 4>;
	clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
	#clock-cells = <0>;
	};
	fmso_clk: fmso@e6150014 {
	compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
	reg = <0xe6150014 4>;
	clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
	#clock-cells = <0>;
	};
	fsia_clk: fsia@e6150018 {
	compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
	reg = <0xe6150018 4>;
	clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
	#clock-cells = <0>;
	};
	sub_clk: sub@e6150080 {
	compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
	reg = <0xe6150080 4>;
	clocks = <&pllc1_div2_clk>,
	<&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
	#clock-cells = <0>;
	};
	spu_clk: spu@e6150084 {
	compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
	reg = <0xe6150084 4>;
	clocks = <&pllc1_div2_clk>,
	<&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
	#clock-cells = <0>;
	};
	vou_clk: vou@e6150088 {
	compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
	reg = <0xe6150088 4>;
	clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
	<0>;
	#clock-cells = <0>;
	};
	stpro_clk: stpro@e615009c {
	compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
	reg = <0xe615009c 4>;
	clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
	#clock-cells = <0>;
	};

	/* Fixed factor clocks */
	pllc1_div2_clk: pllc1_div2 {
	compatible = "fixed-factor-clock";
	clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
	#clock-cells = <0>;
	clock-div = <2>;
	clock-mult = <1>;
	};
	extal1_div2_clk: extal1_div2 {
	compatible = "fixed-factor-clock";
	clocks = <&extal1_clk>;
	#clock-cells = <0>;
	clock-div = <2>;
	clock-mult = <1>;
	};

	/* Gate clocks */
	subck_clks: subck_clks@e6150080 {
	compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0xe6150080 4>;
	clocks = <&sub_clk>, <&sub_clk>;
	#clock-cells = <1>;
	clock-indices = <
	R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
	>;
	clock-output-names =
	"subck", "subck2";
	};
	mstp1_clks: mstp1_clks@e6150134 {
	compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0xe6150134 4>, <0xe6150038 4>;
	clocks = <&cpg_clocks R8A7740_CLK_S>,
	<&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
	<&cpg_clocks R8A7740_CLK_B>,
	<&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
	<&cpg_clocks R8A7740_CLK_B>;
	#clock-cells = <1>;
	clock-indices = <
	R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
	R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
	R8A7740_CLK_LCDC0
	>;
	clock-output-names =
	"ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
	"tmu1", "lcdc0";
	};
	mstp2_clks: mstp2_clks@e6150138 {
	compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0xe6150138 4>, <0xe6150040 4>;
	clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
	<&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
	<&cpg_clocks R8A7740_CLK_HP>,
	<&cpg_clocks R8A7740_CLK_HP>,
	<&cpg_clocks R8A7740_CLK_HP>,
	<&sub_clk>, <&sub_clk>, <&sub_clk>,
	<&sub_clk>, <&sub_clk>, <&sub_clk>,
	<&sub_clk>;
	#clock-cells = <1>;
	clock-indices = <
	R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
	R8A7740_CLK_SCIFA7
	R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
	R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
	R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
	R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
	R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
	R8A7740_CLK_SCIFA4
	>;
	clock-output-names =
	"scifa6", "intca",
	"scifa7", "dmac1", "dmac2", "dmac3",
	"usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
	"scifa2", "scifa3", "scifa4";
	};
	mstp3_clks: mstp3_clks@e615013c {
	compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0xe615013c 4>, <0xe6150048 4>;
	clocks = <&cpg_clocks R8A7740_CLK_R>,
	<&cpg_clocks R8A7740_CLK_HP>,
	<&sub_clk>,
	<&cpg_clocks R8A7740_CLK_HP>,
	<&cpg_clocks R8A7740_CLK_HP>,
	<&cpg_clocks R8A7740_CLK_HP>,
	<&cpg_clocks R8A7740_CLK_HP>,
	<&cpg_clocks R8A7740_CLK_HP>,
	<&cpg_clocks R8A7740_CLK_HP>;
	#clock-cells = <1>;
	clock-indices = <
	R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
	R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
	R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
	>;
	clock-output-names =
	"cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
	"mmc", "gether", "tpu0";
	};
	mstp4_clks: mstp4_clks@e6150140 {
	compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
	reg = <0xe6150140 4>, <0xe615004c 4>;
	clocks = <&cpg_clocks R8A7740_CLK_HP>,
	<&cpg_clocks R8A7740_CLK_HP>,
	<&cpg_clocks R8A7740_CLK_HP>,
	<&cpg_clocks R8A7740_CLK_HP>;
	#clock-cells = <1>;
	clock-indices = <
	R8A7740_CLK_USBH R8A7740_CLK_SDHI2
	R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
	>;
	clock-output-names =
	"usbhost", "sdhi2", "usbfunc", "usphy";
	};
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
	reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;

	pm-domains {
	pd_c5: c5 {
	#address-cells = <1>;
	#size-cells = <0>;
	#power-domain-cells = <0>;

	pd_a4lc: a4lc@1 {
	reg = <1>;
	#power-domain-cells = <0>;
	};

	pd_a4mp: a4mp@2 {
	reg = <2>;
	#power-domain-cells = <0>;
	};

	pd_d4: d4@3 {
	reg = <3>;
	#power-domain-cells = <0>;
	};

	pd_a4r: a4r@5 {
	reg = <5>;
	#address-cells = <1>;
	#size-cells = <0>;
	#power-domain-cells = <0>;

	pd_a3rv: a3rv@6 {
	reg = <6>;
	#power-domain-cells = <0>;
	};
	};

	pd_a4s: a4s@10 {
	reg = <10>;
	#address-cells = <1>;
	#size-cells = <0>;
	#power-domain-cells = <0>;

	pd_a3sp: a3sp@11 {
	reg = <11>;
	#power-domain-cells = <0>;
	};

	pd_a3sm: a3sm@12 {
	reg = <12>;
	#power-domain-cells = <0>;
	};

	pd_a3sg: a3sg@13 {
	reg = <13>;
	#power-domain-cells = <0>;
	};
	};

	pd_a4su: a4su@20 {
	reg = <20>;
	#power-domain-cells = <0>;
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/r8a7743.dtsi b/sys/gnu/dts/arm/r8a7743.dtsi
	index 1cd19a569bd0..e8b340bb99bc 100644
	--- a/sys/gnu/dts/arm/r8a7743.dtsi
	+++ b/sys/gnu/dts/arm/r8a7743.dtsi
	@@ -1,1793 +1,1794 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the r8a7743 SoC
	*
	* Copyright (C) 2016-2017 Cogent Embedded Inc.
	*/

	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/r8a7743-cpg-mssr.h>
	#include <dt-bindings/power/r8a7743-sysc.h>

	/ {
	compatible = "renesas,r8a7743";
	#address-cells = <2>;
	#size-cells = <2>;

	/*
	* The external audio clocks are configured as 0 Hz fixed frequency
	* clocks by default.
	* Boards that provide audio clocks should override them.
	*/
	audio_clk_a: audio_clk_a {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_b: audio_clk_b {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_c: audio_clk_c {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	/* External CAN clock */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "renesas,apmu";

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0>;
	clock-frequency = <1500000000>;
	clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
	clock-latency = <300000>; /* 300 us */
	power-domains = <&sysc R8A7743_PD_CA15_CPU0>;
	next-level-cache = <&L2_CA15>;

	/* kHz - uV - OPPs unknown yet */
	operating-points = <1500000 1000000>,
	<1312500 1000000>,
	<1125000 1000000>,
	< 937500 1000000>,
	< 750000 1000000>,
	< 375000 1000000>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <1>;
	clock-frequency = <1500000000>;
	clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
	clock-latency = <300000>; /* 300 us */
	power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
	next-level-cache = <&L2_CA15>;

	/* kHz - uV - OPPs unknown yet */
	operating-points = <1500000 1000000>,
	<1312500 1000000>,
	<1125000 1000000>,
	< 937500 1000000>,
	< 750000 1000000>,
	< 375000 1000000>;
	};

	L2_CA15: cache-controller-0 {
	compatible = "cache";
	cache-unified;
	cache-level = <2>;
	power-domains = <&sysc R8A7743_PD_CA15_SCU>;
	};
	};

	/* External root clock */
	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	/* External PCIe clock - can be overridden by the board */
	pcie_bus_clk: pcie_bus {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	pmu {
	compatible = "arm,cortex-a15-pmu";
	interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	/* External SCIF clock */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;

	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a7743-wdt",
	"renesas,rcar-gen2-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a7743",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a7743",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a7743",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a7743",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a7743",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a7743",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	gpio6: gpio@e6055400 {
	compatible = "renesas,gpio-r8a7743",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055400 0 0x50>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 192 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 905>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 905>;
	};

	gpio7: gpio@e6055800 {
	compatible = "renesas,gpio-r8a7743",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055800 0 0x50>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 224 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 904>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 904>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a7743";
	reg = <0 0xe6060000 0 0x250>;
	};

	tpu: pwm@e60f0000 {
	compatible = "renesas,tpu-r8a7743", "renesas,tpu";
	reg = <0 0xe60f0000 0 0x148>;
	clocks = <&cpg CPG_MOD 304>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 304>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a7743-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>, <&usb_extal_clk>;
	clock-names = "extal", "usb_extal";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	apmu@e6152000 {
	compatible = "renesas,r8a7743-apmu", "renesas,apmu";
	reg = <0 0xe6152000 0 0x188>;
	cpus = <&cpu0 &cpu1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a7743-rst";
	reg = <0 0xe6160000 0 0x100>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a7743-sysc";
	reg = <0 0xe6180000 0 0x200>;
	#power-domain-cells = <1>;
	};

	irqc: interrupt-controller@e61c0000 {
	compatible = "renesas,irqc-r8a7743", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	thermal: thermal@e61f0000 {
	compatible = "renesas,thermal-r8a7743",
	"renesas,rcar-gen2-thermal";
	reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 522>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 522>;
	#thermal-sensor-cells = <0>;
	};

	ipmmu_sy0: mmu@e6280000 {
	compatible = "renesas,ipmmu-r8a7743",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6280000 0 0x1000>;
	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_sy1: mmu@e6290000 {
	compatible = "renesas,ipmmu-r8a7743",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6290000 0 0x1000>;
	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_ds: mmu@e6740000 {
	compatible = "renesas,ipmmu-r8a7743",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6740000 0 0x1000>;
	interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_mp: mmu@ec680000 {
	compatible = "renesas,ipmmu-r8a7743",
	"renesas,ipmmu-vmsa";
	reg = <0 0xec680000 0 0x1000>;
	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_mx: mmu@fe951000 {
	compatible = "renesas,ipmmu-r8a7743",
	"renesas,ipmmu-vmsa";
	reg = <0 0xfe951000 0 0x1000>;
	interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_gp: mmu@e62a0000 {
	compatible = "renesas,ipmmu-r8a7743",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe62a0000 0 0x1000>;
	interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	icram0: sram@e63a0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63a0000 0 0x12000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63a0000 0x12000>;
	};

	icram1: sram@e63c0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63c0000 0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63c0000 0x1000>;

	smp-sram@0 {
	compatible = "renesas,smp-sram";
	reg = <0 0x100>;
	};
	};

	icram2: sram@e6300000 {
	compatible = "mmio-sram";
	reg = <0 0xe6300000 0 0x40000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe6300000 0x40000>;
	};

	/* The memory map in the User's Manual maps the cores to
	* bus numbers
	*/
	i2c0: i2c@e6508000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7743",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c1: i2c@e6518000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7743",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6518000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c2: i2c@e6530000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7743",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6530000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c3: i2c@e6540000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7743",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6540000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c4: i2c@e6520000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7743",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6520000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c5: i2c@e6528000 {
	/* doesn't need pinmux */
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7743",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6528000 0 0x40>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 925>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 925>;
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	iic0: i2c@e6500000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7743",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe6500000 0 0x425>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 318>;
	dmas = <&dmac0 0x61>, <&dmac0 0x62>,
	<&dmac1 0x61>, <&dmac1 0x62>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 318>;
	status = "disabled";
	};

	iic1: i2c@e6510000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7743",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe6510000 0 0x425>;
	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 323>;
	dmas = <&dmac0 0x65>, <&dmac0 0x66>,
	<&dmac1 0x65>, <&dmac1 0x66>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 323>;
	status = "disabled";
	};

	iic3: i2c@e60b0000 {
	/* doesn't need pinmux */
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7743";
	reg = <0 0xe60b0000 0 0x425>;
	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 926>;
	dmas = <&dmac0 0x77>, <&dmac0 0x78>,
	<&dmac1 0x77>, <&dmac1 0x78>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 926>;
	status = "disabled";
	};

	hsusb: usb@e6590000 {
	compatible = "renesas,usbhs-r8a7743",
	"renesas,rcar-gen2-usbhs";
	reg = <0 0xe6590000 0 0x100>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 704>;
	dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
	<&usb_dmac1 0>, <&usb_dmac1 1>;
	dma-names = "ch0", "ch1", "ch2", "ch3";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 704>;
	renesas,buswait = <4>;
	phys = <&usb0 1>;
	phy-names = "usb";
	status = "disabled";
	};

	usbphy: usb-phy@e6590100 {
	compatible = "renesas,usb-phy-r8a7743",
	"renesas,rcar-gen2-usb-phy";
	reg = <0 0xe6590100 0 0x100>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cpg CPG_MOD 704>;
	clock-names = "usbhs";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 704>;
	status = "disabled";

	usb0: usb-channel@0 {
	reg = <0>;
	#phy-cells = <1>;
	};
	usb2: usb-channel@2 {
	reg = <2>;
	#phy-cells = <1>;
	};
	};

	usb_dmac0: dma-controller@e65a0000 {
	compatible = "renesas,r8a7743-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65a0000 0 0x100>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 330>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 330>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac1: dma-controller@e65b0000 {
	compatible = "renesas,r8a7743-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65b0000 0 0x100>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 331>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 331>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a7743",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x20000>;
	interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	dmac1: dma-controller@e6720000 {
	compatible = "renesas,dmac-r8a7743",
	"renesas,rcar-dmac";
	reg = <0 0xe6720000 0 0x20000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a7743",
	"renesas,etheravb-rcar-gen2";
	reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
	interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	qspi: spi@e6b10000 {
	compatible = "renesas,qspi-r8a7743", "renesas,qspi";
	reg = <0 0xe6b10000 0 0x2c>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 917>;
	dmas = <&dmac0 0x17>, <&dmac0 0x18>,
	<&dmac1 0x17>, <&dmac1 0x18>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	resets = <&cpg 917>;
	status = "disabled";
	};

	scifa0: serial@e6c40000 {
	compatible = "renesas,scifa-r8a7743",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c40000 0 0x40>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 204>;
	clock-names = "fck";
	dmas = <&dmac0 0x21>, <&dmac0 0x22>,
	<&dmac1 0x21>, <&dmac1 0x22>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 204>;
	status = "disabled";
	};

	scifa1: serial@e6c50000 {
	compatible = "renesas,scifa-r8a7743",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c50000 0 0x40>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 203>;
	clock-names = "fck";
	dmas = <&dmac0 0x25>, <&dmac0 0x26>,
	<&dmac1 0x25>, <&dmac1 0x26>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 203>;
	status = "disabled";
	};

	scifa2: serial@e6c60000 {
	compatible = "renesas,scifa-r8a7743",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c60000 0 0x40>;
	interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 202>;
	clock-names = "fck";
	dmas = <&dmac0 0x27>, <&dmac0 0x28>,
	<&dmac1 0x27>, <&dmac1 0x28>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 202>;
	status = "disabled";
	};

	scifa3: serial@e6c70000 {
	compatible = "renesas,scifa-r8a7743",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c70000 0 0x40>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1106>;
	clock-names = "fck";
	dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
	<&dmac1 0x1b>, <&dmac1 0x1c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 1106>;
	status = "disabled";
	};

	scifa4: serial@e6c78000 {
	compatible = "renesas,scifa-r8a7743",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c78000 0 0x40>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1107>;
	clock-names = "fck";
	dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
	<&dmac1 0x1f>, <&dmac1 0x20>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 1107>;
	status = "disabled";
	};

	scifa5: serial@e6c80000 {
	compatible = "renesas,scifa-r8a7743",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c80000 0 0x40>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1108>;
	clock-names = "fck";
	dmas = <&dmac0 0x23>, <&dmac0 0x24>,
	<&dmac1 0x23>, <&dmac1 0x24>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 1108>;
	status = "disabled";
	};

	scifb0: serial@e6c20000 {
	compatible = "renesas,scifb-r8a7743",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6c20000 0 0x100>;
	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 206>;
	clock-names = "fck";
	dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
	<&dmac1 0x3d>, <&dmac1 0x3e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 206>;
	status = "disabled";
	};

	scifb1: serial@e6c30000 {
	compatible = "renesas,scifb-r8a7743",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6c30000 0 0x100>;
	interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 207>;
	clock-names = "fck";
	dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
	<&dmac1 0x19>, <&dmac1 0x1a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 207>;
	status = "disabled";
	};

	scifb2: serial@e6ce0000 {
	compatible = "renesas,scifb-r8a7743",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6ce0000 0 0x100>;
	interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 216>;
	clock-names = "fck";
	dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
	<&dmac1 0x1d>, <&dmac1 0x1e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 216>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a7743",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e60000 0 0x40>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 721>,
	<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
	<&dmac1 0x29>, <&dmac1 0x2a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 721>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a7743",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e68000 0 0x40>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 720>,
	<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
	<&dmac1 0x2d>, <&dmac1 0x2e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 720>;
	status = "disabled";
	};

	scif2: serial@e6e58000 {
	compatible = "renesas,scif-r8a7743",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e58000 0 0x40>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 719>,
	<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
	<&dmac1 0x2b>, <&dmac1 0x2c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 719>;
	status = "disabled";
	};

	scif3: serial@e6ea8000 {
	compatible = "renesas,scif-r8a7743",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ea8000 0 0x40>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 718>,
	<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
	<&dmac1 0x2f>, <&dmac1 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 718>;
	status = "disabled";
	};

	scif4: serial@e6ee0000 {
	compatible = "renesas,scif-r8a7743",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ee0000 0 0x40>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 715>,
	<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
	<&dmac1 0xfb>, <&dmac1 0xfc>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 715>;
	status = "disabled";
	};

	scif5: serial@e6ee8000 {
	compatible = "renesas,scif-r8a7743",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ee8000 0 0x40>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 714>,
	<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
	<&dmac1 0xfd>, <&dmac1 0xfe>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 714>;
	status = "disabled";
	};

	hscif0: serial@e62c0000 {
	compatible = "renesas,hscif-r8a7743",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c0000 0 0x60>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 717>,
	<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
	<&dmac1 0x39>, <&dmac1 0x3a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 717>;
	status = "disabled";
	};

	hscif1: serial@e62c8000 {
	compatible = "renesas,hscif-r8a7743",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c8000 0 0x60>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>,
	<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
	<&dmac1 0x4d>, <&dmac1 0x4e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";
	};

	hscif2: serial@e62d0000 {
	compatible = "renesas,hscif-r8a7743",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62d0000 0 0x60>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 713>,
	<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
	<&dmac1 0x3b>, <&dmac1 0x3c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 713>;
	status = "disabled";
	};

	msiof0: spi@e6e20000 {
	compatible = "renesas,msiof-r8a7743",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6e20000 0 0x0064>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 000>;
	dmas = <&dmac0 0x51>, <&dmac0 0x52>,
	<&dmac1 0x51>, <&dmac1 0x52>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	#address-cells = <1>;
	#size-cells = <0>;
	resets = <&cpg 000>;
	status = "disabled";
	};

	msiof1: spi@e6e10000 {
	compatible = "renesas,msiof-r8a7743",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6e10000 0 0x0064>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 208>;
	dmas = <&dmac0 0x55>, <&dmac0 0x56>,
	<&dmac1 0x55>, <&dmac1 0x56>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	#address-cells = <1>;
	#size-cells = <0>;
	resets = <&cpg 208>;
	status = "disabled";
	};

	msiof2: spi@e6e00000 {
	compatible = "renesas,msiof-r8a7743",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6e00000 0 0x0064>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 205>;
	dmas = <&dmac0 0x41>, <&dmac0 0x42>,
	<&dmac1 0x41>, <&dmac1 0x42>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	#address-cells = <1>;
	#size-cells = <0>;
	resets = <&cpg 205>;
	status = "disabled";
	};

	pwm0: pwm@e6e30000 {
	compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
	reg = <0 0xe6e30000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm1: pwm@e6e31000 {
	compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
	reg = <0 0xe6e31000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm2: pwm@e6e32000 {
	compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
	reg = <0 0xe6e32000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm3: pwm@e6e33000 {
	compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
	reg = <0 0xe6e33000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm4: pwm@e6e34000 {
	compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
	reg = <0 0xe6e34000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm5: pwm@e6e35000 {
	compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
	reg = <0 0xe6e35000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm6: pwm@e6e36000 {
	compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
	reg = <0 0xe6e36000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	can0: can@e6e80000 {
	compatible = "renesas,can-r8a7743",
	"renesas,rcar-gen2-can";
	reg = <0 0xe6e80000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 916>,
	<&cpg CPG_CORE R8A7743_CLK_RCAN>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 916>;
	status = "disabled";
	};

	can1: can@e6e88000 {
	compatible = "renesas,can-r8a7743",
	"renesas,rcar-gen2-can";
	reg = <0 0xe6e88000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 915>,
	<&cpg CPG_CORE R8A7743_CLK_RCAN>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 915>;
	status = "disabled";
	};

	vin0: video@e6ef0000 {
	compatible = "renesas,vin-r8a7743",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef0000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 811>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 811>;
	status = "disabled";
	};

	vin1: video@e6ef1000 {
	compatible = "renesas,vin-r8a7743",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef1000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 810>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 810>;
	status = "disabled";
	};

	vin2: video@e6ef2000 {
	compatible = "renesas,vin-r8a7743",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef2000 0 0x1000>;
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 809>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 809>;
	status = "disabled";
	};

	rcar_sound: sound@ec500000 {
	/*
	* #sound-dai-cells is required
	*
	* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
	* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
	*/
	compatible = "renesas,rcar_sound-r8a7743",
	"renesas,rcar_sound-gen2";
	reg = <0 0xec500000 0 0x1000>, /* SCU */
	<0 0xec5a0000 0 0x100>, /* ADG */
	<0 0xec540000 0 0x1000>, /* SSIU */
	<0 0xec541000 0 0x280>, /* SSI */
	<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
	reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

	clocks = <&cpg CPG_MOD 1005>,
	<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
	<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
	<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
	<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
	<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
	<&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
	<&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
	<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
	<&cpg CPG_CORE R8A7743_CLK_M2>;
	clock-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
	"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
	"src.9", "src.8", "src.7", "src.6", "src.5",
	"src.4", "src.3", "src.2", "src.1", "src.0",
	"ctu.0", "ctu.1",
	"mix.0", "mix.1",
	"dvc.0", "dvc.1",
	"clk_a", "clk_b", "clk_c", "clk_i";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 1005>,
	<&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
	<&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
	<&cpg 1014>, <&cpg 1015>;
	reset-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
	"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
	status = "disabled";

	rcar_sound,dvc {
	dvc0: dvc-0 {
	dmas = <&audma1 0xbc>;
	dma-names = "tx";
	};
	dvc1: dvc-1 {
	dmas = <&audma1 0xbe>;
	dma-names = "tx";
	};
	};

	rcar_sound,mix {
	mix0: mix-0 { };
	mix1: mix-1 { };
	};

	rcar_sound,ctu {
	ctu00: ctu-0 { };
	ctu01: ctu-1 { };
	ctu02: ctu-2 { };
	ctu03: ctu-3 { };
	ctu10: ctu-4 { };
	ctu11: ctu-5 { };
	ctu12: ctu-6 { };
	ctu13: ctu-7 { };
	};

	rcar_sound,src {
	src0: src-0 {
	interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x85>, <&audma1 0x9a>;
	dma-names = "rx", "tx";
	};
	src1: src-1 {
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x87>, <&audma1 0x9c>;
	dma-names = "rx", "tx";
	};
	src2: src-2 {
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x89>, <&audma1 0x9e>;
	dma-names = "rx", "tx";
	};
	src3: src-3 {
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8b>, <&audma1 0xa0>;
	dma-names = "rx", "tx";
	};
	src4: src-4 {
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8d>, <&audma1 0xb0>;
	dma-names = "rx", "tx";
	};
	src5: src-5 {
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8f>, <&audma1 0xb2>;
	dma-names = "rx", "tx";
	};
	src6: src-6 {
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x91>, <&audma1 0xb4>;
	dma-names = "rx", "tx";
	};
	src7: src-7 {
	interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x93>, <&audma1 0xb6>;
	dma-names = "rx", "tx";
	};
	src8: src-8 {
	interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x95>, <&audma1 0xb8>;
	dma-names = "rx", "tx";
	};
	src9: src-9 {
	interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x97>, <&audma1 0xba>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssi {
	ssi0: ssi-0 {
	interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi1: ssi-1 {
	interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi2: ssi-2 {
	interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi3: ssi-3 {
	interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi4: ssi-4 {
	interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi5: ssi-5 {
	interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi6: ssi-6 {
	interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi7: ssi-7 {
	interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi8: ssi-8 {
	interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi9: ssi-9 {
	interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	};
	};

	audma0: dma-controller@ec700000 {
	compatible = "renesas,dmac-r8a7743",
	"renesas,rcar-dmac";
	reg = <0 0xec700000 0 0x10000>;
	interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12";
	clocks = <&cpg CPG_MOD 502>;
	clock-names = "fck";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 502>;
	#dma-cells = <1>;
	dma-channels = <13>;
	};

	audma1: dma-controller@ec720000 {
	compatible = "renesas,dmac-r8a7743",
	"renesas,rcar-dmac";
	reg = <0 0xec720000 0 0x10000>;
	interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12";
	clocks = <&cpg CPG_MOD 501>;
	clock-names = "fck";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 501>;
	#dma-cells = <1>;
	dma-channels = <13>;
	};

	/*
	* pci1 and xhci share the same phy, therefore only one of them
	* can be active at any one time. If both of them are enabled,
	* a race condition will determine who'll control the phy.
	* A firmware file is needed by the xhci driver in order for
	* USB 3.0 to work properly.
	*/
	xhci: usb@ee000000 {
	compatible = "renesas,xhci-r8a7743",
	"renesas,rcar-gen2-xhci";
	reg = <0 0xee000000 0 0xc00>;
	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	phys = <&usb2 1>;
	phy-names = "usb";
	status = "disabled";
	};

	pci0: pci@ee090000 {
	compatible = "renesas,pci-r8a7743",
	"renesas,pci-rcar-gen2";
	device_type = "pci";
	reg = <0 0xee090000 0 0xc00>,
	<0 0xee080000 0 0x1100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 703>;
	status = "disabled";

	bus-range = <0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
	interrupt-map-mask = <0xf800 0 0 0x7>;
	interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

	usb@1,0 {
	reg = <0x800 0 0 0 0>;
	phys = <&usb0 0>;
	phy-names = "usb";
	};

	usb@2,0 {
	reg = <0x1000 0 0 0 0>;
	phys = <&usb0 0>;
	phy-names = "usb";
	};
	};

	pci1: pci@ee0d0000 {
	compatible = "renesas,pci-r8a7743",
	"renesas,pci-rcar-gen2";
	device_type = "pci";
	reg = <0 0xee0d0000 0 0xc00>,
	<0 0xee0c0000 0 0x1100>;
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 703>;
	status = "disabled";

	bus-range = <1 1>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
	interrupt-map-mask = <0xf800 0 0 0x7>;
	interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

	usb@1,0 {
	reg = <0x10800 0 0 0 0>;
	phys = <&usb2 0>;
	phy-names = "usb";
	};

	usb@2,0 {
	reg = <0x11000 0 0 0 0>;
	phys = <&usb2 0>;
	phy-names = "usb";
	};
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a7743",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee100000 0 0x328>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
	<&dmac1 0xcd>, <&dmac1 0xce>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <195000000>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	status = "disabled";
	};

	sdhi1: sd@ee140000 {
	compatible = "renesas,sdhi-r8a7743",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee140000 0 0x100>;
	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 312>;
	dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
	<&dmac1 0xc1>, <&dmac1 0xc2>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <97500000>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 312>;
	status = "disabled";
	};

	sdhi2: sd@ee160000 {
	compatible = "renesas,sdhi-r8a7743",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee160000 0 0x100>;
	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 311>;
	dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
	<&dmac1 0xd3>, <&dmac1 0xd4>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <97500000>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 311>;
	status = "disabled";
	};

	mmcif0: mmc@ee200000 {
	compatible = "renesas,mmcif-r8a7743",
	"renesas,sh-mmcif";
	reg = <0 0xee200000 0 0x80>;
	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 315>;
	dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
	<&dmac1 0xd1>, <&dmac1 0xd2>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 315>;
	reg-io-width = <4>;
	max-frequency = <97500000>;
	status = "disabled";
	};

	ether: ethernet@ee700000 {
	compatible = "renesas,ether-r8a7743",
	"renesas,rcar-gen2-ether";
	reg = <0 0xee700000 0 0x400>;
	interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 813>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 813>;
	phy-mode = "rmii";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	gic: interrupt-controller@f1001000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
	<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	pciec: pcie@fe000000 {
	compatible = "renesas,pcie-r8a7743",
	"renesas,pcie-rcar-gen2";
	reg = <0 0xfe000000 0 0x80000>;
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x00 0xff>;
	device_type = "pci";
	ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
	<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
	<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
	<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
	/* Map all possible DDR as inbound ranges */
	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
	<0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
	clock-names = "pcie", "pcie_bus";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 319>;
	status = "disabled";
	};

	vsp@fe928000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe928000 0 0x8000>;
	interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 131>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 131>;
	};

	vsp@fe930000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe930000 0 0x8000>;
	interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 128>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 128>;
	};

	vsp@fe938000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe938000 0 0x8000>;
	interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 127>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 127>;
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a7743";
	reg = <0 0xfeb00000 0 0x40000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&cpg CPG_MOD 724>,
	- <&cpg CPG_MOD 723>;
	+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
	clock-names = "du.0", "du.1";
	+ resets = <&cpg 724>;
	+ reset-names = "du.0";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb: endpoint {
	};
	};
	port@1 {
	reg = <1>;
	du_out_lvds0: endpoint {
	remote-endpoint = <&lvds0_in>;
	};
	};
	};
	};

	lvds0: lvds@feb90000 {
	compatible = "renesas,r8a7743-lvds";
	reg = <0 0xfeb90000 0 0x1c>;
	clocks = <&cpg CPG_MOD 726>;
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 726>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds0_in: endpoint {
	remote-endpoint = <&du_out_lvds0>;
	};
	};
	port@1 {
	reg = <1>;
	lvds0_out: endpoint {
	};
	};
	};
	};

	prr: chipid@ff000044 {
	compatible = "renesas,prr";
	reg = <0 0xff000044 0 4>;
	};

	cmt0: timer@ffca0000 {
	compatible = "renesas,r8a7743-cmt0",
	"renesas,rcar-gen2-cmt0";
	reg = <0 0xffca0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 124>;
	clock-names = "fck";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 124>;
	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a7743-cmt1",
	"renesas,rcar-gen2-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 329>;
	clock-names = "fck";
	power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
	resets = <&cpg 329>;
	status = "disabled";
	};
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	polling-delay-passive = <0>;
	polling-delay = <0>;

	thermal-sensors = <&thermal>;

	trips {
	cpu-crit {
	temperature = <95000>;
	hysteresis = <0>;
	type = "critical";
	};
	};

	cooling-maps {
	};
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clock - can be overridden by the board */
	usb_extal_clk: usb_extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <48000000>;
	};
	};
	diff --git a/sys/gnu/dts/arm/r8a7744.dtsi b/sys/gnu/dts/arm/r8a7744.dtsi
	index 1c82dd0abd76..def840b8b2d3 100644
	--- a/sys/gnu/dts/arm/r8a7744.dtsi
	+++ b/sys/gnu/dts/arm/r8a7744.dtsi
	@@ -1,1779 +1,1780 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the r8a7744 SoC
	*
	* Copyright (C) 2018 Renesas Electronics Corp.
	*/

	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/r8a7744-cpg-mssr.h>
	#include <dt-bindings/power/r8a7744-sysc.h>

	/ {
	compatible = "renesas,r8a7744";
	#address-cells = <2>;
	#size-cells = <2>;

	/*
	* The external audio clocks are configured as 0 Hz fixed frequency
	* clocks by default.
	* Boards that provide audio clocks should override them.
	*/
	audio_clk_a: audio_clk_a {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_b: audio_clk_b {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_c: audio_clk_c {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	/* External CAN clock */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "renesas,apmu";

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0>;
	clock-frequency = <1500000000>;
	clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
	clock-latency = <300000>; /* 300 us */
	power-domains = <&sysc R8A7744_PD_CA15_CPU0>;
	next-level-cache = <&L2_CA15>;

	/* kHz - uV - OPPs unknown yet */
	operating-points = <1500000 1000000>,
	<1312500 1000000>,
	<1125000 1000000>,
	< 937500 1000000>,
	< 750000 1000000>,
	< 375000 1000000>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <1>;
	clock-frequency = <1500000000>;
	clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
	clock-latency = <300000>; /* 300 us */
	power-domains = <&sysc R8A7744_PD_CA15_CPU1>;
	next-level-cache = <&L2_CA15>;

	/* kHz - uV - OPPs unknown yet */
	operating-points = <1500000 1000000>,
	<1312500 1000000>,
	<1125000 1000000>,
	< 937500 1000000>,
	< 750000 1000000>,
	< 375000 1000000>;
	};

	L2_CA15: cache-controller-0 {
	compatible = "cache";
	cache-unified;
	cache-level = <2>;
	power-domains = <&sysc R8A7744_PD_CA15_SCU>;
	};
	};

	/* External root clock */
	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	/* External PCIe clock - can be overridden by the board */
	pcie_bus_clk: pcie_bus {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	pmu {
	compatible = "arm,cortex-a15-pmu";
	interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	/* External SCIF clock */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;

	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a7744-wdt",
	"renesas,rcar-gen2-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a7744",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a7744",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a7744",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a7744",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a7744",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a7744",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	gpio6: gpio@e6055400 {
	compatible = "renesas,gpio-r8a7744",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055400 0 0x50>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 192 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 905>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 905>;
	};

	gpio7: gpio@e6055800 {
	compatible = "renesas,gpio-r8a7744",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055800 0 0x50>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 224 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 904>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 904>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a7744";
	reg = <0 0xe6060000 0 0x250>;
	};

	tpu: pwm@e60f0000 {
	compatible = "renesas,tpu-r8a7744", "renesas,tpu";
	reg = <0 0xe60f0000 0 0x148>;
	clocks = <&cpg CPG_MOD 304>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 304>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a7744-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>, <&usb_extal_clk>;
	clock-names = "extal", "usb_extal";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	apmu@e6152000 {
	compatible = "renesas,r8a7744-apmu", "renesas,apmu";
	reg = <0 0xe6152000 0 0x188>;
	cpus = <&cpu0 &cpu1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a7744-rst";
	reg = <0 0xe6160000 0 0x100>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a7744-sysc";
	reg = <0 0xe6180000 0 0x200>;
	#power-domain-cells = <1>;
	};

	irqc: interrupt-controller@e61c0000 {
	compatible = "renesas,irqc-r8a7744", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	thermal: thermal@e61f0000 {
	compatible = "renesas,thermal-r8a7744",
	"renesas,rcar-gen2-thermal";
	reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 522>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 522>;
	#thermal-sensor-cells = <0>;
	};

	ipmmu_sy0: mmu@e6280000 {
	compatible = "renesas,ipmmu-r8a7744",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6280000 0 0x1000>;
	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_sy1: mmu@e6290000 {
	compatible = "renesas,ipmmu-r8a7744",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6290000 0 0x1000>;
	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_ds: mmu@e6740000 {
	compatible = "renesas,ipmmu-r8a7744",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6740000 0 0x1000>;
	interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_mp: mmu@ec680000 {
	compatible = "renesas,ipmmu-r8a7744",
	"renesas,ipmmu-vmsa";
	reg = <0 0xec680000 0 0x1000>;
	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_mx: mmu@fe951000 {
	compatible = "renesas,ipmmu-r8a7744",
	"renesas,ipmmu-vmsa";
	reg = <0 0xfe951000 0 0x1000>;
	interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_gp: mmu@e62a0000 {
	compatible = "renesas,ipmmu-r8a7744",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe62a0000 0 0x1000>;
	interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	icram0: sram@e63a0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63a0000 0 0x12000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63a0000 0x12000>;
	};

	icram1: sram@e63c0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63c0000 0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63c0000 0x1000>;

	smp-sram@0 {
	compatible = "renesas,smp-sram";
	reg = <0 0x100>;
	};
	};

	icram2: sram@e6300000 {
	compatible = "mmio-sram";
	reg = <0 0xe6300000 0 0x40000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe6300000 0x40000>;
	};

	/* The memory map in the User's Manual maps the cores to
	* bus numbers
	*/
	i2c0: i2c@e6508000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7744",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c1: i2c@e6518000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7744",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6518000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c2: i2c@e6530000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7744",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6530000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c3: i2c@e6540000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7744",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6540000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c4: i2c@e6520000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7744",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6520000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c5: i2c@e6528000 {
	/* doesn't need pinmux */
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7744",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6528000 0 0x40>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 925>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 925>;
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	iic0: i2c@e6500000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7744",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe6500000 0 0x425>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 318>;
	dmas = <&dmac0 0x61>, <&dmac0 0x62>,
	<&dmac1 0x61>, <&dmac1 0x62>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 318>;
	status = "disabled";
	};

	iic1: i2c@e6510000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7744",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe6510000 0 0x425>;
	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 323>;
	dmas = <&dmac0 0x65>, <&dmac0 0x66>,
	<&dmac1 0x65>, <&dmac1 0x66>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 323>;
	status = "disabled";
	};

	iic3: i2c@e60b0000 {
	/* doesn't need pinmux */
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7744";
	reg = <0 0xe60b0000 0 0x425>;
	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 926>;
	dmas = <&dmac0 0x77>, <&dmac0 0x78>,
	<&dmac1 0x77>, <&dmac1 0x78>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 926>;
	status = "disabled";
	};

	hsusb: usb@e6590000 {
	compatible = "renesas,usbhs-r8a7744",
	"renesas,rcar-gen2-usbhs";
	reg = <0 0xe6590000 0 0x100>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 704>;
	dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
	<&usb_dmac1 0>, <&usb_dmac1 1>;
	dma-names = "ch0", "ch1", "ch2", "ch3";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 704>;
	renesas,buswait = <4>;
	phys = <&usb0 1>;
	phy-names = "usb";
	status = "disabled";
	};

	usbphy: usb-phy@e6590100 {
	compatible = "renesas,usb-phy-r8a7744",
	"renesas,rcar-gen2-usb-phy";
	reg = <0 0xe6590100 0 0x100>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cpg CPG_MOD 704>;
	clock-names = "usbhs";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 704>;
	status = "disabled";

	usb0: usb-channel@0 {
	reg = <0>;
	#phy-cells = <1>;
	};
	usb2: usb-channel@2 {
	reg = <2>;
	#phy-cells = <1>;
	};
	};

	usb_dmac0: dma-controller@e65a0000 {
	compatible = "renesas,r8a7744-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65a0000 0 0x100>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 330>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 330>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac1: dma-controller@e65b0000 {
	compatible = "renesas,r8a7744-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65b0000 0 0x100>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 331>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 331>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a7744",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x20000>;
	interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	dmac1: dma-controller@e6720000 {
	compatible = "renesas,dmac-r8a7744",
	"renesas,rcar-dmac";
	reg = <0 0xe6720000 0 0x20000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a7744",
	"renesas,etheravb-rcar-gen2";
	reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
	interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	qspi: spi@e6b10000 {
	compatible = "renesas,qspi-r8a7744", "renesas,qspi";
	reg = <0 0xe6b10000 0 0x2c>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 917>;
	dmas = <&dmac0 0x17>, <&dmac0 0x18>,
	<&dmac1 0x17>, <&dmac1 0x18>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	resets = <&cpg 917>;
	status = "disabled";
	};

	scifa0: serial@e6c40000 {
	compatible = "renesas,scifa-r8a7744",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c40000 0 0x40>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 204>;
	clock-names = "fck";
	dmas = <&dmac0 0x21>, <&dmac0 0x22>,
	<&dmac1 0x21>, <&dmac1 0x22>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 204>;
	status = "disabled";
	};

	scifa1: serial@e6c50000 {
	compatible = "renesas,scifa-r8a7744",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c50000 0 0x40>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 203>;
	clock-names = "fck";
	dmas = <&dmac0 0x25>, <&dmac0 0x26>,
	<&dmac1 0x25>, <&dmac1 0x26>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 203>;
	status = "disabled";
	};

	scifa2: serial@e6c60000 {
	compatible = "renesas,scifa-r8a7744",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c60000 0 0x40>;
	interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 202>;
	clock-names = "fck";
	dmas = <&dmac0 0x27>, <&dmac0 0x28>,
	<&dmac1 0x27>, <&dmac1 0x28>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 202>;
	status = "disabled";
	};

	scifa3: serial@e6c70000 {
	compatible = "renesas,scifa-r8a7744",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c70000 0 0x40>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1106>;
	clock-names = "fck";
	dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
	<&dmac1 0x1b>, <&dmac1 0x1c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 1106>;
	status = "disabled";
	};

	scifa4: serial@e6c78000 {
	compatible = "renesas,scifa-r8a7744",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c78000 0 0x40>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1107>;
	clock-names = "fck";
	dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
	<&dmac1 0x1f>, <&dmac1 0x20>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 1107>;
	status = "disabled";
	};

	scifa5: serial@e6c80000 {
	compatible = "renesas,scifa-r8a7744",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c80000 0 0x40>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1108>;
	clock-names = "fck";
	dmas = <&dmac0 0x23>, <&dmac0 0x24>,
	<&dmac1 0x23>, <&dmac1 0x24>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 1108>;
	status = "disabled";
	};

	scifb0: serial@e6c20000 {
	compatible = "renesas,scifb-r8a7744",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6c20000 0 0x100>;
	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 206>;
	clock-names = "fck";
	dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
	<&dmac1 0x3d>, <&dmac1 0x3e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 206>;
	status = "disabled";
	};

	scifb1: serial@e6c30000 {
	compatible = "renesas,scifb-r8a7744",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6c30000 0 0x100>;
	interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 207>;
	clock-names = "fck";
	dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
	<&dmac1 0x19>, <&dmac1 0x1a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 207>;
	status = "disabled";
	};

	scifb2: serial@e6ce0000 {
	compatible = "renesas,scifb-r8a7744",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6ce0000 0 0x100>;
	interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 216>;
	clock-names = "fck";
	dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
	<&dmac1 0x1d>, <&dmac1 0x1e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 216>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a7744",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e60000 0 0x40>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 721>,
	<&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
	<&dmac1 0x29>, <&dmac1 0x2a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 721>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a7744",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e68000 0 0x40>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 720>,
	<&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
	<&dmac1 0x2d>, <&dmac1 0x2e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 720>;
	status = "disabled";
	};

	scif2: serial@e6e58000 {
	compatible = "renesas,scif-r8a7744",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e58000 0 0x40>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 719>,
	<&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
	<&dmac1 0x2b>, <&dmac1 0x2c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 719>;
	status = "disabled";
	};

	scif3: serial@e6ea8000 {
	compatible = "renesas,scif-r8a7744",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ea8000 0 0x40>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 718>,
	<&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
	<&dmac1 0x2f>, <&dmac1 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 718>;
	status = "disabled";
	};

	scif4: serial@e6ee0000 {
	compatible = "renesas,scif-r8a7744",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ee0000 0 0x40>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 715>,
	<&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
	<&dmac1 0xfb>, <&dmac1 0xfc>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 715>;
	status = "disabled";
	};

	scif5: serial@e6ee8000 {
	compatible = "renesas,scif-r8a7744",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ee8000 0 0x40>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 714>,
	<&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
	<&dmac1 0xfd>, <&dmac1 0xfe>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 714>;
	status = "disabled";
	};

	hscif0: serial@e62c0000 {
	compatible = "renesas,hscif-r8a7744",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c0000 0 0x60>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 717>,
	<&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
	<&dmac1 0x39>, <&dmac1 0x3a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 717>;
	status = "disabled";
	};

	hscif1: serial@e62c8000 {
	compatible = "renesas,hscif-r8a7744",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c8000 0 0x60>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>,
	<&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
	<&dmac1 0x4d>, <&dmac1 0x4e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";
	};

	hscif2: serial@e62d0000 {
	compatible = "renesas,hscif-r8a7744",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62d0000 0 0x60>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 713>,
	<&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
	<&dmac1 0x3b>, <&dmac1 0x3c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 713>;
	status = "disabled";
	};

	msiof0: spi@e6e20000 {
	compatible = "renesas,msiof-r8a7744",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6e20000 0 0x0064>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 000>;
	dmas = <&dmac0 0x51>, <&dmac0 0x52>,
	<&dmac1 0x51>, <&dmac1 0x52>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	#address-cells = <1>;
	#size-cells = <0>;
	resets = <&cpg 000>;
	status = "disabled";
	};

	msiof1: spi@e6e10000 {
	compatible = "renesas,msiof-r8a7744",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6e10000 0 0x0064>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 208>;
	dmas = <&dmac0 0x55>, <&dmac0 0x56>,
	<&dmac1 0x55>, <&dmac1 0x56>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	#address-cells = <1>;
	#size-cells = <0>;
	resets = <&cpg 208>;
	status = "disabled";
	};

	msiof2: spi@e6e00000 {
	compatible = "renesas,msiof-r8a7744",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6e00000 0 0x0064>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 205>;
	dmas = <&dmac0 0x41>, <&dmac0 0x42>,
	<&dmac1 0x41>, <&dmac1 0x42>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	#address-cells = <1>;
	#size-cells = <0>;
	resets = <&cpg 205>;
	status = "disabled";
	};

	pwm0: pwm@e6e30000 {
	compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
	reg = <0 0xe6e30000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm1: pwm@e6e31000 {
	compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
	reg = <0 0xe6e31000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm2: pwm@e6e32000 {
	compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
	reg = <0 0xe6e32000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm3: pwm@e6e33000 {
	compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
	reg = <0 0xe6e33000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm4: pwm@e6e34000 {
	compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
	reg = <0 0xe6e34000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm5: pwm@e6e35000 {
	compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
	reg = <0 0xe6e35000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm6: pwm@e6e36000 {
	compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
	reg = <0 0xe6e36000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	can0: can@e6e80000 {
	compatible = "renesas,can-r8a7744",
	"renesas,rcar-gen2-can";
	reg = <0 0xe6e80000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 916>,
	<&cpg CPG_CORE R8A7744_CLK_RCAN>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 916>;
	status = "disabled";
	};

	can1: can@e6e88000 {
	compatible = "renesas,can-r8a7744",
	"renesas,rcar-gen2-can";
	reg = <0 0xe6e88000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 915>,
	<&cpg CPG_CORE R8A7744_CLK_RCAN>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 915>;
	status = "disabled";
	};

	vin0: video@e6ef0000 {
	compatible = "renesas,vin-r8a7744",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef0000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 811>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 811>;
	status = "disabled";
	};

	vin1: video@e6ef1000 {
	compatible = "renesas,vin-r8a7744",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef1000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 810>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 810>;
	status = "disabled";
	};

	vin2: video@e6ef2000 {
	compatible = "renesas,vin-r8a7744",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef2000 0 0x1000>;
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 809>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 809>;
	status = "disabled";
	};

	rcar_sound: sound@ec500000 {
	/*
	* #sound-dai-cells is required
	*
	* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
	* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
	*/
	compatible = "renesas,rcar_sound-r8a7744",
	"renesas,rcar_sound-gen2";
	reg = <0 0xec500000 0 0x1000>, /* SCU */
	<0 0xec5a0000 0 0x100>, /* ADG */
	<0 0xec540000 0 0x1000>, /* SSIU */
	<0 0xec541000 0 0x280>, /* SSI */
	<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
	reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

	clocks = <&cpg CPG_MOD 1005>,
	<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
	<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
	<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
	<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
	<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
	<&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
	<&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
	<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
	<&cpg CPG_CORE R8A7744_CLK_M2>;
	clock-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
	"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
	"src.9", "src.8", "src.7", "src.6", "src.5",
	"src.4", "src.3", "src.2", "src.1", "src.0",
	"ctu.0", "ctu.1",
	"mix.0", "mix.1",
	"dvc.0", "dvc.1",
	"clk_a", "clk_b", "clk_c", "clk_i";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 1005>,
	<&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
	<&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
	<&cpg 1014>, <&cpg 1015>;
	reset-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
	"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
	status = "disabled";

	rcar_sound,dvc {
	dvc0: dvc-0 {
	dmas = <&audma1 0xbc>;
	dma-names = "tx";
	};
	dvc1: dvc-1 {
	dmas = <&audma1 0xbe>;
	dma-names = "tx";
	};
	};

	rcar_sound,mix {
	mix0: mix-0 { };
	mix1: mix-1 { };
	};

	rcar_sound,ctu {
	ctu00: ctu-0 { };
	ctu01: ctu-1 { };
	ctu02: ctu-2 { };
	ctu03: ctu-3 { };
	ctu10: ctu-4 { };
	ctu11: ctu-5 { };
	ctu12: ctu-6 { };
	ctu13: ctu-7 { };
	};

	rcar_sound,src {
	src0: src-0 {
	interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x85>, <&audma1 0x9a>;
	dma-names = "rx", "tx";
	};
	src1: src-1 {
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x87>, <&audma1 0x9c>;
	dma-names = "rx", "tx";
	};
	src2: src-2 {
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x89>, <&audma1 0x9e>;
	dma-names = "rx", "tx";
	};
	src3: src-3 {
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8b>, <&audma1 0xa0>;
	dma-names = "rx", "tx";
	};
	src4: src-4 {
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8d>, <&audma1 0xb0>;
	dma-names = "rx", "tx";
	};
	src5: src-5 {
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8f>, <&audma1 0xb2>;
	dma-names = "rx", "tx";
	};
	src6: src-6 {
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x91>, <&audma1 0xb4>;
	dma-names = "rx", "tx";
	};
	src7: src-7 {
	interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x93>, <&audma1 0xb6>;
	dma-names = "rx", "tx";
	};
	src8: src-8 {
	interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x95>, <&audma1 0xb8>;
	dma-names = "rx", "tx";
	};
	src9: src-9 {
	interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x97>, <&audma1 0xba>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssi {
	ssi0: ssi-0 {
	interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi1: ssi-1 {
	interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi2: ssi-2 {
	interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi3: ssi-3 {
	interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi4: ssi-4 {
	interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi5: ssi-5 {
	interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi6: ssi-6 {
	interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi7: ssi-7 {
	interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi8: ssi-8 {
	interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi9: ssi-9 {
	interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	};
	};

	audma0: dma-controller@ec700000 {
	compatible = "renesas,dmac-r8a7744",
	"renesas,rcar-dmac";
	reg = <0 0xec700000 0 0x10000>;
	interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12";
	clocks = <&cpg CPG_MOD 502>;
	clock-names = "fck";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 502>;
	#dma-cells = <1>;
	dma-channels = <13>;
	};

	audma1: dma-controller@ec720000 {
	compatible = "renesas,dmac-r8a7744",
	"renesas,rcar-dmac";
	reg = <0 0xec720000 0 0x10000>;
	interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12";
	clocks = <&cpg CPG_MOD 501>;
	clock-names = "fck";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 501>;
	#dma-cells = <1>;
	dma-channels = <13>;
	};

	/*
	* pci1 and xhci share the same phy, therefore only one of them
	* can be active at any one time. If both of them are enabled,
	* a race condition will determine who'll control the phy.
	* A firmware file is needed by the xhci driver in order for
	* USB 3.0 to work properly.
	*/
	xhci: usb@ee000000 {
	compatible = "renesas,xhci-r8a7744",
	"renesas,rcar-gen2-xhci";
	reg = <0 0xee000000 0 0xc00>;
	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	phys = <&usb2 1>;
	phy-names = "usb";
	status = "disabled";
	};

	pci0: pci@ee090000 {
	compatible = "renesas,pci-r8a7744",
	"renesas,pci-rcar-gen2";
	device_type = "pci";
	reg = <0 0xee090000 0 0xc00>,
	<0 0xee080000 0 0x1100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 703>;
	status = "disabled";

	bus-range = <0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
	interrupt-map-mask = <0xf800 0 0 0x7>;
	interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

	usb@1,0 {
	reg = <0x800 0 0 0 0>;
	phys = <&usb0 0>;
	phy-names = "usb";
	};

	usb@2,0 {
	reg = <0x1000 0 0 0 0>;
	phys = <&usb0 0>;
	phy-names = "usb";
	};
	};

	pci1: pci@ee0d0000 {
	compatible = "renesas,pci-r8a7744",
	"renesas,pci-rcar-gen2";
	device_type = "pci";
	reg = <0 0xee0d0000 0 0xc00>,
	<0 0xee0c0000 0 0x1100>;
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 703>;
	status = "disabled";

	bus-range = <1 1>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
	interrupt-map-mask = <0xf800 0 0 0x7>;
	interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

	usb@1,0 {
	reg = <0x10800 0 0 0 0>;
	phys = <&usb2 0>;
	phy-names = "usb";
	};

	usb@2,0 {
	reg = <0x11000 0 0 0 0>;
	phys = <&usb2 0>;
	phy-names = "usb";
	};
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a7744",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee100000 0 0x328>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
	<&dmac1 0xcd>, <&dmac1 0xce>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <195000000>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	status = "disabled";
	};

	sdhi1: sd@ee140000 {
	compatible = "renesas,sdhi-r8a7744",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee140000 0 0x100>;
	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 312>;
	dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
	<&dmac1 0xc1>, <&dmac1 0xc2>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <97500000>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 312>;
	status = "disabled";
	};

	sdhi2: sd@ee160000 {
	compatible = "renesas,sdhi-r8a7744",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee160000 0 0x100>;
	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 311>;
	dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
	<&dmac1 0xd3>, <&dmac1 0xd4>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <97500000>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 311>;
	status = "disabled";
	};

	mmcif0: mmc@ee200000 {
	compatible = "renesas,mmcif-r8a7744",
	"renesas,sh-mmcif";
	reg = <0 0xee200000 0 0x80>;
	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 315>;
	dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
	<&dmac1 0xd1>, <&dmac1 0xd2>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 315>;
	reg-io-width = <4>;
	max-frequency = <97500000>;
	status = "disabled";
	};

	gic: interrupt-controller@f1001000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
	<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	pciec: pcie@fe000000 {
	compatible = "renesas,pcie-r8a7744",
	"renesas,pcie-rcar-gen2";
	reg = <0 0xfe000000 0 0x80000>;
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x00 0xff>;
	device_type = "pci";
	ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
	<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
	<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
	<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
	/* Map all possible DDR as inbound ranges */
	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
	<0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
	clock-names = "pcie", "pcie_bus";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 319>;
	status = "disabled";
	};

	vsp@fe928000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe928000 0 0x8000>;
	interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 131>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 131>;
	};

	vsp@fe930000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe930000 0 0x8000>;
	interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 128>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 128>;
	};

	vsp@fe938000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe938000 0 0x8000>;
	interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 127>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 127>;
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a7744";
	reg = <0 0xfeb00000 0 0x40000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&cpg CPG_MOD 724>,
	- <&cpg CPG_MOD 723>;
	+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
	clock-names = "du.0", "du.1";
	+ resets = <&cpg 724>;
	+ reset-names = "du.0";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb: endpoint {
	};
	};
	port@1 {
	reg = <1>;
	du_out_lvds0: endpoint {
	remote-endpoint = <&lvds0_in>;
	};
	};
	};
	};

	lvds0: lvds@feb90000 {
	compatible = "renesas,r8a7744-lvds";
	reg = <0 0xfeb90000 0 0x1c>;
	clocks = <&cpg CPG_MOD 726>;
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 726>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds0_in: endpoint {
	remote-endpoint = <&du_out_lvds0>;
	};
	};
	port@1 {
	reg = <1>;
	lvds0_out: endpoint {
	};
	};
	};
	};

	prr: chipid@ff000044 {
	compatible = "renesas,prr";
	reg = <0 0xff000044 0 4>;
	};

	cmt0: timer@ffca0000 {
	compatible = "renesas,r8a7744-cmt0",
	"renesas,rcar-gen2-cmt0";
	reg = <0 0xffca0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 124>;
	clock-names = "fck";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 124>;
	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a7744-cmt1",
	"renesas,rcar-gen2-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 329>;
	clock-names = "fck";
	power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
	resets = <&cpg 329>;
	status = "disabled";
	};
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	polling-delay-passive = <0>;
	polling-delay = <0>;

	thermal-sensors = <&thermal>;

	trips {
	cpu-crit {
	temperature = <95000>;
	hysteresis = <0>;
	type = "critical";
	};
	};

	cooling-maps {
	};
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clock - can be overridden by the board */
	usb_extal_clk: usb_extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <48000000>;
	};
	};
	diff --git a/sys/gnu/dts/arm/r8a7745-iwg22d-sodimm-dbhd-ca.dts b/sys/gnu/dts/arm/r8a7745-iwg22d-sodimm-dbhd-ca.dts
	index 2aeebfc9e4f1..b1f679da36b2 100644
	--- a/sys/gnu/dts/arm/r8a7745-iwg22d-sodimm-dbhd-ca.dts
	+++ b/sys/gnu/dts/arm/r8a7745-iwg22d-sodimm-dbhd-ca.dts
	@@ -1,155 +1,159 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the iWave-RZG1E SODIMM carrier board + HDMI daughter
	* board
	*
	* Copyright (C) 2017 Renesas Electronics Corp.
	*/

	#include "r8a7745-iwg22d-sodimm.dts"

	/ {
	model = "iWave RainboW-G22D-SODIMM RZ/G1E based board with HDMI add-on";
	compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745";

	aliases {
	serial0 = &scif1;
	serial4 = &scif5;
	serial6 = &hscif2;
	};

	cec_clock: cec-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <12000000>;
	};

	hdmi-out {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con: endpoint {
	remote-endpoint = <&adv7511_out>;
	};
	};
	};
	};

	&du {
	pinctrl-0 = <&du0_pins>;
	pinctrl-names = "default";

	status = "okay";

	ports {
	port@0 {
	endpoint {
	remote-endpoint = <&adv7511_in>;
	};
	};
	};
	};

	&can1 {
	pinctrl-0 = <&can1_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&hscif2 {
	pinctrl-0 = <&hscif2_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&i2c1 {
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-names = "default";

	status = "okay";
	clock-frequency = <400000>;

	hdmi@39 {
	compatible = "adi,adv7511w";
	reg = <0x39>;
	interrupt-parent = <&gpio1>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&cec_clock>;
	clock-names = "cec";
	pd-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;

	adi,input-depth = <8>;
	adi,input-colorspace = "rgb";
	adi,input-clock = "1x";
	- adi,input-style = <1>;
	- adi,input-justification = "evenly";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7511_in: endpoint {
	remote-endpoint = <&du_out_rgb0>;
	};
	};

	port@1 {
	reg = <1>;
	adv7511_out: endpoint {
	remote-endpoint = <&hdmi_con>;
	};
	};
	};
	};
	};

	+&lcd_panel {
	+ status = "disabled";
	+
	+ /delete-node/ port;
	+};
	+
	&pfc {
	can1_pins: can1 {
	groups = "can1_data_b";
	function = "can1";
	};

	du0_pins: du0 {
	groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out";
	function = "du0";
	};

	hscif2_pins: hscif2 {
	groups = "hscif2_data";
	function = "hscif2";
	};

	i2c1_pins: i2c1 {
	groups = "i2c1_d";
	function = "i2c1";
	};

	scif1_pins: scif1 {
	groups = "scif1_data";
	function = "scif1";
	};

	scif5_pins: scif5 {
	groups = "scif5_data_d";
	function = "scif5";
	};
	};

	&scif1 {
	pinctrl-0 = <&scif1_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&scif5 {
	pinctrl-0 = <&scif5_pins>;
	pinctrl-names = "default";

	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/r8a7745-iwg22d-sodimm.dts b/sys/gnu/dts/arm/r8a7745-iwg22d-sodimm.dts
	index 58d369ad8279..b15b1b088a32 100644
	--- a/sys/gnu/dts/arm/r8a7745-iwg22d-sodimm.dts
	+++ b/sys/gnu/dts/arm/r8a7745-iwg22d-sodimm.dts
	@@ -1,234 +1,327 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the iWave-RZG1E SODIMM carrier board
	*
	* Copyright (C) 2017 Renesas Electronics Corp.
	*/

	/*
	* SSI-SGTL5000
	*
	* This command is required when Playback/Capture
	*
	* amixer set "DVC Out" 100%
	* amixer set "DVC In" 100%
	*
	* You can use Mute
	*
	* amixer set "DVC Out Mute" on
	* amixer set "DVC In Mute" on
	*
	* You can use Volume Ramp
	*
	* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
	* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
	* amixer set "DVC Out Ramp" on
	* aplay xxx.wav &
	* amixer set "DVC Out" 80% // Volume Down
	* amixer set "DVC Out" 100% // Volume Up
	*/

	/dts-v1/;
	#include "r8a7745-iwg22m.dtsi"
	+#include <dt-bindings/pwm/pwm.h>

	/ {
	model = "iWave Systems RainboW-G22D-SODIMM board based on RZ/G1E";
	compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745";

	aliases {
	ethernet0 = &avb;
	serial3 = &scif4;
	serial5 = &hscif1;
	};

	chosen {
	bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
	stdout-path = "serial3:115200n8";
	};

	audio_clock: audio_clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <26000000>;
	};

	rsnd_sgtl5000: sound {
	compatible = "simple-audio-card";
	simple-audio-card,format = "i2s";
	simple-audio-card,bitclock-master = <&sndcodec>;
	simple-audio-card,frame-master = <&sndcodec>;

	sndcpu: simple-audio-card,cpu {
	sound-dai = <&rcar_sound>;
	};

	sndcodec: simple-audio-card,codec {
	sound-dai = <&sgtl5000>;
	};
	};

	vccq_sdhi0: regulator-vccq-sdhi0 {
	compatible = "regulator-gpio";

	regulator-name = "SDHI0 VccQ";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
	gpios-states = <1>;
	states = <3300000 1>, <1800000 0>;
	};
	+
	+ vccq_panel: regulator-vccq-panel {
	+ compatible = "regulator-fixed";
	+ regulator-name = "Panel VccQ";
	+ regulator-min-microvolt = <3300000>;
	+ regulator-max-microvolt = <3300000>;
	+ gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
	+ enable-active-high;
	+ };
	+
	+ backlight_lcd: backlight {
	+ compatible = "pwm-backlight";
	+ pwms = <&tpu 3 5000000 PWM_POLARITY_INVERTED>;
	+ brightness-levels = <0 4 8 16 32 64 128 255>;
	+ default-brightness-level = <7>;
	+ };
	+
	+ lcd_panel: lcd {
	+ compatible = "edt,etm043080dh6gp";
	+ power-supply = <&vccq_panel>;
	+ backlight = <&backlight_lcd>;
	+
	+ port {
	+ lcd_in: endpoint {
	+ remote-endpoint = <&du_out_rgb0>;
	+ };
	+ };
	+ };
	+};
	+
	+&du {
	+ pinctrl-0 = <&du0_pins>;
	+ pinctrl-names = "default";
	+
	+ status = "okay";
	+
	+ ports {
	+ port@0 {
	+ endpoint {
	+ remote-endpoint = <&lcd_in>;
	+ };
	+ };
	+ };
	};

	&avb {
	pinctrl-0 = <&avb_pins>;
	pinctrl-names = "default";

	phy-handle = <&phy3>;
	phy-mode = "gmii";
	renesas,no-ether-link;
	status = "okay";

	phy3: ethernet-phy@3 {
	/*
	* On some older versions of the platform (before R4.0) the phy address
	* may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
	*/
	reg = <3>;
	micrel,led-mode = <1>;
	};
	};

	&can0 {
	pinctrl-0 = <&can0_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&hscif1 {
	pinctrl-0 = <&hscif1_pins>;
	pinctrl-names = "default";

	uart-has-rtscts;
	status = "okay";
	};

	&hsusb {
	status = "okay";
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";
	};

	&i2c5 {
	pinctrl-0 = <&i2c5_pins>;
	pinctrl-names = "default";

	status = "okay";
	clock-frequency = <400000>;

	+ stmpe811@44 {
	+ compatible = "st,stmpe811";
	+ reg = <0x44>;
	+ interrupt-parent = <&gpio4>;
	+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
	+
	+ /* 3.25 MHz ADC clock speed */
	+ st,adc-freq = <1>;
	+ /* ADC converstion time: 80 clocks */
	+ st,sample-time = <4>;
	+ /* 12-bit ADC */
	+ st,mod-12b = <1>;
	+ /* internal ADC reference */
	+ st,ref-sel = <0>;
	+
	+ stmpe_touchscreen {
	+ compatible = "st,stmpe-ts";
	+ /* 8 sample average control */
	+ st,ave-ctrl = <3>;
	+ /* 7 length fractional part in z */
	+ st,fraction-z = <7>;
	+ /*
	+ * 50 mA typical 80 mA max touchscreen drivers
	+ * current limit value
	+ */
	+ st,i-drive = <1>;
	+ /* 1 ms panel driver settling time */
	+ st,settling = <3>;
	+ /* 5 ms touch detect interrupt delay */
	+ st,touch-det-delay = <5>;
	+ };
	+ };
	+
	sgtl5000: codec@a {
	compatible = "fsl,sgtl5000";
	#sound-dai-cells = <0>;
	reg = <0x0a>;
	clocks = <&audio_clock>;
	VDDA-supply = <&reg_3p3v>;
	VDDIO-supply = <&reg_3p3v>;
	};
	};

	&pci1 {
	status = "okay";
	pinctrl-0 = <&usb1_pins>;
	pinctrl-names = "default";
	};

	&pfc {
	avb_pins: avb {
	groups = "avb_mdio", "avb_gmii";
	function = "avb";
	};

	+ backlight_pins: backlight {
	+ groups = "tpu_to3_c";
	+ function = "tpu";
	+ };
	+
	can0_pins: can0 {
	groups = "can0_data";
	function = "can0";
	};

	+ du0_pins: du0 {
	+ groups = "du0_rgb666", "du0_sync", "du0_disp", "du0_clk0_out";
	+ function = "du0";
	+ };
	+
	hscif1_pins: hscif1 {
	groups = "hscif1_data", "hscif1_ctrl";
	function = "hscif1";
	};

	i2c5_pins: i2c5 {
	groups = "i2c5_b";
	function = "i2c5";
	};

	scif4_pins: scif4 {
	groups = "scif4_data_b";
	function = "scif4";
	};

	sdhi0_pins: sd0 {
	groups = "sdhi0_data4", "sdhi0_ctrl";
	function = "sdhi0";
	power-source = <3300>;
	};

	sound_pins: sound {
	groups = "ssi34_ctrl", "ssi3_data", "ssi4_data";
	function = "ssi";
	};

	usb0_pins: usb0 {
	groups = "usb0";
	function = "usb0";
	};

	usb1_pins: usb1 {
	groups = "usb1";
	function = "usb1";
	};
	};

	&rcar_sound {
	pinctrl-0 = <&sound_pins>;
	pinctrl-names = "default";
	status = "okay";

	/* Single DAI */

	#sound-dai-cells = <0>;

	rcar_sound,dai {
	dai0 {
	playback = <&ssi3 &src3 &dvc0>;
	capture = <&ssi4 &src4 &dvc1>;
	};
	};
	};

	&scif4 {
	pinctrl-0 = <&scif4_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&vccq_sdhi0>;
	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&ssi4 {
	shared-pin;
	};

	+&tpu {
	+ pinctrl-0 = <&backlight_pins>;
	+ pinctrl-names = "default";
	+ status = "okay";
	+};
	+
	&usbphy {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/r8a7745.dtsi b/sys/gnu/dts/arm/r8a7745.dtsi
	index 3f88a7e34af2..7ab58d8bb740 100644
	--- a/sys/gnu/dts/arm/r8a7745.dtsi
	+++ b/sys/gnu/dts/arm/r8a7745.dtsi
	@@ -1,1585 +1,1586 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the r8a7745 SoC
	*
	* Copyright (C) 2016-2017 Cogent Embedded Inc.
	*/

	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/r8a7745-cpg-mssr.h>
	#include <dt-bindings/power/r8a7745-sysc.h>

	/ {
	compatible = "renesas,r8a7745";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	i2c6 = &iic0;
	i2c7 = &iic1;
	spi0 = &qspi;
	spi1 = &msiof0;
	spi2 = &msiof1;
	spi3 = &msiof2;
	vin0 = &vin0;
	vin1 = &vin1;
	};

	/*
	* The external audio clocks are configured as 0 Hz fixed
	* frequency clocks by default. Boards that provide audio
	* clocks should override them.
	*/
	audio_clka: audio_clka {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	audio_clkb: audio_clkb {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	audio_clkc: audio_clkc {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	/* External CAN clock */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "renesas,apmu";

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0>;
	clock-frequency = <1000000000>;
	clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
	power-domains = <&sysc R8A7745_PD_CA7_CPU0>;
	next-level-cache = <&L2_CA7>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <1>;
	clock-frequency = <1000000000>;
	clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
	power-domains = <&sysc R8A7745_PD_CA7_CPU1>;
	next-level-cache = <&L2_CA7>;
	};

	L2_CA7: cache-controller-0 {
	compatible = "cache";
	cache-unified;
	cache-level = <2>;
	power-domains = <&sysc R8A7745_PD_CA7_SCU>;
	};
	};

	/* External root clock */
	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	pmu {
	compatible = "arm,cortex-a7-pmu";
	interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	/* External SCIF clock */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;

	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a7745",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a7745",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a7745",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a7745",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a7745",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a7745",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 28>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	gpio6: gpio@e6055400 {
	compatible = "renesas,gpio-r8a7745",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055400 0 0x50>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 192 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 905>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 905>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a7745";
	reg = <0 0xe6060000 0 0x11c>;
	};

	tpu: pwm@e60f0000 {
	compatible = "renesas,tpu-r8a7745", "renesas,tpu";
	reg = <0 0xe60f0000 0 0x148>;
	clocks = <&cpg CPG_MOD 304>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 304>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a7745-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>, <&usb_extal_clk>;
	clock-names = "extal", "usb_extal";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	apmu@e6151000 {
	compatible = "renesas,r8a7745-apmu", "renesas,apmu";
	reg = <0 0xe6151000 0 0x188>;
	cpus = <&cpu0 &cpu1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a7745-rst";
	reg = <0 0xe6160000 0 0x100>;
	};

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a7745-wdt",
	"renesas,rcar-gen2-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a7745-sysc";
	reg = <0 0xe6180000 0 0x200>;
	#power-domain-cells = <1>;
	};

	irqc: interrupt-controller@e61c0000 {
	compatible = "renesas,irqc-r8a7745", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	ipmmu_sy0: mmu@e6280000 {
	compatible = "renesas,ipmmu-r8a7745",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6280000 0 0x1000>;
	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_sy1: mmu@e6290000 {
	compatible = "renesas,ipmmu-r8a7745",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6290000 0 0x1000>;
	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_ds: mmu@e6740000 {
	compatible = "renesas,ipmmu-r8a7745",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6740000 0 0x1000>;
	interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_mp: mmu@ec680000 {
	compatible = "renesas,ipmmu-r8a7745",
	"renesas,ipmmu-vmsa";
	reg = <0 0xec680000 0 0x1000>;
	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_mx: mmu@fe951000 {
	compatible = "renesas,ipmmu-r8a7745",
	"renesas,ipmmu-vmsa";
	reg = <0 0xfe951000 0 0x1000>;
	interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_gp: mmu@e62a0000 {
	compatible = "renesas,ipmmu-r8a7745",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe62a0000 0 0x1000>;
	interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	icram0: sram@e63a0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63a0000 0 0x12000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63a0000 0x12000>;
	};

	icram1: sram@e63c0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63c0000 0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63c0000 0x1000>;

	smp-sram@0 {
	compatible = "renesas,smp-sram";
	reg = <0 0x100>;
	};
	};

	icram2: sram@e6300000 {
	compatible = "mmio-sram";
	reg = <0 0xe6300000 0 0x40000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe6300000 0x40000>;
	};
	i2c0: i2c@e6508000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7745",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c1: i2c@e6518000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7745",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6518000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c2: i2c@e6530000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7745",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6530000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c3: i2c@e6540000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7745",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6540000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c4: i2c@e6520000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7745",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6520000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c5: i2c@e6528000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7745",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6528000 0 0x40>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 925>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 925>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	iic0: i2c@e6500000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7745",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe6500000 0 0x425>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 318>;
	dmas = <&dmac0 0x61>, <&dmac0 0x62>,
	<&dmac1 0x61>, <&dmac1 0x62>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 318>;
	status = "disabled";
	};

	iic1: i2c@e6510000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7745",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe6510000 0 0x425>;
	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 323>;
	dmas = <&dmac0 0x65>, <&dmac0 0x66>,
	<&dmac1 0x65>, <&dmac1 0x66>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 323>;
	status = "disabled";
	};

	hsusb: usb@e6590000 {
	compatible = "renesas,usbhs-r8a7745",
	"renesas,rcar-gen2-usbhs";
	reg = <0 0xe6590000 0 0x100>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 704>;
	dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
	<&usb_dmac1 0>, <&usb_dmac1 1>;
	dma-names = "ch0", "ch1", "ch2", "ch3";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 704>;
	renesas,buswait = <4>;
	phys = <&usb0 1>;
	phy-names = "usb";
	status = "disabled";
	};

	usbphy: usb-phy@e6590100 {
	compatible = "renesas,usb-phy-r8a7745",
	"renesas,rcar-gen2-usb-phy";
	reg = <0 0xe6590100 0 0x100>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cpg CPG_MOD 704>;
	clock-names = "usbhs";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 704>;
	status = "disabled";

	usb0: usb-channel@0 {
	reg = <0>;
	#phy-cells = <1>;
	};
	usb2: usb-channel@2 {
	reg = <2>;
	#phy-cells = <1>;
	};
	};

	usb_dmac0: dma-controller@e65a0000 {
	compatible = "renesas,r8a7745-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65a0000 0 0x100>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 330>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 330>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac1: dma-controller@e65b0000 {
	compatible = "renesas,r8a7745-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65b0000 0 0x100>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 331>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 331>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a7745",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x20000>;
	interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	dmac1: dma-controller@e6720000 {
	compatible = "renesas,dmac-r8a7745",
	"renesas,rcar-dmac";
	reg = <0 0xe6720000 0 0x20000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a7745",
	"renesas,etheravb-rcar-gen2";
	reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
	interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	qspi: spi@e6b10000 {
	compatible = "renesas,qspi-r8a7745", "renesas,qspi";
	reg = <0 0xe6b10000 0 0x2c>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 917>;
	dmas = <&dmac0 0x17>, <&dmac0 0x18>,
	<&dmac1 0x17>, <&dmac1 0x18>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	resets = <&cpg 917>;
	status = "disabled";
	};

	scifa0: serial@e6c40000 {
	compatible = "renesas,scifa-r8a7745",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c40000 0 0x40>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 204>;
	clock-names = "fck";
	dmas = <&dmac0 0x21>, <&dmac0 0x22>,
	<&dmac1 0x21>, <&dmac1 0x22>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 204>;
	status = "disabled";
	};

	scifa1: serial@e6c50000 {
	compatible = "renesas,scifa-r8a7745",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c50000 0 0x40>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 203>;
	clock-names = "fck";
	dmas = <&dmac0 0x25>, <&dmac0 0x26>,
	<&dmac1 0x25>, <&dmac1 0x26>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 203>;
	status = "disabled";
	};

	scifa2: serial@e6c60000 {
	compatible = "renesas,scifa-r8a7745",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c60000 0 0x40>;
	interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 202>;
	clock-names = "fck";
	dmas = <&dmac0 0x27>, <&dmac0 0x28>,
	<&dmac1 0x27>, <&dmac1 0x28>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 202>;
	status = "disabled";
	};

	scifa3: serial@e6c70000 {
	compatible = "renesas,scifa-r8a7745",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c70000 0 0x40>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1106>;
	clock-names = "fck";
	dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
	<&dmac1 0x1b>, <&dmac1 0x1c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 1106>;
	status = "disabled";
	};

	scifa4: serial@e6c78000 {
	compatible = "renesas,scifa-r8a7745",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c78000 0 0x40>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1107>;
	clock-names = "fck";
	dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
	<&dmac1 0x1f>, <&dmac1 0x20>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 1107>;
	status = "disabled";
	};

	scifa5: serial@e6c80000 {
	compatible = "renesas,scifa-r8a7745",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c80000 0 0x40>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1108>;
	clock-names = "fck";
	dmas = <&dmac0 0x23>, <&dmac0 0x24>,
	<&dmac1 0x23>, <&dmac1 0x24>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 1108>;
	status = "disabled";
	};

	scifb0: serial@e6c20000 {
	compatible = "renesas,scifb-r8a7745",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6c20000 0 0x100>;
	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 206>;
	clock-names = "fck";
	dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
	<&dmac1 0x3d>, <&dmac1 0x3e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 206>;
	status = "disabled";
	};

	scifb1: serial@e6c30000 {
	compatible = "renesas,scifb-r8a7745",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6c30000 0 0x100>;
	interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 207>;
	clock-names = "fck";
	dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
	<&dmac1 0x19>, <&dmac1 0x1a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 207>;
	status = "disabled";
	};

	scifb2: serial@e6ce0000 {
	compatible = "renesas,scifb-r8a7745",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6ce0000 0 0x100>;
	interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 216>;
	clock-names = "fck";
	dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
	<&dmac1 0x1d>, <&dmac1 0x1e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 216>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a7745",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e60000 0 0x40>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 721>,
	<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
	<&dmac1 0x29>, <&dmac1 0x2a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 721>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a7745",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e68000 0 0x40>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 720>,
	<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
	<&dmac1 0x2d>, <&dmac1 0x2e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 720>;
	status = "disabled";
	};

	scif2: serial@e6e58000 {
	compatible = "renesas,scif-r8a7745",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e58000 0 0x40>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 719>,
	<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
	<&dmac1 0x2b>, <&dmac1 0x2c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 719>;
	status = "disabled";
	};

	scif3: serial@e6ea8000 {
	compatible = "renesas,scif-r8a7745",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ea8000 0 0x40>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 718>,
	<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
	<&dmac1 0x2f>, <&dmac1 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 718>;
	status = "disabled";
	};

	scif4: serial@e6ee0000 {
	compatible = "renesas,scif-r8a7745",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ee0000 0 0x40>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 715>,
	<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
	<&dmac1 0xfb>, <&dmac1 0xfc>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 715>;
	status = "disabled";
	};

	scif5: serial@e6ee8000 {
	compatible = "renesas,scif-r8a7745",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ee8000 0 0x40>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 714>,
	<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
	<&dmac1 0xfd>, <&dmac1 0xfe>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 714>;
	status = "disabled";
	};

	hscif0: serial@e62c0000 {
	compatible = "renesas,hscif-r8a7745",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c0000 0 0x60>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 717>,
	<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
	<&dmac1 0x39>, <&dmac1 0x3a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 717>;
	status = "disabled";
	};

	hscif1: serial@e62c8000 {
	compatible = "renesas,hscif-r8a7745",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c8000 0 0x60>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>,
	<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
	<&dmac1 0x4d>, <&dmac1 0x4e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";
	};

	hscif2: serial@e62d0000 {
	compatible = "renesas,hscif-r8a7745",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62d0000 0 0x60>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 713>,
	<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
	<&dmac1 0x3b>, <&dmac1 0x3c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 713>;
	status = "disabled";
	};

	msiof0: spi@e6e20000 {
	compatible = "renesas,msiof-r8a7745",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6e20000 0 0x0064>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 000>;
	dmas = <&dmac0 0x51>, <&dmac0 0x52>,
	<&dmac1 0x51>, <&dmac1 0x52>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	#address-cells = <1>;
	#size-cells = <0>;
	resets = <&cpg 000>;
	status = "disabled";
	};

	msiof1: spi@e6e10000 {
	compatible = "renesas,msiof-r8a7745",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6e10000 0 0x0064>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 208>;
	dmas = <&dmac0 0x55>, <&dmac0 0x56>,
	<&dmac1 0x55>, <&dmac1 0x56>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	#address-cells = <1>;
	#size-cells = <0>;
	resets = <&cpg 208>;
	status = "disabled";
	};

	msiof2: spi@e6e00000 {
	compatible = "renesas,msiof-r8a7745",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6e00000 0 0x0064>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 205>;
	dmas = <&dmac0 0x41>, <&dmac0 0x42>,
	<&dmac1 0x41>, <&dmac1 0x42>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	#address-cells = <1>;
	#size-cells = <0>;
	resets = <&cpg 205>;
	status = "disabled";
	};

	pwm0: pwm@e6e30000 {
	compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
	reg = <0 0xe6e30000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm1: pwm@e6e31000 {
	compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
	reg = <0 0xe6e31000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm2: pwm@e6e32000 {
	compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
	reg = <0 0xe6e32000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm3: pwm@e6e33000 {
	compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
	reg = <0 0xe6e33000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm4: pwm@e6e34000 {
	compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
	reg = <0 0xe6e34000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm5: pwm@e6e35000 {
	compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
	reg = <0 0xe6e35000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm6: pwm@e6e36000 {
	compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
	reg = <0 0xe6e36000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	can0: can@e6e80000 {
	compatible = "renesas,can-r8a7745",
	"renesas,rcar-gen2-can";
	reg = <0 0xe6e80000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 916>,
	<&cpg CPG_CORE R8A7745_CLK_RCAN>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 916>;
	status = "disabled";
	};

	can1: can@e6e88000 {
	compatible = "renesas,can-r8a7745",
	"renesas,rcar-gen2-can";
	reg = <0 0xe6e88000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 915>,
	<&cpg CPG_CORE R8A7745_CLK_RCAN>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 915>;
	status = "disabled";
	};

	vin0: video@e6ef0000 {
	compatible = "renesas,vin-r8a7745",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef0000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 811>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 811>;
	status = "disabled";
	};

	vin1: video@e6ef1000 {
	compatible = "renesas,vin-r8a7745",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef1000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 810>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 810>;
	status = "disabled";
	};

	rcar_sound: sound@ec500000 {
	/*
	* #sound-dai-cells is required
	*
	* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
	* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
	*/
	compatible = "renesas,rcar_sound-r8a7745",
	"renesas,rcar_sound-gen2";
	reg = <0 0xec500000 0 0x1000>, /* SCU */
	<0 0xec5a0000 0 0x100>, /* ADG */
	<0 0xec540000 0 0x1000>, /* SSIU */
	<0 0xec541000 0 0x280>, /* SSI */
	<0 0xec740000 0 0x200>; /* Audio DMAC peri peri */
	reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

	clocks = <&cpg CPG_MOD 1005>,
	<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	<&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
	<&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
	<&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
	<&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
	<&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
	<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	<&audio_clka>, <&audio_clkb>, <&audio_clkc>,
	<&cpg CPG_CORE R8A7745_CLK_M2>;
	clock-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0",
	"src.6", "src.5", "src.4", "src.3",
	"src.2", "src.1",
	"ctu.0", "ctu.1",
	"mix.0", "mix.1",
	"dvc.0", "dvc.1",
	"clk_a", "clk_b", "clk_c", "clk_i";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 1005>,
	<&cpg 1006>, <&cpg 1007>, <&cpg 1008>,
	<&cpg 1009>, <&cpg 1010>, <&cpg 1011>,
	<&cpg 1012>, <&cpg 1013>, <&cpg 1014>,
	<&cpg 1015>;
	reset-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0";

	status = "disabled";

	rcar_sound,dvc {
	dvc0: dvc-0 {
	dmas = <&audma0 0xbc>;
	dma-names = "tx";
	};
	dvc1: dvc-1 {
	dmas = <&audma0 0xbe>;
	dma-names = "tx";
	};
	};

	rcar_sound,mix {
	mix0: mix-0 { };
	mix1: mix-1 { };
	};

	rcar_sound,ctu {
	ctu00: ctu-0 { };
	ctu01: ctu-1 { };
	ctu02: ctu-2 { };
	ctu03: ctu-3 { };
	ctu10: ctu-4 { };
	ctu11: ctu-5 { };
	ctu12: ctu-6 { };
	ctu13: ctu-7 { };
	};

	rcar_sound,src {
	src-0 {
	status = "disabled";
	};
	src1: src-1 {
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x87>, <&audma0 0x9c>;
	dma-names = "rx", "tx";
	};
	src2: src-2 {
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x89>, <&audma0 0x9e>;
	dma-names = "rx", "tx";
	};
	src3: src-3 {
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8b>, <&audma0 0xa0>;
	dma-names = "rx", "tx";
	};
	src4: src-4 {
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8d>, <&audma0 0xb0>;
	dma-names = "rx", "tx";
	};
	src5: src-5 {
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8f>, <&audma0 0xb2>;
	dma-names = "rx", "tx";
	};
	src6: src-6 {
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x91>, <&audma0 0xb4>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssi {
	ssi0: ssi-0 {
	interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x01>, <&audma0 0x02>,
	<&audma0 0x15>, <&audma0 0x16>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi1: ssi-1 {
	interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x03>, <&audma0 0x04>,
	<&audma0 0x49>, <&audma0 0x4a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi2: ssi-2 {
	interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x05>, <&audma0 0x06>,
	<&audma0 0x63>, <&audma0 0x64>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi3: ssi-3 {
	interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x07>, <&audma0 0x08>,
	<&audma0 0x6f>, <&audma0 0x70>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi4: ssi-4 {
	interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x09>, <&audma0 0x0a>,
	<&audma0 0x71>, <&audma0 0x72>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi5: ssi-5 {
	interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0b>, <&audma0 0x0c>,
	<&audma0 0x73>, <&audma0 0x74>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi6: ssi-6 {
	interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0d>, <&audma0 0x0e>,
	<&audma0 0x75>, <&audma0 0x76>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi7: ssi-7 {
	interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0f>, <&audma0 0x10>,
	<&audma0 0x79>, <&audma0 0x7a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi8: ssi-8 {
	interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x11>, <&audma0 0x12>,
	<&audma0 0x7b>, <&audma0 0x7c>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi9: ssi-9 {
	interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x13>, <&audma0 0x14>,
	<&audma0 0x7d>, <&audma0 0x7e>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	};
	};

	audma0: dma-controller@ec700000 {
	compatible = "renesas,dmac-r8a7745",
	"renesas,rcar-dmac";
	reg = <0 0xec700000 0 0x10000>;
	interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12";
	clocks = <&cpg CPG_MOD 502>;
	clock-names = "fck";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 502>;
	#dma-cells = <1>;
	dma-channels = <13>;
	};

	pci0: pci@ee090000 {
	compatible = "renesas,pci-r8a7745",
	"renesas,pci-rcar-gen2";
	device_type = "pci";
	reg = <0 0xee090000 0 0xc00>,
	<0 0xee080000 0 0x1100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 703>;
	status = "disabled";

	bus-range = <0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
	interrupt-map-mask = <0xf800 0 0 0x7>;
	interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

	usb@1,0 {
	reg = <0x800 0 0 0 0>;
	phys = <&usb0 0>;
	phy-names = "usb";
	};

	usb@2,0 {
	reg = <0x1000 0 0 0 0>;
	phys = <&usb0 0>;
	phy-names = "usb";
	};
	};

	pci1: pci@ee0d0000 {
	compatible = "renesas,pci-r8a7745",
	"renesas,pci-rcar-gen2";
	device_type = "pci";
	reg = <0 0xee0d0000 0 0xc00>,
	<0 0xee0c0000 0 0x1100>;
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 703>;
	status = "disabled";

	bus-range = <1 1>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
	interrupt-map-mask = <0xf800 0 0 0x7>;
	interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

	usb@1,0 {
	reg = <0x10800 0 0 0 0>;
	phys = <&usb2 0>;
	phy-names = "usb";
	};

	usb@2,0 {
	reg = <0x11000 0 0 0 0>;
	phys = <&usb2 0>;
	phy-names = "usb";
	};
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a7745",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee100000 0 0x328>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
	<&dmac1 0xcd>, <&dmac1 0xce>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <195000000>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	status = "disabled";
	};

	sdhi1: sd@ee140000 {
	compatible = "renesas,sdhi-r8a7745",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee140000 0 0x100>;
	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 312>;
	dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
	<&dmac1 0xc1>, <&dmac1 0xc2>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <97500000>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 312>;
	status = "disabled";
	};

	sdhi2: sd@ee160000 {
	compatible = "renesas,sdhi-r8a7745",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee160000 0 0x100>;
	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 311>;
	dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
	<&dmac1 0xd3>, <&dmac1 0xd4>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <97500000>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 311>;
	status = "disabled";
	};

	mmcif0: mmc@ee200000 {
	compatible = "renesas,mmcif-r8a7745",
	"renesas,sh-mmcif";
	reg = <0 0xee200000 0 0x80>;
	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 315>;
	dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
	<&dmac1 0xd1>, <&dmac1 0xd2>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 315>;
	reg-io-width = <4>;
	max-frequency = <97500000>;
	status = "disabled";
	};

	ether: ethernet@ee700000 {
	compatible = "renesas,ether-r8a7745",
	"renesas,rcar-gen2-ether";
	reg = <0 0xee700000 0 0x400>;
	interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 813>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 813>;
	phy-mode = "rmii";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	gic: interrupt-controller@f1001000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
	<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	vsp@fe928000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe928000 0 0x8000>;
	interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 131>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 131>;
	};

	vsp@fe930000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe930000 0 0x8000>;
	interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 128>;
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 128>;
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a7745";
	reg = <0 0xfeb00000 0 0x40000>;
	- reg-names = "du";
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
	clock-names = "du.0", "du.1";
	+ resets = <&cpg 724>;
	+ reset-names = "du.0";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb0: endpoint {
	};
	};
	port@1 {
	reg = <1>;
	du_out_rgb1: endpoint {
	};
	};
	};
	};

	prr: chipid@ff000044 {
	compatible = "renesas,prr";
	reg = <0 0xff000044 0 4>;
	};

	cmt0: timer@ffca0000 {
	compatible = "renesas,r8a7745-cmt0",
	"renesas,rcar-gen2-cmt0";
	reg = <0 0xffca0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 124>;
	clock-names = "fck";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 124>;
	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a7745-cmt1",
	"renesas,rcar-gen2-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 329>;
	clock-names = "fck";
	power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
	resets = <&cpg 329>;
	status = "disabled";
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clock - can be overridden by the board */
	usb_extal_clk: usb_extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <48000000>;
	};
	};
	diff --git a/sys/gnu/dts/arm/r8a77470.dtsi b/sys/gnu/dts/arm/r8a77470.dtsi
	index 6efcef1670e1..f55153192276 100644
	--- a/sys/gnu/dts/arm/r8a77470.dtsi
	+++ b/sys/gnu/dts/arm/r8a77470.dtsi
	@@ -1,1024 +1,1025 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the r8a77470 SoC
	*
	* Copyright (C) 2018 Renesas Electronics Corp.
	*/

	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/r8a77470-cpg-mssr.h>
	#include <dt-bindings/power/r8a77470-sysc.h>
	/ {
	compatible = "renesas,r8a77470";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "renesas,apmu";

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0>;
	clock-frequency = <1000000000>;
	clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
	power-domains = <&sysc R8A77470_PD_CA7_CPU0>;
	next-level-cache = <&L2_CA7>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <1>;
	clock-frequency = <1000000000>;
	clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
	power-domains = <&sysc R8A77470_PD_CA7_CPU1>;
	next-level-cache = <&L2_CA7>;
	};

	L2_CA7: cache-controller-0 {
	compatible = "cache";
	cache-unified;
	cache-level = <2>;
	power-domains = <&sysc R8A77470_PD_CA7_SCU>;
	};
	};

	/* External root clock */
	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	pmu {
	compatible = "arm,cortex-a7-pmu";
	interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	/* External SCIF clock */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;

	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a77470-wdt",
	"renesas,rcar-gen2-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a77470",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 23>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a77470",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 23>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a77470",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a77470",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 30>;
	gpio-reserved-ranges = <17 10>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a77470",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a77470",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a77470";
	reg = <0 0xe6060000 0 0x118>;
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a77470-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>, <&usb_extal_clk>;
	clock-names = "extal", "usb_extal";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	apmu@e6151000 {
	compatible = "renesas,r8a77470-apmu", "renesas,apmu";
	reg = <0 0xe6151000 0 0x188>;
	cpus = <&cpu0 &cpu1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a77470-rst";
	reg = <0 0xe6160000 0 0x100>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a77470-sysc";
	reg = <0 0xe6180000 0 0x200>;
	#power-domain-cells = <1>;
	};

	irqc: interrupt-controller@e61c0000 {
	compatible = "renesas,irqc-r8a77470", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	icram0: sram@e63a0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63a0000 0 0x12000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63a0000 0x12000>;
	};

	icram1: sram@e63c0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63c0000 0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63c0000 0x1000>;

	smp-sram@0 {
	compatible = "renesas,smp-sram";
	reg = <0 0x100>;
	};
	};

	icram2: sram@e6300000 {
	compatible = "mmio-sram";
	reg = <0 0xe6300000 0 0x20000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe6300000 0x20000>;
	};

	i2c0: i2c@e6508000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77470",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c1: i2c@e6518000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77470",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6518000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c2: i2c@e6530000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77470",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6530000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c3: i2c@e6540000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77470",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6540000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c4: i2c@e6520000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77470",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6520000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	hsusb0: hsusb@e6590000 {
	compatible = "renesas,usbhs-r8a77470",
	"renesas,rcar-gen2-usbhs";
	reg = <0 0xe6590000 0 0x100>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 704>;
	dmas = <&usb_dmac00 0>, <&usb_dmac00 1>,
	<&usb_dmac10 0>, <&usb_dmac10 1>;
	dma-names = "ch0", "ch1", "ch2", "ch3";
	renesas,buswait = <4>;
	phys = <&usb0 1>;
	phy-names = "usb";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 704>;
	status = "disabled";
	};

	usbphy0: usb-phy@e6590100 {
	compatible = "renesas,usb-phy-r8a77470",
	"renesas,rcar-gen2-usb-phy";
	reg = <0 0xe6590100 0 0x100>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cpg CPG_MOD 704>;
	clock-names = "usbhs";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 704>;
	status = "disabled";

	usb0: usb-channel@0 {
	reg = <0>;
	#phy-cells = <1>;
	};
	};

	hsusb1: hsusb@e6598000 {
	compatible = "renesas,usbhs-r8a77470",
	"renesas,rcar-gen2-usbhs";
	reg = <0 0xe6598000 0 0x100>;
	interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 706>;
	dmas = <&usb_dmac01 0>, <&usb_dmac01 1>,
	<&usb_dmac11 0>, <&usb_dmac11 1>;
	dma-names = "ch0", "ch1", "ch2", "ch3";
	renesas,buswait = <4>;
	/* We need to turn on usbphy0 to make usbphy1 to work */
	phys = <&usb1 1>;
	phy-names = "usb";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 706>;
	status = "disabled";
	};

	usbphy1: usb-phy@e6598100 {
	compatible = "renesas,usb-phy-r8a77470",
	"renesas,rcar-gen2-usb-phy";
	reg = <0 0xe6598100 0 0x100>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cpg CPG_MOD 706>;
	clock-names = "usbhs";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 706>;
	status = "disabled";

	usb1: usb-channel@0 {
	reg = <0>;
	#phy-cells = <1>;
	};
	};

	usb_dmac00: dma-controller@e65a0000 {
	compatible = "renesas,r8a77470-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65a0000 0 0x100>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 330>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 330>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac10: dma-controller@e65b0000 {
	compatible = "renesas,r8a77470-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65b0000 0 0x100>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 331>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 331>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac01: dma-controller@e65a8000 {
	compatible = "renesas,r8a77470-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65a8000 0 0x100>;
	interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 326>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 326>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac11: dma-controller@e65b8000 {
	compatible = "renesas,r8a77470-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65b8000 0 0x100>;
	interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 327>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 327>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a77470",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x20000>;
	interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	dmac1: dma-controller@e6720000 {
	compatible = "renesas,dmac-r8a77470",
	"renesas,rcar-dmac";
	reg = <0 0xe6720000 0 0x20000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a77470",
	"renesas,etheravb-rcar-gen2";
	reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
	interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	qspi0: spi@e6b10000 {
	compatible = "renesas,qspi-r8a77470", "renesas,qspi";
	reg = <0 0xe6b10000 0 0x2c>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 918>;
	dmas = <&dmac0 0x17>, <&dmac0 0x18>,
	<&dmac1 0x17>, <&dmac1 0x18>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	resets = <&cpg 918>;
	status = "disabled";
	};

	qspi1: spi@ee200000 {
	compatible = "renesas,qspi-r8a77470", "renesas,qspi";
	reg = <0 0xee200000 0 0x2c>;
	interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 917>;
	dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
	<&dmac1 0xd1>, <&dmac1 0xd2>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	resets = <&cpg 917>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a77470",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e60000 0 0x40>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 721>,
	<&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
	<&dmac1 0x29>, <&dmac1 0x2a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 721>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a77470",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e68000 0 0x40>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 720>,
	<&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
	<&dmac1 0x2d>, <&dmac1 0x2e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 720>;
	status = "disabled";
	};

	scif2: serial@e6e58000 {
	compatible = "renesas,scif-r8a77470",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e58000 0 0x40>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 719>,
	<&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
	<&dmac1 0x2b>, <&dmac1 0x2c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 719>;
	status = "disabled";
	};

	scif3: serial@e6ea8000 {
	compatible = "renesas,scif-r8a77470",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ea8000 0 0x40>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 718>,
	<&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
	<&dmac1 0x2f>, <&dmac1 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 718>;
	status = "disabled";
	};

	scif4: serial@e6ee0000 {
	compatible = "renesas,scif-r8a77470",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ee0000 0 0x40>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 715>,
	<&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
	<&dmac1 0xfb>, <&dmac1 0xfc>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 715>;
	status = "disabled";
	};

	scif5: serial@e6ee8000 {
	compatible = "renesas,scif-r8a77470",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ee8000 0 0x40>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 714>,
	<&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
	<&dmac1 0xfd>, <&dmac1 0xfe>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 714>;
	status = "disabled";
	};

	hscif0: serial@e62c0000 {
	compatible = "renesas,hscif-r8a77470",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c0000 0 0x60>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 717>,
	<&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
	<&dmac1 0x39>, <&dmac1 0x3a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 717>;
	status = "disabled";
	};

	hscif1: serial@e62c8000 {
	compatible = "renesas,hscif-r8a77470",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c8000 0 0x60>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>,
	<&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
	<&dmac1 0x4d>, <&dmac1 0x4e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";
	};

	hscif2: serial@e62d0000 {
	compatible = "renesas,hscif-r8a77470",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62d0000 0 0x60>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 713>,
	<&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
	<&dmac1 0x3b>, <&dmac1 0x3c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 713>;
	status = "disabled";
	};

	pwm0: pwm@e6e30000 {
	compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
	reg = <0 0xe6e30000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm1: pwm@e6e31000 {
	compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
	reg = <0 0xe6e31000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm2: pwm@e6e32000 {
	compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
	reg = <0 0xe6e32000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm3: pwm@e6e33000 {
	compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
	reg = <0 0xe6e33000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm4: pwm@e6e34000 {
	compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
	reg = <0 0xe6e34000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm5: pwm@e6e35000 {
	compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
	reg = <0 0xe6e35000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm6: pwm@e6e36000 {
	compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
	reg = <0 0xe6e36000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	vin0: video@e6ef0000 {
	compatible = "renesas,vin-r8a77470",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef0000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 811>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 811>;
	status = "disabled";
	};

	vin1: video@e6ef1000 {
	compatible = "renesas,vin-r8a77470",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef1000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 810>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 810>;
	status = "disabled";
	};

	ohci0: usb@ee080000 {
	compatible = "generic-ohci";
	reg = <0 0xee080000 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>;
	phys = <&usb0 0>, <&usb2_phy0>;
	phy-names = "usb";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 703>;
	status = "disabled";
	};

	ehci0: usb@ee080100 {
	compatible = "generic-ehci";
	reg = <0 0xee080100 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>;
	phys = <&usb0 0>, <&usb2_phy0>;
	phy-names = "usb";
	companion = <&ohci0>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 703>;
	status = "disabled";
	};

	usb2_phy0: usb-phy@ee080200 {
	compatible = "renesas,usb2-phy-r8a77470";
	reg = <0 0xee080200 0 0x700>;
	clocks = <&cpg CPG_MOD 703>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 703>;
	#phy-cells = <0>;
	status = "disabled";
	};

	ohci1: usb@ee0c0000 {
	compatible = "generic-ohci";
	reg = <0 0xee0c0000 0 0x100>;
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 705>;
	phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>;
	phy-names = "usb";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 705>;
	status = "disabled";
	};

	ehci1: usb@ee0c0100 {
	compatible = "generic-ehci";
	reg = <0 0xee0c0100 0 0x100>;
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 705>;
	phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>;
	phy-names = "usb";
	companion = <&ohci1>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 705>;
	status = "disabled";
	};

	usb2_phy1: usb-phy@ee0c0200 {
	compatible = "renesas,usb2-phy-r8a77470";
	reg = <0 0xee0c0200 0 0x700>;
	clocks = <&cpg CPG_MOD 705>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 705>;
	#phy-cells = <0>;
	status = "disabled";
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a77470",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee100000 0 0x328>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
	<&dmac1 0xcd>, <&dmac1 0xce>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <156000000>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	status = "disabled";
	};

	sdhi1: sd@ee300000 {
	compatible = "renesas,sdhi-mmc-r8a77470";
	reg = <0 0xee300000 0 0x2000>;
	interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 313>;
	max-frequency = <156000000>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 313>;
	status = "disabled";
	};

	sdhi2: sd@ee160000 {
	compatible = "renesas,sdhi-r8a77470",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee160000 0 0x328>;
	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 312>;
	dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
	<&dmac1 0xd3>, <&dmac1 0xd4>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <78000000>;
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 312>;
	status = "disabled";
	};

	gic: interrupt-controller@f1001000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
	<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a77470";
	reg = <0 0xfeb00000 0 0x40000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&cpg CPG_MOD 724>,
	- <&cpg CPG_MOD 723>;
	+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
	clock-names = "du.0", "du.1";
	+ resets = <&cpg 724>;
	+ reset-names = "du.0";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb0: endpoint {
	};
	};
	port@1 {
	reg = <1>;
	du_out_rgb1: endpoint {
	};
	};
	port@2 {
	reg = <2>;
	du_out_lvds0: endpoint {
	};
	};
	};
	};

	prr: chipid@ff000044 {
	compatible = "renesas,prr";
	reg = <0 0xff000044 0 4>;
	};

	cmt0: timer@ffca0000 {
	compatible = "renesas,r8a77470-cmt0",
	"renesas,rcar-gen2-cmt0";
	reg = <0 0xffca0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 124>;
	clock-names = "fck";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 124>;
	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a77470-cmt1",
	"renesas,rcar-gen2-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 329>;
	clock-names = "fck";
	power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
	resets = <&cpg 329>;
	status = "disabled";
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clock - can be overridden by the board */
	usb_extal_clk: usb_extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <48000000>;
	};
	};
	diff --git a/sys/gnu/dts/arm/r8a7790-lager.dts b/sys/gnu/dts/arm/r8a7790-lager.dts
	index 097fd9317c6e..bfe778c4c47b 100644
	--- a/sys/gnu/dts/arm/r8a7790-lager.dts
	+++ b/sys/gnu/dts/arm/r8a7790-lager.dts
	@@ -1,936 +1,935 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the Lager board
	*
	* Copyright (C) 2013-2014 Renesas Solutions Corp.
	* Copyright (C) 2014 Cogent Embedded, Inc.
	* Copyright (C) 2015-2016 Renesas Electronics Corporation
	*/

	/*
	* SSI-AK4643
	*
	* SW1: 1: AK4643
	* 2: CN22
	* 3: ADV7511
	*
	* This command is required when Playback/Capture
	*
	* amixer set "LINEOUT Mixer DACL" on
	* amixer set "DVC Out" 100%
	* amixer set "DVC In" 100%
	*
	* You can use Mute
	*
	* amixer set "DVC Out Mute" on
	* amixer set "DVC In Mute" on
	*
	* You can use Volume Ramp
	*
	* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
	* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
	* amixer set "DVC Out Ramp" on
	* aplay xxx.wav &
	* amixer set "DVC Out" 80% // Volume Down
	* amixer set "DVC Out" 100% // Volume Up
	*/

	/dts-v1/;
	#include "r8a7790.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>

	/ {
	model = "Lager";
	compatible = "renesas,lager", "renesas,r8a7790";

	aliases {
	serial0 = &scif0;
	serial1 = &scifa1;
	i2c8 = &gpioi2c1;
	i2c9 = &gpioi2c2;
	i2c10 = &i2cexio0;
	i2c11 = &i2cexio1;
	i2c12 = &i2chdmi;
	i2c13 = &i2cpwr;
	};

	chosen {
	bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
	stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
	device_type = "memory";
	reg = <0 0x40000000 0 0x40000000>;
	};

	memory@140000000 {
	device_type = "memory";
	reg = <1 0x40000000 0 0xc0000000>;
	};

	lbsc {
	#address-cells = <1>;
	#size-cells = <1>;
	};

	keyboard {
	compatible = "gpio-keys";

	one {
	linux,code = <KEY_1>;
	label = "SW2-1";
	wakeup-source;
	debounce-interval = <20>;
	gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
	};
	two {
	linux,code = <KEY_2>;
	label = "SW2-2";
	wakeup-source;
	debounce-interval = <20>;
	gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
	};
	three {
	linux,code = <KEY_3>;
	label = "SW2-3";
	wakeup-source;
	debounce-interval = <20>;
	gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
	};
	four {
	linux,code = <KEY_4>;
	label = "SW2-4";
	wakeup-source;
	debounce-interval = <20>;
	gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
	};
	};

	leds {
	compatible = "gpio-leds";
	led6 {
	gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
	};
	led7 {
	gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
	};
	led8 {
	gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
	};
	};

	fixedregulator3v3: regulator-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "fixed-3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vcc_sdhi0: regulator-vcc-sdhi0 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI0 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vccq_sdhi0: regulator-vccq-sdhi0 {
	compatible = "regulator-gpio";

	regulator-name = "SDHI0 VccQ";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
	gpios-states = <1>;
	states = <3300000 1>, <1800000 0>;
	};

	vcc_sdhi2: regulator-vcc-sdhi2 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI2 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vccq_sdhi2: regulator-vccq-sdhi2 {
	compatible = "regulator-gpio";

	regulator-name = "SDHI2 VccQ";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
	gpios-states = <1>;
	states = <3300000 1>, <1800000 0>;
	};

	audio_clock: audio_clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <11289600>;
	};

	rsnd_ak4643: sound {
	compatible = "simple-audio-card";

	simple-audio-card,format = "left_j";
	simple-audio-card,bitclock-master = <&sndcodec>;
	simple-audio-card,frame-master = <&sndcodec>;

	sndcpu: simple-audio-card,cpu {
	sound-dai = <&rcar_sound>;
	};

	sndcodec: simple-audio-card,codec {
	sound-dai = <&ak4643>;
	clocks = <&audio_clock>;
	};
	};

	vga-encoder {
	compatible = "adi,adv7123";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7123_in: endpoint {
	remote-endpoint = <&du_out_rgb>;
	};
	};
	port@1 {
	reg = <1>;
	adv7123_out: endpoint {
	remote-endpoint = <&vga_in>;
	};
	};
	};
	};

	vga {
	compatible = "vga-connector";

	port {
	vga_in: endpoint {
	remote-endpoint = <&adv7123_out>;
	};
	};
	};

	hdmi-in {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con_in: endpoint {
	remote-endpoint = <&adv7612_in>;
	};
	};
	};

	cec_clock: cec-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <12000000>;
	};

	hdmi-out {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con_out: endpoint {
	remote-endpoint = <&adv7511_out>;
	};
	};
	};

	x2_clk: x2-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <148500000>;
	};

	x13_clk: x13-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <148500000>;
	};

	gpioi2c1: i2c-8 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "i2c-gpio";
	status = "disabled";
	scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	i2c-gpio,delay-us = <5>;
	};

	gpioi2c2: i2c-9 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "i2c-gpio";
	status = "disabled";
	scl-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 6 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	i2c-gpio,delay-us = <5>;
	};

	/*
	* IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only.
	* We use the I2C demuxer, so the desired IP core can be selected at runtime
	* depending on the use case (e.g. DMA with IIC0 or slave support with I2C0).
	* Note: For testing the I2C slave feature, it is convenient to connect this
	* bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and
	* instantiate the slave device at runtime according to the documentation.
	* You can then communicate with the slave via IIC3.
	*
	* IIC0/I2C0 does not appear to support fallback to GPIO.
	*/
	i2cexio0: i2c-10 {
	compatible = "i2c-demux-pinctrl";
	i2c-parent = <&iic0>, <&i2c0>;
	i2c-bus-name = "i2c-exio0";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	/*
	* IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA).
	* This is similar to the arangement described for i2cexio0 (above)
	* with a fallback to GPIO also provided.
	*/
	i2cexio1: i2c-11 {
	compatible = "i2c-demux-pinctrl";
	i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>;
	i2c-bus-name = "i2c-exio1";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	/*
	* IIC2 and I2C2 may be switched using pinmux.
	* A fallback to GPIO is also provided.
	*/
	i2chdmi: i2c-12 {
	compatible = "i2c-demux-pinctrl";
	i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>;
	i2c-bus-name = "i2c-hdmi";
	#address-cells = <1>;
	#size-cells = <0>;

	ak4643: codec@12 {
	compatible = "asahi-kasei,ak4643";
	#sound-dai-cells = <0>;
	reg = <0x12>;
	};

	composite-in@20 {
	compatible = "adi,adv7180";
	reg = <0x20>;
	remote = <&vin1>;

	port {
	adv7180: endpoint {
	bus-width = <8>;
	remote-endpoint = <&vin1ep0>;
	};
	};
	};

	hdmi@39 {
	compatible = "adi,adv7511w";
	reg = <0x39>;
	interrupt-parent = <&gpio1>;
	interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&cec_clock>;
	clock-names = "cec";

	adi,input-depth = <8>;
	adi,input-colorspace = "rgb";
	adi,input-clock = "1x";
	- adi,input-style = <1>;
	- adi,input-justification = "evenly";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7511_in: endpoint {
	remote-endpoint = <&lvds0_out>;
	};
	};

	port@1 {
	reg = <1>;
	adv7511_out: endpoint {
	remote-endpoint = <&hdmi_con_out>;
	};
	};
	};
	};

	hdmi-in@4c {
	compatible = "adi,adv7612";
	reg = <0x4c>;
	interrupt-parent = <&gpio1>;
	interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
	default-input = <0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7612_in: endpoint {
	remote-endpoint = <&hdmi_con_in>;
	};
	};

	port@2 {
	reg = <2>;
	adv7612_out: endpoint {
	remote-endpoint = <&vin0ep2>;
	};
	};
	};
	};
	};

	/*
	* IIC3 and I2C3 may be switched using pinmux.
	* IIC3/I2C3 does not appear to support fallback to GPIO.
	*/
	i2cpwr: i2c-13 {
	compatible = "i2c-demux-pinctrl";
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_irq_pins>;
	i2c-parent = <&iic3>, <&i2c3>;
	i2c-bus-name = "i2c-pwr";
	#address-cells = <1>;
	#size-cells = <0>;

	pmic@58 {
	compatible = "dlg,da9063";
	reg = <0x58>;
	interrupt-parent = <&irqc0>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;

	rtc {
	compatible = "dlg,da9063-rtc";
	};

	wdt {
	compatible = "dlg,da9063-watchdog";
	};
	};

	vdd_dvfs: regulator@68 {
	compatible = "dlg,da9210";
	reg = <0x68>;
	interrupt-parent = <&irqc0>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;

	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};
	};

	&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";
	status = "okay";

	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
	<&x13_clk>, <&x2_clk>;
	clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1";

	ports {
	port@0 {
	endpoint {
	remote-endpoint = <&adv7123_in>;
	};
	};
	};
	};

	&lvds0 {
	status = "okay";

	ports {
	port@1 {
	endpoint {
	remote-endpoint = <&adv7511_in>;
	};
	};
	};
	};

	&lvds1 {
	ports {
	port@1 {
	lvds_connector: endpoint {
	};
	};
	};
	};

	&extal_clk {
	clock-frequency = <20000000>;
	};

	&pfc {
	pinctrl-0 = <&scif_clk_pins>;
	pinctrl-names = "default";

	du_pins: du {
	groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
	function = "du";
	};

	scif0_pins: scif0 {
	groups = "scif0_data";
	function = "scif0";
	};

	scif_clk_pins: scif_clk {
	groups = "scif_clk";
	function = "scif_clk";
	};

	ether_pins: ether {
	groups = "eth_link", "eth_mdio", "eth_rmii";
	function = "eth";
	};

	phy1_pins: phy1 {
	groups = "intc_irq0";
	function = "intc";
	};

	scifa1_pins: scifa1 {
	groups = "scifa1_data";
	function = "scifa1";
	};

	sdhi0_pins: sd0 {
	groups = "sdhi0_data4", "sdhi0_ctrl";
	function = "sdhi0";
	power-source = <3300>;
	};

	sdhi0_pins_uhs: sd0_uhs {
	groups = "sdhi0_data4", "sdhi0_ctrl";
	function = "sdhi0";
	power-source = <1800>;
	};

	sdhi2_pins: sd2 {
	groups = "sdhi2_data4", "sdhi2_ctrl";
	function = "sdhi2";
	power-source = <3300>;
	};

	sdhi2_pins_uhs: sd2_uhs {
	groups = "sdhi2_data4", "sdhi2_ctrl";
	function = "sdhi2";
	power-source = <1800>;
	};

	mmc1_pins: mmc1 {
	groups = "mmc1_data8", "mmc1_ctrl";
	function = "mmc1";
	};

	qspi_pins: qspi {
	groups = "qspi_ctrl", "qspi_data4";
	function = "qspi";
	};

	msiof1_pins: msiof1 {
	groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
	"msiof1_tx";
	function = "msiof1";
	};

	i2c0_pins: i2c0 {
	groups = "i2c0";
	function = "i2c0";
	};

	iic0_pins: iic0 {
	groups = "iic0";
	function = "iic0";
	};

	i2c1_pins: i2c1 {
	groups = "i2c1";
	function = "i2c1";
	};

	iic1_pins: iic1 {
	groups = "iic1";
	function = "iic1";
	};

	i2c2_pins: i2c2 {
	groups = "i2c2";
	function = "i2c2";
	};

	iic2_pins: iic2 {
	groups = "iic2";
	function = "iic2";
	};

	i2c3_pins: i2c3 {
	groups = "i2c3";
	function = "i2c3";
	};

	iic3_pins: iic3 {
	groups = "iic3";
	function = "iic3";
	};

	pmic_irq_pins: pmicirq {
	groups = "intc_irq2";
	function = "intc";
	};

	hsusb_pins: hsusb {
	groups = "usb0_ovc_vbus";
	function = "usb0";
	};

	usb0_pins: usb0 {
	groups = "usb0";
	function = "usb0";
	};

	usb1_pins: usb1 {
	groups = "usb1";
	function = "usb1";
	};

	usb2_pins: usb2 {
	groups = "usb2";
	function = "usb2";
	};

	vin0_pins: vin0 {
	groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
	function = "vin0";
	};

	vin1_pins: vin1 {
	groups = "vin1_data8", "vin1_clk";
	function = "vin1";
	};

	sound_pins: sound {
	groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
	function = "ssi";
	};

	sound_clk_pins: sound_clk {
	groups = "audio_clk_a";
	function = "audio_clk";
	};
	};

	&ether {
	pinctrl-0 = <&ether_pins &phy1_pins>;
	pinctrl-names = "default";

	phy-handle = <&phy1>;
	renesas,ether-link-active-low;
	status = "okay";

	phy1: ethernet-phy@1 {
	reg = <1>;
	interrupt-parent = <&irqc0>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	micrel,led-mode = <1>;
	+ reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>;
	};
	};

	&cmt0 {
	status = "okay";
	};

	&mmcif1 {
	pinctrl-0 = <&mmc1_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&fixedregulator3v3>;
	bus-width = <8>;
	non-removable;
	status = "okay";
	};

	&sata1 {
	status = "okay";
	};

	&qspi {
	pinctrl-0 = <&qspi_pins>;
	pinctrl-names = "default";

	status = "okay";

	flash: flash@0 {
	compatible = "spansion,s25fl512s", "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <30000000>;
	spi-tx-bus-width = <4>;
	spi-rx-bus-width = <4>;
	spi-cpha;
	spi-cpol;
	m25p,fast-read;

	partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
	label = "loader";
	reg = <0x00000000 0x00040000>;
	read-only;
	};
	partition@40000 {
	label = "user";
	reg = <0x00040000 0x00400000>;
	read-only;
	};
	partition@440000 {
	label = "flash";
	reg = <0x00440000 0x03bc0000>;
	};
	};
	};
	};

	&scif0 {
	pinctrl-0 = <&scif0_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&scifa1 {
	pinctrl-0 = <&scifa1_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&scif_clk {
	clock-frequency = <14745600>;
	};

	&msiof1 {
	pinctrl-0 = <&msiof1_pins>;
	pinctrl-names = "default";

	status = "okay";

	pmic: pmic@0 {
	compatible = "renesas,r2a11302ft";
	reg = <0>;
	spi-max-frequency = <6000000>;
	spi-cpol;
	spi-cpha;
	};
	};

	&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-1 = <&sdhi0_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi0>;
	vqmmc-supply = <&vccq_sdhi0>;
	cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
	};

	&sdhi2 {
	pinctrl-0 = <&sdhi2_pins>;
	pinctrl-1 = <&sdhi2_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi2>;
	vqmmc-supply = <&vccq_sdhi2>;
	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
	sd-uhs-sdr50;
	status = "okay";
	};

	&cpu0 {
	cpu0-supply = <&vdd_dvfs>;
	};

	&i2c0 {
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "i2c-exio0";
	};

	&iic0 {
	pinctrl-0 = <&iic0_pins>;
	pinctrl-names = "i2c-exio0";
	};

	&i2c1 {
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-names = "i2c-exio1";
	};

	&iic1 {
	pinctrl-0 = <&iic1_pins>;
	pinctrl-names = "i2c-exio1";
	};

	&i2c2 {
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-names = "i2c-hdmi";

	clock-frequency = <100000>;
	};

	&iic2 {
	pinctrl-0 = <&iic2_pins>;
	pinctrl-names = "i2c-hdmi";

	clock-frequency = <100000>;
	};

	&i2c3 {
	pinctrl-0 = <&i2c3_pins>;
	pinctrl-names = "i2c-pwr";
	};

	&iic3 {
	pinctrl-0 = <&iic3_pins>;
	pinctrl-names = "i2c-pwr";
	};

	&pci0 {
	status = "okay";
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";
	};

	&pci1 {
	status = "okay";
	pinctrl-0 = <&usb1_pins>;
	pinctrl-names = "default";
	};

	&xhci {
	status = "okay";
	pinctrl-0 = <&usb2_pins>;
	pinctrl-names = "default";
	};

	&pci2 {
	status = "okay";
	pinctrl-0 = <&usb2_pins>;
	pinctrl-names = "default";
	};

	&hsusb {
	status = "okay";
	pinctrl-0 = <&hsusb_pins>;
	pinctrl-names = "default";
	renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
	};

	&usbphy {
	status = "okay";
	};

	/* HDMI video input */
	&vin0 {
	pinctrl-0 = <&vin0_pins>;
	pinctrl-names = "default";

	status = "okay";

	port {
	vin0ep2: endpoint {
	remote-endpoint = <&adv7612_out>;
	bus-width = <24>;
	hsync-active = <0>;
	vsync-active = <0>;
	pclk-sample = <1>;
	data-active = <1>;
	};
	};
	};

	/* composite video input */
	&vin1 {
	pinctrl-0 = <&vin1_pins>;
	pinctrl-names = "default";

	status = "okay";

	port {
	vin1ep0: endpoint {
	remote-endpoint = <&adv7180>;
	bus-width = <8>;
	};
	};
	};

	&rcar_sound {
	pinctrl-0 = <&sound_pins &sound_clk_pins>;
	pinctrl-names = "default";

	/* Single DAI */
	#sound-dai-cells = <0>;

	status = "okay";

	rcar_sound,dai {
	dai0 {
	playback = <&ssi0 &src2 &dvc0>;
	capture = <&ssi1 &src3 &dvc1>;
	};
	};
	};

	&rwdt {
	timeout-sec = <60>;
	status = "okay";
	};

	&ssi1 {
	shared-pin;
	};
	diff --git a/sys/gnu/dts/arm/r8a7790-stout.dts b/sys/gnu/dts/arm/r8a7790-stout.dts
	index a315ba749aa4..6a457bc9280a 100644
	--- a/sys/gnu/dts/arm/r8a7790-stout.dts
	+++ b/sys/gnu/dts/arm/r8a7790-stout.dts
	@@ -1,381 +1,380 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the Stout board
	*
	* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
	*/

	/dts-v1/;
	#include "r8a7790.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>

	/ {
	model = "Stout";
	compatible = "renesas,stout", "renesas,r8a7790";

	aliases {
	serial0 = &scifa0;
	};

	chosen {
	bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
	stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
	device_type = "memory";
	reg = <0 0x40000000 0 0x40000000>;
	};

	leds {
	compatible = "gpio-leds";
	led1 {
	gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
	};
	led2 {
	gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
	};
	led3 {
	gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
	};
	led5 {
	gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
	};
	};

	fixedregulator3v3: regulator-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "fixed-3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vcc_sdhi0: regulator-vcc-sdhi0 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI0 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	hdmi-out {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con_out: endpoint {
	remote-endpoint = <&adv7511_out>;
	};
	};
	};

	osc1_clk: osc1-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <148500000>;
	};

	osc4_clk: osc4-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <12000000>;
	};
	};

	&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";
	status = "okay";

	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
	<&osc1_clk>;
	clock-names = "du.0", "du.1", "du.2", "dclkin.0";

	ports {
	port@0 {
	endpoint {
	remote-endpoint = <&adv7511_in>;
	};
	};
	};
	};

	&lvds0 {
	ports {
	port@1 {
	lvds_connector0: endpoint {
	};
	};
	};
	};

	&lvds1 {
	ports {
	port@1 {
	lvds_connector1: endpoint {
	};
	};
	};
	};

	&extal_clk {
	clock-frequency = <20000000>;
	};

	&pfc {

	pinctrl-0 = <&scif_clk_pins>;
	pinctrl-names = "default";

	du_pins: du {
	groups = "du_rgb888", "du_sync_1", "du_clk_out_0";
	function = "du";
	};

	scifa0_pins: scifa0 {
	groups = "scifa0_data_b";
	function = "scifa0";
	};

	scif_clk_pins: scif_clk {
	groups = "scif_clk";
	function = "scif_clk";
	};

	ether_pins: ether {
	groups = "eth_link", "eth_mdio", "eth_rmii";
	function = "eth";
	};

	phy1_pins: phy1 {
	groups = "intc_irq1";
	function = "intc";
	};

	sdhi0_pins: sd0 {
	groups = "sdhi0_data4", "sdhi0_ctrl";
	function = "sdhi0";
	power-source = <3300>;
	};

	qspi_pins: qspi {
	groups = "qspi_ctrl", "qspi_data4";
	function = "qspi";
	};

	iic2_pins: iic2 {
	groups = "iic2_b";
	function = "iic2";
	};

	iic3_pins: iic3 {
	groups = "iic3";
	function = "iic3";
	};

	pmic_irq_pins: pmicirq {
	groups = "intc_irq2";
	function = "intc";
	};

	usb0_pins: usb0 {
	groups = "usb0";
	function = "usb0";
	};
	};

	&ether {
	pinctrl-0 = <&ether_pins &phy1_pins>;
	pinctrl-names = "default";

	phy-handle = <&phy1>;
	renesas,ether-link-active-low;
	status = "okay";

	phy1: ethernet-phy@1 {
	reg = <1>;
	interrupt-parent = <&irqc0>;
	interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
	micrel,led-mode = <1>;
	+ reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
	};
	};

	&cmt0 {
	status = "okay";
	};

	&qspi {
	pinctrl-0 = <&qspi_pins>;
	pinctrl-names = "default";

	status = "okay";

	flash: flash@0 {
	compatible = "spansion,s25fl512s", "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <30000000>;
	spi-tx-bus-width = <4>;
	spi-rx-bus-width = <4>;
	spi-cpha;
	spi-cpol;
	m25p,fast-read;

	partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
	label = "loader";
	reg = <0x00000000 0x00080000>;
	read-only;
	};
	partition@80000 {
	label = "uboot";
	reg = <0x00080000 0x00040000>;
	read-only;
	};
	partition@c0000 {
	label = "uboot-env";
	reg = <0x000c0000 0x00040000>;
	read-only;
	};
	partition@100000 {
	label = "flash";
	reg = <0x00100000 0x03f00000>;
	};
	};
	};
	};

	&scifa0 {
	pinctrl-0 = <&scifa0_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&scif_clk {
	clock-frequency = <14745600>;
	};

	&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&vcc_sdhi0>;
	cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&cpu0 {
	cpu0-supply = <&vdd_dvfs>;
	};

	&iic2 {
	status = "okay";
	pinctrl-0 = <&iic2_pins>;
	pinctrl-names = "default";

	clock-frequency = <100000>;

	hdmi@39 {
	compatible = "adi,adv7511w";
	reg = <0x39>;
	interrupt-parent = <&gpio1>;
	interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&osc4_clk>;
	clock-names = "cec";

	adi,input-depth = <8>;
	adi,input-colorspace = "rgb";
	adi,input-clock = "1x";
	- adi,input-style = <1>;
	- adi,input-justification = "evenly";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7511_in: endpoint {
	remote-endpoint = <&du_out_rgb>;
	};
	};

	port@1 {
	reg = <1>;
	adv7511_out: endpoint {
	remote-endpoint = <&hdmi_con_out>;
	};
	};
	};
	};
	};

	&iic3 {
	pinctrl-names = "default";
	pinctrl-0 = <&iic3_pins &pmic_irq_pins>;
	status = "okay";

	pmic@58 {
	compatible = "dlg,da9063";
	reg = <0x58>;
	interrupt-parent = <&irqc0>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;

	onkey {
	compatible = "dlg,da9063-onkey";
	};

	rtc {
	compatible = "dlg,da9063-rtc";
	};

	wdt {
	compatible = "dlg,da9063-watchdog";
	};
	};

	vdd_dvfs: regulator@68 {
	compatible = "dlg,da9210";
	reg = <0x68>;
	interrupt-parent = <&irqc0>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;

	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vdd: regulator@70 {
	compatible = "dlg,da9210";
	reg = <0x70>;
	interrupt-parent = <&irqc0>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;

	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};

	&pci0 {
	status = "okay";
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";
	};

	&usbphy {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/r8a7790.dtsi b/sys/gnu/dts/arm/r8a7790.dtsi
	index 334ba19769b9..e5ef9fd4284a 100644
	--- a/sys/gnu/dts/arm/r8a7790.dtsi
	+++ b/sys/gnu/dts/arm/r8a7790.dtsi
	@@ -1,1873 +1,1875 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the R-Car H2 (R8A77900) SoC
	*
	* Copyright (C) 2015 Renesas Electronics Corporation
	* Copyright (C) 2013-2014 Renesas Solutions Corp.
	* Copyright (C) 2014 Cogent Embedded Inc.
	*/

	#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/power/r8a7790-sysc.h>

	/ {
	compatible = "renesas,r8a7790";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &iic0;
	i2c5 = &iic1;
	i2c6 = &iic2;
	i2c7 = &iic3;
	spi0 = &qspi;
	spi1 = &msiof0;
	spi2 = &msiof1;
	spi3 = &msiof2;
	spi4 = &msiof3;
	vin0 = &vin0;
	vin1 = &vin1;
	vin2 = &vin2;
	vin3 = &vin3;
	};

	/*
	* The external audio clocks are configured as 0 Hz fixed frequency
	* clocks by default.
	* Boards that provide audio clocks should override them.
	*/
	audio_clk_a: audio_clk_a {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	audio_clk_b: audio_clk_b {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	audio_clk_c: audio_clk_c {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	/* External CAN clock */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "renesas,apmu";

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0>;
	clock-frequency = <1300000000>;
	clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
	power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
	next-level-cache = <&L2_CA15>;
	capacity-dmips-mhz = <1024>;
	voltage-tolerance = <1>; /* 1% */
	clock-latency = <300000>; /* 300 us */

	/* kHz - uV - OPPs unknown yet */
	operating-points = <1400000 1000000>,
	<1225000 1000000>,
	<1050000 1000000>,
	< 875000 1000000>,
	< 700000 1000000>,
	< 350000 1000000>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <1>;
	clock-frequency = <1300000000>;
	clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
	power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
	next-level-cache = <&L2_CA15>;
	capacity-dmips-mhz = <1024>;
	voltage-tolerance = <1>; /* 1% */
	clock-latency = <300000>; /* 300 us */

	/* kHz - uV - OPPs unknown yet */
	operating-points = <1400000 1000000>,
	<1225000 1000000>,
	<1050000 1000000>,
	< 875000 1000000>,
	< 700000 1000000>,
	< 350000 1000000>;
	};

	cpu2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <2>;
	clock-frequency = <1300000000>;
	clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
	power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
	next-level-cache = <&L2_CA15>;
	capacity-dmips-mhz = <1024>;
	voltage-tolerance = <1>; /* 1% */
	clock-latency = <300000>; /* 300 us */

	/* kHz - uV - OPPs unknown yet */
	operating-points = <1400000 1000000>,
	<1225000 1000000>,
	<1050000 1000000>,
	< 875000 1000000>,
	< 700000 1000000>,
	< 350000 1000000>;
	};

	cpu3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <3>;
	clock-frequency = <1300000000>;
	clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
	power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
	next-level-cache = <&L2_CA15>;
	capacity-dmips-mhz = <1024>;
	voltage-tolerance = <1>; /* 1% */
	clock-latency = <300000>; /* 300 us */

	/* kHz - uV - OPPs unknown yet */
	operating-points = <1400000 1000000>,
	<1225000 1000000>,
	<1050000 1000000>,
	< 875000 1000000>,
	< 700000 1000000>,
	< 350000 1000000>;
	};

	cpu4: cpu@100 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x100>;
	clock-frequency = <780000000>;
	clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
	power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
	next-level-cache = <&L2_CA7>;
	capacity-dmips-mhz = <539>;
	};

	cpu5: cpu@101 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x101>;
	clock-frequency = <780000000>;
	clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
	power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
	next-level-cache = <&L2_CA7>;
	capacity-dmips-mhz = <539>;
	};

	cpu6: cpu@102 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x102>;
	clock-frequency = <780000000>;
	clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
	power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
	next-level-cache = <&L2_CA7>;
	capacity-dmips-mhz = <539>;
	};

	cpu7: cpu@103 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x103>;
	clock-frequency = <780000000>;
	clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
	power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
	next-level-cache = <&L2_CA7>;
	capacity-dmips-mhz = <539>;
	};

	L2_CA15: cache-controller-0 {
	compatible = "cache";
	power-domains = <&sysc R8A7790_PD_CA15_SCU>;
	cache-unified;
	cache-level = <2>;
	};

	L2_CA7: cache-controller-1 {
	compatible = "cache";
	power-domains = <&sysc R8A7790_PD_CA7_SCU>;
	cache-unified;
	cache-level = <2>;
	};
	};

	/* External root clock */
	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	/* External PCIe clock - can be overridden by the board */
	pcie_bus_clk: pcie_bus {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	pmu-0 {
	compatible = "arm,cortex-a15-pmu";
	interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	pmu-1 {
	compatible = "arm,cortex-a7-pmu";
	interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
	};

	/* External SCIF clock */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;

	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a7790-wdt",
	"renesas,rcar-gen2-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a7790",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a7790",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 30>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a7790",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 30>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a7790",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a7790",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a7790",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a7790";
	reg = <0 0xe6060000 0 0x250>;
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a7790-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>, <&usb_extal_clk>;
	clock-names = "extal", "usb_extal";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	apmu@e6151000 {
	compatible = "renesas,r8a7790-apmu", "renesas,apmu";
	reg = <0 0xe6151000 0 0x188>;
	cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
	};

	apmu@e6152000 {
	compatible = "renesas,r8a7790-apmu", "renesas,apmu";
	reg = <0 0xe6152000 0 0x188>;
	cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a7790-rst";
	reg = <0 0xe6160000 0 0x0100>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a7790-sysc";
	reg = <0 0xe6180000 0 0x0200>;
	#power-domain-cells = <1>;
	};

	irqc0: interrupt-controller@e61c0000 {
	compatible = "renesas,irqc-r8a7790", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	thermal: thermal@e61f0000 {
	compatible = "renesas,thermal-r8a7790",
	"renesas,rcar-gen2-thermal",
	"renesas,rcar-thermal";
	reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 522>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 522>;
	#thermal-sensor-cells = <0>;
	};

	ipmmu_sy0: mmu@e6280000 {
	compatible = "renesas,ipmmu-r8a7790",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6280000 0 0x1000>;
	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_sy1: mmu@e6290000 {
	compatible = "renesas,ipmmu-r8a7790",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6290000 0 0x1000>;
	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_ds: mmu@e6740000 {
	compatible = "renesas,ipmmu-r8a7790",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6740000 0 0x1000>;
	interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_mp: mmu@ec680000 {
	compatible = "renesas,ipmmu-r8a7790",
	"renesas,ipmmu-vmsa";
	reg = <0 0xec680000 0 0x1000>;
	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_mx: mmu@fe951000 {
	compatible = "renesas,ipmmu-r8a7790",
	"renesas,ipmmu-vmsa";
	reg = <0 0xfe951000 0 0x1000>;
	interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_rt: mmu@ffc80000 {
	compatible = "renesas,ipmmu-r8a7790",
	"renesas,ipmmu-vmsa";
	reg = <0 0xffc80000 0 0x1000>;
	interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	icram0: sram@e63a0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63a0000 0 0x12000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63a0000 0x12000>;
	};

	icram1: sram@e63c0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63c0000 0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63c0000 0x1000>;

	smp-sram@0 {
	compatible = "renesas,smp-sram";
	reg = <0 0x100>;
	};
	};

	i2c0: i2c@e6508000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7790",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c1: i2c@e6518000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7790",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6518000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c2: i2c@e6530000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7790",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6530000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c3: i2c@e6540000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7790",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6540000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	iic0: i2c@e6500000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7790",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe6500000 0 0x425>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 318>;
	dmas = <&dmac0 0x61>, <&dmac0 0x62>,
	<&dmac1 0x61>, <&dmac1 0x62>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 318>;
	status = "disabled";
	};

	iic1: i2c@e6510000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7790",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe6510000 0 0x425>;
	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 323>;
	dmas = <&dmac0 0x65>, <&dmac0 0x66>,
	<&dmac1 0x65>, <&dmac1 0x66>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 323>;
	status = "disabled";
	};

	iic2: i2c@e6520000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7790",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe6520000 0 0x425>;
	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 300>;
	dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
	<&dmac1 0x69>, <&dmac1 0x6a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 300>;
	status = "disabled";
	};

	iic3: i2c@e60b0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7790",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe60b0000 0 0x425>;
	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 926>;
	dmas = <&dmac0 0x77>, <&dmac0 0x78>,
	<&dmac1 0x77>, <&dmac1 0x78>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 926>;
	status = "disabled";
	};

	hsusb: usb@e6590000 {
	compatible = "renesas,usbhs-r8a7790",
	"renesas,rcar-gen2-usbhs";
	reg = <0 0xe6590000 0 0x100>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 704>;
	dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
	<&usb_dmac1 0>, <&usb_dmac1 1>;
	dma-names = "ch0", "ch1", "ch2", "ch3";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 704>;
	renesas,buswait = <4>;
	phys = <&usb0 1>;
	phy-names = "usb";
	status = "disabled";
	};

	usbphy: usb-phy@e6590100 {
	compatible = "renesas,usb-phy-r8a7790",
	"renesas,rcar-gen2-usb-phy";
	reg = <0 0xe6590100 0 0x100>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cpg CPG_MOD 704>;
	clock-names = "usbhs";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 704>;
	status = "disabled";

	usb0: usb-channel@0 {
	reg = <0>;
	#phy-cells = <1>;
	};
	usb2: usb-channel@2 {
	reg = <2>;
	#phy-cells = <1>;
	};
	};

	usb_dmac0: dma-controller@e65a0000 {
	compatible = "renesas,r8a7790-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65a0000 0 0x100>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 330>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 330>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac1: dma-controller@e65b0000 {
	compatible = "renesas,r8a7790-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65b0000 0 0x100>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 331>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 331>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a7790",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x20000>;
	interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	dmac1: dma-controller@e6720000 {
	compatible = "renesas,dmac-r8a7790",
	"renesas,rcar-dmac";
	reg = <0 0xe6720000 0 0x20000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a7790",
	"renesas,etheravb-rcar-gen2";
	reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
	interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	qspi: spi@e6b10000 {
	compatible = "renesas,qspi-r8a7790", "renesas,qspi";
	reg = <0 0xe6b10000 0 0x2c>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 917>;
	dmas = <&dmac0 0x17>, <&dmac0 0x18>,
	<&dmac1 0x17>, <&dmac1 0x18>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 917>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	scifa0: serial@e6c40000 {
	compatible = "renesas,scifa-r8a7790",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c40000 0 64>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 204>;
	clock-names = "fck";
	dmas = <&dmac0 0x21>, <&dmac0 0x22>,
	<&dmac1 0x21>, <&dmac1 0x22>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 204>;
	status = "disabled";
	};

	scifa1: serial@e6c50000 {
	compatible = "renesas,scifa-r8a7790",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c50000 0 64>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 203>;
	clock-names = "fck";
	dmas = <&dmac0 0x25>, <&dmac0 0x26>,
	<&dmac1 0x25>, <&dmac1 0x26>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 203>;
	status = "disabled";
	};

	scifa2: serial@e6c60000 {
	compatible = "renesas,scifa-r8a7790",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c60000 0 64>;
	interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 202>;
	clock-names = "fck";
	dmas = <&dmac0 0x27>, <&dmac0 0x28>,
	<&dmac1 0x27>, <&dmac1 0x28>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 202>;
	status = "disabled";
	};

	scifb0: serial@e6c20000 {
	compatible = "renesas,scifb-r8a7790",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6c20000 0 0x100>;
	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 206>;
	clock-names = "fck";
	dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
	<&dmac1 0x3d>, <&dmac1 0x3e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 206>;
	status = "disabled";
	};

	scifb1: serial@e6c30000 {
	compatible = "renesas,scifb-r8a7790",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6c30000 0 0x100>;
	interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 207>;
	clock-names = "fck";
	dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
	<&dmac1 0x19>, <&dmac1 0x1a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 207>;
	status = "disabled";
	};

	scifb2: serial@e6ce0000 {
	compatible = "renesas,scifb-r8a7790",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6ce0000 0 0x100>;
	interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 216>;
	clock-names = "fck";
	dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
	<&dmac1 0x1d>, <&dmac1 0x1e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 216>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a7790",
	"renesas,rcar-gen2-scif",
	"renesas,scif";
	reg = <0 0xe6e60000 0 64>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 721>,
	<&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
	<&dmac1 0x29>, <&dmac1 0x2a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 721>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a7790",
	"renesas,rcar-gen2-scif",
	"renesas,scif";
	reg = <0 0xe6e68000 0 64>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 720>,
	<&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
	<&dmac1 0x2d>, <&dmac1 0x2e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 720>;
	status = "disabled";
	};

	scif2: serial@e6e56000 {
	compatible = "renesas,scif-r8a7790",
	"renesas,rcar-gen2-scif",
	"renesas,scif";
	reg = <0 0xe6e56000 0 64>;
	interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 310>,
	<&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
	<&dmac1 0x2b>, <&dmac1 0x2c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 310>;
	status = "disabled";
	};

	hscif0: serial@e62c0000 {
	compatible = "renesas,hscif-r8a7790",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c0000 0 96>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 717>,
	<&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
	<&dmac1 0x39>, <&dmac1 0x3a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 717>;
	status = "disabled";
	};

	hscif1: serial@e62c8000 {
	compatible = "renesas,hscif-r8a7790",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c8000 0 96>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>,
	<&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
	<&dmac1 0x4d>, <&dmac1 0x4e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";
	};

	msiof0: spi@e6e20000 {
	compatible = "renesas,msiof-r8a7790",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6e20000 0 0x0064>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 0>;
	dmas = <&dmac0 0x51>, <&dmac0 0x52>,
	<&dmac1 0x51>, <&dmac1 0x52>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 0>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof1: spi@e6e10000 {
	compatible = "renesas,msiof-r8a7790",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6e10000 0 0x0064>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 208>;
	dmas = <&dmac0 0x55>, <&dmac0 0x56>,
	<&dmac1 0x55>, <&dmac1 0x56>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 208>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof2: spi@e6e00000 {
	compatible = "renesas,msiof-r8a7790",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6e00000 0 0x0064>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 205>;
	dmas = <&dmac0 0x41>, <&dmac0 0x42>,
	<&dmac1 0x41>, <&dmac1 0x42>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 205>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof3: spi@e6c90000 {
	compatible = "renesas,msiof-r8a7790",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6c90000 0 0x0064>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 215>;
	dmas = <&dmac0 0x45>, <&dmac0 0x46>,
	<&dmac1 0x45>, <&dmac1 0x46>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 215>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	can0: can@e6e80000 {
	compatible = "renesas,can-r8a7790",
	"renesas,rcar-gen2-can";
	reg = <0 0xe6e80000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 916>,
	<&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 916>;
	status = "disabled";
	};

	can1: can@e6e88000 {
	compatible = "renesas,can-r8a7790",
	"renesas,rcar-gen2-can";
	reg = <0 0xe6e88000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 915>,
	<&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 915>;
	status = "disabled";
	};

	vin0: video@e6ef0000 {
	compatible = "renesas,vin-r8a7790",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef0000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 811>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 811>;
	status = "disabled";
	};

	vin1: video@e6ef1000 {
	compatible = "renesas,vin-r8a7790",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef1000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 810>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 810>;
	status = "disabled";
	};

	vin2: video@e6ef2000 {
	compatible = "renesas,vin-r8a7790",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef2000 0 0x1000>;
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 809>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 809>;
	status = "disabled";
	};

	vin3: video@e6ef3000 {
	compatible = "renesas,vin-r8a7790",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef3000 0 0x1000>;
	interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 808>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 808>;
	status = "disabled";
	};

	rcar_sound: sound@ec500000 {
	/*
	* #sound-dai-cells is required
	*
	* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
	* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
	*/
	compatible = "renesas,rcar_sound-r8a7790",
	"renesas,rcar_sound-gen2";
	reg = <0 0xec500000 0 0x1000>, /* SCU */
	<0 0xec5a0000 0 0x100>, /* ADG */
	<0 0xec540000 0 0x1000>, /* SSIU */
	<0 0xec541000 0 0x280>, /* SSI */
	<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
	reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

	clocks = <&cpg CPG_MOD 1005>,
	<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
	<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
	<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
	<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
	<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
	<&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
	<&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
	<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
	<&cpg CPG_CORE R8A7790_CLK_M2>;
	clock-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0",
	"src.9", "src.8", "src.7", "src.6",
	"src.5", "src.4", "src.3", "src.2",
	"src.1", "src.0",
	"ctu.0", "ctu.1",
	"mix.0", "mix.1",
	"dvc.0", "dvc.1",
	"clk_a", "clk_b", "clk_c", "clk_i";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 1005>,
	<&cpg 1006>, <&cpg 1007>,
	<&cpg 1008>, <&cpg 1009>,
	<&cpg 1010>, <&cpg 1011>,
	<&cpg 1012>, <&cpg 1013>,
	<&cpg 1014>, <&cpg 1015>;
	reset-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0";

	status = "disabled";

	rcar_sound,dvc {
	dvc0: dvc-0 {
	dmas = <&audma1 0xbc>;
	dma-names = "tx";
	};
	dvc1: dvc-1 {
	dmas = <&audma1 0xbe>;
	dma-names = "tx";
	};
	};

	rcar_sound,mix {
	mix0: mix-0 { };
	mix1: mix-1 { };
	};

	rcar_sound,ctu {
	ctu00: ctu-0 { };
	ctu01: ctu-1 { };
	ctu02: ctu-2 { };
	ctu03: ctu-3 { };
	ctu10: ctu-4 { };
	ctu11: ctu-5 { };
	ctu12: ctu-6 { };
	ctu13: ctu-7 { };
	};

	rcar_sound,src {
	src0: src-0 {
	interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x85>, <&audma1 0x9a>;
	dma-names = "rx", "tx";
	};
	src1: src-1 {
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x87>, <&audma1 0x9c>;
	dma-names = "rx", "tx";
	};
	src2: src-2 {
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x89>, <&audma1 0x9e>;
	dma-names = "rx", "tx";
	};
	src3: src-3 {
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8b>, <&audma1 0xa0>;
	dma-names = "rx", "tx";
	};
	src4: src-4 {
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8d>, <&audma1 0xb0>;
	dma-names = "rx", "tx";
	};
	src5: src-5 {
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8f>, <&audma1 0xb2>;
	dma-names = "rx", "tx";
	};
	src6: src-6 {
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x91>, <&audma1 0xb4>;
	dma-names = "rx", "tx";
	};
	src7: src-7 {
	interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x93>, <&audma1 0xb6>;
	dma-names = "rx", "tx";
	};
	src8: src-8 {
	interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x95>, <&audma1 0xb8>;
	dma-names = "rx", "tx";
	};
	src9: src-9 {
	interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x97>, <&audma1 0xba>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssi {
	ssi0: ssi-0 {
	interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x01>, <&audma1 0x02>,
	<&audma0 0x15>, <&audma1 0x16>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi1: ssi-1 {
	interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x03>, <&audma1 0x04>,
	<&audma0 0x49>, <&audma1 0x4a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi2: ssi-2 {
	interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x05>, <&audma1 0x06>,
	<&audma0 0x63>, <&audma1 0x64>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi3: ssi-3 {
	interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x07>, <&audma1 0x08>,
	<&audma0 0x6f>, <&audma1 0x70>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi4: ssi-4 {
	interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x09>, <&audma1 0x0a>,
	<&audma0 0x71>, <&audma1 0x72>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi5: ssi-5 {
	interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0b>, <&audma1 0x0c>,
	<&audma0 0x73>, <&audma1 0x74>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi6: ssi-6 {
	interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0d>, <&audma1 0x0e>,
	<&audma0 0x75>, <&audma1 0x76>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi7: ssi-7 {
	interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0f>, <&audma1 0x10>,
	<&audma0 0x79>, <&audma1 0x7a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi8: ssi-8 {
	interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x11>, <&audma1 0x12>,
	<&audma0 0x7b>, <&audma1 0x7c>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi9: ssi-9 {
	interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x13>, <&audma1 0x14>,
	<&audma0 0x7d>, <&audma1 0x7e>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	};
	};

	audma0: dma-controller@ec700000 {
	compatible = "renesas,dmac-r8a7790",
	"renesas,rcar-dmac";
	reg = <0 0xec700000 0 0x10000>;
	interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12";
	clocks = <&cpg CPG_MOD 502>;
	clock-names = "fck";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 502>;
	#dma-cells = <1>;
	dma-channels = <13>;
	};

	audma1: dma-controller@ec720000 {
	compatible = "renesas,dmac-r8a7790",
	"renesas,rcar-dmac";
	reg = <0 0xec720000 0 0x10000>;
	interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12";
	clocks = <&cpg CPG_MOD 501>;
	clock-names = "fck";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 501>;
	#dma-cells = <1>;
	dma-channels = <13>;
	};

	xhci: usb@ee000000 {
	compatible = "renesas,xhci-r8a7790",
	"renesas,rcar-gen2-xhci";
	reg = <0 0xee000000 0 0xc00>;
	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	phys = <&usb2 1>;
	phy-names = "usb";
	status = "disabled";
	};

	pci0: pci@ee090000 {
	compatible = "renesas,pci-r8a7790",
	"renesas,pci-rcar-gen2";
	device_type = "pci";
	reg = <0 0xee090000 0 0xc00>,
	<0 0xee080000 0 0x1100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 703>;
	status = "disabled";

	bus-range = <0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
	interrupt-map-mask = <0xf800 0 0 0x7>;
	interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

	usb@1,0 {
	reg = <0x800 0 0 0 0>;
	phys = <&usb0 0>;
	phy-names = "usb";
	};

	usb@2,0 {
	reg = <0x1000 0 0 0 0>;
	phys = <&usb0 0>;
	phy-names = "usb";
	};
	};

	pci1: pci@ee0b0000 {
	compatible = "renesas,pci-r8a7790",
	"renesas,pci-rcar-gen2";
	device_type = "pci";
	reg = <0 0xee0b0000 0 0xc00>,
	<0 0xee0a0000 0 0x1100>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 703>;
	status = "disabled";

	bus-range = <1 1>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
	interrupt-map-mask = <0xf800 0 0 0x7>;
	interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	<0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	<0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	};

	pci2: pci@ee0d0000 {
	compatible = "renesas,pci-r8a7790",
	"renesas,pci-rcar-gen2";
	device_type = "pci";
	clocks = <&cpg CPG_MOD 703>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 703>;
	reg = <0 0xee0d0000 0 0xc00>,
	<0 0xee0c0000 0 0x1100>;
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";

	bus-range = <2 2>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
	interrupt-map-mask = <0xf800 0 0 0x7>;
	interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

	usb@1,0 {
	reg = <0x20800 0 0 0 0>;
	phys = <&usb2 0>;
	phy-names = "usb";
	};

	usb@2,0 {
	reg = <0x21000 0 0 0 0>;
	phys = <&usb2 0>;
	phy-names = "usb";
	};
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a7790",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee100000 0 0x328>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
	<&dmac1 0xcd>, <&dmac1 0xce>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <195000000>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	status = "disabled";
	};

	sdhi1: sd@ee120000 {
	compatible = "renesas,sdhi-r8a7790",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee120000 0 0x328>;
	interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 313>;
	dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
	<&dmac1 0xc9>, <&dmac1 0xca>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <195000000>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 313>;
	status = "disabled";
	};

	sdhi2: sd@ee140000 {
	compatible = "renesas,sdhi-r8a7790",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee140000 0 0x100>;
	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 312>;
	dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
	<&dmac1 0xc1>, <&dmac1 0xc2>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <97500000>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 312>;
	status = "disabled";
	};

	sdhi3: sd@ee160000 {
	compatible = "renesas,sdhi-r8a7790",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee160000 0 0x100>;
	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 311>;
	dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
	<&dmac1 0xd3>, <&dmac1 0xd4>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <97500000>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 311>;
	status = "disabled";
	};

	mmcif0: mmc@ee200000 {
	compatible = "renesas,mmcif-r8a7790",
	"renesas,sh-mmcif";
	reg = <0 0xee200000 0 0x80>;
	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 315>;
	dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
	<&dmac1 0xd1>, <&dmac1 0xd2>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 315>;
	reg-io-width = <4>;
	status = "disabled";
	max-frequency = <97500000>;
	};

	mmcif1: mmc@ee220000 {
	compatible = "renesas,mmcif-r8a7790",
	"renesas,sh-mmcif";
	reg = <0 0xee220000 0 0x80>;
	interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 305>;
	dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
	<&dmac1 0xe1>, <&dmac1 0xe2>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 305>;
	reg-io-width = <4>;
	status = "disabled";
	max-frequency = <97500000>;
	};

	sata0: sata@ee300000 {
	compatible = "renesas,sata-r8a7790",
	"renesas,rcar-gen2-sata";
	reg = <0 0xee300000 0 0x200000>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 815>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 815>;
	status = "disabled";
	};

	sata1: sata@ee500000 {
	compatible = "renesas,sata-r8a7790",
	"renesas,rcar-gen2-sata";
	reg = <0 0xee500000 0 0x200000>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 814>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 814>;
	status = "disabled";
	};

	ether: ethernet@ee700000 {
	compatible = "renesas,ether-r8a7790",
	"renesas,rcar-gen2-ether";
	reg = <0 0xee700000 0 0x400>;
	interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 813>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 813>;
	phy-mode = "rmii";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	gic: interrupt-controller@f1001000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
	<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	pciec: pcie@fe000000 {
	compatible = "renesas,pcie-r8a7790",
	"renesas,pcie-rcar-gen2";
	reg = <0 0xfe000000 0 0x80000>;
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x00 0xff>;
	device_type = "pci";
	ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
	<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
	<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
	<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
	/* Map all possible DDR as inbound ranges */
	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
	<0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
	clock-names = "pcie", "pcie_bus";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 319>;
	status = "disabled";
	};

	vsp@fe920000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe920000 0 0x8000>;
	interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 130>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 130>;
	};

	vsp@fe928000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe928000 0 0x8000>;
	interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 131>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 131>;
	};

	vsp@fe930000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe930000 0 0x8000>;
	interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 128>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 128>;
	};

	vsp@fe938000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe938000 0 0x8000>;
	interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 127>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 127>;
	};

	fdp1@fe940000 {
	compatible = "renesas,fdp1";
	reg = <0 0xfe940000 0 0x2400>;
	interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 119>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 119>;
	};

	fdp1@fe944000 {
	compatible = "renesas,fdp1";
	reg = <0 0xfe944000 0 0x2400>;
	interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 118>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 118>;
	};

	fdp1@fe948000 {
	compatible = "renesas,fdp1";
	reg = <0 0xfe948000 0 0x2400>;
	interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 117>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 117>;
	};

	jpu: jpeg-codec@fe980000 {
	compatible = "renesas,jpu-r8a7790",
	"renesas,rcar-gen2-jpu";
	reg = <0 0xfe980000 0 0x10300>;
	interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 106>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 106>;
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a7790";
	reg = <0 0xfeb00000 0 0x70000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
	<&cpg CPG_MOD 722>;
	clock-names = "du.0", "du.1", "du.2";
	+ resets = <&cpg 724>;
	+ reset-names = "du.0";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb: endpoint {
	};
	};
	port@1 {
	reg = <1>;
	du_out_lvds0: endpoint {
	remote-endpoint = <&lvds0_in>;
	};
	};
	port@2 {
	reg = <2>;
	du_out_lvds1: endpoint {
	remote-endpoint = <&lvds1_in>;
	};
	};
	};
	};

	lvds0: lvds@feb90000 {
	compatible = "renesas,r8a7790-lvds";
	reg = <0 0xfeb90000 0 0x1c>;
	clocks = <&cpg CPG_MOD 726>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 726>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds0_in: endpoint {
	remote-endpoint = <&du_out_lvds0>;
	};
	};
	port@1 {
	reg = <1>;
	lvds0_out: endpoint {
	};
	};
	};
	};

	lvds1: lvds@feb94000 {
	compatible = "renesas,r8a7790-lvds";
	reg = <0 0xfeb94000 0 0x1c>;
	clocks = <&cpg CPG_MOD 725>;
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 725>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds1_in: endpoint {
	remote-endpoint = <&du_out_lvds1>;
	};
	};
	port@1 {
	reg = <1>;
	lvds1_out: endpoint {
	};
	};
	};
	};

	prr: chipid@ff000044 {
	compatible = "renesas,prr";
	reg = <0 0xff000044 0 4>;
	};

	cmt0: timer@ffca0000 {
	compatible = "renesas,r8a7790-cmt0",
	"renesas,rcar-gen2-cmt0";
	reg = <0 0xffca0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 124>;
	clock-names = "fck";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 124>;

	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a7790-cmt1",
	"renesas,rcar-gen2-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 329>;
	clock-names = "fck";
	power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
	resets = <&cpg 329>;

	status = "disabled";
	};
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	polling-delay-passive = <0>;
	polling-delay = <0>;

	thermal-sensors = <&thermal>;

	trips {
	cpu-crit {
	temperature = <95000>;
	hysteresis = <0>;
	type = "critical";
	};
	};
	cooling-maps {
	};
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clock - can be overridden by the board */
	usb_extal_clk: usb_extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <48000000>;
	};
	};
	diff --git a/sys/gnu/dts/arm/r8a7791-koelsch.dts b/sys/gnu/dts/arm/r8a7791-koelsch.dts
	index 2b096d5e06fb..fc74c6cd6def 100644
	--- a/sys/gnu/dts/arm/r8a7791-koelsch.dts
	+++ b/sys/gnu/dts/arm/r8a7791-koelsch.dts
	@@ -1,901 +1,900 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the Koelsch board
	*
	* Copyright (C) 2013 Renesas Electronics Corporation
	* Copyright (C) 2013-2014 Renesas Solutions Corp.
	* Copyright (C) 2014 Cogent Embedded, Inc.
	*/

	/*
	* SSI-AK4643
	*
	* SW1: 1: AK4643
	* 2: CN22
	* 3: ADV7511
	*
	* This command is required when Playback/Capture
	*
	* amixer set "LINEOUT Mixer DACL" on
	* amixer set "DVC Out" 100%
	* amixer set "DVC In" 100%
	*
	* You can use Mute
	*
	* amixer set "DVC Out Mute" on
	* amixer set "DVC In Mute" on
	*
	* You can use Volume Ramp
	*
	* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
	* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
	* amixer set "DVC Out Ramp" on
	* aplay xxx.wav &
	* amixer set "DVC Out" 80% // Volume Down
	* amixer set "DVC Out" 100% // Volume Up
	*/

	/dts-v1/;
	#include "r8a7791.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>

	/ {
	model = "Koelsch";
	compatible = "renesas,koelsch", "renesas,r8a7791";

	aliases {
	serial0 = &scif0;
	serial1 = &scif1;
	i2c9 = &gpioi2c1;
	i2c10 = &gpioi2c2;
	i2c11 = &gpioi2c4;
	i2c12 = &i2cexio1;
	i2c13 = &i2chdmi;
	i2c14 = &i2cexio4;
	};

	chosen {
	bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
	stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
	device_type = "memory";
	reg = <0 0x40000000 0 0x40000000>;
	};

	memory@200000000 {
	device_type = "memory";
	reg = <2 0x00000000 0 0x40000000>;
	};

	lbsc {
	#address-cells = <1>;
	#size-cells = <1>;
	};

	keyboard {
	compatible = "gpio-keys";

	key-1 {
	gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_1>;
	label = "SW2-1";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-2 {
	gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_2>;
	label = "SW2-2";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-3 {
	gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_3>;
	label = "SW2-3";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-4 {
	gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_4>;
	label = "SW2-4";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-a {
	gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_A>;
	label = "SW30";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-b {
	gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_B>;
	label = "SW31";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-c {
	gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_C>;
	label = "SW32";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-d {
	gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_D>;
	label = "SW33";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-e {
	gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_E>;
	label = "SW34";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-f {
	gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_F>;
	label = "SW35";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-g {
	gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_G>;
	label = "SW36";
	wakeup-source;
	debounce-interval = <20>;
	};
	};

	leds {
	compatible = "gpio-leds";
	led6 {
	gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
	label = "LED6";
	};
	led7 {
	gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
	label = "LED7";
	};
	led8 {
	gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
	label = "LED8";
	};
	};

	vcc_sdhi0: regulator-vcc-sdhi0 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI0 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vccq_sdhi0: regulator-vccq-sdhi0 {
	compatible = "regulator-gpio";

	regulator-name = "SDHI0 VccQ";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
	gpios-states = <1>;
	states = <3300000 1>, <1800000 0>;
	};

	vcc_sdhi1: regulator-vcc-sdhi1 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI1 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vccq_sdhi1: regulator-vccq-sdhi1 {
	compatible = "regulator-gpio";

	regulator-name = "SDHI1 VccQ";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
	gpios-states = <1>;
	states = <3300000 1>, <1800000 0>;
	};

	vcc_sdhi2: regulator-vcc-sdhi2 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI2 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vccq_sdhi2: regulator-vccq-sdhi2 {
	compatible = "regulator-gpio";

	regulator-name = "SDHI2 VccQ";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
	gpios-states = <1>;
	states = <3300000 1>, <1800000 0>;
	};

	audio_clock: audio_clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <11289600>;
	};

	rsnd_ak4643: sound {
	compatible = "simple-audio-card";

	simple-audio-card,format = "left_j";
	simple-audio-card,bitclock-master = <&sndcodec>;
	simple-audio-card,frame-master = <&sndcodec>;

	sndcpu: simple-audio-card,cpu {
	sound-dai = <&rcar_sound>;
	};

	sndcodec: simple-audio-card,codec {
	sound-dai = <&ak4643>;
	clocks = <&audio_clock>;
	};
	};

	hdmi-in {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con_in: endpoint {
	remote-endpoint = <&adv7612_in>;
	};
	};
	};

	cec_clock: cec-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <12000000>;
	};

	hdmi-out {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con_out: endpoint {
	remote-endpoint = <&adv7511_out>;
	};
	};
	};

	x2_clk: x2-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <74250000>;
	};

	x13_clk: x13-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <148500000>;
	};

	gpioi2c1: i2c-9 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "i2c-gpio";
	status = "disabled";
	scl-gpios = <&gpio7 15 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	i2c-gpio,delay-us = <5>;
	};

	gpioi2c2: i2c-10 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "i2c-gpio";
	status = "disabled";
	scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	i2c-gpio,delay-us = <5>;
	};

	gpioi2c4: i2c-11 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "i2c-gpio";
	status = "disabled";
	scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	i2c-gpio,delay-us = <5>;
	};

	/*
	* I2C1 is routed to EXIO connector B, pins 64 (SCL) + 66 (SDA).
	* A fallback to GPIO is provided.
	*/
	i2cexio1: i2c-12 {
	compatible = "i2c-demux-pinctrl";
	i2c-parent = <&i2c1>, <&gpioi2c1>;
	i2c-bus-name = "i2c-exio1";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	/*
	* A fallback to GPIO is provided for I2C2.
	*/
	i2chdmi: i2c-13 {
	compatible = "i2c-demux-pinctrl";
	i2c-parent = <&i2c2>, <&gpioi2c2>;
	i2c-bus-name = "i2c-hdmi";
	#address-cells = <1>;
	#size-cells = <0>;

	ak4643: codec@12 {
	compatible = "asahi-kasei,ak4643";
	#sound-dai-cells = <0>;
	reg = <0x12>;
	};

	composite-in@20 {
	compatible = "adi,adv7180";
	reg = <0x20>;
	remote = <&vin1>;

	port {
	adv7180: endpoint {
	bus-width = <8>;
	remote-endpoint = <&vin1ep>;
	};
	};
	};

	hdmi@39 {
	compatible = "adi,adv7511w";
	reg = <0x39>;
	interrupt-parent = <&gpio3>;
	interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&cec_clock>;
	clock-names = "cec";

	adi,input-depth = <8>;
	adi,input-colorspace = "rgb";
	adi,input-clock = "1x";
	- adi,input-style = <1>;
	- adi,input-justification = "evenly";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7511_in: endpoint {
	remote-endpoint = <&du_out_rgb>;
	};
	};

	port@1 {
	reg = <1>;
	adv7511_out: endpoint {
	remote-endpoint = <&hdmi_con_out>;
	};
	};
	};
	};

	hdmi-in@4c {
	compatible = "adi,adv7612";
	reg = <0x4c>;
	interrupt-parent = <&gpio4>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
	default-input = <0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7612_in: endpoint {
	remote-endpoint = <&hdmi_con_in>;
	};
	};

	port@2 {
	reg = <2>;
	adv7612_out: endpoint {
	remote-endpoint = <&vin0ep2>;
	};
	};
	};
	};

	eeprom@50 {
	compatible = "renesas,r1ex24002", "atmel,24c02";
	reg = <0x50>;
	pagesize = <16>;
	};
	};

	/*
	* I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA).
	* A fallback to GPIO is provided.
	*/
	i2cexio4: i2c-14 {
	compatible = "i2c-demux-pinctrl";
	i2c-parent = <&i2c4>, <&gpioi2c4>;
	i2c-bus-name = "i2c-exio4";
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";
	status = "okay";

	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
	<&x13_clk>, <&x2_clk>;
	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";

	ports {
	port@0 {
	endpoint {
	remote-endpoint = <&adv7511_in>;
	};
	};
	};
	};

	&lvds0 {
	ports {
	port@1 {
	lvds_connector: endpoint {
	};
	};
	};
	};

	&extal_clk {
	clock-frequency = <20000000>;
	};

	&pfc {
	pinctrl-0 = <&scif_clk_pins>;
	pinctrl-names = "default";

	i2c1_pins: i2c1 {
	groups = "i2c1";
	function = "i2c1";
	};

	i2c2_pins: i2c2 {
	groups = "i2c2";
	function = "i2c2";
	};

	i2c4_pins: i2c4 {
	groups = "i2c4_c";
	function = "i2c4";
	};

	du_pins: du {
	groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
	function = "du";
	};

	scif0_pins: scif0 {
	groups = "scif0_data_d";
	function = "scif0";
	};

	scif1_pins: scif1 {
	groups = "scif1_data_d";
	function = "scif1";
	};

	scif_clk_pins: scif_clk {
	groups = "scif_clk";
	function = "scif_clk";
	};

	ether_pins: ether {
	groups = "eth_link", "eth_mdio", "eth_rmii";
	function = "eth";
	};

	phy1_pins: phy1 {
	groups = "intc_irq0";
	function = "intc";
	};

	pmic_irq_pins: pmicirq {
	groups = "intc_irq2";
	function = "intc";
	};

	sdhi0_pins: sd0 {
	groups = "sdhi0_data4", "sdhi0_ctrl";
	function = "sdhi0";
	power-source = <3300>;
	};

	sdhi0_pins_uhs: sd0_uhs {
	groups = "sdhi0_data4", "sdhi0_ctrl";
	function = "sdhi0";
	power-source = <1800>;
	};

	sdhi1_pins: sd1 {
	groups = "sdhi1_data4", "sdhi1_ctrl";
	function = "sdhi1";
	power-source = <3300>;
	};

	sdhi1_pins_uhs: sd1_uhs {
	groups = "sdhi1_data4", "sdhi1_ctrl";
	function = "sdhi1";
	power-source = <1800>;
	};

	sdhi2_pins: sd2 {
	groups = "sdhi2_data4", "sdhi2_ctrl";
	function = "sdhi2";
	power-source = <3300>;
	};

	sdhi2_pins_uhs: sd2_uhs {
	groups = "sdhi2_data4", "sdhi2_ctrl";
	function = "sdhi2";
	power-source = <1800>;
	};

	qspi_pins: qspi {
	groups = "qspi_ctrl", "qspi_data4";
	function = "qspi";
	};

	msiof0_pins: msiof0 {
	groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
	"msiof0_tx";
	function = "msiof0";
	};

	usb0_pins: usb0 {
	groups = "usb0";
	function = "usb0";
	};

	usb1_pins: usb1 {
	groups = "usb1";
	function = "usb1";
	};

	vin0_pins: vin0 {
	groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
	function = "vin0";
	};

	vin1_pins: vin1 {
	groups = "vin1_data8", "vin1_clk";
	function = "vin1";
	};

	sound_pins: sound {
	groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
	function = "ssi";
	};

	sound_clk_pins: sound_clk {
	groups = "audio_clk_a";
	function = "audio_clk";
	};
	};

	&ether {
	pinctrl-0 = <&ether_pins &phy1_pins>;
	pinctrl-names = "default";

	phy-handle = <&phy1>;
	renesas,ether-link-active-low;
	status = "okay";

	phy1: ethernet-phy@1 {
	reg = <1>;
	interrupt-parent = <&irqc0>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	micrel,led-mode = <1>;
	+ reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
	};
	};

	&cmt0 {
	status = "okay";
	};

	&rwdt {
	timeout-sec = <60>;
	status = "okay";
	};

	&sata0 {
	status = "okay";
	};

	&scif0 {
	pinctrl-0 = <&scif0_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&scif1 {
	pinctrl-0 = <&scif1_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&scif_clk {
	clock-frequency = <14745600>;
	};

	&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-1 = <&sdhi0_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi0>;
	vqmmc-supply = <&vccq_sdhi0>;
	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
	};

	&sdhi1 {
	pinctrl-0 = <&sdhi1_pins>;
	pinctrl-1 = <&sdhi1_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi1>;
	vqmmc-supply = <&vccq_sdhi1>;
	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
	sd-uhs-sdr50;
	status = "okay";
	};

	&sdhi2 {
	pinctrl-0 = <&sdhi2_pins>;
	pinctrl-1 = <&sdhi2_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi2>;
	vqmmc-supply = <&vccq_sdhi2>;
	cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
	sd-uhs-sdr50;
	status = "okay";
	};

	&qspi {
	pinctrl-0 = <&qspi_pins>;
	pinctrl-names = "default";

	status = "okay";

	flash: flash@0 {
	compatible = "spansion,s25fl512s", "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <30000000>;
	spi-tx-bus-width = <4>;
	spi-rx-bus-width = <4>;
	spi-cpha;
	spi-cpol;
	m25p,fast-read;

	partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
	label = "loader";
	reg = <0x00000000 0x00080000>;
	read-only;
	};
	partition@80000 {
	label = "user";
	reg = <0x00080000 0x00580000>;
	read-only;
	};
	partition@600000 {
	label = "flash";
	reg = <0x00600000 0x03a00000>;
	};
	};
	};
	};

	&msiof0 {
	pinctrl-0 = <&msiof0_pins>;
	pinctrl-names = "default";

	status = "okay";

	pmic: pmic@0 {
	compatible = "renesas,r2a11302ft";
	reg = <0>;
	spi-max-frequency = <6000000>;
	spi-cpol;
	spi-cpha;
	};
	};

	&i2c1 {
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-names = "i2c-exio1";
	};

	&i2c2 {
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-names = "i2c-hdmi";

	clock-frequency = <100000>;
	};

	&i2c4 {
	pinctrl-0 = <&i2c4_pins>;
	pinctrl-names = "i2c-exio4";
	};

	&i2c6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_irq_pins>;
	status = "okay";
	clock-frequency = <100000>;

	pmic@58 {
	compatible = "dlg,da9063";
	reg = <0x58>;
	interrupt-parent = <&irqc0>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;

	rtc {
	compatible = "dlg,da9063-rtc";
	};

	wdt {
	compatible = "dlg,da9063-watchdog";
	};
	};

	vdd_dvfs: regulator@68 {
	compatible = "dlg,da9210";
	reg = <0x68>;
	interrupt-parent = <&irqc0>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;

	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};

	&pci0 {
	status = "okay";
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";
	};

	&pci1 {
	status = "okay";
	pinctrl-0 = <&usb1_pins>;
	pinctrl-names = "default";
	};

	&hsusb {
	status = "okay";
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";
	renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
	};

	&usbphy {
	status = "okay";
	};

	&pcie_bus_clk {
	clock-frequency = <100000000>;
	};

	&pciec {
	status = "okay";
	};

	&cpu0 {
	cpu0-supply = <&vdd_dvfs>;
	};

	/* HDMI video input */
	&vin0 {
	status = "okay";
	pinctrl-0 = <&vin0_pins>;
	pinctrl-names = "default";

	port {
	vin0ep2: endpoint {
	remote-endpoint = <&adv7612_out>;
	bus-width = <24>;
	hsync-active = <0>;
	vsync-active = <0>;
	pclk-sample = <1>;
	data-active = <1>;
	};
	};
	};

	/* composite video input */
	&vin1 {
	status = "okay";
	pinctrl-0 = <&vin1_pins>;
	pinctrl-names = "default";

	port {
	vin1ep: endpoint {
	remote-endpoint = <&adv7180>;
	bus-width = <8>;
	};
	};
	};

	&rcar_sound {
	pinctrl-0 = <&sound_pins &sound_clk_pins>;
	pinctrl-names = "default";

	/* Single DAI */
	#sound-dai-cells = <0>;

	status = "okay";

	rcar_sound,dai {
	dai0 {
	playback = <&ssi0 &src2 &dvc0>;
	capture = <&ssi1 &src3 &dvc1>;
	};
	};
	};

	&ssi1 {
	shared-pin;
	};
	diff --git a/sys/gnu/dts/arm/r8a7791-porter.dts b/sys/gnu/dts/arm/r8a7791-porter.dts
	index f9ece7ab2010..114bf1c4199b 100644
	--- a/sys/gnu/dts/arm/r8a7791-porter.dts
	+++ b/sys/gnu/dts/arm/r8a7791-porter.dts
	@@ -1,521 +1,520 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the Porter board
	*
	* Copyright (C) 2015 Cogent Embedded, Inc.
	*/

	/*
	* SSI-AK4642
	*
	* JP3: 2-1: AK4642
	* 2-3: ADV7511
	*
	* This command is required before playback/capture:
	*
	* amixer set "LINEOUT Mixer DACL" on
	*/

	/dts-v1/;
	#include "r8a7791.dtsi"
	#include <dt-bindings/gpio/gpio.h>

	/ {
	model = "Porter";
	compatible = "renesas,porter", "renesas,r8a7791";

	aliases {
	serial0 = &scif0;
	i2c9 = &gpioi2c2;
	i2c10 = &i2chdmi;
	};

	chosen {
	bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
	stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
	device_type = "memory";
	reg = <0 0x40000000 0 0x40000000>;
	};

	memory@200000000 {
	device_type = "memory";
	reg = <2 0x00000000 0 0x40000000>;
	};

	vcc_sdhi0: regulator-vcc-sdhi0 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI0 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vccq_sdhi0: regulator-vccq-sdhi0 {
	compatible = "regulator-gpio";

	regulator-name = "SDHI0 VccQ";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
	gpios-states = <1>;
	states = <3300000 1>, <1800000 0>;
	};

	vcc_sdhi2: regulator-vcc-sdhi2 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI2 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vccq_sdhi2: regulator-vccq-sdhi2 {
	compatible = "regulator-gpio";

	regulator-name = "SDHI2 VccQ";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
	gpios-states = <1>;
	states = <3300000 1>, <1800000 0>;
	};

	hdmi-out {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con: endpoint {
	remote-endpoint = <&adv7511_out>;
	};
	};
	};

	x3_clk: x3-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <148500000>;
	};

	x16_clk: x16-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <74250000>;
	};

	x14_clk: audio_clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <11289600>;
	};

	sound {
	compatible = "simple-audio-card";

	simple-audio-card,format = "left_j";
	simple-audio-card,bitclock-master = <&soundcodec>;
	simple-audio-card,frame-master = <&soundcodec>;

	simple-audio-card,cpu {
	sound-dai = <&rcar_sound>;
	};

	soundcodec: simple-audio-card,codec {
	sound-dai = <&ak4642>;
	clocks = <&x14_clk>;
	};
	};

	gpioi2c2: i2c-9 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "i2c-gpio";
	status = "disabled";
	scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	i2c-gpio,delay-us = <5>;
	};

	/*
	* A fallback to GPIO is provided for I2C2.
	*/
	i2chdmi: i2c-10 {
	compatible = "i2c-demux-pinctrl";
	i2c-parent = <&i2c2>, <&gpioi2c2>;
	i2c-bus-name = "i2c-hdmi";
	#address-cells = <1>;
	#size-cells = <0>;

	ak4642: codec@12 {
	compatible = "asahi-kasei,ak4642";
	#sound-dai-cells = <0>;
	reg = <0x12>;
	};

	composite-in@20 {
	compatible = "adi,adv7180";
	reg = <0x20>;
	remote = <&vin0>;

	port {
	adv7180: endpoint {
	bus-width = <8>;
	remote-endpoint = <&vin0ep>;
	};
	};
	};

	hdmi@39 {
	compatible = "adi,adv7511w";
	reg = <0x39>;
	interrupt-parent = <&gpio3>;
	interrupts = <29 IRQ_TYPE_LEVEL_LOW>;

	adi,input-depth = <8>;
	adi,input-colorspace = "rgb";
	adi,input-clock = "1x";
	- adi,input-style = <1>;
	- adi,input-justification = "evenly";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7511_in: endpoint {
	remote-endpoint = <&du_out_rgb>;
	};
	};

	port@1 {
	reg = <1>;
	adv7511_out: endpoint {
	remote-endpoint = <&hdmi_con>;
	};
	};
	};
	};
	};
	};

	&extal_clk {
	clock-frequency = <20000000>;
	};

	&pfc {
	scif0_pins: scif0 {
	groups = "scif0_data_d";
	function = "scif0";
	};

	ether_pins: ether {
	groups = "eth_link", "eth_mdio", "eth_rmii";
	function = "eth";
	};

	phy1_pins: phy1 {
	groups = "intc_irq0";
	function = "intc";
	};

	pmic_irq_pins: pmicirq {
	groups = "intc_irq2";
	function = "intc";
	};

	sdhi0_pins: sd0 {
	groups = "sdhi0_data4", "sdhi0_ctrl";
	function = "sdhi0";
	};

	sdhi2_pins: sd2 {
	groups = "sdhi2_data4", "sdhi2_ctrl";
	function = "sdhi2";
	};

	qspi_pins: qspi {
	groups = "qspi_ctrl", "qspi_data4";
	function = "qspi";
	};

	i2c2_pins: i2c2 {
	groups = "i2c2";
	function = "i2c2";
	};

	usb0_pins: usb0 {
	groups = "usb0";
	function = "usb0";
	};

	usb1_pins: usb1 {
	groups = "usb1";
	function = "usb1";
	};

	vin0_pins: vin0 {
	groups = "vin0_data8", "vin0_clk";
	function = "vin0";
	};

	can0_pins: can0 {
	groups = "can0_data";
	function = "can0";
	};

	du_pins: du {
	groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
	function = "du";
	};

	ssi_pins: sound {
	groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
	function = "ssi";
	};

	audio_clk_pins: audio_clk {
	groups = "audio_clk_a";
	function = "audio_clk";
	};
	};

	&scif0 {
	pinctrl-0 = <&scif0_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&ether {
	pinctrl-0 = <&ether_pins &phy1_pins>;
	pinctrl-names = "default";

	phy-handle = <&phy1>;
	renesas,ether-link-active-low;
	status = "okay";

	phy1: ethernet-phy@1 {
	reg = <1>;
	interrupt-parent = <&irqc0>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	micrel,led-mode = <1>;
	+ reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
	};
	};

	&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&vcc_sdhi0>;
	vqmmc-supply = <&vccq_sdhi0>;
	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
	status = "okay";
	};

	&sdhi2 {
	pinctrl-0 = <&sdhi2_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&vcc_sdhi2>;
	vqmmc-supply = <&vccq_sdhi2>;
	cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&qspi {
	pinctrl-0 = <&qspi_pins>;
	pinctrl-names = "default";

	status = "okay";

	flash@0 {
	compatible = "spansion,s25fl512s", "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <30000000>;
	spi-tx-bus-width = <4>;
	spi-rx-bus-width = <4>;
	m25p,fast-read;

	partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
	label = "loader_prg";
	reg = <0x00000000 0x00040000>;
	read-only;
	};
	partition@40000 {
	label = "user_prg";
	reg = <0x00040000 0x00400000>;
	read-only;
	};
	partition@440000 {
	label = "flash_fs";
	reg = <0x00440000 0x03bc0000>;
	};
	};
	};
	};

	&i2c2 {
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-names = "i2c-hdmi";

	clock-frequency = <400000>;
	};

	&i2c6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_irq_pins>;
	status = "okay";
	clock-frequency = <100000>;

	pmic@5a {
	compatible = "dlg,da9063l";
	reg = <0x5a>;
	interrupt-parent = <&irqc0>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;

	wdt {
	compatible = "dlg,da9063-watchdog";
	};
	};

	vdd_dvfs: regulator@68 {
	compatible = "dlg,da9210";
	reg = <0x68>;
	interrupt-parent = <&irqc0>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;

	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};

	&sata0 {
	status = "okay";
	};

	&cpu0 {
	cpu0-supply = <&vdd_dvfs>;
	};

	/* composite video input */
	&vin0 {
	status = "okay";
	pinctrl-0 = <&vin0_pins>;
	pinctrl-names = "default";

	port {
	vin0ep: endpoint {
	remote-endpoint = <&adv7180>;
	bus-width = <8>;
	};
	};
	};

	&pci0 {
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&pci1 {
	pinctrl-0 = <&usb1_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&hsusb {
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&usbphy {
	status = "okay";
	};

	&pcie_bus_clk {
	clock-frequency = <100000000>;
	};

	&pciec {
	status = "okay";
	};

	&can0 {
	pinctrl-0 = <&can0_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";
	status = "okay";

	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
	<&x3_clk>, <&x16_clk>;
	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";

	ports {
	port@0 {
	endpoint {
	remote-endpoint = <&adv7511_in>;
	};
	};
	};
	};

	&lvds0 {
	ports {
	port@1 {
	lvds_connector: endpoint {
	};
	};
	};
	};

	&rcar_sound {
	pinctrl-0 = <&ssi_pins &audio_clk_pins>;
	pinctrl-names = "default";
	status = "okay";

	/* Single DAI */
	#sound-dai-cells = <0>;

	rcar_sound,dai {
	dai0 {
	playback = <&ssi0>;
	capture = <&ssi1>;
	};
	};
	};

	&rwdt {
	timeout-sec = <60>;
	status = "okay";
	};

	&ssi1 {
	shared-pin;
	};
	diff --git a/sys/gnu/dts/arm/r8a7791.dtsi b/sys/gnu/dts/arm/r8a7791.dtsi
	index 59a55e87fcc6..6e5bd86731cd 100644
	--- a/sys/gnu/dts/arm/r8a7791.dtsi
	+++ b/sys/gnu/dts/arm/r8a7791.dtsi
	@@ -1,1806 +1,1807 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the R-Car M2-W (R8A77910) SoC
	*
	* Copyright (C) 2013-2015 Renesas Electronics Corporation
	* Copyright (C) 2013-2014 Renesas Solutions Corp.
	* Copyright (C) 2014 Cogent Embedded Inc.
	*/

	#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/power/r8a7791-sysc.h>

	/ {
	compatible = "renesas,r8a7791";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	i2c6 = &i2c6;
	i2c7 = &i2c7;
	i2c8 = &i2c8;
	spi0 = &qspi;
	spi1 = &msiof0;
	spi2 = &msiof1;
	spi3 = &msiof2;
	vin0 = &vin0;
	vin1 = &vin1;
	vin2 = &vin2;
	};

	/*
	* The external audio clocks are configured as 0 Hz fixed frequency
	* clocks by default.
	* Boards that provide audio clocks should override them.
	*/
	audio_clk_a: audio_clk_a {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	audio_clk_b: audio_clk_b {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	audio_clk_c: audio_clk_c {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	/* External CAN clock */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "renesas,apmu";

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0>;
	clock-frequency = <1500000000>;
	clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
	power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
	next-level-cache = <&L2_CA15>;
	voltage-tolerance = <1>; /* 1% */
	clock-latency = <300000>; /* 300 us */

	/* kHz - uV - OPPs unknown yet */
	operating-points = <1500000 1000000>,
	<1312500 1000000>,
	<1125000 1000000>,
	< 937500 1000000>,
	< 750000 1000000>,
	< 375000 1000000>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <1>;
	clock-frequency = <1500000000>;
	clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
	power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
	next-level-cache = <&L2_CA15>;
	voltage-tolerance = <1>; /* 1% */
	clock-latency = <300000>; /* 300 us */

	/* kHz - uV - OPPs unknown yet */
	operating-points = <1500000 1000000>,
	<1312500 1000000>,
	<1125000 1000000>,
	< 937500 1000000>,
	< 750000 1000000>,
	< 375000 1000000>;
	};

	L2_CA15: cache-controller-0 {
	compatible = "cache";
	power-domains = <&sysc R8A7791_PD_CA15_SCU>;
	cache-unified;
	cache-level = <2>;
	};
	};

	/* External root clock */
	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	/* External PCIe clock - can be overridden by the board */
	pcie_bus_clk: pcie_bus {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	pmu {
	compatible = "arm,cortex-a15-pmu";
	interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	/* External SCIF clock */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;

	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a7791-wdt",
	"renesas,rcar-gen2-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a7791",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a7791",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a7791",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a7791",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a7791",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a7791",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	gpio6: gpio@e6055400 {
	compatible = "renesas,gpio-r8a7791",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055400 0 0x50>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 192 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 905>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 905>;
	};

	gpio7: gpio@e6055800 {
	compatible = "renesas,gpio-r8a7791",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055800 0 0x50>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 224 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 904>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 904>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a7791";
	reg = <0 0xe6060000 0 0x250>;
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a7791-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>, <&usb_extal_clk>;
	clock-names = "extal", "usb_extal";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	apmu@e6152000 {
	compatible = "renesas,r8a7791-apmu", "renesas,apmu";
	reg = <0 0xe6152000 0 0x188>;
	cpus = <&cpu0 &cpu1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a7791-rst";
	reg = <0 0xe6160000 0 0x0100>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a7791-sysc";
	reg = <0 0xe6180000 0 0x0200>;
	#power-domain-cells = <1>;
	};

	irqc0: interrupt-controller@e61c0000 {
	compatible = "renesas,irqc-r8a7791", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	thermal: thermal@e61f0000 {
	compatible = "renesas,thermal-r8a7791",
	"renesas,rcar-gen2-thermal",
	"renesas,rcar-thermal";
	reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 522>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 522>;
	#thermal-sensor-cells = <0>;
	};

	ipmmu_sy0: mmu@e6280000 {
	compatible = "renesas,ipmmu-r8a7791",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6280000 0 0x1000>;
	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_sy1: mmu@e6290000 {
	compatible = "renesas,ipmmu-r8a7791",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6290000 0 0x1000>;
	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_ds: mmu@e6740000 {
	compatible = "renesas,ipmmu-r8a7791",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6740000 0 0x1000>;
	interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_mp: mmu@ec680000 {
	compatible = "renesas,ipmmu-r8a7791",
	"renesas,ipmmu-vmsa";
	reg = <0 0xec680000 0 0x1000>;
	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_mx: mmu@fe951000 {
	compatible = "renesas,ipmmu-r8a7791",
	"renesas,ipmmu-vmsa";
	reg = <0 0xfe951000 0 0x1000>;
	interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_rt: mmu@ffc80000 {
	compatible = "renesas,ipmmu-r8a7791",
	"renesas,ipmmu-vmsa";
	reg = <0 0xffc80000 0 0x1000>;
	interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_gp: mmu@e62a0000 {
	compatible = "renesas,ipmmu-r8a7791",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe62a0000 0 0x1000>;
	interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	icram0: sram@e63a0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63a0000 0 0x12000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63a0000 0x12000>;
	};

	icram1: sram@e63c0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63c0000 0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63c0000 0x1000>;

	smp-sram@0 {
	compatible = "renesas,smp-sram";
	reg = <0 0x100>;
	};
	};

	/* The memory map in the User's Manual maps the cores to
	* bus numbers
	*/
	i2c0: i2c@e6508000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7791",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c1: i2c@e6518000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7791",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6518000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c2: i2c@e6530000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7791",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6530000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c3: i2c@e6540000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7791",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6540000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c4: i2c@e6520000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7791",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6520000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c5: i2c@e6528000 {
	/* doesn't need pinmux */
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7791",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6528000 0 0x40>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 925>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 925>;
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c6: i2c@e60b0000 {
	/* doesn't need pinmux */
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7791",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe60b0000 0 0x425>;
	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 926>;
	dmas = <&dmac0 0x77>, <&dmac0 0x78>,
	<&dmac1 0x77>, <&dmac1 0x78>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 926>;
	status = "disabled";
	};

	i2c7: i2c@e6500000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7791",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe6500000 0 0x425>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 318>;
	dmas = <&dmac0 0x61>, <&dmac0 0x62>,
	<&dmac1 0x61>, <&dmac1 0x62>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 318>;
	status = "disabled";
	};

	i2c8: i2c@e6510000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7791",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe6510000 0 0x425>;
	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 323>;
	dmas = <&dmac0 0x65>, <&dmac0 0x66>,
	<&dmac1 0x65>, <&dmac1 0x66>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 323>;
	status = "disabled";
	};

	hsusb: usb@e6590000 {
	compatible = "renesas,usbhs-r8a7791",
	"renesas,rcar-gen2-usbhs";
	reg = <0 0xe6590000 0 0x100>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 704>;
	dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
	<&usb_dmac1 0>, <&usb_dmac1 1>;
	dma-names = "ch0", "ch1", "ch2", "ch3";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 704>;
	renesas,buswait = <4>;
	phys = <&usb0 1>;
	phy-names = "usb";
	status = "disabled";
	};

	usbphy: usb-phy@e6590100 {
	compatible = "renesas,usb-phy-r8a7791",
	"renesas,rcar-gen2-usb-phy";
	reg = <0 0xe6590100 0 0x100>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cpg CPG_MOD 704>;
	clock-names = "usbhs";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 704>;
	status = "disabled";

	usb0: usb-channel@0 {
	reg = <0>;
	#phy-cells = <1>;
	};
	usb2: usb-channel@2 {
	reg = <2>;
	#phy-cells = <1>;
	};
	};

	usb_dmac0: dma-controller@e65a0000 {
	compatible = "renesas,r8a7791-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65a0000 0 0x100>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 330>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 330>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac1: dma-controller@e65b0000 {
	compatible = "renesas,r8a7791-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65b0000 0 0x100>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 331>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 331>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a7791",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x20000>;
	interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	dmac1: dma-controller@e6720000 {
	compatible = "renesas,dmac-r8a7791",
	"renesas,rcar-dmac";
	reg = <0 0xe6720000 0 0x20000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a7791",
	"renesas,etheravb-rcar-gen2";
	reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
	interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	qspi: spi@e6b10000 {
	compatible = "renesas,qspi-r8a7791", "renesas,qspi";
	reg = <0 0xe6b10000 0 0x2c>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 917>;
	dmas = <&dmac0 0x17>, <&dmac0 0x18>,
	<&dmac1 0x17>, <&dmac1 0x18>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 917>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	scifa0: serial@e6c40000 {
	compatible = "renesas,scifa-r8a7791",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c40000 0 64>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 204>;
	clock-names = "fck";
	dmas = <&dmac0 0x21>, <&dmac0 0x22>,
	<&dmac1 0x21>, <&dmac1 0x22>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 204>;
	status = "disabled";
	};

	scifa1: serial@e6c50000 {
	compatible = "renesas,scifa-r8a7791",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c50000 0 64>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 203>;
	clock-names = "fck";
	dmas = <&dmac0 0x25>, <&dmac0 0x26>,
	<&dmac1 0x25>, <&dmac1 0x26>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 203>;
	status = "disabled";
	};

	scifa2: serial@e6c60000 {
	compatible = "renesas,scifa-r8a7791",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c60000 0 64>;
	interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 202>;
	clock-names = "fck";
	dmas = <&dmac0 0x27>, <&dmac0 0x28>,
	<&dmac1 0x27>, <&dmac1 0x28>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 202>;
	status = "disabled";
	};

	scifa3: serial@e6c70000 {
	compatible = "renesas,scifa-r8a7791",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c70000 0 64>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1106>;
	clock-names = "fck";
	dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
	<&dmac1 0x1b>, <&dmac1 0x1c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 1106>;
	status = "disabled";
	};

	scifa4: serial@e6c78000 {
	compatible = "renesas,scifa-r8a7791",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c78000 0 64>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1107>;
	clock-names = "fck";
	dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
	<&dmac1 0x1f>, <&dmac1 0x20>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 1107>;
	status = "disabled";
	};

	scifa5: serial@e6c80000 {
	compatible = "renesas,scifa-r8a7791",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c80000 0 64>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1108>;
	clock-names = "fck";
	dmas = <&dmac0 0x23>, <&dmac0 0x24>,
	<&dmac1 0x23>, <&dmac1 0x24>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 1108>;
	status = "disabled";
	};

	scifb0: serial@e6c20000 {
	compatible = "renesas,scifb-r8a7791",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6c20000 0 0x100>;
	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 206>;
	clock-names = "fck";
	dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
	<&dmac1 0x3d>, <&dmac1 0x3e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 206>;
	status = "disabled";
	};

	scifb1: serial@e6c30000 {
	compatible = "renesas,scifb-r8a7791",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6c30000 0 0x100>;
	interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 207>;
	clock-names = "fck";
	dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
	<&dmac1 0x19>, <&dmac1 0x1a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 207>;
	status = "disabled";
	};

	scifb2: serial@e6ce0000 {
	compatible = "renesas,scifb-r8a7791",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6ce0000 0 0x100>;
	interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 216>;
	clock-names = "fck";
	dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
	<&dmac1 0x1d>, <&dmac1 0x1e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 216>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a7791",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e60000 0 64>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
	<&dmac1 0x29>, <&dmac1 0x2a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 721>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a7791",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e68000 0 64>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
	<&dmac1 0x2d>, <&dmac1 0x2e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 720>;
	status = "disabled";
	};

	scif2: serial@e6e58000 {
	compatible = "renesas,scif-r8a7791",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e58000 0 64>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
	<&dmac1 0x2b>, <&dmac1 0x2c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 719>;
	status = "disabled";
	};

	scif3: serial@e6ea8000 {
	compatible = "renesas,scif-r8a7791",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ea8000 0 64>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
	<&dmac1 0x2f>, <&dmac1 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 718>;
	status = "disabled";
	};

	scif4: serial@e6ee0000 {
	compatible = "renesas,scif-r8a7791",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ee0000 0 64>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
	<&dmac1 0xfb>, <&dmac1 0xfc>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 715>;
	status = "disabled";
	};

	scif5: serial@e6ee8000 {
	compatible = "renesas,scif-r8a7791",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ee8000 0 64>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
	<&dmac1 0xfd>, <&dmac1 0xfe>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 714>;
	status = "disabled";
	};

	hscif0: serial@e62c0000 {
	compatible = "renesas,hscif-r8a7791",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c0000 0 96>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
	<&dmac1 0x39>, <&dmac1 0x3a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 717>;
	status = "disabled";
	};

	hscif1: serial@e62c8000 {
	compatible = "renesas,hscif-r8a7791",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c8000 0 96>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
	<&dmac1 0x4d>, <&dmac1 0x4e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";
	};

	hscif2: serial@e62d0000 {
	compatible = "renesas,hscif-r8a7791",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62d0000 0 96>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
	<&dmac1 0x3b>, <&dmac1 0x3c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 713>;
	status = "disabled";
	};

	msiof0: spi@e6e20000 {
	compatible = "renesas,msiof-r8a7791",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6e20000 0 0x0064>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 000>;
	dmas = <&dmac0 0x51>, <&dmac0 0x52>,
	<&dmac1 0x51>, <&dmac1 0x52>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 0>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof1: spi@e6e10000 {
	compatible = "renesas,msiof-r8a7791",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6e10000 0 0x0064>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 208>;
	dmas = <&dmac0 0x55>, <&dmac0 0x56>,
	<&dmac1 0x55>, <&dmac1 0x56>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 208>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof2: spi@e6e00000 {
	compatible = "renesas,msiof-r8a7791",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6e00000 0 0x0064>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 205>;
	dmas = <&dmac0 0x41>, <&dmac0 0x42>,
	<&dmac1 0x41>, <&dmac1 0x42>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 205>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	adc: adc@e6e54000 {
	compatible = "renesas,r8a7791-gyroadc",
	"renesas,rcar-gyroadc";
	reg = <0 0xe6e54000 0 64>;
	clocks = <&cpg CPG_MOD 901>;
	clock-names = "fck";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 901>;
	status = "disabled";
	};

	can0: can@e6e80000 {
	compatible = "renesas,can-r8a7791",
	"renesas,rcar-gen2-can";
	reg = <0 0xe6e80000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 916>,
	<&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 916>;
	status = "disabled";
	};

	can1: can@e6e88000 {
	compatible = "renesas,can-r8a7791",
	"renesas,rcar-gen2-can";
	reg = <0 0xe6e88000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 915>,
	<&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 915>;
	status = "disabled";
	};

	vin0: video@e6ef0000 {
	compatible = "renesas,vin-r8a7791",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef0000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 811>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 811>;
	status = "disabled";
	};

	vin1: video@e6ef1000 {
	compatible = "renesas,vin-r8a7791",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef1000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 810>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 810>;
	status = "disabled";
	};

	vin2: video@e6ef2000 {
	compatible = "renesas,vin-r8a7791",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef2000 0 0x1000>;
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 809>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 809>;
	status = "disabled";
	};

	rcar_sound: sound@ec500000 {
	/*
	* #sound-dai-cells is required
	*
	* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
	* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
	*/
	compatible = "renesas,rcar_sound-r8a7791",
	"renesas,rcar_sound-gen2";
	reg = <0 0xec500000 0 0x1000>, /* SCU */
	<0 0xec5a0000 0 0x100>, /* ADG */
	<0 0xec540000 0 0x1000>, /* SSIU */
	<0 0xec541000 0 0x280>, /* SSI */
	<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
	reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

	clocks = <&cpg CPG_MOD 1005>,
	<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
	<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
	<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
	<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
	<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
	<&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
	<&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
	<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
	<&cpg CPG_CORE R8A7791_CLK_M2>;
	clock-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0", "src.9", "src.8",
	"src.7", "src.6", "src.5", "src.4",
	"src.3", "src.2", "src.1", "src.0",
	"ctu.0", "ctu.1",
	"mix.0", "mix.1",
	"dvc.0", "dvc.1",
	"clk_a", "clk_b", "clk_c", "clk_i";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 1005>,
	<&cpg 1006>, <&cpg 1007>,
	<&cpg 1008>, <&cpg 1009>,
	<&cpg 1010>, <&cpg 1011>,
	<&cpg 1012>, <&cpg 1013>,
	<&cpg 1014>, <&cpg 1015>;
	reset-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0";

	status = "disabled";

	rcar_sound,dvc {
	dvc0: dvc-0 {
	dmas = <&audma1 0xbc>;
	dma-names = "tx";
	};
	dvc1: dvc-1 {
	dmas = <&audma1 0xbe>;
	dma-names = "tx";
	};
	};

	rcar_sound,mix {
	mix0: mix-0 { };
	mix1: mix-1 { };
	};

	rcar_sound,ctu {
	ctu00: ctu-0 { };
	ctu01: ctu-1 { };
	ctu02: ctu-2 { };
	ctu03: ctu-3 { };
	ctu10: ctu-4 { };
	ctu11: ctu-5 { };
	ctu12: ctu-6 { };
	ctu13: ctu-7 { };
	};

	rcar_sound,src {
	src0: src-0 {
	interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x85>, <&audma1 0x9a>;
	dma-names = "rx", "tx";
	};
	src1: src-1 {
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x87>, <&audma1 0x9c>;
	dma-names = "rx", "tx";
	};
	src2: src-2 {
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x89>, <&audma1 0x9e>;
	dma-names = "rx", "tx";
	};
	src3: src-3 {
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8b>, <&audma1 0xa0>;
	dma-names = "rx", "tx";
	};
	src4: src-4 {
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8d>, <&audma1 0xb0>;
	dma-names = "rx", "tx";
	};
	src5: src-5 {
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8f>, <&audma1 0xb2>;
	dma-names = "rx", "tx";
	};
	src6: src-6 {
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x91>, <&audma1 0xb4>;
	dma-names = "rx", "tx";
	};
	src7: src-7 {
	interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x93>, <&audma1 0xb6>;
	dma-names = "rx", "tx";
	};
	src8: src-8 {
	interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x95>, <&audma1 0xb8>;
	dma-names = "rx", "tx";
	};
	src9: src-9 {
	interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x97>, <&audma1 0xba>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssi {
	ssi0: ssi-0 {
	interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x01>, <&audma1 0x02>,
	<&audma0 0x15>, <&audma1 0x16>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi1: ssi-1 {
	interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x03>, <&audma1 0x04>,
	<&audma0 0x49>, <&audma1 0x4a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi2: ssi-2 {
	interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x05>, <&audma1 0x06>,
	<&audma0 0x63>, <&audma1 0x64>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi3: ssi-3 {
	interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x07>, <&audma1 0x08>,
	<&audma0 0x6f>, <&audma1 0x70>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi4: ssi-4 {
	interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x09>, <&audma1 0x0a>,
	<&audma0 0x71>, <&audma1 0x72>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi5: ssi-5 {
	interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0b>, <&audma1 0x0c>,
	<&audma0 0x73>, <&audma1 0x74>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi6: ssi-6 {
	interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0d>, <&audma1 0x0e>,
	<&audma0 0x75>, <&audma1 0x76>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi7: ssi-7 {
	interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0f>, <&audma1 0x10>,
	<&audma0 0x79>, <&audma1 0x7a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi8: ssi-8 {
	interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x11>, <&audma1 0x12>,
	<&audma0 0x7b>, <&audma1 0x7c>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi9: ssi-9 {
	interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x13>, <&audma1 0x14>,
	<&audma0 0x7d>, <&audma1 0x7e>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	};
	};

	audma0: dma-controller@ec700000 {
	compatible = "renesas,dmac-r8a7791",
	"renesas,rcar-dmac";
	reg = <0 0xec700000 0 0x10000>;
	interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12";
	clocks = <&cpg CPG_MOD 502>;
	clock-names = "fck";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 502>;
	#dma-cells = <1>;
	dma-channels = <13>;
	};

	audma1: dma-controller@ec720000 {
	compatible = "renesas,dmac-r8a7791",
	"renesas,rcar-dmac";
	reg = <0 0xec720000 0 0x10000>;
	interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12";
	clocks = <&cpg CPG_MOD 501>;
	clock-names = "fck";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 501>;
	#dma-cells = <1>;
	dma-channels = <13>;
	};

	xhci: usb@ee000000 {
	compatible = "renesas,xhci-r8a7791",
	"renesas,rcar-gen2-xhci";
	reg = <0 0xee000000 0 0xc00>;
	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	phys = <&usb2 1>;
	phy-names = "usb";
	status = "disabled";
	};

	pci0: pci@ee090000 {
	compatible = "renesas,pci-r8a7791",
	"renesas,pci-rcar-gen2";
	device_type = "pci";
	reg = <0 0xee090000 0 0xc00>,
	<0 0xee080000 0 0x1100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 703>;
	status = "disabled";

	bus-range = <0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
	interrupt-map-mask = <0xf800 0 0 0x7>;
	interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

	usb@1,0 {
	reg = <0x800 0 0 0 0>;
	phys = <&usb0 0>;
	phy-names = "usb";
	};

	usb@2,0 {
	reg = <0x1000 0 0 0 0>;
	phys = <&usb0 0>;
	phy-names = "usb";
	};
	};

	pci1: pci@ee0d0000 {
	compatible = "renesas,pci-r8a7791",
	"renesas,pci-rcar-gen2";
	device_type = "pci";
	reg = <0 0xee0d0000 0 0xc00>,
	<0 0xee0c0000 0 0x1100>;
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 703>;
	status = "disabled";

	bus-range = <1 1>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
	interrupt-map-mask = <0xf800 0 0 0x7>;
	interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

	usb@1,0 {
	reg = <0x10800 0 0 0 0>;
	phys = <&usb2 0>;
	phy-names = "usb";
	};

	usb@2,0 {
	reg = <0x11000 0 0 0 0>;
	phys = <&usb2 0>;
	phy-names = "usb";
	};
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a7791",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee100000 0 0x328>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
	<&dmac1 0xcd>, <&dmac1 0xce>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <195000000>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	status = "disabled";
	};

	sdhi1: sd@ee140000 {
	compatible = "renesas,sdhi-r8a7791",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee140000 0 0x100>;
	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 312>;
	dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
	<&dmac1 0xc1>, <&dmac1 0xc2>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <97500000>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 312>;
	status = "disabled";
	};

	sdhi2: sd@ee160000 {
	compatible = "renesas,sdhi-r8a7791",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee160000 0 0x100>;
	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 311>;
	dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
	<&dmac1 0xd3>, <&dmac1 0xd4>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <97500000>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 311>;
	status = "disabled";
	};

	mmcif0: mmc@ee200000 {
	compatible = "renesas,mmcif-r8a7791",
	"renesas,sh-mmcif";
	reg = <0 0xee200000 0 0x80>;
	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 315>;
	dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
	<&dmac1 0xd1>, <&dmac1 0xd2>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 315>;
	reg-io-width = <4>;
	status = "disabled";
	max-frequency = <97500000>;
	};

	sata0: sata@ee300000 {
	compatible = "renesas,sata-r8a7791",
	"renesas,rcar-gen2-sata";
	reg = <0 0xee300000 0 0x200000>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 815>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 815>;
	status = "disabled";
	};

	sata1: sata@ee500000 {
	compatible = "renesas,sata-r8a7791",
	"renesas,rcar-gen2-sata";
	reg = <0 0xee500000 0 0x200000>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 814>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 814>;
	status = "disabled";
	};

	ether: ethernet@ee700000 {
	compatible = "renesas,ether-r8a7791",
	"renesas,rcar-gen2-ether";
	reg = <0 0xee700000 0 0x400>;
	interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 813>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 813>;
	phy-mode = "rmii";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	gic: interrupt-controller@f1001000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
	<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	pciec: pcie@fe000000 {
	compatible = "renesas,pcie-r8a7791",
	"renesas,pcie-rcar-gen2";
	reg = <0 0xfe000000 0 0x80000>;
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x00 0xff>;
	device_type = "pci";
	ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
	<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
	<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
	<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
	/* Map all possible DDR as inbound ranges */
	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
	<0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
	clock-names = "pcie", "pcie_bus";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 319>;
	status = "disabled";
	};

	vsp@fe928000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe928000 0 0x8000>;
	interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 131>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 131>;
	};

	vsp@fe930000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe930000 0 0x8000>;
	interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 128>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 128>;
	};

	vsp@fe938000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe938000 0 0x8000>;
	interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 127>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 127>;
	};

	fdp1@fe940000 {
	compatible = "renesas,fdp1";
	reg = <0 0xfe940000 0 0x2400>;
	interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 119>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 119>;
	};

	fdp1@fe944000 {
	compatible = "renesas,fdp1";
	reg = <0 0xfe944000 0 0x2400>;
	interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 118>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 118>;
	};

	jpu: jpeg-codec@fe980000 {
	compatible = "renesas,jpu-r8a7791",
	"renesas,rcar-gen2-jpu";
	reg = <0 0xfe980000 0 0x10300>;
	interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 106>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 106>;
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a7791";
	reg = <0 0xfeb00000 0 0x40000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&cpg CPG_MOD 724>,
	- <&cpg CPG_MOD 723>;
	+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
	clock-names = "du.0", "du.1";
	+ resets = <&cpg 724>;
	+ reset-names = "du.0";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb: endpoint {
	};
	};
	port@1 {
	reg = <1>;
	du_out_lvds0: endpoint {
	remote-endpoint = <&lvds0_in>;
	};
	};
	};
	};

	lvds0: lvds@feb90000 {
	compatible = "renesas,r8a7791-lvds";
	reg = <0 0xfeb90000 0 0x1c>;
	clocks = <&cpg CPG_MOD 726>;
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 726>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds0_in: endpoint {
	remote-endpoint = <&du_out_lvds0>;
	};
	};
	port@1 {
	reg = <1>;
	lvds0_out: endpoint {
	};
	};
	};
	};

	prr: chipid@ff000044 {
	compatible = "renesas,prr";
	reg = <0 0xff000044 0 4>;
	};

	cmt0: timer@ffca0000 {
	compatible = "renesas,r8a7791-cmt0",
	"renesas,rcar-gen2-cmt0";
	reg = <0 0xffca0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 124>;
	clock-names = "fck";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 124>;

	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a7791-cmt1",
	"renesas,rcar-gen2-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 329>;
	clock-names = "fck";
	power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
	resets = <&cpg 329>;

	status = "disabled";
	};
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	polling-delay-passive = <0>;
	polling-delay = <0>;

	thermal-sensors = <&thermal>;

	trips {
	cpu-crit {
	temperature = <95000>;
	hysteresis = <0>;
	type = "critical";
	};
	};
	cooling-maps {
	};
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clock - can be overridden by the board */
	usb_extal_clk: usb_extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <48000000>;
	};
	};
	diff --git a/sys/gnu/dts/arm/r8a7792-blanche.dts b/sys/gnu/dts/arm/r8a7792-blanche.dts
	index 248eb717eb35..9368ac2cf508 100644
	--- a/sys/gnu/dts/arm/r8a7792-blanche.dts
	+++ b/sys/gnu/dts/arm/r8a7792-blanche.dts
	@@ -1,358 +1,356 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the Blanche board
	*
	* Copyright (C) 2014 Renesas Electronics Corporation
	* Copyright (C) 2016 Cogent Embedded, Inc.
	*/

	/dts-v1/;
	#include "r8a7792.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>

	/ {
	model = "Blanche";
	compatible = "renesas,blanche", "renesas,r8a7792";

	aliases {
	serial0 = &scif0;
	serial1 = &scif3;
	};

	chosen {
	bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
	stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
	device_type = "memory";
	reg = <0 0x40000000 0 0x40000000>;
	};

	d3_3v: regulator-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "D3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ethernet@18000000 {
	compatible = "smsc,lan89218", "smsc,lan9115";
	reg = <0 0x18000000 0 0x100>;
	phy-mode = "mii";
	interrupt-parent = <&irqc>;
	interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
	smsc,irq-push-pull;
	reg-io-width = <4>;
	vddvario-supply = <&d3_3v>;
	vdd33a-supply = <&d3_3v>;

	pinctrl-0 = <&lan89218_pins>;
	pinctrl-names = "default";
	};

	vga-encoder {
	compatible = "adi,adv7123";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7123_in: endpoint {
	remote-endpoint = <&du_out_rgb1>;
	};
	};
	port@1 {
	reg = <1>;
	adv7123_out: endpoint {
	remote-endpoint = <&vga_in>;
	};
	};
	};
	};

	hdmi-out {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con: endpoint {
	remote-endpoint = <&adv7511_out>;
	};
	};
	};

	vga {
	compatible = "vga-connector";

	port {
	vga_in: endpoint {
	remote-endpoint = <&adv7123_out>;
	};
	};
	};

	x1_clk: x1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <74250000>;
	};

	x2_clk: x2 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <65000000>;
	};

	keyboard {
	compatible = "gpio-keys";

	key-1 {
	linux,code = <KEY_1>;
	label = "SW2-1";
	wakeup-source;
	debounce-interval = <20>;
	gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
	};
	key-2 {
	linux,code = <KEY_2>;
	label = "SW2-2";
	wakeup-source;
	debounce-interval = <20>;
	gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
	};
	key-3 {
	linux,code = <KEY_3>;
	label = "SW2-3";
	wakeup-source;
	debounce-interval = <20>;
	gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
	};
	key-4 {
	linux,code = <KEY_4>;
	label = "SW2-4";
	wakeup-source;
	debounce-interval = <20>;
	gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
	};
	key-a {
	linux,code = <KEY_A>;
	label = "SW24";
	wakeup-source;
	debounce-interval = <20>;
	gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
	};
	key-b {
	linux,code = <KEY_B>;
	label = "SW25";
	wakeup-source;
	debounce-interval = <20>;
	gpios = <&gpio11 2 GPIO_ACTIVE_LOW>;
	};
	};

	leds {
	compatible = "gpio-leds";

	led17 {
	gpios = <&gpio10 10 GPIO_ACTIVE_HIGH>;
	};
	led18 {
	gpios = <&gpio10 11 GPIO_ACTIVE_HIGH>;
	};
	led19 {
	gpios = <&gpio10 12 GPIO_ACTIVE_HIGH>;
	};
	led20 {
	gpios = <&gpio10 23 GPIO_ACTIVE_HIGH>;
	};
	};

	vcc_sdhi0: regulator-vcc-sdhi0 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI0 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};
	};

	&extal_clk {
	clock-frequency = <20000000>;
	};

	&can_clk {
	clock-frequency = <48000000>;
	};

	&pfc {
	scif0_pins: scif0 {
	groups = "scif0_data";
	function = "scif0";
	};

	scif3_pins: scif3 {
	groups = "scif3_data";
	function = "scif3";
	};

	lan89218_pins: lan89218 {
	intc {
	groups = "intc_irq0";
	function = "intc";
	};
	lbsc {
	groups = "lbsc_ex_cs0";
	function = "lbsc";
	};
	};

	can0_pins: can0 {
	groups = "can0_data", "can_clk";
	function = "can0";
	};

	sdhi0_pins: sdhi0 {
	groups = "sdhi0_data4", "sdhi0_ctrl";
	function = "sdhi0";
	};

	du0_pins: du0 {
	groups = "du0_rgb888", "du0_sync", "du0_disp";
	function = "du0";
	};

	du1_pins: du1 {
	groups = "du1_rgb666", "du1_sync", "du1_disp";
	function = "du1";
	};

	pmic_irq_pins: pmicirq {
	groups = "intc_irq2";
	function = "intc";
	};
	};

	&rwdt {
	timeout-sec = <60>;
	status = "okay";
	};

	&scif0 {
	pinctrl-0 = <&scif0_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&scif3 {
	pinctrl-0 = <&scif3_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&can0 {
	pinctrl-0 = <&can0_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&vcc_sdhi0>;
	cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

	hdmi@39 {
	compatible = "adi,adv7511w";
	reg = <0x39>;
	interrupt-parent = <&irqc>;
	interrupts = <3 IRQ_TYPE_EDGE_FALLING>;

	adi,input-depth = <8>;
	adi,input-colorspace = "rgb";
	adi,input-clock = "1x";
	- adi,input-style = <1>;
	- adi,input-justification = "evenly";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7511_in: endpoint {
	remote-endpoint = <&du_out_rgb0>;
	};
	};

	port@1 {
	reg = <1>;
	adv7511_out: endpoint {
	remote-endpoint = <&hdmi_con>;
	};
	};
	};
	};
	};

	&iic3 {
	status = "okay";

	pmic@58 {
	compatible = "dlg,da9063";
	reg = <0x58>;
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_irq_pins>;
	interrupt-parent = <&irqc>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;

	rtc {
	compatible = "dlg,da9063-rtc";
	};

	wdt {
	compatible = "dlg,da9063-watchdog";
	};
	};
	};

	&du {
	pinctrl-0 = <&du0_pins &du1_pins>;
	pinctrl-names = "default";

	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>;
	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
	status = "okay";

	ports {
	port@0 {
	endpoint {
	remote-endpoint = <&adv7511_in>;
	};
	};
	port@1 {
	endpoint {
	remote-endpoint = <&adv7123_in>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/r8a7792-wheat.dts b/sys/gnu/dts/arm/r8a7792-wheat.dts
	index bd2a63bdab3d..ba2d2a589012 100644
	--- a/sys/gnu/dts/arm/r8a7792-wheat.dts
	+++ b/sys/gnu/dts/arm/r8a7792-wheat.dts
	@@ -1,333 +1,329 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the Wheat board
	*
	* Copyright (C) 2016 Renesas Electronics Corporation
	* Copyright (C) 2016 Cogent Embedded, Inc.
	*/

	/dts-v1/;
	#include "r8a7792.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>

	/ {
	model = "Wheat";
	compatible = "renesas,wheat", "renesas,r8a7792";

	aliases {
	serial0 = &scif0;
	};

	chosen {
	bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
	stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
	device_type = "memory";
	reg = <0 0x40000000 0 0x40000000>;
	};

	d3_3v: regulator-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "D3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ethernet@18000000 {
	compatible = "smsc,lan89218", "smsc,lan9115";
	reg = <0 0x18000000 0 0x100>;
	phy-mode = "mii";
	interrupt-parent = <&irqc>;
	interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
	smsc,irq-push-pull;
	smsc,save-mac-address;
	reg-io-width = <4>;
	vddvario-supply = <&d3_3v>;
	vdd33a-supply = <&d3_3v>;

	pinctrl-0 = <&lan89218_pins>;
	pinctrl-names = "default";
	};

	keyboard {
	compatible = "gpio-keys";

	key-a {
	linux,code = <KEY_A>;
	label = "SW2";
	wakeup-source;
	debounce-interval = <20>;
	gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
	};
	key-b {
	linux,code = <KEY_B>;
	label = "SW3";
	wakeup-source;
	debounce-interval = <20>;
	gpios = <&gpio11 2 GPIO_ACTIVE_LOW>;
	};
	};

	vcc_sdhi0: regulator-vcc-sdhi0 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI0 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	hdmi-out0 {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con0: endpoint {
	remote-endpoint = <&adv7513_0_out>;
	};
	};
	};

	hdmi-out1 {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con1: endpoint {
	remote-endpoint = <&adv7513_1_out>;
	};
	};
	};

	osc2_clk: osc2 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <74250000>;
	};
	};

	&extal_clk {
	clock-frequency = <20000000>;
	};

	&pfc {
	scif0_pins: scif0 {
	groups = "scif0_data";
	function = "scif0";
	};

	lan89218_pins: lan89218 {
	intc {
	groups = "intc_irq0";
	function = "intc";
	};
	lbsc {
	groups = "lbsc_ex_cs0";
	function = "lbsc";
	};
	};

	can0_pins: can0 {
	groups = "can0_data";
	function = "can0";
	};

	can1_pins: can1 {
	groups = "can1_data";
	function = "can1";
	};

	sdhi0_pins: sdhi0 {
	groups = "sdhi0_data4", "sdhi0_ctrl";
	function = "sdhi0";
	};

	qspi_pins: qspi {
	groups = "qspi_ctrl", "qspi_data4";
	function = "qspi";
	};

	du0_pins: du0 {
	groups = "du0_rgb888", "du0_sync", "du0_disp";
	function = "du0";
	};

	du1_pins: du1 {
	groups = "du1_rgb666", "du1_sync", "du1_disp";
	function = "du1";
	};
	};

	&rwdt {
	timeout-sec = <60>;
	status = "okay";
	};

	&scif0 {
	pinctrl-0 = <&scif0_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&can0 {
	pinctrl-0 = <&can0_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&can1 {
	pinctrl-0 = <&can1_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&vcc_sdhi0>;
	cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&qspi {
	pinctrl-0 = <&qspi_pins>;
	pinctrl-names = "default";
	status = "okay";

	flash@0 {
	compatible = "spansion,s25fl512s", "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <30000000>;
	spi-tx-bus-width = <4>;
	spi-rx-bus-width = <4>;
	spi-cpol;
	spi-cpha;
	m25p,fast-read;

	partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
	label = "loader";
	reg = <0x00000000 0x00040000>;
	read-only;
	};
	partition@40000 {
	label = "user";
	reg = <0x00040000 0x00400000>;
	read-only;
	};
	partition@440000 {
	label = "flash";
	reg = <0x00440000 0x03bc0000>;
	};
	};
	};
	};

	&i2c4 {
	status = "okay";
	clock-frequency = <400000>;

	/*
	* The adv75xx resets its addresses to defaults during low power mode.
	* Because we have two ADV7513 devices on the same bus, we must change
	* both of them away from the defaults so that they do not conflict.
	*/
	hdmi@3d {
	compatible = "adi,adv7513";
	- reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>;
	- reg-names = "main", "cec", "edid", "packet";
	+ reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>;
	+ reg-names = "main", "edid", "cec", "packet";

	adi,input-depth = <8>;
	adi,input-colorspace = "rgb";
	adi,input-clock = "1x";
	- adi,input-style = <1>;
	- adi,input-justification = "evenly";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7513_0_in: endpoint {
	remote-endpoint = <&du_out_rgb0>;
	};
	};

	port@1 {
	reg = <1>;
	adv7513_0_out: endpoint {
	remote-endpoint = <&hdmi_con0>;
	};
	};
	};
	};

	hdmi@39 {
	compatible = "adi,adv7513";
	- reg = <0x39>, <0x29>, <0x49>, <0x59>;
	- reg-names = "main", "cec", "edid", "packet";
	+ reg = <0x39>, <0x49>, <0x29>, <0x59>;
	+ reg-names = "main", "edid", "cec", "packet";

	adi,input-depth = <8>;
	adi,input-colorspace = "rgb";
	adi,input-clock = "1x";
	- adi,input-style = <1>;
	- adi,input-justification = "evenly";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7513_1_in: endpoint {
	remote-endpoint = <&du_out_rgb1>;
	};
	};

	port@1 {
	reg = <1>;
	adv7513_1_out: endpoint {
	remote-endpoint = <&hdmi_con1>;
	};
	};
	};
	};
	};

	&du {
	pinctrl-0 = <&du0_pins &du1_pins>;
	pinctrl-names = "default";

	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&osc2_clk>;
	clock-names = "du.0", "du.1", "dclkin.0";
	status = "okay";

	ports {
	port@0 {
	endpoint {
	remote-endpoint = <&adv7513_0_in>;
	};
	};
	port@1 {
	endpoint {
	remote-endpoint = <&adv7513_1_in>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/r8a7792.dtsi b/sys/gnu/dts/arm/r8a7792.dtsi
	index 39af16caa2ae..4627eefa502b 100644
	--- a/sys/gnu/dts/arm/r8a7792.dtsi
	+++ b/sys/gnu/dts/arm/r8a7792.dtsi
	@@ -1,924 +1,925 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the R-Car V2H (R8A77920) SoC
	*
	* Copyright (C) 2016 Cogent Embedded Inc.
	*/

	#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/power/r8a7792-sysc.h>

	/ {
	compatible = "renesas,r8a7792";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	i2c6 = &iic3;
	spi0 = &qspi;
	spi1 = &msiof0;
	spi2 = &msiof1;
	vin0 = &vin0;
	vin1 = &vin1;
	vin2 = &vin2;
	vin3 = &vin3;
	vin4 = &vin4;
	vin5 = &vin5;
	};

	/* External CAN clock */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "renesas,apmu";

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0>;
	clock-frequency = <1000000000>;
	clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
	power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
	next-level-cache = <&L2_CA15>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <1>;
	clock-frequency = <1000000000>;
	clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
	power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
	next-level-cache = <&L2_CA15>;
	};

	L2_CA15: cache-controller-0 {
	compatible = "cache";
	cache-unified;
	cache-level = <2>;
	power-domains = <&sysc R8A7792_PD_CA15_SCU>;
	};
	};

	/* External root clock */
	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	pmu {
	compatible = "arm,cortex-a15-pmu";
	interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	/* External SCIF clock */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;

	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a7792-wdt",
	"renesas,rcar-gen2-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a7792",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 29>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a7792",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 23>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a7792",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a7792",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 28>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a7792",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 17>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a7792",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 17>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	gpio6: gpio@e6055100 {
	compatible = "renesas,gpio-r8a7792",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055100 0 0x50>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 192 17>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 905>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 905>;
	};

	gpio7: gpio@e6055200 {
	compatible = "renesas,gpio-r8a7792",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055200 0 0x50>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 224 17>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 904>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 904>;
	};

	gpio8: gpio@e6055300 {
	compatible = "renesas,gpio-r8a7792",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055300 0 0x50>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 256 17>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 921>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 921>;
	};

	gpio9: gpio@e6055400 {
	compatible = "renesas,gpio-r8a7792",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055400 0 0x50>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 288 17>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 919>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 919>;
	};

	gpio10: gpio@e6055500 {
	compatible = "renesas,gpio-r8a7792",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055500 0 0x50>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 320 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 914>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 914>;
	};

	gpio11: gpio@e6055600 {
	compatible = "renesas,gpio-r8a7792",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055600 0 0x50>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 352 30>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 913>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 913>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a7792";
	reg = <0 0xe6060000 0 0x144>;
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a7792-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>;
	clock-names = "extal";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	apmu@e6152000 {
	compatible = "renesas,r8a7792-apmu", "renesas,apmu";
	reg = <0 0xe6152000 0 0x188>;
	cpus = <&cpu0 &cpu1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a7792-rst";
	reg = <0 0xe6160000 0 0x0100>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a7792-sysc";
	reg = <0 0xe6180000 0 0x0200>;
	#power-domain-cells = <1>;
	};

	irqc: interrupt-controller@e61c0000 {
	compatible = "renesas,irqc-r8a7792", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	icram0: sram@e63a0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63a0000 0 0x12000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63a0000 0x12000>;
	};

	icram1: sram@e63c0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63c0000 0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63c0000 0x1000>;

	smp-sram@0 {
	compatible = "renesas,smp-sram";
	reg = <0 0x100>;
	};
	};

	/* I2C doesn't need pinmux */
	i2c0: i2c@e6508000 {
	compatible = "renesas,i2c-r8a7792",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	i2c-scl-internal-delay-ns = <6>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c1: i2c@e6518000 {
	compatible = "renesas,i2c-r8a7792",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6518000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	i2c-scl-internal-delay-ns = <6>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c2: i2c@e6530000 {
	compatible = "renesas,i2c-r8a7792",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6530000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	i2c-scl-internal-delay-ns = <6>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c3: i2c@e6540000 {
	compatible = "renesas,i2c-r8a7792",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6540000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	i2c-scl-internal-delay-ns = <6>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c4: i2c@e6520000 {
	compatible = "renesas,i2c-r8a7792",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6520000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	i2c-scl-internal-delay-ns = <6>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c5: i2c@e6528000 {
	compatible = "renesas,i2c-r8a7792",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6528000 0 0x40>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 925>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 925>;
	i2c-scl-internal-delay-ns = <110>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	iic3: i2c@e60b0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7792",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe60b0000 0 0x425>;
	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 926>;
	dmas = <&dmac0 0x77>, <&dmac0 0x78>,
	<&dmac1 0x77>, <&dmac1 0x78>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 926>;
	status = "disabled";
	};

	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a7792",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x20000>;
	interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	dmac1: dma-controller@e6720000 {
	compatible = "renesas,dmac-r8a7792",
	"renesas,rcar-dmac";
	reg = <0 0xe6720000 0 0x20000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a7792",
	"renesas,etheravb-rcar-gen2";
	reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
	interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	qspi: spi@e6b10000 {
	compatible = "renesas,qspi-r8a7792", "renesas,qspi";
	reg = <0 0xe6b10000 0 0x2c>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 917>;
	dmas = <&dmac0 0x17>, <&dmac0 0x18>,
	<&dmac1 0x17>, <&dmac1 0x18>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 917>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a7792",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e60000 0 64>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 721>,
	<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
	<&dmac1 0x29>, <&dmac1 0x2a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 721>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a7792",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e68000 0 64>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 720>,
	<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
	<&dmac1 0x2d>, <&dmac1 0x2e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 720>;
	status = "disabled";
	};

	scif2: serial@e6e58000 {
	compatible = "renesas,scif-r8a7792",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e58000 0 64>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 719>,
	<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
	<&dmac1 0x2b>, <&dmac1 0x2c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 719>;
	status = "disabled";
	};

	scif3: serial@e6ea8000 {
	compatible = "renesas,scif-r8a7792",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ea8000 0 64>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 718>,
	<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
	<&dmac1 0x2f>, <&dmac1 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 718>;
	status = "disabled";
	};

	hscif0: serial@e62c0000 {
	compatible = "renesas,hscif-r8a7792",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c0000 0 96>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 717>,
	<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
	<&dmac1 0x39>, <&dmac1 0x3a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 717>;
	status = "disabled";
	};

	hscif1: serial@e62c8000 {
	compatible = "renesas,hscif-r8a7792",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c8000 0 96>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>,
	<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
	<&dmac1 0x4d>, <&dmac1 0x4e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";
	};

	msiof0: spi@e6e20000 {
	compatible = "renesas,msiof-r8a7792",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6e20000 0 0x0064>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 000>;
	dmas = <&dmac0 0x51>, <&dmac0 0x52>,
	<&dmac1 0x51>, <&dmac1 0x52>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 000>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof1: spi@e6e10000 {
	compatible = "renesas,msiof-r8a7792",
	"renesas,rcar-gen2-msiof";
	reg = <0 0xe6e10000 0 0x0064>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 208>;
	dmas = <&dmac0 0x55>, <&dmac0 0x56>,
	<&dmac1 0x55>, <&dmac1 0x56>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 208>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	can0: can@e6e80000 {
	compatible = "renesas,can-r8a7792",
	"renesas,rcar-gen2-can";
	reg = <0 0xe6e80000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 916>,
	<&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 916>;
	status = "disabled";
	};

	can1: can@e6e88000 {
	compatible = "renesas,can-r8a7792",
	"renesas,rcar-gen2-can";
	reg = <0 0xe6e88000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 915>,
	<&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 915>;
	status = "disabled";
	};

	vin0: video@e6ef0000 {
	compatible = "renesas,vin-r8a7792",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef0000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 811>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 811>;
	status = "disabled";
	};

	vin1: video@e6ef1000 {
	compatible = "renesas,vin-r8a7792",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef1000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 810>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 810>;
	status = "disabled";
	};

	vin2: video@e6ef2000 {
	compatible = "renesas,vin-r8a7792",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef2000 0 0x1000>;
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 809>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 809>;
	status = "disabled";
	};

	vin3: video@e6ef3000 {
	compatible = "renesas,vin-r8a7792",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef3000 0 0x1000>;
	interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 808>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 808>;
	status = "disabled";
	};

	vin4: video@e6ef4000 {
	compatible = "renesas,vin-r8a7792",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef4000 0 0x1000>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 805>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 805>;
	status = "disabled";
	};

	vin5: video@e6ef5000 {
	compatible = "renesas,vin-r8a7792",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef5000 0 0x1000>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 804>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 804>;
	status = "disabled";
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a7792",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee100000 0 0x328>;
	interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
	<&dmac1 0xcd>, <&dmac1 0xce>;
	dma-names = "tx", "rx", "tx", "rx";
	clocks = <&cpg CPG_MOD 314>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	status = "disabled";
	};

	gic: interrupt-controller@f1001000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0 0xf1001000 0 0x1000>,
	<0 0xf1002000 0 0x2000>,
	<0 0xf1004000 0 0x2000>,
	<0 0xf1006000 0 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	vsp@fe928000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe928000 0 0x8000>;
	interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 131>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 131>;
	};

	vsp@fe930000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe930000 0 0x8000>;
	interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 128>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 128>;
	};

	vsp@fe938000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe938000 0 0x8000>;
	interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 127>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 127>;
	};

	jpu: jpeg-codec@fe980000 {
	compatible = "renesas,jpu-r8a7792",
	"renesas,rcar-gen2-jpu";
	reg = <0 0xfe980000 0 0x10300>;
	interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 106>;
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 106>;
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a7792";
	reg = <0 0xfeb00000 0 0x40000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&cpg CPG_MOD 724>,
	- <&cpg CPG_MOD 723>;
	+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
	clock-names = "du.0", "du.1";
	+ resets = <&cpg 724>;
	+ reset-names = "du.0";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb0: endpoint {
	};
	};
	port@1 {
	reg = <1>;
	du_out_rgb1: endpoint {
	};
	};
	};
	};

	prr: chipid@ff000044 {
	compatible = "renesas,prr";
	reg = <0 0xff000044 0 4>;
	};

	cmt0: timer@ffca0000 {
	compatible = "renesas,r8a7792-cmt0",
	"renesas,rcar-gen2-cmt0";
	reg = <0 0xffca0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 124>;
	clock-names = "fck";
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 124>;

	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a7792-cmt1",
	"renesas,rcar-gen2-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 329>;
	clock-names = "fck";
	power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
	resets = <&cpg 329>;

	status = "disabled";
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	};
	};
	diff --git a/sys/gnu/dts/arm/r8a7793-gose.dts b/sys/gnu/dts/arm/r8a7793-gose.dts
	index 22ca7cd1e7d2..79baf06019f5 100644
	--- a/sys/gnu/dts/arm/r8a7793-gose.dts
	+++ b/sys/gnu/dts/arm/r8a7793-gose.dts
	@@ -1,807 +1,806 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the Gose board
	*
	* Copyright (C) 2014-2015 Renesas Electronics Corporation
	*/

	/*
	* SSI-AK4643
	*
	* SW1: 1: AK4643
	* 2: CN22
	* 3: ADV7511
	*
	* This command is required when Playback/Capture
	*
	* amixer set "LINEOUT Mixer DACL" on
	* amixer set "DVC Out" 100%
	* amixer set "DVC In" 100%
	*
	* You can use Mute
	*
	* amixer set "DVC Out Mute" on
	* amixer set "DVC In Mute" on
	*
	* You can use Volume Ramp
	*
	* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
	* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
	* amixer set "DVC Out Ramp" on
	* aplay xxx.wav &
	* amixer set "DVC Out" 80% // Volume Down
	* amixer set "DVC Out" 100% // Volume Up
	*/

	/dts-v1/;
	#include "r8a7793.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>

	/ {
	model = "Gose";
	compatible = "renesas,gose", "renesas,r8a7793";

	aliases {
	serial0 = &scif0;
	serial1 = &scif1;
	i2c9 = &gpioi2c2;
	i2c10 = &gpioi2c4;
	i2c11 = &i2chdmi;
	i2c12 = &i2cexio4;
	};

	chosen {
	bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
	stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
	device_type = "memory";
	reg = <0 0x40000000 0 0x40000000>;
	};

	gpio-keys {
	compatible = "gpio-keys";

	key-1 {
	gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_1>;
	label = "SW2-1";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-2 {
	gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_2>;
	label = "SW2-2";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-3 {
	gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_3>;
	label = "SW2-3";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-4 {
	gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_4>;
	label = "SW2-4";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-a {
	gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_A>;
	label = "SW30";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-b {
	gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_B>;
	label = "SW31";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-c {
	gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_C>;
	label = "SW32";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-d {
	gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_D>;
	label = "SW33";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-e {
	gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_E>;
	label = "SW34";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-f {
	gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_F>;
	label = "SW35";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-g {
	gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_G>;
	label = "SW36";
	wakeup-source;
	debounce-interval = <20>;
	};
	};

	leds {
	compatible = "gpio-leds";
	led6 {
	gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
	label = "LED6";
	};
	led7 {
	gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
	label = "LED7";
	};
	led8 {
	gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
	label = "LED8";
	};
	};

	vcc_sdhi0: regulator-vcc-sdhi0 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI0 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vccq_sdhi0: regulator-vccq-sdhi0 {
	compatible = "regulator-gpio";

	regulator-name = "SDHI0 VccQ";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
	gpios-states = <1>;
	states = <3300000 1>, <1800000 0>;
	};

	vcc_sdhi1: regulator-vcc-sdhi1 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI1 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vccq_sdhi1: regulator-vccq-sdhi1 {
	compatible = "regulator-gpio";

	regulator-name = "SDHI1 VccQ";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
	gpios-states = <1>;
	states = <3300000 1>, <1800000 0>;
	};

	vcc_sdhi2: regulator-vcc-sdhi2 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI2 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vccq_sdhi2: regulator-vccq-sdhi2 {
	compatible = "regulator-gpio";

	regulator-name = "SDHI2 VccQ";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
	gpios-states = <1>;
	states = <3300000 1>, <1800000 0>;
	};

	audio_clock: audio_clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <11289600>;
	};

	rsnd_ak4643: sound {
	compatible = "simple-audio-card";

	simple-audio-card,format = "left_j";
	simple-audio-card,bitclock-master = <&sndcodec>;
	simple-audio-card,frame-master = <&sndcodec>;

	sndcpu: simple-audio-card,cpu {
	sound-dai = <&rcar_sound>;
	};

	sndcodec: simple-audio-card,codec {
	sound-dai = <&ak4643>;
	clocks = <&audio_clock>;
	};
	};

	hdmi-in {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con_in: endpoint {
	remote-endpoint = <&adv7612_in>;
	};
	};
	};

	hdmi-out {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con_out: endpoint {
	remote-endpoint = <&adv7511_out>;
	};
	};
	};

	composite-in {
	compatible = "composite-video-connector";

	port {
	composite_con_in: endpoint {
	remote-endpoint = <&adv7180_in>;
	};
	};
	};

	x2_clk: x2-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <74250000>;
	};

	x13_clk: x13-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <148500000>;
	};

	gpioi2c2: i2c-9 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "i2c-gpio";
	status = "disabled";
	scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	i2c-gpio,delay-us = <5>;
	};

	gpioi2c4: i2c-10 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "i2c-gpio";
	status = "disabled";
	scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	i2c-gpio,delay-us = <5>;
	};

	/*
	* A fallback to GPIO is provided for I2C2.
	*/
	i2chdmi: i2c-11 {
	compatible = "i2c-demux-pinctrl";
	i2c-parent = <&i2c2>, <&gpioi2c2>;
	i2c-bus-name = "i2c-hdmi";
	#address-cells = <1>;
	#size-cells = <0>;

	ak4643: codec@12 {
	compatible = "asahi-kasei,ak4643";
	#sound-dai-cells = <0>;
	reg = <0x12>;
	};

	composite-in@20 {
	compatible = "adi,adv7180cp";
	reg = <0x20>;
	remote = <&vin1>;

	port {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7180_in: endpoint {
	remote-endpoint = <&composite_con_in>;
	};
	};

	port@3 {
	reg = <3>;
	adv7180_out: endpoint {
	bus-width = <8>;
	remote-endpoint = <&vin1ep>;
	};
	};
	};
	};

	hdmi@39 {
	compatible = "adi,adv7511w";
	reg = <0x39>;
	interrupt-parent = <&gpio3>;
	interrupts = <29 IRQ_TYPE_LEVEL_LOW>;

	adi,input-depth = <8>;
	adi,input-colorspace = "rgb";
	adi,input-clock = "1x";
	- adi,input-style = <1>;
	- adi,input-justification = "evenly";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7511_in: endpoint {
	remote-endpoint = <&du_out_rgb>;
	};
	};

	port@1 {
	reg = <1>;
	adv7511_out: endpoint {
	remote-endpoint = <&hdmi_con_out>;
	};
	};
	};
	};

	hdmi-in@4c {
	compatible = "adi,adv7612";
	reg = <0x4c>;
	interrupt-parent = <&gpio4>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
	default-input = <0>;

	port {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7612_in: endpoint {
	remote-endpoint = <&hdmi_con_in>;
	};
	};

	port@2 {
	reg = <2>;
	adv7612_out: endpoint {
	remote-endpoint = <&vin0ep2>;
	};
	};
	};
	};

	eeprom@50 {
	compatible = "renesas,r1ex24002", "atmel,24c02";
	reg = <0x50>;
	pagesize = <16>;
	};
	};

	/*
	* I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA).
	* A fallback to GPIO is provided.
	*/
	i2cexio4: i2c-12 {
	compatible = "i2c-demux-pinctrl";
	i2c-parent = <&i2c4>, <&gpioi2c4>;
	i2c-bus-name = "i2c-exio4";
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";
	status = "okay";

	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
	<&x13_clk>, <&x2_clk>;
	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";

	ports {
	port@0 {
	endpoint {
	remote-endpoint = <&adv7511_in>;
	};
	};
	};
	};

	&lvds0 {
	ports {
	port@1 {
	lvds_connector: endpoint {
	};
	};
	};
	};

	&extal_clk {
	clock-frequency = <20000000>;
	};

	&pfc {
	pinctrl-0 = <&scif_clk_pins>;
	pinctrl-names = "default";

	i2c2_pins: i2c2 {
	groups = "i2c2";
	function = "i2c2";
	};

	i2c4_pins: i2c4 {
	groups = "i2c4_c";
	function = "i2c4";
	};

	du_pins: du {
	groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
	function = "du";
	};

	scif0_pins: scif0 {
	groups = "scif0_data_d";
	function = "scif0";
	};

	scif1_pins: scif1 {
	groups = "scif1_data_d";
	function = "scif1";
	};

	scif_clk_pins: scif_clk {
	groups = "scif_clk";
	function = "scif_clk";
	};

	ether_pins: ether {
	groups = "eth_link", "eth_mdio", "eth_rmii";
	function = "eth";
	};

	phy1_pins: phy1 {
	groups = "intc_irq0";
	function = "intc";
	};

	pmic_irq_pins: pmicirq {
	groups = "intc_irq2";
	function = "intc";
	};

	sdhi0_pins: sd0 {
	groups = "sdhi0_data4", "sdhi0_ctrl";
	function = "sdhi0";
	power-source = <3300>;
	};

	sdhi0_pins_uhs: sd0_uhs {
	groups = "sdhi0_data4", "sdhi0_ctrl";
	function = "sdhi0";
	power-source = <1800>;
	};

	sdhi1_pins: sd1 {
	groups = "sdhi1_data4", "sdhi1_ctrl";
	function = "sdhi1";
	power-source = <3300>;
	};

	sdhi1_pins_uhs: sd1_uhs {
	groups = "sdhi1_data4", "sdhi1_ctrl";
	function = "sdhi1";
	power-source = <1800>;
	};

	sdhi2_pins: sd2 {
	groups = "sdhi2_data4", "sdhi2_ctrl";
	function = "sdhi2";
	power-source = <3300>;
	};

	sdhi2_pins_uhs: sd2_uhs {
	groups = "sdhi2_data4", "sdhi2_ctrl";
	function = "sdhi2";
	power-source = <1800>;
	};

	qspi_pins: qspi {
	groups = "qspi_ctrl", "qspi_data4";
	function = "qspi";
	};

	sound_pins: sound {
	groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
	function = "ssi";
	};

	sound_clk_pins: sound_clk {
	groups = "audio_clk_a";
	function = "audio_clk";
	};

	vin0_pins: vin0 {
	groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
	function = "vin0";
	};

	vin1_pins: vin1 {
	groups = "vin1_data8", "vin1_clk";
	function = "vin1";
	};
	};

	&ether {
	pinctrl-0 = <&ether_pins &phy1_pins>;
	pinctrl-names = "default";

	phy-handle = <&phy1>;
	renesas,ether-link-active-low;
	status = "okay";

	phy1: ethernet-phy@1 {
	reg = <1>;
	interrupt-parent = <&irqc0>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	micrel,led-mode = <1>;
	+ reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
	};
	};

	&cmt0 {
	status = "okay";
	};

	&cpu0 {
	cpu0-supply = <&vdd_dvfs>;
	};

	&rwdt {
	timeout-sec = <60>;
	status = "okay";
	};

	&scif0 {
	pinctrl-0 = <&scif0_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&scif1 {
	pinctrl-0 = <&scif1_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&scif_clk {
	clock-frequency = <14745600>;
	};

	&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-1 = <&sdhi0_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi0>;
	vqmmc-supply = <&vccq_sdhi0>;
	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
	};

	&sdhi1 {
	pinctrl-0 = <&sdhi1_pins>;
	pinctrl-1 = <&sdhi1_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi1>;
	vqmmc-supply = <&vccq_sdhi1>;
	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
	sd-uhs-sdr50;
	status = "okay";
	};

	&sdhi2 {
	pinctrl-0 = <&sdhi2_pins>;
	pinctrl-1 = <&sdhi2_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi2>;
	vqmmc-supply = <&vccq_sdhi2>;
	cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
	sd-uhs-sdr50;
	status = "okay";
	};

	&qspi {
	pinctrl-0 = <&qspi_pins>;
	pinctrl-names = "default";

	status = "okay";

	flash@0 {
	compatible = "spansion,s25fl512s", "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <30000000>;
	spi-tx-bus-width = <4>;
	spi-rx-bus-width = <4>;
	spi-cpol;
	spi-cpha;
	m25p,fast-read;

	partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
	label = "loader";
	reg = <0x00000000 0x00040000>;
	read-only;
	};
	partition@40000 {
	label = "user";
	reg = <0x00040000 0x00400000>;
	read-only;
	};
	partition@440000 {
	label = "flash";
	reg = <0x00440000 0x03bc0000>;
	};
	};
	};
	};

	&i2c2 {
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-names = "i2c-hdmi";

	status = "okay";
	clock-frequency = <100000>;

	};

	&i2c6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_irq_pins>;
	status = "okay";
	clock-frequency = <100000>;

	pmic@58 {
	compatible = "dlg,da9063";
	reg = <0x58>;
	interrupt-parent = <&irqc0>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;

	rtc {
	compatible = "dlg,da9063-rtc";
	};

	wdt {
	compatible = "dlg,da9063-watchdog";
	};
	};

	vdd_dvfs: regulator@68 {
	compatible = "dlg,da9210";
	reg = <0x68>;
	interrupt-parent = <&irqc0>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;

	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};

	&i2c4 {
	pinctrl-0 = <&i2c4_pins>;
	pinctrl-names = "i2c-exio4";
	};

	&rcar_sound {
	pinctrl-0 = <&sound_pins &sound_clk_pins>;
	pinctrl-names = "default";

	/* Single DAI */
	#sound-dai-cells = <0>;

	status = "okay";

	rcar_sound,dai {
	dai0 {
	playback = <&ssi0 &src2 &dvc0>;
	capture = <&ssi1 &src3 &dvc1>;
	};
	};
	};

	&ssi1 {
	shared-pin;
	};

	/* HDMI video input */
	&vin0 {
	status = "okay";
	pinctrl-0 = <&vin0_pins>;
	pinctrl-names = "default";

	port {
	vin0ep2: endpoint {
	remote-endpoint = <&adv7612_out>;
	bus-width = <24>;
	hsync-active = <0>;
	vsync-active = <0>;
	pclk-sample = <1>;
	data-active = <1>;
	};
	};
	};

	/* composite video input */
	&vin1 {
	pinctrl-0 = <&vin1_pins>;
	pinctrl-names = "default";

	status = "okay";

	port {
	vin1ep: endpoint {
	remote-endpoint = <&adv7180_out>;
	bus-width = <8>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/r8a7793.dtsi b/sys/gnu/dts/arm/r8a7793.dtsi
	index eef035c4d983..dadbda16161b 100644
	--- a/sys/gnu/dts/arm/r8a7793.dtsi
	+++ b/sys/gnu/dts/arm/r8a7793.dtsi
	@@ -1,1467 +1,1468 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the R-Car M2-N (R8A77930) SoC
	*
	* Copyright (C) 2014-2015 Renesas Electronics Corporation
	*/

	#include <dt-bindings/clock/r8a7793-cpg-mssr.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/power/r8a7793-sysc.h>

	/ {
	compatible = "renesas,r8a7793";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	i2c6 = &i2c6;
	i2c7 = &i2c7;
	i2c8 = &i2c8;
	spi0 = &qspi;
	};

	/*
	* The external audio clocks are configured as 0 Hz fixed frequency
	* clocks by default.
	* Boards that provide audio clocks should override them.
	*/
	audio_clk_a: audio_clk_a {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	audio_clk_b: audio_clk_b {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	audio_clk_c: audio_clk_c {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	/* External CAN clock */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "renesas,apmu";

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0>;
	clock-frequency = <1500000000>;
	clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
	power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
	voltage-tolerance = <1>; /* 1% */
	clock-latency = <300000>; /* 300 us */

	/* kHz - uV - OPPs unknown yet */
	operating-points = <1500000 1000000>,
	<1312500 1000000>,
	<1125000 1000000>,
	< 937500 1000000>,
	< 750000 1000000>,
	< 375000 1000000>;
	next-level-cache = <&L2_CA15>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <1>;
	clock-frequency = <1500000000>;
	clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
	power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
	voltage-tolerance = <1>; /* 1% */
	clock-latency = <300000>; /* 300 us */

	/* kHz - uV - OPPs unknown yet */
	operating-points = <1500000 1000000>,
	<1312500 1000000>,
	<1125000 1000000>,
	< 937500 1000000>,
	< 750000 1000000>,
	< 375000 1000000>;
	next-level-cache = <&L2_CA15>;
	};

	L2_CA15: cache-controller-0 {
	compatible = "cache";
	power-domains = <&sysc R8A7793_PD_CA15_SCU>;
	cache-unified;
	cache-level = <2>;
	};
	};

	/* External root clock */
	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	pmu {
	compatible = "arm,cortex-a15-pmu";
	interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	/* External SCIF clock */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;

	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a7793-wdt",
	"renesas,rcar-gen2-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a7793",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a7793",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a7793",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a7793",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a7793",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a7793",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	gpio6: gpio@e6055400 {
	compatible = "renesas,gpio-r8a7793",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055400 0 0x50>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 192 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 905>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 905>;
	};

	gpio7: gpio@e6055800 {
	compatible = "renesas,gpio-r8a7793",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055800 0 0x50>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 224 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 904>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 904>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a7793";
	reg = <0 0xe6060000 0 0x250>;
	};

	/* Special CPG clocks */
	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a7793-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>, <&usb_extal_clk>;
	clock-names = "extal", "usb_extal";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	apmu@e6152000 {
	compatible = "renesas,r8a7793-apmu", "renesas,apmu";
	reg = <0 0xe6152000 0 0x188>;
	cpus = <&cpu0 &cpu1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a7793-rst";
	reg = <0 0xe6160000 0 0x0100>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a7793-sysc";
	reg = <0 0xe6180000 0 0x0200>;
	#power-domain-cells = <1>;
	};

	irqc0: interrupt-controller@e61c0000 {
	compatible = "renesas,irqc-r8a7793", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	thermal: thermal@e61f0000 {
	compatible = "renesas,thermal-r8a7793",
	"renesas,rcar-gen2-thermal",
	"renesas,rcar-thermal";
	reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 522>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 522>;
	#thermal-sensor-cells = <0>;
	};

	ipmmu_sy0: mmu@e6280000 {
	compatible = "renesas,ipmmu-r8a7793",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6280000 0 0x1000>;
	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_sy1: mmu@e6290000 {
	compatible = "renesas,ipmmu-r8a7793",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6290000 0 0x1000>;
	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_ds: mmu@e6740000 {
	compatible = "renesas,ipmmu-r8a7793",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6740000 0 0x1000>;
	interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_mp: mmu@ec680000 {
	compatible = "renesas,ipmmu-r8a7793",
	"renesas,ipmmu-vmsa";
	reg = <0 0xec680000 0 0x1000>;
	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_mx: mmu@fe951000 {
	compatible = "renesas,ipmmu-r8a7793",
	"renesas,ipmmu-vmsa";
	reg = <0 0xfe951000 0 0x1000>;
	interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_rt: mmu@ffc80000 {
	compatible = "renesas,ipmmu-r8a7793",
	"renesas,ipmmu-vmsa";
	reg = <0 0xffc80000 0 0x1000>;
	interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_gp: mmu@e62a0000 {
	compatible = "renesas,ipmmu-r8a7793",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe62a0000 0 0x1000>;
	interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	icram0: sram@e63a0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63a0000 0 0x12000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63a0000 0x12000>;
	};

	icram1: sram@e63c0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63c0000 0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63c0000 0x1000>;

	smp-sram@0 {
	compatible = "renesas,smp-sram";
	reg = <0 0x100>;
	};
	};

	/* The memory map in the User's Manual maps the cores to
	* bus numbers
	*/
	i2c0: i2c@e6508000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7793",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c1: i2c@e6518000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7793",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6518000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c2: i2c@e6530000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7793",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6530000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c3: i2c@e6540000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7793",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6540000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c4: i2c@e6520000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7793",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6520000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c5: i2c@e6528000 {
	/* doesn't need pinmux */
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7793",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6528000 0 0x40>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 925>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 925>;
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c6: i2c@e60b0000 {
	/* doesn't need pinmux */
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7793",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe60b0000 0 0x425>;
	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 926>;
	dmas = <&dmac0 0x77>, <&dmac0 0x78>,
	<&dmac1 0x77>, <&dmac1 0x78>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 926>;
	status = "disabled";
	};

	i2c7: i2c@e6500000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7793",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe6500000 0 0x425>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 318>;
	dmas = <&dmac0 0x61>, <&dmac0 0x62>,
	<&dmac1 0x61>, <&dmac1 0x62>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 318>;
	status = "disabled";
	};

	i2c8: i2c@e6510000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7793",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe6510000 0 0x425>;
	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 323>;
	dmas = <&dmac0 0x65>, <&dmac0 0x66>,
	<&dmac1 0x65>, <&dmac1 0x66>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 323>;
	status = "disabled";
	};

	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a7793",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x20000>;
	interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	dmac1: dma-controller@e6720000 {
	compatible = "renesas,dmac-r8a7793",
	"renesas,rcar-dmac";
	reg = <0 0xe6720000 0 0x20000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	qspi: spi@e6b10000 {
	compatible = "renesas,qspi-r8a7793", "renesas,qspi";
	reg = <0 0xe6b10000 0 0x2c>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 917>;
	dmas = <&dmac0 0x17>, <&dmac0 0x18>,
	<&dmac1 0x17>, <&dmac1 0x18>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 917>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	scifa0: serial@e6c40000 {
	compatible = "renesas,scifa-r8a7793",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c40000 0 64>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 204>;
	clock-names = "fck";
	dmas = <&dmac0 0x21>, <&dmac0 0x22>,
	<&dmac1 0x21>, <&dmac1 0x22>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 204>;
	status = "disabled";
	};

	scifa1: serial@e6c50000 {
	compatible = "renesas,scifa-r8a7793",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c50000 0 64>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 203>;
	clock-names = "fck";
	dmas = <&dmac0 0x25>, <&dmac0 0x26>,
	<&dmac1 0x25>, <&dmac1 0x26>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 203>;
	status = "disabled";
	};

	scifa2: serial@e6c60000 {
	compatible = "renesas,scifa-r8a7793",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c60000 0 64>;
	interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 202>;
	clock-names = "fck";
	dmas = <&dmac0 0x27>, <&dmac0 0x28>,
	<&dmac1 0x27>, <&dmac1 0x28>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 202>;
	status = "disabled";
	};

	scifa3: serial@e6c70000 {
	compatible = "renesas,scifa-r8a7793",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c70000 0 64>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1106>;
	clock-names = "fck";
	dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
	<&dmac1 0x1b>, <&dmac1 0x1c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 1106>;
	status = "disabled";
	};

	scifa4: serial@e6c78000 {
	compatible = "renesas,scifa-r8a7793",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c78000 0 64>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1107>;
	clock-names = "fck";
	dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
	<&dmac1 0x1f>, <&dmac1 0x20>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 1107>;
	status = "disabled";
	};

	scifa5: serial@e6c80000 {
	compatible = "renesas,scifa-r8a7793",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c80000 0 64>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1108>;
	clock-names = "fck";
	dmas = <&dmac0 0x23>, <&dmac0 0x24>,
	<&dmac1 0x23>, <&dmac1 0x24>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 1108>;
	status = "disabled";
	};

	scifb0: serial@e6c20000 {
	compatible = "renesas,scifb-r8a7793",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6c20000 0 0x100>;
	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 206>;
	clock-names = "fck";
	dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
	<&dmac1 0x3d>, <&dmac1 0x3e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 206>;
	status = "disabled";
	};

	scifb1: serial@e6c30000 {
	compatible = "renesas,scifb-r8a7793",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6c30000 0 0x100>;
	interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 207>;
	clock-names = "fck";
	dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
	<&dmac1 0x19>, <&dmac1 0x1a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 207>;
	status = "disabled";
	};

	scifb2: serial@e6ce0000 {
	compatible = "renesas,scifb-r8a7793",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6ce0000 0 0x100>;
	interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 216>;
	clock-names = "fck";
	dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
	<&dmac1 0x1d>, <&dmac1 0x1e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 216>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a7793",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e60000 0 64>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
	<&dmac1 0x29>, <&dmac1 0x2a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 721>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a7793",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e68000 0 64>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
	<&dmac1 0x2d>, <&dmac1 0x2e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 720>;
	status = "disabled";
	};

	scif2: serial@e6e58000 {
	compatible = "renesas,scif-r8a7793",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e58000 0 64>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
	<&dmac1 0x2b>, <&dmac1 0x2c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 719>;
	status = "disabled";
	};

	scif3: serial@e6ea8000 {
	compatible = "renesas,scif-r8a7793",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ea8000 0 64>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
	<&dmac1 0x2f>, <&dmac1 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 718>;
	status = "disabled";
	};

	scif4: serial@e6ee0000 {
	compatible = "renesas,scif-r8a7793",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ee0000 0 64>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
	<&dmac1 0xfb>, <&dmac1 0xfc>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 715>;
	status = "disabled";
	};

	scif5: serial@e6ee8000 {
	compatible = "renesas,scif-r8a7793",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ee8000 0 64>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
	<&dmac1 0xfd>, <&dmac1 0xfe>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 714>;
	status = "disabled";
	};

	hscif0: serial@e62c0000 {
	compatible = "renesas,hscif-r8a7793",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c0000 0 96>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
	<&dmac1 0x39>, <&dmac1 0x3a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 717>;
	status = "disabled";
	};

	hscif1: serial@e62c8000 {
	compatible = "renesas,hscif-r8a7793",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c8000 0 96>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
	<&dmac1 0x4d>, <&dmac1 0x4e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";
	};

	hscif2: serial@e62d0000 {
	compatible = "renesas,hscif-r8a7793",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62d0000 0 96>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
	<&dmac1 0x3b>, <&dmac1 0x3c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 713>;
	status = "disabled";
	};

	can0: can@e6e80000 {
	compatible = "renesas,can-r8a7793",
	"renesas,rcar-gen2-can";
	reg = <0 0xe6e80000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 916>;
	status = "disabled";
	};

	can1: can@e6e88000 {
	compatible = "renesas,can-r8a7793",
	"renesas,rcar-gen2-can";
	reg = <0 0xe6e88000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 915>;
	status = "disabled";
	};

	vin0: video@e6ef0000 {
	compatible = "renesas,vin-r8a7793",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef0000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 811>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 811>;
	status = "disabled";
	};

	vin1: video@e6ef1000 {
	compatible = "renesas,vin-r8a7793",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef1000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 810>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 810>;
	status = "disabled";
	};

	vin2: video@e6ef2000 {
	compatible = "renesas,vin-r8a7793",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef2000 0 0x1000>;
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 809>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 809>;
	status = "disabled";
	};

	rcar_sound: sound@ec500000 {
	/*
	* #sound-dai-cells is required
	*
	* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
	* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
	*/
	compatible = "renesas,rcar_sound-r8a7793",
	"renesas,rcar_sound-gen2";
	reg = <0 0xec500000 0 0x1000>, /* SCU */
	<0 0xec5a0000 0 0x100>, /* ADG */
	<0 0xec540000 0 0x1000>, /* SSIU */
	<0 0xec541000 0 0x280>, /* SSI */
	<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
	reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

	clocks = <&cpg CPG_MOD 1005>,
	<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
	<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
	<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
	<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
	<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
	<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
	<&cpg CPG_CORE R8A7793_CLK_M2>;
	clock-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0",
	"src.9", "src.8", "src.7", "src.6",
	"src.5", "src.4", "src.3", "src.2",
	"src.1", "src.0",
	"dvc.0", "dvc.1",
	"clk_a", "clk_b", "clk_c", "clk_i";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 1005>,
	<&cpg 1006>, <&cpg 1007>,
	<&cpg 1008>, <&cpg 1009>,
	<&cpg 1010>, <&cpg 1011>,
	<&cpg 1012>, <&cpg 1013>,
	<&cpg 1014>, <&cpg 1015>;
	reset-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0";

	status = "disabled";

	rcar_sound,dvc {
	dvc0: dvc-0 {
	dmas = <&audma1 0xbc>;
	dma-names = "tx";
	};
	dvc1: dvc-1 {
	dmas = <&audma1 0xbe>;
	dma-names = "tx";
	};
	};

	rcar_sound,src {
	src0: src-0 {
	interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x85>, <&audma1 0x9a>;
	dma-names = "rx", "tx";
	};
	src1: src-1 {
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x87>, <&audma1 0x9c>;
	dma-names = "rx", "tx";
	};
	src2: src-2 {
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x89>, <&audma1 0x9e>;
	dma-names = "rx", "tx";
	};
	src3: src-3 {
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8b>, <&audma1 0xa0>;
	dma-names = "rx", "tx";
	};
	src4: src-4 {
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8d>, <&audma1 0xb0>;
	dma-names = "rx", "tx";
	};
	src5: src-5 {
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8f>, <&audma1 0xb2>;
	dma-names = "rx", "tx";
	};
	src6: src-6 {
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x91>, <&audma1 0xb4>;
	dma-names = "rx", "tx";
	};
	src7: src-7 {
	interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x93>, <&audma1 0xb6>;
	dma-names = "rx", "tx";
	};
	src8: src-8 {
	interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x95>, <&audma1 0xb8>;
	dma-names = "rx", "tx";
	};
	src9: src-9 {
	interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x97>, <&audma1 0xba>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssi {
	ssi0: ssi-0 {
	interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x01>, <&audma1 0x02>,
	<&audma0 0x15>, <&audma1 0x16>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi1: ssi-1 {
	interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x03>, <&audma1 0x04>,
	<&audma0 0x49>, <&audma1 0x4a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi2: ssi-2 {
	interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x05>, <&audma1 0x06>,
	<&audma0 0x63>, <&audma1 0x64>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi3: ssi-3 {
	interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x07>, <&audma1 0x08>,
	<&audma0 0x6f>, <&audma1 0x70>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi4: ssi-4 {
	interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x09>, <&audma1 0x0a>,
	<&audma0 0x71>, <&audma1 0x72>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi5: ssi-5 {
	interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0b>, <&audma1 0x0c>,
	<&audma0 0x73>, <&audma1 0x74>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi6: ssi-6 {
	interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0d>, <&audma1 0x0e>,
	<&audma0 0x75>, <&audma1 0x76>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi7: ssi-7 {
	interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0f>, <&audma1 0x10>,
	<&audma0 0x79>, <&audma1 0x7a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi8: ssi-8 {
	interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x11>, <&audma1 0x12>,
	<&audma0 0x7b>, <&audma1 0x7c>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi9: ssi-9 {
	interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x13>, <&audma1 0x14>,
	<&audma0 0x7d>, <&audma1 0x7e>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	};
	};

	audma0: dma-controller@ec700000 {
	compatible = "renesas,dmac-r8a7793",
	"renesas,rcar-dmac";
	reg = <0 0xec700000 0 0x10000>;
	interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12";
	clocks = <&cpg CPG_MOD 502>;
	clock-names = "fck";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 502>;
	#dma-cells = <1>;
	dma-channels = <13>;
	};

	audma1: dma-controller@ec720000 {
	compatible = "renesas,dmac-r8a7793",
	"renesas,rcar-dmac";
	reg = <0 0xec720000 0 0x10000>;
	interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12";
	clocks = <&cpg CPG_MOD 501>;
	clock-names = "fck";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 501>;
	#dma-cells = <1>;
	dma-channels = <13>;
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a7793",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee100000 0 0x328>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
	<&dmac1 0xcd>, <&dmac1 0xce>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <195000000>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	status = "disabled";
	};

	sdhi1: sd@ee140000 {
	compatible = "renesas,sdhi-r8a7793",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee140000 0 0x100>;
	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 312>;
	dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
	<&dmac1 0xc1>, <&dmac1 0xc2>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <97500000>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 312>;
	status = "disabled";
	};

	sdhi2: sd@ee160000 {
	compatible = "renesas,sdhi-r8a7793",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee160000 0 0x100>;
	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 311>;
	dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
	<&dmac1 0xd3>, <&dmac1 0xd4>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <97500000>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 311>;
	status = "disabled";
	};

	mmcif0: mmc@ee200000 {
	compatible = "renesas,mmcif-r8a7793",
	"renesas,sh-mmcif";
	reg = <0 0xee200000 0 0x80>;
	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 315>;
	dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
	<&dmac1 0xd1>, <&dmac1 0xd2>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 315>;
	reg-io-width = <4>;
	status = "disabled";
	max-frequency = <97500000>;
	};

	ether: ethernet@ee700000 {
	compatible = "renesas,ether-r8a7793",
	"renesas,rcar-gen2-ether";
	reg = <0 0xee700000 0 0x400>;
	interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 813>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 813>;
	phy-mode = "rmii";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	gic: interrupt-controller@f1001000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0 0xf1001000 0 0x1000>,
	<0 0xf1002000 0 0x2000>,
	<0 0xf1004000 0 0x2000>,
	<0 0xf1006000 0 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	fdp1@fe940000 {
	compatible = "renesas,fdp1";
	reg = <0 0xfe940000 0 0x2400>;
	interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 119>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 119>;
	};

	fdp1@fe944000 {
	compatible = "renesas,fdp1";
	reg = <0 0xfe944000 0 0x2400>;
	interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 118>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 118>;
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a7793";
	reg = <0 0xfeb00000 0 0x40000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&cpg CPG_MOD 724>,
	- <&cpg CPG_MOD 723>;
	+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
	clock-names = "du.0", "du.1";
	+ resets = <&cpg 724>;
	+ reset-names = "du.0";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb: endpoint {
	};
	};
	port@1 {
	reg = <1>;
	du_out_lvds0: endpoint {
	remote-endpoint = <&lvds0_in>;
	};
	};
	};
	};

	lvds0: lvds@feb90000 {
	compatible = "renesas,r8a7793-lvds";
	reg = <0 0xfeb90000 0 0x1c>;
	clocks = <&cpg CPG_MOD 726>;
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 726>;

	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds0_in: endpoint {
	remote-endpoint = <&du_out_lvds0>;
	};
	};
	port@1 {
	reg = <1>;
	lvds0_out: endpoint {
	};
	};
	};
	};

	prr: chipid@ff000044 {
	compatible = "renesas,prr";
	reg = <0 0xff000044 0 4>;
	};

	cmt0: timer@ffca0000 {
	compatible = "renesas,r8a7793-cmt0",
	"renesas,rcar-gen2-cmt0";
	reg = <0 0xffca0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 124>;
	clock-names = "fck";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 124>;

	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a7793-cmt1",
	"renesas,rcar-gen2-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 329>;
	clock-names = "fck";
	power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
	resets = <&cpg 329>;

	status = "disabled";
	};
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	polling-delay-passive = <0>;
	polling-delay = <0>;

	thermal-sensors = <&thermal>;

	trips {
	cpu-crit {
	temperature = <95000>;
	hysteresis = <0>;
	type = "critical";
	};
	};
	cooling-maps {
	};
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clock - can be overridden by the board */
	usb_extal_clk: usb_extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <48000000>;
	};
	};
	diff --git a/sys/gnu/dts/arm/r8a7794-alt.dts b/sys/gnu/dts/arm/r8a7794-alt.dts
	index f79fce74cd9c..935935c1dbac 100644
	--- a/sys/gnu/dts/arm/r8a7794-alt.dts
	+++ b/sys/gnu/dts/arm/r8a7794-alt.dts
	@@ -1,486 +1,487 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the Alt board
	*
	* Copyright (C) 2014 Renesas Electronics Corporation
	*/

	/dts-v1/;
	#include "r8a7794.dtsi"
	#include <dt-bindings/gpio/gpio.h>

	/ {
	model = "Alt";
	compatible = "renesas,alt", "renesas,r8a7794";

	aliases {
	serial0 = &scif2;
	i2c9 = &gpioi2c1;
	i2c10 = &gpioi2c4;
	i2c11 = &i2chdmi;
	i2c12 = &i2cexio4;
	};

	chosen {
	bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
	stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
	device_type = "memory";
	reg = <0 0x40000000 0 0x40000000>;
	};

	d3_3v: regulator-d3-3v {
	compatible = "regulator-fixed";
	regulator-name = "D3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vcc_sdhi0: regulator-vcc-sdhi0 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI0 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vccq_sdhi0: regulator-vccq-sdhi0 {
	compatible = "regulator-gpio";

	regulator-name = "SDHI0 VccQ";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
	gpios-states = <1>;
	states = <3300000 1>, <1800000 0>;
	};

	vcc_sdhi1: regulator-vcc-sdhi1 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI1 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vccq_sdhi1: regulator-vccq-sdhi1 {
	compatible = "regulator-gpio";

	regulator-name = "SDHI1 VccQ";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
	gpios-states = <1>;
	states = <3300000 1>, <1800000 0>;
	};

	lbsc {
	#address-cells = <1>;
	#size-cells = <1>;
	};

	vga-encoder {
	compatible = "adi,adv7123";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7123_in: endpoint {
	remote-endpoint = <&du_out_rgb1>;
	};
	};
	port@1 {
	reg = <1>;
	adv7123_out: endpoint {
	remote-endpoint = <&vga_in>;
	};
	};
	};
	};

	vga {
	compatible = "vga-connector";

	port {
	vga_in: endpoint {
	remote-endpoint = <&adv7123_out>;
	};
	};
	};

	x2_clk: x2-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <74250000>;
	};

	x13_clk: x13-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <148500000>;
	};

	gpioi2c1: i2c-9 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "i2c-gpio";
	status = "disabled";
	scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	};

	gpioi2c4: i2c-10 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "i2c-gpio";
	status = "disabled";
	scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	i2c-gpio,delay-us = <5>;
	};

	/*
	* A fallback to GPIO is provided for I2C1.
	*/
	i2chdmi: i2c-11 {
	compatible = "i2c-demux-pinctrl";
	i2c-parent = <&i2c1>, <&gpioi2c1>;
	i2c-bus-name = "i2c-hdmi";
	#address-cells = <1>;
	#size-cells = <0>;

	composite-in@20 {
	compatible = "adi,adv7180";
	reg = <0x20>;
	remote = <&vin0>;

	port {
	adv7180: endpoint {
	bus-width = <8>;
	remote-endpoint = <&vin0ep>;
	};
	};
	};

	eeprom@50 {
	compatible = "renesas,r1ex24002", "atmel,24c02";
	reg = <0x50>;
	pagesize = <16>;
	};
	};

	/*
	* I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
	* A fallback to GPIO is provided.
	*/
	i2cexio4: i2c-14 {
	compatible = "i2c-demux-pinctrl";
	i2c-parent = <&i2c4>, <&gpioi2c4>;
	i2c-bus-name = "i2c-exio4";
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	&pci0 {
	status = "okay";
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";
	};

	&pci1 {
	status = "okay";
	pinctrl-0 = <&usb1_pins>;
	pinctrl-names = "default";
	};

	&usbphy {
	status = "okay";
	};

	&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";
	status = "okay";

	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
	<&x13_clk>, <&x2_clk>;
	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";

	ports {
	port@1 {
	endpoint {
	remote-endpoint = <&adv7123_in>;
	};
	};
	};
	};

	&extal_clk {
	clock-frequency = <20000000>;
	};

	&pfc {
	pinctrl-0 = <&scif_clk_pins>;
	pinctrl-names = "default";

	du_pins: du {
	groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
	function = "du1";
	};

	scif2_pins: scif2 {
	groups = "scif2_data";
	function = "scif2";
	};

	scif_clk_pins: scif_clk {
	groups = "scif_clk";
	function = "scif_clk";
	};

	ether_pins: ether {
	groups = "eth_link", "eth_mdio", "eth_rmii";
	function = "eth";
	};

	phy1_pins: phy1 {
	groups = "intc_irq8";
	function = "intc";
	};

	i2c1_pins: i2c1 {
	groups = "i2c1";
	function = "i2c1";
	};

	i2c4_pins: i2c4 {
	groups = "i2c4";
	function = "i2c4";
	};

	vin0_pins: vin0 {
	groups = "vin0_data8", "vin0_clk";
	function = "vin0";
	};

	mmcif0_pins: mmcif0 {
	groups = "mmc_data8", "mmc_ctrl";
	function = "mmc";
	};

	sdhi0_pins: sd0 {
	groups = "sdhi0_data4", "sdhi0_ctrl";
	function = "sdhi0";
	power-source = <3300>;
	};

	sdhi0_pins_uhs: sd0_uhs {
	groups = "sdhi0_data4", "sdhi0_ctrl";
	function = "sdhi0";
	power-source = <1800>;
	};

	sdhi1_pins: sd1 {
	groups = "sdhi1_data4", "sdhi1_ctrl";
	function = "sdhi1";
	power-source = <3300>;
	};

	sdhi1_pins_uhs: sd1_uhs {
	groups = "sdhi1_data4", "sdhi1_ctrl";
	function = "sdhi1";
	power-source = <1800>;
	};

	usb0_pins: usb0 {
	groups = "usb0";
	function = "usb0";
	};

	usb1_pins: usb1 {
	groups = "usb1";
	function = "usb1";
	};
	};

	&cmt0 {
	status = "okay";
	};

	&pfc {
	qspi_pins: qspi {
	groups = "qspi_ctrl", "qspi_data4";
	function = "qspi";
	};
	};

	&ether {
	pinctrl-0 = <&ether_pins &phy1_pins>;
	pinctrl-names = "default";

	phy-handle = <&phy1>;
	renesas,ether-link-active-low;
	status = "okay";

	phy1: ethernet-phy@1 {
	reg = <1>;
	interrupt-parent = <&irqc0>;
	interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
	micrel,led-mode = <1>;
	+ reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
	};
	};

	&mmcif0 {
	pinctrl-0 = <&mmcif0_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&d3_3v>;
	vqmmc-supply = <&d3_3v>;
	bus-width = <8>;
	non-removable;
	status = "okay";
	};

	&rwdt {
	timeout-sec = <60>;
	status = "okay";
	};

	&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-1 = <&sdhi0_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi0>;
	vqmmc-supply = <&vccq_sdhi0>;
	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
	};

	&sdhi1 {
	pinctrl-0 = <&sdhi1_pins>;
	pinctrl-1 = <&sdhi1_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi1>;
	vqmmc-supply = <&vccq_sdhi1>;
	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
	sd-uhs-sdr50;
	status = "okay";
	};

	&i2c1 {
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-names = "i2c-hdmi";

	clock-frequency = <400000>;
	};

	&i2c4 {
	pinctrl-0 = <&i2c4_pins>;
	pinctrl-names = "i2c-exio4";
	};

	&i2c7 {
	status = "okay";
	clock-frequency = <100000>;

	pmic@58 {
	compatible = "dlg,da9063";
	reg = <0x58>;
	interrupt-parent = <&gpio3>;
	interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;

	rtc {
	compatible = "dlg,da9063-rtc";
	};

	wdt {
	compatible = "dlg,da9063-watchdog";
	};
	};
	};

	&vin0 {
	status = "okay";
	pinctrl-0 = <&vin0_pins>;
	pinctrl-names = "default";

	port {
	vin0ep: endpoint {
	remote-endpoint = <&adv7180>;
	bus-width = <8>;
	};
	};
	};

	&scif2 {
	pinctrl-0 = <&scif2_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&scif_clk {
	clock-frequency = <14745600>;
	};

	&qspi {
	pinctrl-0 = <&qspi_pins>;
	pinctrl-names = "default";

	status = "okay";

	flash@0 {
	compatible = "spansion,s25fl512s", "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <30000000>;
	spi-tx-bus-width = <4>;
	spi-rx-bus-width = <4>;
	spi-cpol;
	spi-cpha;
	m25p,fast-read;

	partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
	label = "loader";
	reg = <0x00000000 0x00040000>;
	read-only;
	};
	partition@40000 {
	label = "system";
	reg = <0x00040000 0x00040000>;
	read-only;
	};
	partition@80000 {
	label = "user";
	reg = <0x00080000 0x03f80000>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/r8a7794-silk.dts b/sys/gnu/dts/arm/r8a7794-silk.dts
	index 2c16ad854300..b8b0941f677c 100644
	--- a/sys/gnu/dts/arm/r8a7794-silk.dts
	+++ b/sys/gnu/dts/arm/r8a7794-silk.dts
	@@ -1,568 +1,567 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the SILK board
	*
	* Copyright (C) 2014 Renesas Electronics Corporation
	* Copyright (C) 2014-2015 Renesas Solutions Corp.
	* Copyright (C) 2014-2015 Cogent Embedded, Inc.
	*/

	/*
	* SSI-AK4643
	*
	* SW1: 2-1: AK4643
	* 2-3: ADV7511
	*
	* This command is required before playback/capture:
	*
	* amixer set "LINEOUT Mixer DACL" on
	*/

	/dts-v1/;
	#include "r8a7794.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>

	/ {
	model = "SILK";
	compatible = "renesas,silk", "renesas,r8a7794";

	aliases {
	serial0 = &scif2;
	i2c9 = &gpioi2c1;
	i2c10 = &i2chdmi;
	};

	chosen {
	bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
	stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
	device_type = "memory";
	reg = <0 0x40000000 0 0x40000000>;
	};

	gpio-keys {
	compatible = "gpio-keys";

	key-3 {
	gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_3>;
	label = "SW3";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-4 {
	gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_4>;
	label = "SW4";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-6 {
	gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_6>;
	label = "SW6";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-a {
	gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_A>;
	label = "SW12-1";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-b {
	gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_B>;
	label = "SW12-2";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-c {
	gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_C>;
	label = "SW12-3";
	wakeup-source;
	debounce-interval = <20>;
	};
	key-d {
	gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_D>;
	label = "SW12-4";
	wakeup-source;
	debounce-interval = <20>;
	};
	};

	d3_3v: regulator-d3-3v {
	compatible = "regulator-fixed";
	regulator-name = "D3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vcc_sdhi1: regulator-vcc-sdhi1 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI1 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vccq_sdhi1: regulator-vccq-sdhi1 {
	compatible = "regulator-gpio";

	regulator-name = "SDHI1 VccQ";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
	gpios-states = <1>;
	states = <3300000 1>, <1800000 0>;
	};

	vga-encoder {
	compatible = "adi,adv7123";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7123_in: endpoint {
	remote-endpoint = <&du_out_rgb1>;
	};
	};
	port@1 {
	reg = <1>;
	adv7123_out: endpoint {
	remote-endpoint = <&vga_in>;
	};
	};
	};
	};

	hdmi-out {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con: endpoint {
	remote-endpoint = <&adv7511_out>;
	};
	};
	};

	vga {
	compatible = "vga-connector";

	port {
	vga_in: endpoint {
	remote-endpoint = <&adv7123_out>;
	};
	};
	};

	x2_clk: x2-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <148500000>;
	};

	x3_clk: x3-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <74250000>;
	};

	x9_clk: audio_clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <12288000>;
	};

	sound {
	compatible = "simple-audio-card";

	simple-audio-card,format = "left_j";
	simple-audio-card,bitclock-master = <&soundcodec>;
	simple-audio-card,frame-master = <&soundcodec>;

	simple-audio-card,cpu {
	sound-dai = <&rcar_sound>;
	};

	soundcodec: simple-audio-card,codec {
	sound-dai = <&ak4643>;
	clocks = <&x9_clk>;
	};
	};

	gpioi2c1: i2c-9 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "i2c-gpio";
	status = "disabled";
	scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	i2c-gpio,delay-us = <5>;
	};

	/*
	* A fallback to GPIO is provided for I2C1.
	*/
	i2chdmi: i2c-10 {
	compatible = "i2c-demux-pinctrl";
	i2c-parent = <&i2c1>, <&gpioi2c1>;
	i2c-bus-name = "i2c-hdmi";
	#address-cells = <1>;
	#size-cells = <0>;

	ak4643: codec@12 {
	compatible = "asahi-kasei,ak4643";
	#sound-dai-cells = <0>;
	reg = <0x12>;
	};

	composite-in@20 {
	compatible = "adi,adv7180";
	reg = <0x20>;
	remote = <&vin0>;

	port {
	adv7180: endpoint {
	bus-width = <8>;
	remote-endpoint = <&vin0ep>;
	};
	};
	};

	hdmi@39 {
	compatible = "adi,adv7511w";
	reg = <0x39>;
	interrupt-parent = <&gpio5>;
	interrupts = <23 IRQ_TYPE_LEVEL_LOW>;

	adi,input-depth = <8>;
	adi,input-colorspace = "rgb";
	adi,input-clock = "1x";
	- adi,input-style = <1>;
	- adi,input-justification = "evenly";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7511_in: endpoint {
	remote-endpoint = <&du_out_rgb0>;
	};
	};

	port@1 {
	reg = <1>;
	adv7511_out: endpoint {
	remote-endpoint = <&hdmi_con>;
	};
	};
	};
	};

	eeprom@50 {
	compatible = "renesas,r1ex24002", "atmel,24c02";
	reg = <0x50>;
	pagesize = <16>;
	};
	};
	};

	&extal_clk {
	clock-frequency = <20000000>;
	};

	&pfc {
	pinctrl-0 = <&scif_clk_pins>;
	pinctrl-names = "default";

	scif2_pins: scif2 {
	groups = "scif2_data";
	function = "scif2";
	};

	scif_clk_pins: scif_clk {
	groups = "scif_clk";
	function = "scif_clk";
	};

	ether_pins: ether {
	groups = "eth_link", "eth_mdio", "eth_rmii";
	function = "eth";
	};

	phy1_pins: phy1 {
	groups = "intc_irq8";
	function = "intc";
	};

	i2c1_pins: i2c1 {
	groups = "i2c1";
	function = "i2c1";
	};

	mmcif0_pins: mmcif0 {
	groups = "mmc_data8", "mmc_ctrl";
	function = "mmc";
	};

	sdhi1_pins: sd1 {
	groups = "sdhi1_data4", "sdhi1_ctrl";
	function = "sdhi1";
	};

	qspi_pins: qspi {
	groups = "qspi_ctrl", "qspi_data4";
	function = "qspi";
	};

	vin0_pins: vin0 {
	groups = "vin0_data8", "vin0_clk";
	function = "vin0";
	};

	usb0_pins: usb0 {
	groups = "usb0";
	function = "usb0";
	};

	usb1_pins: usb1 {
	groups = "usb1";
	function = "usb1";
	};

	du0_pins: du0 {
	groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out";
	function = "du0";
	};

	du1_pins: du1 {
	groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
	function = "du1";
	};

	ssi_pins: sound {
	groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
	function = "ssi";
	};

	audio_clk_pins: audio_clk {
	groups = "audio_clkc";
	function = "audio_clk";
	};
	};

	&scif2 {
	pinctrl-0 = <&scif2_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&scif_clk {
	clock-frequency = <14745600>;
	};

	&ether {
	pinctrl-0 = <&ether_pins &phy1_pins>;
	pinctrl-names = "default";

	phy-handle = <&phy1>;
	renesas,ether-link-active-low;
	status = "okay";

	phy1: ethernet-phy@1 {
	reg = <1>;
	interrupt-parent = <&irqc0>;
	interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
	micrel,led-mode = <1>;
	+ reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
	};
	};

	&i2c1 {
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-names = "i2c-hdmi";

	clock-frequency = <400000>;
	};

	&i2c7 {
	status = "okay";
	clock-frequency = <100000>;

	pmic@58 {
	compatible = "dlg,da9063";
	reg = <0x58>;
	interrupt-parent = <&gpio3>;
	interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;

	onkey {
	compatible = "dlg,da9063-onkey";
	};

	rtc {
	compatible = "dlg,da9063-rtc";
	};

	wdt {
	compatible = "dlg,da9063-watchdog";
	};
	};
	};

	&mmcif0 {
	pinctrl-0 = <&mmcif0_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&d3_3v>;
	vqmmc-supply = <&d3_3v>;
	bus-width = <8>;
	non-removable;
	status = "okay";
	};

	&sdhi1 {
	pinctrl-0 = <&sdhi1_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&vcc_sdhi1>;
	vqmmc-supply = <&vccq_sdhi1>;
	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&qspi {
	pinctrl-0 = <&qspi_pins>;
	pinctrl-names = "default";

	status = "okay";

	flash@0 {
	compatible = "spansion,s25fl512s", "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <30000000>;
	spi-tx-bus-width = <4>;
	spi-rx-bus-width = <4>;
	spi-cpol;
	spi-cpha;
	m25p,fast-read;

	partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
	label = "loader";
	reg = <0x00000000 0x00040000>;
	read-only;
	};
	partition@40000 {
	label = "user";
	reg = <0x00040000 0x00400000>;
	read-only;
	};
	partition@440000 {
	label = "flash";
	reg = <0x00440000 0x03bc0000>;
	};
	};
	};
	};

	/* composite video input */
	&vin0 {
	status = "okay";
	pinctrl-0 = <&vin0_pins>;
	pinctrl-names = "default";

	port {
	vin0ep: endpoint {
	remote-endpoint = <&adv7180>;
	bus-width = <8>;
	};
	};
	};

	&pci0 {
	status = "okay";
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";
	};

	&pci1 {
	status = "okay";
	pinctrl-0 = <&usb1_pins>;
	pinctrl-names = "default";
	};

	&usbphy {
	status = "okay";
	};

	&du {
	pinctrl-0 = <&du0_pins &du1_pins>;
	pinctrl-names = "default";
	status = "okay";

	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
	<&x2_clk>, <&x3_clk>;
	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";

	ports {
	port@0 {
	endpoint {
	remote-endpoint = <&adv7511_in>;
	};
	};
	port@1 {
	endpoint {
	remote-endpoint = <&adv7123_in>;
	};
	};
	};
	};

	&rcar_sound {
	pinctrl-0 = <&ssi_pins &audio_clk_pins>;
	pinctrl-names = "default";
	status = "okay";

	/* Single DAI */
	#sound-dai-cells = <0>;

	rcar_sound,dai {
	dai0 {
	playback = <&ssi0>;
	capture = <&ssi1>;
	};
	};
	};

	&rwdt {
	timeout-sec = <60>;
	status = "okay";
	};

	&ssi1 {
	shared-pin;
	};
	diff --git a/sys/gnu/dts/arm/r8a7794.dtsi b/sys/gnu/dts/arm/r8a7794.dtsi
	index 05ef79c6ed7f..2c9e7a1ebfec 100644
	--- a/sys/gnu/dts/arm/r8a7794.dtsi
	+++ b/sys/gnu/dts/arm/r8a7794.dtsi
	@@ -1,1432 +1,1434 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the R-Car E2 (R8A77940) SoC
	*
	* Copyright (C) 2014 Renesas Electronics Corporation
	* Copyright (C) 2014 Ulrich Hecht
	*/

	#include <dt-bindings/clock/r8a7794-cpg-mssr.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/power/r8a7794-sysc.h>

	/ {
	compatible = "renesas,r8a7794";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	i2c6 = &i2c6;
	i2c7 = &i2c7;
	spi0 = &qspi;
	vin0 = &vin0;
	vin1 = &vin1;
	};

	/*
	* The external audio clocks are configured as 0 Hz fixed frequency
	* clocks by default.
	* Boards that provide audio clocks should override them.
	*/
	audio_clka: audio_clka {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	audio_clkb: audio_clkb {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	audio_clkc: audio_clkc {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	/* External CAN clock */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "renesas,apmu";

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0>;
	clock-frequency = <1000000000>;
	clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
	power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
	next-level-cache = <&L2_CA7>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <1>;
	clock-frequency = <1000000000>;
	clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
	power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
	next-level-cache = <&L2_CA7>;
	};

	L2_CA7: cache-controller-0 {
	compatible = "cache";
	power-domains = <&sysc R8A7794_PD_CA7_SCU>;
	cache-unified;
	cache-level = <2>;
	};
	};

	/* External root clock */
	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	pmu {
	compatible = "arm,cortex-a7-pmu";
	interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	/* External SCIF clock */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;

	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a7794-wdt",
	"renesas,rcar-gen2-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a7794",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a7794",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a7794",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a7794",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a7794",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a7794",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 28>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	gpio6: gpio@e6055400 {
	compatible = "renesas,gpio-r8a7794",
	"renesas,rcar-gen2-gpio";
	reg = <0 0xe6055400 0 0x50>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 192 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 905>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 905>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a7794";
	reg = <0 0xe6060000 0 0x11c>;
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a7794-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>, <&usb_extal_clk>;
	clock-names = "extal", "usb_extal";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	apmu@e6151000 {
	compatible = "renesas,r8a7794-apmu", "renesas,apmu";
	reg = <0 0xe6151000 0 0x188>;
	cpus = <&cpu0 &cpu1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a7794-rst";
	reg = <0 0xe6160000 0 0x0100>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a7794-sysc";
	reg = <0 0xe6180000 0 0x0200>;
	#power-domain-cells = <1>;
	};

	irqc0: interrupt-controller@e61c0000 {
	compatible = "renesas,irqc-r8a7794", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	ipmmu_sy0: mmu@e6280000 {
	compatible = "renesas,ipmmu-r8a7794",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6280000 0 0x1000>;
	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_sy1: mmu@e6290000 {
	compatible = "renesas,ipmmu-r8a7794",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6290000 0 0x1000>;
	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_ds: mmu@e6740000 {
	compatible = "renesas,ipmmu-r8a7794",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe6740000 0 0x1000>;
	interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_mp: mmu@ec680000 {
	compatible = "renesas,ipmmu-r8a7794",
	"renesas,ipmmu-vmsa";
	reg = <0 0xec680000 0 0x1000>;
	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_mx: mmu@fe951000 {
	compatible = "renesas,ipmmu-r8a7794",
	"renesas,ipmmu-vmsa";
	reg = <0 0xfe951000 0 0x1000>;
	interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	ipmmu_gp: mmu@e62a0000 {
	compatible = "renesas,ipmmu-r8a7794",
	"renesas,ipmmu-vmsa";
	reg = <0 0xe62a0000 0 0x1000>;
	interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	status = "disabled";
	};

	icram0: sram@e63a0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63a0000 0 0x12000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63a0000 0x12000>;
	};

	icram1: sram@e63c0000 {
	compatible = "mmio-sram";
	reg = <0 0xe63c0000 0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0xe63c0000 0x1000>;

	smp-sram@0 {
	compatible = "renesas,smp-sram";
	reg = <0 0x100>;
	};
	};

	/* The memory map in the User's Manual maps the cores to
	* bus numbers
	*/
	i2c0: i2c@e6508000 {
	compatible = "renesas,i2c-r8a7794",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	#address-cells = <1>;
	#size-cells = <0>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c1: i2c@e6518000 {
	compatible = "renesas,i2c-r8a7794",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6518000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	#address-cells = <1>;
	#size-cells = <0>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c2: i2c@e6530000 {
	compatible = "renesas,i2c-r8a7794",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6530000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	#address-cells = <1>;
	#size-cells = <0>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c3: i2c@e6540000 {
	compatible = "renesas,i2c-r8a7794",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6540000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	#address-cells = <1>;
	#size-cells = <0>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c4: i2c@e6520000 {
	compatible = "renesas,i2c-r8a7794",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6520000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	#address-cells = <1>;
	#size-cells = <0>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c5: i2c@e6528000 {
	compatible = "renesas,i2c-r8a7794",
	"renesas,rcar-gen2-i2c";
	reg = <0 0xe6528000 0 0x40>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 925>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 925>;
	#address-cells = <1>;
	#size-cells = <0>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c6: i2c@e6500000 {
	compatible = "renesas,iic-r8a7794",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe6500000 0 0x425>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 318>;
	dmas = <&dmac0 0x61>, <&dmac0 0x62>,
	<&dmac1 0x61>, <&dmac1 0x62>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 318>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c7: i2c@e6510000 {
	compatible = "renesas,iic-r8a7794",
	"renesas,rcar-gen2-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe6510000 0 0x425>;
	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 323>;
	dmas = <&dmac0 0x65>, <&dmac0 0x66>,
	<&dmac1 0x65>, <&dmac1 0x66>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 323>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	hsusb: usb@e6590000 {
	compatible = "renesas,usbhs-r8a7794",
	"renesas,rcar-gen2-usbhs";
	reg = <0 0xe6590000 0 0x100>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 704>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 704>;
	renesas,buswait = <4>;
	phys = <&usb0 1>;
	phy-names = "usb";
	status = "disabled";
	};

	usbphy: usb-phy@e6590100 {
	compatible = "renesas,usb-phy-r8a7794",
	"renesas,rcar-gen2-usb-phy";
	reg = <0 0xe6590100 0 0x100>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cpg CPG_MOD 704>;
	clock-names = "usbhs";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 704>;
	status = "disabled";

	usb0: usb-channel@0 {
	reg = <0>;
	#phy-cells = <1>;
	};
	usb2: usb-channel@2 {
	reg = <2>;
	#phy-cells = <1>;
	};
	};

	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a7794",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x20000>;
	interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	dmac1: dma-controller@e6720000 {
	compatible = "renesas,dmac-r8a7794",
	"renesas,rcar-dmac";
	reg = <0 0xe6720000 0 0x20000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <15>;
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a7794",
	"renesas,etheravb-rcar-gen2";
	reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
	interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	qspi: spi@e6b10000 {
	compatible = "renesas,qspi-r8a7794", "renesas,qspi";
	reg = <0 0xe6b10000 0 0x2c>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 917>;
	dmas = <&dmac0 0x17>, <&dmac0 0x18>,
	<&dmac1 0x17>, <&dmac1 0x18>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 917>;
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	scifa0: serial@e6c40000 {
	compatible = "renesas,scifa-r8a7794",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c40000 0 64>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 204>;
	clock-names = "fck";
	dmas = <&dmac0 0x21>, <&dmac0 0x22>,
	<&dmac1 0x21>, <&dmac1 0x22>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 204>;
	status = "disabled";
	};

	scifa1: serial@e6c50000 {
	compatible = "renesas,scifa-r8a7794",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c50000 0 64>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 203>;
	clock-names = "fck";
	dmas = <&dmac0 0x25>, <&dmac0 0x26>,
	<&dmac1 0x25>, <&dmac1 0x26>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 203>;
	status = "disabled";
	};

	scifa2: serial@e6c60000 {
	compatible = "renesas,scifa-r8a7794",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c60000 0 64>;
	interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 202>;
	clock-names = "fck";
	dmas = <&dmac0 0x27>, <&dmac0 0x28>,
	<&dmac1 0x27>, <&dmac1 0x28>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 202>;
	status = "disabled";
	};

	scifa3: serial@e6c70000 {
	compatible = "renesas,scifa-r8a7794",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c70000 0 64>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1106>;
	clock-names = "fck";
	dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
	<&dmac1 0x1b>, <&dmac1 0x1c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 1106>;
	status = "disabled";
	};

	scifa4: serial@e6c78000 {
	compatible = "renesas,scifa-r8a7794",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c78000 0 64>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1107>;
	clock-names = "fck";
	dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
	<&dmac1 0x1f>, <&dmac1 0x20>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 1107>;
	status = "disabled";
	};

	scifa5: serial@e6c80000 {
	compatible = "renesas,scifa-r8a7794",
	"renesas,rcar-gen2-scifa", "renesas,scifa";
	reg = <0 0xe6c80000 0 64>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1108>;
	clock-names = "fck";
	dmas = <&dmac0 0x23>, <&dmac0 0x24>,
	<&dmac1 0x23>, <&dmac1 0x24>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 1108>;
	status = "disabled";
	};

	scifb0: serial@e6c20000 {
	compatible = "renesas,scifb-r8a7794",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6c20000 0 0x100>;
	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 206>;
	clock-names = "fck";
	dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
	<&dmac1 0x3d>, <&dmac1 0x3e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 206>;
	status = "disabled";
	};

	scifb1: serial@e6c30000 {
	compatible = "renesas,scifb-r8a7794",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6c30000 0 0x100>;
	interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 207>;
	clock-names = "fck";
	dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
	<&dmac1 0x19>, <&dmac1 0x1a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 207>;
	status = "disabled";
	};

	scifb2: serial@e6ce0000 {
	compatible = "renesas,scifb-r8a7794",
	"renesas,rcar-gen2-scifb", "renesas,scifb";
	reg = <0 0xe6ce0000 0 0x100>;
	interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 216>;
	clock-names = "fck";
	dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
	<&dmac1 0x1d>, <&dmac1 0x1e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 216>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a7794",
	"renesas,rcar-gen2-scif",
	"renesas,scif";
	reg = <0 0xe6e60000 0 64>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
	<&dmac1 0x29>, <&dmac1 0x2a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 721>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a7794",
	"renesas,rcar-gen2-scif",
	"renesas,scif";
	reg = <0 0xe6e68000 0 64>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
	<&dmac1 0x2d>, <&dmac1 0x2e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 720>;
	status = "disabled";
	};

	scif2: serial@e6e58000 {
	compatible = "renesas,scif-r8a7794",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6e58000 0 64>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
	<&dmac1 0x2b>, <&dmac1 0x2c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 719>;
	status = "disabled";
	};

	scif3: serial@e6ea8000 {
	compatible = "renesas,scif-r8a7794",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ea8000 0 64>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
	<&dmac1 0x2f>, <&dmac1 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 718>;
	status = "disabled";
	};

	scif4: serial@e6ee0000 {
	compatible = "renesas,scif-r8a7794",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ee0000 0 64>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
	<&dmac1 0xfb>, <&dmac1 0xfc>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 715>;
	status = "disabled";
	};

	scif5: serial@e6ee8000 {
	compatible = "renesas,scif-r8a7794",
	"renesas,rcar-gen2-scif", "renesas,scif";
	reg = <0 0xe6ee8000 0 64>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
	<&dmac1 0xfd>, <&dmac1 0xfe>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 714>;
	status = "disabled";
	};

	hscif0: serial@e62c0000 {
	compatible = "renesas,hscif-r8a7794",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c0000 0 96>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 717>,
	<&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
	<&dmac1 0x39>, <&dmac1 0x3a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 717>;
	status = "disabled";
	};

	hscif1: serial@e62c8000 {
	compatible = "renesas,hscif-r8a7794",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62c8000 0 96>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>,
	<&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
	<&dmac1 0x4d>, <&dmac1 0x4e>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";
	};

	hscif2: serial@e62d0000 {
	compatible = "renesas,hscif-r8a7794",
	"renesas,rcar-gen2-hscif", "renesas,hscif";
	reg = <0 0xe62d0000 0 96>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
	<&dmac1 0x3b>, <&dmac1 0x3c>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 713>;
	status = "disabled";
	};

	can0: can@e6e80000 {
	compatible = "renesas,can-r8a7794",
	"renesas,rcar-gen2-can";
	reg = <0 0xe6e80000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 916>;
	status = "disabled";
	};

	can1: can@e6e88000 {
	compatible = "renesas,can-r8a7794",
	"renesas,rcar-gen2-can";
	reg = <0 0xe6e88000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 915>;
	status = "disabled";
	};

	vin0: video@e6ef0000 {
	compatible = "renesas,vin-r8a7794",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef0000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 811>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 811>;
	status = "disabled";
	};

	vin1: video@e6ef1000 {
	compatible = "renesas,vin-r8a7794",
	"renesas,rcar-gen2-vin";
	reg = <0 0xe6ef1000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 810>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 810>;
	status = "disabled";
	};

	rcar_sound: sound@ec500000 {
	/*
	* #sound-dai-cells is required
	*
	* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
	* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
	*/
	compatible = "renesas,rcar_sound-r8a7794",
	"renesas,rcar_sound-gen2";
	reg = <0 0xec500000 0 0x1000>, /* SCU */
	<0 0xec5a0000 0 0x100>, /* ADG */
	<0 0xec540000 0 0x1000>, /* SSIU */
	<0 0xec541000 0 0x280>, /* SSI */
	<0 0xec740000 0 0x200>; /* Audio DMAC peri peri */
	reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

	clocks = <&cpg CPG_MOD 1005>,
	<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	<&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
	<&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
	<&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
	<&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
	<&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
	<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	<&audio_clka>, <&audio_clkb>, <&audio_clkc>,
	<&cpg CPG_CORE R8A7794_CLK_M2>;
	clock-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0",
	"src.6", "src.5", "src.4", "src.3",
	"src.2", "src.1",
	"ctu.0", "ctu.1",
	"mix.0", "mix.1",
	"dvc.0", "dvc.1",
	"clk_a", "clk_b", "clk_c", "clk_i";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 1005>,
	<&cpg 1006>, <&cpg 1007>,
	<&cpg 1008>, <&cpg 1009>,
	<&cpg 1010>, <&cpg 1011>,
	<&cpg 1012>, <&cpg 1013>,
	<&cpg 1014>, <&cpg 1015>;
	reset-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0";

	status = "disabled";

	rcar_sound,dvc {
	dvc0: dvc-0 {
	dmas = <&audma0 0xbc>;
	dma-names = "tx";
	};
	dvc1: dvc-1 {
	dmas = <&audma0 0xbe>;
	dma-names = "tx";
	};
	};

	rcar_sound,mix {
	mix0: mix-0 { };
	mix1: mix-1 { };
	};

	rcar_sound,ctu {
	ctu00: ctu-0 { };
	ctu01: ctu-1 { };
	ctu02: ctu-2 { };
	ctu03: ctu-3 { };
	ctu10: ctu-4 { };
	ctu11: ctu-5 { };
	ctu12: ctu-6 { };
	ctu13: ctu-7 { };
	};

	rcar_sound,src {
	src-0 {
	status = "disabled";
	};
	src1: src-1 {
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x87>, <&audma0 0x9c>;
	dma-names = "rx", "tx";
	};
	src2: src-2 {
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x89>, <&audma0 0x9e>;
	dma-names = "rx", "tx";
	};
	src3: src-3 {
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8b>, <&audma0 0xa0>;
	dma-names = "rx", "tx";
	};
	src4: src-4 {
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8d>, <&audma0 0xb0>;
	dma-names = "rx", "tx";
	};
	src5: src-5 {
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8f>, <&audma0 0xb2>;
	dma-names = "rx", "tx";
	};
	src6: src-6 {
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x91>, <&audma0 0xb4>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssi {
	ssi0: ssi-0 {
	interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x01>, <&audma0 0x02>,
	<&audma0 0x15>, <&audma0 0x16>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi1: ssi-1 {
	interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x03>, <&audma0 0x04>,
	<&audma0 0x49>, <&audma0 0x4a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi2: ssi-2 {
	interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x05>, <&audma0 0x06>,
	<&audma0 0x63>, <&audma0 0x64>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi3: ssi-3 {
	interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x07>, <&audma0 0x08>,
	<&audma0 0x6f>, <&audma0 0x70>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi4: ssi-4 {
	interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x09>, <&audma0 0x0a>,
	<&audma0 0x71>, <&audma0 0x72>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi5: ssi-5 {
	interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0b>, <&audma0 0x0c>,
	<&audma0 0x73>, <&audma0 0x74>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi6: ssi-6 {
	interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0d>, <&audma0 0x0e>,
	<&audma0 0x75>, <&audma0 0x76>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi7: ssi-7 {
	interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0f>, <&audma0 0x10>,
	<&audma0 0x79>, <&audma0 0x7a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi8: ssi-8 {
	interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x11>, <&audma0 0x12>,
	<&audma0 0x7b>, <&audma0 0x7c>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi9: ssi-9 {
	interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x13>, <&audma0 0x14>,
	<&audma0 0x7d>, <&audma0 0x7e>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	};
	};

	audma0: dma-controller@ec700000 {
	compatible = "renesas,dmac-r8a7794",
	"renesas,rcar-dmac";
	reg = <0 0xec700000 0 0x10000>;
	interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3", "ch4",
	"ch5", "ch6", "ch7", "ch8", "ch9",
	"ch10", "ch11",
	"ch12";
	clocks = <&cpg CPG_MOD 502>;
	clock-names = "fck";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 502>;
	#dma-cells = <1>;
	dma-channels = <13>;
	};

	pci0: pci@ee090000 {
	compatible = "renesas,pci-r8a7794",
	"renesas,pci-rcar-gen2";
	device_type = "pci";
	reg = <0 0xee090000 0 0xc00>,
	<0 0xee080000 0 0x1100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 703>;
	status = "disabled";

	bus-range = <0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
	interrupt-map-mask = <0xf800 0 0 0x7>;
	interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

	usb@1,0 {
	reg = <0x800 0 0 0 0>;
	phys = <&usb0 0>;
	phy-names = "usb";
	};

	usb@2,0 {
	reg = <0x1000 0 0 0 0>;
	phys = <&usb0 0>;
	phy-names = "usb";
	};
	};

	pci1: pci@ee0d0000 {
	compatible = "renesas,pci-r8a7794",
	"renesas,pci-rcar-gen2";
	device_type = "pci";
	reg = <0 0xee0d0000 0 0xc00>,
	<0 0xee0c0000 0 0x1100>;
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 703>;
	status = "disabled";

	bus-range = <1 1>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
	interrupt-map-mask = <0xf800 0 0 0x7>;
	interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

	usb@1,0 {
	reg = <0x10800 0 0 0 0>;
	phys = <&usb2 0>;
	phy-names = "usb";
	};

	usb@2,0 {
	reg = <0x11000 0 0 0 0>;
	phys = <&usb2 0>;
	phy-names = "usb";
	};
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a7794",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee100000 0 0x328>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
	<&dmac1 0xcd>, <&dmac1 0xce>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <195000000>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	status = "disabled";
	};

	sdhi1: sd@ee140000 {
	compatible = "renesas,sdhi-r8a7794",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee140000 0 0x100>;
	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 312>;
	dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
	<&dmac1 0xc1>, <&dmac1 0xc2>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <97500000>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 312>;
	status = "disabled";
	};

	sdhi2: sd@ee160000 {
	compatible = "renesas,sdhi-r8a7794",
	"renesas,rcar-gen2-sdhi";
	reg = <0 0xee160000 0 0x100>;
	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 311>;
	dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
	<&dmac1 0xd3>, <&dmac1 0xd4>;
	dma-names = "tx", "rx", "tx", "rx";
	max-frequency = <97500000>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 311>;
	status = "disabled";
	};

	mmcif0: mmc@ee200000 {
	compatible = "renesas,mmcif-r8a7794",
	"renesas,sh-mmcif";
	reg = <0 0xee200000 0 0x80>;
	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 315>;
	dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
	<&dmac1 0xd1>, <&dmac1 0xd2>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 315>;
	reg-io-width = <4>;
	status = "disabled";
	};

	ether: ethernet@ee700000 {
	compatible = "renesas,ether-r8a7794",
	"renesas,rcar-gen2-ether";
	reg = <0 0xee700000 0 0x400>;
	interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 813>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 813>;
	phy-mode = "rmii";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	gic: interrupt-controller@f1001000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0 0xf1001000 0 0x1000>,
	<0 0xf1002000 0 0x2000>,
	<0 0xf1004000 0 0x2000>,
	<0 0xf1006000 0 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	vsp@fe928000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe928000 0 0x8000>;
	interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 131>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 131>;
	};

	vsp@fe930000 {
	compatible = "renesas,vsp1";
	reg = <0 0xfe930000 0 0x8000>;
	interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 128>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 128>;
	};

	fdp1@fe940000 {
	compatible = "renesas,fdp1";
	reg = <0 0xfe940000 0 0x2400>;
	interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 119>;
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 119>;
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a7794";
	reg = <0 0xfeb00000 0 0x40000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
	clock-names = "du.0", "du.1";
	+ resets = <&cpg 724>;
	+ reset-names = "du.0";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb0: endpoint {
	};
	};
	port@1 {
	reg = <1>;
	du_out_rgb1: endpoint {
	};
	};
	};
	};

	prr: chipid@ff000044 {
	compatible = "renesas,prr";
	reg = <0 0xff000044 0 4>;
	};

	cmt0: timer@ffca0000 {
	compatible = "renesas,r8a7794-cmt0",
	"renesas,rcar-gen2-cmt0";
	reg = <0 0xffca0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 124>;
	clock-names = "fck";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 124>;

	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a7794-cmt1",
	"renesas,rcar-gen2-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 329>;
	clock-names = "fck";
	power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
	resets = <&cpg 329>;

	status = "disabled";
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clock - can be overridden by the board */
	usb_extal_clk: usb_extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <48000000>;
	};
	};
	diff --git a/sys/gnu/dts/arm/rk3036-kylin.dts b/sys/gnu/dts/arm/rk3036-kylin.dts
	index fb3cf005cc90..2ff9f152d29b 100644
	--- a/sys/gnu/dts/arm/rk3036-kylin.dts
	+++ b/sys/gnu/dts/arm/rk3036-kylin.dts
	@@ -1,398 +1,398 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

	/dts-v1/;

	#include "rk3036.dtsi"

	/ {
	model = "Rockchip RK3036 KylinBoard";
	compatible = "rockchip,rk3036-kylin", "rockchip,rk3036";

	memory@60000000 {
	device_type = "memory";
	reg = <0x60000000 0x20000000>;
	};

	leds: gpio-leds {
	compatible = "gpio-leds";

	work {
	gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
	label = "kylin:red:led";
	pinctrl-names = "default";
	pinctrl-0 = <&led_ctl>;
	};
	};

	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	pinctrl-names = "default";
	pinctrl-0 = <&bt_wake_h>;

	/*
	* On the module itself this is one of these (depending
	* on the actual card populated):
	* - SDIO_RESET_L_WL_REG_ON
	* - SDIO_RESET_L_WL_RST
	* - SDIO_RESET_L_BT_EN
	*/
	reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
	<&gpio0 RK_PD3 GPIO_ACTIVE_LOW>, /* WL_RST */
	<&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; /* BT_EN */
	};

	sound {
	compatible = "simple-audio-card";
	simple-audio-card,format = "i2s";
	simple-audio-card,name = "rockchip,rt5616-codec";
	simple-audio-card,mclk-fs = <512>;
	simple-audio-card,widgets =
	"Microphone", "Microphone Jack",
	"Headphone", "Headphone Jack";
	simple-audio-card,routing =
	"MIC1", "Microphone Jack",
	"MIC2", "Microphone Jack",
	"Microphone Jack", "micbias1",
	"Headphone Jack", "HPOL",
	"Headphone Jack", "HPOR";

	simple-audio-card,cpu {
	sound-dai = <&i2s>;
	};

	simple-audio-card,codec {
	sound-dai = <&rt5616>;
	};
	};

	vcc_sys: vsys-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vcc_sys";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	};
	};

	&acodec {
	status = "okay";
	};

	&emac {
	pinctrl-names = "default";
	pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
	phy = <&phy0>;
	phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
	phy-reset-duration = <10>; /* millisecond */

	status = "okay";

	phy0: ethernet-phy@0 {
	reg = <0>;
	};
	};

	&emmc {
	status = "okay";
	};

	&gpu {
	mali-supply = <&vdd_gpu>;
	status = "okay";
	};

	&hdmi {
	status = "okay";
	};

	&i2c1 {
	clock-frequency = <400000>;

	status = "okay";

	rk808: pmic@1b {
	compatible = "rockchip,rk808";
	reg = <0x1b>;
	interrupt-parent = <&gpio2>;
	interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int &global_pwroff>;
	rockchip,system-power-controller;
	wakeup-source;
	#clock-cells = <1>;
	clock-output-names = "xin32k", "rk808-clkout2";

	vcc1-supply = <&vcc_sys>;
	vcc2-supply = <&vcc_sys>;
	vcc3-supply = <&vcc_sys>;
	vcc4-supply = <&vcc_sys>;
	vcc6-supply = <&vcc_sys>;
	vcc7-supply = <&vcc_sys>;
	vcc8-supply = <&vcc_18>;
	vcc9-supply = <&vcc_io>;
	vcc10-supply = <&vcc_io>;
	vcc11-supply = <&vcc_sys>;
	vcc12-supply = <&vcc_io>;
	vddio-supply = <&vccio_pmu>;

	regulators {
	vdd_cpu: DCDC_REG1 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <1350000>;
	regulator-name = "vdd_arm";
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_gpu: DCDC_REG2 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1250000>;
	regulator-name = "vdd_gpu";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1000000>;
	};
	};

	vcc_ddr: DCDC_REG3 {
	regulator-always-on;
	regulator-boot-on;
	regulator-name = "vcc_ddr";
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	vcc_io: DCDC_REG4 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc_io";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3300000>;
	};
	};

	vccio_pmu: LDO_REG1 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vccio_pmu";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3300000>;
	};
	};

	vcc_tp: LDO_REG2 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc_tp";
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_10: LDO_REG3 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-name = "vdd_10";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1000000>;
	};
	};

	vcc18_lcd: LDO_REG4 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc18_lcd";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vccio_sd: LDO_REG5 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vccio_sd";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3300000>;
	};
	};

	vout5: LDO_REG6 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2500000>;
	regulator-name = "vout5";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc_18: LDO_REG7 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc_18";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcca_codec: LDO_REG8 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcca_codec";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc_wl: SWITCH_REG1 {
	regulator-always-on;
	regulator-boot-on;
	regulator-name = "vcc_wl";
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	vcc_lcd: SWITCH_REG2 {
	regulator-always-on;
	regulator-boot-on;
	regulator-name = "vcc_lcd";
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};
	};
	};
	};

	&i2c2 {
	status = "okay";

	rt5616: rt5616@1b {
	compatible = "rt5616";
	reg = <0x1b>;
	clocks = <&cru SCLK_I2S_OUT>;
	clock-names = "mclk";
	#sound-dai-cells = <0>;
	};
	};

	&i2s {
	status = "okay";
	};

	&sdio {
	status = "okay";

	bus-width = <4>;
	cap-sd-highspeed;
	cap-sdio-irq;
	- default-sample-phase = <90>;
	+ rockchip,default-sample-phase = <90>;
	keep-power-in-suspend;
	mmc-pwrseq = <&sdio_pwrseq>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	};

	&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	card-detect-delay = <200>;
	disable-wp;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
	};

	&uart0 {
	status = "okay";
	};

	&uart2 {
	status = "okay";
	};

	&usb_host {
	status = "okay";
	};

	&usb_otg {
	status = "okay";
	};

	&vop {
	status = "okay";
	};

	&vop_mmu {
	status = "okay";
	};

	&pinctrl {
	leds {
	led_ctl: led-ctl {
	rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	pmic {
	pmic_int: pmic-int {
	rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_default>;
	};
	};

	sdio {
	bt_wake_h: bt-wake-h {
	rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_default>;
	};
	};

	sdmmc {
	sdmmc_pwr: sdmmc-pwr {
	rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	sleep {
	global_pwroff: global-pwroff {
	rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/rk3036.dtsi b/sys/gnu/dts/arm/rk3036.dtsi
	index cf36e25195b4..d9a0c9a29b68 100644
	--- a/sys/gnu/dts/arm/rk3036.dtsi
	+++ b/sys/gnu/dts/arm/rk3036.dtsi
	@@ -1,761 +1,759 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/pinctrl/rockchip.h>
	#include <dt-bindings/clock/rk3036-cru.h>
	#include <dt-bindings/soc/rockchip,boot-mode.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;

	compatible = "rockchip,rk3036";

	interrupt-parent = <&gic>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	mshc0 = &emmc;
	mshc1 = &sdmmc;
	mshc2 = &sdio;
	serial0 = &uart0;
	serial1 = &uart1;
	serial2 = &uart2;
	spi = &spi;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "rockchip,rk3036-smp";

	cpu0: cpu@f00 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0xf00>;
	resets = <&cru SRST_CORE0>;
	operating-points = <
	/* KHz uV */
	816000 1000000
	>;
	clock-latency = <40000>;
	clocks = <&cru ARMCLK>;
	};

	cpu1: cpu@f01 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0xf01>;
	resets = <&cru SRST_CORE1>;
	};
	};

	- amba {
	+ amba: bus {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	pdma: pdma@20078000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x20078000 0x4000>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	arm,pl330-broken-no-flushp;
	clocks = <&cru ACLK_DMAC2>;
	clock-names = "apb_pclk";
	};
	};

	arm-pmu {
	compatible = "arm,cortex-a7-pmu";
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	display-subsystem {
	compatible = "rockchip,display-subsystem";
	ports = <&vop_out>;
	};

	timer {
	compatible = "arm,armv7-timer";
	arm,cpu-registers-not-fw-configured;
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	clock-frequency = <24000000>;
	};

	xin24m: oscillator {
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-output-names = "xin24m";
	#clock-cells = <0>;
	};

	- bus_intmem@10080000 {
	+ bus_intmem: sram@10080000 {
	compatible = "mmio-sram";
	reg = <0x10080000 0x2000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x10080000 0x2000>;

	smp-sram@0 {
	compatible = "rockchip,rk3066-smp-sram";
	reg = <0x00 0x10>;
	};
	};

	gpu: gpu@10090000 {
	compatible = "rockchip,rk3036-mali", "arm,mali-400";
	reg = <0x10090000 0x10000>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gp",
	"gpmmu",
	"pp0",
	"ppmmu0";
	assigned-clocks = <&cru SCLK_GPU>;
	assigned-clock-rates = <100000000>;
	clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
	- clock-names = "core", "bus";
	+ clock-names = "bus", "core";
	resets = <&cru SRST_GPU>;
	status = "disabled";
	};

	vop: vop@10118000 {
	compatible = "rockchip,rk3036-vop";
	reg = <0x10118000 0x19c>;
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
	reset-names = "axi", "ahb", "dclk";
	iommus = <&vop_mmu>;
	status = "disabled";

	vop_out: port {
	#address-cells = <1>;
	#size-cells = <0>;
	vop_out_hdmi: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&hdmi_in_vop>;
	};
	};
	};

	vop_mmu: iommu@10118300 {
	compatible = "rockchip,iommu";
	reg = <0x10118300 0x100>;
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "vop_mmu";
	clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	status = "disabled";
	};

	gic: interrupt-controller@10139000 {
	compatible = "arm,gic-400";
	interrupt-controller;
	#interrupt-cells = <3>;
	#address-cells = <0>;

	reg = <0x10139000 0x1000>,
	<0x1013a000 0x2000>,
	<0x1013c000 0x2000>,
	<0x1013e000 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	usb_otg: usb@10180000 {
	compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
	"snps,dwc2";
	reg = <0x10180000 0x40000>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_OTG0>;
	clock-names = "otg";
	dr_mode = "otg";
	g-np-tx-fifo-size = <16>;
	g-rx-fifo-size = <275>;
	g-tx-fifo-size = <256 128 128 64 64 32>;
	status = "disabled";
	};

	usb_host: usb@101c0000 {
	compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
	"snps,dwc2";
	reg = <0x101c0000 0x40000>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_OTG1>;
	clock-names = "otg";
	dr_mode = "host";
	status = "disabled";
	};

	emac: ethernet@10200000 {
	compatible = "rockchip,rk3036-emac", "snps,arc-emac";
	reg = <0x10200000 0x4000>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	rockchip,grf = <&grf>;
	clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
	clock-names = "hclk", "macref", "macclk";
	/*
	* Fix the emac parent clock is DPLL instead of APLL.
	* since that will cause some unstable things if the cpufreq
	* is working. (e.g: the accurate 50MHz what mac_ref need)
	*/
	assigned-clocks = <&cru SCLK_MACPLL>;
	assigned-clock-parents = <&cru PLL_DPLL>;
	max-speed = <100>;
	phy-mode = "rmii";
	status = "disabled";
	};

	sdmmc: mmc@10214000 {
	compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x10214000 0x4000>;
	clock-frequency = <37500000>;
	max-frequency = <37500000>;
	clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
	clock-names = "biu", "ciu";
	fifo-depth = <0x100>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&cru SRST_MMC0>;
	reset-names = "reset";
	status = "disabled";
	};

	sdio: mmc@10218000 {
	compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x10218000 0x4000>;
	max-frequency = <37500000>;
	clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
	<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&cru SRST_SDIO>;
	reset-names = "reset";
	status = "disabled";
	};

	emmc: mmc@1021c000 {
	compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x1021c000 0x4000>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	bus-width = <8>;
	cap-mmc-highspeed;
	clock-frequency = <37500000>;
	max-frequency = <37500000>;
	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
	<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	- default-sample-phase = <158>;
	+ rockchip,default-sample-phase = <158>;
	disable-wp;
	dmas = <&pdma 12>;
	dma-names = "rx-tx";
	fifo-depth = <0x100>;
	mmc-ddr-1_8v;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
	resets = <&cru SRST_EMMC>;
	reset-names = "reset";
	status = "disabled";
	};

	i2s: i2s@10220000 {
	compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
	reg = <0x10220000 0x4000>;
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	- #address-cells = <1>;
	- #size-cells = <0>;
	clock-names = "i2s_clk", "i2s_hclk";
	clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
	dmas = <&pdma 0>, <&pdma 1>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&i2s_bus>;
	#sound-dai-cells = <0>;
	status = "disabled";
	};

	cru: clock-controller@20000000 {
	compatible = "rockchip,rk3036-cru";
	reg = <0x20000000 0x1000>;
	rockchip,grf = <&grf>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	assigned-clocks = <&cru PLL_GPLL>;
	assigned-clock-rates = <594000000>;
	};

	grf: syscon@20008000 {
	compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
	reg = <0x20008000 0x1000>;

	reboot-mode {
	compatible = "syscon-reboot-mode";
	offset = <0x1d8>;
	mode-normal = <BOOT_NORMAL>;
	mode-recovery = <BOOT_RECOVERY>;
	mode-bootloader = <BOOT_FASTBOOT>;
	mode-loader = <BOOT_BL_DOWNLOAD>;
	};
	};

	acodec: acodec-ana@20030000 {
	compatible = "rk3036-codec";
	reg = <0x20030000 0x4000>;
	rockchip,grf = <&grf>;
	clock-names = "acodec_pclk";
	clocks = <&cru PCLK_ACODEC>;
	status = "disabled";
	};

	hdmi: hdmi@20034000 {
	compatible = "rockchip,rk3036-inno-hdmi";
	reg = <0x20034000 0x4000>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_HDMI>;
	clock-names = "pclk";
	rockchip,grf = <&grf>;
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_ctl>;
	status = "disabled";

	hdmi_in: port {
	#address-cells = <1>;
	#size-cells = <0>;
	hdmi_in_vop: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vop_out_hdmi>;
	};
	};
	};

	timer: timer@20044000 {
	compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
	reg = <0x20044000 0x20>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&xin24m>, <&cru PCLK_TIMER>;
	clock-names = "timer", "pclk";
	};

	pwm0: pwm@20050000 {
	compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
	reg = <0x20050000 0x10>;
	#pwm-cells = <3>;
	clocks = <&cru PCLK_PWM>;
	clock-names = "pwm";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_pin>;
	status = "disabled";
	};

	pwm1: pwm@20050010 {
	compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
	reg = <0x20050010 0x10>;
	#pwm-cells = <3>;
	clocks = <&cru PCLK_PWM>;
	clock-names = "pwm";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_pin>;
	status = "disabled";
	};

	pwm2: pwm@20050020 {
	compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
	reg = <0x20050020 0x10>;
	#pwm-cells = <3>;
	clocks = <&cru PCLK_PWM>;
	clock-names = "pwm";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_pin>;
	status = "disabled";
	};

	pwm3: pwm@20050030 {
	compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
	reg = <0x20050030 0x10>;
	#pwm-cells = <2>;
	clocks = <&cru PCLK_PWM>;
	clock-names = "pwm";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_pin>;
	status = "disabled";
	};

	i2c1: i2c@20056000 {
	compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
	reg = <0x20056000 0x1000>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C1>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
	status = "disabled";
	};

	i2c2: i2c@2005a000 {
	compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
	reg = <0x2005a000 0x1000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C2>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
	status = "disabled";
	};

	uart0: serial@20060000 {
	compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
	reg = <0x20060000 0x100>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clock-frequency = <24000000>;
	clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
	clock-names = "baudclk", "apb_pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
	status = "disabled";
	};

	uart1: serial@20064000 {
	compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
	reg = <0x20064000 0x100>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clock-frequency = <24000000>;
	clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
	clock-names = "baudclk", "apb_pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer>;
	status = "disabled";
	};

	uart2: serial@20068000 {
	compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
	reg = <0x20068000 0x100>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clock-frequency = <24000000>;
	clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
	clock-names = "baudclk", "apb_pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_xfer>;
	status = "disabled";
	};

	i2c0: i2c@20072000 {
	compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
	reg = <0x20072000 0x1000>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
	status = "disabled";
	};

	spi: spi@20074000 {
	compatible = "rockchip,rockchip-spi";
	reg = <0x20074000 0x1000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
	clock-names = "apb-pclk","spi_pclk";
	dmas = <&pdma 8>, <&pdma 9>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	pinctrl: pinctrl {
	compatible = "rockchip,rk3036-pinctrl";
	rockchip,grf = <&grf>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	gpio0: gpio0@2007c000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x2007c000 0x100>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO0>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio1: gpio1@20080000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x20080000 0x100>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO1>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio2@20084000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x20084000 0x100>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO2>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	pcfg_pull_default: pcfg_pull_default {
	bias-pull-pin-default;
	};

	pcfg_pull_none: pcfg-pull-none {
	bias-disable;
	};

	pwm0 {
	pwm0_pin: pwm0-pin {
	rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
	};
	};

	pwm1 {
	pwm1_pin: pwm1-pin {
	rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
	};
	};

	pwm2 {
	pwm2_pin: pwm2-pin {
	rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
	};
	};

	pwm3 {
	pwm3_pin: pwm3-pin {
	rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
	};
	};

	sdmmc {
	sdmmc_clk: sdmmc-clk {
	rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
	};

	sdmmc_cmd: sdmmc-cmd {
	rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
	};

	sdmmc_cd: sdmmc-cd {
	rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
	};

	sdmmc_bus1: sdmmc-bus1 {
	rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
	};

	sdmmc_bus4: sdmmc-bus4 {
	rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
	<1 RK_PC3 1 &pcfg_pull_default>,
	<1 RK_PC4 1 &pcfg_pull_default>,
	<1 RK_PC5 1 &pcfg_pull_default>;
	};
	};

	sdio {
	sdio_bus1: sdio-bus1 {
	rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
	};

	sdio_bus4: sdio-bus4 {
	rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
	<0 RK_PB4 1 &pcfg_pull_default>,
	<0 RK_PB5 1 &pcfg_pull_default>,
	<0 RK_PB6 1 &pcfg_pull_default>;
	};

	sdio_cmd: sdio-cmd {
	rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
	};

	sdio_clk: sdio-clk {
	rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
	};
	};

	emmc {
	/*
	* We run eMMC at max speed; bump up drive strength.
	* We also have external pulls, so disable the internal ones.
	*/
	emmc_clk: emmc-clk {
	rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
	};

	emmc_cmd: emmc-cmd {
	rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
	};

	emmc_bus8: emmc-bus8 {
	rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
	<1 RK_PD1 2 &pcfg_pull_default>,
	<1 RK_PD2 2 &pcfg_pull_default>,
	<1 RK_PD3 2 &pcfg_pull_default>,
	<1 RK_PD4 2 &pcfg_pull_default>,
	<1 RK_PD5 2 &pcfg_pull_default>,
	<1 RK_PD6 2 &pcfg_pull_default>,
	<1 RK_PD7 2 &pcfg_pull_default>;
	};
	};

	emac {
	emac_xfer: emac-xfer {
	rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
	<2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
	<2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
	<2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
	<2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
	<2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
	<2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
	<2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
	};

	emac_mdio: emac-mdio {
	rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
	<2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
	};
	};

	i2c0 {
	i2c0_xfer: i2c0-xfer {
	rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
	<0 RK_PA1 1 &pcfg_pull_none>;
	};
	};

	i2c1 {
	i2c1_xfer: i2c1-xfer {
	rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
	<0 RK_PA3 1 &pcfg_pull_none>;
	};
	};

	i2c2 {
	i2c2_xfer: i2c2-xfer {
	rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
	<2 RK_PC5 1 &pcfg_pull_none>;
	};
	};

	i2s {
	i2s_bus: i2s-bus {
	rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
	<1 RK_PA1 1 &pcfg_pull_default>,
	<1 RK_PA2 1 &pcfg_pull_default>,
	<1 RK_PA3 1 &pcfg_pull_default>,
	<1 RK_PA4 1 &pcfg_pull_default>,
	<1 RK_PA5 1 &pcfg_pull_default>;
	};
	};

	hdmi {
	hdmi_ctl: hdmi-ctl {
	rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
	<1 RK_PB1 1 &pcfg_pull_none>,
	<1 RK_PB2 1 &pcfg_pull_none>,
	<1 RK_PB3 1 &pcfg_pull_none>;
	};
	};

	uart0 {
	uart0_xfer: uart0-xfer {
	rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
	<0 RK_PC1 1 &pcfg_pull_none>;
	};

	uart0_cts: uart0-cts {
	rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
	};

	uart0_rts: uart0-rts {
	rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
	};
	};

	uart1 {
	uart1_xfer: uart1-xfer {
	rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
	<2 RK_PC7 1 &pcfg_pull_none>;
	};
	/* no rts / cts for uart1 */
	};

	uart2 {
	uart2_xfer: uart2-xfer {
	rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
	<1 RK_PC3 2 &pcfg_pull_none>;
	};
	/* no rts / cts for uart2 */
	};

	spi-pins {
	spi_txd:spi-txd {
	rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
	};

	spi_rxd:spi-rxd {
	rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
	};

	spi_clk:spi-clk {
	rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
	};

	spi_cs0:spi-cs0 {
	rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;

	};

	spi_cs1:spi-cs1 {
	rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;

	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/rk3066a.dtsi b/sys/gnu/dts/arm/rk3066a.dtsi
	index 3d1b02f45ffd..b599394d149d 100644
	--- a/sys/gnu/dts/arm/rk3066a.dtsi
	+++ b/sys/gnu/dts/arm/rk3066a.dtsi
	@@ -1,876 +1,870 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2013 MundoReader S.L.
	* Author: Heiko Stuebner <heiko@sntech.de>
	*/

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/pinctrl/rockchip.h>
	#include <dt-bindings/clock/rk3066a-cru.h>
	#include <dt-bindings/power/rk3066-power.h>
	#include "rk3xxx.dtsi"

	/ {
	compatible = "rockchip,rk3066a";

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "rockchip,rk3066-smp";

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	next-level-cache = <&L2>;
	reg = <0x0>;
	operating-points = <
	/* kHz uV */
	1416000 1300000
	1200000 1175000
	1008000 1125000
	816000 1125000
	600000 1100000
	504000 1100000
	312000 1075000
	>;
	clock-latency = <40000>;
	clocks = <&cru ARMCLK>;
	};
	cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	next-level-cache = <&L2>;
	reg = <0x1>;
	};
	};

	display-subsystem {
	compatible = "rockchip,display-subsystem";
	ports = <&vop0_out>, <&vop1_out>;
	};

	sram: sram@10080000 {
	compatible = "mmio-sram";
	reg = <0x10080000 0x10000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x10080000 0x10000>;

	smp-sram@0 {
	compatible = "rockchip,rk3066-smp-sram";
	reg = <0x0 0x50>;
	};
	};

	vop0: vop@1010c000 {
	compatible = "rockchip,rk3066-vop";
	reg = <0x1010c000 0x19c>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru ACLK_LCDC0>,
	<&cru DCLK_LCDC0>,
	<&cru HCLK_LCDC0>;
	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	power-domains = <&power RK3066_PD_VIO>;
	resets = <&cru SRST_LCDC0_AXI>,
	<&cru SRST_LCDC0_AHB>,
	<&cru SRST_LCDC0_DCLK>;
	reset-names = "axi", "ahb", "dclk";
	status = "disabled";

	vop0_out: port {
	#address-cells = <1>;
	#size-cells = <0>;

	vop0_out_hdmi: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&hdmi_in_vop0>;
	};
	};
	};

	vop1: vop@1010e000 {
	compatible = "rockchip,rk3066-vop";
	reg = <0x1010e000 0x19c>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru ACLK_LCDC1>,
	<&cru DCLK_LCDC1>,
	<&cru HCLK_LCDC1>;
	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	power-domains = <&power RK3066_PD_VIO>;
	resets = <&cru SRST_LCDC1_AXI>,
	<&cru SRST_LCDC1_AHB>,
	<&cru SRST_LCDC1_DCLK>;
	reset-names = "axi", "ahb", "dclk";
	status = "disabled";

	vop1_out: port {
	#address-cells = <1>;
	#size-cells = <0>;

	vop1_out_hdmi: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&hdmi_in_vop1>;
	};
	};
	};

	hdmi: hdmi@10116000 {
	compatible = "rockchip,rk3066-hdmi";
	reg = <0x10116000 0x2000>;
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_HDMI>;
	clock-names = "hclk";
	pinctrl-names = "default";
	pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
	power-domains = <&power RK3066_PD_VIO>;
	rockchip,grf = <&grf>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	hdmi_in: port@0 {
	reg = <0>;
	#address-cells = <1>;
	#size-cells = <0>;

	hdmi_in_vop0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vop0_out_hdmi>;
	};

	hdmi_in_vop1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vop1_out_hdmi>;
	};
	};

	hdmi_out: port@1 {
	reg = <1>;
	};
	};
	};

	i2s0: i2s@10118000 {
	compatible = "rockchip,rk3066-i2s";
	reg = <0x10118000 0x2000>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	- #address-cells = <1>;
	- #size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2s0_bus>;
	+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
	+ clock-names = "i2s_clk", "i2s_hclk";
	dmas = <&dmac1_s 4>, <&dmac1_s 5>;
	dma-names = "tx", "rx";
	- clock-names = "i2s_hclk", "i2s_clk";
	- clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
	rockchip,playback-channels = <8>;
	rockchip,capture-channels = <2>;
	#sound-dai-cells = <0>;
	status = "disabled";
	};

	i2s1: i2s@1011a000 {
	compatible = "rockchip,rk3066-i2s";
	reg = <0x1011a000 0x2000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	- #address-cells = <1>;
	- #size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2s1_bus>;
	+ clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
	+ clock-names = "i2s_clk", "i2s_hclk";
	dmas = <&dmac1_s 6>, <&dmac1_s 7>;
	dma-names = "tx", "rx";
	- clock-names = "i2s_hclk", "i2s_clk";
	- clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
	rockchip,playback-channels = <2>;
	rockchip,capture-channels = <2>;
	#sound-dai-cells = <0>;
	status = "disabled";
	};

	i2s2: i2s@1011c000 {
	compatible = "rockchip,rk3066-i2s";
	reg = <0x1011c000 0x2000>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	- #address-cells = <1>;
	- #size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2s2_bus>;
	+ clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
	+ clock-names = "i2s_clk", "i2s_hclk";
	dmas = <&dmac1_s 9>, <&dmac1_s 10>;
	dma-names = "tx", "rx";
	- clock-names = "i2s_hclk", "i2s_clk";
	- clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
	rockchip,playback-channels = <2>;
	rockchip,capture-channels = <2>;
	#sound-dai-cells = <0>;
	status = "disabled";
	};

	cru: clock-controller@20000000 {
	compatible = "rockchip,rk3066a-cru";
	reg = <0x20000000 0x1000>;
	rockchip,grf = <&grf>;

	#clock-cells = <1>;
	#reset-cells = <1>;
	assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
	<&cru ACLK_CPU>, <&cru HCLK_CPU>,
	<&cru PCLK_CPU>, <&cru ACLK_PERI>,
	<&cru HCLK_PERI>, <&cru PCLK_PERI>;
	assigned-clock-rates = <400000000>, <594000000>,
	<300000000>, <150000000>,
	<75000000>, <300000000>,
	<150000000>, <75000000>;
	};

	timer@2000e000 {
	compatible = "snps,dw-apb-timer-osc";
	reg = <0x2000e000 0x100>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
	clock-names = "timer", "pclk";
	};

	efuse: efuse@20010000 {
	compatible = "rockchip,rk3066a-efuse";
	reg = <0x20010000 0x4000>;
	#address-cells = <1>;
	#size-cells = <1>;
	clocks = <&cru PCLK_EFUSE>;
	clock-names = "pclk_efuse";

	cpu_leakage: cpu_leakage@17 {
	reg = <0x17 0x1>;
	};
	};

	timer@20038000 {
	compatible = "snps,dw-apb-timer-osc";
	reg = <0x20038000 0x100>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
	clock-names = "timer", "pclk";
	};

	timer@2003a000 {
	compatible = "snps,dw-apb-timer-osc";
	reg = <0x2003a000 0x100>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
	clock-names = "timer", "pclk";
	};

	tsadc: tsadc@20060000 {
	compatible = "rockchip,rk3066-tsadc";
	reg = <0x20060000 0x100>;
	clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
	clock-names = "saradc", "apb_pclk";
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	#io-channel-cells = <1>;
	resets = <&cru SRST_TSADC>;
	reset-names = "saradc-apb";
	status = "disabled";
	};

	usbphy: phy {
	compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
	rockchip,grf = <&grf>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";

	usbphy0: usb-phy@17c {
	#phy-cells = <0>;
	reg = <0x17c>;
	clocks = <&cru SCLK_OTGPHY0>;
	clock-names = "phyclk";
	#clock-cells = <0>;
	};

	usbphy1: usb-phy@188 {
	#phy-cells = <0>;
	reg = <0x188>;
	clocks = <&cru SCLK_OTGPHY1>;
	clock-names = "phyclk";
	#clock-cells = <0>;
	};
	};

	pinctrl: pinctrl {
	compatible = "rockchip,rk3066a-pinctrl";
	rockchip,grf = <&grf>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	gpio0: gpio0@20034000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x20034000 0x100>;
	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO0>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio1: gpio1@2003c000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x2003c000 0x100>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO1>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio2@2003e000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x2003e000 0x100>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO2>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio3@20080000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x20080000 0x100>;
	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO3>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio4: gpio4@20084000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x20084000 0x100>;
	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO4>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio6: gpio6@2000a000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x2000a000 0x100>;
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO6>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	pcfg_pull_default: pcfg_pull_default {
	bias-pull-pin-default;
	};

	pcfg_pull_none: pcfg_pull_none {
	bias-disable;
	};

	emac {
	emac_xfer: emac-xfer {
	rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */
	<1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */
	<1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */
	<1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */
	<1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */
	<1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */
	<1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */
	<1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */
	};

	emac_mdio: emac-mdio {
	rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */
	<1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */
	};
	};

	emmc {
	emmc_clk: emmc-clk {
	rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>;
	};

	emmc_cmd: emmc-cmd {
	rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>;
	};

	emmc_rst: emmc-rst {
	rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>;
	};

	/*
	* The data pins are shared between nandc and emmc and
	* not accessible through pinctrl. Also they should've
	* been already set correctly by firmware, as
	* flash/emmc is the boot-device.
	*/
	};

	hdmi {
	hdmi_hpd: hdmi-hpd {
	rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
	};

	hdmii2c_xfer: hdmii2c-xfer {
	rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
	<0 RK_PA2 1 &pcfg_pull_none>;
	};
	};

	i2c0 {
	i2c0_xfer: i2c0-xfer {
	rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>,
	<2 RK_PD5 1 &pcfg_pull_none>;
	};
	};

	i2c1 {
	i2c1_xfer: i2c1-xfer {
	rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>,
	<2 RK_PD7 1 &pcfg_pull_none>;
	};
	};

	i2c2 {
	i2c2_xfer: i2c2-xfer {
	rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>,
	<3 RK_PA1 1 &pcfg_pull_none>;
	};
	};

	i2c3 {
	i2c3_xfer: i2c3-xfer {
	rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>,
	<3 RK_PA3 2 &pcfg_pull_none>;
	};
	};

	i2c4 {
	i2c4_xfer: i2c4-xfer {
	rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
	<3 RK_PA5 1 &pcfg_pull_none>;
	};
	};

	pwm0 {
	pwm0_out: pwm0-out {
	rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
	};
	};

	pwm1 {
	pwm1_out: pwm1-out {
	rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
	};
	};

	pwm2 {
	pwm2_out: pwm2-out {
	rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
	};
	};

	pwm3 {
	pwm3_out: pwm3-out {
	rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
	};
	};

	spi0 {
	spi0_clk: spi0-clk {
	rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>;
	};
	spi0_cs0: spi0-cs0 {
	rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>;
	};
	spi0_tx: spi0-tx {
	rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>;
	};
	spi0_rx: spi0-rx {
	rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>;
	};
	spi0_cs1: spi0-cs1 {
	rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>;
	};
	};

	spi1 {
	spi1_clk: spi1-clk {
	rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>;
	};
	spi1_cs0: spi1-cs0 {
	rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>;
	};
	spi1_rx: spi1-rx {
	rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>;
	};
	spi1_tx: spi1-tx {
	rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>;
	};
	spi1_cs1: spi1-cs1 {
	rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>;
	};
	};

	uart0 {
	uart0_xfer: uart0-xfer {
	rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
	<1 RK_PA1 1 &pcfg_pull_default>;
	};

	uart0_cts: uart0-cts {
	rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>;
	};

	uart0_rts: uart0-rts {
	rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>;
	};
	};

	uart1 {
	uart1_xfer: uart1-xfer {
	rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>,
	<1 RK_PA5 1 &pcfg_pull_default>;
	};

	uart1_cts: uart1-cts {
	rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>;
	};

	uart1_rts: uart1-rts {
	rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
	};
	};

	uart2 {
	uart2_xfer: uart2-xfer {
	rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
	<1 RK_PB1 1 &pcfg_pull_default>;
	};
	/* no rts / cts for uart2 */
	};

	uart3 {
	uart3_xfer: uart3-xfer {
	rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>,
	<3 RK_PD4 1 &pcfg_pull_default>;
	};

	uart3_cts: uart3-cts {
	rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>;
	};

	uart3_rts: uart3-rts {
	rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>;
	};
	};

	sd0 {
	sd0_clk: sd0-clk {
	rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>;
	};

	sd0_cmd: sd0-cmd {
	rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>;
	};

	sd0_cd: sd0-cd {
	rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>;
	};

	sd0_wp: sd0-wp {
	rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>;
	};

	sd0_bus1: sd0-bus-width1 {
	rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>;
	};

	sd0_bus4: sd0-bus-width4 {
	rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>,
	<3 RK_PB3 1 &pcfg_pull_default>,
	<3 RK_PB4 1 &pcfg_pull_default>,
	<3 RK_PB5 1 &pcfg_pull_default>;
	};
	};

	sd1 {
	sd1_clk: sd1-clk {
	rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>;
	};

	sd1_cmd: sd1-cmd {
	rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>;
	};

	sd1_cd: sd1-cd {
	rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>;
	};

	sd1_wp: sd1-wp {
	rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>;
	};

	sd1_bus1: sd1-bus-width1 {
	rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>;
	};

	sd1_bus4: sd1-bus-width4 {
	rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>,
	<3 RK_PC2 1 &pcfg_pull_default>,
	<3 RK_PC3 1 &pcfg_pull_default>,
	<3 RK_PC4 1 &pcfg_pull_default>;
	};
	};

	i2s0 {
	i2s0_bus: i2s0-bus {
	rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>,
	<0 RK_PB0 1 &pcfg_pull_default>,
	<0 RK_PB1 1 &pcfg_pull_default>,
	<0 RK_PB2 1 &pcfg_pull_default>,
	<0 RK_PB3 1 &pcfg_pull_default>,
	<0 RK_PB4 1 &pcfg_pull_default>,
	<0 RK_PB5 1 &pcfg_pull_default>,
	<0 RK_PB6 1 &pcfg_pull_default>,
	<0 RK_PB7 1 &pcfg_pull_default>;
	};
	};

	i2s1 {
	i2s1_bus: i2s1-bus {
	rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
	<0 RK_PC1 1 &pcfg_pull_default>,
	<0 RK_PC2 1 &pcfg_pull_default>,
	<0 RK_PC3 1 &pcfg_pull_default>,
	<0 RK_PC4 1 &pcfg_pull_default>,
	<0 RK_PC5 1 &pcfg_pull_default>;
	};
	};

	i2s2 {
	i2s2_bus: i2s2-bus {
	rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>,
	<0 RK_PD1 1 &pcfg_pull_default>,
	<0 RK_PD2 1 &pcfg_pull_default>,
	<0 RK_PD3 1 &pcfg_pull_default>,
	<0 RK_PD4 1 &pcfg_pull_default>,
	<0 RK_PD5 1 &pcfg_pull_default>;
	};
	};
	};
	};

	&gpu {
	compatible = "rockchip,rk3066-mali", "arm,mali-400";
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gp",
	"gpmmu",
	"pp0",
	"ppmmu0",
	"pp1",
	"ppmmu1",
	"pp2",
	"ppmmu2",
	"pp3",
	"ppmmu3";
	power-domains = <&power RK3066_PD_GPU>;
	};

	&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
	};

	&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
	};

	&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
	};

	&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
	};

	&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_xfer>;
	};

	&mmc0 {
	clock-frequency = <50000000>;
	dmas = <&dmac2 1>;
	dma-names = "rx-tx";
	max-frequency = <50000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
	};

	&mmc1 {
	dmas = <&dmac2 3>;
	dma-names = "rx-tx";
	pinctrl-names = "default";
	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
	};

	&emmc {
	dmas = <&dmac2 4>;
	dma-names = "rx-tx";
	};

	&pmu {
	power: power-controller {
	compatible = "rockchip,rk3066-power-controller";
	#power-domain-cells = <1>;
	#address-cells = <1>;
	#size-cells = <0>;

	pd_vio@RK3066_PD_VIO {
	reg = <RK3066_PD_VIO>;
	clocks = <&cru ACLK_LCDC0>,
	<&cru ACLK_LCDC1>,
	<&cru DCLK_LCDC0>,
	<&cru DCLK_LCDC1>,
	<&cru HCLK_LCDC0>,
	<&cru HCLK_LCDC1>,
	<&cru SCLK_CIF1>,
	<&cru ACLK_CIF1>,
	<&cru HCLK_CIF1>,
	<&cru SCLK_CIF0>,
	<&cru ACLK_CIF0>,
	<&cru HCLK_CIF0>,
	<&cru HCLK_HDMI>,
	<&cru ACLK_IPP>,
	<&cru HCLK_IPP>,
	<&cru ACLK_RGA>,
	<&cru HCLK_RGA>;
	pm_qos = <&qos_lcdc0>,
	<&qos_lcdc1>,
	<&qos_cif0>,
	<&qos_cif1>,
	<&qos_ipp>,
	<&qos_rga>;
	};

	pd_video@RK3066_PD_VIDEO {
	reg = <RK3066_PD_VIDEO>;
	clocks = <&cru ACLK_VDPU>,
	<&cru ACLK_VEPU>,
	<&cru HCLK_VDPU>,
	<&cru HCLK_VEPU>;
	pm_qos = <&qos_vpu>;
	};

	pd_gpu@RK3066_PD_GPU {
	reg = <RK3066_PD_GPU>;
	clocks = <&cru ACLK_GPU>;
	pm_qos = <&qos_gpu>;
	};
	};
	};

	&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_out>;
	};

	&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_out>;
	};

	&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_out>;
	};

	&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_out>;
	};

	&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
	};

	&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
	};

	&uart0 {
	compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
	dmas = <&dmac1_s 0>, <&dmac1_s 1>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer>;
	};

	&uart1 {
	compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
	dmas = <&dmac1_s 2>, <&dmac1_s 3>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer>;
	};

	&uart2 {
	compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
	dmas = <&dmac2 6>, <&dmac2 7>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_xfer>;
	};

	&uart3 {
	compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
	dmas = <&dmac2 8>, <&dmac2 9>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_xfer>;
	};

	&wdt {
	compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
	};

	&emac {
	compatible = "rockchip,rk3066-emac";
	};
	diff --git a/sys/gnu/dts/arm/rk3188-bqedison2qc.dts b/sys/gnu/dts/arm/rk3188-bqedison2qc.dts
	index ad1afd403052..66a0ff196eb1 100644
	--- a/sys/gnu/dts/arm/rk3188-bqedison2qc.dts
	+++ b/sys/gnu/dts/arm/rk3188-bqedison2qc.dts
	@@ -1,727 +1,732 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2018 MundoReader S.L.
	* Author: Heiko Stuebner <heiko.stuebner@bq.com>
	*/

	/dts-v1/;
	#include <dt-bindings/i2c/i2c.h>
	#include <dt-bindings/input/input.h>
	#include "rk3188.dtsi"

	/ {
	model = "BQ Edison2 Quad-Core";
	compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188";

	memory@60000000 {
	device_type = "memory";
	reg = <0x60000000 0x80000000>;
	};

	backlight: backlight {
	compatible = "pwm-backlight";
	power-supply = <&vsys>;
	pwms = <&pwm1 0 25000>;
	};

	gpio-keys {
	compatible = "gpio-keys";
	autorepeat;
	pinctrl-names = "default";
	pinctrl-0 = <&pwr_key &usb_int>;

	power {
	gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_POWER>;
	label = "GPIO Key Power";
	linux,input-type = <1>;
	debounce-interval = <100>;
	wakeup-source;
	};

	wake_on_usb: wake-on-usb {
	label = "Wake-on-USB";
	gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_WAKEUP>;
	wakeup-source;
	};
	};

	gpio-poweroff {
	compatible = "gpio-poweroff";
	gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pwr_hold>;
	/* only drive the pin low until device is off */
	active-delay-ms = <3000>;
	};

	lvds-encoder {
	compatible = "ti,sn75lvds83", "lvds-encoder";
	- #address-cells = <1>;
	- #size-cells = <0>;

	- port@0 {
	- reg = <0>;
	- lvds_in_vop0: endpoint {
	- remote-endpoint = <&vop0_out_lvds>;
	+ ports {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ port@0 {
	+ reg = <0>;
	+
	+ lvds_in_vop0: endpoint {
	+ remote-endpoint = <&vop0_out_lvds>;
	+ };
	};
	- };

	- port@1 {
	- reg = <1>;
	- lvds_out_panel: endpoint {
	- remote-endpoint = <&panel_in_lvds>;
	+ port@1 {
	+ reg = <1>;
	+
	+ lvds_out_panel: endpoint {
	+ remote-endpoint = <&panel_in_lvds>;
	+ };
	};
	};
	};

	panel {
	compatible = "innolux,ee101ia-01d", "panel-lvds";
	backlight = <&backlight>;

	/* pin LCD_CS, Nshtdn input of lvds-encoder */
	enable-gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&lcd_cs>;
	power-supply = <&vcc_lcd>;

	data-mapping = "vesa-24";
	height-mm = <163>;
	width-mm = <261>;

	panel-timing {
	clock-frequency = <72000000>;
	hactive = <1280>;
	vactive = <800>;
	hback-porch = <160>;
	hfront-porch = <16>;
	hsync-len = <10>;
	vback-porch = <23>;
	vfront-porch = <12>;
	vsync-len = <3>;
	};

	port {
	panel_in_lvds: endpoint {
	remote-endpoint = <&lvds_out_panel>;
	};
	};
	};

	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	clocks = <&hym8563>;
	clock-names = "ext_clock";
	pinctrl-names = "default";
	pinctrl-0 = <&wifi_reg_on>;
	reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>;
	};

	avdd_cif: cif-avdd-regulator {
	compatible = "regulator-fixed";
	regulator-name = "avdd-cif";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&cif_avdd_en>;
	startup-delay-us = <100000>;
	vin-supply = <&vcc28_cif>;
	};

	vcc_5v: vcc-5v-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vcc-5v";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	enable-active-high;
	gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&v5_drv>;
	vin-supply = <&vsys>;
	};

	vcc_lcd: lcd-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vcc-lcd";
	gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&lcd_en>;
	startup-delay-us = <50000>;
	vin-supply = <&vcc_io>;
	};

	vcc_otg: usb-otg-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vcc-otg";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	enable-active-high;
	gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&otg_drv>;
	startup-delay-us = <100000>;
	vin-supply = <&vcc_5v>;
	};

	vcc_sd: sdmmc-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vcc-sd";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_pwr>;
	startup-delay-us = <100000>;
	vin-supply = <&vcc_io>;
	};

	vccq_emmc: emmc-vccq-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vccq-emmc";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	vin-supply = <&vcc_io>;
	};

	/* supplied from the bq24196 */
	vsys: vsys-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vsys";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-boot-on;
	};
	};

	&cpu0 {
	cpu-supply = <&vdd_arm>;
	};

	&cpu1 {
	cpu-supply = <&vdd_arm>;
	};

	&cpu2 {
	cpu-supply = <&vdd_arm>;
	};

	&cpu3 {
	cpu-supply = <&vdd_arm>;
	};

	&cru {
	assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
	<&cru ACLK_CPU>,
	<&cru HCLK_CPU>, <&cru PCLK_CPU>,
	<&cru ACLK_PERI>, <&cru HCLK_PERI>,
	<&cru PCLK_PERI>;
	assigned-clock-rates = <594000000>, <504000000>,
	<300000000>,
	<150000000>, <75000000>,
	<300000000>, <150000000>,
	<75000000>;
	};

	&emmc {
	bus-width = <8>;
	cap-mmc-highspeed;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_clk &emmc_cmd>;
	vmmc-supply = <&vcc_io>;
	vqmmc-supply = <&vccq_emmc>;
	status = "okay";
	};

	&gpu {
	status = "okay";
	};

	&i2c0 {
	clock-frequency = <400000>;
	status = "okay";

	lis3de: accelerometer@29 {
	compatible = "st,lis3de";
	reg = <0x29>;
	interrupt-parent = <&gpio0>;
	interrupts = <RK_PB7 IRQ_TYPE_EDGE_RISING>;
	pinctrl-names = "default";
	pinctrl-0 = <&gsensor_int>;
	rotation-matrix = "1", "0", "0",
	"0", "-1", "0",
	"0", "0", "1";
	vdd-supply = <&vcc_io>;
	};
	};

	&i2c1 {
	clock-frequency = <400000>;
	status = "okay";

	tmp108@48 {
	compatible = "ti,tmp108";
	reg = <0x48>;
	interrupt-parent = <&gpio1>;
	interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&tmp_alrt>;
	#thermal-sensor-cells = <0>;
	};

	hym8563: rtc@51 {
	compatible = "haoyu,hym8563";
	reg = <0x51>;
	interrupt-parent = <&gpio0>;
	interrupts = <RK_PB5 IRQ_TYPE_EDGE_FALLING>;
	pinctrl-names = "default";
	pinctrl-0 = <&rtc_int>;
	#clock-cells = <0>;
	clock-output-names = "xin32k";
	};

	bat: battery@55 {
	compatible = "ti,bq27541";
	reg = <0x55>;
	power-supplies = <&bq24196>;
	};

	act8846: pmic@5a {
	compatible = "active-semi,act8846";
	reg = <0x5a>;
	pinctrl-names = "default";
	pinctrl-0 = <&dvs0_ctl &pmic_int>;

	vp1-supply = <&vsys>;
	vp2-supply = <&vsys>;
	vp3-supply = <&vsys>;
	vp4-supply = <&vsys>;
	inl1-supply = <&vcc_io>;
	inl2-supply = <&vsys>;
	inl3-supply = <&vsys>;

	regulators {
	vcc_ddr: REG1 {
	regulator-name = "VCC_DDR";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	vdd_log: REG2 {
	regulator-name = "VDD_LOG";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	vdd_arm: REG3 {
	regulator-name = "VDD_ARM";
	regulator-min-microvolt = <875000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	};

	vcc_io: vcc_hdmi: REG4 {
	regulator-name = "VCC_IO";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;
	};

	vdd_10: REG5 {
	regulator-name = "VDD_10";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	vdd_12: REG6 {
	regulator-name = "VDD_12";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	vcc18_cif: REG7 {
	regulator-name = "VCC18_CIF";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	vcca_33: REG8 {
	regulator-name = "VCCA_33";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vcc_tp: REG9 {
	regulator-name = "VCC_TP";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vccio_wl: REG10 {
	regulator-name = "VCCIO_WL";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-always-on;
	};

	vcc_18: REG11 {
	regulator-name = "VCC_18";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	vcc28_cif: REG12 {
	regulator-name = "VCC28_CIF";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-always-on;
	};
	};
	};

	bq24196: charger@6b {
	compatible = "ti,bq24196";
	reg = <0x6b>;
	interrupt-parent = <&gpio0>;
	interrupts = <RK_PD7 IRQ_TYPE_EDGE_FALLING>;
	pinctrl-names = "default";
	pinctrl-0 = <&charger_int &chg_ctl &otg_en>;
	ti,system-minimum-microvolt = <3200000>;
	monitored-battery = <&bat>;
	omit-battery-class;

	usb_otg_vbus: usb-otg-vbus { };
	};
	};

	&i2c2 {
	clock-frequency = <400000>;
	status = "okay";

	ft5606: touchscreen@3e {
	compatible = "edt,edt-ft5506";
	reg = <0x3e>;
	interrupt-parent = <&gpio1>;
	interrupts = <RK_PB7 IRQ_TYPE_EDGE_FALLING>;
	pinctrl-names = "default";
	pinctrl-0 = <&tp_int &tp_rst>;
	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
	touchscreen-inverted-y;
	/* hw ts resolution does not match display */
	touchscreen-size-y = <1024>;
	touchscreen-size-x = <768>;
	touchscreen-swapped-x-y;
	};
	};

	&i2c3 {
	clock-frequency = <400000>;
	status = "okay";
	};

	&i2c4 {
	clock-frequency = <400000>;
	status = "okay";

	rt5616: codec@1b {
	compatible = "realtek,rt5616";
	reg = <0x1b>;
	clocks = <&cru SCLK_I2S0>;
	clock-names = "mclk";
	#sound-dai-cells = <0>;
	};
	};

	&i2s0 {
	status = "okay";
	};

	&mmc0 {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	disable-wp;
	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
	vmmc-supply = <&vcc_sd>;
	status = "okay";
	};

	&mmc1 {
	bus-width = <4>;
	cap-sd-highspeed;
	keep-power-in-suspend;
	mmc-pwrseq = <&sdio_pwrseq>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>;
	- vmmcq-supply = <&vccio_wl>;
	+ vqmmc-supply = <&vccio_wl>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	brcmf: wifi@1 {
	reg = <1>;
	compatible = "brcm,bcm4329-fmac";
	interrupt-parent = <&gpio3>;
	interrupts = <RK_PD2 GPIO_ACTIVE_HIGH>;
	interrupt-names = "host-wake";
	brcm,drive-strength = <5>;
	pinctrl-names = "default";
	pinctrl-0 = <&wifi_host_wake>;
	};
	};

	&pwm1 {
	status = "okay";
	};

	&pinctrl {
	pcfg_output_high: pcfg-output-high {
	output-high;
	};

	pcfg_output_low: pcfg-output-low {
	output-low;
	};

	act8846 {
	dvs0_ctl: dvs0-ctl {
	rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>;
	};

	pmic_int: pmic-int {
	rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	bq24196 {
	charger_int: charger-int {
	rockchip,pins = <0 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>;
	};

	/* pin hog to make it select usb profile */
	chg_ctl: chg-ctl {
	rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>;
	};

	/* low: charging, high: complete, fault: blinking */
	chg_det: chg-det {
	rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	/* charging enabled when pin low and register set */
	chg_en: chg-en {
	rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>;
	};

	/* bq29196 powergood (when low) signal */
	dc_det: dc-det {
	rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	/* wire bq24196 otg pin to high, to enable 500mA charging */
	otg_en: otg-en {
	rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>;
	};
	};

	camera {
	cif0_pdn: cif0-pdn {
	rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	cif1_pdn: cif1-pdn {
	rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	cif_avdd_en: cif-avdd-en {
	rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	display {
	lcd_cs: lcd-cs {
	rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	lcd_en: lcd-en {
	rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	ft5606 {
	tp_int: tp-int {
	rockchip,pins = <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
	};

	tp_rst: tp-rst {
	rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	hdmi {
	hdmi_int: hdmi-int {
	rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
	};

	hdmi_rst: hdmi-rst {
	rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	hym8563 {
	rtc_int: rtc-int {
	rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	keys {
	pwr_hold: pwr-hold {
	rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
	};

	pwr_key: pwr-key {
	rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	lis3de {
	gsensor_int: gsensor-int {
	rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	mmc {
	sdmmc_pwr: sdmmc-pwr {
	rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	tmp108 {
	tmp_alrt: tmp-alrt {
	rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	usb {
	v5_drv: v5-drv {
	rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	otg_drv: otg-drv {
	rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	usb_int: usb-int {
	rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	rk903 {
	bt_host_wake: bt-host-wake {
	rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
	};

	bt_reg_on: bt-reg-on {
	rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	/* pin hog to pull the reset high */
	bt_rst: bt-rst {
	rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_output_high>;
	};

	bt_wake: bt-wake {
	rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	wifi_host_wake: wifi-host-wake {
	rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
	};

	wifi_reg_on: wifi-reg-on {
	rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};
	};

	&saradc {
	vref-supply = <&vcc_18>;
	status = "okay";
	};

	&spdif {
	status = "okay";
	};

	&uart0 {
	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
	status = "okay";

	bluetooth {
	compatible = "brcm,bcm43438-bt";
	max-speed = <2000000>;
	device-wakeup-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
	host-wakeup-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
	shutdown-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&bt_host_wake &bt_reg_on &bt_rst &bt_wake>;
	};
	};

	&uart1 {
	status = "okay";
	};

	&uart2 {
	status = "okay";
	};

	&uart3 {
	pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
	status = "okay";
	};

	&usbphy {
	status = "okay";
	};

	&usb_host {
	status = "okay";
	};

	&usb_otg {
	status = "okay";
	};

	&vop0 {
	status = "okay";
	};

	&vop0_out {
	vop0_out_lvds: endpoint {
	remote-endpoint = <&lvds_in_vop0>;
	};
	};

	&vop1 {
	pinctrl-names = "default";
	pinctrl-0 = <&lcdc1_dclk &lcdc1_den &lcdc1_hsync
	&lcdc1_vsync &lcdc1_rgb24>;
	status = "okay";
	};

	&wdt {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/rk3188.dtsi b/sys/gnu/dts/arm/rk3188.dtsi
	index 10ede65d90f3..2298a8d840ba 100644
	--- a/sys/gnu/dts/arm/rk3188.dtsi
	+++ b/sys/gnu/dts/arm/rk3188.dtsi
	@@ -1,801 +1,799 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2013 MundoReader S.L.
	* Author: Heiko Stuebner <heiko@sntech.de>
	*/

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/pinctrl/rockchip.h>
	#include <dt-bindings/clock/rk3188-cru.h>
	#include <dt-bindings/power/rk3188-power.h>
	#include "rk3xxx.dtsi"

	/ {
	compatible = "rockchip,rk3188";

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "rockchip,rk3066-smp";

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	next-level-cache = <&L2>;
	reg = <0x0>;
	clock-latency = <40000>;
	clocks = <&cru ARMCLK>;
	operating-points-v2 = <&cpu0_opp_table>;
	resets = <&cru SRST_CORE0>;
	};
	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	next-level-cache = <&L2>;
	reg = <0x1>;
	operating-points-v2 = <&cpu0_opp_table>;
	resets = <&cru SRST_CORE1>;
	};
	cpu2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	next-level-cache = <&L2>;
	reg = <0x2>;
	operating-points-v2 = <&cpu0_opp_table>;
	resets = <&cru SRST_CORE2>;
	};
	cpu3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	next-level-cache = <&L2>;
	reg = <0x3>;
	operating-points-v2 = <&cpu0_opp_table>;
	resets = <&cru SRST_CORE3>;
	};
	};

	cpu0_opp_table: opp_table0 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-312000000 {
	opp-hz = /bits/ 64 <312000000>;
	opp-microvolt = <875000>;
	clock-latency-ns = <40000>;
	};
	opp-504000000 {
	opp-hz = /bits/ 64 <504000000>;
	opp-microvolt = <925000>;
	};
	opp-600000000 {
	opp-hz = /bits/ 64 <600000000>;
	opp-microvolt = <950000>;
	opp-suspend;
	};
	opp-816000000 {
	opp-hz = /bits/ 64 <816000000>;
	opp-microvolt = <975000>;
	};
	opp-1008000000 {
	opp-hz = /bits/ 64 <1008000000>;
	opp-microvolt = <1075000>;
	};
	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	opp-microvolt = <1150000>;
	};
	opp-1416000000 {
	opp-hz = /bits/ 64 <1416000000>;
	opp-microvolt = <1250000>;
	};
	opp-1608000000 {
	opp-hz = /bits/ 64 <1608000000>;
	opp-microvolt = <1350000>;
	};
	};

	display-subsystem {
	compatible = "rockchip,display-subsystem";
	ports = <&vop0_out>, <&vop1_out>;
	};

	sram: sram@10080000 {
	compatible = "mmio-sram";
	reg = <0x10080000 0x8000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x10080000 0x8000>;

	smp-sram@0 {
	compatible = "rockchip,rk3066-smp-sram";
	reg = <0x0 0x50>;
	};
	};

	vop0: vop@1010c000 {
	compatible = "rockchip,rk3188-vop";
	reg = <0x1010c000 0x1000>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	power-domains = <&power RK3188_PD_VIO>;
	resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
	reset-names = "axi", "ahb", "dclk";
	status = "disabled";

	vop0_out: port {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	vop1: vop@1010e000 {
	compatible = "rockchip,rk3188-vop";
	reg = <0x1010e000 0x1000>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	power-domains = <&power RK3188_PD_VIO>;
	resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
	reset-names = "axi", "ahb", "dclk";
	status = "disabled";

	vop1_out: port {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	timer3: timer@2000e000 {
	compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
	reg = <0x2000e000 0x20>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>;
	clock-names = "timer", "pclk";
	};

	timer6: timer@200380a0 {
	compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
	reg = <0x200380a0 0x20>;
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>;
	clock-names = "timer", "pclk";
	};

	i2s0: i2s@1011a000 {
	compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
	reg = <0x1011a000 0x2000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	- #address-cells = <1>;
	- #size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2s0_bus>;
	+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
	+ clock-names = "i2s_clk", "i2s_hclk";
	dmas = <&dmac1_s 6>, <&dmac1_s 7>;
	dma-names = "tx", "rx";
	- clock-names = "i2s_hclk", "i2s_clk";
	- clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
	rockchip,playback-channels = <2>;
	rockchip,capture-channels = <2>;
	#sound-dai-cells = <0>;
	status = "disabled";
	};

	spdif: sound@1011e000 {
	compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
	reg = <0x1011e000 0x2000>;
	#sound-dai-cells = <0>;
	- clock-names = "hclk", "mclk";
	- clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
	+ clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
	+ clock-names = "mclk", "hclk";
	dmas = <&dmac1_s 8>;
	dma-names = "tx";
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&spdif_tx>;
	status = "disabled";
	};

	cru: clock-controller@20000000 {
	compatible = "rockchip,rk3188-cru";
	reg = <0x20000000 0x1000>;
	rockchip,grf = <&grf>;

	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	efuse: efuse@20010000 {
	compatible = "rockchip,rk3188-efuse";
	reg = <0x20010000 0x4000>;
	#address-cells = <1>;
	#size-cells = <1>;
	clocks = <&cru PCLK_EFUSE>;
	clock-names = "pclk_efuse";

	cpu_leakage: cpu_leakage@17 {
	reg = <0x17 0x1>;
	};
	};

	usbphy: phy {
	compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
	rockchip,grf = <&grf>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";

	usbphy0: usb-phy@10c {
	#phy-cells = <0>;
	reg = <0x10c>;
	clocks = <&cru SCLK_OTGPHY0>;
	clock-names = "phyclk";
	#clock-cells = <0>;
	};

	usbphy1: usb-phy@11c {
	#phy-cells = <0>;
	reg = <0x11c>;
	clocks = <&cru SCLK_OTGPHY1>;
	clock-names = "phyclk";
	#clock-cells = <0>;
	};
	};

	pinctrl: pinctrl {
	compatible = "rockchip,rk3188-pinctrl";
	rockchip,grf = <&grf>;
	rockchip,pmu = <&pmu>;

	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	gpio0: gpio0@2000a000 {
	compatible = "rockchip,rk3188-gpio-bank0";
	reg = <0x2000a000 0x100>;
	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO0>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio1: gpio1@2003c000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x2003c000 0x100>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO1>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio2@2003e000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x2003e000 0x100>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO2>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio3@20080000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x20080000 0x100>;
	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO3>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	pcfg_pull_up: pcfg_pull_up {
	bias-pull-up;
	};

	pcfg_pull_down: pcfg_pull_down {
	bias-pull-down;
	};

	pcfg_pull_none: pcfg_pull_none {
	bias-disable;
	};

	emmc {
	emmc_clk: emmc-clk {
	rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
	};

	emmc_cmd: emmc-cmd {
	rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>;
	};

	emmc_rst: emmc-rst {
	rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>;
	};

	/*
	* The data pins are shared between nandc and emmc and
	* not accessible through pinctrl. Also they should've
	* been already set correctly by firmware, as
	* flash/emmc is the boot-device.
	*/
	};

	emac {
	emac_xfer: emac-xfer {
	rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */
	<3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */
	<3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */
	<3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */
	<3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */
	<3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */
	<3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */
	<3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */
	};

	emac_mdio: emac-mdio {
	rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
	<3 RK_PD1 2 &pcfg_pull_none>;
	};
	};

	i2c0 {
	i2c0_xfer: i2c0-xfer {
	rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
	<1 RK_PD1 1 &pcfg_pull_none>;
	};
	};

	i2c1 {
	i2c1_xfer: i2c1-xfer {
	rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>,
	<1 RK_PD3 1 &pcfg_pull_none>;
	};
	};

	i2c2 {
	i2c2_xfer: i2c2-xfer {
	rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>,
	<1 RK_PD5 1 &pcfg_pull_none>;
	};
	};

	i2c3 {
	i2c3_xfer: i2c3-xfer {
	rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>,
	<3 RK_PB7 2 &pcfg_pull_none>;
	};
	};

	i2c4 {
	i2c4_xfer: i2c4-xfer {
	rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>,
	<1 RK_PD7 1 &pcfg_pull_none>;
	};
	};

	lcdc1 {
	lcdc1_dclk: lcdc1-dclk {
	rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>;
	};

	lcdc1_den: lcdc1-den {
	rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>;
	};

	lcdc1_hsync: lcdc1-hsync {
	rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
	};

	lcdc1_vsync: lcdc1-vsync {
	rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
	};

	lcdc1_rgb24: ldcd1-rgb24 {
	rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
	<2 RK_PA1 1 &pcfg_pull_none>,
	<2 RK_PA2 1 &pcfg_pull_none>,
	<2 RK_PA3 1 &pcfg_pull_none>,
	<2 RK_PA4 1 &pcfg_pull_none>,
	<2 RK_PA5 1 &pcfg_pull_none>,
	<2 RK_PA6 1 &pcfg_pull_none>,
	<2 RK_PA7 1 &pcfg_pull_none>,
	<2 RK_PB0 1 &pcfg_pull_none>,
	<2 RK_PB1 1 &pcfg_pull_none>,
	<2 RK_PB2 1 &pcfg_pull_none>,
	<2 RK_PB3 1 &pcfg_pull_none>,
	<2 RK_PB4 1 &pcfg_pull_none>,
	<2 RK_PB5 1 &pcfg_pull_none>,
	<2 RK_PB6 1 &pcfg_pull_none>,
	<2 RK_PB7 1 &pcfg_pull_none>,
	<2 RK_PC0 1 &pcfg_pull_none>,
	<2 RK_PC1 1 &pcfg_pull_none>,
	<2 RK_PC2 1 &pcfg_pull_none>,
	<2 RK_PC3 1 &pcfg_pull_none>,
	<2 RK_PC4 1 &pcfg_pull_none>,
	<2 RK_PC5 1 &pcfg_pull_none>,
	<2 RK_PC6 1 &pcfg_pull_none>,
	<2 RK_PC7 1 &pcfg_pull_none>;
	};
	};

	pwm0 {
	pwm0_out: pwm0-out {
	rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
	};
	};

	pwm1 {
	pwm1_out: pwm1-out {
	rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>;
	};
	};

	pwm2 {
	pwm2_out: pwm2-out {
	rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>;
	};
	};

	pwm3 {
	pwm3_out: pwm3-out {
	rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>;
	};
	};

	spi0 {
	spi0_clk: spi0-clk {
	rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>;
	};
	spi0_cs0: spi0-cs0 {
	rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>;
	};
	spi0_tx: spi0-tx {
	rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>;
	};
	spi0_rx: spi0-rx {
	rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>;
	};
	spi0_cs1: spi0-cs1 {
	rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>;
	};
	};

	spi1 {
	spi1_clk: spi1-clk {
	rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>;
	};
	spi1_cs0: spi1-cs0 {
	rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>;
	};
	spi1_rx: spi1-rx {
	rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>;
	};
	spi1_tx: spi1-tx {
	rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>;
	};
	spi1_cs1: spi1-cs1 {
	rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
	};
	};

	uart0 {
	uart0_xfer: uart0-xfer {
	rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>,
	<1 RK_PA1 1 &pcfg_pull_none>;
	};

	uart0_cts: uart0-cts {
	rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>;
	};

	uart0_rts: uart0-rts {
	rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>;
	};
	};

	uart1 {
	uart1_xfer: uart1-xfer {
	rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>,
	<1 RK_PA5 1 &pcfg_pull_none>;
	};

	uart1_cts: uart1-cts {
	rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
	};

	uart1_rts: uart1-rts {
	rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>;
	};
	};

	uart2 {
	uart2_xfer: uart2-xfer {
	rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>,
	<1 RK_PB1 1 &pcfg_pull_none>;
	};
	/* no rts / cts for uart2 */
	};

	uart3 {
	uart3_xfer: uart3-xfer {
	rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>,
	<1 RK_PB3 1 &pcfg_pull_none>;
	};

	uart3_cts: uart3-cts {
	rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>;
	};

	uart3_rts: uart3-rts {
	rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>;
	};
	};

	sd0 {
	sd0_clk: sd0-clk {
	rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>;
	};

	sd0_cmd: sd0-cmd {
	rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
	};

	sd0_cd: sd0-cd {
	rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>;
	};

	sd0_wp: sd0-wp {
	rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>;
	};

	sd0_pwr: sd0-pwr {
	rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
	};

	sd0_bus1: sd0-bus-width1 {
	rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
	};

	sd0_bus4: sd0-bus-width4 {
	rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
	<3 RK_PA5 1 &pcfg_pull_none>,
	<3 RK_PA6 1 &pcfg_pull_none>,
	<3 RK_PA7 1 &pcfg_pull_none>;
	};
	};

	sd1 {
	sd1_clk: sd1-clk {
	rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
	};

	sd1_cmd: sd1-cmd {
	rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>;
	};

	sd1_cd: sd1-cd {
	rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>;
	};

	sd1_wp: sd1-wp {
	rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>;
	};

	sd1_bus1: sd1-bus-width1 {
	rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>;
	};

	sd1_bus4: sd1-bus-width4 {
	rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>,
	<3 RK_PC2 1 &pcfg_pull_none>,
	<3 RK_PC3 1 &pcfg_pull_none>,
	<3 RK_PC4 1 &pcfg_pull_none>;
	};
	};

	i2s0 {
	i2s0_bus: i2s0-bus {
	rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
	<1 RK_PC1 1 &pcfg_pull_none>,
	<1 RK_PC2 1 &pcfg_pull_none>,
	<1 RK_PC3 1 &pcfg_pull_none>,
	<1 RK_PC4 1 &pcfg_pull_none>,
	<1 RK_PC5 1 &pcfg_pull_none>;
	};
	};

	spdif {
	spdif_tx: spdif-tx {
	rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>;
	};
	};
	};
	};

	&emac {
	compatible = "rockchip,rk3188-emac";
	};

	&global_timer {
	interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_EDGE_RISING)>;
	status = "disabled";
	};

	&local_timer {
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_EDGE_RISING)>;
	};

	&gpu {
	compatible = "rockchip,rk3188-mali", "arm,mali-400";
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gp",
	"gpmmu",
	"pp0",
	"ppmmu0",
	"pp1",
	"ppmmu1",
	"pp2",
	"ppmmu2",
	"pp3",
	"ppmmu3";
	power-domains = <&power RK3188_PD_GPU>;
	};

	&i2c0 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
	};

	&i2c1 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
	};

	&i2c2 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
	};

	&i2c3 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
	};

	&i2c4 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_xfer>;
	};

	&pmu {
	power: power-controller {
	compatible = "rockchip,rk3188-power-controller";
	#power-domain-cells = <1>;
	#address-cells = <1>;
	#size-cells = <0>;

	pd_vio@RK3188_PD_VIO {
	reg = <RK3188_PD_VIO>;
	clocks = <&cru ACLK_LCDC0>,
	<&cru ACLK_LCDC1>,
	<&cru DCLK_LCDC0>,
	<&cru DCLK_LCDC1>,
	<&cru HCLK_LCDC0>,
	<&cru HCLK_LCDC1>,
	<&cru SCLK_CIF0>,
	<&cru ACLK_CIF0>,
	<&cru HCLK_CIF0>,
	<&cru ACLK_IPP>,
	<&cru HCLK_IPP>,
	<&cru ACLK_RGA>,
	<&cru HCLK_RGA>;
	pm_qos = <&qos_lcdc0>,
	<&qos_lcdc1>,
	<&qos_cif0>,
	<&qos_ipp>,
	<&qos_rga>;
	};

	pd_video@RK3188_PD_VIDEO {
	reg = <RK3188_PD_VIDEO>;
	clocks = <&cru ACLK_VDPU>,
	<&cru ACLK_VEPU>,
	<&cru HCLK_VDPU>,
	<&cru HCLK_VEPU>;
	pm_qos = <&qos_vpu>;
	};

	pd_gpu@RK3188_PD_GPU {
	reg = <RK3188_PD_GPU>;
	clocks = <&cru ACLK_GPU>;
	pm_qos = <&qos_gpu>;
	};
	};
	};

	&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_out>;
	};

	&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_out>;
	};

	&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_out>;
	};

	&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_out>;
	};

	&spi0 {
	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
	};

	&spi1 {
	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
	};

	&uart0 {
	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer>;
	};

	&uart1 {
	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer>;
	};

	&uart2 {
	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_xfer>;
	};

	&uart3 {
	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_xfer>;
	};

	&wdt {
	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
	};
	diff --git a/sys/gnu/dts/arm/rk3228-evb.dts b/sys/gnu/dts/arm/rk3228-evb.dts
	index 5670b33fd1bd..aed879db6c15 100644
	--- a/sys/gnu/dts/arm/rk3228-evb.dts
	+++ b/sys/gnu/dts/arm/rk3228-evb.dts
	@@ -1,68 +1,68 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

	/dts-v1/;

	#include "rk322x.dtsi"

	/ {
	model = "Rockchip RK3228 Evaluation board";
	compatible = "rockchip,rk3228-evb", "rockchip,rk3228";

	memory@60000000 {
	device_type = "memory";
	reg = <0x60000000 0x40000000>;
	};

	vcc_phy: vcc-phy-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	regulator-name = "vcc_phy";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};
	};

	&emmc {
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	disable-wp;
	non-removable;
	status = "okay";
	};

	&gmac {
	assigned-clocks = <&cru SCLK_MAC_SRC>;
	assigned-clock-rates = <50000000>;
	clock_in_out = "output";
	phy-supply = <&vcc_phy>;
	phy-mode = "rmii";
	phy-handle = <&phy>;
	status = "okay";

	mdio {
	compatible = "snps,dwmac-mdio";
	#address-cells = <1>;
	#size-cells = <0>;

	- phy: phy@0 {
	+ phy: ethernet-phy@0 {
	compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
	reg = <0>;
	clocks = <&cru SCLK_MAC_PHY>;
	resets = <&cru SRST_MACPHY>;
	phy-is-integrated;
	};
	};
	};

	&tsadc {
	status = "okay";

	rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
	};

	&uart2 {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/rk3229-xms6.dts b/sys/gnu/dts/arm/rk3229-xms6.dts
	index 679fc2b00e5a..933ef69da32a 100644
	--- a/sys/gnu/dts/arm/rk3229-xms6.dts
	+++ b/sys/gnu/dts/arm/rk3229-xms6.dts
	@@ -1,283 +1,283 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

	/dts-v1/;

	#include <dt-bindings/input/input.h>
	#include "rk3229.dtsi"

	/ {
	model = "Mecer Xtreme Mini S6";
	compatible = "mecer,xms6", "rockchip,rk3229";

	memory@60000000 {
	device_type = "memory";
	reg = <0x60000000 0x40000000>;
	};

	dc_12v: dc-12v-regulator {
	compatible = "regulator-fixed";
	regulator-name = "dc_12v";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	};

	ext_gmac: ext_gmac {
	compatible = "fixed-clock";
	clock-frequency = <125000000>;
	clock-output-names = "ext_gmac";
	#clock-cells = <0>;
	};

	power-led {
	compatible = "gpio-leds";

	blue {
	gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
	default-state = "on";
	};
	};

	vcc_host: vcc-host-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&host_vbus_drv>;
	regulator-name = "vcc_host";
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vcc_sys>;
	};

	vcc_phy: vcc-phy-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	regulator-name = "vcc_phy";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vccio_1v8>;
	};

	vcc_sys: vcc-sys-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vcc_sys";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&dc_12v>;
	};

	vccio_1v8: vccio-1v8-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vccio_1v8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	vin-supply = <&vcc_sys>;
	};

	vccio_3v3: vccio-3v3-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vccio_3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	vin-supply = <&vcc_sys>;
	};

	vdd_arm: vdd-arm-regulator {
	compatible = "pwm-regulator";
	pwms = <&pwm1 0 25000 1>;
	pwm-supply = <&vcc_sys>;
	regulator-name = "vdd_arm";
	regulator-min-microvolt = <950000>;
	regulator-max-microvolt = <1400000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_log: vdd-log-regulator {
	compatible = "pwm-regulator";
	pwms = <&pwm2 0 25000 1>;
	pwm-supply = <&vcc_sys>;
	regulator-name = "vdd_log";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1300000>;
	regulator-always-on;
	regulator-boot-on;
	};
	};

	&cpu0 {
	cpu-supply = <&vdd_arm>;
	};

	&cpu1 {
	cpu-supply = <&vdd_arm>;
	};

	&cpu2 {
	cpu-supply = <&vdd_arm>;
	};

	&cpu3 {
	cpu-supply = <&vdd_arm>;
	};

	&emmc {
	cap-mmc-highspeed;
	disable-wp;
	non-removable;
	status = "okay";
	};

	&gmac {
	assigned-clocks = <&cru SCLK_MAC_SRC>;
	assigned-clock-rates = <50000000>;
	clock_in_out = "output";
	phy-handle = <&phy>;
	phy-mode = "rmii";
	phy-supply = <&vcc_phy>;
	status = "okay";

	mdio {
	compatible = "snps,dwmac-mdio";
	#address-cells = <1>;
	#size-cells = <0>;

	- phy: phy@0 {
	+ phy: ethernet-phy@0 {
	compatible = "ethernet-phy-id1234.d400",
	"ethernet-phy-ieee802.3-c22";
	reg = <0>;
	clocks = <&cru SCLK_MAC_PHY>;
	phy-is-integrated;
	resets = <&cru SRST_MACPHY>;
	};
	};
	};

	&gpu {
	mali-supply = <&vdd_log>;
	status = "okay";
	};

	&hdmi {
	status = "okay";
	};

	&hdmi_phy {
	status = "okay";
	};

	&iep_mmu {
	status = "okay";
	};

	&io_domains {
	status = "okay";

	vccio1-supply = <&vccio_3v3>;
	vccio2-supply = <&vccio_1v8>;
	vccio4-supply = <&vccio_3v3>;
	};

	&pinctrl {
	usb {
	host_vbus_drv: host-vbus-drv {
	rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};
	};

	&pwm1 {
	status = "okay";
	};

	&pwm2 {
	status = "okay";
	};

	&sdmmc {
	cap-mmc-highspeed;
	disable-wp;
	status = "okay";
	};

	&tsadc {
	rockchip,hw-tshut-mode = <0>;
	status = "okay";
	};

	&u2phy0 {
	status = "okay";

	u2phy0_host: host-port {
	phy-supply = <&vcc_host>;
	status = "okay";
	};

	u2phy0_otg: otg-port {
	phy-supply = <&vcc_host>;
	status = "okay";
	};
	};

	&u2phy1 {
	status = "okay";

	u2phy1_host: host-port {
	phy-supply = <&vcc_host>;
	status = "okay";
	};

	u2phy1_otg: otg-port {
	phy-supply = <&vcc_host>;
	status = "okay";
	};
	};

	&uart2 {
	pinctrl-0 = <&uart21_xfer>;
	status = "okay";
	};

	&usb_host0_ehci {
	status = "okay";
	};

	&usb_host0_ohci {
	status = "okay";
	};

	&usb_host1_ehci {
	status = "okay";
	};

	&usb_host1_ohci {
	status = "okay";
	};

	&usb_host2_ehci {
	status = "okay";
	};

	&usb_host2_ohci {
	status = "okay";
	};

	&usb_otg {
	status = "okay";
	};

	&vop {
	status = "okay";
	};

	&vop_mmu {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/rk322x.dtsi b/sys/gnu/dts/arm/rk322x.dtsi
	index 4e90efdc9630..5485a9918da6 100644
	--- a/sys/gnu/dts/arm/rk322x.dtsi
	+++ b/sys/gnu/dts/arm/rk322x.dtsi
	@@ -1,1176 +1,1163 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/pinctrl/rockchip.h>
	#include <dt-bindings/clock/rk3228-cru.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	aliases {
	serial0 = &uart0;
	serial1 = &uart1;
	serial2 = &uart2;
	spi0 = &spi0;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@f00 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0xf00>;
	resets = <&cru SRST_CORE0>;
	operating-points-v2 = <&cpu0_opp_table>;
	#cooling-cells = <2>; /* min followed by max */
	clock-latency = <40000>;
	clocks = <&cru ARMCLK>;
	enable-method = "psci";
	};

	cpu1: cpu@f01 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0xf01>;
	resets = <&cru SRST_CORE1>;
	operating-points-v2 = <&cpu0_opp_table>;
	#cooling-cells = <2>; /* min followed by max */
	enable-method = "psci";
	};

	cpu2: cpu@f02 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0xf02>;
	resets = <&cru SRST_CORE2>;
	operating-points-v2 = <&cpu0_opp_table>;
	#cooling-cells = <2>; /* min followed by max */
	enable-method = "psci";
	};

	cpu3: cpu@f03 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0xf03>;
	resets = <&cru SRST_CORE3>;
	operating-points-v2 = <&cpu0_opp_table>;
	#cooling-cells = <2>; /* min followed by max */
	enable-method = "psci";
	};
	};

	cpu0_opp_table: opp_table0 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-408000000 {
	opp-hz = /bits/ 64 <408000000>;
	opp-microvolt = <950000>;
	clock-latency-ns = <40000>;
	opp-suspend;
	};
	opp-600000000 {
	opp-hz = /bits/ 64 <600000000>;
	opp-microvolt = <975000>;
	};
	opp-816000000 {
	opp-hz = /bits/ 64 <816000000>;
	opp-microvolt = <1000000>;
	};
	opp-1008000000 {
	opp-hz = /bits/ 64 <1008000000>;
	opp-microvolt = <1175000>;
	};
	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	opp-microvolt = <1275000>;
	};
	};

	- amba {
	+ amba: bus {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	pdma: pdma@110f0000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x110f0000 0x4000>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	clocks = <&cru ACLK_DMAC>;
	clock-names = "apb_pclk";
	};
	};

	arm-pmu {
	compatible = "arm,cortex-a7-pmu";
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	psci {
	compatible = "arm,psci-1.0", "arm,psci-0.2";
	method = "smc";
	};

	timer {
	compatible = "arm,armv7-timer";
	arm,cpu-registers-not-fw-configured;
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	clock-frequency = <24000000>;
	};

	xin24m: oscillator {
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-output-names = "xin24m";
	#clock-cells = <0>;
	};

	display_subsystem: display-subsystem {
	compatible = "rockchip,display-subsystem";
	ports = <&vop_out>;
	};

	i2s1: i2s1@100b0000 {
	compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
	reg = <0x100b0000 0x4000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	- #address-cells = <1>;
	- #size-cells = <0>;
	clock-names = "i2s_clk", "i2s_hclk";
	clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
	dmas = <&pdma 14>, <&pdma 15>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&i2s1_bus>;
	status = "disabled";
	};

	i2s0: i2s0@100c0000 {
	compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
	reg = <0x100c0000 0x4000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	- #address-cells = <1>;
	- #size-cells = <0>;
	clock-names = "i2s_clk", "i2s_hclk";
	clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
	dmas = <&pdma 11>, <&pdma 12>;
	dma-names = "tx", "rx";
	status = "disabled";
	};

	spdif: spdif@100d0000 {
	compatible = "rockchip,rk3228-spdif";
	reg = <0x100d0000 0x1000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
	clock-names = "mclk", "hclk";
	dmas = <&pdma 10>;
	dma-names = "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&spdif_tx>;
	status = "disabled";
	};

	i2s2: i2s2@100e0000 {
	compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
	reg = <0x100e0000 0x4000>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	- #address-cells = <1>;
	- #size-cells = <0>;
	clock-names = "i2s_clk", "i2s_hclk";
	clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
	dmas = <&pdma 0>, <&pdma 1>;
	dma-names = "tx", "rx";
	status = "disabled";
	};

	grf: syscon@11000000 {
	compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
	reg = <0x11000000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;

	io_domains: io-domains {
	compatible = "rockchip,rk3228-io-voltage-domain";
	status = "disabled";
	};

	u2phy0: usb2-phy@760 {
	compatible = "rockchip,rk3228-usb2phy";
	reg = <0x0760 0x0c>;
	clocks = <&cru SCLK_OTGPHY0>;
	clock-names = "phyclk";
	clock-output-names = "usb480m_phy0";
	#clock-cells = <0>;
	status = "disabled";

	u2phy0_otg: otg-port {
	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "otg-bvalid", "otg-id",
	"linestate";
	#phy-cells = <0>;
	status = "disabled";
	};

	u2phy0_host: host-port {
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "linestate";
	#phy-cells = <0>;
	status = "disabled";
	};
	};

	u2phy1: usb2-phy@800 {
	compatible = "rockchip,rk3228-usb2phy";
	reg = <0x0800 0x0c>;
	clocks = <&cru SCLK_OTGPHY1>;
	clock-names = "phyclk";
	clock-output-names = "usb480m_phy1";
	#clock-cells = <0>;
	status = "disabled";

	u2phy1_otg: otg-port {
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "linestate";
	#phy-cells = <0>;
	status = "disabled";
	};

	u2phy1_host: host-port {
	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "linestate";
	#phy-cells = <0>;
	status = "disabled";
	};
	};
	};

	uart0: serial@11010000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x11010000 0x100>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <24000000>;
	clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
	clock-names = "baudclk", "apb_pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
	reg-shift = <2>;
	reg-io-width = <4>;
	status = "disabled";
	};

	uart1: serial@11020000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x11020000 0x100>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <24000000>;
	clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
	clock-names = "baudclk", "apb_pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer>;
	reg-shift = <2>;
	reg-io-width = <4>;
	status = "disabled";
	};

	uart2: serial@11030000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x11030000 0x100>;
	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <24000000>;
	clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
	clock-names = "baudclk", "apb_pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_xfer>;
	reg-shift = <2>;
	reg-io-width = <4>;
	status = "disabled";
	};

	efuse: efuse@11040000 {
	compatible = "rockchip,rk3228-efuse";
	reg = <0x11040000 0x20>;
	clocks = <&cru PCLK_EFUSE_256>;
	clock-names = "pclk_efuse";
	#address-cells = <1>;
	#size-cells = <1>;

	/* Data cells */
	efuse_id: id@7 {
	reg = <0x7 0x10>;
	};
	cpu_leakage: cpu_leakage@17 {
	reg = <0x17 0x1>;
	};
	};

	i2c0: i2c@11050000 {
	compatible = "rockchip,rk3228-i2c";
	reg = <0x11050000 0x1000>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
	status = "disabled";
	};

	i2c1: i2c@11060000 {
	compatible = "rockchip,rk3228-i2c";
	reg = <0x11060000 0x1000>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C1>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
	status = "disabled";
	};

	i2c2: i2c@11070000 {
	compatible = "rockchip,rk3228-i2c";
	reg = <0x11070000 0x1000>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C2>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
	status = "disabled";
	};

	i2c3: i2c@11080000 {
	compatible = "rockchip,rk3228-i2c";
	reg = <0x11080000 0x1000>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C3>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
	status = "disabled";
	};

	spi0: spi@11090000 {
	compatible = "rockchip,rk3228-spi";
	reg = <0x11090000 0x1000>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
	clock-names = "spiclk", "apb_pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
	status = "disabled";
	};

	wdt: watchdog@110a0000 {
	compatible = "snps,dw-wdt";
	reg = <0x110a0000 0x100>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_CPU>;
	status = "disabled";
	};

	pwm0: pwm@110b0000 {
	compatible = "rockchip,rk3288-pwm";
	reg = <0x110b0000 0x10>;
	#pwm-cells = <3>;
	clocks = <&cru PCLK_PWM>;
	clock-names = "pwm";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_pin>;
	status = "disabled";
	};

	pwm1: pwm@110b0010 {
	compatible = "rockchip,rk3288-pwm";
	reg = <0x110b0010 0x10>;
	#pwm-cells = <3>;
	clocks = <&cru PCLK_PWM>;
	clock-names = "pwm";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_pin>;
	status = "disabled";
	};

	pwm2: pwm@110b0020 {
	compatible = "rockchip,rk3288-pwm";
	reg = <0x110b0020 0x10>;
	#pwm-cells = <3>;
	clocks = <&cru PCLK_PWM>;
	clock-names = "pwm";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_pin>;
	status = "disabled";
	};

	pwm3: pwm@110b0030 {
	compatible = "rockchip,rk3288-pwm";
	reg = <0x110b0030 0x10>;
	#pwm-cells = <2>;
	clocks = <&cru PCLK_PWM>;
	clock-names = "pwm";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_pin>;
	status = "disabled";
	};

	timer: timer@110c0000 {
	compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
	reg = <0x110c0000 0x20>;
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&xin24m>, <&cru PCLK_TIMER>;
	clock-names = "timer", "pclk";
	};

	cru: clock-controller@110e0000 {
	compatible = "rockchip,rk3228-cru";
	reg = <0x110e0000 0x1000>;
	rockchip,grf = <&grf>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	assigned-clocks =
	<&cru PLL_GPLL>, <&cru ARMCLK>,
	<&cru PLL_CPLL>, <&cru ACLK_PERI>,
	<&cru HCLK_PERI>, <&cru PCLK_PERI>,
	<&cru ACLK_CPU>, <&cru HCLK_CPU>,
	<&cru PCLK_CPU>;
	assigned-clock-rates =
	<594000000>, <816000000>,
	<500000000>, <150000000>,
	<150000000>, <75000000>,
	<150000000>, <150000000>,
	<75000000>;
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	polling-delay-passive = <100>; /* milliseconds */
	polling-delay = <5000>; /* milliseconds */

	thermal-sensors = <&tsadc 0>;

	trips {
	cpu_alert0: cpu_alert0 {
	temperature = <70000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "passive";
	};
	cpu_alert1: cpu_alert1 {
	temperature = <75000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "passive";
	};
	cpu_crit: cpu_crit {
	temperature = <90000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu_alert0>;
	cooling-device =
	<&cpu0 THERMAL_NO_LIMIT 6>,
	<&cpu1 THERMAL_NO_LIMIT 6>,
	<&cpu2 THERMAL_NO_LIMIT 6>,
	<&cpu3 THERMAL_NO_LIMIT 6>;
	};
	map1 {
	trip = <&cpu_alert1>;
	cooling-device =
	<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};
	};

	tsadc: tsadc@11150000 {
	compatible = "rockchip,rk3228-tsadc";
	reg = <0x11150000 0x100>;
	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
	clock-names = "tsadc", "apb_pclk";
	assigned-clocks = <&cru SCLK_TSADC>;
	assigned-clock-rates = <32768>;
	resets = <&cru SRST_TSADC>;
	reset-names = "tsadc-apb";
	pinctrl-names = "init", "default", "sleep";
	pinctrl-0 = <&otp_gpio>;
	pinctrl-1 = <&otp_out>;
	pinctrl-2 = <&otp_gpio>;
	#thermal-sensor-cells = <0>;
	rockchip,hw-tshut-temp = <95000>;
	status = "disabled";
	};

	hdmi_phy: hdmi-phy@12030000 {
	compatible = "rockchip,rk3228-hdmi-phy";
	reg = <0x12030000 0x10000>;
	clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
	clock-names = "sysclk", "refoclk", "refpclk";
	#clock-cells = <0>;
	clock-output-names = "hdmiphy_phy";
	#phy-cells = <0>;
	status = "disabled";
	};

	gpu: gpu@20000000 {
	compatible = "rockchip,rk3228-mali", "arm,mali-400";
	reg = <0x20000000 0x10000>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gp",
	"gpmmu",
	"pp0",
	"ppmmu0",
	"pp1",
	"ppmmu1";
	clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
	- clock-names = "core", "bus";
	+ clock-names = "bus", "core";
	resets = <&cru SRST_GPU_A>;
	status = "disabled";
	};

	vpu_mmu: iommu@20020800 {
	compatible = "rockchip,iommu";
	reg = <0x20020800 0x100>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "vpu_mmu";
	clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
	clock-names = "aclk", "iface";
	iommu-cells = <0>;
	status = "disabled";
	};

	vdec_mmu: iommu@20030480 {
	compatible = "rockchip,iommu";
	reg = <0x20030480 0x40>, <0x200304c0 0x40>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "vdec_mmu";
	clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
	clock-names = "aclk", "iface";
	iommu-cells = <0>;
	status = "disabled";
	};

	vop: vop@20050000 {
	compatible = "rockchip,rk3228-vop";
	reg = <0x20050000 0x1ffc>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
	reset-names = "axi", "ahb", "dclk";
	iommus = <&vop_mmu>;
	status = "disabled";

	vop_out: port {
	#address-cells = <1>;
	#size-cells = <0>;

	vop_out_hdmi: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&hdmi_in_vop>;
	};
	};
	};

	vop_mmu: iommu@20053f00 {
	compatible = "rockchip,iommu";
	reg = <0x20053f00 0x100>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "vop_mmu";
	clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	status = "disabled";
	};

	iep_mmu: iommu@20070800 {
	compatible = "rockchip,iommu";
	reg = <0x20070800 0x100>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "iep_mmu";
	clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
	clock-names = "aclk", "iface";
	iommu-cells = <0>;
	status = "disabled";
	};

	hdmi: hdmi@200a0000 {
	compatible = "rockchip,rk3228-dw-hdmi";
	reg = <0x200a0000 0x20000>;
	reg-io-width = <4>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	assigned-clocks = <&cru SCLK_HDMI_PHY>;
	assigned-clock-parents = <&hdmi_phy>;
	clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>;
	clock-names = "isfr", "iahb", "cec";
	pinctrl-names = "default";
	pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
	resets = <&cru SRST_HDMI_P>;
	reset-names = "hdmi";
	phys = <&hdmi_phy>;
	phy-names = "hdmi";
	rockchip,grf = <&grf>;
	status = "disabled";

	ports {
	hdmi_in: port {
	#address-cells = <1>;
	#size-cells = <0>;
	hdmi_in_vop: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vop_out_hdmi>;
	};
	};
	};
	};

	sdmmc: mmc@30000000 {
	compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x30000000 0x4000>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
	<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
	status = "disabled";
	};

	sdio: mmc@30010000 {
	compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x30010000 0x4000>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
	<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
	status = "disabled";
	};

	emmc: mmc@30020000 {
	compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x30020000 0x4000>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <37500000>;
	max-frequency = <37500000>;
	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
	<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	bus-width = <8>;
	- default-sample-phase = <158>;
	+ rockchip,default-sample-phase = <158>;
	fifo-depth = <0x100>;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
	resets = <&cru SRST_EMMC>;
	reset-names = "reset";
	status = "disabled";
	};

	usb_otg: usb@30040000 {
	compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
	"snps,dwc2";
	reg = <0x30040000 0x40000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_OTG>;
	clock-names = "otg";
	dr_mode = "otg";
	g-np-tx-fifo-size = <16>;
	g-rx-fifo-size = <280>;
	g-tx-fifo-size = <256 128 128 64 32 16>;
	- g-use-dma;
	phys = <&u2phy0_otg>;
	phy-names = "usb2-phy";
	status = "disabled";
	};

	usb_host0_ehci: usb@30080000 {
	compatible = "generic-ehci";
	reg = <0x30080000 0x20000>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_HOST0>, <&u2phy0>;
	- clock-names = "usbhost", "utmi";
	phys = <&u2phy0_host>;
	phy-names = "usb";
	status = "disabled";
	};

	usb_host0_ohci: usb@300a0000 {
	compatible = "generic-ohci";
	reg = <0x300a0000 0x20000>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_HOST0>, <&u2phy0>;
	- clock-names = "usbhost", "utmi";
	phys = <&u2phy0_host>;
	phy-names = "usb";
	status = "disabled";
	};

	usb_host1_ehci: usb@300c0000 {
	compatible = "generic-ehci";
	reg = <0x300c0000 0x20000>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_HOST1>, <&u2phy1>;
	- clock-names = "usbhost", "utmi";
	phys = <&u2phy1_otg>;
	phy-names = "usb";
	status = "disabled";
	};

	usb_host1_ohci: usb@300e0000 {
	compatible = "generic-ohci";
	reg = <0x300e0000 0x20000>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_HOST1>, <&u2phy1>;
	- clock-names = "usbhost", "utmi";
	phys = <&u2phy1_otg>;
	phy-names = "usb";
	status = "disabled";
	};

	usb_host2_ehci: usb@30100000 {
	compatible = "generic-ehci";
	reg = <0x30100000 0x20000>;
	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_HOST2>, <&u2phy1>;
	phys = <&u2phy1_host>;
	phy-names = "usb";
	- clock-names = "usbhost", "utmi";
	status = "disabled";
	};

	usb_host2_ohci: usb@30120000 {
	compatible = "generic-ohci";
	reg = <0x30120000 0x20000>;
	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_HOST2>, <&u2phy1>;
	- clock-names = "usbhost", "utmi";
	phys = <&u2phy1_host>;
	phy-names = "usb";
	status = "disabled";
	};

	gmac: ethernet@30200000 {
	compatible = "rockchip,rk3228-gmac";
	reg = <0x30200000 0x10000>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
	<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
	<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
	<&cru PCLK_GMAC>;
	clock-names = "stmmaceth", "mac_clk_rx",
	"mac_clk_tx", "clk_mac_ref",
	"clk_mac_refout", "aclk_mac",
	"pclk_mac";
	resets = <&cru SRST_GMAC>;
	reset-names = "stmmaceth";
	rockchip,grf = <&grf>;
	status = "disabled";
	};

	gic: interrupt-controller@32010000 {
	compatible = "arm,gic-400";
	interrupt-controller;
	#interrupt-cells = <3>;
	#address-cells = <0>;

	reg = <0x32011000 0x1000>,
	<0x32012000 0x2000>,
	<0x32014000 0x2000>,
	<0x32016000 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	pinctrl: pinctrl {
	compatible = "rockchip,rk3228-pinctrl";
	rockchip,grf = <&grf>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	gpio0: gpio0@11110000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x11110000 0x100>;
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO0>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio1: gpio1@11120000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x11120000 0x100>;
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO1>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio2@11130000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x11130000 0x100>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO2>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio3@11140000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x11140000 0x100>;
	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO3>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	pcfg_pull_up: pcfg-pull-up {
	bias-pull-up;
	};

	pcfg_pull_down: pcfg-pull-down {
	bias-pull-down;
	};

	pcfg_pull_none: pcfg-pull-none {
	bias-disable;
	};

	pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
	drive-strength = <12>;
	};

	sdmmc {
	sdmmc_clk: sdmmc-clk {
	rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
	};

	sdmmc_cmd: sdmmc-cmd {
	rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
	};

	sdmmc_bus4: sdmmc-bus4 {
	rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
	<1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
	<1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
	<1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
	};
	};

	sdio {
	sdio_clk: sdio-clk {
	rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
	};

	sdio_cmd: sdio-cmd {
	rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
	};

	sdio_bus4: sdio-bus4 {
	rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
	<3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
	<3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
	<3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
	};
	};

	emmc {
	emmc_clk: emmc-clk {
	rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
	};

	emmc_cmd: emmc-cmd {
	rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;
	};

	emmc_bus8: emmc-bus8 {
	rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
	<1 RK_PD1 2 &pcfg_pull_none>,
	<1 RK_PD2 2 &pcfg_pull_none>,
	<1 RK_PD3 2 &pcfg_pull_none>,
	<1 RK_PD4 2 &pcfg_pull_none>,
	<1 RK_PD5 2 &pcfg_pull_none>,
	<1 RK_PD6 2 &pcfg_pull_none>,
	<1 RK_PD7 2 &pcfg_pull_none>;
	};
	};

	gmac {
	rgmii_pins: rgmii-pins {
	rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
	<2 RK_PB4 1 &pcfg_pull_none>,
	<2 RK_PD1 1 &pcfg_pull_none>,
	<2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
	<2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
	<2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,
	<2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,
	<2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,
	<2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
	<2 RK_PC1 1 &pcfg_pull_none>,
	<2 RK_PC0 1 &pcfg_pull_none>,
	<2 RK_PC5 2 &pcfg_pull_none>,
	<2 RK_PC4 2 &pcfg_pull_none>,
	<2 RK_PB3 1 &pcfg_pull_none>,
	<2 RK_PB0 1 &pcfg_pull_none>;
	};

	rmii_pins: rmii-pins {
	rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
	<2 RK_PB4 1 &pcfg_pull_none>,
	<2 RK_PD1 1 &pcfg_pull_none>,
	<2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
	<2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
	<2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
	<2 RK_PC1 1 &pcfg_pull_none>,
	<2 RK_PC0 1 &pcfg_pull_none>,
	<2 RK_PB0 1 &pcfg_pull_none>,
	<2 RK_PB7 1 &pcfg_pull_none>;
	};

	phy_pins: phy-pins {
	rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,
	<2 RK_PB0 2 &pcfg_pull_none>;
	};
	};

	hdmi {
	hdmi_hpd: hdmi-hpd {
	rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
	};

	hdmii2c_xfer: hdmii2c-xfer {
	rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
	<0 RK_PA7 2 &pcfg_pull_none>;
	};

	hdmi_cec: hdmi-cec {
	rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
	};
	};

	i2c0 {
	i2c0_xfer: i2c0-xfer {
	rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
	<0 RK_PA1 1 &pcfg_pull_none>;
	};
	};

	i2c1 {
	i2c1_xfer: i2c1-xfer {
	rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
	<0 RK_PA3 1 &pcfg_pull_none>;
	};
	};

	i2c2 {
	i2c2_xfer: i2c2-xfer {
	rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
	<2 RK_PC5 1 &pcfg_pull_none>;
	};
	};

	i2c3 {
	i2c3_xfer: i2c3-xfer {
	rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
	<0 RK_PA7 1 &pcfg_pull_none>;
	};
	};

	- spi-0 {
	+ spi0 {
	spi0_clk: spi0-clk {
	rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
	};
	spi0_cs0: spi0-cs0 {
	rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
	};
	spi0_tx: spi0-tx {
	rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
	};
	spi0_rx: spi0-rx {
	rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
	};
	spi0_cs1: spi0-cs1 {
	rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
	};
	};

	- spi-1 {
	+ spi1 {
	spi1_clk: spi1-clk {
	rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
	};
	spi1_cs0: spi1-cs0 {
	rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;
	};
	spi1_rx: spi1-rx {
	rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
	};
	spi1_tx: spi1-tx {
	rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;
	};
	spi1_cs1: spi1-cs1 {
	rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;
	};
	};

	i2s1 {
	i2s1_bus: i2s1-bus {
	rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
	<0 RK_PB1 1 &pcfg_pull_none>,
	<0 RK_PB3 1 &pcfg_pull_none>,
	<0 RK_PB4 1 &pcfg_pull_none>,
	<0 RK_PB5 1 &pcfg_pull_none>,
	<0 RK_PB6 1 &pcfg_pull_none>,
	<1 RK_PA2 2 &pcfg_pull_none>,
	<1 RK_PA4 2 &pcfg_pull_none>,
	<1 RK_PA5 2 &pcfg_pull_none>;
	};
	};

	pwm0 {
	pwm0_pin: pwm0-pin {
	rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
	};
	};

	pwm1 {
	pwm1_pin: pwm1-pin {
	rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
	};
	};

	pwm2 {
	pwm2_pin: pwm2-pin {
	rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
	};
	};

	pwm3 {
	pwm3_pin: pwm3-pin {
	rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
	};
	};

	spdif {
	spdif_tx: spdif-tx {
	rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;
	};
	};

	tsadc {
	otp_gpio: otp-gpio {
	rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	otp_out: otp-out {
	rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
	};
	};

	uart0 {
	uart0_xfer: uart0-xfer {
	rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
	<2 RK_PD3 1 &pcfg_pull_none>;
	};

	uart0_cts: uart0-cts {
	rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;
	};

	uart0_rts: uart0-rts {
	rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
	};
	};

	uart1 {
	uart1_xfer: uart1-xfer {
	rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
	<1 RK_PB2 1 &pcfg_pull_none>;
	};

	uart1_cts: uart1-cts {
	rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
	};

	uart1_rts: uart1-rts {
	rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
	};
	};

	uart2 {
	uart2_xfer: uart2-xfer {
	rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
	<1 RK_PC3 2 &pcfg_pull_none>;
	};

	uart21_xfer: uart21-xfer {
	rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
	<1 RK_PB1 2 &pcfg_pull_none>;
	};

	uart2_cts: uart2-cts {
	rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
	};

	uart2_rts: uart2-rts {
	rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/rk3288-evb-act8846.dts b/sys/gnu/dts/arm/rk3288-evb-act8846.dts
	index 80080767c365..be695b8c1f67 100644
	--- a/sys/gnu/dts/arm/rk3288-evb-act8846.dts
	+++ b/sys/gnu/dts/arm/rk3288-evb-act8846.dts
	@@ -1,187 +1,188 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

	/dts-v1/;
	#include "rk3288-evb.dtsi"

	/ {
	+ model = "Rockchip RK3288 EVB ACT8846";
	compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288";

	vcc_lcd: vcc-lcd {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio7 RK_PA3 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&lcd_en>;
	regulator-name = "vcc_lcd";
	vin-supply = <&vcc_io>;
	};

	vcc_wl: vcc-wl {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio7 RK_PB1 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&wifi_pwr>;
	regulator-name = "vcc_wl";
	vin-supply = <&vcc_18>;
	};
	};

	&i2c0 {
	clock-frequency = <400000>;

	vdd_cpu: syr827@40 {
	compatible = "silergy,syr827";
	fcs,suspend-voltage-selector = <1>;
	reg = <0x40>;
	regulator-name = "vdd_cpu";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vcc_sys>;
	};

	vdd_gpu: syr828@41 {
	compatible = "silergy,syr828";
	fcs,suspend-voltage-selector = <1>;
	reg = <0x41>;
	regulator-name = "vdd_gpu";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	vin-supply = <&vcc_sys>;
	};

	hym8563@51 {
	compatible = "haoyu,hym8563";
	reg = <0x51>;

	interrupt-parent = <&gpio0>;
	interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;

	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int>;

	#clock-cells = <0>;
	clock-output-names = "xin32k";
	};

	act8846: act8846@5a {
	compatible = "active-semi,act8846";
	reg = <0x5a>;
	status = "okay";

	vp1-supply = <&vcc_sys>;
	vp2-supply = <&vcc_sys>;
	vp3-supply = <&vcc_sys>;
	vp4-supply = <&vcc_sys>;
	inl1-supply = <&vcc_io>;
	inl2-supply = <&vcc_sys>;
	inl3-supply = <&vcc_20>;

	regulators {
	vcc_ddr: REG1 {
	regulator-name = "VCC_DDR";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	vcc_io: REG2 {
	regulator-name = "VCC_IO";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vdd_log: REG3 {
	regulator-name = "VDD_LOG";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;
	};

	vcc_20: REG4 {
	regulator-name = "VCC_20";
	regulator-min-microvolt = <2000000>;
	regulator-max-microvolt = <2000000>;
	regulator-always-on;
	};

	vccio_sd: REG5 {
	regulator-name = "VCCIO_SD";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vdd10_lcd: REG6 {
	regulator-name = "VDD10_LCD";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	vcca_codec: REG7 {
	regulator-name = "VCCA_CODEC";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vcc_tp: REG8 {
	regulator-name = "VCCA_TP";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vccio_pmu: REG9 {
	regulator-name = "VCCIO_PMU";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vdd_10: REG10 {
	regulator-name = "VDD_10";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	vcc_18: REG11 {
	regulator-name = "VCC_18";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	vcc18_lcd: REG12 {
	regulator-name = "VCC18_LCD";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};
	};
	};
	};

	&panel {
	power-supply = <&vcc_lcd>;
	};

	&pinctrl {
	lcd {
	lcd_en: lcd-en {
	rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	wifi {
	wifi_pwr: wifi-pwr {
	rockchip,pins = <7 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/rk3288-evb-rk808.dts b/sys/gnu/dts/arm/rk3288-evb-rk808.dts
	index 16788209625b..42384ea4ca21 100644
	--- a/sys/gnu/dts/arm/rk3288-evb-rk808.dts
	+++ b/sys/gnu/dts/arm/rk3288-evb-rk808.dts
	@@ -1,201 +1,202 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

	/dts-v1/;
	#include "rk3288-evb.dtsi"

	/ {
	+ model = "Rockchip RK3288 EVB RK808";
	compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
	};

	&i2c0 {
	clock-frequency = <400000>;

	rk808: pmic@1b {
	compatible = "rockchip,rk808";
	reg = <0x1b>;
	interrupt-parent = <&gpio0>;
	interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int &global_pwroff>;
	rockchip,system-power-controller;
	wakeup-source;
	#clock-cells = <1>;
	clock-output-names = "xin32k", "rk808-clkout2";

	vcc1-supply = <&vcc_sys>;
	vcc2-supply = <&vcc_sys>;
	vcc3-supply = <&vcc_sys>;
	vcc4-supply = <&vcc_sys>;
	vcc6-supply = <&vcc_sys>;
	vcc7-supply = <&vcc_sys>;
	vcc8-supply = <&vcc_18>;
	vcc9-supply = <&vcc_io>;
	vcc10-supply = <&vcc_io>;
	vcc11-supply = <&vcc_sys>;
	vcc12-supply = <&vcc_io>;
	vddio-supply = <&vccio_pmu>;

	regulators {
	vdd_cpu: DCDC_REG1 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <1350000>;
	regulator-name = "vdd_arm";
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_gpu: DCDC_REG2 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1250000>;
	regulator-name = "vdd_gpu";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1000000>;
	};
	};

	vcc_ddr: DCDC_REG3 {
	regulator-always-on;
	regulator-boot-on;
	regulator-name = "vcc_ddr";
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	vcc_io: DCDC_REG4 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc_io";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3300000>;
	};
	};

	vccio_pmu: LDO_REG1 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vccio_pmu";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3300000>;
	};
	};

	vcc_tp: LDO_REG2 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc_tp";
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_10: LDO_REG3 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-name = "vdd_10";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1000000>;
	};
	};

	vcc18_lcd: LDO_REG4 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc18_lcd";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vccio_sd: LDO_REG5 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vccio_sd";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3300000>;
	};
	};

	vdd10_lcd: LDO_REG6 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-name = "vdd10_lcd";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1000000>;
	};
	};

	vcc_18: LDO_REG7 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc_18";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcca_codec: LDO_REG8 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcca_codec";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3300000>;
	};
	};

	vcc_wl: SWITCH_REG1 {
	regulator-always-on;
	regulator-boot-on;
	regulator-name = "vcc_wl";
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	vcc_lcd: SWITCH_REG2 {
	regulator-always-on;
	regulator-boot-on;
	regulator-name = "vcc_lcd";
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};
	};
	};
	};

	&panel {
	power-supply = <&vcc_lcd>;
	};
	diff --git a/sys/gnu/dts/arm/rk3288-firefly-reload.dts b/sys/gnu/dts/arm/rk3288-firefly-reload.dts
	index 1574383fd2dc..8c38bda21a7c 100644
	--- a/sys/gnu/dts/arm/rk3288-firefly-reload.dts
	+++ b/sys/gnu/dts/arm/rk3288-firefly-reload.dts
	@@ -1,391 +1,392 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Device tree file for Firefly Rockchip RK3288 Core board
	* Copyright (c) 2016 Randy Li <ayaka@soulik.info>
	*/

	/dts-v1/;
	#include "rk3288-firefly-reload-core.dtsi"

	/ {
	model = "Firefly-RK3288-reload";
	compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288";

	adc-keys {
	compatible = "adc-keys";
	io-channels = <&saradc 1>;
	io-channel-names = "buttons";
	keyup-threshold-microvolt = <1800000>;

	button-recovery {
	label = "Recovery";
	linux,code = <KEY_VENDOR>;
	press-threshold-microvolt = <0>;
	};
	};

	gpio-keys {
	compatible = "gpio-keys";

	power {
	wakeup-source;
	gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
	label = "GPIO Power";
	linux,code = <KEY_POWER>;
	pinctrl-names = "default";
	pinctrl-0 = <&pwr_key>;
	};
	};

	ir-receiver {
	compatible = "gpio-ir-receiver";
	gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>;
	};

	leds {
	compatible = "gpio-leds";

	power {
	gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>;
	label = "firefly:blue:power";
	pinctrl-names = "default";
	pinctrl-0 = <&power_led>;
	panic-indicator;
	};

	work {
	gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>;
	label = "firefly:blue:user";
	linux,default-trigger = "rc-feedback";
	pinctrl-names = "default";
	pinctrl-0 = <&work_led>;
	};
	};

	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	clocks = <&hym8563>;
	clock-names = "ext_clock";
	pinctrl-names = "default";
	pinctrl-0 = <&wifi_enable>;
	reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
	};

	sound {
	compatible = "simple-audio-card";
	simple-audio-card,name = "SPDIF";
	simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */
	cpu { sound-dai = <&spdif>; };
	codec { sound-dai = <&spdif_out>; };
	};
	};

	spdif_out: spdif-out {
	compatible = "linux,spdif-dit";
	#sound-dai-cells = <0>;
	};

	vcc_host_5v: usb-host-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&host_vbus_drv>;
	regulator-name = "vcc_host_5v";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	vin-supply = <&vcc_5v>;
	};

	vcc_5v: vcc_sys: vsys-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vcc_5v";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vcc_sd: sdmmc-regulator {
	compatible = "regulator-fixed";
	gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_pwr>;
	regulator-name = "vcc_sd";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	startup-delay-us = <100000>;
	vin-supply = <&vcc_io>;
	};

	vcc_otg_5v: usb-otg-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&otg_vbus_drv>;
	regulator-name = "vcc_otg_5v";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	vin-supply = <&vcc_5v>;
	};

	dovdd_1v8: dovdd-1v8-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&dvp_pwr>;
	regulator-name = "dovdd_1v8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vcc_io>;
	};

	vcc28_dvp: vcc28-dvp-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&dvp_pwr>;
	regulator-name = "vcc28_dvp";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	vin-supply = <&vcc_io>;
	};

	af_28: af_28-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&dvp_pwr>;
	regulator-name = "af_28";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	vin-supply = <&vcc_io>;
	};

	dvdd_1v2: af_28-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&cif_pwr>;
	regulator-name = "dvdd_1v2";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	vin-supply = <&vcc_io>;
	};

	vbat_wl: wifi-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vbat_wl";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vcc_io>;
	};
	};

	&hdmi {
	ddc-i2c-bus = <&i2c5>;
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_cec_c0>;
	status = "okay";
	};

	&i2c0 {
	hym8563: hym8563@51 {
	compatible = "haoyu,hym8563";
	reg = <0x51>;
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "xin32k";
	interrupt-parent = <&gpio7>;
	interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
	pinctrl-names = "default";
	pinctrl-0 = <&rtc_int>;
	};
	};

	&i2c2 {
	status = "okay";

	codec: es8328@10 {
	compatible = "everest,es8328";
	DVDD-supply = <&vcca_33>;
	AVDD-supply = <&vcca_33>;
	PVDD-supply = <&vcca_33>;
	HPVDD-supply = <&vcca_33>;
	clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
	clock-names = "i2s_hclk", "i2s_clk";
	reg = <0x10>;
	};
	};

	&i2c5 {
	status = "okay";
	};

	&i2s {
	status = "okay";
	};

	&saradc {
	+ vref-supply = <&vcc_18>;
	status = "okay";
	};

	&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	card-detect-delay = <200>;
	disable-wp;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
	vmmc-supply = <&vcc_sd>;
	vqmmc-supply = <&vccio_sd>;
	status = "okay";
	};

	&sdio0 {
	bus-width = <4>;
	cap-sd-highspeed;
	cap-sdio-irq;
	mmc-pwrseq = <&sdio_pwrseq>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-ddr50;
	vmmc-supply = <&vbat_wl>;
	vqmmc-supply = <&vccio_wl>;
	status = "okay";
	};

	&spdif {
	status = "okay";
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
	status = "okay";
	};

	&uart1 {
	status = "okay";
	};

	&uart2 {
	status = "okay";
	};

	&uart3 {
	status = "okay";
	};

	&usbphy {
	status = "okay";
	};

	&usb_host1 {
	pinctrl-names = "default";
	pinctrl-0 = <&usbhub_rst>;
	status = "okay";
	};

	&usb_otg {
	status = "okay";
	};

	&pinctrl {
	ir {
	ir_int: ir-int {
	rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	dvp {
	dvp_pwr: dvp-pwr {
	rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	cif_pwr: cif-pwr {
	rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	hym8563 {
	rtc_int: rtc-int {
	rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	keys {
	pwr_key: pwr-key {
	rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	leds {
	power_led: power-led {
	rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	work_led: work-led {
	rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	sdmmc {
	/*
	* Default drive strength isn't enough to achieve even
	* high-speed mode on firefly board so bump up to 12ma.
	*/
	sdmmc_bus4: sdmmc-bus4 {
	rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>,
	<6 RK_PC1 1 &pcfg_pull_up_drv_12ma>,
	<6 RK_PC2 1 &pcfg_pull_up_drv_12ma>,
	<6 RK_PC3 1 &pcfg_pull_up_drv_12ma>;
	};

	sdmmc_clk: sdmmc-clk {
	rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>;
	};

	sdmmc_cmd: sdmmc-cmd {
	rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>;
	};

	sdmmc_pwr: sdmmc-pwr {
	rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	sdio {
	wifi_enable: wifi-enable {
	rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	usb_host {
	host_vbus_drv: host-vbus-drv {
	rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	usbhub_rst: usbhub-rst {
	rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>;
	};
	};

	usb_otg {
	otg_vbus_drv: otg-vbus-drv {
	rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/rk3288-r89.dts b/sys/gnu/dts/arm/rk3288-r89.dts
	index a6ffc381abaa..a258c7ae5329 100644
	--- a/sys/gnu/dts/arm/rk3288-r89.dts
	+++ b/sys/gnu/dts/arm/rk3288-r89.dts
	@@ -1,387 +1,388 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
	*/

	/dts-v1/;
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/pwm/pwm.h>
	#include "rk3288.dtsi"

	/ {
	+ model = "Netxeon R89";
	compatible = "netxeon,r89", "rockchip,rk3288";

	memory@0 {
	device_type = "memory";
	reg = <0x0 0x0 0x0 0x80000000>;
	};

	ext_gmac: external-gmac-clock {
	compatible = "fixed-clock";
	clock-frequency = <125000000>;
	clock-output-names = "ext_gmac";
	#clock-cells = <0>;
	};

	gpio-keys {
	compatible = "gpio-keys";
	autorepeat;

	pinctrl-names = "default";
	pinctrl-0 = <&pwrbtn>;

	power {
	gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_POWER>;
	label = "GPIO Key Power";
	linux,input-type = <1>;
	wakeup-source;
	debounce-interval = <100>;
	};
	};

	ir: ir-receiver {
	compatible = "gpio-ir-receiver";
	gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&ir_int>;
	};

	vcc_host: vcc-host-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&host_vbus_drv>;
	regulator-name = "vcc_host";
	regulator-always-on;
	regulator-boot-on;
	};

	vcc_otg: vcc-otg-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&otg_vbus_drv>;
	regulator-name = "vcc_otg";
	regulator-always-on;
	regulator-boot-on;
	};

	vcc_sdmmc: sdmmc-regulator {
	compatible = "regulator-fixed";
	regulator-name = "sdmmc-supply";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
	startup-delay-us = <100000>;
	vin-supply = <&vcc_io>;
	};

	vcc_sys: sys-regulator {
	compatible = "regulator-fixed";
	regulator-name = "sys-supply";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	};
	};

	&cpu0 {
	cpu0-supply = <&vdd_cpu>;
	};

	&gmac {
	phy-supply = <&vcc_lan>;
	phy-mode = "rgmii";
	clock_in_out = "input";
	snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
	snps,reset-active-low;
	snps,reset-delays-us = <0 10000 1000000>;
	assigned-clocks = <&cru SCLK_MAC>;
	assigned-clock-parents = <&ext_gmac>;
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins>;
	tx_delay = <0x30>;
	rx_delay = <0x10>;
	status = "ok";
	};

	&hdmi {
	status = "okay";
	};

	&i2c0 {
	status = "okay";

	vdd_cpu: pmic@40 {
	compatible = "silergy,syr827";
	reg = <0x40>;
	fcs,suspend-voltage-selector = <1>;
	regulator-name = "VDD_CPU";
	regulator-enable-ramp-delay = <300>;
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1350000>;
	regulator-ramp-delay = <8000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vcc_sys>;
	};

	vdd_gpu: pmic@41 {
	compatible = "silergy,syr828";
	reg = <0x41>;
	fcs,suspend-voltage-selector = <1>;
	regulator-name = "VDD_GPU";
	regulator-enable-ramp-delay = <300>;
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1350000>;
	regulator-ramp-delay = <8000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vcc_sys>;
	};

	rtc@51 {
	compatible = "haoyu,hym8563";
	reg = <0x51>;
	#clock-cells = <0>;
	clock-output-names = "xin32k";
	interrupt-parent = <&gpio0>;
	interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int>;
	};

	act8846: pmic@5a {
	compatible = "active-semi,act8846";
	reg = <0x5a>;
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_vsel>, <&pwr_hold>;
	system-power-controller;

	regulators {
	vcc_ddr: REG1 {
	regulator-name = "VCC_DDR";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	vcc_io: REG2 {
	regulator-name = "VCC_IO";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vdd_log: REG3 {
	regulator-name = "VDD_LOG";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	vcc_20: REG4 {
	regulator-name = "VCC_20";
	regulator-min-microvolt = <2000000>;
	regulator-max-microvolt = <2000000>;
	regulator-always-on;
	};

	vccio_sd: REG5 {
	regulator-name = "VCCIO_SD";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vdd10_lcd: REG6 {
	regulator-name = "VDD10_LCD";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	vcc_wl: REG7 {
	regulator-name = "VCC_WL";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vcca_33: REG8 {
	regulator-name = "VCCA_33";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vcc_lan: REG9 {
	regulator-name = "VCC_LAN";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vdd_10: REG10 {
	regulator-name = "VDD_10";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	vcc_18: REG11 {
	regulator-name = "VCC_18";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	vcc18_lcd: REG12 {
	regulator-name = "VCC18_LCD";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};
	};
	};
	};

	&i2c5 {
	status = "okay";
	};

	&pinctrl {
	pcfg_output_high: pcfg-output-high {
	output-high;
	};

	pcfg_output_low: pcfg-output-low {
	output-low;
	};

	act8846 {
	pmic_vsel: pmic-vsel {
	rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>;
	};

	pwr_hold: pwr-hold {
	rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>;
	};
	};

	buttons {
	pwrbtn: pwrbtn {
	rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	ir {
	ir_int: ir-int {
	rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	pmic {
	pmic_int: pmic-int {
	rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	usb {
	host_vbus_drv: host-vbus-drv {
	rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	otg_vbus_drv: otg-vbus-drv {
	rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};
	};

	&pwm0 {
	status = "okay";
	};

	&saradc {
	vref-supply = <&vcc_18>;
	status = "okay";
	};

	&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	card-detect-delay = <200>;
	disable-wp;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
	vmmc-supply = <&vcc_sdmmc>;
	vqmmc-supply = <&vccio_sd>;
	status = "okay";
	};

	&tsadc {
	rockchip,hw-tshut-mode = <0>;
	rockchip,hw-tshut-polarity = <0>;
	status = "okay";
	};

	&uart0 {
	status = "okay";
	};

	&uart1 {
	status = "okay";
	};

	&uart2 {
	status = "okay";
	};

	&uart3 {
	status = "okay";
	};

	&uart4 {
	status = "okay";
	};

	&usb_host0_ehci {
	status = "okay";
	};

	&usb_host1 {
	status = "okay";
	};

	&usb_otg {
	status = "okay";
	};

	&usbphy {
	status = "okay";
	};

	&vopb {
	status = "okay";
	};

	&vopb_mmu {
	status = "okay";
	};

	&vopl {
	status = "okay";
	};

	&vopl_mmu {
	status = "okay";
	};

	&wdt {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/rk3288-tinker.dtsi b/sys/gnu/dts/arm/rk3288-tinker.dtsi
	index 312582c1bd37..acfaa12ec239 100644
	--- a/sys/gnu/dts/arm/rk3288-tinker.dtsi
	+++ b/sys/gnu/dts/arm/rk3288-tinker.dtsi
	@@ -1,547 +1,548 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
	*/

	#include "rk3288.dtsi"
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/clock/rockchip,rk808.h>

	/ {
	chosen {
	stdout-path = "serial2:115200n8";
	};

	memory {
	reg = <0x0 0x0 0x0 0x80000000>;
	device_type = "memory";
	};

	ext_gmac: external-gmac-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <125000000>;
	clock-output-names = "ext_gmac";
	};

	gpio-keys {
	compatible = "gpio-keys";
	#address-cells = <1>;
	#size-cells = <0>;
	autorepeat;

	pinctrl-names = "default";
	pinctrl-0 = <&pwrbtn>;

	button@0 {
	gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_POWER>;
	label = "GPIO Key Power";
	linux,input-type = <1>;
	wakeup-source;
	debounce-interval = <100>;
	};
	};

	gpio-leds {
	compatible = "gpio-leds";

	act-led {
	gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "mmc0";
	};

	heartbeat-led {
	gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	};

	pwr-led {
	gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "default-on";
	};
	};

	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	clocks = <&rk808 RK808_CLKOUT1>;
	clock-names = "ext_clock";
	pinctrl-names = "default";
	pinctrl-0 = <&wifi_enable>;
	reset-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>,
	<&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
	};

	sound {
	compatible = "simple-audio-card";
	simple-audio-card,format = "i2s";
	simple-audio-card,name = "rockchip,tinker-codec";
	simple-audio-card,mclk-fs = <512>;

	simple-audio-card,codec {
	sound-dai = <&hdmi>;
	};

	simple-audio-card,cpu {
	sound-dai = <&i2s>;
	};
	};

	vcc_sys: vsys-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vcc_sys";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vcc_sd: sdmmc-regulator {
	compatible = "regulator-fixed";
	gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_pwr>;
	regulator-name = "vcc_sd";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	startup-delay-us = <100000>;
	vin-supply = <&vcc_io>;
	};
	};

	&cpu0 {
	cpu0-supply = <&vdd_cpu>;
	};

	&cpu_opp_table {
	opp-1704000000 {
	opp-hz = /bits/ 64 <1704000000>;
	opp-microvolt = <1350000>;
	};
	opp-1800000000 {
	opp-hz = /bits/ 64 <1800000000>;
	opp-microvolt = <1400000>;
	};
	};

	&gmac {
	assigned-clocks = <&cru SCLK_MAC>;
	assigned-clock-parents = <&ext_gmac>;
	clock_in_out = "input";
	phy-mode = "rgmii";
	phy-supply = <&vcc33_lan>;
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins>;
	snps,reset-gpio = <&gpio4 7 0>;
	snps,reset-active-low;
	snps,reset-delays-us = <0 10000 1000000>;
	tx_delay = <0x30>;
	rx_delay = <0x10>;
	status = "ok";
	};

	&gpu {
	mali-supply = <&vdd_gpu>;
	status = "okay";
	};

	&hdmi {
	ddc-i2c-bus = <&i2c5>;
	status = "okay";
	};

	&i2c0 {
	clock-frequency = <400000>;
	status = "okay";

	rk808: pmic@1b {
	compatible = "rockchip,rk808";
	reg = <0x1b>;
	interrupt-parent = <&gpio0>;
	interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
	#clock-cells = <1>;
	clock-output-names = "xin32k", "rk808-clkout2";
	dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
	<&gpio0 12 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>;
	rockchip,system-power-controller;
	wakeup-source;

	vcc1-supply = <&vcc_sys>;
	vcc2-supply = <&vcc_sys>;
	vcc3-supply = <&vcc_sys>;
	vcc4-supply = <&vcc_sys>;
	vcc6-supply = <&vcc_sys>;
	vcc7-supply = <&vcc_sys>;
	vcc8-supply = <&vcc_io>;
	vcc9-supply = <&vcc_io>;
	vcc10-supply = <&vcc_io>;
	vcc11-supply = <&vcc_sys>;
	vcc12-supply = <&vcc_io>;
	vddio-supply = <&vcc_io>;

	regulators {
	vdd_cpu: DCDC_REG1 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <1400000>;
	regulator-name = "vdd_arm";
	regulator-ramp-delay = <6000>;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_gpu: DCDC_REG2 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1250000>;
	regulator-name = "vdd_gpu";
	regulator-ramp-delay = <6000>;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1000000>;
	};
	};

	vcc_ddr: DCDC_REG3 {
	regulator-always-on;
	regulator-boot-on;
	regulator-name = "vcc_ddr";
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	vcc_io: DCDC_REG4 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc_io";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3300000>;
	};
	};

	vcc18_ldo1: LDO_REG1 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc18_ldo1";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc33_mipi: LDO_REG2 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc33_mipi";
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_10: LDO_REG3 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-name = "vdd_10";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1000000>;
	};
	};

	vcc18_codec: LDO_REG4 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc18_codec";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vccio_sd: LDO_REG5 {
	+ regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vccio_sd";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3300000>;
	};
	};

	vdd10_lcd: LDO_REG6 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-name = "vdd10_lcd";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1000000>;
	};
	};

	vcc_18: LDO_REG7 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc_18";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc18_lcd: LDO_REG8 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc18_lcd";
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc33_sd: SWITCH_REG1 {
	regulator-always-on;
	regulator-boot-on;
	regulator-name = "vcc33_sd";
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	vcc33_lan: SWITCH_REG2 {
	regulator-always-on;
	regulator-boot-on;
	regulator-name = "vcc33_lan";
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};
	};
	};
	};

	&i2c2 {
	status = "okay";
	};

	&i2c5 {
	status = "okay";
	};

	&i2s {
	#sound-dai-cells = <0>;
	status = "okay";
	};

	&io_domains {
	status = "okay";

	sdcard-supply = <&vccio_sd>;
	wifi-supply = <&vcc_18>;
	};

	&pinctrl {
	pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
	drive-strength = <8>;
	};

	pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
	bias-pull-up;
	drive-strength = <8>;
	};

	backlight {
	bl_en: bl-en {
	rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	buttons {
	pwrbtn: pwrbtn {
	rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	eth_phy {
	eth_phy_pwr: eth-phy-pwr {
	rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	pmic {
	pmic_int: pmic-int {
	rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
	};

	dvs_1: dvs-1 {
	rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
	};

	dvs_2: dvs-2 {
	rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
	};
	};

	sdmmc {
	sdmmc_bus4: sdmmc-bus4 {
	rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>,
	<6 RK_PC1 1 &pcfg_pull_up_drv_8ma>,
	<6 RK_PC2 1 &pcfg_pull_up_drv_8ma>,
	<6 RK_PC3 1 &pcfg_pull_up_drv_8ma>;
	};

	sdmmc_clk: sdmmc-clk {
	rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
	};

	sdmmc_cmd: sdmmc-cmd {
	rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>;
	};

	sdmmc_pwr: sdmmc-pwr {
	rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	usb {
	host_vbus_drv: host-vbus-drv {
	rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	pwr_3g: pwr-3g {
	rockchip,pins = <7 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	sdio {
	wifi_enable: wifi-enable {
	rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
	<4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};
	};

	&pwm0 {
	status = "okay";
	};

	&saradc {
	vref-supply = <&vcc18_ldo1>;
	status = "okay";
	};

	&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	broken-cd;
	disable-wp; /* wp not hooked up */
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
	status = "okay";
	vmmc-supply = <&vcc33_sd>;
	vqmmc-supply = <&vccio_sd>;
	};

	&sdio0 {
	bus-width = <4>;
	cap-sd-highspeed;
	cap-sdio-irq;
	keep-power-in-suspend;
	max-frequency = <50000000>;
	mmc-pwrseq = <&sdio_pwrseq>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	vmmc-supply = <&vcc_io>;
	vqmmc-supply = <&vcc_18>;
	status = "okay";
	};

	&tsadc {
	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
	status = "okay";
	};

	&uart0 {
	status = "okay";
	};

	&uart1 {
	status = "okay";
	};

	&uart2 {
	status = "okay";
	};

	&uart3 {
	status = "okay";
	};

	&uart4 {
	status = "okay";
	};

	&usbphy {
	status = "okay";
	};

	&usb_host0_ehci {
	status = "okay";
	};

	&usb_host1 {
	status = "okay";
	};

	&usb_otg {
	status = "okay";
	};

	&vopb {
	status = "okay";
	};

	&vopb_mmu {
	status = "okay";
	};

	&vopl {
	status = "okay";
	};

	&vopl_mmu {
	status = "okay";
	};

	&wdt {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/rk3288-vyasa.dts b/sys/gnu/dts/arm/rk3288-vyasa.dts
	index ba06e9f97ddc..385dd59393e1 100644
	--- a/sys/gnu/dts/arm/rk3288-vyasa.dts
	+++ b/sys/gnu/dts/arm/rk3288-vyasa.dts
	@@ -1,471 +1,489 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
	*/

	/dts-v1/;
	#include "rk3288.dtsi"

	/ {
	model = "Amarula Vyasa-RK3288";
	compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";

	chosen {
	stdout-path = &uart2;
	};

	memory {
	reg = <0x0 0x0 0x0 0x80000000>;
	device_type = "memory";
	};

	dc12_vbat: dc12-vbat {
	compatible = "regulator-fixed";
	regulator-name = "dc12_vbat";
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vboot_3v3: vboot-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "vboot_3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&dc12_vbat>;
	};

	vcc_sys: vsys-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vcc_sys";
	regulator-min-microvolt = <3700000>;
	regulator-max-microvolt = <3700000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&dc12_vbat>;
	};

	vboot_5v: vboot-5v {
	compatible = "regulator-fixed";
	regulator-name = "vboot_sv";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&dc12_vbat>;
	};

	v3g_3v3: v3g-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "v3g_3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&dc12_vbat>;
	};

	vsus_5v: vsus-5v {
	compatible = "regulator-fixed";
	regulator-name = "vsus_5v";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vcc_io>;
	};

	+ vcc50_hdmi: vcc50-hdmi {
	+ compatible = "regulator-fixed";
	+ regulator-name = "vcc50_hdmi";
	+ enable-active-high;
	+ gpio = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>; /* HDMI_EN */
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&vcc50_hdmi_en>;
	+ regulator-always-on;
	+ regulator-boot-on;
	+ vin-supply = <&vsus_5v>;
	+ };
	+
	vusb1_5v: vusb1-5v {
	compatible = "regulator-fixed";
	regulator-name = "vusb1_5v";
	enable-active-high;
	gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; /* OTG_VBUS_DRV */
	pinctrl-names = "default";
	pinctrl-0 = <&otg_vbus_drv>;
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vsus_5v>;
	};

	vusb2_5v: vusb2-5v {
	compatible = "regulator-fixed";
	regulator-name = "vusb2_5v";
	enable-active-high;
	gpio = <&gpio8 RK_PB1 GPIO_ACTIVE_HIGH>; /* USB2_PWR_EN */
	pinctrl-names = "default";
	pinctrl-0 = <&usb2_pwr_en>;
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vsus_5v>;
	};

	ext_gmac: external-gmac-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <125000000>;
	clock-output-names = "ext_gmac";
	};
	};

	&cpu0 {
	cpu0-supply = <&vdd_cpu>;
	};

	&emmc {
	bus-width = <8>;
	cap-mmc-highspeed;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
	vmmc-supply = <&vcc_io>;
	status = "okay";
	};

	&gmac {
	assigned-clocks = <&cru SCLK_MAC>;
	assigned-clock-parents = <&ext_gmac>;
	clock_in_out = "input";
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
	phy-supply = <&vcc_lan>;
	phy-mode = "rgmii";
	snps,reset-active-low;
	snps,reset-delays-us = <0 10000 1000000>;
	snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
	tx_delay = <0x30>;
	rx_delay = <0x10>;
	status = "okay";
	};

	&gpu {
	mali-supply = <&vdd_gpu>;
	status = "okay";
	};

	&hdmi {
	- ddc-i2c-bus = <&i2c2>;
	+ ddc-i2c-bus = <&i2c5>;
	status = "okay";
	};

	&i2c0 {
	clock-frequency = <400000>;
	status = "okay";

	rk808: pmic@1b {
	compatible = "rockchip,rk808";
	reg = <0x1b>;
	interrupt-parent = <&gpio0>;
	interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
	#clock-cells = <1>;
	clock-output-names = "xin32k", "rk808-clkout2";
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int &global_pwroff>;
	rockchip,system-power-controller;
	wakeup-source;

	vcc1-supply = <&vcc_sys>;
	vcc2-supply = <&vcc_sys>;
	vcc3-supply = <&vcc_sys>;
	vcc4-supply = <&vcc_sys>;
	vcc6-supply = <&vcc_sys>;
	vcc7-supply = <&vcc_sys>;
	vcc8-supply = <&vcc_io>;
	vcc9-supply = <&vcc_sys>;
	vcc10-supply = <&vcc_sys>;
	vcc11-supply = <&vcc_sys>;
	vcc12-supply = <&vcc_io>;

	regulators {
	vdd_cpu: DCDC_REG1 {
	regulator-name = "vdd_arm";
	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_gpu: DCDC_REG2 {
	regulator-name = "vdd_gpu";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1250000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1000000>;
	};
	};

	vcc_ddr: DCDC_REG3 {
	regulator-name = "vcc_ddr";
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	vcc_io: DCDC_REG4 {
	regulator-name = "vcc_io";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3300000>;
	};
	};

	vcca_tp: LDO_REG1 {
	regulator-name = "vcc_tp";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3300000>;
	};
	};

	vcc_codec: LDO_REG2 {
	regulator-name = "vcc_codec";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_10: LDO_REG3 {
	regulator-name = "vdd_10";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1000000>;
	};
	};

	vcc_gps: LDO_REG4 {
	regulator-name = "vcc_gps";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vccio_sd: LDO_REG5 {
	regulator-name = "vccio_sd";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3300000>;
	};
	};

	- vcc10_lcd: LDO_REG6 {
	- regulator-name = "vcc10_lcd";
	+ vdd10_lcd: LDO_REG6 {
	+ regulator-name = "vdd10_lcd";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	- regulator-suspend-microvolt = <1800000>;
	+ regulator-suspend-microvolt = <1000000>;
	};
	};

	vcc_18: LDO_REG7 {
	regulator-name = "vcc_18";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc18_lcd: LDO_REG8 {
	regulator-name = "vcc18_lcd";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc_sd: SWITCH_REG1 {
	regulator-name = "vcc_sd";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	vcc_lan: SWITCH_REG2 {
	regulator-name = "vcc_lan";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};
	};
	};
	};

	-&i2c2 {
	+&i2c5 {
	status = "okay";
	};

	&io_domains {
	status = "okay";

	audio-supply = <&vcc_18>;
	bb-supply = <&vcc_io>;
	dvp-supply = <&vcc_io>;
	flash0-suuply = <&vcc_18>;
	flash1-supply = <&vcc_lan>;
	gpio30-supply = <&vcc_io>;
	gpio1830 = <&vcc_io>;
	lcdc-supply = <&vcc_io>;
	sdcard-supply = <&vccio_sd>;
	wifi-supply = <&vcc_18>;
	};

	&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	card-detect-delay = <200>;
	disable-wp;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
	vmmc-supply = <&vcc_sd>;
	vqmmc-supply = <&vccio_sd>;
	status = "okay";
	};

	&tsadc {
	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
	status = "okay";
	};

	&uart2 {
	status = "okay";
	};

	&usbphy {
	status = "okay";
	};

	&usb_host0_ehci {
	status = "okay";
	};

	&usb_host1 {
	pinctrl-names = "default";
	pinctrl-0 = <&phy_pwr_en>;
	status = "okay";
	};

	&usb_otg {
	status = "okay";
	};

	&vopb {
	status = "okay";
	};

	&vopb_mmu {
	status = "okay";
	};

	&vopl {
	status = "okay";
	};

	&vopl_mmu {
	status = "okay";
	};

	&wdt {
	status = "okay";
	};

	&pinctrl {
	pcfg_output_high: pcfg-output-high {
	output-high;
	};

	gmac {
	phy_int: phy-int {
	rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
	};

	phy_pmeb: phy-pmeb {
	rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
	};

	phy_rst: phy-rst {
	rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
	};
	};

	+ hdmi {
	+ vcc50_hdmi_en: vcc50-hdmi-en {
	+ rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
	+ };
	+ };
	+
	pmic {
	pmic_int: pmic-int {
	rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	usb_host {
	phy_pwr_en: phy-pwr-en {
	rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>;
	};

	usb2_pwr_en: usb2-pwr-en {
	rockchip,pins = <8 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	usb_otg {
	otg_vbus_drv: otg-vbus-drv {
	rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;

	};
	};
	};
	diff --git a/sys/gnu/dts/arm/rk3288.dtsi b/sys/gnu/dts/arm/rk3288.dtsi
	index 9beb662166aa..0cd88774db95 100644
	--- a/sys/gnu/dts/arm/rk3288.dtsi
	+++ b/sys/gnu/dts/arm/rk3288.dtsi
	@@ -1,2001 +1,2005 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/pinctrl/rockchip.h>
	#include <dt-bindings/clock/rk3288-cru.h>
	#include <dt-bindings/power/rk3288-power.h>
	#include <dt-bindings/thermal/thermal.h>
	#include <dt-bindings/power/rk3288-power.h>
	#include <dt-bindings/soc/rockchip,boot-mode.h>

	/ {
	#address-cells = <2>;
	#size-cells = <2>;

	compatible = "rockchip,rk3288";

	interrupt-parent = <&gic>;

	aliases {
	ethernet0 = &gmac;
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	mshc0 = &emmc;
	mshc1 = &sdmmc;
	mshc2 = &sdio0;
	mshc3 = &sdio1;
	serial0 = &uart0;
	serial1 = &uart1;
	serial2 = &uart2;
	serial3 = &uart3;
	serial4 = &uart4;
	spi0 = &spi0;
	spi1 = &spi1;
	spi2 = &spi2;
	};

	arm-pmu {
	compatible = "arm,cortex-a12-pmu";
	interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "rockchip,rk3066-smp";
	rockchip,pmu = <&pmu>;

	cpu0: cpu@500 {
	device_type = "cpu";
	compatible = "arm,cortex-a12";
	reg = <0x500>;
	resets = <&cru SRST_CORE0>;
	operating-points-v2 = <&cpu_opp_table>;
	#cooling-cells = <2>; /* min followed by max */
	clock-latency = <40000>;
	clocks = <&cru ARMCLK>;
	dynamic-power-coefficient = <370>;
	};
	cpu1: cpu@501 {
	device_type = "cpu";
	compatible = "arm,cortex-a12";
	reg = <0x501>;
	resets = <&cru SRST_CORE1>;
	operating-points-v2 = <&cpu_opp_table>;
	#cooling-cells = <2>; /* min followed by max */
	clock-latency = <40000>;
	clocks = <&cru ARMCLK>;
	dynamic-power-coefficient = <370>;
	};
	cpu2: cpu@502 {
	device_type = "cpu";
	compatible = "arm,cortex-a12";
	reg = <0x502>;
	resets = <&cru SRST_CORE2>;
	operating-points-v2 = <&cpu_opp_table>;
	#cooling-cells = <2>; /* min followed by max */
	clock-latency = <40000>;
	clocks = <&cru ARMCLK>;
	dynamic-power-coefficient = <370>;
	};
	cpu3: cpu@503 {
	device_type = "cpu";
	compatible = "arm,cortex-a12";
	reg = <0x503>;
	resets = <&cru SRST_CORE3>;
	operating-points-v2 = <&cpu_opp_table>;
	#cooling-cells = <2>; /* min followed by max */
	clock-latency = <40000>;
	clocks = <&cru ARMCLK>;
	dynamic-power-coefficient = <370>;
	};
	};

	cpu_opp_table: cpu-opp-table {
	compatible = "operating-points-v2";
	opp-shared;

	opp-126000000 {
	opp-hz = /bits/ 64 <126000000>;
	opp-microvolt = <900000>;
	};
	opp-216000000 {
	opp-hz = /bits/ 64 <216000000>;
	opp-microvolt = <900000>;
	};
	opp-312000000 {
	opp-hz = /bits/ 64 <312000000>;
	opp-microvolt = <900000>;
	};
	opp-408000000 {
	opp-hz = /bits/ 64 <408000000>;
	opp-microvolt = <900000>;
	};
	opp-600000000 {
	opp-hz = /bits/ 64 <600000000>;
	opp-microvolt = <900000>;
	};
	opp-696000000 {
	opp-hz = /bits/ 64 <696000000>;
	opp-microvolt = <950000>;
	};
	opp-816000000 {
	opp-hz = /bits/ 64 <816000000>;
	opp-microvolt = <1000000>;
	};
	opp-1008000000 {
	opp-hz = /bits/ 64 <1008000000>;
	opp-microvolt = <1050000>;
	};
	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	opp-microvolt = <1100000>;
	};
	opp-1416000000 {
	opp-hz = /bits/ 64 <1416000000>;
	opp-microvolt = <1200000>;
	};
	opp-1512000000 {
	opp-hz = /bits/ 64 <1512000000>;
	opp-microvolt = <1300000>;
	};
	opp-1608000000 {
	opp-hz = /bits/ 64 <1608000000>;
	opp-microvolt = <1350000>;
	};
	};

	- amba {
	+ amba: bus {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	dmac_peri: dma-controller@ff250000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x0 0xff250000 0x0 0x4000>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	arm,pl330-broken-no-flushp;
	clocks = <&cru ACLK_DMAC2>;
	clock-names = "apb_pclk";
	};

	dmac_bus_ns: dma-controller@ff600000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x0 0xff600000 0x0 0x4000>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	arm,pl330-broken-no-flushp;
	clocks = <&cru ACLK_DMAC1>;
	clock-names = "apb_pclk";
	status = "disabled";
	};

	dmac_bus_s: dma-controller@ffb20000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x0 0xffb20000 0x0 0x4000>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	arm,pl330-broken-no-flushp;
	clocks = <&cru ACLK_DMAC1>;
	clock-names = "apb_pclk";
	};
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	/*
	* The rk3288 cannot use the memory area above 0xfe000000
	* for dma operations for some reason. While there is
	* probably a better solution available somewhere, we
	* haven't found it yet and while devices with 2GB of ram
	* are not affected, this issue prevents 4GB from booting.
	* So to make these devices at least bootable, block
	* this area for the time being until the real solution
	* is found.
	*/
	dma-unusable@fe000000 {
	reg = <0x0 0xfe000000 0x0 0x1000000>;
	};
	};

	xin24m: oscillator {
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-output-names = "xin24m";
	#clock-cells = <0>;
	};

	timer {
	compatible = "arm,armv7-timer";
	arm,cpu-registers-not-fw-configured;
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	clock-frequency = <24000000>;
	arm,no-tick-in-suspend;
	};

	timer: timer@ff810000 {
	compatible = "rockchip,rk3288-timer";
	reg = <0x0 0xff810000 0x0 0x20>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&xin24m>, <&cru PCLK_TIMER>;
	clock-names = "timer", "pclk";
	};

	display-subsystem {
	compatible = "rockchip,display-subsystem";
	ports = <&vopl_out>, <&vopb_out>;
	};

	sdmmc: mmc@ff0c0000 {
	compatible = "rockchip,rk3288-dw-mshc";
	max-frequency = <150000000>;
	clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
	<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x0 0xff0c0000 0x0 0x4000>;
	resets = <&cru SRST_MMC0>;
	reset-names = "reset";
	status = "disabled";
	};

	sdio0: mmc@ff0d0000 {
	compatible = "rockchip,rk3288-dw-mshc";
	max-frequency = <150000000>;
	clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
	<&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x0 0xff0d0000 0x0 0x4000>;
	resets = <&cru SRST_SDIO0>;
	reset-names = "reset";
	status = "disabled";
	};

	sdio1: mmc@ff0e0000 {
	compatible = "rockchip,rk3288-dw-mshc";
	max-frequency = <150000000>;
	clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
	<&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x0 0xff0e0000 0x0 0x4000>;
	resets = <&cru SRST_SDIO1>;
	reset-names = "reset";
	status = "disabled";
	};

	emmc: mmc@ff0f0000 {
	compatible = "rockchip,rk3288-dw-mshc";
	max-frequency = <150000000>;
	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
	<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x0 0xff0f0000 0x0 0x4000>;
	resets = <&cru SRST_EMMC>;
	reset-names = "reset";
	status = "disabled";
	};

	saradc: saradc@ff100000 {
	compatible = "rockchip,saradc";
	reg = <0x0 0xff100000 0x0 0x100>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	#io-channel-cells = <1>;
	clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
	clock-names = "saradc", "apb_pclk";
	resets = <&cru SRST_SARADC>;
	reset-names = "saradc-apb";
	status = "disabled";
	};

	spi0: spi@ff110000 {
	compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
	clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
	clock-names = "spiclk", "apb_pclk";
	dmas = <&dmac_peri 11>, <&dmac_peri 12>;
	dma-names = "tx", "rx";
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
	reg = <0x0 0xff110000 0x0 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi1: spi@ff120000 {
	compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
	clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
	clock-names = "spiclk", "apb_pclk";
	dmas = <&dmac_peri 13>, <&dmac_peri 14>;
	dma-names = "tx", "rx";
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
	reg = <0x0 0xff120000 0x0 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi2: spi@ff130000 {
	compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
	clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
	clock-names = "spiclk", "apb_pclk";
	dmas = <&dmac_peri 15>, <&dmac_peri 16>;
	dma-names = "tx", "rx";
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
	reg = <0x0 0xff130000 0x0 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c1: i2c@ff140000 {
	compatible = "rockchip,rk3288-i2c";
	reg = <0x0 0xff140000 0x0 0x1000>;
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C1>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
	status = "disabled";
	};

	i2c3: i2c@ff150000 {
	compatible = "rockchip,rk3288-i2c";
	reg = <0x0 0xff150000 0x0 0x1000>;
	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C3>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
	status = "disabled";
	};

	i2c4: i2c@ff160000 {
	compatible = "rockchip,rk3288-i2c";
	reg = <0x0 0xff160000 0x0 0x1000>;
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C4>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_xfer>;
	status = "disabled";
	};

	i2c5: i2c@ff170000 {
	compatible = "rockchip,rk3288-i2c";
	reg = <0x0 0xff170000 0x0 0x1000>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C5>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c5_xfer>;
	status = "disabled";
	};

	uart0: serial@ff180000 {
	compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff180000 0x0 0x100>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
	clock-names = "baudclk", "apb_pclk";
	+ dmas = <&dmac_peri 1>, <&dmac_peri 2>;
	+ dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer>;
	status = "disabled";
	};

	uart1: serial@ff190000 {
	compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff190000 0x0 0x100>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
	clock-names = "baudclk", "apb_pclk";
	+ dmas = <&dmac_peri 3>, <&dmac_peri 4>;
	+ dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer>;
	status = "disabled";
	};

	uart2: serial@ff690000 {
	compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff690000 0x0 0x100>;
	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
	clock-names = "baudclk", "apb_pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_xfer>;
	status = "disabled";
	};

	uart3: serial@ff1b0000 {
	compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff1b0000 0x0 0x100>;
	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
	clock-names = "baudclk", "apb_pclk";
	+ dmas = <&dmac_peri 7>, <&dmac_peri 8>;
	+ dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_xfer>;
	status = "disabled";
	};

	uart4: serial@ff1c0000 {
	compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff1c0000 0x0 0x100>;
	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
	clock-names = "baudclk", "apb_pclk";
	+ dmas = <&dmac_peri 9>, <&dmac_peri 10>;
	+ dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_xfer>;
	status = "disabled";
	};

	thermal-zones {
	reserve_thermal: reserve_thermal {
	polling-delay-passive = <1000>; /* milliseconds */
	polling-delay = <5000>; /* milliseconds */

	thermal-sensors = <&tsadc 0>;
	};

	cpu_thermal: cpu_thermal {
	polling-delay-passive = <100>; /* milliseconds */
	polling-delay = <5000>; /* milliseconds */

	thermal-sensors = <&tsadc 1>;

	trips {
	cpu_alert0: cpu_alert0 {
	temperature = <70000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "passive";
	};
	cpu_alert1: cpu_alert1 {
	temperature = <75000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "passive";
	};
	cpu_crit: cpu_crit {
	temperature = <90000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu_alert0>;
	cooling-device =
	<&cpu0 THERMAL_NO_LIMIT 6>,
	<&cpu1 THERMAL_NO_LIMIT 6>,
	<&cpu2 THERMAL_NO_LIMIT 6>,
	<&cpu3 THERMAL_NO_LIMIT 6>;
	};
	map1 {
	trip = <&cpu_alert1>;
	cooling-device =
	<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	gpu_thermal: gpu_thermal {
	polling-delay-passive = <100>; /* milliseconds */
	polling-delay = <5000>; /* milliseconds */

	thermal-sensors = <&tsadc 2>;

	trips {
	gpu_alert0: gpu_alert0 {
	temperature = <70000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "passive";
	};
	gpu_crit: gpu_crit {
	temperature = <90000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&gpu_alert0>;
	cooling-device =
	<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};
	};

	tsadc: tsadc@ff280000 {
	compatible = "rockchip,rk3288-tsadc";
	reg = <0x0 0xff280000 0x0 0x100>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
	clock-names = "tsadc", "apb_pclk";
	resets = <&cru SRST_TSADC>;
	reset-names = "tsadc-apb";
	pinctrl-names = "init", "default", "sleep";
	pinctrl-0 = <&otp_gpio>;
	pinctrl-1 = <&otp_out>;
	pinctrl-2 = <&otp_gpio>;
	#thermal-sensor-cells = <1>;
	rockchip,grf = <&grf>;
	rockchip,hw-tshut-temp = <95000>;
	status = "disabled";
	};

	gmac: ethernet@ff290000 {
	compatible = "rockchip,rk3288-gmac";
	reg = <0x0 0xff290000 0x0 0x10000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq", "eth_wake_irq";
	rockchip,grf = <&grf>;
	clocks = <&cru SCLK_MAC>,
	<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
	<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
	<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
	clock-names = "stmmaceth",
	"mac_clk_rx", "mac_clk_tx",
	"clk_mac_ref", "clk_mac_refout",
	"aclk_mac", "pclk_mac";
	resets = <&cru SRST_MAC>;
	reset-names = "stmmaceth";
	status = "disabled";
	};

	usb_host0_ehci: usb@ff500000 {
	compatible = "generic-ehci";
	reg = <0x0 0xff500000 0x0 0x100>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_USBHOST0>;
	- clock-names = "usbhost";
	phys = <&usbphy1>;
	phy-names = "usb";
	status = "disabled";
	};

	/* NOTE: ohci@ff520000 doesn't actually work on hardware */

	usb_host1: usb@ff540000 {
	compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
	"snps,dwc2";
	reg = <0x0 0xff540000 0x0 0x40000>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_USBHOST1>;
	clock-names = "otg";
	dr_mode = "host";
	phys = <&usbphy2>;
	phy-names = "usb2-phy";
	snps,reset-phy-on-wake;
	status = "disabled";
	};

	usb_otg: usb@ff580000 {
	compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
	"snps,dwc2";
	reg = <0x0 0xff580000 0x0 0x40000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_OTG0>;
	clock-names = "otg";
	dr_mode = "otg";
	g-np-tx-fifo-size = <16>;
	g-rx-fifo-size = <275>;
	g-tx-fifo-size = <256 128 128 64 64 32>;
	phys = <&usbphy0>;
	phy-names = "usb2-phy";
	status = "disabled";
	};

	usb_hsic: usb@ff5c0000 {
	compatible = "generic-ehci";
	reg = <0x0 0xff5c0000 0x0 0x100>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_HSIC>;
	- clock-names = "usbhost";
	status = "disabled";
	};

	i2c0: i2c@ff650000 {
	compatible = "rockchip,rk3288-i2c";
	reg = <0x0 0xff650000 0x0 0x1000>;
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
	status = "disabled";
	};

	i2c2: i2c@ff660000 {
	compatible = "rockchip,rk3288-i2c";
	reg = <0x0 0xff660000 0x0 0x1000>;
	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C2>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
	status = "disabled";
	};

	pwm0: pwm@ff680000 {
	compatible = "rockchip,rk3288-pwm";
	reg = <0x0 0xff680000 0x0 0x10>;
	#pwm-cells = <3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_pin>;
	clocks = <&cru PCLK_RKPWM>;
	clock-names = "pwm";
	status = "disabled";
	};

	pwm1: pwm@ff680010 {
	compatible = "rockchip,rk3288-pwm";
	reg = <0x0 0xff680010 0x0 0x10>;
	#pwm-cells = <3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_pin>;
	clocks = <&cru PCLK_RKPWM>;
	clock-names = "pwm";
	status = "disabled";
	};

	pwm2: pwm@ff680020 {
	compatible = "rockchip,rk3288-pwm";
	reg = <0x0 0xff680020 0x0 0x10>;
	#pwm-cells = <3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_pin>;
	clocks = <&cru PCLK_RKPWM>;
	clock-names = "pwm";
	status = "disabled";
	};

	pwm3: pwm@ff680030 {
	compatible = "rockchip,rk3288-pwm";
	reg = <0x0 0xff680030 0x0 0x10>;
	#pwm-cells = <3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_pin>;
	clocks = <&cru PCLK_RKPWM>;
	clock-names = "pwm";
	status = "disabled";
	};

	- bus_intmem@ff700000 {
	+ bus_intmem: sram@ff700000 {
	compatible = "mmio-sram";
	reg = <0x0 0xff700000 0x0 0x18000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x0 0xff700000 0x18000>;
	smp-sram@0 {
	compatible = "rockchip,rk3066-smp-sram";
	reg = <0x00 0x10>;
	};
	};

	- sram@ff720000 {
	+ pmu_sram: sram@ff720000 {
	compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
	reg = <0x0 0xff720000 0x0 0x1000>;
	};

	pmu: power-management@ff730000 {
	compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
	reg = <0x0 0xff730000 0x0 0x100>;

	power: power-controller {
	compatible = "rockchip,rk3288-power-controller";
	#power-domain-cells = <1>;
	#address-cells = <1>;
	#size-cells = <0>;

	assigned-clocks = <&cru SCLK_EDP_24M>;
	assigned-clock-parents = <&xin24m>;

	/*
	* Note: Although SCLK_* are the working clocks
	* of device without including on the NOC, needed for
	* synchronous reset.
	*
	* The clocks on the which NOC:
	* ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
	* ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
	* ACLK_RGA is on ACLK_RGA_NIU.
	* The others (HCLK_,PLCK_) are on HCLK_VIO_NIU.
	*
	* Which clock are device clocks:
	* clocks devices
	* *_IEP IEP:Image Enhancement Processor
	* *_ISP ISP:Image Signal Processing
	* *_VIP VIP:Video Input Processor
	* _VOP VOP:Visual Output Processor
	* *_RGA RGA
	* _EDP EDP
	* _LVDS_ LVDS
	* *_HDMI HDMI
	* _MIPI_ MIPI
	*/
	pd_vio@RK3288_PD_VIO {
	reg = <RK3288_PD_VIO>;
	clocks = <&cru ACLK_IEP>,
	<&cru ACLK_ISP>,
	<&cru ACLK_RGA>,
	<&cru ACLK_VIP>,
	<&cru ACLK_VOP0>,
	<&cru ACLK_VOP1>,
	<&cru DCLK_VOP0>,
	<&cru DCLK_VOP1>,
	<&cru HCLK_IEP>,
	<&cru HCLK_ISP>,
	<&cru HCLK_RGA>,
	<&cru HCLK_VIP>,
	<&cru HCLK_VOP0>,
	<&cru HCLK_VOP1>,
	<&cru PCLK_EDP_CTRL>,
	<&cru PCLK_HDMI_CTRL>,
	<&cru PCLK_LVDS_PHY>,
	<&cru PCLK_MIPI_CSI>,
	<&cru PCLK_MIPI_DSI0>,
	<&cru PCLK_MIPI_DSI1>,
	<&cru SCLK_EDP_24M>,
	<&cru SCLK_EDP>,
	<&cru SCLK_ISP_JPE>,
	<&cru SCLK_ISP>,
	<&cru SCLK_RGA>;
	pm_qos = <&qos_vio0_iep>,
	<&qos_vio1_vop>,
	<&qos_vio1_isp_w0>,
	<&qos_vio1_isp_w1>,
	<&qos_vio0_vop>,
	<&qos_vio0_vip>,
	<&qos_vio2_rga_r>,
	<&qos_vio2_rga_w>,
	<&qos_vio1_isp_r>;
	};

	/*
	* Note: The following 3 are HEVC(H.265) clocks,
	* and on the ACLK_HEVC_NIU (NOC).
	*/
	pd_hevc@RK3288_PD_HEVC {
	reg = <RK3288_PD_HEVC>;
	clocks = <&cru ACLK_HEVC>,
	<&cru SCLK_HEVC_CABAC>,
	<&cru SCLK_HEVC_CORE>;
	pm_qos = <&qos_hevc_r>,
	<&qos_hevc_w>;
	};

	/*
	* Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
	* (video endecoder & decoder) clocks that on the
	* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
	*/
	pd_video@RK3288_PD_VIDEO {
	reg = <RK3288_PD_VIDEO>;
	clocks = <&cru ACLK_VCODEC>,
	<&cru HCLK_VCODEC>;
	pm_qos = <&qos_video>;
	};

	/*
	* Note: ACLK_GPU is the GPU clock,
	* and on the ACLK_GPU_NIU (NOC).
	*/
	pd_gpu@RK3288_PD_GPU {
	reg = <RK3288_PD_GPU>;
	clocks = <&cru ACLK_GPU>;
	pm_qos = <&qos_gpu_r>,
	<&qos_gpu_w>;
	};
	};

	reboot-mode {
	compatible = "syscon-reboot-mode";
	offset = <0x94>;
	mode-normal = <BOOT_NORMAL>;
	mode-recovery = <BOOT_RECOVERY>;
	mode-bootloader = <BOOT_FASTBOOT>;
	mode-loader = <BOOT_BL_DOWNLOAD>;
	};
	};

	sgrf: syscon@ff740000 {
	compatible = "rockchip,rk3288-sgrf", "syscon";
	reg = <0x0 0xff740000 0x0 0x1000>;
	};

	cru: clock-controller@ff760000 {
	compatible = "rockchip,rk3288-cru";
	reg = <0x0 0xff760000 0x0 0x1000>;
	rockchip,grf = <&grf>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
	<&cru PLL_NPLL>, <&cru ACLK_CPU>,
	<&cru HCLK_CPU>, <&cru PCLK_CPU>,
	<&cru ACLK_PERI>, <&cru HCLK_PERI>,
	<&cru PCLK_PERI>;
	assigned-clock-rates = <594000000>, <400000000>,
	<500000000>, <300000000>,
	<150000000>, <75000000>,
	<300000000>, <150000000>,
	<75000000>;
	};

	grf: syscon@ff770000 {
	compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
	reg = <0x0 0xff770000 0x0 0x1000>;

	edp_phy: edp-phy {
	compatible = "rockchip,rk3288-dp-phy";
	clocks = <&cru SCLK_EDP_24M>;
	clock-names = "24m";
	#phy-cells = <0>;
	status = "disabled";
	};

	io_domains: io-domains {
	compatible = "rockchip,rk3288-io-voltage-domain";
	status = "disabled";
	};

	usbphy: usbphy {
	compatible = "rockchip,rk3288-usb-phy";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";

	usbphy0: usb-phy@320 {
	#phy-cells = <0>;
	reg = <0x320>;
	clocks = <&cru SCLK_OTGPHY0>;
	clock-names = "phyclk";
	#clock-cells = <0>;
	resets = <&cru SRST_USBOTG_PHY>;
	reset-names = "phy-reset";
	};

	usbphy1: usb-phy@334 {
	#phy-cells = <0>;
	reg = <0x334>;
	clocks = <&cru SCLK_OTGPHY1>;
	clock-names = "phyclk";
	#clock-cells = <0>;
	resets = <&cru SRST_USBHOST0_PHY>;
	reset-names = "phy-reset";
	};

	usbphy2: usb-phy@348 {
	#phy-cells = <0>;
	reg = <0x348>;
	clocks = <&cru SCLK_OTGPHY2>;
	clock-names = "phyclk";
	#clock-cells = <0>;
	resets = <&cru SRST_USBHOST1_PHY>;
	reset-names = "phy-reset";
	};
	};
	};

	wdt: watchdog@ff800000 {
	compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
	reg = <0x0 0xff800000 0x0 0x100>;
	clocks = <&cru PCLK_WDT>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	spdif: sound@ff88b0000 {
	compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
	reg = <0x0 0xff8b0000 0x0 0x10000>;
	#sound-dai-cells = <0>;
	- clock-names = "hclk", "mclk";
	- clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
	+ clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
	+ clock-names = "mclk", "hclk";
	dmas = <&dmac_bus_s 3>;
	dma-names = "tx";
	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&spdif_tx>;
	rockchip,grf = <&grf>;
	status = "disabled";
	};

	i2s: i2s@ff890000 {
	compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
	reg = <0x0 0xff890000 0x0 0x10000>;
	#sound-dai-cells = <0>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	- #address-cells = <1>;
	- #size-cells = <0>;
	+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
	+ clock-names = "i2s_clk", "i2s_hclk";
	dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
	dma-names = "tx", "rx";
	- clock-names = "i2s_hclk", "i2s_clk";
	- clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2s0_bus>;
	rockchip,playback-channels = <8>;
	rockchip,capture-channels = <2>;
	status = "disabled";
	};

	crypto: cypto-controller@ff8a0000 {
	compatible = "rockchip,rk3288-crypto";
	reg = <0x0 0xff8a0000 0x0 0x4000>;
	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
	<&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
	clock-names = "aclk", "hclk", "sclk", "apb_pclk";
	resets = <&cru SRST_CRYPTO>;
	reset-names = "crypto-rst";
	status = "okay";
	};

	iep_mmu: iommu@ff900800 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff900800 0x0 0x40>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "iep_mmu";
	clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	status = "disabled";
	};

	isp_mmu: iommu@ff914000 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "isp_mmu";
	clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	rockchip,disable-mmu-reset;
	status = "disabled";
	};

	rga: rga@ff920000 {
	compatible = "rockchip,rk3288-rga";
	reg = <0x0 0xff920000 0x0 0x180>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
	clock-names = "aclk", "hclk", "sclk";
	power-domains = <&power RK3288_PD_VIO>;
	resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
	reset-names = "core", "axi", "ahb";
	};

	vopb: vop@ff930000 {
	compatible = "rockchip,rk3288-vop";
	reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	power-domains = <&power RK3288_PD_VIO>;
	resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
	reset-names = "axi", "ahb", "dclk";
	iommus = <&vopb_mmu>;
	status = "disabled";

	vopb_out: port {
	#address-cells = <1>;
	#size-cells = <0>;

	vopb_out_hdmi: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&hdmi_in_vopb>;
	};

	vopb_out_edp: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&edp_in_vopb>;
	};

	vopb_out_mipi: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&mipi_in_vopb>;
	};

	vopb_out_lvds: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&lvds_in_vopb>;
	};
	};
	};

	vopb_mmu: iommu@ff930300 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff930300 0x0 0x100>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "vopb_mmu";
	clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
	clock-names = "aclk", "iface";
	power-domains = <&power RK3288_PD_VIO>;
	#iommu-cells = <0>;
	status = "disabled";
	};

	vopl: vop@ff940000 {
	compatible = "rockchip,rk3288-vop";
	reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	power-domains = <&power RK3288_PD_VIO>;
	resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
	reset-names = "axi", "ahb", "dclk";
	iommus = <&vopl_mmu>;
	status = "disabled";

	vopl_out: port {
	#address-cells = <1>;
	#size-cells = <0>;

	vopl_out_hdmi: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&hdmi_in_vopl>;
	};

	vopl_out_edp: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&edp_in_vopl>;
	};

	vopl_out_mipi: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&mipi_in_vopl>;
	};

	vopl_out_lvds: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&lvds_in_vopl>;
	};
	};
	};

	vopl_mmu: iommu@ff940300 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff940300 0x0 0x100>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "vopl_mmu";
	clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
	clock-names = "aclk", "iface";
	power-domains = <&power RK3288_PD_VIO>;
	#iommu-cells = <0>;
	status = "disabled";
	};

	mipi_dsi: mipi@ff960000 {
	compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
	reg = <0x0 0xff960000 0x0 0x4000>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
	clock-names = "ref", "pclk";
	power-domains = <&power RK3288_PD_VIO>;
	rockchip,grf = <&grf>;
	status = "disabled";

	ports {
	mipi_in: port {
	#address-cells = <1>;
	#size-cells = <0>;
	mipi_in_vopb: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vopb_out_mipi>;
	};
	mipi_in_vopl: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vopl_out_mipi>;
	};
	};
	};
	};

	lvds: lvds@ff96c000 {
	compatible = "rockchip,rk3288-lvds";
	reg = <0x0 0xff96c000 0x0 0x4000>;
	clocks = <&cru PCLK_LVDS_PHY>;
	clock-names = "pclk_lvds";
	pinctrl-names = "lcdc";
	pinctrl-0 = <&lcdc_ctl>;
	power-domains = <&power RK3288_PD_VIO>;
	rockchip,grf = <&grf>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	lvds_in: port@0 {
	reg = <0>;

	#address-cells = <1>;
	#size-cells = <0>;

	lvds_in_vopb: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vopb_out_lvds>;
	};
	lvds_in_vopl: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vopl_out_lvds>;
	};
	};
	};
	};

	edp: dp@ff970000 {
	compatible = "rockchip,rk3288-dp";
	reg = <0x0 0xff970000 0x0 0x4000>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
	clock-names = "dp", "pclk";
	phys = <&edp_phy>;
	phy-names = "dp";
	resets = <&cru SRST_EDP>;
	reset-names = "dp";
	rockchip,grf = <&grf>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;
	edp_in: port@0 {
	reg = <0>;
	#address-cells = <1>;
	#size-cells = <0>;
	edp_in_vopb: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vopb_out_edp>;
	};
	edp_in_vopl: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vopl_out_edp>;
	};
	};
	};
	};

	hdmi: hdmi@ff980000 {
	compatible = "rockchip,rk3288-dw-hdmi";
	reg = <0x0 0xff980000 0x0 0x20000>;
	reg-io-width = <4>;
	#sound-dai-cells = <0>;
	rockchip,grf = <&grf>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
	clock-names = "iahb", "isfr", "cec";
	power-domains = <&power RK3288_PD_VIO>;
	status = "disabled";

	ports {
	hdmi_in: port {
	#address-cells = <1>;
	#size-cells = <0>;
	hdmi_in_vopb: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vopb_out_hdmi>;
	};
	hdmi_in_vopl: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vopl_out_hdmi>;
	};
	};
	};
	};

	vpu: video-codec@ff9a0000 {
	compatible = "rockchip,rk3288-vpu";
	reg = <0x0 0xff9a0000 0x0 0x800>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "vepu", "vdpu";
	clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
	clock-names = "aclk", "hclk";
	iommus = <&vpu_mmu>;
	power-domains = <&power RK3288_PD_VIDEO>;
	};

	vpu_mmu: iommu@ff9a0800 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff9a0800 0x0 0x100>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "vpu_mmu";
	clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	power-domains = <&power RK3288_PD_VIDEO>;
	};

	hevc_mmu: iommu@ff9c0440 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hevc_mmu";
	clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	status = "disabled";
	};

	gpu: gpu@ffa30000 {
	compatible = "rockchip,rk3288-mali", "arm,mali-t760";
	reg = <0x0 0xffa30000 0x0 0x10000>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "job", "mmu", "gpu";
	clocks = <&cru ACLK_GPU>;
	operating-points-v2 = <&gpu_opp_table>;
	#cooling-cells = <2>; /* min followed by max */
	power-domains = <&power RK3288_PD_GPU>;
	status = "disabled";
	};

	gpu_opp_table: gpu-opp-table {
	compatible = "operating-points-v2";

	opp-100000000 {
	opp-hz = /bits/ 64 <100000000>;
	opp-microvolt = <950000>;
	};
	opp-200000000 {
	opp-hz = /bits/ 64 <200000000>;
	opp-microvolt = <950000>;
	};
	opp-300000000 {
	opp-hz = /bits/ 64 <300000000>;
	opp-microvolt = <1000000>;
	};
	opp-400000000 {
	opp-hz = /bits/ 64 <400000000>;
	opp-microvolt = <1100000>;
	};
	opp-600000000 {
	opp-hz = /bits/ 64 <600000000>;
	opp-microvolt = <1250000>;
	};
	};

	qos_gpu_r: qos@ffaa0000 {
	compatible = "syscon";
	reg = <0x0 0xffaa0000 0x0 0x20>;
	};

	qos_gpu_w: qos@ffaa0080 {
	compatible = "syscon";
	reg = <0x0 0xffaa0080 0x0 0x20>;
	};

	qos_vio1_vop: qos@ffad0000 {
	compatible = "syscon";
	reg = <0x0 0xffad0000 0x0 0x20>;
	};

	qos_vio1_isp_w0: qos@ffad0100 {
	compatible = "syscon";
	reg = <0x0 0xffad0100 0x0 0x20>;
	};

	qos_vio1_isp_w1: qos@ffad0180 {
	compatible = "syscon";
	reg = <0x0 0xffad0180 0x0 0x20>;
	};

	qos_vio0_vop: qos@ffad0400 {
	compatible = "syscon";
	reg = <0x0 0xffad0400 0x0 0x20>;
	};

	qos_vio0_vip: qos@ffad0480 {
	compatible = "syscon";
	reg = <0x0 0xffad0480 0x0 0x20>;
	};

	qos_vio0_iep: qos@ffad0500 {
	compatible = "syscon";
	reg = <0x0 0xffad0500 0x0 0x20>;
	};

	qos_vio2_rga_r: qos@ffad0800 {
	compatible = "syscon";
	reg = <0x0 0xffad0800 0x0 0x20>;
	};

	qos_vio2_rga_w: qos@ffad0880 {
	compatible = "syscon";
	reg = <0x0 0xffad0880 0x0 0x20>;
	};

	qos_vio1_isp_r: qos@ffad0900 {
	compatible = "syscon";
	reg = <0x0 0xffad0900 0x0 0x20>;
	};

	qos_video: qos@ffae0000 {
	compatible = "syscon";
	reg = <0x0 0xffae0000 0x0 0x20>;
	};

	qos_hevc_r: qos@ffaf0000 {
	compatible = "syscon";
	reg = <0x0 0xffaf0000 0x0 0x20>;
	};

	qos_hevc_w: qos@ffaf0080 {
	compatible = "syscon";
	reg = <0x0 0xffaf0080 0x0 0x20>;
	};

	efuse: efuse@ffb40000 {
	compatible = "rockchip,rk3288-efuse";
	reg = <0x0 0xffb40000 0x0 0x20>;
	#address-cells = <1>;
	#size-cells = <1>;
	clocks = <&cru PCLK_EFUSE256>;
	clock-names = "pclk_efuse";

	cpu_id: cpu-id@7 {
	reg = <0x07 0x10>;
	};
	cpu_leakage: cpu_leakage@17 {
	reg = <0x17 0x1>;
	};
	};

	gic: interrupt-controller@ffc01000 {
	compatible = "arm,gic-400";
	interrupt-controller;
	#interrupt-cells = <3>;
	#address-cells = <0>;

	reg = <0x0 0xffc01000 0x0 0x1000>,
	<0x0 0xffc02000 0x0 0x2000>,
	<0x0 0xffc04000 0x0 0x2000>,
	<0x0 0xffc06000 0x0 0x2000>;
	interrupts = <GIC_PPI 9 0xf04>;
	};

	pinctrl: pinctrl {
	compatible = "rockchip,rk3288-pinctrl";
	rockchip,grf = <&grf>;
	rockchip,pmu = <&pmu>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	gpio0: gpio0@ff750000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff750000 0x0 0x100>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO0>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio1: gpio1@ff780000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff780000 0x0 0x100>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO1>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio2@ff790000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff790000 0x0 0x100>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO2>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio3@ff7a0000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff7a0000 0x0 0x100>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO3>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio4: gpio4@ff7b0000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff7b0000 0x0 0x100>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO4>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio5: gpio5@ff7c0000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff7c0000 0x0 0x100>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO5>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio6: gpio6@ff7d0000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff7d0000 0x0 0x100>;
	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO6>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio7: gpio7@ff7e0000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff7e0000 0x0 0x100>;
	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO7>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio8: gpio8@ff7f0000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff7f0000 0x0 0x100>;
	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO8>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	hdmi {
	hdmi_cec_c0: hdmi-cec-c0 {
	rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
	};

	hdmi_cec_c7: hdmi-cec-c7 {
	rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;
	};

	hdmi_ddc: hdmi-ddc {
	rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
	<7 RK_PC4 2 &pcfg_pull_none>;
	};

	hdmi_ddc_unwedge: hdmi-ddc-unwedge {
	rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
	<7 RK_PC4 2 &pcfg_pull_none>;
	};
	};

	pcfg_output_low: pcfg-output-low {
	output-low;
	};

	pcfg_pull_up: pcfg-pull-up {
	bias-pull-up;
	};

	pcfg_pull_down: pcfg-pull-down {
	bias-pull-down;
	};

	pcfg_pull_none: pcfg-pull-none {
	bias-disable;
	};

	pcfg_pull_none_12ma: pcfg-pull-none-12ma {
	bias-disable;
	drive-strength = <12>;
	};

	sleep {
	global_pwroff: global-pwroff {
	rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
	};

	ddrio_pwroff: ddrio-pwroff {
	rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
	};

	ddr0_retention: ddr0-retention {
	rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
	};

	ddr1_retention: ddr1-retention {
	rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
	};
	};

	edp {
	edp_hpd: edp-hpd {
	rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
	};
	};

	i2c0 {
	i2c0_xfer: i2c0-xfer {
	rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
	<0 RK_PC0 1 &pcfg_pull_none>;
	};
	};

	i2c1 {
	i2c1_xfer: i2c1-xfer {
	rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
	<8 RK_PA5 1 &pcfg_pull_none>;
	};
	};

	i2c2 {
	i2c2_xfer: i2c2-xfer {
	rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
	<6 RK_PB2 1 &pcfg_pull_none>;
	};
	};

	i2c3 {
	i2c3_xfer: i2c3-xfer {
	rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
	<2 RK_PC1 1 &pcfg_pull_none>;
	};
	};

	i2c4 {
	i2c4_xfer: i2c4-xfer {
	rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
	<7 RK_PC2 1 &pcfg_pull_none>;
	};
	};

	i2c5 {
	i2c5_xfer: i2c5-xfer {
	rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
	<7 RK_PC4 1 &pcfg_pull_none>;
	};
	};

	i2s0 {
	i2s0_bus: i2s0-bus {
	rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
	<6 RK_PA1 1 &pcfg_pull_none>,
	<6 RK_PA2 1 &pcfg_pull_none>,
	<6 RK_PA3 1 &pcfg_pull_none>,
	<6 RK_PA4 1 &pcfg_pull_none>,
	<6 RK_PB0 1 &pcfg_pull_none>;
	};
	};

	lcdc {
	lcdc_ctl: lcdc-ctl {
	rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
	<1 RK_PD1 1 &pcfg_pull_none>,
	<1 RK_PD2 1 &pcfg_pull_none>,
	<1 RK_PD3 1 &pcfg_pull_none>;
	};
	};

	sdmmc {
	sdmmc_clk: sdmmc-clk {
	rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
	};

	sdmmc_cmd: sdmmc-cmd {
	rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
	};

	sdmmc_cd: sdmmc-cd {
	rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
	};

	sdmmc_bus1: sdmmc-bus1 {
	rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
	};

	sdmmc_bus4: sdmmc-bus4 {
	rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
	<6 RK_PC1 1 &pcfg_pull_up>,
	<6 RK_PC2 1 &pcfg_pull_up>,
	<6 RK_PC3 1 &pcfg_pull_up>;
	};
	};

	sdio0 {
	sdio0_bus1: sdio0-bus1 {
	rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
	};

	sdio0_bus4: sdio0-bus4 {
	rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
	<4 RK_PC5 1 &pcfg_pull_up>,
	<4 RK_PC6 1 &pcfg_pull_up>,
	<4 RK_PC7 1 &pcfg_pull_up>;
	};

	sdio0_cmd: sdio0-cmd {
	rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
	};

	sdio0_clk: sdio0-clk {
	rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
	};

	sdio0_cd: sdio0-cd {
	rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
	};

	sdio0_wp: sdio0-wp {
	rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
	};

	sdio0_pwr: sdio0-pwr {
	rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
	};

	sdio0_bkpwr: sdio0-bkpwr {
	rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
	};

	sdio0_int: sdio0-int {
	rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
	};
	};

	sdio1 {
	sdio1_bus1: sdio1-bus1 {
	rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
	};

	sdio1_bus4: sdio1-bus4 {
	rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
	<3 RK_PD1 4 &pcfg_pull_up>,
	<3 RK_PD2 4 &pcfg_pull_up>,
	<3 RK_PD3 4 &pcfg_pull_up>;
	};

	sdio1_cd: sdio1-cd {
	rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
	};

	sdio1_wp: sdio1-wp {
	rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
	};

	sdio1_bkpwr: sdio1-bkpwr {
	rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
	};

	sdio1_int: sdio1-int {
	rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
	};

	sdio1_cmd: sdio1-cmd {
	rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
	};

	sdio1_clk: sdio1-clk {
	rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
	};

	sdio1_pwr: sdio1-pwr {
	rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
	};
	};

	emmc {
	emmc_clk: emmc-clk {
	rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
	};

	emmc_cmd: emmc-cmd {
	rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
	};

	emmc_pwr: emmc-pwr {
	rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
	};

	emmc_bus1: emmc-bus1 {
	rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
	};

	emmc_bus4: emmc-bus4 {
	rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
	<3 RK_PA1 2 &pcfg_pull_up>,
	<3 RK_PA2 2 &pcfg_pull_up>,
	<3 RK_PA3 2 &pcfg_pull_up>;
	};

	emmc_bus8: emmc-bus8 {
	rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
	<3 RK_PA1 2 &pcfg_pull_up>,
	<3 RK_PA2 2 &pcfg_pull_up>,
	<3 RK_PA3 2 &pcfg_pull_up>,
	<3 RK_PA4 2 &pcfg_pull_up>,
	<3 RK_PA5 2 &pcfg_pull_up>,
	<3 RK_PA6 2 &pcfg_pull_up>,
	<3 RK_PA7 2 &pcfg_pull_up>;
	};
	};

	spi0 {
	spi0_clk: spi0-clk {
	rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
	};
	spi0_cs0: spi0-cs0 {
	rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
	};
	spi0_tx: spi0-tx {
	rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
	};
	spi0_rx: spi0-rx {
	rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
	};
	spi0_cs1: spi0-cs1 {
	rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
	};
	};
	spi1 {
	spi1_clk: spi1-clk {
	rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
	};
	spi1_cs0: spi1-cs0 {
	rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
	};
	spi1_rx: spi1-rx {
	rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
	};
	spi1_tx: spi1-tx {
	rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
	};
	};

	spi2 {
	spi2_cs1: spi2-cs1 {
	rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
	};
	spi2_clk: spi2-clk {
	rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
	};
	spi2_cs0: spi2-cs0 {
	rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
	};
	spi2_rx: spi2-rx {
	rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
	};
	spi2_tx: spi2-tx {
	rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
	};
	};

	uart0 {
	uart0_xfer: uart0-xfer {
	rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
	<4 RK_PC1 1 &pcfg_pull_none>;
	};

	uart0_cts: uart0-cts {
	rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
	};

	uart0_rts: uart0-rts {
	rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
	};
	};

	uart1 {
	uart1_xfer: uart1-xfer {
	rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
	<5 RK_PB1 1 &pcfg_pull_none>;
	};

	uart1_cts: uart1-cts {
	rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
	};

	uart1_rts: uart1-rts {
	rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
	};
	};

	uart2 {
	uart2_xfer: uart2-xfer {
	rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
	<7 RK_PC7 1 &pcfg_pull_none>;
	};
	/* no rts / cts for uart2 */
	};

	uart3 {
	uart3_xfer: uart3-xfer {
	rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
	<7 RK_PB0 1 &pcfg_pull_none>;
	};

	uart3_cts: uart3-cts {
	rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
	};

	uart3_rts: uart3-rts {
	rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
	};
	};

	uart4 {
	uart4_xfer: uart4-xfer {
	rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
	<5 RK_PB6 3 &pcfg_pull_none>;
	};

	uart4_cts: uart4-cts {
	rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
	};

	uart4_rts: uart4-rts {
	rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
	};
	};

	tsadc {
	otp_gpio: otp-gpio {
	rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	otp_out: otp-out {
	rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
	};
	};

	pwm0 {
	pwm0_pin: pwm0-pin {
	rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
	};
	};

	pwm1 {
	pwm1_pin: pwm1-pin {
	rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
	};
	};

	pwm2 {
	pwm2_pin: pwm2-pin {
	rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
	};
	};

	pwm3 {
	pwm3_pin: pwm3-pin {
	rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
	};
	};

	gmac {
	rgmii_pins: rgmii-pins {
	rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
	<3 RK_PD7 3 &pcfg_pull_none>,
	<3 RK_PD2 3 &pcfg_pull_none>,
	<3 RK_PD3 3 &pcfg_pull_none>,
	<3 RK_PD4 3 &pcfg_pull_none_12ma>,
	<3 RK_PD5 3 &pcfg_pull_none_12ma>,
	<3 RK_PD0 3 &pcfg_pull_none_12ma>,
	<3 RK_PD1 3 &pcfg_pull_none_12ma>,
	<4 RK_PA0 3 &pcfg_pull_none>,
	<4 RK_PA5 3 &pcfg_pull_none>,
	<4 RK_PA6 3 &pcfg_pull_none>,
	<4 RK_PB1 3 &pcfg_pull_none_12ma>,
	<4 RK_PA4 3 &pcfg_pull_none_12ma>,
	<4 RK_PA1 3 &pcfg_pull_none>,
	<4 RK_PA3 3 &pcfg_pull_none>;
	};

	rmii_pins: rmii-pins {
	rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
	<3 RK_PD7 3 &pcfg_pull_none>,
	<3 RK_PD4 3 &pcfg_pull_none>,
	<3 RK_PD5 3 &pcfg_pull_none>,
	<4 RK_PA0 3 &pcfg_pull_none>,
	<4 RK_PA5 3 &pcfg_pull_none>,
	<4 RK_PA4 3 &pcfg_pull_none>,
	<4 RK_PA1 3 &pcfg_pull_none>,
	<4 RK_PA2 3 &pcfg_pull_none>,
	<4 RK_PA3 3 &pcfg_pull_none>;
	};
	};

	spdif {
	spdif_tx: spdif-tx {
	rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/rk3xxx.dtsi b/sys/gnu/dts/arm/rk3xxx.dtsi
	index 241f43e29c77..d929b60517ab 100644
	--- a/sys/gnu/dts/arm/rk3xxx.dtsi
	+++ b/sys/gnu/dts/arm/rk3xxx.dtsi
	@@ -1,469 +1,469 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2013 MundoReader S.L.
	* Author: Heiko Stuebner <heiko@sntech.de>
	*/

	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/soc/rockchip,boot-mode.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	aliases {
	ethernet0 = &emac;
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	mshc0 = &emmc;
	mshc1 = &mmc0;
	mshc2 = &mmc1;
	serial0 = &uart0;
	serial1 = &uart1;
	serial2 = &uart2;
	serial3 = &uart3;
	spi0 = &spi0;
	spi1 = &spi1;
	};

	- amba {
	+ amba: bus {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	dmac1_s: dma-controller@20018000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x20018000 0x4000>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	arm,pl330-broken-no-flushp;
	clocks = <&cru ACLK_DMA1>;
	clock-names = "apb_pclk";
	};

	dmac1_ns: dma-controller@2001c000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x2001c000 0x4000>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	arm,pl330-broken-no-flushp;
	clocks = <&cru ACLK_DMA1>;
	clock-names = "apb_pclk";
	status = "disabled";
	};

	dmac2: dma-controller@20078000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x20078000 0x4000>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	arm,pl330-broken-no-flushp;
	clocks = <&cru ACLK_DMA2>;
	clock-names = "apb_pclk";
	};
	};

	xin24m: oscillator {
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	#clock-cells = <0>;
	clock-output-names = "xin24m";
	};

	gpu: gpu@10090000 {
	compatible = "arm,mali-400";
	reg = <0x10090000 0x10000>;
	clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
	- clock-names = "core", "bus";
	+ clock-names = "bus", "core";
	assigned-clocks = <&cru ACLK_GPU>;
	assigned-clock-rates = <100000000>;
	resets = <&cru SRST_GPU>;
	status = "disabled";
	};

	- L2: l2-cache-controller@10138000 {
	+ L2: cache-controller@10138000 {
	compatible = "arm,pl310-cache";
	reg = <0x10138000 0x1000>;
	cache-unified;
	cache-level = <2>;
	};

	scu@1013c000 {
	compatible = "arm,cortex-a9-scu";
	reg = <0x1013c000 0x100>;
	};

	global_timer: global-timer@1013c200 {
	compatible = "arm,cortex-a9-global-timer";
	reg = <0x1013c200 0x20>;
	interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_EDGE_RISING)>;
	clocks = <&cru CORE_PERI>;
	};

	local_timer: local-timer@1013c600 {
	compatible = "arm,cortex-a9-twd-timer";
	reg = <0x1013c600 0x20>;
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_EDGE_RISING)>;
	clocks = <&cru CORE_PERI>;
	};

	gic: interrupt-controller@1013d000 {
	compatible = "arm,cortex-a9-gic";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0x1013d000 0x1000>,
	<0x1013c100 0x0100>;
	};

	uart0: serial@10124000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x10124000 0x400>;
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <1>;
	clock-names = "baudclk", "apb_pclk";
	clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
	status = "disabled";
	};

	uart1: serial@10126000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x10126000 0x400>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <1>;
	clock-names = "baudclk", "apb_pclk";
	clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
	status = "disabled";
	};

	qos_gpu: qos@1012d000 {
	compatible = "syscon";
	reg = <0x1012d000 0x20>;
	};

	qos_vpu: qos@1012e000 {
	compatible = "syscon";
	reg = <0x1012e000 0x20>;
	};

	qos_lcdc0: qos@1012f000 {
	compatible = "syscon";
	reg = <0x1012f000 0x20>;
	};

	qos_cif0: qos@1012f080 {
	compatible = "syscon";
	reg = <0x1012f080 0x20>;
	};

	qos_ipp: qos@1012f100 {
	compatible = "syscon";
	reg = <0x1012f100 0x20>;
	};

	qos_lcdc1: qos@1012f180 {
	compatible = "syscon";
	reg = <0x1012f180 0x20>;
	};

	qos_cif1: qos@1012f200 {
	compatible = "syscon";
	reg = <0x1012f200 0x20>;
	};

	qos_rga: qos@1012f280 {
	compatible = "syscon";
	reg = <0x1012f280 0x20>;
	};

	usb_otg: usb@10180000 {
	compatible = "rockchip,rk3066-usb", "snps,dwc2";
	reg = <0x10180000 0x40000>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_OTG0>;
	clock-names = "otg";
	dr_mode = "otg";
	g-np-tx-fifo-size = <16>;
	g-rx-fifo-size = <275>;
	g-tx-fifo-size = <256 128 128 64 64 32>;
	phys = <&usbphy0>;
	phy-names = "usb2-phy";
	status = "disabled";
	};

	usb_host: usb@101c0000 {
	compatible = "snps,dwc2";
	reg = <0x101c0000 0x40000>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_OTG1>;
	clock-names = "otg";
	dr_mode = "host";
	phys = <&usbphy1>;
	phy-names = "usb2-phy";
	status = "disabled";
	};

	emac: ethernet@10204000 {
	compatible = "snps,arc-emac";
	reg = <0x10204000 0x3c>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;

	rockchip,grf = <&grf>;

	clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
	clock-names = "hclk", "macref";
	max-speed = <100>;
	phy-mode = "rmii";

	status = "disabled";
	};

	mmc0: mmc@10214000 {
	compatible = "rockchip,rk2928-dw-mshc";
	reg = <0x10214000 0x1000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
	clock-names = "biu", "ciu";
	dmas = <&dmac2 1>;
	dma-names = "rx-tx";
	fifo-depth = <256>;
	resets = <&cru SRST_SDMMC>;
	reset-names = "reset";
	status = "disabled";
	};

	mmc1: mmc@10218000 {
	compatible = "rockchip,rk2928-dw-mshc";
	reg = <0x10218000 0x1000>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
	clock-names = "biu", "ciu";
	dmas = <&dmac2 3>;
	dma-names = "rx-tx";
	fifo-depth = <256>;
	resets = <&cru SRST_SDIO>;
	reset-names = "reset";
	status = "disabled";
	};

	emmc: mmc@1021c000 {
	compatible = "rockchip,rk2928-dw-mshc";
	reg = <0x1021c000 0x1000>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
	clock-names = "biu", "ciu";
	dmas = <&dmac2 4>;
	dma-names = "rx-tx";
	fifo-depth = <256>;
	resets = <&cru SRST_EMMC>;
	reset-names = "reset";
	status = "disabled";
	};

	pmu: pmu@20004000 {
	compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
	reg = <0x20004000 0x100>;

	reboot-mode {
	compatible = "syscon-reboot-mode";
	offset = <0x40>;
	mode-normal = <BOOT_NORMAL>;
	mode-recovery = <BOOT_RECOVERY>;
	mode-bootloader = <BOOT_FASTBOOT>;
	mode-loader = <BOOT_BL_DOWNLOAD>;
	};
	};

	grf: grf@20008000 {
	compatible = "syscon";
	reg = <0x20008000 0x200>;
	};

	i2c0: i2c@2002d000 {
	compatible = "rockchip,rk3066-i2c";
	reg = <0x2002d000 0x1000>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;

	rockchip,grf = <&grf>;

	clock-names = "i2c";
	clocks = <&cru PCLK_I2C0>;

	status = "disabled";
	};

	i2c1: i2c@2002f000 {
	compatible = "rockchip,rk3066-i2c";
	reg = <0x2002f000 0x1000>;
	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;

	rockchip,grf = <&grf>;

	clocks = <&cru PCLK_I2C1>;
	clock-names = "i2c";

	status = "disabled";
	};

	pwm0: pwm@20030000 {
	compatible = "rockchip,rk2928-pwm";
	reg = <0x20030000 0x10>;
	#pwm-cells = <2>;
	clocks = <&cru PCLK_PWM01>;
	status = "disabled";
	};

	pwm1: pwm@20030010 {
	compatible = "rockchip,rk2928-pwm";
	reg = <0x20030010 0x10>;
	#pwm-cells = <2>;
	clocks = <&cru PCLK_PWM01>;
	status = "disabled";
	};

	wdt: watchdog@2004c000 {
	compatible = "snps,dw-wdt";
	reg = <0x2004c000 0x100>;
	clocks = <&cru PCLK_WDT>;
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	pwm2: pwm@20050020 {
	compatible = "rockchip,rk2928-pwm";
	reg = <0x20050020 0x10>;
	#pwm-cells = <2>;
	clocks = <&cru PCLK_PWM23>;
	status = "disabled";
	};

	pwm3: pwm@20050030 {
	compatible = "rockchip,rk2928-pwm";
	reg = <0x20050030 0x10>;
	#pwm-cells = <2>;
	clocks = <&cru PCLK_PWM23>;
	status = "disabled";
	};

	i2c2: i2c@20056000 {
	compatible = "rockchip,rk3066-i2c";
	reg = <0x20056000 0x1000>;
	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;

	rockchip,grf = <&grf>;

	clocks = <&cru PCLK_I2C2>;
	clock-names = "i2c";

	status = "disabled";
	};

	i2c3: i2c@2005a000 {
	compatible = "rockchip,rk3066-i2c";
	reg = <0x2005a000 0x1000>;
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;

	rockchip,grf = <&grf>;

	clocks = <&cru PCLK_I2C3>;
	clock-names = "i2c";

	status = "disabled";
	};

	i2c4: i2c@2005e000 {
	compatible = "rockchip,rk3066-i2c";
	reg = <0x2005e000 0x1000>;
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;

	rockchip,grf = <&grf>;

	clocks = <&cru PCLK_I2C4>;
	clock-names = "i2c";

	status = "disabled";
	};

	uart2: serial@20064000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x20064000 0x400>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <1>;
	clock-names = "baudclk", "apb_pclk";
	clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
	status = "disabled";
	};

	uart3: serial@20068000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x20068000 0x400>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <1>;
	clock-names = "baudclk", "apb_pclk";
	clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
	status = "disabled";
	};

	saradc: saradc@2006c000 {
	compatible = "rockchip,saradc";
	reg = <0x2006c000 0x100>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	#io-channel-cells = <1>;
	clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
	clock-names = "saradc", "apb_pclk";
	resets = <&cru SRST_SARADC>;
	reset-names = "saradc-apb";
	status = "disabled";
	};

	spi0: spi@20070000 {
	compatible = "rockchip,rk3066-spi";
	clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
	clock-names = "spiclk", "apb_pclk";
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x20070000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	dmas = <&dmac2 10>, <&dmac2 11>;
	dma-names = "tx", "rx";
	status = "disabled";
	};

	spi1: spi@20074000 {
	compatible = "rockchip,rk3066-spi";
	clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
	clock-names = "spiclk", "apb_pclk";
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x20074000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	dmas = <&dmac2 12>, <&dmac2 13>;
	dma-names = "tx", "rx";
	status = "disabled";
	};
	};
	diff --git a/sys/gnu/dts/arm/rv1108.dtsi b/sys/gnu/dts/arm/rv1108.dtsi
	index 1fd06e7cb983..f9cfe2c80791 100644
	--- a/sys/gnu/dts/arm/rv1108.dtsi
	+++ b/sys/gnu/dts/arm/rv1108.dtsi
	@@ -1,941 +1,933 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/rv1108-cru.h>
	#include <dt-bindings/pinctrl/rockchip.h>
	#include <dt-bindings/thermal/thermal.h>
	/ {
	#address-cells = <1>;
	#size-cells = <1>;

	compatible = "rockchip,rv1108";

	interrupt-parent = <&gic>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	serial0 = &uart0;
	serial1 = &uart1;
	serial2 = &uart2;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@f00 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0xf00>;
	clock-latency = <40000>;
	clocks = <&cru ARMCLK>;
	#cooling-cells = <2>; /* min followed by max */
	dynamic-power-coefficient = <75>;
	operating-points-v2 = <&cpu_opp_table>;
	};
	};

	cpu_opp_table: opp_table {
	compatible = "operating-points-v2";

	opp-408000000 {
	opp-hz = /bits/ 64 <408000000>;
	opp-microvolt = <975000>;
	clock-latency-ns = <40000>;
	};
	opp-600000000 {
	opp-hz = /bits/ 64 <600000000>;
	opp-microvolt = <975000>;
	clock-latency-ns = <40000>;
	};
	opp-816000000 {
	opp-hz = /bits/ 64 <816000000>;
	opp-microvolt = <1025000>;
	clock-latency-ns = <40000>;
	};
	opp-1008000000 {
	opp-hz = /bits/ 64 <1008000000>;
	opp-microvolt = <1150000>;
	clock-latency-ns = <40000>;
	};
	};

	arm-pmu {
	compatible = "arm,cortex-a7-pmu";
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_HIGH)>;
	arm,cpu-registers-not-fw-configured;
	clock-frequency = <24000000>;
	};

	xin24m: oscillator {
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-output-names = "xin24m";
	#clock-cells = <0>;
	};

	- amba {
	+ amba: bus {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	pdma: pdma@102a0000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x102a0000 0x4000>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	arm,pl330-broken-no-flushp;
	clocks = <&cru ACLK_DMAC>;
	clock-names = "apb_pclk";
	};
	};

	- bus_intmem@10080000 {
	+ bus_intmem: sram@10080000 {
	compatible = "mmio-sram";
	reg = <0x10080000 0x2000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x10080000 0x2000>;
	};

	uart2: serial@10210000 {
	compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
	reg = <0x10210000 0x100>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clock-frequency = <24000000>;
	clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
	clock-names = "baudclk", "apb_pclk";
	dmas = <&pdma 6>, <&pdma 7>;
	- #dma-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart2m0_xfer>;
	status = "disabled";
	};

	uart1: serial@10220000 {
	compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
	reg = <0x10220000 0x100>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clock-frequency = <24000000>;
	clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
	clock-names = "baudclk", "apb_pclk";
	dmas = <&pdma 4>, <&pdma 5>;
	- #dma-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer>;
	status = "disabled";
	};

	uart0: serial@10230000 {
	compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
	reg = <0x10230000 0x100>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clock-frequency = <24000000>;
	clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
	clock-names = "baudclk", "apb_pclk";
	dmas = <&pdma 2>, <&pdma 3>;
	- #dma-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
	status = "disabled";
	};

	i2c1: i2c@10240000 {
	compatible = "rockchip,rv1108-i2c";
	reg = <0x10240000 0x1000>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
	clock-names = "i2c", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
	rockchip,grf = <&grf>;
	status = "disabled";
	};

	i2c2: i2c@10250000 {
	compatible = "rockchip,rv1108-i2c";
	reg = <0x10250000 0x1000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
	clock-names = "i2c", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2m1_xfer>;
	rockchip,grf = <&grf>;
	status = "disabled";
	};

	i2c3: i2c@10260000 {
	compatible = "rockchip,rv1108-i2c";
	reg = <0x10260000 0x1000>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
	clock-names = "i2c", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
	rockchip,grf = <&grf>;
	status = "disabled";
	};

	spi: spi@10270000 {
	compatible = "rockchip,rv1108-spi";
	reg = <0x10270000 0x1000>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
	clock-names = "spiclk", "apb_pclk";
	dmas = <&pdma 8>, <&pdma 9>;
	dma-names = "tx", "rx";
	- #dma-cells = <2>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	pwm4: pwm@10280000 {
	compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
	reg = <0x10280000 0x10>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm4_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm5: pwm@10280010 {
	compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
	reg = <0x10280010 0x10>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm5_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm6: pwm@10280020 {
	compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
	reg = <0x10280020 0x10>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm6_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm7: pwm@10280030 {
	compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
	reg = <0x10280030 0x10>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm7_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	grf: syscon@10300000 {
	compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
	reg = <0x10300000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;

	u2phy: usb2-phy@100 {
	compatible = "rockchip,rv1108-usb2phy";
	reg = <0x100 0x0c>;
	clocks = <&cru SCLK_USBPHY>;
	clock-names = "phyclk";
	#clock-cells = <0>;
	clock-output-names = "usbphy";
	rockchip,usbgrf = <&usbgrf>;
	status = "disabled";

	u2phy_otg: otg-port {
	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "otg-mux";
	#phy-cells = <0>;
	status = "disabled";
	};

	u2phy_host: host-port {
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "linestate";
	#phy-cells = <0>;
	status = "disabled";
	};
	};
	};

	timer: timer@10350000 {
	compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
	reg = <0x10350000 0x20>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&xin24m>, <&cru PCLK_TIMER>;
	clock-names = "timer", "pclk";
	};

	watchdog: wdt@10360000 {
	compatible = "snps,dw-wdt";
	reg = <0x10360000 0x100>;
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_WDT>;
	clock-names = "pclk_wdt";
	status = "disabled";
	};

	thermal-zones {
	soc_thermal: soc-thermal {
	polling-delay-passive = <20>;
	polling-delay = <1000>;
	sustainable-power = <50>;
	thermal-sensors = <&tsadc 0>;

	trips {
	threshold: trip-point0 {
	temperature = <70000>;
	hysteresis = <2000>;
	type = "passive";
	};
	target: trip-point1 {
	temperature = <85000>;
	hysteresis = <2000>;
	type = "passive";
	};
	soc_crit: soc-crit {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&target>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	contribution = <4096>;
	};
	};
	};
	};

	tsadc: tsadc@10370000 {
	compatible = "rockchip,rv1108-tsadc";
	reg = <0x10370000 0x100>;
	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	assigned-clocks = <&cru SCLK_TSADC>;
	assigned-clock-rates = <750000>;
	clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
	clock-names = "tsadc", "apb_pclk";
	pinctrl-names = "init", "default", "sleep";
	pinctrl-0 = <&otp_gpio>;
	pinctrl-1 = <&otp_out>;
	pinctrl-2 = <&otp_gpio>;
	resets = <&cru SRST_TSADC>;
	reset-names = "tsadc-apb";
	rockchip,hw-tshut-temp = <120000>;
	#thermal-sensor-cells = <1>;
	status = "disabled";
	};

	adc: adc@1038c000 {
	compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
	reg = <0x1038c000 0x100>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#io-channel-cells = <1>;
	- clock-frequency = <1000000>;
	clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
	clock-names = "saradc", "apb_pclk";
	status = "disabled";
	};

	i2c0: i2c@20000000 {
	compatible = "rockchip,rv1108-i2c";
	reg = <0x20000000 0x1000>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
	clock-names = "i2c", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
	rockchip,grf = <&grf>;
	status = "disabled";
	};

	pwm0: pwm@20040000 {
	compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
	reg = <0x20040000 0x10>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm1: pwm@20040010 {
	compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
	reg = <0x20040010 0x10>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm2: pwm@20040020 {
	compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
	reg = <0x20040020 0x10>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm3: pwm@20040030 {
	compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
	reg = <0x20040030 0x10>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pmugrf: syscon@20060000 {
	compatible = "rockchip,rv1108-pmugrf", "syscon";
	reg = <0x20060000 0x1000>;
	};

	usbgrf: syscon@202a0000 {
	compatible = "rockchip,rv1108-usbgrf", "syscon";
	reg = <0x202a0000 0x1000>;
	};

	cru: clock-controller@20200000 {
	compatible = "rockchip,rv1108-cru";
	reg = <0x20200000 0x1000>;
	rockchip,grf = <&grf>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	emmc: mmc@30110000 {
	compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x30110000 0x4000>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
	<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	max-frequency = <150000000>;
	status = "disabled";
	};

	sdio: mmc@30120000 {
	compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x30120000 0x4000>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
	<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	max-frequency = <150000000>;
	status = "disabled";
	};

	sdmmc: mmc@30130000 {
	compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x30130000 0x4000>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
	<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	max-frequency = <100000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
	status = "disabled";
	};

	usb_host_ehci: usb@30140000 {
	compatible = "generic-ehci";
	reg = <0x30140000 0x20000>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_HOST0>, <&u2phy>;
	- clock-names = "usbhost", "utmi";
	phys = <&u2phy_host>;
	phy-names = "usb";
	status = "disabled";
	};

	usb_host_ohci: usb@30160000 {
	compatible = "generic-ohci";
	reg = <0x30160000 0x20000>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_HOST0>, <&u2phy>;
	- clock-names = "usbhost", "utmi";
	phys = <&u2phy_host>;
	phy-names = "usb";
	status = "disabled";
	};

	usb_otg: usb@30180000 {
	compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
	"snps,dwc2";
	reg = <0x30180000 0x40000>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_OTG>;
	clock-names = "otg";
	dr_mode = "otg";
	g-np-tx-fifo-size = <16>;
	g-rx-fifo-size = <280>;
	g-tx-fifo-size = <256 128 128 64 32 16>;
	- g-use-dma;
	phys = <&u2phy_otg>;
	phy-names = "usb2-phy";
	status = "disabled";
	};

	gmac: eth@30200000 {
	compatible = "rockchip,rv1108-gmac";
	reg = <0x30200000 0x10000>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq", "eth_wake_irq";
	clocks = <&cru SCLK_MAC>,
	<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
	<&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
	<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
	clock-names = "stmmaceth",
	"mac_clk_rx", "mac_clk_tx",
	"clk_mac_ref", "clk_mac_refout",
	"aclk_mac", "pclk_mac";
	/* rv1108 only supports an rmii interface */
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&rmii_pins>;
	rockchip,grf = <&grf>;
	status = "disabled";
	};

	gic: interrupt-controller@32010000 {
	compatible = "arm,gic-400";
	interrupt-controller;
	#interrupt-cells = <3>;
	#address-cells = <0>;

	reg = <0x32011000 0x1000>,
	<0x32012000 0x2000>,
	<0x32014000 0x2000>,
	<0x32016000 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	pinctrl: pinctrl {
	compatible = "rockchip,rv1108-pinctrl";
	rockchip,grf = <&grf>;
	rockchip,pmu = <&pmugrf>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	gpio0: gpio0@20030000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x20030000 0x100>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO0_PMU>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio1: gpio1@10310000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x10310000 0x100>;
	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO1>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio2@10320000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x10320000 0x100>;
	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO2>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio3@10330000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x10330000 0x100>;
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO3>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	pcfg_pull_up: pcfg-pull-up {
	bias-pull-up;
	};

	pcfg_pull_down: pcfg-pull-down {
	bias-pull-down;
	};

	pcfg_pull_none: pcfg-pull-none {
	bias-disable;
	};

	pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
	drive-strength = <8>;
	};

	pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
	drive-strength = <12>;
	};

	pcfg_pull_none_smt: pcfg-pull-none-smt {
	bias-disable;
	input-schmitt-enable;
	};

	pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
	bias-pull-up;
	drive-strength = <8>;
	};

	pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
	drive-strength = <4>;
	};

	pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
	bias-pull-up;
	drive-strength = <4>;
	};

	pcfg_output_high: pcfg-output-high {
	output-high;
	};

	pcfg_output_low: pcfg-output-low {
	output-low;
	};

	pcfg_input_high: pcfg-input-high {
	bias-pull-up;
	input-enable;
	};

	emmc {
	emmc_bus8: emmc-bus8 {
	rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>,
	<2 RK_PA1 2 &pcfg_pull_up_drv_8ma>,
	<2 RK_PA2 2 &pcfg_pull_up_drv_8ma>,
	<2 RK_PA3 2 &pcfg_pull_up_drv_8ma>,
	<2 RK_PA4 2 &pcfg_pull_up_drv_8ma>,
	<2 RK_PA5 2 &pcfg_pull_up_drv_8ma>,
	<2 RK_PA6 2 &pcfg_pull_up_drv_8ma>,
	<2 RK_PA7 2 &pcfg_pull_up_drv_8ma>;
	};

	emmc_clk: emmc-clk {
	rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>;
	};

	emmc_cmd: emmc-cmd {
	rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>;
	};
	};

	gmac {
	rmii_pins: rmii-pins {
	rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
	<1 RK_PC3 2 &pcfg_pull_none>,
	<1 RK_PC4 2 &pcfg_pull_none>,
	<1 RK_PB2 3 &pcfg_pull_none_drv_12ma>,
	<1 RK_PB3 3 &pcfg_pull_none_drv_12ma>,
	<1 RK_PB4 3 &pcfg_pull_none_drv_12ma>,
	<1 RK_PB5 3 &pcfg_pull_none>,
	<1 RK_PB6 3 &pcfg_pull_none>,
	<1 RK_PB7 3 &pcfg_pull_none>,
	<1 RK_PC2 3 &pcfg_pull_none>;
	};
	};

	i2c0 {
	i2c0_xfer: i2c0-xfer {
	rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>,
	<0 RK_PB2 1 &pcfg_pull_none_smt>;
	};
	};

	i2c1 {
	i2c1_xfer: i2c1-xfer {
	rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>,
	<2 RK_PD4 1 &pcfg_pull_up>;
	};
	};

	i2c2m1 {
	i2c2m1_xfer: i2c2m1-xfer {
	rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>,
	<0 RK_PC6 3 &pcfg_pull_none>;
	};

	i2c2m1_gpio: i2c2m1-gpio {
	rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
	<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	i2c2m05v {
	i2c2m05v_xfer: i2c2m05v-xfer {
	rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>,
	<1 RK_PD4 2 &pcfg_pull_none>;
	};

	i2c2m05v_gpio: i2c2m05v-gpio {
	rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
	<1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	i2c3 {
	i2c3_xfer: i2c3-xfer {
	rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>,
	<0 RK_PC4 2 &pcfg_pull_none>;
	};
	};

	pwm0 {
	pwm0_pin: pwm0-pin {
	rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>;
	};
	};

	pwm1 {
	pwm1_pin: pwm1-pin {
	rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
	};
	};

	pwm2 {
	pwm2_pin: pwm2-pin {
	rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>;
	};
	};

	pwm3 {
	pwm3_pin: pwm3-pin {
	rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>;
	};
	};

	pwm4 {
	pwm4_pin: pwm4-pin {
	rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>;
	};
	};

	pwm5 {
	pwm5_pin: pwm5-pin {
	rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>;
	};
	};

	pwm6 {
	pwm6_pin: pwm6-pin {
	rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
	};
	};

	pwm7 {
	pwm7_pin: pwm7-pin {
	rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>;
	};
	};

	sdmmc {
	sdmmc_clk: sdmmc-clk {
	rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>;
	};

	sdmmc_cmd: sdmmc-cmd {
	rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>;
	};

	sdmmc_cd: sdmmc-cd {
	rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>;
	};

	sdmmc_bus1: sdmmc-bus1 {
	rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>;
	};

	sdmmc_bus4: sdmmc-bus4 {
	rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>,
	<3 RK_PC2 1 &pcfg_pull_up_drv_4ma>,
	<3 RK_PC1 1 &pcfg_pull_up_drv_4ma>,
	<3 RK_PC0 1 &pcfg_pull_up_drv_4ma>;
	};
	};

	spim0 {
	spim0_clk: spim0-clk {
	rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>;
	};

	spim0_cs0: spim0-cs0 {
	rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>;
	};

	spim0_tx: spim0-tx {
	rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
	};

	spim0_rx: spim0-rx {
	rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
	};
	};

	spim1 {
	spim1_clk: spim1-clk {
	rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
	};

	spim1_cs0: spim1-cs0 {
	rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>;
	};

	spim1_rx: spim1-rx {
	rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>;
	};

	spim1_tx: spim1-tx {
	rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>;
	};
	};

	tsadc {
	otp_out: otp-out {
	rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
	};

	otp_gpio: otp-gpio {
	rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	uart0 {
	uart0_xfer: uart0-xfer {
	rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>,
	<3 RK_PA5 1 &pcfg_pull_none>;
	};

	uart0_cts: uart0-cts {
	rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
	};

	uart0_rts: uart0-rts {
	rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
	};

	uart0_rts_gpio: uart0-rts-gpio {
	rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	uart1 {
	uart1_xfer: uart1-xfer {
	rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>,
	<1 RK_PD2 1 &pcfg_pull_none>;
	};

	uart1_cts: uart1-cts {
	rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
	};

	uart1_rts: uart1-rts {
	rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
	};
	};

	uart2m0 {
	uart2m0_xfer: uart2m0-xfer {
	rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>,
	<2 RK_PD1 1 &pcfg_pull_none>;
	};
	};

	uart2m1 {
	uart2m1_xfer: uart2m1-xfer {
	rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>,
	<3 RK_PC2 2 &pcfg_pull_none>;
	};
	};

	uart2_5v {
	uart2_5v_cts: uart2_5v-cts {
	rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
	};

	uart2_5v_rts: uart2_5v-rts {
	rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/sam9x60.dtsi b/sys/gnu/dts/arm/sam9x60.dtsi
	index 326b39328b58..6763423d64b8 100644
	--- a/sys/gnu/dts/arm/sam9x60.dtsi
	+++ b/sys/gnu/dts/arm/sam9x60.dtsi
	@@ -1,691 +1,699 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
	*
	* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
	*
	* Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
	*/

	#include <dt-bindings/dma/at91.h>
	#include <dt-bindings/pinctrl/at91.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/clock/at91.h>
	#include <dt-bindings/mfd/atmel-flexcom.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Microchip SAM9X60 SoC";
	compatible = "microchip,sam9x60";
	interrupt-parent = <&aic>;

	aliases {
	serial0 = &dbgu;
	gpio0 = &pioA;
	gpio1 = &pioB;
	gpio2 = &pioC;
	gpio3 = &pioD;
	tcb0 = &tcb0;
	tcb1 = &tcb1;
	};

	cpus {
	#address-cells = <0>;
	#size-cells = <0>;

	cpu {
	compatible = "arm,arm926ej-s";
	device_type = "cpu";
	};
	};

	memory {
	device_type = "memory";
	reg = <0x20000000 0x10000000>;
	};

	clocks {
	slow_xtal: slow_xtal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	};

	main_xtal: main_xtal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	};
	};

	sram: sram@300000 {
	compatible = "mmio-sram";
	reg = <0x00300000 0x100000>;
	};

	ahb {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	usb1: ohci@600000 {
	compatible = "atmel,at91rm9200-ohci", "usb-ohci";
	reg = <0x00600000 0x100000>;
	interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
	clock-names = "ohci_clk", "hclk", "uhpck";
	status = "disabled";
	};

	usb2: ehci@700000 {
	compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
	reg = <0x00700000 0x100000>;
	interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
	clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
	clock-names = "usb_clk", "ehci_clk";
	assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
	assigned-clock-rates = <480000000>;
	status = "disabled";
	};

	ebi: ebi@10000000 {
	compatible = "microchip,sam9x60-ebi";
	#address-cells = <2>;
	#size-cells = <1>;
	atmel,smc = <&smc>;
	microchip,sfr = <&sfr>;
	reg = <0x10000000 0x60000000>;
	ranges = <0x0 0x0 0x10000000 0x10000000
	0x1 0x0 0x20000000 0x10000000
	0x2 0x0 0x30000000 0x10000000
	0x3 0x0 0x40000000 0x10000000
	0x4 0x0 0x50000000 0x10000000
	0x5 0x0 0x60000000 0x10000000>;
	clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
	status = "disabled";

	nand_controller: nand-controller {
	compatible = "microchip,sam9x60-nand-controller";
	ecc-engine = <&pmecc>;
	#address-cells = <2>;
	#size-cells = <1>;
	ranges;
	status = "disabled";
	};
	};

	sdmmc0: sdio-host@80000000 {
	compatible = "microchip,sam9x60-sdhci";
	reg = <0x80000000 0x300>;
	interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
	clock-names = "hclock", "multclk";
	assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
	assigned-clock-rates = <100000000>;
	status = "disabled";
	};

	sdmmc1: sdio-host@90000000 {
	compatible = "microchip,sam9x60-sdhci";
	reg = <0x90000000 0x300>;
	interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
	clock-names = "hclock", "multclk";
	assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
	assigned-clock-rates = <100000000>;
	status = "disabled";
	};

	apb {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	flx4: flexcom@f0000000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xf0000000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf0000000 0x800>;
	status = "disabled";
	};

	flx5: flexcom@f0004000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xf0004000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf0004000 0x800>;
	status = "disabled";
	};

	dma0: dma-controller@f0008000 {
	compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
	reg = <0xf0008000 0x1000>;
	interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
	#dma-cells = <1>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
	clock-names = "dma_clk";
	};

	ssc: ssc@f0010000 {
	compatible = "atmel,at91sam9g45-ssc";
	reg = <0xf0010000 0x4000>;
	interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(38))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(39))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
	clock-names = "pclk";
	status = "disabled";
	};

	qspi: spi@f0014000 {
	compatible = "microchip,sam9x60-qspi";
	reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
	reg-names = "qspi_base", "qspi_mmap";
	interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(26))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(27))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>;
	clock-names = "pclk", "qspick";
	atmel,pmc = <&pmc>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2s: i2s@f001c000 {
	compatible = "microchip,sam9x60-i2smcc";
	reg = <0xf001c000 0x100>;
	interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(36))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(37))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
	clock-names = "pclk", "gclk";
	status = "disabled";
	};

	flx11: flexcom@f0020000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xf0020000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf0020000 0x800>;
	status = "disabled";
	};

	flx12: flexcom@f0024000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xf0024000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf0024000 0x800>;
	status = "disabled";
	};

	pit64b: timer@f0028000 {
	compatible = "microchip,sam9x60-pit64b";
	reg = <0xf0028000 0x100>;
	interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
	clock-names = "pclk", "gclk";
	};

	sha: sha@f002c000 {
	compatible = "atmel,at91sam9g46-sha";
	reg = <0xf002c000 0x100>;
	interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(34))>;
	dma-names = "tx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
	clock-names = "sha_clk";
	status = "okay";
	};

	trng: trng@f0030000 {
	compatible = "microchip,sam9x60-trng";
	reg = <0xf0030000 0x100>;
	interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
	status = "okay";
	};

	aes: aes@f0034000 {
	compatible = "atmel,at91sam9g46-aes";
	reg = <0xf0034000 0x100>;
	interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(32))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(33))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
	clock-names = "aes_clk";
	status = "okay";
	};

	tdes: tdes@f0038000 {
	compatible = "atmel,at91sam9g46-tdes";
	reg = <0xf0038000 0x100>;
	interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(31))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(30))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
	clock-names = "tdes_clk";
	status = "okay";
	};

	classd: classd@f003c000 {
	compatible = "atmel,sama5d2-classd";
	reg = <0xf003c000 0x100>;
	interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(35))>;
	dma-names = "tx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
	clock-names = "pclk", "gclk";
	status = "disabled";
	};

	can0: can@f8000000 {
	compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
	reg = <0xf8000000 0x300>;
	interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
	clock-names = "can_clk";
	status = "disabled";
	};

	can1: can@f8004000 {
	compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
	reg = <0xf8004000 0x300>;
	interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
	clock-names = "can_clk";
	status = "disabled";
	};

	tcb0: timer@f8008000 {
	compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xf8008000 0x100>;
	interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
	clock-names = "t0_clk", "slow_clk";
	};

	tcb1: timer@f800c000 {
	compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xf800c000 0x100>;
	interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
	clock-names = "t0_clk", "slow_clk";
	};

	flx6: flexcom@f8010000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xf8010000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf8010000 0x800>;
	status = "disabled";
	};

	flx7: flexcom@f8014000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xf8014000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf8014000 0x800>;
	status = "disabled";
	};

	flx8: flexcom@f8018000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xf8018000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf8018000 0x800>;
	status = "disabled";
	};

	flx0: flexcom@f801c000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xf801c000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf801c000 0x800>;
	status = "disabled";
	};

	flx1: flexcom@f8020000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xf8020000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf8020000 0x800>;
	status = "disabled";
	};

	flx2: flexcom@f8024000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xf8024000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf8024000 0x800>;
	status = "disabled";
	};

	flx3: flexcom@f8028000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xf8028000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf8028000 0x800>;
	status = "disabled";
	};

	macb0: ethernet@f802c000 {
	compatible = "cdns,sam9x60-macb", "cdns,macb";
	reg = <0xf802c000 0x1000>;
	interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
	clock-names = "hclk", "pclk";
	status = "disabled";
	};

	macb1: ethernet@f8030000 {
	compatible = "cdns,sam9x60-macb", "cdns,macb";
	reg = <0xf8030000 0x1000>;
	interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
	clock-names = "hclk", "pclk";
	status = "disabled";
	};

	pwm0: pwm@f8034000 {
	compatible = "microchip,sam9x60-pwm";
	reg = <0xf8034000 0x300>;
	interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
	#pwm-cells = <3>;
	status="disabled";
	};

	hlcdc: hlcdc@f8038000 {
	compatible = "microchip,sam9x60-hlcdc";
	reg = <0xf8038000 0x4000>;
	interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
	clock-names = "periph_clk","sys_clk", "slow_clk";
	assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
	assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
	status = "disabled";

	hlcdc-display-controller {
	compatible = "atmel,hlcdc-display-controller";
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;
	};
	};

	hlcdc_pwm: hlcdc-pwm {
	compatible = "atmel,hlcdc-pwm";
	#pwm-cells = <3>;
	};
	};

	flx9: flexcom@f8040000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xf8040000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf8040000 0x800>;
	status = "disabled";
	};

	flx10: flexcom@f8044000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xf8044000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf8044000 0x800>;
	status = "disabled";
	};

	isi: isi@f8048000 {
	compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
	reg = <0xf8048000 0x100>;
	interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
	clock-names = "isi_clk";
	status = "disabled";
	port {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	adc: adc@f804c000 {
	compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
	reg = <0xf804c000 0x100>;
	interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
	clock-names = "adc_clk";
	dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \| AT91_XDMAC_DT_PERID(40))>;
	dma-names = "rx";
	atmel,min-sample-rate-hz = <200000>;
	atmel,max-sample-rate-hz = <20000000>;
	atmel,startup-time-ms = <4>;
	atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
	#io-channel-cells = <1>;
	status = "disabled";
	};

	sfr: sfr@f8050000 {
	compatible = "microchip,sam9x60-sfr", "syscon";
	reg = <0xf8050000 0x100>;
	};

	matrix: matrix@ffffde00 {
	compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
	reg = <0xffffde00 0x200>;
	};

	pmecc: ecc-engine@ffffe000 {
	compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
	reg = <0xffffe000 0x300>,
	<0xffffe600 0x100>;
	};

	mpddrc: mpddrc@ffffe800 {
	compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
	reg = <0xffffe800 0x200>;
	clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
	clock-names = "ddrck", "mpddr";
	};

	smc: smc@ffffea00 {
	compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
	reg = <0xffffea00 0x100>;
	};

	aic: interrupt-controller@fffff100 {
	compatible = "microchip,sam9x60-aic";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0xfffff100 0x100>;
	atmel,external-irqs = <31>;
	};

	dbgu: serial@fffff200 {
	compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
	reg = <0xfffff200 0x200>;
	interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(28))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(29))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
	clock-names = "usart";
	status = "disabled";
	};

	pinctrl: pinctrl@fffff400 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
	ranges = <0xfffff400 0xfffff400 0x800>;

	pioA: gpio@fffff400 {
	compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	reg = <0xfffff400 0x200>;
	interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
	#gpio-cells = <2>;
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
	};

	pioB: gpio@fffff600 {
	compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	reg = <0xfffff600 0x200>;
	interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
	#gpio-cells = <2>;
	gpio-controller;
	#gpio-lines = <26>;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
	};

	pioC: gpio@fffff800 {
	compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	reg = <0xfffff800 0x200>;
	interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
	#gpio-cells = <2>;
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
	};

	pioD: gpio@fffffa00 {
	compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	reg = <0xfffffa00 0x200>;
	interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
	#gpio-cells = <2>;
	gpio-controller;
	#gpio-lines = <22>;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
	};
	};

	pmc: pmc@fffffc00 {
	compatible = "microchip,sam9x60-pmc", "syscon";
	reg = <0xfffffc00 0x200>;
	interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
	#clock-cells = <2>;
	clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
	clock-names = "td_slck", "md_slck", "main_xtal";
	};

	reset_controller: rstc@fffffe00 {
	compatible = "microchip,sam9x60-rstc";
	reg = <0xfffffe00 0x10>;
	clocks = <&clk32k 0>;
	};

	shutdown_controller: shdwc@fffffe10 {
	compatible = "microchip,sam9x60-shdwc";
	reg = <0xfffffe10 0x10>;
	clocks = <&clk32k 0>;
	#address-cells = <1>;
	#size-cells = <0>;
	atmel,wakeup-rtc-timer;
	atmel,wakeup-rtt-timer;
	status = "disabled";
	};

	pit: timer@fffffe40 {
	compatible = "atmel,at91sam9260-pit";
	reg = <0xfffffe40 0x10>;
	interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
	clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
	};

	clk32k: sckc@fffffe50 {
	compatible = "microchip,sam9x60-sckc";
	reg = <0xfffffe50 0x4>;
	clocks = <&slow_xtal>;
	#clock-cells = <1>;
	};

	gpbr: syscon@fffffe60 {
	compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
	reg = <0xfffffe60 0x10>;
	};

	rtc: rtc@fffffea8 {
	compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
	reg = <0xfffffea8 0x100>;
	interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
	clocks = <&clk32k 0>;
	};
	+
	+ watchdog: watchdog@ffffff80 {
	+ compatible = "microchip,sam9x60-wdt";
	+ reg = <0xffffff80 0x24>;
	+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
	+ clocks = <&clk32k 0>;
	+ status = "disabled";
	+ };
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/sama5d2.dtsi b/sys/gnu/dts/arm/sama5d2.dtsi
	index 2012b7407c60..ab550d69db91 100644
	--- a/sys/gnu/dts/arm/sama5d2.dtsi
	+++ b/sys/gnu/dts/arm/sama5d2.dtsi
	@@ -1,974 +1,974 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
	*
	* Copyright (C) 2015 Atmel,
	* 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
	*/

	#include <dt-bindings/dma/at91.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/clock/at91.h>
	#include <dt-bindings/iio/adc/at91-sama5d2_adc.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Atmel SAMA5D2 family SoC";
	compatible = "atmel,sama5d2";
	interrupt-parent = <&aic>;

	aliases {
	serial0 = &uart1;
	serial1 = &uart3;
	tcb0 = &tcb0;
	tcb1 = &tcb1;
	i2s0 = &i2s0;
	i2s1 = &i2s1;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a5";
	reg = <0>;
	next-level-cache = <&L2>;
	};
	};

	pmu {
	compatible = "arm,cortex-a5-pmu";
	interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
	};

	etb {
	compatible = "arm,coresight-etb10", "arm,primecell";
	reg = <0x740000 0x1000>;

	clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
	clock-names = "apb_pclk";

	in-ports {
	port {
	etb_in: endpoint {
	remote-endpoint = <&etm_out>;
	};
	};
	};
	};

	etm {
	compatible = "arm,coresight-etm3x", "arm,primecell";
	reg = <0x73C000 0x1000>;

	clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	etm_out: endpoint {
	remote-endpoint = <&etb_in>;
	};
	};
	};
	};

	memory {
	device_type = "memory";
	reg = <0x20000000 0x20000000>;
	};

	clocks {
	slow_xtal: slow_xtal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	main_xtal: main_xtal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	};

	ns_sram: sram@200000 {
	compatible = "mmio-sram";
	reg = <0x00200000 0x20000>;
	};

	ahb {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	nfc_sram: sram@100000 {
	compatible = "mmio-sram";
	no-memory-wc;
	reg = <0x00100000 0x2400>;
	};

	usb0: gadget@300000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "atmel,sama5d3-udc";
	reg = <0x00300000 0x100000
	0xfc02c000 0x400>;
	interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
	clock-names = "pclk", "hclk";
	status = "disabled";

	ep@0 {
	reg = <0>;
	atmel,fifo-size = <64>;
	atmel,nb-banks = <1>;
	};

	ep@1 {
	reg = <1>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <3>;
	atmel,can-dma;
	atmel,can-isoc;
	};

	ep@2 {
	reg = <2>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <3>;
	atmel,can-dma;
	atmel,can-isoc;
	};

	ep@3 {
	reg = <3>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-dma;
	atmel,can-isoc;
	};

	ep@4 {
	reg = <4>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-dma;
	atmel,can-isoc;
	};

	ep@5 {
	reg = <5>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-dma;
	atmel,can-isoc;
	};

	ep@6 {
	reg = <6>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-dma;
	atmel,can-isoc;
	};

	ep@7 {
	reg = <7>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-dma;
	atmel,can-isoc;
	};

	ep@8 {
	reg = <8>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-isoc;
	};

	ep@9 {
	reg = <9>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-isoc;
	};

	ep@10 {
	reg = <10>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-isoc;
	};

	ep@11 {
	reg = <11>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-isoc;
	};

	ep@12 {
	reg = <12>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-isoc;
	};

	ep@13 {
	reg = <13>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-isoc;
	};

	ep@14 {
	reg = <14>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-isoc;
	};

	ep@15 {
	reg = <15>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-isoc;
	};
	};

	usb1: ohci@400000 {
	compatible = "atmel,at91rm9200-ohci", "usb-ohci";
	reg = <0x00400000 0x100000>;
	interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>;
	clock-names = "ohci_clk", "hclk", "uhpck";
	status = "disabled";
	};

	usb2: ehci@500000 {
	compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
	reg = <0x00500000 0x100000>;
	interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
	clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>;
	clock-names = "usb_clk", "ehci_clk";
	status = "disabled";
	};

	L2: cache-controller@a00000 {
	compatible = "arm,pl310-cache";
	reg = <0x00a00000 0x1000>;
	interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
	cache-unified;
	cache-level = <2>;
	};

	ebi: ebi@10000000 {
	compatible = "atmel,sama5d3-ebi";
	#address-cells = <2>;
	#size-cells = <1>;
	atmel,smc = <&hsmc>;
	reg = <0x10000000 0x10000000
	0x60000000 0x30000000>;
	ranges = <0x0 0x0 0x10000000 0x10000000
	0x1 0x0 0x60000000 0x10000000
	0x2 0x0 0x70000000 0x10000000
	0x3 0x0 0x80000000 0x10000000>;
	clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
	status = "disabled";

	nand_controller: nand-controller {
	compatible = "atmel,sama5d3-nand-controller";
	atmel,nfc-sram = <&nfc_sram>;
	atmel,nfc-io = <&nfc_io>;
	ecc-engine = <&pmecc>;
	#address-cells = <2>;
	#size-cells = <1>;
	ranges;
	status = "disabled";
	};
	};

	sdmmc0: sdio-host@a0000000 {
	compatible = "atmel,sama5d2-sdhci";
	reg = <0xa0000000 0x300>;
	interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
	clock-names = "hclock", "multclk", "baseclk";
	assigned-clocks = <&pmc PMC_TYPE_GCK 31>;
	assigned-clock-rates = <480000000>;
	status = "disabled";
	};

	sdmmc1: sdio-host@b0000000 {
	compatible = "atmel,sama5d2-sdhci";
	reg = <0xb0000000 0x300>;
	interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
	clock-names = "hclock", "multclk", "baseclk";
	assigned-clocks = <&pmc PMC_TYPE_GCK 32>;
	assigned-clock-rates = <480000000>;
	status = "disabled";
	};

	nfc_io: nfc-io@c0000000 {
	compatible = "atmel,sama5d3-nfc-io", "syscon";
	reg = <0xc0000000 0x8000000>;
	};

	apb {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	hlcdc: hlcdc@f0000000 {
	compatible = "atmel,sama5d2-hlcdc";
	reg = <0xf0000000 0x2000>;
	interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
	clock-names = "periph_clk","sys_clk", "slow_clk";
	status = "disabled";

	hlcdc-display-controller {
	compatible = "atmel,hlcdc-display-controller";
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;
	};
	};

	hlcdc_pwm: hlcdc-pwm {
	compatible = "atmel,hlcdc-pwm";
	#pwm-cells = <3>;
	};
	};

	isc: isc@f0008000 {
	compatible = "atmel,sama5d2-isc";
	reg = <0xf0008000 0x4000>;
	interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>;
	clock-names = "hclock", "iscck", "gck";
	#clock-cells = <0>;
	clock-output-names = "isc-mck";
	status = "disabled";
	};

	ramc0: ramc@f000c000 {
	compatible = "atmel,sama5d3-ddramc";
	reg = <0xf000c000 0x200>;
	clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>;
	clock-names = "ddrck", "mpddr";
	};

	dma0: dma-controller@f0010000 {
	compatible = "atmel,sama5d4-dma";
	reg = <0xf0010000 0x1000>;
	interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
	#dma-cells = <1>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
	clock-names = "dma_clk";
	};

	/* Place dma1 here despite its address */
	dma1: dma-controller@f0004000 {
	compatible = "atmel,sama5d4-dma";
	reg = <0xf0004000 0x1000>;
	interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
	#dma-cells = <1>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
	clock-names = "dma_clk";
	};

	pmc: pmc@f0014000 {
	compatible = "atmel,sama5d2-pmc", "syscon";
	reg = <0xf0014000 0x160>;
	interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
	#clock-cells = <2>;
	clocks = <&clk32k>, <&main_xtal>;
	clock-names = "slow_clk", "main_xtal";
	};

	qspi0: spi@f0020000 {
	compatible = "atmel,sama5d2-qspi";
	reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
	reg-names = "qspi_base", "qspi_mmap";
	interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	qspi1: spi@f0024000 {
	compatible = "atmel,sama5d2-qspi";
	reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
	reg-names = "qspi_base", "qspi_mmap";
	interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	sha@f0028000 {
	compatible = "atmel,at91sam9g46-sha";
	reg = <0xf0028000 0x100>;
	interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(30))>;
	dma-names = "tx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
	clock-names = "sha_clk";
	status = "okay";
	};

	aes@f002c000 {
	compatible = "atmel,at91sam9g46-aes";
	reg = <0xf002c000 0x100>;
	interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(26))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(27))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
	clock-names = "aes_clk";
	status = "okay";
	};

	spi0: spi@f8000000 {
	compatible = "atmel,at91rm9200-spi";
	reg = <0xf8000000 0x100>;
	interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(6))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(7))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
	clock-names = "spi_clk";
	atmel,fifo-size = <16>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	ssc0: ssc@f8004000 {
	compatible = "atmel,at91sam9g45-ssc";
	reg = <0xf8004000 0x4000>;
	interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(21))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(22))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
	clock-names = "pclk";
	status = "disabled";
	};

	macb0: ethernet@f8008000 {
	compatible = "atmel,sama5d2-gem";
	reg = <0xf8008000 0x1000>;
	interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
	66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
	67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>;
	clock-names = "hclk", "pclk";
	status = "disabled";
	};

	tcb0: timer@f800c000 {
	compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xf800c000 0x100>;
	interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&clk32k>;
	clock-names = "t0_clk", "slow_clk";
	};

	tcb1: timer@f8010000 {
	compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xf8010000 0x100>;
	interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&clk32k>;
	clock-names = "t0_clk", "slow_clk";
	};

	hsmc: hsmc@f8014000 {
	compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
	reg = <0xf8014000 0x1000>;
	interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	pmecc: ecc-engine@f8014070 {
	compatible = "atmel,sama5d2-pmecc";
	reg = <0xf8014070 0x490>,
	<0xf8014500 0x100>;
	};
	};

	pdmic: pdmic@f8018000 {
	compatible = "atmel,sama5d2-pdmic";
	reg = <0xf8018000 0x124>;
	interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(50))>;
	dma-names = "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>;
	clock-names = "pclk", "gclk";
	status = "disabled";
	};

	uart0: serial@f801c000 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xf801c000 0x100>;
	interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(35))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(36))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
	clock-names = "usart";
	status = "disabled";
	};

	uart1: serial@f8020000 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xf8020000 0x100>;
	interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(37))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(38))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
	clock-names = "usart";
	status = "disabled";
	};

	uart2: serial@f8024000 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xf8024000 0x100>;
	interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(39))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(40))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
	clock-names = "usart";
	status = "disabled";
	};

	i2c0: i2c@f8028000 {
	compatible = "atmel,sama5d2-i2c";
	reg = <0xf8028000 0x100>;
	interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(0))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(1))>;
	dma-names = "tx", "rx";
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
	atmel,fifo-size = <16>;
	status = "disabled";
	};

	pwm0: pwm@f802c000 {
	compatible = "atmel,sama5d2-pwm";
	reg = <0xf802c000 0x4000>;
	interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
	#pwm-cells = <3>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
	status = "disabled";
	};

	sfr: sfr@f8030000 {
	compatible = "atmel,sama5d2-sfr", "syscon";
	reg = <0xf8030000 0x98>;
	};

	flx0: flexcom@f8034000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xf8034000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf8034000 0x800>;
	status = "disabled";
	};

	flx1: flexcom@f8038000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xf8038000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf8038000 0x800>;
	status = "disabled";
	};

	securam: sram@f8044000 {
	compatible = "atmel,sama5d2-securam", "mmio-sram";
	reg = <0xf8044000 0x1420>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 51>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0xf8044000 0x1420>;
	};

	reset_controller: rstc@f8048000 {
	compatible = "atmel,sama5d3-rstc";
	reg = <0xf8048000 0x10>;
	clocks = <&clk32k>;
	};

	shutdown_controller: shdwc@f8048010 {
	compatible = "atmel,sama5d2-shdwc";
	reg = <0xf8048010 0x10>;
	clocks = <&clk32k>;
	#address-cells = <1>;
	#size-cells = <0>;
	atmel,wakeup-rtc-timer;
	};

	pit: timer@f8048030 {
	compatible = "atmel,at91sam9260-pit";
	reg = <0xf8048030 0x10>;
	interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
	clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
	};

	watchdog: watchdog@f8048040 {
	compatible = "atmel,sama5d4-wdt";
	reg = <0xf8048040 0x10>;
	interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
	clocks = <&clk32k>;
	status = "disabled";
	};

	clk32k: sckc@f8048050 {
	compatible = "atmel,sama5d4-sckc";
	reg = <0xf8048050 0x4>;

	clocks = <&slow_xtal>;
	#clock-cells = <0>;
	};

	rtc: rtc@f80480b0 {
	- compatible = "atmel,at91rm9200-rtc";
	+ compatible = "atmel,sama5d2-rtc";
	reg = <0xf80480b0 0x30>;
	interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
	clocks = <&clk32k>;
	};

	i2s0: i2s@f8050000 {
	compatible = "atmel,sama5d2-i2s";
	reg = <0xf8050000 0x100>;
	interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(31))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(32))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>;
	clock-names = "pclk", "gclk";
	assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>;
	assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>;
	status = "disabled";
	};

	can0: can@f8054000 {
	compatible = "bosch,m_can";
	reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
	reg-names = "m_can", "message_ram";
	interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
	<64 IRQ_TYPE_LEVEL_HIGH 7>;
	interrupt-names = "int0", "int1";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>;
	clock-names = "hclk", "cclk";
	assigned-clocks = <&pmc PMC_TYPE_GCK 56>;
	assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
	assigned-clock-rates = <40000000>;
	bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
	status = "disabled";
	};

	spi1: spi@fc000000 {
	compatible = "atmel,at91rm9200-spi";
	reg = <0xfc000000 0x100>;
	interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(8))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(9))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
	clock-names = "spi_clk";
	atmel,fifo-size = <16>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart3: serial@fc008000 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xfc008000 0x100>;
	interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(41))>,
	<&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(42))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
	clock-names = "usart";
	status = "disabled";
	};

	uart4: serial@fc00c000 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xfc00c000 0x100>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(43))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(44))>;
	dma-names = "tx", "rx";
	interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
	clock-names = "usart";
	status = "disabled";
	};

	flx2: flexcom@fc010000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xfc010000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xfc010000 0x800>;
	status = "disabled";
	};

	flx3: flexcom@fc014000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xfc014000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xfc014000 0x800>;
	status = "disabled";
	};

	flx4: flexcom@fc018000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xfc018000 0x200>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xfc018000 0x800>;
	status = "disabled";
	};

	trng@fc01c000 {
	compatible = "atmel,at91sam9g45-trng";
	reg = <0xfc01c000 0x100>;
	interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
	};

	aic: interrupt-controller@fc020000 {
	#interrupt-cells = <3>;
	compatible = "atmel,sama5d2-aic";
	interrupt-controller;
	reg = <0xfc020000 0x200>;
	atmel,external-irqs = <49>;
	};

	i2c1: i2c@fc028000 {
	compatible = "atmel,sama5d2-i2c";
	reg = <0xfc028000 0x100>;
	interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(2))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(3))>;
	dma-names = "tx", "rx";
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
	atmel,fifo-size = <16>;
	status = "disabled";
	};

	adc: adc@fc030000 {
	compatible = "atmel,sama5d2-adc";
	reg = <0xfc030000 0x100>;
	interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
	clock-names = "adc_clk";
	dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \| AT91_XDMAC_DT_PERID(25))>;
	dma-names = "rx";
	atmel,min-sample-rate-hz = <200000>;
	atmel,max-sample-rate-hz = <20000000>;
	atmel,startup-time-ms = <4>;
	atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
	#io-channel-cells = <1>;
	status = "disabled";
	};

	resistive_touch: resistive-touch {
	compatible = "resistive-adc-touch";
	io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>,
	<&adc AT91_SAMA5D2_ADC_Y_CHANNEL>,
	<&adc AT91_SAMA5D2_ADC_P_CHANNEL>;
	io-channel-names = "x", "y", "pressure";
	touchscreen-min-pressure = <50000>;
	status = "disabled";
	};

	pioA: pinctrl@fc038000 {
	compatible = "atmel,sama5d2-pinctrl";
	reg = <0xfc038000 0x600>;
	interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
	<68 IRQ_TYPE_LEVEL_HIGH 7>,
	<69 IRQ_TYPE_LEVEL_HIGH 7>,
	<70 IRQ_TYPE_LEVEL_HIGH 7>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
	};

	pioBU: secumod@fc040000 {
	compatible = "atmel,sama5d2-secumod", "syscon";
	reg = <0xfc040000 0x100>;

	gpio-controller;
	#gpio-cells = <2>;
	};

	tdes@fc044000 {
	compatible = "atmel,at91sam9g46-tdes";
	reg = <0xfc044000 0x100>;
	interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(28))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(29))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
	clock-names = "tdes_clk";
	status = "okay";
	};

	classd: classd@fc048000 {
	compatible = "atmel,sama5d2-classd";
	reg = <0xfc048000 0x100>;
	interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(47))>;
	dma-names = "tx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
	clock-names = "pclk", "gclk";
	status = "disabled";
	};

	i2s1: i2s@fc04c000 {
	compatible = "atmel,sama5d2-i2s";
	reg = <0xfc04c000 0x100>;
	interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(33))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	AT91_XDMAC_DT_PERID(34))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>;
	clock-names = "pclk", "gclk";
	assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>;
	assigned-parrents = <&pmc PMC_TYPE_GCK 55>;
	status = "disabled";
	};

	can1: can@fc050000 {
	compatible = "bosch,m_can";
	reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
	reg-names = "m_can", "message_ram";
	interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
	<65 IRQ_TYPE_LEVEL_HIGH 7>;
	interrupt-names = "int0", "int1";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
	clock-names = "hclk", "cclk";
	assigned-clocks = <&pmc PMC_TYPE_GCK 57>;
	assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
	assigned-clock-rates = <40000000>;
	bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
	status = "disabled";
	};

	sfrbu: sfr@fc05c000 {
	compatible = "atmel,sama5d2-sfrbu", "syscon";
	reg = <0xfc05c000 0x20>;
	};

	chipid@fc069000 {
	compatible = "atmel,sama5d2-chipid";
	reg = <0xfc069000 0x8>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/sama5d3.dtsi b/sys/gnu/dts/arm/sama5d3.dtsi
	index 203d40be70a5..f11b018e9173 100644
	--- a/sys/gnu/dts/arm/sama5d3.dtsi
	+++ b/sys/gnu/dts/arm/sama5d3.dtsi
	@@ -1,1561 +1,1588 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	/*
	* sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
	* applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
	*
	* Copyright (C) 2013 Atmel,
	* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
	*/

	#include <dt-bindings/dma/at91.h>
	#include <dt-bindings/pinctrl/at91.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/clock/at91.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Atmel SAMA5D3 family SoC";
	compatible = "atmel,sama5d3", "atmel,sama5";
	interrupt-parent = <&aic>;

	aliases {
	serial0 = &dbgu;
	serial1 = &usart0;
	serial2 = &usart1;
	serial3 = &usart2;
	serial4 = &usart3;
	serial5 = &uart0;
	gpio0 = &pioA;
	gpio1 = &pioB;
	gpio2 = &pioC;
	gpio3 = &pioD;
	gpio4 = &pioE;
	tcb0 = &tcb0;
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	ssc0 = &ssc0;
	ssc1 = &ssc1;
	pwm0 = &pwm0;
	};
	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a5";
	reg = <0x0>;
	};
	};

	pmu {
	compatible = "arm,cortex-a5-pmu";
	interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
	};

	memory {
	device_type = "memory";
	reg = <0x20000000 0x8000000>;
	};

	clocks {
	slow_xtal: slow_xtal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	main_xtal: main_xtal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	adc_op_clk: adc_op_clk{
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <1000000>;
	};
	};

	sram: sram@300000 {
	compatible = "mmio-sram";
	reg = <0x00300000 0x20000>;
	};

	ahb {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	apb {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	mmc0: mmc@f0000000 {
	compatible = "atmel,hsmci";
	reg = <0xf0000000 0x600>;
	interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
	dma-names = "rxtx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&mci0_clk>;
	clock-names = "mci_clk";
	};

	spi0: spi@f0004000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "atmel,at91rm9200-spi";
	reg = <0xf0004000 0x100>;
	interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
	dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
	<&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi0>;
	clocks = <&spi0_clk>;
	clock-names = "spi_clk";
	status = "disabled";
	};

	ssc0: ssc@f0008000 {
	compatible = "atmel,at91sam9g45-ssc";
	reg = <0xf0008000 0x4000>;
	interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
	dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>,
	<&dma0 2 AT91_DMA_CFG_PER_ID(14)>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
	clocks = <&ssc0_clk>;
	clock-names = "pclk";
	status = "disabled";
	};

	tcb0: timer@f0010000 {
	compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xf0010000 0x100>;
	interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&tcb0_clk>, <&clk32k>;
	clock-names = "t0_clk", "slow_clk";
	};

	i2c0: i2c@f0014000 {
	compatible = "atmel,at91sam9x5-i2c";
	reg = <0xf0014000 0x4000>;
	interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
	dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
	<&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
	dma-names = "tx", "rx";
	- pinctrl-names = "default";
	+ pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c0>;
	+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
	+ sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
	+ scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&twi0_clk>;
	status = "disabled";
	};

	i2c1: i2c@f0018000 {
	compatible = "atmel,at91sam9x5-i2c";
	reg = <0xf0018000 0x4000>;
	interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
	dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
	<&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
	dma-names = "tx", "rx";
	- pinctrl-names = "default";
	+ pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
	+ sda-gpios = <&pioC 26 GPIO_ACTIVE_HIGH>;
	+ scl-gpios = <&pioC 27 GPIO_ACTIVE_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&twi1_clk>;
	status = "disabled";
	};

	usart0: serial@f001c000 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xf001c000 0x100>;
	interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
	dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
	<&dma0 2 (AT91_DMA_CFG_PER_ID(4) \| AT91_DMA_CFG_FIFOCFG_ASAP)>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usart0>;
	clocks = <&usart0_clk>;
	clock-names = "usart";
	status = "disabled";
	};

	usart1: serial@f0020000 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xf0020000 0x100>;
	interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
	dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>,
	<&dma0 2 (AT91_DMA_CFG_PER_ID(6) \| AT91_DMA_CFG_FIFOCFG_ASAP)>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usart1>;
	clocks = <&usart1_clk>;
	clock-names = "usart";
	status = "disabled";
	};

	uart0: serial@f0024000 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xf0024000 0x100>;
	interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	clocks = <&uart0_clk>;
	clock-names = "usart";
	status = "disabled";
	};

	pwm0: pwm@f002c000 {
	compatible = "atmel,sama5d3-pwm";
	reg = <0xf002c000 0x300>;
	interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
	#pwm-cells = <3>;
	clocks = <&pwm_clk>;
	status = "disabled";
	};

	isi: isi@f0034000 {
	compatible = "atmel,at91sam9g45-isi";
	reg = <0xf0034000 0x4000>;
	interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_isi_data_0_7>;
	clocks = <&isi_clk>;
	clock-names = "isi_clk";
	status = "disabled";
	port {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	sfr: sfr@f0038000 {
	compatible = "atmel,sama5d3-sfr", "syscon";
	reg = <0xf0038000 0x60>;
	};

	mmc1: mmc@f8000000 {
	compatible = "atmel,hsmci";
	reg = <0xf8000000 0x600>;
	interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
	dma-names = "rxtx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&mci1_clk>;
	clock-names = "mci_clk";
	};

	spi1: spi@f8008000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "atmel,at91rm9200-spi";
	reg = <0xf8008000 0x100>;
	interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
	dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
	<&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi1>;
	clocks = <&spi1_clk>;
	clock-names = "spi_clk";
	status = "disabled";
	};

	ssc1: ssc@f800c000 {
	compatible = "atmel,at91sam9g45-ssc";
	reg = <0xf800c000 0x4000>;
	interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
	dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>,
	<&dma1 2 AT91_DMA_CFG_PER_ID(4)>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
	clocks = <&ssc1_clk>;
	clock-names = "pclk";
	status = "disabled";
	};

	adc0: adc@f8018000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "atmel,at91sam9x5-adc";
	reg = <0xf8018000 0x100>;
	interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
	pinctrl-names = "default";
	pinctrl-0 = <
	&pinctrl_adc0_adtrg
	&pinctrl_adc0_ad0
	&pinctrl_adc0_ad1
	&pinctrl_adc0_ad2
	&pinctrl_adc0_ad3
	&pinctrl_adc0_ad4
	&pinctrl_adc0_ad5
	&pinctrl_adc0_ad6
	&pinctrl_adc0_ad7
	&pinctrl_adc0_ad8
	&pinctrl_adc0_ad9
	&pinctrl_adc0_ad10
	&pinctrl_adc0_ad11
	>;
	clocks = <&adc_clk>,
	<&adc_op_clk>;
	clock-names = "adc_clk", "adc_op_clk";
	atmel,adc-channels-used = <0xfff>;
	atmel,adc-startup-time = <40>;
	atmel,adc-use-external-triggers;
	atmel,adc-vref = <3000>;
	atmel,adc-res = <10 12>;
	atmel,adc-sample-hold-time = <11>;
	atmel,adc-res-names = "lowres", "highres";
	status = "disabled";

	trigger0 {
	trigger-name = "external-rising";
	trigger-value = <0x1>;
	trigger-external;
	};
	trigger1 {
	trigger-name = "external-falling";
	trigger-value = <0x2>;
	trigger-external;
	};
	trigger2 {
	trigger-name = "external-any";
	trigger-value = <0x3>;
	trigger-external;
	};
	trigger3 {
	trigger-name = "continuous";
	trigger-value = <0x6>;
	};
	};

	i2c2: i2c@f801c000 {
	compatible = "atmel,at91sam9x5-i2c";
	reg = <0xf801c000 0x4000>;
	interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
	dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
	<&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
	dma-names = "tx", "rx";
	- pinctrl-names = "default";
	+ pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
	+ sda-gpios = <&pioA 18 GPIO_ACTIVE_HIGH>;
	+ scl-gpios = <&pioA 19 GPIO_ACTIVE_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&twi2_clk>;
	status = "disabled";
	};

	usart2: serial@f8020000 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xf8020000 0x100>;
	interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
	dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>,
	<&dma1 2 (AT91_DMA_CFG_PER_ID(8) \| AT91_DMA_CFG_FIFOCFG_ASAP)>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usart2>;
	clocks = <&usart2_clk>;
	clock-names = "usart";
	status = "disabled";
	};

	usart3: serial@f8024000 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xf8024000 0x100>;
	interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
	dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>,
	<&dma1 2 (AT91_DMA_CFG_PER_ID(10) \| AT91_DMA_CFG_FIFOCFG_ASAP)>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usart3>;
	clocks = <&usart3_clk>;
	clock-names = "usart";
	status = "disabled";
	};

	sha@f8034000 {
	compatible = "atmel,at91sam9g46-sha";
	reg = <0xf8034000 0x100>;
	interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
	dma-names = "tx";
	clocks = <&sha_clk>;
	clock-names = "sha_clk";
	};

	aes@f8038000 {
	compatible = "atmel,at91sam9g46-aes";
	reg = <0xf8038000 0x100>;
	interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
	<&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
	dma-names = "tx", "rx";
	clocks = <&aes_clk>;
	clock-names = "aes_clk";
	};

	tdes@f803c000 {
	compatible = "atmel,at91sam9g46-tdes";
	reg = <0xf803c000 0x100>;
	interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
	<&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
	dma-names = "tx", "rx";
	clocks = <&tdes_clk>;
	clock-names = "tdes_clk";
	};

	trng@f8040000 {
	compatible = "atmel,at91sam9g45-trng";
	reg = <0xf8040000 0x100>;
	interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&trng_clk>;
	};

	hsmc: hsmc@ffffc000 {
	compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
	reg = <0xffffc000 0x1000>;
	interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
	clocks = <&hsmc_clk>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	pmecc: ecc-engine@ffffc070 {
	compatible = "atmel,at91sam9g45-pmecc";
	reg = <0xffffc070 0x490>,
	<0xffffc500 0x100>;
	};
	};

	dma0: dma-controller@ffffe600 {
	compatible = "atmel,at91sam9g45-dma";
	reg = <0xffffe600 0x200>;
	interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
	#dma-cells = <2>;
	clocks = <&dma0_clk>;
	clock-names = "dma_clk";
	};

	dma1: dma-controller@ffffe800 {
	compatible = "atmel,at91sam9g45-dma";
	reg = <0xffffe800 0x200>;
	interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
	#dma-cells = <2>;
	clocks = <&dma1_clk>;
	clock-names = "dma_clk";
	};

	ramc0: ramc@ffffea00 {
	compatible = "atmel,sama5d3-ddramc";
	reg = <0xffffea00 0x200>;
	clocks = <&ddrck>, <&mpddr_clk>;
	clock-names = "ddrck", "mpddr";
	};

	dbgu: serial@ffffee00 {
	compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
	reg = <0xffffee00 0x200>;
	interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
	dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
	<&dma1 2 (AT91_DMA_CFG_PER_ID(14) \| AT91_DMA_CFG_FIFOCFG_ASAP)>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dbgu>;
	clocks = <&dbgu_clk>;
	clock-names = "usart";
	status = "disabled";
	};

	aic: interrupt-controller@fffff000 {
	#interrupt-cells = <3>;
	compatible = "atmel,sama5d3-aic";
	interrupt-controller;
	reg = <0xfffff000 0x200>;
	atmel,external-irqs = <47>;
	};

	pinctrl: pinctrl@fffff200 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
	ranges = <0xfffff200 0xfffff200 0xa00>;
	atmel,mux-mask = <
	/* A B C */
	0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
	0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
	0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
	0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
	0xffffffff 0xbf9f8000 0x18000000 /* pioE */
	>;

	/* shared pinctrl settings */
	adc0 {
	pinctrl_adc0_adtrg: adc0_adtrg {
	atmel,pins =
	<AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
	};
	pinctrl_adc0_ad0: adc0_ad0 {
	atmel,pins =
	<AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
	};
	pinctrl_adc0_ad1: adc0_ad1 {
	atmel,pins =
	<AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
	};
	pinctrl_adc0_ad2: adc0_ad2 {
	atmel,pins =
	<AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
	};
	pinctrl_adc0_ad3: adc0_ad3 {
	atmel,pins =
	<AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
	};
	pinctrl_adc0_ad4: adc0_ad4 {
	atmel,pins =
	<AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
	};
	pinctrl_adc0_ad5: adc0_ad5 {
	atmel,pins =
	<AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
	};
	pinctrl_adc0_ad6: adc0_ad6 {
	atmel,pins =
	<AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
	};
	pinctrl_adc0_ad7: adc0_ad7 {
	atmel,pins =
	<AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
	};
	pinctrl_adc0_ad8: adc0_ad8 {
	atmel,pins =
	<AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
	};
	pinctrl_adc0_ad9: adc0_ad9 {
	atmel,pins =
	<AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
	};
	pinctrl_adc0_ad10: adc0_ad10 {
	atmel,pins =
	<AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
	};
	pinctrl_adc0_ad11: adc0_ad11 {
	atmel,pins =
	<AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
	};
	};

	dbgu {
	pinctrl_dbgu: dbgu-0 {
	atmel,pins =
	<AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
	AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};
	};

	ebi {
	pinctrl_ebi_addr: ebi-addr-0 {
	atmel,pins =
	<AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_nand_addr: ebi-addr-1 {
	atmel,pins =
	<AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_cs0: ebi-cs0-0 {
	atmel,pins =
	<AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_cs1: ebi-cs1-0 {
	atmel,pins =
	<AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_cs2: ebi-cs2-0 {
	atmel,pins =
	<AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_nwait: ebi-nwait-0 {
	atmel,pins =
	<AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
	atmel,pins =
	<AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};
	};

	i2c0 {
	pinctrl_i2c0: i2c0-0 {
	atmel,pins =
	<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
	AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
	};
	+
	+ pinctrl_i2c0_gpio: i2c0-gpio {
	+ atmel,pins =
	+ <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
	+ AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
	+ };
	};

	i2c1 {
	pinctrl_i2c1: i2c1-0 {
	atmel,pins =
	<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
	AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
	};
	+
	+ pinctrl_i2c1_gpio: i2c1-gpio {
	+ atmel,pins =
	+ <AT91_PIOC 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
	+ AT91_PIOC 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
	+ };
	};

	i2c2 {
	pinctrl_i2c2: i2c2-0 {
	atmel,pins =
	<AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
	AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
	};
	+
	+ pinctrl_i2c2_gpio: i2c2-gpio {
	+ atmel,pins =
	+ <AT91_PIOA 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
	+ AT91_PIOA 19 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
	+ };
	};

	isi {
	pinctrl_isi_data_0_7: isi-0-data-0-7 {
	atmel,pins =
	<AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
	AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
	AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
	AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
	AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
	AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
	AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
	AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
	AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
	AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
	AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
	};

	pinctrl_isi_data_8_9: isi-0-data-8-9 {
	atmel,pins =
	<AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
	AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
	};

	pinctrl_isi_data_10_11: isi-0-data-10-11 {
	atmel,pins =
	<AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC27 periph C ISI_PD10, conflicts with SPI1_NPCS2, TWCK1 */
	AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */
	};
	};

	mmc0 {
	pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
	atmel,pins =
	<AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
	AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
	AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
	};
	pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
	atmel,pins =
	<AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
	AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
	AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
	};
	pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
	atmel,pins =
	<AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
	AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
	AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
	AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
	};
	};

	mmc1 {
	pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
	atmel,pins =
	<AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
	AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
	AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
	};
	pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
	atmel,pins =
	<AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
	AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
	AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
	};
	};

	nand0 {
	pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
	atmel,pins =
	<AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
	AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
	};
	};

	pwm0 {
	pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
	atmel,pins =
	<AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */
	};
	pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 {
	atmel,pins =
	<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */
	};
	pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 {
	atmel,pins =
	<AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */
	};
	pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 {
	atmel,pins =
	<AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */
	};

	pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
	atmel,pins =
	<AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */
	};
	pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 {
	atmel,pins =
	<AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */
	};
	pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 {
	atmel,pins =
	<AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */
	};
	pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 {
	atmel,pins =
	<AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */
	};
	pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 {
	atmel,pins =
	<AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */
	};
	pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 {
	atmel,pins =
	<AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */
	};

	pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
	atmel,pins =
	<AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */
	};
	pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 {
	atmel,pins =
	<AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */
	};
	pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 {
	atmel,pins =
	<AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */
	};
	pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 {
	atmel,pins =
	<AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */
	};

	pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
	atmel,pins =
	<AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */
	};
	pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 {
	atmel,pins =
	<AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */
	};
	pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 {
	atmel,pins =
	<AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */
	};
	pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 {
	atmel,pins =
	<AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */
	};
	};

	spi0 {
	pinctrl_spi0: spi0-0 {
	atmel,pins =
	<AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
	AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
	AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
	};
	};

	spi1 {
	pinctrl_spi1: spi1-0 {
	atmel,pins =
	<AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
	AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
	AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
	};
	};

	ssc0 {
	pinctrl_ssc0_tx: ssc0_tx {
	atmel,pins =
	<AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
	AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
	AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
	};

	pinctrl_ssc0_rx: ssc0_rx {
	atmel,pins =
	<AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
	AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
	AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
	};
	};

	ssc1 {
	pinctrl_ssc1_tx: ssc1_tx {
	atmel,pins =
	<AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
	AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
	AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
	};

	pinctrl_ssc1_rx: ssc1_rx {
	atmel,pins =
	<AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
	AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
	AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
	};
	};

	uart0 {
	pinctrl_uart0: uart0-0 {
	atmel,pins =
	<AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* conflicts with PWMFI2, ISI_D8 */
	AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with ISI_PCK */
	};
	};

	uart1 {
	pinctrl_uart1: uart1-0 {
	atmel,pins =
	<AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* conflicts with TWD0, ISI_VSYNC */
	AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with TWCK0, ISI_HSYNC */
	};
	};

	usart0 {
	pinctrl_usart0: usart0-0 {
	atmel,pins =
	<AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
	AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
	atmel,pins =
	<AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
	AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
	};
	};

	usart1 {
	pinctrl_usart1: usart1-0 {
	atmel,pins =
	<AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
	AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
	atmel,pins =
	<AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
	AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
	};
	};

	usart2 {
	pinctrl_usart2: usart2-0 {
	atmel,pins =
	<AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* conflicts with A25 */
	AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts NCS0 */
	};

	pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
	atmel,pins =
	<AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
	AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
	};
	};

	usart3 {
	pinctrl_usart3: usart3-0 {
	atmel,pins =
	<AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* conflicts with A18 */
	AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with A19 */
	};

	pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
	atmel,pins =
	<AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
	AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
	};
	};


	pioA: gpio@fffff200 {
	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	reg = <0xfffff200 0x100>;
	interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
	#gpio-cells = <2>;
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pioA_clk>;
	};

	pioB: gpio@fffff400 {
	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	reg = <0xfffff400 0x100>;
	interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
	#gpio-cells = <2>;
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pioB_clk>;
	};

	pioC: gpio@fffff600 {
	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	reg = <0xfffff600 0x100>;
	interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
	#gpio-cells = <2>;
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pioC_clk>;
	};

	pioD: gpio@fffff800 {
	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	reg = <0xfffff800 0x100>;
	interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
	#gpio-cells = <2>;
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pioD_clk>;
	};

	pioE: gpio@fffffa00 {
	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	reg = <0xfffffa00 0x100>;
	interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
	#gpio-cells = <2>;
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pioE_clk>;
	};
	};

	pmc: pmc@fffffc00 {
	compatible = "atmel,sama5d3-pmc", "syscon";
	reg = <0xfffffc00 0x120>;
	interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
	interrupt-controller;
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;

	main_rc_osc: main_rc_osc {
	compatible = "atmel,at91sam9x5-clk-main-rc-osc";
	#clock-cells = <0>;
	interrupt-parent = <&pmc>;
	interrupts = <AT91_PMC_MOSCRCS>;
	clock-frequency = <12000000>;
	clock-accuracy = <50000000>;
	};

	main_osc: main_osc {
	compatible = "atmel,at91rm9200-clk-main-osc";
	#clock-cells = <0>;
	interrupt-parent = <&pmc>;
	interrupts = <AT91_PMC_MOSCS>;
	clocks = <&main_xtal>;
	};

	main: mainck {
	compatible = "atmel,at91sam9x5-clk-main";
	#clock-cells = <0>;
	interrupt-parent = <&pmc>;
	interrupts = <AT91_PMC_MOSCSELS>;
	clocks = <&main_rc_osc &main_osc>;
	};

	plla: pllack {
	compatible = "atmel,sama5d3-clk-pll";
	#clock-cells = <0>;
	interrupt-parent = <&pmc>;
	interrupts = <AT91_PMC_LOCKA>;
	clocks = <&main>;
	reg = <0>;
	atmel,clk-input-range = <8000000 50000000>;
	#atmel,pll-clk-output-range-cells = <4>;
	atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
	};

	plladiv: plladivck {
	compatible = "atmel,at91sam9x5-clk-plldiv";
	#clock-cells = <0>;
	clocks = <&plla>;
	};

	utmi: utmick {
	compatible = "atmel,at91sam9x5-clk-utmi";
	#clock-cells = <0>;
	interrupt-parent = <&pmc>;
	interrupts = <AT91_PMC_LOCKU>;
	clocks = <&main>;
	};

	mck: masterck {
	compatible = "atmel,at91sam9x5-clk-master";
	#clock-cells = <0>;
	interrupt-parent = <&pmc>;
	interrupts = <AT91_PMC_MCKRDY>;
	clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
	atmel,clk-output-range = <0 166000000>;
	atmel,clk-divisors = <1 2 4 3>;
	};

	usb: usbck {
	compatible = "atmel,at91sam9x5-clk-usb";
	#clock-cells = <0>;
	clocks = <&plladiv>, <&utmi>;
	};

	prog: progck {
	compatible = "atmel,at91sam9x5-clk-programmable";
	#address-cells = <1>;
	#size-cells = <0>;
	interrupt-parent = <&pmc>;
	clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;

	prog0: prog0 {
	#clock-cells = <0>;
	reg = <0>;
	interrupts = <AT91_PMC_PCKRDY(0)>;
	};

	prog1: prog1 {
	#clock-cells = <0>;
	reg = <1>;
	interrupts = <AT91_PMC_PCKRDY(1)>;
	};

	prog2: prog2 {
	#clock-cells = <0>;
	reg = <2>;
	interrupts = <AT91_PMC_PCKRDY(2)>;
	};
	};

	smd: smdclk {
	compatible = "atmel,at91sam9x5-clk-smd";
	#clock-cells = <0>;
	clocks = <&plladiv>, <&utmi>;
	};

	systemck {
	compatible = "atmel,at91rm9200-clk-system";
	#address-cells = <1>;
	#size-cells = <0>;

	ddrck: ddrck {
	#clock-cells = <0>;
	reg = <2>;
	clocks = <&mck>;
	};

	smdck: smdck {
	#clock-cells = <0>;
	reg = <4>;
	clocks = <&smd>;
	};

	uhpck: uhpck {
	#clock-cells = <0>;
	reg = <6>;
	clocks = <&usb>;
	};

	udpck: udpck {
	#clock-cells = <0>;
	reg = <7>;
	clocks = <&usb>;
	};

	pck0: pck0 {
	#clock-cells = <0>;
	reg = <8>;
	clocks = <&prog0>;
	};

	pck1: pck1 {
	#clock-cells = <0>;
	reg = <9>;
	clocks = <&prog1>;
	};

	pck2: pck2 {
	#clock-cells = <0>;
	reg = <10>;
	clocks = <&prog2>;
	};
	};

	periphck {
	compatible = "atmel,at91sam9x5-clk-peripheral";
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&mck>;

	dbgu_clk: dbgu_clk {
	#clock-cells = <0>;
	reg = <2>;
	};

	hsmc_clk: hsmc_clk {
	#clock-cells = <0>;
	reg = <5>;
	};

	pioA_clk: pioA_clk {
	#clock-cells = <0>;
	reg = <6>;
	};

	pioB_clk: pioB_clk {
	#clock-cells = <0>;
	reg = <7>;
	};

	pioC_clk: pioC_clk {
	#clock-cells = <0>;
	reg = <8>;
	};

	pioD_clk: pioD_clk {
	#clock-cells = <0>;
	reg = <9>;
	};

	pioE_clk: pioE_clk {
	#clock-cells = <0>;
	reg = <10>;
	};

	usart0_clk: usart0_clk {
	#clock-cells = <0>;
	reg = <12>;
	atmel,clk-output-range = <0 83000000>;
	};

	usart1_clk: usart1_clk {
	#clock-cells = <0>;
	reg = <13>;
	atmel,clk-output-range = <0 83000000>;
	};

	usart2_clk: usart2_clk {
	#clock-cells = <0>;
	reg = <14>;
	atmel,clk-output-range = <0 83000000>;
	};

	usart3_clk: usart3_clk {
	#clock-cells = <0>;
	reg = <15>;
	atmel,clk-output-range = <0 83000000>;
	};

	uart0_clk: uart0_clk {
	#clock-cells = <0>;
	reg = <16>;
	atmel,clk-output-range = <0 83000000>;
	};

	twi0_clk: twi0_clk {
	reg = <18>;
	#clock-cells = <0>;
	atmel,clk-output-range = <0 41500000>;
	};

	twi1_clk: twi1_clk {
	#clock-cells = <0>;
	reg = <19>;
	atmel,clk-output-range = <0 41500000>;
	};

	twi2_clk: twi2_clk {
	#clock-cells = <0>;
	reg = <20>;
	atmel,clk-output-range = <0 41500000>;
	};

	mci0_clk: mci0_clk {
	#clock-cells = <0>;
	reg = <21>;
	};

	mci1_clk: mci1_clk {
	#clock-cells = <0>;
	reg = <22>;
	};

	spi0_clk: spi0_clk {
	#clock-cells = <0>;
	reg = <24>;
	atmel,clk-output-range = <0 166000000>;
	};

	spi1_clk: spi1_clk {
	#clock-cells = <0>;
	reg = <25>;
	atmel,clk-output-range = <0 166000000>;
	};

	tcb0_clk: tcb0_clk {
	#clock-cells = <0>;
	reg = <26>;
	atmel,clk-output-range = <0 166000000>;
	};

	pwm_clk: pwm_clk {
	#clock-cells = <0>;
	reg = <28>;
	};

	adc_clk: adc_clk {
	#clock-cells = <0>;
	reg = <29>;
	atmel,clk-output-range = <0 83000000>;
	};

	dma0_clk: dma0_clk {
	#clock-cells = <0>;
	reg = <30>;
	};

	dma1_clk: dma1_clk {
	#clock-cells = <0>;
	reg = <31>;
	};

	uhphs_clk: uhphs_clk {
	#clock-cells = <0>;
	reg = <32>;
	};

	udphs_clk: udphs_clk {
	#clock-cells = <0>;
	reg = <33>;
	};

	isi_clk: isi_clk {
	#clock-cells = <0>;
	reg = <37>;
	};

	ssc0_clk: ssc0_clk {
	#clock-cells = <0>;
	reg = <38>;
	atmel,clk-output-range = <0 83000000>;
	};

	ssc1_clk: ssc1_clk {
	#clock-cells = <0>;
	reg = <39>;
	atmel,clk-output-range = <0 83000000>;
	};

	sha_clk: sha_clk {
	#clock-cells = <0>;
	reg = <42>;
	};

	aes_clk: aes_clk {
	#clock-cells = <0>;
	reg = <43>;
	};

	tdes_clk: tdes_clk {
	#clock-cells = <0>;
	reg = <44>;
	};

	trng_clk: trng_clk {
	#clock-cells = <0>;
	reg = <45>;
	};

	fuse_clk: fuse_clk {
	#clock-cells = <0>;
	reg = <48>;
	};

	mpddr_clk: mpddr_clk {
	#clock-cells = <0>;
	reg = <49>;
	};
	};
	};

	reset_controller: rstc@fffffe00 {
	compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
	reg = <0xfffffe00 0x10>;
	clocks = <&clk32k>;
	};

	shutdown_controller: shutdown-controller@fffffe10 {
	compatible = "atmel,at91sam9x5-shdwc";
	reg = <0xfffffe10 0x10>;
	clocks = <&clk32k>;
	};

	pit: timer@fffffe30 {
	compatible = "atmel,at91sam9260-pit";
	reg = <0xfffffe30 0xf>;
	interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
	clocks = <&mck>;
	};

	watchdog: watchdog@fffffe40 {
	compatible = "atmel,at91sam9260-wdt";
	reg = <0xfffffe40 0x10>;
	interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
	clocks = <&clk32k>;
	atmel,watchdog-type = "hardware";
	atmel,reset-type = "all";
	atmel,dbg-halt;
	status = "disabled";
	};

	clk32k: sckc@fffffe50 {
	compatible = "atmel,sama5d3-sckc";
	reg = <0xfffffe50 0x4>;
	clocks = <&slow_xtal>;
	#clock-cells = <0>;
	};

	rtc@fffffeb0 {
	compatible = "atmel,at91rm9200-rtc";
	reg = <0xfffffeb0 0x30>;
	interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
	clocks = <&clk32k>;
	};
	};

	nfc_sram: sram@200000 {
	compatible = "mmio-sram";
	no-memory-wc;
	reg = <0x200000 0x2400>;
	};

	usb0: gadget@500000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "atmel,sama5d3-udc";
	reg = <0x00500000 0x100000
	0xf8030000 0x4000>;
	interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
	clocks = <&udphs_clk>, <&utmi>;
	clock-names = "pclk", "hclk";
	status = "disabled";

	ep@0 {
	reg = <0>;
	atmel,fifo-size = <64>;
	atmel,nb-banks = <1>;
	};

	ep@1 {
	reg = <1>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <3>;
	atmel,can-dma;
	atmel,can-isoc;
	};

	ep@2 {
	reg = <2>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <3>;
	atmel,can-dma;
	atmel,can-isoc;
	};

	ep@3 {
	reg = <3>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-dma;
	};

	ep@4 {
	reg = <4>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-dma;
	};

	ep@5 {
	reg = <5>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-dma;
	};

	ep@6 {
	reg = <6>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-dma;
	};

	ep@7 {
	reg = <7>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-dma;
	};

	ep@8 {
	reg = <8>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	};

	ep@9 {
	reg = <9>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	};

	ep@10 {
	reg = <10>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	};

	ep@11 {
	reg = <11>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	};

	ep@12 {
	reg = <12>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	};

	ep@13 {
	reg = <13>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	};

	ep@14 {
	reg = <14>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	};

	ep@15 {
	reg = <15>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	};
	};

	usb1: ohci@600000 {
	compatible = "atmel,at91rm9200-ohci", "usb-ohci";
	reg = <0x00600000 0x100000>;
	interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
	clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
	clock-names = "ohci_clk", "hclk", "uhpck";
	status = "disabled";
	};

	usb2: ehci@700000 {
	compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
	reg = <0x00700000 0x100000>;
	interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
	clocks = <&utmi>, <&uhphs_clk>;
	clock-names = "usb_clk", "ehci_clk";
	status = "disabled";
	};

	ebi: ebi@10000000 {
	compatible = "atmel,sama5d3-ebi";
	#address-cells = <2>;
	#size-cells = <1>;
	atmel,smc = <&hsmc>;
	reg = <0x10000000 0x10000000
	0x40000000 0x30000000>;
	ranges = <0x0 0x0 0x10000000 0x10000000
	0x1 0x0 0x40000000 0x10000000
	0x2 0x0 0x50000000 0x10000000
	0x3 0x0 0x60000000 0x10000000>;
	clocks = <&mck>;
	status = "disabled";

	nand_controller: nand-controller {
	compatible = "atmel,sama5d3-nand-controller";
	atmel,nfc-sram = <&nfc_sram>;
	atmel,nfc-io = <&nfc_io>;
	ecc-engine = <&pmecc>;
	#address-cells = <2>;
	#size-cells = <1>;
	ranges;
	status = "disabled";
	};
	};

	nfc_io: nfc-io@70000000 {
	compatible = "atmel,sama5d3-nfc-io", "syscon";
	reg = <0x70000000 0x8000000>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/sama5d4.dtsi b/sys/gnu/dts/arm/sama5d4.dtsi
	index 6ab27a7b388d..c9c0316b5b0e 100644
	--- a/sys/gnu/dts/arm/sama5d4.dtsi
	+++ b/sys/gnu/dts/arm/sama5d4.dtsi
	@@ -1,1549 +1,1576 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
	*
	* Copyright (C) 2014 Atmel,
	* 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
	*/

	#include <dt-bindings/clock/at91.h>
	#include <dt-bindings/dma/at91.h>
	#include <dt-bindings/pinctrl/at91.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/gpio/gpio.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Atmel SAMA5D4 family SoC";
	compatible = "atmel,sama5d4";
	interrupt-parent = <&aic>;

	aliases {
	serial0 = &usart3;
	serial1 = &usart4;
	serial2 = &usart2;
	serial3 = &usart0;
	serial4 = &usart1;
	serial5 = &uart0;
	serial6 = &uart1;
	gpio0 = &pioA;
	gpio1 = &pioB;
	gpio2 = &pioC;
	gpio3 = &pioD;
	gpio4 = &pioE;
	pwm0 = &pwm0;
	ssc0 = &ssc0;
	ssc1 = &ssc1;
	tcb0 = &tcb0;
	tcb1 = &tcb1;
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	};
	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a5";
	reg = <0>;
	next-level-cache = <&L2>;
	};
	};

	memory {
	device_type = "memory";
	reg = <0x20000000 0x20000000>;
	};

	clocks {
	slow_xtal: slow_xtal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	main_xtal: main_xtal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	adc_op_clk: adc_op_clk{
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <1000000>;
	};
	};

	ns_sram: sram@210000 {
	compatible = "mmio-sram";
	reg = <0x00210000 0x10000>;
	};

	ahb {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	nfc_sram: sram@100000 {
	compatible = "mmio-sram";
	no-memory-wc;
	reg = <0x100000 0x2400>;
	};

	usb0: gadget@400000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "atmel,sama5d3-udc";
	reg = <0x00400000 0x100000
	0xfc02c000 0x4000>;
	interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
	clock-names = "pclk", "hclk";
	status = "disabled";

	ep@0 {
	reg = <0>;
	atmel,fifo-size = <64>;
	atmel,nb-banks = <1>;
	};

	ep@1 {
	reg = <1>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <3>;
	atmel,can-dma;
	atmel,can-isoc;
	};

	ep@2 {
	reg = <2>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <3>;
	atmel,can-dma;
	atmel,can-isoc;
	};

	ep@3 {
	reg = <3>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-dma;
	atmel,can-isoc;
	};

	ep@4 {
	reg = <4>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-dma;
	atmel,can-isoc;
	};

	ep@5 {
	reg = <5>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-dma;
	atmel,can-isoc;
	};

	ep@6 {
	reg = <6>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-dma;
	atmel,can-isoc;
	};

	ep@7 {
	reg = <7>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-dma;
	atmel,can-isoc;
	};

	ep@8 {
	reg = <8>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-isoc;
	};

	ep@9 {
	reg = <9>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-isoc;
	};

	ep@10 {
	reg = <10>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-isoc;
	};

	ep@11 {
	reg = <11>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-isoc;
	};

	ep@12 {
	reg = <12>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-isoc;
	};

	ep@13 {
	reg = <13>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-isoc;
	};

	ep@14 {
	reg = <14>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-isoc;
	};

	ep@15 {
	reg = <15>;
	atmel,fifo-size = <1024>;
	atmel,nb-banks = <2>;
	atmel,can-isoc;
	};
	};

	usb1: ohci@500000 {
	compatible = "atmel,at91rm9200-ohci", "usb-ohci";
	reg = <0x00500000 0x100000>;
	interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 6>;
	clock-names = "ohci_clk", "hclk", "uhpck";
	status = "disabled";
	};

	usb2: ehci@600000 {
	compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
	reg = <0x00600000 0x100000>;
	interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
	clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>;
	clock-names = "usb_clk", "ehci_clk";
	status = "disabled";
	};

	L2: cache-controller@a00000 {
	compatible = "arm,pl310-cache";
	reg = <0x00a00000 0x1000>;
	interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
	cache-unified;
	cache-level = <2>;
	};

	ebi: ebi@10000000 {
	compatible = "atmel,sama5d3-ebi";
	#address-cells = <2>;
	#size-cells = <1>;
	atmel,smc = <&hsmc>;
	reg = <0x10000000 0x10000000
	0x60000000 0x28000000>;
	ranges = <0x0 0x0 0x10000000 0x10000000
	0x1 0x0 0x60000000 0x10000000
	0x2 0x0 0x70000000 0x10000000
	0x3 0x0 0x80000000 0x8000000>;
	clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
	status = "disabled";

	nand_controller: nand-controller {
	compatible = "atmel,sama5d3-nand-controller";
	atmel,nfc-sram = <&nfc_sram>;
	atmel,nfc-io = <&nfc_io>;
	ecc-engine = <&pmecc>;
	#address-cells = <2>;
	#size-cells = <1>;
	ranges;
	status = "disabled";
	};
	};

	nfc_io: nfc-io@90000000 {
	compatible = "atmel,sama5d3-nfc-io", "syscon";
	reg = <0x90000000 0x8000000>;
	};

	apb {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	hlcdc: hlcdc@f0000000 {
	compatible = "atmel,sama5d4-hlcdc";
	reg = <0xf0000000 0x4000>;
	interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
	clock-names = "periph_clk","sys_clk", "slow_clk";
	status = "disabled";

	hlcdc-display-controller {
	compatible = "atmel,hlcdc-display-controller";
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;
	};
	};

	hlcdc_pwm: hlcdc-pwm {
	compatible = "atmel,hlcdc-pwm";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcd_pwm>;
	#pwm-cells = <3>;
	};
	};

	dma1: dma-controller@f0004000 {
	compatible = "atmel,sama5d4-dma";
	reg = <0xf0004000 0x200>;
	interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
	#dma-cells = <1>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 50>;
	clock-names = "dma_clk";
	};

	isi: isi@f0008000 {
	compatible = "atmel,at91sam9g45-isi";
	reg = <0xf0008000 0x4000>;
	interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_isi_data_0_7>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
	clock-names = "isi_clk";
	status = "disabled";
	port {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	ramc0: ramc@f0010000 {
	compatible = "atmel,sama5d3-ddramc";
	reg = <0xf0010000 0x200>;
	clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 16>;
	clock-names = "ddrck", "mpddr";
	};

	dma0: dma-controller@f0014000 {
	compatible = "atmel,sama5d4-dma";
	reg = <0xf0014000 0x200>;
	interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
	#dma-cells = <1>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
	clock-names = "dma_clk";
	};

	pmc: pmc@f0018000 {
	compatible = "atmel,sama5d4-pmc", "syscon";
	reg = <0xf0018000 0x120>;
	interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
	#clock-cells = <2>;
	clocks = <&clk32k>, <&main_xtal>;
	clock-names = "slow_clk", "main_xtal";
	};

	mmc0: mmc@f8000000 {
	compatible = "atmel,hsmci";
	reg = <0xf8000000 0x600>;
	interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(0))>;
	dma-names = "rxtx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 35>;
	clock-names = "mci_clk";
	};

	uart0: serial@f8004000 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xf8004000 0x100>;
	interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(22))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(23))>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
	clock-names = "usart";
	status = "disabled";
	};

	ssc0: ssc@f8008000 {
	compatible = "atmel,at91sam9g45-ssc";
	reg = <0xf8008000 0x4000>;
	interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
	dmas = <&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(26))>,
	<&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(27))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 48>;
	clock-names = "pclk";
	status = "disabled";
	};

	pwm0: pwm@f800c000 {
	compatible = "atmel,sama5d3-pwm";
	reg = <0xf800c000 0x300>;
	interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
	#pwm-cells = <3>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
	status = "disabled";
	};

	spi0: spi@f8010000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "atmel,at91rm9200-spi";
	reg = <0xf8010000 0x100>;
	interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
	dmas = <&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(10))>,
	<&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(11))>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
	clock-names = "spi_clk";
	status = "disabled";
	};

	i2c0: i2c@f8014000 {
	compatible = "atmel,sama5d4-i2c";
	reg = <0xf8014000 0x4000>;
	interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
	dmas = <&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(2))>,
	<&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(3))>;
	dma-names = "tx", "rx";
	- pinctrl-names = "default";
	+ pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c0>;
	+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
	+ sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
	+ scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
	status = "disabled";
	};

	i2c1: i2c@f8018000 {
	compatible = "atmel,sama5d4-i2c";
	reg = <0xf8018000 0x4000>;
	interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(4))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(5))>;
	dma-names = "tx", "rx";
	- pinctrl-names = "default";
	+ pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
	+ sda-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>;
	+ scl-gpios = <&pioE 30 GPIO_ACTIVE_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
	status = "disabled";
	};

	tcb0: timer@f801c000 {
	compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xf801c000 0x100>;
	interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 40>, <&clk32k>;
	clock-names = "t0_clk", "slow_clk";
	};

	macb0: ethernet@f8020000 {
	compatible = "atmel,sama5d4-gem";
	reg = <0xf8020000 0x100>;
	interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_macb0_rmii>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_PERIPHERAL 54>;
	clock-names = "hclk", "pclk";
	status = "disabled";
	};

	i2c2: i2c@f8024000 {
	compatible = "atmel,sama5d4-i2c";
	reg = <0xf8024000 0x4000>;
	interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
	dmas = <&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(6))>,
	<&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(7))>;
	dma-names = "tx", "rx";
	- pinctrl-names = "default";
	+ pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
	+ sda-gpios = <&pioB 29 GPIO_ACTIVE_HIGH>;
	+ scl-gpios = <&pioB 30 GPIO_ACTIVE_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
	status = "disabled";
	};

	sfr: sfr@f8028000 {
	compatible = "atmel,sama5d4-sfr", "syscon";
	reg = <0xf8028000 0x60>;
	};

	usart0: serial@f802c000 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xf802c000 0x100>;
	interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(36))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(37))>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
	clock-names = "usart";
	status = "disabled";
	};

	usart1: serial@f8030000 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xf8030000 0x100>;
	interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(38))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(39))>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
	clock-names = "usart";
	status = "disabled";
	};

	mmc1: mmc@fc000000 {
	compatible = "atmel,hsmci";
	reg = <0xfc000000 0x600>;
	interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(1))>;
	dma-names = "rxtx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
	clock-names = "mci_clk";
	};

	uart1: serial@fc004000 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xfc004000 0x100>;
	interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(24))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(25))>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
	clock-names = "usart";
	status = "disabled";
	};

	usart2: serial@fc008000 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xfc008000 0x100>;
	interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
	dmas = <&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(16))>,
	<&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(17))>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
	clock-names = "usart";
	status = "disabled";
	};

	usart3: serial@fc00c000 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xfc00c000 0x100>;
	interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
	dmas = <&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(18))>,
	<&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(19))>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usart3>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
	clock-names = "usart";
	status = "disabled";
	};

	usart4: serial@fc010000 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xfc010000 0x100>;
	interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
	dmas = <&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(20))>,
	<&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(21))>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usart4>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
	clock-names = "usart";
	status = "disabled";
	};

	ssc1: ssc@fc014000 {
	compatible = "atmel,at91sam9g45-ssc";
	reg = <0xfc014000 0x4000>;
	interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
	dmas = <&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(28))>,
	<&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(29))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
	clock-names = "pclk";
	status = "disabled";
	};

	spi1: spi@fc018000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "atmel,at91rm9200-spi";
	reg = <0xfc018000 0x100>;
	interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>;
	dmas = <&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(12))>,
	<&dma1
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(13))>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi1>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
	clock-names = "spi_clk";
	status = "disabled";
	};

	spi2: spi@fc01c000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "atmel,at91rm9200-spi";
	reg = <0xfc01c000 0x100>;
	interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>;
	dmas = <&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(14))>,
	<&dma0
	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(15))>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi2>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
	clock-names = "spi_clk";
	status = "disabled";
	};

	tcb1: timer@fc020000 {
	compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xfc020000 0x100>;
	interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&clk32k>;
	clock-names = "t0_clk", "slow_clk";
	};

	tcb2: timer@fc024000 {
	compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xfc024000 0x100>;
	interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&clk32k>;
	clock-names = "t0_clk", "slow_clk";
	};

	macb1: ethernet@fc028000 {
	compatible = "atmel,sama5d4-gem";
	reg = <0xfc028000 0x100>;
	interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_macb1_rmii>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_PERIPHERAL 55>;
	clock-names = "hclk", "pclk";
	status = "disabled";
	};

	trng@fc030000 {
	compatible = "atmel,at91sam9g45-trng";
	reg = <0xfc030000 0x100>;
	interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
	};

	adc0: adc@fc034000 {
	compatible = "atmel,at91sam9x5-adc";
	reg = <0xfc034000 0x100>;
	interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 44>,
	<&adc_op_clk>;
	clock-names = "adc_clk", "adc_op_clk";
	atmel,adc-channels-used = <0x01f>;
	atmel,adc-startup-time = <40>;
	atmel,adc-use-external-triggers;
	atmel,adc-vref = <3000>;
	atmel,adc-res = <8 10>;
	atmel,adc-sample-hold-time = <11>;
	atmel,adc-res-names = "lowres", "highres";
	atmel,adc-ts-pressure-threshold = <10000>;
	status = "disabled";

	trigger0 {
	trigger-name = "external-rising";
	trigger-value = <0x1>;
	trigger-external;
	};
	trigger1 {
	trigger-name = "external-falling";
	trigger-value = <0x2>;
	trigger-external;
	};
	trigger2 {
	trigger-name = "external-any";
	trigger-value = <0x3>;
	trigger-external;
	};
	trigger3 {
	trigger-name = "continuous";
	trigger-value = <0x6>;
	};
	};

	aes@fc044000 {
	compatible = "atmel,at91sam9g46-aes";
	reg = <0xfc044000 0x100>;
	interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(41))>,
	<&dma0 (AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(40))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
	clock-names = "aes_clk";
	status = "okay";
	};

	tdes@fc04c000 {
	compatible = "atmel,at91sam9g46-tdes";
	reg = <0xfc04c000 0x100>;
	interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(42))>,
	<&dma0 (AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(43))>;
	dma-names = "tx", "rx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
	clock-names = "tdes_clk";
	status = "okay";
	};

	sha@fc050000 {
	compatible = "atmel,at91sam9g46-sha";
	reg = <0xfc050000 0x100>;
	interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	\| AT91_XDMAC_DT_PERID(44))>;
	dma-names = "tx";
	clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
	clock-names = "sha_clk";
	status = "okay";
	};

	hsmc: smc@fc05c000 {
	compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
	reg = <0xfc05c000 0x1000>;
	interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	pmecc: ecc-engine@ffffc070 {
	compatible = "atmel,sama5d4-pmecc";
	reg = <0xfc05c070 0x490>,
	<0xfc05c500 0x100>;
	};
	};

	reset_controller: rstc@fc068600 {
	compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
	reg = <0xfc068600 0x10>;
	clocks = <&clk32k>;
	};

	shutdown_controller: shdwc@fc068610 {
	compatible = "atmel,at91sam9x5-shdwc";
	reg = <0xfc068610 0x10>;
	clocks = <&clk32k>;
	};

	pit: timer@fc068630 {
	compatible = "atmel,at91sam9260-pit";
	reg = <0xfc068630 0x10>;
	interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
	clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
	};

	watchdog: watchdog@fc068640 {
	compatible = "atmel,sama5d4-wdt";
	reg = <0xfc068640 0x10>;
	interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
	clocks = <&clk32k>;
	status = "disabled";
	};

	clk32k: sckc@fc068650 {
	compatible = "atmel,sama5d4-sckc";
	reg = <0xfc068650 0x4>;
	#clock-cells = <0>;
	clocks = <&slow_xtal>;
	};

	rtc@fc0686b0 {
	- compatible = "atmel,at91rm9200-rtc";
	+ compatible = "atmel,sama5d4-rtc";
	reg = <0xfc0686b0 0x30>;
	interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
	clocks = <&clk32k>;
	};

	dbgu: serial@fc069000 {
	compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
	reg = <0xfc069000 0x200>;
	interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dbgu>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
	clock-names = "usart";
	status = "disabled";
	};


	pinctrl: pinctrl@fc06a000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
	ranges = <0xfc068000 0xfc068000 0x100
	0xfc06a000 0xfc06a000 0x4000>;
	/* WARNING: revisit as pin spec has changed */
	atmel,mux-mask = <
	/* A B C */
	0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
	0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
	0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
	0x0003ff00 0x8002a800 0x00000000 /* pioD */
	0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
	>;

	pioA: gpio@fc06a000 {
	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	reg = <0xfc06a000 0x100>;
	interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
	#gpio-cells = <2>;
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
	};

	pioB: gpio@fc06b000 {
	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	reg = <0xfc06b000 0x100>;
	interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
	#gpio-cells = <2>;
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
	};

	pioC: gpio@fc06c000 {
	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	reg = <0xfc06c000 0x100>;
	interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
	#gpio-cells = <2>;
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
	};

	pioD: gpio@fc068000 {
	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	reg = <0xfc068000 0x100>;
	interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
	#gpio-cells = <2>;
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
	};

	pioE: gpio@fc06d000 {
	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	reg = <0xfc06d000 0x100>;
	interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
	#gpio-cells = <2>;
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
	};

	/* pinctrl pin settings */
	adc0 {
	pinctrl_adc0_adtrg: adc0_adtrg {
	atmel,pins =
	<AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
	};
	pinctrl_adc0_ad0: adc0_ad0 {
	atmel,pins =
	<AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};
	pinctrl_adc0_ad1: adc0_ad1 {
	atmel,pins =
	<AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};
	pinctrl_adc0_ad2: adc0_ad2 {
	atmel,pins =
	<AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};
	pinctrl_adc0_ad3: adc0_ad3 {
	atmel,pins =
	<AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};
	pinctrl_adc0_ad4: adc0_ad4 {
	atmel,pins =
	<AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};
	};

	dbgu {
	pinctrl_dbgu: dbgu-0 {
	atmel,pins =
	<AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* conflicts with D14 and TDI */
	AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with D15 and TDO */
	};
	};

	ebi {
	pinctrl_ebi_addr: ebi-addr-0 {
	atmel,pins =
	<AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_nand_addr: ebi-addr-1 {
	atmel,pins =
	<AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_cs0: ebi-cs0-0 {
	atmel,pins =
	<AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_cs1: ebi-cs1-0 {
	atmel,pins =
	<AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_cs2: ebi-cs2-0 {
	atmel,pins =
	<AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_cs3: ebi-cs3-0 {
	atmel,pins =
	<AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
	atmel,pins =
	<AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_data_8_15: ebi-data-msb-0 {
	atmel,pins =
	<AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE
	AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE
	AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE
	AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE
	AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE
	AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE
	AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE
	AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_nandrdy: ebi-nandrdy-0 {
	atmel,pins =
	<AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 {
	atmel,pins =
	<AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_nwait: ebi-nwait-0 {
	atmel,pins =
	<AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 {
	atmel,pins =
	<AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};

	pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
	atmel,pins =
	<AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};
	};

	i2c0 {
	pinctrl_i2c0: i2c0-0 {
	atmel,pins =
	<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
	AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};
	+
	+ pinctrl_i2c0_gpio: i2c0-gpio {
	+ atmel,pins =
	+ <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
	+ AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
	+ };
	};

	i2c1 {
	pinctrl_i2c1: i2c1-0 {
	atmel,pins =
	<AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */
	AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
	};
	+
	+ pinctrl_i2c1_gpio: i2c1-gpio {
	+ atmel,pins =
	+ <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
	+ AT91_PIOE 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
	+ };
	};

	i2c2 {
	pinctrl_i2c2: i2c2-0 {
	atmel,pins =
	<AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
	AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
	};
	+
	+ pinctrl_i2c2_gpio: i2c2-gpio {
	+ atmel,pins =
	+ <AT91_PIOB 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
	+ AT91_PIOB 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
	+ };
	};

	isi {
	pinctrl_isi_data_0_7: isi-0-data-0-7 {
	atmel,pins =
	<AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */
	AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */
	AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */
	AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */
	AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */
	AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */
	AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */
	AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */
	AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */
	AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */
	AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
	};
	pinctrl_isi_data_8_9: isi-0-data-8-9 {
	atmel,pins =
	<AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
	AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
	};
	pinctrl_isi_data_10_11: isi-0-data-10-11 {
	atmel,pins =
	<AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
	AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
	};
	};

	lcd {
	pinctrl_lcd_base: lcd-base-0 {
	atmel,pins =
	<AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
	AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
	AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
	AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
	};
	pinctrl_lcd_pwm: lcd-pwm-0 {
	atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
	};
	pinctrl_lcd_rgb444: lcd-rgb-0 {
	atmel,pins =
	<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
	AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
	AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
	AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
	AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
	AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
	AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
	AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
	AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
	AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
	AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
	AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
	};
	pinctrl_lcd_rgb565: lcd-rgb-1 {
	atmel,pins =
	<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
	AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
	AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
	AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
	AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
	AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
	AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
	AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
	AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
	AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
	AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
	AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
	AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
	AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
	AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
	AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
	};
	pinctrl_lcd_rgb666: lcd-rgb-2 {
	atmel,pins =
	<AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
	AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
	AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
	AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
	AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
	AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
	AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
	AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
	AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
	AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
	AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
	AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
	AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
	AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
	AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
	AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
	AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
	AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
	};
	pinctrl_lcd_rgb777: lcd-rgb-3 {
	atmel,pins =
	/* LCDDAT0 conflicts with TMS */
	<AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
	AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
	AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
	AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
	AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
	AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
	AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
	/* LCDDAT8 conflicts with TCK */
	AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
	AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
	AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
	AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
	AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
	AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
	AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
	/* LCDDAT16 conflicts with NTRST */
	AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
	AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
	AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
	AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
	AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
	AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
	AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
	};
	pinctrl_lcd_rgb888: lcd-rgb-4 {
	atmel,pins =
	<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
	AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
	AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
	AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
	AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
	AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
	AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
	AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
	AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
	AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
	AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
	AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
	AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
	AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
	AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
	AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
	AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
	AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
	AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
	AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
	AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
	AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
	AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
	AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
	};
	};

	macb0 {
	pinctrl_macb0_rmii: macb0_rmii-0 {
	atmel,pins =
	<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
	AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
	AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
	AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
	AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
	AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
	AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
	AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
	AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
	AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
	>;
	};
	};

	macb1 {
	pinctrl_macb1_rmii: macb1_rmii-0 {
	atmel,pins =
	<AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX0 */
	AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX1 */
	AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX0 */
	AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX1 */
	AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXDV */
	AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXER */
	AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXEN */
	AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXCK */
	AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDC */
	AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDIO */
	>;
	};
	};

	mmc0 {
	pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
	atmel,pins =
	<AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
	AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDA, conflict with NAND_D0 */
	AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA0, conflict with NAND_D1 */
	>;
	};
	pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
	atmel,pins =
	<AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA1, conflict with NAND_D2 */
	AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA2, conflict with NAND_D3 */
	AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA3, conflict with NAND_D4 */
	>;
	};
	pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
	atmel,pins =
	<AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA4, conflict with NAND_D5 */
	AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA5, conflict with NAND_D6 */
	AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA6, conflict with NAND_D7 */
	AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA7, conflict with NAND_OE */
	>;
	};
	};

	mmc1 {
	pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
	atmel,pins =
	<AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
	AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
	AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
	>;
	};
	pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
	atmel,pins =
	<AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
	AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
	AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
	>;
	};
	};

	nand0 {
	pinctrl_nand: nand-0 {
	atmel,pins =
	<AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
	AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */

	AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
	AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */

	AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
	AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
	AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
	AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
	AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
	AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
	AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
	AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
	AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
	AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
	};
	};

	spi0 {
	pinctrl_spi0: spi0-0 {
	atmel,pins =
	<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
	AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
	AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
	>;
	};
	};

	ssc0 {
	pinctrl_ssc0_tx: ssc0_tx {
	atmel,pins =
	<AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */
	AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */
	AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
	};

	pinctrl_ssc0_rx: ssc0_rx {
	atmel,pins =
	<AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */
	AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */
	AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
	};
	};

	ssc1 {
	pinctrl_ssc1_tx: ssc1_tx {
	atmel,pins =
	<AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */
	AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */
	AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
	};

	pinctrl_ssc1_rx: ssc1_rx {
	atmel,pins =
	<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */
	AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */
	AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
	};
	};

	spi1 {
	pinctrl_spi1: spi1-0 {
	atmel,pins =
	<AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MISO */
	AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MOSI */
	AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_SPCK */
	>;
	};
	};

	spi2 {
	pinctrl_spi2: spi2-0 {
	atmel,pins =
	<AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MISO conflicts with RTS0 */
	AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MOSI conflicts with TXD0 */
	AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_SPCK conflicts with RTS1 */
	>;
	};
	};

	uart0 {
	pinctrl_uart0: uart0-0 {
	atmel,pins =
	<AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
	AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
	>;
	};
	};

	uart1 {
	pinctrl_uart1: uart1-0 {
	atmel,pins =
	<AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* RXD */
	AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE /* TXD */
	>;
	};
	};

	usart0 {
	pinctrl_usart0: usart0-0 {
	atmel,pins =
	<AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */
	AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */
	>;
	};
	pinctrl_usart0_rts: usart0_rts-0 {
	atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};
	pinctrl_usart0_cts: usart0_cts-0 {
	atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};
	};

	usart1 {
	pinctrl_usart1: usart1-0 {
	atmel,pins =
	<AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */
	AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */
	>;
	};
	pinctrl_usart1_rts: usart1_rts-0 {
	atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};
	pinctrl_usart1_cts: usart1_cts-0 {
	atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	};
	};

	usart2 {
	pinctrl_usart2: usart2-0 {
	atmel,pins =
	<AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD - conflicts with G0_CRS, ISI_HSYNC */
	AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD - conflicts with G0_COL, PCK2 */
	>;
	};
	pinctrl_usart2_rts: usart2_rts-0 {
	atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
	};
	pinctrl_usart2_cts: usart2_cts-0 {
	atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
	};
	};

	usart3 {
	pinctrl_usart3: usart3-0 {
	atmel,pins =
	<AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
	AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
	>;
	};
	};

	usart4 {
	pinctrl_usart4: usart4-0 {
	atmel,pins =
	<AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
	AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
	>;
	};
	pinctrl_usart4_rts: usart4_rts-0 {
	atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
	};
	pinctrl_usart4_cts: usart4_cts-0 {
	atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
	};
	};
	};

	aic: interrupt-controller@fc06e000 {
	#interrupt-cells = <3>;
	compatible = "atmel,sama5d4-aic";
	interrupt-controller;
	reg = <0xfc06e000 0x200>;
	atmel,external-irqs = <56>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/sh73a0-kzm9g.dts b/sys/gnu/dts/arm/sh73a0-kzm9g.dts
	index 1916f31a30ff..5a8d92a061df 100644
	--- a/sys/gnu/dts/arm/sh73a0-kzm9g.dts
	+++ b/sys/gnu/dts/arm/sh73a0-kzm9g.dts
	@@ -1,406 +1,403 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the KZM-A9-GT board
	*
	* Copyright (C) 2012 Horms Solutions Ltd.
	*
	* Based on sh73a0-kzm9g.dts
	* Copyright (C) 2012 Renesas Solutions Corp.
	*/

	/dts-v1/;
	#include "sh73a0.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/irq.h>

	/ {
	model = "KZM-A9-GT";
	compatible = "renesas,kzm9g", "renesas,sh73a0";

	aliases {
	serial0 = &scifa4;
	};

	cpus {
	cpu@0 {
	cpu0-supply = <&vdd_dvfs>;
	- operating-points = <
	- /* kHz uV */
	- 1196000 1315000
	- 598000 1175000
	- 398667 1065000
	- >;
	+ operating-points = <1196000 1315000>, /* kHz uV */
	+ < 598000 1175000>,
	+ < 398667 1065000>;
	voltage-tolerance = <1>; /* 1% */
	};
	};

	chosen {
	bootargs = "root=/dev/nfs ip=on ignore_loglevel rw";
	stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
	device_type = "memory";
	reg = <0x40000000 0x20000000>;
	};

	reg_1p8v: regulator-1p8v {
	compatible = "regulator-fixed";
	regulator-name = "fixed-1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	reg_3p3v: regulator-3p3v {
	compatible = "regulator-fixed";
	regulator-name = "fixed-3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vmmc_sdhi0: regulator-vmmc-sdhi0 {
	compatible = "regulator-fixed";
	regulator-name = "SDHI0 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&pfc 15 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vmmc_sdhi2: regulator-vmmc-sdhi2 {
	compatible = "regulator-fixed";
	regulator-name = "SDHI2 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&pfc 14 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	leds {
	compatible = "gpio-leds";
	led1 {
	gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
	label = "LED1";
	};
	led2 {
	gpios = <&pfc 21 GPIO_ACTIVE_LOW>;
	label = "LED2";
	};
	led3 {
	gpios = <&pfc 22 GPIO_ACTIVE_LOW>;
	label = "LED3";
	};
	led4 {
	gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
	label = "LED4";
	};
	};

	keyboard {
	compatible = "gpio-keys";

	back-key {
	gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_BACK>;
	label = "SW3";
	};

	right-key {
	gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_RIGHT>;
	label = "SW2-R";
	};

	left-key {
	gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_LEFT>;
	label = "SW2-L";
	};

	enter-key {
	gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_ENTER>;
	label = "SW2-P";
	};

	up-key {
	gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_UP>;
	label = "SW2-U";
	};

	down-key {
	gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_DOWN>;
	label = "SW2-D";
	};

	home-key {
	gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_HOME>;
	label = "SW1";
	wakeup-source;
	};

	wakeup-key {
	gpios = <&pfc 159 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_WAKEUP>;
	label = "NMI";
	wakeup-source;
	};
	};

	sound {
	compatible = "simple-audio-card";
	simple-audio-card,format = "left_j";
	simple-audio-card,cpu {
	sound-dai = <&sh_fsi2 0>;
	};
	simple-audio-card,codec {
	sound-dai = <&ak4648>;
	bitclock-master;
	frame-master;
	system-clock-frequency = <11289600>;
	};
	};
	};

	&bsc {
	ethernet@10000000 {
	compatible = "smsc,lan9220", "smsc,lan9115";
	reg = <0x10000000 0x100>;
	phy-mode = "mii";
	interrupt-parent = <&irqpin0>;
	interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
	reg-io-width = <4>;
	smsc,irq-push-pull;
	smsc,save-mac-address;
	vddvario-supply = <&reg_1p8v>;
	vdd33a-supply = <&reg_3p3v>;
	};
	};

	&cmt1 {
	status = "okay";
	};

	&extal2_clk {
	clock-frequency = <48000000>;
	};

	&i2c0 {
	status = "okay";

	compass@c {
	compatible = "asahi-kasei,ak8975";
	reg = <0x0c>;
	interrupt-parent = <&irqpin3>;
	interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
	};

	ak4648: codec@12 {
	compatible = "asahi-kasei,ak4648";
	reg = <0x12>;
	#sound-dai-cells = <0>;
	};

	accelerometer@1d {
	compatible = "adi,adxl345";
	reg = <0x1d>;
	interrupt-parent = <&irqpin3>;
	interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
	<3 IRQ_TYPE_LEVEL_HIGH>;
	};

	rtc@32 {
	compatible = "ricoh,r2025sd";
	reg = <0x32>;
	};

	as3711@40 {
	compatible = "ams,as3711";
	reg = <0x40>;

	regulators {
	vdd_dvfs: sd1 {
	regulator-name = "1.315V CPU";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	};
	sd2 {
	regulator-name = "1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};
	sd4 {
	regulator-name = "1.215V";
	regulator-min-microvolt = <1215000>;
	regulator-max-microvolt = <1235000>;
	regulator-always-on;
	regulator-boot-on;
	};
	ldo2 {
	regulator-name = "2.8V CPU";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-always-on;
	regulator-boot-on;
	};
	ldo3 {
	regulator-name = "3.0V CPU";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;
	regulator-boot-on;
	};
	ldo4 {
	regulator-name = "2.8V";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-always-on;
	regulator-boot-on;
	};
	ldo5 {
	regulator-name = "2.8V #2";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-always-on;
	regulator-boot-on;
	};
	ldo7 {
	regulator-name = "1.15V CPU";
	regulator-min-microvolt = <1150000>;
	regulator-max-microvolt = <1150000>;
	regulator-always-on;
	regulator-boot-on;
	};
	ldo8 {
	regulator-name = "1.15V CPU #2";
	regulator-min-microvolt = <1150000>;
	regulator-max-microvolt = <1150000>;
	regulator-always-on;
	regulator-boot-on;
	};
	};
	};
	};

	&i2c1 {
	status = "okay";

	touchscreen@55 {
	compatible = "sitronix,st1232";
	reg = <0x55>;
	interrupt-parent = <&irqpin1>;
	interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
	};
	};

	&i2c3 {
	pinctrl-0 = <&i2c3_pins>;
	pinctrl-names = "default";
	status = "okay";

	pcf8575: gpio@20 {
	compatible = "nxp,pcf8575";
	reg = <0x20>;
	interrupt-parent = <&irqpin2>;
	interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	&mmcif {
	pinctrl-0 = <&mmcif_pins>;
	pinctrl-names = "default";

	bus-width = <8>;
	vmmc-supply = <&reg_1p8v>;
	status = "okay";
	};

	&pfc {
	i2c3_pins: i2c3 {
	groups = "i2c3_1";
	function = "i2c3";
	};

	mmcif_pins: mmc {
	mux {
	groups = "mmc0_data8_0", "mmc0_ctrl_0";
	function = "mmc0";
	};
	cfg {
	groups = "mmc0_data8_0";
	pins = "PORT279";
	bias-pull-up;
	};
	};

	scifa4_pins: scifa4 {
	groups = "scifa4_data", "scifa4_ctrl";
	function = "scifa4";
	};

	sdhi0_pins: sd0 {
	groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
	function = "sdhi0";
	};

	sdhi2_pins: sd2 {
	groups = "sdhi2_data4", "sdhi2_ctrl";
	function = "sdhi2";
	};

	fsia_pins: sounda {
	groups = "fsia_mclk_in", "fsia_sclk_in",
	"fsia_data_in", "fsia_data_out";
	function = "fsia";
	};
	};

	&scifa4 {
	pinctrl-0 = <&scifa4_pins>;
	pinctrl-names = "default";

	uart-has-rtscts;
	status = "okay";
	};

	&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&vmmc_sdhi0>;
	bus-width = <4>;
	status = "okay";
	};

	&sdhi2 {
	pinctrl-0 = <&sdhi2_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&vmmc_sdhi2>;
	bus-width = <4>;
	broken-cd;
	status = "okay";
	};

	&sh_fsi2 {
	pinctrl-0 = <&fsia_pins>;
	pinctrl-names = "default";

	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/socfpga_arria10.dtsi b/sys/gnu/dts/arm/socfpga_arria10.dtsi
	index 2a86e72d9791..3b8571b8b412 100644
	--- a/sys/gnu/dts/arm/socfpga_arria10.dtsi
	+++ b/sys/gnu/dts/arm/socfpga_arria10.dtsi
	@@ -1,901 +1,901 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Copyright Altera Corporation (C) 2014. All rights reserved.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/reset/altr,rst-mgr-a10.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "altr,socfpga-a10-smp";

	cpu@0 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <0>;
	next-level-cache = <&L2>;
	};
	cpu@1 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <1>;
	next-level-cache = <&L2>;
	};
	};

	intc: intc@ffffd000 {
	compatible = "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0xffffd000 0x1000>,
	<0xffffc100 0x100>;
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	device_type = "soc";
	interrupt-parent = <&intc>;
	ranges;

	amba {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	pdma: pdma@ffda1000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0xffda1000 0x1000>;
	interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
	<0 84 IRQ_TYPE_LEVEL_HIGH>,
	<0 85 IRQ_TYPE_LEVEL_HIGH>,
	<0 86 IRQ_TYPE_LEVEL_HIGH>,
	<0 87 IRQ_TYPE_LEVEL_HIGH>,
	<0 88 IRQ_TYPE_LEVEL_HIGH>,
	<0 89 IRQ_TYPE_LEVEL_HIGH>,
	<0 90 IRQ_TYPE_LEVEL_HIGH>,
	<0 91 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	#dma-channels = <8>;
	#dma-requests = <32>;
	clocks = <&l4_main_clk>;
	clock-names = "apb_pclk";
	resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
	reset-names = "dma", "dma-ocp";
	};
	};

	base_fpga_region {
	#address-cells = <0x1>;
	#size-cells = <0x1>;

	compatible = "fpga-region";
	fpga-mgr = <&fpga_mgr>;
	};

	clkmgr@ffd04000 {
	compatible = "altr,clk-mgr";
	reg = <0xffd04000 0x1000>;

	clocks {
	#address-cells = <1>;
	#size-cells = <0>;

	cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	};

	cb_intosc_ls_clk: cb_intosc_ls_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	};

	f2s_free_clk: f2s_free_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	};

	osc1: osc1 {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	};

	main_pll: main_pll@40 {
	#address-cells = <1>;
	#size-cells = <0>;
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-pll-clock";
	clocks = <&osc1>, <&cb_intosc_ls_clk>,
	<&f2s_free_clk>;
	reg = <0x40>;

	main_mpu_base_clk: main_mpu_base_clk {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&main_pll>;
	div-reg = <0x140 0 11>;
	};

	main_noc_base_clk: main_noc_base_clk {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&main_pll>;
	div-reg = <0x144 0 11>;
	};

	main_emaca_clk: main_emaca_clk@68 {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&main_pll>;
	reg = <0x68>;
	};

	main_emacb_clk: main_emacb_clk@6c {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&main_pll>;
	reg = <0x6C>;
	};

	main_emac_ptp_clk: main_emac_ptp_clk@70 {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&main_pll>;
	reg = <0x70>;
	};

	main_gpio_db_clk: main_gpio_db_clk@74 {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&main_pll>;
	reg = <0x74>;
	};

	main_sdmmc_clk: main_sdmmc_clk@78 {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk"
	;
	clocks = <&main_pll>;
	reg = <0x78>;
	};

	main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&main_pll>;
	reg = <0x7C>;
	};

	main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&main_pll>;
	reg = <0x80>;
	};

	main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&main_pll>;
	reg = <0x84>;
	};

	main_periph_ref_clk: main_periph_ref_clk@9c {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&main_pll>;
	reg = <0x9C>;
	};
	};

	periph_pll: periph_pll@c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-pll-clock";
	clocks = <&osc1>, <&cb_intosc_ls_clk>,
	<&f2s_free_clk>, <&main_periph_ref_clk>;
	reg = <0xC0>;

	peri_mpu_base_clk: peri_mpu_base_clk {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&periph_pll>;
	div-reg = <0x140 16 11>;
	};

	peri_noc_base_clk: peri_noc_base_clk {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&periph_pll>;
	div-reg = <0x144 16 11>;
	};

	peri_emaca_clk: peri_emaca_clk@e8 {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&periph_pll>;
	reg = <0xE8>;
	};

	peri_emacb_clk: peri_emacb_clk@ec {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&periph_pll>;
	reg = <0xEC>;
	};

	peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&periph_pll>;
	reg = <0xF0>;
	};

	peri_gpio_db_clk: peri_gpio_db_clk@f4 {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&periph_pll>;
	reg = <0xF4>;
	};

	peri_sdmmc_clk: peri_sdmmc_clk@f8 {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&periph_pll>;
	reg = <0xF8>;
	};

	peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&periph_pll>;
	reg = <0xFC>;
	};

	peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&periph_pll>;
	reg = <0x100>;
	};

	peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&periph_pll>;
	reg = <0x104>;
	};
	};

	mpu_free_clk: mpu_free_clk@60 {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
	<&osc1>, <&cb_intosc_hs_div2_clk>,
	<&f2s_free_clk>;
	reg = <0x60>;
	};

	noc_free_clk: noc_free_clk@64 {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
	<&osc1>, <&cb_intosc_hs_div2_clk>,
	<&f2s_free_clk>;
	reg = <0x64>;
	};

	s2f_user1_free_clk: s2f_user1_free_clk@104 {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
	<&osc1>, <&cb_intosc_hs_div2_clk>,
	<&f2s_free_clk>;
	reg = <0x104>;
	};

	sdmmc_free_clk: sdmmc_free_clk@f8 {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
	<&osc1>, <&cb_intosc_hs_div2_clk>,
	<&f2s_free_clk>;
	fixed-divider = <4>;
	reg = <0xF8>;
	};

	l4_sys_free_clk: l4_sys_free_clk {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-perip-clk";
	clocks = <&noc_free_clk>;
	fixed-divider = <4>;
	};

	l4_main_clk: l4_main_clk {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-gate-clk";
	clocks = <&noc_free_clk>;
	div-reg = <0xA8 0 2>;
	clk-gate = <0x48 1>;
	};

	l4_mp_clk: l4_mp_clk {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-gate-clk";
	clocks = <&noc_free_clk>;
	div-reg = <0xA8 8 2>;
	clk-gate = <0x48 2>;
	};

	l4_sp_clk: l4_sp_clk {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-gate-clk";
	clocks = <&noc_free_clk>;
	div-reg = <0xA8 16 2>;
	clk-gate = <0x48 3>;
	};

	mpu_periph_clk: mpu_periph_clk {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-gate-clk";
	clocks = <&mpu_free_clk>;
	fixed-divider = <4>;
	clk-gate = <0x48 0>;
	};

	sdmmc_clk: sdmmc_clk {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-gate-clk";
	clocks = <&sdmmc_free_clk>;
	clk-gate = <0xC8 5>;
	clk-phase = <0 135>;
	};

	qspi_clk: qspi_clk {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-gate-clk";
	clocks = <&l4_main_clk>;
	clk-gate = <0xC8 11>;
	};

	nand_x_clk: nand_x_clk {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-gate-clk";
	clocks = <&l4_mp_clk>;
	clk-gate = <0xC8 10>;
	};

	nand_ecc_clk: nand_ecc_clk {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-gate-clk";
	clocks = <&nand_x_clk>;
	clk-gate = <0xC8 10>;
	};

	nand_clk: nand_clk {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-gate-clk";
	clocks = <&nand_x_clk>;
	fixed-divider = <4>;
	clk-gate = <0xC8 10>;
	};

	spi_m_clk: spi_m_clk {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-gate-clk";
	clocks = <&l4_main_clk>;
	clk-gate = <0xC8 9>;
	};

	usb_clk: usb_clk {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-gate-clk";
	clocks = <&l4_mp_clk>;
	clk-gate = <0xC8 8>;
	};

	s2f_usr1_clk: s2f_usr1_clk {
	#clock-cells = <0>;
	compatible = "altr,socfpga-a10-gate-clk";
	clocks = <&peri_s2f_usr1_clk>;
	clk-gate = <0xC8 6>;
	};
	};
	};

	socfpga_axi_setup: stmmac-axi-config {
	snps,wr_osr_lmt = <0xf>;
	snps,rd_osr_lmt = <0xf>;
	snps,blen = <0 0 0 0 16 0 0>;
	};

	gmac0: ethernet@ff800000 {
	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
	altr,sysmgr-syscon = <&sysmgr 0x44 0>;
	reg = <0xff800000 0x2000>;
	interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	/* Filled in by bootloader */
	mac-address = [00 00 00 00 00 00];
	snps,multicast-filter-bins = <256>;
	snps,perfect-filter-entries = <128>;
	tx-fifo-depth = <4096>;
	rx-fifo-depth = <16384>;
	- clocks = <&l4_mp_clk>;
	- clock-names = "stmmaceth";
	+ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
	+ clock-names = "stmmaceth", "ptp_ref";
	resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
	reset-names = "stmmaceth", "stmmaceth-ocp";
	snps,axi-config = <&socfpga_axi_setup>;
	status = "disabled";
	};

	gmac1: ethernet@ff802000 {
	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
	altr,sysmgr-syscon = <&sysmgr 0x48 8>;
	reg = <0xff802000 0x2000>;
	interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	/* Filled in by bootloader */
	mac-address = [00 00 00 00 00 00];
	snps,multicast-filter-bins = <256>;
	snps,perfect-filter-entries = <128>;
	tx-fifo-depth = <4096>;
	rx-fifo-depth = <16384>;
	- clocks = <&l4_mp_clk>;
	- clock-names = "stmmaceth";
	+ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
	+ clock-names = "stmmaceth", "ptp_ref";
	resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
	reset-names = "stmmaceth", "stmmaceth-ocp";
	snps,axi-config = <&socfpga_axi_setup>;
	status = "disabled";
	};

	gmac2: ethernet@ff804000 {
	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
	altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
	reg = <0xff804000 0x2000>;
	interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	/* Filled in by bootloader */
	mac-address = [00 00 00 00 00 00];
	snps,multicast-filter-bins = <256>;
	snps,perfect-filter-entries = <128>;
	tx-fifo-depth = <4096>;
	rx-fifo-depth = <16384>;
	- clocks = <&l4_mp_clk>;
	- clock-names = "stmmaceth";
	+ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
	+ clock-names = "stmmaceth", "ptp_ref";
	resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
	reset-names = "stmmaceth", "stmmaceth-ocp";
	snps,axi-config = <&socfpga_axi_setup>;
	status = "disabled";
	};

	gpio0: gpio@ffc02900 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,dw-apb-gpio";
	reg = <0xffc02900 0x100>;
	resets = <&rst GPIO0_RESET>;
	status = "disabled";

	porta: gpio-controller@0 {
	compatible = "snps,dw-apb-gpio-port";
	gpio-controller;
	#gpio-cells = <2>;
	snps,nr-gpios = <29>;
	reg = <0>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	gpio1: gpio@ffc02a00 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,dw-apb-gpio";
	reg = <0xffc02a00 0x100>;
	resets = <&rst GPIO1_RESET>;
	status = "disabled";

	portb: gpio-controller@0 {
	compatible = "snps,dw-apb-gpio-port";
	gpio-controller;
	#gpio-cells = <2>;
	snps,nr-gpios = <29>;
	reg = <0>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	gpio2: gpio@ffc02b00 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,dw-apb-gpio";
	reg = <0xffc02b00 0x100>;
	resets = <&rst GPIO2_RESET>;
	status = "disabled";

	portc: gpio-controller@0 {
	compatible = "snps,dw-apb-gpio-port";
	gpio-controller;
	#gpio-cells = <2>;
	snps,nr-gpios = <27>;
	reg = <0>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	fpga_mgr: fpga-mgr@ffd03000 {
	compatible = "altr,socfpga-a10-fpga-mgr";
	reg = <0xffd03000 0x100
	0xffcfe400 0x20>;
	clocks = <&l4_mp_clk>;
	resets = <&rst FPGAMGR_RESET>;
	reset-names = "fpgamgr";
	};

	i2c0: i2c@ffc02200 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,designware-i2c";
	reg = <0xffc02200 0x100>;
	interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&l4_sp_clk>;
	resets = <&rst I2C0_RESET>;
	status = "disabled";
	};

	i2c1: i2c@ffc02300 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,designware-i2c";
	reg = <0xffc02300 0x100>;
	interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&l4_sp_clk>;
	resets = <&rst I2C1_RESET>;
	status = "disabled";
	};

	i2c2: i2c@ffc02400 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,designware-i2c";
	reg = <0xffc02400 0x100>;
	interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&l4_sp_clk>;
	resets = <&rst I2C2_RESET>;
	status = "disabled";
	};

	i2c3: i2c@ffc02500 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,designware-i2c";
	reg = <0xffc02500 0x100>;
	interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&l4_sp_clk>;
	resets = <&rst I2C3_RESET>;
	status = "disabled";
	};

	i2c4: i2c@ffc02600 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,designware-i2c";
	reg = <0xffc02600 0x100>;
	interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&l4_sp_clk>;
	resets = <&rst I2C4_RESET>;
	status = "disabled";
	};

	spi0: spi@ffda4000 {
	compatible = "snps,dw-apb-ssi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xffda4000 0x100>;
	interrupts = <0 101 4>;
	num-cs = <4>;
	/32bit_access;/
	clocks = <&spi_m_clk>;
	resets = <&rst SPIM0_RESET>;
	status = "disabled";
	};

	spi1: spi@ffda5000 {
	compatible = "snps,dw-apb-ssi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xffda5000 0x100>;
	interrupts = <0 102 4>;
	num-cs = <4>;
	/32bit_access;/
	tx-dma-channel = <&pdma 16>;
	rx-dma-channel = <&pdma 17>;
	clocks = <&spi_m_clk>;
	resets = <&rst SPIM1_RESET>;
	status = "disabled";
	};

	sdr: sdr@ffcfb100 {
	compatible = "altr,sdr-ctl", "syscon";
	reg = <0xffcfb100 0x80>;
	};

	L2: l2-cache@fffff000 {
	compatible = "arm,pl310-cache";
	reg = <0xfffff000 0x1000>;
	interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
	cache-unified;
	cache-level = <2>;
	prefetch-data = <1>;
	prefetch-instr = <1>;
	arm,shared-override;
	};

	mmc: dwmmc0@ff808000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "altr,socfpga-dw-mshc";
	reg = <0xff808000 0x1000>;
	interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
	fifo-depth = <0x400>;
	clocks = <&l4_mp_clk>, <&sdmmc_clk>;
	clock-names = "biu", "ciu";
	resets = <&rst SDMMC_RESET>;
	status = "disabled";
	};

	nand: nand@ffb90000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "altr,socfpga-denali-nand";
	reg = <0xffb90000 0x72000>,
	<0xffb80000 0x10000>;
	reg-names = "nand_data", "denali_reg";
	interrupts = <0 99 4>;
	clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
	clock-names = "nand", "nand_x", "ecc";
	resets = <&rst NAND_RESET>;
	status = "disabled";
	};

	ocram: sram@ffe00000 {
	compatible = "mmio-sram";
	reg = <0xffe00000 0x40000>;
	};

	eccmgr: eccmgr {
	compatible = "altr,socfpga-a10-ecc-manager";
	altr,sysmgr-syscon = <&sysmgr>;
	#address-cells = <1>;
	#size-cells = <1>;
	interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	ranges;

	sdramedac {
	compatible = "altr,sdram-edac-a10";
	altr,sdr-syscon = <&sdr>;
	interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
	<49 IRQ_TYPE_LEVEL_HIGH>;
	};

	l2-ecc@ffd06010 {
	compatible = "altr,socfpga-a10-l2-ecc";
	reg = <0xffd06010 0x4>;
	interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
	<32 IRQ_TYPE_LEVEL_HIGH>;
	};

	ocram-ecc@ff8c3000 {
	compatible = "altr,socfpga-a10-ocram-ecc";
	reg = <0xff8c3000 0x400>;
	interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
	<33 IRQ_TYPE_LEVEL_HIGH>;
	};

	emac0-rx-ecc@ff8c0800 {
	compatible = "altr,socfpga-eth-mac-ecc";
	reg = <0xff8c0800 0x400>;
	altr,ecc-parent = <&gmac0>;
	interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
	<36 IRQ_TYPE_LEVEL_HIGH>;
	};

	emac0-tx-ecc@ff8c0c00 {
	compatible = "altr,socfpga-eth-mac-ecc";
	reg = <0xff8c0c00 0x400>;
	altr,ecc-parent = <&gmac0>;
	interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
	<37 IRQ_TYPE_LEVEL_HIGH>;
	};

	dma-ecc@ff8c8000 {
	compatible = "altr,socfpga-dma-ecc";
	reg = <0xff8c8000 0x400>;
	altr,ecc-parent = <&pdma>;
	interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
	<42 IRQ_TYPE_LEVEL_HIGH>;
	};

	usb0-ecc@ff8c8800 {
	compatible = "altr,socfpga-usb-ecc";
	reg = <0xff8c8800 0x400>;
	altr,ecc-parent = <&usb0>;
	interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
	<34 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	qspi: spi@ff809000 {
	compatible = "cdns,qspi-nor";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xff809000 0x100>,
	<0xffa00000 0x100000>;
	interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
	cdns,fifo-depth = <128>;
	cdns,fifo-width = <4>;
	cdns,trigger-address = <0x00000000>;
	clocks = <&qspi_clk>;
	resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
	reset-names = "qspi", "qspi-ocp";
	status = "disabled";
	};

	rst: rstmgr@ffd05000 {
	#reset-cells = <1>;
	compatible = "altr,rst-mgr";
	reg = <0xffd05000 0x100>;
	altr,modrst-offset = <0x20>;
	};

	scu: snoop-control-unit@ffffc000 {
	compatible = "arm,cortex-a9-scu";
	reg = <0xffffc000 0x100>;
	};

	sysmgr: sysmgr@ffd06000 {
	compatible = "altr,sys-mgr", "syscon";
	reg = <0xffd06000 0x300>;
	cpu1-start-addr = <0xffd06230>;
	};

	/* Local timer */
	timer@ffffc600 {
	compatible = "arm,cortex-a9-twd-timer";
	reg = <0xffffc600 0x100>;
	interrupts = <1 13 0xf01>;
	clocks = <&mpu_periph_clk>;
	};

	timer0: timer0@ffc02700 {
	compatible = "snps,dw-apb-timer";
	interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xffc02700 0x100>;
	clocks = <&l4_sp_clk>;
	clock-names = "timer";
	resets = <&rst SPTIMER0_RESET>;
	reset-names = "timer";
	};

	timer1: timer1@ffc02800 {
	compatible = "snps,dw-apb-timer";
	interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xffc02800 0x100>;
	clocks = <&l4_sp_clk>;
	clock-names = "timer";
	resets = <&rst SPTIMER1_RESET>;
	reset-names = "timer";
	};

	timer2: timer2@ffd00000 {
	compatible = "snps,dw-apb-timer";
	interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xffd00000 0x100>;
	clocks = <&l4_sys_free_clk>;
	clock-names = "timer";
	resets = <&rst L4SYSTIMER0_RESET>;
	reset-names = "timer";
	};

	timer3: timer3@ffd00100 {
	compatible = "snps,dw-apb-timer";
	interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xffd01000 0x100>;
	clocks = <&l4_sys_free_clk>;
	clock-names = "timer";
	resets = <&rst L4SYSTIMER1_RESET>;
	reset-names = "timer";
	};

	uart0: serial0@ffc02000 {
	compatible = "snps,dw-apb-uart";
	reg = <0xffc02000 0x100>;
	interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&l4_sp_clk>;
	resets = <&rst UART0_RESET>;
	status = "disabled";
	};

	uart1: serial1@ffc02100 {
	compatible = "snps,dw-apb-uart";
	reg = <0xffc02100 0x100>;
	interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&l4_sp_clk>;
	resets = <&rst UART1_RESET>;
	status = "disabled";
	};

	usbphy0: usbphy {
	#phy-cells = <0>;
	compatible = "usb-nop-xceiv";
	status = "okay";
	};

	usb0: usb@ffb00000 {
	compatible = "snps,dwc2";
	reg = <0xffb00000 0xffff>;
	interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&usb_clk>;
	clock-names = "otg";
	resets = <&rst USB0_RESET>;
	reset-names = "dwc2";
	phys = <&usbphy0>;
	phy-names = "usb2-phy";
	status = "disabled";
	};

	usb1: usb@ffb40000 {
	compatible = "snps,dwc2";
	reg = <0xffb40000 0xffff>;
	interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&usb_clk>;
	clock-names = "otg";
	resets = <&rst USB1_RESET>;
	reset-names = "dwc2";
	phys = <&usbphy0>;
	phy-names = "usb2-phy";
	status = "disabled";
	};

	watchdog0: watchdog@ffd00200 {
	compatible = "snps,dw-wdt";
	reg = <0xffd00200 0x100>;
	interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&l4_sys_free_clk>;
	resets = <&rst L4WD0_RESET>;
	status = "disabled";
	};

	watchdog1: watchdog@ffd00300 {
	compatible = "snps,dw-wdt";
	reg = <0xffd00300 0x100>;
	interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&l4_sys_free_clk>;
	resets = <&rst L4WD1_RESET>;
	status = "disabled";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/socfpga_arria10_socdk_nand.dts b/sys/gnu/dts/arm/socfpga_arria10_socdk_nand.dts
	index 9bd9e04c7361..9aa897b79544 100644
	--- a/sys/gnu/dts/arm/socfpga_arria10_socdk_nand.dts
	+++ b/sys/gnu/dts/arm/socfpga_arria10_socdk_nand.dts
	@@ -1,26 +1,26 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Copyright (C) 2015 Altera Corporation. All rights reserved.
	*/

	/dts-v1/;
	#include "socfpga_arria10_socdk.dtsi"

	&nand {
	status = "okay";

	nand@0 {
	reg = <0>;
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
	label = "Boot and fpga data";
	- reg = <0x0 0x1C00000>;
	+ reg = <0x0 0x02000000>;
	};
	partition@1c00000 {
	label = "Root Filesystem - JFFS2";
	- reg = <0x1C00000 0x6400000>;
	+ reg = <0x02000000 0x06000000>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/ste-ab8500.dtsi b/sys/gnu/dts/arm/ste-ab8500.dtsi
	index 14d4d8617d75..3cd6ee6d50e0 100644
	--- a/sys/gnu/dts/arm/ste-ab8500.dtsi
	+++ b/sys/gnu/dts/arm/ste-ab8500.dtsi
	@@ -1,328 +1,328 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	/*
	* Copyright 2012 Linaro Ltd
	*/

	#include <dt-bindings/clock/ste-ab8500.h>

	/ {
	/* Essential housekeeping hardware monitors */
	iio-hwmon {
	compatible = "iio-hwmon";
	io-channels = <&gpadc 0x02>, /* Battery temperature */
	<&gpadc 0x03>, /* Main charger voltage */
	<&gpadc 0x08>, /* Main battery voltage */
	<&gpadc 0x09>, /* VBUS */
	<&gpadc 0x0a>, /* Main charger current */
	<&gpadc 0x0b>, /* USB charger current */
	<&gpadc 0x0c>, /* Backup battery voltage */
	<&gpadc 0x0d>, /* Die temperature */
	<&gpadc 0x12>; /* Crystal temperature */
	};

	soc {
	prcmu@80157000 {
	ab8500 {
	compatible = "stericsson,ab8500";
	interrupt-parent = <&intc>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;

	ab8500_clock: clock-controller {
	compatible = "stericsson,ab8500-clk";
	#clock-cells = <1>;
	};

	ab8500_gpio: ab8500-gpio {
	compatible = "stericsson,ab8500-gpio";
	gpio-controller;
	#gpio-cells = <2>;
	};

	ab8500-rtc {
	compatible = "stericsson,ab8500-rtc";
	interrupts = <17 IRQ_TYPE_LEVEL_HIGH
	18 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "60S", "ALARM";
	};

	gpadc: ab8500-gpadc {
	compatible = "stericsson,ab8500-gpadc";
	interrupts = <32 IRQ_TYPE_LEVEL_HIGH
	39 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "HW_CONV_END", "SW_CONV_END";
	vddadc-supply = <&ab8500_ldo_tvout_reg>;
	#address-cells = <1>;
	#size-cells = <0>;
	#io-channel-cells = <1>;

	/* GPADC channels */
	bat_ctrl: channel@01 {
	reg = <0x01>;
	};
	btemp_ball: channel@02 {
	reg = <0x02>;
	};
	main_charger_v: channel@03 {
	reg = <0x03>;
	};
	acc_detect1: channel@04 {
	reg = <0x04>;
	};
	acc_detect2: channel@05 {
	reg = <0x05>;
	};
	adc_aux1: channel@06 {
	reg = <0x06>;
	};
	adc_aux2: channel@07 {
	reg = <0x07>;
	};
	main_batt_v: channel@08 {
	reg = <0x08>;
	};
	vbus_v: channel@09 {
	reg = <0x09>;
	};
	main_charger_c: channel@0a {
	reg = <0x0a>;
	};
	usb_charger_c: channel@0b {
	reg = <0x0b>;
	};
	bk_bat_v: channel@0c {
	reg = <0x0c>;
	};
	die_temp: channel@0d {
	reg = <0x0d>;
	};
	usb_id: channel@0e {
	reg = <0x0e>;
	};
	xtal_temp: channel@12 {
	reg = <0x12>;
	};
	vbat_true_meas: channel@13 {
	reg = <0x13>;
	};
	bat_ctrl_and_ibat: channel@1c {
	reg = <0x1c>;
	};
	vbat_meas_and_ibat: channel@1d {
	reg = <0x1d>;
	};
	vbat_true_meas_and_ibat: channel@1e {
	reg = <0x1e>;
	};
	bat_temp_and_ibat: channel@1f {
	reg = <0x1f>;
	};
	};

	ab8500_temp {
	compatible = "stericsson,abx500-temp";
	io-channels = <&gpadc 0x06>,
	<&gpadc 0x07>;
	io-channel-name = "aux1", "aux2";
	};

	ab8500_battery: ab8500_battery {
	stericsson,battery-type = "LIPO";
	thermistor-on-batctrl;
	};

	ab8500_fg {
	compatible = "stericsson,ab8500-fg";
	battery = <&ab8500_battery>;
	io-channels = <&gpadc 0x08>;
	io-channel-name = "main_bat_v";
	};

	ab8500_btemp {
	compatible = "stericsson,ab8500-btemp";
	battery = <&ab8500_battery>;
	io-channels = <&gpadc 0x02>,
	<&gpadc 0x01>;
	io-channel-name = "btemp_ball",
	"bat_ctrl";
	};

	ab8500_charger {
	compatible = "stericsson,ab8500-charger";
	battery = <&ab8500_battery>;
	vddadc-supply = <&ab8500_ldo_tvout_reg>;
	io-channels = <&gpadc 0x03>,
	<&gpadc 0x0a>,
	<&gpadc 0x09>,
	<&gpadc 0x0b>;
	io-channel-name = "main_charger_v",
	"main_charger_c",
	"vbus_v",
	"usb_charger_c";
	};

	ab8500_chargalg {
	compatible = "stericsson,ab8500-chargalg";
	battery = <&ab8500_battery>;
	};

	ab8500_usb {
	compatible = "stericsson,ab8500-usb";
	interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
	96 IRQ_TYPE_LEVEL_HIGH
	14 IRQ_TYPE_LEVEL_HIGH
	15 IRQ_TYPE_LEVEL_HIGH
	79 IRQ_TYPE_LEVEL_HIGH
	74 IRQ_TYPE_LEVEL_HIGH
	75 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ID_WAKEUP_R",
	"ID_WAKEUP_F",
	"VBUS_DET_F",
	"VBUS_DET_R",
	"USB_LINK_STATUS",
	"USB_ADP_PROBE_PLUG",
	"USB_ADP_PROBE_UNPLUG";
	vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
	v-ape-supply = <&db8500_vape_reg>;
	musb_1v8-supply = <&db8500_vsmps2_reg>;
	clocks = <&prcmu_clk PRCMU_SYSCLK>;
	clock-names = "sysclk";
	};

	ab8500-ponkey {
	compatible = "stericsson,ab8500-poweron-key";
	interrupts = <6 IRQ_TYPE_LEVEL_HIGH
	7 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
	};

	ab8500-sysctrl {
	compatible = "stericsson,ab8500-sysctrl";
	};

	ab8500-pwm {
	compatible = "stericsson,ab8500-pwm";
	clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
	clock-names = "intclk";
	};

	ab8500-debugfs {
	compatible = "stericsson,ab8500-debug";
	};

	codec: ab8500-codec {
	compatible = "stericsson,ab8500-codec";

	V-AUD-supply = <&ab8500_ldo_audio_reg>;
	V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
	V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
	V-DMIC-supply = <&ab8500_ldo_dmic_reg>;

	clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>;
	clock-names = "audioclk";

	stericsson,earpeice-cmv = <950>; /* Units in mV. */
	};

	ext_regulators: ab8500-ext-regulators {
	compatible = "stericsson,ab8500-ext-regulator";

	ab8500_ext1_reg: ab8500_ext1 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ab8500_ext2_reg: ab8500_ext2 {
	regulator-min-microvolt = <1360000>;
	regulator-max-microvolt = <1360000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ab8500_ext3_reg: ab8500_ext3 {
	regulator-min-microvolt = <3400000>;
	regulator-max-microvolt = <3400000>;
	regulator-boot-on;
	};
	};

	ab8500-regulators {
	compatible = "stericsson,ab8500-regulator";
	vin-supply = <&ab8500_ext3_reg>;

	// supplies to the display/camera
	ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
	regulator-min-microvolt = <2500000>;
	regulator-max-microvolt = <2900000>;
	regulator-boot-on;
	/* BUG: If turned off MMC will be affected. */
	regulator-always-on;
	};

	// supplies to the on-board eMMC
	ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <3300000>;
	};

	// supply for VAUX3; SDcard slots
	ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <3300000>;
	};

	// supply for v-intcore12; VINTCORE12 LDO
	ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
	};

	// supply for tvout; gpadc; TVOUT LDO
	ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
	};

	// supply for ab8500-vaudio; VAUDIO LDO
	ab8500_ldo_audio_reg: ab8500_ldo_audio {
	};

	// supply for v-anamic1 VAMIC1 LDO
	ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
	};

	// supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
	ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
	};

	// supply for v-dmic; VDMIC LDO
	ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
	};

	// supply for U8500 CSI/DSI; VANA LDO
	ab8500_ldo_ana_reg: ab8500_ldo_ana {
	};
	};
	};
	};

	sound {
	stericsson,audio-codec = <&codec>;
	clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>;
	clock-names = "sysclk", "ulpclk", "intclk";
	};

	mcde@a0350000 {
	vana-supply = <&ab8500_ldo_ana_reg>;

	- dsi@a0351000 {
	+ dsi-controller@a0351000 {
	vana-supply = <&ab8500_ldo_ana_reg>;
	};
	- dsi@a0352000 {
	+ dsi-controller@a0352000 {
	vana-supply = <&ab8500_ldo_ana_reg>;
	};
	- dsi@a0353000 {
	+ dsi-controller@a0353000 {
	vana-supply = <&ab8500_ldo_ana_reg>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/ste-ab8505.dtsi b/sys/gnu/dts/arm/ste-ab8505.dtsi
	index c72aa250bf6f..67bc69e67b33 100644
	--- a/sys/gnu/dts/arm/ste-ab8505.dtsi
	+++ b/sys/gnu/dts/arm/ste-ab8505.dtsi
	@@ -1,275 +1,275 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	/*
	* Copyright 2012 Linaro Ltd
	*/

	#include <dt-bindings/clock/ste-ab8500.h>

	/ {
	/* Essential housekeeping hardware monitors */
	iio-hwmon {
	compatible = "iio-hwmon";
	io-channels = <&gpadc 0x02>, /* Battery temperature */
	<&gpadc 0x08>, /* Main battery voltage */
	<&gpadc 0x09>, /* VBUS */
	<&gpadc 0x0b>, /* Charger current */
	<&gpadc 0x0c>; /* Backup battery voltage */
	};

	soc {
	prcmu@80157000 {
	ab8505 {
	compatible = "stericsson,ab8505";
	interrupt-parent = <&intc>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;

	ab8500_clock: clock-controller {
	compatible = "stericsson,ab8500-clk";
	#clock-cells = <1>;
	};

	ab8505_gpio: ab8505-gpio {
	compatible = "stericsson,ab8505-gpio";
	gpio-controller;
	#gpio-cells = <2>;
	};

	ab8500-rtc {
	compatible = "stericsson,ab8500-rtc";
	interrupts = <17 IRQ_TYPE_LEVEL_HIGH
	18 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "60S", "ALARM";
	};

	gpadc: ab8500-gpadc {
	compatible = "stericsson,ab8500-gpadc";
	interrupts = <32 IRQ_TYPE_LEVEL_HIGH
	39 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "HW_CONV_END", "SW_CONV_END";
	vddadc-supply = <&ab8500_ldo_adc_reg>;
	#address-cells = <1>;
	#size-cells = <0>;
	#io-channel-cells = <1>;

	/* GPADC channels */
	bat_ctrl: channel@01 {
	reg = <0x01>;
	};
	btemp_ball: channel@02 {
	reg = <0x02>;
	};
	acc_detect1: channel@04 {
	reg = <0x04>;
	};
	acc_detect2: channel@05 {
	reg = <0x05>;
	};
	adc_aux1: channel@06 {
	reg = <0x06>;
	};
	adc_aux2: channel@07 {
	reg = <0x07>;
	};
	main_batt_v: channel@08 {
	reg = <0x08>;
	};
	vbus_v: channel@09 {
	reg = <0x09>;
	};
	charger_c: channel@0b {
	reg = <0x0b>;
	};
	bk_bat_v: channel@0c {
	reg = <0x0c>;
	};
	usb_id: channel@0e {
	reg = <0x0e>;
	};
	};

	ab8500_battery: ab8500_battery {
	status = "disabled";
	thermistor-on-batctrl;
	};

	ab8500_fg {
	status = "disabled";
	compatible = "stericsson,ab8500-fg";
	battery = <&ab8500_battery>;
	io-channels = <&gpadc 0x08>;
	io-channel-name = "main_bat_v";
	};

	ab8500_btemp {
	status = "disabled";
	compatible = "stericsson,ab8500-btemp";
	battery = <&ab8500_battery>;
	io-channels = <&gpadc 0x02>,
	<&gpadc 0x01>;
	io-channel-name = "btemp_ball",
	"bat_ctrl";
	};

	ab8500_charger {
	status = "disabled";
	compatible = "stericsson,ab8500-charger";
	battery = <&ab8500_battery>;
	vddadc-supply = <&ab8500_ldo_adc_reg>;
	io-channels = <&gpadc 0x09>,
	<&gpadc 0x0b>;
	io-channel-name = "vbus_v",
	"usb_charger_c";
	};

	ab8500_chargalg {
	status = "disabled";
	compatible = "stericsson,ab8500-chargalg";
	battery = <&ab8500_battery>;
	};

	ab8500_usb: ab8500_usb {
	compatible = "stericsson,ab8500-usb";
	interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
	96 IRQ_TYPE_LEVEL_HIGH
	14 IRQ_TYPE_LEVEL_HIGH
	15 IRQ_TYPE_LEVEL_HIGH
	79 IRQ_TYPE_LEVEL_HIGH
	74 IRQ_TYPE_LEVEL_HIGH
	75 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ID_WAKEUP_R",
	"ID_WAKEUP_F",
	"VBUS_DET_F",
	"VBUS_DET_R",
	"USB_LINK_STATUS",
	"USB_ADP_PROBE_PLUG",
	"USB_ADP_PROBE_UNPLUG";
	vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
	v-ape-supply = <&db8500_vape_reg>;
	musb_1v8-supply = <&db8500_vsmps2_reg>;
	clocks = <&prcmu_clk PRCMU_SYSCLK>;
	clock-names = "sysclk";
	};

	ab8500-ponkey {
	compatible = "stericsson,ab8500-poweron-key";
	interrupts = <6 IRQ_TYPE_LEVEL_HIGH
	7 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
	};

	ab8500-sysctrl {
	compatible = "stericsson,ab8500-sysctrl";
	};

	ab8500-pwm {
	compatible = "stericsson,ab8500-pwm";
	clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
	clock-names = "intclk";
	};

	ab8500-debugfs {
	compatible = "stericsson,ab8500-debug";
	};

	codec: ab8500-codec {
	compatible = "stericsson,ab8500-codec";

	V-AUD-supply = <&ab8500_ldo_audio_reg>;
	V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
	V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;

	clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>;
	clock-names = "audioclk";

	stericsson,earpeice-cmv = <950>; /* Units in mV. */
	};

	ab8505-regulators {
	compatible = "stericsson,ab8505-regulator";

	ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <3300000>;
	};

	ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <3300000>;
	};

	ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <3300000>;
	};

	ab8500_ldo_aux4_reg: ab8500_ldo_aux4 {
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <3300000>;
	};

	ab8500_ldo_aux5_reg: ab8500_ldo_aux5 {
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <2790000>;
	};

	ab8500_ldo_aux6_reg: ab8500_ldo_aux6 {
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <2790000>;
	};

	// supply for v-intcore12; VINTCORE12 LDO
	ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
	regulator-min-microvolt = <1250000>;
	regulator-max-microvolt = <1350000>;
	};

	// supply for gpadc; ADC LDO
	ab8500_ldo_adc_reg: ab8500_ldo_adc {
	};

	// supply for ab8500-vaudio; VAUDIO LDO
	ab8500_ldo_audio_reg: ab8500_ldo_audio {
	};

	// supply for v-anamic1 VAMIC1 LDO
	ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
	};

	// supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
	ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
	};

	// supply for v-aux8; VAUX8 LDO
	ab8500_ldo_aux8_reg: ab8500_ldo_aux8 {
	};

	// supply for U8500 CSI/DSI; VANA LDO
	ab8500_ldo_ana_reg: ab8500_ldo_ana {
	};
	};
	};
	};

	sound {
	stericsson,audio-codec = <&codec>;
	clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>;
	clock-names = "sysclk", "ulpclk", "intclk";
	};

	mcde@a0350000 {
	vana-supply = <&ab8500_ldo_ana_reg>;

	- dsi@a0351000 {
	+ dsi-controller@a0351000 {
	vana-supply = <&ab8500_ldo_ana_reg>;
	};
	- dsi@a0352000 {
	+ dsi-controller@a0352000 {
	vana-supply = <&ab8500_ldo_ana_reg>;
	};
	- dsi@a0353000 {
	+ dsi-controller@a0353000 {
	vana-supply = <&ab8500_ldo_ana_reg>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/ste-dbx5x0.dtsi b/sys/gnu/dts/arm/ste-dbx5x0.dtsi
	index 6671f74c9f03..3e10da3f8fd3 100644
	--- a/sys/gnu/dts/arm/ste-dbx5x0.dtsi
	+++ b/sys/gnu/dts/arm/ste-dbx5x0.dtsi
	@@ -1,1144 +1,1144 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	/*
	* Copyright 2012 Linaro Ltd
	*/

	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/mfd/dbx500-prcmu.h>
	#include <dt-bindings/arm/ux500_pm_domains.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;

	/* This stablilizes the device enumeration */
	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	spi0 = &spi0;
	spi1 = &spi1;
	spi2 = &spi2;
	spi3 = &spi3;
	serial0 = &serial0;
	serial1 = &serial1;
	serial2 = &serial2;
	};

	chosen {
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "ste,dbx500-smp";

	cpu-map {
	cluster0 {
	core0 {
	cpu = <&CPU0>;
	};
	core1 {
	cpu = <&CPU1>;
	};
	};
	};
	CPU0: cpu@300 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <0x300>;
	clocks = <&prcmu_clk PRCMU_ARMSS>;
	clock-names = "cpu";
	clock-latency = <20000>;
	#cooling-cells = <2>;
	};
	CPU1: cpu@301 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <0x301>;
	};
	};

	thermal-zones {
	/*
	* Thermal zone for the SoC, using the thermal sensor in the
	* PRCMU for temperature and the cpufreq driver for passive
	* cooling.
	*/
	cpu_thermal: cpu-thermal {
	polling-delay-passive = <250>;
	/*
	* This sensor fires interrupts to update the thermal
	* zone, so no polling is needed.
	*/
	polling-delay = <0>;

	thermal-sensors = <&thermal>;

	trips {
	cpu_alert: cpu-alert {
	temperature = <70000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu-crit {
	temperature = <85000>;
	hysteresis = <0>;
	type = "critical";
	};
	};

	cooling-maps {
	trip = <&cpu_alert>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	contribution = <100>;
	};
	};
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "stericsson,db8500", "simple-bus";
	interrupt-parent = <&intc>;
	ranges;

	ptm@801ae000 {
	compatible = "arm,coresight-etm3x", "arm,primecell";
	reg = <0x801ae000 0x1000>;

	clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
	clock-names = "apb_pclk", "atclk";
	cpu = <&CPU0>;
	out-ports {
	port {
	ptm0_out_port: endpoint {
	remote-endpoint = <&funnel_in_port0>;
	};
	};
	};
	};

	ptm@801af000 {
	compatible = "arm,coresight-etm3x", "arm,primecell";
	reg = <0x801af000 0x1000>;

	clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
	clock-names = "apb_pclk", "atclk";
	cpu = <&CPU1>;
	out-ports {
	port {
	ptm1_out_port: endpoint {
	remote-endpoint = <&funnel_in_port1>;
	};
	};
	};
	};

	funnel@801a6000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0x801a6000 0x1000>;

	clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
	clock-names = "apb_pclk", "atclk";
	out-ports {
	port {
	funnel_out_port: endpoint {
	remote-endpoint =
	<&replicator_in_port0>;
	};
	};
	};

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	funnel_in_port0: endpoint {
	remote-endpoint = <&ptm0_out_port>;
	};
	};

	port@1 {
	reg = <1>;
	funnel_in_port1: endpoint {
	remote-endpoint = <&ptm1_out_port>;
	};
	};
	};
	};

	replicator {
	compatible = "arm,coresight-static-replicator";
	clocks = <&prcmu_clk PRCMU_APEATCLK>;
	clock-names = "atclk";

	out-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	replicator_out_port0: endpoint {
	remote-endpoint = <&tpiu_in_port>;
	};
	};
	port@1 {
	reg = <1>;
	replicator_out_port1: endpoint {
	remote-endpoint = <&etb_in_port>;
	};
	};
	};

	in-ports {
	port {
	replicator_in_port0: endpoint {
	remote-endpoint = <&funnel_out_port>;
	};
	};
	};
	};

	tpiu@80190000 {
	compatible = "arm,coresight-tpiu", "arm,primecell";
	reg = <0x80190000 0x1000>;

	clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
	clock-names = "apb_pclk", "atclk";
	in-ports {
	port {
	tpiu_in_port: endpoint {
	remote-endpoint = <&replicator_out_port0>;
	};
	};
	};
	};

	etb@801a4000 {
	compatible = "arm,coresight-etb10", "arm,primecell";
	reg = <0x801a4000 0x1000>;

	clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
	clock-names = "apb_pclk", "atclk";
	in-ports {
	port {
	etb_in_port: endpoint {
	remote-endpoint = <&replicator_out_port1>;
	};
	};
	};
	};

	intc: interrupt-controller@a0411000 {
	compatible = "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	#address-cells = <1>;
	interrupt-controller;
	reg = <0xa0411000 0x1000>,
	<0xa0410100 0x100>;
	};

	scu@a0410000 {
	compatible = "arm,cortex-a9-scu";
	reg = <0xa0410000 0x100>;
	};

	/*
	* The backup RAM is used for retention during sleep
	* and various things like spin tables
	*/
	backupram@80150000 {
	compatible = "ste,dbx500-backupram";
	reg = <0x80150000 0x2000>;
	};

	L2: l2-cache {
	compatible = "arm,pl310-cache";
	reg = <0xa0412000 0x1000>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	cache-unified;
	cache-level = <2>;
	};

	pmu {
	compatible = "arm,cortex-a9-pmu";
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	pm_domains: pm_domains0 {
	compatible = "stericsson,ux500-pm-domains";
	#power-domain-cells = <1>;
	};

	clocks {
	compatible = "stericsson,u8500-clks";
	/*
	* Registers for the CLKRST block on peripheral
	* groups 1, 2, 3, 5, 6,
	*/
	reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
	<0x8000f000 0x1000>, <0xa03ff000 0x1000>,
	<0xa03cf000 0x1000>;

	prcmu_clk: prcmu-clock {
	#clock-cells = <1>;
	};

	prcc_pclk: prcc-periph-clock {
	#clock-cells = <2>;
	};

	prcc_kclk: prcc-kernel-clock {
	#clock-cells = <2>;
	};

	rtc_clk: rtc32k-clock {
	#clock-cells = <0>;
	};

	smp_twd_clk: smp-twd-clock {
	#clock-cells = <0>;
	};
	};

	mtu@a03c6000 {
	/* Nomadik System Timer */
	compatible = "st,nomadik-mtu";
	reg = <0xa03c6000 0x1000>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
	clock-names = "timclk", "apb_pclk";
	};

	timer@a0410600 {
	compatible = "arm,cortex-a9-twd-timer";
	reg = <0xa0410600 0x20>;
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) \| IRQ_TYPE_LEVEL_HIGH)>;

	clocks = <&smp_twd_clk>;
	};

	watchdog@a0410620 {
	compatible = "arm,cortex-a9-twd-wdt";
	reg = <0xa0410620 0x20>;
	interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&smp_twd_clk>;
	};

	rtc@80154000 {
	compatible = "arm,pl031", "arm,primecell";
	reg = <0x80154000 0x1000>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&rtc_clk>;
	clock-names = "apb_pclk";
	};

	gpio0: gpio@8012e000 {
	compatible = "stericsson,db8500-gpio",
	"st,nomadik-gpio";
	reg = <0x8012e000 0x80>;
	interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	st,supports-sleepmode;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-bank = <0>;
	gpio-ranges = <&pinctrl 0 0 32>;
	clocks = <&prcc_pclk 1 9>;
	};

	gpio1: gpio@8012e080 {
	compatible = "stericsson,db8500-gpio",
	"st,nomadik-gpio";
	reg = <0x8012e080 0x80>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	st,supports-sleepmode;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-bank = <1>;
	gpio-ranges = <&pinctrl 0 32 5>;
	clocks = <&prcc_pclk 1 9>;
	};

	gpio2: gpio@8000e000 {
	compatible = "stericsson,db8500-gpio",
	"st,nomadik-gpio";
	reg = <0x8000e000 0x80>;
	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	st,supports-sleepmode;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-bank = <2>;
	gpio-ranges = <&pinctrl 0 64 32>;
	clocks = <&prcc_pclk 3 8>;
	};

	gpio3: gpio@8000e080 {
	compatible = "stericsson,db8500-gpio",
	"st,nomadik-gpio";
	reg = <0x8000e080 0x80>;
	interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	st,supports-sleepmode;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-bank = <3>;
	gpio-ranges = <&pinctrl 0 96 2>;
	clocks = <&prcc_pclk 3 8>;
	};

	gpio4: gpio@8000e100 {
	compatible = "stericsson,db8500-gpio",
	"st,nomadik-gpio";
	reg = <0x8000e100 0x80>;
	interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	st,supports-sleepmode;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-bank = <4>;
	gpio-ranges = <&pinctrl 0 128 32>;
	clocks = <&prcc_pclk 3 8>;
	};

	gpio5: gpio@8000e180 {
	compatible = "stericsson,db8500-gpio",
	"st,nomadik-gpio";
	reg = <0x8000e180 0x80>;
	interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	st,supports-sleepmode;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-bank = <5>;
	gpio-ranges = <&pinctrl 0 160 12>;
	clocks = <&prcc_pclk 3 8>;
	};

	gpio6: gpio@8011e000 {
	compatible = "stericsson,db8500-gpio",
	"st,nomadik-gpio";
	reg = <0x8011e000 0x80>;
	interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	st,supports-sleepmode;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-bank = <6>;
	gpio-ranges = <&pinctrl 0 192 32>;
	clocks = <&prcc_pclk 2 11>;
	};

	gpio7: gpio@8011e080 {
	compatible = "stericsson,db8500-gpio",
	"st,nomadik-gpio";
	reg = <0x8011e080 0x80>;
	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	st,supports-sleepmode;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-bank = <7>;
	gpio-ranges = <&pinctrl 0 224 7>;
	clocks = <&prcc_pclk 2 11>;
	};

	gpio8: gpio@a03fe000 {
	compatible = "stericsson,db8500-gpio",
	"st,nomadik-gpio";
	reg = <0xa03fe000 0x80>;
	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	st,supports-sleepmode;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-bank = <8>;
	gpio-ranges = <&pinctrl 0 256 12>;
	clocks = <&prcc_pclk 5 1>;
	};

	pinctrl: pinctrl {
	compatible = "stericsson,db8500-pinctrl";
	nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
	<&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
	<&gpio8>;
	prcm = <&prcmu>;
	};

	usb_per5@a03e0000 {
	compatible = "stericsson,db8500-musb";
	reg = <0xa03e0000 0x10000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "mc";

	dr_mode = "otg";

	dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
	<&dma 38 0 0x0>, /* Logical - MemToDev */
	<&dma 37 0 0x2>, /* Logical - DevToMem */
	<&dma 37 0 0x0>, /* Logical - MemToDev */
	<&dma 36 0 0x2>, /* Logical - DevToMem */
	<&dma 36 0 0x0>, /* Logical - MemToDev */
	<&dma 19 0 0x2>, /* Logical - DevToMem */
	<&dma 19 0 0x0>, /* Logical - MemToDev */
	<&dma 18 0 0x2>, /* Logical - DevToMem */
	<&dma 18 0 0x0>, /* Logical - MemToDev */
	<&dma 17 0 0x2>, /* Logical - DevToMem */
	<&dma 17 0 0x0>, /* Logical - MemToDev */
	<&dma 16 0 0x2>, /* Logical - DevToMem */
	<&dma 16 0 0x0>, /* Logical - MemToDev */
	<&dma 39 0 0x2>, /* Logical - DevToMem */
	<&dma 39 0 0x0>; /* Logical - MemToDev */

	dma-names = "iep_1_9", "oep_1_9",
	"iep_2_10", "oep_2_10",
	"iep_3_11", "oep_3_11",
	"iep_4_12", "oep_4_12",
	"iep_5_13", "oep_5_13",
	"iep_6_14", "oep_6_14",
	"iep_7_15", "oep_7_15",
	"iep_8", "oep_8";

	clocks = <&prcc_pclk 5 0>;
	};

	dma: dma-controller@801C0000 {
	compatible = "stericsson,db8500-dma40", "stericsson,dma40";
	reg = <0x801C0000 0x1000 0x40010000 0x800>;
	reg-names = "base", "lcpa";
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

	#dma-cells = <3>;
	memcpy-channels = <56 57 58 59 60>;

	clocks = <&prcmu_clk PRCMU_DMACLK>;
	};

	prcmu: prcmu@80157000 {
	compatible = "stericsson,db8500-prcmu", "syscon";
	reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
	reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-controller;
	#interrupt-cells = <2>;
	ranges;

	prcmu-timer-4@80157450 {
	compatible = "stericsson,db8500-prcmu-timer-4";
	reg = <0x80157450 0xC>;
	};

	thermal: thermal@801573c0 {
	compatible = "stericsson,db8500-thermal";
	reg = <0x801573c0 0x40>;
	interrupt-parent = <&prcmu>;
	interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
	<22 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
	#thermal-sensor-cells = <0>;
	};

	db8500-prcmu-regulators {
	compatible = "stericsson,db8500-prcmu-regulator";

	// DB8500_REGULATOR_VAPE
	db8500_vape_reg: db8500_vape {
	regulator-always-on;
	};

	// DB8500_REGULATOR_VARM
	db8500_varm_reg: db8500_varm {
	};

	// DB8500_REGULATOR_VMODEM
	db8500_vmodem_reg: db8500_vmodem {
	};

	// DB8500_REGULATOR_VPLL
	db8500_vpll_reg: db8500_vpll {
	};

	// DB8500_REGULATOR_VSMPS1
	db8500_vsmps1_reg: db8500_vsmps1 {
	};

	// DB8500_REGULATOR_VSMPS2
	db8500_vsmps2_reg: db8500_vsmps2 {
	};

	// DB8500_REGULATOR_VSMPS3
	db8500_vsmps3_reg: db8500_vsmps3 {
	};

	// DB8500_REGULATOR_VRF1
	db8500_vrf1_reg: db8500_vrf1 {
	};

	// DB8500_REGULATOR_SWITCH_SVAMMDSP
	db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
	};

	// DB8500_REGULATOR_SWITCH_SVAMMDSPRET
	db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
	};

	// DB8500_REGULATOR_SWITCH_SVAPIPE
	db8500_sva_pipe_reg: db8500_sva_pipe {
	};

	// DB8500_REGULATOR_SWITCH_SIAMMDSP
	db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
	};

	// DB8500_REGULATOR_SWITCH_SIAMMDSPRET
	db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
	};

	// DB8500_REGULATOR_SWITCH_SIAPIPE
	db8500_sia_pipe_reg: db8500_sia_pipe {
	};

	// DB8500_REGULATOR_SWITCH_SGA
	db8500_sga_reg: db8500_sga {
	vin-supply = <&db8500_vape_reg>;
	};

	// DB8500_REGULATOR_SWITCH_B2R2_MCDE
	db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
	vin-supply = <&db8500_vape_reg>;
	};

	// DB8500_REGULATOR_SWITCH_ESRAM12
	db8500_esram12_reg: db8500_esram12 {
	};

	// DB8500_REGULATOR_SWITCH_ESRAM12RET
	db8500_esram12_ret_reg: db8500_esram12_ret {
	};

	// DB8500_REGULATOR_SWITCH_ESRAM34
	db8500_esram34_reg: db8500_esram34 {
	};

	// DB8500_REGULATOR_SWITCH_ESRAM34RET
	db8500_esram34_ret_reg: db8500_esram34_ret {
	};
	};
	};

	i2c0: i2c@80004000 {
	compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
	reg = <0x80004000 0x1000>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;

	#address-cells = <1>;
	#size-cells = <0>;
	v-i2c-supply = <&db8500_vape_reg>;

	clock-frequency = <400000>;
	clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
	clock-names = "i2cclk", "apb_pclk";
	power-domains = <&pm_domains DOMAIN_VAPE>;

	status = "disabled";
	};

	i2c1: i2c@80122000 {
	compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
	reg = <0x80122000 0x1000>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;

	#address-cells = <1>;
	#size-cells = <0>;
	v-i2c-supply = <&db8500_vape_reg>;

	clock-frequency = <400000>;

	clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
	clock-names = "i2cclk", "apb_pclk";
	power-domains = <&pm_domains DOMAIN_VAPE>;

	status = "disabled";
	};

	i2c2: i2c@80128000 {
	compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
	reg = <0x80128000 0x1000>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;

	#address-cells = <1>;
	#size-cells = <0>;
	v-i2c-supply = <&db8500_vape_reg>;

	clock-frequency = <400000>;

	clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
	clock-names = "i2cclk", "apb_pclk";
	power-domains = <&pm_domains DOMAIN_VAPE>;

	status = "disabled";
	};

	i2c3: i2c@80110000 {
	compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
	reg = <0x80110000 0x1000>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;

	#address-cells = <1>;
	#size-cells = <0>;
	v-i2c-supply = <&db8500_vape_reg>;

	clock-frequency = <400000>;

	clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
	clock-names = "i2cclk", "apb_pclk";
	power-domains = <&pm_domains DOMAIN_VAPE>;

	status = "disabled";
	};

	i2c4: i2c@8012a000 {
	compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
	reg = <0x8012a000 0x1000>;
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

	#address-cells = <1>;
	#size-cells = <0>;
	v-i2c-supply = <&db8500_vape_reg>;

	clock-frequency = <400000>;

	clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
	clock-names = "i2cclk", "apb_pclk";
	power-domains = <&pm_domains DOMAIN_VAPE>;

	status = "disabled";
	};

	ssp0: spi@80002000 {
	compatible = "arm,pl022", "arm,primecell";
	reg = <0x80002000 0x1000>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
	clock-names = "SSPCLK", "apb_pclk";
	dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
	<&dma 8 0 0x0>; /* Logical - MemToDev */
	dma-names = "rx", "tx";
	power-domains = <&pm_domains DOMAIN_VAPE>;

	status = "disabled";
	};

	ssp1: spi@80003000 {
	compatible = "arm,pl022", "arm,primecell";
	reg = <0x80003000 0x1000>;
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
	clock-names = "SSPCLK", "apb_pclk";
	dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
	<&dma 9 0 0x0>; /* Logical - MemToDev */
	dma-names = "rx", "tx";
	power-domains = <&pm_domains DOMAIN_VAPE>;

	status = "disabled";
	};

	spi0: spi@8011a000 {
	compatible = "arm,pl022", "arm,primecell";
	reg = <0x8011a000 0x1000>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	/* Same clock wired to kernel and pclk */
	clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
	clock-names = "SSPCLK", "apb_pclk";
	dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
	<&dma 0 0 0x0>; /* Logical - MemToDev */
	dma-names = "rx", "tx";
	power-domains = <&pm_domains DOMAIN_VAPE>;

	status = "disabled";
	};

	spi1: spi@80112000 {
	compatible = "arm,pl022", "arm,primecell";
	reg = <0x80112000 0x1000>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	/* Same clock wired to kernel and pclk */
	clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
	clock-names = "SSPCLK", "apb_pclk";
	dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
	<&dma 35 0 0x0>; /* Logical - MemToDev */
	dma-names = "rx", "tx";
	power-domains = <&pm_domains DOMAIN_VAPE>;

	status = "disabled";
	};

	spi2: spi@80111000 {
	compatible = "arm,pl022", "arm,primecell";
	reg = <0x80111000 0x1000>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	/* Same clock wired to kernel and pclk */
	clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
	clock-names = "SSPCLK", "apb_pclk";
	dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
	<&dma 33 0 0x0>; /* Logical - MemToDev */
	dma-names = "rx", "tx";
	power-domains = <&pm_domains DOMAIN_VAPE>;

	status = "disabled";
	};

	spi3: spi@80129000 {
	compatible = "arm,pl022", "arm,primecell";
	reg = <0x80129000 0x1000>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	/* Same clock wired to kernel and pclk */
	clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
	clock-names = "SSPCLK", "apb_pclk";
	dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
	<&dma 40 0 0x0>; /* Logical - MemToDev */
	dma-names = "rx", "tx";
	power-domains = <&pm_domains DOMAIN_VAPE>;

	status = "disabled";
	};

	serial0: uart@80120000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x80120000 0x1000>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

	dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
	<&dma 13 0 0x0>; /* Logical - MemToDev */
	dma-names = "rx", "tx";

	clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
	clock-names = "uart", "apb_pclk";

	status = "disabled";
	};

	serial1: uart@80121000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x80121000 0x1000>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;

	dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
	<&dma 12 0 0x0>; /* Logical - MemToDev */
	dma-names = "rx", "tx";

	clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
	clock-names = "uart", "apb_pclk";

	status = "disabled";
	};

	serial2: uart@80007000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x80007000 0x1000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;

	dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
	<&dma 11 0 0x0>; /* Logical - MemToDev */
	dma-names = "rx", "tx";

	clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
	clock-names = "uart", "apb_pclk";

	status = "disabled";
	};

	sdi0_per1@80126000 {
	compatible = "arm,pl18x", "arm,primecell";
	reg = <0x80126000 0x1000>;
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;

	dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
	<&dma 29 0 0x0>; /* Logical - MemToDev */
	dma-names = "rx", "tx";

	clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
	clock-names = "sdi", "apb_pclk";
	power-domains = <&pm_domains DOMAIN_VAPE>;

	status = "disabled";
	};

	sdi1_per2@80118000 {
	compatible = "arm,pl18x", "arm,primecell";
	reg = <0x80118000 0x1000>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;

	dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
	<&dma 32 0 0x0>; /* Logical - MemToDev */
	dma-names = "rx", "tx";

	clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
	clock-names = "sdi", "apb_pclk";
	power-domains = <&pm_domains DOMAIN_VAPE>;

	status = "disabled";
	};

	sdi2_per3@80005000 {
	compatible = "arm,pl18x", "arm,primecell";
	reg = <0x80005000 0x1000>;
	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;

	dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
	<&dma 28 0 0x0>; /* Logical - MemToDev */
	dma-names = "rx", "tx";

	clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
	clock-names = "sdi", "apb_pclk";
	power-domains = <&pm_domains DOMAIN_VAPE>;

	status = "disabled";
	};

	sdi3_per2@80119000 {
	compatible = "arm,pl18x", "arm,primecell";
	reg = <0x80119000 0x1000>;
	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;

	dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
	<&dma 41 0 0x0>; /* Logical - MemToDev */
	dma-names = "rx", "tx";

	clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
	clock-names = "sdi", "apb_pclk";
	power-domains = <&pm_domains DOMAIN_VAPE>;

	status = "disabled";
	};

	sdi4_per2@80114000 {
	compatible = "arm,pl18x", "arm,primecell";
	reg = <0x80114000 0x1000>;
	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

	dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
	<&dma 42 0 0x0>; /* Logical - MemToDev */
	dma-names = "rx", "tx";

	clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
	clock-names = "sdi", "apb_pclk";
	power-domains = <&pm_domains DOMAIN_VAPE>;

	status = "disabled";
	};

	sdi5_per3@80008000 {
	compatible = "arm,pl18x", "arm,primecell";
	reg = <0x80008000 0x1000>;
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;

	dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
	<&dma 43 0 0x0>; /* Logical - MemToDev */
	dma-names = "rx", "tx";

	clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
	clock-names = "sdi", "apb_pclk";
	power-domains = <&pm_domains DOMAIN_VAPE>;

	status = "disabled";
	};

	sound {
	compatible = "stericsson,snd-soc-mop500";
	stericsson,cpu-dai = <&msp1 &msp3>;
	};

	msp0: msp@80123000 {
	compatible = "stericsson,ux500-msp-i2s";
	reg = <0x80123000 0x1000>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	v-ape-supply = <&db8500_vape_reg>;

	dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
	<&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
	dma-names = "rx", "tx";

	clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
	clock-names = "msp", "apb_pclk";

	status = "disabled";
	};

	msp1: msp@80124000 {
	compatible = "stericsson,ux500-msp-i2s";
	reg = <0x80124000 0x1000>;
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	v-ape-supply = <&db8500_vape_reg>;

	/* This DMA channel only exist on DB8500 v1 */
	dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
	dma-names = "tx";

	clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
	clock-names = "msp", "apb_pclk";

	status = "disabled";
	};

	// HDMI sound
	msp2: msp@80117000 {
	compatible = "stericsson,ux500-msp-i2s";
	reg = <0x80117000 0x1000>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	v-ape-supply = <&db8500_vape_reg>;

	dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
	<&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
	HighPrio - Fixed */
	dma-names = "rx", "tx";

	clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
	clock-names = "msp", "apb_pclk";

	status = "disabled";
	};

	msp3: msp@80125000 {
	compatible = "stericsson,ux500-msp-i2s";
	reg = <0x80125000 0x1000>;
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	v-ape-supply = <&db8500_vape_reg>;

	/* This DMA channel only exist on DB8500 v2 */
	dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
	dma-names = "rx";

	clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
	clock-names = "msp", "apb_pclk";

	status = "disabled";
	};

	external-bus@50000000 {
	compatible = "simple-bus";
	reg = <0x50000000 0x4000000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x50000000 0x4000000>;
	status = "disabled";
	};

	gpu@a0300000 {
	/*
	* This block is referred to as "Smart Graphics Adapter SGA500"
	* in documentation but is in practice a pretty straight-forward
	* MALI-400 GPU block.
	*/
	compatible = "stericsson,db8500-mali", "arm,mali-400";
	reg = <0xa0300000 0x10000>;
	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gp",
	"gpmmu",
	"pp0",
	"ppmmu0",
	"combined";
	clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>;
	clock-names = "bus", "core";
	mali-supply = <&db8500_sga_reg>;
	power-domains = <&pm_domains DOMAIN_VAPE>;
	};

	mcde@a0350000 {
	compatible = "ste,mcde";
	reg = <0xa0350000 0x1000>;
	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	epod-supply = <&db8500_b2r2_mcde_reg>;
	clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
	<&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
	<&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */
	clock-names = "mcde", "lcd", "hdmi";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	status = "disabled";

	- dsi0: dsi@a0351000 {
	+ dsi0: dsi-controller@a0351000 {
	compatible = "ste,mcde-dsi";
	reg = <0xa0351000 0x1000>;
	clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
	clock-names = "hs", "lp";
	#address-cells = <1>;
	#size-cells = <0>;
	};
	- dsi1: dsi@a0352000 {
	+ dsi1: dsi-controller@a0352000 {
	compatible = "ste,mcde-dsi";
	reg = <0xa0352000 0x1000>;
	clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
	clock-names = "hs", "lp";
	#address-cells = <1>;
	#size-cells = <0>;
	};
	- dsi2: dsi@a0353000 {
	+ dsi2: dsi-controller@a0353000 {
	compatible = "ste,mcde-dsi";
	reg = <0xa0353000 0x1000>;
	/* This DSI port only has the Low Power / Energy Save clock */
	clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
	clock-names = "lp";
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	cryp@a03cb000 {
	compatible = "stericsson,ux500-cryp";
	reg = <0xa03cb000 0x1000>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;

	v-ape-supply = <&db8500_vape_reg>;
	clocks = <&prcc_pclk 6 1>;
	};

	hash@a03c2000 {
	compatible = "stericsson,ux500-hash";
	reg = <0xa03c2000 0x1000>;

	v-ape-supply = <&db8500_vape_reg>;
	clocks = <&prcc_pclk 6 2>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/ste-href-stuib.dtsi b/sys/gnu/dts/arm/ste-href-stuib.dtsi
	index e32d0c36feb8..b8fd8f18ba16 100644
	--- a/sys/gnu/dts/arm/ste-href-stuib.dtsi
	+++ b/sys/gnu/dts/arm/ste-href-stuib.dtsi
	@@ -1,212 +1,212 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	/*
	* Copyright 2012 ST-Ericsson AB
	*/

	#include <dt-bindings/interrupt-controller/irq.h>

	/ {
	gpio_keys {
	compatible = "gpio-keys";
	#address-cells = <1>;
	#size-cells = <0>;
	vdd-supply = <&ab8500_ldo_aux1_reg>;
	pinctrl-names = "default";
	pinctrl-0 = <&prox_stuib_mode>, <&hall_stuib_mode>;

	button@139 {
	/* Proximity sensor */
	gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>;
	linux,code = <11>; /* SW_FRONT_PROXIMITY */
	label = "SFH7741 Proximity Sensor";
	};
	button@145 {
	/* Hall sensor */
	gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>;
	linux,code = <0>; /* SW_LID */
	label = "HED54XXU11 Hall Effect Sensor";
	};
	};

	soc {
	i2c@80004000 {
	stmpe1601: stmpe1601@40 {
	compatible = "st,stmpe1601";
	reg = <0x40>;
	interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
	interrupt-parent = <&gpio6>;
	interrupt-controller;
	vcc-supply = <&db8500_vsmps2_reg>;
	vio-supply = <&db8500_vsmps2_reg>;
	pinctrl-names = "default";
	pinctrl-0 = <&stmpe_stuib_mode>;

	wakeup-source;
	st,autosleep-timeout = <1024>;

	stmpe_keypad {
	compatible = "st,stmpe-keypad";

	debounce-interval = <64>;
	st,scan-count = <8>;
	st,no-autorepeat;

	linux,keymap = <0x205006b
	0x4010074
	0x3050072
	0x1030004
	0x502006a
	0x500000a
	0x5008b
	0x706001c
	0x405000b
	0x6070003
	0x3040067
	0x303006c
	0x60400e7
	0x602009e
	0x4020073
	0x5050002
	0x4030069
	0x3020008>;
	};
	};
	};

	/* Sensors mounted on this board variant */
	i2c@80128000 {
	lis331dl@1c {
	/* Accelerometer */
	compatible = "st,lis331dl-accel";
	st,drdy-int-pin = <1>;
	reg = <0x1c>;
	vdd-supply = <&ab8500_ldo_aux1_reg>;
	vddio-supply = <&db8500_vsmps2_reg>;
	pinctrl-names = "default";
	pinctrl-0 = <&accel_stuib_mode>;
	interrupt-parent = <&gpio2>;
	interrupts = <18 IRQ_TYPE_EDGE_RISING>,
	<19 IRQ_TYPE_EDGE_RISING>;
	};
	ak8974@f {
	/* Magnetometer */
	compatible = "asahi-kasei,ak8974";
	reg = <0x0f>;
	vdd-supply = <&ab8500_ldo_aux1_reg>;
	vddio-supply = <&db8500_vsmps2_reg>;
	pinctrl-names = "default";
	pinctrl-0 = <&magneto_stuib_mode>;
	interrupt-parent = <&gpio1>;
	interrupts = <0 IRQ_TYPE_EDGE_RISING>;
	};
	};

	i2c@80110000 {
	bu21013_tp@5c {
	compatible = "rohm,bu21013_tp";
	reg = <0x5c>;
	avdd-supply = <&ab8500_ldo_aux1_reg>;

	rohm,touch-max-x = <384>;
	rohm,touch-max-y = <704>;
	rohm,flip-y;
	pinctrl-names = "default";
	pinctrl-0 = <&touch_rohm_mode>;
	};

	bu21013_tp@5d {
	compatible = "rohm,bu21013_tp";
	reg = <0x5d>;
	avdd-supply = <&ab8500_ldo_aux1_reg>;

	rohm,touch-max-x = <384>;
	rohm,touch-max-y = <704>;
	rohm,flip-y;
	pinctrl-names = "default";
	pinctrl-0 = <&touch_rohm_mode>;
	};
	};

	pinctrl {
	/* Pull up this GPIO pin */
	stmpe {
	stmpe_stuib_mode: stmpe_stuib {
	stuib_cfg {
	ste,pins = "GPIO218_AH11";
	ste,config = <&gpio_in_pu>;
	};
	};
	};
	prox {
	prox_stuib_mode: prox_stuib {
	stuib_cfg {
	pins = "GPIO217_AH12";
	ste,config = <&gpio_in_pu>;
	};
	};
	};
	hall {
	hall_stuib_mode: stuib_tvk {
	stuib_cfg {
	pins = "GPIO145_C13";
	ste,config = <&gpio_in_pu>;
	};
	};
	};
	accelerometer {
	accel_stuib_mode: accel_stuib {
	/* Accelerometer interrupt lines 1 & 2 */
	stuib_cfg {
	pins = "GPIO82_C1", "GPIO83_D3";
	ste,config = <&gpio_in_pu>;
	};
	};
	};
	magnetometer {
	magneto_stuib_mode: magneto_stuib {
	/* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
	stuib_cfg1 {
	pins = "GPIO31_V3";
	ste,config = <&gpio_in_pu>;
	};
	stuib_cfg2 {
	pins = "GPIO32_V2";
	ste,config = <&gpio_in_pd>;
	};
	};
	};
	touch {
	touch_rohm_mode: touch_rohm {
	/*
	* ROHM touch screen uses GPIO 143 for
	* RST1, GPIO 146 for RST2 and
	* GPIO 67 for interrupts. Pull-up
	* the IRQ line and drive both
	* reset signals low.
	*/
	stuib_cfg1 {
	pins = "GPIO143_D12", "GPIO146_D13";
	ste,config = <&gpio_out_lo>;
	};
	stuib_cfg2 {
	pins = "GPIO67_G2";
	ste,config = <&gpio_in_pu>;
	};
	};
	};
	};

	mcde@a0350000 {
	status = "okay";

	- dsi@a0351000 {
	+ dsi-controller@a0351000 {
	panel {
	compatible = "samsung,s6d16d0";
	reg = <0>;
	vdd1-supply = <&ab8500_ldo_aux1_reg>;
	reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/ste-href-tvk1281618-r2.dtsi b/sys/gnu/dts/arm/ste-href-tvk1281618-r2.dtsi
	index e024520f4d47..de82b9db956f 100644
	--- a/sys/gnu/dts/arm/ste-href-tvk1281618-r2.dtsi
	+++ b/sys/gnu/dts/arm/ste-href-tvk1281618-r2.dtsi
	@@ -1,79 +1,79 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	/*
	* Device Tree for the TVK1281618 R2 UIB
	*/

	#include "ste-href-tvk1281618.dtsi"

	/ {
	soc {
	i2c@80128000 {
	lsm303dlh@18 {
	/* Accelerometer */
	compatible = "st,lsm303dlh-accel";
	st,drdy-int-pin = <1>;
	drive-open-drain;
	reg = <0x18>;
	vdd-supply = <&ab8500_ldo_aux1_reg>;
	vddio-supply = <&db8500_vsmps2_reg>;
	pinctrl-names = "default";
	pinctrl-0 = <&accel_tvk_mode>;
	/*
	* These interrupts cannot be used: the other component
	* ST-Micro L3D4200D gyro that is connected to the same lines
	* cannot set its DRDY line to open drain, so it cannot be
	* shared with other peripherals. The should be defined for
	* the falling edge if they could be wired together.
	*
	* interrupts-extended =
	* <&gpio1 0 IRQ_TYPE_EDGE_FALLING>,
	* <&gpio2 19 IRQ_TYPE_EDGE_FALLING>;
	*/
	};
	lsm303dlh@1e {
	/* Magnetometer */
	compatible = "st,lsm303dlh-magn";
	reg = <0x1e>;
	vdd-supply = <&ab8500_ldo_aux1_reg>;
	vddio-supply = <&db8500_vsmps2_reg>;
	/*
	* These interrupts cannot be used: the other component
	* ST-Micro L3D4200D gyro that is connected to the same lines
	* cannot set its DRDY line to open drain, so it cannot be
	* shared with other peripherals. The should be defined for
	* the falling edge if they could be wired together.
	*
	* interrupts-extended =
	* <&gpio1 0 IRQ_TYPE_EDGE_FALLING>,
	* <&gpio2 19 IRQ_TYPE_EDGE_FALLING>;
	*/
	};
	lis331dl@1c {
	/* Accelerometer */
	compatible = "st,lis331dl-accel";
	st,drdy-int-pin = <1>;
	reg = <0x1c>;
	vdd-supply = <&ab8500_ldo_aux1_reg>;
	vddio-supply = <&db8500_vsmps2_reg>;
	pinctrl-names = "default";
	pinctrl-0 = <&accel_tvk_mode>;
	interrupt-parent = <&gpio2>;
	/* INT2 would need to be open drain */
	interrupts = <18 IRQ_TYPE_EDGE_RISING>,
	<19 IRQ_TYPE_EDGE_RISING>;
	};
	};
	mcde@a0350000 {
	status = "okay";

	- dsi@a0351000 {
	+ dsi-controller@a0351000 {
	panel {
	compatible = "samsung,s6d16d0";
	reg = <0>;
	vdd1-supply = <&ab8500_ldo_aux1_reg>;
	reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/ste-href-tvk1281618-r3.dtsi b/sys/gnu/dts/arm/ste-href-tvk1281618-r3.dtsi
	index cb3677f0a1cb..9f285c7cf914 100644
	--- a/sys/gnu/dts/arm/ste-href-tvk1281618-r3.dtsi
	+++ b/sys/gnu/dts/arm/ste-href-tvk1281618-r3.dtsi
	@@ -1,58 +1,58 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	/*
	* Device Tree for the TVK1281618 R2 UIB
	*/

	#include "ste-href-tvk1281618.dtsi"

	/ {
	soc {
	i2c@80128000 {
	/* Marked:
	* 129
	* M35
	* L3GD20
	*/
	l3gd20@6a {
	/* Gyroscope */
	compatible = "st,l3gd20";
	status = "disabled";
	st,drdy-int-pin = <1>;
	drive-open-drain;
	reg = <0x6a>; // 0x6a or 0x6b
	vdd-supply = <&ab8500_ldo_aux1_reg>;
	vddio-supply = <&db8500_vsmps2_reg>;
	};
	/*
	* Marked:
	* 2122
	* C3H
	* DQEEE
	* LIS3DH?
	*/
	lis3dh@18 {
	/* Accelerometer */
	compatible = "st,lis3dh-accel";
	st,drdy-int-pin = <1>;
	reg = <0x18>;
	vdd-supply = <&ab8500_ldo_aux1_reg>;
	vddio-supply = <&db8500_vsmps2_reg>;
	pinctrl-names = "default";
	pinctrl-0 = <&accel_tvk_mode>;
	};
	};

	mcde@a0350000 {
	status = "okay";

	- dsi@a0351000 {
	+ dsi-controller@a0351000 {
	panel {
	compatible = "sony,acx424akp";
	reg = <0>;
	vddi-supply = <&ab8500_ldo_aux1_reg>;
	reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/ste-ux500-samsung-skomer.dts b/sys/gnu/dts/arm/ste-ux500-samsung-skomer.dts
	new file mode 100644
	index 000000000000..292ed5286652
	--- /dev/null
	+++ b/sys/gnu/dts/arm/ste-ux500-samsung-skomer.dts
	@@ -0,0 +1,581 @@
	+// SPDX-License-Identifier: GPL-2.0-only
	+/*
	+ * Devicetree for the Samsung XCover 2 GT-S7710 also known as Skomer.
	+ */
	+
	+/dts-v1/;
	+#include "ste-db8500.dtsi"
	+#include "ste-ab8505.dtsi"
	+#include "ste-dbx5x0-pinctrl.dtsi"
	+#include <dt-bindings/gpio/gpio.h>
	+#include <dt-bindings/input/input.h>
	+#include <dt-bindings/interrupt-controller/irq.h>
	+
	+/ {
	+ model = "Samsung XCover 2 (GT-S7710)";
	+ compatible = "samsung,skomer", "st-ericsson,u8500";
	+
	+ chosen {
	+ stdout-path = &serial2;
	+ };
	+
	+ /* TI TXS0206 level translator for 2.9 V */
	+ sd_level_translator: regulator-gpio {
	+ compatible = "regulator-fixed";
	+
	+ /* GPIO87 EN */
	+ gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
	+ enable-active-high;
	+
	+ regulator-name = "sd-level-translator";
	+ regulator-min-microvolt = <2900000>;
	+ regulator-max-microvolt = <2900000>;
	+ regulator-type = "voltage";
	+
	+ startup-delay-us = <200>;
	+
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&sd_level_translator_default>;
	+ };
	+
	+ /* External LDO MIC5366-3.3YMT for eMMC */
	+ ldo_3v3_reg: regulator-gpio-ldo-3v3 {
	+ compatible = "regulator-fixed";
	+ regulator-name = "en-3v3-fixed-supply";
	+ regulator-min-microvolt = <3300000>;
	+ regulator-max-microvolt = <3300000>;
	+ gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>;
	+ startup-delay-us = <5000>;
	+ enable-active-high;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&emmc_ldo_en_default_mode>;
	+ };
	+
	+ wlan_en: regulator-gpio-wlan-en {
	+ compatible = "regulator-fixed";
	+ regulator-name = "wl-reg-on";
	+ regulator-min-microvolt = <3000000>;
	+ regulator-max-microvolt = <3000000>;
	+ startup-delay-us = <200000>;
	+ /* GPIO215 WLAN_EN */
	+ gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>;
	+ enable-active-high;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&wlan_en_default_mode>;
	+ };
	+
	+ vibrator {
	+ compatible = "gpio-vibrator";
	+ enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&vibrator_default>;
	+ };
	+
	+ gpio-keys {
	+ compatible = "gpio-keys";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&gpio_keys_default_mode>;
	+
	+ button-home {
	+ linux,code = <KEY_HOME>;
	+ label = "HOME";
	+ /* GPIO91 */
	+ gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
	+ };
	+ button-volup {
	+ linux,code = <KEY_VOLUMEUP>;
	+ label = "VOL+";
	+ /* GPIO67 */
	+ gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
	+ };
	+ button-voldown {
	+ linux,code = <KEY_VOLUMEDOWN>;
	+ label = "VOL-";
	+ /* GPIO92 */
	+ gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
	+ };
	+ button-menu {
	+ linux,code = <KEY_MENU>;
	+ label = "MENU";
	+ /* GPIO204 */
	+ gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
	+ };
	+ button-back {
	+ linux,code = <KEY_BACK>;
	+ label = "BACK";
	+ /* GPIO205 */
	+ gpios = <&gpio6 13 GPIO_ACTIVE_LOW>;
	+ };
	+ };
	+
	+ /*
	+ * FIXME: this is not quite GPIO backlight. This is a
	+ * KTD253 one-wire GPIO-controlled backlight. It can
	+ * work as a GPIO backlight.
	+ */
	+ gpio_bl: backlight {
	+ compatible = "gpio-backlight";
	+ /* GPIO 69 */
	+ gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&gpio_backlight_default_mode>;
	+ };
	+
	+ i2c-gpio-0 {
	+ compatible = "i2c-gpio";
	+ sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH\|GPIO_OPEN_DRAIN)>;
	+ scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH\|GPIO_OPEN_DRAIN)>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&i2c_gpio_0_default>;
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ /* TODO: this should be used by the NCP6914 Camera power management unit */
	+ };
	+
	+ i2c-gpio-1 {
	+ compatible = "i2c-gpio";
	+ sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH\|GPIO_OPEN_DRAIN)>;
	+ scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH\|GPIO_OPEN_DRAIN)>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&i2c_gpio_1_default>;
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ /* TODO: this should be used by the ALPS HSCDTD008A compass sensor */
	+ };
	+
	+ soc {
	+ // External Micro SD slot
	+ sdi0_per1@80126000 {
	+ arm,primecell-periphid = <0x10480180>;
	+ max-frequency = <100000000>;
	+ bus-width = <4>;
	+ cap-sd-highspeed;
	+ cap-mmc-highspeed;
	+ /* All direction control is used */
	+ st,sig-dir-cmd;
	+ st,sig-dir-dat0;
	+ st,sig-dir-dat2;
	+ st,sig-dir-dat31;
	+ st,sig-pin-fbclk;
	+ full-pwr-cycle;
	+ vmmc-supply = <&ab8500_ldo_aux3_reg>;
	+ vqmmc-supply = <&sd_level_translator>;
	+ pinctrl-names = "default", "sleep";
	+ pinctrl-0 = <&mc0_a_1_default>;
	+ pinctrl-1 = <&mc0_a_1_sleep>;
	+ status = "okay";
	+ };
	+
	+ // WLAN SDIO channel
	+ sdi1_per2@80118000 {
	+ arm,primecell-periphid = <0x10480180>;
	+ max-frequency = <50000000>;
	+ bus-width = <4>;
	+ non-removable;
	+ cap-sd-highspeed;
	+ vmmc-supply = <&wlan_en>;
	+ pinctrl-names = "default", "sleep";
	+ pinctrl-0 = <&mc1_a_2_default>;
	+ pinctrl-1 = <&mc1_a_2_sleep>;
	+ status = "okay";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ wifi@1 {
	+ compatible = "brcm,bcm4329-fmac";
	+ reg = <1>;
	+ /* GPIO216 WL_HOST_WAKE */
	+ interrupt-parent = <&gpio6>;
	+ interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
	+ interrupt-names = "host-wake";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&wlan_default_mode>;
	+ };
	+ };
	+
	+ // eMMC
	+ sdi2_per3@80005000 {
	+ arm,primecell-periphid = <0x10480180>;
	+ max-frequency = <100000000>;
	+ bus-width = <8>;
	+ non-removable;
	+ cap-mmc-highspeed;
	+ mmc-ddr-1_8v;
	+ vmmc-supply = <&ldo_3v3_reg>;
	+ pinctrl-names = "default", "sleep";
	+ pinctrl-0 = <&mc2_a_1_default>;
	+ pinctrl-1 = <&mc2_a_1_sleep>;
	+
	+ status = "okay";
	+ };
	+
	+ /* GBF (Bluetooth) UART */
	+ uart@80120000 {
	+ pinctrl-names = "default", "sleep";
	+ pinctrl-0 = <&u0_a_1_default>;
	+ pinctrl-1 = <&u0_a_1_sleep>;
	+ status = "okay";
	+
	+ /* FIXME: not quite working yet, probably needs regulators */
	+ bluetooth {
	+ compatible = "brcm,bcm4330-bt";
	+ shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
	+ device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
	+ host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&bluetooth_default_mode>;
	+ };
	+ };
	+
	+ /* GPF UART */
	+ uart@80121000 {
	+ status = "okay";
	+ pinctrl-names = "default", "sleep";
	+ pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>;
	+ pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>;
	+ };
	+
	+ /* Debugging console UART connected to AB8505 USB */
	+ uart@80007000 {
	+ status = "okay";
	+ pinctrl-names = "default", "sleep";
	+ pinctrl-0 = <&u2rxtx_c_1_default>;
	+ pinctrl-1 = <&u2rxtx_c_1_sleep>;
	+ };
	+
	+ prcmu@80157000 {
	+ ab8505 {
	+ ab8500_usb {
	+ pinctrl-names = "default", "sleep";
	+ pinctrl-0 = <&usb_a_1_default>;
	+ pinctrl-1 = <&usb_a_1_sleep>;
	+ };
	+
	+ ab8505-regulators {
	+ ab8500_ldo_aux1 {
	+ /* Used for VDD for sensors */
	+ regulator-name = "AUX1";
	+ regulator-min-microvolt = <3000000>;
	+ regulator-max-microvolt = <3300000>;
	+ };
	+
	+ ab8500_ldo_aux2 {
	+ /* Supplies the Cypress TMA140 touchscreen only with 3.3V */
	+ regulator-name = "AUX2";
	+ regulator-min-microvolt = <3300000>;
	+ regulator-max-microvolt = <3300000>;
	+ };
	+
	+ ab8500_ldo_aux3 {
	+ /* Used for voltage for external MMC/SD card */
	+ regulator-name = "AUX3";
	+ regulator-min-microvolt = <1100000>;
	+ regulator-max-microvolt = <3300000>;
	+ };
	+
	+ ab8500_ldo_aux4 {
	+ regulator-name = "AUX4";
	+ /* Hammer to 3.0V for the display */
	+ regulator-min-microvolt = <3000000>;
	+ regulator-max-microvolt = <3000000>;
	+ };
	+
	+ ab8500_ldo_aux5 {
	+ regulator-name = "AUX5";
	+ regulator-min-microvolt = <1050000>;
	+ regulator-max-microvolt = <2790000>;
	+ regulator-always-on;
	+ };
	+
	+ ab8500_ldo_aux6 {
	+ regulator-name = "AUX6";
	+ /* Hammer to 1.8V for the display */
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+ };
	+
	+ ab8500_ldo_aux8 {
	+ /* Mostly VIO for sensors */
	+ regulator-name = "AUX8";
	+ };
	+ };
	+ };
	+ };
	+
	+ /* I2C0 */
	+ i2c@80004000 {
	+ status = "okay";
	+
	+ pinctrl-names = "default", "sleep";
	+ pinctrl-0 = <&i2c0_a_1_default>;
	+ pinctrl-1 = <&i2c0_a_1_sleep>;
	+
	+ proximity@44 {
	+ compatible = "sharp,gp2ap002s00f";
	+ clock-frequency = <400000>;
	+ reg = <0x44>;
	+
	+ interrupt-parent = <&gpio4>;
	+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
	+ vdd-supply = <&ab8500_ldo_aux1_reg>;
	+ vio-supply = <&ab8500_ldo_aux8_reg>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&gp2ap002_skomer_default>;
	+ sharp,proximity-far-hysteresis = /bits/ 8 <0x2f>;
	+ sharp,proximity-close-hysteresis = /bits/ 8 <0x0f>;
	+ };
	+ };
	+
	+
	+ /* I2C2 */
	+ i2c@80128000 {
	+ status = "okay";
	+
	+ pinctrl-names = "default", "sleep";
	+ pinctrl-0 = <&i2c2_b_2_default>;
	+ pinctrl-1 = <&i2c2_b_2_sleep>;
	+
	+ accel@18 {
	+ compatible = "bosch,bma254";
	+ clock-frequency = <400000>;
	+ reg = <0x18>;
	+
	+ /* GPIO224 used as "smart alert" interrupt */
	+ interrupt-parent = <&gpio7>;
	+ interrupts = <0 IRQ_TYPE_EDGE_RISING>;
	+
	+ mount-matrix = "0", "1", "0",
	+ "-1", "0", "0",
	+ "0", "0", "1";
	+ vdd-supply = <&ab8500_ldo_aux1_reg>;
	+ vddio-supply = <&ab8500_ldo_aux8_reg>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&bma254_skomer_default>;
	+ };
	+ };
	+
	+ /* I2C3 */
	+ i2c@80110000 {
	+ status = "okay";
	+
	+ pinctrl-names = "default", "sleep";
	+ pinctrl-0 = <&i2c3_c_2_default>;
	+ pinctrl-1 = <&i2c3_c_2_sleep>;
	+
	+ /* TODO: this should be used by the Cypress TMA140 touchscreen */
	+ };
	+
	+ mcde@a0350000 {
	+ status = "okay";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&dsi_default_mode>;
	+
	+ dsi-controller@a0351000 {
	+ panel {
	+ /* NT35510-based Hydis HVA40WV1 */
	+ compatible = "hydis,hva40wv1", "novatek,nt35510";
	+ reg = <0>;
	+ /* v_lcd_3v0 2.3-4.8V */
	+ vdd-supply = <&ab8500_ldo_aux4_reg>;
	+ /* v_lcd_1v8 1.65-3.3V */
	+ vddi-supply = <&ab8500_ldo_aux6_reg>;
	+ /* GPIO 139 */
	+ reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&display_default_mode>;
	+ backlight = <&gpio_bl>;
	+ };
	+ };
	+ };
	+ };
	+};
	+
	+&pinctrl {
	+ /*
	+ * This extends the MC0 default config to include DAT32DIR
	+ * which is used by this machine. If we don't do this the
	+ * SD card does not work.
	+ */
	+ sdi0 {
	+ mc0_a_1_default {
	+ default_mux {
	+ function = "mc0";
	+ /* This machine uses the DAT31 pin */
	+ groups = "mc0_a_1", "mc0dat31dir_a_1";
	+ };
	+ default_cfg5 {
	+ pins = "GPIO21_AB3"; /* DAT31DIR */
	+ ste,config = <&out_hi>;
	+ };
	+ };
	+ };
	+
	+ mcde {
	+ dsi_default_mode: dsi_default {
	+ default_mux1 {
	+ /* Mux in VSI0 used for DSI TE */
	+ function = "lcd";
	+ groups = "lcdvsi0_a_1"; /* VSI0 for LCD */
	+ };
	+ default_cfg1 {
	+ pins = "GPIO68_E1"; /* VSI0 */
	+ ste,config = <&in_nopull>;
	+ };
	+ };
	+ };
	+
	+ /* Two GPIO lines used by the display */
	+ display {
	+ display_default_mode: display_default {
	+ skomer_cfg1 {
	+ /*
	+ * OLED DETECT or check_pba, this appears to be high
	+ * on "PBA" which I guess is "prototype board A".
	+ */
	+ pins = "GPIO93_B7";
	+ ste,config = <&gpio_in_nopull>;
	+ };
	+ skomer_cfg2 {
	+ pins = "GPIO139_C9";
	+ /*
	+ * MIPI_DSI0_RESET_N resets the display, leave high
	+ * (de-asserted) so we only assert reset explicitly
	+ * from the display driver.
	+ */
	+ ste,config = <&gpio_out_hi>;
	+ };
	+ };
	+ };
	+ backlight {
	+ gpio_backlight_default_mode: backlight_default {
	+ skomer_cfg1 {
	+ pins = "GPIO69_E2"; /* LCD_BL_CTRL */
	+ ste,config = <&gpio_out_lo>;
	+ };
	+ };
	+ };
	+ /* GPIO that enables the 2.9V SD card level translator */
	+ sd-level-translator {
	+ sd_level_translator_default: sd_level_translator_default {
	+ /* level shifter on GPIO87 */
	+ skomer_cfg1 {
	+ pins = "GPIO87_B3";
	+ ste,config = <&gpio_out_hi>;
	+ };
	+ };
	+ };
	+ /* GPIO that enables the LDO regulator for the eMMC */
	+ emmc-ldo {
	+ emmc_ldo_en_default_mode: emmc_ldo_default {
	+ /* LDO enable on GPIO223 */
	+ skomer_cfg1 {
	+ pins = "GPIO223_AH9";
	+ ste,config = <&gpio_out_hi>;
	+ };
	+ };
	+ };
	+ /* GPIO keys */
	+ gpio-keys {
	+ gpio_keys_default_mode: gpio_keys_default {
	+ skomer_cfg1 {
	+ pins = "GPIO67_G2", /* VOL UP */
	+ "GPIO91_B6", /* HOME */
	+ "GPIO92_D6", /* VOL DOWN */
	+ "GPIO204_AF23", /* MENU */
	+ "GPIO205_AG23"; /* BACK */
	+ ste,config = <&gpio_in_pu>;
	+ };
	+ };
	+ };
	+ /* Interrupt line for BMA254 */
	+ bma254 {
	+ bma254_skomer_default: bma254_skomer {
	+ skomer_cfg1 {
	+ pins = "GPIO224_AG9";
	+ ste,config = <&gpio_in_pd>;
	+ };
	+ };
	+ };
	+ /* Interrupt line for light/proximity sensor GP2AP002 */
	+ gp2ap002 {
	+ gp2ap002_skomer_default: gp2ap002_skomer {
	+ skomer_cfg1 {
	+ pins = "GPIO146_D13";
	+ ste,config = <&gpio_in_nopull>;
	+ };
	+ };
	+ };
	+ /* GPIO-based I2C bus for NCP6914 */
	+ i2c-gpio-0 {
	+ i2c_gpio_0_default: i2c_gpio_0 {
	+ skomer_cfg1 {
	+ pins = "GPIO143_D12", "GPIO144_B13";
	+ ste,config = <&gpio_in_nopull>;
	+ };
	+ };
	+ };
	+ /* GPIO-based I2C bus for ALPS HSCD compass */
	+ i2c-gpio-1 {
	+ i2c_gpio_1_default: i2c_gpio_1 {
	+ skomer_cfg1 {
	+ pins = "GPIO151_B17", "GPIO152_D16";
	+ ste,config = <&gpio_in_nopull>;
	+ };
	+ };
	+ };
	+ wlan {
	+ wlan_default_mode: wlan_default {
	+ skomer_cfg1 {
	+ pins = "GPIO216_AG12";
	+ ste,config = <&gpio_in_pd>;
	+ };
	+ };
	+ wlan_en_default_mode: wlan_en_default {
	+ skomer_cfg2 {
	+ pins = "GPIO215_AH13";
	+ ste,config = <&gpio_out_lo>;
	+ };
	+ };
	+ };
	+ bluetooth {
	+ bluetooth_default_mode: bluetooth_default {
	+ skomer_cfg1 {
	+ pins = "GPIO199_AH23", "GPIO222_AJ9";
	+ ste,config = <&gpio_out_lo>;
	+ };
	+ skomer_cfg2 {
	+ pins = "GPIO97_D9";
	+ ste,config = <&gpio_in_nopull>;
	+ };
	+ };
	+ };
	+ vibrator {
	+ vibrator_default: vibrator_default {
	+ skomer_cfg1 {
	+ pins = "GPIO195_AG28"; /* MOT_EN */
	+ ste,config = <&gpio_out_lo>;
	+ };
	+ };
	+ };
	+};
	+
	+&ab8505_gpio {
	+ /* Hog a few default settings */
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&gpio_default>;
	+
	+ gpio {
	+ gpio_default: gpio_default {
	+ skomer_mux {
	+ /* Change unused pins to GPIO mode */
	+ function = "gpio";
	+ groups = "gpio3_a_1", /* default: SysClkReq4 */
	+ "gpio14_a_1"; /* default: PWMOut1 */
	+ };
	+ skomer_cfg1 {
	+ pins = "GPIO11_B17", "GPIO13_D17", "GPIO50_L4";
	+ bias-disable;
	+ };
	+ };
	+ };
	+};
	diff --git a/sys/gnu/dts/arm/stm32746g-eval.dts b/sys/gnu/dts/arm/stm32746g-eval.dts
	index fcc804e3c158..4ea3f98dd275 100644
	--- a/sys/gnu/dts/arm/stm32746g-eval.dts
	+++ b/sys/gnu/dts/arm/stm32746g-eval.dts
	@@ -1,212 +1,212 @@
	/*
	* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	/dts-v1/;
	#include "stm32f746.dtsi"
	#include "stm32f746-pinctrl.dtsi"
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/irq.h>

	/ {
	model = "STMicroelectronics STM32746g-EVAL board";
	compatible = "st,stm32746g-eval", "st,stm32f746";

	chosen {
	bootargs = "root=/dev/ram";
	stdout-path = "serial0:115200n8";
	};

	memory@c0000000 {
	device_type = "memory";
	reg = <0xc0000000 0x2000000>;
	};

	aliases {
	serial0 = &usart1;
	};

	leds {
	compatible = "gpio-leds";
	green {
	gpios = <&gpiof 10 1>;
	linux,default-trigger = "heartbeat";
	};
	orange {
	gpios = <&stmfx_pinctrl 17 1>;
	};
	red {
	gpios = <&gpiob 7 1>;
	};
	blue {
	gpios = <&stmfx_pinctrl 19 1>;
	};
	};

	gpio_keys {
	compatible = "gpio-keys";
	#address-cells = <1>;
	#size-cells = <0>;
	autorepeat;
	button@0 {
	label = "Wake up";
	linux,code = <KEY_WAKEUP>;
	gpios = <&gpioc 13 0>;
	};
	};

	joystick {
	compatible = "gpio-keys";
	pinctrl-0 = <&joystick_pins>;
	pinctrl-names = "default";
	button-0 {
	label = "JoySel";
	linux,code = <KEY_ENTER>;
	interrupt-parent = <&stmfx_pinctrl>;
	interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
	};
	button-1 {
	label = "JoyDown";
	linux,code = <KEY_DOWN>;
	interrupt-parent = <&stmfx_pinctrl>;
	interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
	};
	button-2 {
	label = "JoyLeft";
	linux,code = <KEY_LEFT>;
	interrupt-parent = <&stmfx_pinctrl>;
	interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
	};
	button-3 {
	label = "JoyRight";
	linux,code = <KEY_RIGHT>;
	interrupt-parent = <&stmfx_pinctrl>;
	interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
	};
	button-4 {
	label = "JoyUp";
	linux,code = <KEY_UP>;
	interrupt-parent = <&stmfx_pinctrl>;
	interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
	};
	};

	usbotg_hs_phy: usb-phy {
	#phy-cells = <0>;
	compatible = "usb-nop-xceiv";
	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
	clock-names = "main_clk";
	};

	mmc_vcard: mmc_vcard {
	compatible = "regulator-fixed";
	regulator-name = "mmc_vcard";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};
	};

	&clk_hse {
	clock-frequency = <25000000>;
	};

	&crc {
	status = "okay";
	};

	&i2c1 {
	pinctrl-0 = <&i2c1_pins_b>;
	pinctrl-names = "default";
	i2c-scl-rising-time-ns = <185>;
	i2c-scl-falling-time-ns = <20>;
	status = "okay";

	stmfx: stmfx@42 {
	compatible = "st,stmfx-0300";
	reg = <0x42>;
	interrupts = <8 IRQ_TYPE_EDGE_RISING>;
	interrupt-parent = <&gpioi>;

	- stmfx_pinctrl: stmfx-pin-controller {
	+ stmfx_pinctrl: pinctrl {
	compatible = "st,stmfx-0300-pinctrl";
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&stmfx_pinctrl 0 0 24>;

	joystick_pins: joystick {
	pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
	drive-push-pull;
	bias-pull-up;
	};
	};
	};
	};

	&rtc {
	status = "okay";
	};

	&sdio1 {
	status = "okay";
	vmmc-supply = <&mmc_vcard>;
	broken-cd;
	pinctrl-names = "default", "opendrain";
	pinctrl-0 = <&sdio_pins_a>;
	pinctrl-1 = <&sdio_pins_od_a>;
	bus-width = <4>;
	};

	&usart1 {
	pinctrl-0 = <&usart1_pins_a>;
	pinctrl-names = "default";
	status = "okay";
	};

	&usbotg_hs {
	dr_mode = "otg";
	phys = <&usbotg_hs_phy>;
	phy-names = "usb2-phy";
	pinctrl-0 = <&usbotg_hs_pins_a>;
	pinctrl-names = "default";
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/stm32mp15-pinctrl.dtsi b/sys/gnu/dts/arm/stm32mp15-pinctrl.dtsi
	index 0237d4ddaa92..73c07f0dfad2 100644
	--- a/sys/gnu/dts/arm/stm32mp15-pinctrl.dtsi
	+++ b/sys/gnu/dts/arm/stm32mp15-pinctrl.dtsi
	@@ -1,1092 +1,1185 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
	/*
	* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
	* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
	*/
	#include <dt-bindings/pinctrl/stm32-pinfunc.h>

	&pinctrl {
	adc1_in6_pins_a: adc1-in6 {
	pins {
	pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
	};
	};

	adc12_ain_pins_a: adc12-ain-0 {
	pins {
	pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
	<STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
	<STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
	<STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
	};
	};

	adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
	pins {
	pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
	<STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
	};
	};

	cec_pins_a: cec-0 {
	pins {
	pinmux = <STM32_PINMUX('A', 15, AF4)>;
	bias-disable;
	drive-open-drain;
	slew-rate = <0>;
	};
	};

	cec_pins_sleep_a: cec-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
	};
	};

	cec_pins_b: cec-1 {
	pins {
	pinmux = <STM32_PINMUX('B', 6, AF5)>;
	bias-disable;
	drive-open-drain;
	slew-rate = <0>;
	};
	};

	cec_pins_sleep_b: cec-sleep-1 {
	pins {
	pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
	};
	};

	dac_ch1_pins_a: dac-ch1 {
	pins {
	pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
	};
	};

	dac_ch2_pins_a: dac-ch2 {
	pins {
	pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
	};
	};

	dcmi_pins_a: dcmi-0 {
	pins {
	pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
	<STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
	<STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
	<STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
	<STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
	<STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
	<STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
	<STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
	<STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
	<STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
	<STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
	<STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
	<STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
	<STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
	<STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
	bias-disable;
	};
	};

	dcmi_sleep_pins_a: dcmi-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
	<STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
	<STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
	<STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
	<STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
	<STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
	<STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
	<STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
	<STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
	<STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
	<STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
	<STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
	<STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
	<STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
	<STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
	};
	};

	ethernet0_rgmii_pins_a: rgmii-0 {
	pins1 {
	pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
	<STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
	<STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
	<STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
	<STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
	<STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
	<STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
	<STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
	bias-disable;
	drive-push-pull;
	slew-rate = <2>;
	};
	pins2 {
	pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
	bias-disable;
	drive-push-pull;
	slew-rate = <0>;
	};
	pins3 {
	pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
	<STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
	<STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
	<STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
	<STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
	<STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
	bias-disable;
	};
	};

	ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
	pins1 {
	pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
	<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
	<STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
	<STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
	<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
	<STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
	<STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
	<STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
	<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
	<STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
	<STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
	<STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
	<STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
	<STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
	<STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
	};
	};

	+ ethernet0_rmii_pins_a: rmii-0 {
	+ pins1 {
	+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
	+ <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
	+ <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
	+ <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
	+ <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
	+ <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
	+ bias-disable;
	+ drive-push-pull;
	+ slew-rate = <2>;
	+ };
	+ pins2 {
	+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
	+ <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
	+ <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
	+ bias-disable;
	+ };
	+ };
	+
	+ ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
	+ pins1 {
	+ pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
	+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
	+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
	+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
	+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
	+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
	+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
	+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
	+ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
	+ };
	+ };
	+
	fmc_pins_a: fmc-0 {
	pins1 {
	pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
	<STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
	<STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
	<STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
	<STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
	<STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
	<STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
	<STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
	<STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
	<STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
	<STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
	<STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
	<STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
	bias-disable;
	drive-push-pull;
	slew-rate = <1>;
	};
	pins2 {
	pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
	bias-pull-up;
	};
	};

	fmc_sleep_pins_a: fmc-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
	<STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
	<STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
	<STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
	<STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
	<STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
	<STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
	<STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
	<STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
	<STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
	<STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
	<STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
	<STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
	<STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
	};
	};

	i2c1_pins_a: i2c1-0 {
	pins {
	pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
	<STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
	bias-disable;
	drive-open-drain;
	slew-rate = <0>;
	};
	};

	i2c1_pins_sleep_a: i2c1-1 {
	pins {
	pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
	<STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
	};
	};

	i2c1_pins_b: i2c1-2 {
	pins {
	pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
	<STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
	bias-disable;
	drive-open-drain;
	slew-rate = <0>;
	};
	};

	i2c1_pins_sleep_b: i2c1-3 {
	pins {
	pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
	<STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
	};
	};

	i2c2_pins_a: i2c2-0 {
	pins {
	pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
	<STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
	bias-disable;
	drive-open-drain;
	slew-rate = <0>;
	};
	};

	i2c2_pins_sleep_a: i2c2-1 {
	pins {
	pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
	<STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
	};
	};

	i2c2_pins_b1: i2c2-2 {
	pins {
	pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
	bias-disable;
	drive-open-drain;
	slew-rate = <0>;
	};
	};

	i2c2_pins_sleep_b1: i2c2-3 {
	pins {
	pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
	};
	};

	i2c5_pins_a: i2c5-0 {
	pins {
	pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
	<STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
	bias-disable;
	drive-open-drain;
	slew-rate = <0>;
	};
	};

	i2c5_pins_sleep_a: i2c5-1 {
	pins {
	pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
	<STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */

	};
	};

	i2s2_pins_a: i2s2-0 {
	pins {
	pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
	<STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
	<STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
	slew-rate = <1>;
	drive-push-pull;
	bias-disable;
	};
	};

	i2s2_pins_sleep_a: i2s2-1 {
	pins {
	pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
	<STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
	<STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
	};
	};

	ltdc_pins_a: ltdc-a-0 {
	pins {
	pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
	<STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
	<STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
	<STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
	<STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
	<STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
	<STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
	<STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
	<STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
	<STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
	<STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
	<STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
	<STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
	<STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
	<STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
	<STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
	<STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
	<STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
	<STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
	<STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
	<STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
	<STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
	<STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
	<STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
	<STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
	<STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
	<STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
	<STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
	bias-disable;
	drive-push-pull;
	slew-rate = <1>;
	};
	};

	ltdc_pins_sleep_a: ltdc-a-1 {
	pins {
	pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
	<STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
	<STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
	<STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
	<STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
	<STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
	<STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
	<STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
	<STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
	<STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
	<STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
	<STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
	<STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
	<STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
	<STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
	<STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
	<STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
	<STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
	<STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
	<STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
	<STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
	<STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
	<STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
	<STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
	<STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
	<STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
	<STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
	<STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
	};
	};

	ltdc_pins_b: ltdc-b-0 {
	pins {
	pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
	<STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
	<STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
	<STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
	<STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
	<STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
	<STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
	<STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
	<STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
	<STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
	<STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
	<STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
	<STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
	<STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
	<STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
	<STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
	<STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
	<STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
	<STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
	<STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
	<STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
	<STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
	<STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
	<STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
	<STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
	<STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
	<STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
	<STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
	bias-disable;
	drive-push-pull;
	slew-rate = <1>;
	};
	};

	ltdc_pins_sleep_b: ltdc-b-1 {
	pins {
	pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
	<STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
	<STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
	<STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
	<STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
	<STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
	<STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
	<STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
	<STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
	<STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
	<STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
	<STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
	<STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
	<STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
	<STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
	<STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
	<STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
	<STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
	<STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
	<STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
	<STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
	<STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
	<STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
	<STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
	<STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
	<STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
	<STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
	<STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
	};
	};

	m_can1_pins_a: m-can1-0 {
	pins1 {
	pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
	slew-rate = <1>;
	drive-push-pull;
	bias-disable;
	};
	pins2 {
	pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
	bias-disable;
	};
	};

	m_can1_sleep_pins_a: m_can1-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
	<STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
	};
	};

	pwm1_pins_a: pwm1-0 {
	pins {
	pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
	<STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */
	<STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */
	bias-pull-down;
	drive-push-pull;
	slew-rate = <0>;
	};
	};

	pwm1_sleep_pins_a: pwm1-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
	<STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */
	<STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */
	};
	};

	pwm2_pins_a: pwm2-0 {
	pins {
	pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
	bias-pull-down;
	drive-push-pull;
	slew-rate = <0>;
	};
	};

	pwm2_sleep_pins_a: pwm2-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
	};
	};

	pwm3_pins_a: pwm3-0 {
	pins {
	pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */
	bias-pull-down;
	drive-push-pull;
	slew-rate = <0>;
	};
	};

	pwm3_sleep_pins_a: pwm3-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */
	};
	};

	pwm4_pins_a: pwm4-0 {
	pins {
	pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
	<STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
	bias-pull-down;
	drive-push-pull;
	slew-rate = <0>;
	};
	};

	pwm4_sleep_pins_a: pwm4-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
	<STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
	};
	};

	pwm4_pins_b: pwm4-1 {
	pins {
	pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
	bias-pull-down;
	drive-push-pull;
	slew-rate = <0>;
	};
	};

	pwm4_sleep_pins_b: pwm4-sleep-1 {
	pins {
	pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
	};
	};

	pwm5_pins_a: pwm5-0 {
	pins {
	pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */
	bias-pull-down;
	drive-push-pull;
	slew-rate = <0>;
	};
	};

	pwm5_sleep_pins_a: pwm5-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */
	};
	};

	pwm8_pins_a: pwm8-0 {
	pins {
	pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
	bias-pull-down;
	drive-push-pull;
	slew-rate = <0>;
	};
	};

	pwm8_sleep_pins_a: pwm8-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */
	};
	};

	pwm12_pins_a: pwm12-0 {
	pins {
	pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
	bias-pull-down;
	drive-push-pull;
	slew-rate = <0>;
	};
	};

	pwm12_sleep_pins_a: pwm12-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */
	};
	};

	qspi_clk_pins_a: qspi-clk-0 {
	pins {
	pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
	bias-disable;
	drive-push-pull;
	slew-rate = <3>;
	};
	};

	qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
	};
	};

	qspi_bk1_pins_a: qspi-bk1-0 {
	pins1 {
	pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
	<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
	<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
	<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
	bias-disable;
	drive-push-pull;
	slew-rate = <1>;
	};
	pins2 {
	pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
	bias-pull-up;
	drive-push-pull;
	slew-rate = <1>;
	};
	};

	qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
	<STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
	<STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
	<STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
	<STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
	};
	};

	qspi_bk2_pins_a: qspi-bk2-0 {
	pins1 {
	pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
	<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
	<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
	<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
	bias-disable;
	drive-push-pull;
	slew-rate = <1>;
	};
	pins2 {
	pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
	bias-pull-up;
	drive-push-pull;
	slew-rate = <1>;
	};
	};

	qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
	<STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
	<STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
	<STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
	<STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
	};
	};

	sai2a_pins_a: sai2a-0 {
	pins {
	pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
	<STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
	<STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
	<STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
	slew-rate = <0>;
	drive-push-pull;
	bias-disable;
	};
	};

	sai2a_sleep_pins_a: sai2a-1 {
	pins {
	pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
	<STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
	<STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
	<STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
	};
	};

	+
	+ sai2a_pins_b: sai2a-2 {
	+ pins1 {
	+ pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
	+ <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
	+ <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */
	+ slew-rate = <0>;
	+ drive-push-pull;
	+ bias-disable;
	+ };
	+ };
	+
	+ sai2a_sleep_pins_b: sai2a-sleep-3 {
	+ pins {
	+ pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
	+ <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
	+ <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */
	+ };
	+ };
	+
	sai2b_pins_a: sai2b-0 {
	pins1 {
	pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
	<STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
	<STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
	slew-rate = <0>;
	drive-push-pull;
	bias-disable;
	};
	pins2 {
	pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
	bias-disable;
	};
	};

	sai2b_sleep_pins_a: sai2b-1 {
	pins {
	pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
	<STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
	<STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
	<STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
	};
	};

	sai2b_pins_b: sai2b-2 {
	pins {
	pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
	bias-disable;
	};
	};

	sai2b_sleep_pins_b: sai2b-3 {
	pins {
	pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
	};
	};

	sai4a_pins_a: sai4a-0 {
	pins {
	pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
	slew-rate = <0>;
	drive-push-pull;
	bias-disable;
	};
	};

	sai4a_sleep_pins_a: sai4a-1 {
	pins {
	pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
	};
	};

	sdmmc1_b4_pins_a: sdmmc1-b4-0 {
	pins1 {
	pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
	<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
	<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
	<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
	<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
	slew-rate = <1>;
	drive-push-pull;
	bias-disable;
	};
	pins2 {
	pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
	slew-rate = <2>;
	drive-push-pull;
	bias-disable;
	};
	};

	sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
	pins1 {
	pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
	<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
	<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
	<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
	slew-rate = <1>;
	drive-push-pull;
	bias-disable;
	};
	pins2 {
	pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
	slew-rate = <2>;
	drive-push-pull;
	bias-disable;
	};
	pins3 {
	pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
	slew-rate = <1>;
	drive-open-drain;
	bias-disable;
	};
	};

	sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
	<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
	<STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
	<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
	<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
	<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
	};
	};

	sdmmc1_dir_pins_a: sdmmc1-dir-0 {
	pins1 {
	pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
	<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
	<STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
	slew-rate = <1>;
	drive-push-pull;
	bias-pull-up;
	};
	pins2{
	pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
	bias-pull-up;
	};
	};

	sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
	<STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
	<STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
	<STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
	};
	};

	sdmmc2_b4_pins_a: sdmmc2-b4-0 {
	pins1 {
	pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
	<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
	<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
	<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
	<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
	slew-rate = <1>;
	drive-push-pull;
	bias-pull-up;
	};
	pins2 {
	pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
	slew-rate = <2>;
	drive-push-pull;
	bias-pull-up;
	};
	};

	sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
	pins1 {
	pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
	<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
	<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
	<STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
	slew-rate = <1>;
	drive-push-pull;
	bias-pull-up;
	};
	pins2 {
	pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
	slew-rate = <2>;
	drive-push-pull;
	bias-pull-up;
	};
	pins3 {
	pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
	slew-rate = <1>;
	drive-open-drain;
	bias-pull-up;
	};
	};

	sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
	<STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
	<STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
	<STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
	<STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
	<STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
	};
	};

	sdmmc2_b4_pins_b: sdmmc2-b4-1 {
	pins1 {
	pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
	<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
	<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
	<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
	<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
	slew-rate = <1>;
	drive-push-pull;
	bias-disable;
	};
	pins2 {
	pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
	slew-rate = <2>;
	drive-push-pull;
	bias-disable;
	};
	};

	sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
	pins1 {
	pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
	<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
	<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
	<STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
	slew-rate = <1>;
	drive-push-pull;
	bias-disable;
	};
	pins2 {
	pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
	slew-rate = <2>;
	drive-push-pull;
	bias-disable;
	};
	pins3 {
	pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
	slew-rate = <1>;
	drive-open-drain;
	bias-disable;
	};
	};

	sdmmc2_d47_pins_a: sdmmc2-d47-0 {
	pins {
	pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
	<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
	<STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
	<STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
	slew-rate = <1>;
	drive-push-pull;
	bias-pull-up;
	};
	};

	sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
	<STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
	<STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
	<STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
	};
	};

	sdmmc3_b4_pins_a: sdmmc3-b4-0 {
	pins1 {
	pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
	<STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
	<STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
	<STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
	<STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
	slew-rate = <1>;
	drive-push-pull;
	bias-pull-up;
	};
	pins2 {
	pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
	slew-rate = <2>;
	drive-push-pull;
	bias-pull-up;
	};
	};

	sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
	pins1 {
	pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
	<STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
	<STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
	<STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
	slew-rate = <1>;
	drive-push-pull;
	bias-pull-up;
	};
	pins2 {
	pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
	slew-rate = <2>;
	drive-push-pull;
	bias-pull-up;
	};
	pins3 {
	pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
	slew-rate = <1>;
	drive-open-drain;
	bias-pull-up;
	};
	};

	sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
	pins {
	pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
	<STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
	<STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
	<STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
	<STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
	<STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
	};
	};

	spdifrx_pins_a: spdifrx-0 {
	pins {
	pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
	bias-disable;
	};
	};

	spdifrx_sleep_pins_a: spdifrx-1 {
	pins {
	pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
	};
	};

	+ usart3_pins_a: usart3-0 {
	+ pins1 {
	+ pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
	+ bias-disable;
	+ drive-push-pull;
	+ slew-rate = <0>;
	+ };
	+ pins2 {
	+ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
	+ bias-disable;
	+ };
	+ };
	+
	uart4_pins_a: uart4-0 {
	pins1 {
	pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
	bias-disable;
	drive-push-pull;
	slew-rate = <0>;
	};
	pins2 {
	pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
	bias-disable;
	};
	};

	uart4_pins_b: uart4-1 {
	pins1 {
	pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
	bias-disable;
	drive-push-pull;
	slew-rate = <0>;
	};
	pins2 {
	pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
	bias-disable;
	};
	};

	uart7_pins_a: uart7-0 {
	pins1 {
	pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
	bias-disable;
	drive-push-pull;
	slew-rate = <0>;
	};
	pins2 {
	pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
	<STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
	<STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
	bias-disable;
	};
	};
	+
	+ uart8_pins_a: uart8-0 {
	+ pins1 {
	+ pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
	+ bias-disable;
	+ drive-push-pull;
	+ slew-rate = <0>;
	+ };
	+ pins2 {
	+ pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
	+ bias-disable;
	+ };
	+ };
	+
	+ usbotg_hs_pins_a: usbotg-hs-0 {
	+ pins {
	+ pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
	+ };
	+ };
	+
	+ usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
	+ pins {
	+ pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
	+ <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
	+ };
	+ };
	};

	&pinctrl_z {
	i2c2_pins_b2: i2c2-0 {
	pins {
	pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
	bias-disable;
	drive-open-drain;
	slew-rate = <0>;
	};
	};

	i2c2_pins_sleep_b2: i2c2-1 {
	pins {
	pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
	};
	};

	i2c4_pins_a: i2c4-0 {
	pins {
	pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
	<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
	bias-disable;
	drive-open-drain;
	slew-rate = <0>;
	};
	};

	i2c4_pins_sleep_a: i2c4-1 {
	pins {
	pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
	<STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
	};
	};

	spi1_pins_a: spi1-0 {
	pins1 {
	pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
	<STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
	bias-disable;
	drive-push-pull;
	slew-rate = <1>;
	};

	pins2 {
	pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
	bias-disable;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/stm32mp151.dtsi b/sys/gnu/dts/arm/stm32mp151.dtsi
	index fb41d0778b00..3ea05ba48215 100644
	--- a/sys/gnu/dts/arm/stm32mp151.dtsi
	+++ b/sys/gnu/dts/arm/stm32mp151.dtsi
	@@ -1,1692 +1,1706 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
	/*
	* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
	* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
	*/
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/stm32mp1-clks.h>
	#include <dt-bindings/reset/stm32mp1-resets.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a7";
	+ clock-frequency = <650000000>;
	device_type = "cpu";
	reg = <0>;
	};
	};

	psci {
	compatible = "arm,psci";
	method = "smc";
	cpu_off = <0x84000002>;
	cpu_on = <0x84000003>;
	};

	intc: interrupt-controller@a0021000 {
	compatible = "arm,cortex-a7-gic";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0xa0021000 0x1000>,
	<0xa0022000 0x2000>;
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	interrupt-parent = <&intc>;
	};

	clocks {
	clk_hse: clk-hse {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	};

	clk_hsi: clk-hsi {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <64000000>;
	};

	clk_lse: clk-lse {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	};

	clk_lsi: clk-lsi {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32000>;
	};

	clk_csi: clk-csi {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <4000000>;
	};
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	polling-delay-passive = <0>;
	polling-delay = <0>;
	thermal-sensors = <&dts>;

	trips {
	cpu_alert1: cpu-alert1 {
	temperature = <85000>;
	hysteresis = <0>;
	type = "passive";
	};

	cpu-crit {
	temperature = <120000>;
	hysteresis = <0>;
	type = "critical";
	};
	};

	cooling-maps {
	};
	};
	};

	booster: regulator-booster {
	compatible = "st,stm32mp1-booster";
	st,syscfg = <&syscfg>;
	status = "disabled";
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&intc>;
	ranges;

	timers2: timer@40000000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32-timers";
	reg = <0x40000000 0x400>;
	clocks = <&rcc TIM2_K>;
	clock-names = "int";
	dmas = <&dmamux1 18 0x400 0x1>,
	<&dmamux1 19 0x400 0x1>,
	<&dmamux1 20 0x400 0x1>,
	<&dmamux1 21 0x400 0x1>,
	<&dmamux1 22 0x400 0x1>;
	dma-names = "ch1", "ch2", "ch3", "ch4", "up";
	status = "disabled";

	pwm {
	compatible = "st,stm32-pwm";
	#pwm-cells = <3>;
	status = "disabled";
	};

	timer@1 {
	compatible = "st,stm32h7-timer-trigger";
	reg = <1>;
	status = "disabled";
	};

	counter {
	compatible = "st,stm32-timer-counter";
	status = "disabled";
	};
	};

	timers3: timer@40001000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32-timers";
	reg = <0x40001000 0x400>;
	clocks = <&rcc TIM3_K>;
	clock-names = "int";
	dmas = <&dmamux1 23 0x400 0x1>,
	<&dmamux1 24 0x400 0x1>,
	<&dmamux1 25 0x400 0x1>,
	<&dmamux1 26 0x400 0x1>,
	<&dmamux1 27 0x400 0x1>,
	<&dmamux1 28 0x400 0x1>;
	dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
	status = "disabled";

	pwm {
	compatible = "st,stm32-pwm";
	#pwm-cells = <3>;
	status = "disabled";
	};

	timer@2 {
	compatible = "st,stm32h7-timer-trigger";
	reg = <2>;
	status = "disabled";
	};

	counter {
	compatible = "st,stm32-timer-counter";
	status = "disabled";
	};
	};

	timers4: timer@40002000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32-timers";
	reg = <0x40002000 0x400>;
	clocks = <&rcc TIM4_K>;
	clock-names = "int";
	dmas = <&dmamux1 29 0x400 0x1>,
	<&dmamux1 30 0x400 0x1>,
	<&dmamux1 31 0x400 0x1>,
	<&dmamux1 32 0x400 0x1>;
	dma-names = "ch1", "ch2", "ch3", "ch4";
	status = "disabled";

	pwm {
	compatible = "st,stm32-pwm";
	#pwm-cells = <3>;
	status = "disabled";
	};

	timer@3 {
	compatible = "st,stm32h7-timer-trigger";
	reg = <3>;
	status = "disabled";
	};

	counter {
	compatible = "st,stm32-timer-counter";
	status = "disabled";
	};
	};

	timers5: timer@40003000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32-timers";
	reg = <0x40003000 0x400>;
	clocks = <&rcc TIM5_K>;
	clock-names = "int";
	dmas = <&dmamux1 55 0x400 0x1>,
	<&dmamux1 56 0x400 0x1>,
	<&dmamux1 57 0x400 0x1>,
	<&dmamux1 58 0x400 0x1>,
	<&dmamux1 59 0x400 0x1>,
	<&dmamux1 60 0x400 0x1>;
	dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
	status = "disabled";

	pwm {
	compatible = "st,stm32-pwm";
	#pwm-cells = <3>;
	status = "disabled";
	};

	timer@4 {
	compatible = "st,stm32h7-timer-trigger";
	reg = <4>;
	status = "disabled";
	};

	counter {
	compatible = "st,stm32-timer-counter";
	status = "disabled";
	};
	};

	timers6: timer@40004000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32-timers";
	reg = <0x40004000 0x400>;
	clocks = <&rcc TIM6_K>;
	clock-names = "int";
	dmas = <&dmamux1 69 0x400 0x1>;
	dma-names = "up";
	status = "disabled";

	timer@5 {
	compatible = "st,stm32h7-timer-trigger";
	reg = <5>;
	status = "disabled";
	};
	};

	timers7: timer@40005000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32-timers";
	reg = <0x40005000 0x400>;
	clocks = <&rcc TIM7_K>;
	clock-names = "int";
	dmas = <&dmamux1 70 0x400 0x1>;
	dma-names = "up";
	status = "disabled";

	timer@6 {
	compatible = "st,stm32h7-timer-trigger";
	reg = <6>;
	status = "disabled";
	};
	};

	timers12: timer@40006000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32-timers";
	reg = <0x40006000 0x400>;
	clocks = <&rcc TIM12_K>;
	clock-names = "int";
	status = "disabled";

	pwm {
	compatible = "st,stm32-pwm";
	#pwm-cells = <3>;
	status = "disabled";
	};

	timer@11 {
	compatible = "st,stm32h7-timer-trigger";
	reg = <11>;
	status = "disabled";
	};
	};

	timers13: timer@40007000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32-timers";
	reg = <0x40007000 0x400>;
	clocks = <&rcc TIM13_K>;
	clock-names = "int";
	status = "disabled";

	pwm {
	compatible = "st,stm32-pwm";
	#pwm-cells = <3>;
	status = "disabled";
	};

	timer@12 {
	compatible = "st,stm32h7-timer-trigger";
	reg = <12>;
	status = "disabled";
	};
	};

	timers14: timer@40008000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32-timers";
	reg = <0x40008000 0x400>;
	clocks = <&rcc TIM14_K>;
	clock-names = "int";
	status = "disabled";

	pwm {
	compatible = "st,stm32-pwm";
	#pwm-cells = <3>;
	status = "disabled";
	};

	timer@13 {
	compatible = "st,stm32h7-timer-trigger";
	reg = <13>;
	status = "disabled";
	};
	};

	lptimer1: timer@40009000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32-lptimer";
	reg = <0x40009000 0x400>;
	clocks = <&rcc LPTIM1_K>;
	clock-names = "mux";
	status = "disabled";

	pwm {
	compatible = "st,stm32-pwm-lp";
	#pwm-cells = <3>;
	status = "disabled";
	};

	trigger@0 {
	compatible = "st,stm32-lptimer-trigger";
	reg = <0>;
	status = "disabled";
	};

	counter {
	compatible = "st,stm32-lptimer-counter";
	status = "disabled";
	};
	};

	spi2: spi@4000b000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32h7-spi";
	reg = <0x4000b000 0x400>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc SPI2_K>;
	resets = <&rcc SPI2_R>;
	dmas = <&dmamux1 39 0x400 0x05>,
	<&dmamux1 40 0x400 0x05>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2s2: audio-controller@4000b000 {
	compatible = "st,stm32h7-i2s";
	#sound-dai-cells = <0>;
	reg = <0x4000b000 0x400>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&dmamux1 39 0x400 0x01>,
	<&dmamux1 40 0x400 0x01>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi3: spi@4000c000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32h7-spi";
	reg = <0x4000c000 0x400>;
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc SPI3_K>;
	resets = <&rcc SPI3_R>;
	dmas = <&dmamux1 61 0x400 0x05>,
	<&dmamux1 62 0x400 0x05>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2s3: audio-controller@4000c000 {
	compatible = "st,stm32h7-i2s";
	#sound-dai-cells = <0>;
	reg = <0x4000c000 0x400>;
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&dmamux1 61 0x400 0x01>,
	<&dmamux1 62 0x400 0x01>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spdifrx: audio-controller@4000d000 {
	compatible = "st,stm32h7-spdifrx";
	#sound-dai-cells = <0>;
	reg = <0x4000d000 0x400>;
	clocks = <&rcc SPDIF_K>;
	clock-names = "kclk";
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&dmamux1 93 0x400 0x01>,
	<&dmamux1 94 0x400 0x01>;
	dma-names = "rx", "rx-ctrl";
	status = "disabled";
	};

	usart2: serial@4000e000 {
	compatible = "st,stm32h7-uart";
	reg = <0x4000e000 0x400>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc USART2_K>;
	status = "disabled";
	};

	usart3: serial@4000f000 {
	compatible = "st,stm32h7-uart";
	reg = <0x4000f000 0x400>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc USART3_K>;
	status = "disabled";
	};

	uart4: serial@40010000 {
	compatible = "st,stm32h7-uart";
	reg = <0x40010000 0x400>;
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc UART4_K>;
	status = "disabled";
	};

	uart5: serial@40011000 {
	compatible = "st,stm32h7-uart";
	reg = <0x40011000 0x400>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc UART5_K>;
	status = "disabled";
	};

	i2c1: i2c@40012000 {
	compatible = "st,stm32f7-i2c";
	reg = <0x40012000 0x400>;
	interrupt-names = "event", "error";
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc I2C1_K>;
	resets = <&rcc I2C1_R>;
	#address-cells = <1>;
	#size-cells = <0>;
	+ wakeup-source;
	status = "disabled";
	};

	i2c2: i2c@40013000 {
	compatible = "st,stm32f7-i2c";
	reg = <0x40013000 0x400>;
	interrupt-names = "event", "error";
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc I2C2_K>;
	resets = <&rcc I2C2_R>;
	#address-cells = <1>;
	#size-cells = <0>;
	+ wakeup-source;
	status = "disabled";
	};

	i2c3: i2c@40014000 {
	compatible = "st,stm32f7-i2c";
	reg = <0x40014000 0x400>;
	interrupt-names = "event", "error";
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc I2C3_K>;
	resets = <&rcc I2C3_R>;
	#address-cells = <1>;
	#size-cells = <0>;
	+ wakeup-source;
	status = "disabled";
	};

	i2c5: i2c@40015000 {
	compatible = "st,stm32f7-i2c";
	reg = <0x40015000 0x400>;
	interrupt-names = "event", "error";
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc I2C5_K>;
	resets = <&rcc I2C5_R>;
	#address-cells = <1>;
	#size-cells = <0>;
	+ wakeup-source;
	status = "disabled";
	};

	cec: cec@40016000 {
	compatible = "st,stm32-cec";
	reg = <0x40016000 0x400>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc CEC_K>, <&clk_lse>;
	clock-names = "cec", "hdmi-cec";
	status = "disabled";
	};

	dac: dac@40017000 {
	compatible = "st,stm32h7-dac-core";
	reg = <0x40017000 0x400>;
	clocks = <&rcc DAC12>;
	clock-names = "pclk";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";

	dac1: dac@1 {
	compatible = "st,stm32-dac";
	#io-channels-cells = <1>;
	reg = <1>;
	status = "disabled";
	};

	dac2: dac@2 {
	compatible = "st,stm32-dac";
	#io-channels-cells = <1>;
	reg = <2>;
	status = "disabled";
	};
	};

	uart7: serial@40018000 {
	compatible = "st,stm32h7-uart";
	reg = <0x40018000 0x400>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc UART7_K>;
	status = "disabled";
	};

	uart8: serial@40019000 {
	compatible = "st,stm32h7-uart";
	reg = <0x40019000 0x400>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc UART8_K>;
	status = "disabled";
	};

	timers1: timer@44000000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32-timers";
	reg = <0x44000000 0x400>;
	clocks = <&rcc TIM1_K>;
	clock-names = "int";
	dmas = <&dmamux1 11 0x400 0x1>,
	<&dmamux1 12 0x400 0x1>,
	<&dmamux1 13 0x400 0x1>,
	<&dmamux1 14 0x400 0x1>,
	<&dmamux1 15 0x400 0x1>,
	<&dmamux1 16 0x400 0x1>,
	<&dmamux1 17 0x400 0x1>;
	dma-names = "ch1", "ch2", "ch3", "ch4",
	"up", "trig", "com";
	status = "disabled";

	pwm {
	compatible = "st,stm32-pwm";
	#pwm-cells = <3>;
	status = "disabled";
	};

	timer@0 {
	compatible = "st,stm32h7-timer-trigger";
	reg = <0>;
	status = "disabled";
	};

	counter {
	compatible = "st,stm32-timer-counter";
	status = "disabled";
	};
	};

	timers8: timer@44001000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32-timers";
	reg = <0x44001000 0x400>;
	clocks = <&rcc TIM8_K>;
	clock-names = "int";
	dmas = <&dmamux1 47 0x400 0x1>,
	<&dmamux1 48 0x400 0x1>,
	<&dmamux1 49 0x400 0x1>,
	<&dmamux1 50 0x400 0x1>,
	<&dmamux1 51 0x400 0x1>,
	<&dmamux1 52 0x400 0x1>,
	<&dmamux1 53 0x400 0x1>;
	dma-names = "ch1", "ch2", "ch3", "ch4",
	"up", "trig", "com";
	status = "disabled";

	pwm {
	compatible = "st,stm32-pwm";
	#pwm-cells = <3>;
	status = "disabled";
	};

	timer@7 {
	compatible = "st,stm32h7-timer-trigger";
	reg = <7>;
	status = "disabled";
	};

	counter {
	compatible = "st,stm32-timer-counter";
	status = "disabled";
	};
	};

	usart6: serial@44003000 {
	compatible = "st,stm32h7-uart";
	reg = <0x44003000 0x400>;
	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc USART6_K>;
	status = "disabled";
	};

	spi1: spi@44004000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32h7-spi";
	reg = <0x44004000 0x400>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc SPI1_K>;
	resets = <&rcc SPI1_R>;
	dmas = <&dmamux1 37 0x400 0x05>,
	<&dmamux1 38 0x400 0x05>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2s1: audio-controller@44004000 {
	compatible = "st,stm32h7-i2s";
	#sound-dai-cells = <0>;
	reg = <0x44004000 0x400>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&dmamux1 37 0x400 0x01>,
	<&dmamux1 38 0x400 0x01>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi4: spi@44005000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32h7-spi";
	reg = <0x44005000 0x400>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc SPI4_K>;
	resets = <&rcc SPI4_R>;
	dmas = <&dmamux1 83 0x400 0x05>,
	<&dmamux1 84 0x400 0x05>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	timers15: timer@44006000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32-timers";
	reg = <0x44006000 0x400>;
	clocks = <&rcc TIM15_K>;
	clock-names = "int";
	dmas = <&dmamux1 105 0x400 0x1>,
	<&dmamux1 106 0x400 0x1>,
	<&dmamux1 107 0x400 0x1>,
	<&dmamux1 108 0x400 0x1>;
	dma-names = "ch1", "up", "trig", "com";
	status = "disabled";

	pwm {
	compatible = "st,stm32-pwm";
	#pwm-cells = <3>;
	status = "disabled";
	};

	timer@14 {
	compatible = "st,stm32h7-timer-trigger";
	reg = <14>;
	status = "disabled";
	};
	};

	timers16: timer@44007000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32-timers";
	reg = <0x44007000 0x400>;
	clocks = <&rcc TIM16_K>;
	clock-names = "int";
	dmas = <&dmamux1 109 0x400 0x1>,
	<&dmamux1 110 0x400 0x1>;
	dma-names = "ch1", "up";
	status = "disabled";

	pwm {
	compatible = "st,stm32-pwm";
	#pwm-cells = <3>;
	status = "disabled";
	};
	timer@15 {
	compatible = "st,stm32h7-timer-trigger";
	reg = <15>;
	status = "disabled";
	};
	};

	timers17: timer@44008000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32-timers";
	reg = <0x44008000 0x400>;
	clocks = <&rcc TIM17_K>;
	clock-names = "int";
	dmas = <&dmamux1 111 0x400 0x1>,
	<&dmamux1 112 0x400 0x1>;
	dma-names = "ch1", "up";
	status = "disabled";

	pwm {
	compatible = "st,stm32-pwm";
	#pwm-cells = <3>;
	status = "disabled";
	};

	timer@16 {
	compatible = "st,stm32h7-timer-trigger";
	reg = <16>;
	status = "disabled";
	};
	};

	spi5: spi@44009000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32h7-spi";
	reg = <0x44009000 0x400>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc SPI5_K>;
	resets = <&rcc SPI5_R>;
	dmas = <&dmamux1 85 0x400 0x05>,
	<&dmamux1 86 0x400 0x05>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	sai1: sai@4400a000 {
	compatible = "st,stm32h7-sai";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x4400a000 0x400>;
	reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&rcc SAI1_R>;
	status = "disabled";

	sai1a: audio-controller@4400a004 {
	#sound-dai-cells = <0>;

	compatible = "st,stm32-sai-sub-a";
	reg = <0x4 0x1c>;
	clocks = <&rcc SAI1_K>;
	clock-names = "sai_ck";
	dmas = <&dmamux1 87 0x400 0x01>;
	status = "disabled";
	};

	sai1b: audio-controller@4400a024 {
	#sound-dai-cells = <0>;
	compatible = "st,stm32-sai-sub-b";
	reg = <0x24 0x1c>;
	clocks = <&rcc SAI1_K>;
	clock-names = "sai_ck";
	dmas = <&dmamux1 88 0x400 0x01>;
	status = "disabled";
	};
	};

	sai2: sai@4400b000 {
	compatible = "st,stm32h7-sai";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x4400b000 0x400>;
	reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&rcc SAI2_R>;
	status = "disabled";

	sai2a: audio-controller@4400b004 {
	#sound-dai-cells = <0>;
	compatible = "st,stm32-sai-sub-a";
	reg = <0x4 0x1c>;
	clocks = <&rcc SAI2_K>;
	clock-names = "sai_ck";
	dmas = <&dmamux1 89 0x400 0x01>;
	status = "disabled";
	};

	sai2b: audio-controller@4400b024 {
	#sound-dai-cells = <0>;
	compatible = "st,stm32-sai-sub-b";
	reg = <0x24 0x1c>;
	clocks = <&rcc SAI2_K>;
	clock-names = "sai_ck";
	dmas = <&dmamux1 90 0x400 0x01>;
	status = "disabled";
	};
	};

	sai3: sai@4400c000 {
	compatible = "st,stm32h7-sai";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x4400c000 0x400>;
	reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&rcc SAI3_R>;
	status = "disabled";

	sai3a: audio-controller@4400c004 {
	#sound-dai-cells = <0>;
	compatible = "st,stm32-sai-sub-a";
	reg = <0x04 0x1c>;
	clocks = <&rcc SAI3_K>;
	clock-names = "sai_ck";
	dmas = <&dmamux1 113 0x400 0x01>;
	status = "disabled";
	};

	sai3b: audio-controller@4400c024 {
	#sound-dai-cells = <0>;
	compatible = "st,stm32-sai-sub-b";
	reg = <0x24 0x1c>;
	clocks = <&rcc SAI3_K>;
	clock-names = "sai_ck";
	dmas = <&dmamux1 114 0x400 0x01>;
	status = "disabled";
	};
	};

	dfsdm: dfsdm@4400d000 {
	compatible = "st,stm32mp1-dfsdm";
	reg = <0x4400d000 0x800>;
	clocks = <&rcc DFSDM_K>;
	clock-names = "dfsdm";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";

	dfsdm0: filter@0 {
	compatible = "st,stm32-dfsdm-adc";
	#io-channel-cells = <1>;
	reg = <0>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&dmamux1 101 0x400 0x01>;
	dma-names = "rx";
	status = "disabled";
	};

	dfsdm1: filter@1 {
	compatible = "st,stm32-dfsdm-adc";
	#io-channel-cells = <1>;
	reg = <1>;
	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&dmamux1 102 0x400 0x01>;
	dma-names = "rx";
	status = "disabled";
	};

	dfsdm2: filter@2 {
	compatible = "st,stm32-dfsdm-adc";
	#io-channel-cells = <1>;
	reg = <2>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&dmamux1 103 0x400 0x01>;
	dma-names = "rx";
	status = "disabled";
	};

	dfsdm3: filter@3 {
	compatible = "st,stm32-dfsdm-adc";
	#io-channel-cells = <1>;
	reg = <3>;
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&dmamux1 104 0x400 0x01>;
	dma-names = "rx";
	status = "disabled";
	};

	dfsdm4: filter@4 {
	compatible = "st,stm32-dfsdm-adc";
	#io-channel-cells = <1>;
	reg = <4>;
	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&dmamux1 91 0x400 0x01>;
	dma-names = "rx";
	status = "disabled";
	};

	dfsdm5: filter@5 {
	compatible = "st,stm32-dfsdm-adc";
	#io-channel-cells = <1>;
	reg = <5>;
	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&dmamux1 92 0x400 0x01>;
	dma-names = "rx";
	status = "disabled";
	};
	};

	dma1: dma-controller@48000000 {
	compatible = "st,stm32-dma";
	reg = <0x48000000 0x400>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc DMA1>;
	+ resets = <&rcc DMA1_R>;
	#dma-cells = <4>;
	st,mem2mem;
	dma-requests = <8>;
	};

	dma2: dma-controller@48001000 {
	compatible = "st,stm32-dma";
	reg = <0x48001000 0x400>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc DMA2>;
	+ resets = <&rcc DMA2_R>;
	#dma-cells = <4>;
	st,mem2mem;
	dma-requests = <8>;
	};

	dmamux1: dma-router@48002000 {
	compatible = "st,stm32h7-dmamux";
	reg = <0x48002000 0x1c>;
	#dma-cells = <3>;
	dma-requests = <128>;
	dma-masters = <&dma1 &dma2>;
	dma-channels = <16>;
	clocks = <&rcc DMAMUX>;
	+ resets = <&rcc DMAMUX_R>;
	};

	adc: adc@48003000 {
	compatible = "st,stm32mp1-adc-core";
	reg = <0x48003000 0x400>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc ADC12>, <&rcc ADC12_K>;
	clock-names = "bus", "adc";
	interrupt-controller;
	st,syscfg = <&syscfg>;
	#interrupt-cells = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";

	adc1: adc@0 {
	compatible = "st,stm32mp1-adc";
	#io-channel-cells = <1>;
	reg = <0x0>;
	interrupt-parent = <&adc>;
	interrupts = <0>;
	dmas = <&dmamux1 9 0x400 0x01>;
	dma-names = "rx";
	status = "disabled";
	};

	adc2: adc@100 {
	compatible = "st,stm32mp1-adc";
	#io-channel-cells = <1>;
	reg = <0x100>;
	interrupt-parent = <&adc>;
	interrupts = <1>;
	dmas = <&dmamux1 10 0x400 0x01>;
	dma-names = "rx";
	status = "disabled";
	};
	};

	sdmmc3: sdmmc@48004000 {
	compatible = "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x10153180>;
	reg = <0x48004000 0x400>;
	interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&rcc SDMMC3_K>;
	clock-names = "apb_pclk";
	resets = <&rcc SDMMC3_R>;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	max-frequency = <120000000>;
	status = "disabled";
	};

	usbotg_hs: usb-otg@49000000 {
	- compatible = "snps,dwc2";
	+ compatible = "st,stm32mp15-hsotg", "snps,dwc2";
	reg = <0x49000000 0x10000>;
	clocks = <&rcc USBO_K>;
	clock-names = "otg";
	resets = <&rcc USBO_R>;
	reset-names = "dwc2";
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	g-rx-fifo-size = <256>;
	g-np-tx-fifo-size = <32>;
	g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
	dr_mode = "otg";
	+ usb33d-supply = <&usb33>;
	status = "disabled";
	};

	ipcc: mailbox@4c001000 {
	compatible = "st,stm32mp1-ipcc";
	#mbox-cells = <1>;
	reg = <0x4c001000 0x400>;
	st,proc-id = <0>;
	interrupts-extended =
	<&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
	<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
	<&exti 61 1>;
	interrupt-names = "rx", "tx", "wakeup";
	clocks = <&rcc IPCC>;
	wakeup-source;
	status = "disabled";
	};

	dcmi: dcmi@4c006000 {
	compatible = "st,stm32-dcmi";
	reg = <0x4c006000 0x400>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&rcc CAMITF_R>;
	clocks = <&rcc DCMI>;
	clock-names = "mclk";
	dmas = <&dmamux1 75 0x400 0x0d>;
	dma-names = "tx";
	status = "disabled";
	};

	rcc: rcc@50000000 {
	compatible = "st,stm32mp1-rcc", "syscon";
	reg = <0x50000000 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pwr_regulators: pwr@50001000 {
	compatible = "st,stm32mp1,pwr-reg";
	reg = <0x50001000 0x10>;

	reg11: reg11 {
	regulator-name = "reg11";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	};

	reg18: reg18 {
	regulator-name = "reg18";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	usb33: usb33 {
	regulator-name = "usb33";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};
	};

	exti: interrupt-controller@5000d000 {
	compatible = "st,stm32mp1-exti", "syscon";
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x5000d000 0x400>;
	};

	syscfg: syscon@50020000 {
	compatible = "st,stm32mp157-syscfg", "syscon";
	reg = <0x50020000 0x400>;
	clocks = <&rcc SYSCFG>;
	};

	lptimer2: timer@50021000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32-lptimer";
	reg = <0x50021000 0x400>;
	clocks = <&rcc LPTIM2_K>;
	clock-names = "mux";
	status = "disabled";

	pwm {
	compatible = "st,stm32-pwm-lp";
	#pwm-cells = <3>;
	status = "disabled";
	};

	trigger@1 {
	compatible = "st,stm32-lptimer-trigger";
	reg = <1>;
	status = "disabled";
	};

	counter {
	compatible = "st,stm32-lptimer-counter";
	status = "disabled";
	};
	};

	lptimer3: timer@50022000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32-lptimer";
	reg = <0x50022000 0x400>;
	clocks = <&rcc LPTIM3_K>;
	clock-names = "mux";
	status = "disabled";

	pwm {
	compatible = "st,stm32-pwm-lp";
	#pwm-cells = <3>;
	status = "disabled";
	};

	trigger@2 {
	compatible = "st,stm32-lptimer-trigger";
	reg = <2>;
	status = "disabled";
	};
	};

	lptimer4: timer@50023000 {
	compatible = "st,stm32-lptimer";
	reg = <0x50023000 0x400>;
	clocks = <&rcc LPTIM4_K>;
	clock-names = "mux";
	status = "disabled";

	pwm {
	compatible = "st,stm32-pwm-lp";
	#pwm-cells = <3>;
	status = "disabled";
	};
	};

	lptimer5: timer@50024000 {
	compatible = "st,stm32-lptimer";
	reg = <0x50024000 0x400>;
	clocks = <&rcc LPTIM5_K>;
	clock-names = "mux";
	status = "disabled";

	pwm {
	compatible = "st,stm32-pwm-lp";
	#pwm-cells = <3>;
	status = "disabled";
	};
	};

	vrefbuf: vrefbuf@50025000 {
	compatible = "st,stm32-vrefbuf";
	reg = <0x50025000 0x8>;
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <2500000>;
	clocks = <&rcc VREF>;
	status = "disabled";
	};

	sai4: sai@50027000 {
	compatible = "st,stm32h7-sai";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x50027000 0x400>;
	reg = <0x50027000 0x4>, <0x500273f0 0x10>;
	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&rcc SAI4_R>;
	status = "disabled";

	sai4a: audio-controller@50027004 {
	#sound-dai-cells = <0>;
	compatible = "st,stm32-sai-sub-a";
	reg = <0x04 0x1c>;
	clocks = <&rcc SAI4_K>;
	clock-names = "sai_ck";
	dmas = <&dmamux1 99 0x400 0x01>;
	status = "disabled";
	};

	sai4b: audio-controller@50027024 {
	#sound-dai-cells = <0>;
	compatible = "st,stm32-sai-sub-b";
	reg = <0x24 0x1c>;
	clocks = <&rcc SAI4_K>;
	clock-names = "sai_ck";
	dmas = <&dmamux1 100 0x400 0x01>;
	status = "disabled";
	};
	};

	dts: thermal@50028000 {
	compatible = "st,stm32-thermal";
	reg = <0x50028000 0x100>;
	interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc TMPSENS>;
	clock-names = "pclk";
	#thermal-sensor-cells = <0>;
	status = "disabled";
	};

	hash1: hash@54002000 {
	compatible = "st,stm32f756-hash";
	reg = <0x54002000 0x400>;
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc HASH1>;
	resets = <&rcc HASH1_R>;
	dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
	dma-names = "in";
	dma-maxburst = <2>;
	status = "disabled";
	};

	rng1: rng@54003000 {
	compatible = "st,stm32-rng";
	reg = <0x54003000 0x400>;
	clocks = <&rcc RNG1_K>;
	resets = <&rcc RNG1_R>;
	status = "disabled";
	};

	mdma1: dma-controller@58000000 {
	compatible = "st,stm32h7-mdma";
	reg = <0x58000000 0x1000>;
	interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc MDMA>;
	+ resets = <&rcc MDMA_R>;
	#dma-cells = <5>;
	dma-channels = <32>;
	dma-requests = <48>;
	};

	fmc: nand-controller@58002000 {
	compatible = "st,stm32mp15-fmc2";
	reg = <0x58002000 0x1000>,
	<0x80000000 0x1000>,
	<0x88010000 0x1000>,
	<0x88020000 0x1000>,
	<0x81000000 0x1000>,
	<0x89010000 0x1000>,
	<0x89020000 0x1000>;
	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
	<&mdma1 20 0x10 0x12000a08 0x0 0x0>,
	<&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
	dma-names = "tx", "rx", "ecc";
	clocks = <&rcc FMC_K>;
	resets = <&rcc FMC_R>;
	status = "disabled";
	};

	qspi: spi@58003000 {
	compatible = "st,stm32f469-qspi";
	reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
	reg-names = "qspi", "qspi_mm";
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
	<&mdma1 22 0x10 0x100008 0x0 0x0>;
	dma-names = "tx", "rx";
	clocks = <&rcc QSPI_K>;
	resets = <&rcc QSPI_R>;
	status = "disabled";
	};

	sdmmc1: sdmmc@58005000 {
	compatible = "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x10153180>;
	reg = <0x58005000 0x1000>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&rcc SDMMC1_K>;
	clock-names = "apb_pclk";
	resets = <&rcc SDMMC1_R>;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	max-frequency = <120000000>;
	status = "disabled";
	};

	sdmmc2: sdmmc@58007000 {
	compatible = "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x10153180>;
	reg = <0x58007000 0x1000>;
	interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&rcc SDMMC2_K>;
	clock-names = "apb_pclk";
	resets = <&rcc SDMMC2_R>;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	max-frequency = <120000000>;
	status = "disabled";
	};

	crc1: crc@58009000 {
	compatible = "st,stm32f7-crc";
	reg = <0x58009000 0x400>;
	clocks = <&rcc CRC1>;
	status = "disabled";
	};

	stmmac_axi_config_0: stmmac-axi-config {
	snps,wr_osr_lmt = <0x7>;
	snps,rd_osr_lmt = <0x7>;
	snps,blen = <0 0 0 0 16 8 4>;
	};

	ethernet0: ethernet@5800a000 {
	compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
	reg = <0x5800a000 0x2000>;
	reg-names = "stmmaceth";
	interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	clock-names = "stmmaceth",
	"mac-clk-tx",
	"mac-clk-rx",
	+ "eth-ck",
	"ethstp";
	clocks = <&rcc ETHMAC>,
	<&rcc ETHTX>,
	<&rcc ETHRX>,
	+ <&rcc ETHCK_K>,
	<&rcc ETHSTP>;
	st,syscon = <&syscfg 0x4>;
	snps,mixed-burst;
	snps,pbl = <2>;
	snps,en-tx-lpi-clockgating;
	snps,axi-config = <&stmmac_axi_config_0>;
	snps,tso;
	status = "disabled";
	};

	usbh_ohci: usbh-ohci@5800c000 {
	compatible = "generic-ohci";
	reg = <0x5800c000 0x1000>;
	clocks = <&rcc USBH>;
	resets = <&rcc USBH_R>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	usbh_ehci: usbh-ehci@5800d000 {
	compatible = "generic-ehci";
	reg = <0x5800d000 0x1000>;
	clocks = <&rcc USBH>;
	resets = <&rcc USBH_R>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	companion = <&usbh_ohci>;
	status = "disabled";
	};

	ltdc: display-controller@5a001000 {
	compatible = "st,stm32-ltdc";
	reg = <0x5a001000 0x400>;
	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc LTDC_PX>;
	clock-names = "lcd";
	resets = <&rcc LTDC_R>;
	status = "disabled";
	};

	iwdg2: watchdog@5a002000 {
	compatible = "st,stm32mp1-iwdg";
	reg = <0x5a002000 0x400>;
	clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
	clock-names = "pclk", "lsi";
	status = "disabled";
	};

	usbphyc: usbphyc@5a006000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32mp1-usbphyc";
	reg = <0x5a006000 0x1000>;
	clocks = <&rcc USBPHY_K>;
	resets = <&rcc USBPHY_R>;
	status = "disabled";

	usbphyc_port0: usb-phy@0 {
	#phy-cells = <0>;
	reg = <0>;
	};

	usbphyc_port1: usb-phy@1 {
	#phy-cells = <1>;
	reg = <1>;
	};
	};

	usart1: serial@5c000000 {
	compatible = "st,stm32h7-uart";
	reg = <0x5c000000 0x400>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc USART1_K>;
	status = "disabled";
	};

	spi6: spi@5c001000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "st,stm32h7-spi";
	reg = <0x5c001000 0x400>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc SPI6_K>;
	resets = <&rcc SPI6_R>;
	dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
	<&mdma1 35 0x0 0x40002 0x0 0x0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c4: i2c@5c002000 {
	compatible = "st,stm32f7-i2c";
	reg = <0x5c002000 0x400>;
	interrupt-names = "event", "error";
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc I2C4_K>;
	resets = <&rcc I2C4_R>;
	#address-cells = <1>;
	#size-cells = <0>;
	+ wakeup-source;
	status = "disabled";
	};

	rtc: rtc@5c004000 {
	compatible = "st,stm32mp1-rtc";
	reg = <0x5c004000 0x400>;
	clocks = <&rcc RTCAPB>, <&rcc RTC>;
	clock-names = "pclk", "rtc_ck";
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	bsec: efuse@5c005000 {
	compatible = "st,stm32mp15-bsec";
	reg = <0x5c005000 0x400>;
	#address-cells = <1>;
	#size-cells = <1>;
	ts_cal1: calib@5c {
	reg = <0x5c 0x2>;
	};
	ts_cal2: calib@5e {
	reg = <0x5e 0x2>;
	};
	};

	i2c6: i2c@5c009000 {
	compatible = "st,stm32f7-i2c";
	reg = <0x5c009000 0x400>;
	interrupt-names = "event", "error";
	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&rcc I2C6_K>;
	resets = <&rcc I2C6_R>;
	#address-cells = <1>;
	#size-cells = <0>;
	+ wakeup-source;
	status = "disabled";
	};

	/*
	* Break node order to solve dependency probe issue between
	* pinctrl and exti.
	*/
	pinctrl: pin-controller@50002000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "st,stm32mp157-pinctrl";
	ranges = <0 0x50002000 0xa400>;
	interrupt-parent = <&exti>;
	st,syscfg = <&exti 0x60 0xff>;
	pins-are-numbered;

	gpioa: gpio@50002000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x0 0x400>;
	clocks = <&rcc GPIOA>;
	st,bank-name = "GPIOA";
	status = "disabled";
	};

	gpiob: gpio@50003000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x1000 0x400>;
	clocks = <&rcc GPIOB>;
	st,bank-name = "GPIOB";
	status = "disabled";
	};

	gpioc: gpio@50004000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x2000 0x400>;
	clocks = <&rcc GPIOC>;
	st,bank-name = "GPIOC";
	status = "disabled";
	};

	gpiod: gpio@50005000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x3000 0x400>;
	clocks = <&rcc GPIOD>;
	st,bank-name = "GPIOD";
	status = "disabled";
	};

	gpioe: gpio@50006000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x4000 0x400>;
	clocks = <&rcc GPIOE>;
	st,bank-name = "GPIOE";
	status = "disabled";
	};

	gpiof: gpio@50007000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x5000 0x400>;
	clocks = <&rcc GPIOF>;
	st,bank-name = "GPIOF";
	status = "disabled";
	};

	gpiog: gpio@50008000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x6000 0x400>;
	clocks = <&rcc GPIOG>;
	st,bank-name = "GPIOG";
	status = "disabled";
	};

	gpioh: gpio@50009000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x7000 0x400>;
	clocks = <&rcc GPIOH>;
	st,bank-name = "GPIOH";
	status = "disabled";
	};

	gpioi: gpio@5000a000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x8000 0x400>;
	clocks = <&rcc GPIOI>;
	st,bank-name = "GPIOI";
	status = "disabled";
	};

	gpioj: gpio@5000b000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x9000 0x400>;
	clocks = <&rcc GPIOJ>;
	st,bank-name = "GPIOJ";
	status = "disabled";
	};

	gpiok: gpio@5000c000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0xa000 0x400>;
	clocks = <&rcc GPIOK>;
	st,bank-name = "GPIOK";
	status = "disabled";
	};
	};

	pinctrl_z: pin-controller-z@54004000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "st,stm32mp157-z-pinctrl";
	ranges = <0 0x54004000 0x400>;
	pins-are-numbered;
	interrupt-parent = <&exti>;
	st,syscfg = <&exti 0x60 0xff>;

	gpioz: gpio@54004000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0 0x400>;
	clocks = <&rcc GPIOZ>;
	st,bank-name = "GPIOZ";
	st,bank-ioport = <11>;
	status = "disabled";
	};
	};
	};

	mlahb: ahb {
	compatible = "st,mlahb", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	dma-ranges = <0x00000000 0x38000000 0x10000>,
	<0x10000000 0x10000000 0x60000>,
	<0x30000000 0x30000000 0x60000>;

	m4_rproc: m4@10000000 {
	compatible = "st,stm32mp1-m4";
	reg = <0x10000000 0x40000>,
	<0x30000000 0x40000>,
	<0x38000000 0x10000>;
	resets = <&rcc MCU_R>;
	st,syscfg-holdboot = <&rcc 0x10C 0x1>;
	st,syscfg-tz = <&rcc 0x000 0x1>;
	status = "disabled";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/stm32mp153.dtsi b/sys/gnu/dts/arm/stm32mp153.dtsi
	index 2d759fc6015c..6d9ab08667fc 100644
	--- a/sys/gnu/dts/arm/stm32mp153.dtsi
	+++ b/sys/gnu/dts/arm/stm32mp153.dtsi
	@@ -1,45 +1,46 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
	/*
	* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
	* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
	*/

	#include "stm32mp151.dtsi"

	/ {
	cpus {
	cpu1: cpu@1 {
	compatible = "arm,cortex-a7";
	+ clock-frequency = <650000000>;
	device_type = "cpu";
	reg = <1>;
	};
	};

	soc {
	m_can1: can@4400e000 {
	compatible = "bosch,m_can";
	reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
	reg-names = "m_can", "message_ram";
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "int0", "int1";
	clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
	clock-names = "hclk", "cclk";
	bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
	status = "disabled";
	};

	m_can2: can@4400f000 {
	compatible = "bosch,m_can";
	reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
	reg-names = "m_can", "message_ram";
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "int0", "int1";
	clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
	clock-names = "hclk", "cclk";
	bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
	status = "disabled";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/stm32mp157a-avenger96.dts b/sys/gnu/dts/arm/stm32mp157a-avenger96.dts
	index cbfa4075907e..425175f7d83c 100644
	--- a/sys/gnu/dts/arm/stm32mp157a-avenger96.dts
	+++ b/sys/gnu/dts/arm/stm32mp157a-avenger96.dts
	@@ -1,326 +1,319 @@
	// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
	/*
	* Copyright (C) Linaro Ltd 2019 - All Rights Reserved
	* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
	*/

	/dts-v1/;

	#include "stm32mp157.dtsi"
	#include "stm32mp15-pinctrl.dtsi"
	#include "stm32mp15xxac-pinctrl.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/mfd/st,stpmic1.h>

	/ {
	model = "Arrow Electronics STM32MP157A Avenger96 board";
	compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";

	aliases {
	ethernet0 = &ethernet0;
	mmc0 = &sdmmc1;
	serial0 = &uart4;
	serial1 = &uart7;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@c0000000 {
	device_type = "memory";
	reg = <0xc0000000 0x40000000>;
	};

	led {
	compatible = "gpio-leds";
	led1 {
	label = "green:user1";
	gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	default-state = "off";
	};

	led2 {
	label = "green:user2";
	gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "mmc0";
	default-state = "off";
	};

	led3 {
	label = "green:user3";
	gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "mmc1";
	default-state = "off";
	};

	led4 {
	label = "green:user3";
	gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "none";
	default-state = "off";
	panic-indicator;
	};

	led5 {
	label = "yellow:wifi";
	gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "phy0tx";
	default-state = "off";
	};

	led6 {
	label = "blue:bt";
	gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "bluetooth-power";
	default-state = "off";
	};
	};
	};

	&ethernet0 {
	status = "okay";
	pinctrl-0 = <&ethernet0_rgmii_pins_a>;
	pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
	pinctrl-names = "default", "sleep";
	phy-mode = "rgmii";
	max-speed = <1000>;
	phy-handle = <&phy0>;

	mdio0 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,dwmac-mdio";
	phy0: ethernet-phy@7 {
	reg = <7>;
	};
	};
	};

	&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins_b>;
	i2c-scl-rising-time-ns = <185>;
	i2c-scl-falling-time-ns = <20>;
	status = "okay";
	/delete-property/dmas;
	/delete-property/dma-names;
	};

	&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>;
	i2c-scl-rising-time-ns = <185>;
	i2c-scl-falling-time-ns = <20>;
	status = "okay";
	/delete-property/dmas;
	/delete-property/dma-names;
	};

	&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins_a>;
	i2c-scl-rising-time-ns = <185>;
	i2c-scl-falling-time-ns = <20>;
	status = "okay";
	/delete-property/dmas;
	/delete-property/dma-names;

	pmic: stpmic@33 {
	compatible = "st,stpmic1";
	reg = <0x33>;
	interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>;
	interrupt-controller;
	#interrupt-cells = <2>;
	status = "okay";

	- st,main-control-register = <0x04>;
	- st,vin-control-register = <0xc0>;
	- st,usb-control-register = <0x30>;
	-
	regulators {
	compatible = "st,stpmic1-regulators";

	ldo1-supply = <&v3v3>;
	ldo2-supply = <&v3v3>;
	ldo3-supply = <&vdd_ddr>;
	ldo5-supply = <&v3v3>;
	ldo6-supply = <&v3v3>;
	pwr_sw1-supply = <&bst_out>;
	pwr_sw2-supply = <&bst_out>;

	vddcore: buck1 {
	regulator-name = "vddcore";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-initial-mode = <0>;
	regulator-over-current-protection;
	};

	vdd_ddr: buck2 {
	regulator-name = "vdd_ddr";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-initial-mode = <0>;
	regulator-over-current-protection;
	};

	vdd: buck3 {
	regulator-name = "vdd";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	- st,mask_reset;
	regulator-initial-mode = <0>;
	regulator-over-current-protection;
	};

	v3v3: buck4 {
	regulator-name = "v3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-over-current-protection;
	regulator-initial-mode = <0>;
	};

	vdda: ldo1 {
	regulator-name = "vdda";
	regulator-min-microvolt = <2900000>;
	regulator-max-microvolt = <2900000>;
	interrupts = <IT_CURLIM_LDO1 0>;
	interrupt-parent = <&pmic>;
	};

	v2v8: ldo2 {
	regulator-name = "v2v8";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	interrupts = <IT_CURLIM_LDO2 0>;
	interrupt-parent = <&pmic>;
	};

	vtt_ddr: ldo3 {
	regulator-name = "vtt_ddr";
	regulator-min-microvolt = <500000>;
	regulator-max-microvolt = <750000>;
	regulator-always-on;
	regulator-over-current-protection;
	};

	vdd_usb: ldo4 {
	regulator-name = "vdd_usb";
	- regulator-min-microvolt = <3300000>;
	- regulator-max-microvolt = <3300000>;
	interrupts = <IT_CURLIM_LDO4 0>;
	interrupt-parent = <&pmic>;
	};

	vdd_sd: ldo5 {
	regulator-name = "vdd_sd";
	regulator-min-microvolt = <2900000>;
	regulator-max-microvolt = <2900000>;
	interrupts = <IT_CURLIM_LDO5 0>;
	interrupt-parent = <&pmic>;
	regulator-boot-on;
	};

	v1v8: ldo6 {
	regulator-name = "v1v8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	interrupts = <IT_CURLIM_LDO6 0>;
	interrupt-parent = <&pmic>;
	regulator-enable-ramp-delay = <300000>;
	};

	vref_ddr: vref_ddr {
	regulator-name = "vref_ddr";
	regulator-always-on;
	- regulator-over-current-protection;
	};

	bst_out: boost {
	regulator-name = "bst_out";
	interrupts = <IT_OCP_BOOST 0>;
	interrupt-parent = <&pmic>;
	};

	vbus_otg: pwr_sw1 {
	regulator-name = "vbus_otg";
	interrupts = <IT_OCP_OTG 0>;
	interrupt-parent = <&pmic>;
	};

	vbus_sw: pwr_sw2 {
	regulator-name = "vbus_sw";
	interrupts = <IT_OCP_SWOUT 0>;
	interrupt-parent = <&pmic>;
	regulator-active-discharge = <1>;
	};
	};

	onkey {
	compatible = "st,stpmic1-onkey";
	interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
	interrupt-names = "onkey-falling", "onkey-rising";
	status = "okay";
	};

	watchdog {
	compatible = "st,stpmic1-wdt";
	status = "disabled";
	};
	};
	};

	&iwdg2 {
	timeout-sec = <32>;
	status = "okay";
	};

	&pwr_regulators {
	vdd-supply = <&vdd>;
	vdd_3v3_usbfs-supply = <&vdd_usb>;
	};

	&rng1 {
	status = "okay";
	};

	&rtc {
	status = "okay";
	};

	&sdmmc1 {
	pinctrl-names = "default", "opendrain", "sleep";
	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
	pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
	- broken-cd;
	+ cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW \| GPIO_PULL_UP)>;
	+ disable-wp;
	st,sig-dir;
	st,neg-edge;
	st,use-ckin;
	bus-width = <4>;
	vmmc-supply = <&vdd_sd>;
	status = "okay";
	};

	&uart4 {
	/* On Low speed expansion header */
	label = "LS-UART1";
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_pins_b>;
	status = "okay";
	};

	&uart7 {
	/* On Low speed expansion header */
	label = "LS-UART0";
	pinctrl-names = "default";
	pinctrl-0 = <&uart7_pins_a>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/stm32mp157c-dhcom-pdk2.dts b/sys/gnu/dts/arm/stm32mp157c-dhcom-pdk2.dts
	new file mode 100644
	index 000000000000..af99e132e1b1
	--- /dev/null
	+++ b/sys/gnu/dts/arm/stm32mp157c-dhcom-pdk2.dts
	@@ -0,0 +1,265 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
	+/*
	+ * Copyright (C) 2019 Marek Vasut <marex@denx.de>
	+ */
	+
	+#include "stm32mp157c-dhcom-som.dtsi"
	+#include <dt-bindings/pwm/pwm.h>
	+
	+/ {
	+ model = "STMicroelectronics STM32MP157C DHCOM Premium Developer Kit (2)";
	+ compatible = "dh,stm32mp157c-dhcom-pdk2", "st,stm32mp157";
	+
	+ aliases {
	+ serial0 = &uart4;
	+ serial1 = &usart3;
	+ serial2 = &uart8;
	+ ethernet0 = &ethernet0;
	+ };
	+
	+ chosen {
	+ stdout-path = "serial0:115200n8";
	+ };
	+
	+ clk_ext_audio_codec: clock-codec {
	+ compatible = "fixed-clock";
	+ #clock-cells = <0>;
	+ clock-frequency = <24000000>;
	+ };
	+
	+ display_bl: display-bl {
	+ compatible = "pwm-backlight";
	+ pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
	+ brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
	+ default-brightness-level = <8>;
	+ enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>;
	+ status = "okay";
	+ };
	+
	+ ethernet_vio: vioregulator {
	+ compatible = "regulator-fixed";
	+ regulator-name = "vio";
	+ regulator-min-microvolt = <3300000>;
	+ regulator-max-microvolt = <3300000>;
	+ gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
	+ regulator-always-on;
	+ regulator-boot-on;
	+ };
	+
	+ panel {
	+ compatible = "edt,etm0700g0edh6";
	+ backlight = <&display_bl>;
	+
	+ port {
	+ lcd_panel_in: endpoint {
	+ remote-endpoint = <&lcd_display_out>;
	+ };
	+ };
	+ };
	+
	+ sound {
	+ compatible = "audio-graph-card";
	+ routing =
	+ "MIC_IN", "Capture",
	+ "Capture", "Mic Bias",
	+ "Playback", "HP_OUT";
	+ dais = <&sai2a_port &sai2b_port>;
	+ status = "okay";
	+ };
	+};
	+
	+&cec {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&cec_pins_a>;
	+ status = "okay";
	+};
	+
	+&ethernet0 {
	+ status = "okay";
	+ pinctrl-0 = <&ethernet0_rmii_pins_a>;
	+ pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
	+ pinctrl-names = "default", "sleep";
	+ phy-mode = "rmii";
	+ max-speed = <100>;
	+ phy-handle = <&phy0>;
	+ st,eth-ref-clk-sel;
	+ phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
	+
	+ mdio0 {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ compatible = "snps,dwmac-mdio";
	+
	+ phy0: ethernet-phy@1 {
	+ reg = <1>;
	+ };
	+ };
	+};
	+
	+&i2c5 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&i2c5_pins_a>;
	+ i2c-scl-rising-time-ns = <185>;
	+ i2c-scl-falling-time-ns = <20>;
	+ status = "okay";
	+ /* spare dmas for other usage */
	+ /delete-property/dmas;
	+ /delete-property/dma-names;
	+
	+ sgtl5000: codec@a {
	+ compatible = "fsl,sgtl5000";
	+ reg = <0x0a>;
	+ #sound-dai-cells = <0>;
	+ clocks = <&clk_ext_audio_codec>;
	+ VDDA-supply = <&v3v3>;
	+ VDDIO-supply = <&vdd>;
	+
	+ sgtl5000_port: port {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ sgtl5000_tx_endpoint: endpoint@0 {
	+ reg = <0>;
	+ remote-endpoint = <&sai2a_endpoint>;
	+ frame-master;
	+ bitclock-master;
	+ };
	+
	+ sgtl5000_rx_endpoint: endpoint@1 {
	+ reg = <1>;
	+ remote-endpoint = <&sai2b_endpoint>;
	+ frame-master;
	+ bitclock-master;
	+ };
	+ };
	+
	+ };
	+
	+ polytouch@38 {
	+ compatible = "edt,edt-ft5x06";
	+ reg = <0x38>;
	+ interrupt-parent = <&gpiog>;
	+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
	+ linux,wakeup;
	+ };
	+};
	+
	+&ltdc {
	+ pinctrl-names = "default", "sleep";
	+ pinctrl-0 = <&ltdc_pins_b>;
	+ pinctrl-1 = <&ltdc_pins_sleep_b>;
	+ status = "okay";
	+
	+ port {
	+ lcd_display_out: endpoint {
	+ remote-endpoint = <&lcd_panel_in>;
	+ };
	+ };
	+};
	+
	+&m_can1 {
	+ pinctrl-names = "default", "sleep";
	+ pinctrl-0 = <&m_can1_pins_a>;
	+ pinctrl-1 = <&m_can1_sleep_pins_a>;
	+ status = "okay";
	+};
	+
	+&sai2 {
	+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
	+ clock-names = "pclk", "x8k", "x11k";
	+ pinctrl-names = "default", "sleep";
	+ pinctrl-0 = <&sai2a_pins_b &sai2b_pins_b>;
	+ pinctrl-1 = <&sai2a_sleep_pins_b &sai2b_sleep_pins_b>;
	+ status = "okay";
	+
	+ sai2a: audio-controller@4400b004 {
	+ #clock-cells = <0>;
	+ dma-names = "tx";
	+ clocks = <&rcc SAI2_K>;
	+ clock-names = "sai_ck";
	+ status = "okay";
	+
	+ sai2a_port: port {
	+ sai2a_endpoint: endpoint {
	+ remote-endpoint = <&sgtl5000_tx_endpoint>;
	+ format = "i2s";
	+ mclk-fs = <512>;
	+ dai-tdm-slot-num = <2>;
	+ dai-tdm-slot-width = <16>;
	+ };
	+ };
	+ };
	+
	+ sai2b: audio-controller@4400b024 {
	+ dma-names = "rx";
	+ st,sync = <&sai2a 2>;
	+ clocks = <&rcc SAI2_K>, <&sai2a>;
	+ clock-names = "sai_ck", "MCLK";
	+ status = "okay";
	+
	+ sai2b_port: port {
	+ sai2b_endpoint: endpoint {
	+ remote-endpoint = <&sgtl5000_rx_endpoint>;
	+ format = "i2s";
	+ mclk-fs = <512>;
	+ dai-tdm-slot-num = <2>;
	+ dai-tdm-slot-width = <16>;
	+ };
	+ };
	+ };
	+};
	+
	+&timers2 {
	+ /* spare dmas for other usage (un-delete to enable pwm capture) */
	+ /delete-property/dmas;
	+ /delete-property/dma-names;
	+ status = "okay";
	+ pwm2: pwm {
	+ pinctrl-0 = <&pwm2_pins_a>;
	+ pinctrl-names = "default";
	+ status = "okay";
	+ };
	+ timer@1 {
	+ status = "okay";
	+ };
	+};
	+
	+&usart3 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&usart3_pins_a>;
	+ status = "okay";
	+};
	+
	+&uart8 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&uart8_pins_a>;
	+ status = "okay";
	+};
	+
	+&usbh_ehci {
	+ phys = <&usbphyc_port0>;
	+ status = "okay";
	+};
	+
	+&usbotg_hs {
	+ dr_mode = "peripheral";
	+ phys = <&usbphyc_port1 0>;
	+ phy-names = "usb2-phy";
	+ status = "okay";
	+};
	+
	+&usbphyc {
	+ status = "okay";
	+};
	+
	+&usbphyc_port0 {
	+ phy-supply = <&vdd_usb>;
	+ vdda1v1-supply = <&reg11>;
	+ vdda1v8-supply = <&reg18>;
	+};
	+
	+&usbphyc_port1 {
	+ phy-supply = <&vdd_usb>;
	+ vdda1v1-supply = <&reg11>;
	+ vdda1v8-supply = <&reg18>;
	+};
	diff --git a/sys/gnu/dts/arm/stm32mp157c-ed1.dts b/sys/gnu/dts/arm/stm32mp157c-dhcom-som.dtsi
	similarity index 80%
	copy from sys/gnu/dts/arm/stm32mp157c-ed1.dts
	copy to sys/gnu/dts/arm/stm32mp157c-dhcom-som.dtsi
	index 1fc43251d697..f81dc3134135 100644
	--- a/sys/gnu/dts/arm/stm32mp157c-ed1.dts
	+++ b/sys/gnu/dts/arm/stm32mp157c-dhcom-som.dtsi
	@@ -1,368 +1,368 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
	/*
	- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
	- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
	+ * Copyright (C) 2019 Marek Vasut <marex@denx.de>
	*/
	/dts-v1/;

	#include "stm32mp157.dtsi"
	#include "stm32mp15xc.dtsi"
	#include "stm32mp15-pinctrl.dtsi"
	#include "stm32mp15xxaa-pinctrl.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/mfd/st,stpmic1.h>

	/ {
	- model = "STMicroelectronics STM32MP157C eval daughter";
	- compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
	-
	- chosen {
	- stdout-path = "serial0:115200n8";
	- };
	-
	memory@c0000000 {
	device_type = "memory";
	reg = <0xC0000000 0x40000000>;
	};

	reserved-memory {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	mcuram2: mcuram2@10000000 {
	compatible = "shared-dma-pool";
	reg = <0x10000000 0x40000>;
	no-map;
	};

	vdev0vring0: vdev0vring0@10040000 {
	compatible = "shared-dma-pool";
	reg = <0x10040000 0x1000>;
	no-map;
	};

	vdev0vring1: vdev0vring1@10041000 {
	compatible = "shared-dma-pool";
	reg = <0x10041000 0x1000>;
	no-map;
	};

	vdev0buffer: vdev0buffer@10042000 {
	compatible = "shared-dma-pool";
	reg = <0x10042000 0x4000>;
	no-map;
	};

	mcuram: mcuram@30000000 {
	compatible = "shared-dma-pool";
	reg = <0x30000000 0x40000>;
	no-map;
	};

	retram: retram@38000000 {
	compatible = "shared-dma-pool";
	reg = <0x38000000 0x10000>;
	no-map;
	};
	-
	- gpu_reserved: gpu@e8000000 {
	- reg = <0xe8000000 0x8000000>;
	- no-map;
	- };
	- };
	-
	- aliases {
	- serial0 = &uart4;
	- };
	-
	- sd_switch: regulator-sd_switch {
	- compatible = "regulator-gpio";
	- regulator-name = "sd_switch";
	- regulator-min-microvolt = <1800000>;
	- regulator-max-microvolt = <2900000>;
	- regulator-type = "voltage";
	- regulator-always-on;
	-
	- gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
	- gpios-states = <0>;
	- states = <1800000 0x1>,
	- <2900000 0x0>;
	};
	};

	&adc {
	- /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
	- pinctrl-0 = <&adc1_in6_pins_a>;
	- pinctrl-names = "default";
	vdd-supply = <&vdd>;
	vdda-supply = <&vdda>;
	vref-supply = <&vdda>;
	- status = "disabled";
	+ status = "okay";
	+
	adc1: adc@0 {
	- st,adc-channels = <0 1 6>;
	- /* 16.5 ck_cycles sampling time */
	- st,min-sample-time-nsecs = <400>;
	+ st,min-sample-time-nsecs = <5000>;
	+ st,adc-channels = <0>;
	+ status = "okay";
	+ };
	+
	+ adc2: adc@100 {
	+ st,adc-channels = <1>;
	+ st,min-sample-time-nsecs = <5000>;
	status = "okay";
	};
	};

	&dac {
	pinctrl-names = "default";
	pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
	vref-supply = <&vdda>;
	- status = "disabled";
	+ status = "okay";
	+
	dac1: dac@1 {
	status = "okay";
	};
	dac2: dac@2 {
	status = "okay";
	};
	};

	&dts {
	status = "okay";
	};

	&gpu {
	- contiguous-area = <&gpu_reserved>;
	status = "okay";
	};

	&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins_a>;
	i2c-scl-rising-time-ns = <185>;
	i2c-scl-falling-time-ns = <20>;
	status = "okay";
	/* spare dmas for other usage */
	/delete-property/dmas;
	/delete-property/dma-names;

	+ rtc@32 {
	+ compatible = "microcrystal,rv8803";
	+ reg = <0x32>;
	+ };
	+
	pmic: stpmic@33 {
	compatible = "st,stpmic1";
	reg = <0x33>;
	interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
	interrupt-controller;
	#interrupt-cells = <2>;
	status = "okay";

	regulators {
	compatible = "st,stpmic1-regulators";
	ldo1-supply = <&v3v3>;
	ldo2-supply = <&v3v3>;
	ldo3-supply = <&vdd_ddr>;
	ldo5-supply = <&v3v3>;
	ldo6-supply = <&v3v3>;
	pwr_sw1-supply = <&bst_out>;
	pwr_sw2-supply = <&bst_out>;

	vddcore: buck1 {
	regulator-name = "vddcore";
	- regulator-min-microvolt = <1200000>;
	+ regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-initial-mode = <0>;
	regulator-over-current-protection;
	};

	vdd_ddr: buck2 {
	regulator-name = "vdd_ddr";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-initial-mode = <0>;
	regulator-over-current-protection;
	};

	vdd: buck3 {
	regulator-name = "vdd";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	st,mask-reset;
	regulator-initial-mode = <0>;
	regulator-over-current-protection;
	};

	v3v3: buck4 {
	regulator-name = "v3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-over-current-protection;
	regulator-initial-mode = <0>;
	};

	vdda: ldo1 {
	regulator-name = "vdda";
	regulator-min-microvolt = <2900000>;
	regulator-max-microvolt = <2900000>;
	interrupts = <IT_CURLIM_LDO1 0>;
	};

	v2v8: ldo2 {
	regulator-name = "v2v8";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	interrupts = <IT_CURLIM_LDO2 0>;
	};

	vtt_ddr: ldo3 {
	regulator-name = "vtt_ddr";
	regulator-min-microvolt = <500000>;
	regulator-max-microvolt = <750000>;
	regulator-always-on;
	regulator-over-current-protection;
	};

	vdd_usb: ldo4 {
	regulator-name = "vdd_usb";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	interrupts = <IT_CURLIM_LDO4 0>;
	};

	vdd_sd: ldo5 {
	regulator-name = "vdd_sd";
	regulator-min-microvolt = <2900000>;
	regulator-max-microvolt = <2900000>;
	interrupts = <IT_CURLIM_LDO5 0>;
	regulator-boot-on;
	};

	v1v8: ldo6 {
	regulator-name = "v1v8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	interrupts = <IT_CURLIM_LDO6 0>;
	};

	vref_ddr: vref_ddr {
	regulator-name = "vref_ddr";
	regulator-always-on;
	regulator-over-current-protection;
	};

	bst_out: boost {
	regulator-name = "bst_out";
	interrupts = <IT_OCP_BOOST 0>;
	};

	vbus_otg: pwr_sw1 {
	regulator-name = "vbus_otg";
	interrupts = <IT_OCP_OTG 0>;
	- };
	+ };

	- vbus_sw: pwr_sw2 {
	+ vbus_sw: pwr_sw2 {
	regulator-name = "vbus_sw";
	interrupts = <IT_OCP_SWOUT 0>;
	- regulator-active-discharge = <1>;
	- };
	+ regulator-active-discharge;
	+ };
	};

	onkey {
	compatible = "st,stpmic1-onkey";
	interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
	interrupt-names = "onkey-falling", "onkey-rising";
	power-off-time-sec = <10>;
	status = "okay";
	};

	watchdog {
	compatible = "st,stpmic1-wdt";
	status = "disabled";
	};
	};
	+
	+ touchscreen@49 {
	+ compatible = "ti,tsc2004";
	+ reg = <0x49>;
	+ vio-supply = <&v3v3>;
	+ interrupts-extended = <&gpioh 3 IRQ_TYPE_EDGE_FALLING>;
	+ };
	+
	+ eeprom@50 {
	+ compatible = "atmel,24c02";
	+ reg = <0x50>;
	+ pagesize = <16>;
	+ };
	};

	&ipcc {
	status = "okay";
	};

	&iwdg2 {
	timeout-sec = <32>;
	status = "okay";
	};

	&m4_rproc {
	memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
	<&vdev0vring1>, <&vdev0buffer>;
	mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
	mbox-names = "vq0", "vq1", "shutdown";
	interrupt-parent = <&exti>;
	interrupts = <68 1>;
	status = "okay";
	};

	&pwr_regulators {
	vdd-supply = <&vdd>;
	vdd_3v3_usbfs-supply = <&vdd_usb>;
	};

	+&qspi {
	+ pinctrl-names = "default", "sleep";
	+ pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
	+ pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
	+ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ status = "okay";
	+
	+ flash0: mx66l51235l@0 {
	+ compatible = "jedec,spi-nor";
	+ reg = <0>;
	+ spi-rx-bus-width = <4>;
	+ spi-max-frequency = <108000000>;
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ };
	+};
	+
	&rng1 {
	status = "okay";
	};

	&rtc {
	status = "okay";
	};

	&sdmmc1 {
	pinctrl-names = "default", "opendrain", "sleep";
	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
	pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
	broken-cd;
	st,sig-dir;
	st,neg-edge;
	st,use-ckin;
	bus-width = <4>;
	vmmc-supply = <&vdd_sd>;
	- vqmmc-supply = <&sd_switch>;
	status = "okay";
	};

	&sdmmc2 {
	pinctrl-names = "default", "opendrain", "sleep";
	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
	pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
	pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
	non-removable;
	no-sd;
	no-sdio;
	st,neg-edge;
	bus-width = <8>;
	vmmc-supply = <&v3v3>;
	vqmmc-supply = <&v3v3>;
	mmc-ddr-3_3v;
	status = "okay";
	};

	-&timers6 {
	+&sdmmc3 {
	+ pinctrl-names = "default", "opendrain", "sleep";
	+ pinctrl-0 = <&sdmmc3_b4_pins_a>;
	+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
	+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
	+ broken-cd;
	+ st,neg-edge;
	+ bus-width = <4>;
	+ vmmc-supply = <&v3v3>;
	+ vqmmc-supply = <&v3v3>;
	+ mmc-ddr-3_3v;
	status = "okay";
	- /* spare dmas for other usage */
	- /delete-property/dmas;
	- /delete-property/dma-names;
	- timer@5 {
	- status = "okay";
	- };
	};

	&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_pins_a>;
	status = "okay";
	};
	-
	-&usbphyc_port0 {
	- phy-supply = <&vdd_usb>;
	- vdda1v1-supply = <&reg11>;
	- vdda1v8-supply = <&reg18>;
	-};
	-
	-&usbphyc_port1 {
	- phy-supply = <&vdd_usb>;
	- vdda1v1-supply = <&reg11>;
	- vdda1v8-supply = <&reg18>;
	-};
	diff --git a/sys/gnu/dts/arm/stm32mp157c-ed1.dts b/sys/gnu/dts/arm/stm32mp157c-ed1.dts
	index 1fc43251d697..9d2592db630c 100644
	--- a/sys/gnu/dts/arm/stm32mp157c-ed1.dts
	+++ b/sys/gnu/dts/arm/stm32mp157c-ed1.dts
	@@ -1,368 +1,372 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
	/*
	* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
	* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
	*/
	/dts-v1/;

	#include "stm32mp157.dtsi"
	#include "stm32mp15xc.dtsi"
	#include "stm32mp15-pinctrl.dtsi"
	#include "stm32mp15xxaa-pinctrl.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/mfd/st,stpmic1.h>

	/ {
	model = "STMicroelectronics STM32MP157C eval daughter";
	compatible = "st,stm32mp157c-ed1", "st,stm32mp157";

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@c0000000 {
	device_type = "memory";
	reg = <0xC0000000 0x40000000>;
	};

	reserved-memory {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	mcuram2: mcuram2@10000000 {
	compatible = "shared-dma-pool";
	reg = <0x10000000 0x40000>;
	no-map;
	};

	vdev0vring0: vdev0vring0@10040000 {
	compatible = "shared-dma-pool";
	reg = <0x10040000 0x1000>;
	no-map;
	};

	vdev0vring1: vdev0vring1@10041000 {
	compatible = "shared-dma-pool";
	reg = <0x10041000 0x1000>;
	no-map;
	};

	vdev0buffer: vdev0buffer@10042000 {
	compatible = "shared-dma-pool";
	reg = <0x10042000 0x4000>;
	no-map;
	};

	mcuram: mcuram@30000000 {
	compatible = "shared-dma-pool";
	reg = <0x30000000 0x40000>;
	no-map;
	};

	retram: retram@38000000 {
	compatible = "shared-dma-pool";
	reg = <0x38000000 0x10000>;
	no-map;
	};

	gpu_reserved: gpu@e8000000 {
	reg = <0xe8000000 0x8000000>;
	no-map;
	};
	};

	aliases {
	serial0 = &uart4;
	};

	sd_switch: regulator-sd_switch {
	compatible = "regulator-gpio";
	regulator-name = "sd_switch";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2900000>;
	regulator-type = "voltage";
	regulator-always-on;

	gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
	gpios-states = <0>;
	states = <1800000 0x1>,
	<2900000 0x0>;
	};
	};

	&adc {
	/* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
	pinctrl-0 = <&adc1_in6_pins_a>;
	pinctrl-names = "default";
	vdd-supply = <&vdd>;
	vdda-supply = <&vdda>;
	vref-supply = <&vdda>;
	status = "disabled";
	adc1: adc@0 {
	st,adc-channels = <0 1 6>;
	/* 16.5 ck_cycles sampling time */
	st,min-sample-time-nsecs = <400>;
	status = "okay";
	};
	};

	&dac {
	pinctrl-names = "default";
	pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
	vref-supply = <&vdda>;
	status = "disabled";
	dac1: dac@1 {
	status = "okay";
	};
	dac2: dac@2 {
	status = "okay";
	};
	};

	&dts {
	status = "okay";
	};

	&gpu {
	contiguous-area = <&gpu_reserved>;
	status = "okay";
	};

	&i2c4 {
	- pinctrl-names = "default";
	+ pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c4_pins_a>;
	+ pinctrl-1 = <&i2c4_pins_sleep_a>;
	i2c-scl-rising-time-ns = <185>;
	i2c-scl-falling-time-ns = <20>;
	+ clock-frequency = <400000>;
	status = "okay";
	/* spare dmas for other usage */
	/delete-property/dmas;
	/delete-property/dma-names;

	pmic: stpmic@33 {
	compatible = "st,stpmic1";
	reg = <0x33>;
	interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
	interrupt-controller;
	#interrupt-cells = <2>;
	status = "okay";

	regulators {
	compatible = "st,stpmic1-regulators";
	ldo1-supply = <&v3v3>;
	ldo2-supply = <&v3v3>;
	ldo3-supply = <&vdd_ddr>;
	ldo5-supply = <&v3v3>;
	ldo6-supply = <&v3v3>;
	pwr_sw1-supply = <&bst_out>;
	pwr_sw2-supply = <&bst_out>;

	vddcore: buck1 {
	regulator-name = "vddcore";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-initial-mode = <0>;
	regulator-over-current-protection;
	};

	vdd_ddr: buck2 {
	regulator-name = "vdd_ddr";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-initial-mode = <0>;
	regulator-over-current-protection;
	};

	vdd: buck3 {
	regulator-name = "vdd";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	st,mask-reset;
	regulator-initial-mode = <0>;
	regulator-over-current-protection;
	};

	v3v3: buck4 {
	regulator-name = "v3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-over-current-protection;
	regulator-initial-mode = <0>;
	};

	vdda: ldo1 {
	regulator-name = "vdda";
	regulator-min-microvolt = <2900000>;
	regulator-max-microvolt = <2900000>;
	interrupts = <IT_CURLIM_LDO1 0>;
	};

	v2v8: ldo2 {
	regulator-name = "v2v8";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	interrupts = <IT_CURLIM_LDO2 0>;
	};

	vtt_ddr: ldo3 {
	regulator-name = "vtt_ddr";
	regulator-min-microvolt = <500000>;
	regulator-max-microvolt = <750000>;
	regulator-always-on;
	regulator-over-current-protection;
	};

	vdd_usb: ldo4 {
	regulator-name = "vdd_usb";
	- regulator-min-microvolt = <3300000>;
	- regulator-max-microvolt = <3300000>;
	interrupts = <IT_CURLIM_LDO4 0>;
	};

	vdd_sd: ldo5 {
	regulator-name = "vdd_sd";
	regulator-min-microvolt = <2900000>;
	regulator-max-microvolt = <2900000>;
	interrupts = <IT_CURLIM_LDO5 0>;
	regulator-boot-on;
	};

	v1v8: ldo6 {
	regulator-name = "v1v8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	interrupts = <IT_CURLIM_LDO6 0>;
	};

	vref_ddr: vref_ddr {
	regulator-name = "vref_ddr";
	regulator-always-on;
	- regulator-over-current-protection;
	};

	bst_out: boost {
	regulator-name = "bst_out";
	interrupts = <IT_OCP_BOOST 0>;
	};

	vbus_otg: pwr_sw1 {
	regulator-name = "vbus_otg";
	interrupts = <IT_OCP_OTG 0>;
	};

	vbus_sw: pwr_sw2 {
	regulator-name = "vbus_sw";
	interrupts = <IT_OCP_SWOUT 0>;
	regulator-active-discharge = <1>;
	};
	};

	onkey {
	compatible = "st,stpmic1-onkey";
	interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
	interrupt-names = "onkey-falling", "onkey-rising";
	power-off-time-sec = <10>;
	status = "okay";
	};

	watchdog {
	compatible = "st,stpmic1-wdt";
	status = "disabled";
	};
	};
	};

	&ipcc {
	status = "okay";
	};

	&iwdg2 {
	timeout-sec = <32>;
	status = "okay";
	};

	&m4_rproc {
	memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
	<&vdev0vring1>, <&vdev0buffer>;
	mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
	mbox-names = "vq0", "vq1", "shutdown";
	interrupt-parent = <&exti>;
	interrupts = <68 1>;
	status = "okay";
	};

	&pwr_regulators {
	vdd-supply = <&vdd>;
	vdd_3v3_usbfs-supply = <&vdd_usb>;
	};

	&rng1 {
	status = "okay";
	};

	&rtc {
	status = "okay";
	};

	&sdmmc1 {
	pinctrl-names = "default", "opendrain", "sleep";
	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
	pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
	- broken-cd;
	+ cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW \| GPIO_PULL_UP)>;
	+ disable-wp;
	st,sig-dir;
	st,neg-edge;
	st,use-ckin;
	bus-width = <4>;
	vmmc-supply = <&vdd_sd>;
	vqmmc-supply = <&sd_switch>;
	status = "okay";
	};

	&sdmmc2 {
	pinctrl-names = "default", "opendrain", "sleep";
	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
	pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
	pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
	non-removable;
	no-sd;
	no-sdio;
	st,neg-edge;
	bus-width = <8>;
	vmmc-supply = <&v3v3>;
	- vqmmc-supply = <&v3v3>;
	+ vqmmc-supply = <&vdd>;
	mmc-ddr-3_3v;
	status = "okay";
	};

	&timers6 {
	status = "okay";
	/* spare dmas for other usage */
	/delete-property/dmas;
	/delete-property/dma-names;
	timer@5 {
	status = "okay";
	};
	};

	&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_pins_a>;
	status = "okay";
	};

	+&usbotg_hs {
	+ vbus-supply = <&vbus_otg>;
	+};
	+
	&usbphyc_port0 {
	phy-supply = <&vdd_usb>;
	vdda1v1-supply = <&reg11>;
	vdda1v8-supply = <&reg18>;
	};

	&usbphyc_port1 {
	phy-supply = <&vdd_usb>;
	vdda1v1-supply = <&reg11>;
	vdda1v8-supply = <&reg18>;
	};
	diff --git a/sys/gnu/dts/arm/stm32mp157c-ev1.dts b/sys/gnu/dts/arm/stm32mp157c-ev1.dts
	index 228e35e16884..8a4c7ff31a92 100644
	--- a/sys/gnu/dts/arm/stm32mp157c-ev1.dts
	+++ b/sys/gnu/dts/arm/stm32mp157c-ev1.dts
	@@ -1,364 +1,367 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
	/*
	* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
	* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
	*/
	/dts-v1/;

	#include "stm32mp157c-ed1.dts"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>

	/ {
	model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
	compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";

	chosen {
	stdout-path = "serial0:115200n8";
	};

	aliases {
	serial0 = &uart4;
	ethernet0 = &ethernet0;
	};

	clocks {
	clk_ext_camera: clk-ext-camera {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	};
	};

	joystick {
	compatible = "gpio-keys";
	pinctrl-0 = <&joystick_pins>;
	pinctrl-names = "default";
	button-0 {
	label = "JoySel";
	linux,code = <KEY_ENTER>;
	interrupt-parent = <&stmfx_pinctrl>;
	interrupts = <0 IRQ_TYPE_EDGE_RISING>;
	};
	button-1 {
	label = "JoyDown";
	linux,code = <KEY_DOWN>;
	interrupt-parent = <&stmfx_pinctrl>;
	interrupts = <1 IRQ_TYPE_EDGE_RISING>;
	};
	button-2 {
	label = "JoyLeft";
	linux,code = <KEY_LEFT>;
	interrupt-parent = <&stmfx_pinctrl>;
	interrupts = <2 IRQ_TYPE_EDGE_RISING>;
	};
	button-3 {
	label = "JoyRight";
	linux,code = <KEY_RIGHT>;
	interrupt-parent = <&stmfx_pinctrl>;
	interrupts = <3 IRQ_TYPE_EDGE_RISING>;
	};
	button-4 {
	label = "JoyUp";
	linux,code = <KEY_UP>;
	interrupt-parent = <&stmfx_pinctrl>;
	interrupts = <4 IRQ_TYPE_EDGE_RISING>;
	};
	};

	panel_backlight: panel-backlight {
	compatible = "gpio-backlight";
	gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
	default-on;
	status = "okay";
	};
	};

	&cec {
	pinctrl-names = "default";
	pinctrl-0 = <&cec_pins_a>;
	status = "okay";
	};

	&dcmi {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&dcmi_pins_a>;
	pinctrl-1 = <&dcmi_sleep_pins_a>;

	port {
	dcmi_0: endpoint {
	remote-endpoint = <&ov5640_0>;
	bus-width = <8>;
	hsync-active = <0>;
	vsync-active = <0>;
	pclk-sample = <1>;
	};
	};
	};

	&dsi {
	#address-cells = <1>;
	#size-cells = <0>;
	phy-dsi-supply = <&reg18>;
	status = "okay";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	dsi_in: endpoint {
	remote-endpoint = <&ltdc_ep0_out>;
	};
	};

	port@1 {
	reg = <1>;
	dsi_out: endpoint {
	remote-endpoint = <&dsi_panel_in>;
	};
	};
	};

	panel-dsi@0 {
	compatible = "raydium,rm68200";
	reg = <0>;
	reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
	backlight = <&panel_backlight>;
	power-supply = <&v3v3>;
	status = "okay";

	port {
	dsi_panel_in: endpoint {
	remote-endpoint = <&dsi_out>;
	};
	};
	};
	};

	&ethernet0 {
	status = "okay";
	pinctrl-0 = <&ethernet0_rgmii_pins_a>;
	pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
	pinctrl-names = "default", "sleep";
	phy-mode = "rgmii-id";
	max-speed = <1000>;
	phy-handle = <&phy0>;

	mdio0 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,dwmac-mdio";
	phy0: ethernet-phy@0 {
	reg = <0>;
	};
	};
	};

	&fmc {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&fmc_pins_a>;
	pinctrl-1 = <&fmc_sleep_pins_a>;
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	nand@0 {
	reg = <0>;
	nand-on-flash-bbt;
	#address-cells = <1>;
	#size-cells = <1>;
	};
	};

	&i2c2 {
	- pinctrl-names = "default";
	+ pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c2_pins_a>;
	+ pinctrl-1 = <&i2c2_pins_sleep_a>;
	i2c-scl-rising-time-ns = <185>;
	i2c-scl-falling-time-ns = <20>;
	status = "okay";

	ov5640: camera@3c {
	compatible = "ovti,ov5640";
	reg = <0x3c>;
	clocks = <&clk_ext_camera>;
	clock-names = "xclk";
	DOVDD-supply = <&v2v8>;
	powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH \| GPIO_PUSH_PULL)>;
	reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW \| GPIO_PUSH_PULL)>;
	rotation = <180>;
	status = "okay";

	port {
	ov5640_0: endpoint {
	remote-endpoint = <&dcmi_0>;
	bus-width = <8>;
	data-shift = <2>; /* lines 9:2 are used */
	hsync-active = <0>;
	vsync-active = <0>;
	pclk-sample = <1>;
	};
	};
	};

	stmfx: stmfx@42 {
	compatible = "st,stmfx-0300";
	reg = <0x42>;
	interrupts = <8 IRQ_TYPE_EDGE_RISING>;
	interrupt-parent = <&gpioi>;
	vdd-supply = <&v3v3>;

	- stmfx_pinctrl: stmfx-pin-controller {
	+ stmfx_pinctrl: pinctrl {
	compatible = "st,stmfx-0300-pinctrl";
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&stmfx_pinctrl 0 0 24>;

	- joystick_pins: joystick {
	+ joystick_pins: joystick-pins {
	pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
	bias-pull-down;
	};
	};
	};
	};

	&i2c5 {
	- pinctrl-names = "default";
	+ pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c5_pins_a>;
	+ pinctrl-1 = <&i2c5_pins_sleep_a>;
	i2c-scl-rising-time-ns = <185>;
	i2c-scl-falling-time-ns = <20>;
	status = "okay";
	};

	&ltdc {
	status = "okay";

	port {
	#address-cells = <1>;
	#size-cells = <0>;

	ltdc_ep0_out: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&dsi_in>;
	};
	};
	};

	&m_can1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&m_can1_pins_a>;
	pinctrl-1 = <&m_can1_sleep_pins_a>;
	status = "okay";
	};

	&qspi {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
	pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	flash0: mx66l51235l@0 {
	compatible = "jedec,spi-nor";
	reg = <0>;
	spi-rx-bus-width = <4>;
	spi-max-frequency = <108000000>;
	#address-cells = <1>;
	#size-cells = <1>;
	};

	flash1: mx66l51235l@1 {
	compatible = "jedec,spi-nor";
	reg = <1>;
	spi-rx-bus-width = <4>;
	spi-max-frequency = <108000000>;
	#address-cells = <1>;
	#size-cells = <1>;
	};
	};

	&sdmmc3 {
	pinctrl-names = "default", "opendrain", "sleep";
	pinctrl-0 = <&sdmmc3_b4_pins_a>;
	pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
	pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
	broken-cd;
	st,neg-edge;
	bus-width = <4>;
	vmmc-supply = <&v3v3>;
	status = "disabled";
	};

	&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_pins_a>;
	status = "disabled";
	};

	&timers2 {
	/* spare dmas for other usage (un-delete to enable pwm capture) */
	/delete-property/dmas;
	/delete-property/dma-names;
	status = "disabled";
	pwm {
	pinctrl-0 = <&pwm2_pins_a>;
	pinctrl-1 = <&pwm2_sleep_pins_a>;
	pinctrl-names = "default", "sleep";
	status = "okay";
	};
	timer@1 {
	status = "okay";
	};
	};

	&timers8 {
	/delete-property/dmas;
	/delete-property/dma-names;
	status = "disabled";
	pwm {
	pinctrl-0 = <&pwm8_pins_a>;
	pinctrl-1 = <&pwm8_sleep_pins_a>;
	pinctrl-names = "default", "sleep";
	status = "okay";
	};
	timer@7 {
	status = "okay";
	};
	};

	&timers12 {
	/delete-property/dmas;
	/delete-property/dma-names;
	status = "disabled";
	pwm {
	pinctrl-0 = <&pwm12_pins_a>;
	pinctrl-1 = <&pwm12_sleep_pins_a>;
	pinctrl-names = "default", "sleep";
	status = "okay";
	};
	timer@11 {
	status = "okay";
	};
	};

	&usbh_ehci {
	phys = <&usbphyc_port0>;
	status = "okay";
	};

	&usbotg_hs {
	- dr_mode = "peripheral";
	+ pinctrl-0 = <&usbotg_hs_pins_a>;
	+ pinctrl-names = "default";
	phys = <&usbphyc_port1 0>;
	phy-names = "usb2-phy";
	status = "okay";
	};

	&usbphyc {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/stm32mp15xx-dkx.dtsi b/sys/gnu/dts/arm/stm32mp15xx-dkx.dtsi
	index f6672e87aef3..d946e0a02f5c 100644
	--- a/sys/gnu/dts/arm/stm32mp15xx-dkx.dtsi
	+++ b/sys/gnu/dts/arm/stm32mp15xx-dkx.dtsi
	@@ -1,625 +1,625 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
	/*
	* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
	* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
	*/

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/mfd/st,stpmic1.h>

	/ {
	memory@c0000000 {
	device_type = "memory";
	reg = <0xc0000000 0x20000000>;
	};

	reserved-memory {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	mcuram2: mcuram2@10000000 {
	compatible = "shared-dma-pool";
	reg = <0x10000000 0x40000>;
	no-map;
	};

	vdev0vring0: vdev0vring0@10040000 {
	compatible = "shared-dma-pool";
	reg = <0x10040000 0x1000>;
	no-map;
	};

	vdev0vring1: vdev0vring1@10041000 {
	compatible = "shared-dma-pool";
	reg = <0x10041000 0x1000>;
	no-map;
	};

	vdev0buffer: vdev0buffer@10042000 {
	compatible = "shared-dma-pool";
	reg = <0x10042000 0x4000>;
	no-map;
	};

	mcuram: mcuram@30000000 {
	compatible = "shared-dma-pool";
	reg = <0x30000000 0x40000>;
	no-map;
	};

	retram: retram@38000000 {
	compatible = "shared-dma-pool";
	reg = <0x38000000 0x10000>;
	no-map;
	};

	gpu_reserved: gpu@d4000000 {
	reg = <0xd4000000 0x4000000>;
	no-map;
	};
	};

	led {
	compatible = "gpio-leds";
	blue {
	label = "heartbeat";
	gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	default-state = "off";
	};
	};

	sound {
	compatible = "audio-graph-card";
	label = "STM32MP1-DK";
	routing =
	"Playback" , "MCLK",
	"Capture" , "MCLK",
	"MICL" , "Mic Bias";
	dais = <&sai2a_port &sai2b_port &i2s2_port>;
	status = "okay";
	};
	};

	&adc {
	pinctrl-names = "default";
	pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
	vdd-supply = <&vdd>;
	vdda-supply = <&vdd>;
	vref-supply = <&vrefbuf>;
	status = "disabled";
	adc1: adc@0 {
	/*
	* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
	* Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
	* 5 * (56 + 47kOhms) * 5pF => 2.5us.
	* Use arbitrary margin here (e.g. 5us).
	*/
	st,min-sample-time-nsecs = <5000>;
	/* AIN connector, USB Type-C CC1 & CC2 */
	st,adc-channels = <0 1 6 13 18 19>;
	status = "okay";
	};
	adc2: adc@100 {
	/* AIN connector, USB Type-C CC1 & CC2 */
	st,adc-channels = <0 1 2 6 18 19>;
	st,min-sample-time-nsecs = <5000>;
	status = "okay";
	};
	};

	&cec {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&cec_pins_b>;
	pinctrl-1 = <&cec_pins_sleep_b>;
	status = "okay";
	};

	&ethernet0 {
	status = "okay";
	pinctrl-0 = <&ethernet0_rgmii_pins_a>;
	pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
	pinctrl-names = "default", "sleep";
	phy-mode = "rgmii-id";
	max-speed = <1000>;
	phy-handle = <&phy0>;

	mdio0 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,dwmac-mdio";
	phy0: ethernet-phy@0 {
	reg = <0>;
	};
	};
	};

	&gpu {
	contiguous-area = <&gpu_reserved>;
	status = "okay";
	};

	&i2c1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c1_pins_a>;
	pinctrl-1 = <&i2c1_pins_sleep_a>;
	i2c-scl-rising-time-ns = <100>;
	i2c-scl-falling-time-ns = <7>;
	status = "okay";
	/delete-property/dmas;
	/delete-property/dma-names;

	hdmi-transmitter@39 {
	compatible = "sil,sii9022";
	reg = <0x39>;
	iovcc-supply = <&v3v3_hdmi>;
	cvcc12-supply = <&v1v2_hdmi>;
	reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
	interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
	interrupt-parent = <&gpiog>;
	#sound-dai-cells = <0>;
	status = "okay";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	sii9022_in: endpoint {
	remote-endpoint = <&ltdc_ep0_out>;
	};
	};

	port@3 {
	reg = <3>;
	sii9022_tx_endpoint: endpoint {
	remote-endpoint = <&i2s2_endpoint>;
	};
	};
	};
	};

	cs42l51: cs42l51@4a {
	compatible = "cirrus,cs42l51";
	reg = <0x4a>;
	#sound-dai-cells = <0>;
	VL-supply = <&v3v3>;
	VD-supply = <&v1v8_audio>;
	VA-supply = <&v1v8_audio>;
	VAHP-supply = <&v1v8_audio>;
	reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
	clocks = <&sai2a>;
	clock-names = "MCLK";
	status = "okay";

	cs42l51_port: port {
	#address-cells = <1>;
	#size-cells = <0>;

	cs42l51_tx_endpoint: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&sai2a_endpoint>;
	frame-master;
	bitclock-master;
	};

	cs42l51_rx_endpoint: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&sai2b_endpoint>;
	frame-master;
	bitclock-master;
	};
	};
	};
	};

	&i2c4 {
	- pinctrl-names = "default";
	+ pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c4_pins_a>;
	+ pinctrl-1 = <&i2c4_pins_sleep_a>;
	i2c-scl-rising-time-ns = <185>;
	i2c-scl-falling-time-ns = <20>;
	+ clock-frequency = <400000>;
	status = "okay";
	/* spare dmas for other usage */
	/delete-property/dmas;
	/delete-property/dma-names;

	pmic: stpmic@33 {
	compatible = "st,stpmic1";
	reg = <0x33>;
	interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
	interrupt-controller;
	#interrupt-cells = <2>;
	status = "okay";

	regulators {
	compatible = "st,stpmic1-regulators";
	ldo1-supply = <&v3v3>;
	ldo3-supply = <&vdd_ddr>;
	ldo6-supply = <&v3v3>;
	pwr_sw1-supply = <&bst_out>;
	pwr_sw2-supply = <&bst_out>;

	vddcore: buck1 {
	regulator-name = "vddcore";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-initial-mode = <0>;
	regulator-over-current-protection;
	};

	vdd_ddr: buck2 {
	regulator-name = "vdd_ddr";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-initial-mode = <0>;
	regulator-over-current-protection;
	};

	vdd: buck3 {
	regulator-name = "vdd";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	st,mask-reset;
	regulator-initial-mode = <0>;
	regulator-over-current-protection;
	};

	v3v3: buck4 {
	regulator-name = "v3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-over-current-protection;
	regulator-initial-mode = <0>;
	};

	v1v8_audio: ldo1 {
	regulator-name = "v1v8_audio";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	interrupts = <IT_CURLIM_LDO1 0>;
	};

	v3v3_hdmi: ldo2 {
	regulator-name = "v3v3_hdmi";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	interrupts = <IT_CURLIM_LDO2 0>;
	};

	vtt_ddr: ldo3 {
	regulator-name = "vtt_ddr";
	regulator-min-microvolt = <500000>;
	regulator-max-microvolt = <750000>;
	regulator-always-on;
	regulator-over-current-protection;
	};

	vdd_usb: ldo4 {
	regulator-name = "vdd_usb";
	- regulator-min-microvolt = <3300000>;
	- regulator-max-microvolt = <3300000>;
	interrupts = <IT_CURLIM_LDO4 0>;
	};

	vdda: ldo5 {
	regulator-name = "vdda";
	regulator-min-microvolt = <2900000>;
	regulator-max-microvolt = <2900000>;
	interrupts = <IT_CURLIM_LDO5 0>;
	regulator-boot-on;
	};

	v1v2_hdmi: ldo6 {
	regulator-name = "v1v2_hdmi";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	interrupts = <IT_CURLIM_LDO6 0>;
	};

	vref_ddr: vref_ddr {
	regulator-name = "vref_ddr";
	regulator-always-on;
	- regulator-over-current-protection;
	};

	bst_out: boost {
	regulator-name = "bst_out";
	interrupts = <IT_OCP_BOOST 0>;
	};

	vbus_otg: pwr_sw1 {
	regulator-name = "vbus_otg";
	interrupts = <IT_OCP_OTG 0>;
	};

	vbus_sw: pwr_sw2 {
	regulator-name = "vbus_sw";
	interrupts = <IT_OCP_SWOUT 0>;
	regulator-active-discharge = <1>;
	};
	};

	onkey {
	compatible = "st,stpmic1-onkey";
	interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
	interrupt-names = "onkey-falling", "onkey-rising";
	power-off-time-sec = <10>;
	status = "okay";
	};

	watchdog {
	compatible = "st,stpmic1-wdt";
	status = "disabled";
	};
	};
	};

	&i2s2 {
	clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
	clock-names = "pclk", "i2sclk", "x8k", "x11k";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2s2_pins_a>;
	pinctrl-1 = <&i2s2_pins_sleep_a>;
	status = "okay";

	i2s2_port: port {
	i2s2_endpoint: endpoint {
	remote-endpoint = <&sii9022_tx_endpoint>;
	format = "i2s";
	mclk-fs = <256>;
	};
	};
	};

	&ipcc {
	status = "okay";
	};

	&iwdg2 {
	timeout-sec = <32>;
	status = "okay";
	};

	&ltdc {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&ltdc_pins_a>;
	pinctrl-1 = <&ltdc_pins_sleep_a>;
	status = "okay";

	port {
	#address-cells = <1>;
	#size-cells = <0>;

	ltdc_ep0_out: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&sii9022_in>;
	};
	};
	};

	&m4_rproc {
	memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
	<&vdev0vring1>, <&vdev0buffer>;
	mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
	mbox-names = "vq0", "vq1", "shutdown";
	interrupt-parent = <&exti>;
	interrupts = <68 1>;
	status = "okay";
	};

	&pwr_regulators {
	vdd-supply = <&vdd>;
	vdd_3v3_usbfs-supply = <&vdd_usb>;
	};

	&rng1 {
	status = "okay";
	};

	&rtc {
	status = "okay";
	};

	&sai2 {
	clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
	clock-names = "pclk", "x8k", "x11k";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>;
	pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>;
	status = "okay";

	sai2a: audio-controller@4400b004 {
	#clock-cells = <0>;
	dma-names = "tx";
	clocks = <&rcc SAI2_K>;
	clock-names = "sai_ck";
	status = "okay";

	sai2a_port: port {
	sai2a_endpoint: endpoint {
	remote-endpoint = <&cs42l51_tx_endpoint>;
	format = "i2s";
	mclk-fs = <256>;
	dai-tdm-slot-num = <2>;
	dai-tdm-slot-width = <32>;
	};
	};
	};

	sai2b: audio-controller@4400b024 {
	dma-names = "rx";
	st,sync = <&sai2a 2>;
	clocks = <&rcc SAI2_K>, <&sai2a>;
	clock-names = "sai_ck", "MCLK";
	status = "okay";

	sai2b_port: port {
	sai2b_endpoint: endpoint {
	remote-endpoint = <&cs42l51_rx_endpoint>;
	format = "i2s";
	mclk-fs = <256>;
	dai-tdm-slot-num = <2>;
	dai-tdm-slot-width = <32>;
	};
	};
	};
	};

	&sdmmc1 {
	pinctrl-names = "default", "opendrain", "sleep";
	pinctrl-0 = <&sdmmc1_b4_pins_a>;
	pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
	- broken-cd;
	+ cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW \| GPIO_PULL_UP)>;
	+ disable-wp;
	st,neg-edge;
	bus-width = <4>;
	vmmc-supply = <&v3v3>;
	status = "okay";
	};

	&sdmmc3 {
	pinctrl-names = "default", "opendrain", "sleep";
	pinctrl-0 = <&sdmmc3_b4_pins_a>;
	pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
	pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
	broken-cd;
	st,neg-edge;
	bus-width = <4>;
	vmmc-supply = <&v3v3>;
	status = "disabled";
	};

	&timers1 {
	/* spare dmas for other usage */
	/delete-property/dmas;
	/delete-property/dma-names;
	status = "disabled";
	pwm {
	pinctrl-0 = <&pwm1_pins_a>;
	pinctrl-1 = <&pwm1_sleep_pins_a>;
	pinctrl-names = "default", "sleep";
	status = "okay";
	};
	timer@0 {
	status = "okay";
	};
	};

	&timers3 {
	/delete-property/dmas;
	/delete-property/dma-names;
	status = "disabled";
	pwm {
	pinctrl-0 = <&pwm3_pins_a>;
	pinctrl-1 = <&pwm3_sleep_pins_a>;
	pinctrl-names = "default", "sleep";
	status = "okay";
	};
	timer@2 {
	status = "okay";
	};
	};

	&timers4 {
	/delete-property/dmas;
	/delete-property/dma-names;
	status = "disabled";
	pwm {
	pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>;
	pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>;
	pinctrl-names = "default", "sleep";
	status = "okay";
	};
	timer@3 {
	status = "okay";
	};
	};

	&timers5 {
	/delete-property/dmas;
	/delete-property/dma-names;
	status = "disabled";
	pwm {
	pinctrl-0 = <&pwm5_pins_a>;
	pinctrl-1 = <&pwm5_sleep_pins_a>;
	pinctrl-names = "default", "sleep";
	status = "okay";
	};
	timer@4 {
	status = "okay";
	};
	};

	&timers6 {
	/delete-property/dmas;
	/delete-property/dma-names;
	status = "disabled";
	timer@5 {
	status = "okay";
	};
	};

	&timers12 {
	/delete-property/dmas;
	/delete-property/dma-names;
	status = "disabled";
	pwm {
	pinctrl-0 = <&pwm12_pins_a>;
	pinctrl-1 = <&pwm12_sleep_pins_a>;
	pinctrl-names = "default", "sleep";
	status = "okay";
	};
	timer@11 {
	status = "okay";
	};
	};

	&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_pins_a>;
	status = "okay";
	};

	&usbh_ehci {
	phys = <&usbphyc_port0>;
	status = "okay";
	};

	&usbotg_hs {
	dr_mode = "peripheral";
	phys = <&usbphyc_port1 0>;
	phy-names = "usb2-phy";
	status = "okay";
	};

	&usbphyc {
	status = "okay";
	};

	&usbphyc_port0 {
	phy-supply = <&vdd_usb>;
	vdda1v1-supply = <&reg11>;
	vdda1v8-supply = <&reg18>;
	};

	&usbphyc_port1 {
	phy-supply = <&vdd_usb>;
	vdda1v1-supply = <&reg11>;
	vdda1v8-supply = <&reg18>;
	};

	&vrefbuf {
	regulator-min-microvolt = <2500000>;
	regulator-max-microvolt = <2500000>;
	vdda-supply = <&vdd>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/sun5i-a13-pocketbook-touch-lux-3.dts b/sys/gnu/dts/arm/sun5i-a13-pocketbook-touch-lux-3.dts
	new file mode 100644
	index 000000000000..e9ef97c9c893
	--- /dev/null
	+++ b/sys/gnu/dts/arm/sun5i-a13-pocketbook-touch-lux-3.dts
	@@ -0,0 +1,257 @@
	+// SPDX-License-Identifier: GPL-2.0 OR MIT
	+/*
	+ * Copyright 2019 Ondrej Jirman <megous@megous.com>
	+ */
	+
	+/dts-v1/;
	+#include "sun5i-a13.dtsi"
	+#include "sunxi-common-regulators.dtsi"
	+#include <dt-bindings/gpio/gpio.h>
	+#include <dt-bindings/input/input.h>
	+#include <dt-bindings/interrupt-controller/irq.h>
	+#include <dt-bindings/pwm/pwm.h>
	+
	+/ {
	+ model = "PocketBook Touch Lux 3";
	+ compatible = "pocketbook,touch-lux-3", "allwinner,sun5i-a13";
	+
	+ aliases {
	+ serial0 = &uart1;
	+ i2c0 = &i2c0;
	+ i2c1 = &i2c1;
	+ i2c2 = &i2c2;
	+ };
	+
	+ backlight {
	+ compatible = "pwm-backlight";
	+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
	+ enable-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
	+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
	+ default-brightness-level = <8>;
	+ };
	+
	+ chosen {
	+ stdout-path = "serial0:115200n8";
	+ };
	+
	+ leds {
	+ compatible = "gpio-leds";
	+
	+ power {
	+ gpios = <&pio 4 8 GPIO_ACTIVE_LOW>; /* PE8 */
	+ default-state = "on";
	+ };
	+ };
	+
	+ gpio-keys {
	+ compatible = "gpio-keys";
	+ autorepeat;
	+ label = "GPIO Keys";
	+
	+ key-right {
	+ label = "Right";
	+ linux,code = <KEY_RIGHT>;
	+ gpios = <&pio 6 9 (GPIO_ACTIVE_LOW \| GPIO_PULL_UP)>; /* PG9 */
	+ };
	+
	+ key-left {
	+ label = "Left";
	+ linux,code = <KEY_LEFT>;
	+ gpios = <&pio 6 10 (GPIO_ACTIVE_LOW \| GPIO_PULL_UP)>; /* PG10 */
	+ };
	+ };
	+
	+ reg_1v8: regulator-1v8 {
	+ compatible = "regulator-fixed";
	+ regulator-name = "vdd-1v8-nor-ctp";
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+ gpio = <&pio 2 15 GPIO_ACTIVE_HIGH>;
	+ enable-active-high;
	+ };
	+
	+ reg_1v8_nor: regulator-nor {
	+ compatible = "regulator-fixed";
	+ regulator-name = "vdd-nor";
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+ gpio = <&pio 2 14 GPIO_ACTIVE_HIGH>;
	+ enable-active-high;
	+ vin-supply = <&reg_1v8>;
	+ regulator-always-on;
	+ };
	+
	+ reg_1v8_ctp: regulator-ctp {
	+ compatible = "regulator-fixed";
	+ regulator-name = "vdd-ctp";
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+ gpio = <&pio 2 13 GPIO_ACTIVE_HIGH>;
	+ enable-active-high;
	+ vin-supply = <&reg_1v8>;
	+ };
	+
	+ reg_3v3_mmc0: regulator-mmc0 {
	+ compatible = "regulator-fixed";
	+ regulator-name = "vdd-mmc0";
	+ regulator-min-microvolt = <3300000>;
	+ regulator-max-microvolt = <3300000>;
	+ gpio = <&pio 4 4 GPIO_ACTIVE_LOW>; /* PE4 */
	+ vin-supply = <&reg_vcc3v3>;
	+ };
	+};
	+
	+&cpu0 {
	+ cpu-supply = <&reg_dcdc2>;
	+};
	+
	+&ehci0 {
	+ status = "okay";
	+};
	+
	+&i2c0 {
	+ status = "okay";
	+
	+ axp209: pmic@34 {
	+ reg = <0x34>;
	+ interrupts = <0>;
	+ };
	+};
	+
	+#include "axp209.dtsi"
	+
	+&i2c1 {
	+ status = "okay";
	+
	+ pcf8563: rtc@51 {
	+ compatible = "nxp,pcf8563";
	+ reg = <0x51>;
	+ };
	+};
	+
	+&i2c2 {
	+ status = "okay";
	+
	+ /* Touchpanel is connected here. */
	+};
	+
	+&lradc {
	+ vref-supply = <&reg_ldo2>;
	+ status = "okay";
	+
	+ button-200 {
	+ label = "Home";
	+ linux,code = <KEY_HOME>;
	+ channel = <0>;
	+ voltage = <200000>;
	+ };
	+
	+ button-400 {
	+ label = "Menu";
	+ linux,code = <KEY_MENU>;
	+ channel = <0>;
	+ voltage = <400000>;
	+ };
	+};
	+
	+&mmc0 {
	+ vmmc-supply = <&reg_3v3_mmc0>;
	+ bus-width = <4>;
	+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
	+ status = "okay";
	+};
	+
	+&mmc2 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&mmc2_4bit_pc_pins>;
	+ vmmc-supply = <&reg_vcc3v3>;
	+ bus-width = <4>;
	+ non-removable;
	+ status = "okay";
	+};
	+
	+&ohci0 {
	+ status = "okay";
	+};
	+
	+&otg_sram {
	+ status = "okay";
	+};
	+
	+&pwm {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pwm0_pin>;
	+ status = "okay";
	+};
	+
	+&reg_dcdc2 {
	+ regulator-always-on;
	+ regulator-min-microvolt = <1000000>;
	+ regulator-max-microvolt = <1400000>;
	+ regulator-name = "vdd-cpu";
	+};
	+
	+&reg_dcdc3 {
	+ regulator-always-on;
	+ regulator-min-microvolt = <1200000>;
	+ regulator-max-microvolt = <1200000>;
	+ regulator-name = "vdd-int-pll";
	+};
	+
	+&reg_ldo1 {
	+ regulator-name = "vdd-rtc";
	+};
	+
	+&reg_ldo2 {
	+ regulator-always-on;
	+ regulator-min-microvolt = <3000000>;
	+ regulator-max-microvolt = <3000000>;
	+ regulator-name = "avcc";
	+};
	+
	+&reg_ldo3 {
	+ regulator-min-microvolt = <3300000>;
	+ regulator-max-microvolt = <3300000>;
	+ regulator-name = "vcc-wifi";
	+ /* We need this otherwise the LDO3 would overload */
	+ regulator-soft-start;
	+ regulator-ramp-delay = <1600>;
	+};
	+
	+&spi2 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&spi2_pe_pins>, <&spi2_cs0_pe_pin>;
	+ status = "okay";
	+
	+ epd_flash: flash@0 {
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ compatible = "macronix,mx25u4033", "jedec,spi-nor";
	+ reg = <0>;
	+ spi-max-frequency = <4000000>;
	+ };
	+};
	+
	+&uart1 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&uart1_pg_pins>;
	+ status = "okay";
	+};
	+
	+&usb_otg {
	+ dr_mode = "peripheral";
	+ status = "okay";
	+};
	+
	+&battery_power_supply {
	+ status = "okay";
	+};
	+
	+&usb_power_supply {
	+ status = "okay";
	+};
	+
	+&usbphy {
	+ usb1_vbus-supply = <&reg_ldo3>;
	+ status = "okay";
	+};
	diff --git a/sys/gnu/dts/arm/sun5i.dtsi b/sys/gnu/dts/arm/sun5i.dtsi
	index 0b526e6e5a95..e6b036734a64 100644
	--- a/sys/gnu/dts/arm/sun5i.dtsi
	+++ b/sys/gnu/dts/arm/sun5i.dtsi
	@@ -1,799 +1,798 @@
	/*
	* Copyright 2012-2015 Maxime Ripard
	*
	* Maxime Ripard <maxime.ripard@free-electrons.com>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This library is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This library is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include <dt-bindings/clock/sun5i-ccu.h>
	#include <dt-bindings/dma/sun4i-a10.h>
	#include <dt-bindings/reset/sun5i-ccu.h>

	/ {
	interrupt-parent = <&intc>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a8";
	reg = <0x0>;
	clocks = <&ccu CLK_CPU>;
	};
	};

	chosen {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	framebuffer-lcd0 {
	compatible = "allwinner,simple-framebuffer",
	"simple-framebuffer";
	allwinner,pipeline = "de_be0-lcd0";
	clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
	<&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
	status = "disabled";
	};

	framebuffer-lcd0-tve0 {
	compatible = "allwinner,simple-framebuffer",
	"simple-framebuffer";
	allwinner,pipeline = "de_be0-lcd0-tve0";
	clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
	<&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
	<&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
	status = "disabled";
	};
	};

	clocks {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	osc24M: clk-24M {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-output-names = "osc24M";
	};

	osc32k: clk-32k {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	clock-output-names = "osc32k";
	};
	};

	reserved-memory {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
	default-pool {
	compatible = "shared-dma-pool";
	size = <0x6000000>;
	alloc-ranges = <0x4a000000 0x6000000>;
	reusable;
	linux,cma-default;
	};
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	dma-ranges;
	ranges;

	system-control@1c00000 {
	compatible = "allwinner,sun5i-a13-system-control";
	reg = <0x01c00000 0x30>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	sram_a: sram@0 {
	compatible = "mmio-sram";
	reg = <0x00000000 0xc000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x00000000 0xc000>;

	emac_sram: sram-section@8000 {
	compatible = "allwinner,sun5i-a13-sram-a3-a4",
	"allwinner,sun4i-a10-sram-a3-a4";
	reg = <0x8000 0x4000>;
	status = "disabled";
	};
	};

	sram_d: sram@10000 {
	compatible = "mmio-sram";
	reg = <0x00010000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x00010000 0x1000>;

	otg_sram: sram-section@0 {
	compatible = "allwinner,sun5i-a13-sram-d",
	"allwinner,sun4i-a10-sram-d";
	reg = <0x0000 0x1000>;
	status = "disabled";
	};
	};

	sram_c: sram@1d00000 {
	compatible = "mmio-sram";
	reg = <0x01d00000 0xd0000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x01d00000 0xd0000>;

	ve_sram: sram-section@0 {
	compatible = "allwinner,sun5i-a13-sram-c1",
	"allwinner,sun4i-a10-sram-c1";
	reg = <0x000000 0x80000>;
	};
	};
	};

	mbus: dram-controller@1c01000 {
	compatible = "allwinner,sun5i-a13-mbus";
	reg = <0x01c01000 0x1000>;
	clocks = <&ccu CLK_MBUS>;
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	dma-ranges = <0x00000000 0x40000000 0x20000000>;
	#interconnect-cells = <1>;
	};

	dma: dma-controller@1c02000 {
	compatible = "allwinner,sun4i-a10-dma";
	reg = <0x01c02000 0x1000>;
	interrupts = <27>;
	clocks = <&ccu CLK_AHB_DMA>;
	#dma-cells = <2>;
	};

	nfc: nand-controller@1c03000 {
	compatible = "allwinner,sun4i-a10-nand";
	reg = <0x01c03000 0x1000>;
	interrupts = <37>;
	clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
	clock-names = "ahb", "mod";
	dmas = <&dma SUN4I_DMA_DEDICATED 3>;
	dma-names = "rxtx";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	spi0: spi@1c05000 {
	compatible = "allwinner,sun4i-a10-spi";
	reg = <0x01c05000 0x1000>;
	interrupts = <10>;
	clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
	clock-names = "ahb", "mod";
	dmas = <&dma SUN4I_DMA_DEDICATED 27>,
	<&dma SUN4I_DMA_DEDICATED 26>;
	dma-names = "rx", "tx";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	spi1: spi@1c06000 {
	compatible = "allwinner,sun4i-a10-spi";
	reg = <0x01c06000 0x1000>;
	interrupts = <11>;
	clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
	clock-names = "ahb", "mod";
	dmas = <&dma SUN4I_DMA_DEDICATED 9>,
	<&dma SUN4I_DMA_DEDICATED 8>;
	dma-names = "rx", "tx";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	tve0: tv-encoder@1c0a000 {
	compatible = "allwinner,sun4i-a10-tv-encoder";
	reg = <0x01c0a000 0x1000>;
	clocks = <&ccu CLK_AHB_TVE>;
	resets = <&ccu RST_TVE>;
	status = "disabled";

	port {

	tve0_in_tcon0: endpoint {
	remote-endpoint = <&tcon0_out_tve0>;
	};
	};
	};

	emac: ethernet@1c0b000 {
	compatible = "allwinner,sun4i-a10-emac";
	reg = <0x01c0b000 0x1000>;
	interrupts = <55>;
	clocks = <&ccu CLK_AHB_EMAC>;
	allwinner,sram = <&emac_sram 1>;
	status = "disabled";
	};

	mdio: mdio@1c0b080 {
	compatible = "allwinner,sun4i-a10-mdio";
	reg = <0x01c0b080 0x14>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	tcon0: lcd-controller@1c0c000 {
	compatible = "allwinner,sun5i-a13-tcon";
	reg = <0x01c0c000 0x1000>;
	interrupts = <44>;
	dmas = <&dma SUN4I_DMA_DEDICATED 14>;
	resets = <&ccu RST_LCD>;
	reset-names = "lcd";
	clocks = <&ccu CLK_AHB_LCD>,
	<&ccu CLK_TCON_CH0>,
	<&ccu CLK_TCON_CH1>;
	clock-names = "ahb",
	"tcon-ch0",
	"tcon-ch1";
	clock-output-names = "tcon-pixel-clock";
	#clock-cells = <0>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon0_in: port@0 {
	reg = <0>;

	tcon0_in_be0: endpoint {
	remote-endpoint = <&be0_out_tcon0>;
	};
	};

	tcon0_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	tcon0_out_tve0: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&tve0_in_tcon0>;
	allwinner,tcon-channel = <1>;
	};
	};
	};
	};

	video-codec@1c0e000 {
	compatible = "allwinner,sun5i-a13-video-engine";
	reg = <0x01c0e000 0x1000>;
	clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
	<&ccu CLK_DRAM_VE>;
	clock-names = "ahb", "mod", "ram";
	resets = <&ccu RST_VE>;
	interrupts = <53>;
	allwinner,sram = <&ve_sram 1>;
	};

	mmc0: mmc@1c0f000 {
	compatible = "allwinner,sun5i-a13-mmc";
	reg = <0x01c0f000 0x1000>;
	clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
	clock-names = "ahb", "mmc";
	interrupts = <32>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc1: mmc@1c10000 {
	compatible = "allwinner,sun5i-a13-mmc";
	reg = <0x01c10000 0x1000>;
	clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
	clock-names = "ahb", "mmc";
	interrupts = <33>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc2: mmc@1c11000 {
	compatible = "allwinner,sun5i-a13-mmc";
	reg = <0x01c11000 0x1000>;
	clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
	clock-names = "ahb", "mmc";
	interrupts = <34>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	usb_otg: usb@1c13000 {
	compatible = "allwinner,sun4i-a10-musb";
	reg = <0x01c13000 0x0400>;
	clocks = <&ccu CLK_AHB_OTG>;
	interrupts = <38>;
	interrupt-names = "mc";
	phys = <&usbphy 0>;
	phy-names = "usb";
	extcon = <&usbphy 0>;
	allwinner,sram = <&otg_sram 1>;
	dr_mode = "otg";
	status = "disabled";
	};

	usbphy: phy@1c13400 {
	#phy-cells = <1>;
	compatible = "allwinner,sun5i-a13-usb-phy";
	reg = <0x01c13400 0x10>, <0x01c14800 0x4>;
	reg-names = "phy_ctrl", "pmu1";
	clocks = <&ccu CLK_USB_PHY0>;
	clock-names = "usb_phy";
	resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
	reset-names = "usb0_reset", "usb1_reset";
	status = "disabled";
	};

	ehci0: usb@1c14000 {
	compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
	reg = <0x01c14000 0x100>;
	interrupts = <39>;
	clocks = <&ccu CLK_AHB_EHCI>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	ohci0: usb@1c14400 {
	compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
	reg = <0x01c14400 0x100>;
	interrupts = <40>;
	clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	crypto: crypto-engine@1c15000 {
	compatible = "allwinner,sun5i-a13-crypto",
	"allwinner,sun4i-a10-crypto";
	reg = <0x01c15000 0x1000>;
	interrupts = <54>;
	clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
	clock-names = "ahb", "mod";
	};

	spi2: spi@1c17000 {
	compatible = "allwinner,sun4i-a10-spi";
	reg = <0x01c17000 0x1000>;
	interrupts = <12>;
	clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
	clock-names = "ahb", "mod";
	dmas = <&dma SUN4I_DMA_DEDICATED 29>,
	<&dma SUN4I_DMA_DEDICATED 28>;
	dma-names = "rx", "tx";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	ccu: clock@1c20000 {
	reg = <0x01c20000 0x400>;
	clocks = <&osc24M>, <&osc32k>;
	clock-names = "hosc", "losc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	intc: interrupt-controller@1c20400 {
	compatible = "allwinner,sun4i-a10-ic";
	reg = <0x01c20400 0x400>;
	interrupt-controller;
	#interrupt-cells = <1>;
	};

	pio: pinctrl@1c20800 {
	reg = <0x01c20800 0x400>;
	interrupts = <28>;
	clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
	clock-names = "apb", "hosc", "losc";
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <3>;
	#gpio-cells = <3>;

	emac_pd_pins: emac-pd-pins {
	pins = "PD6", "PD7", "PD10",
	"PD11", "PD12", "PD13", "PD14",
	"PD15", "PD18", "PD19", "PD20",
	"PD21", "PD22", "PD23", "PD24",
	"PD25", "PD26", "PD27";
	function = "emac";
	};

	i2c0_pins: i2c0-pins {
	pins = "PB0", "PB1";
	function = "i2c0";
	};

	i2c1_pins: i2c1-pins {
	pins = "PB15", "PB16";
	function = "i2c1";
	};

	i2c2_pins: i2c2-pins {
	pins = "PB17", "PB18";
	function = "i2c2";
	};

	ir0_rx_pin: ir0-rx-pin {
	pins = "PB4";
	function = "ir0";
	};

	lcd_rgb565_pins: lcd-rgb565-pins {
	pins = "PD3", "PD4", "PD5", "PD6", "PD7",
	"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
	"PD19", "PD20", "PD21", "PD22", "PD23",
	"PD24", "PD25", "PD26", "PD27";
	function = "lcd0";
	};

	lcd_rgb666_pins: lcd-rgb666-pins {
	pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
	"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
	"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
	"PD24", "PD25", "PD26", "PD27";
	function = "lcd0";
	};

	mmc0_pins: mmc0-pins {
	pins = "PF0", "PF1", "PF2", "PF3",
	"PF4", "PF5";
	function = "mmc0";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
	pins = "PC6", "PC7", "PC8", "PC9",
	"PC10", "PC11";
	function = "mmc2";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc2_8bit_pins: mmc2-8bit-pins {
	pins = "PC6", "PC7", "PC8", "PC9",
	"PC10", "PC11", "PC12", "PC13",
	"PC14", "PC15";
	function = "mmc2";
	drive-strength = <30>;
	bias-pull-up;
	};

	nand_pins: nand-pins {
	pins = "PC0", "PC1", "PC2",
	"PC5", "PC8", "PC9", "PC10",
	"PC11", "PC12", "PC13", "PC14",
	"PC15";
	function = "nand0";
	};

	nand_cs0_pin: nand-cs0-pin {
	pins = "PC4";
	function = "nand0";
	};

	nand_rb0_pin: nand-rb0-pin {
	pins = "PC6";
	function = "nand0";
	};

	pwm0_pin: pwm0-pin {
	pins = "PB2";
	function = "pwm";
	};

	spi2_pe_pins: spi2-pe-pins {
	pins = "PE1", "PE2", "PE3";
	function = "spi2";
	};

	spi2_cs0_pe_pin: spi2-cs0-pe-pin {
	pins = "PE0";
	function = "spi2";
	};

	uart1_pe_pins: uart1-pe-pins {
	pins = "PE10", "PE11";
	function = "uart1";
	};

	uart1_pg_pins: uart1-pg-pins {
	pins = "PG3", "PG4";
	function = "uart1";
	};

	uart2_pd_pins: uart2-pd-pins {
	pins = "PD2", "PD3";
	function = "uart2";
	};

	uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins {
	pins = "PD4", "PD5";
	function = "uart2";
	};

	uart3_pg_pins: uart3-pg-pins {
	pins = "PG9", "PG10";
	function = "uart3";
	};

	uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
	pins = "PG11", "PG12";
	function = "uart3";
	};
	};

	timer@1c20c00 {
	compatible = "allwinner,sun4i-a10-timer";
	reg = <0x01c20c00 0x90>;
	interrupts = <22>,
	<23>,
	<24>,
	<25>,
	<67>,
	<68>;
	clocks = <&ccu CLK_HOSC>;
	};

	wdt: watchdog@1c20c90 {
	compatible = "allwinner,sun4i-a10-wdt";
	reg = <0x01c20c90 0x10>;
	interrupts = <24>;
	clocks = <&osc24M>;
	};

	ir0: ir@1c21800 {
	compatible = "allwinner,sun4i-a10-ir";
	clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
	clock-names = "apb", "ir";
	interrupts = <5>;
	reg = <0x01c21800 0x40>;
	status = "disabled";
	};

	lradc: lradc@1c22800 {
	compatible = "allwinner,sun4i-a10-lradc-keys";
	reg = <0x01c22800 0x100>;
	interrupts = <31>;
	status = "disabled";
	};

	codec: codec@1c22c00 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun4i-a10-codec";
	reg = <0x01c22c00 0x40>;
	interrupts = <30>;
	clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
	clock-names = "apb", "codec";
	dmas = <&dma SUN4I_DMA_NORMAL 19>,
	<&dma SUN4I_DMA_NORMAL 19>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	sid: eeprom@1c23800 {
	compatible = "allwinner,sun4i-a10-sid";
	reg = <0x01c23800 0x10>;
	};

	rtp: rtp@1c25000 {
	compatible = "allwinner,sun5i-a13-ts";
	reg = <0x01c25000 0x100>;
	interrupts = <29>;
	#thermal-sensor-cells = <0>;
	};

	uart0: serial@1c28000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28000 0x400>;
	interrupts = <1>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB1_UART0>;
	status = "disabled";
	};

	uart1: serial@1c28400 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28400 0x400>;
	interrupts = <2>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB1_UART1>;
	status = "disabled";
	};

	uart2: serial@1c28800 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28800 0x400>;
	interrupts = <3>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB1_UART2>;
	status = "disabled";
	};

	uart3: serial@1c28c00 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28c00 0x400>;
	interrupts = <4>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB1_UART3>;
	status = "disabled";
	};

	i2c0: i2c@1c2ac00 {
	compatible = "allwinner,sun4i-a10-i2c";
	reg = <0x01c2ac00 0x400>;
	interrupts = <7>;
	clocks = <&ccu CLK_APB1_I2C0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c1: i2c@1c2b000 {
	compatible = "allwinner,sun4i-a10-i2c";
	reg = <0x01c2b000 0x400>;
	interrupts = <8>;
	clocks = <&ccu CLK_APB1_I2C1>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c2: i2c@1c2b400 {
	compatible = "allwinner,sun4i-a10-i2c";
	reg = <0x01c2b400 0x400>;
	interrupts = <9>;
	clocks = <&ccu CLK_APB1_I2C2>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	timer@1c60000 {
	compatible = "allwinner,sun5i-a13-hstimer";
	reg = <0x01c60000 0x1000>;
	interrupts = <82>, <83>;
	clocks = <&ccu CLK_AHB_HSTIMER>;
	};

	fe0: display-frontend@1e00000 {
	compatible = "allwinner,sun5i-a13-display-frontend";
	reg = <0x01e00000 0x20000>;
	interrupts = <47>;
	clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
	<&ccu CLK_DRAM_DE_FE>;
	clock-names = "ahb", "mod",
	"ram";
	resets = <&ccu RST_DE_FE>;
	interconnects = <&mbus 19>;
	interconnect-names = "dma-mem";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	fe0_out: port@1 {
	reg = <1>;

	fe0_out_be0: endpoint {
	remote-endpoint = <&be0_in_fe0>;
	};
	};
	};
	};

	be0: display-backend@1e60000 {
	compatible = "allwinner,sun5i-a13-display-backend";
	reg = <0x01e60000 0x10000>;
	interrupts = <47>;
	clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
	<&ccu CLK_DRAM_DE_BE>;
	clock-names = "ahb", "mod",
	"ram";
	resets = <&ccu RST_DE_BE>;
	interconnects = <&mbus 18>;
	interconnect-names = "dma-mem";
	status = "disabled";

	- assigned-clocks = <&ccu CLK_DE_BE>;
	- assigned-clock-rates = <300000000>;
	-
	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	be0_in: port@0 {
	reg = <0>;

	be0_in_fe0: endpoint {
	remote-endpoint = <&fe0_out_be0>;
	};
	};

	be0_out: port@1 {
	reg = <1>;

	be0_out_tcon0: endpoint {
	remote-endpoint = <&tcon0_in_be0>;
	};
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/sun6i-a31.dtsi b/sys/gnu/dts/arm/sun6i-a31.dtsi
	index 7762fbd9a133..f3425a66fc0a 100644
	--- a/sys/gnu/dts/arm/sun6i-a31.dtsi
	+++ b/sys/gnu/dts/arm/sun6i-a31.dtsi
	@@ -1,1433 +1,1421 @@
	/*
	* Copyright 2013 Maxime Ripard
	*
	* Maxime Ripard <maxime.ripard@free-electrons.com>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/thermal/thermal.h>

	#include <dt-bindings/clock/sun6i-a31-ccu.h>
	#include <dt-bindings/reset/sun6i-a31-ccu.h>

	/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
	ethernet0 = &gmac;
	};

	chosen {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	simplefb_hdmi: framebuffer-lcd0-hdmi {
	compatible = "allwinner,simple-framebuffer",
	"simple-framebuffer";
	allwinner,pipeline = "de_be0-lcd0-hdmi";
	clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
	<&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
	<&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
	<&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
	status = "disabled";
	};

	simplefb_lcd: framebuffer-lcd0 {
	compatible = "allwinner,simple-framebuffer",
	"simple-framebuffer";
	allwinner,pipeline = "de_be0-lcd0";
	clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
	<&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
	<&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
	status = "disabled";
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	clock-frequency = <24000000>;
	arm,cpu-registers-not-fw-configured;
	};

	cpus {
	enable-method = "allwinner,sun6i-a31";
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <0>;
	clocks = <&ccu CLK_CPU>;
	clock-latency = <244144>; /* 8 32k periods */
	operating-points = <
	/* kHz uV */
	1008000 1200000
	864000 1200000
	720000 1100000
	480000 1000000
	>;
	#cooling-cells = <2>;
	};

	cpu1: cpu@1 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <1>;
	clocks = <&ccu CLK_CPU>;
	clock-latency = <244144>; /* 8 32k periods */
	operating-points = <
	/* kHz uV */
	1008000 1200000
	864000 1200000
	720000 1100000
	480000 1000000
	>;
	#cooling-cells = <2>;
	};

	cpu2: cpu@2 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <2>;
	clocks = <&ccu CLK_CPU>;
	clock-latency = <244144>; /* 8 32k periods */
	operating-points = <
	/* kHz uV */
	1008000 1200000
	864000 1200000
	720000 1100000
	480000 1000000
	>;
	#cooling-cells = <2>;
	};

	cpu3: cpu@3 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <3>;
	clocks = <&ccu CLK_CPU>;
	clock-latency = <244144>; /* 8 32k periods */
	operating-points = <
	/* kHz uV */
	1008000 1200000
	864000 1200000
	720000 1100000
	480000 1000000
	>;
	#cooling-cells = <2>;
	};
	};

	thermal-zones {
	cpu_thermal {
	/* milliseconds */
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&rtp>;

	cooling-maps {
	map0 {
	trip = <&cpu_alert0>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};

	trips {
	cpu_alert0: cpu_alert0 {
	/* milliCelsius */
	temperature = <70000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu_crit: cpu_crit {
	/* milliCelsius */
	temperature = <100000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};
	};

	pmu {
	compatible = "arm,cortex-a7-pmu";
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
	};

	clocks {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	osc24M: clk-24M {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-accuracy = <50000>;
	clock-output-names = "osc24M";
	};

	osc32k: clk-32k {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	clock-accuracy = <50000>;
	clock-output-names = "ext_osc32k";
	};

	/*
	* The following two are dummy clocks, placeholders
	* used in the gmac_tx clock. The gmac driver will
	* choose one parent depending on the PHY interface
	* mode, using clk_set_rate auto-reparenting.
	*
	* The actual TX clock rate is not controlled by the
	* gmac_tx clock.
	*/
	mii_phy_tx_clk: clk-mii-phy-tx {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <25000000>;
	clock-output-names = "mii_phy_tx";
	};

	gmac_int_tx_clk: clk-gmac-int-tx {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <125000000>;
	clock-output-names = "gmac_int_tx";
	};

	gmac_tx_clk: clk@1c200d0 {
	#clock-cells = <0>;
	compatible = "allwinner,sun7i-a20-gmac-clk";
	reg = <0x01c200d0 0x4>;
	clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
	clock-output-names = "gmac_tx";
	};
	};

	de: display-engine {
	compatible = "allwinner,sun6i-a31-display-engine";
	allwinner,pipelines = <&fe0>, <&fe1>;
	status = "disabled";
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	dma: dma-controller@1c02000 {
	compatible = "allwinner,sun6i-a31-dma";
	reg = <0x01c02000 0x1000>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_DMA>;
	resets = <&ccu RST_AHB1_DMA>;
	#dma-cells = <1>;
	};

	tcon0: lcd-controller@1c0c000 {
	compatible = "allwinner,sun6i-a31-tcon";
	reg = <0x01c0c000 0x1000>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&dma 11>;
	resets = <&ccu RST_AHB1_LCD0>,
	<&ccu RST_AHB1_LVDS>;
	reset-names = "lcd",
	"lvds";
	clocks = <&ccu CLK_AHB1_LCD0>,
	<&ccu CLK_LCD0_CH0>,
	<&ccu CLK_LCD0_CH1>,
	<&ccu 15>;
	clock-names = "ahb",
	"tcon-ch0",
	"tcon-ch1",
	"lvds-alt";
	clock-output-names = "tcon0-pixel-clock";
	#clock-cells = <0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon0_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	tcon0_in_drc0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&drc0_out_tcon0>;
	};

	tcon0_in_drc1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&drc1_out_tcon0>;
	};
	};

	tcon0_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	tcon0_out_hdmi: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&hdmi_in_tcon0>;
	allwinner,tcon-channel = <1>;
	};
	};
	};
	};

	tcon1: lcd-controller@1c0d000 {
	compatible = "allwinner,sun6i-a31-tcon";
	reg = <0x01c0d000 0x1000>;
	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&dma 12>;
	resets = <&ccu RST_AHB1_LCD1>,
	<&ccu RST_AHB1_LVDS>;
	reset-names = "lcd", "lvds";
	clocks = <&ccu CLK_AHB1_LCD1>,
	<&ccu CLK_LCD1_CH0>,
	<&ccu CLK_LCD1_CH1>,
	<&ccu 15>;
	clock-names = "ahb",
	"tcon-ch0",
	"tcon-ch1",
	"lvds-alt";
	clock-output-names = "tcon1-pixel-clock";
	#clock-cells = <0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon1_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	tcon1_in_drc0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&drc0_out_tcon1>;
	};

	tcon1_in_drc1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&drc1_out_tcon1>;
	};
	};

	tcon1_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	tcon1_out_hdmi: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&hdmi_in_tcon1>;
	allwinner,tcon-channel = <1>;
	};
	};
	};
	};

	mmc0: mmc@1c0f000 {
	compatible = "allwinner,sun7i-a20-mmc";
	reg = <0x01c0f000 0x1000>;
	clocks = <&ccu CLK_AHB1_MMC0>,
	<&ccu CLK_MMC0>,
	<&ccu CLK_MMC0_OUTPUT>,
	<&ccu CLK_MMC0_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	resets = <&ccu RST_AHB1_MMC0>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc1: mmc@1c10000 {
	compatible = "allwinner,sun7i-a20-mmc";
	reg = <0x01c10000 0x1000>;
	clocks = <&ccu CLK_AHB1_MMC1>,
	<&ccu CLK_MMC1>,
	<&ccu CLK_MMC1_OUTPUT>,
	<&ccu CLK_MMC1_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	resets = <&ccu RST_AHB1_MMC1>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc2: mmc@1c11000 {
	compatible = "allwinner,sun7i-a20-mmc";
	reg = <0x01c11000 0x1000>;
	clocks = <&ccu CLK_AHB1_MMC2>,
	<&ccu CLK_MMC2>,
	<&ccu CLK_MMC2_OUTPUT>,
	<&ccu CLK_MMC2_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	resets = <&ccu RST_AHB1_MMC2>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc3: mmc@1c12000 {
	compatible = "allwinner,sun7i-a20-mmc";
	reg = <0x01c12000 0x1000>;
	clocks = <&ccu CLK_AHB1_MMC3>,
	<&ccu CLK_MMC3>,
	<&ccu CLK_MMC3_OUTPUT>,
	<&ccu CLK_MMC3_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	resets = <&ccu RST_AHB1_MMC3>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	hdmi: hdmi@1c16000 {
	compatible = "allwinner,sun6i-a31-hdmi";
	reg = <0x01c16000 0x1000>;
	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
	<&ccu CLK_HDMI_DDC>,
	<&ccu CLK_PLL_VIDEO0_2X>,
	<&ccu CLK_PLL_VIDEO1_2X>;
	clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
	resets = <&ccu RST_AHB1_HDMI>;
	dma-names = "ddc-tx", "ddc-rx", "audio-tx";
	dmas = <&dma 13>, <&dma 13>, <&dma 14>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	hdmi_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	hdmi_in_tcon0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&tcon0_out_hdmi>;
	};

	hdmi_in_tcon1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&tcon1_out_hdmi>;
	};
	};

	hdmi_out: port@1 {
	reg = <1>;
	};
	};
	};

	usb_otg: usb@1c19000 {
	compatible = "allwinner,sun6i-a31-musb";
	reg = <0x01c19000 0x0400>;
	clocks = <&ccu CLK_AHB1_OTG>;
	resets = <&ccu RST_AHB1_OTG>;
	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "mc";
	phys = <&usbphy 0>;
	phy-names = "usb";
	extcon = <&usbphy 0>;
	dr_mode = "otg";
	status = "disabled";
	};

	usbphy: phy@1c19400 {
	compatible = "allwinner,sun6i-a31-usb-phy";
	reg = <0x01c19400 0x10>,
	<0x01c1a800 0x4>,
	<0x01c1b800 0x4>;
	reg-names = "phy_ctrl",
	"pmu1",
	"pmu2";
	clocks = <&ccu CLK_USB_PHY0>,
	<&ccu CLK_USB_PHY1>,
	<&ccu CLK_USB_PHY2>;
	clock-names = "usb0_phy",
	"usb1_phy",
	"usb2_phy";
	resets = <&ccu RST_USB_PHY0>,
	<&ccu RST_USB_PHY1>,
	<&ccu RST_USB_PHY2>;
	reset-names = "usb0_reset",
	"usb1_reset",
	"usb2_reset";
	status = "disabled";
	#phy-cells = <1>;
	};

	ehci0: usb@1c1a000 {
	compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
	reg = <0x01c1a000 0x100>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_EHCI0>;
	resets = <&ccu RST_AHB1_EHCI0>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	ohci0: usb@1c1a400 {
	compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
	reg = <0x01c1a400 0x100>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
	resets = <&ccu RST_AHB1_OHCI0>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	ehci1: usb@1c1b000 {
	compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
	reg = <0x01c1b000 0x100>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_EHCI1>;
	resets = <&ccu RST_AHB1_EHCI1>;
	phys = <&usbphy 2>;
	phy-names = "usb";
	status = "disabled";
	};

	ohci1: usb@1c1b400 {
	compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
	reg = <0x01c1b400 0x100>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
	resets = <&ccu RST_AHB1_OHCI1>;
	phys = <&usbphy 2>;
	phy-names = "usb";
	status = "disabled";
	};

	ohci2: usb@1c1c400 {
	compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
	reg = <0x01c1c400 0x100>;
	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
	resets = <&ccu RST_AHB1_OHCI2>;
	status = "disabled";
	};

	ccu: clock@1c20000 {
	compatible = "allwinner,sun6i-a31-ccu";
	reg = <0x01c20000 0x400>;
	clocks = <&osc24M>, <&rtc 0>;
	clock-names = "hosc", "losc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pio: pinctrl@1c20800 {
	compatible = "allwinner,sun6i-a31-pinctrl";
	reg = <0x01c20800 0x400>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>;
	clock-names = "apb", "hosc", "losc";
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <3>;
	#gpio-cells = <3>;

	gmac_gmii_pins: gmac-gmii-pins {
	pins = "PA0", "PA1", "PA2", "PA3",
	"PA4", "PA5", "PA6", "PA7",
	"PA8", "PA9", "PA10", "PA11",
	"PA12", "PA13", "PA14", "PA15",
	"PA16", "PA17", "PA18", "PA19",
	"PA20", "PA21", "PA22", "PA23",
	"PA24", "PA25", "PA26", "PA27";
	function = "gmac";
	/*
	* data lines in GMII mode run at 125MHz and
	* might need a higher signal drive strength
	*/
	drive-strength = <30>;
	};

	gmac_mii_pins: gmac-mii-pins {
	pins = "PA0", "PA1", "PA2", "PA3",
	"PA8", "PA9", "PA11",
	"PA12", "PA13", "PA14", "PA19",
	"PA20", "PA21", "PA22", "PA23",
	"PA24", "PA26", "PA27";
	function = "gmac";
	};

	gmac_rgmii_pins: gmac-rgmii-pins {
	pins = "PA0", "PA1", "PA2", "PA3",
	"PA9", "PA10", "PA11",
	"PA12", "PA13", "PA14", "PA19",
	"PA20", "PA25", "PA26", "PA27";
	function = "gmac";
	/*
	* data lines in RGMII mode use DDR mode
	* and need a higher signal drive strength
	*/
	drive-strength = <40>;
	};

	i2c0_pins: i2c0-pins {
	pins = "PH14", "PH15";
	function = "i2c0";
	};

	i2c1_pins: i2c1-pins {
	pins = "PH16", "PH17";
	function = "i2c1";
	};

	i2c2_pins: i2c2-pins {
	pins = "PH18", "PH19";
	function = "i2c2";
	};

	lcd0_rgb888_pins: lcd0-rgb888-pins {
	pins = "PD0", "PD1", "PD2", "PD3",
	"PD4", "PD5", "PD6", "PD7",
	"PD8", "PD9", "PD10", "PD11",
	"PD12", "PD13", "PD14", "PD15",
	"PD16", "PD17", "PD18", "PD19",
	"PD20", "PD21", "PD22", "PD23",
	"PD24", "PD25", "PD26", "PD27";
	function = "lcd0";
	};

	mmc0_pins: mmc0-pins {
	pins = "PF0", "PF1", "PF2",
	"PF3", "PF4", "PF5";
	function = "mmc0";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc1_pins: mmc1-pins {
	pins = "PG0", "PG1", "PG2", "PG3",
	"PG4", "PG5";
	function = "mmc1";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc2_4bit_pins: mmc2-4bit-pins {
	pins = "PC6", "PC7", "PC8", "PC9",
	"PC10", "PC11";
	function = "mmc2";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
	pins = "PC6", "PC7", "PC8", "PC9",
	"PC10", "PC11", "PC12",
	"PC13", "PC14", "PC15",
	"PC24";
	function = "mmc2";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins {
	pins = "PC6", "PC7", "PC8", "PC9",
	"PC10", "PC11", "PC12",
	"PC13", "PC14", "PC15",
	"PC24";
	function = "mmc3";
	drive-strength = <40>;
	bias-pull-up;
	};

	spdif_tx_pin: spdif-tx-pin {
	pins = "PH28";
	function = "spdif";
	};

	uart0_ph_pins: uart0-ph-pins {
	pins = "PH20", "PH21";
	function = "uart0";
	};
	};

	timer@1c20c00 {
	compatible = "allwinner,sun4i-a10-timer";
	reg = <0x01c20c00 0xa0>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc24M>;
	};

	wdt1: watchdog@1c20ca0 {
	compatible = "allwinner,sun6i-a31-wdt";
	reg = <0x01c20ca0 0x20>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc24M>;
	};

	spdif: spdif@1c21000 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun6i-a31-spdif";
	reg = <0x01c21000 0x400>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
	resets = <&ccu RST_APB1_SPDIF>;
	clock-names = "apb", "spdif";
	dmas = <&dma 2>, <&dma 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2s0: i2s@1c22000 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun6i-a31-i2s";
	reg = <0x01c22000 0x400>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
	resets = <&ccu RST_APB1_DAUDIO0>;
	clock-names = "apb", "mod";
	dmas = <&dma 3>, <&dma 3>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2s1: i2s@1c22400 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun6i-a31-i2s";
	reg = <0x01c22400 0x400>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
	resets = <&ccu RST_APB1_DAUDIO1>;
	clock-names = "apb", "mod";
	dmas = <&dma 4>, <&dma 4>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	lradc: lradc@1c22800 {
	compatible = "allwinner,sun4i-a10-lradc-keys";
	reg = <0x01c22800 0x100>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	rtp: rtp@1c25000 {
	compatible = "allwinner,sun6i-a31-ts";
	reg = <0x01c25000 0x100>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	#thermal-sensor-cells = <0>;
	};

	uart0: serial@1c28000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28000 0x400>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB2_UART0>;
	resets = <&ccu RST_APB2_UART0>;
	dmas = <&dma 6>, <&dma 6>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart1: serial@1c28400 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28400 0x400>;
	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB2_UART1>;
	resets = <&ccu RST_APB2_UART1>;
	dmas = <&dma 7>, <&dma 7>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart2: serial@1c28800 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28800 0x400>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB2_UART2>;
	resets = <&ccu RST_APB2_UART2>;
	dmas = <&dma 8>, <&dma 8>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart3: serial@1c28c00 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28c00 0x400>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB2_UART3>;
	resets = <&ccu RST_APB2_UART3>;
	dmas = <&dma 9>, <&dma 9>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart4: serial@1c29000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c29000 0x400>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB2_UART4>;
	resets = <&ccu RST_APB2_UART4>;
	dmas = <&dma 10>, <&dma 10>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart5: serial@1c29400 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c29400 0x400>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB2_UART5>;
	resets = <&ccu RST_APB2_UART5>;
	dmas = <&dma 22>, <&dma 22>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c0: i2c@1c2ac00 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2ac00 0x400>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB2_I2C0>;
	resets = <&ccu RST_APB2_I2C0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c1: i2c@1c2b000 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2b000 0x400>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB2_I2C1>;
	resets = <&ccu RST_APB2_I2C1>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c2: i2c@1c2b400 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2b400 0x400>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB2_I2C2>;
	resets = <&ccu RST_APB2_I2C2>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c3: i2c@1c2b800 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2b800 0x400>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB2_I2C3>;
	resets = <&ccu RST_APB2_I2C3>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	gmac: ethernet@1c30000 {
	compatible = "allwinner,sun7i-a20-gmac";
	reg = <0x01c30000 0x1054>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
	clock-names = "stmmaceth", "allwinner_gmac_tx";
	resets = <&ccu RST_AHB1_EMAC>;
	reset-names = "stmmaceth";
	snps,pbl = <2>;
	snps,fixed-burst;
	snps,force_sf_dma_mode;
	status = "disabled";

	mdio: mdio {
	compatible = "snps,dwmac-mdio";
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	crypto: crypto-engine@1c15000 {
	compatible = "allwinner,sun6i-a31-crypto",
	"allwinner,sun4i-a10-crypto";
	reg = <0x01c15000 0x1000>;
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
	clock-names = "ahb", "mod";
	resets = <&ccu RST_AHB1_SS>;
	reset-names = "ahb";
	};

	codec: codec@1c22c00 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun6i-a31-codec";
	reg = <0x01c22c00 0x400>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
	clock-names = "apb", "codec";
	resets = <&ccu RST_APB1_CODEC>;
	dmas = <&dma 15>, <&dma 15>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	timer@1c60000 {
	compatible = "allwinner,sun6i-a31-hstimer",
	"allwinner,sun7i-a20-hstimer";
	reg = <0x01c60000 0x1000>;
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_HSTIMER>;
	resets = <&ccu RST_AHB1_HSTIMER>;
	};

	spi0: spi@1c68000 {
	compatible = "allwinner,sun6i-a31-spi";
	reg = <0x01c68000 0x1000>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
	clock-names = "ahb", "mod";
	dmas = <&dma 23>, <&dma 23>;
	dma-names = "rx", "tx";
	resets = <&ccu RST_AHB1_SPI0>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	spi1: spi@1c69000 {
	compatible = "allwinner,sun6i-a31-spi";
	reg = <0x01c69000 0x1000>;
	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
	clock-names = "ahb", "mod";
	dmas = <&dma 24>, <&dma 24>;
	dma-names = "rx", "tx";
	resets = <&ccu RST_AHB1_SPI1>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	spi2: spi@1c6a000 {
	compatible = "allwinner,sun6i-a31-spi";
	reg = <0x01c6a000 0x1000>;
	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
	clock-names = "ahb", "mod";
	dmas = <&dma 25>, <&dma 25>;
	dma-names = "rx", "tx";
	resets = <&ccu RST_AHB1_SPI2>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	spi3: spi@1c6b000 {
	compatible = "allwinner,sun6i-a31-spi";
	reg = <0x01c6b000 0x1000>;
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
	clock-names = "ahb", "mod";
	dmas = <&dma 26>, <&dma 26>;
	dma-names = "rx", "tx";
	resets = <&ccu RST_AHB1_SPI3>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	gic: interrupt-controller@1c81000 {
	compatible = "arm,gic-400";
	reg = <0x01c81000 0x1000>,
	<0x01c82000 0x2000>,
	<0x01c84000 0x2000>,
	<0x01c86000 0x2000>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	fe0: display-frontend@1e00000 {
	compatible = "allwinner,sun6i-a31-display-frontend";
	reg = <0x01e00000 0x20000>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
	<&ccu CLK_DRAM_FE0>;
	clock-names = "ahb", "mod",
	"ram";
	resets = <&ccu RST_AHB1_FE0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	fe0_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	fe0_out_be0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&be0_in_fe0>;
	};

	fe0_out_be1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&be1_in_fe0>;
	};
	};
	};
	};

	fe1: display-frontend@1e20000 {
	compatible = "allwinner,sun6i-a31-display-frontend";
	reg = <0x01e20000 0x20000>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
	<&ccu CLK_DRAM_FE1>;
	clock-names = "ahb", "mod",
	"ram";
	resets = <&ccu RST_AHB1_FE1>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	fe1_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	fe1_out_be0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&be0_in_fe1>;
	};

	fe1_out_be1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&be1_in_fe1>;
	};
	};
	};
	};

	be1: display-backend@1e40000 {
	compatible = "allwinner,sun6i-a31-display-backend";
	reg = <0x01e40000 0x10000>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
	<&ccu CLK_DRAM_BE1>;
	clock-names = "ahb", "mod",
	"ram";
	resets = <&ccu RST_AHB1_BE1>;

	- assigned-clocks = <&ccu CLK_BE1>;
	- assigned-clock-rates = <300000000>;
	-
	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	be1_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	be1_in_fe0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&fe0_out_be1>;
	};

	be1_in_fe1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&fe1_out_be1>;
	};
	};

	be1_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	be1_out_drc1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&drc1_in_be1>;
	};
	};
	};
	};

	drc1: drc@1e50000 {
	compatible = "allwinner,sun6i-a31-drc";
	reg = <0x01e50000 0x10000>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
	<&ccu CLK_DRAM_DRC1>;
	clock-names = "ahb", "mod",
	"ram";
	resets = <&ccu RST_AHB1_DRC1>;

	- assigned-clocks = <&ccu CLK_IEP_DRC1>;
	- assigned-clock-rates = <300000000>;
	-
	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	drc1_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	drc1_in_be1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&be1_out_drc1>;
	};
	};

	drc1_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	drc1_out_tcon0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&tcon0_in_drc1>;
	};

	drc1_out_tcon1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&tcon1_in_drc1>;
	};
	};
	};
	};

	be0: display-backend@1e60000 {
	compatible = "allwinner,sun6i-a31-display-backend";
	reg = <0x01e60000 0x10000>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
	<&ccu CLK_DRAM_BE0>;
	clock-names = "ahb", "mod",
	"ram";
	resets = <&ccu RST_AHB1_BE0>;

	- assigned-clocks = <&ccu CLK_BE0>;
	- assigned-clock-rates = <300000000>;
	-
	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	be0_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	be0_in_fe0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&fe0_out_be0>;
	};

	be0_in_fe1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&fe1_out_be0>;
	};
	};

	be0_out: port@1 {
	reg = <1>;

	be0_out_drc0: endpoint {
	remote-endpoint = <&drc0_in_be0>;
	};
	};
	};
	};

	drc0: drc@1e70000 {
	compatible = "allwinner,sun6i-a31-drc";
	reg = <0x01e70000 0x10000>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
	<&ccu CLK_DRAM_DRC0>;
	clock-names = "ahb", "mod",
	"ram";
	resets = <&ccu RST_AHB1_DRC0>;

	- assigned-clocks = <&ccu CLK_IEP_DRC0>;
	- assigned-clock-rates = <300000000>;
	-
	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	drc0_in: port@0 {
	reg = <0>;

	drc0_in_be0: endpoint {
	remote-endpoint = <&be0_out_drc0>;
	};
	};

	drc0_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	drc0_out_tcon0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&tcon0_in_drc0>;
	};

	drc0_out_tcon1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&tcon1_in_drc0>;
	};
	};
	};
	};

	rtc: rtc@1f00000 {
	#clock-cells = <1>;
	compatible = "allwinner,sun6i-a31-rtc";
	reg = <0x01f00000 0x54>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc32k>;
	clock-output-names = "osc32k";
	};

	nmi_intc: interrupt-controller@1f00c00 {
	compatible = "allwinner,sun6i-a31-r-intc";
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x01f00c00 0x400>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	};

	prcm@1f01400 {
	compatible = "allwinner,sun6i-a31-prcm";
	reg = <0x01f01400 0x200>;

	ar100: ar100_clk {
	compatible = "allwinner,sun6i-a31-ar100-clk";
	#clock-cells = <0>;
	clocks = <&rtc 0>, <&osc24M>,
	<&ccu CLK_PLL_PERIPH>,
	<&ccu CLK_PLL_PERIPH>;
	clock-output-names = "ar100";
	};

	ahb0: ahb0_clk {
	compatible = "fixed-factor-clock";
	#clock-cells = <0>;
	clock-div = <1>;
	clock-mult = <1>;
	clocks = <&ar100>;
	clock-output-names = "ahb0";
	};

	apb0: apb0_clk {
	compatible = "allwinner,sun6i-a31-apb0-clk";
	#clock-cells = <0>;
	clocks = <&ahb0>;
	clock-output-names = "apb0";
	};

	apb0_gates: apb0_gates_clk {
	compatible = "allwinner,sun6i-a31-apb0-gates-clk";
	#clock-cells = <1>;
	clocks = <&apb0>;
	clock-output-names = "apb0_pio", "apb0_ir",
	"apb0_timer", "apb0_p2wi",
	"apb0_uart", "apb0_1wire",
	"apb0_i2c";
	};

	ir_clk: ir_clk {
	#clock-cells = <0>;
	compatible = "allwinner,sun4i-a10-mod0-clk";
	clocks = <&rtc 0>, <&osc24M>;
	clock-output-names = "ir";
	};

	apb0_rst: apb0_rst {
	compatible = "allwinner,sun6i-a31-clock-reset";
	#reset-cells = <1>;
	};
	};

	cpucfg@1f01c00 {
	compatible = "allwinner,sun6i-a31-cpuconfig";
	reg = <0x01f01c00 0x300>;
	};

	ir: ir@1f02000 {
	compatible = "allwinner,sun6i-a31-ir";
	clocks = <&apb0_gates 1>, <&ir_clk>;
	clock-names = "apb", "ir";
	resets = <&apb0_rst 1>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x01f02000 0x40>;
	status = "disabled";
	};

	r_pio: pinctrl@1f02c00 {
	compatible = "allwinner,sun6i-a31-r-pinctrl";
	reg = <0x01f02c00 0x400>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
	clock-names = "apb", "hosc", "losc";
	resets = <&apb0_rst 0>;
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <3>;
	#gpio-cells = <3>;

	s_ir_rx_pin: s-ir-rx-pin {
	pins = "PL4";
	function = "s_ir";
	};

	s_p2wi_pins: s-p2wi-pins {
	pins = "PL0", "PL1";
	function = "s_p2wi";
	};
	};

	p2wi: i2c@1f03400 {
	compatible = "allwinner,sun6i-a31-p2wi";
	reg = <0x01f03400 0x400>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&apb0_gates 3>;
	clock-frequency = <100000>;
	resets = <&apb0_rst 3>;
	pinctrl-names = "default";
	pinctrl-0 = <&s_p2wi_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/sun7i-a20-linutronix-testbox-v2.dts b/sys/gnu/dts/arm/sun7i-a20-linutronix-testbox-v2.dts
	new file mode 100644
	index 000000000000..da5a2eea4ce3
	--- /dev/null
	+++ b/sys/gnu/dts/arm/sun7i-a20-linutronix-testbox-v2.dts
	@@ -0,0 +1,47 @@
	+// SPDX-License-Identifier: GPL-2.0-or-later
	+/*
	+ * Copyright 2020 Linutronix GmbH
	+ * Author: Benedikt Spranger <b.spranger@linutronix.de>
	+ */
	+
	+/dts-v1/;
	+#include "sun7i-a20-lamobo-r1.dts"
	+
	+/ {
	+ model = "Lamobo R1";
	+ compatible = "linutronix,testbox-v2", "lamobo,lamobo-r1", "allwinner,sun7i-a20";
	+
	+ leds {
	+ led-opto1 {
	+ label = "lamobo_r1:opto:powerswitch";
	+ gpios = <&pio 7 3 GPIO_ACTIVE_HIGH>;
	+ };
	+
	+ led-opto2 {
	+ label = "lamobo_r1:opto:relay";
	+ gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>;
	+ };
	+ };
	+};
	+
	+&i2c2 {
	+ clock-frequency = <100000>;
	+ status = "okay";
	+
	+ eeprom: eeprom@50 {
	+ compatible = "atmel,24c08";
	+ reg = <0x50>;
	+ status = "okay";
	+ };
	+
	+ atecc508a@60 {
	+ compatible = "atmel,atecc508a";
	+ reg = <0x60>;
	+ };
	+};
	+
	+&can0 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&can_ph_pins>;
	+ status = "okay";
	+};
	diff --git a/sys/gnu/dts/arm/sun7i-a20.dtsi b/sys/gnu/dts/arm/sun7i-a20.dtsi
	index 92b5be97085d..ffe1d10a1a84 100644
	--- a/sys/gnu/dts/arm/sun7i-a20.dtsi
	+++ b/sys/gnu/dts/arm/sun7i-a20.dtsi
	@@ -1,1695 +1,1712 @@
	/*
	* Copyright 2013 Maxime Ripard
	*
	* Maxime Ripard <maxime.ripard@free-electrons.com>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/thermal/thermal.h>
	#include <dt-bindings/dma/sun4i-a10.h>
	#include <dt-bindings/clock/sun7i-a20-ccu.h>
	#include <dt-bindings/reset/sun4i-a10-ccu.h>
	+#include <dt-bindings/pinctrl/sun4i-a10.h>

	/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
	ethernet0 = &gmac;
	};

	chosen {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	framebuffer-lcd0-hdmi {
	compatible = "allwinner,simple-framebuffer",
	"simple-framebuffer";
	allwinner,pipeline = "de_be0-lcd0-hdmi";
	clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
	<&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
	<&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
	<&ccu CLK_HDMI>;
	status = "disabled";
	};

	framebuffer-lcd0 {
	compatible = "allwinner,simple-framebuffer",
	"simple-framebuffer";
	allwinner,pipeline = "de_be0-lcd0";
	clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
	<&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
	<&ccu CLK_DRAM_DE_BE0>;
	status = "disabled";
	};

	framebuffer-lcd0-tve0 {
	compatible = "allwinner,simple-framebuffer",
	"simple-framebuffer";
	allwinner,pipeline = "de_be0-lcd0-tve0";
	clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
	<&ccu CLK_AHB_DE_BE0>,
	<&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
	<&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
	status = "disabled";
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <0>;
	clocks = <&ccu CLK_CPU>;
	clock-latency = <244144>; /* 8 32k periods */
	operating-points = <
	/* kHz uV */
	960000 1400000
	912000 1400000
	864000 1300000
	720000 1200000
	528000 1100000
	312000 1000000
	144000 1000000
	>;
	#cooling-cells = <2>;
	};

	cpu1: cpu@1 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <1>;
	clocks = <&ccu CLK_CPU>;
	clock-latency = <244144>; /* 8 32k periods */
	operating-points = <
	/* kHz uV */
	960000 1400000
	912000 1400000
	864000 1300000
	720000 1200000
	528000 1100000
	312000 1000000
	144000 1000000
	>;
	#cooling-cells = <2>;
	};
	};

	thermal-zones {
	cpu_thermal {
	/* milliseconds */
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&rtp>;

	cooling-maps {
	map0 {
	trip = <&cpu_alert0>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};

	trips {
	cpu_alert0: cpu_alert0 {
	/* milliCelsius */
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu_crit: cpu_crit {
	/* milliCelsius */
	temperature = <100000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};
	};

	reserved-memory {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
	default-pool {
	compatible = "shared-dma-pool";
	size = <0x6000000>;
	alloc-ranges = <0x4a000000 0x6000000>;
	reusable;
	linux,cma-default;
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
	compatible = "arm,cortex-a7-pmu";
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
	};

	clocks {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	osc24M: clk-24M {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-output-names = "osc24M";
	};

	osc32k: clk-32k {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	clock-output-names = "osc32k";
	};

	/*
	* The following two are dummy clocks, placeholders
	* used in the gmac_tx clock. The gmac driver will
	* choose one parent depending on the PHY interface
	* mode, using clk_set_rate auto-reparenting.
	*
	* The actual TX clock rate is not controlled by the
	* gmac_tx clock.
	*/
	mii_phy_tx_clk: clk-mii-phy-tx {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <25000000>;
	clock-output-names = "mii_phy_tx";
	};

	gmac_int_tx_clk: clk-gmac-int-tx {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <125000000>;
	clock-output-names = "gmac_int_tx";
	};

	gmac_tx_clk: clk@1c20164 {
	#clock-cells = <0>;
	compatible = "allwinner,sun7i-a20-gmac-clk";
	reg = <0x01c20164 0x4>;
	clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
	clock-output-names = "gmac_tx";
	};
	};


	de: display-engine {
	compatible = "allwinner,sun7i-a20-display-engine";
	allwinner,pipelines = <&fe0>, <&fe1>;
	status = "disabled";
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	system-control@1c00000 {
	compatible = "allwinner,sun7i-a20-system-control",
	"allwinner,sun4i-a10-system-control";
	reg = <0x01c00000 0x30>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	sram_a: sram@0 {
	compatible = "mmio-sram";
	reg = <0x00000000 0xc000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x00000000 0xc000>;

	emac_sram: sram-section@8000 {
	compatible = "allwinner,sun7i-a20-sram-a3-a4",
	"allwinner,sun4i-a10-sram-a3-a4";
	reg = <0x8000 0x4000>;
	status = "disabled";
	};
	};

	sram_d: sram@10000 {
	compatible = "mmio-sram";
	reg = <0x00010000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x00010000 0x1000>;

	otg_sram: sram-section@0 {
	compatible = "allwinner,sun7i-a20-sram-d",
	"allwinner,sun4i-a10-sram-d";
	reg = <0x0000 0x1000>;
	status = "disabled";
	};
	};

	sram_c: sram@1d00000 {
	compatible = "mmio-sram";
	reg = <0x01d00000 0xd0000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x01d00000 0xd0000>;

	ve_sram: sram-section@0 {
	compatible = "allwinner,sun7i-a20-sram-c1",
	"allwinner,sun4i-a10-sram-c1";
	reg = <0x000000 0x80000>;
	};
	};
	};

	nmi_intc: interrupt-controller@1c00030 {
	compatible = "allwinner,sun7i-a20-sc-nmi";
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x01c00030 0x0c>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	};

	dma: dma-controller@1c02000 {
	compatible = "allwinner,sun4i-a10-dma";
	reg = <0x01c02000 0x1000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_DMA>;
	#dma-cells = <2>;
	};

	nfc: nand-controller@1c03000 {
	compatible = "allwinner,sun4i-a10-nand";
	reg = <0x01c03000 0x1000>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
	clock-names = "ahb", "mod";
	dmas = <&dma SUN4I_DMA_DEDICATED 3>;
	dma-names = "rxtx";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	spi0: spi@1c05000 {
	compatible = "allwinner,sun4i-a10-spi";
	reg = <0x01c05000 0x1000>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
	clock-names = "ahb", "mod";
	dmas = <&dma SUN4I_DMA_DEDICATED 27>,
	<&dma SUN4I_DMA_DEDICATED 26>;
	dma-names = "rx", "tx";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	num-cs = <4>;
	};

	spi1: spi@1c06000 {
	compatible = "allwinner,sun4i-a10-spi";
	reg = <0x01c06000 0x1000>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
	clock-names = "ahb", "mod";
	dmas = <&dma SUN4I_DMA_DEDICATED 9>,
	<&dma SUN4I_DMA_DEDICATED 8>;
	dma-names = "rx", "tx";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	num-cs = <1>;
	};

	csi0: csi@1c09000 {
	compatible = "allwinner,sun7i-a20-csi0";
	reg = <0x01c09000 0x1000>;
	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
	clock-names = "bus", "isp", "ram";
	resets = <&ccu RST_CSI0>;
	status = "disabled";
	};

	emac: ethernet@1c0b000 {
	compatible = "allwinner,sun4i-a10-emac";
	reg = <0x01c0b000 0x1000>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_EMAC>;
	allwinner,sram = <&emac_sram 1>;
	status = "disabled";
	};

	mdio: mdio@1c0b080 {
	compatible = "allwinner,sun4i-a10-mdio";
	reg = <0x01c0b080 0x14>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	tcon0: lcd-controller@1c0c000 {
	- compatible = "allwinner,sun7i-a20-tcon";
	+ compatible = "allwinner,sun7i-a20-tcon0",
	+ "allwinner,sun7i-a20-tcon";
	reg = <0x01c0c000 0x1000>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	- resets = <&ccu RST_TCON0>;
	- reset-names = "lcd";
	+ resets = <&ccu RST_TCON0>, <&ccu RST_LVDS>;
	+ reset-names = "lcd", "lvds";
	clocks = <&ccu CLK_AHB_LCD0>,
	<&ccu CLK_TCON0_CH0>,
	<&ccu CLK_TCON0_CH1>;
	clock-names = "ahb",
	"tcon-ch0",
	"tcon-ch1";
	clock-output-names = "tcon0-pixel-clock";
	#clock-cells = <0>;
	dmas = <&dma SUN4I_DMA_DEDICATED 14>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon0_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	tcon0_in_be0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&be0_out_tcon0>;
	};

	tcon0_in_be1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&be1_out_tcon0>;
	};
	};

	tcon0_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	tcon0_out_hdmi: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&hdmi_in_tcon0>;
	allwinner,tcon-channel = <1>;
	};
	};
	};
	};

	tcon1: lcd-controller@1c0d000 {
	- compatible = "allwinner,sun7i-a20-tcon";
	+ compatible = "allwinner,sun7i-a20-tcon1",
	+ "allwinner,sun7i-a20-tcon";
	reg = <0x01c0d000 0x1000>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&ccu RST_TCON1>;
	reset-names = "lcd";
	clocks = <&ccu CLK_AHB_LCD1>,
	<&ccu CLK_TCON1_CH0>,
	<&ccu CLK_TCON1_CH1>;
	clock-names = "ahb",
	"tcon-ch0",
	"tcon-ch1";
	clock-output-names = "tcon1-pixel-clock";
	#clock-cells = <0>;
	dmas = <&dma SUN4I_DMA_DEDICATED 15>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon1_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	tcon1_in_be0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&be0_out_tcon1>;
	};

	tcon1_in_be1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&be1_out_tcon1>;
	};
	};

	tcon1_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	tcon1_out_hdmi: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&hdmi_in_tcon1>;
	allwinner,tcon-channel = <1>;
	};
	};
	};
	};

	video-codec@1c0e000 {
	compatible = "allwinner,sun7i-a20-video-engine";
	reg = <0x01c0e000 0x1000>;
	clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
	<&ccu CLK_DRAM_VE>;
	clock-names = "ahb", "mod", "ram";
	resets = <&ccu RST_VE>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	allwinner,sram = <&ve_sram 1>;
	};

	mmc0: mmc@1c0f000 {
	compatible = "allwinner,sun7i-a20-mmc";
	reg = <0x01c0f000 0x1000>;
	clocks = <&ccu CLK_AHB_MMC0>,
	<&ccu CLK_MMC0>,
	<&ccu CLK_MMC0_OUTPUT>,
	<&ccu CLK_MMC0_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc1: mmc@1c10000 {
	compatible = "allwinner,sun7i-a20-mmc";
	reg = <0x01c10000 0x1000>;
	clocks = <&ccu CLK_AHB_MMC1>,
	<&ccu CLK_MMC1>,
	<&ccu CLK_MMC1_OUTPUT>,
	<&ccu CLK_MMC1_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc2: mmc@1c11000 {
	compatible = "allwinner,sun7i-a20-mmc";
	reg = <0x01c11000 0x1000>;
	clocks = <&ccu CLK_AHB_MMC2>,
	<&ccu CLK_MMC2>,
	<&ccu CLK_MMC2_OUTPUT>,
	<&ccu CLK_MMC2_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc3: mmc@1c12000 {
	compatible = "allwinner,sun7i-a20-mmc";
	reg = <0x01c12000 0x1000>;
	clocks = <&ccu CLK_AHB_MMC3>,
	<&ccu CLK_MMC3>,
	<&ccu CLK_MMC3_OUTPUT>,
	<&ccu CLK_MMC3_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc3_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	usb_otg: usb@1c13000 {
	compatible = "allwinner,sun4i-a10-musb";
	reg = <0x01c13000 0x0400>;
	clocks = <&ccu CLK_AHB_OTG>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "mc";
	phys = <&usbphy 0>;
	phy-names = "usb";
	extcon = <&usbphy 0>;
	allwinner,sram = <&otg_sram 1>;
	dr_mode = "otg";
	status = "disabled";
	};

	usbphy: phy@1c13400 {
	#phy-cells = <1>;
	compatible = "allwinner,sun7i-a20-usb-phy";
	reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
	reg-names = "phy_ctrl", "pmu1", "pmu2";
	clocks = <&ccu CLK_USB_PHY>;
	clock-names = "usb_phy";
	resets = <&ccu RST_USB_PHY0>,
	<&ccu RST_USB_PHY1>,
	<&ccu RST_USB_PHY2>;
	reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
	status = "disabled";
	};

	ehci0: usb@1c14000 {
	compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
	reg = <0x01c14000 0x100>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_EHCI0>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	ohci0: usb@1c14400 {
	compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
	reg = <0x01c14400 0x100>;
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	crypto: crypto-engine@1c15000 {
	compatible = "allwinner,sun7i-a20-crypto",
	"allwinner,sun4i-a10-crypto";
	reg = <0x01c15000 0x1000>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
	clock-names = "ahb", "mod";
	};

	hdmi: hdmi@1c16000 {
	compatible = "allwinner,sun7i-a20-hdmi",
	"allwinner,sun5i-a10s-hdmi";
	reg = <0x01c16000 0x1000>;
	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
	<&ccu CLK_PLL_VIDEO0_2X>,
	<&ccu CLK_PLL_VIDEO1_2X>;
	clock-names = "ahb", "mod", "pll-0", "pll-1";
	dmas = <&dma SUN4I_DMA_NORMAL 16>,
	<&dma SUN4I_DMA_NORMAL 16>,
	<&dma SUN4I_DMA_DEDICATED 24>;
	dma-names = "ddc-tx", "ddc-rx", "audio-tx";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	hdmi_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	hdmi_in_tcon0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&tcon0_out_hdmi>;
	};

	hdmi_in_tcon1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&tcon1_out_hdmi>;
	};
	};

	hdmi_out: port@1 {
	reg = <1>;
	};
	};
	};

	spi2: spi@1c17000 {
	compatible = "allwinner,sun4i-a10-spi";
	reg = <0x01c17000 0x1000>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
	clock-names = "ahb", "mod";
	dmas = <&dma SUN4I_DMA_DEDICATED 29>,
	<&dma SUN4I_DMA_DEDICATED 28>;
	dma-names = "rx", "tx";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	num-cs = <1>;
	};

	ahci: sata@1c18000 {
	compatible = "allwinner,sun4i-a10-ahci";
	reg = <0x01c18000 0x1000>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
	status = "disabled";
	};

	ehci1: usb@1c1c000 {
	compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
	reg = <0x01c1c000 0x100>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_EHCI1>;
	phys = <&usbphy 2>;
	phy-names = "usb";
	status = "disabled";
	};

	ohci1: usb@1c1c400 {
	compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
	reg = <0x01c1c400 0x100>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
	phys = <&usbphy 2>;
	phy-names = "usb";
	status = "disabled";
	};

	csi1: csi@1c1d000 {
	compatible = "allwinner,sun7i-a20-csi1",
	"allwinner,sun4i-a10-csi1";
	reg = <0x01c1d000 0x1000>;
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
	clock-names = "bus", "ram";
	resets = <&ccu RST_CSI1>;
	status = "disabled";
	};

	spi3: spi@1c1f000 {
	compatible = "allwinner,sun4i-a10-spi";
	reg = <0x01c1f000 0x1000>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
	clock-names = "ahb", "mod";
	dmas = <&dma SUN4I_DMA_DEDICATED 31>,
	<&dma SUN4I_DMA_DEDICATED 30>;
	dma-names = "rx", "tx";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	num-cs = <1>;
	};

	ccu: clock@1c20000 {
	compatible = "allwinner,sun7i-a20-ccu";
	reg = <0x01c20000 0x400>;
	clocks = <&osc24M>, <&osc32k>;
	clock-names = "hosc", "losc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pio: pinctrl@1c20800 {
	compatible = "allwinner,sun7i-a20-pinctrl";
	reg = <0x01c20800 0x400>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
	clock-names = "apb", "hosc", "losc";
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <3>;
	#gpio-cells = <3>;

	/omit-if-no-ref/
	can_pa_pins: can-pa-pins {
	pins = "PA16", "PA17";
	function = "can";
	};

	/omit-if-no-ref/
	can_ph_pins: can-ph-pins {
	pins = "PH20", "PH21";
	function = "can";
	};

	/omit-if-no-ref/
	clk_out_a_pin: clk-out-a-pin {
	pins = "PI12";
	function = "clk_out_a";
	};

	/omit-if-no-ref/
	clk_out_b_pin: clk-out-b-pin {
	pins = "PI13";
	function = "clk_out_b";
	};

	/omit-if-no-ref/
	csi0_8bits_pins: csi-8bits-pins {
	pins = "PE0", "PE2", "PE3", "PE4", "PE5",
	"PE6", "PE7", "PE8", "PE9", "PE10",
	"PE11";
	function = "csi0";
	};

	/omit-if-no-ref/
	csi0_clk_pin: csi-clk-pin {
	pins = "PE1";
	function = "csi0";
	};

	/omit-if-no-ref/
	csi1_8bits_pg_pins: csi1-8bits-pg-pins {
	pins = "PG0", "PG2", "PG3", "PG4", "PG5",
	"PG6", "PG7", "PG8", "PG9", "PG10",
	"PG11";
	function = "csi1";
	};

	/omit-if-no-ref/
	csi1_24bits_ph_pins: csi1-24bits-ph-pins {
	pins = "PH0", "PH1", "PH2", "PH3", "PH4",
	"PH5", "PH6", "PH7", "PH8", "PH9",
	"PH10", "PH11", "PH12", "PH13", "PH14",
	"PH15", "PH16", "PH17", "PH18", "PH19",
	"PH20", "PH21", "PH22", "PH23", "PH24",
	"PH25", "PH26", "PH27";
	function = "csi1";
	};

	/omit-if-no-ref/
	csi1_clk_pg_pin: csi1-clk-pg-pin {
	pins = "PG1";
	function = "csi1";
	};

	/omit-if-no-ref/
	emac_pa_pins: emac-pa-pins {
	pins = "PA0", "PA1", "PA2",
	"PA3", "PA4", "PA5", "PA6",
	"PA7", "PA8", "PA9", "PA10",
	"PA11", "PA12", "PA13", "PA14",
	"PA15", "PA16";
	function = "emac";
	};

	/omit-if-no-ref/
	emac_ph_pins: emac-ph-pins {
	pins = "PH8", "PH9", "PH10", "PH11",
	"PH14", "PH15", "PH16", "PH17",
	"PH18", "PH19", "PH20", "PH21",
	"PH22", "PH23", "PH24", "PH25",
	"PH26";
	function = "emac";
	};

	/omit-if-no-ref/
	gmac_mii_pins: gmac-mii-pins {
	pins = "PA0", "PA1", "PA2",
	"PA3", "PA4", "PA5", "PA6",
	"PA7", "PA8", "PA9", "PA10",
	"PA11", "PA12", "PA13", "PA14",
	"PA15", "PA16";
	function = "gmac";
	};

	/omit-if-no-ref/
	gmac_rgmii_pins: gmac-rgmii-pins {
	pins = "PA0", "PA1", "PA2",
	"PA3", "PA4", "PA5", "PA6",
	"PA7", "PA8", "PA10",
	"PA11", "PA12", "PA13",
	"PA15", "PA16";
	function = "gmac";
	/*
	* data lines in RGMII mode use DDR mode
	* and need a higher signal drive strength
	*/
	drive-strength = <40>;
	};

	/omit-if-no-ref/
	i2c0_pins: i2c0-pins {
	pins = "PB0", "PB1";
	function = "i2c0";
	};

	/omit-if-no-ref/
	i2c1_pins: i2c1-pins {
	pins = "PB18", "PB19";
	function = "i2c1";
	};

	/omit-if-no-ref/
	i2c2_pins: i2c2-pins {
	pins = "PB20", "PB21";
	function = "i2c2";
	};

	/omit-if-no-ref/
	i2c3_pins: i2c3-pins {
	pins = "PI0", "PI1";
	function = "i2c3";
	};

	/omit-if-no-ref/
	ir0_rx_pin: ir0-rx-pin {
	pins = "PB4";
	function = "ir0";
	};

	/omit-if-no-ref/
	ir0_tx_pin: ir0-tx-pin {
	pins = "PB3";
	function = "ir0";
	};

	/omit-if-no-ref/
	ir1_rx_pin: ir1-rx-pin {
	pins = "PB23";
	function = "ir1";
	};

	/omit-if-no-ref/
	ir1_tx_pin: ir1-tx-pin {
	pins = "PB22";
	function = "ir1";
	};

	+ /omit-if-no-ref/
	+ lcd_lvds0_pins: lcd-lvds0-pins {
	+ pins = "PD0", "PD1", "PD2", "PD3", "PD4",
	+ "PD5", "PD6", "PD7", "PD8", "PD9";
	+ function = "lvds0";
	+ };
	+
	+ /omit-if-no-ref/
	+ lcd_lvds1_pins: lcd-lvds1-pins {
	+ pins = "PD10", "PD11", "PD12", "PD13", "PD14",
	+ "PD15", "PD16", "PD17", "PD18", "PD19";
	+ function = "lvds1";
	+ };
	+
	/omit-if-no-ref/
	mmc0_pins: mmc0-pins {
	pins = "PF0", "PF1", "PF2",
	"PF3", "PF4", "PF5";
	function = "mmc0";
	drive-strength = <30>;
	bias-pull-up;
	};

	/omit-if-no-ref/
	mmc2_pins: mmc2-pins {
	pins = "PC6", "PC7", "PC8",
	"PC9", "PC10", "PC11";
	function = "mmc2";
	drive-strength = <30>;
	bias-pull-up;
	};

	/omit-if-no-ref/
	mmc3_pins: mmc3-pins {
	pins = "PI4", "PI5", "PI6",
	"PI7", "PI8", "PI9";
	function = "mmc3";
	drive-strength = <30>;
	bias-pull-up;
	};

	/omit-if-no-ref/
	ps2_0_pins: ps2-0-pins {
	pins = "PI20", "PI21";
	function = "ps2";
	};

	/omit-if-no-ref/
	ps2_1_ph_pins: ps2-1-ph-pins {
	pins = "PH12", "PH13";
	function = "ps2";
	};

	/omit-if-no-ref/
	pwm0_pin: pwm0-pin {
	pins = "PB2";
	function = "pwm";
	};

	/omit-if-no-ref/
	pwm1_pin: pwm1-pin {
	pins = "PI3";
	function = "pwm";
	};

	/omit-if-no-ref/
	spdif_tx_pin: spdif-tx-pin {
	pins = "PB13";
	function = "spdif";
	bias-pull-up;
	};

	/omit-if-no-ref/
	spi0_pi_pins: spi0-pi-pins {
	pins = "PI11", "PI12", "PI13";
	function = "spi0";
	};

	/omit-if-no-ref/
	spi0_cs0_pi_pin: spi0-cs0-pi-pin {
	pins = "PI10";
	function = "spi0";
	};

	/omit-if-no-ref/
	spi0_cs1_pi_pin: spi0-cs1-pi-pin {
	pins = "PI14";
	function = "spi0";
	};

	/omit-if-no-ref/
	spi1_pi_pins: spi1-pi-pins {
	pins = "PI17", "PI18", "PI19";
	function = "spi1";
	};

	/omit-if-no-ref/
	spi1_cs0_pi_pin: spi1-cs0-pi-pin {
	pins = "PI16";
	function = "spi1";
	};

	/omit-if-no-ref/
	spi2_pb_pins: spi2-pb-pins {
	pins = "PB15", "PB16", "PB17";
	function = "spi2";
	};

	/omit-if-no-ref/
	spi2_cs0_pb_pin: spi2-cs0-pb-pin {
	pins = "PB14";
	function = "spi2";
	};

	/omit-if-no-ref/
	spi2_pc_pins: spi2-pc-pins {
	pins = "PC20", "PC21", "PC22";
	function = "spi2";
	};

	/omit-if-no-ref/
	spi2_cs0_pc_pin: spi2-cs0-pc-pin {
	pins = "PC19";
	function = "spi2";
	};

	/omit-if-no-ref/
	uart0_pb_pins: uart0-pb-pins {
	pins = "PB22", "PB23";
	function = "uart0";
	};

	/omit-if-no-ref/
	uart0_pf_pins: uart0-pf-pins {
	pins = "PF2", "PF4";
	function = "uart0";
	};

	/omit-if-no-ref/
	uart1_pa_pins: uart1-pa-pins {
	pins = "PA10", "PA11";
	function = "uart1";
	};

	/omit-if-no-ref/
	uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins {
	pins = "PA12", "PA13";
	function = "uart1";
	};

	/omit-if-no-ref/
	uart2_pa_pins: uart2-pa-pins {
	pins = "PA2", "PA3";
	function = "uart2";
	};

	/omit-if-no-ref/
	uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins {
	pins = "PA0", "PA1";
	function = "uart2";
	};

	/omit-if-no-ref/
	uart2_pi_pins: uart2-pi-pins {
	pins = "PI18", "PI19";
	function = "uart2";
	};

	/omit-if-no-ref/
	uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
	pins = "PI16", "PI17";
	function = "uart2";
	};

	/omit-if-no-ref/
	uart3_pg_pins: uart3-pg-pins {
	pins = "PG6", "PG7";
	function = "uart3";
	};

	/omit-if-no-ref/
	uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
	pins = "PG8", "PG9";
	function = "uart3";
	};

	/omit-if-no-ref/
	uart3_ph_pins: uart3-ph-pins {
	pins = "PH0", "PH1";
	function = "uart3";
	};

	/omit-if-no-ref/
	uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins {
	pins = "PH2", "PH3";
	function = "uart3";
	};

	/omit-if-no-ref/
	uart4_pg_pins: uart4-pg-pins {
	pins = "PG10", "PG11";
	function = "uart4";
	};

	/omit-if-no-ref/
	uart4_ph_pins: uart4-ph-pins {
	pins = "PH4", "PH5";
	function = "uart4";
	};

	/omit-if-no-ref/
	uart5_ph_pins: uart5-ph-pins {
	pins = "PH6", "PH7";
	function = "uart5";
	};

	/omit-if-no-ref/
	uart5_pi_pins: uart5-pi-pins {
	pins = "PI10", "PI11";
	function = "uart5";
	};

	/omit-if-no-ref/
	uart6_pa_pins: uart6-pa-pins {
	pins = "PA12", "PA13";
	function = "uart6";
	};

	/omit-if-no-ref/
	uart6_pi_pins: uart6-pi-pins {
	pins = "PI12", "PI13";
	function = "uart6";
	};

	/omit-if-no-ref/
	uart7_pa_pins: uart7-pa-pins {
	pins = "PA14", "PA15";
	function = "uart7";
	};

	/omit-if-no-ref/
	uart7_pi_pins: uart7-pi-pins {
	pins = "PI20", "PI21";
	function = "uart7";
	};
	};

	timer@1c20c00 {
	compatible = "allwinner,sun4i-a10-timer";
	reg = <0x01c20c00 0x90>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc24M>;
	};

	wdt: watchdog@1c20c90 {
	compatible = "allwinner,sun4i-a10-wdt";
	reg = <0x01c20c90 0x10>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc24M>;
	};

	rtc: rtc@1c20d00 {
	compatible = "allwinner,sun7i-a20-rtc";
	reg = <0x01c20d00 0x20>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	};

	pwm: pwm@1c20e00 {
	compatible = "allwinner,sun7i-a20-pwm";
	reg = <0x01c20e00 0xc>;
	clocks = <&osc24M>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	spdif: spdif@1c21000 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun4i-a10-spdif";
	reg = <0x01c21000 0x400>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
	clock-names = "apb", "spdif";
	dmas = <&dma SUN4I_DMA_NORMAL 2>,
	<&dma SUN4I_DMA_NORMAL 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	ir0: ir@1c21800 {
	compatible = "allwinner,sun4i-a10-ir";
	clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
	clock-names = "apb", "ir";
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x01c21800 0x40>;
	status = "disabled";
	};

	ir1: ir@1c21c00 {
	compatible = "allwinner,sun4i-a10-ir";
	clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
	clock-names = "apb", "ir";
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x01c21c00 0x40>;
	status = "disabled";
	};

	i2s1: i2s@1c22000 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun4i-a10-i2s";
	reg = <0x01c22000 0x400>;
	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
	clock-names = "apb", "mod";
	dmas = <&dma SUN4I_DMA_NORMAL 4>,
	<&dma SUN4I_DMA_NORMAL 4>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2s0: i2s@1c22400 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun4i-a10-i2s";
	reg = <0x01c22400 0x400>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
	clock-names = "apb", "mod";
	dmas = <&dma SUN4I_DMA_NORMAL 3>,
	<&dma SUN4I_DMA_NORMAL 3>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	lradc: lradc@1c22800 {
	compatible = "allwinner,sun4i-a10-lradc-keys";
	reg = <0x01c22800 0x100>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	codec: codec@1c22c00 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun7i-a20-codec";
	reg = <0x01c22c00 0x40>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
	clock-names = "apb", "codec";
	dmas = <&dma SUN4I_DMA_NORMAL 19>,
	<&dma SUN4I_DMA_NORMAL 19>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	sid: eeprom@1c23800 {
	compatible = "allwinner,sun7i-a20-sid";
	reg = <0x01c23800 0x200>;
	};

	i2s2: i2s@1c24400 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun4i-a10-i2s";
	reg = <0x01c24400 0x400>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
	clock-names = "apb", "mod";
	dmas = <&dma SUN4I_DMA_NORMAL 6>,
	<&dma SUN4I_DMA_NORMAL 6>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	rtp: rtp@1c25000 {
	compatible = "allwinner,sun5i-a13-ts";
	reg = <0x01c25000 0x100>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	#thermal-sensor-cells = <0>;
	};

	uart0: serial@1c28000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28000 0x400>;
	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB1_UART0>;
	status = "disabled";
	};

	uart1: serial@1c28400 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28400 0x400>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB1_UART1>;
	status = "disabled";
	};

	uart2: serial@1c28800 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28800 0x400>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB1_UART2>;
	status = "disabled";
	};

	uart3: serial@1c28c00 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28c00 0x400>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB1_UART3>;
	status = "disabled";
	};

	uart4: serial@1c29000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c29000 0x400>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB1_UART4>;
	status = "disabled";
	};

	uart5: serial@1c29400 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c29400 0x400>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB1_UART5>;
	status = "disabled";
	};

	uart6: serial@1c29800 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c29800 0x400>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB1_UART6>;
	status = "disabled";
	};

	uart7: serial@1c29c00 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c29c00 0x400>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_APB1_UART7>;
	status = "disabled";
	};

	ps20: ps2@1c2a000 {
	compatible = "allwinner,sun4i-a10-ps2";
	reg = <0x01c2a000 0x400>;
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB1_PS20>;
	status = "disabled";
	};

	ps21: ps2@1c2a400 {
	compatible = "allwinner,sun4i-a10-ps2";
	reg = <0x01c2a400 0x400>;
	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB1_PS21>;
	status = "disabled";
	};

	i2c0: i2c@1c2ac00 {
	compatible = "allwinner,sun7i-a20-i2c",
	"allwinner,sun4i-a10-i2c";
	reg = <0x01c2ac00 0x400>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB1_I2C0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c1: i2c@1c2b000 {
	compatible = "allwinner,sun7i-a20-i2c",
	"allwinner,sun4i-a10-i2c";
	reg = <0x01c2b000 0x400>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB1_I2C1>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c2: i2c@1c2b400 {
	compatible = "allwinner,sun7i-a20-i2c",
	"allwinner,sun4i-a10-i2c";
	reg = <0x01c2b400 0x400>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB1_I2C2>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c3: i2c@1c2b800 {
	compatible = "allwinner,sun7i-a20-i2c",
	"allwinner,sun4i-a10-i2c";
	reg = <0x01c2b800 0x400>;
	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB1_I2C3>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	can0: can@1c2bc00 {
	compatible = "allwinner,sun7i-a20-can",
	"allwinner,sun4i-a10-can";
	reg = <0x01c2bc00 0x400>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB1_CAN>;
	status = "disabled";
	};

	i2c4: i2c@1c2c000 {
	compatible = "allwinner,sun7i-a20-i2c",
	"allwinner,sun4i-a10-i2c";
	reg = <0x01c2c000 0x400>;
	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB1_I2C4>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mali: gpu@1c40000 {
	compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
	reg = <0x01c40000 0x10000>;
	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gp",
	"gpmmu",
	"pp0",
	"ppmmu0",
	"pp1",
	"ppmmu1",
	"pmu";
	clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
	clock-names = "bus", "core";
	resets = <&ccu RST_GPU>;

	assigned-clocks = <&ccu CLK_GPU>;
	assigned-clock-rates = <384000000>;
	};

	gmac: ethernet@1c50000 {
	compatible = "allwinner,sun7i-a20-gmac";
	reg = <0x01c50000 0x10000>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
	clock-names = "stmmaceth", "allwinner_gmac_tx";
	snps,pbl = <2>;
	snps,fixed-burst;
	snps,force_sf_dma_mode;
	status = "disabled";

	gmac_mdio: mdio {
	compatible = "snps,dwmac-mdio";
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	hstimer@1c60000 {
	compatible = "allwinner,sun7i-a20-hstimer";
	reg = <0x01c60000 0x1000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_HSTIMER>;
	};

	gic: interrupt-controller@1c81000 {
	compatible = "arm,gic-400";
	reg = <0x01c81000 0x1000>,
	<0x01c82000 0x2000>,
	<0x01c84000 0x2000>,
	<0x01c86000 0x2000>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	fe0: display-frontend@1e00000 {
	compatible = "allwinner,sun7i-a20-display-frontend";
	reg = <0x01e00000 0x20000>;
	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
	<&ccu CLK_DRAM_DE_FE0>;
	clock-names = "ahb", "mod",
	"ram";
	resets = <&ccu RST_DE_FE0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	fe0_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	fe0_out_be0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&be0_in_fe0>;
	};

	fe0_out_be1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&be1_in_fe0>;
	};
	};
	};
	};

	fe1: display-frontend@1e20000 {
	compatible = "allwinner,sun7i-a20-display-frontend";
	reg = <0x01e20000 0x20000>;
	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
	<&ccu CLK_DRAM_DE_FE1>;
	clock-names = "ahb", "mod",
	"ram";
	resets = <&ccu RST_DE_FE1>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	fe1_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	fe1_out_be0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&be0_in_fe1>;
	};

	fe1_out_be1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&be1_in_fe1>;
	};
	};
	};
	};

	be1: display-backend@1e40000 {
	compatible = "allwinner,sun7i-a20-display-backend";
	reg = <0x01e40000 0x10000>;
	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
	<&ccu CLK_DRAM_DE_BE1>;
	clock-names = "ahb", "mod",
	"ram";
	resets = <&ccu RST_DE_BE1>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	be1_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	be1_in_fe0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&fe0_out_be1>;
	};

	be1_in_fe1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&fe1_out_be1>;
	};
	};

	be1_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	be1_out_tcon0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&tcon0_in_be1>;
	};

	be1_out_tcon1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&tcon1_in_be1>;
	};
	};
	};
	};

	be0: display-backend@1e60000 {
	compatible = "allwinner,sun7i-a20-display-backend";
	reg = <0x01e60000 0x10000>;
	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
	<&ccu CLK_DRAM_DE_BE0>;
	clock-names = "ahb", "mod",
	"ram";
	resets = <&ccu RST_DE_BE0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	be0_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	be0_in_fe0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&fe0_out_be0>;
	};

	be0_in_fe1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&fe1_out_be0>;
	};
	};

	be0_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	be0_out_tcon0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&tcon0_in_be0>;
	};

	be0_out_tcon1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&tcon1_in_be0>;
	};
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/sun8i-a23-a33.dtsi b/sys/gnu/dts/arm/sun8i-a23-a33.dtsi
	index 48487f6d4ab9..c1362d0f0ff8 100644
	--- a/sys/gnu/dts/arm/sun8i-a23-a33.dtsi
	+++ b/sys/gnu/dts/arm/sun8i-a23-a33.dtsi
	@@ -1,853 +1,850 @@
	/*
	* Copyright 2014 Chen-Yu Tsai
	*
	* Chen-Yu Tsai <wens@csie.org>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>

	#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
	#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>

	/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	chosen {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	simplefb_lcd: framebuffer-lcd0 {
	compatible = "allwinner,simple-framebuffer",
	"simple-framebuffer";
	allwinner,pipeline = "de_be0-lcd0";
	clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
	<&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
	<&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
	status = "disabled";
	};
	};

	de: display-engine {
	/* compatible gets set in SoC specific dtsi file */
	allwinner,pipelines = <&fe0>;
	status = "disabled";
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	clock-frequency = <24000000>;
	arm,cpu-registers-not-fw-configured;
	};

	cpus {
	enable-method = "allwinner,sun8i-a23";
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <0>;
	};

	cpu@1 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <1>;
	};
	};

	clocks {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	osc24M: osc24M_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-accuracy = <50000>;
	clock-output-names = "osc24M";
	};

	ext_osc32k: ext_osc32k_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	clock-accuracy = <50000>;
	clock-output-names = "ext-osc32k";
	};
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	system-control@1c00000 {
	compatible = "allwinner,sun8i-a23-system-control";
	reg = <0x01c00000 0x30>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	sram_c: sram@1d00000 {
	compatible = "mmio-sram";
	reg = <0x01d00000 0x80000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x01d00000 0x80000>;

	ve_sram: sram-section@0 {
	compatible = "allwinner,sun8i-a23-sram-c1",
	"allwinner,sun4i-a10-sram-c1";
	reg = <0x000000 0x80000>;
	};
	};
	};

	dma: dma-controller@1c02000 {
	compatible = "allwinner,sun8i-a23-dma";
	reg = <0x01c02000 0x1000>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_DMA>;
	resets = <&ccu RST_BUS_DMA>;
	#dma-cells = <1>;
	};

	nfc: nand-controller@1c03000 {
	compatible = "allwinner,sun8i-a23-nand-controller";
	reg = <0x01c03000 0x1000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
	clock-names = "ahb", "mod";
	resets = <&ccu RST_BUS_NAND>;
	reset-names = "ahb";
	dmas = <&dma 5>;
	dma-names = "rxtx";
	pinctrl-names = "default";
	pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	tcon0: lcd-controller@1c0c000 {
	/* compatible gets set in SoC specific dtsi file */
	reg = <0x01c0c000 0x1000>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&dma 12>;
	clocks = <&ccu CLK_BUS_LCD>,
	<&ccu CLK_LCD_CH0>,
	<&ccu 13>;
	clock-names = "ahb",
	"tcon-ch0",
	"lvds-alt";
	clock-output-names = "tcon-pixel-clock";
	#clock-cells = <0>;
	resets = <&ccu RST_BUS_LCD>,
	<&ccu RST_BUS_LVDS>;
	reset-names = "lcd",
	"lvds";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon0_in: port@0 {
	reg = <0>;

	tcon0_in_drc0: endpoint {
	remote-endpoint = <&drc0_out_tcon0>;
	};
	};

	tcon0_out: port@1 {
	reg = <1>;
	};
	};
	};

	mmc0: mmc@1c0f000 {
	compatible = "allwinner,sun7i-a20-mmc";
	reg = <0x01c0f000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC0>,
	<&ccu CLK_MMC0>,
	<&ccu CLK_MMC0_OUTPUT>,
	<&ccu CLK_MMC0_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	resets = <&ccu RST_BUS_MMC0>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc1: mmc@1c10000 {
	compatible = "allwinner,sun7i-a20-mmc";
	reg = <0x01c10000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC1>,
	<&ccu CLK_MMC1>,
	<&ccu CLK_MMC1_OUTPUT>,
	<&ccu CLK_MMC1_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	resets = <&ccu RST_BUS_MMC1>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc2: mmc@1c11000 {
	compatible = "allwinner,sun7i-a20-mmc";
	reg = <0x01c11000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC2>,
	<&ccu CLK_MMC2>,
	<&ccu CLK_MMC2_OUTPUT>,
	<&ccu CLK_MMC2_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	resets = <&ccu RST_BUS_MMC2>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	usb_otg: usb@1c19000 {
	/* compatible gets set in SoC specific dtsi file */
	reg = <0x01c19000 0x0400>;
	clocks = <&ccu CLK_BUS_OTG>;
	resets = <&ccu RST_BUS_OTG>;
	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "mc";
	phys = <&usbphy 0>;
	phy-names = "usb";
	extcon = <&usbphy 0>;
	dr_mode = "otg";
	status = "disabled";
	};

	usbphy: phy@1c19400 {
	/*
	* compatible and address regions get set in
	* SoC specific dtsi file
	*/
	clocks = <&ccu CLK_USB_PHY0>,
	<&ccu CLK_USB_PHY1>;
	clock-names = "usb0_phy",
	"usb1_phy";
	resets = <&ccu RST_USB_PHY0>,
	<&ccu RST_USB_PHY1>;
	reset-names = "usb0_reset",
	"usb1_reset";
	status = "disabled";
	#phy-cells = <1>;
	};

	ehci0: usb@1c1a000 {
	compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
	reg = <0x01c1a000 0x100>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_EHCI>;
	resets = <&ccu RST_BUS_EHCI>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	ohci0: usb@1c1a400 {
	compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
	reg = <0x01c1a400 0x100>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
	resets = <&ccu RST_BUS_OHCI>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	ccu: clock@1c20000 {
	reg = <0x01c20000 0x400>;
	clocks = <&osc24M>, <&rtc 0>;
	clock-names = "hosc", "losc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pio: pinctrl@1c20800 {
	/* compatible gets set in SoC specific dtsi file */
	reg = <0x01c20800 0x400>;
	/* interrupts get set in SoC specific dtsi file */
	clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
	clock-names = "apb", "hosc", "losc";
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <3>;
	#gpio-cells = <3>;

	i2c0_pins: i2c0-pins {
	pins = "PH2", "PH3";
	function = "i2c0";
	};

	i2c1_pins: i2c1-pins {
	pins = "PH4", "PH5";
	function = "i2c1";
	};

	i2c2_pins: i2c2-pins {
	pins = "PE12", "PE13";
	function = "i2c2";
	};

	lcd_rgb666_pins: lcd-rgb666-pins {
	pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
	"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
	"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
	"PD24", "PD25", "PD26", "PD27";
	function = "lcd0";
	};

	mmc0_pins: mmc0-pins {
	pins = "PF0", "PF1", "PF2",
	"PF3", "PF4", "PF5";
	function = "mmc0";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc1_pg_pins: mmc1-pg-pins {
	pins = "PG0", "PG1", "PG2",
	"PG3", "PG4", "PG5";
	function = "mmc1";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc2_8bit_pins: mmc2-8bit-pins {
	pins = "PC5", "PC6", "PC8",
	"PC9", "PC10", "PC11",
	"PC12", "PC13", "PC14",
	"PC15", "PC16";
	function = "mmc2";
	drive-strength = <30>;
	bias-pull-up;
	};

	nand_pins: nand-pins {
	pins = "PC0", "PC1", "PC2", "PC5",
	"PC8", "PC9", "PC10", "PC11",
	"PC12", "PC13", "PC14", "PC15";
	function = "nand0";
	};

	nand_cs0_pin: nand-cs0-pin {
	pins = "PC4";
	function = "nand0";
	bias-pull-up;
	};

	nand_cs1_pin: nand-cs1-pin {
	pins = "PC3";
	function = "nand0";
	bias-pull-up;
	};

	nand_rb0_pin: nand-rb0-pin {
	pins = "PC6";
	function = "nand0";
	bias-pull-up;
	};

	nand_rb1_pin: nand-rb1-pin {
	pins = "PC7";
	function = "nand0";
	bias-pull-up;
	};

	pwm0_pin: pwm0-pin {
	pins = "PH0";
	function = "pwm0";
	};

	uart0_pf_pins: uart0-pf-pins {
	pins = "PF2", "PF4";
	function = "uart0";
	};

	uart1_pg_pins: uart1-pg-pins {
	pins = "PG6", "PG7";
	function = "uart1";
	};

	uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins {
	pins = "PG8", "PG9";
	function = "uart1";
	};
	};

	timer@1c20c00 {
	compatible = "allwinner,sun8i-a23-timer";
	reg = <0x01c20c00 0xa0>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc24M>;
	};

	wdt0: watchdog@1c20ca0 {
	compatible = "allwinner,sun6i-a31-wdt";
	reg = <0x01c20ca0 0x20>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc24M>;
	};

	pwm: pwm@1c21400 {
	compatible = "allwinner,sun7i-a20-pwm";
	reg = <0x01c21400 0xc>;
	clocks = <&osc24M>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	lradc: lradc@1c22800 {
	compatible = "allwinner,sun4i-a10-lradc-keys";
	reg = <0x01c22800 0x100>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	uart0: serial@1c28000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28000 0x400>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART0>;
	resets = <&ccu RST_BUS_UART0>;
	dmas = <&dma 6>, <&dma 6>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart1: serial@1c28400 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28400 0x400>;
	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART1>;
	resets = <&ccu RST_BUS_UART1>;
	dmas = <&dma 7>, <&dma 7>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart2: serial@1c28800 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28800 0x400>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART2>;
	resets = <&ccu RST_BUS_UART2>;
	dmas = <&dma 8>, <&dma 8>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart3: serial@1c28c00 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28c00 0x400>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART3>;
	resets = <&ccu RST_BUS_UART3>;
	dmas = <&dma 9>, <&dma 9>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart4: serial@1c29000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c29000 0x400>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART4>;
	resets = <&ccu RST_BUS_UART4>;
	dmas = <&dma 10>, <&dma 10>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c0: i2c@1c2ac00 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2ac00 0x400>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C0>;
	resets = <&ccu RST_BUS_I2C0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c1: i2c@1c2b000 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2b000 0x400>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C1>;
	resets = <&ccu RST_BUS_I2C1>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c2: i2c@1c2b400 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2b400 0x400>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C2>;
	resets = <&ccu RST_BUS_I2C2>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mali: gpu@1c40000 {
	compatible = "allwinner,sun8i-a23-mali",
	"allwinner,sun7i-a20-mali", "arm,mali-400";
	reg = <0x01c40000 0x10000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gp",
	"gpmmu",
	"pp0",
	"ppmmu0",
	"pp1",
	"ppmmu1",
	"pmu";
	clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
	clock-names = "bus", "core";
	resets = <&ccu RST_BUS_GPU>;
	#cooling-cells = <2>;

	assigned-clocks = <&ccu CLK_GPU>;
	assigned-clock-rates = <384000000>;
	};

	gic: interrupt-controller@1c81000 {
	compatible = "arm,gic-400";
	reg = <0x01c81000 0x1000>,
	<0x01c82000 0x2000>,
	<0x01c84000 0x2000>,
	<0x01c86000 0x2000>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	fe0: display-frontend@1e00000 {
	/* compatible gets set in SoC specific dtsi file */
	reg = <0x01e00000 0x20000>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
	<&ccu CLK_DRAM_DE_FE>;
	clock-names = "ahb", "mod",
	"ram";
	resets = <&ccu RST_BUS_DE_FE>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	fe0_out: port@1 {
	reg = <1>;

	fe0_out_be0: endpoint {
	remote-endpoint = <&be0_in_fe0>;
	};
	};
	};
	};

	be0: display-backend@1e60000 {
	/* compatible gets set in SoC specific dtsi file */
	reg = <0x01e60000 0x10000>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
	<&ccu CLK_DRAM_DE_BE>;
	clock-names = "ahb", "mod",
	"ram";
	resets = <&ccu RST_BUS_DE_BE>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	be0_in: port@0 {
	reg = <0>;

	be0_in_fe0: endpoint {
	remote-endpoint = <&fe0_out_be0>;
	};
	};

	be0_out: port@1 {
	reg = <1>;

	be0_out_drc0: endpoint {
	remote-endpoint = <&drc0_in_be0>;
	};
	};
	};
	};

	drc0: drc@1e70000 {
	/* compatible gets set in SoC specific dtsi file */
	reg = <0x01e70000 0x10000>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
	<&ccu CLK_DRAM_DRC>;
	clock-names = "ahb", "mod", "ram";
	resets = <&ccu RST_BUS_DRC>;

	- assigned-clocks = <&ccu CLK_DRC>;
	- assigned-clock-rates = <300000000>;
	-
	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	drc0_in: port@0 {
	reg = <0>;

	drc0_in_be0: endpoint {
	remote-endpoint = <&be0_out_drc0>;
	};
	};

	drc0_out: port@1 {
	reg = <1>;

	drc0_out_tcon0: endpoint {
	remote-endpoint = <&tcon0_in_drc0>;
	};
	};
	};
	};

	rtc: rtc@1f00000 {
	compatible = "allwinner,sun8i-a23-rtc";
	reg = <0x01f00000 0x400>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	clock-output-names = "osc32k", "osc32k-out";
	clocks = <&ext_osc32k>;
	#clock-cells = <1>;
	};

	nmi_intc: interrupt-controller@1f00c00 {
	compatible = "allwinner,sun6i-a31-r-intc";
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x01f00c00 0x400>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	};

	prcm@1f01400 {
	compatible = "allwinner,sun8i-a23-prcm";
	reg = <0x01f01400 0x200>;

	ar100: ar100_clk {
	compatible = "fixed-factor-clock";
	#clock-cells = <0>;
	clock-div = <1>;
	clock-mult = <1>;
	clocks = <&osc24M>;
	clock-output-names = "ar100";
	};

	ahb0: ahb0_clk {
	compatible = "fixed-factor-clock";
	#clock-cells = <0>;
	clock-div = <1>;
	clock-mult = <1>;
	clocks = <&ar100>;
	clock-output-names = "ahb0";
	};

	apb0: apb0_clk {
	compatible = "allwinner,sun8i-a23-apb0-clk";
	#clock-cells = <0>;
	clocks = <&ahb0>;
	clock-output-names = "apb0";
	};

	apb0_gates: apb0_gates_clk {
	compatible = "allwinner,sun8i-a23-apb0-gates-clk";
	#clock-cells = <1>;
	clocks = <&apb0>;
	clock-output-names = "apb0_pio", "apb0_timer",
	"apb0_rsb", "apb0_uart",
	"apb0_i2c";
	};

	apb0_rst: apb0_rst {
	compatible = "allwinner,sun6i-a31-clock-reset";
	#reset-cells = <1>;
	};

	codec_analog: codec-analog {
	compatible = "allwinner,sun8i-a23-codec-analog";
	};
	};

	cpucfg@1f01c00 {
	compatible = "allwinner,sun8i-a23-cpuconfig";
	reg = <0x01f01c00 0x300>;
	};

	r_uart: serial@1f02800 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01f02800 0x400>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&apb0_gates 4>;
	resets = <&apb0_rst 4>;
	status = "disabled";
	};

	r_i2c: i2c@1f02400 {
	compatible = "allwinner,sun8i-a23-i2c",
	"allwinner,sun6i-a31-i2c";
	reg = <0x01f02400 0x400>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&r_i2c_pins>;
	clocks = <&apb0_gates 6>;
	resets = <&apb0_rst 6>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	r_pio: pinctrl@1f02c00 {
	compatible = "allwinner,sun8i-a23-r-pinctrl";
	reg = <0x01f02c00 0x400>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
	clock-names = "apb", "hosc", "losc";
	resets = <&apb0_rst 0>;
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <3>;
	#gpio-cells = <3>;

	r_i2c_pins: r-i2c-pins {
	pins = "PL0", "PL1";
	function = "s_i2c";
	bias-pull-up;
	};

	r_rsb_pins: r-rsb-pins {
	pins = "PL0", "PL1";
	function = "s_rsb";
	drive-strength = <20>;
	bias-pull-up;
	};

	r_uart_pins_a: r-uart-pins {
	pins = "PL2", "PL3";
	function = "s_uart";
	};
	};

	r_rsb: rsb@1f03400 {
	compatible = "allwinner,sun8i-a23-rsb";
	reg = <0x01f03400 0x400>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&apb0_gates 3>;
	clock-frequency = <3000000>;
	resets = <&apb0_rst 3>;
	pinctrl-names = "default";
	pinctrl-0 = <&r_rsb_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/sun8i-a33.dtsi b/sys/gnu/dts/arm/sun8i-a33.dtsi
	index a2c37adacf77..cfd3858afb3e 100644
	--- a/sys/gnu/dts/arm/sun8i-a33.dtsi
	+++ b/sys/gnu/dts/arm/sun8i-a33.dtsi
	@@ -1,433 +1,431 @@
	/*
	* Copyright 2014 Chen-Yu Tsai
	*
	* Chen-Yu Tsai <wens@csie.org>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include "sun8i-a23-a33.dtsi"
	#include <dt-bindings/thermal/thermal.h>

	/ {
	cpu0_opp_table: opp_table0 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-120000000 {
	opp-hz = /bits/ 64 <120000000>;
	opp-microvolt = <1040000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-240000000 {
	opp-hz = /bits/ 64 <240000000>;
	opp-microvolt = <1040000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-312000000 {
	opp-hz = /bits/ 64 <312000000>;
	opp-microvolt = <1040000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-408000000 {
	opp-hz = /bits/ 64 <408000000>;
	opp-microvolt = <1040000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-480000000 {
	opp-hz = /bits/ 64 <480000000>;
	opp-microvolt = <1040000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-504000000 {
	opp-hz = /bits/ 64 <504000000>;
	opp-microvolt = <1040000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-600000000 {
	opp-hz = /bits/ 64 <600000000>;
	opp-microvolt = <1040000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-648000000 {
	opp-hz = /bits/ 64 <648000000>;
	opp-microvolt = <1040000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-720000000 {
	opp-hz = /bits/ 64 <720000000>;
	opp-microvolt = <1100000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-816000000 {
	opp-hz = /bits/ 64 <816000000>;
	opp-microvolt = <1100000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-912000000 {
	opp-hz = /bits/ 64 <912000000>;
	opp-microvolt = <1200000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-1008000000 {
	opp-hz = /bits/ 64 <1008000000>;
	opp-microvolt = <1200000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};
	};

	cpus {
	cpu@0 {
	clocks = <&ccu CLK_CPUX>;
	clock-names = "cpu";
	operating-points-v2 = <&cpu0_opp_table>;
	#cooling-cells = <2>;
	};

	cpu1: cpu@1 {
	clocks = <&ccu CLK_CPUX>;
	clock-names = "cpu";
	operating-points-v2 = <&cpu0_opp_table>;
	#cooling-cells = <2>;
	};

	cpu2: cpu@2 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <2>;
	clocks = <&ccu CLK_CPUX>;
	clock-names = "cpu";
	operating-points-v2 = <&cpu0_opp_table>;
	#cooling-cells = <2>;
	};

	cpu3: cpu@3 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <3>;
	clocks = <&ccu CLK_CPUX>;
	clock-names = "cpu";
	operating-points-v2 = <&cpu0_opp_table>;
	#cooling-cells = <2>;
	};
	};

	iio-hwmon {
	compatible = "iio-hwmon";
	io-channels = <&ths>;
	};

	mali_opp_table: gpu-opp-table {
	compatible = "operating-points-v2";

	opp-144000000 {
	opp-hz = /bits/ 64 <144000000>;
	};

	opp-240000000 {
	opp-hz = /bits/ 64 <240000000>;
	};

	opp-384000000 {
	opp-hz = /bits/ 64 <384000000>;
	};
	};

	sound: sound {
	compatible = "simple-audio-card";
	simple-audio-card,name = "sun8i-a33-audio";
	simple-audio-card,format = "i2s";
	simple-audio-card,frame-master = <&link_codec>;
	simple-audio-card,bitclock-master = <&link_codec>;
	simple-audio-card,mclk-fs = <128>;
	simple-audio-card,aux-devs = <&codec_analog>;
	simple-audio-card,routing =
	"Left DAC", "AIF1 Slot 0 Left",
	"Right DAC", "AIF1 Slot 0 Right";
	status = "disabled";

	simple-audio-card,cpu {
	sound-dai = <&dai>;
	};

	link_codec: simple-audio-card,codec {
	sound-dai = <&codec>;
	};
	};

	soc {
	video-codec@1c0e000 {
	compatible = "allwinner,sun8i-a33-video-engine";
	reg = <0x01c0e000 0x1000>;
	clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
	<&ccu CLK_DRAM_VE>;
	clock-names = "ahb", "mod", "ram";
	resets = <&ccu RST_BUS_VE>;
	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	allwinner,sram = <&ve_sram 1>;
	};

	crypto: crypto-engine@1c15000 {
	compatible = "allwinner,sun8i-a33-crypto";
	reg = <0x01c15000 0x1000>;
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
	clock-names = "ahb", "mod";
	resets = <&ccu RST_BUS_SS>;
	reset-names = "ahb";
	};

	dai: dai@1c22c00 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun6i-a31-i2s";
	reg = <0x01c22c00 0x200>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
	clock-names = "apb", "mod";
	resets = <&ccu RST_BUS_CODEC>;
	dmas = <&dma 15>, <&dma 15>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	codec: codec@1c22e00 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun8i-a33-codec";
	reg = <0x01c22e00 0x400>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
	clock-names = "bus", "mod";
	status = "disabled";
	};

	ths: ths@1c25000 {
	compatible = "allwinner,sun8i-a33-ths";
	reg = <0x01c25000 0x100>;
	#thermal-sensor-cells = <0>;
	#io-channel-cells = <0>;
	};

	dsi: dsi@1ca0000 {
	compatible = "allwinner,sun6i-a31-mipi-dsi";
	reg = <0x01ca0000 0x1000>;
	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_MIPI_DSI>,
	<&ccu CLK_DSI_SCLK>;
	clock-names = "bus", "mod";
	resets = <&ccu RST_BUS_MIPI_DSI>;
	phys = <&dphy>;
	phy-names = "dphy";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;

	port {
	dsi_in_tcon0: endpoint {
	remote-endpoint = <&tcon0_out_dsi>;
	};
	};
	};

	dphy: d-phy@1ca1000 {
	compatible = "allwinner,sun6i-a31-mipi-dphy";
	reg = <0x01ca1000 0x1000>;
	clocks = <&ccu CLK_BUS_MIPI_DSI>,
	<&ccu CLK_DSI_DPHY>;
	clock-names = "bus", "mod";
	resets = <&ccu RST_BUS_MIPI_DSI>;
	status = "disabled";
	#phy-cells = <0>;
	};
	};

	thermal-zones {
	cpu_thermal {
	/* milliseconds */
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&ths>;

	cooling-maps {
	map0 {
	trip = <&cpu_alert0>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu_alert1>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};

	map2 {
	trip = <&gpu_alert0>;
	cooling-device = <&mali 1 THERMAL_NO_LIMIT>;
	};

	map3 {
	trip = <&gpu_alert1>;
	cooling-device = <&mali 2 THERMAL_NO_LIMIT>;
	};
	};

	trips {
	cpu_alert0: cpu_alert0 {
	/* milliCelsius */
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};

	gpu_alert0: gpu_alert0 {
	/* milliCelsius */
	temperature = <85000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu_alert1: cpu_alert1 {
	/* milliCelsius */
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};

	gpu_alert1: gpu_alert1 {
	/* milliCelsius */
	temperature = <95000>;
	hysteresis = <2000>;
	type = "hot";
	};

	cpu_crit: cpu_crit {
	/* milliCelsius */
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};
	};
	};

	&be0 {
	compatible = "allwinner,sun8i-a33-display-backend";
	/* A33 has an extra "SAT" module packed inside the display backend */
	reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
	reg-names = "be", "sat";
	clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
	<&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
	clock-names = "ahb", "mod",
	"ram", "sat";
	resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
	reset-names = "be", "sat";
	- assigned-clocks = <&ccu CLK_DE_BE>;
	- assigned-clock-rates = <300000000>;
	};

	&ccu {
	compatible = "allwinner,sun8i-a33-ccu";
	};

	&de {
	compatible = "allwinner,sun8i-a33-display-engine";
	};

	&drc0 {
	compatible = "allwinner,sun8i-a33-drc";
	};

	&fe0 {
	compatible = "allwinner,sun8i-a33-display-frontend";
	};

	&mali {
	operating-points-v2 = <&mali_opp_table>;
	};

	&pio {
	compatible = "allwinner,sun8i-a33-pinctrl";
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

	uart0_pb_pins: uart0-pb-pins {
	pins = "PB0", "PB1";
	function = "uart0";
	};

	};

	&tcon0 {
	compatible = "allwinner,sun8i-a33-tcon";
	};

	&tcon0_out {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon0_out_dsi: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&dsi_in_tcon0>;
	};
	};

	&usb_otg {
	compatible = "allwinner,sun8i-a33-musb";
	};

	&usbphy {
	compatible = "allwinner,sun8i-a33-usb-phy";
	reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
	reg-names = "phy_ctrl", "pmu1";
	};
	diff --git a/sys/gnu/dts/arm/sun8i-a83t-tbs-a711.dts b/sys/gnu/dts/arm/sun8i-a83t-tbs-a711.dts
	index e8b3669e0e5d..bfc9bb277a49 100644
	--- a/sys/gnu/dts/arm/sun8i-a83t-tbs-a711.dts
	+++ b/sys/gnu/dts/arm/sun8i-a83t-tbs-a711.dts
	@@ -1,507 +1,506 @@
	/*
	* Copyright (C) 2017 Touchless Biometric Systems AG
	* Tomas Novotny <tomas@novotny.cz>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	/dts-v1/;
	#include "sun8i-a83t.dtsi"

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/pwm/pwm.h>
	#include <dt-bindings/input/input.h>

	/ {
	model = "TBS A711 Tablet";
	compatible = "tbs-biometrics,a711", "allwinner,sun8i-a83t";

	aliases {
	serial0 = &uart0;
	serial1 = &uart1;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	backlight: backlight {
	compatible = "pwm-backlight";
	pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
	enable-gpios = <&pio 3 29 GPIO_ACTIVE_HIGH>;

	brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
	default-brightness-level = <9>;
	};

	panel {
	compatible = "tbs,a711-panel", "panel-lvds";
	backlight = <&backlight>;
	power-supply = <&reg_sw>;

	width-mm = <153>;
	height-mm = <90>;
	data-mapping = "vesa-24";

	panel-timing {
	/* 1024x600 @60Hz */
	clock-frequency = <52000000>;
	hactive = <1024>;
	vactive = <600>;
	hsync-len = <20>;
	hfront-porch = <180>;
	hback-porch = <160>;
	vfront-porch = <12>;
	vback-porch = <23>;
	vsync-len = <5>;
	};

	port {
	panel_input: endpoint {
	remote-endpoint = <&tcon0_out_lcd>;
	};
	};
	};

	reg_gps: reg-gps {
	compatible = "regulator-fixed";
	regulator-name = "gps";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	};

	reg_vbat: reg-vbat {
	compatible = "regulator-fixed";
	regulator-name = "vbat";
	regulator-min-microvolt = <3700000>;
	regulator-max-microvolt = <3700000>;
	};

	reg_vmain: reg-vmain {
	compatible = "regulator-fixed";
	regulator-name = "vmain";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&reg_vbat>;
	};

	wifi_pwrseq: wifi_pwrseq {
	compatible = "mmc-pwrseq-simple";
	reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */

	/*
	* This is actually Bluetooth's clock, but we have to
	* hook it up somewheere
	*/
	clocks = <&ac100_rtc 1>;
	clock-names = "ext_clock";
	};
	};

	&cpu0 {
	cpu-supply = <&reg_dcdc2>;
	};

	&cpu100 {
	cpu-supply = <&reg_dcdc3>;
	};

	&de {
	status = "okay";
	};

	/*
	* An USB-2 hub is connected here, which also means we don't need to
	* enable the OHCI controller.
	*/
	&ehci0 {
	status = "okay";
	};

	/*
	* There's a modem connected here that needs to be initialised before
	* being able to be enumerated.
	*/
	&ehci1 {
	status = "okay";
	};

	&i2c0 {
	clock-frequency = <400000>;
	status = "okay";

	touchscreen@38 {
	compatible = "edt,edt-ft5x06";
	reg = <0x38>;
	interrupt-parent = <&r_pio>;
	interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>; /* PL7 */
	reset-gpios = <&pio 3 5 GPIO_ACTIVE_LOW>; /* PD5 */
	vcc-supply = <&reg_ldo_io0>;
	touchscreen-size-x = <1024>;
	touchscreen-size-y = <600>;
	};
	};

	&i2c1 {
	clock-frequency = <400000>;
	status = "okay";

	accelerometer@18 {
	compatible = "bosch,bma250";
	reg = <0x18>;
	interrupt-parent = <&pio>;
	interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
	};
	};

	&mmc0 {
	vmmc-supply = <&reg_dcdc1>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	bus-width = <4>;
	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&mmc1 {
	mmc-pwrseq = <&wifi_pwrseq>;
	bus-width = <4>;
	vmmc-supply = <&reg_dldo1>;
	vqmmc-supply = <&reg_dldo1>;
	non-removable;
	wakeup-source;
	keep-power-in-suspend;
	status = "okay";

	brcmf: wifi@1 {
	reg = <1>;
	compatible = "brcm,bcm4329-fmac";
	interrupt-parent = <&r_pio>;
	interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 WL_WAKE_UP */
	interrupt-names = "host-wake";
	};
	};

	&mmc2 {
	pinctrl-0 = <&mmc2_8bit_emmc_pins>;
	pinctrl-names = "default";
	vmmc-supply = <&reg_dcdc1>;
	vqmmc-supply = <&reg_dcdc1>;
	bus-width = <8>;
	non-removable;
	cap-mmc-hw-reset;
	status = "okay";
	};

	&pwm {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm_pin>;
	status = "okay";
	};

	&r_lradc {
	vref-supply = <&reg_aldo2>;
	status = "okay";

	button-210 {
	label = "Volume Up";
	linux,code = <KEY_VOLUMEUP>;
	channel = <0>;
	voltage = <210000>;
	};

	button-410 {
	label = "Volume Down";
	linux,code = <KEY_VOLUMEDOWN>;
	channel = <0>;
	voltage = <410000>;
	};
	};

	&r_rsb {
	status = "okay";

	axp81x: pmic@3a3 {
	compatible = "x-powers,axp813";
	reg = <0x3a3>;
	interrupt-parent = <&r_intc>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	swin-supply = <&reg_dcdc1>;
	x-powers,drive-vbus-en;
	};

	ac100: codec@e89 {
	compatible = "x-powers,ac100";
	reg = <0xe89>;

	ac100_codec: codec {
	compatible = "x-powers,ac100-codec";
	interrupt-parent = <&r_pio>;
	interrupts = <0 12 IRQ_TYPE_LEVEL_LOW>; /* PL12 */
	#clock-cells = <0>;
	clock-output-names = "4M_adda";
	};

	ac100_rtc: rtc {
	compatible = "x-powers,ac100-rtc";
	interrupt-parent = <&r_intc>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&ac100_codec>;
	#clock-cells = <1>;
	clock-output-names = "cko1_rtc",
	"cko2_rtc",
	"cko3_rtc";
	};
	};

	};

	#include "axp81x.dtsi"

	&battery_power_supply {
	status = "okay";
	};

	&reg_aldo1 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc-1.8";
	};

	&reg_aldo2 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-name = "vdd-drampll";
	};

	&reg_aldo3 {
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;
	regulator-name = "avcc";
	};

	&reg_dcdc1 {
	regulator-min-microvolt = <3100000>;
	regulator-max-microvolt = <3100000>;
	regulator-always-on;
	regulator-name = "vcc-io";
	};

	&reg_dcdc2 {
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;
	regulator-name = "vdd-cpu-A";
	};

	&reg_dcdc3 {
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;
	regulator-name = "vdd-cpu-B";
	};

	&reg_dcdc4 {
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1100000>;
	regulator-name = "vdd-gpu";
	};

	&reg_dcdc5 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;
	regulator-name = "vcc-dram";
	};

	&reg_dcdc6 {
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <900000>;
	regulator-always-on;
	regulator-name = "vdd-sys";
	};

	&reg_dldo1 {
	regulator-min-microvolt = <3100000>;
	regulator-max-microvolt = <3100000>;
	regulator-name = "vcc-wifi-io";
	};

	&reg_dldo2 {
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <4200000>;
	regulator-name = "vcc-mipi";
	};

	&reg_dldo3 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vdd-csi";
	};

	&reg_dldo4 {
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-name = "avdd-csi";
	};

	&reg_drivevbus {
	regulator-name = "usb0-vbus";
	status = "okay";
	};

	&reg_eldo1 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "dvdd-csi-r";
	};

	&reg_eldo2 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc-dsi";
	};

	&reg_eldo3 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "dvdd-csi-f";
	};

	&reg_fldo1 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-name = "vcc-hsic";
	};

	&reg_fldo2 {
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;
	regulator-name = "vdd-cpus";
	};

	&reg_ldo_io0 {
	regulator-min-microvolt = <3100000>;
	regulator-max-microvolt = <3100000>;
	regulator-name = "vcc-ctp";
	status = "okay";
	};

	&reg_ldo_io1 {
	regulator-min-microvolt = <3100000>;
	regulator-max-microvolt = <3100000>;
	regulator-name = "vcc-vb";
	status = "okay";
	};

	&reg_sw {
	regulator-min-microvolt = <3100000>;
	regulator-max-microvolt = <3100000>;
	regulator-name = "vcc-lcd";
	};

	&tcon0 {
	pinctrl-names = "default";
	pinctrl-0 = <&lcd_lvds_pins>;
	};

	&tcon0_out {
	tcon0_out_lcd: endpoint {
	remote-endpoint = <&panel_input>;
	};
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pb_pins>;
	status = "okay";
	};

	/* There's the BT part of the AP6210 connected to that UART */
	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
	uart-has-rtscts;
	status = "okay";

	bluetooth {
	compatible = "brcm,bcm20702a1";
	clocks = <&ac100_rtc 1>;
	clock-names = "lpo";
	vbat-supply = <&reg_vbat>;
	vddio-supply = <&reg_dldo1>;
	device-wakeup-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
	host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
	shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
	max-speed = <1500000>;
	};
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pb_pins>;
	status = "okay";

	gnss {
	compatible = "u-blox,neo-6m";

	v-bckp-supply = <&reg_rtc_ldo>;
	vcc-supply = <&reg_gps>;
	current-speed = <9600>;
	};
	};

	&usb_otg {
	- dr_mode = "otg";
	status = "okay";
	};

	&usbphy {
	usb0_id_det-gpios = <&pio 7 11 (GPIO_ACTIVE_HIGH \| GPIO_PULL_UP)>; /* PH11 */
	usb0_vbus_power-supply = <&usb_power_supply>;
	usb0_vbus-supply = <&reg_drivevbus>;
	usb1_vbus-supply = <&reg_vmain>;
	usb2_vbus-supply = <&reg_vmain>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/sun8i-a83t.dtsi b/sys/gnu/dts/arm/sun8i-a83t.dtsi
	index e7b9bef1be6b..655404d6d3a3 100644
	--- a/sys/gnu/dts/arm/sun8i-a83t.dtsi
	+++ b/sys/gnu/dts/arm/sun8i-a83t.dtsi
	@@ -1,1205 +1,1264 @@
	/*
	* Copyright 2015 Vishnu Patekar
	*
	* Vishnu Patekar <vishnupatekar0510@gmail.com>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>

	#include <dt-bindings/clock/sun8i-a83t-ccu.h>
	#include <dt-bindings/clock/sun8i-de2.h>
	#include <dt-bindings/clock/sun8i-r-ccu.h>
	#include <dt-bindings/reset/sun8i-a83t-ccu.h>
	#include <dt-bindings/reset/sun8i-de2.h>
	#include <dt-bindings/reset/sun8i-r-ccu.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	clocks = <&ccu CLK_C0CPUX>;
	operating-points-v2 = <&cpu0_opp_table>;
	cci-control-port = <&cci_control0>;
	enable-method = "allwinner,sun8i-a83t-smp";
	reg = <0>;
	#cooling-cells = <2>;
	};

	- cpu@1 {
	+ cpu1: cpu@1 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	clocks = <&ccu CLK_C0CPUX>;
	operating-points-v2 = <&cpu0_opp_table>;
	cci-control-port = <&cci_control0>;
	enable-method = "allwinner,sun8i-a83t-smp";
	reg = <1>;
	#cooling-cells = <2>;
	};

	- cpu@2 {
	+ cpu2: cpu@2 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	clocks = <&ccu CLK_C0CPUX>;
	operating-points-v2 = <&cpu0_opp_table>;
	cci-control-port = <&cci_control0>;
	enable-method = "allwinner,sun8i-a83t-smp";
	reg = <2>;
	#cooling-cells = <2>;
	};

	- cpu@3 {
	+ cpu3: cpu@3 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	clocks = <&ccu CLK_C0CPUX>;
	operating-points-v2 = <&cpu0_opp_table>;
	cci-control-port = <&cci_control0>;
	enable-method = "allwinner,sun8i-a83t-smp";
	reg = <3>;
	#cooling-cells = <2>;
	};

	cpu100: cpu@100 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	clocks = <&ccu CLK_C1CPUX>;
	operating-points-v2 = <&cpu1_opp_table>;
	cci-control-port = <&cci_control1>;
	enable-method = "allwinner,sun8i-a83t-smp";
	reg = <0x100>;
	#cooling-cells = <2>;
	};

	- cpu@101 {
	+ cpu101: cpu@101 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	clocks = <&ccu CLK_C1CPUX>;
	operating-points-v2 = <&cpu1_opp_table>;
	cci-control-port = <&cci_control1>;
	enable-method = "allwinner,sun8i-a83t-smp";
	reg = <0x101>;
	#cooling-cells = <2>;
	};

	- cpu@102 {
	+ cpu102: cpu@102 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	clocks = <&ccu CLK_C1CPUX>;
	operating-points-v2 = <&cpu1_opp_table>;
	cci-control-port = <&cci_control1>;
	enable-method = "allwinner,sun8i-a83t-smp";
	reg = <0x102>;
	#cooling-cells = <2>;
	};

	- cpu@103 {
	+ cpu103: cpu@103 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	clocks = <&ccu CLK_C1CPUX>;
	operating-points-v2 = <&cpu1_opp_table>;
	cci-control-port = <&cci_control1>;
	enable-method = "allwinner,sun8i-a83t-smp";
	reg = <0x103>;
	#cooling-cells = <2>;
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	clocks {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	/* TODO: PRCM block has a mux for this. */
	osc24M: osc24M_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-accuracy = <50000>;
	clock-output-names = "osc24M";
	};

	/*
	* This is called "internal OSC" in some places.
	* It is an internal RC-based oscillator.
	* TODO: Its controls are in the PRCM block.
	*/
	osc16M: osc16M_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <16000000>;
	clock-output-names = "osc16M";
	};

	osc16Md512: osc16Md512_clk {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clock-div = <512>;
	clock-mult = <1>;
	clocks = <&osc16M>;
	clock-output-names = "osc16M-d512";
	};
	};

	de: display-engine {
	compatible = "allwinner,sun8i-a83t-display-engine";
	allwinner,pipelines = <&mixer0>, <&mixer1>;
	status = "disabled";
	};

	cpu0_opp_table: opp_table0 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-480000000 {
	opp-hz = /bits/ 64 <480000000>;
	opp-microvolt = <840000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-600000000 {
	opp-hz = /bits/ 64 <600000000>;
	opp-microvolt = <840000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-720000000 {
	opp-hz = /bits/ 64 <720000000>;
	opp-microvolt = <840000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-864000000 {
	opp-hz = /bits/ 64 <864000000>;
	opp-microvolt = <840000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-912000000 {
	opp-hz = /bits/ 64 <912000000>;
	opp-microvolt = <840000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-1008000000 {
	opp-hz = /bits/ 64 <1008000000>;
	opp-microvolt = <840000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-1128000000 {
	opp-hz = /bits/ 64 <1128000000>;
	opp-microvolt = <840000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	opp-microvolt = <840000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};
	};

	cpu1_opp_table: opp_table1 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-480000000 {
	opp-hz = /bits/ 64 <480000000>;
	opp-microvolt = <840000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-600000000 {
	opp-hz = /bits/ 64 <600000000>;
	opp-microvolt = <840000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-720000000 {
	opp-hz = /bits/ 64 <720000000>;
	opp-microvolt = <840000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-864000000 {
	opp-hz = /bits/ 64 <864000000>;
	opp-microvolt = <840000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-912000000 {
	opp-hz = /bits/ 64 <912000000>;
	opp-microvolt = <840000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-1008000000 {
	opp-hz = /bits/ 64 <1008000000>;
	opp-microvolt = <840000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-1128000000 {
	opp-hz = /bits/ 64 <1128000000>;
	opp-microvolt = <840000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	opp-microvolt = <840000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	display_clocks: clock@1000000 {
	compatible = "allwinner,sun8i-a83t-de2-clk";
	- reg = <0x01000000 0x100000>;
	+ reg = <0x01000000 0x10000>;
	clocks = <&ccu CLK_BUS_DE>,
	<&ccu CLK_PLL_DE>;
	clock-names = "bus",
	"mod";
	resets = <&ccu RST_BUS_DE>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	+ rotate: rotate@1020000 {
	+ compatible = "allwinner,sun8i-a83t-de2-rotate";
	+ reg = <0x1020000 0x10000>;
	+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&display_clocks CLK_BUS_ROT>,
	+ <&display_clocks CLK_ROT>;
	+ clock-names = "bus",
	+ "mod";
	+ resets = <&display_clocks RST_ROT>;
	+ };
	+
	mixer0: mixer@1100000 {
	compatible = "allwinner,sun8i-a83t-de2-mixer-0";
	reg = <0x01100000 0x100000>;
	clocks = <&display_clocks CLK_BUS_MIXER0>,
	<&display_clocks CLK_MIXER0>;
	clock-names = "bus",
	"mod";
	resets = <&display_clocks RST_MIXER0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	mixer0_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	mixer0_out_tcon0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&tcon0_in_mixer0>;
	};

	mixer0_out_tcon1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&tcon1_in_mixer0>;
	};
	};
	};
	};

	mixer1: mixer@1200000 {
	compatible = "allwinner,sun8i-a83t-de2-mixer-1";
	reg = <0x01200000 0x100000>;
	clocks = <&display_clocks CLK_BUS_MIXER1>,
	<&display_clocks CLK_MIXER1>;
	clock-names = "bus",
	"mod";
	resets = <&display_clocks RST_WB>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	mixer1_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	mixer1_out_tcon0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&tcon0_in_mixer1>;
	};

	mixer1_out_tcon1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&tcon1_in_mixer1>;
	};
	};
	};
	};

	cpucfg@1700000 {
	compatible = "allwinner,sun8i-a83t-cpucfg";
	reg = <0x01700000 0x400>;
	};

	cci@1790000 {
	compatible = "arm,cci-400";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x01790000 0x10000>;
	ranges = <0x0 0x01790000 0x10000>;

	cci_control0: slave-if@4000 {
	compatible = "arm,cci-400-ctrl-if";
	interface-type = "ace";
	reg = <0x4000 0x1000>;
	};

	cci_control1: slave-if@5000 {
	compatible = "arm,cci-400-ctrl-if";
	interface-type = "ace";
	reg = <0x5000 0x1000>;
	};

	pmu@9000 {
	compatible = "arm,cci-400-pmu,r1";
	reg = <0x9000 0x5000>;
	interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	syscon: syscon@1c00000 {
	compatible = "allwinner,sun8i-a83t-system-controller",
	"syscon";
	reg = <0x01c00000 0x1000>;
	};

	dma: dma-controller@1c02000 {
	compatible = "allwinner,sun8i-a83t-dma";
	reg = <0x01c02000 0x1000>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_DMA>;
	resets = <&ccu RST_BUS_DMA>;
	#dma-cells = <1>;
	};

	tcon0: lcd-controller@1c0c000 {
	compatible = "allwinner,sun8i-a83t-tcon-lcd";
	reg = <0x01c0c000 0x1000>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
	clock-names = "ahb", "tcon-ch0";
	clock-output-names = "tcon-pixel-clock";
	#clock-cells = <0>;
	resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
	reset-names = "lcd", "lvds";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon0_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	tcon0_in_mixer0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&mixer0_out_tcon0>;
	};

	tcon0_in_mixer1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&mixer1_out_tcon0>;
	};
	};

	tcon0_out: port@1 {
	reg = <1>;
	};
	};
	};

	tcon1: lcd-controller@1c0d000 {
	compatible = "allwinner,sun8i-a83t-tcon-tv";
	reg = <0x01c0d000 0x1000>;
	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
	clock-names = "ahb", "tcon-ch1";
	resets = <&ccu RST_BUS_TCON1>;
	reset-names = "lcd";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon1_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	tcon1_in_mixer0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&mixer0_out_tcon1>;
	};

	tcon1_in_mixer1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&mixer1_out_tcon1>;
	};
	};

	tcon1_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	tcon1_out_hdmi: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&hdmi_in_tcon1>;
	};
	};
	};
	};

	mmc0: mmc@1c0f000 {
	compatible = "allwinner,sun8i-a83t-mmc",
	"allwinner,sun7i-a20-mmc";
	reg = <0x01c0f000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC0>,
	<&ccu CLK_MMC0>,
	<&ccu CLK_MMC0_OUTPUT>,
	<&ccu CLK_MMC0_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	resets = <&ccu RST_BUS_MMC0>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc1: mmc@1c10000 {
	compatible = "allwinner,sun8i-a83t-mmc",
	"allwinner,sun7i-a20-mmc";
	reg = <0x01c10000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC1>,
	<&ccu CLK_MMC1>,
	<&ccu CLK_MMC1_OUTPUT>,
	<&ccu CLK_MMC1_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	resets = <&ccu RST_BUS_MMC1>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc2: mmc@1c11000 {
	compatible = "allwinner,sun8i-a83t-emmc";
	reg = <0x01c11000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC2>,
	<&ccu CLK_MMC2>,
	<&ccu CLK_MMC2_OUTPUT>,
	<&ccu CLK_MMC2_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	resets = <&ccu RST_BUS_MMC2>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	sid: eeprom@1c14000 {
	compatible = "allwinner,sun8i-a83t-sid";
	reg = <0x1c14000 0x400>;
	#address-cells = <1>;
	#size-cells = <1>;

	ths_calibration: thermal-sensor-calibration@34 {
	reg = <0x34 8>;
	};
	};

	crypto: crypto@1c15000 {
	compatible = "allwinner,sun8i-a83t-crypto";
	reg = <0x01c15000 0x1000>;
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&ccu RST_BUS_SS>;
	clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
	clock-names = "bus", "mod";
	};

	usb_otg: usb@1c19000 {
	compatible = "allwinner,sun8i-a83t-musb",
	"allwinner,sun8i-a33-musb";
	reg = <0x01c19000 0x0400>;
	clocks = <&ccu CLK_BUS_OTG>;
	resets = <&ccu RST_BUS_OTG>;
	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "mc";
	phys = <&usbphy 0>;
	phy-names = "usb";
	extcon = <&usbphy 0>;
	dr_mode = "otg";
	status = "disabled";
	};

	usbphy: phy@1c19400 {
	compatible = "allwinner,sun8i-a83t-usb-phy";
	reg = <0x01c19400 0x10>,
	<0x01c1a800 0x14>,
	<0x01c1b800 0x14>;
	reg-names = "phy_ctrl",
	"pmu1",
	"pmu2";
	clocks = <&ccu CLK_USB_PHY0>,
	<&ccu CLK_USB_PHY1>,
	<&ccu CLK_USB_HSIC>,
	<&ccu CLK_USB_HSIC_12M>;
	clock-names = "usb0_phy",
	"usb1_phy",
	"usb2_phy",
	"usb2_hsic_12M";
	resets = <&ccu RST_USB_PHY0>,
	<&ccu RST_USB_PHY1>,
	<&ccu RST_USB_HSIC>;
	reset-names = "usb0_reset",
	"usb1_reset",
	"usb2_reset";
	status = "disabled";
	#phy-cells = <1>;
	};

	ehci0: usb@1c1a000 {
	compatible = "allwinner,sun8i-a83t-ehci",
	"generic-ehci";
	reg = <0x01c1a000 0x100>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_EHCI0>;
	resets = <&ccu RST_BUS_EHCI0>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	ohci0: usb@1c1a400 {
	compatible = "allwinner,sun8i-a83t-ohci",
	"generic-ohci";
	reg = <0x01c1a400 0x100>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
	resets = <&ccu RST_BUS_OHCI0>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	ehci1: usb@1c1b000 {
	compatible = "allwinner,sun8i-a83t-ehci",
	"generic-ehci";
	reg = <0x01c1b000 0x100>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_EHCI1>;
	resets = <&ccu RST_BUS_EHCI1>;
	phys = <&usbphy 2>;
	phy-names = "usb";
	status = "disabled";
	};

	ccu: clock@1c20000 {
	compatible = "allwinner,sun8i-a83t-ccu";
	reg = <0x01c20000 0x400>;
	clocks = <&osc24M>, <&osc16Md512>;
	clock-names = "hosc", "losc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pio: pinctrl@1c20800 {
	compatible = "allwinner,sun8i-a83t-pinctrl";
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x01c20800 0x400>;
	clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
	clock-names = "apb", "hosc", "losc";
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <3>;
	#gpio-cells = <3>;

	/omit-if-no-ref/
	csi_8bit_parallel_pins: csi-8bit-parallel-pins {
	pins = "PE0", "PE2", "PE3", "PE6", "PE7",
	"PE8", "PE9", "PE10", "PE11",
	"PE12", "PE13";
	function = "csi";
	};

	/omit-if-no-ref/
	csi_mclk_pin: csi-mclk-pin {
	pins = "PE1";
	function = "csi";
	};

	emac_rgmii_pins: emac-rgmii-pins {
	pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
	"PD11", "PD12", "PD13", "PD14", "PD18",
	"PD19", "PD21", "PD22", "PD23";
	function = "gmac";
	/*
	* data lines in RGMII mode use DDR mode
	* and need a higher signal drive strength
	*/
	drive-strength = <40>;
	};

	hdmi_pins: hdmi-pins {
	pins = "PH6", "PH7", "PH8";
	function = "hdmi";
	};

	i2c0_pins: i2c0-pins {
	pins = "PH0", "PH1";
	function = "i2c0";
	};

	i2c1_pins: i2c1-pins {
	pins = "PH2", "PH3";
	function = "i2c1";
	};

	/omit-if-no-ref/
	i2c2_pe_pins: i2c2-pe-pins {
	pins = "PE14", "PE15";
	function = "i2c2";
	};

	i2c2_ph_pins: i2c2-ph-pins {
	pins = "PH4", "PH5";
	function = "i2c2";
	};

	i2s1_pins: i2s1-pins {
	/* I2S1 does not have external MCLK pin */
	pins = "PG10", "PG11", "PG12", "PG13";
	function = "i2s1";
	};

	lcd_lvds_pins: lcd-lvds-pins {
	pins = "PD18", "PD19", "PD20", "PD21", "PD22",
	"PD23", "PD24", "PD25", "PD26", "PD27";
	function = "lvds0";
	};

	mmc0_pins: mmc0-pins {
	pins = "PF0", "PF1", "PF2",
	"PF3", "PF4", "PF5";
	function = "mmc0";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc1_pins: mmc1-pins {
	pins = "PG0", "PG1", "PG2",
	"PG3", "PG4", "PG5";
	function = "mmc1";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
	pins = "PC5", "PC6", "PC8", "PC9",
	"PC10", "PC11", "PC12", "PC13",
	"PC14", "PC15", "PC16";
	function = "mmc2";
	drive-strength = <30>;
	bias-pull-up;
	};

	pwm_pin: pwm-pin {
	pins = "PD28";
	function = "pwm";
	};

	spdif_tx_pin: spdif-tx-pin {
	pins = "PE18";
	function = "spdif";
	};

	uart0_pb_pins: uart0-pb-pins {
	pins = "PB9", "PB10";
	function = "uart0";
	};

	uart0_pf_pins: uart0-pf-pins {
	pins = "PF2", "PF4";
	function = "uart0";
	};

	uart1_pins: uart1-pins {
	pins = "PG6", "PG7";
	function = "uart1";
	};

	uart1_rts_cts_pins: uart1-rts-cts-pins {
	pins = "PG8", "PG9";
	function = "uart1";
	};

	/omit-if-no-ref/
	uart2_pb_pins: uart2-pb-pins {
	pins = "PB0", "PB1";
	function = "uart2";
	};
	};

	timer@1c20c00 {
	compatible = "allwinner,sun8i-a23-timer";
	reg = <0x01c20c00 0xa0>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc24M>;
	};

	watchdog@1c20ca0 {
	compatible = "allwinner,sun6i-a31-wdt";
	reg = <0x01c20ca0 0x20>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc24M>;
	};

	spdif: spdif@1c21000 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun8i-a83t-spdif",
	"allwinner,sun8i-h3-spdif";
	reg = <0x01c21000 0x400>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
	resets = <&ccu RST_BUS_SPDIF>;
	clock-names = "apb", "spdif";
	dmas = <&dma 2>;
	dma-names = "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&spdif_tx_pin>;
	status = "disabled";
	};

	i2s0: i2s@1c22000 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun8i-a83t-i2s";
	reg = <0x01c22000 0x400>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
	clock-names = "apb", "mod";
	dmas = <&dma 3>, <&dma 3>;
	resets = <&ccu RST_BUS_I2S0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2s1: i2s@1c22400 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun8i-a83t-i2s";
	reg = <0x01c22400 0x400>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
	clock-names = "apb", "mod";
	dmas = <&dma 4>, <&dma 4>;
	resets = <&ccu RST_BUS_I2S1>;
	dma-names = "rx", "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&i2s1_pins>;
	status = "disabled";
	};

	i2s2: i2s@1c22800 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun8i-a83t-i2s";
	reg = <0x01c22800 0x400>;
	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
	clock-names = "apb", "mod";
	dmas = <&dma 27>;
	resets = <&ccu RST_BUS_I2S2>;
	dma-names = "tx";
	status = "disabled";
	};

	pwm: pwm@1c21400 {
	compatible = "allwinner,sun8i-a83t-pwm",
	"allwinner,sun8i-h3-pwm";
	reg = <0x01c21400 0x400>;
	clocks = <&osc24M>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	uart0: serial@1c28000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28000 0x400>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART0>;
	resets = <&ccu RST_BUS_UART0>;
	status = "disabled";
	};

	uart1: serial@1c28400 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28400 0x400>;
	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART1>;
	resets = <&ccu RST_BUS_UART1>;
	status = "disabled";
	};

	uart2: serial@1c28800 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28800 0x400>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART2>;
	resets = <&ccu RST_BUS_UART2>;
	status = "disabled";
	};

	uart3: serial@1c28c00 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28c00 0x400>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART3>;
	resets = <&ccu RST_BUS_UART3>;
	status = "disabled";
	};

	uart4: serial@1c29000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c29000 0x400>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART4>;
	resets = <&ccu RST_BUS_UART4>;
	status = "disabled";
	};

	i2c0: i2c@1c2ac00 {
	compatible = "allwinner,sun8i-a83t-i2c",
	"allwinner,sun6i-a31-i2c";
	reg = <0x01c2ac00 0x400>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C0>;
	resets = <&ccu RST_BUS_I2C0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c1: i2c@1c2b000 {
	compatible = "allwinner,sun8i-a83t-i2c",
	"allwinner,sun6i-a31-i2c";
	reg = <0x01c2b000 0x400>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C1>;
	resets = <&ccu RST_BUS_I2C1>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c2: i2c@1c2b400 {
	compatible = "allwinner,sun8i-a83t-i2c",
	"allwinner,sun6i-a31-i2c";
	reg = <0x01c2b400 0x400>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C2>;
	resets = <&ccu RST_BUS_I2C2>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	emac: ethernet@1c30000 {
	compatible = "allwinner,sun8i-a83t-emac";
	syscon = <&syscon>;
	reg = <0x01c30000 0x104>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	clocks = <&ccu CLK_BUS_EMAC>;
	clock-names = "stmmaceth";
	resets = <&ccu RST_BUS_EMAC>;
	reset-names = "stmmaceth";
	status = "disabled";

	mdio: mdio {
	compatible = "snps,dwmac-mdio";
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	gic: interrupt-controller@1c81000 {
	compatible = "arm,gic-400";
	reg = <0x01c81000 0x1000>,
	<0x01c82000 0x2000>,
	<0x01c84000 0x2000>,
	<0x01c86000 0x2000>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	csi: camera@1cb0000 {
	compatible = "allwinner,sun8i-a83t-csi";
	reg = <0x01cb0000 0x1000>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_CSI>,
	<&ccu CLK_CSI_SCLK>,
	<&ccu CLK_DRAM_CSI>;
	clock-names = "bus", "mod", "ram";
	resets = <&ccu RST_BUS_CSI>;
	status = "disabled";

	csi_in: port {
	};
	};

	hdmi: hdmi@1ee0000 {
	compatible = "allwinner,sun8i-a83t-dw-hdmi";
	reg = <0x01ee0000 0x10000>;
	reg-io-width = <1>;
	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
	<&ccu CLK_HDMI>;
	clock-names = "iahb", "isfr", "tmds";
	resets = <&ccu RST_BUS_HDMI1>;
	reset-names = "ctrl";
	phys = <&hdmi_phy>;
	phy-names = "phy";
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_pins>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	hdmi_in: port@0 {
	reg = <0>;

	hdmi_in_tcon1: endpoint {
	remote-endpoint = <&tcon1_out_hdmi>;
	};
	};

	hdmi_out: port@1 {
	reg = <1>;
	};
	};
	};

	hdmi_phy: hdmi-phy@1ef0000 {
	compatible = "allwinner,sun8i-a83t-hdmi-phy";
	reg = <0x01ef0000 0x10000>;
	clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
	clock-names = "bus", "mod";
	resets = <&ccu RST_BUS_HDMI0>;
	reset-names = "phy";
	#phy-cells = <0>;
	};

	r_intc: interrupt-controller@1f00c00 {
	compatible = "allwinner,sun8i-a83t-r-intc",
	"allwinner,sun6i-a31-r-intc";
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x01f00c00 0x400>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	};

	r_ccu: clock@1f01400 {
	compatible = "allwinner,sun8i-a83t-r-ccu";
	reg = <0x01f01400 0x400>;
	clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
	<&ccu CLK_PLL_PERIPH>;
	clock-names = "hosc", "losc", "iosc", "pll-periph";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	r_cpucfg@1f01c00 {
	compatible = "allwinner,sun8i-a83t-r-cpucfg";
	reg = <0x1f01c00 0x400>;
	};

	r_cir: ir@1f02000 {
	compatible = "allwinner,sun8i-a83t-ir",
	"allwinner,sun6i-a31-ir";
	clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
	clock-names = "apb", "ir";
	resets = <&r_ccu RST_APB0_IR>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x01f02000 0x400>;
	pinctrl-names = "default";
	pinctrl-0 = <&r_cir_pin>;
	status = "disabled";
	};

	r_lradc: lradc@1f03c00 {
	compatible = "allwinner,sun8i-a83t-r-lradc";
	reg = <0x01f03c00 0x100>;
	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	r_pio: pinctrl@1f02c00 {
	compatible = "allwinner,sun8i-a83t-r-pinctrl";
	reg = <0x01f02c00 0x400>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
	<&osc16Md512>;
	clock-names = "apb", "hosc", "losc";
	gpio-controller;
	#gpio-cells = <3>;
	interrupt-controller;
	#interrupt-cells = <3>;

	r_cir_pin: r-cir-pin {
	pins = "PL12";
	function = "s_cir_rx";
	};

	r_rsb_pins: r-rsb-pins {
	pins = "PL0", "PL1";
	function = "s_rsb";
	drive-strength = <20>;
	bias-pull-up;
	};
	};

	r_rsb: rsb@1f03400 {
	compatible = "allwinner,sun8i-a83t-rsb",
	"allwinner,sun8i-a23-rsb";
	reg = <0x01f03400 0x400>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&r_ccu CLK_APB0_RSB>;
	clock-frequency = <3000000>;
	resets = <&r_ccu RST_APB0_RSB>;
	pinctrl-names = "default";
	pinctrl-0 = <&r_rsb_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	ths: thermal-sensor@1f04000 {
	compatible = "allwinner,sun8i-a83t-ths";
	reg = <0x01f04000 0x100>;
	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	nvmem-cells = <&ths_calibration>;
	nvmem-cell-names = "calibration";
	#thermal-sensor-cells = <1>;
	};
	};

	thermal-zones {
	cpu0_thermal: cpu0-thermal {
	polling-delay-passive = <0>;
	polling-delay = <0>;
	thermal-sensors = <&ths 0>;
	+
	+ trips {
	+ cpu0_hot: cpu-hot {
	+ temperature = <80000>;
	+ hysteresis = <2000>;
	+ type = "passive";
	+ };
	+
	+ cpu0_very_hot: cpu-very-hot {
	+ temperature = <100000>;
	+ hysteresis = <0>;
	+ type = "critical";
	+ };
	+ };
	+
	+ cooling-maps {
	+ cpu-hot-limit {
	+ trip = <&cpu0_hot>;
	+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	+ };
	+ };
	};

	cpu1_thermal: cpu1-thermal {
	polling-delay-passive = <0>;
	polling-delay = <0>;
	thermal-sensors = <&ths 1>;
	+
	+ trips {
	+ cpu1_hot: cpu-hot {
	+ temperature = <80000>;
	+ hysteresis = <2000>;
	+ type = "passive";
	+ };
	+
	+ cpu1_very_hot: cpu-very-hot {
	+ temperature = <100000>;
	+ hysteresis = <0>;
	+ type = "critical";
	+ };
	+ };
	+
	+ cooling-maps {
	+ cpu-hot-limit {
	+ trip = <&cpu1_hot>;
	+ cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	+ };
	+ };
	};

	gpu_thermal: gpu-thermal {
	polling-delay-passive = <0>;
	polling-delay = <0>;
	thermal-sensors = <&ths 2>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/sun8i-h3.dtsi b/sys/gnu/dts/arm/sun8i-h3.dtsi
	index 20217e2ca4d3..e83aa6866e7e 100644
	--- a/sys/gnu/dts/arm/sun8i-h3.dtsi
	+++ b/sys/gnu/dts/arm/sun8i-h3.dtsi
	@@ -1,288 +1,313 @@
	/*
	* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include "sunxi-h3-h5.dtsi"
	+#include <dt-bindings/thermal/thermal.h>

	/ {
	cpu0_opp_table: opp_table0 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-648000000 {
	opp-hz = /bits/ 64 <648000000>;
	opp-microvolt = <1040000 1040000 1300000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-816000000 {
	opp-hz = /bits/ 64 <816000000>;
	opp-microvolt = <1100000 1100000 1300000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};

	opp-1008000000 {
	opp-hz = /bits/ 64 <1008000000>;
	opp-microvolt = <1200000 1200000 1300000>;
	clock-latency-ns = <244144>; /* 8 32k periods */
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <0>;
	clocks = <&ccu CLK_CPUX>;
	clock-names = "cpu";
	operating-points-v2 = <&cpu0_opp_table>;
	#cooling-cells = <2>;
	};

	cpu1: cpu@1 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <1>;
	clocks = <&ccu CLK_CPUX>;
	clock-names = "cpu";
	operating-points-v2 = <&cpu0_opp_table>;
	#cooling-cells = <2>;
	};

	cpu2: cpu@2 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <2>;
	clocks = <&ccu CLK_CPUX>;
	clock-names = "cpu";
	operating-points-v2 = <&cpu0_opp_table>;
	#cooling-cells = <2>;
	};

	cpu3: cpu@3 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <3>;
	clocks = <&ccu CLK_CPUX>;
	clock-names = "cpu";
	operating-points-v2 = <&cpu0_opp_table>;
	#cooling-cells = <2>;
	};
	};

	pmu {
	compatible = "arm,cortex-a7-pmu";
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	soc {
	deinterlace: deinterlace@1400000 {
	compatible = "allwinner,sun8i-h3-deinterlace";
	reg = <0x01400000 0x20000>;
	clocks = <&ccu CLK_BUS_DEINTERLACE>,
	<&ccu CLK_DEINTERLACE>,
	<&ccu CLK_DRAM_DEINTERLACE>;
	clock-names = "bus", "mod", "ram";
	resets = <&ccu RST_BUS_DEINTERLACE>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	interconnects = <&mbus 9>;
	interconnect-names = "dma-mem";
	};

	syscon: system-control@1c00000 {
	compatible = "allwinner,sun8i-h3-system-control";
	reg = <0x01c00000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	sram_c: sram@1d00000 {
	compatible = "mmio-sram";
	reg = <0x01d00000 0x80000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x01d00000 0x80000>;

	ve_sram: sram-section@0 {
	compatible = "allwinner,sun8i-h3-sram-c1",
	"allwinner,sun4i-a10-sram-c1";
	reg = <0x000000 0x80000>;
	};
	};
	};

	video-codec@1c0e000 {
	compatible = "allwinner,sun8i-h3-video-engine";
	reg = <0x01c0e000 0x1000>;
	clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
	<&ccu CLK_DRAM_VE>;
	clock-names = "ahb", "mod", "ram";
	resets = <&ccu RST_BUS_VE>;
	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	allwinner,sram = <&ve_sram 1>;
	};

	crypto: crypto@1c15000 {
	compatible = "allwinner,sun8i-h3-crypto";
	reg = <0x01c15000 0x1000>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
	clock-names = "bus", "mod";
	resets = <&ccu RST_BUS_CE>;
	};

	mali: gpu@1c40000 {
	compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
	reg = <0x01c40000 0x10000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gp",
	"gpmmu",
	"pp0",
	"ppmmu0",
	"pp1",
	"ppmmu1",
	"pmu";
	clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
	clock-names = "bus", "core";
	resets = <&ccu RST_BUS_GPU>;

	assigned-clocks = <&ccu CLK_GPU>;
	assigned-clock-rates = <384000000>;
	};

	ths: thermal-sensor@1c25000 {
	compatible = "allwinner,sun8i-h3-ths";
	reg = <0x01c25000 0x400>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&ccu RST_BUS_THS>;
	clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
	clock-names = "bus", "mod";
	nvmem-cells = <&ths_calibration>;
	nvmem-cell-names = "calibration";
	#thermal-sensor-cells = <0>;
	};
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	polling-delay-passive = <0>;
	polling-delay = <0>;
	thermal-sensors = <&ths 0>;
	+
	+ trips {
	+ cpu_hot_trip: cpu-hot {
	+ temperature = <80000>;
	+ hysteresis = <2000>;
	+ type = "passive";
	+ };
	+
	+ cpu_very_hot_trip: cpu-very-hot {
	+ temperature = <100000>;
	+ hysteresis = <0>;
	+ type = "critical";
	+ };
	+ };
	+
	+ cooling-maps {
	+ cpu-hot-limit {
	+ trip = <&cpu_hot_trip>;
	+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	+ };
	+ };
	};
	};
	};

	&ccu {
	compatible = "allwinner,sun8i-h3-ccu";
	};

	&display_clocks {
	compatible = "allwinner,sun8i-h3-de2-clk";
	};

	&mmc0 {
	compatible = "allwinner,sun7i-a20-mmc";
	clocks = <&ccu CLK_BUS_MMC0>,
	<&ccu CLK_MMC0>,
	<&ccu CLK_MMC0_OUTPUT>,
	<&ccu CLK_MMC0_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	};

	&mmc1 {
	compatible = "allwinner,sun7i-a20-mmc";
	clocks = <&ccu CLK_BUS_MMC1>,
	<&ccu CLK_MMC1>,
	<&ccu CLK_MMC1_OUTPUT>,
	<&ccu CLK_MMC1_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	};

	&mmc2 {
	compatible = "allwinner,sun7i-a20-mmc";
	clocks = <&ccu CLK_BUS_MMC2>,
	<&ccu CLK_MMC2>,
	<&ccu CLK_MMC2_OUTPUT>,
	<&ccu CLK_MMC2_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	};

	&pio {
	compatible = "allwinner,sun8i-h3-pinctrl";
	};

	&rtc {
	compatible = "allwinner,sun8i-h3-rtc";
	};

	&sid {
	compatible = "allwinner,sun8i-h3-sid";
	};
	diff --git a/sys/gnu/dts/arm/sun8i-r40.dtsi b/sys/gnu/dts/arm/sun8i-r40.dtsi
	index a9d5d6ddbd71..b782041e0e04 100644
	--- a/sys/gnu/dts/arm/sun8i-r40.dtsi
	+++ b/sys/gnu/dts/arm/sun8i-r40.dtsi
	@@ -1,1021 +1,1051 @@
	/*
	* Copyright 2017 Chen-Yu Tsai <wens@csie.org>
	* Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/sun8i-de2.h>
	#include <dt-bindings/clock/sun8i-r40-ccu.h>
	#include <dt-bindings/clock/sun8i-tcon-top.h>
	#include <dt-bindings/reset/sun8i-r40-ccu.h>
	#include <dt-bindings/reset/sun8i-de2.h>
	+#include <dt-bindings/thermal/thermal.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	clocks {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	osc24M: osc24M {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-accuracy = <50000>;
	clock-output-names = "osc24M";
	};

	osc32k: osc32k {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	clock-accuracy = <20000>;
	clock-output-names = "ext-osc32k";
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <0>;
	};

	cpu1: cpu@1 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <1>;
	};

	cpu2: cpu@2 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <2>;
	};

	cpu3: cpu@3 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <3>;
	};
	};

	de: display-engine {
	compatible = "allwinner,sun8i-r40-display-engine";
	allwinner,pipelines = <&mixer0>, <&mixer1>;
	status = "disabled";
	};

	+ thermal-zones {
	+ cpu_thermal: cpu0-thermal {
	+ /* milliseconds */
	+ polling-delay-passive = <0>;
	+ polling-delay = <0>;
	+ thermal-sensors = <&ths 0>;
	+ };
	+
	+ gpu_thermal: gpu-thermal {
	+ /* milliseconds */
	+ polling-delay-passive = <0>;
	+ polling-delay = <0>;
	+ thermal-sensors = <&ths 1>;
	+ };
	+ };
	+
	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	display_clocks: clock@1000000 {
	compatible = "allwinner,sun8i-r40-de2-clk",
	"allwinner,sun8i-h3-de2-clk";
	- reg = <0x01000000 0x100000>;
	+ reg = <0x01000000 0x10000>;
	clocks = <&ccu CLK_BUS_DE>,
	<&ccu CLK_DE>;
	clock-names = "bus",
	"mod";
	resets = <&ccu RST_BUS_DE>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	mixer0: mixer@1100000 {
	compatible = "allwinner,sun8i-r40-de2-mixer-0";
	reg = <0x01100000 0x100000>;
	clocks = <&display_clocks CLK_BUS_MIXER0>,
	<&display_clocks CLK_MIXER0>;
	clock-names = "bus",
	"mod";
	resets = <&display_clocks RST_MIXER0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	mixer0_out: port@1 {
	reg = <1>;
	mixer0_out_tcon_top: endpoint {
	remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
	};
	};
	};
	};

	mixer1: mixer@1200000 {
	compatible = "allwinner,sun8i-r40-de2-mixer-1";
	reg = <0x01200000 0x100000>;
	clocks = <&display_clocks CLK_BUS_MIXER1>,
	<&display_clocks CLK_MIXER1>;
	clock-names = "bus",
	"mod";
	resets = <&display_clocks RST_WB>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	mixer1_out: port@1 {
	reg = <1>;
	mixer1_out_tcon_top: endpoint {
	remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
	};
	};
	};
	};

	nmi_intc: interrupt-controller@1c00030 {
	compatible = "allwinner,sun7i-a20-sc-nmi";
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x01c00030 0x0c>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	};

	spi0: spi@1c05000 {
	compatible = "allwinner,sun8i-r40-spi",
	"allwinner,sun8i-h3-spi";
	reg = <0x01c05000 0x1000>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
	clock-names = "ahb", "mod";
	resets = <&ccu RST_BUS_SPI0>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	spi1: spi@1c06000 {
	compatible = "allwinner,sun8i-r40-spi",
	"allwinner,sun8i-h3-spi";
	reg = <0x01c06000 0x1000>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
	clock-names = "ahb", "mod";
	resets = <&ccu RST_BUS_SPI1>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	csi0: csi@1c09000 {
	compatible = "allwinner,sun8i-r40-csi0",
	"allwinner,sun7i-a20-csi0";
	reg = <0x01c09000 0x1000>;
	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
	<&ccu CLK_DRAM_CSI0>;
	clock-names = "bus", "isp", "ram";
	resets = <&ccu RST_BUS_CSI0>;
	interconnects = <&mbus 5>;
	interconnect-names = "dma-mem";
	status = "disabled";
	};

	mmc0: mmc@1c0f000 {
	compatible = "allwinner,sun8i-r40-mmc",
	"allwinner,sun50i-a64-mmc";
	reg = <0x01c0f000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
	clock-names = "ahb", "mmc";
	resets = <&ccu RST_BUS_MMC0>;
	reset-names = "ahb";
	pinctrl-0 = <&mmc0_pins>;
	pinctrl-names = "default";
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc1: mmc@1c10000 {
	compatible = "allwinner,sun8i-r40-mmc",
	"allwinner,sun50i-a64-mmc";
	reg = <0x01c10000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
	clock-names = "ahb", "mmc";
	resets = <&ccu RST_BUS_MMC1>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc2: mmc@1c11000 {
	compatible = "allwinner,sun8i-r40-emmc",
	"allwinner,sun50i-a64-emmc";
	reg = <0x01c11000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
	clock-names = "ahb", "mmc";
	resets = <&ccu RST_BUS_MMC2>;
	reset-names = "ahb";
	pinctrl-0 = <&mmc2_pins>;
	pinctrl-names = "default";
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc3: mmc@1c12000 {
	compatible = "allwinner,sun8i-r40-mmc",
	"allwinner,sun50i-a64-mmc";
	reg = <0x01c12000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
	clock-names = "ahb", "mmc";
	resets = <&ccu RST_BUS_MMC3>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	usbphy: phy@1c13400 {
	compatible = "allwinner,sun8i-r40-usb-phy";
	reg = <0x01c13400 0x14>,
	<0x01c14800 0x4>,
	<0x01c19800 0x4>,
	<0x01c1c800 0x4>;
	reg-names = "phy_ctrl",
	"pmu0",
	"pmu1",
	"pmu2";
	clocks = <&ccu CLK_USB_PHY0>,
	<&ccu CLK_USB_PHY1>,
	<&ccu CLK_USB_PHY2>;
	clock-names = "usb0_phy",
	"usb1_phy",
	"usb2_phy";
	resets = <&ccu RST_USB_PHY0>,
	<&ccu RST_USB_PHY1>,
	<&ccu RST_USB_PHY2>;
	reset-names = "usb0_reset",
	"usb1_reset",
	"usb2_reset";
	status = "disabled";
	#phy-cells = <1>;
	};

	crypto: crypto@1c15000 {
	compatible = "allwinner,sun8i-r40-crypto";
	reg = <0x01c15000 0x1000>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
	clock-names = "bus", "mod";
	resets = <&ccu RST_BUS_CE>;
	};

	spi2: spi@1c17000 {
	compatible = "allwinner,sun8i-r40-spi",
	"allwinner,sun8i-h3-spi";
	reg = <0x01c17000 0x1000>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
	clock-names = "ahb", "mod";
	resets = <&ccu RST_BUS_SPI2>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	ahci: sata@1c18000 {
	compatible = "allwinner,sun8i-r40-ahci";
	reg = <0x01c18000 0x1000>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
	resets = <&ccu RST_BUS_SATA>;
	reset-names = "ahci";
	status = "disabled";
	};

	ehci1: usb@1c19000 {
	compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
	reg = <0x01c19000 0x100>;
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_EHCI1>;
	resets = <&ccu RST_BUS_EHCI1>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	ohci1: usb@1c19400 {
	compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
	reg = <0x01c19400 0x100>;
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_OHCI1>,
	<&ccu CLK_USB_OHCI1>;
	resets = <&ccu RST_BUS_OHCI1>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	ehci2: usb@1c1c000 {
	compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
	reg = <0x01c1c000 0x100>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_EHCI2>;
	resets = <&ccu RST_BUS_EHCI2>;
	phys = <&usbphy 2>;
	phy-names = "usb";
	status = "disabled";
	};

	ohci2: usb@1c1c400 {
	compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
	reg = <0x01c1c400 0x100>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_OHCI2>,
	<&ccu CLK_USB_OHCI2>;
	resets = <&ccu RST_BUS_OHCI2>;
	phys = <&usbphy 2>;
	phy-names = "usb";
	status = "disabled";
	};

	spi3: spi@1c1f000 {
	compatible = "allwinner,sun8i-r40-spi",
	"allwinner,sun8i-h3-spi";
	reg = <0x01c1f000 0x1000>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
	clock-names = "ahb", "mod";
	resets = <&ccu RST_BUS_SPI3>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	ccu: clock@1c20000 {
	compatible = "allwinner,sun8i-r40-ccu";
	reg = <0x01c20000 0x400>;
	clocks = <&osc24M>, <&rtc 0>;
	clock-names = "hosc", "losc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	rtc: rtc@1c20400 {
	compatible = "allwinner,sun8i-r40-rtc";
	reg = <0x01c20400 0x400>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clock-output-names = "osc32k", "osc32k-out";
	clocks = <&osc32k>;
	#clock-cells = <1>;
	};

	pio: pinctrl@1c20800 {
	compatible = "allwinner,sun8i-r40-pinctrl";
	reg = <0x01c20800 0x400>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
	clock-names = "apb", "hosc", "losc";
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <3>;
	#gpio-cells = <3>;

	clk_out_a_pin: clk-out-a-pin {
	pins = "PI12";
	function = "clk_out_a";
	};

	/omit-if-no-ref/
	csi0_8bits_pins: csi0-8bits-pins {
	pins = "PE0", "PE2", "PE3", "PE4", "PE5",
	"PE6", "PE7", "PE8", "PE9", "PE10",
	"PE11";
	function = "csi0";
	};

	/omit-if-no-ref/
	csi0_mclk_pin: csi0-mclk-pin {
	pins = "PE1";
	function = "csi0";
	};

	gmac_rgmii_pins: gmac-rgmii-pins {
	pins = "PA0", "PA1", "PA2", "PA3",
	"PA4", "PA5", "PA6", "PA7",
	"PA8", "PA10", "PA11", "PA12",
	"PA13", "PA15", "PA16";
	function = "gmac";
	/*
	* data lines in RGMII mode use DDR mode
	* and need a higher signal drive strength
	*/
	drive-strength = <40>;
	};

	i2c0_pins: i2c0-pins {
	pins = "PB0", "PB1";
	function = "i2c0";
	};

	i2c1_pins: i2c1-pins {
	pins = "PB18", "PB19";
	function = "i2c1";
	};

	i2c2_pins: i2c2-pins {
	pins = "PB20", "PB21";
	function = "i2c2";
	};

	i2c3_pins: i2c3-pins {
	pins = "PI0", "PI1";
	function = "i2c3";
	};

	i2c4_pins: i2c4-pins {
	pins = "PI2", "PI3";
	function = "i2c4";
	};

	mmc0_pins: mmc0-pins {
	pins = "PF0", "PF1", "PF2",
	"PF3", "PF4", "PF5";
	function = "mmc0";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc1_pg_pins: mmc1-pg-pins {
	pins = "PG0", "PG1", "PG2",
	"PG3", "PG4", "PG5";
	function = "mmc1";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc2_pins: mmc2-pins {
	pins = "PC5", "PC6", "PC7", "PC8", "PC9",
	"PC10", "PC11", "PC12", "PC13", "PC14",
	"PC15", "PC24";
	function = "mmc2";
	drive-strength = <30>;
	bias-pull-up;
	};

	/omit-if-no-ref/
	spi0_pc_pins: spi0-pc-pins {
	pins = "PC0", "PC1", "PC2";
	function = "spi0";
	};

	/omit-if-no-ref/
	spi0_cs0_pc_pin: spi0-cs0-pc-pin {
	pins = "PC23";
	function = "spi0";
	};

	/omit-if-no-ref/
	spi1_pi_pins: spi1-pi-pins {
	pins = "PI17", "PI18", "PI19";
	function = "spi1";
	};

	/omit-if-no-ref/
	spi1_cs0_pi_pin: spi1-cs0-pi-pin {
	pins = "PI16";
	function = "spi1";
	};

	/omit-if-no-ref/
	spi1_cs1_pi_pin: spi1-cs1-pi-pin {
	pins = "PI15";
	function = "spi1";
	};

	uart0_pb_pins: uart0-pb-pins {
	pins = "PB22", "PB23";
	function = "uart0";
	};

	uart3_pg_pins: uart3-pg-pins {
	pins = "PG6", "PG7";
	function = "uart3";
	};

	uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
	pins = "PG8", "PG9";
	function = "uart3";
	};
	};

	wdt: watchdog@1c20c90 {
	compatible = "allwinner,sun4i-a10-wdt";
	reg = <0x01c20c90 0x10>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc24M>;
	};

	+ ths: thermal-sensor@1c24c00 {
	+ compatible = "allwinner,sun8i-r40-ths";
	+ reg = <0x01c24c00 0x100>;
	+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
	+ clock-names = "bus", "mod";
	+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	+ resets = <&ccu RST_BUS_THS>;
	+ /* TODO: add nvmem-cells for calibration */
	+ #thermal-sensor-cells = <1>;
	+ };
	+
	uart0: serial@1c28000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28000 0x400>;
	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART0>;
	resets = <&ccu RST_BUS_UART0>;
	status = "disabled";
	};

	uart1: serial@1c28400 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28400 0x400>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART1>;
	resets = <&ccu RST_BUS_UART1>;
	status = "disabled";
	};

	uart2: serial@1c28800 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28800 0x400>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART2>;
	resets = <&ccu RST_BUS_UART2>;
	status = "disabled";
	};

	uart3: serial@1c28c00 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28c00 0x400>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART3>;
	resets = <&ccu RST_BUS_UART3>;
	status = "disabled";
	};

	uart4: serial@1c29000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c29000 0x400>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART4>;
	resets = <&ccu RST_BUS_UART4>;
	status = "disabled";
	};

	uart5: serial@1c29400 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c29400 0x400>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART5>;
	resets = <&ccu RST_BUS_UART5>;
	status = "disabled";
	};

	uart6: serial@1c29800 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c29800 0x400>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART6>;
	resets = <&ccu RST_BUS_UART6>;
	status = "disabled";
	};

	uart7: serial@1c29c00 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c29c00 0x400>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART7>;
	resets = <&ccu RST_BUS_UART7>;
	status = "disabled";
	};

	i2c0: i2c@1c2ac00 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2ac00 0x400>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C0>;
	resets = <&ccu RST_BUS_I2C0>;
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "default";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c1: i2c@1c2b000 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2b000 0x400>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C1>;
	resets = <&ccu RST_BUS_I2C1>;
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-names = "default";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c2: i2c@1c2b400 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2b400 0x400>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C2>;
	resets = <&ccu RST_BUS_I2C2>;
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-names = "default";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c3: i2c@1c2b800 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2b800 0x400>;
	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C3>;
	resets = <&ccu RST_BUS_I2C3>;
	pinctrl-0 = <&i2c3_pins>;
	pinctrl-names = "default";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c4: i2c@1c2c000 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2c000 0x400>;
	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C4>;
	resets = <&ccu RST_BUS_I2C4>;
	pinctrl-0 = <&i2c4_pins>;
	pinctrl-names = "default";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	gmac: ethernet@1c50000 {
	compatible = "allwinner,sun8i-r40-gmac";
	syscon = <&ccu>;
	reg = <0x01c50000 0x10000>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	resets = <&ccu RST_BUS_GMAC>;
	reset-names = "stmmaceth";
	clocks = <&ccu CLK_BUS_GMAC>;
	clock-names = "stmmaceth";
	status = "disabled";

	gmac_mdio: mdio {
	compatible = "snps,dwmac-mdio";
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	mbus: dram-controller@1c62000 {
	compatible = "allwinner,sun8i-r40-mbus";
	reg = <0x01c62000 0x1000>;
	clocks = <&ccu 155>;
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	dma-ranges = <0x00000000 0x40000000 0x80000000>;
	#interconnect-cells = <1>;
	};

	tcon_top: tcon-top@1c70000 {
	compatible = "allwinner,sun8i-r40-tcon-top";
	reg = <0x01c70000 0x1000>;
	clocks = <&ccu CLK_BUS_TCON_TOP>,
	<&ccu CLK_TCON_TV0>,
	<&ccu CLK_TVE0>,
	<&ccu CLK_TCON_TV1>,
	<&ccu CLK_TVE1>,
	<&ccu CLK_DSI_DPHY>;
	clock-names = "bus",
	"tcon-tv0",
	"tve0",
	"tcon-tv1",
	"tve1",
	"dsi";
	clock-output-names = "tcon-top-tv0",
	"tcon-top-tv1",
	"tcon-top-dsi";
	resets = <&ccu RST_BUS_TCON_TOP>;
	#clock-cells = <1>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon_top_mixer0_in: port@0 {
	reg = <0>;

	tcon_top_mixer0_in_mixer0: endpoint {
	remote-endpoint = <&mixer0_out_tcon_top>;
	};
	};

	tcon_top_mixer0_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
	reg = <0>;
	};

	tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
	reg = <1>;
	};

	tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
	};

	tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
	};
	};

	tcon_top_mixer1_in: port@2 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <2>;

	tcon_top_mixer1_in_mixer1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&mixer1_out_tcon_top>;
	};
	};

	tcon_top_mixer1_out: port@3 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <3>;

	tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
	reg = <0>;
	};

	tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
	reg = <1>;
	};

	tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
	};

	tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
	};
	};

	tcon_top_hdmi_in: port@4 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <4>;

	tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&tcon_tv0_out_tcon_top>;
	};

	tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&tcon_tv1_out_tcon_top>;
	};
	};

	tcon_top_hdmi_out: port@5 {
	reg = <5>;

	tcon_top_hdmi_out_hdmi: endpoint {
	remote-endpoint = <&hdmi_in_tcon_top>;
	};
	};
	};
	};

	tcon_tv0: lcd-controller@1c73000 {
	compatible = "allwinner,sun8i-r40-tcon-tv";
	reg = <0x01c73000 0x1000>;
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
	clock-names = "ahb", "tcon-ch1";
	resets = <&ccu RST_BUS_TCON_TV0>;
	reset-names = "lcd";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon_tv0_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
	};

	tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
	};
	};

	tcon_tv0_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	tcon_tv0_out_tcon_top: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
	};
	};
	};
	};

	tcon_tv1: lcd-controller@1c74000 {
	compatible = "allwinner,sun8i-r40-tcon-tv";
	reg = <0x01c74000 0x1000>;
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
	clock-names = "ahb", "tcon-ch1";
	resets = <&ccu RST_BUS_TCON_TV1>;
	reset-names = "lcd";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon_tv1_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
	};

	tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
	};
	};

	tcon_tv1_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	tcon_tv1_out_tcon_top: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
	};
	};
	};
	};

	gic: interrupt-controller@1c81000 {
	compatible = "arm,gic-400";
	reg = <0x01c81000 0x1000>,
	<0x01c82000 0x2000>,
	<0x01c84000 0x2000>,
	<0x01c86000 0x2000>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	hdmi: hdmi@1ee0000 {
	compatible = "allwinner,sun8i-r40-dw-hdmi",
	"allwinner,sun8i-a83t-dw-hdmi";
	reg = <0x01ee0000 0x10000>;
	reg-io-width = <1>;
	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
	<&ccu CLK_HDMI>;
	clock-names = "iahb", "isfr", "tmds";
	resets = <&ccu RST_BUS_HDMI1>;
	reset-names = "ctrl";
	phys = <&hdmi_phy>;
	phy-names = "phy";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	hdmi_in: port@0 {
	reg = <0>;

	hdmi_in_tcon_top: endpoint {
	remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
	};
	};

	hdmi_out: port@1 {
	reg = <1>;
	};
	};
	};

	hdmi_phy: hdmi-phy@1ef0000 {
	compatible = "allwinner,sun8i-r40-hdmi-phy";
	reg = <0x01ef0000 0x10000>;
	clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
	<&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
	clock-names = "bus", "mod", "pll-0", "pll-1";
	resets = <&ccu RST_BUS_HDMI0>;
	reset-names = "phy";
	#phy-cells = <0>;
	};
	};

	pmu {
	compatible = "arm,cortex-a7-pmu";
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	};
	};
	diff --git a/sys/gnu/dts/arm/sun8i-v3s.dtsi b/sys/gnu/dts/arm/sun8i-v3s.dtsi
	index 81ea50838cd5..e5312869c0d2 100644
	--- a/sys/gnu/dts/arm/sun8i-v3s.dtsi
	+++ b/sys/gnu/dts/arm/sun8i-v3s.dtsi
	@@ -1,432 +1,432 @@
	/*
	* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/sun8i-v3s-ccu.h>
	#include <dt-bindings/reset/sun8i-v3s-ccu.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <0>;
	clocks = <&ccu CLK_CPU>;
	};
	};

	de: display-engine {
	compatible = "allwinner,sun8i-v3s-display-engine";
	allwinner,pipelines = <&mixer0>;
	status = "disabled";
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	clocks {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	osc24M: osc24M_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-accuracy = <50000>;
	clock-output-names = "osc24M";
	};

	osc32k: osc32k_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	clock-accuracy = <50000>;
	clock-output-names = "ext-osc32k";
	};
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	display_clocks: clock@1000000 {
	compatible = "allwinner,sun8i-v3s-de2-clk";
	- reg = <0x01000000 0x100000>;
	+ reg = <0x01000000 0x10000>;
	clocks = <&ccu CLK_BUS_DE>,
	<&ccu CLK_DE>;
	clock-names = "bus",
	"mod";
	resets = <&ccu RST_BUS_DE>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	mixer0: mixer@1100000 {
	compatible = "allwinner,sun8i-v3s-de2-mixer";
	reg = <0x01100000 0x100000>;
	clocks = <&display_clocks 0>,
	<&display_clocks 6>;
	clock-names = "bus",
	"mod";
	resets = <&display_clocks 0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	mixer0_out: port@1 {
	reg = <1>;

	mixer0_out_tcon0: endpoint {
	remote-endpoint = <&tcon0_in_mixer0>;
	};
	};
	};
	};

	tcon0: lcd-controller@1c0c000 {
	compatible = "allwinner,sun8i-v3s-tcon";
	reg = <0x01c0c000 0x1000>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_TCON0>,
	<&ccu CLK_TCON0>;
	clock-names = "ahb",
	"tcon-ch0";
	clock-output-names = "tcon-pixel-clock";
	#clock-cells = <0>;
	resets = <&ccu RST_BUS_TCON0>;
	reset-names = "lcd";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon0_in: port@0 {
	reg = <0>;

	tcon0_in_mixer0: endpoint {
	remote-endpoint = <&mixer0_out_tcon0>;
	};
	};

	tcon0_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;
	};
	};
	};


	mmc0: mmc@1c0f000 {
	compatible = "allwinner,sun7i-a20-mmc";
	reg = <0x01c0f000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC0>,
	<&ccu CLK_MMC0>,
	<&ccu CLK_MMC0_OUTPUT>,
	<&ccu CLK_MMC0_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	resets = <&ccu RST_BUS_MMC0>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc1: mmc@1c10000 {
	compatible = "allwinner,sun7i-a20-mmc";
	reg = <0x01c10000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC1>,
	<&ccu CLK_MMC1>,
	<&ccu CLK_MMC1_OUTPUT>,
	<&ccu CLK_MMC1_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	resets = <&ccu RST_BUS_MMC1>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc2: mmc@1c11000 {
	compatible = "allwinner,sun7i-a20-mmc";
	reg = <0x01c11000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC2>,
	<&ccu CLK_MMC2>,
	<&ccu CLK_MMC2_OUTPUT>,
	<&ccu CLK_MMC2_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	resets = <&ccu RST_BUS_MMC2>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	usb_otg: usb@1c19000 {
	compatible = "allwinner,sun8i-h3-musb";
	reg = <0x01c19000 0x0400>;
	clocks = <&ccu CLK_BUS_OTG>;
	resets = <&ccu RST_BUS_OTG>;
	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "mc";
	phys = <&usbphy 0>;
	phy-names = "usb";
	extcon = <&usbphy 0>;
	status = "disabled";
	};

	usbphy: phy@1c19400 {
	compatible = "allwinner,sun8i-v3s-usb-phy";
	reg = <0x01c19400 0x2c>,
	<0x01c1a800 0x4>;
	reg-names = "phy_ctrl",
	"pmu0";
	clocks = <&ccu CLK_USB_PHY0>;
	clock-names = "usb0_phy";
	resets = <&ccu RST_USB_PHY0>;
	reset-names = "usb0_reset";
	status = "disabled";
	#phy-cells = <1>;
	};

	ccu: clock@1c20000 {
	compatible = "allwinner,sun8i-v3s-ccu";
	reg = <0x01c20000 0x400>;
	clocks = <&osc24M>, <&rtc 0>;
	clock-names = "hosc", "losc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	rtc: rtc@1c20400 {
	#clock-cells = <1>;
	compatible = "allwinner,sun8i-v3-rtc";
	reg = <0x01c20400 0x54>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc32k>;
	clock-output-names = "osc32k", "osc32k-out";
	};

	pio: pinctrl@1c20800 {
	compatible = "allwinner,sun8i-v3s-pinctrl";
	reg = <0x01c20800 0x400>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
	clock-names = "apb", "hosc", "losc";
	gpio-controller;
	#gpio-cells = <3>;
	interrupt-controller;
	#interrupt-cells = <3>;

	i2c0_pins: i2c0-pins {
	pins = "PB6", "PB7";
	function = "i2c0";
	};

	uart0_pb_pins: uart0-pb-pins {
	pins = "PB8", "PB9";
	function = "uart0";
	};

	mmc0_pins: mmc0-pins {
	pins = "PF0", "PF1", "PF2", "PF3",
	"PF4", "PF5";
	function = "mmc0";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc1_pins: mmc1-pins {
	pins = "PG0", "PG1", "PG2", "PG3",
	"PG4", "PG5";
	function = "mmc1";
	drive-strength = <30>;
	bias-pull-up;
	};

	spi0_pins: spi0-pins {
	pins = "PC0", "PC1", "PC2", "PC3";
	function = "spi0";
	};
	};

	timer@1c20c00 {
	compatible = "allwinner,sun8i-v3s-timer";
	reg = <0x01c20c00 0xa0>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc24M>;
	};

	wdt0: watchdog@1c20ca0 {
	compatible = "allwinner,sun6i-a31-wdt";
	reg = <0x01c20ca0 0x20>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc24M>;
	};

	lradc: lradc@1c22800 {
	compatible = "allwinner,sun4i-a10-lradc-keys";
	reg = <0x01c22800 0x400>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	uart0: serial@1c28000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28000 0x400>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART0>;
	resets = <&ccu RST_BUS_UART0>;
	status = "disabled";
	};

	uart1: serial@1c28400 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28400 0x400>;
	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART1>;
	resets = <&ccu RST_BUS_UART1>;
	status = "disabled";
	};

	uart2: serial@1c28800 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28800 0x400>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART2>;
	resets = <&ccu RST_BUS_UART2>;
	status = "disabled";
	};

	i2c0: i2c@1c2ac00 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2ac00 0x400>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C0>;
	resets = <&ccu RST_BUS_I2C0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c1: i2c@1c2b000 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2b000 0x400>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C1>;
	resets = <&ccu RST_BUS_I2C1>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	spi0: spi@1c68000 {
	compatible = "allwinner,sun8i-h3-spi";
	reg = <0x01c68000 0x1000>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
	clock-names = "ahb", "mod";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pins>;
	resets = <&ccu RST_BUS_SPI0>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	gic: interrupt-controller@1c81000 {
	compatible = "arm,gic-400";
	reg = <0x01c81000 0x1000>,
	<0x01c82000 0x1000>,
	<0x01c84000 0x2000>,
	<0x01c86000 0x2000>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/sunxi-h3-h5.dtsi b/sys/gnu/dts/arm/sunxi-h3-h5.dtsi
	index 5e9c3060aa08..01a5df9aa71b 100644
	--- a/sys/gnu/dts/arm/sunxi-h3-h5.dtsi
	+++ b/sys/gnu/dts/arm/sunxi-h3-h5.dtsi
	@@ -1,897 +1,914 @@
	/*
	* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include <dt-bindings/clock/sun8i-de2.h>
	#include <dt-bindings/clock/sun8i-h3-ccu.h>
	#include <dt-bindings/clock/sun8i-r-ccu.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/reset/sun8i-de2.h>
	#include <dt-bindings/reset/sun8i-h3-ccu.h>
	#include <dt-bindings/reset/sun8i-r-ccu.h>

	/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	chosen {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	framebuffer-hdmi {
	compatible = "allwinner,simple-framebuffer",
	"simple-framebuffer";
	allwinner,pipeline = "mixer0-lcd0-hdmi";
	clocks = <&display_clocks CLK_MIXER0>,
	<&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
	status = "disabled";
	};

	framebuffer-tve {
	compatible = "allwinner,simple-framebuffer",
	"simple-framebuffer";
	allwinner,pipeline = "mixer1-lcd1-tve";
	clocks = <&display_clocks CLK_MIXER1>,
	<&ccu CLK_TVE>;
	status = "disabled";
	};
	};

	clocks {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	osc24M: osc24M_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-accuracy = <50000>;
	clock-output-names = "osc24M";
	};

	osc32k: osc32k_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	clock-accuracy = <50000>;
	clock-output-names = "ext_osc32k";
	};
	};

	de: display-engine {
	compatible = "allwinner,sun8i-h3-display-engine";
	allwinner,pipelines = <&mixer0>;
	status = "disabled";
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	dma-ranges;
	ranges;

	display_clocks: clock@1000000 {
	/* compatible is in per SoC .dtsi file */
	- reg = <0x01000000 0x100000>;
	+ reg = <0x01000000 0x10000>;
	clocks = <&ccu CLK_BUS_DE>,
	<&ccu CLK_DE>;
	clock-names = "bus",
	"mod";
	resets = <&ccu RST_BUS_DE>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	mixer0: mixer@1100000 {
	compatible = "allwinner,sun8i-h3-de2-mixer-0";
	reg = <0x01100000 0x100000>;
	clocks = <&display_clocks CLK_BUS_MIXER0>,
	<&display_clocks CLK_MIXER0>;
	clock-names = "bus",
	"mod";
	resets = <&display_clocks RST_MIXER0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	mixer0_out: port@1 {
	reg = <1>;

	mixer0_out_tcon0: endpoint {
	remote-endpoint = <&tcon0_in_mixer0>;
	};
	};
	};
	};

	dma: dma-controller@1c02000 {
	compatible = "allwinner,sun8i-h3-dma";
	reg = <0x01c02000 0x1000>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_DMA>;
	resets = <&ccu RST_BUS_DMA>;
	#dma-cells = <1>;
	};

	tcon0: lcd-controller@1c0c000 {
	compatible = "allwinner,sun8i-h3-tcon-tv",
	"allwinner,sun8i-a83t-tcon-tv";
	reg = <0x01c0c000 0x1000>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
	clock-names = "ahb", "tcon-ch1";
	resets = <&ccu RST_BUS_TCON0>;
	reset-names = "lcd";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon0_in: port@0 {
	reg = <0>;

	tcon0_in_mixer0: endpoint {
	remote-endpoint = <&mixer0_out_tcon0>;
	};
	};

	tcon0_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	tcon0_out_hdmi: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&hdmi_in_tcon0>;
	};
	};
	};
	};

	mmc0: mmc@1c0f000 {
	/* compatible and clocks are in per SoC .dtsi file */
	reg = <0x01c0f000 0x1000>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	resets = <&ccu RST_BUS_MMC0>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc1: mmc@1c10000 {
	/* compatible and clocks are in per SoC .dtsi file */
	reg = <0x01c10000 0x1000>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	resets = <&ccu RST_BUS_MMC1>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc2: mmc@1c11000 {
	/* compatible and clocks are in per SoC .dtsi file */
	reg = <0x01c11000 0x1000>;
	resets = <&ccu RST_BUS_MMC2>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	sid: eeprom@1c14000 {
	/* compatible is in per SoC .dtsi file */
	reg = <0x1c14000 0x400>;
	#address-cells = <1>;
	#size-cells = <1>;

	ths_calibration: thermal-sensor-calibration@34 {
	reg = <0x34 4>;
	};
	};

	usb_otg: usb@1c19000 {
	compatible = "allwinner,sun8i-h3-musb";
	reg = <0x01c19000 0x400>;
	clocks = <&ccu CLK_BUS_OTG>;
	resets = <&ccu RST_BUS_OTG>;
	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "mc";
	phys = <&usbphy 0>;
	phy-names = "usb";
	extcon = <&usbphy 0>;
	dr_mode = "otg";
	status = "disabled";
	};

	usbphy: phy@1c19400 {
	compatible = "allwinner,sun8i-h3-usb-phy";
	reg = <0x01c19400 0x2c>,
	<0x01c1a800 0x4>,
	<0x01c1b800 0x4>,
	<0x01c1c800 0x4>,
	<0x01c1d800 0x4>;
	reg-names = "phy_ctrl",
	"pmu0",
	"pmu1",
	"pmu2",
	"pmu3";
	clocks = <&ccu CLK_USB_PHY0>,
	<&ccu CLK_USB_PHY1>,
	<&ccu CLK_USB_PHY2>,
	<&ccu CLK_USB_PHY3>;
	clock-names = "usb0_phy",
	"usb1_phy",
	"usb2_phy",
	"usb3_phy";
	resets = <&ccu RST_USB_PHY0>,
	<&ccu RST_USB_PHY1>,
	<&ccu RST_USB_PHY2>,
	<&ccu RST_USB_PHY3>;
	reset-names = "usb0_reset",
	"usb1_reset",
	"usb2_reset",
	"usb3_reset";
	status = "disabled";
	#phy-cells = <1>;
	};

	ehci0: usb@1c1a000 {
	compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
	reg = <0x01c1a000 0x100>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
	resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
	status = "disabled";
	};

	ohci0: usb@1c1a400 {
	compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
	reg = <0x01c1a400 0x100>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
	<&ccu CLK_USB_OHCI0>;
	resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
	status = "disabled";
	};

	ehci1: usb@1c1b000 {
	compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
	reg = <0x01c1b000 0x100>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
	resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	ohci1: usb@1c1b400 {
	compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
	reg = <0x01c1b400 0x100>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
	<&ccu CLK_USB_OHCI1>;
	resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	ehci2: usb@1c1c000 {
	compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
	reg = <0x01c1c000 0x100>;
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
	resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
	phys = <&usbphy 2>;
	phy-names = "usb";
	status = "disabled";
	};

	ohci2: usb@1c1c400 {
	compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
	reg = <0x01c1c400 0x100>;
	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
	<&ccu CLK_USB_OHCI2>;
	resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
	phys = <&usbphy 2>;
	phy-names = "usb";
	status = "disabled";
	};

	ehci3: usb@1c1d000 {
	compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
	reg = <0x01c1d000 0x100>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
	resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
	phys = <&usbphy 3>;
	phy-names = "usb";
	status = "disabled";
	};

	ohci3: usb@1c1d400 {
	compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
	reg = <0x01c1d400 0x100>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
	<&ccu CLK_USB_OHCI3>;
	resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
	phys = <&usbphy 3>;
	phy-names = "usb";
	status = "disabled";
	};

	ccu: clock@1c20000 {
	/* compatible is in per SoC .dtsi file */
	reg = <0x01c20000 0x400>;
	clocks = <&osc24M>, <&rtc 0>;
	clock-names = "hosc", "losc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pio: pinctrl@1c20800 {
	/* compatible is in per SoC .dtsi file */
	reg = <0x01c20800 0x400>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
	clock-names = "apb", "hosc", "losc";
	gpio-controller;
	#gpio-cells = <3>;
	interrupt-controller;
	#interrupt-cells = <3>;

	csi_pins: csi-pins {
	pins = "PE0", "PE2", "PE3", "PE4", "PE5",
	"PE6", "PE7", "PE8", "PE9", "PE10",
	"PE11";
	function = "csi";
	};

	emac_rgmii_pins: emac-rgmii-pins {
	pins = "PD0", "PD1", "PD2", "PD3", "PD4",
	"PD5", "PD7", "PD8", "PD9", "PD10",
	"PD12", "PD13", "PD15", "PD16", "PD17";
	function = "emac";
	drive-strength = <40>;
	};

	i2c0_pins: i2c0-pins {
	pins = "PA11", "PA12";
	function = "i2c0";
	};

	i2c1_pins: i2c1-pins {
	pins = "PA18", "PA19";
	function = "i2c1";
	};

	i2c2_pins: i2c2-pins {
	pins = "PE12", "PE13";
	function = "i2c2";
	};

	mmc0_pins: mmc0-pins {
	pins = "PF0", "PF1", "PF2", "PF3",
	"PF4", "PF5";
	function = "mmc0";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc1_pins: mmc1-pins {
	pins = "PG0", "PG1", "PG2", "PG3",
	"PG4", "PG5";
	function = "mmc1";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc2_8bit_pins: mmc2-8bit-pins {
	pins = "PC5", "PC6", "PC8",
	"PC9", "PC10", "PC11",
	"PC12", "PC13", "PC14",
	"PC15", "PC16";
	function = "mmc2";
	drive-strength = <30>;
	bias-pull-up;
	};

	spdif_tx_pin: spdif-tx-pin {
	pins = "PA17";
	function = "spdif";
	};

	spi0_pins: spi0-pins {
	pins = "PC0", "PC1", "PC2", "PC3";
	function = "spi0";
	};

	spi1_pins: spi1-pins {
	pins = "PA15", "PA16", "PA14", "PA13";
	function = "spi1";
	};

	uart0_pa_pins: uart0-pa-pins {
	pins = "PA4", "PA5";
	function = "uart0";
	};

	uart1_pins: uart1-pins {
	pins = "PG6", "PG7";
	function = "uart1";
	};

	uart1_rts_cts_pins: uart1-rts-cts-pins {
	pins = "PG8", "PG9";
	function = "uart1";
	};

	uart2_pins: uart2-pins {
	pins = "PA0", "PA1";
	function = "uart2";
	};

	uart2_rts_cts_pins: uart2-rts-cts-pins {
	pins = "PA2", "PA3";
	function = "uart2";
	};

	uart3_pins: uart3-pins {
	pins = "PA13", "PA14";
	function = "uart3";
	};

	uart3_rts_cts_pins: uart3-rts-cts-pins {
	pins = "PA15", "PA16";
	function = "uart3";
	};
	};

	timer@1c20c00 {
	compatible = "allwinner,sun8i-a23-timer";
	reg = <0x01c20c00 0xa0>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc24M>;
	};

	emac: ethernet@1c30000 {
	compatible = "allwinner,sun8i-h3-emac";
	syscon = <&syscon>;
	reg = <0x01c30000 0x10000>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	resets = <&ccu RST_BUS_EMAC>;
	reset-names = "stmmaceth";
	clocks = <&ccu CLK_BUS_EMAC>;
	clock-names = "stmmaceth";
	status = "disabled";

	mdio: mdio {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,dwmac-mdio";
	};

	mdio-mux {
	compatible = "allwinner,sun8i-h3-mdio-mux";
	#address-cells = <1>;
	#size-cells = <0>;

	mdio-parent-bus = <&mdio>;
	/* Only one MDIO is usable at the time */
	internal_mdio: mdio@1 {
	compatible = "allwinner,sun8i-h3-mdio-internal";
	reg = <1>;
	#address-cells = <1>;
	#size-cells = <0>;

	int_mii_phy: ethernet-phy@1 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <1>;
	clocks = <&ccu CLK_BUS_EPHY>;
	resets = <&ccu RST_BUS_EPHY>;
	};
	};

	external_mdio: mdio@2 {
	reg = <2>;
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};
	};

	mbus: dram-controller@1c62000 {
	compatible = "allwinner,sun8i-h3-mbus";
	reg = <0x01c62000 0x1000>;
	clocks = <&ccu CLK_MBUS>;
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	dma-ranges = <0x00000000 0x40000000 0xc0000000>;
	#interconnect-cells = <1>;
	};

	spi0: spi@1c68000 {
	compatible = "allwinner,sun8i-h3-spi";
	reg = <0x01c68000 0x1000>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
	clock-names = "ahb", "mod";
	dmas = <&dma 23>, <&dma 23>;
	dma-names = "rx", "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pins>;
	resets = <&ccu RST_BUS_SPI0>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	spi1: spi@1c69000 {
	compatible = "allwinner,sun8i-h3-spi";
	reg = <0x01c69000 0x1000>;
	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
	clock-names = "ahb", "mod";
	dmas = <&dma 24>, <&dma 24>;
	dma-names = "rx", "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_pins>;
	resets = <&ccu RST_BUS_SPI1>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	wdt0: watchdog@1c20ca0 {
	compatible = "allwinner,sun6i-a31-wdt";
	reg = <0x01c20ca0 0x20>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc24M>;
	};

	spdif: spdif@1c21000 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun8i-h3-spdif";
	reg = <0x01c21000 0x400>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
	resets = <&ccu RST_BUS_SPDIF>;
	clock-names = "apb", "spdif";
	dmas = <&dma 2>;
	dma-names = "tx";
	status = "disabled";
	};

	pwm: pwm@1c21400 {
	compatible = "allwinner,sun8i-h3-pwm";
	reg = <0x01c21400 0x8>;
	clocks = <&osc24M>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	i2s0: i2s@1c22000 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun8i-h3-i2s";
	reg = <0x01c22000 0x400>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
	clock-names = "apb", "mod";
	dmas = <&dma 3>, <&dma 3>;
	resets = <&ccu RST_BUS_I2S0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2s1: i2s@1c22400 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun8i-h3-i2s";
	reg = <0x01c22400 0x400>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
	clock-names = "apb", "mod";
	dmas = <&dma 4>, <&dma 4>;
	resets = <&ccu RST_BUS_I2S1>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	codec: codec@1c22c00 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun8i-h3-codec";
	reg = <0x01c22c00 0x400>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
	clock-names = "apb", "codec";
	resets = <&ccu RST_BUS_CODEC>;
	dmas = <&dma 15>, <&dma 15>;
	dma-names = "rx", "tx";
	allwinner,codec-analog-controls = <&codec_analog>;
	status = "disabled";
	};

	uart0: serial@1c28000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28000 0x400>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART0>;
	resets = <&ccu RST_BUS_UART0>;
	dmas = <&dma 6>, <&dma 6>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart1: serial@1c28400 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28400 0x400>;
	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART1>;
	resets = <&ccu RST_BUS_UART1>;
	dmas = <&dma 7>, <&dma 7>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart2: serial@1c28800 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28800 0x400>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART2>;
	resets = <&ccu RST_BUS_UART2>;
	dmas = <&dma 8>, <&dma 8>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart3: serial@1c28c00 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28c00 0x400>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART3>;
	resets = <&ccu RST_BUS_UART3>;
	dmas = <&dma 9>, <&dma 9>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c0: i2c@1c2ac00 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2ac00 0x400>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C0>;
	resets = <&ccu RST_BUS_I2C0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c1: i2c@1c2b000 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2b000 0x400>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C1>;
	resets = <&ccu RST_BUS_I2C1>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c2: i2c@1c2b400 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2b400 0x400>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C2>;
	resets = <&ccu RST_BUS_I2C2>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	gic: interrupt-controller@1c81000 {
	compatible = "arm,gic-400";
	reg = <0x01c81000 0x1000>,
	<0x01c82000 0x2000>,
	<0x01c84000 0x2000>,
	<0x01c86000 0x2000>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	csi: camera@1cb0000 {
	compatible = "allwinner,sun8i-h3-csi";
	reg = <0x01cb0000 0x1000>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_CSI>,
	<&ccu CLK_CSI_SCLK>,
	<&ccu CLK_DRAM_CSI>;
	clock-names = "bus", "mod", "ram";
	resets = <&ccu RST_BUS_CSI>;
	pinctrl-names = "default";
	pinctrl-0 = <&csi_pins>;
	status = "disabled";
	};

	hdmi: hdmi@1ee0000 {
	compatible = "allwinner,sun8i-h3-dw-hdmi",
	"allwinner,sun8i-a83t-dw-hdmi";
	reg = <0x01ee0000 0x10000>;
	reg-io-width = <1>;
	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
	<&ccu CLK_HDMI>;
	clock-names = "iahb", "isfr", "tmds";
	resets = <&ccu RST_BUS_HDMI1>;
	reset-names = "ctrl";
	phys = <&hdmi_phy>;
	phy-names = "phy";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	hdmi_in: port@0 {
	reg = <0>;

	hdmi_in_tcon0: endpoint {
	remote-endpoint = <&tcon0_out_hdmi>;
	};
	};

	hdmi_out: port@1 {
	reg = <1>;
	};
	};
	};

	hdmi_phy: hdmi-phy@1ef0000 {
	compatible = "allwinner,sun8i-h3-hdmi-phy";
	reg = <0x01ef0000 0x10000>;
	clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
	<&ccu CLK_PLL_VIDEO>;
	clock-names = "bus", "mod", "pll-0";
	resets = <&ccu RST_BUS_HDMI0>;
	reset-names = "phy";
	#phy-cells = <0>;
	};

	rtc: rtc@1f00000 {
	/* compatible is in per SoC .dtsi file */
	reg = <0x01f00000 0x400>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	clock-output-names = "osc32k", "osc32k-out", "iosc";
	clocks = <&osc32k>;
	#clock-cells = <1>;
	};

	r_ccu: clock@1f01400 {
	compatible = "allwinner,sun8i-h3-r-ccu";
	reg = <0x01f01400 0x100>;
	clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
	<&ccu CLK_PLL_PERIPH0>;
	clock-names = "hosc", "losc", "iosc", "pll-periph";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	codec_analog: codec-analog@1f015c0 {
	compatible = "allwinner,sun8i-h3-codec-analog";
	reg = <0x01f015c0 0x4>;
	};

	ir: ir@1f02000 {
	compatible = "allwinner,sun6i-a31-ir";
	clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
	clock-names = "apb", "ir";
	resets = <&r_ccu RST_APB0_IR>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x01f02000 0x400>;
	status = "disabled";
	};

	r_i2c: i2c@1f02400 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01f02400 0x400>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&r_i2c_pins>;
	clocks = <&r_ccu CLK_APB0_I2C>;
	resets = <&r_ccu RST_APB0_I2C>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	r_pio: pinctrl@1f02c00 {
	compatible = "allwinner,sun8i-h3-r-pinctrl";
	reg = <0x01f02c00 0x400>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>;
	clock-names = "apb", "hosc", "losc";
	gpio-controller;
	#gpio-cells = <3>;
	interrupt-controller;
	#interrupt-cells = <3>;

	r_ir_rx_pin: r-ir-rx-pin {
	pins = "PL11";
	function = "s_cir_rx";
	};

	r_i2c_pins: r-i2c-pins {
	pins = "PL0", "PL1";
	function = "s_i2c";
	};
	+
	+ r_pwm_pin: r-pwm-pin {
	+ pins = "PL10";
	+ function = "s_pwm";
	+ };
	+ };
	+
	+ r_pwm: pwm@1f03800 {
	+ compatible = "allwinner,sun8i-h3-pwm";
	+ reg = <0x01f03800 0x8>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&r_pwm_pin>;
	+ clocks = <&osc24M>;
	+ #pwm-cells = <3>;
	+ status = "disabled";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/tango4-common.dtsi b/sys/gnu/dts/arm/tango4-common.dtsi
	index ff72a8efb73d..54fd522badfc 100644
	--- a/sys/gnu/dts/arm/tango4-common.dtsi
	+++ b/sys/gnu/dts/arm/tango4-common.dtsi
	@@ -1,184 +1,184 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Based on Mans Rullgard's Tango3 DT
	* https://github.com/mansr/linux-tangox
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>

	#define CPU_CLK 0
	#define SYS_CLK 1
	#define USB_CLK 2
	#define SDIO_CLK 3

	/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	periph_clk: periph_clk {
	compatible = "fixed-factor-clock";
	clocks = <&clkgen CPU_CLK>;
	clock-mult = <1>;
	clock-div = <2>;
	#clock-cells = <0>;
	};

	mpcore {
	compatible = "simple-bus";
	ranges = <0x00000000 0x20000000 0x2000>;
	#address-cells = <1>;
	#size-cells = <1>;

	scu@0 {
	compatible = "arm,cortex-a9-scu";
	reg = <0x0 0x100>;
	};

	twd@600 {
	compatible = "arm,cortex-a9-twd-timer";
	reg = <0x600 0x10>;
	interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
	clocks = <&periph_clk>;
	always-on;
	};

	gic: interrupt-controller@1000 {
	compatible = "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x1000 0x1000>, <0x100 0x100>;
	};
	};

	l2cc: l2-cache-controller@20100000 {
	compatible = "arm,pl310-cache";
	reg = <0x20100000 0x1000>;
	cache-level = <2>;
	cache-unified;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&irq0>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	xtal: xtal {
	compatible = "fixed-clock";
	clock-frequency = <27000000>;
	#clock-cells = <0>;
	};

	clkgen: clkgen@10000 {
	compatible = "sigma,tango4-clkgen";
	reg = <0x10000 0x100>;
	clocks = <&xtal>;
	#clock-cells = <1>;
	};

	tick-counter@10048 {
	compatible = "sigma,tick-counter";
	reg = <0x10048 0x4>;
	clocks = <&xtal>;
	};

	uart: serial@10700 {
	- compatible = "ralink,rt2880-uart";
	+ compatible = "ralink,rt2880-uart", "ns16550a";
	reg = <0x10700 0x30>;
	interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <7372800>;
	reg-shift = <2>;
	};

	watchdog@1fd00 {
	compatible = "sigma,smp8759-wdt";
	reg = <0x1fd00 8>;
	clocks = <&xtal>;
	};

	mmc0: mmc@21000 {
	compatible = "arasan,sdhci-8.9a";
	reg = <0x21000 0x200>;
	clock-names = "clk_xin", "clk_ahb";
	clocks = <&clkgen SDIO_CLK>, <&clkgen SYS_CLK>;
	interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
	};

	mmc1: mmc@21200 {
	compatible = "arasan,sdhci-8.9a";
	reg = <0x21200 0x200>;
	clock-names = "clk_xin", "clk_ahb";
	clocks = <&clkgen SDIO_CLK>, <&clkgen SYS_CLK>;
	interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
	};

	usb0: usb@21400 {
	compatible = "chipidea,usb2";
	reg = <0x21400 0x200>;
	interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
	phys = <&usb0_phy>;
	phy-names = "usb-phy";
	};

	usb0_phy: phy@21700 {
	compatible = "sigma,smp8642-usb-phy";
	reg = <0x21700 0x100>;
	#phy-cells = <0>;
	clocks = <&clkgen USB_CLK>;
	};

	usb1: usb@25400 {
	compatible = "chipidea,usb2";
	reg = <0x25400 0x200>;
	interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
	phys = <&usb1_phy>;
	phy-names = "usb-phy";
	};

	usb1_phy: phy@25700 {
	compatible = "sigma,smp8642-usb-phy";
	reg = <0x25700 0x100>;
	#phy-cells = <0>;
	clocks = <&clkgen USB_CLK>;
	};

	eth0: ethernet@26000 {
	compatible = "sigma,smp8734-ethernet";
	reg = <0x26000 0x800>;
	interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clkgen SYS_CLK>;
	};

	intc: interrupt-controller@6e000 {
	compatible = "sigma,smp8642-intc";
	reg = <0x6e000 0x400>;
	ranges = <0 0x6e000 0x400>;
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	irq0: irq0@0 {
	reg = <0x000 0x100>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	};

	irq1: irq1@100 {
	reg = <0x100 0x100>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	};

	irq2: irq2@300 {
	reg = <0x300 0x100>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/tegra114-dalmore.dts b/sys/gnu/dts/arm/tegra114-dalmore.dts
	index 97a5c3504bbe..d3e032e7d21a 100644
	--- a/sys/gnu/dts/arm/tegra114-dalmore.dts
	+++ b/sys/gnu/dts/arm/tegra114-dalmore.dts
	@@ -1,1302 +1,1308 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* This dts file supports Dalmore A04.
	* Other board revisions are not supported
	*/

	/dts-v1/;

	#include <dt-bindings/input/input.h>
	#include "tegra114.dtsi"

	/ {
	model = "NVIDIA Tegra114 Dalmore evaluation board";
	compatible = "nvidia,dalmore", "nvidia,tegra114";

	aliases {
	rtc0 = "/i2c@7000d000/tps65913@58";
	rtc1 = "/rtc@7000e000";
	serial0 = &uartd;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@80000000 {
	reg = <0x80000000 0x40000000>;
	};

	host1x@50000000 {
	hdmi@54280000 {
	status = "okay";

	hdmi-supply = <&vdd_5v0_hdmi>;
	vdd-supply = <&vdd_hdmi_reg>;
	pll-supply = <&palmas_smps3_reg>;

	nvidia,ddc-i2c-bus = <&hdmi_ddc>;
	nvidia,hpd-gpio =
	<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
	};

	dsi@54300000 {
	status = "okay";

	avdd-dsi-csi-supply = <&avdd_1v2_reg>;

	panel@0 {
	compatible = "panasonic,vvx10f004b00",
	"simple-panel";
	reg = <0>;

	power-supply = <&avdd_lcd_reg>;
	backlight = <&backlight>;
	};
	};
	};

	pinmux@70000868 {
	pinctrl-names = "default";
	pinctrl-0 = <&state_default>;

	state_default: pinmux {
	clk1_out_pw4 {
	nvidia,pins = "clk1_out_pw4";
	nvidia,function = "extperiph1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap1_din_pn1 {
	nvidia,pins = "dap1_din_pn1";
	nvidia,function = "i2s0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap1_dout_pn2 {
	nvidia,pins = "dap1_dout_pn2",
	"dap1_fs_pn0",
	"dap1_sclk_pn3";
	nvidia,function = "i2s0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap2_din_pa4 {
	nvidia,pins = "dap2_din_pa4";
	nvidia,function = "i2s1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap2_dout_pa5 {
	nvidia,pins = "dap2_dout_pa5",
	"dap2_fs_pa2",
	"dap2_sclk_pa3";
	nvidia,function = "i2s1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap4_din_pp5 {
	nvidia,pins = "dap4_din_pp5",
	"dap4_dout_pp6",
	"dap4_fs_pp4",
	"dap4_sclk_pp7";
	nvidia,function = "i2s3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dvfs_pwm_px0 {
	nvidia,pins = "dvfs_pwm_px0",
	"dvfs_clk_px2";
	nvidia,function = "cldvfs";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi_clk_py0 {
	nvidia,pins = "ulpi_clk_py0",
	"ulpi_data0_po1",
	"ulpi_data1_po2",
	"ulpi_data2_po3",
	"ulpi_data3_po4",
	"ulpi_data4_po5",
	"ulpi_data5_po6",
	"ulpi_data6_po7",
	"ulpi_data7_po0";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ulpi_dir_py1 {
	nvidia,pins = "ulpi_dir_py1",
	"ulpi_nxt_py2";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ulpi_stp_py3 {
	nvidia,pins = "ulpi_stp_py3";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	cam_i2c_scl_pbb1 {
	nvidia,pins = "cam_i2c_scl_pbb1",
	"cam_i2c_sda_pbb2";
	nvidia,function = "i2c3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,lock = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cam_mclk_pcc0 {
	nvidia,pins = "cam_mclk_pcc0",
	"pbb0";
	nvidia,function = "vi_alt3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,lock = <TEGRA_PIN_DISABLE>;
	};
	gen2_i2c_scl_pt5 {
	nvidia,pins = "gen2_i2c_scl_pt5",
	"gen2_i2c_sda_pt6";
	nvidia,function = "i2c2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,lock = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	gmi_a16_pj7 {
	nvidia,pins = "gmi_a16_pj7";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_a17_pb0 {
	nvidia,pins = "gmi_a17_pb0",
	"gmi_a18_pb1";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gmi_a19_pk7 {
	nvidia,pins = "gmi_a19_pk7";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_ad5_pg5 {
	nvidia,pins = "gmi_ad5_pg5",
	"gmi_cs6_n_pi3",
	"gmi_wr_n_pi0";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gmi_ad6_pg6 {
	nvidia,pins = "gmi_ad6_pg6",
	"gmi_ad7_pg7";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gmi_ad12_ph4 {
	nvidia,pins = "gmi_ad12_ph4";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_ad9_ph1 {
	nvidia,pins = "gmi_ad9_ph1";
	nvidia,function = "pwm1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_cs1_n_pj2 {
	nvidia,pins = "gmi_cs1_n_pj2",
	"gmi_oe_n_pi1";
	nvidia,function = "soc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	clk2_out_pw5 {
	nvidia,pins = "clk2_out_pw5";
	nvidia,function = "extperiph2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_clk_pz0 {
	nvidia,pins = "sdmmc1_clk_pz0";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1_cmd_pz1 {
	nvidia,pins = "sdmmc1_cmd_pz1",
	"sdmmc1_dat0_py7",
	"sdmmc1_dat1_py6",
	"sdmmc1_dat2_py5",
	"sdmmc1_dat3_py4";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1_wp_n_pv3 {
	nvidia,pins = "sdmmc1_wp_n_pv3";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_clk_pa6 {
	nvidia,pins = "sdmmc3_clk_pa6";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_cmd_pa7 {
	nvidia,pins = "sdmmc3_cmd_pa7",
	"sdmmc3_dat0_pb7",
	"sdmmc3_dat1_pb6",
	"sdmmc3_dat2_pb5",
	"sdmmc3_dat3_pb4",
	"kb_col4_pq4",
	"sdmmc3_clk_lb_out_pee4",
	"sdmmc3_clk_lb_in_pee5";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_clk_pcc4 {
	nvidia,pins = "sdmmc4_clk_pcc4";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_cmd_pt7 {
	nvidia,pins = "sdmmc4_cmd_pt7",
	"sdmmc4_dat0_paa0",
	"sdmmc4_dat1_paa1",
	"sdmmc4_dat2_paa2",
	"sdmmc4_dat3_paa3",
	"sdmmc4_dat4_paa4",
	"sdmmc4_dat5_paa5",
	"sdmmc4_dat6_paa6",
	"sdmmc4_dat7_paa7";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	clk_32k_out_pa0 {
	nvidia,pins = "clk_32k_out_pa0";
	nvidia,function = "blink";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_col0_pq0 {
	nvidia,pins = "kb_col0_pq0",
	"kb_col1_pq1",
	"kb_col2_pq2",
	"kb_row0_pr0",
	"kb_row1_pr1",
	"kb_row2_pr2";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap3_din_pp1 {
	nvidia,pins = "dap3_din_pp1",
	"dap3_sclk_pp3";
	nvidia,function = "displayb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pv0 {
	nvidia,pins = "pv0";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_row7_pr7 {
	nvidia,pins = "kb_row7_pr7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row10_ps2 {
	nvidia,pins = "kb_row10_ps2";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row9_ps1 {
	nvidia,pins = "kb_row9_ps1";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pwr_i2c_scl_pz6 {
	nvidia,pins = "pwr_i2c_scl_pz6",
	"pwr_i2c_sda_pz7";
	nvidia,function = "i2cpwr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,lock = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sys_clk_req_pz5 {
	nvidia,pins = "sys_clk_req_pz5";
	nvidia,function = "sysclk";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	core_pwr_req {
	nvidia,pins = "core_pwr_req";
	nvidia,function = "pwron";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	cpu_pwr_req {
	nvidia,pins = "cpu_pwr_req";
	nvidia,function = "cpu";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pwr_int_n {
	nvidia,pins = "pwr_int_n";
	nvidia,function = "pmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	reset_out_n {
	nvidia,pins = "reset_out_n";
	nvidia,function = "reset_out_n";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	clk3_out_pee0 {
	nvidia,pins = "clk3_out_pee0";
	nvidia,function = "extperiph3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gen1_i2c_scl_pc4 {
	nvidia,pins = "gen1_i2c_scl_pc4",
	"gen1_i2c_sda_pc5";
	nvidia,function = "i2c1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,lock = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart2_cts_n_pj5 {
	nvidia,pins = "uart2_cts_n_pj5";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart2_rts_n_pj6 {
	nvidia,pins = "uart2_rts_n_pj6";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart2_rxd_pc3 {
	nvidia,pins = "uart2_rxd_pc3";
	nvidia,function = "irda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart2_txd_pc2 {
	nvidia,pins = "uart2_txd_pc2";
	nvidia,function = "irda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart3_cts_n_pa1 {
	nvidia,pins = "uart3_cts_n_pa1",
	"uart3_rxd_pw7";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart3_rts_n_pc0 {
	nvidia,pins = "uart3_rts_n_pc0",
	"uart3_txd_pw6";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	owr {
	nvidia,pins = "owr";
	nvidia,function = "owr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	hdmi_cec_pee3 {
	nvidia,pins = "hdmi_cec_pee3";
	nvidia,function = "cec";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,lock = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	ddc_scl_pv4 {
	nvidia,pins = "ddc_scl_pv4",
	"ddc_sda_pv5";
	nvidia,function = "i2c4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,lock = <TEGRA_PIN_DISABLE>;
	nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
	};
	spdif_in_pk6 {
	nvidia,pins = "spdif_in_pk6";
	nvidia,function = "usb";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,lock = <TEGRA_PIN_DISABLE>;
	};
	usb_vbus_en0_pn4 {
	nvidia,pins = "usb_vbus_en0_pn4";
	nvidia,function = "usb";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,lock = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	gpio_x6_aud_px6 {
	nvidia,pins = "gpio_x6_aud_px6";
	nvidia,function = "spi6";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gpio_x4_aud_px4 {
	nvidia,pins = "gpio_x4_aud_px4",
	"gpio_x7_aud_px7";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gpio_x5_aud_px5 {
	nvidia,pins = "gpio_x5_aud_px5";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gpio_w2_aud_pw2 {
	nvidia,pins = "gpio_w2_aud_pw2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gpio_w3_aud_pw3 {
	nvidia,pins = "gpio_w3_aud_pw3";
	nvidia,function = "spi6";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gpio_x1_aud_px1 {
	nvidia,pins = "gpio_x1_aud_px1";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gpio_x3_aud_px3 {
	nvidia,pins = "gpio_x3_aud_px3";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap3_fs_pp0 {
	nvidia,pins = "dap3_fs_pp0";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap3_dout_pp2 {
	nvidia,pins = "dap3_dout_pp2";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pv1 {
	nvidia,pins = "pv1";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pbb3 {
	nvidia,pins = "pbb3",
	"pbb5",
	"pbb6",
	"pbb7";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pcc1 {
	nvidia,pins = "pcc1",
	"pcc2";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gmi_ad0_pg0 {
	nvidia,pins = "gmi_ad0_pg0",
	"gmi_ad1_pg1";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_ad10_ph2 {
	nvidia,pins = "gmi_ad10_ph2",
	"gmi_ad11_ph3",
	"gmi_ad13_ph5",
	"gmi_ad8_ph0",
	"gmi_clk_pk1";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_ad2_pg2 {
	nvidia,pins = "gmi_ad2_pg2",
	"gmi_ad3_pg3";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gmi_adv_n_pk0 {
	nvidia,pins = "gmi_adv_n_pk0",
	"gmi_cs0_n_pj0",
	"gmi_cs2_n_pk3",
	"gmi_cs4_n_pk2",
	"gmi_cs7_n_pi6",
	"gmi_dqs_p_pj3",
	"gmi_iordy_pi5",
	"gmi_wp_n_pc7";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gmi_cs3_n_pk4 {
	nvidia,pins = "gmi_cs3_n_pk4";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	clk2_req_pcc5 {
	nvidia,pins = "clk2_req_pcc5";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_col3_pq3 {
	nvidia,pins = "kb_col3_pq3",
	"kb_col6_pq6",
	"kb_col7_pq7";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_col5_pq5 {
	nvidia,pins = "kb_col5_pq5";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row3_pr3 {
	nvidia,pins = "kb_row3_pr3",
	"kb_row4_pr4",
	"kb_row6_pr6",
	"kb_row8_ps0";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	clk3_req_pee1 {
	nvidia,pins = "clk3_req_pee1";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pu4 {
	nvidia,pins = "pu4";
	nvidia,function = "displayb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pu5 {
	nvidia,pins = "pu5",
	"pu6";
	nvidia,function = "displayb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	hdmi_int_pn7 {
	nvidia,pins = "hdmi_int_pn7";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	clk1_req_pee2 {
	nvidia,pins = "clk1_req_pee2",
	"usb_vbus_en1_pn5";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	drive_sdio1 {
	nvidia,pins = "drive_sdio1";
	nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
	nvidia,schmitt = <TEGRA_PIN_DISABLE>;
	nvidia,pull-down-strength = <36>;
	nvidia,pull-up-strength = <20>;
	nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
	nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
	};
	drive_sdio3 {
	nvidia,pins = "drive_sdio3";
	nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
	nvidia,schmitt = <TEGRA_PIN_DISABLE>;
	nvidia,pull-down-strength = <22>;
	nvidia,pull-up-strength = <36>;
	nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
	nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
	};
	drive_gma {
	nvidia,pins = "drive_gma";
	nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
	nvidia,schmitt = <TEGRA_PIN_DISABLE>;
	nvidia,pull-down-strength = <2>;
	nvidia,pull-up-strength = <1>;
	nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
	nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
	};
	};
	};

	serial@70006300 {
	status = "okay";
	};

	pwm@7000a000 {
	status = "okay";
	};

	i2c@7000c000 {
	status = "okay";
	clock-frequency = <100000>;

	battery: smart-battery@b {
	compatible = "ti,bq20z45", "sbs,sbs-battery";
	reg = <0xb>;
	battery-name = "battery";
	sbs,i2c-retry-count = <2>;
	sbs,poll-retry-count = <100>;
	power-supplies = <&charger>;
	};

	rt5640: rt5640@1c {
	compatible = "realtek,rt5640";
	reg = <0x1c>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
	realtek,ldo1-en-gpios =
	<&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
	};

	temperature-sensor@4c {
	compatible = "onnn,nct1008";
	reg = <0x4c>;
	vcc-supply = <&palmas_ldo6_reg>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_LOW>;
	};
	};

	hdmi_ddc: i2c@7000c700 {
	status = "okay";
	};

	i2c@7000d000 {
	status = "okay";
	clock-frequency = <400000>;

	tps51632@43 {
	compatible = "ti,tps51632";
	reg = <0x43>;
	regulator-name = "vdd-cpu";
	regulator-min-microvolt = <500000>;
	regulator-max-microvolt = <1520000>;
	regulator-boot-on;
	regulator-always-on;
	};

	tps65090@48 {
	compatible = "ti,tps65090";
	reg = <0x48>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;

	vsys1-supply = <&vdd_ac_bat_reg>;
	vsys2-supply = <&vdd_ac_bat_reg>;
	vsys3-supply = <&vdd_ac_bat_reg>;
	infet1-supply = <&vdd_ac_bat_reg>;
	infet2-supply = <&vdd_ac_bat_reg>;
	infet3-supply = <&tps65090_dcdc2_reg>;
	infet4-supply = <&tps65090_dcdc2_reg>;
	infet5-supply = <&tps65090_dcdc2_reg>;
	infet6-supply = <&tps65090_dcdc2_reg>;
	infet7-supply = <&tps65090_dcdc2_reg>;
	vsys-l1-supply = <&vdd_ac_bat_reg>;
	vsys-l2-supply = <&vdd_ac_bat_reg>;

	charger: charger {
	compatible = "ti,tps65090-charger";
	ti,enable-low-current-chrg;
	};

	regulators {
	tps65090_dcdc1_reg: dcdc1 {
	regulator-name = "vdd-sys-5v0";
	regulator-always-on;
	regulator-boot-on;
	};

	tps65090_dcdc2_reg: dcdc2 {
	regulator-name = "vdd-sys-3v3";
	regulator-always-on;
	regulator-boot-on;
	};

	tps65090_dcdc3_reg: dcdc3 {
	regulator-name = "vdd-ao";
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_bl_reg: fet1 {
	regulator-name = "vdd-lcd-bl";
	};

	fet3 {
	regulator-name = "vdd-modem-3v3";
	};

	avdd_lcd_reg: fet4 {
	regulator-name = "avdd-lcd";
	};

	fet5 {
	regulator-name = "vdd-lvds";
	};

	fet6 {
	regulator-name = "vdd-sd-slot";
	regulator-always-on;
	regulator-boot-on;
	};

	fet7 {
	regulator-name = "vdd-com-3v3";
	};

	ldo1 {
	regulator-name = "vdd-sby-5v0";
	regulator-always-on;
	regulator-boot-on;
	};

	ldo2 {
	regulator-name = "vdd-sby-3v3";
	regulator-always-on;
	regulator-boot-on;
	};
	};
	};

	palmas: tps65913@58 {
	compatible = "ti,palmas";
	reg = <0x58>;
	interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;

	#interrupt-cells = <2>;
	interrupt-controller;

	ti,system-power-controller;

	palmas_gpio: gpio {
	compatible = "ti,palmas-gpio";
	gpio-controller;
	#gpio-cells = <2>;
	};

	pmic {
	compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
	smps1-in-supply = <&tps65090_dcdc3_reg>;
	smps3-in-supply = <&tps65090_dcdc3_reg>;
	smps4-in-supply = <&tps65090_dcdc2_reg>;
	smps7-in-supply = <&tps65090_dcdc2_reg>;
	smps8-in-supply = <&tps65090_dcdc2_reg>;
	smps9-in-supply = <&tps65090_dcdc2_reg>;
	ldo1-in-supply = <&tps65090_dcdc2_reg>;
	ldo2-in-supply = <&tps65090_dcdc2_reg>;
	ldo3-in-supply = <&palmas_smps3_reg>;
	ldo4-in-supply = <&tps65090_dcdc2_reg>;
	ldo5-in-supply = <&vdd_ac_bat_reg>;
	ldo6-in-supply = <&tps65090_dcdc2_reg>;
	ldo7-in-supply = <&tps65090_dcdc2_reg>;
	ldo8-in-supply = <&tps65090_dcdc3_reg>;
	ldo9-in-supply = <&palmas_smps9_reg>;
	ldoln-in-supply = <&tps65090_dcdc1_reg>;
	ldousb-in-supply = <&tps65090_dcdc1_reg>;

	regulators {
	smps12 {
	regulator-name = "vddio-ddr";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	};

	palmas_smps3_reg: smps3 {
	regulator-name = "vddio-1v8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	smps45 {
	regulator-name = "vdd-core";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1400000>;
	regulator-always-on;
	regulator-boot-on;
	};

	smps457 {
	regulator-name = "vdd-core";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1400000>;
	regulator-always-on;
	regulator-boot-on;
	};

	smps8 {
	regulator-name = "avdd-pll";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	regulator-always-on;
	regulator-boot-on;
	};

	palmas_smps9_reg: smps9 {
	regulator-name = "sdhci-vdd-sd-slot";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-always-on;
	};

	ldo1 {
	regulator-name = "avdd-cam1";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	ldo2 {
	regulator-name = "avdd-cam2";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	avdd_1v2_reg: ldo3 {
	regulator-name = "avdd-dsi-csi";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	ldo4 {
	regulator-name = "vpp-fuse";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	palmas_ldo6_reg: ldo6 {
	regulator-name = "vdd-sensor-2v85";
	regulator-min-microvolt = <2850000>;
	regulator-max-microvolt = <2850000>;
	};

	ldo7 {
	regulator-name = "vdd-af-cam1";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	ldo8 {
	regulator-name = "vdd-rtc";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <900000>;
	regulator-always-on;
	regulator-boot-on;
	ti,enable-ldo8-tracking;
	};

	ldo9 {
	regulator-name = "vddio-sdmmc-2";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldoln {
	regulator-name = "hvdd-usb";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	ldousb {
	regulator-name = "avdd-usb";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	};

	regen1 {
	regulator-name = "rail-3v3";
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	};

	regen2 {
	regulator-name = "rail-5v0";
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	};
	};
	};

	rtc {
	compatible = "ti,palmas-rtc";
	interrupt-parent = <&palmas>;
	interrupts = <8 0>;
	};

	pinmux {
	compatible = "ti,tps65913-pinctrl";
	pinctrl-names = "default";
	pinctrl-0 = <&palmas_default>;

	palmas_default: pinmux {
	pin_gpio6 {
	pins = "gpio6";
	function = "gpio";
	};
	};
	};
	};
	};

	spi@7000da00 {
	status = "okay";
	spi-max-frequency = <25000000>;
	spi-flash@0 {
	compatible = "winbond,w25q32dw", "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <20000000>;
	};
	};

	pmc@7000e400 {
	nvidia,invert-interrupt;
	nvidia,suspend-mode = <1>;
	nvidia,cpu-pwr-good-time = <500>;
	nvidia,cpu-pwr-off-time = <300>;
	nvidia,core-pwr-good-time = <641 3845>;
	nvidia,core-pwr-off-time = <61036>;
	nvidia,core-power-req-active-high;
	nvidia,sys-clock-req-active-high;
	};

	ahub@70080000 {
	i2s@70080400 {
	status = "okay";
	};
	};

	sdhci@78000400 {
	cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
	bus-width = <4>;
	status = "okay";
	};

	sdhci@78000600 {
	bus-width = <8>;
	status = "okay";
	non-removable;
	};

	usb@7d000000 {
	compatible = "nvidia,tegra114-udc";
	status = "okay";
	dr_mode = "peripheral";
	};

	usb-phy@7d000000 {
	status = "okay";
	};

	usb@7d008000 {
	status = "okay";
	};

	usb-phy@7d008000 {
	status = "okay";
	vbus-supply = <&usb3_vbus_reg>;
	};

	backlight: backlight {
	compatible = "pwm-backlight";

	enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
	power-supply = <&vdd_bl_reg>;
	pwms = <&pwm 1 1000000>;

	brightness-levels = <0 4 8 16 32 64 128 255>;
	default-brightness-level = <6>;
	};

	clocks {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	clk32k_in: clock@0 {
	compatible = "fixed-clock";
	reg = <0>;
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	};

	gpio-keys {
	compatible = "gpio-keys";

	home {
	label = "Home";
	gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
	linux,code = <KEY_HOME>;
	};

	power {
	label = "Power";
	gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
	linux,code = <KEY_POWER>;
	wakeup-source;
	};

	volume_down {
	label = "Volume Down";
	gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
	linux,code = <KEY_VOLUMEDOWN>;
	};

	volume_up {
	label = "Volume Up";
	gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
	linux,code = <KEY_VOLUMEUP>;
	};
	};

	regulators {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	vdd_ac_bat_reg: regulator@0 {
	compatible = "regulator-fixed";
	reg = <0>;
	regulator-name = "vdd_ac_bat";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	dvdd_ts_reg: regulator@1 {
	compatible = "regulator-fixed";
	reg = <1>;
	regulator-name = "dvdd_ts";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
	};

	usb1_vbus_reg: regulator@3 {
	compatible = "regulator-fixed";
	reg = <3>;
	regulator-name = "usb1_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
	gpio-open-drain;
	vin-supply = <&tps65090_dcdc1_reg>;
	};

	usb3_vbus_reg: regulator@4 {
	compatible = "regulator-fixed";
	reg = <4>;
	regulator-name = "usb2_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
	gpio-open-drain;
	vin-supply = <&tps65090_dcdc1_reg>;
	};

	vdd_hdmi_reg: regulator@5 {
	compatible = "regulator-fixed";
	reg = <5>;
	regulator-name = "vdd_hdmi_5v0";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&tps65090_dcdc1_reg>;
	};

	vdd_cam_1v8_reg: regulator@6 {
	compatible = "regulator-fixed";
	reg = <6>;
	regulator-name = "vdd_cam_1v8_reg";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	enable-active-high;
	gpio = <&palmas_gpio 6 0>;
	};

	vdd_5v0_hdmi: regulator@7 {
	compatible = "regulator-fixed";
	reg = <7>;
	regulator-name = "VDD_5V0_HDMI_CON";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&tps65090_dcdc1_reg>;
	};
	};

	sound {
	compatible = "nvidia,tegra-audio-rt5640-dalmore",
	"nvidia,tegra-audio-rt5640";
	nvidia,model = "NVIDIA Tegra Dalmore";

	nvidia,audio-routing =
	"Headphones", "HPOR",
	"Headphones", "HPOL",
	"Speakers", "SPORP",
	"Speakers", "SPORN",
	"Speakers", "SPOLP",
	"Speakers", "SPOLN",
	"Mic Jack", "MICBIAS1",
	"IN2P", "Mic Jack";

	nvidia,i2s-controller = <&tegra_i2s1>;
	nvidia,audio-codec = <&rt5640>;

	nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;

	clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
	<&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
	- <&tegra_car TEGRA114_CLK_EXTERN1>;
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	clock-names = "pll_a", "pll_a_out0", "mclk";
	+
	+ assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>,
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	+
	+ assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
	+ <&tegra_car TEGRA114_CLK_EXTERN1>;
	};
	};
	diff --git a/sys/gnu/dts/arm/tegra114.dtsi b/sys/gnu/dts/arm/tegra114.dtsi
	index 0d7a6327e404..450a1f1b12a0 100644
	--- a/sys/gnu/dts/arm/tegra114.dtsi
	+++ b/sys/gnu/dts/arm/tegra114.dtsi
	@@ -1,798 +1,800 @@
	// SPDX-License-Identifier: GPL-2.0
	#include <dt-bindings/clock/tegra114-car.h>
	#include <dt-bindings/gpio/tegra-gpio.h>
	#include <dt-bindings/memory/tegra114-mc.h>
	#include <dt-bindings/pinctrl/pinctrl-tegra.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	+#include <dt-bindings/soc/tegra-pmc.h>

	/ {
	compatible = "nvidia,tegra114";
	interrupt-parent = <&lic>;
	#address-cells = <1>;
	#size-cells = <1>;

	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x0>;
	};

	host1x@50000000 {
	compatible = "nvidia,tegra114-host1x", "simple-bus";
	reg = <0x50000000 0x00028000>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
	clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
	resets = <&tegra_car 28>;
	reset-names = "host1x";
	iommus = <&mc TEGRA_SWGROUP_HC>;

	#address-cells = <1>;
	#size-cells = <1>;

	ranges = <0x54000000 0x54000000 0x01000000>;

	gr2d@54140000 {
	compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
	reg = <0x54140000 0x00040000>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA114_CLK_GR2D>;
	resets = <&tegra_car 21>;
	reset-names = "2d";

	iommus = <&mc TEGRA_SWGROUP_G2>;
	};

	gr3d@54180000 {
	compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
	reg = <0x54180000 0x00040000>;
	clocks = <&tegra_car TEGRA114_CLK_GR3D>;
	resets = <&tegra_car 24>;
	reset-names = "3d";

	iommus = <&mc TEGRA_SWGROUP_NV>;
	};

	dc@54200000 {
	compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
	reg = <0x54200000 0x00040000>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA114_CLK_DISP1>,
	<&tegra_car TEGRA114_CLK_PLL_P>;
	clock-names = "dc", "parent";
	resets = <&tegra_car 27>;
	reset-names = "dc";

	iommus = <&mc TEGRA_SWGROUP_DC>;

	nvidia,head = <0>;

	rgb {
	status = "disabled";
	};
	};

	dc@54240000 {
	compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
	reg = <0x54240000 0x00040000>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA114_CLK_DISP2>,
	<&tegra_car TEGRA114_CLK_PLL_P>;
	clock-names = "dc", "parent";
	resets = <&tegra_car 26>;
	reset-names = "dc";

	iommus = <&mc TEGRA_SWGROUP_DCB>;

	nvidia,head = <1>;

	rgb {
	status = "disabled";
	};
	};

	hdmi@54280000 {
	compatible = "nvidia,tegra114-hdmi";
	reg = <0x54280000 0x00040000>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA114_CLK_HDMI>,
	<&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
	clock-names = "hdmi", "parent";
	resets = <&tegra_car 51>;
	reset-names = "hdmi";
	status = "disabled";
	};

	dsi@54300000 {
	compatible = "nvidia,tegra114-dsi";
	reg = <0x54300000 0x00040000>;
	clocks = <&tegra_car TEGRA114_CLK_DSIA>,
	<&tegra_car TEGRA114_CLK_DSIALP>,
	<&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
	clock-names = "dsi", "lp", "parent";
	resets = <&tegra_car 48>;
	reset-names = "dsi";
	nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
	status = "disabled";

	#address-cells = <1>;
	#size-cells = <0>;
	};

	dsi@54400000 {
	compatible = "nvidia,tegra114-dsi";
	reg = <0x54400000 0x00040000>;
	clocks = <&tegra_car TEGRA114_CLK_DSIB>,
	<&tegra_car TEGRA114_CLK_DSIBLP>,
	<&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
	clock-names = "dsi", "lp", "parent";
	resets = <&tegra_car 82>;
	reset-names = "dsi";
	nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
	status = "disabled";

	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	gic: interrupt-controller@50041000 {
	compatible = "arm,cortex-a15-gic";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x50041000 0x1000>,
	<0x50042000 0x1000>,
	<0x50044000 0x2000>,
	<0x50046000 0x2000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	interrupt-parent = <&gic>;
	};

	lic: interrupt-controller@60004000 {
	compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
	reg = <0x60004000 0x100>,
	<0x60004100 0x50>,
	<0x60004200 0x50>,
	<0x60004300 0x50>,
	<0x60004400 0x50>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	};

	timer@60005000 {
	compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
	reg = <0x60005000 0x400>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA114_CLK_TIMER>;
	};

	tegra_car: clock@60006000 {
	compatible = "nvidia,tegra114-car";
	reg = <0x60006000 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	flow-controller@60007000 {
	compatible = "nvidia,tegra114-flowctrl";
	reg = <0x60007000 0x1000>;
	};

	apbdma: dma@6000a000 {
	compatible = "nvidia,tegra114-apbdma";
	reg = <0x6000a000 0x1400>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
	resets = <&tegra_car 34>;
	reset-names = "dma";
	#dma-cells = <1>;
	};

	ahb: ahb@6000c000 {
	compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
	reg = <0x6000c000 0x150>;
	};

	gpio: gpio@6000d000 {
	compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
	reg = <0x6000d000 0x1000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	#interrupt-cells = <2>;
	interrupt-controller;
	/*
	gpio-ranges = <&pinmux 0 0 246>;
	*/
	};

	apbmisc@70000800 {
	compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
	reg = <0x70000800 0x64 /* Chip revision */
	0x70000008 0x04>; /* Strapping options */
	};

	pinmux: pinmux@70000868 {
	compatible = "nvidia,tegra114-pinmux";
	reg = <0x70000868 0x148 /* Pad control registers */
	0x70003000 0x40c>; /* Mux registers */
	};

	/*
	* There are two serial driver i.e. 8250 based simple serial
	* driver and APB DMA based serial driver for higher baudrate
	* and performace. To enable the 8250 based driver, the compatible
	* is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
	* the APB DMA based serial driver, the compatible is
	* "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
	*/
	uarta: serial@70006000 {
	compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
	reg = <0x70006000 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA114_CLK_UARTA>;
	resets = <&tegra_car 6>;
	reset-names = "serial";
	dmas = <&apbdma 8>, <&apbdma 8>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartb: serial@70006040 {
	compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
	reg = <0x70006040 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA114_CLK_UARTB>;
	resets = <&tegra_car 7>;
	reset-names = "serial";
	dmas = <&apbdma 9>, <&apbdma 9>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartc: serial@70006200 {
	compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
	reg = <0x70006200 0x100>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA114_CLK_UARTC>;
	resets = <&tegra_car 55>;
	reset-names = "serial";
	dmas = <&apbdma 10>, <&apbdma 10>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartd: serial@70006300 {
	compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
	reg = <0x70006300 0x100>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA114_CLK_UARTD>;
	resets = <&tegra_car 65>;
	reset-names = "serial";
	dmas = <&apbdma 19>, <&apbdma 19>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	pwm: pwm@7000a000 {
	compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
	reg = <0x7000a000 0x100>;
	#pwm-cells = <2>;
	clocks = <&tegra_car TEGRA114_CLK_PWM>;
	resets = <&tegra_car 17>;
	reset-names = "pwm";
	status = "disabled";
	};

	i2c@7000c000 {
	compatible = "nvidia,tegra114-i2c";
	reg = <0x7000c000 0x100>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA114_CLK_I2C1>;
	clock-names = "div-clk";
	resets = <&tegra_car 12>;
	reset-names = "i2c";
	dmas = <&apbdma 21>, <&apbdma 21>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000c400 {
	compatible = "nvidia,tegra114-i2c";
	reg = <0x7000c400 0x100>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA114_CLK_I2C2>;
	clock-names = "div-clk";
	resets = <&tegra_car 54>;
	reset-names = "i2c";
	dmas = <&apbdma 22>, <&apbdma 22>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000c500 {
	compatible = "nvidia,tegra114-i2c";
	reg = <0x7000c500 0x100>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA114_CLK_I2C3>;
	clock-names = "div-clk";
	resets = <&tegra_car 67>;
	reset-names = "i2c";
	dmas = <&apbdma 23>, <&apbdma 23>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000c700 {
	compatible = "nvidia,tegra114-i2c";
	reg = <0x7000c700 0x100>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA114_CLK_I2C4>;
	clock-names = "div-clk";
	resets = <&tegra_car 103>;
	reset-names = "i2c";
	dmas = <&apbdma 26>, <&apbdma 26>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000d000 {
	compatible = "nvidia,tegra114-i2c";
	reg = <0x7000d000 0x100>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA114_CLK_I2C5>;
	clock-names = "div-clk";
	resets = <&tegra_car 47>;
	reset-names = "i2c";
	dmas = <&apbdma 24>, <&apbdma 24>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000d400 {
	compatible = "nvidia,tegra114-spi";
	reg = <0x7000d400 0x200>;
	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA114_CLK_SBC1>;
	clock-names = "spi";
	resets = <&tegra_car 41>;
	reset-names = "spi";
	dmas = <&apbdma 15>, <&apbdma 15>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000d600 {
	compatible = "nvidia,tegra114-spi";
	reg = <0x7000d600 0x200>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA114_CLK_SBC2>;
	clock-names = "spi";
	resets = <&tegra_car 44>;
	reset-names = "spi";
	dmas = <&apbdma 16>, <&apbdma 16>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000d800 {
	compatible = "nvidia,tegra114-spi";
	reg = <0x7000d800 0x200>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA114_CLK_SBC3>;
	clock-names = "spi";
	resets = <&tegra_car 46>;
	reset-names = "spi";
	dmas = <&apbdma 17>, <&apbdma 17>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000da00 {
	compatible = "nvidia,tegra114-spi";
	reg = <0x7000da00 0x200>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA114_CLK_SBC4>;
	clock-names = "spi";
	resets = <&tegra_car 68>;
	reset-names = "spi";
	dmas = <&apbdma 18>, <&apbdma 18>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000dc00 {
	compatible = "nvidia,tegra114-spi";
	reg = <0x7000dc00 0x200>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA114_CLK_SBC5>;
	clock-names = "spi";
	resets = <&tegra_car 104>;
	reset-names = "spi";
	dmas = <&apbdma 27>, <&apbdma 27>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000de00 {
	compatible = "nvidia,tegra114-spi";
	reg = <0x7000de00 0x200>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA114_CLK_SBC6>;
	clock-names = "spi";
	resets = <&tegra_car 105>;
	reset-names = "spi";
	dmas = <&apbdma 28>, <&apbdma 28>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	rtc@7000e000 {
	compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
	reg = <0x7000e000 0x100>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA114_CLK_RTC>;
	};

	kbc@7000e200 {
	compatible = "nvidia,tegra114-kbc";
	reg = <0x7000e200 0x100>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA114_CLK_KBC>;
	resets = <&tegra_car 36>;
	reset-names = "kbc";
	status = "disabled";
	};

	- pmc@7000e400 {
	+ tegra_pmc: pmc@7000e400 {
	compatible = "nvidia,tegra114-pmc";
	reg = <0x7000e400 0x400>;
	clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
	clock-names = "pclk", "clk32k_in";
	+ #clock-cells = <1>;
	};

	fuse@7000f800 {
	compatible = "nvidia,tegra114-efuse";
	reg = <0x7000f800 0x400>;
	clocks = <&tegra_car TEGRA114_CLK_FUSE>;
	clock-names = "fuse";
	resets = <&tegra_car 39>;
	reset-names = "fuse";
	};

	mc: memory-controller@70019000 {
	compatible = "nvidia,tegra114-mc";
	reg = <0x70019000 0x1000>;
	clocks = <&tegra_car TEGRA114_CLK_MC>;
	clock-names = "mc";

	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;

	#iommu-cells = <1>;
	};

	ahub@70080000 {
	compatible = "nvidia,tegra114-ahub";
	reg = <0x70080000 0x200>,
	<0x70080200 0x100>,
	<0x70081000 0x200>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
	<&tegra_car TEGRA114_CLK_APBIF>;
	clock-names = "d_audio", "apbif";
	resets = <&tegra_car 106>, /* d_audio */
	<&tegra_car 107>, /* apbif */
	<&tegra_car 30>, /* i2s0 */
	<&tegra_car 11>, /* i2s1 */
	<&tegra_car 18>, /* i2s2 */
	<&tegra_car 101>, /* i2s3 */
	<&tegra_car 102>, /* i2s4 */
	<&tegra_car 108>, /* dam0 */
	<&tegra_car 109>, /* dam1 */
	<&tegra_car 110>, /* dam2 */
	<&tegra_car 10>, /* spdif */
	<&tegra_car 153>, /* amx */
	<&tegra_car 154>; /* adx */
	reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
	"i2s3", "i2s4", "dam0", "dam1", "dam2",
	"spdif", "amx", "adx";
	dmas = <&apbdma 1>, <&apbdma 1>,
	<&apbdma 2>, <&apbdma 2>,
	<&apbdma 3>, <&apbdma 3>,
	<&apbdma 4>, <&apbdma 4>,
	<&apbdma 6>, <&apbdma 6>,
	<&apbdma 7>, <&apbdma 7>,
	<&apbdma 12>, <&apbdma 12>,
	<&apbdma 13>, <&apbdma 13>,
	<&apbdma 14>, <&apbdma 14>,
	<&apbdma 29>, <&apbdma 29>;
	dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
	"rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
	"rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
	"rx9", "tx9";
	ranges;
	#address-cells = <1>;
	#size-cells = <1>;

	tegra_i2s0: i2s@70080300 {
	compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
	reg = <0x70080300 0x100>;
	nvidia,ahub-cif-ids = <4 4>;
	clocks = <&tegra_car TEGRA114_CLK_I2S0>;
	resets = <&tegra_car 30>;
	reset-names = "i2s";
	status = "disabled";
	};

	tegra_i2s1: i2s@70080400 {
	compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
	reg = <0x70080400 0x100>;
	nvidia,ahub-cif-ids = <5 5>;
	clocks = <&tegra_car TEGRA114_CLK_I2S1>;
	resets = <&tegra_car 11>;
	reset-names = "i2s";
	status = "disabled";
	};

	tegra_i2s2: i2s@70080500 {
	compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
	reg = <0x70080500 0x100>;
	nvidia,ahub-cif-ids = <6 6>;
	clocks = <&tegra_car TEGRA114_CLK_I2S2>;
	resets = <&tegra_car 18>;
	reset-names = "i2s";
	status = "disabled";
	};

	tegra_i2s3: i2s@70080600 {
	compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
	reg = <0x70080600 0x100>;
	nvidia,ahub-cif-ids = <7 7>;
	clocks = <&tegra_car TEGRA114_CLK_I2S3>;
	resets = <&tegra_car 101>;
	reset-names = "i2s";
	status = "disabled";
	};

	tegra_i2s4: i2s@70080700 {
	compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
	reg = <0x70080700 0x100>;
	nvidia,ahub-cif-ids = <8 8>;
	clocks = <&tegra_car TEGRA114_CLK_I2S4>;
	resets = <&tegra_car 102>;
	reset-names = "i2s";
	status = "disabled";
	};
	};

	mipi: mipi@700e3000 {
	compatible = "nvidia,tegra114-mipi";
	reg = <0x700e3000 0x100>;
	clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
	#nvidia,mipi-calibrate-cells = <1>;
	};

	sdhci@78000000 {
	compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
	reg = <0x78000000 0x200>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
	resets = <&tegra_car 14>;
	reset-names = "sdhci";
	status = "disabled";
	};

	sdhci@78000200 {
	compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
	reg = <0x78000200 0x200>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
	resets = <&tegra_car 9>;
	reset-names = "sdhci";
	status = "disabled";
	};

	sdhci@78000400 {
	compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
	reg = <0x78000400 0x200>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
	resets = <&tegra_car 69>;
	reset-names = "sdhci";
	status = "disabled";
	};

	sdhci@78000600 {
	compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
	reg = <0x78000600 0x200>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
	resets = <&tegra_car 15>;
	reset-names = "sdhci";
	status = "disabled";
	};

	usb@7d000000 {
	compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
	reg = <0x7d000000 0x4000>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA114_CLK_USBD>;
	resets = <&tegra_car 22>;
	reset-names = "usb";
	nvidia,phy = <&phy1>;
	status = "disabled";
	};

	phy1: usb-phy@7d000000 {
	compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
	reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA114_CLK_USBD>,
	<&tegra_car TEGRA114_CLK_PLL_U>,
	<&tegra_car TEGRA114_CLK_USBD>;
	clock-names = "reg", "pll_u", "utmi-pads";
	resets = <&tegra_car 22>, <&tegra_car 22>;
	reset-names = "usb", "utmi-pads";
	nvidia,hssync-start-delay = <0>;
	nvidia,idle-wait-delay = <17>;
	nvidia,elastic-limit = <16>;
	nvidia,term-range-adj = <6>;
	nvidia,xcvr-setup = <9>;
	nvidia,xcvr-lsfslew = <0>;
	nvidia,xcvr-lsrslew = <3>;
	nvidia,hssquelch-level = <2>;
	nvidia,hsdiscon-level = <5>;
	nvidia,xcvr-hsslew = <12>;
	nvidia,has-utmi-pad-registers;
	status = "disabled";
	};

	usb@7d008000 {
	compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
	reg = <0x7d008000 0x4000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA114_CLK_USB3>;
	resets = <&tegra_car 59>;
	reset-names = "usb";
	nvidia,phy = <&phy3>;
	status = "disabled";
	};

	phy3: usb-phy@7d008000 {
	compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
	reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA114_CLK_USB3>,
	<&tegra_car TEGRA114_CLK_PLL_U>,
	<&tegra_car TEGRA114_CLK_USBD>;
	clock-names = "reg", "pll_u", "utmi-pads";
	resets = <&tegra_car 59>, <&tegra_car 22>;
	reset-names = "usb", "utmi-pads";
	nvidia,hssync-start-delay = <0>;
	nvidia,idle-wait-delay = <17>;
	nvidia,elastic-limit = <16>;
	nvidia,term-range-adj = <6>;
	nvidia,xcvr-setup = <9>;
	nvidia,xcvr-lsfslew = <0>;
	nvidia,xcvr-lsrslew = <3>;
	nvidia,hssquelch-level = <2>;
	nvidia,hsdiscon-level = <5>;
	nvidia,xcvr-hsslew = <12>;
	status = "disabled";
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0>;
	};

	cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <1>;
	};

	cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <2>;
	};

	cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <3>;
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts =
	<GIC_PPI 13
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	interrupt-parent = <&gic>;
	};
	};
	diff --git a/sys/gnu/dts/arm/tegra124-apalis-v1.2.dtsi b/sys/gnu/dts/arm/tegra124-apalis-v1.2.dtsi
	index 0462ed2dd8b8..de499f736bda 100644
	--- a/sys/gnu/dts/arm/tegra124-apalis-v1.2.dtsi
	+++ b/sys/gnu/dts/arm/tegra124-apalis-v1.2.dtsi
	@@ -1,2065 +1,2071 @@
	// SPDX-License-Identifier: GPL-2.0 OR MIT
	/*
	* Copyright 2016-2018 Toradex AG
	*/

	#include "tegra124.dtsi"
	#include "tegra124-apalis-emc.dtsi"

	/*
	* Toradex Apalis TK1 Module Device Tree
	* Compatible for Revisions 2GB: V1.2A
	*/
	/ {
	memory@80000000 {
	reg = <0x0 0x80000000 0x0 0x80000000>;
	};

	pcie@1003000 {
	status = "okay";

	avddio-pex-supply = <&reg_1v05_vdd>;
	avdd-pex-pll-supply = <&reg_1v05_vdd>;
	avdd-pll-erefe-supply = <&reg_1v05_avdd>;
	dvddio-pex-supply = <&reg_1v05_vdd>;
	hvdd-pex-pll-e-supply = <&reg_module_3v3>;
	hvdd-pex-supply = <&reg_module_3v3>;
	vddio-pex-ctl-supply = <&reg_module_3v3>;

	/* Apalis PCIe (additional lane Apalis type specific) */
	pci@1,0 {
	/* PCIE1_RX/TX and TS_DIFF1/2 */
	phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
	phy-names = "pcie-0", "pcie-1";
	};

	/* I210 Gigabit Ethernet Controller (On-module) */
	pci@2,0 {
	phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
	phy-names = "pcie-0";
	status = "okay";

	pcie@0 {
	reg = <0 0 0 0 0>;
	local-mac-address = [00 00 00 00 00 00];
	};
	};
	};

	host1x@50000000 {
	hdmi@54280000 {
	nvidia,ddc-i2c-bus = <&hdmi_ddc>;
	nvidia,hpd-gpio =
	<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
	pll-supply = <&reg_1v05_avdd_hdmi_pll>;
	vdd-supply = <&reg_3v3_avdd_hdmi>;
	};
	};

	gpu@0,57000000 {
	/*
	* Node left disabled on purpose - the bootloader will enable
	* it after having set the VPR up
	*/
	vdd-supply = <&reg_vdd_gpu>;
	};

	pinmux@70000868 {
	pinctrl-names = "default";
	pinctrl-0 = <&state_default>;

	state_default: pinmux {
	/* Analogue Audio (On-module) */
	dap3-fs-pp0 {
	nvidia,pins = "dap3_fs_pp0";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap3-din-pp1 {
	nvidia,pins = "dap3_din_pp1";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap3-dout-pp2 {
	nvidia,pins = "dap3_dout_pp2";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap3-sclk-pp3 {
	nvidia,pins = "dap3_sclk_pp3";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap-mclk1-pw4 {
	nvidia,pins = "dap_mclk1_pw4";
	nvidia,function = "extperiph1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis BKL1_ON */
	pbb5 {
	nvidia,pins = "pbb5";
	nvidia,function = "vgp5";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis BKL1_PWM */
	pu6 {
	nvidia,pins = "pu6";
	nvidia,function = "pwm3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis CAM1_MCLK */
	cam-mclk-pcc0 {
	nvidia,pins = "cam_mclk_pcc0";
	nvidia,function = "vi_alt3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis Digital Audio */
	dap2-fs-pa2 {
	nvidia,pins = "dap2_fs_pa2";
	nvidia,function = "hda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap2-sclk-pa3 {
	nvidia,pins = "dap2_sclk_pa3";
	nvidia,function = "hda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap2-din-pa4 {
	nvidia,pins = "dap2_din_pa4";
	nvidia,function = "hda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap2-dout-pa5 {
	nvidia,pins = "dap2_dout_pa5";
	nvidia,function = "hda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pbb3 { /* DAP1_RESET */
	nvidia,pins = "pbb3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	clk3-out-pee0 {
	nvidia,pins = "clk3_out_pee0";
	nvidia,function = "extperiph3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis GPIO */
	usb-vbus-en0-pn4 {
	nvidia,pins = "usb_vbus_en0_pn4";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	usb-vbus-en1-pn5 {
	nvidia,pins = "usb_vbus_en1_pn5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pex-l0-rst-n-pdd1 {
	nvidia,pins = "pex_l0_rst_n_pdd1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pex-l0-clkreq-n-pdd2 {
	nvidia,pins = "pex_l0_clkreq_n_pdd2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pex-l1-rst-n-pdd5 {
	nvidia,pins = "pex_l1_rst_n_pdd5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pex-l1-clkreq-n-pdd6 {
	nvidia,pins = "pex_l1_clkreq_n_pdd6";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dp-hpd-pff0 {
	nvidia,pins = "dp_hpd_pff0";
	nvidia,function = "dp";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pff2 {
	nvidia,pins = "pff2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
	nvidia,pins = "owr";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis HDMI1_CEC */
	hdmi-cec-pee3 {
	nvidia,pins = "hdmi_cec_pee3";
	nvidia,function = "cec";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis HDMI1_HPD */
	hdmi-int-pn7 {
	nvidia,pins = "hdmi_int_pn7";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis I2C1 */
	gen1-i2c-scl-pc4 {
	nvidia,pins = "gen1_i2c_scl_pc4";
	nvidia,function = "i2c1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	gen1-i2c-sda-pc5 {
	nvidia,pins = "gen1_i2c_sda_pc5";
	nvidia,function = "i2c1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis I2C3 (CAM) */
	cam-i2c-scl-pbb1 {
	nvidia,pins = "cam_i2c_scl_pbb1";
	nvidia,function = "i2c3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	cam-i2c-sda-pbb2 {
	nvidia,pins = "cam_i2c_sda_pbb2";
	nvidia,function = "i2c3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis I2C4 (DDC) */
	ddc-scl-pv4 {
	nvidia,pins = "ddc_scl_pv4";
	nvidia,function = "i2c4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
	};
	ddc-sda-pv5 {
	nvidia,pins = "ddc_sda_pv5";
	nvidia,function = "i2c4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis MMC1 */
	sdmmc1-cd-n-pv3 { /* CD# GPIO */
	nvidia,pins = "sdmmc1_wp_n_pv3";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	clk2-out-pw5 { /* D5 GPIO */
	nvidia,pins = "clk2_out_pw5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1-dat3-py4 {
	nvidia,pins = "sdmmc1_dat3_py4";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1-dat2-py5 {
	nvidia,pins = "sdmmc1_dat2_py5";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1-dat1-py6 {
	nvidia,pins = "sdmmc1_dat1_py6";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1-dat0-py7 {
	nvidia,pins = "sdmmc1_dat0_py7";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1-clk-pz0 {
	nvidia,pins = "sdmmc1_clk_pz0";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1-cmd-pz1 {
	nvidia,pins = "sdmmc1_cmd_pz1";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	clk2-req-pcc5 { /* D4 GPIO */
	nvidia,pins = "clk2_req_pcc5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */
	nvidia,pins = "sdmmc3_clk_lb_in_pee5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	usb-vbus-en2-pff1 { /* D7 GPIO */
	nvidia,pins = "usb_vbus_en2_pff1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis PWM */
	ph0 {
	nvidia,pins = "ph0";
	nvidia,function = "pwm0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph1 {
	nvidia,pins = "ph1";
	nvidia,function = "pwm1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph2 {
	nvidia,pins = "ph2";
	nvidia,function = "pwm2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	/* PWM3 active on pu6 being Apalis BKL1_PWM as well */
	ph3 {
	nvidia,pins = "ph3";
	nvidia,function = "pwm3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis SATA1_ACT# */
	dap1-dout-pn2 {
	nvidia,pins = "dap1_dout_pn2";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis SD1 */
	sdmmc3-clk-pa6 {
	nvidia,pins = "sdmmc3_clk_pa6";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3-cmd-pa7 {
	nvidia,pins = "sdmmc3_cmd_pa7";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3-dat3-pb4 {
	nvidia,pins = "sdmmc3_dat3_pb4";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3-dat2-pb5 {
	nvidia,pins = "sdmmc3_dat2_pb5";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3-dat1-pb6 {
	nvidia,pins = "sdmmc3_dat1_pb6";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3-dat0-pb7 {
	nvidia,pins = "sdmmc3_dat0_pb7";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3-cd-n-pv2 { /* CD# GPIO */
	nvidia,pins = "sdmmc3_cd_n_pv2";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis SPDIF */
	spdif-out-pk5 {
	nvidia,pins = "spdif_out_pk5";
	nvidia,function = "spdif";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	spdif-in-pk6 {
	nvidia,pins = "spdif_in_pk6";
	nvidia,function = "spdif";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis SPI1 */
	ulpi-clk-py0 {
	nvidia,pins = "ulpi_clk_py0";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi-dir-py1 {
	nvidia,pins = "ulpi_dir_py1";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ulpi-nxt-py2 {
	nvidia,pins = "ulpi_nxt_py2";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi-stp-py3 {
	nvidia,pins = "ulpi_stp_py3";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis SPI2 */
	pg5 {
	nvidia,pins = "pg5";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pg6 {
	nvidia,pins = "pg6";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pg7 {
	nvidia,pins = "pg7";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pi3 {
	nvidia,pins = "pi3";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis UART1 */
	pb1 { /* DCD GPIO */
	nvidia,pins = "pb1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pk7 { /* RI GPIO */
	nvidia,pins = "pk7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart1-txd-pu0 {
	nvidia,pins = "pu0";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart1-rxd-pu1 {
	nvidia,pins = "pu1";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart1-cts-n-pu2 {
	nvidia,pins = "pu2";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart1-rts-n-pu3 {
	nvidia,pins = "pu3";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart3-cts-n-pa1 { /* DSR GPIO */
	nvidia,pins = "uart3_cts_n_pa1";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart3-rts-n-pc0 { /* DTR GPIO */
	nvidia,pins = "uart3_rts_n_pc0";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis UART2 */
	uart2-txd-pc2 {
	nvidia,pins = "uart2_txd_pc2";
	nvidia,function = "irda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart2-rxd-pc3 {
	nvidia,pins = "uart2_rxd_pc3";
	nvidia,function = "irda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart2-cts-n-pj5 {
	nvidia,pins = "uart2_cts_n_pj5";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart2-rts-n-pj6 {
	nvidia,pins = "uart2_rts_n_pj6";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis UART3 */
	uart3-txd-pw6 {
	nvidia,pins = "uart3_txd_pw6";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart3-rxd-pw7 {
	nvidia,pins = "uart3_rxd_pw7";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis UART4 */
	uart4-rxd-pb0 {
	nvidia,pins = "pb0";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart4-txd-pj7 {
	nvidia,pins = "pj7";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis USBH_EN */
	gen2-i2c-sda-pt6 {
	nvidia,pins = "gen2_i2c_sda_pt6";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis USBH_OC# */
	pbb0 {
	nvidia,pins = "pbb0";
	nvidia,function = "vgp6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis USBO1_EN */
	gen2-i2c-scl-pt5 {
	nvidia,pins = "gen2_i2c_scl_pt5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis USBO1_OC# */
	pbb4 {
	nvidia,pins = "pbb4";
	nvidia,function = "vgp4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis WAKE1_MICO */
	pex-wake-n-pdd3 {
	nvidia,pins = "pex_wake_n_pdd3";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* CORE_PWR_REQ */
	core-pwr-req {
	nvidia,pins = "core_pwr_req";
	nvidia,function = "pwron";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* CPU_PWR_REQ */
	cpu-pwr-req {
	nvidia,pins = "cpu_pwr_req";
	nvidia,function = "cpu";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* DVFS */
	dvfs-pwm-px0 {
	nvidia,pins = "dvfs_pwm_px0";
	nvidia,function = "cldvfs";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dvfs-clk-px2 {
	nvidia,pins = "dvfs_clk_px2";
	nvidia,function = "cldvfs";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* eMMC */
	sdmmc4-dat0-paa0 {
	nvidia,pins = "sdmmc4_dat0_paa0";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-dat1-paa1 {
	nvidia,pins = "sdmmc4_dat1_paa1";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-dat2-paa2 {
	nvidia,pins = "sdmmc4_dat2_paa2";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-dat3-paa3 {
	nvidia,pins = "sdmmc4_dat3_paa3";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-dat4-paa4 {
	nvidia,pins = "sdmmc4_dat4_paa4";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-dat5-paa5 {
	nvidia,pins = "sdmmc4_dat5_paa5";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-dat6-paa6 {
	nvidia,pins = "sdmmc4_dat6_paa6";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-dat7-paa7 {
	nvidia,pins = "sdmmc4_dat7_paa7";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-clk-pcc4 {
	nvidia,pins = "sdmmc4_clk_pcc4";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-cmd-pt7 {
	nvidia,pins = "sdmmc4_cmd_pt7";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* JTAG_RTCK */
	jtag-rtck {
	nvidia,pins = "jtag_rtck";
	nvidia,function = "rtck";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* LAN_DEV_OFF# */
	ulpi-data5-po6 {
	nvidia,pins = "ulpi_data5_po6";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* LAN_RESET# */
	kb-row10-ps2 {
	nvidia,pins = "kb_row10_ps2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* LAN_WAKE# */
	ulpi-data4-po5 {
	nvidia,pins = "ulpi_data4_po5";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* MCU_INT1# */
	pk2 {
	nvidia,pins = "pk2";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* MCU_INT2# */
	pj2 {
	nvidia,pins = "pj2";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* MCU_INT3# */
	pi5 {
	nvidia,pins = "pi5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* MCU_INT4# */
	pj0 {
	nvidia,pins = "pj0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* MCU_RESET */
	pbb6 {
	nvidia,pins = "pbb6";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* MCU SPI */
	gpio-x4-aud-px4 {
	nvidia,pins = "gpio_x4_aud_px4";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gpio-x5-aud-px5 {
	nvidia,pins = "gpio_x5_aud_px5";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gpio-x6-aud-px6 { /* MCU_CS */
	nvidia,pins = "gpio_x6_aud_px6";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gpio-x7-aud-px7 {
	nvidia,pins = "gpio_x7_aud_px7";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gpio-w2-aud-pw2 { /* MCU_CSEZP */
	nvidia,pins = "gpio_w2_aud_pw2";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* PMIC_CLK_32K */
	clk-32k-in {
	nvidia,pins = "clk_32k_in";
	nvidia,function = "clk";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* PMIC_CPU_OC_INT */
	clk-32k-out-pa0 {
	nvidia,pins = "clk_32k_out_pa0";
	nvidia,function = "soc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* PWR_I2C */
	pwr-i2c-scl-pz6 {
	nvidia,pins = "pwr_i2c_scl_pz6";
	nvidia,function = "i2cpwr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	pwr-i2c-sda-pz7 {
	nvidia,pins = "pwr_i2c_sda_pz7";
	nvidia,function = "i2cpwr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};

	/* PWR_INT_N */
	pwr-int-n {
	nvidia,pins = "pwr_int_n";
	nvidia,function = "pmi";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* RESET_MOCI_CTRL */
	pu4 {
	nvidia,pins = "pu4";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* RESET_OUT_N */
	reset-out-n {
	nvidia,pins = "reset_out_n";
	nvidia,function = "reset_out_n";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* SHIFT_CTRL_DIR_IN */
	kb-row0-pr0 {
	nvidia,pins = "kb_row0_pr0";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row1-pr1 {
	nvidia,pins = "kb_row1_pr1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Configure level-shifter as output for HDA */
	kb-row11-ps3 {
	nvidia,pins = "kb_row11_ps3";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* SHIFT_CTRL_DIR_OUT */
	kb-col5-pq5 {
	nvidia,pins = "kb_col5_pq5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-col6-pq6 {
	nvidia,pins = "kb_col6_pq6";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-col7-pq7 {
	nvidia,pins = "kb_col7_pq7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* SHIFT_CTRL_OE */
	kb-col0-pq0 {
	nvidia,pins = "kb_col0_pq0";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-col1-pq1 {
	nvidia,pins = "kb_col1_pq1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-col2-pq2 {
	nvidia,pins = "kb_col2_pq2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-col4-pq4 {
	nvidia,pins = "kb_col4_pq4";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row2-pr2 {
	nvidia,pins = "kb_row2_pr2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
	pi6 {
	nvidia,pins = "pi6";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* TOUCH_INT */
	gpio-w3-aud-pw3 {
	nvidia,pins = "gpio_w3_aud_pw3";
	nvidia,function = "spi6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	pc7 { /* NC */
	nvidia,pins = "pc7";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pg0 { /* NC */
	nvidia,pins = "pg0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pg1 { /* NC */
	nvidia,pins = "pg1";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pg2 { /* NC */
	nvidia,pins = "pg2";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pg3 { /* NC */
	nvidia,pins = "pg3";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pg4 { /* NC */
	nvidia,pins = "pg4";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph4 { /* NC */
	nvidia,pins = "ph4";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph5 { /* NC */
	nvidia,pins = "ph5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph6 { /* NC */
	nvidia,pins = "ph6";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph7 { /* NC */
	nvidia,pins = "ph7";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pi0 { /* NC */
	nvidia,pins = "pi0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pi1 { /* NC */
	nvidia,pins = "pi1";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pi2 { /* NC */
	nvidia,pins = "pi2";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pi4 { /* NC */
	nvidia,pins = "pi4";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pi7 { /* NC */
	nvidia,pins = "pi7";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pk0 { /* NC */
	nvidia,pins = "pk0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pk1 { /* NC */
	nvidia,pins = "pk1";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pk3 { /* NC */
	nvidia,pins = "pk3";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pk4 { /* NC */
	nvidia,pins = "pk4";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap1-fs-pn0 { /* NC */
	nvidia,pins = "dap1_fs_pn0";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap1-din-pn1 { /* NC */
	nvidia,pins = "dap1_din_pn1";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap1-sclk-pn3 { /* NC */
	nvidia,pins = "dap1_sclk_pn3";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi-data7-po0 { /* NC */
	nvidia,pins = "ulpi_data7_po0";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi-data0-po1 { /* NC */
	nvidia,pins = "ulpi_data0_po1";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi-data1-po2 { /* NC */
	nvidia,pins = "ulpi_data1_po2";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi-data2-po3 { /* NC */
	nvidia,pins = "ulpi_data2_po3";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi-data3-po4 { /* NC */
	nvidia,pins = "ulpi_data3_po4";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi-data6-po7 { /* NC */
	nvidia,pins = "ulpi_data6_po7";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap4-fs-pp4 { /* NC */
	nvidia,pins = "dap4_fs_pp4";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap4-din-pp5 { /* NC */
	nvidia,pins = "dap4_din_pp5";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap4-dout-pp6 { /* NC */
	nvidia,pins = "dap4_dout_pp6";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap4-sclk-pp7 { /* NC */
	nvidia,pins = "dap4_sclk_pp7";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-col3-pq3 { /* NC */
	nvidia,pins = "kb_col3_pq3";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row3-pr3 { /* NC */
	nvidia,pins = "kb_row3_pr3";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row4-pr4 { /* NC */
	nvidia,pins = "kb_row4_pr4";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row5-pr5 { /* NC */
	nvidia,pins = "kb_row5_pr5";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row6-pr6 { /* NC */
	nvidia,pins = "kb_row6_pr6";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row7-pr7 { /* NC */
	nvidia,pins = "kb_row7_pr7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row8-ps0 { /* NC */
	nvidia,pins = "kb_row8_ps0";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row9-ps1 { /* NC */
	nvidia,pins = "kb_row9_ps1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row12-ps4 { /* NC */
	nvidia,pins = "kb_row12_ps4";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row13-ps5 { /* NC */
	nvidia,pins = "kb_row13_ps5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row14-ps6 { /* NC */
	nvidia,pins = "kb_row14_ps6";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row15-ps7 { /* NC */
	nvidia,pins = "kb_row15_ps7";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row16-pt0 { /* NC */
	nvidia,pins = "kb_row16_pt0";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row17-pt1 { /* NC */
	nvidia,pins = "kb_row17_pt1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pu5 { /* NC */
	nvidia,pins = "pu5";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	/*
	* PCB Version Indication: V1.2 and later have GPIO_PV0
	* wired to GND, was NC before
	*/
	pv0 {
	nvidia,pins = "pv0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pv1 { /* NC */
	nvidia,pins = "pv1";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gpio-x1-aud-px1 { /* NC */
	nvidia,pins = "gpio_x1_aud_px1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gpio-x3-aud-px3 { /* NC */
	nvidia,pins = "gpio_x3_aud_px3";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pbb7 { /* NC */
	nvidia,pins = "pbb7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pcc1 { /* NC */
	nvidia,pins = "pcc1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pcc2 { /* NC */
	nvidia,pins = "pcc2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	clk3-req-pee1 { /* NC */
	nvidia,pins = "clk3_req_pee1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap-mclk1-req-pee2 { /* NC */
	nvidia,pins = "dap_mclk1_req_pee2";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	/*
	* Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
	* driver enabled aka not tristated and input driver
	* enabled as well as it features some magic properties
	* even though the external loopback is disabled and the
	* internal loopback used as per
	* SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
	* bits being set to 0xfffd according to the TRM!
	*/
	sdmmc3-clk-lb-out-pee4 { /* NC */
	nvidia,pins = "sdmmc3_clk_lb_out_pee4";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	};
	};

	serial@70006040 {
	compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
	};

	serial@70006200 {
	compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
	};

	serial@70006300 {
	compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
	};

	hdmi_ddc: i2c@7000c700 {
	clock-frequency = <10000>;
	};

	/* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
	i2c@7000d000 {
	status = "okay";
	clock-frequency = <400000>;

	/* SGTL5000 audio codec */
	sgtl5000: codec@a {
	compatible = "fsl,sgtl5000";
	reg = <0x0a>;
	VDDA-supply = <&reg_module_3v3_audio>;
	VDDD-supply = <&reg_1v8_vddio>;
	VDDIO-supply = <&reg_1v8_vddio>;
	clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
	};

	pmic: pmic@40 {
	compatible = "ams,as3722";
	reg = <0x40>;
	interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
	ams,system-power-controller;
	#interrupt-cells = <2>;
	interrupt-controller;
	gpio-controller;
	#gpio-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&as3722_default>;

	as3722_default: pinmux {
	gpio2-7 {
	pins = "gpio2", /* PWR_EN_+V3.3 */
	"gpio7"; /* +V1.6_LPO */
	function = "gpio";
	bias-pull-up;
	};

	gpio0-1-3-4-5-6 {
	pins = "gpio0", "gpio1", "gpio3",
	"gpio4", "gpio5", "gpio6";
	bias-high-impedance;
	};
	};

	regulators {
	vsup-sd2-supply = <&reg_module_3v3>;
	vsup-sd3-supply = <&reg_module_3v3>;
	vsup-sd4-supply = <&reg_module_3v3>;
	vsup-sd5-supply = <&reg_module_3v3>;
	vin-ldo0-supply = <&reg_1v35_vddio_ddr>;
	vin-ldo1-6-supply = <&reg_module_3v3>;
	vin-ldo2-5-7-supply = <&reg_1v8_vddio>;
	vin-ldo3-4-supply = <&reg_module_3v3>;
	vin-ldo9-10-supply = <&reg_module_3v3>;
	vin-ldo11-supply = <&reg_module_3v3>;

	reg_vdd_cpu: sd0 {
	regulator-name = "+VDD_CPU_AP";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1400000>;
	regulator-min-microamp = <3500000>;
	regulator-max-microamp = <3500000>;
	regulator-always-on;
	regulator-boot-on;
	ams,ext-control = <2>;
	};

	sd1 {
	regulator-name = "+VDD_CORE";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1350000>;
	regulator-min-microamp = <2500000>;
	regulator-max-microamp = <4000000>;
	regulator-always-on;
	regulator-boot-on;
	ams,ext-control = <1>;
	};

	reg_1v35_vddio_ddr: sd2 {
	regulator-name =
	"+V1.35_VDDIO_DDR(sd2)";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	};

	sd3 {
	regulator-name =
	"+V1.35_VDDIO_DDR(sd3)";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	};

	reg_1v05_vdd: sd4 {
	regulator-name = "+V1.05";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	};

	reg_1v8_vddio: sd5 {
	regulator-name = "+V1.8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_vdd_gpu: sd6 {
	regulator-name = "+VDD_GPU_AP";
	regulator-min-microvolt = <650000>;
	regulator-max-microvolt = <1200000>;
	regulator-min-microamp = <3500000>;
	regulator-max-microamp = <3500000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_1v05_avdd: ldo0 {
	regulator-name = "+V1.05_AVDD";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	regulator-boot-on;
	regulator-always-on;
	ams,ext-control = <1>;
	};

	vddio_sdmmc1: ldo1 {
	regulator-name = "VDDIO_SDMMC1";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	};

	ldo2 {
	regulator-name = "+V1.2";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo3 {
	regulator-name = "+V1.05_RTC";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-boot-on;
	regulator-always-on;
	ams,enable-tracking;
	};

	/* 1.8V for LVDS, 3.3V for eDP */
	ldo4 {
	regulator-name = "AVDD_LVDS0_PLL";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	/* LDO5 not used */

	vddio_sdmmc3: ldo6 {
	regulator-name = "VDDIO_SDMMC3";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	};

	/* LDO7 not used */

	ldo9 {
	regulator-name = "+V3.3_ETH(ldo9)";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	ldo10 {
	regulator-name = "+V3.3_ETH(ldo10)";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	ldo11 {
	regulator-name = "+V1.8_VPP_FUSE";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	};
	};

	/*
	* TMP451 temperature sensor
	* Note: THERM_N directly connected to AS3722 PMIC THERM
	*/
	temp-sensor@4c {
	compatible = "ti,tmp451";
	reg = <0x4c>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
	#thermal-sensor-cells = <1>;
	vcc-supply = <&reg_module_3v3>;
	};
	};

	/* SPI2: MCU SPI */
	spi@7000d600 {
	status = "okay";
	spi-max-frequency = <25000000>;
	};

	pmc@7000e400 {
	nvidia,invert-interrupt;
	nvidia,suspend-mode = <1>;
	nvidia,cpu-pwr-good-time = <500>;
	nvidia,cpu-pwr-off-time = <300>;
	nvidia,core-pwr-good-time = <641 3845>;
	nvidia,core-pwr-off-time = <61036>;
	nvidia,core-power-req-active-high;
	nvidia,sys-clock-req-active-high;

	/* Set power_off bit in ResetControl register of AS3722 PMIC */
	i2c-thermtrip {
	nvidia,i2c-controller-id = <4>;
	nvidia,bus-addr = <0x40>;
	nvidia,reg-addr = <0x36>;
	nvidia,reg-data = <0x2>;
	};
	};

	sata@70020000 {
	phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
	phy-names = "sata-0";
	avdd-supply = <&reg_1v05_vdd>;
	hvdd-supply = <&reg_module_3v3>;
	vddio-supply = <&reg_1v05_vdd>;
	};

	usb@70090000 {
	/* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
	phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
	<&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
	<&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
	phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";

	avddio-pex-supply = <&reg_1v05_vdd>;
	avdd-pll-erefe-supply = <&reg_1v05_avdd>;
	avdd-pll-utmip-supply = <&reg_1v8_vddio>;
	avdd-usb-ss-pll-supply = <&reg_1v05_vdd>;
	avdd-usb-supply = <&reg_module_3v3>;
	dvddio-pex-supply = <&reg_1v05_vdd>;
	hvdd-usb-ss-pll-e-supply = <&reg_module_3v3>;
	hvdd-usb-ss-supply = <&reg_module_3v3>;
	};

	padctl@7009f000 {
	avdd-pll-utmip-supply = <&reg_1v8_vddio>;
	avdd-pll-erefe-supply = <&reg_1v05_avdd>;
	avdd-pex-pll-supply = <&reg_1v05_vdd>;
	hvdd-pex-pll-e-supply = <&reg_module_3v3>;

	pads {
	usb2 {
	status = "okay";

	lanes {
	usb2-0 {
	status = "okay";
	nvidia,function = "xusb";
	};

	usb2-1 {
	status = "okay";
	nvidia,function = "xusb";
	};

	usb2-2 {
	status = "okay";
	nvidia,function = "xusb";
	};
	};
	};

	pcie {
	status = "okay";

	lanes {
	pcie-0 {
	status = "okay";
	nvidia,function = "usb3-ss";
	};

	pcie-1 {
	status = "okay";
	nvidia,function = "usb3-ss";
	};

	pcie-2 {
	status = "okay";
	nvidia,function = "pcie";
	};

	pcie-3 {
	status = "okay";
	nvidia,function = "pcie";
	};

	pcie-4 {
	status = "okay";
	nvidia,function = "pcie";
	};
	};
	};

	sata {
	status = "okay";

	lanes {
	sata-0 {
	status = "okay";
	nvidia,function = "sata";
	};
	};
	};
	};

	ports {
	/* USBO1 */
	usb2-0 {
	status = "okay";
	mode = "otg";
	vbus-supply = <&reg_usbo1_vbus>;
	};

	/* USBH2 */
	usb2-1 {
	status = "okay";
	mode = "host";
	vbus-supply = <&reg_usbh_vbus>;
	};

	/* USBH4 */
	usb2-2 {
	status = "okay";
	mode = "host";
	vbus-supply = <&reg_usbh_vbus>;
	};

	usb3-0 {
	status = "okay";
	nvidia,usb2-companion = <2>;
	vbus-supply = <&reg_usbh_vbus>;
	};

	usb3-1 {
	status = "okay";
	nvidia,usb2-companion = <0>;
	vbus-supply = <&reg_usbo1_vbus>;
	};
	};
	};

	/* eMMC */
	sdhci@700b0600 {
	status = "okay";
	bus-width = <8>;
	non-removable;
	vmmc-supply = <&reg_module_3v3>; /* VCC */
	vqmmc-supply = <&reg_1v8_vddio>; /* VCCQ */
	mmc-ddr-1_8v;
	};

	/* CPU DFLL clock */
	clock@70110000 {
	status = "okay";
	nvidia,i2c-fs-rate = <400000>;
	vdd-cpu-supply = <&reg_vdd_cpu>;
	};

	ahub@70300000 {
	i2s@70301200 {
	status = "okay";
	};
	};

	clk32k_in: osc3 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};

	cpus {
	cpu@0 {
	vdd-cpu-supply = <&reg_vdd_cpu>;
	};
	};

	reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
	compatible = "regulator-fixed";
	regulator-name = "+V1.05_AVDD_HDMI_PLL";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
	vin-supply = <&reg_1v05_vdd>;
	};

	reg_3v3_mxm: regulator-3v3-mxm {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3_MXM";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	};

	reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3_AVDD_HDMI";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&reg_1v05_vdd>;
	};

	reg_module_3v3: regulator-module-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	/* PWR_EN_+V3.3 */
	gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&reg_3v3_mxm>;
	};

	reg_module_3v3_audio: regulator-module-3v3-audio {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3_AUDIO_AVDD_S";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	sound {
	compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
	"nvidia,tegra-audio-sgtl5000";
	nvidia,model = "Toradex Apalis TK1";
	nvidia,audio-routing =
	"Headphone Jack", "HP_OUT",
	"LINE_IN", "Line In Jack",
	"MIC_IN", "Mic Jack";
	nvidia,i2s-controller = <&tegra_i2s2>;
	nvidia,audio-codec = <&sgtl5000>;
	clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
	<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
	- <&tegra_car TEGRA124_CLK_EXTERN1>;
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	clock-names = "pll_a", "pll_a_out0", "mclk";
	+
	+ assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	+
	+ assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
	+ <&tegra_car TEGRA124_CLK_EXTERN1>;
	};

	thermal-zones {
	cpu {
	trips {
	cpu-shutdown-trip {
	temperature = <101000>;
	hysteresis = <0>;
	type = "critical";
	};
	};
	};

	mem {
	trips {
	mem-shutdown-trip {
	temperature = <101000>;
	hysteresis = <0>;
	type = "critical";
	};
	};
	};

	gpu {
	trips {
	gpu-shutdown-trip {
	temperature = <101000>;
	hysteresis = <0>;
	type = "critical";
	};
	};
	};
	};
	};

	&gpio {
	/* I210 Gigabit Ethernet Controller Reset */
	lan-reset-n {
	gpio-hog;
	gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
	output-high;
	line-name = "LAN_RESET_N";
	};

	/* Control MXM3 pin 26 Reset Module Output Carrier Input */
	reset-moci-ctrl {
	gpio-hog;
	gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
	output-high;
	line-name = "RESET_MOCI_CTRL";
	};
	};
	diff --git a/sys/gnu/dts/arm/tegra124-apalis.dtsi b/sys/gnu/dts/arm/tegra124-apalis.dtsi
	index d1e8593ef0d9..d70a86da4ee4 100644
	--- a/sys/gnu/dts/arm/tegra124-apalis.dtsi
	+++ b/sys/gnu/dts/arm/tegra124-apalis.dtsi
	@@ -1,2057 +1,2063 @@
	// SPDX-License-Identifier: GPL-2.0 OR X11
	/*
	* Copyright 2016-2019 Toradex AG
	*/

	#include "tegra124.dtsi"
	#include "tegra124-apalis-emc.dtsi"

	/*
	* Toradex Apalis TK1 Module Device Tree
	* Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A
	*/
	/ {
	memory@80000000 {
	reg = <0x0 0x80000000 0x0 0x80000000>;
	};

	pcie@1003000 {
	status = "okay";
	avddio-pex-supply = <&reg_1v05_vdd>;
	avdd-pex-pll-supply = <&reg_1v05_vdd>;
	avdd-pll-erefe-supply = <&reg_1v05_avdd>;
	dvddio-pex-supply = <&reg_1v05_vdd>;
	hvdd-pex-pll-e-supply = <&reg_module_3v3>;
	hvdd-pex-supply = <&reg_module_3v3>;
	vddio-pex-ctl-supply = <&reg_module_3v3>;

	/* Apalis PCIe (additional lane Apalis type specific) */
	pci@1,0 {
	/* PCIE1_RX/TX and TS_DIFF1/2 */
	phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
	phy-names = "pcie-0", "pcie-1";
	};

	/* I210 Gigabit Ethernet Controller (On-module) */
	pci@2,0 {
	phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
	phy-names = "pcie-0";
	status = "okay";

	pcie@0 {
	reg = <0 0 0 0 0>;
	local-mac-address = [00 00 00 00 00 00];
	};
	};
	};

	host1x@50000000 {
	hdmi@54280000 {
	nvidia,ddc-i2c-bus = <&hdmi_ddc>;
	nvidia,hpd-gpio =
	<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
	pll-supply = <&reg_1v05_avdd_hdmi_pll>;
	vdd-supply = <&reg_3v3_avdd_hdmi>;
	};
	};

	gpu@0,57000000 {
	/*
	* Node left disabled on purpose - the bootloader will enable
	* it after having set the VPR up
	*/
	vdd-supply = <&reg_vdd_gpu>;
	};

	pinmux@70000868 {
	pinctrl-names = "default";
	pinctrl-0 = <&state_default>;

	state_default: pinmux {
	/* Analogue Audio (On-module) */
	dap3-fs-pp0 {
	nvidia,pins = "dap3_fs_pp0";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap3-din-pp1 {
	nvidia,pins = "dap3_din_pp1";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap3-dout-pp2 {
	nvidia,pins = "dap3_dout_pp2";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap3-sclk-pp3 {
	nvidia,pins = "dap3_sclk_pp3";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap-mclk1-pw4 {
	nvidia,pins = "dap_mclk1_pw4";
	nvidia,function = "extperiph1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis BKL1_ON */
	pbb5 {
	nvidia,pins = "pbb5";
	nvidia,function = "vgp5";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis BKL1_PWM */
	pu6 {
	nvidia,pins = "pu6";
	nvidia,function = "pwm3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis CAM1_MCLK */
	cam-mclk-pcc0 {
	nvidia,pins = "cam_mclk_pcc0";
	nvidia,function = "vi_alt3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis Digital Audio */
	dap2-fs-pa2 {
	nvidia,pins = "dap2_fs_pa2";
	nvidia,function = "hda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap2-sclk-pa3 {
	nvidia,pins = "dap2_sclk_pa3";
	nvidia,function = "hda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap2-din-pa4 {
	nvidia,pins = "dap2_din_pa4";
	nvidia,function = "hda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap2-dout-pa5 {
	nvidia,pins = "dap2_dout_pa5";
	nvidia,function = "hda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pbb3 { /* DAP1_RESET */
	nvidia,pins = "pbb3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	clk3-out-pee0 {
	nvidia,pins = "clk3_out_pee0";
	nvidia,function = "extperiph3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis GPIO */
	ddc-scl-pv4 {
	nvidia,pins = "ddc_scl_pv4";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ddc-sda-pv5 {
	nvidia,pins = "ddc_sda_pv5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pex-l0-rst-n-pdd1 {
	nvidia,pins = "pex_l0_rst_n_pdd1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pex-l0-clkreq-n-pdd2 {
	nvidia,pins = "pex_l0_clkreq_n_pdd2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pex-l1-rst-n-pdd5 {
	nvidia,pins = "pex_l1_rst_n_pdd5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pex-l1-clkreq-n-pdd6 {
	nvidia,pins = "pex_l1_clkreq_n_pdd6";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dp-hpd-pff0 {
	nvidia,pins = "dp_hpd_pff0";
	nvidia,function = "dp";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pff2 {
	nvidia,pins = "pff2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
	nvidia,pins = "owr";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis HDMI1_CEC */
	hdmi-cec-pee3 {
	nvidia,pins = "hdmi_cec_pee3";
	nvidia,function = "cec";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis HDMI1_HPD */
	hdmi-int-pn7 {
	nvidia,pins = "hdmi_int_pn7";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis I2C1 */
	gen1-i2c-scl-pc4 {
	nvidia,pins = "gen1_i2c_scl_pc4";
	nvidia,function = "i2c1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	gen1-i2c-sda-pc5 {
	nvidia,pins = "gen1_i2c_sda_pc5";
	nvidia,function = "i2c1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis I2C2 (DDC) */
	gen2-i2c-scl-pt5 {
	nvidia,pins = "gen2_i2c_scl_pt5";
	nvidia,function = "i2c2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	gen2-i2c-sda-pt6 {
	nvidia,pins = "gen2_i2c_sda_pt6";
	nvidia,function = "i2c2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis I2C3 (CAM) */
	cam-i2c-scl-pbb1 {
	nvidia,pins = "cam_i2c_scl_pbb1";
	nvidia,function = "i2c3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	cam-i2c-sda-pbb2 {
	nvidia,pins = "cam_i2c_sda_pbb2";
	nvidia,function = "i2c3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis MMC1 */
	sdmmc1-cd-n-pv3 { /* CD# GPIO */
	nvidia,pins = "sdmmc1_wp_n_pv3";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	clk2-out-pw5 { /* D5 GPIO */
	nvidia,pins = "clk2_out_pw5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1-dat3-py4 {
	nvidia,pins = "sdmmc1_dat3_py4";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1-dat2-py5 {
	nvidia,pins = "sdmmc1_dat2_py5";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1-dat1-py6 {
	nvidia,pins = "sdmmc1_dat1_py6";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1-dat0-py7 {
	nvidia,pins = "sdmmc1_dat0_py7";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1-clk-pz0 {
	nvidia,pins = "sdmmc1_clk_pz0";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1-cmd-pz1 {
	nvidia,pins = "sdmmc1_cmd_pz1";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	clk2-req-pcc5 { /* D4 GPIO */
	nvidia,pins = "clk2_req_pcc5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */
	nvidia,pins = "sdmmc3_clk_lb_in_pee5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	usb-vbus-en2-pff1 { /* D7 GPIO */
	nvidia,pins = "usb_vbus_en2_pff1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis PWM */
	ph0 {
	nvidia,pins = "ph0";
	nvidia,function = "pwm0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph1 {
	nvidia,pins = "ph1";
	nvidia,function = "pwm1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph2 {
	nvidia,pins = "ph2";
	nvidia,function = "pwm2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	/* PWM3 active on pu6 being Apalis BKL1_PWM as well */
	ph3 {
	nvidia,pins = "ph3";
	nvidia,function = "pwm3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis SATA1_ACT# */
	dap1-dout-pn2 {
	nvidia,pins = "dap1_dout_pn2";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis SD1 */
	sdmmc3-clk-pa6 {
	nvidia,pins = "sdmmc3_clk_pa6";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3-cmd-pa7 {
	nvidia,pins = "sdmmc3_cmd_pa7";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3-dat3-pb4 {
	nvidia,pins = "sdmmc3_dat3_pb4";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3-dat2-pb5 {
	nvidia,pins = "sdmmc3_dat2_pb5";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3-dat1-pb6 {
	nvidia,pins = "sdmmc3_dat1_pb6";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3-dat0-pb7 {
	nvidia,pins = "sdmmc3_dat0_pb7";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3-cd-n-pv2 { /* CD# GPIO */
	nvidia,pins = "sdmmc3_cd_n_pv2";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis SPDIF */
	spdif-out-pk5 {
	nvidia,pins = "spdif_out_pk5";
	nvidia,function = "spdif";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	spdif-in-pk6 {
	nvidia,pins = "spdif_in_pk6";
	nvidia,function = "spdif";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis SPI1 */
	ulpi-clk-py0 {
	nvidia,pins = "ulpi_clk_py0";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi-dir-py1 {
	nvidia,pins = "ulpi_dir_py1";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ulpi-nxt-py2 {
	nvidia,pins = "ulpi_nxt_py2";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi-stp-py3 {
	nvidia,pins = "ulpi_stp_py3";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis SPI2 */
	pg5 {
	nvidia,pins = "pg5";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pg6 {
	nvidia,pins = "pg6";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pg7 {
	nvidia,pins = "pg7";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pi3 {
	nvidia,pins = "pi3";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis UART1 */
	pb1 { /* DCD GPIO */
	nvidia,pins = "pb1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pk7 { /* RI GPIO */
	nvidia,pins = "pk7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart1-txd-pu0 {
	nvidia,pins = "pu0";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart1-rxd-pu1 {
	nvidia,pins = "pu1";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart1-cts-n-pu2 {
	nvidia,pins = "pu2";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart1-rts-n-pu3 {
	nvidia,pins = "pu3";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart3-cts-n-pa1 { /* DSR GPIO */
	nvidia,pins = "uart3_cts_n_pa1";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart3-rts-n-pc0 { /* DTR GPIO */
	nvidia,pins = "uart3_rts_n_pc0";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis UART2 */
	uart2-txd-pc2 {
	nvidia,pins = "uart2_txd_pc2";
	nvidia,function = "irda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart2-rxd-pc3 {
	nvidia,pins = "uart2_rxd_pc3";
	nvidia,function = "irda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart2-cts-n-pj5 {
	nvidia,pins = "uart2_cts_n_pj5";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart2-rts-n-pj6 {
	nvidia,pins = "uart2_rts_n_pj6";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis UART3 */
	uart3-txd-pw6 {
	nvidia,pins = "uart3_txd_pw6";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart3-rxd-pw7 {
	nvidia,pins = "uart3_rxd_pw7";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis UART4 */
	uart4-rxd-pb0 {
	nvidia,pins = "pb0";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart4-txd-pj7 {
	nvidia,pins = "pj7";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis USBH_EN */
	usb-vbus-en1-pn5 {
	nvidia,pins = "usb_vbus_en1_pn5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis USBH_OC# */
	pbb0 {
	nvidia,pins = "pbb0";
	nvidia,function = "vgp6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis USBO1_EN */
	usb-vbus-en0-pn4 {
	nvidia,pins = "usb_vbus_en0_pn4";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis USBO1_OC# */
	pbb4 {
	nvidia,pins = "pbb4";
	nvidia,function = "vgp4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis WAKE1_MICO */
	pex-wake-n-pdd3 {
	nvidia,pins = "pex_wake_n_pdd3";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* CORE_PWR_REQ */
	core-pwr-req {
	nvidia,pins = "core_pwr_req";
	nvidia,function = "pwron";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* CPU_PWR_REQ */
	cpu-pwr-req {
	nvidia,pins = "cpu_pwr_req";
	nvidia,function = "cpu";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* DVFS */
	dvfs-pwm-px0 {
	nvidia,pins = "dvfs_pwm_px0";
	nvidia,function = "cldvfs";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dvfs-clk-px2 {
	nvidia,pins = "dvfs_clk_px2";
	nvidia,function = "cldvfs";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* eMMC */
	sdmmc4-dat0-paa0 {
	nvidia,pins = "sdmmc4_dat0_paa0";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-dat1-paa1 {
	nvidia,pins = "sdmmc4_dat1_paa1";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-dat2-paa2 {
	nvidia,pins = "sdmmc4_dat2_paa2";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-dat3-paa3 {
	nvidia,pins = "sdmmc4_dat3_paa3";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-dat4-paa4 {
	nvidia,pins = "sdmmc4_dat4_paa4";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-dat5-paa5 {
	nvidia,pins = "sdmmc4_dat5_paa5";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-dat6-paa6 {
	nvidia,pins = "sdmmc4_dat6_paa6";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-dat7-paa7 {
	nvidia,pins = "sdmmc4_dat7_paa7";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-clk-pcc4 {
	nvidia,pins = "sdmmc4_clk_pcc4";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-cmd-pt7 {
	nvidia,pins = "sdmmc4_cmd_pt7";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* JTAG_RTCK */
	jtag-rtck {
	nvidia,pins = "jtag_rtck";
	nvidia,function = "rtck";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* LAN_DEV_OFF# */
	ulpi-data5-po6 {
	nvidia,pins = "ulpi_data5_po6";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* LAN_RESET# */
	kb-row10-ps2 {
	nvidia,pins = "kb_row10_ps2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* LAN_WAKE# */
	ulpi-data4-po5 {
	nvidia,pins = "ulpi_data4_po5";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* MCU_INT1# */
	pk2 {
	nvidia,pins = "pk2";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* MCU_INT2# */
	pj2 {
	nvidia,pins = "pj2";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* MCU_INT3# */
	pi5 {
	nvidia,pins = "pi5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* MCU_INT4# */
	pj0 {
	nvidia,pins = "pj0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* MCU_RESET */
	pbb6 {
	nvidia,pins = "pbb6";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* MCU SPI */
	gpio-x4-aud-px4 {
	nvidia,pins = "gpio_x4_aud_px4";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gpio-x5-aud-px5 {
	nvidia,pins = "gpio_x5_aud_px5";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gpio-x6-aud-px6 { /* MCU_CS */
	nvidia,pins = "gpio_x6_aud_px6";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gpio-x7-aud-px7 {
	nvidia,pins = "gpio_x7_aud_px7";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gpio-w2-aud-pw2 { /* MCU_CSEZP */
	nvidia,pins = "gpio_w2_aud_pw2";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* PMIC_CLK_32K */
	clk-32k-in {
	nvidia,pins = "clk_32k_in";
	nvidia,function = "clk";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* PMIC_CPU_OC_INT */
	clk-32k-out-pa0 {
	nvidia,pins = "clk_32k_out_pa0";
	nvidia,function = "soc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* PWR_I2C */
	pwr-i2c-scl-pz6 {
	nvidia,pins = "pwr_i2c_scl_pz6";
	nvidia,function = "i2cpwr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	pwr-i2c-sda-pz7 {
	nvidia,pins = "pwr_i2c_sda_pz7";
	nvidia,function = "i2cpwr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};

	/* PWR_INT_N */
	pwr-int-n {
	nvidia,pins = "pwr_int_n";
	nvidia,function = "pmi";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* RESET_MOCI_CTRL */
	pu4 {
	nvidia,pins = "pu4";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* RESET_OUT_N */
	reset-out-n {
	nvidia,pins = "reset_out_n";
	nvidia,function = "reset_out_n";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* SHIFT_CTRL_DIR_IN */
	kb-row0-pr0 {
	nvidia,pins = "kb_row0_pr0";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row1-pr1 {
	nvidia,pins = "kb_row1_pr1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Configure level-shifter as output for HDA */
	kb-row11-ps3 {
	nvidia,pins = "kb_row11_ps3";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* SHIFT_CTRL_DIR_OUT */
	kb-col5-pq5 {
	nvidia,pins = "kb_col5_pq5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-col6-pq6 {
	nvidia,pins = "kb_col6_pq6";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-col7-pq7 {
	nvidia,pins = "kb_col7_pq7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* SHIFT_CTRL_OE */
	kb-col0-pq0 {
	nvidia,pins = "kb_col0_pq0";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-col1-pq1 {
	nvidia,pins = "kb_col1_pq1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-col2-pq2 {
	nvidia,pins = "kb_col2_pq2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-col4-pq4 {
	nvidia,pins = "kb_col4_pq4";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row2-pr2 {
	nvidia,pins = "kb_row2_pr2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
	pi6 {
	nvidia,pins = "pi6";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* TOUCH_INT */
	gpio-w3-aud-pw3 {
	nvidia,pins = "gpio_w3_aud_pw3";
	nvidia,function = "spi6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	pc7 { /* NC */
	nvidia,pins = "pc7";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pg0 { /* NC */
	nvidia,pins = "pg0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pg1 { /* NC */
	nvidia,pins = "pg1";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pg2 { /* NC */
	nvidia,pins = "pg2";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pg3 { /* NC */
	nvidia,pins = "pg3";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pg4 { /* NC */
	nvidia,pins = "pg4";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph4 { /* NC */
	nvidia,pins = "ph4";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph5 { /* NC */
	nvidia,pins = "ph5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph6 { /* NC */
	nvidia,pins = "ph6";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph7 { /* NC */
	nvidia,pins = "ph7";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pi0 { /* NC */
	nvidia,pins = "pi0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pi1 { /* NC */
	nvidia,pins = "pi1";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pi2 { /* NC */
	nvidia,pins = "pi2";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pi4 { /* NC */
	nvidia,pins = "pi4";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pi7 { /* NC */
	nvidia,pins = "pi7";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pk0 { /* NC */
	nvidia,pins = "pk0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pk1 { /* NC */
	nvidia,pins = "pk1";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pk3 { /* NC */
	nvidia,pins = "pk3";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pk4 { /* NC */
	nvidia,pins = "pk4";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap1-fs-pn0 { /* NC */
	nvidia,pins = "dap1_fs_pn0";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap1-din-pn1 { /* NC */
	nvidia,pins = "dap1_din_pn1";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap1-sclk-pn3 { /* NC */
	nvidia,pins = "dap1_sclk_pn3";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi-data7-po0 { /* NC */
	nvidia,pins = "ulpi_data7_po0";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi-data0-po1 { /* NC */
	nvidia,pins = "ulpi_data0_po1";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi-data1-po2 { /* NC */
	nvidia,pins = "ulpi_data1_po2";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi-data2-po3 { /* NC */
	nvidia,pins = "ulpi_data2_po3";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi-data3-po4 { /* NC */
	nvidia,pins = "ulpi_data3_po4";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi-data6-po7 { /* NC */
	nvidia,pins = "ulpi_data6_po7";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap4-fs-pp4 { /* NC */
	nvidia,pins = "dap4_fs_pp4";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap4-din-pp5 { /* NC */
	nvidia,pins = "dap4_din_pp5";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap4-dout-pp6 { /* NC */
	nvidia,pins = "dap4_dout_pp6";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap4-sclk-pp7 { /* NC */
	nvidia,pins = "dap4_sclk_pp7";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-col3-pq3 { /* NC */
	nvidia,pins = "kb_col3_pq3";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row3-pr3 { /* NC */
	nvidia,pins = "kb_row3_pr3";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row4-pr4 { /* NC */
	nvidia,pins = "kb_row4_pr4";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row5-pr5 { /* NC */
	nvidia,pins = "kb_row5_pr5";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row6-pr6 { /* NC */
	nvidia,pins = "kb_row6_pr6";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row7-pr7 { /* NC */
	nvidia,pins = "kb_row7_pr7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row8-ps0 { /* NC */
	nvidia,pins = "kb_row8_ps0";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row9-ps1 { /* NC */
	nvidia,pins = "kb_row9_ps1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row12-ps4 { /* NC */
	nvidia,pins = "kb_row12_ps4";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row13-ps5 { /* NC */
	nvidia,pins = "kb_row13_ps5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row14-ps6 { /* NC */
	nvidia,pins = "kb_row14_ps6";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row15-ps7 { /* NC */
	nvidia,pins = "kb_row15_ps7";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row16-pt0 { /* NC */
	nvidia,pins = "kb_row16_pt0";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row17-pt1 { /* NC */
	nvidia,pins = "kb_row17_pt1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pu5 { /* NC */
	nvidia,pins = "pu5";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pv0 { /* NC */
	nvidia,pins = "pv0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pv1 { /* NC */
	nvidia,pins = "pv1";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gpio-x1-aud-px1 { /* NC */
	nvidia,pins = "gpio_x1_aud_px1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gpio-x3-aud-px3 { /* NC */
	nvidia,pins = "gpio_x3_aud_px3";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pbb7 { /* NC */
	nvidia,pins = "pbb7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pcc1 { /* NC */
	nvidia,pins = "pcc1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pcc2 { /* NC */
	nvidia,pins = "pcc2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	clk3-req-pee1 { /* NC */
	nvidia,pins = "clk3_req_pee1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap-mclk1-req-pee2 { /* NC */
	nvidia,pins = "dap_mclk1_req_pee2";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	/*
	* Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
	* driver enabled aka not tristated and input driver
	* enabled as well as it features some magic properties
	* even though the external loopback is disabled and the
	* internal loopback used as per
	* SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
	* bits being set to 0xfffd according to the TRM!
	*/
	sdmmc3-clk-lb-out-pee4 { /* NC */
	nvidia,pins = "sdmmc3_clk_lb_out_pee4";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	};
	};

	serial@70006040 {
	compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
	};

	serial@70006200 {
	compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
	};

	serial@70006300 {
	compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
	};

	hdmi_ddc: i2c@7000c400 {
	clock-frequency = <10000>;
	};

	/* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
	i2c@7000d000 {
	status = "okay";
	clock-frequency = <400000>;

	/* SGTL5000 audio codec */
	sgtl5000: codec@a {
	compatible = "fsl,sgtl5000";
	reg = <0x0a>;
	VDDA-supply = <&reg_module_3v3_audio>;
	VDDD-supply = <&reg_1v8_vddio>;
	VDDIO-supply = <&reg_1v8_vddio>;
	clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
	};

	pmic: pmic@40 {
	compatible = "ams,as3722";
	reg = <0x40>;
	interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
	ams,system-power-controller;
	#interrupt-cells = <2>;
	interrupt-controller;
	gpio-controller;
	#gpio-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&as3722_default>;

	as3722_default: pinmux {
	gpio2-7 {
	pins = "gpio2", /* PWR_EN_+V3.3 */
	"gpio7"; /* +V1.6_LPO */
	function = "gpio";
	bias-pull-up;
	};

	gpio0-1-3-4-5-6 {
	pins = "gpio0", "gpio1", "gpio3",
	"gpio4", "gpio5", "gpio6";
	bias-high-impedance;
	};
	};

	regulators {
	vsup-sd2-supply = <&reg_module_3v3>;
	vsup-sd3-supply = <&reg_module_3v3>;
	vsup-sd4-supply = <&reg_module_3v3>;
	vsup-sd5-supply = <&reg_module_3v3>;
	vin-ldo0-supply = <&reg_1v35_vddio_ddr>;
	vin-ldo1-6-supply = <&reg_module_3v3>;
	vin-ldo2-5-7-supply = <&reg_1v8_vddio>;
	vin-ldo3-4-supply = <&reg_module_3v3>;
	vin-ldo9-10-supply = <&reg_module_3v3>;
	vin-ldo11-supply = <&reg_module_3v3>;

	reg_vdd_cpu: sd0 {
	regulator-name = "+VDD_CPU_AP";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1400000>;
	regulator-min-microamp = <3500000>;
	regulator-max-microamp = <3500000>;
	regulator-always-on;
	regulator-boot-on;
	ams,ext-control = <2>;
	};

	sd1 {
	regulator-name = "+VDD_CORE";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1350000>;
	regulator-min-microamp = <2500000>;
	regulator-max-microamp = <4000000>;
	regulator-always-on;
	regulator-boot-on;
	ams,ext-control = <1>;
	};

	reg_1v35_vddio_ddr: sd2 {
	regulator-name =
	"+V1.35_VDDIO_DDR(sd2)";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	};

	sd3 {
	regulator-name =
	"+V1.35_VDDIO_DDR(sd3)";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	};

	reg_1v05_vdd: sd4 {
	regulator-name = "+V1.05";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	};

	reg_1v8_vddio: sd5 {
	regulator-name = "+V1.8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_vdd_gpu: sd6 {
	regulator-name = "+VDD_GPU_AP";
	regulator-min-microvolt = <650000>;
	regulator-max-microvolt = <1200000>;
	regulator-min-microamp = <3500000>;
	regulator-max-microamp = <3500000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_1v05_avdd: ldo0 {
	regulator-name = "+V1.05_AVDD";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	regulator-boot-on;
	regulator-always-on;
	ams,ext-control = <1>;
	};

	vddio_sdmmc1: ldo1 {
	regulator-name = "VDDIO_SDMMC1";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	};

	ldo2 {
	regulator-name = "+V1.2";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo3 {
	regulator-name = "+V1.05_RTC";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-boot-on;
	regulator-always-on;
	ams,enable-tracking;
	};

	/* 1.8V for LVDS, 3.3V for eDP */
	ldo4 {
	regulator-name = "AVDD_LVDS0_PLL";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	/* LDO5 not used */

	vddio_sdmmc3: ldo6 {
	regulator-name = "VDDIO_SDMMC3";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	};

	/* LDO7 not used */

	ldo9 {
	regulator-name = "+V3.3_ETH(ldo9)";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	ldo10 {
	regulator-name = "+V3.3_ETH(ldo10)";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	ldo11 {
	regulator-name = "+V1.8_VPP_FUSE";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	};
	};

	/*
	* TMP451 temperature sensor
	* Note: THERM_N directly connected to AS3722 PMIC THERM
	*/
	temp-sensor@4c {
	compatible = "ti,tmp451";
	reg = <0x4c>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
	#thermal-sensor-cells = <1>;
	vcc-supply = <&reg_module_3v3>;
	};
	};

	/* SPI2: MCU SPI */
	spi@7000d600 {
	status = "okay";
	spi-max-frequency = <25000000>;
	};

	pmc@7000e400 {
	nvidia,invert-interrupt;
	nvidia,suspend-mode = <1>;
	nvidia,cpu-pwr-good-time = <500>;
	nvidia,cpu-pwr-off-time = <300>;
	nvidia,core-pwr-good-time = <641 3845>;
	nvidia,core-pwr-off-time = <61036>;
	nvidia,core-power-req-active-high;
	nvidia,sys-clock-req-active-high;

	/* Set power_off bit in ResetControl register of AS3722 PMIC */
	i2c-thermtrip {
	nvidia,i2c-controller-id = <4>;
	nvidia,bus-addr = <0x40>;
	nvidia,reg-addr = <0x36>;
	nvidia,reg-data = <0x2>;
	};
	};

	sata@70020000 {
	phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
	phy-names = "sata-0";
	avdd-supply = <&reg_1v05_vdd>;
	hvdd-supply = <&reg_module_3v3>;
	vddio-supply = <&reg_1v05_vdd>;
	};

	usb@70090000 {
	/* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
	phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
	<&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
	<&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
	phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
	avddio-pex-supply = <&reg_1v05_vdd>;
	avdd-pll-erefe-supply = <&reg_1v05_avdd>;
	avdd-pll-utmip-supply = <&reg_1v8_vddio>;
	avdd-usb-ss-pll-supply = <&reg_1v05_vdd>;
	avdd-usb-supply = <&reg_module_3v3>;
	dvddio-pex-supply = <&reg_1v05_vdd>;
	hvdd-usb-ss-pll-e-supply = <&reg_module_3v3>;
	hvdd-usb-ss-supply = <&reg_module_3v3>;
	};

	padctl@7009f000 {
	avdd-pll-utmip-supply = <&reg_1v8_vddio>;
	avdd-pll-erefe-supply = <&reg_1v05_avdd>;
	avdd-pex-pll-supply = <&reg_1v05_vdd>;
	hvdd-pex-pll-e-supply = <&reg_module_3v3>;

	pads {
	usb2 {
	status = "okay";

	lanes {
	usb2-0 {
	status = "okay";
	nvidia,function = "xusb";
	};

	usb2-1 {
	status = "okay";
	nvidia,function = "xusb";
	};

	usb2-2 {
	status = "okay";
	nvidia,function = "xusb";
	};
	};
	};

	pcie {
	status = "okay";

	lanes {
	pcie-0 {
	status = "okay";
	nvidia,function = "usb3-ss";
	};

	pcie-1 {
	status = "okay";
	nvidia,function = "usb3-ss";
	};

	pcie-2 {
	status = "okay";
	nvidia,function = "pcie";
	};

	pcie-3 {
	status = "okay";
	nvidia,function = "pcie";
	};

	pcie-4 {
	status = "okay";
	nvidia,function = "pcie";
	};
	};
	};

	sata {
	status = "okay";

	lanes {
	sata-0 {
	status = "okay";
	nvidia,function = "sata";
	};
	};
	};
	};

	ports {
	/* USBO1 */
	usb2-0 {
	status = "okay";
	mode = "otg";
	vbus-supply = <&reg_usbo1_vbus>;
	};

	/* USBH2 */
	usb2-1 {
	status = "okay";
	mode = "host";
	vbus-supply = <&reg_usbh_vbus>;
	};

	/* USBH4 */
	usb2-2 {
	status = "okay";
	mode = "host";
	vbus-supply = <&reg_usbh_vbus>;
	};

	usb3-0 {
	status = "okay";
	nvidia,usb2-companion = <2>;
	vbus-supply = <&reg_usbh_vbus>;
	};

	usb3-1 {
	status = "okay";
	nvidia,usb2-companion = <0>;
	vbus-supply = <&reg_usbo1_vbus>;
	};
	};
	};

	/* eMMC */
	sdhci@700b0600 {
	status = "okay";
	bus-width = <8>;
	non-removable;
	vmmc-supply = <&reg_module_3v3>; /* VCC */
	vqmmc-supply = <&reg_1v8_vddio>; /* VCCQ */
	mmc-ddr-1_8v;
	};

	/* CPU DFLL clock */
	clock@70110000 {
	status = "okay";
	nvidia,i2c-fs-rate = <400000>;
	vdd-cpu-supply = <&reg_vdd_cpu>;
	};

	ahub@70300000 {
	i2s@70301200 {
	status = "okay";
	};
	};

	clk32k_in: osc3 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};

	cpus {
	cpu@0 {
	vdd-cpu-supply = <&reg_vdd_cpu>;
	};
	};

	reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
	compatible = "regulator-fixed";
	regulator-name = "+V1.05_AVDD_HDMI_PLL";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
	vin-supply = <&reg_1v05_vdd>;
	};

	reg_3v3_mxm: regulator-3v3-mxm {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3_MXM";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	};

	reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3_AVDD_HDMI";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&reg_1v05_vdd>;
	};

	reg_module_3v3: regulator-module-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	/* PWR_EN_+V3.3 */
	gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&reg_3v3_mxm>;
	};

	reg_module_3v3_audio: regulator-module-3v3-audio {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3_AUDIO_AVDD_S";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	sound {
	compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
	"nvidia,tegra-audio-sgtl5000";
	nvidia,model = "Toradex Apalis TK1";
	nvidia,audio-routing =
	"Headphone Jack", "HP_OUT",
	"LINE_IN", "Line In Jack",
	"MIC_IN", "Mic Jack";
	nvidia,i2s-controller = <&tegra_i2s2>;
	nvidia,audio-codec = <&sgtl5000>;
	clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
	<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
	- <&tegra_car TEGRA124_CLK_EXTERN1>;
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	clock-names = "pll_a", "pll_a_out0", "mclk";
	+
	+ assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	+
	+ assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
	+ <&tegra_car TEGRA124_CLK_EXTERN1>;
	};

	thermal-zones {
	cpu {
	trips {
	cpu-shutdown-trip {
	temperature = <101000>;
	hysteresis = <0>;
	type = "critical";
	};
	};
	};

	mem {
	trips {
	mem-shutdown-trip {
	temperature = <101000>;
	hysteresis = <0>;
	type = "critical";
	};
	};
	};

	gpu {
	trips {
	gpu-shutdown-trip {
	temperature = <101000>;
	hysteresis = <0>;
	type = "critical";
	};
	};
	};
	};
	};

	&gpio {
	/* I210 Gigabit Ethernet Controller Reset */
	lan-reset-n {
	gpio-hog;
	gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
	output-high;
	line-name = "LAN_RESET_N";
	};

	/* Control MXM3 pin 26 Reset Module Output Carrier Input */
	reset-moci-ctrl {
	gpio-hog;
	gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
	output-high;
	line-name = "RESET_MOCI_CTRL";
	};
	};
	diff --git a/sys/gnu/dts/arm/tegra124-jetson-tk1.dts b/sys/gnu/dts/arm/tegra124-jetson-tk1.dts
	index d5fd642f8b77..1b567e2d5ce0 100644
	--- a/sys/gnu/dts/arm/tegra124-jetson-tk1.dts
	+++ b/sys/gnu/dts/arm/tegra124-jetson-tk1.dts
	@@ -1,2096 +1,2096 @@
	// SPDX-License-Identifier: GPL-2.0
	/dts-v1/;

	#include <dt-bindings/input/input.h>
	#include "tegra124.dtsi"

	#include "tegra124-jetson-tk1-emc.dtsi"

	/ {
	model = "NVIDIA Tegra124 Jetson TK1";
	compatible = "nvidia,jetson-tk1", "nvidia,tegra124";

	aliases {
	rtc0 = "/i2c@7000d000/pmic@40";
	rtc1 = "/rtc@7000e000";

	/* This order keeps the mapping DB9 connector <-> ttyS0 */
	serial0 = &uartd;
	serial1 = &uarta;
	serial2 = &uartb;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@80000000 {
	reg = <0x0 0x80000000 0x0 0x80000000>;
	};

	pcie@1003000 {
	status = "okay";

	avddio-pex-supply = <&vdd_1v05_run>;
	dvddio-pex-supply = <&vdd_1v05_run>;
	avdd-pex-pll-supply = <&vdd_1v05_run>;
	hvdd-pex-supply = <&vdd_3v3_lp0>;
	hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
	vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
	avdd-pll-erefe-supply = <&avdd_1v05_run>;

	/* Mini PCIe */
	pci@1,0 {
	phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
	phy-names = "pcie-0";
	status = "okay";
	};

	/* Gigabit Ethernet */
	pci@2,0 {
	phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
	phy-names = "pcie-0";
	status = "okay";
	};
	};

	host1x@50000000 {
	hdmi@54280000 {
	status = "okay";

	hdmi-supply = <&vdd_5v0_hdmi>;
	pll-supply = <&vdd_hdmi_pll>;
	vdd-supply = <&vdd_3v3_hdmi>;

	nvidia,ddc-i2c-bus = <&hdmi_ddc>;
	nvidia,hpd-gpio =
	<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
	};
	};

	cec@70015000 {
	status = "okay";
	};

	gpu@0,57000000 {
	/*
	* Node left disabled on purpose - the bootloader will enable
	* it after having set the VPR up
	*/
	vdd-supply = <&vdd_gpu>;
	};

	pinmux: pinmux@70000868 {
	pinctrl-names = "boot";
	pinctrl-0 = <&state_boot>;

	state_boot: pinmux {
	clk_32k_out_pa0 {
	nvidia,pins = "clk_32k_out_pa0";
	nvidia,function = "soc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart3_cts_n_pa1 {
	nvidia,pins = "uart3_cts_n_pa1";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap2_fs_pa2 {
	nvidia,pins = "dap2_fs_pa2";
	nvidia,function = "i2s1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap2_sclk_pa3 {
	nvidia,pins = "dap2_sclk_pa3";
	nvidia,function = "i2s1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap2_din_pa4 {
	nvidia,pins = "dap2_din_pa4";
	nvidia,function = "i2s1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap2_dout_pa5 {
	nvidia,pins = "dap2_dout_pa5";
	nvidia,function = "i2s1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_clk_pa6 {
	nvidia,pins = "sdmmc3_clk_pa6";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_cmd_pa7 {
	nvidia,pins = "sdmmc3_cmd_pa7";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pb0 {
	nvidia,pins = "pb0";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pb1 {
	nvidia,pins = "pb1";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_dat3_pb4 {
	nvidia,pins = "sdmmc3_dat3_pb4";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_dat2_pb5 {
	nvidia,pins = "sdmmc3_dat2_pb5";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_dat1_pb6 {
	nvidia,pins = "sdmmc3_dat1_pb6";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_dat0_pb7 {
	nvidia,pins = "sdmmc3_dat0_pb7";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart3_rts_n_pc0 {
	nvidia,pins = "uart3_rts_n_pc0";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart2_txd_pc2 {
	nvidia,pins = "uart2_txd_pc2";
	nvidia,function = "irda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart2_rxd_pc3 {
	nvidia,pins = "uart2_rxd_pc3";
	nvidia,function = "irda";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gen1_i2c_scl_pc4 {
	nvidia,pins = "gen1_i2c_scl_pc4";
	nvidia,function = "i2c1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	gen1_i2c_sda_pc5 {
	nvidia,pins = "gen1_i2c_sda_pc5";
	nvidia,function = "i2c1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	pc7 {
	nvidia,pins = "pc7";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pg0 {
	nvidia,pins = "pg0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pg1 {
	nvidia,pins = "pg1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pg2 {
	nvidia,pins = "pg2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pg3 {
	nvidia,pins = "pg3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pg4 {
	nvidia,pins = "pg4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pg5 {
	nvidia,pins = "pg5";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pg6 {
	nvidia,pins = "pg6";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pg7 {
	nvidia,pins = "pg7";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ph0 {
	nvidia,pins = "ph0";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph1 {
	nvidia,pins = "ph1";
	nvidia,function = "pwm1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph2 {
	nvidia,pins = "ph2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph3 {
	nvidia,pins = "ph3";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph4 {
	nvidia,pins = "ph4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ph5 {
	nvidia,pins = "ph5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph6 {
	nvidia,pins = "ph6";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph7 {
	nvidia,pins = "ph7";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pi0 {
	nvidia,pins = "pi0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pi1 {
	nvidia,pins = "pi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pi2 {
	nvidia,pins = "pi2";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pi3 {
	nvidia,pins = "pi3";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pi4 {
	nvidia,pins = "pi4";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pi5 {
	nvidia,pins = "pi5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pi6 {
	nvidia,pins = "pi6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pi7 {
	nvidia,pins = "pi7";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pj0 {
	nvidia,pins = "pj0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pj2 {
	nvidia,pins = "pj2";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart2_cts_n_pj5 {
	nvidia,pins = "uart2_cts_n_pj5";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart2_rts_n_pj6 {
	nvidia,pins = "uart2_rts_n_pj6";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pj7 {
	nvidia,pins = "pj7";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pk0 {
	nvidia,pins = "pk0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pk1 {
	nvidia,pins = "pk1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pk2 {
	nvidia,pins = "pk2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pk3 {
	nvidia,pins = "pk3";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pk4 {
	nvidia,pins = "pk4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	spdif_out_pk5 {
	nvidia,pins = "spdif_out_pk5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	spdif_in_pk6 {
	nvidia,pins = "spdif_in_pk6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pk7 {
	nvidia,pins = "pk7";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap1_fs_pn0 {
	nvidia,pins = "dap1_fs_pn0";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap1_din_pn1 {
	nvidia,pins = "dap1_din_pn1";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap1_dout_pn2 {
	nvidia,pins = "dap1_dout_pn2";
	nvidia,function = "sata";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap1_sclk_pn3 {
	nvidia,pins = "dap1_sclk_pn3";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	usb_vbus_en0_pn4 {
	nvidia,pins = "usb_vbus_en0_pn4";
	nvidia,function = "usb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	usb_vbus_en1_pn5 {
	nvidia,pins = "usb_vbus_en1_pn5";
	nvidia,function = "usb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	hdmi_int_pn7 {
	nvidia,pins = "hdmi_int_pn7";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
	};
	ulpi_data7_po0 {
	nvidia,pins = "ulpi_data7_po0";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi_data0_po1 {
	nvidia,pins = "ulpi_data0_po1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ulpi_data1_po2 {
	nvidia,pins = "ulpi_data1_po2";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi_data2_po3 {
	nvidia,pins = "ulpi_data2_po3";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi_data3_po4 {
	nvidia,pins = "ulpi_data3_po4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ulpi_data4_po5 {
	nvidia,pins = "ulpi_data4_po5";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi_data5_po6 {
	nvidia,pins = "ulpi_data5_po6";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi_data6_po7 {
	nvidia,pins = "ulpi_data6_po7";
	nvidia,function = "ulpi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap3_fs_pp0 {
	nvidia,pins = "dap3_fs_pp0";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap3_din_pp1 {
	nvidia,pins = "dap3_din_pp1";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap3_dout_pp2 {
	nvidia,pins = "dap3_dout_pp2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap3_sclk_pp3 {
	nvidia,pins = "dap3_sclk_pp3";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap4_fs_pp4 {
	nvidia,pins = "dap4_fs_pp4";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap4_din_pp5 {
	nvidia,pins = "dap4_din_pp5";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap4_dout_pp6 {
	nvidia,pins = "dap4_dout_pp6";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap4_sclk_pp7 {
	nvidia,pins = "dap4_sclk_pp7";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_col0_pq0 {
	nvidia,pins = "kb_col0_pq0";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_col1_pq1 {
	nvidia,pins = "kb_col1_pq1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_col2_pq2 {
	nvidia,pins = "kb_col2_pq2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_col3_pq3 {
	nvidia,pins = "kb_col3_pq3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_col4_pq4 {
	nvidia,pins = "kb_col4_pq4";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_col5_pq5 {
	nvidia,pins = "kb_col5_pq5";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_col6_pq6 {
	nvidia,pins = "kb_col6_pq6";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_col7_pq7 {
	nvidia,pins = "kb_col7_pq7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_row0_pr0 {
	nvidia,pins = "kb_row0_pr0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_row1_pr1 {
	nvidia,pins = "kb_row1_pr1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_row2_pr2 {
	nvidia,pins = "kb_row2_pr2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_row3_pr3 {
	nvidia,pins = "kb_row3_pr3";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_row4_pr4 {
	nvidia,pins = "kb_row4_pr4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row5_pr5 {
	nvidia,pins = "kb_row5_pr5";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_row6_pr6 {
	nvidia,pins = "kb_row6_pr6";
	nvidia,function = "displaya_alt";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row7_pr7 {
	nvidia,pins = "kb_row7_pr7";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row8_ps0 {
	nvidia,pins = "kb_row8_ps0";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_row9_ps1 {
	nvidia,pins = "kb_row9_ps1";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_row10_ps2 {
	nvidia,pins = "kb_row10_ps2";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row11_ps3 {
	nvidia,pins = "kb_row11_ps3";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_row12_ps4 {
	nvidia,pins = "kb_row12_ps4";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_row13_ps5 {
	nvidia,pins = "kb_row13_ps5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_row14_ps6 {
	nvidia,pins = "kb_row14_ps6";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_row15_ps7 {
	nvidia,pins = "kb_row15_ps7";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row16_pt0 {
	nvidia,pins = "kb_row16_pt0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_row17_pt1 {
	nvidia,pins = "kb_row17_pt1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gen2_i2c_scl_pt5 {
	nvidia,pins = "gen2_i2c_scl_pt5";
	nvidia,function = "i2c2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	gen2_i2c_sda_pt6 {
	nvidia,pins = "gen2_i2c_sda_pt6";
	nvidia,function = "i2c2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_cmd_pt7 {
	nvidia,pins = "sdmmc4_cmd_pt7";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pu0 {
	nvidia,pins = "pu0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pu1 {
	nvidia,pins = "pu1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pu2 {
	nvidia,pins = "pu2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pu3 {
	nvidia,pins = "pu3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pu4 {
	nvidia,pins = "pu4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pu5 {
	nvidia,pins = "pu5";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pu6 {
	nvidia,pins = "pu6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pv0 {
	nvidia,pins = "pv0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pv1 {
	nvidia,pins = "pv1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_cd_n_pv2 {
	nvidia,pins = "sdmmc3_cd_n_pv2";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1_wp_n_pv3 {
	nvidia,pins = "sdmmc1_wp_n_pv3";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ddc_scl_pv4 {
	nvidia,pins = "ddc_scl_pv4";
	nvidia,function = "i2c4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
	};
	ddc_sda_pv5 {
	nvidia,pins = "ddc_sda_pv5";
	nvidia,function = "i2c4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
	};
	gpio_w2_aud_pw2 {
	nvidia,pins = "gpio_w2_aud_pw2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gpio_w3_aud_pw3 {
	nvidia,pins = "gpio_w3_aud_pw3";
	nvidia,function = "spi6";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap_mclk1_pw4 {
	nvidia,pins = "dap_mclk1_pw4";
	nvidia,function = "extperiph1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	clk2_out_pw5 {
	nvidia,pins = "clk2_out_pw5";
	nvidia,function = "extperiph2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart3_txd_pw6 {
	nvidia,pins = "uart3_txd_pw6";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart3_rxd_pw7 {
	nvidia,pins = "uart3_rxd_pw7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dvfs_pwm_px0 {
	nvidia,pins = "dvfs_pwm_px0";
	nvidia,function = "cldvfs";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gpio_x1_aud_px1 {
	nvidia,pins = "gpio_x1_aud_px1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dvfs_clk_px2 {
	nvidia,pins = "dvfs_clk_px2";
	nvidia,function = "cldvfs";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gpio_x3_aud_px3 {
	nvidia,pins = "gpio_x3_aud_px3";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gpio_x4_aud_px4 {
	nvidia,pins = "gpio_x4_aud_px4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gpio_x5_aud_px5 {
	nvidia,pins = "gpio_x5_aud_px5";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gpio_x6_aud_px6 {
	nvidia,pins = "gpio_x6_aud_px6";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gpio_x7_aud_px7 {
	nvidia,pins = "gpio_x7_aud_px7";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi_clk_py0 {
	nvidia,pins = "ulpi_clk_py0";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi_dir_py1 {
	nvidia,pins = "ulpi_dir_py1";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ulpi_nxt_py2 {
	nvidia,pins = "ulpi_nxt_py2";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi_stp_py3 {
	nvidia,pins = "ulpi_stp_py3";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_dat3_py4 {
	nvidia,pins = "sdmmc1_dat3_py4";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_dat2_py5 {
	nvidia,pins = "sdmmc1_dat2_py5";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_dat1_py6 {
	nvidia,pins = "sdmmc1_dat1_py6";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_dat0_py7 {
	nvidia,pins = "sdmmc1_dat0_py7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_clk_pz0 {
	nvidia,pins = "sdmmc1_clk_pz0";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_cmd_pz1 {
	nvidia,pins = "sdmmc1_cmd_pz1";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pwr_i2c_scl_pz6 {
	nvidia,pins = "pwr_i2c_scl_pz6";
	nvidia,function = "i2cpwr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	pwr_i2c_sda_pz7 {
	nvidia,pins = "pwr_i2c_sda_pz7";
	nvidia,function = "i2cpwr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_dat0_paa0 {
	nvidia,pins = "sdmmc4_dat0_paa0";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_dat1_paa1 {
	nvidia,pins = "sdmmc4_dat1_paa1";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_dat2_paa2 {
	nvidia,pins = "sdmmc4_dat2_paa2";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_dat3_paa3 {
	nvidia,pins = "sdmmc4_dat3_paa3";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_dat4_paa4 {
	nvidia,pins = "sdmmc4_dat4_paa4";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_dat5_paa5 {
	nvidia,pins = "sdmmc4_dat5_paa5";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_dat6_paa6 {
	nvidia,pins = "sdmmc4_dat6_paa6";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_dat7_paa7 {
	nvidia,pins = "sdmmc4_dat7_paa7";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pbb0 {
	nvidia,pins = "pbb0";
	nvidia,function = "vimclk2_alt";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	cam_i2c_scl_pbb1 {
	nvidia,pins = "cam_i2c_scl_pbb1";
	nvidia,function = "i2c3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	cam_i2c_sda_pbb2 {
	nvidia,pins = "cam_i2c_sda_pbb2";
	nvidia,function = "i2c3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	pbb3 {
	nvidia,pins = "pbb3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pbb4 {
	nvidia,pins = "pbb4";
	nvidia,function = "vgp4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pbb5 {
	nvidia,pins = "pbb5";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pbb6 {
	nvidia,pins = "pbb6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pbb7 {
	nvidia,pins = "pbb7";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	cam_mclk_pcc0 {
	nvidia,pins = "cam_mclk_pcc0";
	nvidia,function = "vi_alt3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pcc1 {
	nvidia,pins = "pcc1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pcc2 {
	nvidia,pins = "pcc2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_clk_pcc4 {
	nvidia,pins = "sdmmc4_clk_pcc4";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	clk2_req_pcc5 {
	nvidia,pins = "clk2_req_pcc5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pex_l0_rst_n_pdd1 {
	nvidia,pins = "pex_l0_rst_n_pdd1";
	nvidia,function = "pe0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pex_l0_clkreq_n_pdd2 {
	nvidia,pins = "pex_l0_clkreq_n_pdd2";
	nvidia,function = "pe0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pex_wake_n_pdd3 {
	nvidia,pins = "pex_wake_n_pdd3";
	nvidia,function = "pe";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pex_l1_rst_n_pdd5 {
	nvidia,pins = "pex_l1_rst_n_pdd5";
	nvidia,function = "pe1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pex_l1_clkreq_n_pdd6 {
	nvidia,pins = "pex_l1_clkreq_n_pdd6";
	nvidia,function = "pe1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	clk3_out_pee0 {
	nvidia,pins = "clk3_out_pee0";
	nvidia,function = "extperiph3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	clk3_req_pee1 {
	nvidia,pins = "clk3_req_pee1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap_mclk1_req_pee2 {
	nvidia,pins = "dap_mclk1_req_pee2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	hdmi_cec_pee3 {
	nvidia,pins = "hdmi_cec_pee3";
	nvidia,function = "cec";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_clk_lb_out_pee4 {
	nvidia,pins = "sdmmc3_clk_lb_out_pee4";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_clk_lb_in_pee5 {
	nvidia,pins = "sdmmc3_clk_lb_in_pee5";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dp_hpd_pff0 {
	nvidia,pins = "dp_hpd_pff0";
	nvidia,function = "dp";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	usb_vbus_en2_pff1 {
	nvidia,pins = "usb_vbus_en2_pff1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pff2 {
	nvidia,pins = "pff2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	core_pwr_req {
	nvidia,pins = "core_pwr_req";
	nvidia,function = "pwron";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	cpu_pwr_req {
	nvidia,pins = "cpu_pwr_req";
	nvidia,function = "cpu";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pwr_int_n {
	nvidia,pins = "pwr_int_n";
	nvidia,function = "pmi";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	reset_out_n {
	nvidia,pins = "reset_out_n";
	nvidia,function = "reset_out_n";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	clk_32k_in {
	nvidia,pins = "clk_32k_in";
	nvidia,function = "clk";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	jtag_rtck {
	nvidia,pins = "jtag_rtck";
	nvidia,function = "rtck";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dsi_b {
	nvidia,pins = "mipi_pad_ctrl_dsi_b";
	nvidia,function = "dsi_b";
	};
	};
	};

	/*
	* First high speed UART, exposed on the expansion connector J3A2
	* Pin 41: BR_UART1_TXD
	* Pin 44: BR_UART1_RXD
	*/
	serial@70006000 {
	compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
	status = "okay";
	};

	/*
	* Second high speed UART, exposed on the expansion connector J3A2
	* Pin 65: UART2_RXD
	* Pin 68: UART2_TXD
	* Pin 71: UART2_CTS_L
	* Pin 74: UART2_RTS_L
	*/
	serial@70006040 {
	compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
	status = "okay";
	};

	/* DB9 serial port */
	serial@70006300 {
	status = "okay";
	};

	/* Expansion GEN1_I2C_, mini-PCIe I2C, on-board components /
	i2c@7000c000 {
	status = "okay";
	clock-frequency = <100000>;

	rt5639: audio-codec@1c {
	compatible = "realtek,rt5639";
	reg = <0x1c>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
	realtek,ldo1-en-gpios =
	<&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
	};

	temperature-sensor@4c {
	compatible = "ti,tmp451";
	reg = <0x4c>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
	};

	eeprom@56 {
	compatible = "atmel,24c02";
	reg = <0x56>;
	pagesize = <8>;
	};
	};

	/* Expansion GEN2_I2C_* */
	i2c@7000c400 {
	status = "okay";
	clock-frequency = <100000>;
	};

	/* Expansion CAM_I2C_* */
	i2c@7000c500 {
	status = "okay";
	clock-frequency = <100000>;
	};

	/* HDMI DDC */
	hdmi_ddc: i2c@7000c700 {
	status = "okay";
	clock-frequency = <100000>;
	};

	/* Expansion PWR_I2C_, on-board components /
	i2c@7000d000 {
	status = "okay";
	clock-frequency = <400000>;

	pmic: pmic@40 {
	compatible = "ams,as3722";
	reg = <0x40>;
	interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;

	ams,system-power-controller;

	#interrupt-cells = <2>;
	interrupt-controller;

	gpio-controller;
	#gpio-cells = <2>;

	pinctrl-names = "default";
	pinctrl-0 = <&as3722_default>;

	as3722_default: pinmux {
	gpio0 {
	pins = "gpio0";
	function = "gpio";
	bias-pull-down;
	};

	gpio1_2_4_7 {
	pins = "gpio1", "gpio2", "gpio4", "gpio7";
	function = "gpio";
	bias-pull-up;
	};

	gpio3_5_6 {
	pins = "gpio3", "gpio5", "gpio6";
	bias-high-impedance;
	};
	};

	regulators {
	vsup-sd2-supply = <&vdd_5v0_sys>;
	vsup-sd3-supply = <&vdd_5v0_sys>;
	vsup-sd4-supply = <&vdd_5v0_sys>;
	vsup-sd5-supply = <&vdd_5v0_sys>;
	vin-ldo0-supply = <&vdd_1v35_lp0>;
	vin-ldo1-6-supply = <&vdd_3v3_run>;
	vin-ldo2-5-7-supply = <&vddio_1v8>;
	vin-ldo3-4-supply = <&vdd_3v3_sys>;
	vin-ldo9-10-supply = <&vdd_5v0_sys>;
	vin-ldo11-supply = <&vdd_3v3_run>;

	vdd_cpu: sd0 {
	regulator-name = "+VDD_CPU_AP";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1400000>;
	regulator-min-microamp = <3500000>;
	regulator-max-microamp = <3500000>;
	regulator-always-on;
	regulator-boot-on;
	ams,ext-control = <2>;
	};

	sd1 {
	regulator-name = "+VDD_CORE";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1350000>;
	regulator-min-microamp = <2500000>;
	regulator-max-microamp = <2500000>;
	regulator-always-on;
	regulator-boot-on;
	ams,ext-control = <1>;
	};

	vdd_1v35_lp0: sd2 {
	regulator-name = "+1.35V_LP0(sd2)";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	};

	sd3 {
	regulator-name = "+1.35V_LP0(sd3)";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_1v05_run: sd4 {
	regulator-name = "+1.05V_RUN";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	};

	vddio_1v8: sd5 {
	regulator-name = "+1.8V_VDDIO";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vdd_gpu: sd6 {
	regulator-name = "+VDD_GPU_AP";
	regulator-min-microvolt = <650000>;
	regulator-max-microvolt = <1200000>;
	regulator-min-microamp = <3500000>;
	regulator-max-microamp = <3500000>;
	regulator-boot-on;
	regulator-always-on;
	};

	avdd_1v05_run: ldo0 {
	regulator-name = "+1.05V_RUN_AVDD";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	regulator-boot-on;
	regulator-always-on;
	ams,ext-control = <1>;
	};

	ldo1 {
	regulator-name = "+1.8V_RUN_CAM";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo2 {
	regulator-name = "+1.2V_GEN_AVDD";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo3 {
	regulator-name = "+1.05V_LP0_VDD_RTC";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-boot-on;
	regulator-always-on;
	ams,enable-tracking;
	};

	ldo4 {
	regulator-name = "+2.8V_RUN_CAM";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	ldo5 {
	regulator-name = "+1.2V_RUN_CAM_FRONT";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	vddio_sdmmc3: ldo6 {
	regulator-name = "+VDDIO_SDMMC3";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	};

	ldo7 {
	regulator-name = "+1.05V_RUN_CAM_REAR";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	};

	ldo9 {
	regulator-name = "+3.3V_RUN_TOUCH";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	ldo10 {
	regulator-name = "+2.8V_RUN_CAM_AF";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	ldo11 {
	regulator-name = "+1.8V_RUN_VPP_FUSE";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	};
	};
	};

	/* Expansion TS_SPI_* */
	spi@7000d400 {
	status = "okay";
	};

	/* Internal SPI */
	spi@7000da00 {
	status = "okay";
	spi-max-frequency = <25000000>;
	spi-flash@0 {
	compatible = "winbond,w25q32dw", "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <20000000>;
	};
	};

	pmc@7000e400 {
	nvidia,invert-interrupt;
	nvidia,suspend-mode = <1>;
	nvidia,cpu-pwr-good-time = <500>;
	nvidia,cpu-pwr-off-time = <300>;
	nvidia,core-pwr-good-time = <641 3845>;
	nvidia,core-pwr-off-time = <61036>;
	nvidia,core-power-req-active-high;
	nvidia,sys-clock-req-active-high;

	i2c-thermtrip {
	nvidia,i2c-controller-id = <4>;
	nvidia,bus-addr = <0x40>;
	nvidia,reg-addr = <0x36>;
	nvidia,reg-data = <0x2>;
	};
	};

	/* Serial ATA */
	sata@70020000 {
	status = "okay";

	phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
	phy-names = "sata-0";

	hvdd-supply = <&vdd_3v3_lp0>;
	vddio-supply = <&vdd_1v05_run>;
	avdd-supply = <&vdd_1v05_run>;

	target-5v-supply = <&vdd_5v0_sata>;
	target-12v-supply = <&vdd_12v0_sata>;
	};

	hda@70030000 {
	status = "okay";
	};

	usb@70090000 {
	phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */
	<&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */
	<&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */
	phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";

	avddio-pex-supply = <&vdd_1v05_run>;
	dvddio-pex-supply = <&vdd_1v05_run>;
	avdd-usb-supply = <&vdd_3v3_lp0>;
	avdd-pll-utmip-supply = <&vddio_1v8>;
	avdd-pll-erefe-supply = <&avdd_1v05_run>;
	avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
	hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
	hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;

	status = "okay";
	};

	padctl@7009f000 {
	status = "okay";

	avdd-pll-utmip-supply = <&vddio_1v8>;
	avdd-pll-erefe-supply = <&avdd_1v05_run>;
	avdd-pex-pll-supply = <&vdd_1v05_run>;
	hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;

	pads {
	usb2 {
	status = "okay";

	lanes {
	usb2-0 {
	nvidia,function = "snps";
	status = "okay";
	};

	usb2-1 {
	nvidia,function = "xusb";
	status = "okay";
	};

	usb2-2 {
	nvidia,function = "xusb";
	status = "okay";
	};
	};
	};

	pcie {
	status = "okay";

	lanes {
	pcie-0 {
	nvidia,function = "usb3-ss";
	status = "okay";
	};

	pcie-2 {
	nvidia,function = "pcie";
	status = "okay";
	};

	pcie-4 {
	nvidia,function = "pcie";
	status = "okay";
	};
	};
	};

	sata {
	status = "okay";

	lanes {
	sata-0 {
	nvidia,function = "sata";
	status = "okay";
	};
	};
	};
	};

	ports {
	- /* Micro A/B */
	- usb2-0 {
	- status = "okay";
	- mode = "otg";
	- };
	-
	/* Mini PCIe */
	usb2-1 {
	status = "okay";
	mode = "host";
	};

	/* USB3 */
	usb2-2 {
	status = "okay";
	mode = "host";

	vbus-supply = <&vdd_usb3_vbus>;
	};

	usb3-0 {
	nvidia,usb2-companion = <2>;
	status = "okay";
	};
	};
	};

	/* SD card */
	sdhci@700b0400 {
	status = "okay";
	cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
	power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
	wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
	bus-width = <4>;
	vqmmc-supply = <&vddio_sdmmc3>;
	};

	/* eMMC */
	sdhci@700b0600 {
	status = "okay";
	bus-width = <8>;
	non-removable;
	};

	/* CPU DFLL clock */
	clock@70110000 {
	status = "okay";
	vdd-cpu-supply = <&vdd_cpu>;
	nvidia,i2c-fs-rate = <400000>;
	};

	ahub@70300000 {
	i2s@70301100 {
	status = "okay";
	};
	};

	usb@7d000000 {
	compatible = "nvidia,tegra124-udc";
	status = "okay";
	dr_mode = "peripheral";
	};

	usb-phy@7d000000 {
	status = "okay";
	};

	/* mini-PCIe USB */
	usb@7d004000 {
	status = "okay";
	};

	usb-phy@7d004000 {
	status = "okay";
	};

	/* USB A connector */
	usb@7d008000 {
	status = "okay";
	};

	usb-phy@7d008000 {
	status = "okay";
	vbus-supply = <&vdd_usb3_vbus>;
	};

	clocks {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	clk32k_in: clock@0 {
	compatible = "fixed-clock";
	reg = <0>;
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	};

	cpus {
	cpu@0 {
	vdd-cpu-supply = <&vdd_cpu>;
	};
	};

	gpio-keys {
	compatible = "gpio-keys";

	power {
	label = "Power";
	gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
	linux,code = <KEY_POWER>;
	debounce-interval = <10>;
	wakeup-source;
	};
	};

	regulators {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	vdd_mux: regulator@0 {
	compatible = "regulator-fixed";
	reg = <0>;
	regulator-name = "+VDD_MUX";
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_5v0_sys: regulator@1 {
	compatible = "regulator-fixed";
	reg = <1>;
	regulator-name = "+5V_SYS";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vdd_mux>;
	};

	vdd_3v3_sys: regulator@2 {
	compatible = "regulator-fixed";
	reg = <2>;
	regulator-name = "+3.3V_SYS";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vdd_mux>;
	};

	vdd_3v3_run: regulator@3 {
	compatible = "regulator-fixed";
	reg = <3>;
	regulator-name = "+3.3V_RUN";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_3v3_sys>;
	};

	vdd_3v3_hdmi: regulator@4 {
	compatible = "regulator-fixed";
	reg = <4>;
	regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vdd_3v3_run>;
	};

	vdd_usb1_vbus: regulator@7 {
	compatible = "regulator-fixed";
	reg = <7>;
	regulator-name = "+USB0_VBUS_SW";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	gpio-open-drain;
	vin-supply = <&vdd_5v0_sys>;
	};

	vdd_usb3_vbus: regulator@8 {
	compatible = "regulator-fixed";
	reg = <8>;
	regulator-name = "+5V_USB_HS";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	gpio-open-drain;
	vin-supply = <&vdd_5v0_sys>;
	};

	vdd_3v3_lp0: regulator@10 {
	compatible = "regulator-fixed";
	reg = <10>;
	regulator-name = "+3.3V_LP0";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_3v3_sys>;
	};

	vdd_hdmi_pll: regulator@11 {
	compatible = "regulator-fixed";
	reg = <11>;
	regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
	vin-supply = <&vdd_1v05_run>;
	};

	vdd_5v0_hdmi: regulator@12 {
	compatible = "regulator-fixed";
	reg = <12>;
	regulator-name = "+5V_HDMI_CON";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_5v0_sys>;
	};

	/* Molex power connector */
	vdd_5v0_sata: regulator@13 {
	compatible = "regulator-fixed";
	reg = <13>;
	regulator-name = "+5V_SATA";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_5v0_sys>;
	};

	vdd_12v0_sata: regulator@14 {
	compatible = "regulator-fixed";
	reg = <14>;
	regulator-name = "+12V_SATA";
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_mux>;
	};
	};

	sound {
	compatible = "nvidia,tegra-audio-rt5640-jetson-tk1",
	"nvidia,tegra-audio-rt5640";
	nvidia,model = "NVIDIA Tegra Jetson TK1";

	nvidia,audio-routing =
	"Headphones", "HPOR",
	"Headphones", "HPOL",
	"Mic Jack", "MICBIAS1",
	"IN2P", "Mic Jack";

	nvidia,i2s-controller = <&tegra_i2s1>;
	nvidia,audio-codec = <&rt5639>;

	nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>;

	clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
	<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
	- <&tegra_car TEGRA124_CLK_EXTERN1>;
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	clock-names = "pll_a", "pll_a_out0", "mclk";
	+
	+ assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	+
	+ assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
	+ <&tegra_car TEGRA124_CLK_EXTERN1>;
	};

	thermal-zones {
	cpu {
	trips {
	cpu-shutdown-trip {
	temperature = <101000>;
	hysteresis = <0>;
	type = "critical";
	};
	};
	};

	mem {
	trips {
	mem-shutdown-trip {
	temperature = <101000>;
	hysteresis = <0>;
	type = "critical";
	};
	};
	};

	gpu {
	trips {
	gpu-shutdown-trip {
	temperature = <101000>;
	hysteresis = <0>;
	type = "critical";
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/tegra124-nyan.dtsi b/sys/gnu/dts/arm/tegra124-nyan.dtsi
	index 3b10f475037f..9b1af50cd4b8 100644
	--- a/sys/gnu/dts/arm/tegra124-nyan.dtsi
	+++ b/sys/gnu/dts/arm/tegra124-nyan.dtsi
	@@ -1,806 +1,812 @@
	// SPDX-License-Identifier: GPL-2.0
	#include <dt-bindings/input/input.h>
	#include "tegra124.dtsi"

	/ {
	aliases {
	rtc0 = "/i2c@7000d000/pmic@40";
	rtc1 = "/rtc@7000e000";
	serial0 = &uarta;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	/*
	* Note that recent version of the device tree compiler (starting with
	* version 1.4.2) warn about this node containing a reg property, but
	* missing a unit-address. However, the bootloader on these Chromebook
	* devices relies on the full name of this node to be exactly /memory.
	* Adding the unit-address causes the bootloader to create a /memory
	* node and write the memory bank configuration to that node, which in
	* turn leads the kernel to believe that the device has 2 GiB of
	* memory instead of the amount detected by the bootloader.
	*
	* The name of this node is effectively ABI and must not be changed.
	*/
	memory {
	device_type = "memory";
	reg = <0x0 0x80000000 0x0 0x80000000>;
	};

	/delete-node/ memory@80000000;

	host1x@50000000 {
	hdmi@54280000 {
	status = "okay";

	vdd-supply = <&vdd_3v3_hdmi>;
	pll-supply = <&vdd_hdmi_pll>;
	hdmi-supply = <&vdd_5v0_hdmi>;

	nvidia,ddc-i2c-bus = <&hdmi_ddc>;
	nvidia,hpd-gpio =
	<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
	};

	sor@54540000 {
	status = "okay";

	nvidia,dpaux = <&dpaux>;
	nvidia,panel = <&panel>;
	};

	dpaux@545c0000 {
	vdd-supply = <&vdd_3v3_panel>;
	status = "okay";
	};
	};

	gpu@0,57000000 {
	status = "okay";

	vdd-supply = <&vdd_gpu>;
	};

	serial@70006000 {
	/* Debug connector on the bottom of the board near SD card. */
	status = "okay";
	};

	pwm@7000a000 {
	status = "okay";
	};

	i2c@7000c000 {
	status = "okay";
	clock-frequency = <100000>;

	acodec: audio-codec@10 {
	compatible = "maxim,max98090";
	reg = <0x10>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
	};

	temperature-sensor@4c {
	compatible = "ti,tmp451";
	reg = <0x4c>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;

	#thermal-sensor-cells = <1>;
	};
	};

	i2c@7000c400 {
	status = "okay";
	clock-frequency = <100000>;

	trackpad@15 {
	compatible = "elan,ekth3000";
	reg = <0x15>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
	wakeup-source;
	};
	};

	i2c@7000c500 {
	status = "okay";
	clock-frequency = <400000>;

	tpm@20 {
	compatible = "infineon,slb9645tt";
	reg = <0x20>;
	};
	};

	hdmi_ddc: i2c@7000c700 {
	status = "okay";
	clock-frequency = <100000>;
	};

	i2c@7000d000 {
	status = "okay";
	clock-frequency = <400000>;

	pmic: pmic@40 {
	compatible = "ams,as3722";
	reg = <0x40>;
	interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;

	ams,system-power-controller;

	#interrupt-cells = <2>;
	interrupt-controller;

	gpio-controller;
	#gpio-cells = <2>;

	pinctrl-names = "default";
	pinctrl-0 = <&as3722_default>;

	as3722_default: pinmux {
	gpio0 {
	pins = "gpio0";
	function = "gpio";
	bias-pull-down;
	};

	gpio1 {
	pins = "gpio1";
	function = "gpio";
	bias-pull-up;
	};

	gpio2_4_7 {
	pins = "gpio2", "gpio4", "gpio7";
	function = "gpio";
	bias-pull-up;
	};

	gpio3_6 {
	pins = "gpio3", "gpio6";
	bias-high-impedance;
	};

	gpio5 {
	pins = "gpio5";
	function = "clk32k-out";
	bias-pull-down;
	};
	};

	regulators {
	vsup-sd2-supply = <&vdd_5v0_sys>;
	vsup-sd3-supply = <&vdd_5v0_sys>;
	vsup-sd4-supply = <&vdd_5v0_sys>;
	vsup-sd5-supply = <&vdd_5v0_sys>;
	vin-ldo0-supply = <&vdd_1v35_lp0>;
	vin-ldo1-6-supply = <&vdd_3v3_run>;
	vin-ldo2-5-7-supply = <&vddio_1v8>;
	vin-ldo3-4-supply = <&vdd_3v3_sys>;
	vin-ldo9-10-supply = <&vdd_5v0_sys>;
	vin-ldo11-supply = <&vdd_3v3_run>;

	vdd_cpu: sd0 {
	regulator-name = "+VDD_CPU_AP";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1350000>;
	regulator-min-microamp = <3500000>;
	regulator-max-microamp = <3500000>;
	regulator-always-on;
	regulator-boot-on;
	ams,ext-control = <2>;
	};

	sd1 {
	regulator-name = "+VDD_CORE";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1350000>;
	regulator-min-microamp = <2500000>;
	regulator-max-microamp = <4000000>;
	regulator-always-on;
	regulator-boot-on;
	ams,ext-control = <1>;
	};

	vdd_1v35_lp0: sd2 {
	regulator-name = "+1.35V_LP0(sd2)";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	};

	sd3 {
	regulator-name = "+1.35V_LP0(sd3)";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_1v05_run: sd4 {
	regulator-name = "+1.05V_RUN";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	};

	vddio_1v8: sd5 {
	regulator-name = "+1.8V_VDDIO";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	vdd_gpu: sd6 {
	regulator-name = "+VDD_GPU_AP";
	regulator-min-microvolt = <650000>;
	regulator-max-microvolt = <1200000>;
	regulator-min-microamp = <3500000>;
	regulator-max-microamp = <3500000>;
	regulator-boot-on;
	regulator-always-on;
	};

	avdd_1v05_run: ldo0 {
	regulator-name = "+1.05V_RUN_AVDD";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	regulator-boot-on;
	regulator-always-on;
	ams,ext-control = <1>;
	};

	ldo1 {
	regulator-name = "+1.8V_RUN_CAM";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo2 {
	regulator-name = "+1.2V_GEN_AVDD";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo3 {
	regulator-name = "+1.00V_LP0_VDD_RTC";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-boot-on;
	regulator-always-on;
	ams,enable-tracking;
	};

	vdd_run_cam: ldo4 {
	regulator-name = "+3.3V_RUN_CAM";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	ldo5 {
	regulator-name = "+1.2V_RUN_CAM_FRONT";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	vddio_sdmmc3: ldo6 {
	regulator-name = "+VDDIO_SDMMC3";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	};

	ldo7 {
	regulator-name = "+1.05V_RUN_CAM_REAR";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	};

	ldo9 {
	regulator-name = "+2.8V_RUN_TOUCH";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	ldo10 {
	regulator-name = "+2.8V_RUN_CAM_AF";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	ldo11 {
	regulator-name = "+1.8V_RUN_VPP_FUSE";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	};
	};
	};

	spi@7000d400 {
	status = "okay";

	cros_ec: cros-ec@0 {
	compatible = "google,cros-ec-spi";
	spi-max-frequency = <3000000>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
	reg = <0>;

	google,cros-ec-spi-msg-delay = <2000>;

	i2c-tunnel {
	compatible = "google,cros-ec-i2c-tunnel";
	#address-cells = <1>;
	#size-cells = <0>;

	google,remote-bus = <0>;

	charger: bq24735@9 {
	compatible = "ti,bq24735";
	reg = <0x9>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(J, 0)
	IRQ_TYPE_EDGE_BOTH>;
	ti,ac-detect-gpios = <&gpio
	TEGRA_GPIO(J, 0)
	GPIO_ACTIVE_HIGH>;
	ti,external-control;
	};

	battery: sbs-battery@b {
	compatible = "sbs,sbs-battery";
	reg = <0xb>;
	sbs,i2c-retry-count = <2>;
	sbs,poll-retry-count = <10>;
	power-supplies = <&charger>;
	};
	};
	};
	};

	spi@7000da00 {
	status = "okay";
	spi-max-frequency = <25000000>;

	flash@0 {
	compatible = "winbond,w25q32dw", "jedec,spi-nor";
	spi-max-frequency = <25000000>;
	reg = <0>;
	};
	};

	pmc@7000e400 {
	nvidia,invert-interrupt;
	nvidia,suspend-mode = <0>;
	nvidia,cpu-pwr-good-time = <500>;
	nvidia,cpu-pwr-off-time = <300>;
	nvidia,core-pwr-good-time = <641 3845>;
	nvidia,core-pwr-off-time = <61036>;
	nvidia,core-power-req-active-high;
	nvidia,sys-clock-req-active-high;
	};

	hda@70030000 {
	status = "okay";
	};

	usb@70090000 {
	phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
	<&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
	<&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
	phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";

	avddio-pex-supply = <&vdd_1v05_run>;
	dvddio-pex-supply = <&vdd_1v05_run>;
	avdd-usb-supply = <&vdd_3v3_lp0>;
	avdd-pll-utmip-supply = <&vddio_1v8>;
	avdd-pll-erefe-supply = <&avdd_1v05_run>;
	avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
	hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
	hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;

	status = "okay";
	};

	padctl@7009f000 {
	status = "okay";

	avdd-pll-utmip-supply = <&vddio_1v8>;
	avdd-pll-erefe-supply = <&avdd_1v05_run>;
	avdd-pex-pll-supply = <&vdd_1v05_run>;
	hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;

	pads {
	usb2 {
	status = "okay";

	lanes {
	usb2-0 {
	nvidia,function = "xusb";
	status = "okay";
	};

	usb2-1 {
	nvidia,function = "xusb";
	status = "okay";
	};

	usb2-2 {
	nvidia,function = "xusb";
	status = "okay";
	};
	};
	};

	pcie {
	status = "okay";

	lanes {
	pcie-0 {
	nvidia,function = "usb3-ss";
	status = "okay";
	};

	pcie-1 {
	nvidia,function = "usb3-ss";
	status = "okay";
	};
	};
	};
	};

	ports {
	usb2-0 {
	vbus-supply = <&vdd_usb1_vbus>;
	status = "okay";
	mode = "otg";
	};

	usb2-1 {
	vbus-supply = <&vdd_run_cam>;
	status = "okay";
	mode = "host";
	};

	usb2-2 {
	vbus-supply = <&vdd_usb3_vbus>;
	status = "okay";
	mode = "host";
	};

	usb3-0 {
	nvidia,usb2-companion = <0>;
	status = "okay";
	};

	usb3-1 {
	nvidia,usb2-companion = <1>;
	status = "okay";
	};
	};
	};

	sdhci0_pwrseq: sdhci0_pwrseq {
	compatible = "mmc-pwrseq-simple";

	reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
	};

	sdhci@700b0000 { /* WiFi/BT on this bus */
	status = "okay";
	bus-width = <4>;
	no-1-8-v;
	non-removable;
	mmc-pwrseq = <&sdhci0_pwrseq>;
	vmmc-supply = <&vdd_3v3_lp0>;
	vqmmc-supply = <&vddio_1v8>;
	keep-power-in-suspend;
	};

	sdhci@700b0400 { /* SD Card on this bus */
	status = "okay";
	cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
	power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
	bus-width = <4>;
	no-1-8-v;
	vqmmc-supply = <&vddio_sdmmc3>;
	};

	sdhci@700b0600 { /* eMMC on this bus */
	status = "okay";
	bus-width = <8>;
	no-1-8-v;
	non-removable;
	};

	/* CPU DFLL clock */
	clock@70110000 {
	status = "disabled";
	vdd-cpu-supply = <&vdd_cpu>;
	nvidia,i2c-fs-rate = <400000>;
	};

	ahub@70300000 {
	i2s@70301100 {
	status = "okay";
	};
	};

	backlight: backlight {
	compatible = "pwm-backlight";

	enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
	power-supply = <&vdd_led>;
	pwms = <&pwm 1 1000000>;

	default-brightness-level = <224>;
	brightness-levels =
	< 0 1 2 3 4 5 6 7
	8 9 10 11 12 13 14 15
	16 17 18 19 20 21 22 23
	24 25 26 27 28 29 30 31
	32 33 34 35 36 37 38 39
	40 41 42 43 44 45 46 47
	48 49 50 51 52 53 54 55
	56 57 58 59 60 61 62 63
	64 65 66 67 68 69 70 71
	72 73 74 75 76 77 78 79
	80 81 82 83 84 85 86 87
	88 89 90 91 92 93 94 95
	96 97 98 99 100 101 102 103
	104 105 106 107 108 109 110 111
	112 113 114 115 116 117 118 119
	120 121 122 123 124 125 126 127
	128 129 130 131 132 133 134 135
	136 137 138 139 140 141 142 143
	144 145 146 147 148 149 150 151
	152 153 154 155 156 157 158 159
	160 161 162 163 164 165 166 167
	168 169 170 171 172 173 174 175
	176 177 178 179 180 181 182 183
	184 185 186 187 188 189 190 191
	192 193 194 195 196 197 198 199
	200 201 202 203 204 205 206 207
	208 209 210 211 212 213 214 215
	216 217 218 219 220 221 222 223
	224 225 226 227 228 229 230 231
	232 233 234 235 236 237 238 239
	240 241 242 243 244 245 246 247
	248 249 250 251 252 253 254 255
	256>;
	};

	clocks {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	clk32k_in: clock@0 {
	compatible = "fixed-clock";
	reg = <0>;
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	};

	cpus {
	cpu@0 {
	vdd-cpu-supply = <&vdd_cpu>;
	};
	};

	gpio-keys {
	compatible = "gpio-keys";

	lid {
	label = "Lid";
	gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
	linux,input-type = <5>;
	linux,code = <KEY_RESERVED>;
	debounce-interval = <1>;
	wakeup-source;
	};

	power {
	label = "Power";
	gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
	linux,code = <KEY_POWER>;
	debounce-interval = <30>;
	wakeup-source;
	};
	};

	regulators {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	vdd_mux: regulator@0 {
	compatible = "regulator-fixed";
	reg = <0>;
	regulator-name = "+VDD_MUX";
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_5v0_sys: regulator@1 {
	compatible = "regulator-fixed";
	reg = <1>;
	regulator-name = "+5V_SYS";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vdd_mux>;
	};

	vdd_3v3_sys: regulator@2 {
	compatible = "regulator-fixed";
	reg = <2>;
	regulator-name = "+3.3V_SYS";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vdd_mux>;
	};

	vdd_3v3_run: regulator@3 {
	compatible = "regulator-fixed";
	reg = <3>;
	regulator-name = "+3.3V_RUN";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_3v3_sys>;
	};

	vdd_3v3_hdmi: regulator@4 {
	compatible = "regulator-fixed";
	reg = <4>;
	regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vdd_3v3_run>;
	};

	vdd_led: regulator@5 {
	compatible = "regulator-fixed";
	reg = <5>;
	regulator-name = "+VDD_LED";
	gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_mux>;
	};

	vdd_5v0_ts: regulator@6 {
	compatible = "regulator-fixed";
	reg = <6>;
	regulator-name = "+5V_VDD_TS_SW";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-boot-on;
	gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_5v0_sys>;
	};

	vdd_usb1_vbus: regulator@7 {
	compatible = "regulator-fixed";
	reg = <7>;
	regulator-name = "+5V_USB_HS";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	gpio-open-drain;
	vin-supply = <&vdd_5v0_sys>;
	};

	vdd_usb3_vbus: regulator@8 {
	compatible = "regulator-fixed";
	reg = <8>;
	regulator-name = "+5V_USB_SS";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	gpio-open-drain;
	vin-supply = <&vdd_5v0_sys>;
	};

	vdd_3v3_panel: regulator@9 {
	compatible = "regulator-fixed";
	reg = <9>;
	regulator-name = "+3.3V_PANEL";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_3v3_run>;
	};

	vdd_3v3_lp0: regulator@10 {
	compatible = "regulator-fixed";
	reg = <10>;
	regulator-name = "+3.3V_LP0";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	/*
	* TODO: find a way to wire this up with the USB EHCI
	* controllers so that it can be enabled on demand.
	*/
	regulator-always-on;
	gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_3v3_sys>;
	};

	vdd_hdmi_pll: regulator@11 {
	compatible = "regulator-fixed";
	reg = <11>;
	regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
	vin-supply = <&vdd_1v05_run>;
	};

	vdd_5v0_hdmi: regulator@12 {
	compatible = "regulator-fixed";
	reg = <12>;
	regulator-name = "+5V_HDMI_CON";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_5v0_sys>;
	};
	};

	sound {
	nvidia,audio-routing =
	"Headphones", "HPR",
	"Headphones", "HPL",
	"Speakers", "SPKR",
	"Speakers", "SPKL",
	"Mic Jack", "MICBIAS",
	"DMICL", "Int Mic",
	"DMICR", "Int Mic",
	"IN34", "Mic Jack";

	nvidia,i2s-controller = <&tegra_i2s1>;
	nvidia,audio-codec = <&acodec>;

	clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
	<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
	- <&tegra_car TEGRA124_CLK_EXTERN1>;
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	clock-names = "pll_a", "pll_a_out0", "mclk";

	+ assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	+
	+ assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
	+ <&tegra_car TEGRA124_CLK_EXTERN1>;
	+
	nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
	nvidia,mic-det-gpios =
	<&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
	};

	gpio-restart {
	compatible = "gpio-restart";
	gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
	priority = <200>;
	};
	};

	#include "cros-ec-keyboard.dtsi"
	diff --git a/sys/gnu/dts/arm/tegra124-venice2.dts b/sys/gnu/dts/arm/tegra124-venice2.dts
	index 7309393bfced..8c2ee6e7d6f1 100644
	--- a/sys/gnu/dts/arm/tegra124-venice2.dts
	+++ b/sys/gnu/dts/arm/tegra124-venice2.dts
	@@ -1,1274 +1,1280 @@
	// SPDX-License-Identifier: GPL-2.0
	/dts-v1/;

	#include <dt-bindings/input/input.h>
	#include "tegra124.dtsi"

	/ {
	model = "NVIDIA Tegra124 Venice2";
	compatible = "nvidia,venice2", "nvidia,tegra124";

	aliases {
	rtc0 = "/i2c@7000d000/pmic@40";
	rtc1 = "/rtc@7000e000";
	serial0 = &uarta;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@80000000 {
	reg = <0x0 0x80000000 0x0 0x80000000>;
	};

	host1x@50000000 {
	hdmi@54280000 {
	status = "okay";

	vdd-supply = <&vdd_3v3_hdmi>;
	pll-supply = <&vdd_hdmi_pll>;
	hdmi-supply = <&vdd_5v0_hdmi>;

	nvidia,ddc-i2c-bus = <&hdmi_ddc>;
	nvidia,hpd-gpio =
	<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
	};

	sor@54540000 {
	status = "okay";

	avdd-io-hdmi-dp-supply = <&vdd_1v05_run>;
	vdd-hdmi-dp-pll-supply = <&vdd_3v3_run>;

	nvidia,dpaux = <&dpaux>;
	nvidia,panel = <&panel>;
	};

	dpaux@545c0000 {
	vdd-supply = <&vdd_3v3_panel>;
	status = "okay";
	};
	};

	gpu@0,57000000 {
	/*
	* Node left disabled on purpose - the bootloader will enable
	* it after having set the VPR up
	*/
	vdd-supply = <&vdd_gpu>;
	};

	pinmux: pinmux@70000868 {
	pinctrl-names = "boot";
	pinctrl-0 = <&pinmux_boot>;

	pinmux_boot: common {
	dap_mclk1_pw4 {
	nvidia,pins = "dap_mclk1_pw4";
	nvidia,function = "extperiph1";
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	dap1_din_pn1 {
	nvidia,pins = "dap1_din_pn1";
	nvidia,function = "i2s0";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	};
	dap1_dout_pn2 {
	nvidia,pins = "dap1_dout_pn2",
	"dap1_fs_pn0",
	"dap1_sclk_pn3";
	nvidia,function = "i2s0";
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	};
	dap2_din_pa4 {
	nvidia,pins = "dap2_din_pa4";
	nvidia,function = "i2s1";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	dap2_dout_pa5 {
	nvidia,pins = "dap2_dout_pa5",
	"dap2_fs_pa2",
	"dap2_sclk_pa3";
	nvidia,function = "i2s1";
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	dvfs_pwm_px0 {
	nvidia,pins = "dvfs_pwm_px0",
	"dvfs_clk_px2";
	nvidia,function = "cldvfs";
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	ulpi_clk_py0 {
	nvidia,pins = "ulpi_clk_py0",
	"ulpi_nxt_py2",
	"ulpi_stp_py3";
	nvidia,function = "spi1";
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	ulpi_dir_py1 {
	nvidia,pins = "ulpi_dir_py1";
	nvidia,function = "spi1";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	cam_i2c_scl_pbb1 {
	nvidia,pins = "cam_i2c_scl_pbb1",
	"cam_i2c_sda_pbb2";
	nvidia,function = "i2c3";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,lock = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	gen2_i2c_scl_pt5 {
	nvidia,pins = "gen2_i2c_scl_pt5",
	"gen2_i2c_sda_pt6";
	nvidia,function = "i2c2";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,lock = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	pg4 {
	nvidia,pins = "pg4",
	"pg5",
	"pg6",
	"pi3";
	nvidia,function = "spi4";
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	pg7 {
	nvidia,pins = "pg7";
	nvidia,function = "spi4";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	ph1 {
	nvidia,pins = "ph1";
	nvidia,function = "pwm1";
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	pk0 {
	nvidia,pins = "pk0",
	"kb_row15_ps7",
	"clk_32k_out_pa0";
	nvidia,function = "soc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1_clk_pz0 {
	nvidia,pins = "sdmmc1_clk_pz0";
	nvidia,function = "sdmmc1";
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_cmd_pz1 {
	nvidia,pins = "sdmmc1_cmd_pz1",
	"sdmmc1_dat0_py7",
	"sdmmc1_dat1_py6",
	"sdmmc1_dat2_py5",
	"sdmmc1_dat3_py4";
	nvidia,function = "sdmmc1";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_clk_pa6 {
	nvidia,pins = "sdmmc3_clk_pa6";
	nvidia,function = "sdmmc3";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_cmd_pa7 {
	nvidia,pins = "sdmmc3_cmd_pa7",
	"sdmmc3_dat0_pb7",
	"sdmmc3_dat1_pb6",
	"sdmmc3_dat2_pb5",
	"sdmmc3_dat3_pb4",
	"sdmmc3_clk_lb_out_pee4",
	"sdmmc3_clk_lb_in_pee5";
	nvidia,function = "sdmmc3";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	sdmmc4_clk_pcc4 {
	nvidia,pins = "sdmmc4_clk_pcc4";
	nvidia,function = "sdmmc4";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	sdmmc4_cmd_pt7 {
	nvidia,pins = "sdmmc4_cmd_pt7",
	"sdmmc4_dat0_paa0",
	"sdmmc4_dat1_paa1",
	"sdmmc4_dat2_paa2",
	"sdmmc4_dat3_paa3",
	"sdmmc4_dat4_paa4",
	"sdmmc4_dat5_paa5",
	"sdmmc4_dat6_paa6",
	"sdmmc4_dat7_paa7";
	nvidia,function = "sdmmc4";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	pwr_i2c_scl_pz6 {
	nvidia,pins = "pwr_i2c_scl_pz6",
	"pwr_i2c_sda_pz7";
	nvidia,function = "i2cpwr";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,lock = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	jtag_rtck {
	nvidia,pins = "jtag_rtck";
	nvidia,function = "rtck";
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	clk_32k_in {
	nvidia,pins = "clk_32k_in";
	nvidia,function = "clk";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	core_pwr_req {
	nvidia,pins = "core_pwr_req";
	nvidia,function = "pwron";
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	cpu_pwr_req {
	nvidia,pins = "cpu_pwr_req";
	nvidia,function = "cpu";
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	pwr_int_n {
	nvidia,pins = "pwr_int_n";
	nvidia,function = "pmi";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	reset_out_n {
	nvidia,pins = "reset_out_n";
	nvidia,function = "reset_out_n";
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	clk3_out_pee0 {
	nvidia,pins = "clk3_out_pee0";
	nvidia,function = "extperiph3";
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	dap4_din_pp5 {
	nvidia,pins = "dap4_din_pp5";
	nvidia,function = "i2s3";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	};
	dap4_dout_pp6 {
	nvidia,pins = "dap4_dout_pp6",
	"dap4_fs_pp4",
	"dap4_sclk_pp7";
	nvidia,function = "i2s3";
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	};
	gen1_i2c_sda_pc5 {
	nvidia,pins = "gen1_i2c_sda_pc5",
	"gen1_i2c_scl_pc4";
	nvidia,function = "i2c1";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,lock = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	uart2_cts_n_pj5 {
	nvidia,pins = "uart2_cts_n_pj5";
	nvidia,function = "uartb";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	uart2_rts_n_pj6 {
	nvidia,pins = "uart2_rts_n_pj6";
	nvidia,function = "uartb";
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	uart2_rxd_pc3 {
	nvidia,pins = "uart2_rxd_pc3";
	nvidia,function = "irda";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	uart2_txd_pc2 {
	nvidia,pins = "uart2_txd_pc2";
	nvidia,function = "irda";
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	uart3_cts_n_pa1 {
	nvidia,pins = "uart3_cts_n_pa1",
	"uart3_rxd_pw7";
	nvidia,function = "uartc";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	uart3_rts_n_pc0 {
	nvidia,pins = "uart3_rts_n_pc0",
	"uart3_txd_pw6";
	nvidia,function = "uartc";
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	hdmi_cec_pee3 {
	nvidia,pins = "hdmi_cec_pee3";
	nvidia,function = "cec";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,lock = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	hdmi_int_pn7 {
	nvidia,pins = "hdmi_int_pn7";
	nvidia,function = "rsvd1";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	ddc_scl_pv4 {
	nvidia,pins = "ddc_scl_pv4",
	"ddc_sda_pv5";
	nvidia,function = "i2c4";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,lock = <TEGRA_PIN_DISABLE>;
	nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
	};
	pj7 {
	nvidia,pins = "pj7",
	"pk7";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pb0 {
	nvidia,pins = "pb0",
	"pb1";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ph0 {
	nvidia,pins = "ph0";
	nvidia,function = "pwm0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_row10_ps2 {
	nvidia,pins = "kb_row10_ps2";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row9_ps1 {
	nvidia,pins = "kb_row9_ps1";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb_row6_pr6 {
	nvidia,pins = "kb_row6_pr6";
	nvidia,function = "displaya_alt";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	usb_vbus_en0_pn4 {
	nvidia,pins = "usb_vbus_en0_pn4",
	"usb_vbus_en1_pn5";
	nvidia,function = "usb";
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,lock = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	drive_sdio1 {
	nvidia,pins = "drive_sdio1";
	nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
	nvidia,schmitt = <TEGRA_PIN_DISABLE>;
	nvidia,pull-down-strength = <32>;
	nvidia,pull-up-strength = <42>;
	nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
	nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
	};
	drive_sdio3 {
	nvidia,pins = "drive_sdio3";
	nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
	nvidia,schmitt = <TEGRA_PIN_DISABLE>;
	nvidia,pull-down-strength = <20>;
	nvidia,pull-up-strength = <36>;
	nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
	nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
	};
	drive_gma {
	nvidia,pins = "drive_gma";
	nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
	nvidia,schmitt = <TEGRA_PIN_DISABLE>;
	nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
	nvidia,pull-down-strength = <1>;
	nvidia,pull-up-strength = <2>;
	nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
	nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
	nvidia,drive-type = <1>;
	};
	als_irq_l {
	nvidia,pins = "gpio_x3_aud_px3";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	codec_irq_l {
	nvidia,pins = "ph4";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_bl_en {
	nvidia,pins = "ph2";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	touch_irq_l {
	nvidia,pins = "gpio_w3_aud_pw3";
	nvidia,function = "spi6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	tpm_davint_l {
	nvidia,pins = "ph6";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ts_irq_l {
	nvidia,pins = "pk2";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ts_reset_l {
	nvidia,pins = "pk4";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ts_shdn_l {
	nvidia,pins = "pk1";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ph7 {
	nvidia,pins = "ph7";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_col0_ap {
	nvidia,pins = "kb_col0_pq0";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lid_open {
	nvidia,pins = "kb_row4_pr4";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	en_vdd_sd {
	nvidia,pins = "kb_row0_pr0";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ac_ok {
	nvidia,pins = "pj0";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sensor_irq_l {
	nvidia,pins = "pi6";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	wifi_en {
	nvidia,pins = "gpio_x7_aud_px7";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	wifi_rst_l {
	nvidia,pins = "clk2_req_pcc5";
	nvidia,function = "dap";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	hp_det_l {
	nvidia,pins = "ulpi_data1_po2";
	nvidia,function = "spi3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	};
	};

	serial@70006000 {
	status = "okay";
	};

	pwm@7000a000 {
	status = "okay";
	};

	i2c@7000c000 {
	status = "okay";
	clock-frequency = <100000>;

	acodec: audio-codec@10 {
	compatible = "maxim,max98090";
	reg = <0x10>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
	};
	};

	i2c@7000c400 {
	status = "okay";
	clock-frequency = <100000>;

	trackpad@4b {
	compatible = "atmel,maxtouch";
	reg = <0x4b>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>;
	linux,gpio-keymap = <0 0 0 BTN_LEFT>;
	};
	};

	i2c@7000c500 {
	status = "okay";
	clock-frequency = <100000>;
	};

	hdmi_ddc: i2c@7000c700 {
	status = "okay";
	clock-frequency = <100000>;
	};

	i2c@7000d000 {
	status = "okay";
	clock-frequency = <400000>;

	pmic: pmic@40 {
	compatible = "ams,as3722";
	reg = <0x40>;
	interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;

	ams,system-power-controller;

	#interrupt-cells = <2>;
	interrupt-controller;

	gpio-controller;
	#gpio-cells = <2>;

	pinctrl-names = "default";
	pinctrl-0 = <&as3722_default>;

	as3722_default: pinmux {
	gpio0 {
	pins = "gpio0";
	function = "gpio";
	bias-pull-down;
	};

	gpio1_2_4_7 {
	pins = "gpio1", "gpio2", "gpio4", "gpio7";
	function = "gpio";
	bias-pull-up;
	};

	gpio3_6 {
	pins = "gpio3", "gpio6";
	bias-high-impedance;
	};

	gpio5 {
	pins = "gpio5";
	function = "clk32k-out";
	};
	};

	regulators {
	vsup-sd2-supply = <&vdd_5v0_sys>;
	vsup-sd3-supply = <&vdd_5v0_sys>;
	vsup-sd4-supply = <&vdd_5v0_sys>;
	vsup-sd5-supply = <&vdd_5v0_sys>;
	vin-ldo0-supply = <&vdd_1v35_lp0>;
	vin-ldo1-6-supply = <&vdd_3v3_run>;
	vin-ldo2-5-7-supply = <&vddio_1v8>;
	vin-ldo3-4-supply = <&vdd_3v3_sys>;
	vin-ldo9-10-supply = <&vdd_5v0_sys>;
	vin-ldo11-supply = <&vdd_3v3_run>;

	sd0 {
	regulator-name = "+VDD_CPU_AP";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1400000>;
	regulator-min-microamp = <3500000>;
	regulator-max-microamp = <3500000>;
	regulator-always-on;
	regulator-boot-on;
	ams,ext-control = <2>;
	};

	sd1 {
	regulator-name = "+VDD_CORE";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1350000>;
	regulator-min-microamp = <2500000>;
	regulator-max-microamp = <2500000>;
	regulator-always-on;
	regulator-boot-on;
	ams,ext-control = <1>;
	};

	vdd_1v35_lp0: sd2 {
	regulator-name = "+1.35V_LP0(sd2)";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	};

	sd3 {
	regulator-name = "+1.35V_LP0(sd3)";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_1v05_run: sd4 {
	regulator-name = "+1.05V_RUN";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	};

	vddio_1v8: sd5 {
	regulator-name = "+1.8V_VDDIO";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vdd_gpu: sd6 {
	regulator-name = "+VDD_GPU_AP";
	regulator-min-microvolt = <650000>;
	regulator-max-microvolt = <1200000>;
	regulator-min-microamp = <3500000>;
	regulator-max-microamp = <3500000>;
	regulator-boot-on;
	regulator-always-on;
	};

	avdd_1v05_run: ldo0 {
	regulator-name = "+1.05V_RUN_AVDD";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	regulator-boot-on;
	regulator-always-on;
	ams,ext-control = <1>;
	};

	ldo1 {
	regulator-name = "+1.8V_RUN_CAM";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo2 {
	regulator-name = "+1.2V_GEN_AVDD";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo3 {
	regulator-name = "+1.00V_LP0_VDD_RTC";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-boot-on;
	regulator-always-on;
	ams,enable-tracking;
	};

	vdd_run_cam: ldo4 {
	regulator-name = "+3.3V_RUN_CAM";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	ldo5 {
	regulator-name = "+1.2V_RUN_CAM_FRONT";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	vddio_sdmmc3: ldo6 {
	regulator-name = "+VDDIO_SDMMC3";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	};

	ldo7 {
	regulator-name = "+1.05V_RUN_CAM_REAR";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	};

	ldo9 {
	regulator-name = "+2.8V_RUN_TOUCH";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	ldo10 {
	regulator-name = "+2.8V_RUN_CAM_AF";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	ldo11 {
	regulator-name = "+1.8V_RUN_VPP_FUSE";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	};
	};
	};

	spi@7000d400 {
	status = "okay";

	cros_ec: cros-ec@0 {
	compatible = "google,cros-ec-spi";
	spi-max-frequency = <4000000>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
	reg = <0>;

	google,cros-ec-spi-msg-delay = <2000>;

	i2c-tunnel {
	compatible = "google,cros-ec-i2c-tunnel";
	#address-cells = <1>;
	#size-cells = <0>;

	google,remote-bus = <0>;

	charger: bq24735@9 {
	compatible = "ti,bq24735";
	reg = <0x9>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(J, 0)
	IRQ_TYPE_EDGE_BOTH>;
	ti,ac-detect-gpios = <&gpio
	TEGRA_GPIO(J, 0)
	GPIO_ACTIVE_HIGH>;
	};

	battery: sbs-battery@b {
	compatible = "sbs,sbs-battery";
	reg = <0xb>;
	sbs,i2c-retry-count = <2>;
	sbs,poll-retry-count = <1>;
	};
	};
	};
	};

	spi@7000da00 {
	status = "okay";
	spi-max-frequency = <25000000>;
	spi-flash@0 {
	compatible = "winbond,w25q32dw", "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <20000000>;
	};
	};

	pmc@7000e400 {
	nvidia,invert-interrupt;
	nvidia,suspend-mode = <1>;
	nvidia,cpu-pwr-good-time = <500>;
	nvidia,cpu-pwr-off-time = <300>;
	nvidia,core-pwr-good-time = <641 3845>;
	nvidia,core-pwr-off-time = <61036>;
	nvidia,core-power-req-active-high;
	nvidia,sys-clock-req-active-high;
	};

	hda@70030000 {
	status = "okay";
	};

	usb@70090000 {
	phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
	<&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
	<&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
	phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";

	avddio-pex-supply = <&vdd_1v05_run>;
	dvddio-pex-supply = <&vdd_1v05_run>;
	avdd-usb-supply = <&vdd_3v3_lp0>;
	avdd-pll-utmip-supply = <&vddio_1v8>;
	avdd-pll-erefe-supply = <&avdd_1v05_run>;
	avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
	hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
	hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;

	status = "okay";
	};

	padctl@7009f000 {
	avdd-pll-utmip-supply = <&vddio_1v8>;
	avdd-pll-erefe-supply = <&avdd_1v05_run>;
	avdd-pex-pll-supply = <&vdd_1v05_run>;
	hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;

	pads {
	usb2 {
	status = "okay";

	lanes {
	usb2-0 {
	nvidia,function = "xusb";
	status = "okay";
	};

	usb2-1 {
	nvidia,function = "xusb";
	status = "okay";
	};

	usb2-2 {
	nvidia,function = "xusb";
	status = "okay";
	};
	};
	};

	pcie {
	status = "okay";

	lanes {
	pcie-0 {
	nvidia,function = "usb3-ss";
	status = "okay";
	};

	pcie-1 {
	nvidia,function = "usb3-ss";
	status = "okay";
	};
	};
	};
	};

	ports {
	usb2-0 {
	status = "okay";
	mode = "otg";

	vbus-supply = <&vdd_usb1_vbus>;
	};

	usb2-1 {
	status = "okay";
	mode = "host";

	vbus-supply = <&vdd_run_cam>;
	};

	usb2-2 {
	status = "okay";
	mode = "host";

	vbus-supply = <&vdd_usb3_vbus>;
	};

	usb3-0 {
	nvidia,usb2-companion = <0>;
	status = "okay";
	};

	usb3-1 {
	nvidia,usb2-companion = <2>;
	status = "okay";
	};
	};
	};

	sdhci@700b0400 {
	cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
	power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
	wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
	status = "okay";
	bus-width = <4>;
	vqmmc-supply = <&vddio_sdmmc3>;
	};

	sdhci@700b0600 {
	status = "okay";
	bus-width = <8>;
	non-removable;
	};

	ahub@70300000 {
	i2s@70301100 {
	status = "okay";
	};
	};

	usb@7d000000 {
	status = "okay";
	};

	usb-phy@7d000000 {
	status = "okay";
	vbus-supply = <&vdd_usb1_vbus>;
	};

	usb@7d004000 {
	status = "okay";
	};

	usb-phy@7d004000 {
	status = "okay";
	vbus-supply = <&vdd_run_cam>;
	};

	usb@7d008000 {
	status = "okay";
	};

	usb-phy@7d008000 {
	status = "okay";
	vbus-supply = <&vdd_usb3_vbus>;
	};

	backlight: backlight {
	compatible = "pwm-backlight";

	enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
	power-supply = <&vdd_led>;
	pwms = <&pwm 1 1000000>;

	brightness-levels = <0 4 8 16 32 64 128 255>;
	default-brightness-level = <6>;
	};

	clocks {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	clk32k_in: clock@0 {
	compatible = "fixed-clock";
	reg = <0>;
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	};

	gpio-keys {
	compatible = "gpio-keys";

	power {
	label = "Power";
	gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
	linux,code = <KEY_POWER>;
	debounce-interval = <10>;
	wakeup-source;
	};
	};

	panel: panel {
	compatible = "lg,lp129qe", "simple-panel";

	backlight = <&backlight>;
	ddc-i2c-bus = <&dpaux>;
	};

	regulators {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	vdd_mux: regulator@0 {
	compatible = "regulator-fixed";
	reg = <0>;
	regulator-name = "+VDD_MUX";
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_5v0_sys: regulator@1 {
	compatible = "regulator-fixed";
	reg = <1>;
	regulator-name = "+5V_SYS";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vdd_mux>;
	};

	vdd_3v3_sys: regulator@2 {
	compatible = "regulator-fixed";
	reg = <2>;
	regulator-name = "+3.3V_SYS";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vdd_mux>;
	};

	vdd_3v3_run: regulator@3 {
	compatible = "regulator-fixed";
	reg = <3>;
	regulator-name = "+3.3V_RUN";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_3v3_sys>;
	};

	vdd_3v3_hdmi: regulator@4 {
	compatible = "regulator-fixed";
	reg = <4>;
	regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vdd_3v3_run>;
	};

	vdd_led: regulator@5 {
	compatible = "regulator-fixed";
	reg = <5>;
	regulator-name = "+VDD_LED";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_mux>;
	};

	vdd_5v0_ts: regulator@6 {
	compatible = "regulator-fixed";
	reg = <6>;
	regulator-name = "+5V_VDD_TS_SW";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-boot-on;
	gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_5v0_sys>;
	};

	vdd_usb1_vbus: regulator@7 {
	compatible = "regulator-fixed";
	reg = <7>;
	regulator-name = "+5V_USB_HS";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	gpio-open-drain;
	vin-supply = <&vdd_5v0_sys>;
	};

	vdd_usb3_vbus: regulator@8 {
	compatible = "regulator-fixed";
	reg = <8>;
	regulator-name = "+5V_USB_SS";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	gpio-open-drain;
	vin-supply = <&vdd_5v0_sys>;
	};

	vdd_3v3_panel: regulator@9 {
	compatible = "regulator-fixed";
	reg = <9>;
	regulator-name = "+3.3V_PANEL";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_3v3_run>;
	};

	vdd_3v3_lp0: regulator@10 {
	compatible = "regulator-fixed";
	reg = <10>;
	regulator-name = "+3.3V_LP0";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	/*
	* TODO: find a way to wire this up with the USB EHCI
	* controllers so that it can be enabled on demand.
	*/
	regulator-always-on;
	gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_3v3_sys>;
	};

	vdd_hdmi_pll: regulator@11 {
	compatible = "regulator-fixed";
	reg = <11>;
	regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
	vin-supply = <&vdd_1v05_run>;
	};

	vdd_5v0_hdmi: regulator@12 {
	compatible = "regulator-fixed";
	reg = <12>;
	regulator-name = "+5V_HDMI_CON";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_5v0_sys>;
	};
	};

	sound {
	compatible = "nvidia,tegra-audio-max98090-venice2",
	"nvidia,tegra-audio-max98090";
	nvidia,model = "NVIDIA Tegra Venice2";

	nvidia,audio-routing =
	"Headphones", "HPR",
	"Headphones", "HPL",
	"Speakers", "SPKR",
	"Speakers", "SPKL",
	"Mic Jack", "MICBIAS",
	"IN34", "Mic Jack";

	nvidia,i2s-controller = <&tegra_i2s1>;
	nvidia,audio-codec = <&acodec>;

	clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
	<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
	- <&tegra_car TEGRA124_CLK_EXTERN1>;
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	clock-names = "pll_a", "pll_a_out0", "mclk";
	+
	+ assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	+
	+ assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
	+ <&tegra_car TEGRA124_CLK_EXTERN1>;
	};
	};

	#include "cros-ec-keyboard.dtsi"
	diff --git a/sys/gnu/dts/arm/tegra124.dtsi b/sys/gnu/dts/arm/tegra124.dtsi
	index 7f330b1f150f..94cac13d3e50 100644
	--- a/sys/gnu/dts/arm/tegra124.dtsi
	+++ b/sys/gnu/dts/arm/tegra124.dtsi
	@@ -1,1309 +1,1311 @@
	// SPDX-License-Identifier: GPL-2.0
	#include <dt-bindings/clock/tegra124-car.h>
	#include <dt-bindings/gpio/tegra-gpio.h>
	#include <dt-bindings/memory/tegra124-mc.h>
	#include <dt-bindings/pinctrl/pinctrl-tegra.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/reset/tegra124-car.h>
	#include <dt-bindings/thermal/tegra124-soctherm.h>
	+#include <dt-bindings/soc/tegra-pmc.h>

	/ {
	compatible = "nvidia,tegra124";
	interrupt-parent = <&lic>;
	#address-cells = <2>;
	#size-cells = <2>;

	memory@80000000 {
	device_type = "memory";
	reg = <0x0 0x80000000 0x0 0x0>;
	};

	pcie@1003000 {
	compatible = "nvidia,tegra124-pcie";
	device_type = "pci";
	reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
	0x0 0x01003800 0x0 0x00000800 /* AFI registers */
	0x0 0x02000000 0x0 0x10000000>; /* configuration space */
	reg-names = "pads", "afi", "cs";
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
	<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
	interrupt-names = "intr", "msi";

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

	bus-range = <0x00 0xff>;
	#address-cells = <3>;
	#size-cells = <2>;

	ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
	0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
	0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
	0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
	0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */

	clocks = <&tegra_car TEGRA124_CLK_PCIE>,
	<&tegra_car TEGRA124_CLK_AFI>,
	<&tegra_car TEGRA124_CLK_PLL_E>,
	<&tegra_car TEGRA124_CLK_CML0>;
	clock-names = "pex", "afi", "pll_e", "cml";
	resets = <&tegra_car 70>,
	<&tegra_car 72>,
	<&tegra_car 74>;
	reset-names = "pex", "afi", "pcie_x";
	status = "disabled";

	pci@1,0 {
	device_type = "pci";
	assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
	reg = <0x000800 0 0 0 0>;
	bus-range = <0x00 0xff>;
	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	ranges;

	nvidia,num-lanes = <2>;
	};

	pci@2,0 {
	device_type = "pci";
	assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
	reg = <0x001000 0 0 0 0>;
	bus-range = <0x00 0xff>;
	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	ranges;

	nvidia,num-lanes = <1>;
	};
	};

	host1x@50000000 {
	compatible = "nvidia,tegra124-host1x", "simple-bus";
	reg = <0x0 0x50000000 0x0 0x00034000>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
	clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
	resets = <&tegra_car 28>;
	reset-names = "host1x";
	iommus = <&mc TEGRA_SWGROUP_HC>;

	#address-cells = <2>;
	#size-cells = <2>;

	ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;

	dc@54200000 {
	compatible = "nvidia,tegra124-dc";
	reg = <0x0 0x54200000 0x0 0x00040000>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_DISP1>,
	<&tegra_car TEGRA124_CLK_PLL_P>;
	clock-names = "dc", "parent";
	resets = <&tegra_car 27>;
	reset-names = "dc";

	iommus = <&mc TEGRA_SWGROUP_DC>;

	nvidia,head = <0>;
	};

	dc@54240000 {
	compatible = "nvidia,tegra124-dc";
	reg = <0x0 0x54240000 0x0 0x00040000>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_DISP2>,
	<&tegra_car TEGRA124_CLK_PLL_P>;
	clock-names = "dc", "parent";
	resets = <&tegra_car 26>;
	reset-names = "dc";

	iommus = <&mc TEGRA_SWGROUP_DCB>;

	nvidia,head = <1>;
	};

	hdmi: hdmi@54280000 {
	compatible = "nvidia,tegra124-hdmi";
	reg = <0x0 0x54280000 0x0 0x00040000>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_HDMI>,
	<&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
	clock-names = "hdmi", "parent";
	resets = <&tegra_car 51>;
	reset-names = "hdmi";
	status = "disabled";
	};

	vic@54340000 {
	compatible = "nvidia,tegra124-vic";
	reg = <0x0 0x54340000 0x0 0x00040000>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_VIC03>;
	clock-names = "vic";
	resets = <&tegra_car 178>;
	reset-names = "vic";

	iommus = <&mc TEGRA_SWGROUP_VIC>;
	};

	sor@54540000 {
	compatible = "nvidia,tegra124-sor";
	reg = <0x0 0x54540000 0x0 0x00040000>;
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_SOR0>,
	<&tegra_car TEGRA124_CLK_SOR0_OUT>,
	<&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
	<&tegra_car TEGRA124_CLK_PLL_DP>,
	<&tegra_car TEGRA124_CLK_CLK_M>;
	clock-names = "sor", "out", "parent", "dp", "safe";
	resets = <&tegra_car 182>;
	reset-names = "sor";
	status = "disabled";
	};

	dpaux: dpaux@545c0000 {
	compatible = "nvidia,tegra124-dpaux";
	reg = <0x0 0x545c0000 0x0 0x00040000>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
	<&tegra_car TEGRA124_CLK_PLL_DP>;
	clock-names = "dpaux", "parent";
	resets = <&tegra_car 181>;
	reset-names = "dpaux";
	status = "disabled";
	};
	};

	gic: interrupt-controller@50041000 {
	compatible = "arm,cortex-a15-gic";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x0 0x50041000 0x0 0x1000>,
	<0x0 0x50042000 0x0 0x1000>,
	<0x0 0x50044000 0x0 0x2000>,
	<0x0 0x50046000 0x0 0x2000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	interrupt-parent = <&gic>;
	};

	/*
	* Please keep the following 0, notation in place as a former mainline
	* U-Boot version was looking for that particular notation in order to
	* perform required fix-ups on that GPU node.
	*/
	gpu@0,57000000 {
	compatible = "nvidia,gk20a";
	reg = <0x0 0x57000000 0x0 0x01000000>,
	<0x0 0x58000000 0x0 0x01000000>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "stall", "nonstall";
	clocks = <&tegra_car TEGRA124_CLK_GPU>,
	<&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
	clock-names = "gpu", "pwr";
	resets = <&tegra_car 184>;
	reset-names = "gpu";

	iommus = <&mc TEGRA_SWGROUP_GPU>;

	status = "disabled";
	};

	lic: interrupt-controller@60004000 {
	compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
	reg = <0x0 0x60004000 0x0 0x100>,
	<0x0 0x60004100 0x0 0x100>,
	<0x0 0x60004200 0x0 0x100>,
	<0x0 0x60004300 0x0 0x100>,
	<0x0 0x60004400 0x0 0x100>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	};

	timer@60005000 {
	compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
	reg = <0x0 0x60005000 0x0 0x400>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_TIMER>;
	};

	tegra_car: clock@60006000 {
	compatible = "nvidia,tegra124-car";
	reg = <0x0 0x60006000 0x0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	nvidia,external-memory-controller = <&emc>;
	};

	flow-controller@60007000 {
	compatible = "nvidia,tegra124-flowctrl";
	reg = <0x0 0x60007000 0x0 0x1000>;
	};

	actmon@6000c800 {
	compatible = "nvidia,tegra124-actmon";
	reg = <0x0 0x6000c800 0x0 0x400>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
	<&tegra_car TEGRA124_CLK_EMC>;
	clock-names = "actmon", "emc";
	resets = <&tegra_car 119>;
	reset-names = "actmon";
	};

	gpio: gpio@6000d000 {
	compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
	reg = <0x0 0x6000d000 0x0 0x1000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	#interrupt-cells = <2>;
	interrupt-controller;
	/*
	gpio-ranges = <&pinmux 0 0 251>;
	*/
	};

	apbdma: dma@60020000 {
	compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
	reg = <0x0 0x60020000 0x0 0x1400>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
	resets = <&tegra_car 34>;
	reset-names = "dma";
	#dma-cells = <1>;
	};

	apbmisc@70000800 {
	compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
	reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
	<0x0 0x7000e864 0x0 0x04>; /* Strapping options */
	};

	pinmux: pinmux@70000868 {
	compatible = "nvidia,tegra124-pinmux";
	reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
	<0x0 0x70003000 0x0 0x434>, /* Mux registers */
	<0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
	};

	/*
	* There are two serial driver i.e. 8250 based simple serial
	* driver and APB DMA based serial driver for higher baudrate
	* and performace. To enable the 8250 based driver, the compatible
	* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
	* the APB DMA based serial driver, the compatible is
	* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
	*/
	uarta: serial@70006000 {
	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x70006000 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_UARTA>;
	resets = <&tegra_car 6>;
	reset-names = "serial";
	dmas = <&apbdma 8>, <&apbdma 8>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartb: serial@70006040 {
	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x70006040 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_UARTB>;
	resets = <&tegra_car 7>;
	reset-names = "serial";
	dmas = <&apbdma 9>, <&apbdma 9>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartc: serial@70006200 {
	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x70006200 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_UARTC>;
	resets = <&tegra_car 55>;
	reset-names = "serial";
	dmas = <&apbdma 10>, <&apbdma 10>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartd: serial@70006300 {
	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x70006300 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_UARTD>;
	resets = <&tegra_car 65>;
	reset-names = "serial";
	dmas = <&apbdma 19>, <&apbdma 19>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	pwm: pwm@7000a000 {
	compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
	reg = <0x0 0x7000a000 0x0 0x100>;
	#pwm-cells = <2>;
	clocks = <&tegra_car TEGRA124_CLK_PWM>;
	resets = <&tegra_car 17>;
	reset-names = "pwm";
	status = "disabled";
	};

	i2c@7000c000 {
	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
	reg = <0x0 0x7000c000 0x0 0x100>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_I2C1>;
	clock-names = "div-clk";
	resets = <&tegra_car 12>;
	reset-names = "i2c";
	dmas = <&apbdma 21>, <&apbdma 21>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000c400 {
	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
	reg = <0x0 0x7000c400 0x0 0x100>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_I2C2>;
	clock-names = "div-clk";
	resets = <&tegra_car 54>;
	reset-names = "i2c";
	dmas = <&apbdma 22>, <&apbdma 22>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000c500 {
	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
	reg = <0x0 0x7000c500 0x0 0x100>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_I2C3>;
	clock-names = "div-clk";
	resets = <&tegra_car 67>;
	reset-names = "i2c";
	dmas = <&apbdma 23>, <&apbdma 23>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000c700 {
	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
	reg = <0x0 0x7000c700 0x0 0x100>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_I2C4>;
	clock-names = "div-clk";
	resets = <&tegra_car 103>;
	reset-names = "i2c";
	dmas = <&apbdma 26>, <&apbdma 26>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000d000 {
	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
	reg = <0x0 0x7000d000 0x0 0x100>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_I2C5>;
	clock-names = "div-clk";
	resets = <&tegra_car 47>;
	reset-names = "i2c";
	dmas = <&apbdma 24>, <&apbdma 24>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000d100 {
	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
	reg = <0x0 0x7000d100 0x0 0x100>;
	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_I2C6>;
	clock-names = "div-clk";
	resets = <&tegra_car 166>;
	reset-names = "i2c";
	dmas = <&apbdma 30>, <&apbdma 30>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000d400 {
	compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
	reg = <0x0 0x7000d400 0x0 0x200>;
	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_SBC1>;
	clock-names = "spi";
	resets = <&tegra_car 41>;
	reset-names = "spi";
	dmas = <&apbdma 15>, <&apbdma 15>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000d600 {
	compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
	reg = <0x0 0x7000d600 0x0 0x200>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_SBC2>;
	clock-names = "spi";
	resets = <&tegra_car 44>;
	reset-names = "spi";
	dmas = <&apbdma 16>, <&apbdma 16>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000d800 {
	compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
	reg = <0x0 0x7000d800 0x0 0x200>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_SBC3>;
	clock-names = "spi";
	resets = <&tegra_car 46>;
	reset-names = "spi";
	dmas = <&apbdma 17>, <&apbdma 17>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000da00 {
	compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
	reg = <0x0 0x7000da00 0x0 0x200>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_SBC4>;
	clock-names = "spi";
	resets = <&tegra_car 68>;
	reset-names = "spi";
	dmas = <&apbdma 18>, <&apbdma 18>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000dc00 {
	compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
	reg = <0x0 0x7000dc00 0x0 0x200>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_SBC5>;
	clock-names = "spi";
	resets = <&tegra_car 104>;
	reset-names = "spi";
	dmas = <&apbdma 27>, <&apbdma 27>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000de00 {
	compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
	reg = <0x0 0x7000de00 0x0 0x200>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_SBC6>;
	clock-names = "spi";
	resets = <&tegra_car 105>;
	reset-names = "spi";
	dmas = <&apbdma 28>, <&apbdma 28>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	rtc@7000e000 {
	compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
	reg = <0x0 0x7000e000 0x0 0x100>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_RTC>;
	};

	- pmc@7000e400 {
	+ tegra_pmc: pmc@7000e400 {
	compatible = "nvidia,tegra124-pmc";
	reg = <0x0 0x7000e400 0x0 0x400>;
	clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
	clock-names = "pclk", "clk32k_in";
	+ #clock-cells = <1>;
	};

	fuse@7000f800 {
	compatible = "nvidia,tegra124-efuse";
	reg = <0x0 0x7000f800 0x0 0x400>;
	clocks = <&tegra_car TEGRA124_CLK_FUSE>;
	clock-names = "fuse";
	resets = <&tegra_car 39>;
	reset-names = "fuse";
	};

	mc: memory-controller@70019000 {
	compatible = "nvidia,tegra124-mc";
	reg = <0x0 0x70019000 0x0 0x1000>;
	clocks = <&tegra_car TEGRA124_CLK_MC>;
	clock-names = "mc";

	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;

	#iommu-cells = <1>;
	};

	emc: external-memory-controller@7001b000 {
	compatible = "nvidia,tegra124-emc";
	reg = <0x0 0x7001b000 0x0 0x1000>;
	clocks = <&tegra_car TEGRA124_CLK_EMC>;
	clock-names = "emc";

	nvidia,memory-controller = <&mc>;
	};

	sata@70020000 {
	compatible = "nvidia,tegra124-ahci";
	reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
	<0x0 0x70020000 0x0 0x7000>; /* SATA */
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_SATA>,
	<&tegra_car TEGRA124_CLK_SATA_OOB>,
	<&tegra_car TEGRA124_CLK_CML1>,
	<&tegra_car TEGRA124_CLK_PLL_E>;
	clock-names = "sata", "sata-oob", "cml1", "pll_e";
	resets = <&tegra_car 124>,
	<&tegra_car 123>,
	<&tegra_car 129>;
	reset-names = "sata", "sata-oob", "sata-cold";
	status = "disabled";
	};

	hda@70030000 {
	compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
	reg = <0x0 0x70030000 0x0 0x10000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_HDA>,
	<&tegra_car TEGRA124_CLK_HDA2HDMI>,
	<&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
	clock-names = "hda", "hda2hdmi", "hda2codec_2x";
	resets = <&tegra_car 125>, /* hda */
	<&tegra_car 128>, /* hda2hdmi */
	<&tegra_car 111>; /* hda2codec_2x */
	reset-names = "hda", "hda2hdmi", "hda2codec_2x";
	status = "disabled";
	};

	usb@70090000 {
	compatible = "nvidia,tegra124-xusb";
	reg = <0x0 0x70090000 0x0 0x8000>,
	<0x0 0x70098000 0x0 0x1000>,
	<0x0 0x70099000 0x0 0x1000>;
	reg-names = "hcd", "fpci", "ipfs";

	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
	<&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
	<&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
	<&tegra_car TEGRA124_CLK_XUSB_SS>,
	<&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
	<&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
	<&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
	<&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
	<&tegra_car TEGRA124_CLK_PLL_U_480M>,
	<&tegra_car TEGRA124_CLK_CLK_M>,
	<&tegra_car TEGRA124_CLK_PLL_E>;
	clock-names = "xusb_host", "xusb_host_src",
	"xusb_falcon_src", "xusb_ss",
	"xusb_ss_div2", "xusb_ss_src",
	"xusb_hs_src", "xusb_fs_src",
	"pll_u_480m", "clk_m", "pll_e";
	resets = <&tegra_car 89>, <&tegra_car 156>,
	<&tegra_car 143>;
	reset-names = "xusb_host", "xusb_ss", "xusb_src";

	nvidia,xusb-padctl = <&padctl>;

	status = "disabled";
	};

	padctl: padctl@7009f000 {
	compatible = "nvidia,tegra124-xusb-padctl";
	reg = <0x0 0x7009f000 0x0 0x1000>;
	resets = <&tegra_car 142>;
	reset-names = "padctl";

	pads {
	usb2 {
	status = "disabled";

	lanes {
	usb2-0 {
	status = "disabled";
	#phy-cells = <0>;
	};

	usb2-1 {
	status = "disabled";
	#phy-cells = <0>;
	};

	usb2-2 {
	status = "disabled";
	#phy-cells = <0>;
	};
	};
	};

	ulpi {
	status = "disabled";

	lanes {
	ulpi-0 {
	status = "disabled";
	#phy-cells = <0>;
	};
	};
	};

	hsic {
	status = "disabled";

	lanes {
	hsic-0 {
	status = "disabled";
	#phy-cells = <0>;
	};

	hsic-1 {
	status = "disabled";
	#phy-cells = <0>;
	};
	};
	};

	pcie {
	status = "disabled";

	lanes {
	pcie-0 {
	status = "disabled";
	#phy-cells = <0>;
	};

	pcie-1 {
	status = "disabled";
	#phy-cells = <0>;
	};

	pcie-2 {
	status = "disabled";
	#phy-cells = <0>;
	};

	pcie-3 {
	status = "disabled";
	#phy-cells = <0>;
	};

	pcie-4 {
	status = "disabled";
	#phy-cells = <0>;
	};
	};
	};

	sata {
	status = "disabled";

	lanes {
	sata-0 {
	status = "disabled";
	#phy-cells = <0>;
	};
	};
	};
	};

	ports {
	usb2-0 {
	status = "disabled";
	};

	usb2-1 {
	status = "disabled";
	};

	usb2-2 {
	status = "disabled";
	};

	ulpi-0 {
	status = "disabled";
	};

	hsic-0 {
	status = "disabled";
	};

	hsic-1 {
	status = "disabled";
	};

	usb3-0 {
	status = "disabled";
	};

	usb3-1 {
	status = "disabled";
	};
	};
	};

	sdhci@700b0000 {
	compatible = "nvidia,tegra124-sdhci";
	reg = <0x0 0x700b0000 0x0 0x200>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
	resets = <&tegra_car 14>;
	reset-names = "sdhci";
	status = "disabled";
	};

	sdhci@700b0200 {
	compatible = "nvidia,tegra124-sdhci";
	reg = <0x0 0x700b0200 0x0 0x200>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
	resets = <&tegra_car 9>;
	reset-names = "sdhci";
	status = "disabled";
	};

	sdhci@700b0400 {
	compatible = "nvidia,tegra124-sdhci";
	reg = <0x0 0x700b0400 0x0 0x200>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
	resets = <&tegra_car 69>;
	reset-names = "sdhci";
	status = "disabled";
	};

	sdhci@700b0600 {
	compatible = "nvidia,tegra124-sdhci";
	reg = <0x0 0x700b0600 0x0 0x200>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
	resets = <&tegra_car 15>;
	reset-names = "sdhci";
	status = "disabled";
	};

	cec@70015000 {
	compatible = "nvidia,tegra124-cec";
	reg = <0x0 0x70015000 0x0 0x00001000>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_CEC>;
	clock-names = "cec";
	status = "disabled";
	hdmi-phandle = <&hdmi>;
	};

	soctherm: thermal-sensor@700e2000 {
	compatible = "nvidia,tegra124-soctherm";
	reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
	0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
	reg-names = "soctherm-reg", "car-reg";
	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
	<&tegra_car TEGRA124_CLK_SOC_THERM>;
	clock-names = "tsensor", "soctherm";
	resets = <&tegra_car 78>;
	reset-names = "soctherm";
	#thermal-sensor-cells = <1>;

	throttle-cfgs {
	throttle_heavy: heavy {
	nvidia,priority = <100>;
	nvidia,cpu-throt-percent = <85>;

	#cooling-cells = <2>;
	};
	};
	};

	dfll: clock@70110000 {
	compatible = "nvidia,tegra124-dfll";
	reg = <0 0x70110000 0 0x100>, /* DFLL control */
	<0 0x70110000 0 0x100>, /* I2C output control */
	<0 0x70110100 0 0x100>, /* Integrated I2C controller */
	<0 0x70110200 0 0x100>; /* Look-up table RAM */
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
	<&tegra_car TEGRA124_CLK_DFLL_REF>,
	<&tegra_car TEGRA124_CLK_I2C5>;
	clock-names = "soc", "ref", "i2c";
	resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
	reset-names = "dvco";
	#clock-cells = <0>;
	clock-output-names = "dfllCPU_out";
	nvidia,sample-rate = <12500>;
	nvidia,droop-ctrl = <0x00000f00>;
	nvidia,force-mode = <1>;
	nvidia,cf = <10>;
	nvidia,ci = <0>;
	nvidia,cg = <2>;
	status = "disabled";
	};

	ahub@70300000 {
	compatible = "nvidia,tegra124-ahub";
	reg = <0x0 0x70300000 0x0 0x200>,
	<0x0 0x70300800 0x0 0x800>,
	<0x0 0x70300200 0x0 0x600>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
	<&tegra_car TEGRA124_CLK_APBIF>;
	clock-names = "d_audio", "apbif";
	resets = <&tegra_car 106>, /* d_audio */
	<&tegra_car 107>, /* apbif */
	<&tegra_car 30>, /* i2s0 */
	<&tegra_car 11>, /* i2s1 */
	<&tegra_car 18>, /* i2s2 */
	<&tegra_car 101>, /* i2s3 */
	<&tegra_car 102>, /* i2s4 */
	<&tegra_car 108>, /* dam0 */
	<&tegra_car 109>, /* dam1 */
	<&tegra_car 110>, /* dam2 */
	<&tegra_car 10>, /* spdif */
	<&tegra_car 153>, /* amx */
	<&tegra_car 185>, /* amx1 */
	<&tegra_car 154>, /* adx */
	<&tegra_car 180>, /* adx1 */
	<&tegra_car 186>, /* afc0 */
	<&tegra_car 187>, /* afc1 */
	<&tegra_car 188>, /* afc2 */
	<&tegra_car 189>, /* afc3 */
	<&tegra_car 190>, /* afc4 */
	<&tegra_car 191>; /* afc5 */
	reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
	"i2s3", "i2s4", "dam0", "dam1", "dam2",
	"spdif", "amx", "amx1", "adx", "adx1",
	"afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
	dmas = <&apbdma 1>, <&apbdma 1>,
	<&apbdma 2>, <&apbdma 2>,
	<&apbdma 3>, <&apbdma 3>,
	<&apbdma 4>, <&apbdma 4>,
	<&apbdma 6>, <&apbdma 6>,
	<&apbdma 7>, <&apbdma 7>,
	<&apbdma 12>, <&apbdma 12>,
	<&apbdma 13>, <&apbdma 13>,
	<&apbdma 14>, <&apbdma 14>,
	<&apbdma 29>, <&apbdma 29>;
	dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
	"rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
	"rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
	"rx9", "tx9";
	ranges;
	#address-cells = <2>;
	#size-cells = <2>;

	tegra_i2s0: i2s@70301000 {
	compatible = "nvidia,tegra124-i2s";
	reg = <0x0 0x70301000 0x0 0x100>;
	nvidia,ahub-cif-ids = <4 4>;
	clocks = <&tegra_car TEGRA124_CLK_I2S0>;
	resets = <&tegra_car 30>;
	reset-names = "i2s";
	status = "disabled";
	};

	tegra_i2s1: i2s@70301100 {
	compatible = "nvidia,tegra124-i2s";
	reg = <0x0 0x70301100 0x0 0x100>;
	nvidia,ahub-cif-ids = <5 5>;
	clocks = <&tegra_car TEGRA124_CLK_I2S1>;
	resets = <&tegra_car 11>;
	reset-names = "i2s";
	status = "disabled";
	};

	tegra_i2s2: i2s@70301200 {
	compatible = "nvidia,tegra124-i2s";
	reg = <0x0 0x70301200 0x0 0x100>;
	nvidia,ahub-cif-ids = <6 6>;
	clocks = <&tegra_car TEGRA124_CLK_I2S2>;
	resets = <&tegra_car 18>;
	reset-names = "i2s";
	status = "disabled";
	};

	tegra_i2s3: i2s@70301300 {
	compatible = "nvidia,tegra124-i2s";
	reg = <0x0 0x70301300 0x0 0x100>;
	nvidia,ahub-cif-ids = <7 7>;
	clocks = <&tegra_car TEGRA124_CLK_I2S3>;
	resets = <&tegra_car 101>;
	reset-names = "i2s";
	status = "disabled";
	};

	tegra_i2s4: i2s@70301400 {
	compatible = "nvidia,tegra124-i2s";
	reg = <0x0 0x70301400 0x0 0x100>;
	nvidia,ahub-cif-ids = <8 8>;
	clocks = <&tegra_car TEGRA124_CLK_I2S4>;
	resets = <&tegra_car 102>;
	reset-names = "i2s";
	status = "disabled";
	};
	};

	usb@7d000000 {
	compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
	reg = <0x0 0x7d000000 0x0 0x4000>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA124_CLK_USBD>;
	resets = <&tegra_car 22>;
	reset-names = "usb";
	nvidia,phy = <&phy1>;
	status = "disabled";
	};

	phy1: usb-phy@7d000000 {
	compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
	reg = <0x0 0x7d000000 0x0 0x4000>,
	<0x0 0x7d000000 0x0 0x4000>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA124_CLK_USBD>,
	<&tegra_car TEGRA124_CLK_PLL_U>,
	<&tegra_car TEGRA124_CLK_USBD>;
	clock-names = "reg", "pll_u", "utmi-pads";
	resets = <&tegra_car 22>, <&tegra_car 22>;
	reset-names = "usb", "utmi-pads";
	nvidia,hssync-start-delay = <0>;
	nvidia,idle-wait-delay = <17>;
	nvidia,elastic-limit = <16>;
	nvidia,term-range-adj = <6>;
	nvidia,xcvr-setup = <9>;
	nvidia,xcvr-lsfslew = <0>;
	nvidia,xcvr-lsrslew = <3>;
	nvidia,hssquelch-level = <2>;
	nvidia,hsdiscon-level = <5>;
	nvidia,xcvr-hsslew = <12>;
	nvidia,has-utmi-pad-registers;
	status = "disabled";
	};

	usb@7d004000 {
	compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
	reg = <0x0 0x7d004000 0x0 0x4000>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA124_CLK_USB2>;
	resets = <&tegra_car 58>;
	reset-names = "usb";
	nvidia,phy = <&phy2>;
	status = "disabled";
	};

	phy2: usb-phy@7d004000 {
	compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
	reg = <0x0 0x7d004000 0x0 0x4000>,
	<0x0 0x7d000000 0x0 0x4000>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA124_CLK_USB2>,
	<&tegra_car TEGRA124_CLK_PLL_U>,
	<&tegra_car TEGRA124_CLK_USBD>;
	clock-names = "reg", "pll_u", "utmi-pads";
	resets = <&tegra_car 58>, <&tegra_car 22>;
	reset-names = "usb", "utmi-pads";
	nvidia,hssync-start-delay = <0>;
	nvidia,idle-wait-delay = <17>;
	nvidia,elastic-limit = <16>;
	nvidia,term-range-adj = <6>;
	nvidia,xcvr-setup = <9>;
	nvidia,xcvr-lsfslew = <0>;
	nvidia,xcvr-lsrslew = <3>;
	nvidia,hssquelch-level = <2>;
	nvidia,hsdiscon-level = <5>;
	nvidia,xcvr-hsslew = <12>;
	status = "disabled";
	};

	usb@7d008000 {
	compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
	reg = <0x0 0x7d008000 0x0 0x4000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA124_CLK_USB3>;
	resets = <&tegra_car 59>;
	reset-names = "usb";
	nvidia,phy = <&phy3>;
	status = "disabled";
	};

	phy3: usb-phy@7d008000 {
	compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
	reg = <0x0 0x7d008000 0x0 0x4000>,
	<0x0 0x7d000000 0x0 0x4000>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA124_CLK_USB3>,
	<&tegra_car TEGRA124_CLK_PLL_U>,
	<&tegra_car TEGRA124_CLK_USBD>;
	clock-names = "reg", "pll_u", "utmi-pads";
	resets = <&tegra_car 59>, <&tegra_car 22>;
	reset-names = "usb", "utmi-pads";
	nvidia,hssync-start-delay = <0>;
	nvidia,idle-wait-delay = <17>;
	nvidia,elastic-limit = <16>;
	nvidia,term-range-adj = <6>;
	nvidia,xcvr-setup = <9>;
	nvidia,xcvr-lsfslew = <0>;
	nvidia,xcvr-lsrslew = <3>;
	nvidia,hssquelch-level = <2>;
	nvidia,hsdiscon-level = <5>;
	nvidia,xcvr-hsslew = <12>;
	status = "disabled";
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0>;

	clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
	<&tegra_car TEGRA124_CLK_CCLK_LP>,
	<&tegra_car TEGRA124_CLK_PLL_X>,
	<&tegra_car TEGRA124_CLK_PLL_P>,
	<&dfll>;
	clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
	/* FIXME: what's the actual transition time? */
	clock-latency = <300000>;
	};

	cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <1>;
	};

	cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <2>;
	};

	cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <3>;
	};
	};

	pmu {
	compatible = "arm,cortex-a15-pmu";
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&{/cpus/cpu@0}>,
	<&{/cpus/cpu@1}>,
	<&{/cpus/cpu@2}>,
	<&{/cpus/cpu@3}>;
	};

	thermal-zones {
	cpu {
	polling-delay-passive = <1000>;
	polling-delay = <1000>;

	thermal-sensors =
	<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;

	trips {
	cpu-shutdown-trip {
	temperature = <103000>;
	hysteresis = <0>;
	type = "critical";
	};
	cpu_throttle_trip: throttle-trip {
	temperature = <100000>;
	hysteresis = <1000>;
	type = "hot";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu_throttle_trip>;
	cooling-device = <&throttle_heavy 1 1>;
	};
	};
	};

	mem {
	polling-delay-passive = <1000>;
	polling-delay = <1000>;

	thermal-sensors =
	<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;

	trips {
	mem-shutdown-trip {
	temperature = <103000>;
	hysteresis = <0>;
	type = "critical";
	};
	};

	cooling-maps {
	/*
	* There are currently no cooling maps,
	* because there are no cooling devices.
	*/
	};
	};

	gpu {
	polling-delay-passive = <1000>;
	polling-delay = <1000>;

	thermal-sensors =
	<&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;

	trips {
	gpu-shutdown-trip {
	temperature = <101000>;
	hysteresis = <0>;
	type = "critical";
	};
	gpu_throttle_trip: throttle-trip {
	temperature = <99000>;
	hysteresis = <1000>;
	type = "hot";
	};
	};

	cooling-maps {
	map0 {
	trip = <&gpu_throttle_trip>;
	cooling-device = <&throttle_heavy 1 1>;
	};
	};
	};

	pllx {
	polling-delay-passive = <1000>;
	polling-delay = <1000>;

	thermal-sensors =
	<&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;

	trips {
	pllx-shutdown-trip {
	temperature = <103000>;
	hysteresis = <0>;
	type = "critical";
	};
	};

	cooling-maps {
	/*
	* There are currently no cooling maps,
	* because there are no cooling devices.
	*/
	};
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 13
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	interrupt-parent = <&gic>;
	};
	};
	diff --git a/sys/gnu/dts/arm/tegra20.dtsi b/sys/gnu/dts/arm/tegra20.dtsi
	index 9c58e7fcf5c0..c3b8ad53b967 100644
	--- a/sys/gnu/dts/arm/tegra20.dtsi
	+++ b/sys/gnu/dts/arm/tegra20.dtsi
	@@ -1,872 +1,874 @@
	// SPDX-License-Identifier: GPL-2.0
	#include <dt-bindings/clock/tegra20-car.h>
	#include <dt-bindings/gpio/tegra-gpio.h>
	#include <dt-bindings/memory/tegra20-mc.h>
	#include <dt-bindings/pinctrl/pinctrl-tegra.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	+#include <dt-bindings/soc/tegra-pmc.h>

	/ {
	compatible = "nvidia,tegra20";
	interrupt-parent = <&lic>;
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
	device_type = "memory";
	reg = <0 0>;
	};

	iram@40000000 {
	compatible = "mmio-sram";
	reg = <0x40000000 0x40000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x40000000 0x40000>;

	vde_pool: vde@400 {
	reg = <0x400 0x3fc00>;
	pool;
	};
	};

	host1x@50000000 {
	compatible = "nvidia,tegra20-host1x", "simple-bus";
	reg = <0x50000000 0x00024000>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
	clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
	resets = <&tegra_car 28>;
	reset-names = "host1x";

	#address-cells = <1>;
	#size-cells = <1>;

	ranges = <0x54000000 0x54000000 0x04000000>;

	mpe@54040000 {
	compatible = "nvidia,tegra20-mpe";
	reg = <0x54040000 0x00040000>;
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_MPE>;
	resets = <&tegra_car 60>;
	reset-names = "mpe";
	};

	vi@54080000 {
	compatible = "nvidia,tegra20-vi";
	reg = <0x54080000 0x00040000>;
	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_VI>;
	resets = <&tegra_car 20>;
	reset-names = "vi";
	};

	epp@540c0000 {
	compatible = "nvidia,tegra20-epp";
	reg = <0x540c0000 0x00040000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_EPP>;
	resets = <&tegra_car 19>;
	reset-names = "epp";
	};

	isp@54100000 {
	compatible = "nvidia,tegra20-isp";
	reg = <0x54100000 0x00040000>;
	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_ISP>;
	resets = <&tegra_car 23>;
	reset-names = "isp";
	};

	gr2d@54140000 {
	compatible = "nvidia,tegra20-gr2d";
	reg = <0x54140000 0x00040000>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_GR2D>;
	resets = <&tegra_car 21>;
	reset-names = "2d";
	};

	gr3d@54180000 {
	compatible = "nvidia,tegra20-gr3d";
	reg = <0x54180000 0x00040000>;
	clocks = <&tegra_car TEGRA20_CLK_GR3D>;
	resets = <&tegra_car 24>;
	reset-names = "3d";
	};

	dc@54200000 {
	compatible = "nvidia,tegra20-dc";
	reg = <0x54200000 0x00040000>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_DISP1>,
	<&tegra_car TEGRA20_CLK_PLL_P>;
	clock-names = "dc", "parent";
	resets = <&tegra_car 27>;
	reset-names = "dc";

	nvidia,head = <0>;

	rgb {
	status = "disabled";
	};
	};

	dc@54240000 {
	compatible = "nvidia,tegra20-dc";
	reg = <0x54240000 0x00040000>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_DISP2>,
	<&tegra_car TEGRA20_CLK_PLL_P>;
	clock-names = "dc", "parent";
	resets = <&tegra_car 26>;
	reset-names = "dc";

	nvidia,head = <1>;

	rgb {
	status = "disabled";
	};
	};

	hdmi@54280000 {
	compatible = "nvidia,tegra20-hdmi";
	reg = <0x54280000 0x00040000>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_HDMI>,
	<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
	clock-names = "hdmi", "parent";
	resets = <&tegra_car 51>;
	reset-names = "hdmi";
	status = "disabled";
	};

	tvo@542c0000 {
	compatible = "nvidia,tegra20-tvo";
	reg = <0x542c0000 0x00040000>;
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_TVO>;
	status = "disabled";
	};

	dsi@54300000 {
	compatible = "nvidia,tegra20-dsi";
	reg = <0x54300000 0x00040000>;
	clocks = <&tegra_car TEGRA20_CLK_DSI>;
	resets = <&tegra_car 48>;
	reset-names = "dsi";
	status = "disabled";
	};
	};

	timer@50040600 {
	compatible = "arm,cortex-a9-twd-timer";
	interrupt-parent = <&intc>;
	reg = <0x50040600 0x20>;
	interrupts = <GIC_PPI 13
	(GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_EDGE_RISING)>;
	clocks = <&tegra_car TEGRA20_CLK_TWD>;
	};

	intc: interrupt-controller@50041000 {
	compatible = "arm,cortex-a9-gic";
	reg = <0x50041000 0x1000
	0x50040100 0x0100>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&intc>;
	};

	cache-controller@50043000 {
	compatible = "arm,pl310-cache";
	reg = <0x50043000 0x1000>;
	arm,data-latency = <5 5 2>;
	arm,tag-latency = <4 4 2>;
	cache-unified;
	cache-level = <2>;
	};

	lic: interrupt-controller@60004000 {
	compatible = "nvidia,tegra20-ictlr";
	reg = <0x60004000 0x100>,
	<0x60004100 0x50>,
	<0x60004200 0x50>,
	<0x60004300 0x50>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&intc>;
	};

	timer@60005000 {
	compatible = "nvidia,tegra20-timer";
	reg = <0x60005000 0x60>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_TIMER>;
	};

	tegra_car: clock@60006000 {
	compatible = "nvidia,tegra20-car";
	reg = <0x60006000 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	flow-controller@60007000 {
	compatible = "nvidia,tegra20-flowctrl";
	reg = <0x60007000 0x1000>;
	};

	apbdma: dma@6000a000 {
	compatible = "nvidia,tegra20-apbdma";
	reg = <0x6000a000 0x1200>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
	resets = <&tegra_car 34>;
	reset-names = "dma";
	#dma-cells = <1>;
	};

	ahb@6000c000 {
	compatible = "nvidia,tegra20-ahb";
	reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
	};

	gpio: gpio@6000d000 {
	compatible = "nvidia,tegra20-gpio";
	reg = <0x6000d000 0x1000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	#interrupt-cells = <2>;
	interrupt-controller;
	/*
	gpio-ranges = <&pinmux 0 0 224>;
	*/
	};

	vde@6001a000 {
	compatible = "nvidia,tegra20-vde";
	reg = <0x6001a000 0x1000 /* Syntax Engine */
	0x6001b000 0x1000 /* Video Bitstream Engine */
	0x6001c000 0x100 /* Macroblock Engine */
	0x6001c200 0x100 /* Post-processing Engine */
	0x6001c400 0x100 /* Motion Compensation Engine */
	0x6001c600 0x100 /* Transform Engine */
	0x6001c800 0x100 /* Pixel prediction block */
	0x6001ca00 0x100 /* Video DMA */
	0x6001d800 0x300>; /* Video frame controls */
	reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
	"tfe", "ppb", "vdma", "frameid";
	iram = <&vde_pool>; /* IRAM region */
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
	<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
	interrupt-names = "sync-token", "bsev", "sxe";
	clocks = <&tegra_car TEGRA20_CLK_VDE>;
	reset-names = "vde", "mc";
	resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
	};

	apbmisc@70000800 {
	compatible = "nvidia,tegra20-apbmisc";
	reg = <0x70000800 0x64 /* Chip revision */
	0x70000008 0x04>; /* Strapping options */
	};

	pinmux: pinmux@70000014 {
	compatible = "nvidia,tegra20-pinmux";
	reg = <0x70000014 0x10 /* Tri-state registers */
	0x70000080 0x20 /* Mux registers */
	0x700000a0 0x14 /* Pull-up/down registers */
	0x70000868 0xa8>; /* Pad control registers */
	};

	das@70000c00 {
	compatible = "nvidia,tegra20-das";
	reg = <0x70000c00 0x80>;
	};

	tegra_ac97: ac97@70002000 {
	compatible = "nvidia,tegra20-ac97";
	reg = <0x70002000 0x200>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_AC97>;
	resets = <&tegra_car 3>;
	reset-names = "ac97";
	dmas = <&apbdma 12>, <&apbdma 12>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	tegra_i2s1: i2s@70002800 {
	compatible = "nvidia,tegra20-i2s";
	reg = <0x70002800 0x200>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_I2S1>;
	resets = <&tegra_car 11>;
	reset-names = "i2s";
	dmas = <&apbdma 2>, <&apbdma 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	tegra_i2s2: i2s@70002a00 {
	compatible = "nvidia,tegra20-i2s";
	reg = <0x70002a00 0x200>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_I2S2>;
	resets = <&tegra_car 18>;
	reset-names = "i2s";
	dmas = <&apbdma 1>, <&apbdma 1>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	/*
	* There are two serial driver i.e. 8250 based simple serial
	* driver and APB DMA based serial driver for higher baudrate
	* and performace. To enable the 8250 based driver, the compatible
	* is "nvidia,tegra20-uart" and to enable the APB DMA based serial
	* driver, the compatible is "nvidia,tegra20-hsuart".
	*/
	uarta: serial@70006000 {
	compatible = "nvidia,tegra20-uart";
	reg = <0x70006000 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_UARTA>;
	resets = <&tegra_car 6>;
	reset-names = "serial";
	dmas = <&apbdma 8>, <&apbdma 8>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartb: serial@70006040 {
	compatible = "nvidia,tegra20-uart";
	reg = <0x70006040 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_UARTB>;
	resets = <&tegra_car 7>;
	reset-names = "serial";
	dmas = <&apbdma 9>, <&apbdma 9>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartc: serial@70006200 {
	compatible = "nvidia,tegra20-uart";
	reg = <0x70006200 0x100>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_UARTC>;
	resets = <&tegra_car 55>;
	reset-names = "serial";
	dmas = <&apbdma 10>, <&apbdma 10>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartd: serial@70006300 {
	compatible = "nvidia,tegra20-uart";
	reg = <0x70006300 0x100>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_UARTD>;
	resets = <&tegra_car 65>;
	reset-names = "serial";
	dmas = <&apbdma 19>, <&apbdma 19>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uarte: serial@70006400 {
	compatible = "nvidia,tegra20-uart";
	reg = <0x70006400 0x100>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_UARTE>;
	resets = <&tegra_car 66>;
	reset-names = "serial";
	dmas = <&apbdma 20>, <&apbdma 20>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	nand-controller@70008000 {
	compatible = "nvidia,tegra20-nand";
	reg = <0x70008000 0x100>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
	clock-names = "nand";
	resets = <&tegra_car 13>;
	reset-names = "nand";
	assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
	assigned-clock-rates = <150000000>;
	status = "disabled";
	};

	gmi@70009000 {
	compatible = "nvidia,tegra20-gmi";
	reg = <0x70009000 0x1000>;
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0xd0000000 0xfffffff>;
	clocks = <&tegra_car TEGRA20_CLK_NOR>;
	clock-names = "gmi";
	resets = <&tegra_car 42>;
	reset-names = "gmi";
	status = "disabled";
	};

	pwm: pwm@7000a000 {
	compatible = "nvidia,tegra20-pwm";
	reg = <0x7000a000 0x100>;
	#pwm-cells = <2>;
	clocks = <&tegra_car TEGRA20_CLK_PWM>;
	resets = <&tegra_car 17>;
	reset-names = "pwm";
	status = "disabled";
	};

	rtc@7000e000 {
	compatible = "nvidia,tegra20-rtc";
	reg = <0x7000e000 0x100>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_RTC>;
	};

	i2c@7000c000 {
	compatible = "nvidia,tegra20-i2c";
	reg = <0x7000c000 0x100>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA20_CLK_I2C1>,
	<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
	clock-names = "div-clk", "fast-clk";
	resets = <&tegra_car 12>;
	reset-names = "i2c";
	dmas = <&apbdma 21>, <&apbdma 21>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000c380 {
	compatible = "nvidia,tegra20-sflash";
	reg = <0x7000c380 0x80>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA20_CLK_SPI>;
	resets = <&tegra_car 43>;
	reset-names = "spi";
	dmas = <&apbdma 11>, <&apbdma 11>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000c400 {
	compatible = "nvidia,tegra20-i2c";
	reg = <0x7000c400 0x100>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA20_CLK_I2C2>,
	<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
	clock-names = "div-clk", "fast-clk";
	resets = <&tegra_car 54>;
	reset-names = "i2c";
	dmas = <&apbdma 22>, <&apbdma 22>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000c500 {
	compatible = "nvidia,tegra20-i2c";
	reg = <0x7000c500 0x100>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA20_CLK_I2C3>,
	<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
	clock-names = "div-clk", "fast-clk";
	resets = <&tegra_car 67>;
	reset-names = "i2c";
	dmas = <&apbdma 23>, <&apbdma 23>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000d000 {
	compatible = "nvidia,tegra20-i2c-dvc";
	reg = <0x7000d000 0x200>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA20_CLK_DVC>,
	<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
	clock-names = "div-clk", "fast-clk";
	resets = <&tegra_car 47>;
	reset-names = "i2c";
	dmas = <&apbdma 24>, <&apbdma 24>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000d400 {
	compatible = "nvidia,tegra20-slink";
	reg = <0x7000d400 0x200>;
	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA20_CLK_SBC1>;
	resets = <&tegra_car 41>;
	reset-names = "spi";
	dmas = <&apbdma 15>, <&apbdma 15>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000d600 {
	compatible = "nvidia,tegra20-slink";
	reg = <0x7000d600 0x200>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA20_CLK_SBC2>;
	resets = <&tegra_car 44>;
	reset-names = "spi";
	dmas = <&apbdma 16>, <&apbdma 16>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000d800 {
	compatible = "nvidia,tegra20-slink";
	reg = <0x7000d800 0x200>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA20_CLK_SBC3>;
	resets = <&tegra_car 46>;
	reset-names = "spi";
	dmas = <&apbdma 17>, <&apbdma 17>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000da00 {
	compatible = "nvidia,tegra20-slink";
	reg = <0x7000da00 0x200>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA20_CLK_SBC4>;
	resets = <&tegra_car 68>;
	reset-names = "spi";
	dmas = <&apbdma 18>, <&apbdma 18>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	kbc@7000e200 {
	compatible = "nvidia,tegra20-kbc";
	reg = <0x7000e200 0x100>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_KBC>;
	resets = <&tegra_car 36>;
	reset-names = "kbc";
	status = "disabled";
	};

	- pmc@7000e400 {
	+ tegra_pmc: pmc@7000e400 {
	compatible = "nvidia,tegra20-pmc";
	reg = <0x7000e400 0x400>;
	clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
	clock-names = "pclk", "clk32k_in";
	+ #clock-cells = <1>;
	};

	mc: memory-controller@7000f000 {
	compatible = "nvidia,tegra20-mc-gart";
	reg = <0x7000f000 0x400 /* controller registers */
	0x58000000 0x02000000>; /* GART aperture */
	clocks = <&tegra_car TEGRA20_CLK_MC>;
	clock-names = "mc";
	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	#reset-cells = <1>;
	#iommu-cells = <0>;
	};

	memory-controller@7000f400 {
	compatible = "nvidia,tegra20-emc";
	reg = <0x7000f400 0x200>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_EMC>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	fuse@7000f800 {
	compatible = "nvidia,tegra20-efuse";
	reg = <0x7000f800 0x400>;
	clocks = <&tegra_car TEGRA20_CLK_FUSE>;
	clock-names = "fuse";
	resets = <&tegra_car 39>;
	reset-names = "fuse";
	};

	pcie@80003000 {
	compatible = "nvidia,tegra20-pcie";
	device_type = "pci";
	reg = <0x80003000 0x00000800 /* PADS registers */
	0x80003800 0x00000200 /* AFI registers */
	0x90000000 0x10000000>; /* configuration space */
	reg-names = "pads", "afi", "cs";
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
	GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
	interrupt-names = "intr", "msi";

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

	bus-range = <0x00 0xff>;
	#address-cells = <3>;
	#size-cells = <2>;

	ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
	0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
	0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
	0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
	0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */

	clocks = <&tegra_car TEGRA20_CLK_PEX>,
	<&tegra_car TEGRA20_CLK_AFI>,
	<&tegra_car TEGRA20_CLK_PLL_E>;
	clock-names = "pex", "afi", "pll_e";
	resets = <&tegra_car 70>,
	<&tegra_car 72>,
	<&tegra_car 74>;
	reset-names = "pex", "afi", "pcie_x";
	status = "disabled";

	pci@1,0 {
	device_type = "pci";
	assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
	reg = <0x000800 0 0 0 0>;
	bus-range = <0x00 0xff>;
	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	ranges;

	nvidia,num-lanes = <2>;
	};

	pci@2,0 {
	device_type = "pci";
	assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
	reg = <0x001000 0 0 0 0>;
	bus-range = <0x00 0xff>;
	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	ranges;

	nvidia,num-lanes = <2>;
	};
	};

	usb@c5000000 {
	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	reg = <0xc5000000 0x4000>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	phy_type = "utmi";
	nvidia,has-legacy-mode;
	clocks = <&tegra_car TEGRA20_CLK_USBD>;
	resets = <&tegra_car 22>;
	reset-names = "usb";
	nvidia,needs-double-reset;
	nvidia,phy = <&phy1>;
	status = "disabled";
	};

	phy1: usb-phy@c5000000 {
	compatible = "nvidia,tegra20-usb-phy";
	reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA20_CLK_USBD>,
	<&tegra_car TEGRA20_CLK_PLL_U>,
	<&tegra_car TEGRA20_CLK_CLK_M>,
	<&tegra_car TEGRA20_CLK_USBD>;
	clock-names = "reg", "pll_u", "timer", "utmi-pads";
	resets = <&tegra_car 22>, <&tegra_car 22>;
	reset-names = "usb", "utmi-pads";
	nvidia,has-legacy-mode;
	nvidia,hssync-start-delay = <9>;
	nvidia,idle-wait-delay = <17>;
	nvidia,elastic-limit = <16>;
	nvidia,term-range-adj = <6>;
	nvidia,xcvr-setup = <9>;
	nvidia,xcvr-lsfslew = <1>;
	nvidia,xcvr-lsrslew = <1>;
	nvidia,has-utmi-pad-registers;
	status = "disabled";
	};

	usb@c5004000 {
	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	reg = <0xc5004000 0x4000>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	phy_type = "ulpi";
	clocks = <&tegra_car TEGRA20_CLK_USB2>;
	resets = <&tegra_car 58>;
	reset-names = "usb";
	nvidia,phy = <&phy2>;
	status = "disabled";
	};

	phy2: usb-phy@c5004000 {
	compatible = "nvidia,tegra20-usb-phy";
	reg = <0xc5004000 0x4000>;
	phy_type = "ulpi";
	clocks = <&tegra_car TEGRA20_CLK_USB2>,
	<&tegra_car TEGRA20_CLK_PLL_U>,
	<&tegra_car TEGRA20_CLK_CDEV2>;
	clock-names = "reg", "pll_u", "ulpi-link";
	resets = <&tegra_car 58>, <&tegra_car 22>;
	reset-names = "usb", "utmi-pads";
	status = "disabled";
	};

	usb@c5008000 {
	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	reg = <0xc5008000 0x4000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA20_CLK_USB3>;
	resets = <&tegra_car 59>;
	reset-names = "usb";
	nvidia,phy = <&phy3>;
	status = "disabled";
	};

	phy3: usb-phy@c5008000 {
	compatible = "nvidia,tegra20-usb-phy";
	reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA20_CLK_USB3>,
	<&tegra_car TEGRA20_CLK_PLL_U>,
	<&tegra_car TEGRA20_CLK_CLK_M>,
	<&tegra_car TEGRA20_CLK_USBD>;
	clock-names = "reg", "pll_u", "timer", "utmi-pads";
	resets = <&tegra_car 59>, <&tegra_car 22>;
	reset-names = "usb", "utmi-pads";
	nvidia,hssync-start-delay = <9>;
	nvidia,idle-wait-delay = <17>;
	nvidia,elastic-limit = <16>;
	nvidia,term-range-adj = <6>;
	nvidia,xcvr-setup = <9>;
	nvidia,xcvr-lsfslew = <2>;
	nvidia,xcvr-lsrslew = <2>;
	status = "disabled";
	};

	sdhci@c8000000 {
	compatible = "nvidia,tegra20-sdhci";
	reg = <0xc8000000 0x200>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
	resets = <&tegra_car 14>;
	reset-names = "sdhci";
	status = "disabled";
	};

	sdhci@c8000200 {
	compatible = "nvidia,tegra20-sdhci";
	reg = <0xc8000200 0x200>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
	resets = <&tegra_car 9>;
	reset-names = "sdhci";
	status = "disabled";
	};

	sdhci@c8000400 {
	compatible = "nvidia,tegra20-sdhci";
	reg = <0xc8000400 0x200>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
	resets = <&tegra_car 69>;
	reset-names = "sdhci";
	status = "disabled";
	};

	sdhci@c8000600 {
	compatible = "nvidia,tegra20-sdhci";
	reg = <0xc8000600 0x200>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
	resets = <&tegra_car 15>;
	reset-names = "sdhci";
	status = "disabled";
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <0>;
	clocks = <&tegra_car TEGRA20_CLK_CCLK>;
	};

	cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <1>;
	clocks = <&tegra_car TEGRA20_CLK_CCLK>;
	};
	};

	pmu {
	compatible = "arm,cortex-a9-pmu";
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&{/cpus/cpu@0}>,
	<&{/cpus/cpu@1}>;
	};
	};
	diff --git a/sys/gnu/dts/arm/tegra30-apalis-v1.1.dtsi b/sys/gnu/dts/arm/tegra30-apalis-v1.1.dtsi
	index 8b7a827d604d..387b17458e22 100644
	--- a/sys/gnu/dts/arm/tegra30-apalis-v1.1.dtsi
	+++ b/sys/gnu/dts/arm/tegra30-apalis-v1.1.dtsi
	@@ -1,1195 +1,1201 @@
	// SPDX-License-Identifier: GPL-2.0 OR MIT
	#include "tegra30.dtsi"

	/*
	* Toradex Apalis T30 Module Device Tree
	* Compatible for Revisions 1GB: V1.1A, V1.1B; 1GB IT: V1.1A, V1.1B;
	* 2GB: V1.1A, V1.1B
	*/
	/ {
	memory@80000000 {
	reg = <0x80000000 0x40000000>;
	};

	pcie@3000 {
	status = "okay";
	avdd-pexa-supply = <&vdd2_reg>;
	avdd-pexb-supply = <&vdd2_reg>;
	avdd-pex-pll-supply = <&vdd2_reg>;
	avdd-plle-supply = <&ldo6_reg>;
	hvdd-pex-supply = <&reg_module_3v3>;
	vddio-pex-ctl-supply = <&reg_module_3v3>;
	vdd-pexa-supply = <&vdd2_reg>;
	vdd-pexb-supply = <&vdd2_reg>;

	/* Apalis type specific */
	pci@1,0 {
	nvidia,num-lanes = <4>;
	};

	/* Apalis PCIe */
	pci@2,0 {
	nvidia,num-lanes = <1>;
	};

	/* I210/I211 Gigabit Ethernet Controller (on-module) */
	pci@3,0 {
	status = "okay";
	nvidia,num-lanes = <1>;

	pcie@0 {
	reg = <0 0 0 0 0>;
	local-mac-address = [00 00 00 00 00 00];
	};
	};
	};

	host1x@50000000 {
	hdmi@54280000 {
	nvidia,ddc-i2c-bus = <&hdmi_ddc>;
	nvidia,hpd-gpio =
	<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
	pll-supply = <&reg_1v8_avdd_hdmi_pll>;
	vdd-supply = <&reg_3v3_avdd_hdmi>;
	};
	};

	pinmux@70000868 {
	pinctrl-names = "default";
	pinctrl-0 = <&state_default>;

	state_default: pinmux {
	/* Analogue Audio (On-module) */
	clk1-out-pw4 {
	nvidia,pins = "clk1_out_pw4";
	nvidia,function = "extperiph1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap3-fs-pp0 {
	nvidia,pins = "dap3_fs_pp0",
	"dap3_sclk_pp3",
	"dap3_din_pp1",
	"dap3_dout_pp2";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis BKL1_ON */
	pv2 {
	nvidia,pins = "pv2";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis BKL1_PWM */
	uart3-rts-n-pc0 {
	nvidia,pins = "uart3_rts_n_pc0";
	nvidia,function = "pwm0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	/* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
	uart3-cts-n-pa1 {
	nvidia,pins = "uart3_cts_n_pa1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis CAN1 on SPI6 */
	spi2-cs0-n-px3 {
	nvidia,pins = "spi2_cs0_n_px3",
	"spi2_miso_px1",
	"spi2_mosi_px0",
	"spi2_sck_px2";
	nvidia,function = "spi6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	/* CAN_INT1 */
	spi2-cs1-n-pw2 {
	nvidia,pins = "spi2_cs1_n_pw2";
	nvidia,function = "spi3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis CAN2 on SPI4 */
	gmi-a16-pj7 {
	nvidia,pins = "gmi_a16_pj7",
	"gmi_a17_pb0",
	"gmi_a18_pb1",
	"gmi_a19_pk7";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	/* CAN_INT2 */
	spi2-cs2-n-pw3 {
	nvidia,pins = "spi2_cs2_n_pw3";
	nvidia,function = "spi3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis Digital Audio */
	clk1-req-pee2 {
	nvidia,pins = "clk1_req_pee2";
	nvidia,function = "hda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	clk2-out-pw5 {
	nvidia,pins = "clk2_out_pw5";
	nvidia,function = "extperiph2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap1-fs-pn0 {
	nvidia,pins = "dap1_fs_pn0",
	"dap1_din_pn1",
	"dap1_dout_pn2",
	"dap1_sclk_pn3";
	nvidia,function = "hda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis GPIO */
	kb-col0-pq0 {
	nvidia,pins = "kb_col0_pq0",
	"kb_col1_pq1",
	"kb_row10_ps2",
	"kb_row11_ps3",
	"kb_row12_ps4",
	"kb_row13_ps5",
	"kb_row14_ps6",
	"kb_row15_ps7";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	/* Multiplexed and therefore disabled */
	owr {
	nvidia,pins = "owr";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis HDMI1 */
	hdmi-cec-pee3 {
	nvidia,pins = "hdmi_cec_pee3";
	nvidia,function = "cec";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	hdmi-int-pn7 {
	nvidia,pins = "hdmi_int_pn7";
	nvidia,function = "hdmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis I2C1 */
	gen1-i2c-scl-pc4 {
	nvidia,pins = "gen1_i2c_scl_pc4",
	"gen1_i2c_sda_pc5";
	nvidia,function = "i2c1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis I2C2 (DDC) */
	ddc-scl-pv4 {
	nvidia,pins = "ddc_scl_pv4",
	"ddc_sda_pv5";
	nvidia,function = "i2c4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis I2C3 (CAM) */
	cam-i2c-scl-pbb1 {
	nvidia,pins = "cam_i2c_scl_pbb1",
	"cam_i2c_sda_pbb2";
	nvidia,function = "i2c3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis LCD1 */
	lcd-d0-pe0 {
	nvidia,pins = "lcd_d0_pe0",
	"lcd_d1_pe1",
	"lcd_d2_pe2",
	"lcd_d3_pe3",
	"lcd_d4_pe4",
	"lcd_d5_pe5",
	"lcd_d6_pe6",
	"lcd_d7_pe7",
	"lcd_d8_pf0",
	"lcd_d9_pf1",
	"lcd_d10_pf2",
	"lcd_d11_pf3",
	"lcd_d12_pf4",
	"lcd_d13_pf5",
	"lcd_d14_pf6",
	"lcd_d15_pf7",
	"lcd_d16_pm0",
	"lcd_d17_pm1",
	"lcd_d18_pm2",
	"lcd_d19_pm3",
	"lcd_d20_pm4",
	"lcd_d21_pm5",
	"lcd_d22_pm6",
	"lcd_d23_pm7",
	"lcd_de_pj1",
	"lcd_hsync_pj3",
	"lcd_pclk_pb3",
	"lcd_vsync_pj4";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis MMC1 */
	sdmmc3-clk-pa6 {
	nvidia,pins = "sdmmc3_clk_pa6";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3-dat0-pb7 {
	nvidia,pins = "sdmmc3_cmd_pa7",
	"sdmmc3_dat0_pb7",
	"sdmmc3_dat1_pb6",
	"sdmmc3_dat2_pb5",
	"sdmmc3_dat3_pb4",
	"sdmmc3_dat4_pd1",
	"sdmmc3_dat5_pd0",
	"sdmmc3_dat6_pd3",
	"sdmmc3_dat7_pd4";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	/* Apalis MMC1_CD# */
	pv3 {
	nvidia,pins = "pv3";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis Parallel Camera */
	cam-mclk-pcc0 {
	nvidia,pins = "cam_mclk_pcc0";
	nvidia,function = "vi_alt3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	vi-vsync-pd6 {
	nvidia,pins = "vi_d0_pt4",
	"vi_d1_pd5",
	"vi_d2_pl0",
	"vi_d3_pl1",
	"vi_d4_pl2",
	"vi_d5_pl3",
	"vi_d6_pl4",
	"vi_d7_pl5",
	"vi_d8_pl6",
	"vi_d9_pl7",
	"vi_d10_pt2",
	"vi_d11_pt3",
	"vi_hsync_pd7",
	"vi_pclk_pt0",
	"vi_vsync_pd6";
	nvidia,function = "vi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	/* Multiplexed and therefore disabled */
	kb-col2-pq2 {
	nvidia,pins = "kb_col2_pq2",
	"kb_col3_pq3",
	"kb_col4_pq4",
	"kb_row4_pr4";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row0-pr0 {
	nvidia,pins = "kb_row0_pr0",
	"kb_row1_pr1",
	"kb_row2_pr2",
	"kb_row3_pr3";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row5-pr5 {
	nvidia,pins = "kb_row5_pr5",
	"kb_row6_pr6",
	"kb_row7_pr7";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	/*
	* VI level-shifter direction
	* (pull-down => default direction input)
	*/
	vi-mclk-pt1 {
	nvidia,pins = "vi_mclk_pt1";
	nvidia,function = "vi_alt3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis PWM1 */
	pu6 {
	nvidia,pins = "pu6";
	nvidia,function = "pwm3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis PWM2 */
	pu5 {
	nvidia,pins = "pu5";
	nvidia,function = "pwm2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis PWM3 */
	pu4 {
	nvidia,pins = "pu4";
	nvidia,function = "pwm1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis PWM4 */
	pu3 {
	nvidia,pins = "pu3";
	nvidia,function = "pwm0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis RESET_MOCI# */
	gmi-rst-n-pi4 {
	nvidia,pins = "gmi_rst_n_pi4";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis SATA1_ACT# */
	pex-l0-prsnt-n-pdd0 {
	nvidia,pins = "pex_l0_prsnt_n_pdd0";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis SD1 */
	sdmmc1-clk-pz0 {
	nvidia,pins = "sdmmc1_clk_pz0";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1-cmd-pz1 {
	nvidia,pins = "sdmmc1_cmd_pz1",
	"sdmmc1_dat0_py7",
	"sdmmc1_dat1_py6",
	"sdmmc1_dat2_py5",
	"sdmmc1_dat3_py4";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	/* Apalis SD1_CD# */
	clk2-req-pcc5 {
	nvidia,pins = "clk2_req_pcc5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis SPDIF1 */
	spdif-out-pk5 {
	nvidia,pins = "spdif_out_pk5",
	"spdif_in_pk6";
	nvidia,function = "spdif";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis SPI1 */
	spi1-sck-px5 {
	nvidia,pins = "spi1_sck_px5",
	"spi1_mosi_px4",
	"spi1_miso_px7",
	"spi1_cs0_n_px6";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis SPI2 */
	lcd-sck-pz4 {
	nvidia,pins = "lcd_sck_pz4",
	"lcd_sdout_pn5",
	"lcd_sdin_pz2",
	"lcd_cs0_n_pn4";
	nvidia,function = "spi5";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/*
	* Apalis TS (Low-speed type specific)
	* pins may be used as GPIOs
	*/
	kb-col5-pq5 {
	nvidia,pins = "kb_col5_pq5";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb-col6-pq6 {
	nvidia,pins = "kb_col6_pq6",
	"kb_col7_pq7",
	"kb_row8_ps0",
	"kb_row9_ps1";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis UART1 */
	ulpi-data0 {
	nvidia,pins = "ulpi_data0_po1",
	"ulpi_data1_po2",
	"ulpi_data2_po3",
	"ulpi_data3_po4",
	"ulpi_data4_po5",
	"ulpi_data5_po6",
	"ulpi_data6_po7",
	"ulpi_data7_po0";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis UART2 */
	ulpi-clk-py0 {
	nvidia,pins = "ulpi_clk_py0",
	"ulpi_dir_py1",
	"ulpi_nxt_py2",
	"ulpi_stp_py3";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis UART3 */
	uart2-rxd-pc3 {
	nvidia,pins = "uart2_rxd_pc3",
	"uart2_txd_pc2";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis UART4 */
	uart3-rxd-pw7 {
	nvidia,pins = "uart3_rxd_pw7",
	"uart3_txd_pw6";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis USBH_EN */
	pex-l0-rst-n-pdd1 {
	nvidia,pins = "pex_l0_rst_n_pdd1";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis USBH_OC# */
	pex-l0-clkreq-n-pdd2 {
	nvidia,pins = "pex_l0_clkreq_n_pdd2";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis USBO1_EN */
	gen2-i2c-scl-pt5 {
	nvidia,pins = "gen2_i2c_scl_pt5";
	nvidia,function = "rsvd4";
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis USBO1_OC# */
	gen2-i2c-sda-pt6 {
	nvidia,pins = "gen2_i2c_sda_pt6";
	nvidia,function = "rsvd4";
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis VGA1 not supported and therefore disabled */
	crt-hsync-pv6 {
	nvidia,pins = "crt_hsync_pv6",
	"crt_vsync_pv7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis WAKE1_MICO */
	pv1 {
	nvidia,pins = "pv1";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* eMMC (On-module) */
	sdmmc4-clk-pcc4 {
	nvidia,pins = "sdmmc4_clk_pcc4",
	"sdmmc4_cmd_pt7",
	"sdmmc4_rst_n_pcc3";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-dat0-paa0 {
	nvidia,pins = "sdmmc4_dat0_paa0",
	"sdmmc4_dat1_paa1",
	"sdmmc4_dat2_paa2",
	"sdmmc4_dat3_paa3",
	"sdmmc4_dat4_paa4",
	"sdmmc4_dat5_paa5",
	"sdmmc4_dat6_paa6",
	"sdmmc4_dat7_paa7";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* EN_+3.3_SDMMC3 */
	uart2-cts-n-pj5 {
	nvidia,pins = "uart2_cts_n_pj5";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */
	pex-l2-prsnt-n-pdd7 {
	nvidia,pins = "pex_l2_prsnt_n_pdd7",
	"pex_l2_rst_n_pcc6";
	nvidia,function = "pcie";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	/* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */
	pex-wake-n-pdd3 {
	nvidia,pins = "pex_wake_n_pdd3",
	"pex_l2_clkreq_n_pcc7";
	nvidia,function = "pcie";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	/* LAN i210/i211 SMB_ALERT_N (On-module) */
	sys-clk-req-pz5 {
	nvidia,pins = "sys_clk_req_pz5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* LVDS Transceiver Configuration */
	pbb0 {
	nvidia,pins = "pbb0",
	"pbb7",
	"pcc1",
	"pcc2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pbb3 {
	nvidia,pins = "pbb3",
	"pbb4",
	"pbb5",
	"pbb6";
	nvidia,function = "displayb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Not connected and therefore disabled */
	clk-32k-out-pa0 {
	nvidia,pins = "clk3_out_pee0",
	"clk3_req_pee1",
	"clk_32k_out_pa0",
	"dap4_din_pp5",
	"dap4_dout_pp6",
	"dap4_fs_pp4",
	"dap4_sclk_pp7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap2-fs-pa2 {
	nvidia,pins = "dap2_fs_pa2",
	"dap2_sclk_pa3",
	"dap2_din_pa4",
	"dap2_dout_pa5",
	"lcd_dc0_pn6",
	"lcd_m1_pw1",
	"lcd_pwr1_pc1",
	"pex_l1_clkreq_n_pdd6",
	"pex_l1_prsnt_n_pdd4",
	"pex_l1_rst_n_pdd5";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi-ad0-pg0 {
	nvidia,pins = "gmi_ad0_pg0",
	"gmi_ad2_pg2",
	"gmi_ad3_pg3",
	"gmi_ad4_pg4",
	"gmi_ad5_pg5",
	"gmi_ad6_pg6",
	"gmi_ad7_pg7",
	"gmi_ad8_ph0",
	"gmi_ad9_ph1",
	"gmi_ad10_ph2",
	"gmi_ad11_ph3",
	"gmi_ad12_ph4",
	"gmi_ad13_ph5",
	"gmi_ad14_ph6",
	"gmi_ad15_ph7",
	"gmi_adv_n_pk0",
	"gmi_clk_pk1",
	"gmi_cs4_n_pk2",
	"gmi_cs2_n_pk3",
	"gmi_dqs_pi2",
	"gmi_iordy_pi5",
	"gmi_oe_n_pi1",
	"gmi_wait_pi7",
	"gmi_wr_n_pi0",
	"lcd_cs1_n_pw0",
	"pu0",
	"pu1",
	"pu2";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi-cs0-n-pj0 {
	nvidia,pins = "gmi_cs0_n_pj0",
	"gmi_cs1_n_pj2",
	"gmi_cs3_n_pk4";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi-cs6-n-pi3 {
	nvidia,pins = "gmi_cs6_n_pi3";
	nvidia,function = "sata";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi-cs7-n-pi6 {
	nvidia,pins = "gmi_cs7_n_pi6";
	nvidia,function = "gmi_alt";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	lcd-pwr0-pb2 {
	nvidia,pins = "lcd_pwr0_pb2",
	"lcd_pwr2_pc6",
	"lcd_wr_n_pz3";
	nvidia,function = "hdcp";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart2-rts-n-pj6 {
	nvidia,pins = "uart2_rts_n_pj6";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Power I2C (On-module) */
	pwr-i2c-scl-pz6 {
	nvidia,pins = "pwr_i2c_scl_pz6",
	"pwr_i2c_sda_pz7";
	nvidia,function = "i2cpwr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};

	/*
	* THERMD_ALERT#, unlatched I2C address pin of LM95245
	* temperature sensor therefore requires disabling for
	* now
	*/
	lcd-dc1-pd2 {
	nvidia,pins = "lcd_dc1_pd2";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* TOUCH_PEN_INT# (On-module) */
	pv0 {
	nvidia,pins = "pv0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	};
	};

	serial@70006040 {
	compatible = "nvidia,tegra30-hsuart";
	};

	serial@70006200 {
	compatible = "nvidia,tegra30-hsuart";
	};

	serial@70006300 {
	compatible = "nvidia,tegra30-hsuart";
	};

	hdmi_ddc: i2c@7000c700 {
	clock-frequency = <10000>;
	};

	/*
	* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
	* touch screen controller
	*/
	i2c@7000d000 {
	status = "okay";
	clock-frequency = <100000>;

	/* SGTL5000 audio codec */
	sgtl5000: codec@a {
	compatible = "fsl,sgtl5000";
	reg = <0x0a>;
	VDDA-supply = <&reg_module_3v3_audio>;
	VDDD-supply = <&reg_1v8_vio>;
	VDDIO-supply = <&reg_module_3v3>;
	clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
	};

	pmic: pmic@2d {
	compatible = "ti,tps65911";
	reg = <0x2d>;

	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <2>;
	interrupt-controller;

	ti,system-power-controller;

	#gpio-cells = <2>;
	gpio-controller;

	vcc1-supply = <&reg_module_3v3>;
	vcc2-supply = <&reg_module_3v3>;
	vcc3-supply = <&reg_1v8_vio>;
	vcc4-supply = <&reg_module_3v3>;
	vcc5-supply = <&reg_module_3v3>;
	vcc6-supply = <&reg_1v8_vio>;
	vcc7-supply = <&reg_5v0_charge_pump>;
	vccio-supply = <&reg_module_3v3>;

	regulators {
	vdd1_reg: vdd1 {
	regulator-name = "+V1.35_VDDIO_DDR";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	};

	vdd2_reg: vdd2 {
	regulator-name = "+V1.05";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	};

	vddctrl_reg: vddctrl {
	regulator-name = "+V1.0_VDD_CPU";
	regulator-min-microvolt = <1150000>;
	regulator-max-microvolt = <1150000>;
	regulator-always-on;
	};

	reg_1v8_vio: vio {
	regulator-name = "+V1.8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	/*
	* 1.8 volt +VDDIO_SDMMC3 in case EN_+3.3_SDMMC3
	* is off
	*/
	vddio_sdmmc_1v8_reg: ldo1 {
	regulator-name = "+VDDIO_SDMMC3_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	/*
	* EN_+V3.3 switching via FET:
	* +V3.3_AUDIO_AVDD_S, +V3.3
	* see also +V3.3 fixed supply
	*/
	ldo2_reg: ldo2 {
	regulator-name = "EN_+V3.3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	ldo3_reg: ldo3 {
	regulator-name = "+V1.2_CSI";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	ldo4_reg: ldo4 {
	regulator-name = "+V1.2_VDD_RTC";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	/*
	* +V2.8_AVDD_VDAC:
	* only required for (unsupported) analog RGB
	*/
	ldo5_reg: ldo5 {
	regulator-name = "+V2.8_AVDD_VDAC";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-always-on;
	};

	/*
	* +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
	* but LDO6 can't set voltage in 50mV
	* granularity
	*/
	ldo6_reg: ldo6 {
	regulator-name = "+V1.05_AVDD_PLLE";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	};

	ldo7_reg: ldo7 {
	regulator-name = "+V1.2_AVDD_PLL";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	ldo8_reg: ldo8 {
	regulator-name = "+V1.0_VDD_DDR_HS";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};
	};
	};

	/* STMPE811 touch screen controller */
	touchscreen@41 {
	compatible = "st,stmpe811";
	reg = <0x41>;
	irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;
	id = <0>;
	blocks = <0x5>;
	irq-trigger = <0x1>;
	/* 3.25 MHz ADC clock speed */
	st,adc-freq = <1>;
	/* 12-bit ADC */
	st,mod-12b = <1>;
	/* internal ADC reference */
	st,ref-sel = <0>;
	/* ADC converstion time: 80 clocks */
	st,sample-time = <4>;

	stmpe_touchscreen {
	compatible = "st,stmpe-ts";
	/* 8 sample average control */
	st,ave-ctrl = <3>;
	/* 7 length fractional part in z */
	st,fraction-z = <7>;
	/*
	* 50 mA typical 80 mA max touchscreen drivers
	* current limit value
	*/
	st,i-drive = <1>;
	/* 1 ms panel driver settling time */
	st,settling = <3>;
	/* 5 ms touch detect interrupt delay */
	st,touch-det-delay = <5>;
	};

	stmpe_adc {
	compatible = "st,stmpe-adc";
	/* forbid to use ADC channels 3-0 (touch) */
	st,norequest-mask = <0x0F>;
	};
	};

	/*
	* LM95245 temperature sensor
	* Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
	*/
	temp-sensor@4c {
	compatible = "national,lm95245";
	reg = <0x4c>;
	};

	/* SW: +V1.2_VDD_CORE */
	regulator@60 {
	compatible = "ti,tps62362";
	reg = <0x60>;

	regulator-name = "tps62362-vout";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1400000>;
	regulator-boot-on;
	regulator-always-on;
	ti,vsel0-state-low;
	/* VSEL1: EN_CORE_DVFS_N low for DVFS */
	ti,vsel1-state-low;
	};
	};

	/* SPI4: CAN2 */
	spi@7000da00 {
	status = "okay";
	spi-max-frequency = <10000000>;

	can@1 {
	compatible = "microchip,mcp2515";
	reg = <1>;
	clocks = <&clk16m>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
	spi-max-frequency = <10000000>;
	};
	};

	/* SPI6: CAN1 */
	spi@7000de00 {
	status = "okay";
	spi-max-frequency = <10000000>;

	can@0 {
	compatible = "microchip,mcp2515";
	reg = <0>;
	clocks = <&clk16m>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_FALLING>;
	spi-max-frequency = <10000000>;
	};
	};

	pmc@7000e400 {
	nvidia,invert-interrupt;
	nvidia,suspend-mode = <1>;
	nvidia,cpu-pwr-good-time = <5000>;
	nvidia,cpu-pwr-off-time = <5000>;
	nvidia,core-pwr-good-time = <3845 3845>;
	nvidia,core-pwr-off-time = <0>;
	nvidia,core-power-req-active-high;
	nvidia,sys-clock-req-active-high;

	/* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
	i2c-thermtrip {
	nvidia,i2c-controller-id = <4>;
	nvidia,bus-addr = <0x2d>;
	nvidia,reg-addr = <0x3f>;
	nvidia,reg-data = <0x1>;
	};
	};

	hda@70030000 {
	status = "okay";
	};

	ahub@70080000 {
	i2s@70080500 {
	status = "okay";
	};
	};

	/* eMMC */
	sdhci@78000600 {
	status = "okay";
	bus-width = <8>;
	non-removable;
	vmmc-supply = <&reg_module_3v3>; /* VCC */
	vqmmc-supply = <&reg_1v8_vio>; /* VCCQ */
	mmc-ddr-1_8v;
	};

	clk32k_in: xtal1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};

	clk16m: osc4 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <16000000>;
	};

	reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
	compatible = "regulator-fixed";
	regulator-name = "+V1.8_AVDD_HDMI_PLL";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	enable-active-high;
	gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
	vin-supply = <&reg_1v8_vio>;
	};

	reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3_AVDD_HDMI";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	enable-active-high;
	gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
	vin-supply = <&reg_module_3v3>;
	};

	reg_5v0_charge_pump: regulator-5v0-charge-pump {
	compatible = "regulator-fixed";
	regulator-name = "+V5.0";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	reg_module_3v3: regulator-module-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_module_3v3_audio: regulator-module-3v3-audio {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3_AUDIO_AVDD_S";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	sound {
	compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
	"nvidia,tegra-audio-sgtl5000";
	nvidia,model = "Toradex Apalis T30";
	nvidia,audio-routing =
	"Headphone Jack", "HP_OUT",
	"LINE_IN", "Line In Jack",
	"MIC_IN", "Mic Jack";
	nvidia,i2s-controller = <&tegra_i2s2>;
	nvidia,audio-codec = <&sgtl5000>;
	clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
	<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
	- <&tegra_car TEGRA30_CLK_EXTERN1>;
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	clock-names = "pll_a", "pll_a_out0", "mclk";
	+
	+ assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	+
	+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
	+ <&tegra_car TEGRA30_CLK_EXTERN1>;
	};
	};
	diff --git a/sys/gnu/dts/arm/tegra30-apalis.dtsi b/sys/gnu/dts/arm/tegra30-apalis.dtsi
	index c18f6f61d764..6648506f3aa4 100644
	--- a/sys/gnu/dts/arm/tegra30-apalis.dtsi
	+++ b/sys/gnu/dts/arm/tegra30-apalis.dtsi
	@@ -1,1177 +1,1183 @@
	// SPDX-License-Identifier: GPL-2.0
	#include "tegra30.dtsi"

	/*
	* Toradex Apalis T30 Module Device Tree
	* Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C, V1.0E
	*/
	/ {
	memory@80000000 {
	reg = <0x80000000 0x40000000>;
	};

	pcie@3000 {
	status = "okay";
	avdd-pexa-supply = <&vdd2_reg>;
	avdd-pexb-supply = <&vdd2_reg>;
	avdd-pex-pll-supply = <&vdd2_reg>;
	avdd-plle-supply = <&ldo6_reg>;
	hvdd-pex-supply = <&reg_module_3v3>;
	vddio-pex-ctl-supply = <&reg_module_3v3>;
	vdd-pexa-supply = <&vdd2_reg>;
	vdd-pexb-supply = <&vdd2_reg>;

	/* Apalis type specific */
	pci@1,0 {
	nvidia,num-lanes = <4>;
	};

	/* Apalis PCIe */
	pci@2,0 {
	nvidia,num-lanes = <1>;
	};

	/* I210/I211 Gigabit Ethernet Controller (on-module) */
	pci@3,0 {
	status = "okay";
	nvidia,num-lanes = <1>;

	pcie@0 {
	reg = <0 0 0 0 0>;
	local-mac-address = [00 00 00 00 00 00];
	};
	};
	};

	host1x@50000000 {
	hdmi@54280000 {
	nvidia,ddc-i2c-bus = <&hdmi_ddc>;
	nvidia,hpd-gpio =
	<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
	pll-supply = <&reg_1v8_avdd_hdmi_pll>;
	vdd-supply = <&reg_3v3_avdd_hdmi>;
	};
	};

	pinmux@70000868 {
	pinctrl-names = "default";
	pinctrl-0 = <&state_default>;

	state_default: pinmux {
	/* Analogue Audio (On-module) */
	clk1-out-pw4 {
	nvidia,pins = "clk1_out_pw4";
	nvidia,function = "extperiph1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap3-fs-pp0 {
	nvidia,pins = "dap3_fs_pp0",
	"dap3_sclk_pp3",
	"dap3_din_pp1",
	"dap3_dout_pp2";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis BKL1_ON */
	pv2 {
	nvidia,pins = "pv2";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis BKL1_PWM */
	uart3-rts-n-pc0 {
	nvidia,pins = "uart3_rts_n_pc0";
	nvidia,function = "pwm0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	/* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
	uart3-cts-n-pa1 {
	nvidia,pins = "uart3_cts_n_pa1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis CAN1 on SPI6 */
	spi2-cs0-n-px3 {
	nvidia,pins = "spi2_cs0_n_px3",
	"spi2_miso_px1",
	"spi2_mosi_px0",
	"spi2_sck_px2";
	nvidia,function = "spi6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	/* CAN_INT1 */
	spi2-cs1-n-pw2 {
	nvidia,pins = "spi2_cs1_n_pw2";
	nvidia,function = "spi3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis CAN2 on SPI4 */
	gmi-a16-pj7 {
	nvidia,pins = "gmi_a16_pj7",
	"gmi_a17_pb0",
	"gmi_a18_pb1",
	"gmi_a19_pk7";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	/* CAN_INT2 */
	spi2-cs2-n-pw3 {
	nvidia,pins = "spi2_cs2_n_pw3";
	nvidia,function = "spi3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis Digital Audio */
	clk1-req-pee2 {
	nvidia,pins = "clk1_req_pee2";
	nvidia,function = "hda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	clk2-out-pw5 {
	nvidia,pins = "clk2_out_pw5";
	nvidia,function = "extperiph2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap1-fs-pn0 {
	nvidia,pins = "dap1_fs_pn0",
	"dap1_din_pn1",
	"dap1_dout_pn2",
	"dap1_sclk_pn3";
	nvidia,function = "hda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis GPIO */
	kb-col0-pq0 {
	nvidia,pins = "kb_col0_pq0",
	"kb_col1_pq1",
	"kb_row10_ps2",
	"kb_row11_ps3",
	"kb_row12_ps4",
	"kb_row13_ps5",
	"kb_row14_ps6",
	"kb_row15_ps7";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	/* Multiplexed and therefore disabled */
	owr {
	nvidia,pins = "owr";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis HDMI1 */
	hdmi-cec-pee3 {
	nvidia,pins = "hdmi_cec_pee3";
	nvidia,function = "cec";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	hdmi-int-pn7 {
	nvidia,pins = "hdmi_int_pn7";
	nvidia,function = "hdmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis I2C1 */
	gen1-i2c-scl-pc4 {
	nvidia,pins = "gen1_i2c_scl_pc4",
	"gen1_i2c_sda_pc5";
	nvidia,function = "i2c1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis I2C2 (DDC) */
	ddc-scl-pv4 {
	nvidia,pins = "ddc_scl_pv4",
	"ddc_sda_pv5";
	nvidia,function = "i2c4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis I2C3 (CAM) */
	cam-i2c-scl-pbb1 {
	nvidia,pins = "cam_i2c_scl_pbb1",
	"cam_i2c_sda_pbb2";
	nvidia,function = "i2c3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis LCD1 */
	lcd-d0-pe0 {
	nvidia,pins = "lcd_d0_pe0",
	"lcd_d1_pe1",
	"lcd_d2_pe2",
	"lcd_d3_pe3",
	"lcd_d4_pe4",
	"lcd_d5_pe5",
	"lcd_d6_pe6",
	"lcd_d7_pe7",
	"lcd_d8_pf0",
	"lcd_d9_pf1",
	"lcd_d10_pf2",
	"lcd_d11_pf3",
	"lcd_d12_pf4",
	"lcd_d13_pf5",
	"lcd_d14_pf6",
	"lcd_d15_pf7",
	"lcd_d16_pm0",
	"lcd_d17_pm1",
	"lcd_d18_pm2",
	"lcd_d19_pm3",
	"lcd_d20_pm4",
	"lcd_d21_pm5",
	"lcd_d22_pm6",
	"lcd_d23_pm7",
	"lcd_de_pj1",
	"lcd_hsync_pj3",
	"lcd_pclk_pb3",
	"lcd_vsync_pj4";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis MMC1 */
	sdmmc3-clk-pa6 {
	nvidia,pins = "sdmmc3_clk_pa6";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3-dat0-pb7 {
	nvidia,pins = "sdmmc3_cmd_pa7",
	"sdmmc3_dat0_pb7",
	"sdmmc3_dat1_pb6",
	"sdmmc3_dat2_pb5",
	"sdmmc3_dat3_pb4",
	"sdmmc3_dat4_pd1",
	"sdmmc3_dat5_pd0",
	"sdmmc3_dat6_pd3",
	"sdmmc3_dat7_pd4";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	/* Apalis MMC1_CD# */
	pv3 {
	nvidia,pins = "pv3";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis Parallel Camera */
	cam-mclk-pcc0 {
	nvidia,pins = "cam_mclk_pcc0";
	nvidia,function = "vi_alt3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	vi-vsync-pd6 {
	nvidia,pins = "vi_d0_pt4",
	"vi_d1_pd5",
	"vi_d2_pl0",
	"vi_d3_pl1",
	"vi_d4_pl2",
	"vi_d5_pl3",
	"vi_d6_pl4",
	"vi_d7_pl5",
	"vi_d8_pl6",
	"vi_d9_pl7",
	"vi_d10_pt2",
	"vi_d11_pt3",
	"vi_hsync_pd7",
	"vi_pclk_pt0",
	"vi_vsync_pd6";
	nvidia,function = "vi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	/* Multiplexed and therefore disabled */
	kb-col2-pq2 {
	nvidia,pins = "kb_col2_pq2",
	"kb_col3_pq3",
	"kb_col4_pq4",
	"kb_row4_pr4";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row0-pr0 {
	nvidia,pins = "kb_row0_pr0",
	"kb_row1_pr1",
	"kb_row2_pr2",
	"kb_row3_pr3";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row5-pr5 {
	nvidia,pins = "kb_row5_pr5",
	"kb_row6_pr6",
	"kb_row7_pr7";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	/*
	* VI level-shifter direction
	* (pull-down => default direction input)
	*/
	vi-mclk-pt1 {
	nvidia,pins = "vi_mclk_pt1";
	nvidia,function = "vi_alt3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis PWM1 */
	pu6 {
	nvidia,pins = "pu6";
	nvidia,function = "pwm3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis PWM2 */
	pu5 {
	nvidia,pins = "pu5";
	nvidia,function = "pwm2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis PWM3 */
	pu4 {
	nvidia,pins = "pu4";
	nvidia,function = "pwm1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis PWM4 */
	pu3 {
	nvidia,pins = "pu3";
	nvidia,function = "pwm0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis RESET_MOCI# */
	gmi-rst-n-pi4 {
	nvidia,pins = "gmi_rst_n_pi4";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis SATA1_ACT# */
	pex-l0-prsnt-n-pdd0 {
	nvidia,pins = "pex_l0_prsnt_n_pdd0";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis SD1 */
	sdmmc1-clk-pz0 {
	nvidia,pins = "sdmmc1_clk_pz0";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1-cmd-pz1 {
	nvidia,pins = "sdmmc1_cmd_pz1",
	"sdmmc1_dat0_py7",
	"sdmmc1_dat1_py6",
	"sdmmc1_dat2_py5",
	"sdmmc1_dat3_py4";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	/* Apalis SD1_CD# */
	clk2-req-pcc5 {
	nvidia,pins = "clk2_req_pcc5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis SPDIF1 */
	spdif-out-pk5 {
	nvidia,pins = "spdif_out_pk5",
	"spdif_in_pk6";
	nvidia,function = "spdif";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis SPI1 */
	spi1-sck-px5 {
	nvidia,pins = "spi1_sck_px5",
	"spi1_mosi_px4",
	"spi1_miso_px7",
	"spi1_cs0_n_px6";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis SPI2 */
	lcd-sck-pz4 {
	nvidia,pins = "lcd_sck_pz4",
	"lcd_sdout_pn5",
	"lcd_sdin_pz2",
	"lcd_cs0_n_pn4";
	nvidia,function = "spi5";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/*
	* Apalis TS (Low-speed type specific)
	* pins may be used as GPIOs
	*/
	kb-col5-pq5 {
	nvidia,pins = "kb_col5_pq5";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb-col6-pq6 {
	nvidia,pins = "kb_col6_pq6",
	"kb_col7_pq7",
	"kb_row8_ps0",
	"kb_row9_ps1";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis UART1 */
	ulpi-data0 {
	nvidia,pins = "ulpi_data0_po1",
	"ulpi_data1_po2",
	"ulpi_data2_po3",
	"ulpi_data3_po4",
	"ulpi_data4_po5",
	"ulpi_data5_po6",
	"ulpi_data6_po7",
	"ulpi_data7_po0";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis UART2 */
	ulpi-clk-py0 {
	nvidia,pins = "ulpi_clk_py0",
	"ulpi_dir_py1",
	"ulpi_nxt_py2",
	"ulpi_stp_py3";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis UART3 */
	uart2-rxd-pc3 {
	nvidia,pins = "uart2_rxd_pc3",
	"uart2_txd_pc2";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis UART4 */
	uart3-rxd-pw7 {
	nvidia,pins = "uart3_rxd_pw7",
	"uart3_txd_pw6";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis USBH_EN */
	pex-l0-rst-n-pdd1 {
	nvidia,pins = "pex_l0_rst_n_pdd1";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis USBH_OC# */
	pex-l0-clkreq-n-pdd2 {
	nvidia,pins = "pex_l0_clkreq_n_pdd2";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis USBO1_EN */
	gen2-i2c-scl-pt5 {
	nvidia,pins = "gen2_i2c_scl_pt5";
	nvidia,function = "rsvd4";
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis USBO1_OC# */
	gen2-i2c-sda-pt6 {
	nvidia,pins = "gen2_i2c_sda_pt6";
	nvidia,function = "rsvd4";
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Apalis VGA1 not supported and therefore disabled */
	crt-hsync-pv6 {
	nvidia,pins = "crt_hsync_pv6",
	"crt_vsync_pv7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Apalis WAKE1_MICO */
	pv1 {
	nvidia,pins = "pv1";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* eMMC (On-module) */
	sdmmc4-clk-pcc4 {
	nvidia,pins = "sdmmc4_clk_pcc4",
	"sdmmc4_cmd_pt7",
	"sdmmc4_rst_n_pcc3";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-dat0-paa0 {
	nvidia,pins = "sdmmc4_dat0_paa0",
	"sdmmc4_dat1_paa1",
	"sdmmc4_dat2_paa2",
	"sdmmc4_dat3_paa3",
	"sdmmc4_dat4_paa4",
	"sdmmc4_dat5_paa5",
	"sdmmc4_dat6_paa6",
	"sdmmc4_dat7_paa7";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */
	pex-l2-prsnt-n-pdd7 {
	nvidia,pins = "pex_l2_prsnt_n_pdd7",
	"pex_l2_rst_n_pcc6";
	nvidia,function = "pcie";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	/* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */
	pex-wake-n-pdd3 {
	nvidia,pins = "pex_wake_n_pdd3",
	"pex_l2_clkreq_n_pcc7";
	nvidia,function = "pcie";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	/* LAN i210/i211 SMB_ALERT_N (On-module) */
	sys-clk-req-pz5 {
	nvidia,pins = "sys_clk_req_pz5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* LVDS Transceiver Configuration */
	pbb0 {
	nvidia,pins = "pbb0",
	"pbb7",
	"pcc1",
	"pcc2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pbb3 {
	nvidia,pins = "pbb3",
	"pbb4",
	"pbb5",
	"pbb6";
	nvidia,function = "displayb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Not connected and therefore disabled */
	clk-32k-out-pa0 {
	nvidia,pins = "clk3_out_pee0",
	"clk3_req_pee1",
	"clk_32k_out_pa0",
	"dap4_din_pp5",
	"dap4_dout_pp6",
	"dap4_fs_pp4",
	"dap4_sclk_pp7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap2-fs-pa2 {
	nvidia,pins = "dap2_fs_pa2",
	"dap2_sclk_pa3",
	"dap2_din_pa4",
	"dap2_dout_pa5",
	"lcd_dc0_pn6",
	"lcd_m1_pw1",
	"lcd_pwr1_pc1",
	"pex_l1_clkreq_n_pdd6",
	"pex_l1_prsnt_n_pdd4",
	"pex_l1_rst_n_pdd5";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi-ad0-pg0 {
	nvidia,pins = "gmi_ad0_pg0",
	"gmi_ad2_pg2",
	"gmi_ad3_pg3",
	"gmi_ad4_pg4",
	"gmi_ad5_pg5",
	"gmi_ad6_pg6",
	"gmi_ad7_pg7",
	"gmi_ad8_ph0",
	"gmi_ad9_ph1",
	"gmi_ad10_ph2",
	"gmi_ad11_ph3",
	"gmi_ad12_ph4",
	"gmi_ad13_ph5",
	"gmi_ad14_ph6",
	"gmi_ad15_ph7",
	"gmi_adv_n_pk0",
	"gmi_clk_pk1",
	"gmi_cs4_n_pk2",
	"gmi_cs2_n_pk3",
	"gmi_dqs_pi2",
	"gmi_iordy_pi5",
	"gmi_oe_n_pi1",
	"gmi_wait_pi7",
	"gmi_wr_n_pi0",
	"lcd_cs1_n_pw0",
	"pu0",
	"pu1",
	"pu2";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi-cs0-n-pj0 {
	nvidia,pins = "gmi_cs0_n_pj0",
	"gmi_cs1_n_pj2",
	"gmi_cs3_n_pk4";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi-cs6-n-pi3 {
	nvidia,pins = "gmi_cs6_n_pi3";
	nvidia,function = "sata";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi-cs7-n-pi6 {
	nvidia,pins = "gmi_cs7_n_pi6";
	nvidia,function = "gmi_alt";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	lcd-pwr0-pb2 {
	nvidia,pins = "lcd_pwr0_pb2",
	"lcd_pwr2_pc6",
	"lcd_wr_n_pz3";
	nvidia,function = "hdcp";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart2-cts-n-pj5 {
	nvidia,pins = "uart2_cts_n_pj5",
	"uart2_rts_n_pj6";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Power I2C (On-module) */
	pwr-i2c-scl-pz6 {
	nvidia,pins = "pwr_i2c_scl_pz6",
	"pwr_i2c_sda_pz7";
	nvidia,function = "i2cpwr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};

	/*
	* THERMD_ALERT#, unlatched I2C address pin of LM95245
	* temperature sensor therefore requires disabling for
	* now
	*/
	lcd-dc1-pd2 {
	nvidia,pins = "lcd_dc1_pd2";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* TOUCH_PEN_INT# (On-module) */
	pv0 {
	nvidia,pins = "pv0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	};
	};

	serial@70006040 {
	compatible = "nvidia,tegra30-hsuart";
	};

	serial@70006200 {
	compatible = "nvidia,tegra30-hsuart";
	};

	serial@70006300 {
	compatible = "nvidia,tegra30-hsuart";
	};

	hdmi_ddc: i2c@7000c700 {
	clock-frequency = <10000>;
	};

	/*
	* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
	* touch screen controller
	*/
	i2c@7000d000 {
	status = "okay";
	clock-frequency = <100000>;

	/* SGTL5000 audio codec */
	sgtl5000: codec@a {
	compatible = "fsl,sgtl5000";
	reg = <0x0a>;
	VDDA-supply = <&reg_module_3v3_audio>;
	VDDD-supply = <&reg_1v8_vio>;
	VDDIO-supply = <&reg_module_3v3>;
	clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
	};

	pmic: pmic@2d {
	compatible = "ti,tps65911";
	reg = <0x2d>;

	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <2>;
	interrupt-controller;

	ti,system-power-controller;

	#gpio-cells = <2>;
	gpio-controller;

	vcc1-supply = <&reg_module_3v3>;
	vcc2-supply = <&reg_module_3v3>;
	vcc3-supply = <&reg_1v8_vio>;
	vcc4-supply = <&reg_module_3v3>;
	vcc5-supply = <&reg_module_3v3>;
	vcc6-supply = <&reg_1v8_vio>;
	vcc7-supply = <&reg_5v0_charge_pump>;
	vccio-supply = <&reg_module_3v3>;

	regulators {
	vdd1_reg: vdd1 {
	regulator-name = "+V1.35_VDDIO_DDR";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	};

	vdd2_reg: vdd2 {
	regulator-name = "+V1.05";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	};

	vddctrl_reg: vddctrl {
	regulator-name = "+V1.0_VDD_CPU";
	regulator-min-microvolt = <1150000>;
	regulator-max-microvolt = <1150000>;
	regulator-always-on;
	};

	reg_1v8_vio: vio {
	regulator-name = "+V1.8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	/* LDO1: unused */

	/*
	* EN_+V3.3 switching via FET:
	* +V3.3_AUDIO_AVDD_S, +V3.3
	* see also +V3.3 fixed supply
	*/
	ldo2_reg: ldo2 {
	regulator-name = "EN_+V3.3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	ldo3_reg: ldo3 {
	regulator-name = "+V1.2_CSI";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	ldo4_reg: ldo4 {
	regulator-name = "+V1.2_VDD_RTC";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	/*
	* +V2.8_AVDD_VDAC:
	* only required for (unsupported) analog RGB
	*/
	ldo5_reg: ldo5 {
	regulator-name = "+V2.8_AVDD_VDAC";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-always-on;
	};

	/*
	* +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
	* but LDO6 can't set voltage in 50mV
	* granularity
	*/
	ldo6_reg: ldo6 {
	regulator-name = "+V1.05_AVDD_PLLE";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	};

	ldo7_reg: ldo7 {
	regulator-name = "+V1.2_AVDD_PLL";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	ldo8_reg: ldo8 {
	regulator-name = "+V1.0_VDD_DDR_HS";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};
	};
	};

	/* STMPE811 touch screen controller */
	touchscreen@41 {
	compatible = "st,stmpe811";
	reg = <0x41>;
	irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;
	id = <0>;
	blocks = <0x5>;
	irq-trigger = <0x1>;
	/* 3.25 MHz ADC clock speed */
	st,adc-freq = <1>;
	/* 12-bit ADC */
	st,mod-12b = <1>;
	/* internal ADC reference */
	st,ref-sel = <0>;
	/* ADC converstion time: 80 clocks */
	st,sample-time = <4>;

	stmpe_touchscreen {
	compatible = "st,stmpe-ts";
	/* 8 sample average control */
	st,ave-ctrl = <3>;
	/* 7 length fractional part in z */
	st,fraction-z = <7>;
	/*
	* 50 mA typical 80 mA max touchscreen drivers
	* current limit value
	*/
	st,i-drive = <1>;
	/* 1 ms panel driver settling time */
	st,settling = <3>;
	/* 5 ms touch detect interrupt delay */
	st,touch-det-delay = <5>;
	};

	stmpe_adc {
	compatible = "st,stmpe-adc";
	/* forbid to use ADC channels 3-0 (touch) */
	st,norequest-mask = <0x0F>;
	};
	};

	/*
	* LM95245 temperature sensor
	* Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
	*/
	temp-sensor@4c {
	compatible = "national,lm95245";
	reg = <0x4c>;
	};

	/* SW: +V1.2_VDD_CORE */
	regulator@60 {
	compatible = "ti,tps62362";
	reg = <0x60>;

	regulator-name = "tps62362-vout";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1400000>;
	regulator-boot-on;
	regulator-always-on;
	ti,vsel0-state-low;
	/* VSEL1: EN_CORE_DVFS_N low for DVFS */
	ti,vsel1-state-low;
	};
	};

	/* SPI4: CAN2 */
	spi@7000da00 {
	status = "okay";
	spi-max-frequency = <10000000>;

	can@1 {
	compatible = "microchip,mcp2515";
	reg = <1>;
	clocks = <&clk16m>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
	spi-max-frequency = <10000000>;
	};
	};

	/* SPI6: CAN1 */
	spi@7000de00 {
	status = "okay";
	spi-max-frequency = <10000000>;

	can@0 {
	compatible = "microchip,mcp2515";
	reg = <0>;
	clocks = <&clk16m>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_FALLING>;
	spi-max-frequency = <10000000>;
	};
	};

	pmc@7000e400 {
	nvidia,invert-interrupt;
	nvidia,suspend-mode = <1>;
	nvidia,cpu-pwr-good-time = <5000>;
	nvidia,cpu-pwr-off-time = <5000>;
	nvidia,core-pwr-good-time = <3845 3845>;
	nvidia,core-pwr-off-time = <0>;
	nvidia,core-power-req-active-high;
	nvidia,sys-clock-req-active-high;

	/* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
	i2c-thermtrip {
	nvidia,i2c-controller-id = <4>;
	nvidia,bus-addr = <0x2d>;
	nvidia,reg-addr = <0x3f>;
	nvidia,reg-data = <0x1>;
	};
	};

	hda@70030000 {
	status = "okay";
	};

	ahub@70080000 {
	i2s@70080500 {
	status = "okay";
	};
	};

	/* eMMC */
	sdhci@78000600 {
	status = "okay";
	bus-width = <8>;
	non-removable;
	vmmc-supply = <&reg_module_3v3>; /* VCC */
	vqmmc-supply = <&reg_1v8_vio>; /* VCCQ */
	mmc-ddr-1_8v;
	};

	clk32k_in: xtal1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};

	clk16m: osc4 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <16000000>;
	};

	reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
	compatible = "regulator-fixed";
	regulator-name = "+V1.8_AVDD_HDMI_PLL";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	enable-active-high;
	gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
	vin-supply = <&reg_1v8_vio>;
	};

	reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3_AVDD_HDMI";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	enable-active-high;
	gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
	vin-supply = <&reg_module_3v3>;
	};

	reg_5v0_charge_pump: regulator-5v0-charge-pump {
	compatible = "regulator-fixed";
	regulator-name = "+V5.0";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	reg_module_3v3: regulator-module-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_module_3v3_audio: regulator-module-3v3-audio {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3_AUDIO_AVDD_S";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	sound {
	compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
	"nvidia,tegra-audio-sgtl5000";
	nvidia,model = "Toradex Apalis T30";
	nvidia,audio-routing =
	"Headphone Jack", "HP_OUT",
	"LINE_IN", "Line In Jack",
	"MIC_IN", "Mic Jack";
	nvidia,i2s-controller = <&tegra_i2s2>;
	nvidia,audio-codec = <&sgtl5000>;
	clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
	<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
	- <&tegra_car TEGRA30_CLK_EXTERN1>;
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	clock-names = "pll_a", "pll_a_out0", "mclk";
	+
	+ assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	+
	+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
	+ <&tegra_car TEGRA30_CLK_EXTERN1>;
	};
	};
	diff --git a/sys/gnu/dts/arm/tegra30-beaver.dts b/sys/gnu/dts/arm/tegra30-beaver.dts
	index a3b0f3555cd2..45ef6002b225 100644
	--- a/sys/gnu/dts/arm/tegra30-beaver.dts
	+++ b/sys/gnu/dts/arm/tegra30-beaver.dts
	@@ -1,2117 +1,2123 @@
	// SPDX-License-Identifier: GPL-2.0
	/dts-v1/;

	#include "tegra30.dtsi"

	/ {
	model = "NVIDIA Tegra30 Beaver evaluation board";
	compatible = "nvidia,beaver", "nvidia,tegra30";

	aliases {
	rtc0 = "/i2c@7000d000/tps65911@2d";
	rtc1 = "/rtc@7000e000";
	serial0 = &uarta;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@80000000 {
	reg = <0x80000000 0x7ff00000>;
	};

	pcie@3000 {
	status = "okay";

	avdd-pexa-supply = <&ldo1_reg>;
	vdd-pexa-supply = <&ldo1_reg>;
	avdd-pexb-supply = <&ldo1_reg>;
	vdd-pexb-supply = <&ldo1_reg>;
	avdd-pex-pll-supply = <&ldo1_reg>;
	avdd-plle-supply = <&ldo1_reg>;
	vddio-pex-ctl-supply = <&sys_3v3_reg>;
	hvdd-pex-supply = <&sys_3v3_pexs_reg>;

	pci@1,0 {
	status = "okay";
	nvidia,num-lanes = <2>;
	};

	pci@2,0 {
	nvidia,num-lanes = <2>;
	};

	pci@3,0 {
	status = "okay";
	nvidia,num-lanes = <2>;
	};
	};

	host1x@50000000 {
	hdmi@54280000 {
	status = "okay";

	hdmi-supply = <&vdd_5v0_hdmi>;
	vdd-supply = <&sys_3v3_reg>;
	pll-supply = <&vio_reg>;

	nvidia,hpd-gpio =
	<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
	nvidia,ddc-i2c-bus = <&hdmiddc>;
	};
	};

	pinmux@70000868 {
	pinctrl-names = "default";
	pinctrl-0 = <&state_default>;

	state_default: pinmux {
	clk_32k_out_pa0 {
	nvidia,pins = "clk_32k_out_pa0";
	nvidia,function = "blink";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart3_cts_n_pa1 {
	nvidia,pins = "uart3_cts_n_pa1";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap2_fs_pa2 {
	nvidia,pins = "dap2_fs_pa2";
	nvidia,function = "i2s1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap2_sclk_pa3 {
	nvidia,pins = "dap2_sclk_pa3";
	nvidia,function = "i2s1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap2_din_pa4 {
	nvidia,pins = "dap2_din_pa4";
	nvidia,function = "i2s1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap2_dout_pa5 {
	nvidia,pins = "dap2_dout_pa5";
	nvidia,function = "i2s1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_clk_pa6 {
	nvidia,pins = "sdmmc3_clk_pa6";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_cmd_pa7 {
	nvidia,pins = "sdmmc3_cmd_pa7";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gmi_a17_pb0 {
	nvidia,pins = "gmi_a17_pb0";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gmi_a18_pb1 {
	nvidia,pins = "gmi_a18_pb1";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_pwr0_pb2 {
	nvidia,pins = "lcd_pwr0_pb2";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_pclk_pb3 {
	nvidia,pins = "lcd_pclk_pb3";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_dat3_pb4 {
	nvidia,pins = "sdmmc3_dat3_pb4";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_dat2_pb5 {
	nvidia,pins = "sdmmc3_dat2_pb5";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_dat1_pb6 {
	nvidia,pins = "sdmmc3_dat1_pb6";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_dat0_pb7 {
	nvidia,pins = "sdmmc3_dat0_pb7";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart3_rts_n_pc0 {
	nvidia,pins = "uart3_rts_n_pc0";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	lcd_pwr1_pc1 {
	nvidia,pins = "lcd_pwr1_pc1";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart2_txd_pc2 {
	nvidia,pins = "uart2_txd_pc2";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart2_rxd_pc3 {
	nvidia,pins = "uart2_rxd_pc3";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gen1_i2c_scl_pc4 {
	nvidia,pins = "gen1_i2c_scl_pc4";
	nvidia,function = "i2c1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	gen1_i2c_sda_pc5 {
	nvidia,pins = "gen1_i2c_sda_pc5";
	nvidia,function = "i2c1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	lcd_pwr2_pc6 {
	nvidia,pins = "lcd_pwr2_pc6";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gmi_wp_n_pc7 {
	nvidia,pins = "gmi_wp_n_pc7";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_dat5_pd0 {
	nvidia,pins = "sdmmc3_dat5_pd0";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_dat4_pd1 {
	nvidia,pins = "sdmmc3_dat4_pd1";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_dc1_pd2 {
	nvidia,pins = "lcd_dc1_pd2";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_dat6_pd3 {
	nvidia,pins = "sdmmc3_dat6_pd3";
	nvidia,function = "spdif";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc3_dat7_pd4 {
	nvidia,pins = "sdmmc3_dat7_pd4";
	nvidia,function = "spdif";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	vi_d1_pd5 {
	nvidia,pins = "vi_d1_pd5";
	nvidia,function = "sdmmc2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	vi_vsync_pd6 {
	nvidia,pins = "vi_vsync_pd6";
	nvidia,function = "ddr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	vi_hsync_pd7 {
	nvidia,pins = "vi_hsync_pd7";
	nvidia,function = "ddr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d0_pe0 {
	nvidia,pins = "lcd_d0_pe0";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d1_pe1 {
	nvidia,pins = "lcd_d1_pe1";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d2_pe2 {
	nvidia,pins = "lcd_d2_pe2";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d3_pe3 {
	nvidia,pins = "lcd_d3_pe3";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d4_pe4 {
	nvidia,pins = "lcd_d4_pe4";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d5_pe5 {
	nvidia,pins = "lcd_d5_pe5";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d6_pe6 {
	nvidia,pins = "lcd_d6_pe6";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d7_pe7 {
	nvidia,pins = "lcd_d7_pe7";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d8_pf0 {
	nvidia,pins = "lcd_d8_pf0";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d9_pf1 {
	nvidia,pins = "lcd_d9_pf1";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d10_pf2 {
	nvidia,pins = "lcd_d10_pf2";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d11_pf3 {
	nvidia,pins = "lcd_d11_pf3";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d12_pf4 {
	nvidia,pins = "lcd_d12_pf4";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d13_pf5 {
	nvidia,pins = "lcd_d13_pf5";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d14_pf6 {
	nvidia,pins = "lcd_d14_pf6";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d15_pf7 {
	nvidia,pins = "lcd_d15_pf7";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gmi_ad0_pg0 {
	nvidia,pins = "gmi_ad0_pg0";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_ad1_pg1 {
	nvidia,pins = "gmi_ad1_pg1";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_ad2_pg2 {
	nvidia,pins = "gmi_ad2_pg2";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_ad3_pg3 {
	nvidia,pins = "gmi_ad3_pg3";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_ad4_pg4 {
	nvidia,pins = "gmi_ad4_pg4";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_ad5_pg5 {
	nvidia,pins = "gmi_ad5_pg5";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_ad6_pg6 {
	nvidia,pins = "gmi_ad6_pg6";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_ad7_pg7 {
	nvidia,pins = "gmi_ad7_pg7";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_ad8_ph0 {
	nvidia,pins = "gmi_ad8_ph0";
	nvidia,function = "pwm0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_ad9_ph1 {
	nvidia,pins = "gmi_ad9_ph1";
	nvidia,function = "pwm1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_ad10_ph2 {
	nvidia,pins = "gmi_ad10_ph2";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_ad11_ph3 {
	nvidia,pins = "gmi_ad11_ph3";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_ad12_ph4 {
	nvidia,pins = "gmi_ad12_ph4";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gmi_ad13_ph5 {
	nvidia,pins = "gmi_ad13_ph5";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gmi_ad14_ph6 {
	nvidia,pins = "gmi_ad14_ph6";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_wr_n_pi0 {
	nvidia,pins = "gmi_wr_n_pi0";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_oe_n_pi1 {
	nvidia,pins = "gmi_oe_n_pi1";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_dqs_pi2 {
	nvidia,pins = "gmi_dqs_pi2";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_iordy_pi5 {
	nvidia,pins = "gmi_iordy_pi5";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gmi_cs7_n_pi6 {
	nvidia,pins = "gmi_cs7_n_pi6";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gmi_wait_pi7 {
	nvidia,pins = "gmi_wait_pi7";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	lcd_de_pj1 {
	nvidia,pins = "lcd_de_pj1";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_hsync_pj3 {
	nvidia,pins = "lcd_hsync_pj3";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_vsync_pj4 {
	nvidia,pins = "lcd_vsync_pj4";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart2_cts_n_pj5 {
	nvidia,pins = "uart2_cts_n_pj5";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart2_rts_n_pj6 {
	nvidia,pins = "uart2_rts_n_pj6";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_a16_pj7 {
	nvidia,pins = "gmi_a16_pj7";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gmi_adv_n_pk0 {
	nvidia,pins = "gmi_adv_n_pk0";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_clk_pk1 {
	nvidia,pins = "gmi_clk_pk1";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi_cs2_n_pk3 {
	nvidia,pins = "gmi_cs2_n_pk3";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gmi_cs3_n_pk4 {
	nvidia,pins = "gmi_cs3_n_pk4";
	nvidia,function = "nand";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	spdif_out_pk5 {
	nvidia,pins = "spdif_out_pk5";
	nvidia,function = "spdif";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	spdif_in_pk6 {
	nvidia,pins = "spdif_in_pk6";
	nvidia,function = "spdif";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gmi_a19_pk7 {
	nvidia,pins = "gmi_a19_pk7";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	vi_d2_pl0 {
	nvidia,pins = "vi_d2_pl0";
	nvidia,function = "sdmmc2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	vi_d3_pl1 {
	nvidia,pins = "vi_d3_pl1";
	nvidia,function = "sdmmc2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	vi_d4_pl2 {
	nvidia,pins = "vi_d4_pl2";
	nvidia,function = "vi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	vi_d5_pl3 {
	nvidia,pins = "vi_d5_pl3";
	nvidia,function = "sdmmc2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	vi_d6_pl4 {
	nvidia,pins = "vi_d6_pl4";
	nvidia,function = "vi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	vi_d7_pl5 {
	nvidia,pins = "vi_d7_pl5";
	nvidia,function = "sdmmc2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	vi_d8_pl6 {
	nvidia,pins = "vi_d8_pl6";
	nvidia,function = "sdmmc2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	vi_d9_pl7 {
	nvidia,pins = "vi_d9_pl7";
	nvidia,function = "sdmmc2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d16_pm0 {
	nvidia,pins = "lcd_d16_pm0";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d17_pm1 {
	nvidia,pins = "lcd_d17_pm1";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d18_pm2 {
	nvidia,pins = "lcd_d18_pm2";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d19_pm3 {
	nvidia,pins = "lcd_d19_pm3";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d20_pm4 {
	nvidia,pins = "lcd_d20_pm4";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d21_pm5 {
	nvidia,pins = "lcd_d21_pm5";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d22_pm6 {
	nvidia,pins = "lcd_d22_pm6";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_d23_pm7 {
	nvidia,pins = "lcd_d23_pm7";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap1_fs_pn0 {
	nvidia,pins = "dap1_fs_pn0";
	nvidia,function = "i2s0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap1_din_pn1 {
	nvidia,pins = "dap1_din_pn1";
	nvidia,function = "i2s0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap1_dout_pn2 {
	nvidia,pins = "dap1_dout_pn2";
	nvidia,function = "i2s0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap1_sclk_pn3 {
	nvidia,pins = "dap1_sclk_pn3";
	nvidia,function = "i2s0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_cs0_n_pn4 {
	nvidia,pins = "lcd_cs0_n_pn4";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_sdout_pn5 {
	nvidia,pins = "lcd_sdout_pn5";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_dc0_pn6 {
	nvidia,pins = "lcd_dc0_pn6";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	hdmi_int_pn7 {
	nvidia,pins = "hdmi_int_pn7";
	nvidia,function = "hdmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ulpi_data7_po0 {
	nvidia,pins = "ulpi_data7_po0";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi_data0_po1 {
	nvidia,pins = "ulpi_data0_po1";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi_data1_po2 {
	nvidia,pins = "ulpi_data1_po2";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ulpi_data2_po3 {
	nvidia,pins = "ulpi_data2_po3";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ulpi_data3_po4 {
	nvidia,pins = "ulpi_data3_po4";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ulpi_data4_po5 {
	nvidia,pins = "ulpi_data4_po5";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ulpi_data5_po6 {
	nvidia,pins = "ulpi_data5_po6";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ulpi_data6_po7 {
	nvidia,pins = "ulpi_data6_po7";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap3_fs_pp0 {
	nvidia,pins = "dap3_fs_pp0";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap3_din_pp1 {
	nvidia,pins = "dap3_din_pp1";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap3_dout_pp2 {
	nvidia,pins = "dap3_dout_pp2";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap3_sclk_pp3 {
	nvidia,pins = "dap3_sclk_pp3";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap4_fs_pp4 {
	nvidia,pins = "dap4_fs_pp4";
	nvidia,function = "i2s3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap4_din_pp5 {
	nvidia,pins = "dap4_din_pp5";
	nvidia,function = "i2s3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap4_dout_pp6 {
	nvidia,pins = "dap4_dout_pp6";
	nvidia,function = "i2s3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	dap4_sclk_pp7 {
	nvidia,pins = "dap4_sclk_pp7";
	nvidia,function = "i2s3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_col0_pq0 {
	nvidia,pins = "kb_col0_pq0";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_col1_pq1 {
	nvidia,pins = "kb_col1_pq1";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_col2_pq2 {
	nvidia,pins = "kb_col2_pq2";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_col3_pq3 {
	nvidia,pins = "kb_col3_pq3";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_col4_pq4 {
	nvidia,pins = "kb_col4_pq4";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_col5_pq5 {
	nvidia,pins = "kb_col5_pq5";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_col6_pq6 {
	nvidia,pins = "kb_col6_pq6";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_col7_pq7 {
	nvidia,pins = "kb_col7_pq7";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row0_pr0 {
	nvidia,pins = "kb_row0_pr0";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row1_pr1 {
	nvidia,pins = "kb_row1_pr1";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row2_pr2 {
	nvidia,pins = "kb_row2_pr2";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row3_pr3 {
	nvidia,pins = "kb_row3_pr3";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row4_pr4 {
	nvidia,pins = "kb_row4_pr4";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row5_pr5 {
	nvidia,pins = "kb_row5_pr5";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row6_pr6 {
	nvidia,pins = "kb_row6_pr6";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row7_pr7 {
	nvidia,pins = "kb_row7_pr7";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row8_ps0 {
	nvidia,pins = "kb_row8_ps0";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row9_ps1 {
	nvidia,pins = "kb_row9_ps1";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row10_ps2 {
	nvidia,pins = "kb_row10_ps2";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row11_ps3 {
	nvidia,pins = "kb_row11_ps3";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row12_ps4 {
	nvidia,pins = "kb_row12_ps4";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row13_ps5 {
	nvidia,pins = "kb_row13_ps5";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row14_ps6 {
	nvidia,pins = "kb_row14_ps6";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	kb_row15_ps7 {
	nvidia,pins = "kb_row15_ps7";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	vi_pclk_pt0 {
	nvidia,pins = "vi_pclk_pt0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	vi_mclk_pt1 {
	nvidia,pins = "vi_mclk_pt1";
	nvidia,function = "vi";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	vi_d10_pt2 {
	nvidia,pins = "vi_d10_pt2";
	nvidia,function = "ddr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	vi_d11_pt3 {
	nvidia,pins = "vi_d11_pt3";
	nvidia,function = "ddr";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	vi_d0_pt4 {
	nvidia,pins = "vi_d0_pt4";
	nvidia,function = "ddr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	gen2_i2c_scl_pt5 {
	nvidia,pins = "gen2_i2c_scl_pt5";
	nvidia,function = "i2c2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	gen2_i2c_sda_pt6 {
	nvidia,pins = "gen2_i2c_sda_pt6";
	nvidia,function = "i2c2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_cmd_pt7 {
	nvidia,pins = "sdmmc4_cmd_pt7";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pu0 {
	nvidia,pins = "pu0";
	nvidia,function = "owr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pu1 {
	nvidia,pins = "pu1";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pu2 {
	nvidia,pins = "pu2";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pu3 {
	nvidia,pins = "pu3";
	nvidia,function = "pwm0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pu4 {
	nvidia,pins = "pu4";
	nvidia,function = "pwm1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pu5 {
	nvidia,pins = "pu5";
	nvidia,function = "pwm2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pu6 {
	nvidia,pins = "pu6";
	nvidia,function = "pwm3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	jtag_rtck_pu7 {
	nvidia,pins = "jtag_rtck_pu7";
	nvidia,function = "rtck";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pv0 {
	nvidia,pins = "pv0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pv2 {
	nvidia,pins = "pv2";
	nvidia,function = "owr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pv3 {
	nvidia,pins = "pv3";
	nvidia,function = "clk_12m_out";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ddc_scl_pv4 {
	nvidia,pins = "ddc_scl_pv4";
	nvidia,function = "i2c4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ddc_sda_pv5 {
	nvidia,pins = "ddc_sda_pv5";
	nvidia,function = "i2c4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	crt_hsync_pv6 {
	nvidia,pins = "crt_hsync_pv6";
	nvidia,function = "crt";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	crt_vsync_pv7 {
	nvidia,pins = "crt_vsync_pv7";
	nvidia,function = "crt";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	lcd_cs1_n_pw0 {
	nvidia,pins = "lcd_cs1_n_pw0";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_m1_pw1 {
	nvidia,pins = "lcd_m1_pw1";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	spi2_cs1_n_pw2 {
	nvidia,pins = "spi2_cs1_n_pw2";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	clk1_out_pw4 {
	nvidia,pins = "clk1_out_pw4";
	nvidia,function = "extperiph1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	clk2_out_pw5 {
	nvidia,pins = "clk2_out_pw5";
	nvidia,function = "extperiph2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	uart3_txd_pw6 {
	nvidia,pins = "uart3_txd_pw6";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	uart3_rxd_pw7 {
	nvidia,pins = "uart3_rxd_pw7";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	spi2_sck_px2 {
	nvidia,pins = "spi2_sck_px2";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	spi1_mosi_px4 {
	nvidia,pins = "spi1_mosi_px4";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	spi1_sck_px5 {
	nvidia,pins = "spi1_sck_px5";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	spi1_cs0_n_px6 {
	nvidia,pins = "spi1_cs0_n_px6";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	spi1_miso_px7 {
	nvidia,pins = "spi1_miso_px7";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ulpi_clk_py0 {
	nvidia,pins = "ulpi_clk_py0";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	ulpi_dir_py1 {
	nvidia,pins = "ulpi_dir_py1";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ulpi_nxt_py2 {
	nvidia,pins = "ulpi_nxt_py2";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	ulpi_stp_py3 {
	nvidia,pins = "ulpi_stp_py3";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_dat3_py4 {
	nvidia,pins = "sdmmc1_dat3_py4";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1_dat2_py5 {
	nvidia,pins = "sdmmc1_dat2_py5";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1_dat1_py6 {
	nvidia,pins = "sdmmc1_dat1_py6";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1_dat0_py7 {
	nvidia,pins = "sdmmc1_dat0_py7";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1_clk_pz0 {
	nvidia,pins = "sdmmc1_clk_pz0";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc1_cmd_pz1 {
	nvidia,pins = "sdmmc1_cmd_pz1";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_sdin_pz2 {
	nvidia,pins = "lcd_sdin_pz2";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_wr_n_pz3 {
	nvidia,pins = "lcd_wr_n_pz3";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd_sck_pz4 {
	nvidia,pins = "lcd_sck_pz4";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sys_clk_req_pz5 {
	nvidia,pins = "sys_clk_req_pz5";
	nvidia,function = "sysclk";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pwr_i2c_scl_pz6 {
	nvidia,pins = "pwr_i2c_scl_pz6";
	nvidia,function = "i2cpwr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	pwr_i2c_sda_pz7 {
	nvidia,pins = "pwr_i2c_sda_pz7";
	nvidia,function = "i2cpwr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_dat0_paa0 {
	nvidia,pins = "sdmmc4_dat0_paa0";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_dat1_paa1 {
	nvidia,pins = "sdmmc4_dat1_paa1";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_dat2_paa2 {
	nvidia,pins = "sdmmc4_dat2_paa2";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_dat3_paa3 {
	nvidia,pins = "sdmmc4_dat3_paa3";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_dat4_paa4 {
	nvidia,pins = "sdmmc4_dat4_paa4";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_dat5_paa5 {
	nvidia,pins = "sdmmc4_dat5_paa5";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_dat6_paa6 {
	nvidia,pins = "sdmmc4_dat6_paa6";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_dat7_paa7 {
	nvidia,pins = "sdmmc4_dat7_paa7";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pbb0 {
	nvidia,pins = "pbb0";
	nvidia,function = "i2s4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	cam_i2c_scl_pbb1 {
	nvidia,pins = "cam_i2c_scl_pbb1";
	nvidia,function = "i2c3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	cam_i2c_sda_pbb2 {
	nvidia,pins = "cam_i2c_sda_pbb2";
	nvidia,function = "i2c3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};
	pbb3 {
	nvidia,pins = "pbb3";
	nvidia,function = "vgp3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pbb4 {
	nvidia,pins = "pbb4";
	nvidia,function = "vgp4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pbb5 {
	nvidia,pins = "pbb5";
	nvidia,function = "vgp5";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pbb6 {
	nvidia,pins = "pbb6";
	nvidia,function = "vgp6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pbb7 {
	nvidia,pins = "pbb7";
	nvidia,function = "i2s4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	cam_mclk_pcc0 {
	nvidia,pins = "cam_mclk_pcc0";
	nvidia,function = "vi_alt3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pcc1 {
	nvidia,pins = "pcc1";
	nvidia,function = "i2s4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pcc2 {
	nvidia,pins = "pcc2";
	nvidia,function = "i2s4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_rst_n_pcc3 {
	nvidia,pins = "sdmmc4_rst_n_pcc3";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4_clk_pcc4 {
	nvidia,pins = "sdmmc4_clk_pcc4";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	clk2_req_pcc5 {
	nvidia,pins = "clk2_req_pcc5";
	nvidia,function = "dap";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pex_l2_rst_n_pcc6 {
	nvidia,pins = "pex_l2_rst_n_pcc6";
	nvidia,function = "pcie";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pex_l2_clkreq_n_pcc7 {
	nvidia,pins = "pex_l2_clkreq_n_pcc7";
	nvidia,function = "pcie";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pex_l0_prsnt_n_pdd0 {
	nvidia,pins = "pex_l0_prsnt_n_pdd0";
	nvidia,function = "pcie";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pex_l0_rst_n_pdd1 {
	nvidia,pins = "pex_l0_rst_n_pdd1";
	nvidia,function = "pcie";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pex_l0_clkreq_n_pdd2 {
	nvidia,pins = "pex_l0_clkreq_n_pdd2";
	nvidia,function = "pcie";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pex_wake_n_pdd3 {
	nvidia,pins = "pex_wake_n_pdd3";
	nvidia,function = "pcie";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pex_l1_prsnt_n_pdd4 {
	nvidia,pins = "pex_l1_prsnt_n_pdd4";
	nvidia,function = "pcie";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pex_l1_rst_n_pdd5 {
	nvidia,pins = "pex_l1_rst_n_pdd5";
	nvidia,function = "pcie";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pex_l1_clkreq_n_pdd6 {
	nvidia,pins = "pex_l1_clkreq_n_pdd6";
	nvidia,function = "pcie";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pex_l2_prsnt_n_pdd7 {
	nvidia,pins = "pex_l2_prsnt_n_pdd7";
	nvidia,function = "pcie";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	clk3_out_pee0 {
	nvidia,pins = "clk3_out_pee0";
	nvidia,function = "extperiph3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	clk3_req_pee1 {
	nvidia,pins = "clk3_req_pee1";
	nvidia,function = "dev3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	clk1_req_pee2 {
	nvidia,pins = "clk1_req_pee2";
	nvidia,function = "dap";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	hdmi_cec_pee3 {
	nvidia,pins = "hdmi_cec_pee3";
	nvidia,function = "cec";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	owr {
	nvidia,pins = "owr";
	nvidia,function = "owr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdio3 {
	nvidia,pins = "drive_sdio3";
	nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
	nvidia,schmitt = <TEGRA_PIN_DISABLE>;
	nvidia,pull-down-strength = <46>;
	nvidia,pull-up-strength = <42>;
	nvidia,slew-rate-rising = <1>;
	nvidia,slew-rate-falling = <1>;
	};
	gpv {
	nvidia,pins = "drive_gpv";
	nvidia,pull-up-strength = <16>;
	};
	};
	};

	serial@70006000 {
	status = "okay";
	};

	i2c@7000c000 {
	status = "okay";
	clock-frequency = <100000>;
	};

	i2c@7000c400 {
	status = "okay";
	clock-frequency = <100000>;
	};

	i2c@7000c500 {
	status = "okay";
	clock-frequency = <100000>;
	};

	hdmiddc: i2c@7000c700 {
	status = "okay";
	clock-frequency = <100000>;
	};

	i2c@7000d000 {
	status = "okay";
	clock-frequency = <100000>;

	rt5640: rt5640@1c {
	compatible = "realtek,rt5640";
	reg = <0x1c>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_EDGE_FALLING>;
	realtek,ldo1-en-gpios =
	<&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
	};

	pmic: tps65911@2d {
	compatible = "ti,tps65911";
	reg = <0x2d>;

	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <2>;
	interrupt-controller;

	ti,system-power-controller;

	#gpio-cells = <2>;
	gpio-controller;

	vcc1-supply = <&vdd_5v_in_reg>;
	vcc2-supply = <&vdd_5v_in_reg>;
	vcc3-supply = <&vio_reg>;
	vcc4-supply = <&vdd_5v_in_reg>;
	vcc5-supply = <&vdd_5v_in_reg>;
	vcc6-supply = <&vdd2_reg>;
	vcc7-supply = <&vdd_5v_in_reg>;
	vccio-supply = <&vdd_5v_in_reg>;

	regulators {
	vdd1_reg: vdd1 {
	regulator-name = "vddio_ddr_1v2";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	vdd2_reg: vdd2 {
	regulator-name = "vdd_1v5_gen";
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;
	};

	vddctrl_reg: vddctrl {
	regulator-name = "vdd_cpu,vdd_sys";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	vio_reg: vio {
	regulator-name = "vdd_1v8_gen";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	ldo1_reg: ldo1 {
	regulator-name = "vdd_pexa,vdd_pexb";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	};

	ldo2_reg: ldo2 {
	regulator-name = "vdd_sata,avdd_plle";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	};

	/* LDO3 is not connected to anything */

	ldo4_reg: ldo4 {
	regulator-name = "vdd_rtc";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	ldo5_reg: ldo5 {
	regulator-name = "vddio_sdmmc,avdd_vdac";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	ldo6_reg: ldo6 {
	regulator-name = "avdd_dsi_csi,pwrdet_mipi";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	ldo7_reg: ldo7 {
	regulator-name = "vdd_pllm,x,u,a_p_c_s";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	ldo8_reg: ldo8 {
	regulator-name = "vdd_ddr_hs";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};
	};
	};

	tps62361@60 {
	compatible = "ti,tps62361";
	reg = <0x60>;

	regulator-name = "tps62361-vout";
	regulator-min-microvolt = <500000>;
	regulator-max-microvolt = <1500000>;
	regulator-boot-on;
	regulator-always-on;
	ti,vsel0-state-high;
	ti,vsel1-state-high;
	};
	};

	spi@7000da00 {
	status = "okay";
	spi-max-frequency = <25000000>;
	spi-flash@1 {
	compatible = "winbond,w25q32", "jedec,spi-nor";
	reg = <1>;
	spi-max-frequency = <20000000>;
	};
	};

	pmc@7000e400 {
	status = "okay";
	nvidia,invert-interrupt;
	nvidia,suspend-mode = <1>;
	nvidia,cpu-pwr-good-time = <2000>;
	nvidia,cpu-pwr-off-time = <200>;
	nvidia,core-pwr-good-time = <3845 3845>;
	nvidia,core-pwr-off-time = <0>;
	nvidia,core-power-req-active-high;
	nvidia,sys-clock-req-active-high;
	};

	ahub@70080000 {
	i2s@70080400 {
	status = "okay";
	};
	};

	sdhci@78000000 {
	status = "okay";
	vqmmc-supply = <&ldo5_reg>;
	cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
	power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
	bus-width = <4>;
	};

	sdhci@78000600 {
	status = "okay";
	bus-width = <8>;
	non-removable;
	};

	usb@7d000000 {
	compatible = "nvidia,tegra30-udc";
	status = "okay";
	dr_mode = "peripheral";
	};

	usb-phy@7d000000 {
	status = "okay";
	};

	usb@7d004000 {
	status = "okay";
	};

	phy2: usb-phy@7d004000 {
	vbus-supply = <&sys_3v3_reg>;
	status = "okay";
	};

	usb@7d008000 {
	status = "okay";
	};

	usb-phy@7d008000 {
	vbus-supply = <&usb3_vbus_reg>;
	status = "okay";
	};

	clocks {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	clk32k_in: clock@0 {
	compatible = "fixed-clock";
	reg = <0>;
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	};

	gpio-leds {
	compatible = "gpio-leds";

	gpled1 {
	label = "LED1"; /* CR5A1 (blue) */
	gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
	};
	gpled2 {
	label = "LED2"; /* CR4A2 (green) */
	gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
	};
	};

	regulators {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	vdd_5v_in_reg: regulator@0 {
	compatible = "regulator-fixed";
	reg = <0>;
	regulator-name = "vdd_5v_in";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	chargepump_5v_reg: regulator@1 {
	compatible = "regulator-fixed";
	reg = <1>;
	regulator-name = "chargepump_5v";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-boot-on;
	regulator-always-on;
	enable-active-high;
	gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
	};

	ddr_reg: regulator@2 {
	compatible = "regulator-fixed";
	reg = <2>;
	regulator-name = "vdd_ddr";
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;
	regulator-boot-on;
	enable-active-high;
	gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
	vin-supply = <&vdd_5v_in_reg>;
	};

	vdd_5v_sata_reg: regulator@3 {
	compatible = "regulator-fixed";
	reg = <3>;
	regulator-name = "vdd_5v_sata";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
	vin-supply = <&vdd_5v_in_reg>;
	};

	usb1_vbus_reg: regulator@4 {
	compatible = "regulator-fixed";
	reg = <4>;
	regulator-name = "usb1_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
	gpio-open-drain;
	vin-supply = <&vdd_5v_in_reg>;
	};

	usb3_vbus_reg: regulator@5 {
	compatible = "regulator-fixed";
	reg = <5>;
	regulator-name = "usb3_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
	gpio-open-drain;
	vin-supply = <&vdd_5v_in_reg>;
	};

	sys_3v3_reg: regulator@6 {
	compatible = "regulator-fixed";
	reg = <6>;
	regulator-name = "sys_3v3,vdd_3v3_alw";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	enable-active-high;
	gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
	vin-supply = <&vdd_5v_in_reg>;
	};

	sys_3v3_pexs_reg: regulator@7 {
	compatible = "regulator-fixed";
	reg = <7>;
	regulator-name = "sys_3v3_pexs";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
	vin-supply = <&sys_3v3_reg>;
	};

	vdd_5v0_hdmi: regulator@8 {
	compatible = "regulator-fixed";
	reg = <8>;
	regulator-name = "+VDD_5V_HDMI";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&sys_3v3_reg>;
	};
	};

	sound {
	compatible = "nvidia,tegra-audio-rt5640-beaver",
	"nvidia,tegra-audio-rt5640";
	nvidia,model = "NVIDIA Tegra Beaver";

	nvidia,audio-routing =
	"Headphones", "HPOR",
	"Headphones", "HPOL",
	"Mic Jack", "MICBIAS1",
	"IN2P", "Mic Jack";

	nvidia,i2s-controller = <&tegra_i2s1>;
	nvidia,audio-codec = <&rt5640>;

	nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;

	clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
	<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
	- <&tegra_car TEGRA30_CLK_EXTERN1>;
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	clock-names = "pll_a", "pll_a_out0", "mclk";
	+
	+ assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	+
	+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
	+ <&tegra_car TEGRA30_CLK_EXTERN1>;
	};
	};
	diff --git a/sys/gnu/dts/arm/tegra30-cardhu.dtsi b/sys/gnu/dts/arm/tegra30-cardhu.dtsi
	index 7ce61edd52f5..4b4f49a49394 100644
	--- a/sys/gnu/dts/arm/tegra30-cardhu.dtsi
	+++ b/sys/gnu/dts/arm/tegra30-cardhu.dtsi
	@@ -1,652 +1,658 @@
	// SPDX-License-Identifier: GPL-2.0
	#include <dt-bindings/input/input.h>
	#include "tegra30.dtsi"

	/**
	* This file contains common DT entry for all fab version of Cardhu.
	* There is multiple fab version of Cardhu starting from A01 to A07.
	* Cardhu fab version A01 and A03 are not supported. Cardhu fab version
	* A02 will have different sets of GPIOs for fixed regulator compare to
	* Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
	* compatible with fab version A04. Based on Cardhu fab version, the
	* related dts file need to be chosen like for Cardhu fab version A02,
	* use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
	* tegra30-cardhu-a04.dts.
	* The identification of board is done in two ways, by looking the sticker
	* on PCB and by reading board id eeprom.
	* The sticker will have number like 600-81291-1000-002 C.3. In this 4th
	* number is the fab version like here it is 002 and hence fab version A02.
	* The (downstream internal) U-Boot of Cardhu display the board-id as
	* follows:
	* BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
	* In this Fab version is 02 i.e. A02.
	* The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
	* The location 0x8 of this eeprom contains the Fab version. It is 1 byte
	* wide.
	*/

	/ {
	model = "NVIDIA Tegra30 Cardhu evaluation board";
	compatible = "nvidia,cardhu", "nvidia,tegra30";

	aliases {
	rtc0 = "/i2c@7000d000/tps65911@2d";
	rtc1 = "/rtc@7000e000";
	serial0 = &uarta;
	serial1 = &uartc;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@80000000 {
	reg = <0x80000000 0x40000000>;
	};

	pcie@3000 {
	status = "okay";

	/* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
	avdd-pexb-supply = <&ldo1_reg>;
	vdd-pexb-supply = <&ldo1_reg>;
	avdd-pex-pll-supply = <&ldo1_reg>;
	hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
	vddio-pex-ctl-supply = <&sys_3v3_reg>;
	avdd-plle-supply = <&ldo2_reg>;

	pci@1,0 {
	nvidia,num-lanes = <4>;
	};

	pci@2,0 {
	nvidia,num-lanes = <1>;
	};

	pci@3,0 {
	status = "okay";
	nvidia,num-lanes = <1>;
	};
	};

	host1x@50000000 {
	dc@54200000 {
	rgb {
	status = "okay";

	nvidia,panel = <&panel>;
	};
	};
	};

	pinmux@70000868 {
	pinctrl-names = "default";
	pinctrl-0 = <&state_default>;

	state_default: pinmux {
	sdmmc1_clk_pz0 {
	nvidia,pins = "sdmmc1_clk_pz0";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_cmd_pz1 {
	nvidia,pins = "sdmmc1_cmd_pz1",
	"sdmmc1_dat0_py7",
	"sdmmc1_dat1_py6",
	"sdmmc1_dat2_py5",
	"sdmmc1_dat3_py4";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_clk_pa6 {
	nvidia,pins = "sdmmc3_clk_pa6";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_cmd_pa7 {
	nvidia,pins = "sdmmc3_cmd_pa7",
	"sdmmc3_dat0_pb7",
	"sdmmc3_dat1_pb6",
	"sdmmc3_dat2_pb5",
	"sdmmc3_dat3_pb4";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	sdmmc4_clk_pcc4 {
	nvidia,pins = "sdmmc4_clk_pcc4",
	"sdmmc4_rst_n_pcc3";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	sdmmc4_dat0_paa0 {
	nvidia,pins = "sdmmc4_dat0_paa0",
	"sdmmc4_dat1_paa1",
	"sdmmc4_dat2_paa2",
	"sdmmc4_dat3_paa3",
	"sdmmc4_dat4_paa4",
	"sdmmc4_dat5_paa5",
	"sdmmc4_dat6_paa6",
	"sdmmc4_dat7_paa7";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	dap2_fs_pa2 {
	nvidia,pins = "dap2_fs_pa2",
	"dap2_sclk_pa3",
	"dap2_din_pa4",
	"dap2_dout_pa5";
	nvidia,function = "i2s1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	sdio3 {
	nvidia,pins = "drive_sdio3";
	nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
	nvidia,schmitt = <TEGRA_PIN_DISABLE>;
	nvidia,pull-down-strength = <46>;
	nvidia,pull-up-strength = <42>;
	nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
	nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
	};
	uart3_txd_pw6 {
	nvidia,pins = "uart3_txd_pw6",
	"uart3_cts_n_pa1",
	"uart3_rts_n_pc0",
	"uart3_rxd_pw7";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	};
	};

	serial@70006000 {
	status = "okay";
	};

	serial@70006200 {
	compatible = "nvidia,tegra30-hsuart";
	status = "okay";
	};

	pwm@7000a000 {
	status = "okay";
	};

	panelddc: i2c@7000c000 {
	status = "okay";
	clock-frequency = <100000>;
	};

	i2c@7000c400 {
	status = "okay";
	clock-frequency = <100000>;
	};

	i2c@7000c500 {
	status = "okay";
	clock-frequency = <100000>;

	/* ALS and Proximity sensor */
	isl29028@44 {
	compatible = "isil,isl29028";
	reg = <0x44>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
	};

	i2cmux@70 {
	compatible = "nxp,pca9546";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x70>;
	reset-gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>;
	};
	};

	i2c@7000c700 {
	status = "okay";
	clock-frequency = <100000>;
	};

	i2c@7000d000 {
	status = "okay";
	clock-frequency = <100000>;

	wm8903: wm8903@1a {
	compatible = "wlf,wm8903";
	reg = <0x1a>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;

	gpio-controller;
	#gpio-cells = <2>;

	micdet-cfg = <0>;
	micdet-delay = <100>;
	gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
	};

	pmic: tps65911@2d {
	compatible = "ti,tps65911";
	reg = <0x2d>;

	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <2>;
	interrupt-controller;

	ti,system-power-controller;

	#gpio-cells = <2>;
	gpio-controller;

	vcc1-supply = <&vdd_ac_bat_reg>;
	vcc2-supply = <&vdd_ac_bat_reg>;
	vcc3-supply = <&vio_reg>;
	vcc4-supply = <&vdd_5v0_reg>;
	vcc5-supply = <&vdd_ac_bat_reg>;
	vcc6-supply = <&vdd2_reg>;
	vcc7-supply = <&vdd_ac_bat_reg>;
	vccio-supply = <&vdd_ac_bat_reg>;

	regulators {
	vdd1_reg: vdd1 {
	regulator-name = "vddio_ddr_1v2";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	vdd2_reg: vdd2 {
	regulator-name = "vdd_1v5_gen";
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;
	};

	vddctrl_reg: vddctrl {
	regulator-name = "vdd_cpu,vdd_sys";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};

	vio_reg: vio {
	regulator-name = "vdd_1v8_gen";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	ldo1_reg: ldo1 {
	regulator-name = "vdd_pexa,vdd_pexb";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	};

	ldo2_reg: ldo2 {
	regulator-name = "vdd_sata,avdd_plle";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	};

	/* LDO3 is not connected to anything */

	ldo4_reg: ldo4 {
	regulator-name = "vdd_rtc";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	ldo5_reg: ldo5 {
	regulator-name = "vddio_sdmmc,avdd_vdac";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	ldo6_reg: ldo6 {
	regulator-name = "avdd_dsi_csi,pwrdet_mipi";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	ldo7_reg: ldo7 {
	regulator-name = "vdd_pllm,x,u,a_p_c_s";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	ldo8_reg: ldo8 {
	regulator-name = "vdd_ddr_hs";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};
	};
	};

	temperature-sensor@4c {
	compatible = "onnn,nct1008";
	reg = <0x4c>;
	vcc-supply = <&sys_3v3_reg>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
	};

	tps62361@60 {
	compatible = "ti,tps62361";
	reg = <0x60>;

	regulator-name = "tps62361-vout";
	regulator-min-microvolt = <500000>;
	regulator-max-microvolt = <1500000>;
	regulator-boot-on;
	regulator-always-on;
	ti,vsel0-state-high;
	ti,vsel1-state-high;
	};
	};

	spi@7000da00 {
	status = "okay";
	spi-max-frequency = <25000000>;
	spi-flash@1 {
	compatible = "winbond,w25q32", "jedec,spi-nor";
	reg = <1>;
	spi-max-frequency = <20000000>;
	};
	};

	pmc@7000e400 {
	status = "okay";
	nvidia,invert-interrupt;
	nvidia,suspend-mode = <1>;
	nvidia,cpu-pwr-good-time = <2000>;
	nvidia,cpu-pwr-off-time = <200>;
	nvidia,core-pwr-good-time = <3845 3845>;
	nvidia,core-pwr-off-time = <0>;
	nvidia,core-power-req-active-high;
	nvidia,sys-clock-req-active-high;
	};

	ahub@70080000 {
	i2s@70080400 {
	status = "okay";
	};
	};

	sdhci@78000000 {
	status = "okay";
	cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
	power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
	bus-width = <4>;
	};

	sdhci@78000600 {
	status = "okay";
	bus-width = <8>;
	non-removable;
	};

	usb@7d008000 {
	status = "okay";
	};

	usb-phy@7d008000 {
	vbus-supply = <&usb3_vbus_reg>;
	status = "okay";
	};

	backlight: backlight {
	compatible = "pwm-backlight";

	enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
	power-supply = <&vdd_bl_reg>;
	pwms = <&pwm 0 5000000>;

	brightness-levels = <0 4 8 16 32 64 128 255>;
	default-brightness-level = <6>;
	};

	clocks {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	clk32k_in: clock@0 {
	compatible = "fixed-clock";
	reg = <0>;
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	};

	panel: panel {
	compatible = "chunghwa,claa101wb01", "simple-panel";
	ddc-i2c-bus = <&panelddc>;

	power-supply = <&vdd_pnl1_reg>;
	enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;

	backlight = <&backlight>;
	};

	regulators {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	vdd_ac_bat_reg: regulator@0 {
	compatible = "regulator-fixed";
	reg = <0>;
	regulator-name = "vdd_ac_bat";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	cam_1v8_reg: regulator@1 {
	compatible = "regulator-fixed";
	reg = <1>;
	regulator-name = "cam_1v8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
	vin-supply = <&vio_reg>;
	};

	cp_5v_reg: regulator@2 {
	compatible = "regulator-fixed";
	reg = <2>;
	regulator-name = "cp_5v";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-boot-on;
	regulator-always-on;
	enable-active-high;
	gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
	};

	emmc_3v3_reg: regulator@3 {
	compatible = "regulator-fixed";
	reg = <3>;
	regulator-name = "emmc_3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
	vin-supply = <&sys_3v3_reg>;
	};

	modem_3v3_reg: regulator@4 {
	compatible = "regulator-fixed";
	reg = <4>;
	regulator-name = "modem_3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
	};

	pex_hvdd_3v3_reg: regulator@5 {
	compatible = "regulator-fixed";
	reg = <5>;
	regulator-name = "pex_hvdd_3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
	vin-supply = <&sys_3v3_reg>;
	};

	vdd_cam1_ldo_reg: regulator@6 {
	compatible = "regulator-fixed";
	reg = <6>;
	regulator-name = "vdd_cam1_ldo";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
	vin-supply = <&sys_3v3_reg>;
	};

	vdd_cam2_ldo_reg: regulator@7 {
	compatible = "regulator-fixed";
	reg = <7>;
	regulator-name = "vdd_cam2_ldo";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
	vin-supply = <&sys_3v3_reg>;
	};

	vdd_cam3_ldo_reg: regulator@8 {
	compatible = "regulator-fixed";
	reg = <8>;
	regulator-name = "vdd_cam3_ldo";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
	vin-supply = <&sys_3v3_reg>;
	};

	vdd_com_reg: regulator@9 {
	compatible = "regulator-fixed";
	reg = <9>;
	regulator-name = "vdd_com";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
	vin-supply = <&sys_3v3_reg>;
	};

	vdd_fuse_3v3_reg: regulator@10 {
	compatible = "regulator-fixed";
	reg = <10>;
	regulator-name = "vdd_fuse_3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
	vin-supply = <&sys_3v3_reg>;
	};

	vdd_pnl1_reg: regulator@11 {
	compatible = "regulator-fixed";
	reg = <11>;
	regulator-name = "vdd_pnl1";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
	vin-supply = <&sys_3v3_reg>;
	};

	vdd_vid_reg: regulator@12 {
	compatible = "regulator-fixed";
	reg = <12>;
	regulator-name = "vddio_vid";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
	gpio-open-drain;
	vin-supply = <&vdd_5v0_reg>;
	};
	};

	sound {
	compatible = "nvidia,tegra-audio-wm8903-cardhu",
	"nvidia,tegra-audio-wm8903";
	nvidia,model = "NVIDIA Tegra Cardhu";

	nvidia,audio-routing =
	"Headphone Jack", "HPOUTR",
	"Headphone Jack", "HPOUTL",
	"Int Spk", "ROP",
	"Int Spk", "RON",
	"Int Spk", "LOP",
	"Int Spk", "LON",
	"Mic Jack", "MICBIAS",
	"IN1L", "Mic Jack";

	nvidia,i2s-controller = <&tegra_i2s1>;
	nvidia,audio-codec = <&wm8903>;

	nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
	nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
	GPIO_ACTIVE_HIGH>;

	clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
	<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
	- <&tegra_car TEGRA30_CLK_EXTERN1>;
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	clock-names = "pll_a", "pll_a_out0", "mclk";
	+
	+ assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	+
	+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
	+ <&tegra_car TEGRA30_CLK_EXTERN1>;
	};

	gpio-keys {
	compatible = "gpio-keys";

	power {
	label = "Power";
	interrupt-parent = <&pmic>;
	interrupts = <2 0>;
	linux,code = <KEY_POWER>;
	debounce-interval = <100>;
	wakeup-source;
	};

	volume-down {
	label = "Volume Down";
	gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
	linux,code = <KEY_VOLUMEDOWN>;
	debounce-interval = <10>;
	};

	volume-up {
	label = "Volume Up";
	gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
	linux,code = <KEY_VOLUMEUP>;
	debounce-interval = <10>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/tegra30-colibri.dtsi b/sys/gnu/dts/arm/tegra30-colibri.dtsi
	index 1f9198bb24ff..adba554381c7 100644
	--- a/sys/gnu/dts/arm/tegra30-colibri.dtsi
	+++ b/sys/gnu/dts/arm/tegra30-colibri.dtsi
	@@ -1,1045 +1,1051 @@
	// SPDX-License-Identifier: GPL-2.0
	#include "tegra30.dtsi"

	/*
	* Toradex Colibri T30 Module Device Tree
	* Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E, V1.1F; IT: V1.1A, V1.1B
	*/
	/ {
	memory@80000000 {
	reg = <0x80000000 0x40000000>;
	};

	host1x@50000000 {
	hdmi@54280000 {
	nvidia,ddc-i2c-bus = <&hdmi_ddc>;
	nvidia,hpd-gpio =
	<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
	pll-supply = <&reg_1v8_avdd_hdmi_pll>;
	vdd-supply = <&reg_3v3_avdd_hdmi>;
	};
	};

	pinmux@70000868 {
	pinctrl-names = "default";
	pinctrl-0 = <&state_default>;

	state_default: pinmux {
	/* Analogue Audio (On-module) */
	clk1-out-pw4 {
	nvidia,pins = "clk1_out_pw4";
	nvidia,function = "extperiph1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	dap3-fs-pp0 {
	nvidia,pins = "dap3_fs_pp0",
	"dap3_sclk_pp3",
	"dap3_din_pp1",
	"dap3_dout_pp2";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Colibri Address/Data Bus (GMI) */
	gmi-ad0-pg0 {
	nvidia,pins = "gmi_ad0_pg0",
	"gmi_ad2_pg2",
	"gmi_ad3_pg3",
	"gmi_ad4_pg4",
	"gmi_ad5_pg5",
	"gmi_ad6_pg6",
	"gmi_ad7_pg7",
	"gmi_ad8_ph0",
	"gmi_ad9_ph1",
	"gmi_ad10_ph2",
	"gmi_ad11_ph3",
	"gmi_ad12_ph4",
	"gmi_ad13_ph5",
	"gmi_ad14_ph6",
	"gmi_ad15_ph7",
	"gmi_adv_n_pk0",
	"gmi_clk_pk1",
	"gmi_cs4_n_pk2",
	"gmi_cs2_n_pk3",
	"gmi_iordy_pi5",
	"gmi_oe_n_pi1",
	"gmi_wait_pi7",
	"gmi_wr_n_pi0",
	"dap1_fs_pn0",
	"dap1_din_pn1",
	"dap1_dout_pn2",
	"dap1_sclk_pn3",
	"dap2_fs_pa2",
	"dap2_sclk_pa3",
	"dap2_din_pa4",
	"dap2_dout_pa5",
	"spi1_sck_px5",
	"spi1_mosi_px4",
	"spi1_cs0_n_px6",
	"spi2_cs0_n_px3",
	"spi2_miso_px1",
	"spi2_mosi_px0",
	"spi2_sck_px2",
	"uart2_cts_n_pj5",
	"uart2_rts_n_pj6";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	/* Further pins may be used as GPIOs */
	dap4-din-pp5 {
	nvidia,pins = "dap4_din_pp5",
	"dap4_dout_pp6",
	"dap4_fs_pp4",
	"dap4_sclk_pp7",
	"pbb7",
	"sdmmc1_clk_pz0",
	"sdmmc1_cmd_pz1",
	"sdmmc1_dat0_py7",
	"sdmmc1_dat1_py6",
	"sdmmc1_dat3_py4",
	"uart3_cts_n_pa1",
	"uart3_txd_pw6",
	"uart3_rxd_pw7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd-d18-pm2 {
	nvidia,pins = "lcd_d18_pm2",
	"lcd_d19_pm3",
	"lcd_d20_pm4",
	"lcd_d21_pm5",
	"lcd_d22_pm6",
	"lcd_d23_pm7",
	"lcd_dc0_pn6",
	"pex_l2_clkreq_n_pcc7";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd-cs0-n-pn4 {
	nvidia,pins = "lcd_cs0_n_pn4",
	"lcd_sdin_pz2",
	"pu0",
	"pu1",
	"pu2",
	"pu3",
	"pu4",
	"pu5",
	"pu6",
	"spi1_miso_px7",
	"uart3_rts_n_pc0";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd-pwr0-pb2 {
	nvidia,pins = "lcd_pwr0_pb2",
	"lcd_sck_pz4",
	"lcd_sdout_pn5",
	"lcd_wr_n_pz3";
	nvidia,function = "hdcp";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pbb4 {
	nvidia,pins = "pbb4",
	"pbb5",
	"pbb6";
	nvidia,function = "displayb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	/* Multiplexed RDnWR and therefore disabled */
	lcd-cs1-n-pw0 {
	nvidia,pins = "lcd_cs1_n_pw0";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	/* Multiplexed GMI_CLK and therefore disabled */
	owr {
	nvidia,pins = "owr";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	/* Tri-stating GMI_WR_N on nPWE SODIMM pin 99 */
	sdmmc3-dat4-pd1 {
	nvidia,pins = "sdmmc3_dat4_pd1";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	/* Not tri-stating GMI_WR_N on RDnWR SODIMM pin 93 */
	sdmmc3-dat5-pd0 {
	nvidia,pins = "sdmmc3_dat5_pd0";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Colibri BL_ON */
	pv2 {
	nvidia,pins = "pv2";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Colibri Backlight PWM<A> */
	sdmmc3-dat3-pb4 {
	nvidia,pins = "sdmmc3_dat3_pb4";
	nvidia,function = "pwm0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Colibri CAN_INT */
	kb-row8-ps0 {
	nvidia,pins = "kb_row8_ps0";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Colibri DDC */
	ddc-scl-pv4 {
	nvidia,pins = "ddc_scl_pv4",
	"ddc_sda_pv5";
	nvidia,function = "i2c4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Colibri EXT_IO* */
	gen2-i2c-scl-pt5 {
	nvidia,pins = "gen2_i2c_scl_pt5",
	"gen2_i2c_sda_pt6";
	nvidia,function = "rsvd4";
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	spdif-in-pk6 {
	nvidia,pins = "spdif_in_pk6";
	nvidia,function = "hda";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Colibri GPIO */
	clk2-out-pw5 {
	nvidia,pins = "clk2_out_pw5",
	"pcc2",
	"pv3",
	"sdmmc1_dat2_py5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	lcd-pwr1-pc1 {
	nvidia,pins = "lcd_pwr1_pc1",
	"pex_l1_clkreq_n_pdd6",
	"pex_l1_rst_n_pdd5";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	pv1 {
	nvidia,pins = "pv1",
	"sdmmc3_dat0_pb7",
	"sdmmc3_dat1_pb6";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Colibri HOTPLUG_DETECT (HDMI) */
	hdmi-int-pn7 {
	nvidia,pins = "hdmi_int_pn7";
	nvidia,function = "hdmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Colibri I2C */
	gen1-i2c-scl-pc4 {
	nvidia,pins = "gen1_i2c_scl_pc4",
	"gen1_i2c_sda_pc5";
	nvidia,function = "i2c1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};

	/* Colibri LCD (L_* resp. LDD<>) /
	lcd-d0-pe0 {
	nvidia,pins = "lcd_d0_pe0",
	"lcd_d1_pe1",
	"lcd_d2_pe2",
	"lcd_d3_pe3",
	"lcd_d4_pe4",
	"lcd_d5_pe5",
	"lcd_d6_pe6",
	"lcd_d7_pe7",
	"lcd_d8_pf0",
	"lcd_d9_pf1",
	"lcd_d10_pf2",
	"lcd_d11_pf3",
	"lcd_d12_pf4",
	"lcd_d13_pf5",
	"lcd_d14_pf6",
	"lcd_d15_pf7",
	"lcd_d16_pm0",
	"lcd_d17_pm1",
	"lcd_de_pj1",
	"lcd_hsync_pj3",
	"lcd_pclk_pb3",
	"lcd_vsync_pj4";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	/*
	* Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
	* today's display need DE, disable LCD_M1
	*/
	lcd-m1-pw1 {
	nvidia,pins = "lcd_m1_pw1";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Colibri MMC */
	kb-row10-ps2 {
	nvidia,pins = "kb_row10_ps2";
	nvidia,function = "sdmmc2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	kb-row11-ps3 {
	nvidia,pins = "kb_row11_ps3",
	"kb_row12_ps4",
	"kb_row13_ps5",
	"kb_row14_ps6",
	"kb_row15_ps7";
	nvidia,function = "sdmmc2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	/* Colibri MMC_CD */
	gmi-wp-n-pc7 {
	nvidia,pins = "gmi_wp_n_pc7";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	/* Multiplexed and therefore disabled */
	cam-mclk-pcc0 {
	nvidia,pins = "cam_mclk_pcc0";
	nvidia,function = "vi_alt3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	cam-i2c-scl-pbb1 {
	nvidia,pins = "cam_i2c_scl_pbb1",
	"cam_i2c_sda_pbb2";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pbb0 {
	nvidia,pins = "pbb0",
	"pcc1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	pbb3 {
	nvidia,pins = "pbb3";
	nvidia,function = "displayb";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Colibri nRESET_OUT */
	gmi-rst-n-pi4 {
	nvidia,pins = "gmi_rst_n_pi4";
	nvidia,function = "gmi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/*
	* Colibri Parallel Camera (Optional)
	* pins multiplexed with others and therefore disabled
	*/
	vi-vsync-pd6 {
	nvidia,pins = "vi_d0_pt4",
	"vi_d1_pd5",
	"vi_d2_pl0",
	"vi_d3_pl1",
	"vi_d4_pl2",
	"vi_d5_pl3",
	"vi_d6_pl4",
	"vi_d7_pl5",
	"vi_d8_pl6",
	"vi_d9_pl7",
	"vi_d10_pt2",
	"vi_d11_pt3",
	"vi_hsync_pd7",
	"vi_mclk_pt1",
	"vi_pclk_pt0",
	"vi_vsync_pd6";
	nvidia,function = "vi";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Colibri PWM<B> */
	sdmmc3-dat2-pb5 {
	nvidia,pins = "sdmmc3_dat2_pb5";
	nvidia,function = "pwm1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Colibri PWM<C> */
	sdmmc3-clk-pa6 {
	nvidia,pins = "sdmmc3_clk_pa6";
	nvidia,function = "pwm2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Colibri PWM<D> */
	sdmmc3-cmd-pa7 {
	nvidia,pins = "sdmmc3_cmd_pa7";
	nvidia,function = "pwm3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Colibri SSP */
	ulpi-clk-py0 {
	nvidia,pins = "ulpi_clk_py0",
	"ulpi_dir_py1",
	"ulpi_nxt_py2",
	"ulpi_stp_py3";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	/* Multiplexed SSPFRM, SSPTXD and therefore disabled */
	sdmmc3-dat6-pd3 {
	nvidia,pins = "sdmmc3_dat6_pd3",
	"sdmmc3_dat7_pd4";
	nvidia,function = "spdif";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Colibri UART-A */
	ulpi-data0 {
	nvidia,pins = "ulpi_data0_po1",
	"ulpi_data1_po2",
	"ulpi_data2_po3",
	"ulpi_data3_po4",
	"ulpi_data4_po5",
	"ulpi_data5_po6",
	"ulpi_data6_po7",
	"ulpi_data7_po0";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Colibri UART-B */
	gmi-a16-pj7 {
	nvidia,pins = "gmi_a16_pj7",
	"gmi_a17_pb0",
	"gmi_a18_pb1",
	"gmi_a19_pk7";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Colibri UART-C */
	uart2-rxd {
	nvidia,pins = "uart2_rxd_pc3",
	"uart2_txd_pc2";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Colibri USBC_DET */
	spdif-out-pk5 {
	nvidia,pins = "spdif_out_pk5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Colibri USBH_PEN */
	spi2-cs1-n-pw2 {
	nvidia,pins = "spi2_cs1_n_pw2";
	nvidia,function = "spi2_alt";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};

	/* Colibri USBH_OC */
	spi2-cs2-n-pw3, {
	nvidia,pins = "spi2_cs2_n_pw3";
	nvidia,function = "spi2_alt";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Colibri VGA not supported and therefore disabled */
	crt-hsync-pv6 {
	nvidia,pins = "crt_hsync_pv6",
	"crt_vsync_pv7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* eMMC (On-module) */
	sdmmc4-clk-pcc4 {
	nvidia,pins = "sdmmc4_clk_pcc4",
	"sdmmc4_cmd_pt7",
	"sdmmc4_rst_n_pcc3";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	sdmmc4-dat0-paa0 {
	nvidia,pins = "sdmmc4_dat0_paa0",
	"sdmmc4_dat1_paa1",
	"sdmmc4_dat2_paa2",
	"sdmmc4_dat3_paa3",
	"sdmmc4_dat4_paa4",
	"sdmmc4_dat5_paa5",
	"sdmmc4_dat6_paa6",
	"sdmmc4_dat7_paa7";
	nvidia,function = "sdmmc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* LAN_EXT_WAKEUP#, LAN_PME (On-module) */
	pex-l0-rst-n-pdd1 {
	nvidia,pins = "pex_l0_rst_n_pdd1",
	"pex_wake_n_pdd3";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	/* LAN_V_BUS, LAN_RESET# (On-module) */
	pex-l0-clkreq-n-pdd2 {
	nvidia,pins = "pex_l0_clkreq_n_pdd2",
	"pex_l0_prsnt_n_pdd0";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* nBATT_FAULT(SENSE), nVDD_FAULT(SENSE) */
	pex-l2-rst-n-pcc6 {
	nvidia,pins = "pex_l2_rst_n_pcc6",
	"pex_l2_prsnt_n_pdd7";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};

	/* Not connected and therefore disabled */
	clk1-req-pee2 {
	nvidia,pins = "clk1_req_pee2",
	"pex_l1_prsnt_n_pdd4";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	clk2-req-pcc5 {
	nvidia,pins = "clk2_req_pcc5",
	"clk3_out_pee0",
	"clk3_req_pee1",
	"clk_32k_out_pa0",
	"hdmi_cec_pee3",
	"sys_clk_req_pz5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	gmi-dqs-pi2 {
	nvidia,pins = "gmi_dqs_pi2",
	"kb_col2_pq2",
	"kb_col3_pq3",
	"kb_col4_pq4",
	"kb_col5_pq5",
	"kb_row4_pr4";
	nvidia,function = "rsvd4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-col0-pq0 {
	nvidia,pins = "kb_col0_pq0",
	"kb_col1_pq1",
	"kb_col6_pq6",
	"kb_col7_pq7",
	"kb_row5_pr5",
	"kb_row6_pr6",
	"kb_row7_pr7",
	"kb_row9_ps1";
	nvidia,function = "kbc";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	kb-row0-pr0 {
	nvidia,pins = "kb_row0_pr0",
	"kb_row1_pr1",
	"kb_row2_pr2",
	"kb_row3_pr3";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};
	lcd-pwr2-pc6 {
	nvidia,pins = "lcd_pwr2_pc6";
	nvidia,function = "hdcp";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* Power I2C (On-module) */
	pwr-i2c-scl-pz6 {
	nvidia,pins = "pwr_i2c_scl_pz6",
	"pwr_i2c_sda_pz7";
	nvidia,function = "i2cpwr";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};

	/*
	* THERMD_ALERT#, unlatched I2C address pin of LM95245
	* temperature sensor therefore requires disabling for
	* now
	*/
	lcd-dc1-pd2 {
	nvidia,pins = "lcd_dc1_pd2";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	};

	/* TOUCH_PEN_INT# (On-module) */
	pv0 {
	nvidia,pins = "pv0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	};
	};
	};

	serial@70006040 {
	compatible = "nvidia,tegra30-hsuart";
	};

	serial@70006300 {
	compatible = "nvidia,tegra30-hsuart";
	};

	hdmi_ddc: i2c@7000c700 {
	clock-frequency = <10000>;
	};

	/*
	* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
	* touch screen controller (On-module)
	*/
	i2c@7000d000 {
	status = "okay";
	clock-frequency = <100000>;

	/* SGTL5000 audio codec */
	sgtl5000: codec@a {
	compatible = "fsl,sgtl5000";
	reg = <0x0a>;
	VDDA-supply = <&reg_module_3v3_audio>;
	VDDD-supply = <&reg_1v8_vio>;
	VDDIO-supply = <&reg_module_3v3>;
	clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
	};

	pmic: pmic@2d {
	compatible = "ti,tps65911";
	reg = <0x2d>;

	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <2>;
	interrupt-controller;

	ti,system-power-controller;

	#gpio-cells = <2>;
	gpio-controller;

	vcc1-supply = <&reg_module_3v3>;
	vcc2-supply = <&reg_module_3v3>;
	vcc3-supply = <&reg_1v8_vio>;
	vcc4-supply = <&reg_module_3v3>;
	vcc5-supply = <&reg_module_3v3>;
	vcc6-supply = <&reg_1v8_vio>;
	vcc7-supply = <&reg_5v0_charge_pump>;
	vccio-supply = <&reg_module_3v3>;

	regulators {
	vdd1_reg: vdd1 {
	regulator-name = "+V1.35_VDDIO_DDR";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	};

	/* SW2: unused */

	vddctrl_reg: vddctrl {
	regulator-name = "+V1.0_VDD_CPU";
	regulator-min-microvolt = <1150000>;
	regulator-max-microvolt = <1150000>;
	regulator-always-on;
	};

	reg_1v8_vio: vio {
	regulator-name = "+V1.8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	/* LDO1: unused */

	/*
	* EN_+V3.3 switching via FET:
	* +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
	* see also +V3.3 fixed supply
	*/
	ldo2_reg: ldo2 {
	regulator-name = "EN_+V3.3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	/* LDO3: unused */

	ldo4_reg: ldo4 {
	regulator-name = "+V1.2_VDD_RTC";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	/*
	* +V2.8_AVDD_VDAC:
	* only required for (unsupported) analog RGB
	*/
	ldo5_reg: ldo5 {
	regulator-name = "+V2.8_AVDD_VDAC";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-always-on;
	};

	/*
	* +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
	* but LDO6 can't set voltage in 50mV
	* granularity
	*/
	ldo6_reg: ldo6 {
	regulator-name = "+V1.05_AVDD_PLLE";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	};

	ldo7_reg: ldo7 {
	regulator-name = "+V1.2_AVDD_PLL";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	};

	ldo8_reg: ldo8 {
	regulator-name = "+V1.0_VDD_DDR_HS";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	};
	};
	};

	/* STMPE811 touch screen controller */
	touchscreen@41 {
	compatible = "st,stmpe811";
	reg = <0x41>;
	irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;
	id = <0>;
	blocks = <0x5>;
	irq-trigger = <0x1>;
	/* 3.25 MHz ADC clock speed */
	st,adc-freq = <1>;
	/* 12-bit ADC */
	st,mod-12b = <1>;
	/* internal ADC reference */
	st,ref-sel = <0>;
	/* ADC converstion time: 80 clocks */
	st,sample-time = <4>;
	/* forbid to use ADC channels 3-0 (touch) */

	stmpe_touchscreen {
	compatible = "st,stmpe-ts";
	/* 8 sample average control */
	st,ave-ctrl = <3>;
	/* 7 length fractional part in z */
	st,fraction-z = <7>;
	/*
	* 50 mA typical 80 mA max touchscreen drivers
	* current limit value
	*/
	st,i-drive = <1>;
	/* 1 ms panel driver settling time */
	st,settling = <3>;
	/* 5 ms touch detect interrupt delay */
	st,touch-det-delay = <5>;
	};

	stmpe_adc {
	compatible = "st,stmpe-adc";
	st,norequest-mask = <0x0F>;
	};
	};

	/*
	* LM95245 temperature sensor
	* Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
	*/
	temp-sensor@4c {
	compatible = "national,lm95245";
	reg = <0x4c>;
	};

	/* SW: +V1.2_VDD_CORE */
	regulator@60 {
	compatible = "ti,tps62362";
	reg = <0x60>;

	regulator-name = "tps62362-vout";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1400000>;
	regulator-boot-on;
	regulator-always-on;
	ti,vsel0-state-low;
	/* VSEL1: EN_CORE_DVFS_N low for DVFS */
	ti,vsel1-state-low;
	};
	};

	pmc@7000e400 {
	nvidia,invert-interrupt;
	nvidia,suspend-mode = <1>;
	nvidia,cpu-pwr-good-time = <5000>;
	nvidia,cpu-pwr-off-time = <5000>;
	nvidia,core-pwr-good-time = <3845 3845>;
	nvidia,core-pwr-off-time = <0>;
	nvidia,core-power-req-active-high;
	nvidia,sys-clock-req-active-high;

	/* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
	i2c-thermtrip {
	nvidia,i2c-controller-id = <4>;
	nvidia,bus-addr = <0x2d>;
	nvidia,reg-addr = <0x3f>;
	nvidia,reg-data = <0x1>;
	};
	};

	hda@70030000 {
	status = "okay";
	};

	ahub@70080000 {
	i2s@70080500 {
	status = "okay";
	};
	};

	/* eMMC */
	sdhci@78000600 {
	status = "okay";
	bus-width = <8>;
	non-removable;
	vmmc-supply = <&reg_module_3v3>; /* VCC */
	vqmmc-supply = <&reg_1v8_vio>; /* VCCQ */
	mmc-ddr-1_8v;
	};

	/* EHCI instance 1: USB2_DP/N -> AX88772B (On-module) */
	usb@7d004000 {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	asix@1 {
	reg = <1>;
	local-mac-address = [00 00 00 00 00 00];
	};
	};

	usb-phy@7d004000 {
	status = "okay";
	vbus-supply = <&reg_lan_v_bus>;
	};

	clk32k_in: xtal1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};

	reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
	compatible = "regulator-fixed";
	regulator-name = "+V1.8_AVDD_HDMI_PLL";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	enable-active-high;
	gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
	vin-supply = <&reg_1v8_vio>;
	};

	reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3_AVDD_HDMI";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	enable-active-high;
	gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
	vin-supply = <&reg_module_3v3>;
	};

	reg_5v0_charge_pump: regulator-5v0-charge-pump {
	compatible = "regulator-fixed";
	regulator-name = "+V5.0";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	reg_lan_v_bus: regulator-lan-v-bus {
	compatible = "regulator-fixed";
	regulator-name = "LAN_V_BUS";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	enable-active-high;
	gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
	};

	reg_module_3v3: regulator-module-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_module_3v3_audio: regulator-module-3v3-audio {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3_AUDIO_AVDD_S";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	sound {
	compatible = "toradex,tegra-audio-sgtl5000-colibri_t30",
	"nvidia,tegra-audio-sgtl5000";
	nvidia,model = "Toradex Colibri T30";
	nvidia,audio-routing =
	"Headphone Jack", "HP_OUT",
	"LINE_IN", "Line In Jack",
	"MIC_IN", "Mic Jack";
	nvidia,i2s-controller = <&tegra_i2s2>;
	nvidia,audio-codec = <&sgtl5000>;
	clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
	<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
	- <&tegra_car TEGRA30_CLK_EXTERN1>;
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	clock-names = "pll_a", "pll_a_out0", "mclk";
	+
	+ assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
	+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
	+
	+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
	+ <&tegra_car TEGRA30_CLK_EXTERN1>;
	};
	};

	&gpio {
	lan-reset-n {
	gpio-hog;
	gpios = <TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
	output-high;
	line-name = "LAN_RESET#";
	};
	};
	diff --git a/sys/gnu/dts/arm/tegra30.dtsi b/sys/gnu/dts/arm/tegra30.dtsi
	index 55ae050042ce..d2d05f1da274 100644
	--- a/sys/gnu/dts/arm/tegra30.dtsi
	+++ b/sys/gnu/dts/arm/tegra30.dtsi
	@@ -1,1046 +1,1048 @@
	// SPDX-License-Identifier: GPL-2.0
	#include <dt-bindings/clock/tegra30-car.h>
	#include <dt-bindings/gpio/tegra-gpio.h>
	#include <dt-bindings/memory/tegra30-mc.h>
	#include <dt-bindings/pinctrl/pinctrl-tegra.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	+#include <dt-bindings/soc/tegra-pmc.h>

	/ {
	compatible = "nvidia,tegra30";
	interrupt-parent = <&lic>;
	#address-cells = <1>;
	#size-cells = <1>;

	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x0>;
	};

	pcie@3000 {
	compatible = "nvidia,tegra30-pcie";
	device_type = "pci";
	reg = <0x00003000 0x00000800 /* PADS registers */
	0x00003800 0x00000200 /* AFI registers */
	0x10000000 0x10000000>; /* configuration space */
	reg-names = "pads", "afi", "cs";
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
	GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
	interrupt-names = "intr", "msi";

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

	bus-range = <0x00 0xff>;
	#address-cells = <3>;
	#size-cells = <2>;

	ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
	0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
	0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
	0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
	0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
	0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */

	clocks = <&tegra_car TEGRA30_CLK_PCIE>,
	<&tegra_car TEGRA30_CLK_AFI>,
	<&tegra_car TEGRA30_CLK_PLL_E>,
	<&tegra_car TEGRA30_CLK_CML0>;
	clock-names = "pex", "afi", "pll_e", "cml";
	resets = <&tegra_car 70>,
	<&tegra_car 72>,
	<&tegra_car 74>;
	reset-names = "pex", "afi", "pcie_x";
	status = "disabled";

	pci@1,0 {
	device_type = "pci";
	assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
	reg = <0x000800 0 0 0 0>;
	bus-range = <0x00 0xff>;
	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	ranges;

	nvidia,num-lanes = <2>;
	};

	pci@2,0 {
	device_type = "pci";
	assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
	reg = <0x001000 0 0 0 0>;
	bus-range = <0x00 0xff>;
	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	ranges;

	nvidia,num-lanes = <2>;
	};

	pci@3,0 {
	device_type = "pci";
	assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
	reg = <0x001800 0 0 0 0>;
	bus-range = <0x00 0xff>;
	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	ranges;

	nvidia,num-lanes = <2>;
	};
	};

	iram@40000000 {
	compatible = "mmio-sram";
	reg = <0x40000000 0x40000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x40000000 0x40000>;

	vde_pool: vde@400 {
	reg = <0x400 0x3fc00>;
	pool;
	};
	};

	host1x@50000000 {
	compatible = "nvidia,tegra30-host1x", "simple-bus";
	reg = <0x50000000 0x00024000>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
	clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
	resets = <&tegra_car 28>;
	reset-names = "host1x";
	iommus = <&mc TEGRA_SWGROUP_HC>;

	#address-cells = <1>;
	#size-cells = <1>;

	ranges = <0x54000000 0x54000000 0x04000000>;

	mpe@54040000 {
	compatible = "nvidia,tegra30-mpe";
	reg = <0x54040000 0x00040000>;
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_MPE>;
	resets = <&tegra_car 60>;
	reset-names = "mpe";

	iommus = <&mc TEGRA_SWGROUP_MPE>;
	};

	vi@54080000 {
	compatible = "nvidia,tegra30-vi";
	reg = <0x54080000 0x00040000>;
	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_VI>;
	resets = <&tegra_car 20>;
	reset-names = "vi";

	iommus = <&mc TEGRA_SWGROUP_VI>;
	};

	epp@540c0000 {
	compatible = "nvidia,tegra30-epp";
	reg = <0x540c0000 0x00040000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_EPP>;
	resets = <&tegra_car 19>;
	reset-names = "epp";

	iommus = <&mc TEGRA_SWGROUP_EPP>;
	};

	isp@54100000 {
	compatible = "nvidia,tegra30-isp";
	reg = <0x54100000 0x00040000>;
	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_ISP>;
	resets = <&tegra_car 23>;
	reset-names = "isp";

	iommus = <&mc TEGRA_SWGROUP_ISP>;
	};

	gr2d@54140000 {
	compatible = "nvidia,tegra30-gr2d";
	reg = <0x54140000 0x00040000>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_GR2D>;
	resets = <&tegra_car 21>;
	reset-names = "2d";

	iommus = <&mc TEGRA_SWGROUP_G2>;
	};

	gr3d@54180000 {
	compatible = "nvidia,tegra30-gr3d";
	reg = <0x54180000 0x00040000>;
	clocks = <&tegra_car TEGRA30_CLK_GR3D
	&tegra_car TEGRA30_CLK_GR3D2>;
	clock-names = "3d", "3d2";
	resets = <&tegra_car 24>,
	<&tegra_car 98>;
	reset-names = "3d", "3d2";

	iommus = <&mc TEGRA_SWGROUP_NV>,
	<&mc TEGRA_SWGROUP_NV2>;
	};

	dc@54200000 {
	compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
	reg = <0x54200000 0x00040000>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_DISP1>,
	<&tegra_car TEGRA30_CLK_PLL_P>;
	clock-names = "dc", "parent";
	resets = <&tegra_car 27>;
	reset-names = "dc";

	iommus = <&mc TEGRA_SWGROUP_DC>;

	nvidia,head = <0>;

	rgb {
	status = "disabled";
	};
	};

	dc@54240000 {
	compatible = "nvidia,tegra30-dc";
	reg = <0x54240000 0x00040000>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_DISP2>,
	<&tegra_car TEGRA30_CLK_PLL_P>;
	clock-names = "dc", "parent";
	resets = <&tegra_car 26>;
	reset-names = "dc";

	iommus = <&mc TEGRA_SWGROUP_DCB>;

	nvidia,head = <1>;

	rgb {
	status = "disabled";
	};
	};

	hdmi@54280000 {
	compatible = "nvidia,tegra30-hdmi";
	reg = <0x54280000 0x00040000>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_HDMI>,
	<&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
	clock-names = "hdmi", "parent";
	resets = <&tegra_car 51>;
	reset-names = "hdmi";
	status = "disabled";
	};

	tvo@542c0000 {
	compatible = "nvidia,tegra30-tvo";
	reg = <0x542c0000 0x00040000>;
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_TVO>;
	status = "disabled";
	};

	dsi@54300000 {
	compatible = "nvidia,tegra30-dsi";
	reg = <0x54300000 0x00040000>;
	clocks = <&tegra_car TEGRA30_CLK_DSIA>;
	resets = <&tegra_car 48>;
	reset-names = "dsi";
	status = "disabled";
	};
	};

	timer@50040600 {
	compatible = "arm,cortex-a9-twd-timer";
	reg = <0x50040600 0x20>;
	interrupt-parent = <&intc>;
	interrupts = <GIC_PPI 13
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_EDGE_RISING)>;
	clocks = <&tegra_car TEGRA30_CLK_TWD>;
	};

	intc: interrupt-controller@50041000 {
	compatible = "arm,cortex-a9-gic";
	reg = <0x50041000 0x1000
	0x50040100 0x0100>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&intc>;
	};

	cache-controller@50043000 {
	compatible = "arm,pl310-cache";
	reg = <0x50043000 0x1000>;
	arm,data-latency = <6 6 2>;
	arm,tag-latency = <5 5 2>;
	cache-unified;
	cache-level = <2>;
	};

	lic: interrupt-controller@60004000 {
	compatible = "nvidia,tegra30-ictlr";
	reg = <0x60004000 0x100>,
	<0x60004100 0x50>,
	<0x60004200 0x50>,
	<0x60004300 0x50>,
	<0x60004400 0x50>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&intc>;
	};

	timer@60005000 {
	compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
	reg = <0x60005000 0x400>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_TIMER>;
	};

	tegra_car: clock@60006000 {
	compatible = "nvidia,tegra30-car";
	reg = <0x60006000 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	flow-controller@60007000 {
	compatible = "nvidia,tegra30-flowctrl";
	reg = <0x60007000 0x1000>;
	};

	apbdma: dma@6000a000 {
	compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
	reg = <0x6000a000 0x1400>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
	resets = <&tegra_car 34>;
	reset-names = "dma";
	#dma-cells = <1>;
	};

	ahb: ahb@6000c000 {
	compatible = "nvidia,tegra30-ahb";
	reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
	};

	actmon@6000c800 {
	compatible = "nvidia,tegra30-actmon";
	reg = <0x6000c800 0x400>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_ACTMON>,
	<&tegra_car TEGRA30_CLK_EMC>;
	clock-names = "actmon", "emc";
	resets = <&tegra_car TEGRA30_CLK_ACTMON>;
	reset-names = "actmon";
	};

	gpio: gpio@6000d000 {
	compatible = "nvidia,tegra30-gpio";
	reg = <0x6000d000 0x1000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	#interrupt-cells = <2>;
	interrupt-controller;
	/*
	gpio-ranges = <&pinmux 0 0 248>;
	*/
	};

	vde@6001a000 {
	compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
	reg = <0x6001a000 0x1000 /* Syntax Engine */
	0x6001b000 0x1000 /* Video Bitstream Engine */
	0x6001c000 0x100 /* Macroblock Engine */
	0x6001c200 0x100 /* Post-processing Engine */
	0x6001c400 0x100 /* Motion Compensation Engine */
	0x6001c600 0x100 /* Transform Engine */
	0x6001c800 0x100 /* Pixel prediction block */
	0x6001ca00 0x100 /* Video DMA */
	0x6001d800 0x400>; /* Video frame controls */
	reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
	"tfe", "ppb", "vdma", "frameid";
	iram = <&vde_pool>; /* IRAM region */
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
	<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
	interrupt-names = "sync-token", "bsev", "sxe";
	clocks = <&tegra_car TEGRA30_CLK_VDE>;
	reset-names = "vde", "mc";
	resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
	iommus = <&mc TEGRA_SWGROUP_VDE>;
	};

	apbmisc@70000800 {
	compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
	reg = <0x70000800 0x64 /* Chip revision */
	0x70000008 0x04>; /* Strapping options */
	};

	pinmux: pinmux@70000868 {
	compatible = "nvidia,tegra30-pinmux";
	reg = <0x70000868 0xd4 /* Pad control registers */
	0x70003000 0x3e4>; /* Mux registers */
	};

	/*
	* There are two serial driver i.e. 8250 based simple serial
	* driver and APB DMA based serial driver for higher baudrate
	* and performace. To enable the 8250 based driver, the compatible
	* is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
	* the APB DMA based serial driver, the compatible is
	* "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
	*/
	uarta: serial@70006000 {
	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	reg = <0x70006000 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_UARTA>;
	resets = <&tegra_car 6>;
	reset-names = "serial";
	dmas = <&apbdma 8>, <&apbdma 8>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartb: serial@70006040 {
	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	reg = <0x70006040 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_UARTB>;
	resets = <&tegra_car 7>;
	reset-names = "serial";
	dmas = <&apbdma 9>, <&apbdma 9>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartc: serial@70006200 {
	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	reg = <0x70006200 0x100>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_UARTC>;
	resets = <&tegra_car 55>;
	reset-names = "serial";
	dmas = <&apbdma 10>, <&apbdma 10>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartd: serial@70006300 {
	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	reg = <0x70006300 0x100>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_UARTD>;
	resets = <&tegra_car 65>;
	reset-names = "serial";
	dmas = <&apbdma 19>, <&apbdma 19>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uarte: serial@70006400 {
	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	reg = <0x70006400 0x100>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_UARTE>;
	resets = <&tegra_car 66>;
	reset-names = "serial";
	dmas = <&apbdma 20>, <&apbdma 20>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	gmi@70009000 {
	compatible = "nvidia,tegra30-gmi";
	reg = <0x70009000 0x1000>;
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0x48000000 0x7ffffff>;
	clocks = <&tegra_car TEGRA30_CLK_NOR>;
	clock-names = "gmi";
	resets = <&tegra_car 42>;
	reset-names = "gmi";
	status = "disabled";
	};

	pwm: pwm@7000a000 {
	compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
	reg = <0x7000a000 0x100>;
	#pwm-cells = <2>;
	clocks = <&tegra_car TEGRA30_CLK_PWM>;
	resets = <&tegra_car 17>;
	reset-names = "pwm";
	status = "disabled";
	};

	rtc@7000e000 {
	compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
	reg = <0x7000e000 0x100>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_RTC>;
	};

	i2c@7000c000 {
	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	reg = <0x7000c000 0x100>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA30_CLK_I2C1>,
	<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
	clock-names = "div-clk", "fast-clk";
	resets = <&tegra_car 12>;
	reset-names = "i2c";
	dmas = <&apbdma 21>, <&apbdma 21>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000c400 {
	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	reg = <0x7000c400 0x100>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA30_CLK_I2C2>,
	<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
	clock-names = "div-clk", "fast-clk";
	resets = <&tegra_car 54>;
	reset-names = "i2c";
	dmas = <&apbdma 22>, <&apbdma 22>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000c500 {
	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	reg = <0x7000c500 0x100>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA30_CLK_I2C3>,
	<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
	clock-names = "div-clk", "fast-clk";
	resets = <&tegra_car 67>;
	reset-names = "i2c";
	dmas = <&apbdma 23>, <&apbdma 23>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000c700 {
	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	reg = <0x7000c700 0x100>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA30_CLK_I2C4>,
	<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
	resets = <&tegra_car 103>;
	reset-names = "i2c";
	clock-names = "div-clk", "fast-clk";
	dmas = <&apbdma 26>, <&apbdma 26>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000d000 {
	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	reg = <0x7000d000 0x100>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA30_CLK_I2C5>,
	<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
	clock-names = "div-clk", "fast-clk";
	resets = <&tegra_car 47>;
	reset-names = "i2c";
	dmas = <&apbdma 24>, <&apbdma 24>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000d400 {
	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	reg = <0x7000d400 0x200>;
	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA30_CLK_SBC1>;
	resets = <&tegra_car 41>;
	reset-names = "spi";
	dmas = <&apbdma 15>, <&apbdma 15>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000d600 {
	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	reg = <0x7000d600 0x200>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA30_CLK_SBC2>;
	resets = <&tegra_car 44>;
	reset-names = "spi";
	dmas = <&apbdma 16>, <&apbdma 16>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000d800 {
	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	reg = <0x7000d800 0x200>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA30_CLK_SBC3>;
	resets = <&tegra_car 46>;
	reset-names = "spi";
	dmas = <&apbdma 17>, <&apbdma 17>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000da00 {
	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	reg = <0x7000da00 0x200>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA30_CLK_SBC4>;
	resets = <&tegra_car 68>;
	reset-names = "spi";
	dmas = <&apbdma 18>, <&apbdma 18>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000dc00 {
	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	reg = <0x7000dc00 0x200>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA30_CLK_SBC5>;
	resets = <&tegra_car 104>;
	reset-names = "spi";
	dmas = <&apbdma 27>, <&apbdma 27>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000de00 {
	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	reg = <0x7000de00 0x200>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA30_CLK_SBC6>;
	resets = <&tegra_car 106>;
	reset-names = "spi";
	dmas = <&apbdma 28>, <&apbdma 28>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	kbc@7000e200 {
	compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
	reg = <0x7000e200 0x100>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_KBC>;
	resets = <&tegra_car 36>;
	reset-names = "kbc";
	status = "disabled";
	};

	- pmc@7000e400 {
	+ tegra_pmc: pmc@7000e400 {
	compatible = "nvidia,tegra30-pmc";
	reg = <0x7000e400 0x400>;
	clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
	clock-names = "pclk", "clk32k_in";
	+ #clock-cells = <1>;
	};

	mc: memory-controller@7000f000 {
	compatible = "nvidia,tegra30-mc";
	reg = <0x7000f000 0x400>;
	clocks = <&tegra_car TEGRA30_CLK_MC>;
	clock-names = "mc";

	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;

	#iommu-cells = <1>;
	#reset-cells = <1>;
	};

	memory-controller@7000f400 {
	compatible = "nvidia,tegra30-emc";
	reg = <0x7000f400 0x400>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_EMC>;

	nvidia,memory-controller = <&mc>;
	};

	fuse@7000f800 {
	compatible = "nvidia,tegra30-efuse";
	reg = <0x7000f800 0x400>;
	clocks = <&tegra_car TEGRA30_CLK_FUSE>;
	clock-names = "fuse";
	resets = <&tegra_car 39>;
	reset-names = "fuse";
	};

	hda@70030000 {
	compatible = "nvidia,tegra30-hda";
	reg = <0x70030000 0x10000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_HDA>,
	<&tegra_car TEGRA30_CLK_HDA2HDMI>,
	<&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
	clock-names = "hda", "hda2hdmi", "hda2codec_2x";
	resets = <&tegra_car 125>, /* hda */
	<&tegra_car 128>, /* hda2hdmi */
	<&tegra_car 111>; /* hda2codec_2x */
	reset-names = "hda", "hda2hdmi", "hda2codec_2x";
	status = "disabled";
	};

	ahub@70080000 {
	compatible = "nvidia,tegra30-ahub";
	reg = <0x70080000 0x200
	0x70080200 0x100>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
	<&tegra_car TEGRA30_CLK_APBIF>;
	clock-names = "d_audio", "apbif";
	resets = <&tegra_car 106>, /* d_audio */
	<&tegra_car 107>, /* apbif */
	<&tegra_car 30>, /* i2s0 */
	<&tegra_car 11>, /* i2s1 */
	<&tegra_car 18>, /* i2s2 */
	<&tegra_car 101>, /* i2s3 */
	<&tegra_car 102>, /* i2s4 */
	<&tegra_car 108>, /* dam0 */
	<&tegra_car 109>, /* dam1 */
	<&tegra_car 110>, /* dam2 */
	<&tegra_car 10>; /* spdif */
	reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
	"i2s3", "i2s4", "dam0", "dam1", "dam2",
	"spdif";
	dmas = <&apbdma 1>, <&apbdma 1>,
	<&apbdma 2>, <&apbdma 2>,
	<&apbdma 3>, <&apbdma 3>,
	<&apbdma 4>, <&apbdma 4>;
	dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
	"rx3", "tx3";
	ranges;
	#address-cells = <1>;
	#size-cells = <1>;

	tegra_i2s0: i2s@70080300 {
	compatible = "nvidia,tegra30-i2s";
	reg = <0x70080300 0x100>;
	nvidia,ahub-cif-ids = <4 4>;
	clocks = <&tegra_car TEGRA30_CLK_I2S0>;
	resets = <&tegra_car 30>;
	reset-names = "i2s";
	status = "disabled";
	};

	tegra_i2s1: i2s@70080400 {
	compatible = "nvidia,tegra30-i2s";
	reg = <0x70080400 0x100>;
	nvidia,ahub-cif-ids = <5 5>;
	clocks = <&tegra_car TEGRA30_CLK_I2S1>;
	resets = <&tegra_car 11>;
	reset-names = "i2s";
	status = "disabled";
	};

	tegra_i2s2: i2s@70080500 {
	compatible = "nvidia,tegra30-i2s";
	reg = <0x70080500 0x100>;
	nvidia,ahub-cif-ids = <6 6>;
	clocks = <&tegra_car TEGRA30_CLK_I2S2>;
	resets = <&tegra_car 18>;
	reset-names = "i2s";
	status = "disabled";
	};

	tegra_i2s3: i2s@70080600 {
	compatible = "nvidia,tegra30-i2s";
	reg = <0x70080600 0x100>;
	nvidia,ahub-cif-ids = <7 7>;
	clocks = <&tegra_car TEGRA30_CLK_I2S3>;
	resets = <&tegra_car 101>;
	reset-names = "i2s";
	status = "disabled";
	};

	tegra_i2s4: i2s@70080700 {
	compatible = "nvidia,tegra30-i2s";
	reg = <0x70080700 0x100>;
	nvidia,ahub-cif-ids = <8 8>;
	clocks = <&tegra_car TEGRA30_CLK_I2S4>;
	resets = <&tegra_car 102>;
	reset-names = "i2s";
	status = "disabled";
	};
	};

	sdhci@78000000 {
	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	reg = <0x78000000 0x200>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
	resets = <&tegra_car 14>;
	reset-names = "sdhci";
	status = "disabled";
	};

	sdhci@78000200 {
	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	reg = <0x78000200 0x200>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
	resets = <&tegra_car 9>;
	reset-names = "sdhci";
	status = "disabled";
	};

	sdhci@78000400 {
	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	reg = <0x78000400 0x200>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
	resets = <&tegra_car 69>;
	reset-names = "sdhci";
	status = "disabled";
	};

	sdhci@78000600 {
	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	reg = <0x78000600 0x200>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
	resets = <&tegra_car 15>;
	reset-names = "sdhci";
	status = "disabled";
	};

	usb@7d000000 {
	compatible = "nvidia,tegra30-ehci", "usb-ehci";
	reg = <0x7d000000 0x4000>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA30_CLK_USBD>;
	resets = <&tegra_car 22>;
	reset-names = "usb";
	nvidia,needs-double-reset;
	nvidia,phy = <&phy1>;
	status = "disabled";
	};

	phy1: usb-phy@7d000000 {
	compatible = "nvidia,tegra30-usb-phy";
	reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA30_CLK_USBD>,
	<&tegra_car TEGRA30_CLK_PLL_U>,
	<&tegra_car TEGRA30_CLK_USBD>;
	clock-names = "reg", "pll_u", "utmi-pads";
	resets = <&tegra_car 22>, <&tegra_car 22>;
	reset-names = "usb", "utmi-pads";
	nvidia,hssync-start-delay = <9>;
	nvidia,idle-wait-delay = <17>;
	nvidia,elastic-limit = <16>;
	nvidia,term-range-adj = <6>;
	nvidia,xcvr-setup = <51>;
	nvidia,xcvr-setup-use-fuses;
	nvidia,xcvr-lsfslew = <1>;
	nvidia,xcvr-lsrslew = <1>;
	nvidia,xcvr-hsslew = <32>;
	nvidia,hssquelch-level = <2>;
	nvidia,hsdiscon-level = <5>;
	nvidia,has-utmi-pad-registers;
	status = "disabled";
	};

	usb@7d004000 {
	compatible = "nvidia,tegra30-ehci", "usb-ehci";
	reg = <0x7d004000 0x4000>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA30_CLK_USB2>;
	resets = <&tegra_car 58>;
	reset-names = "usb";
	nvidia,phy = <&phy2>;
	status = "disabled";
	};

	phy2: usb-phy@7d004000 {
	compatible = "nvidia,tegra30-usb-phy";
	reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA30_CLK_USB2>,
	<&tegra_car TEGRA30_CLK_PLL_U>,
	<&tegra_car TEGRA30_CLK_USBD>;
	clock-names = "reg", "pll_u", "utmi-pads";
	resets = <&tegra_car 58>, <&tegra_car 22>;
	reset-names = "usb", "utmi-pads";
	nvidia,hssync-start-delay = <9>;
	nvidia,idle-wait-delay = <17>;
	nvidia,elastic-limit = <16>;
	nvidia,term-range-adj = <6>;
	nvidia,xcvr-setup = <51>;
	nvidia,xcvr-setup-use-fuses;
	nvidia,xcvr-lsfslew = <2>;
	nvidia,xcvr-lsrslew = <2>;
	nvidia,xcvr-hsslew = <32>;
	nvidia,hssquelch-level = <2>;
	nvidia,hsdiscon-level = <5>;
	status = "disabled";
	};

	usb@7d008000 {
	compatible = "nvidia,tegra30-ehci", "usb-ehci";
	reg = <0x7d008000 0x4000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA30_CLK_USB3>;
	resets = <&tegra_car 59>;
	reset-names = "usb";
	nvidia,phy = <&phy3>;
	status = "disabled";
	};

	phy3: usb-phy@7d008000 {
	compatible = "nvidia,tegra30-usb-phy";
	reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA30_CLK_USB3>,
	<&tegra_car TEGRA30_CLK_PLL_U>,
	<&tegra_car TEGRA30_CLK_USBD>;
	clock-names = "reg", "pll_u", "utmi-pads";
	resets = <&tegra_car 59>, <&tegra_car 22>;
	reset-names = "usb", "utmi-pads";
	nvidia,hssync-start-delay = <0>;
	nvidia,idle-wait-delay = <17>;
	nvidia,elastic-limit = <16>;
	nvidia,term-range-adj = <6>;
	nvidia,xcvr-setup = <51>;
	nvidia,xcvr-setup-use-fuses;
	nvidia,xcvr-lsfslew = <2>;
	nvidia,xcvr-lsrslew = <2>;
	nvidia,xcvr-hsslew = <32>;
	nvidia,hssquelch-level = <2>;
	nvidia,hsdiscon-level = <5>;
	status = "disabled";
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <0>;
	clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
	};

	cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <1>;
	clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
	};

	cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <2>;
	clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
	};

	cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <3>;
	clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
	};
	};

	pmu {
	compatible = "arm,cortex-a9-pmu";
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&{/cpus/cpu@0}>,
	<&{/cpus/cpu@1}>,
	<&{/cpus/cpu@2}>,
	<&{/cpus/cpu@3}>;
	};
	};
	diff --git a/sys/gnu/dts/arm/uniphier-ld4.dtsi b/sys/gnu/dts/arm/uniphier-ld4.dtsi
	index 64ec46c72a4c..06e7400d2940 100644
	--- a/sys/gnu/dts/arm/uniphier-ld4.dtsi
	+++ b/sys/gnu/dts/arm/uniphier-ld4.dtsi
	@@ -1,419 +1,419 @@
	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	//
	// Device Tree Source for UniPhier LD4 SoC
	//
	// Copyright (C) 2015-2016 Socionext Inc.
	// Author: Masahiro Yamada <yamada.masahiro@socionext.com>

	#include <dt-bindings/gpio/uniphier-gpio.h>

	/ {
	compatible = "socionext,uniphier-ld4";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <0>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	};
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	clocks {
	refclk: ref {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24576000>;
	};

	arm_timer_clk: arm-timer {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <50000000>;
	};
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	interrupt-parent = <&intc>;

	- l2: l2-cache@500c0000 {
	+ l2: cache-controller@500c0000 {
	compatible = "socionext,uniphier-system-cache";
	reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
	<0x506c0000 0x400>;
	interrupts = <0 174 4>, <0 175 4>;
	cache-unified;
	cache-size = <(512 * 1024)>;
	cache-sets = <256>;
	cache-line-size = <128>;
	cache-level = <2>;
	};

	spi: spi@54006000 {
	compatible = "socionext,uniphier-scssi";
	status = "disabled";
	reg = <0x54006000 0x100>;
	interrupts = <0 39 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi0>;
	clocks = <&peri_clk 11>;
	resets = <&peri_rst 11>;
	};

	serial0: serial@54006800 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006800 0x40>;
	interrupts = <0 33 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	clocks = <&peri_clk 0>;
	resets = <&peri_rst 0>;
	};

	serial1: serial@54006900 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006900 0x40>;
	interrupts = <0 35 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	clocks = <&peri_clk 1>;
	resets = <&peri_rst 1>;
	};

	serial2: serial@54006a00 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006a00 0x40>;
	interrupts = <0 37 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	clocks = <&peri_clk 2>;
	resets = <&peri_rst 2>;
	};

	serial3: serial@54006b00 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006b00 0x40>;
	interrupts = <0 29 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	clocks = <&peri_clk 3>;
	resets = <&peri_rst 3>;
	};

	gpio: gpio@55000000 {
	compatible = "socionext,uniphier-gpio";
	reg = <0x55000000 0x200>;
	interrupt-parent = <&aidet>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 0 0>;
	gpio-ranges-group-names = "gpio_range";
	ngpios = <136>;
	socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
	};

	i2c0: i2c@58400000 {
	compatible = "socionext,uniphier-i2c";
	status = "disabled";
	reg = <0x58400000 0x40>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 41 1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	clocks = <&peri_clk 4>;
	resets = <&peri_rst 4>;
	clock-frequency = <100000>;
	};

	i2c1: i2c@58480000 {
	compatible = "socionext,uniphier-i2c";
	status = "disabled";
	reg = <0x58480000 0x40>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 42 1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	clocks = <&peri_clk 5>;
	resets = <&peri_rst 5>;
	clock-frequency = <100000>;
	};

	/* chip-internal connection for DMD */
	i2c2: i2c@58500000 {
	compatible = "socionext,uniphier-i2c";
	reg = <0x58500000 0x40>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 43 1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	clocks = <&peri_clk 6>;
	resets = <&peri_rst 6>;
	clock-frequency = <400000>;
	};

	i2c3: i2c@58580000 {
	compatible = "socionext,uniphier-i2c";
	status = "disabled";
	reg = <0x58580000 0x40>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 44 1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	clocks = <&peri_clk 7>;
	resets = <&peri_rst 7>;
	clock-frequency = <100000>;
	};

	system_bus: system-bus@58c00000 {
	compatible = "socionext,uniphier-system-bus";
	status = "disabled";
	reg = <0x58c00000 0x400>;
	#address-cells = <2>;
	#size-cells = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_system_bus>;
	};

	smpctrl@59801000 {
	compatible = "socionext,uniphier-smpctrl";
	reg = <0x59801000 0x400>;
	};

	mioctrl@59810000 {
	compatible = "socionext,uniphier-ld4-mioctrl",
	"simple-mfd", "syscon";
	reg = <0x59810000 0x800>;

	mio_clk: clock {
	compatible = "socionext,uniphier-ld4-mio-clock";
	#clock-cells = <1>;
	};

	mio_rst: reset {
	compatible = "socionext,uniphier-ld4-mio-reset";
	#reset-cells = <1>;
	};
	};

	perictrl@59820000 {
	compatible = "socionext,uniphier-ld4-perictrl",
	"simple-mfd", "syscon";
	reg = <0x59820000 0x200>;

	peri_clk: clock {
	compatible = "socionext,uniphier-ld4-peri-clock";
	#clock-cells = <1>;
	};

	peri_rst: reset {
	compatible = "socionext,uniphier-ld4-peri-reset";
	#reset-cells = <1>;
	};
	};

	dmac: dma-controller@5a000000 {
	compatible = "socionext,uniphier-mio-dmac";
	reg = <0x5a000000 0x1000>;
	interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
	<0 71 4>, <0 72 4>, <0 73 4>;
	clocks = <&mio_clk 7>;
	resets = <&mio_rst 7>;
	#dma-cells = <1>;
	};

	- sd: sdhc@5a400000 {
	+ sd: mmc@5a400000 {
	compatible = "socionext,uniphier-sd-v2.91";
	status = "disabled";
	reg = <0x5a400000 0x200>;
	interrupts = <0 76 4>;
	pinctrl-names = "default", "uhs";
	pinctrl-0 = <&pinctrl_sd>;
	pinctrl-1 = <&pinctrl_sd_uhs>;
	clocks = <&mio_clk 0>;
	reset-names = "host", "bridge";
	resets = <&mio_rst 0>, <&mio_rst 3>;
	dma-names = "rx-tx";
	dmas = <&dmac 4>;
	bus-width = <4>;
	cap-sd-highspeed;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	};

	- emmc: sdhc@5a500000 {
	+ emmc: mmc@5a500000 {
	compatible = "socionext,uniphier-sd-v2.91";
	status = "disabled";
	reg = <0x5a500000 0x200>;
	interrupts = <0 78 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_emmc>;
	clocks = <&mio_clk 1>;
	reset-names = "host", "bridge", "hw";
	resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
	dma-names = "rx-tx";
	dmas = <&dmac 6>;
	bus-width = <8>;
	cap-mmc-highspeed;
	cap-mmc-hw-reset;
	non-removable;
	};

	usb0: usb@5a800100 {
	compatible = "socionext,uniphier-ehci", "generic-ehci";
	status = "disabled";
	reg = <0x5a800100 0x100>;
	interrupts = <0 80 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb0>;
	clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
	<&mio_clk 12>;
	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
	<&mio_rst 12>;
	has-transaction-translator;
	};

	usb1: usb@5a810100 {
	compatible = "socionext,uniphier-ehci", "generic-ehci";
	status = "disabled";
	reg = <0x5a810100 0x100>;
	interrupts = <0 81 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb1>;
	clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
	<&mio_clk 13>;
	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
	<&mio_rst 13>;
	has-transaction-translator;
	};

	usb2: usb@5a820100 {
	compatible = "socionext,uniphier-ehci", "generic-ehci";
	status = "disabled";
	reg = <0x5a820100 0x100>;
	interrupts = <0 82 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb2>;
	clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
	<&mio_clk 14>;
	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
	<&mio_rst 14>;
	has-transaction-translator;
	};

	soc-glue@5f800000 {
	compatible = "socionext,uniphier-ld4-soc-glue",
	"simple-mfd", "syscon";
	reg = <0x5f800000 0x2000>;

	pinctrl: pinctrl {
	compatible = "socionext,uniphier-ld4-pinctrl";
	};
	};

	soc-glue@5f900000 {
	compatible = "socionext,uniphier-ld4-soc-glue-debug",
	"simple-mfd";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x5f900000 0x2000>;

	efuse@100 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x100 0x28>;
	};

	efuse@130 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x130 0x8>;
	};
	};

	timer@60000200 {
	compatible = "arm,cortex-a9-global-timer";
	reg = <0x60000200 0x20>;
	interrupts = <1 11 0x104>;
	clocks = <&arm_timer_clk>;
	};

	timer@60000600 {
	compatible = "arm,cortex-a9-twd-timer";
	reg = <0x60000600 0x20>;
	interrupts = <1 13 0x104>;
	clocks = <&arm_timer_clk>;
	};

	intc: interrupt-controller@60001000 {
	compatible = "arm,cortex-a9-gic";
	reg = <0x60001000 0x1000>,
	<0x60000100 0x100>;
	#interrupt-cells = <3>;
	interrupt-controller;
	};

	- aidet: aidet@61830000 {
	+ aidet: interrupt-controller@61830000 {
	compatible = "socionext,uniphier-ld4-aidet";
	reg = <0x61830000 0x200>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	sysctrl@61840000 {
	compatible = "socionext,uniphier-ld4-sysctrl",
	"simple-mfd", "syscon";
	reg = <0x61840000 0x10000>;

	sys_clk: clock {
	compatible = "socionext,uniphier-ld4-clock";
	#clock-cells = <1>;
	};

	sys_rst: reset {
	compatible = "socionext,uniphier-ld4-reset";
	#reset-cells = <1>;
	};
	};

	- nand: nand@68000000 {
	+ nand: nand-controller@68000000 {
	compatible = "socionext,uniphier-denali-nand-v5a";
	status = "disabled";
	reg-names = "nand_data", "denali_reg";
	reg = <0x68000000 0x20>, <0x68100000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 65 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nand>;
	clock-names = "nand", "nand_x", "ecc";
	clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
	reset-names = "nand", "reg";
	resets = <&sys_rst 2>, <&sys_rst 2>;
	};
	};
	};

	#include "uniphier-pinctrl.dtsi"
	diff --git a/sys/gnu/dts/arm/uniphier-pro4.dtsi b/sys/gnu/dts/arm/uniphier-pro4.dtsi
	index 2ec04d7972ef..1c866f0306fc 100644
	--- a/sys/gnu/dts/arm/uniphier-pro4.dtsi
	+++ b/sys/gnu/dts/arm/uniphier-pro4.dtsi
	@@ -1,609 +1,609 @@
	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	//
	// Device Tree Source for UniPhier Pro4 SoC
	//
	// Copyright (C) 2015-2016 Socionext Inc.
	// Author: Masahiro Yamada <yamada.masahiro@socionext.com>

	#include <dt-bindings/gpio/uniphier-gpio.h>

	/ {
	compatible = "socionext,uniphier-pro4";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <0>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	};

	cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <1>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	};
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	clocks {
	refclk: ref {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <25000000>;
	};

	arm_timer_clk: arm-timer {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <50000000>;
	};
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	interrupt-parent = <&intc>;

	- l2: l2-cache@500c0000 {
	+ l2: cache-controller@500c0000 {
	compatible = "socionext,uniphier-system-cache";
	reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
	<0x506c0000 0x400>;
	interrupts = <0 174 4>, <0 175 4>;
	cache-unified;
	cache-size = <(768 * 1024)>;
	cache-sets = <256>;
	cache-line-size = <128>;
	cache-level = <2>;
	};

	spi0: spi@54006000 {
	compatible = "socionext,uniphier-scssi";
	status = "disabled";
	reg = <0x54006000 0x100>;
	interrupts = <0 39 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi0>;
	clocks = <&peri_clk 11>;
	resets = <&peri_rst 11>;
	};

	serial0: serial@54006800 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006800 0x40>;
	interrupts = <0 33 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	clocks = <&peri_clk 0>;
	resets = <&peri_rst 0>;
	};

	serial1: serial@54006900 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006900 0x40>;
	interrupts = <0 35 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	clocks = <&peri_clk 1>;
	resets = <&peri_rst 1>;
	};

	serial2: serial@54006a00 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006a00 0x40>;
	interrupts = <0 37 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	clocks = <&peri_clk 2>;
	resets = <&peri_rst 2>;
	};

	serial3: serial@54006b00 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006b00 0x40>;
	interrupts = <0 177 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	clocks = <&peri_clk 3>;
	resets = <&peri_rst 3>;
	};

	gpio: gpio@55000000 {
	compatible = "socionext,uniphier-gpio";
	reg = <0x55000000 0x200>;
	interrupt-parent = <&aidet>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 0 0>;
	gpio-ranges-group-names = "gpio_range";
	ngpios = <248>;
	socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
	};

	i2c0: i2c@58780000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58780000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 41 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	clocks = <&peri_clk 4>;
	resets = <&peri_rst 4>;
	clock-frequency = <100000>;
	};

	i2c1: i2c@58781000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58781000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 42 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	clocks = <&peri_clk 5>;
	resets = <&peri_rst 5>;
	clock-frequency = <100000>;
	};

	i2c2: i2c@58782000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58782000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 43 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	clocks = <&peri_clk 6>;
	resets = <&peri_rst 6>;
	clock-frequency = <100000>;
	};

	i2c3: i2c@58783000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58783000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 44 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	clocks = <&peri_clk 7>;
	resets = <&peri_rst 7>;
	clock-frequency = <100000>;
	};

	/* i2c4 does not exist */

	/* chip-internal connection for DMD */
	i2c5: i2c@58785000 {
	compatible = "socionext,uniphier-fi2c";
	reg = <0x58785000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 25 4>;
	clocks = <&peri_clk 9>;
	resets = <&peri_rst 9>;
	clock-frequency = <400000>;
	};

	/* chip-internal connection for HDMI */
	i2c6: i2c@58786000 {
	compatible = "socionext,uniphier-fi2c";
	reg = <0x58786000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 26 4>;
	clocks = <&peri_clk 10>;
	resets = <&peri_rst 10>;
	clock-frequency = <400000>;
	};

	system_bus: system-bus@58c00000 {
	compatible = "socionext,uniphier-system-bus";
	status = "disabled";
	reg = <0x58c00000 0x400>;
	#address-cells = <2>;
	#size-cells = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_system_bus>;
	};

	smpctrl@59801000 {
	compatible = "socionext,uniphier-smpctrl";
	reg = <0x59801000 0x400>;
	};

	mioctrl@59810000 {
	compatible = "socionext,uniphier-pro4-mioctrl",
	"simple-mfd", "syscon";
	reg = <0x59810000 0x800>;

	mio_clk: clock {
	compatible = "socionext,uniphier-pro4-mio-clock";
	#clock-cells = <1>;
	};

	mio_rst: reset {
	compatible = "socionext,uniphier-pro4-mio-reset";
	#reset-cells = <1>;
	};
	};

	perictrl@59820000 {
	compatible = "socionext,uniphier-pro4-perictrl",
	"simple-mfd", "syscon";
	reg = <0x59820000 0x200>;

	peri_clk: clock {
	compatible = "socionext,uniphier-pro4-peri-clock";
	#clock-cells = <1>;
	};

	peri_rst: reset {
	compatible = "socionext,uniphier-pro4-peri-reset";
	#reset-cells = <1>;
	};
	};

	dmac: dma-controller@5a000000 {
	compatible = "socionext,uniphier-mio-dmac";
	reg = <0x5a000000 0x1000>;
	interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
	<0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
	clocks = <&mio_clk 7>;
	resets = <&mio_rst 7>;
	#dma-cells = <1>;
	};

	- sd: sdhc@5a400000 {
	+ sd: mmc@5a400000 {
	compatible = "socionext,uniphier-sd-v2.91";
	status = "disabled";
	reg = <0x5a400000 0x200>;
	interrupts = <0 76 4>;
	pinctrl-names = "default", "uhs";
	pinctrl-0 = <&pinctrl_sd>;
	pinctrl-1 = <&pinctrl_sd_uhs>;
	clocks = <&mio_clk 0>;
	reset-names = "host", "bridge";
	resets = <&mio_rst 0>, <&mio_rst 3>;
	dma-names = "rx-tx";
	dmas = <&dmac 4>;
	bus-width = <4>;
	cap-sd-highspeed;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	};

	- emmc: sdhc@5a500000 {
	+ emmc: mmc@5a500000 {
	compatible = "socionext,uniphier-sd-v2.91";
	status = "disabled";
	reg = <0x5a500000 0x200>;
	interrupts = <0 78 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_emmc>;
	clocks = <&mio_clk 1>;
	reset-names = "host", "bridge", "hw";
	resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
	dma-names = "rx-tx";
	dmas = <&dmac 5>;
	bus-width = <8>;
	cap-mmc-highspeed;
	cap-mmc-hw-reset;
	non-removable;
	};

	- sd1: sdhc@5a600000 {
	+ sd1: mmc@5a600000 {
	compatible = "socionext,uniphier-sd-v2.91";
	status = "disabled";
	reg = <0x5a600000 0x200>;
	interrupts = <0 85 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sd1>;
	clocks = <&mio_clk 2>;
	reset-names = "host", "bridge";
	resets = <&mio_rst 2>, <&mio_rst 5>;
	dma-names = "rx-tx";
	dmas = <&dmac 6>;
	bus-width = <4>;
	cap-sd-highspeed;
	};

	usb2: usb@5a800100 {
	compatible = "socionext,uniphier-ehci", "generic-ehci";
	status = "disabled";
	reg = <0x5a800100 0x100>;
	interrupts = <0 80 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb2>;
	clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
	<&mio_clk 12>;
	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
	<&mio_rst 12>;
	phy-names = "usb";
	phys = <&usb_phy0>;
	has-transaction-translator;
	};

	usb3: usb@5a810100 {
	compatible = "socionext,uniphier-ehci", "generic-ehci";
	status = "disabled";
	reg = <0x5a810100 0x100>;
	interrupts = <0 81 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb3>;
	clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
	<&mio_clk 13>;
	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
	<&mio_rst 13>;
	phy-names = "usb";
	phys = <&usb_phy1>;
	has-transaction-translator;
	};

	soc_glue: soc-glue@5f800000 {
	compatible = "socionext,uniphier-pro4-soc-glue",
	"simple-mfd", "syscon";
	reg = <0x5f800000 0x2000>;

	pinctrl: pinctrl {
	compatible = "socionext,uniphier-pro4-pinctrl";
	};

	usb-phy {
	compatible = "socionext,uniphier-pro4-usb2-phy";
	#address-cells = <1>;
	#size-cells = <0>;

	usb_phy0: phy@0 {
	reg = <0>;
	#phy-cells = <0>;
	};

	usb_phy1: phy@1 {
	reg = <1>;
	#phy-cells = <0>;
	};

	usb_phy2: phy@2 {
	reg = <2>;
	#phy-cells = <0>;
	vbus-supply = <&usb0_vbus>;
	};

	usb_phy3: phy@3 {
	reg = <3>;
	#phy-cells = <0>;
	vbus-supply = <&usb1_vbus>;
	};
	};
	};

	soc-glue@5f900000 {
	compatible = "socionext,uniphier-pro4-soc-glue-debug",
	"simple-mfd";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x5f900000 0x2000>;

	efuse@100 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x100 0x28>;
	};

	efuse@130 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x130 0x8>;
	};

	efuse@200 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x200 0x14>;
	};
	};

	- aidet: aidet@5fc20000 {
	+ aidet: interrupt-controller@5fc20000 {
	compatible = "socionext,uniphier-pro4-aidet";
	reg = <0x5fc20000 0x200>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	timer@60000200 {
	compatible = "arm,cortex-a9-global-timer";
	reg = <0x60000200 0x20>;
	interrupts = <1 11 0x304>;
	clocks = <&arm_timer_clk>;
	};

	timer@60000600 {
	compatible = "arm,cortex-a9-twd-timer";
	reg = <0x60000600 0x20>;
	interrupts = <1 13 0x304>;
	clocks = <&arm_timer_clk>;
	};

	intc: interrupt-controller@60001000 {
	compatible = "arm,cortex-a9-gic";
	reg = <0x60001000 0x1000>,
	<0x60000100 0x100>;
	#interrupt-cells = <3>;
	interrupt-controller;
	};

	sysctrl@61840000 {
	compatible = "socionext,uniphier-pro4-sysctrl",
	"simple-mfd", "syscon";
	reg = <0x61840000 0x10000>;

	sys_clk: clock {
	compatible = "socionext,uniphier-pro4-clock";
	#clock-cells = <1>;
	};

	sys_rst: reset {
	compatible = "socionext,uniphier-pro4-reset";
	#reset-cells = <1>;
	};
	};

	eth: ethernet@65000000 {
	compatible = "socionext,uniphier-pro4-ave4";
	status = "disabled";
	reg = <0x65000000 0x8500>;
	interrupts = <0 66 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ether_rgmii>;
	clock-names = "gio", "ether", "ether-gb", "ether-phy";
	clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>,
	<&sys_clk 10>;
	reset-names = "gio", "ether";
	resets = <&sys_rst 12>, <&sys_rst 6>;
	phy-mode = "rgmii";
	local-mac-address = [00 00 00 00 00 00];
	socionext,syscon-phy-mode = <&soc_glue 0>;

	mdio: mdio {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	usb0: usb@65a00000 {
	compatible = "socionext,uniphier-dwc3", "snps,dwc3";
	status = "disabled";
	reg = <0x65a00000 0xcd00>;
	interrupt-names = "host", "peripheral";
	interrupts = <0 134 4>, <0 135 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb0>;
	clock-names = "ref", "bus_early", "suspend";
	clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
	resets = <&usb0_rst 4>;
	phys = <&usb_phy2>, <&usb0_ssphy>;
	dr_mode = "host";
	};

	usb-glue@65b00000 {
	compatible = "socionext,uniphier-pro4-dwc3-glue",
	"simple-mfd";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x65b00000 0x100>;

	usb0_vbus: regulator@0 {
	compatible = "socionext,uniphier-pro4-usb3-regulator";
	reg = <0 0x10>;
	clock-names = "gio", "link";
	clocks = <&sys_clk 12>, <&sys_clk 14>;
	reset-names = "gio", "link";
	resets = <&sys_rst 12>, <&sys_rst 14>;
	};

	usb0_ssphy: ss-phy@10 {
	compatible = "socionext,uniphier-pro4-usb3-ssphy";
	reg = <0x10 0x10>;
	#phy-cells = <0>;
	clock-names = "gio", "link";
	clocks = <&sys_clk 12>, <&sys_clk 14>;
	reset-names = "gio", "link";
	resets = <&sys_rst 12>, <&sys_rst 14>;
	vbus-supply = <&usb0_vbus>;
	};

	usb0_rst: reset@40 {
	compatible = "socionext,uniphier-pro4-usb3-reset";
	reg = <0x40 0x4>;
	#reset-cells = <1>;
	clock-names = "gio", "link";
	clocks = <&sys_clk 12>, <&sys_clk 14>;
	reset-names = "gio", "link";
	resets = <&sys_rst 12>, <&sys_rst 14>;
	};
	};

	usb1: usb@65c00000 {
	compatible = "socionext,uniphier-dwc3", "snps,dwc3";
	status = "disabled";
	reg = <0x65c00000 0xcd00>;
	interrupt-names = "host", "peripheral";
	interrupts = <0 137 4>, <0 138 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb1>;
	clock-names = "ref", "bus_early", "suspend";
	clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
	resets = <&usb1_rst 4>;
	phys = <&usb_phy3>;
	dr_mode = "host";
	};

	usb-glue@65d00000 {
	compatible = "socionext,uniphier-pro4-dwc3-glue",
	"simple-mfd";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x65d00000 0x100>;

	usb1_vbus: regulator@0 {
	compatible = "socionext,uniphier-pro4-usb3-regulator";
	reg = <0 0x10>;
	clock-names = "gio", "link";
	clocks = <&sys_clk 12>, <&sys_clk 15>;
	reset-names = "gio", "link";
	resets = <&sys_rst 12>, <&sys_rst 15>;
	};

	usb1_rst: reset@40 {
	compatible = "socionext,uniphier-pro4-usb3-reset";
	reg = <0x40 0x4>;
	#reset-cells = <1>;
	clock-names = "gio", "link";
	clocks = <&sys_clk 12>, <&sys_clk 15>;
	reset-names = "gio", "link";
	resets = <&sys_rst 12>, <&sys_rst 15>;
	};
	};

	- nand: nand@68000000 {
	+ nand: nand-controller@68000000 {
	compatible = "socionext,uniphier-denali-nand-v5a";
	status = "disabled";
	reg-names = "nand_data", "denali_reg";
	reg = <0x68000000 0x20>, <0x68100000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 65 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nand>;
	clock-names = "nand", "nand_x", "ecc";
	clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
	reset-names = "nand", "reg";
	resets = <&sys_rst 2>, <&sys_rst 2>;
	};
	};
	};

	#include "uniphier-pinctrl.dtsi"
	diff --git a/sys/gnu/dts/arm/uniphier-pro5.dtsi b/sys/gnu/dts/arm/uniphier-pro5.dtsi
	index ea3961f920a0..8f1ae0957f5f 100644
	--- a/sys/gnu/dts/arm/uniphier-pro5.dtsi
	+++ b/sys/gnu/dts/arm/uniphier-pro5.dtsi
	@@ -1,508 +1,656 @@
	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	//
	// Device Tree Source for UniPhier Pro5 SoC
	//
	// Copyright (C) 2015-2016 Socionext Inc.
	// Author: Masahiro Yamada <yamada.masahiro@socionext.com>

	/ {
	compatible = "socionext,uniphier-pro5";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <0>;
	clocks = <&sys_clk 32>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	operating-points-v2 = <&cpu_opp>;
	};

	cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <1>;
	clocks = <&sys_clk 32>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	operating-points-v2 = <&cpu_opp>;
	};
	};

	cpu_opp: opp-table {
	compatible = "operating-points-v2";
	opp-shared;

	opp-100000000 {
	opp-hz = /bits/ 64 <100000000>;
	clock-latency-ns = <300>;
	};
	opp-116667000 {
	opp-hz = /bits/ 64 <116667000>;
	clock-latency-ns = <300>;
	};
	opp-150000000 {
	opp-hz = /bits/ 64 <150000000>;
	clock-latency-ns = <300>;
	};
	opp-175000000 {
	opp-hz = /bits/ 64 <175000000>;
	clock-latency-ns = <300>;
	};
	opp-200000000 {
	opp-hz = /bits/ 64 <200000000>;
	clock-latency-ns = <300>;
	};
	opp-233334000 {
	opp-hz = /bits/ 64 <233334000>;
	clock-latency-ns = <300>;
	};
	opp-300000000 {
	opp-hz = /bits/ 64 <300000000>;
	clock-latency-ns = <300>;
	};
	opp-350000000 {
	opp-hz = /bits/ 64 <350000000>;
	clock-latency-ns = <300>;
	};
	opp-400000000 {
	opp-hz = /bits/ 64 <400000000>;
	clock-latency-ns = <300>;
	};
	opp-466667000 {
	opp-hz = /bits/ 64 <466667000>;
	clock-latency-ns = <300>;
	};
	opp-600000000 {
	opp-hz = /bits/ 64 <600000000>;
	clock-latency-ns = <300>;
	};
	opp-700000000 {
	opp-hz = /bits/ 64 <700000000>;
	clock-latency-ns = <300>;
	};
	opp-800000000 {
	opp-hz = /bits/ 64 <800000000>;
	clock-latency-ns = <300>;
	};
	opp-933334000 {
	opp-hz = /bits/ 64 <933334000>;
	clock-latency-ns = <300>;
	};
	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	clock-latency-ns = <300>;
	};
	opp-1400000000 {
	opp-hz = /bits/ 64 <1400000000>;
	clock-latency-ns = <300>;
	};
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	clocks {
	refclk: ref {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <20000000>;
	};

	arm_timer_clk: arm-timer {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <50000000>;
	};
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	interrupt-parent = <&intc>;

	- l2: l2-cache@500c0000 {
	+ l2: cache-controller@500c0000 {
	compatible = "socionext,uniphier-system-cache";
	reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
	<0x506c0000 0x400>;
	interrupts = <0 190 4>, <0 191 4>;
	cache-unified;
	cache-size = <(2 * 1024 * 1024)>;
	cache-sets = <512>;
	cache-line-size = <128>;
	cache-level = <2>;
	next-level-cache = <&l3>;
	};

	- l3: l3-cache@500c8000 {
	+ l3: cache-controller@500c8000 {
	compatible = "socionext,uniphier-system-cache";
	reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
	<0x506c8000 0x400>;
	interrupts = <0 174 4>, <0 175 4>;
	cache-unified;
	cache-size = <(2 * 1024 * 1024)>;
	cache-sets = <512>;
	cache-line-size = <256>;
	cache-level = <3>;
	};

	spi0: spi@54006000 {
	compatible = "socionext,uniphier-scssi";
	status = "disabled";
	reg = <0x54006000 0x100>;
	interrupts = <0 39 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi0>;
	clocks = <&peri_clk 11>;
	resets = <&peri_rst 11>;
	};

	spi1: spi@54006100 {
	compatible = "socionext,uniphier-scssi";
	status = "disabled";
	reg = <0x54006100 0x100>;
	interrupts = <0 216 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi1>;
	- clocks = <&peri_clk 11>;
	- resets = <&peri_rst 11>;
	+ clocks = <&peri_clk 11>; /* common with spi0 */
	+ resets = <&peri_rst 12>;
	};

	serial0: serial@54006800 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006800 0x40>;
	interrupts = <0 33 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	clocks = <&peri_clk 0>;
	resets = <&peri_rst 0>;
	};

	serial1: serial@54006900 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006900 0x40>;
	interrupts = <0 35 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	clocks = <&peri_clk 1>;
	resets = <&peri_rst 1>;
	};

	serial2: serial@54006a00 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006a00 0x40>;
	interrupts = <0 37 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	clocks = <&peri_clk 2>;
	resets = <&peri_rst 2>;
	};

	serial3: serial@54006b00 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006b00 0x40>;
	interrupts = <0 177 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	clocks = <&peri_clk 3>;
	resets = <&peri_rst 3>;
	};

	gpio: gpio@55000000 {
	compatible = "socionext,uniphier-gpio";
	reg = <0x55000000 0x200>;
	interrupt-parent = <&aidet>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 0 0>;
	gpio-ranges-group-names = "gpio_range";
	ngpios = <248>;
	socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
	};

	i2c0: i2c@58780000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58780000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 41 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	clocks = <&peri_clk 4>;
	resets = <&peri_rst 4>;
	clock-frequency = <100000>;
	};

	i2c1: i2c@58781000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58781000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 42 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	clocks = <&peri_clk 5>;
	resets = <&peri_rst 5>;
	clock-frequency = <100000>;
	};

	i2c2: i2c@58782000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58782000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 43 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	clocks = <&peri_clk 6>;
	resets = <&peri_rst 6>;
	clock-frequency = <100000>;
	};

	i2c3: i2c@58783000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58783000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 44 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	clocks = <&peri_clk 7>;
	resets = <&peri_rst 7>;
	clock-frequency = <100000>;
	};

	/* i2c4 does not exist */

	/* chip-internal connection for DMD */
	i2c5: i2c@58785000 {
	compatible = "socionext,uniphier-fi2c";
	reg = <0x58785000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 25 4>;
	clocks = <&peri_clk 9>;
	resets = <&peri_rst 9>;
	clock-frequency = <400000>;
	};

	/* chip-internal connection for HDMI */
	i2c6: i2c@58786000 {
	compatible = "socionext,uniphier-fi2c";
	reg = <0x58786000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 26 4>;
	clocks = <&peri_clk 10>;
	resets = <&peri_rst 10>;
	clock-frequency = <400000>;
	};

	system_bus: system-bus@58c00000 {
	compatible = "socionext,uniphier-system-bus";
	status = "disabled";
	reg = <0x58c00000 0x400>;
	#address-cells = <2>;
	#size-cells = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_system_bus>;
	};

	smpctrl@59801000 {
	compatible = "socionext,uniphier-smpctrl";
	reg = <0x59801000 0x400>;
	};

	sdctrl@59810000 {
	compatible = "socionext,uniphier-pro5-sdctrl",
	"simple-mfd", "syscon";
	reg = <0x59810000 0x400>;

	sd_clk: clock {
	compatible = "socionext,uniphier-pro5-sd-clock";
	#clock-cells = <1>;
	};

	sd_rst: reset {
	compatible = "socionext,uniphier-pro5-sd-reset";
	#reset-cells = <1>;
	};
	};

	perictrl@59820000 {
	compatible = "socionext,uniphier-pro5-perictrl",
	"simple-mfd", "syscon";
	reg = <0x59820000 0x200>;

	peri_clk: clock {
	compatible = "socionext,uniphier-pro5-peri-clock";
	#clock-cells = <1>;
	};

	peri_rst: reset {
	compatible = "socionext,uniphier-pro5-peri-reset";
	#reset-cells = <1>;
	};
	};

	soc-glue@5f800000 {
	compatible = "socionext,uniphier-pro5-soc-glue",
	"simple-mfd", "syscon";
	reg = <0x5f800000 0x2000>;

	pinctrl: pinctrl {
	compatible = "socionext,uniphier-pro5-pinctrl";
	};
	};

	soc-glue@5f900000 {
	compatible = "socionext,uniphier-pro5-soc-glue-debug",
	"simple-mfd";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x5f900000 0x2000>;

	efuse@100 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x100 0x28>;
	};

	efuse@130 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x130 0x8>;
	};

	efuse@200 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x200 0x28>;
	};

	efuse@300 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x300 0x14>;
	};

	efuse@400 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x400 0x8>;
	};
	};

	- aidet: aidet@5fc20000 {
	+ aidet: interrupt-controller@5fc20000 {
	compatible = "socionext,uniphier-pro5-aidet";
	reg = <0x5fc20000 0x200>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	timer@60000200 {
	compatible = "arm,cortex-a9-global-timer";
	reg = <0x60000200 0x20>;
	interrupts = <1 11 0x304>;
	clocks = <&arm_timer_clk>;
	};

	timer@60000600 {
	compatible = "arm,cortex-a9-twd-timer";
	reg = <0x60000600 0x20>;
	interrupts = <1 13 0x304>;
	clocks = <&arm_timer_clk>;
	};

	intc: interrupt-controller@60001000 {
	compatible = "arm,cortex-a9-gic";
	reg = <0x60001000 0x1000>,
	<0x60000100 0x100>;
	#interrupt-cells = <3>;
	interrupt-controller;
	};

	sysctrl@61840000 {
	compatible = "socionext,uniphier-pro5-sysctrl",
	"simple-mfd", "syscon";
	reg = <0x61840000 0x10000>;

	sys_clk: clock {
	compatible = "socionext,uniphier-pro5-clock";
	#clock-cells = <1>;
	};

	sys_rst: reset {
	compatible = "socionext,uniphier-pro5-reset";
	#reset-cells = <1>;
	};
	};

	- nand: nand@68000000 {
	+ usb0: usb@65a00000 {
	+ compatible = "socionext,uniphier-dwc3", "snps,dwc3";
	+ status = "disabled";
	+ reg = <0x65a00000 0xcd00>;
	+ interrupt-names = "host";
	+ interrupts = <0 134 4>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_usb0>;
	+ clock-names = "ref", "bus_early", "suspend";
	+ clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
	+ resets = <&usb0_rst 15>;
	+ phys = <&usb0_hsphy0>, <&usb0_ssphy0>;
	+ dr_mode = "host";
	+ };
	+
	+ usb-glue@65b00000 {
	+ compatible = "socionext,uniphier-pro5-dwc3-glue",
	+ "simple-mfd";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x65b00000 0x400>;
	+
	+ usb0_rst: reset@0 {
	+ compatible = "socionext,uniphier-pro5-usb3-reset";
	+ reg = <0x0 0x4>;
	+ #reset-cells = <1>;
	+ clock-names = "gio", "link";
	+ clocks = <&sys_clk 12>, <&sys_clk 14>;
	+ reset-names = "gio", "link";
	+ resets = <&sys_rst 12>, <&sys_rst 14>;
	+ };
	+
	+ usb0_vbus0: regulator@100 {
	+ compatible = "socionext,uniphier-pro5-usb3-regulator";
	+ reg = <0x100 0x10>;
	+ clock-names = "gio", "link";
	+ clocks = <&sys_clk 12>, <&sys_clk 14>;
	+ reset-names = "gio", "link";
	+ resets = <&sys_rst 12>, <&sys_rst 14>;
	+ };
	+
	+ usb0_hsphy0: hs-phy@280 {
	+ compatible = "socionext,uniphier-pro5-usb3-hsphy";
	+ reg = <0x280 0x10>;
	+ #phy-cells = <0>;
	+ clock-names = "gio", "link";
	+ clocks = <&sys_clk 12>, <&sys_clk 14>;
	+ reset-names = "gio", "link";
	+ resets = <&sys_rst 12>, <&sys_rst 14>;
	+ vbus-supply = <&usb0_vbus0>;
	+ };
	+
	+ usb0_ssphy0: ss-phy@380 {
	+ compatible = "socionext,uniphier-pro5-usb3-ssphy";
	+ reg = <0x380 0x10>;
	+ #phy-cells = <0>;
	+ clock-names = "gio", "link";
	+ clocks = <&sys_clk 12>, <&sys_clk 14>;
	+ reset-names = "gio", "link";
	+ resets = <&sys_rst 12>, <&sys_rst 14>;
	+ vbus-supply = <&usb0_vbus0>;
	+ };
	+ };
	+
	+ usb1: usb@65c00000 {
	+ compatible = "socionext,uniphier-dwc3", "snps,dwc3";
	+ status = "disabled";
	+ reg = <0x65c00000 0xcd00>;
	+ interrupt-names = "host";
	+ interrupts = <0 137 4>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
	+ clock-names = "ref", "bus_early", "suspend";
	+ clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
	+ resets = <&usb1_rst 15>;
	+ phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
	+ dr_mode = "host";
	+ };
	+
	+ usb-glue@65d00000 {
	+ compatible = "socionext,uniphier-pro5-dwc3-glue",
	+ "simple-mfd";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0x65d00000 0x400>;
	+
	+ usb1_rst: reset@0 {
	+ compatible = "socionext,uniphier-pro5-usb3-reset";
	+ reg = <0x0 0x4>;
	+ #reset-cells = <1>;
	+ clock-names = "gio", "link";
	+ clocks = <&sys_clk 12>, <&sys_clk 15>;
	+ reset-names = "gio", "link";
	+ resets = <&sys_rst 12>, <&sys_rst 15>;
	+ };
	+
	+ usb1_vbus0: regulator@100 {
	+ compatible = "socionext,uniphier-pro5-usb3-regulator";
	+ reg = <0x100 0x10>;
	+ clock-names = "gio", "link";
	+ clocks = <&sys_clk 12>, <&sys_clk 15>;
	+ reset-names = "gio", "link";
	+ resets = <&sys_rst 12>, <&sys_rst 15>;
	+ };
	+
	+ usb1_vbus1: regulator@110 {
	+ compatible = "socionext,uniphier-pro5-usb3-regulator";
	+ reg = <0x110 0x10>;
	+ clock-names = "gio", "link";
	+ clocks = <&sys_clk 12>, <&sys_clk 15>;
	+ reset-names = "gio", "link";
	+ resets = <&sys_rst 12>, <&sys_rst 15>;
	+ };
	+
	+ usb1_hsphy0: hs-phy@280 {
	+ compatible = "socionext,uniphier-pro5-usb3-hsphy";
	+ reg = <0x280 0x10>;
	+ #phy-cells = <0>;
	+ clock-names = "gio", "link";
	+ clocks = <&sys_clk 12>, <&sys_clk 15>;
	+ reset-names = "gio", "link";
	+ resets = <&sys_rst 12>, <&sys_rst 15>;
	+ vbus-supply = <&usb1_vbus0>;
	+ };
	+
	+ usb1_hsphy1: hs-phy@290 {
	+ compatible = "socionext,uniphier-pro5-usb3-hsphy";
	+ reg = <0x290 0x10>;
	+ #phy-cells = <0>;
	+ clock-names = "gio", "link";
	+ clocks = <&sys_clk 12>, <&sys_clk 15>;
	+ reset-names = "gio", "link";
	+ resets = <&sys_rst 12>, <&sys_rst 15>;
	+ vbus-supply = <&usb1_vbus1>;
	+ };
	+
	+ usb1_ssphy0: ss-phy@380 {
	+ compatible = "socionext,uniphier-pro5-usb3-ssphy";
	+ reg = <0x380 0x10>;
	+ #phy-cells = <0>;
	+ clock-names = "gio", "link";
	+ clocks = <&sys_clk 12>, <&sys_clk 15>;
	+ reset-names = "gio", "link";
	+ resets = <&sys_rst 12>, <&sys_rst 15>;
	+ vbus-supply = <&usb1_vbus0>;
	+ };
	+ };
	+
	+ nand: nand-controller@68000000 {
	compatible = "socionext,uniphier-denali-nand-v5b";
	status = "disabled";
	reg-names = "nand_data", "denali_reg";
	reg = <0x68000000 0x20>, <0x68100000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 65 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nand>;
	clock-names = "nand", "nand_x", "ecc";
	clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
	reset-names = "nand", "reg";
	resets = <&sys_rst 2>, <&sys_rst 2>;
	};

	- emmc: sdhc@68400000 {
	+ emmc: mmc@68400000 {
	compatible = "socionext,uniphier-sd-v3.1";
	status = "disabled";
	reg = <0x68400000 0x800>;
	interrupts = <0 78 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_emmc>;
	clocks = <&sd_clk 1>;
	reset-names = "host", "hw";
	resets = <&sd_rst 1>, <&sd_rst 6>;
	bus-width = <8>;
	cap-mmc-highspeed;
	cap-mmc-hw-reset;
	non-removable;
	};

	- sd: sdhc@68800000 {
	+ sd: mmc@68800000 {
	compatible = "socionext,uniphier-sd-v3.1";
	status = "disabled";
	reg = <0x68800000 0x800>;
	interrupts = <0 76 4>;
	pinctrl-names = "default", "uhs";
	pinctrl-0 = <&pinctrl_sd>;
	pinctrl-1 = <&pinctrl_sd_uhs>;
	clocks = <&sd_clk 0>;
	reset-names = "host";
	resets = <&sd_rst 0>;
	bus-width = <4>;
	cap-sd-highspeed;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	};
	};
	};

	#include "uniphier-pinctrl.dtsi"
	diff --git a/sys/gnu/dts/arm/uniphier-pxs2.dtsi b/sys/gnu/dts/arm/uniphier-pxs2.dtsi
	index 13b0d4a7741f..2f2a24994c69 100644
	--- a/sys/gnu/dts/arm/uniphier-pxs2.dtsi
	+++ b/sys/gnu/dts/arm/uniphier-pxs2.dtsi
	@@ -1,782 +1,782 @@
	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	//
	// Device Tree Source for UniPhier PXs2 SoC
	//
	// Copyright (C) 2015-2016 Socionext Inc.
	// Author: Masahiro Yamada <yamada.masahiro@socionext.com>

	#include <dt-bindings/gpio/uniphier-gpio.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	compatible = "socionext,uniphier-pxs2";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <0>;
	clocks = <&sys_clk 32>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	operating-points-v2 = <&cpu_opp>;
	#cooling-cells = <2>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <1>;
	clocks = <&sys_clk 32>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	operating-points-v2 = <&cpu_opp>;
	#cooling-cells = <2>;
	};

	cpu2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <2>;
	clocks = <&sys_clk 32>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	operating-points-v2 = <&cpu_opp>;
	#cooling-cells = <2>;
	};

	cpu3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <3>;
	clocks = <&sys_clk 32>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	operating-points-v2 = <&cpu_opp>;
	#cooling-cells = <2>;
	};
	};

	cpu_opp: opp-table {
	compatible = "operating-points-v2";
	opp-shared;

	opp-100000000 {
	opp-hz = /bits/ 64 <100000000>;
	clock-latency-ns = <300>;
	};
	opp-150000000 {
	opp-hz = /bits/ 64 <150000000>;
	clock-latency-ns = <300>;
	};
	opp-200000000 {
	opp-hz = /bits/ 64 <200000000>;
	clock-latency-ns = <300>;
	};
	opp-300000000 {
	opp-hz = /bits/ 64 <300000000>;
	clock-latency-ns = <300>;
	};
	opp-400000000 {
	opp-hz = /bits/ 64 <400000000>;
	clock-latency-ns = <300>;
	};
	opp-600000000 {
	opp-hz = /bits/ 64 <600000000>;
	clock-latency-ns = <300>;
	};
	opp-800000000 {
	opp-hz = /bits/ 64 <800000000>;
	clock-latency-ns = <300>;
	};
	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	clock-latency-ns = <300>;
	};
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	clocks {
	refclk: ref {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <25000000>;
	};

	arm_timer_clk: arm-timer {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <50000000>;
	};
	};

	thermal-zones {
	cpu-thermal {
	polling-delay-passive = <250>; /* 250ms */
	polling-delay = <1000>; /* 1000ms */
	thermal-sensors = <&pvtctl>;

	trips {
	cpu_crit: cpu-crit {
	temperature = <95000>; /* 95C */
	hysteresis = <2000>;
	type = "critical";
	};
	cpu_alert: cpu-alert {
	temperature = <85000>; /* 85C */
	hysteresis = <2000>;
	type = "passive";
	};
	};

	cooling-maps {
	map {
	trip = <&cpu_alert>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	interrupt-parent = <&intc>;

	- l2: l2-cache@500c0000 {
	+ l2: cache-controller@500c0000 {
	compatible = "socionext,uniphier-system-cache";
	reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
	<0x506c0000 0x400>;
	interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
	cache-unified;
	cache-size = <(1280 * 1024)>;
	cache-sets = <512>;
	cache-line-size = <128>;
	cache-level = <2>;
	};

	spi0: spi@54006000 {
	compatible = "socionext,uniphier-scssi";
	status = "disabled";
	reg = <0x54006000 0x100>;
	interrupts = <0 39 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi0>;
	clocks = <&peri_clk 11>;
	resets = <&peri_rst 11>;
	};

	spi1: spi@54006100 {
	compatible = "socionext,uniphier-scssi";
	status = "disabled";
	reg = <0x54006100 0x100>;
	interrupts = <0 216 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi1>;
	- clocks = <&peri_clk 11>;
	- resets = <&peri_rst 11>;
	+ clocks = <&peri_clk 12>;
	+ resets = <&peri_rst 12>;
	};

	serial0: serial@54006800 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006800 0x40>;
	interrupts = <0 33 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	clocks = <&peri_clk 0>;
	resets = <&peri_rst 0>;
	};

	serial1: serial@54006900 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006900 0x40>;
	interrupts = <0 35 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	clocks = <&peri_clk 1>;
	resets = <&peri_rst 1>;
	};

	serial2: serial@54006a00 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006a00 0x40>;
	interrupts = <0 37 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	clocks = <&peri_clk 2>;
	resets = <&peri_rst 2>;
	};

	serial3: serial@54006b00 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006b00 0x40>;
	interrupts = <0 177 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	clocks = <&peri_clk 3>;
	resets = <&peri_rst 3>;
	};

	gpio: gpio@55000000 {
	compatible = "socionext,uniphier-gpio";
	reg = <0x55000000 0x200>;
	interrupt-parent = <&aidet>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 0 0>,
	<&pinctrl 96 0 0>;
	gpio-ranges-group-names = "gpio_range0",
	"gpio_range1";
	ngpios = <232>;
	socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
	<21 217 3>;
	};

	audio@56000000 {
	compatible = "socionext,uniphier-pxs2-aio";
	reg = <0x56000000 0x80000>;
	interrupts = <0 144 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ain1>,
	<&pinctrl_ain2>,
	<&pinctrl_ainiec1>,
	<&pinctrl_aout2>,
	<&pinctrl_aout3>,
	<&pinctrl_aoutiec1>,
	<&pinctrl_aoutiec2>;
	clock-names = "aio";
	clocks = <&sys_clk 40>;
	reset-names = "aio";
	resets = <&sys_rst 40>;
	#sound-dai-cells = <1>;
	socionext,syscon = <&soc_glue>;

	i2s_port0: port@0 {
	i2s_hdmi: endpoint {
	};
	};

	i2s_port1: port@1 {
	i2s_line: endpoint {
	};
	};

	i2s_port2: port@2 {
	i2s_aux: endpoint {
	};
	};

	spdif_port0: port@3 {
	spdif_hiecout1: endpoint {
	};
	};

	spdif_port1: port@4 {
	spdif_iecout1: endpoint {
	};
	};

	comp_spdif_port0: port@5 {
	comp_spdif_hiecout1: endpoint {
	};
	};

	comp_spdif_port1: port@6 {
	comp_spdif_iecout1: endpoint {
	};
	};
	};

	i2c0: i2c@58780000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58780000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 41 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	clocks = <&peri_clk 4>;
	resets = <&peri_rst 4>;
	clock-frequency = <100000>;
	};

	i2c1: i2c@58781000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58781000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 42 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	clocks = <&peri_clk 5>;
	resets = <&peri_rst 5>;
	clock-frequency = <100000>;
	};

	i2c2: i2c@58782000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58782000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 43 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	clocks = <&peri_clk 6>;
	resets = <&peri_rst 6>;
	clock-frequency = <100000>;
	};

	i2c3: i2c@58783000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58783000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 44 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	clocks = <&peri_clk 7>;
	resets = <&peri_rst 7>;
	clock-frequency = <100000>;
	};

	/* chip-internal connection for DMD */
	i2c4: i2c@58784000 {
	compatible = "socionext,uniphier-fi2c";
	reg = <0x58784000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 45 4>;
	clocks = <&peri_clk 8>;
	resets = <&peri_rst 8>;
	clock-frequency = <400000>;
	};

	/* chip-internal connection for STM */
	i2c5: i2c@58785000 {
	compatible = "socionext,uniphier-fi2c";
	reg = <0x58785000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 25 4>;
	clocks = <&peri_clk 9>;
	resets = <&peri_rst 9>;
	clock-frequency = <400000>;
	};

	/* chip-internal connection for HDMI */
	i2c6: i2c@58786000 {
	compatible = "socionext,uniphier-fi2c";
	reg = <0x58786000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 26 4>;
	clocks = <&peri_clk 10>;
	resets = <&peri_rst 10>;
	clock-frequency = <400000>;
	};

	system_bus: system-bus@58c00000 {
	compatible = "socionext,uniphier-system-bus";
	status = "disabled";
	reg = <0x58c00000 0x400>;
	#address-cells = <2>;
	#size-cells = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_system_bus>;
	};

	smpctrl@59801000 {
	compatible = "socionext,uniphier-smpctrl";
	reg = <0x59801000 0x400>;
	};

	sdctrl@59810000 {
	compatible = "socionext,uniphier-pxs2-sdctrl",
	"simple-mfd", "syscon";
	reg = <0x59810000 0x400>;

	sd_clk: clock {
	compatible = "socionext,uniphier-pxs2-sd-clock";
	#clock-cells = <1>;
	};

	sd_rst: reset {
	compatible = "socionext,uniphier-pxs2-sd-reset";
	#reset-cells = <1>;
	};
	};

	perictrl@59820000 {
	compatible = "socionext,uniphier-pxs2-perictrl",
	"simple-mfd", "syscon";
	reg = <0x59820000 0x200>;

	peri_clk: clock {
	compatible = "socionext,uniphier-pxs2-peri-clock";
	#clock-cells = <1>;
	};

	peri_rst: reset {
	compatible = "socionext,uniphier-pxs2-peri-reset";
	#reset-cells = <1>;
	};
	};

	- emmc: sdhc@5a000000 {
	+ emmc: mmc@5a000000 {
	compatible = "socionext,uniphier-sd-v3.1.1";
	status = "disabled";
	reg = <0x5a000000 0x800>;
	interrupts = <0 78 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_emmc>;
	clocks = <&sd_clk 1>;
	reset-names = "host", "hw";
	resets = <&sd_rst 1>, <&sd_rst 6>;
	bus-width = <8>;
	cap-mmc-highspeed;
	cap-mmc-hw-reset;
	non-removable;
	};

	- sd: sdhc@5a400000 {
	+ sd: mmc@5a400000 {
	compatible = "socionext,uniphier-sd-v3.1.1";
	status = "disabled";
	reg = <0x5a400000 0x800>;
	interrupts = <0 76 4>;
	pinctrl-names = "default", "uhs";
	pinctrl-0 = <&pinctrl_sd>;
	pinctrl-1 = <&pinctrl_sd_uhs>;
	clocks = <&sd_clk 0>;
	reset-names = "host";
	resets = <&sd_rst 0>;
	bus-width = <4>;
	cap-sd-highspeed;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	};

	soc_glue: soc-glue@5f800000 {
	compatible = "socionext,uniphier-pxs2-soc-glue",
	"simple-mfd", "syscon";
	reg = <0x5f800000 0x2000>;

	pinctrl: pinctrl {
	compatible = "socionext,uniphier-pxs2-pinctrl";
	};
	};

	soc-glue@5f900000 {
	compatible = "socionext,uniphier-pxs2-soc-glue-debug",
	"simple-mfd";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x5f900000 0x2000>;

	efuse@100 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x100 0x28>;
	};

	efuse@200 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x200 0x58>;
	};
	};

	- aidet: aidet@5fc20000 {
	+ aidet: interrupt-controller@5fc20000 {
	compatible = "socionext,uniphier-pxs2-aidet";
	reg = <0x5fc20000 0x200>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	timer@60000200 {
	compatible = "arm,cortex-a9-global-timer";
	reg = <0x60000200 0x20>;
	interrupts = <1 11 0xf04>;
	clocks = <&arm_timer_clk>;
	};

	timer@60000600 {
	compatible = "arm,cortex-a9-twd-timer";
	reg = <0x60000600 0x20>;
	interrupts = <1 13 0xf04>;
	clocks = <&arm_timer_clk>;
	};

	intc: interrupt-controller@60001000 {
	compatible = "arm,cortex-a9-gic";
	reg = <0x60001000 0x1000>,
	<0x60000100 0x100>;
	#interrupt-cells = <3>;
	interrupt-controller;
	};

	sysctrl@61840000 {
	compatible = "socionext,uniphier-pxs2-sysctrl",
	"simple-mfd", "syscon";
	reg = <0x61840000 0x10000>;

	sys_clk: clock {
	compatible = "socionext,uniphier-pxs2-clock";
	#clock-cells = <1>;
	};

	sys_rst: reset {
	compatible = "socionext,uniphier-pxs2-reset";
	#reset-cells = <1>;
	};

	pvtctl: pvtctl {
	compatible = "socionext,uniphier-pxs2-thermal";
	interrupts = <0 3 4>;
	#thermal-sensor-cells = <0>;
	socionext,tmod-calibration = <0x0f86 0x6844>;
	};
	};

	eth: ethernet@65000000 {
	compatible = "socionext,uniphier-pxs2-ave4";
	status = "disabled";
	reg = <0x65000000 0x8500>;
	interrupts = <0 66 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ether_rgmii>;
	clock-names = "ether";
	clocks = <&sys_clk 6>;
	reset-names = "ether";
	resets = <&sys_rst 6>;
	phy-mode = "rgmii";
	local-mac-address = [00 00 00 00 00 00];
	socionext,syscon-phy-mode = <&soc_glue 0>;

	mdio: mdio {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	usb0: usb@65a00000 {
	compatible = "socionext,uniphier-dwc3", "snps,dwc3";
	status = "disabled";
	reg = <0x65a00000 0xcd00>;
	interrupt-names = "host", "peripheral";
	interrupts = <0 134 4>, <0 135 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
	clock-names = "ref", "bus_early", "suspend";
	clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
	resets = <&usb0_rst 15>;
	phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
	<&usb0_ssphy0>, <&usb0_ssphy1>;
	dr_mode = "host";
	};

	usb-glue@65b00000 {
	compatible = "socionext,uniphier-pxs2-dwc3-glue",
	"simple-mfd";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x65b00000 0x400>;

	usb0_rst: reset@0 {
	compatible = "socionext,uniphier-pxs2-usb3-reset";
	reg = <0x0 0x4>;
	#reset-cells = <1>;
	clock-names = "link";
	clocks = <&sys_clk 14>;
	reset-names = "link";
	resets = <&sys_rst 14>;
	};

	usb0_vbus0: regulator@100 {
	compatible = "socionext,uniphier-pxs2-usb3-regulator";
	reg = <0x100 0x10>;
	clock-names = "link";
	clocks = <&sys_clk 14>;
	reset-names = "link";
	resets = <&sys_rst 14>;
	};

	usb0_vbus1: regulator@110 {
	compatible = "socionext,uniphier-pxs2-usb3-regulator";
	reg = <0x110 0x10>;
	clock-names = "link";
	clocks = <&sys_clk 14>;
	reset-names = "link";
	resets = <&sys_rst 14>;
	};

	usb0_hsphy0: hs-phy@200 {
	compatible = "socionext,uniphier-pxs2-usb3-hsphy";
	reg = <0x200 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy";
	clocks = <&sys_clk 14>, <&sys_clk 16>;
	reset-names = "link", "phy";
	resets = <&sys_rst 14>, <&sys_rst 16>;
	vbus-supply = <&usb0_vbus0>;
	};

	usb0_hsphy1: hs-phy@210 {
	compatible = "socionext,uniphier-pxs2-usb3-hsphy";
	reg = <0x210 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy";
	clocks = <&sys_clk 14>, <&sys_clk 16>;
	reset-names = "link", "phy";
	resets = <&sys_rst 14>, <&sys_rst 16>;
	vbus-supply = <&usb0_vbus1>;
	};

	usb0_ssphy0: ss-phy@300 {
	compatible = "socionext,uniphier-pxs2-usb3-ssphy";
	reg = <0x300 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy";
	clocks = <&sys_clk 14>, <&sys_clk 17>;
	reset-names = "link", "phy";
	resets = <&sys_rst 14>, <&sys_rst 17>;
	vbus-supply = <&usb0_vbus0>;
	};

	usb0_ssphy1: ss-phy@310 {
	compatible = "socionext,uniphier-pxs2-usb3-ssphy";
	reg = <0x310 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy";
	clocks = <&sys_clk 14>, <&sys_clk 18>;
	reset-names = "link", "phy";
	resets = <&sys_rst 14>, <&sys_rst 18>;
	vbus-supply = <&usb0_vbus1>;
	};
	};

	usb1: usb@65c00000 {
	compatible = "socionext,uniphier-dwc3", "snps,dwc3";
	status = "disabled";
	reg = <0x65c00000 0xcd00>;
	interrupt-names = "host", "peripheral";
	interrupts = <0 137 4>, <0 138 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
	clock-names = "ref", "bus_early", "suspend";
	clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>;
	resets = <&usb1_rst 15>;
	phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
	dr_mode = "host";
	};

	usb-glue@65d00000 {
	compatible = "socionext,uniphier-pxs2-dwc3-glue",
	"simple-mfd";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x65d00000 0x400>;

	usb1_rst: reset@0 {
	compatible = "socionext,uniphier-pxs2-usb3-reset";
	reg = <0x0 0x4>;
	#reset-cells = <1>;
	clock-names = "link";
	clocks = <&sys_clk 15>;
	reset-names = "link";
	resets = <&sys_rst 15>;
	};

	usb1_vbus0: regulator@100 {
	compatible = "socionext,uniphier-pxs2-usb3-regulator";
	reg = <0x100 0x10>;
	clock-names = "link";
	clocks = <&sys_clk 15>;
	reset-names = "link";
	resets = <&sys_rst 15>;
	};

	usb1_vbus1: regulator@110 {
	compatible = "socionext,uniphier-pxs2-usb3-regulator";
	reg = <0x110 0x10>;
	clock-names = "link";
	clocks = <&sys_clk 15>;
	reset-names = "link";
	resets = <&sys_rst 15>;
	};

	usb1_hsphy0: hs-phy@200 {
	compatible = "socionext,uniphier-pxs2-usb3-hsphy";
	reg = <0x200 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy";
	clocks = <&sys_clk 15>, <&sys_clk 20>;
	reset-names = "link", "phy";
	resets = <&sys_rst 15>, <&sys_rst 20>;
	vbus-supply = <&usb1_vbus0>;
	};

	usb1_hsphy1: hs-phy@210 {
	compatible = "socionext,uniphier-pxs2-usb3-hsphy";
	reg = <0x210 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy";
	clocks = <&sys_clk 15>, <&sys_clk 20>;
	reset-names = "link", "phy";
	resets = <&sys_rst 15>, <&sys_rst 20>;
	vbus-supply = <&usb1_vbus1>;
	};

	usb1_ssphy0: ss-phy@300 {
	compatible = "socionext,uniphier-pxs2-usb3-ssphy";
	reg = <0x300 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy";
	clocks = <&sys_clk 15>, <&sys_clk 21>;
	reset-names = "link", "phy";
	resets = <&sys_rst 15>, <&sys_rst 21>;
	vbus-supply = <&usb1_vbus0>;
	};
	};

	- nand: nand@68000000 {
	+ nand: nand-controller@68000000 {
	compatible = "socionext,uniphier-denali-nand-v5b";
	status = "disabled";
	reg-names = "nand_data", "denali_reg";
	reg = <0x68000000 0x20>, <0x68100000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 65 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nand>;
	clock-names = "nand", "nand_x", "ecc";
	clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
	reset-names = "nand", "reg";
	resets = <&sys_rst 2>, <&sys_rst 2>;
	};
	};
	};

	#include "uniphier-pinctrl.dtsi"
	diff --git a/sys/gnu/dts/arm/uniphier-ref-daughter.dtsi b/sys/gnu/dts/arm/uniphier-ref-daughter.dtsi
	index 04e60c295319..a11897669c26 100644
	--- a/sys/gnu/dts/arm/uniphier-ref-daughter.dtsi
	+++ b/sys/gnu/dts/arm/uniphier-ref-daughter.dtsi
	@@ -1,14 +1,14 @@
	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	//
	// Device Tree Source for UniPhier Reference Daughter Board
	//
	// Copyright (C) 2015-2017 Socionext Inc.
	// Author: Masahiro Yamada <yamada.masahiro@socionext.com>

	&i2c0 {
	eeprom@50 {
	- compatible = "microchip,24lc128";
	+ compatible = "microchip,24lc128", "atmel,24c128";
	reg = <0x50>;
	pagesize = <64>;
	};
	};
	diff --git a/sys/gnu/dts/arm/uniphier-sld8.dtsi b/sys/gnu/dts/arm/uniphier-sld8.dtsi
	index 4fc6676f5486..09992163e1f4 100644
	--- a/sys/gnu/dts/arm/uniphier-sld8.dtsi
	+++ b/sys/gnu/dts/arm/uniphier-sld8.dtsi
	@@ -1,423 +1,423 @@
	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	//
	// Device Tree Source for UniPhier sLD8 SoC
	//
	// Copyright (C) 2015-2016 Socionext Inc.
	// Author: Masahiro Yamada <yamada.masahiro@socionext.com>

	#include <dt-bindings/gpio/uniphier-gpio.h>

	/ {
	compatible = "socionext,uniphier-sld8";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <0>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	};
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	clocks {
	refclk: ref {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <25000000>;
	};

	arm_timer_clk: arm-timer {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <50000000>;
	};
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	interrupt-parent = <&intc>;

	- l2: l2-cache@500c0000 {
	+ l2: cache-controller@500c0000 {
	compatible = "socionext,uniphier-system-cache";
	reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
	<0x506c0000 0x400>;
	interrupts = <0 174 4>, <0 175 4>;
	cache-unified;
	cache-size = <(256 * 1024)>;
	cache-sets = <256>;
	cache-line-size = <128>;
	cache-level = <2>;
	};

	spi: spi@54006000 {
	compatible = "socionext,uniphier-scssi";
	status = "disabled";
	reg = <0x54006000 0x100>;
	interrupts = <0 39 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi0>;
	clocks = <&peri_clk 11>;
	resets = <&peri_rst 11>;
	};

	serial0: serial@54006800 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006800 0x40>;
	interrupts = <0 33 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	clocks = <&peri_clk 0>;
	resets = <&peri_rst 0>;
	};

	serial1: serial@54006900 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006900 0x40>;
	interrupts = <0 35 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	clocks = <&peri_clk 1>;
	resets = <&peri_rst 1>;
	};

	serial2: serial@54006a00 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006a00 0x40>;
	interrupts = <0 37 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	clocks = <&peri_clk 2>;
	resets = <&peri_rst 2>;
	};

	serial3: serial@54006b00 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006b00 0x40>;
	interrupts = <0 29 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	clocks = <&peri_clk 3>;
	resets = <&peri_rst 3>;
	};

	gpio: gpio@55000000 {
	compatible = "socionext,uniphier-gpio";
	reg = <0x55000000 0x200>;
	interrupt-parent = <&aidet>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 0 0>,
	<&pinctrl 104 0 0>,
	<&pinctrl 112 0 0>;
	gpio-ranges-group-names = "gpio_range0",
	"gpio_range1",
	"gpio_range2";
	ngpios = <136>;
	socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
	};

	i2c0: i2c@58400000 {
	compatible = "socionext,uniphier-i2c";
	status = "disabled";
	reg = <0x58400000 0x40>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 41 1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	clocks = <&peri_clk 4>;
	resets = <&peri_rst 4>;
	clock-frequency = <100000>;
	};

	i2c1: i2c@58480000 {
	compatible = "socionext,uniphier-i2c";
	status = "disabled";
	reg = <0x58480000 0x40>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 42 1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	clocks = <&peri_clk 5>;
	resets = <&peri_rst 5>;
	clock-frequency = <100000>;
	};

	/* chip-internal connection for DMD */
	i2c2: i2c@58500000 {
	compatible = "socionext,uniphier-i2c";
	reg = <0x58500000 0x40>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 43 1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	clocks = <&peri_clk 6>;
	resets = <&peri_rst 6>;
	clock-frequency = <400000>;
	};

	i2c3: i2c@58580000 {
	compatible = "socionext,uniphier-i2c";
	status = "disabled";
	reg = <0x58580000 0x40>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 44 1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	clocks = <&peri_clk 7>;
	resets = <&peri_rst 7>;
	clock-frequency = <100000>;
	};

	system_bus: system-bus@58c00000 {
	compatible = "socionext,uniphier-system-bus";
	status = "disabled";
	reg = <0x58c00000 0x400>;
	#address-cells = <2>;
	#size-cells = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_system_bus>;
	};

	smpctrl@59801000 {
	compatible = "socionext,uniphier-smpctrl";
	reg = <0x59801000 0x400>;
	};

	mioctrl@59810000 {
	compatible = "socionext,uniphier-sld8-mioctrl",
	"simple-mfd", "syscon";
	reg = <0x59810000 0x800>;

	mio_clk: clock {
	compatible = "socionext,uniphier-sld8-mio-clock";
	#clock-cells = <1>;
	};

	mio_rst: reset {
	compatible = "socionext,uniphier-sld8-mio-reset";
	#reset-cells = <1>;
	};
	};

	perictrl@59820000 {
	compatible = "socionext,uniphier-sld8-perictrl",
	"simple-mfd", "syscon";
	reg = <0x59820000 0x200>;

	peri_clk: clock {
	compatible = "socionext,uniphier-sld8-peri-clock";
	#clock-cells = <1>;
	};

	peri_rst: reset {
	compatible = "socionext,uniphier-sld8-peri-reset";
	#reset-cells = <1>;
	};
	};

	dmac: dma-controller@5a000000 {
	compatible = "socionext,uniphier-mio-dmac";
	reg = <0x5a000000 0x1000>;
	interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
	<0 71 4>, <0 72 4>, <0 73 4>;
	clocks = <&mio_clk 7>;
	resets = <&mio_rst 7>;
	#dma-cells = <1>;
	};

	- sd: sdhc@5a400000 {
	+ sd: mmc@5a400000 {
	compatible = "socionext,uniphier-sd-v2.91";
	status = "disabled";
	reg = <0x5a400000 0x200>;
	interrupts = <0 76 4>;
	pinctrl-names = "default", "uhs";
	pinctrl-0 = <&pinctrl_sd>;
	pinctrl-1 = <&pinctrl_sd_uhs>;
	clocks = <&mio_clk 0>;
	reset-names = "host", "bridge";
	resets = <&mio_rst 0>, <&mio_rst 3>;
	dma-names = "rx-tx";
	dmas = <&dmac 4>;
	bus-width = <4>;
	cap-sd-highspeed;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	};

	- emmc: sdhc@5a500000 {
	+ emmc: mmc@5a500000 {
	compatible = "socionext,uniphier-sd-v2.91";
	status = "disabled";
	reg = <0x5a500000 0x200>;
	interrupts = <0 78 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_emmc>;
	clocks = <&mio_clk 1>;
	reset-names = "host", "bridge", "hw";
	resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
	dma-names = "rx-tx";
	dmas = <&dmac 6>;
	bus-width = <8>;
	cap-mmc-highspeed;
	cap-mmc-hw-reset;
	non-removable;
	};

	usb0: usb@5a800100 {
	compatible = "socionext,uniphier-ehci", "generic-ehci";
	status = "disabled";
	reg = <0x5a800100 0x100>;
	interrupts = <0 80 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb0>;
	clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
	<&mio_clk 12>;
	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
	<&mio_rst 12>;
	has-transaction-translator;
	};

	usb1: usb@5a810100 {
	compatible = "socionext,uniphier-ehci", "generic-ehci";
	status = "disabled";
	reg = <0x5a810100 0x100>;
	interrupts = <0 81 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb1>;
	clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
	<&mio_clk 13>;
	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
	<&mio_rst 13>;
	has-transaction-translator;
	};

	usb2: usb@5a820100 {
	compatible = "socionext,uniphier-ehci", "generic-ehci";
	status = "disabled";
	reg = <0x5a820100 0x100>;
	interrupts = <0 82 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb2>;
	clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
	<&mio_clk 14>;
	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
	<&mio_rst 14>;
	has-transaction-translator;
	};

	soc-glue@5f800000 {
	compatible = "socionext,uniphier-sld8-soc-glue",
	"simple-mfd", "syscon";
	reg = <0x5f800000 0x2000>;

	pinctrl: pinctrl {
	compatible = "socionext,uniphier-sld8-pinctrl";
	};
	};

	soc-glue@5f900000 {
	compatible = "socionext,uniphier-sld8-soc-glue-debug",
	"simple-mfd";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x5f900000 0x2000>;

	efuse@100 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x100 0x28>;
	};

	efuse@200 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x200 0x14>;
	};
	};

	timer@60000200 {
	compatible = "arm,cortex-a9-global-timer";
	reg = <0x60000200 0x20>;
	interrupts = <1 11 0x104>;
	clocks = <&arm_timer_clk>;
	};

	timer@60000600 {
	compatible = "arm,cortex-a9-twd-timer";
	reg = <0x60000600 0x20>;
	interrupts = <1 13 0x104>;
	clocks = <&arm_timer_clk>;
	};

	intc: interrupt-controller@60001000 {
	compatible = "arm,cortex-a9-gic";
	reg = <0x60001000 0x1000>,
	<0x60000100 0x100>;
	#interrupt-cells = <3>;
	interrupt-controller;
	};

	- aidet: aidet@61830000 {
	+ aidet: interrupt-controller@61830000 {
	compatible = "socionext,uniphier-sld8-aidet";
	reg = <0x61830000 0x200>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	sysctrl@61840000 {
	compatible = "socionext,uniphier-sld8-sysctrl",
	"simple-mfd", "syscon";
	reg = <0x61840000 0x10000>;

	sys_clk: clock {
	compatible = "socionext,uniphier-sld8-clock";
	#clock-cells = <1>;
	};

	sys_rst: reset {
	compatible = "socionext,uniphier-sld8-reset";
	#reset-cells = <1>;
	};
	};

	- nand: nand@68000000 {
	+ nand: nand-controller@68000000 {
	compatible = "socionext,uniphier-denali-nand-v5a";
	status = "disabled";
	reg-names = "nand_data", "denali_reg";
	reg = <0x68000000 0x20>, <0x68100000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 65 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nand>;
	clock-names = "nand", "nand_x", "ecc";
	clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
	reset-names = "nand", "reg";
	resets = <&sys_rst 2>, <&sys_rst 2>;
	};
	};
	};

	#include "uniphier-pinctrl.dtsi"
	diff --git a/sys/gnu/dts/arm/versatile-ab-ib2.dts b/sys/gnu/dts/arm/versatile-ab-ib2.dts
	index 5890cb974f78..c577ff4bb4be 100644
	--- a/sys/gnu/dts/arm/versatile-ab-ib2.dts
	+++ b/sys/gnu/dts/arm/versatile-ab-ib2.dts
	@@ -1,26 +1,26 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* The Versatile AB with the IB2 expansion board mounted.
	* This works as a superset of the Versatile AB.
	*/

	#include "versatile-ab.dts"

	/ {
	model = "ARM Versatile AB + IB2 board";

	/* Special IB2 control register */
	- ib2_syscon@27000000 {
	+ syscon@27000000 {
	compatible = "arm,versatile-ib2-syscon", "syscon", "simple-mfd";
	reg = <0x27000000 0x4>;

	led@00.4 {
	compatible = "register-bit-led";
	offset = <0x00>;
	mask = <0x10>;
	label = "versatile-ib2:0";
	linux,default-trigger = "heartbeat";
	default-state = "on";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/vexpress-v2m-rs1.dtsi b/sys/gnu/dts/arm/vexpress-v2m-rs1.dtsi
	index dfae90adbb7c..5c183483ec3b 100644
	--- a/sys/gnu/dts/arm/vexpress-v2m-rs1.dtsi
	+++ b/sys/gnu/dts/arm/vexpress-v2m-rs1.dtsi
	@@ -1,441 +1,441 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* ARM Ltd. Versatile Express
	*
	* Motherboard Express uATX
	* V2M-P1
	*
	* HBI-0190D
	*
	* RS1 memory map ("ARM Cortex-A Series memory map" in the board's
	* Technical Reference Manual)
	*
	* WARNING! The hardware described in this file is independent from the
	* original variant (vexpress-v2m.dtsi), but there is a strong
	* correspondence between the two configurations.
	*
	* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
	* CHANGES TO vexpress-v2m.dtsi!
	*/

	/ {
	- smb@8000000 {
	+ bus@8000000 {
	motherboard {
	model = "V2M-P1";
	arm,hbi = <0x190>;
	arm,vexpress,site = <0>;
	arm,v2m-memory-map = "rs1";
	compatible = "arm,vexpress,v2m-p1", "simple-bus";
	#address-cells = <2>; /* SMB chipselect number and offset */
	#size-cells = <1>;
	#interrupt-cells = <1>;
	ranges;

	nor_flash: flash@0,00000000 {
	compatible = "arm,vexpress-flash", "cfi-flash";
	reg = <0 0x00000000 0x04000000>,
	<4 0x00000000 0x04000000>;
	bank-width = <4>;
	partitions {
	compatible = "arm,arm-firmware-suite";
	};
	};

	psram@1,00000000 {
	compatible = "arm,vexpress-psram", "mtd-ram";
	reg = <1 0x00000000 0x02000000>;
	bank-width = <4>;
	};

	ethernet@2,02000000 {
	compatible = "smsc,lan9118", "smsc,lan9115";
	reg = <2 0x02000000 0x10000>;
	interrupts = <15>;
	phy-mode = "mii";
	reg-io-width = <4>;
	smsc,irq-active-high;
	smsc,irq-push-pull;
	vdd33a-supply = <&v2m_fixed_3v3>;
	vddvario-supply = <&v2m_fixed_3v3>;
	};

	usb@2,03000000 {
	compatible = "nxp,usb-isp1761";
	reg = <2 0x03000000 0x20000>;
	interrupts = <16>;
	port1-otg;
	};

	iofpga@3,00000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 3 0 0x200000>;

	v2m_sysreg: sysreg@10000 {
	compatible = "arm,vexpress-sysreg";
	reg = <0x010000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x10000 0x1000>;

	v2m_led_gpios: gpio@8 {
	compatible = "arm,vexpress-sysreg,sys_led";
	reg = <0x008 4>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	v2m_mmc_gpios: gpio@48 {
	compatible = "arm,vexpress-sysreg,sys_mci";
	reg = <0x048 4>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	v2m_flash_gpios: gpio@4c {
	compatible = "arm,vexpress-sysreg,sys_flash";
	reg = <0x04c 4>;
	gpio-controller;
	#gpio-cells = <2>;
	};
	};

	v2m_sysctl: sysctl@20000 {
	compatible = "arm,sp810", "arm,primecell";
	reg = <0x020000 0x1000>;
	clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
	clock-names = "refclk", "timclk", "apb_pclk";
	#clock-cells = <1>;
	clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
	assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
	assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
	};

	/* PCI-E I2C bus */
	v2m_i2c_pcie: i2c@30000 {
	compatible = "arm,versatile-i2c";
	reg = <0x030000 0x1000>;

	#address-cells = <1>;
	#size-cells = <0>;

	pcie-switch@60 {
	compatible = "idt,89hpes32h8";
	reg = <0x60>;
	};
	};

	aaci@40000 {
	compatible = "arm,pl041", "arm,primecell";
	reg = <0x040000 0x1000>;
	interrupts = <11>;
	clocks = <&smbclk>;
	clock-names = "apb_pclk";
	};

	mmci@50000 {
	compatible = "arm,pl180", "arm,primecell";
	reg = <0x050000 0x1000>;
	interrupts = <9>, <10>;
	cd-gpios = <&v2m_mmc_gpios 0 0>;
	wp-gpios = <&v2m_mmc_gpios 1 0>;
	max-frequency = <12000000>;
	vmmc-supply = <&v2m_fixed_3v3>;
	clocks = <&v2m_clk24mhz>, <&smbclk>;
	clock-names = "mclk", "apb_pclk";
	};

	kmi@60000 {
	compatible = "arm,pl050", "arm,primecell";
	reg = <0x060000 0x1000>;
	interrupts = <12>;
	clocks = <&v2m_clk24mhz>, <&smbclk>;
	clock-names = "KMIREFCLK", "apb_pclk";
	};

	kmi@70000 {
	compatible = "arm,pl050", "arm,primecell";
	reg = <0x070000 0x1000>;
	interrupts = <13>;
	clocks = <&v2m_clk24mhz>, <&smbclk>;
	clock-names = "KMIREFCLK", "apb_pclk";
	};

	v2m_serial0: uart@90000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x090000 0x1000>;
	interrupts = <5>;
	clocks = <&v2m_oscclk2>, <&smbclk>;
	clock-names = "uartclk", "apb_pclk";
	};

	v2m_serial1: uart@a0000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x0a0000 0x1000>;
	interrupts = <6>;
	clocks = <&v2m_oscclk2>, <&smbclk>;
	clock-names = "uartclk", "apb_pclk";
	};

	v2m_serial2: uart@b0000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x0b0000 0x1000>;
	interrupts = <7>;
	clocks = <&v2m_oscclk2>, <&smbclk>;
	clock-names = "uartclk", "apb_pclk";
	};

	v2m_serial3: uart@c0000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x0c0000 0x1000>;
	interrupts = <8>;
	clocks = <&v2m_oscclk2>, <&smbclk>;
	clock-names = "uartclk", "apb_pclk";
	};

	wdt@f0000 {
	compatible = "arm,sp805", "arm,primecell";
	reg = <0x0f0000 0x1000>;
	interrupts = <0>;
	clocks = <&v2m_refclk32khz>, <&smbclk>;
	clock-names = "wdogclk", "apb_pclk";
	};

	v2m_timer01: timer@110000 {
	compatible = "arm,sp804", "arm,primecell";
	reg = <0x110000 0x1000>;
	interrupts = <2>;
	clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
	clock-names = "timclken1", "timclken2", "apb_pclk";
	};

	v2m_timer23: timer@120000 {
	compatible = "arm,sp804", "arm,primecell";
	reg = <0x120000 0x1000>;
	interrupts = <3>;
	clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
	clock-names = "timclken1", "timclken2", "apb_pclk";
	};

	/* DVI I2C bus */
	v2m_i2c_dvi: i2c@160000 {
	compatible = "arm,versatile-i2c";
	reg = <0x160000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;

	dvi-transmitter@39 {
	compatible = "sil,sii9022-tpi", "sil,sii9022";
	reg = <0x39>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	dvi_bridge_in: endpoint {
	remote-endpoint = <&clcd_pads>;
	};
	};
	};
	};

	dvi-transmitter@60 {
	compatible = "sil,sii9022-cpi", "sil,sii9022";
	reg = <0x60>;
	};
	};

	rtc@170000 {
	compatible = "arm,pl031", "arm,primecell";
	reg = <0x170000 0x1000>;
	interrupts = <4>;
	clocks = <&smbclk>;
	clock-names = "apb_pclk";
	};

	compact-flash@1a0000 {
	compatible = "arm,vexpress-cf", "ata-generic";
	reg = <0x1a0000 0x100
	0x1a0100 0xf00>;
	reg-shift = <2>;
	};

	clcd@1f0000 {
	compatible = "arm,pl111", "arm,primecell";
	reg = <0x1f0000 0x1000>;
	interrupt-names = "combined";
	interrupts = <14>;
	clocks = <&v2m_oscclk1>, <&smbclk>;
	clock-names = "clcdclk", "apb_pclk";
	/* 800x600 16bpp @36MHz works fine */
	max-memory-bandwidth = <54000000>;
	memory-region = <&vram>;

	port {
	clcd_pads: endpoint {
	remote-endpoint = <&dvi_bridge_in>;
	arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
	};
	};
	};
	};

	v2m_fixed_3v3: fixed-regulator-0 {
	compatible = "regulator-fixed";
	regulator-name = "3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	v2m_clk24mhz: clk24mhz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "v2m:clk24mhz";
	};

	v2m_refclk1mhz: refclk1mhz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <1000000>;
	clock-output-names = "v2m:refclk1mhz";
	};

	v2m_refclk32khz: refclk32khz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "v2m:refclk32khz";
	};

	leds {
	compatible = "gpio-leds";

	user1 {
	label = "v2m:green:user1";
	gpios = <&v2m_led_gpios 0 0>;
	linux,default-trigger = "heartbeat";
	};

	user2 {
	label = "v2m:green:user2";
	gpios = <&v2m_led_gpios 1 0>;
	linux,default-trigger = "mmc0";
	};

	user3 {
	label = "v2m:green:user3";
	gpios = <&v2m_led_gpios 2 0>;
	linux,default-trigger = "cpu0";
	};

	user4 {
	label = "v2m:green:user4";
	gpios = <&v2m_led_gpios 3 0>;
	linux,default-trigger = "cpu1";
	};

	user5 {
	label = "v2m:green:user5";
	gpios = <&v2m_led_gpios 4 0>;
	linux,default-trigger = "cpu2";
	};

	user6 {
	label = "v2m:green:user6";
	gpios = <&v2m_led_gpios 5 0>;
	linux,default-trigger = "cpu3";
	};

	user7 {
	label = "v2m:green:user7";
	gpios = <&v2m_led_gpios 6 0>;
	linux,default-trigger = "cpu4";
	};

	user8 {
	label = "v2m:green:user8";
	gpios = <&v2m_led_gpios 7 0>;
	linux,default-trigger = "cpu5";
	};
	};

	mcc {
	compatible = "arm,vexpress,config-bus";
	arm,vexpress,config-bridge = <&v2m_sysreg>;

	oscclk0 {
	/* MCC static memory clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 0>;
	freq-range = <25000000 60000000>;
	#clock-cells = <0>;
	clock-output-names = "v2m:oscclk0";
	};

	v2m_oscclk1: oscclk1 {
	/* CLCD clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 1>;
	freq-range = <23750000 65000000>;
	#clock-cells = <0>;
	clock-output-names = "v2m:oscclk1";
	};

	v2m_oscclk2: oscclk2 {
	/* IO FPGA peripheral clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 2>;
	freq-range = <24000000 24000000>;
	#clock-cells = <0>;
	clock-output-names = "v2m:oscclk2";
	};

	volt-vio {
	/* Logic level voltage */
	compatible = "arm,vexpress-volt";
	arm,vexpress-sysreg,func = <2 0>;
	regulator-name = "VIO";
	regulator-always-on;
	label = "VIO";
	};

	temp-mcc {
	/* MCC internal operating temperature */
	compatible = "arm,vexpress-temp";
	arm,vexpress-sysreg,func = <4 0>;
	label = "MCC";
	};

	reset {
	compatible = "arm,vexpress-reset";
	arm,vexpress-sysreg,func = <5 0>;
	};

	muxfpga {
	compatible = "arm,vexpress-muxfpga";
	arm,vexpress-sysreg,func = <7 0>;
	};

	shutdown {
	compatible = "arm,vexpress-shutdown";
	arm,vexpress-sysreg,func = <8 0>;
	};

	reboot {
	compatible = "arm,vexpress-reboot";
	arm,vexpress-sysreg,func = <9 0>;
	};

	dvimode {
	compatible = "arm,vexpress-dvimode";
	arm,vexpress-sysreg,func = <11 0>;
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/vexpress-v2m.dtsi b/sys/gnu/dts/arm/vexpress-v2m.dtsi
	index 2e29d7790497..5e48b641068a 100644
	--- a/sys/gnu/dts/arm/vexpress-v2m.dtsi
	+++ b/sys/gnu/dts/arm/vexpress-v2m.dtsi
	@@ -1,454 +1,454 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* ARM Ltd. Versatile Express
	*
	* Motherboard Express uATX
	* V2M-P1
	*
	* HBI-0190D
	*
	* Original memory map ("Legacy memory map" in the board's
	* Technical Reference Manual)
	*
	* WARNING! The hardware described in this file is independent from the
	* RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
	* correspondence between the two configurations.
	*
	* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
	* CHANGES TO vexpress-v2m-rs1.dtsi!
	*/

	/ {
	- smb@4000000 {
	+ bus@4000000 {
	motherboard {
	model = "V2M-P1";
	arm,hbi = <0x190>;
	arm,vexpress,site = <0>;
	compatible = "arm,vexpress,v2m-p1", "simple-bus";
	#address-cells = <2>; /* SMB chipselect number and offset */
	#size-cells = <1>;
	#interrupt-cells = <1>;
	ranges;

	flash@0,00000000 {
	compatible = "arm,vexpress-flash", "cfi-flash";
	reg = <0 0x00000000 0x04000000>,
	<1 0x00000000 0x04000000>;
	bank-width = <4>;
	partitions {
	compatible = "arm,arm-firmware-suite";
	};
	};

	psram@2,00000000 {
	compatible = "arm,vexpress-psram", "mtd-ram";
	reg = <2 0x00000000 0x02000000>;
	bank-width = <4>;
	};

	ethernet@3,02000000 {
	compatible = "smsc,lan9118", "smsc,lan9115";
	reg = <3 0x02000000 0x10000>;
	interrupts = <15>;
	phy-mode = "mii";
	reg-io-width = <4>;
	smsc,irq-active-high;
	smsc,irq-push-pull;
	vdd33a-supply = <&v2m_fixed_3v3>;
	vddvario-supply = <&v2m_fixed_3v3>;
	};

	usb@3,03000000 {
	compatible = "nxp,usb-isp1761";
	reg = <3 0x03000000 0x20000>;
	interrupts = <16>;
	port1-otg;
	};

	iofpga@7,00000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 7 0 0x20000>;

	v2m_sysreg: sysreg@0 {
	compatible = "arm,vexpress-sysreg";
	reg = <0x00000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x1000>;

	v2m_led_gpios: gpio@8 {
	compatible = "arm,vexpress-sysreg,sys_led";
	reg = <0x008 4>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	v2m_mmc_gpios: gpio@48 {
	compatible = "arm,vexpress-sysreg,sys_mci";
	reg = <0x048 4>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	v2m_flash_gpios: gpio@4c {
	compatible = "arm,vexpress-sysreg,sys_flash";
	reg = <0x04c 4>;
	gpio-controller;
	#gpio-cells = <2>;
	};
	};

	v2m_sysctl: sysctl@1000 {
	compatible = "arm,sp810", "arm,primecell";
	reg = <0x01000 0x1000>;
	clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
	clock-names = "refclk", "timclk", "apb_pclk";
	#clock-cells = <1>;
	clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
	assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
	assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
	};

	/* PCI-E I2C bus */
	v2m_i2c_pcie: i2c@2000 {
	compatible = "arm,versatile-i2c";
	reg = <0x02000 0x1000>;

	#address-cells = <1>;
	#size-cells = <0>;

	pcie-switch@60 {
	compatible = "idt,89hpes32h8";
	reg = <0x60>;
	};
	};

	aaci@4000 {
	compatible = "arm,pl041", "arm,primecell";
	reg = <0x04000 0x1000>;
	interrupts = <11>;
	clocks = <&smbclk>;
	clock-names = "apb_pclk";
	};

	mmci@5000 {
	compatible = "arm,pl180", "arm,primecell";
	reg = <0x05000 0x1000>;
	interrupts = <9>, <10>;
	cd-gpios = <&v2m_mmc_gpios 0 0>;
	wp-gpios = <&v2m_mmc_gpios 1 0>;
	max-frequency = <12000000>;
	vmmc-supply = <&v2m_fixed_3v3>;
	clocks = <&v2m_clk24mhz>, <&smbclk>;
	clock-names = "mclk", "apb_pclk";
	};

	kmi@6000 {
	compatible = "arm,pl050", "arm,primecell";
	reg = <0x06000 0x1000>;
	interrupts = <12>;
	clocks = <&v2m_clk24mhz>, <&smbclk>;
	clock-names = "KMIREFCLK", "apb_pclk";
	};

	kmi@7000 {
	compatible = "arm,pl050", "arm,primecell";
	reg = <0x07000 0x1000>;
	interrupts = <13>;
	clocks = <&v2m_clk24mhz>, <&smbclk>;
	clock-names = "KMIREFCLK", "apb_pclk";
	};

	v2m_serial0: uart@9000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x09000 0x1000>;
	interrupts = <5>;
	clocks = <&v2m_oscclk2>, <&smbclk>;
	clock-names = "uartclk", "apb_pclk";
	};

	v2m_serial1: uart@a000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x0a000 0x1000>;
	interrupts = <6>;
	clocks = <&v2m_oscclk2>, <&smbclk>;
	clock-names = "uartclk", "apb_pclk";
	};

	v2m_serial2: uart@b000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x0b000 0x1000>;
	interrupts = <7>;
	clocks = <&v2m_oscclk2>, <&smbclk>;
	clock-names = "uartclk", "apb_pclk";
	};

	v2m_serial3: uart@c000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x0c000 0x1000>;
	interrupts = <8>;
	clocks = <&v2m_oscclk2>, <&smbclk>;
	clock-names = "uartclk", "apb_pclk";
	};

	wdt@f000 {
	compatible = "arm,sp805", "arm,primecell";
	reg = <0x0f000 0x1000>;
	interrupts = <0>;
	clocks = <&v2m_refclk32khz>, <&smbclk>;
	clock-names = "wdogclk", "apb_pclk";
	};

	v2m_timer01: timer@11000 {
	compatible = "arm,sp804", "arm,primecell";
	reg = <0x11000 0x1000>;
	interrupts = <2>;
	clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
	clock-names = "timclken1", "timclken2", "apb_pclk";
	};

	v2m_timer23: timer@12000 {
	compatible = "arm,sp804", "arm,primecell";
	reg = <0x12000 0x1000>;
	interrupts = <3>;
	clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
	clock-names = "timclken1", "timclken2", "apb_pclk";
	};

	/* DVI I2C bus */
	v2m_i2c_dvi: i2c@16000 {
	compatible = "arm,versatile-i2c";
	reg = <0x16000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;

	dvi-transmitter@39 {
	compatible = "sil,sii9022-tpi", "sil,sii9022";
	reg = <0x39>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	/*
	* Both the core tile and the motherboard routes their output
	* pads to this transmitter. The motherboard system controller
	* can select one of them as input using a mux register in
	* "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is
	* the only platform with this specific set-up.
	*/
	port@0 {
	reg = <0>;
	dvi_bridge_in_ct: endpoint {
	remote-endpoint = <&clcd_pads_ct>;
	};
	};
	port@1 {
	reg = <1>;
	dvi_bridge_in_mb: endpoint {
	remote-endpoint = <&clcd_pads_mb>;
	};
	};
	};
	};

	dvi-transmitter@60 {
	compatible = "sil,sii9022-cpi", "sil,sii9022";
	reg = <0x60>;
	};
	};

	rtc@17000 {
	compatible = "arm,pl031", "arm,primecell";
	reg = <0x17000 0x1000>;
	interrupts = <4>;
	clocks = <&smbclk>;
	clock-names = "apb_pclk";
	};

	compact-flash@1a000 {
	compatible = "arm,vexpress-cf", "ata-generic";
	reg = <0x1a000 0x100
	0x1a100 0xf00>;
	reg-shift = <2>;
	};


	clcd@1f000 {
	compatible = "arm,pl111", "arm,primecell";
	reg = <0x1f000 0x1000>;
	interrupt-names = "combined";
	interrupts = <14>;
	clocks = <&v2m_oscclk1>, <&smbclk>;
	clock-names = "clcdclk", "apb_pclk";
	/* 800x600 16bpp @36MHz works fine */
	max-memory-bandwidth = <54000000>;
	memory-region = <&vram>;

	port {
	clcd_pads_mb: endpoint {
	remote-endpoint = <&dvi_bridge_in_mb>;
	arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
	};
	};
	};
	};

	v2m_fixed_3v3: fixed-regulator-0 {
	compatible = "regulator-fixed";
	regulator-name = "3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	v2m_clk24mhz: clk24mhz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "v2m:clk24mhz";
	};

	v2m_refclk1mhz: refclk1mhz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <1000000>;
	clock-output-names = "v2m:refclk1mhz";
	};

	v2m_refclk32khz: refclk32khz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "v2m:refclk32khz";
	};

	leds {
	compatible = "gpio-leds";

	user1 {
	label = "v2m:green:user1";
	gpios = <&v2m_led_gpios 0 0>;
	linux,default-trigger = "heartbeat";
	};

	user2 {
	label = "v2m:green:user2";
	gpios = <&v2m_led_gpios 1 0>;
	linux,default-trigger = "mmc0";
	};

	user3 {
	label = "v2m:green:user3";
	gpios = <&v2m_led_gpios 2 0>;
	linux,default-trigger = "cpu0";
	};

	user4 {
	label = "v2m:green:user4";
	gpios = <&v2m_led_gpios 3 0>;
	linux,default-trigger = "cpu1";
	};

	user5 {
	label = "v2m:green:user5";
	gpios = <&v2m_led_gpios 4 0>;
	linux,default-trigger = "cpu2";
	};

	user6 {
	label = "v2m:green:user6";
	gpios = <&v2m_led_gpios 5 0>;
	linux,default-trigger = "cpu3";
	};

	user7 {
	label = "v2m:green:user7";
	gpios = <&v2m_led_gpios 6 0>;
	linux,default-trigger = "cpu4";
	};

	user8 {
	label = "v2m:green:user8";
	gpios = <&v2m_led_gpios 7 0>;
	linux,default-trigger = "cpu5";
	};
	};

	mcc {
	compatible = "arm,vexpress,config-bus";
	arm,vexpress,config-bridge = <&v2m_sysreg>;

	oscclk0 {
	/* MCC static memory clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 0>;
	freq-range = <25000000 60000000>;
	#clock-cells = <0>;
	clock-output-names = "v2m:oscclk0";
	};

	v2m_oscclk1: oscclk1 {
	/* CLCD clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 1>;
	freq-range = <23750000 65000000>;
	#clock-cells = <0>;
	clock-output-names = "v2m:oscclk1";
	};

	v2m_oscclk2: oscclk2 {
	/* IO FPGA peripheral clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 2>;
	freq-range = <24000000 24000000>;
	#clock-cells = <0>;
	clock-output-names = "v2m:oscclk2";
	};

	volt-vio {
	/* Logic level voltage */
	compatible = "arm,vexpress-volt";
	arm,vexpress-sysreg,func = <2 0>;
	regulator-name = "VIO";
	regulator-always-on;
	label = "VIO";
	};

	temp-mcc {
	/* MCC internal operating temperature */
	compatible = "arm,vexpress-temp";
	arm,vexpress-sysreg,func = <4 0>;
	label = "MCC";
	};

	reset {
	compatible = "arm,vexpress-reset";
	arm,vexpress-sysreg,func = <5 0>;
	};

	muxfpga {
	compatible = "arm,vexpress-muxfpga";
	arm,vexpress-sysreg,func = <7 0>;
	};

	shutdown {
	compatible = "arm,vexpress-shutdown";
	arm,vexpress-sysreg,func = <8 0>;
	};

	reboot {
	compatible = "arm,vexpress-reboot";
	arm,vexpress-sysreg,func = <9 0>;
	};

	dvimode {
	compatible = "arm,vexpress-dvimode";
	arm,vexpress-sysreg,func = <11 0>;
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/vexpress-v2p-ca15-tc1.dts b/sys/gnu/dts/arm/vexpress-v2p-ca15-tc1.dts
	index 0dc4277d5f8b..f82fa34c90be 100644
	--- a/sys/gnu/dts/arm/vexpress-v2p-ca15-tc1.dts
	+++ b/sys/gnu/dts/arm/vexpress-v2p-ca15-tc1.dts
	@@ -1,310 +1,310 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* ARM Ltd. Versatile Express
	*
	* CoreTile Express A15x2 (version with Test Chip 1)
	* Cortex-A15 MPCore (V2P-CA15)
	*
	* HBI-0237A
	*/

	/dts-v1/;
	#include "vexpress-v2m-rs1.dtsi"

	/ {
	model = "V2P-CA15";
	arm,hbi = <0x237>;
	arm,vexpress,site = <0xf>;
	compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	aliases {
	serial0 = &v2m_serial0;
	serial1 = &v2m_serial1;
	serial2 = &v2m_serial2;
	serial3 = &v2m_serial3;
	i2c0 = &v2m_i2c_dvi;
	i2c1 = &v2m_i2c_pcie;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0>;
	};

	cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <1>;
	};
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0 0x80000000 0 0x40000000>;
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	/* Chipselect 2 is physically at 0x18000000 */
	vram: vram@18000000 {
	/* 8 MB of designated video RAM */
	compatible = "shared-dma-pool";
	reg = <0 0x18000000 0 0x00800000>;
	no-map;
	};
	};

	hdlcd@2b000000 {
	compatible = "arm,hdlcd";
	reg = <0 0x2b000000 0 0x1000>;
	interrupts = <0 85 4>;
	clocks = <&hdlcd_clk>;
	clock-names = "pxlclk";
	};

	memory-controller@2b0a0000 {
	compatible = "arm,pl341", "arm,primecell";
	reg = <0 0x2b0a0000 0 0x1000>;
	clocks = <&sys_pll>;
	clock-names = "apb_pclk";
	};

	wdt@2b060000 {
	compatible = "arm,sp805", "arm,primecell";
	status = "disabled";
	reg = <0 0x2b060000 0 0x1000>;
	interrupts = <0 98 4>;
	clocks = <&sys_pll>;
	clock-names = "apb_pclk";
	};

	gic: interrupt-controller@2c001000 {
	compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0 0x2c001000 0 0x1000>,
	<0 0x2c002000 0 0x2000>,
	<0 0x2c004000 0 0x2000>,
	<0 0x2c006000 0 0x2000>;
	interrupts = <1 9 0xf04>;
	};

	memory-controller@7ffd0000 {
	compatible = "arm,pl354", "arm,primecell";
	reg = <0 0x7ffd0000 0 0x1000>;
	interrupts = <0 86 4>,
	<0 87 4>;
	clocks = <&sys_pll>;
	clock-names = "apb_pclk";
	};

	dma@7ffb0000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0 0x7ffb0000 0 0x1000>;
	interrupts = <0 92 4>,
	<0 88 4>,
	<0 89 4>,
	<0 90 4>,
	<0 91 4>;
	clocks = <&sys_pll>;
	clock-names = "apb_pclk";
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <1 13 0xf08>,
	<1 14 0xf08>,
	<1 11 0xf08>,
	<1 10 0xf08>;
	};

	pmu {
	compatible = "arm,cortex-a15-pmu";
	interrupts = <0 68 4>,
	<0 69 4>;
	};

	dcc {
	compatible = "arm,vexpress,config-bus";
	arm,vexpress,config-bridge = <&v2m_sysreg>;

	oscclk0 {
	/* CPU PLL reference clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 0>;
	freq-range = <50000000 60000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk0";
	};

	oscclk4 {
	/* Multiplexed AXI master clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 4>;
	freq-range = <20000000 40000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk4";
	};

	hdlcd_clk: oscclk5 {
	/* HDLCD PLL reference clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 5>;
	freq-range = <23750000 165000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk5";
	};

	smbclk: oscclk6 {
	/* SMB clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 6>;
	freq-range = <20000000 50000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk6";
	};

	sys_pll: oscclk7 {
	/* SYS PLL reference clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 7>;
	freq-range = <20000000 60000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk7";
	};

	oscclk8 {
	/* DDR2 PLL reference clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 8>;
	freq-range = <40000000 40000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk8";
	};

	volt-cores {
	/* CPU core voltage */
	compatible = "arm,vexpress-volt";
	arm,vexpress-sysreg,func = <2 0>;
	regulator-name = "Cores";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1050000>;
	regulator-always-on;
	label = "Cores";
	};

	amp-cores {
	/* Total current for the two cores */
	compatible = "arm,vexpress-amp";
	arm,vexpress-sysreg,func = <3 0>;
	label = "Cores";
	};

	temp-dcc {
	/* DCC internal temperature */
	compatible = "arm,vexpress-temp";
	arm,vexpress-sysreg,func = <4 0>;
	label = "DCC";
	};

	power-cores {
	/* Total power */
	compatible = "arm,vexpress-power";
	arm,vexpress-sysreg,func = <12 0>;
	label = "Cores";
	};

	energy {
	/* Total energy */
	compatible = "arm,vexpress-energy";
	arm,vexpress-sysreg,func = <13 0>;
	label = "Cores";
	};
	};

	- smb@8000000 {
	+ bus@8000000 {
	compatible = "simple-bus";

	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0 0x08000000 0x04000000>,
	<1 0 0 0x14000000 0x04000000>,
	<2 0 0 0x18000000 0x04000000>,
	<3 0 0 0x1c000000 0x04000000>,
	<4 0 0 0x0c000000 0x04000000>,
	<5 0 0 0x10000000 0x04000000>;

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 63>;
	interrupt-map = <0 0 0 &gic 0 0 4>,
	<0 0 1 &gic 0 1 4>,
	<0 0 2 &gic 0 2 4>,
	<0 0 3 &gic 0 3 4>,
	<0 0 4 &gic 0 4 4>,
	<0 0 5 &gic 0 5 4>,
	<0 0 6 &gic 0 6 4>,
	<0 0 7 &gic 0 7 4>,
	<0 0 8 &gic 0 8 4>,
	<0 0 9 &gic 0 9 4>,
	<0 0 10 &gic 0 10 4>,
	<0 0 11 &gic 0 11 4>,
	<0 0 12 &gic 0 12 4>,
	<0 0 13 &gic 0 13 4>,
	<0 0 14 &gic 0 14 4>,
	<0 0 15 &gic 0 15 4>,
	<0 0 16 &gic 0 16 4>,
	<0 0 17 &gic 0 17 4>,
	<0 0 18 &gic 0 18 4>,
	<0 0 19 &gic 0 19 4>,
	<0 0 20 &gic 0 20 4>,
	<0 0 21 &gic 0 21 4>,
	<0 0 22 &gic 0 22 4>,
	<0 0 23 &gic 0 23 4>,
	<0 0 24 &gic 0 24 4>,
	<0 0 25 &gic 0 25 4>,
	<0 0 26 &gic 0 26 4>,
	<0 0 27 &gic 0 27 4>,
	<0 0 28 &gic 0 28 4>,
	<0 0 29 &gic 0 29 4>,
	<0 0 30 &gic 0 30 4>,
	<0 0 31 &gic 0 31 4>,
	<0 0 32 &gic 0 32 4>,
	<0 0 33 &gic 0 33 4>,
	<0 0 34 &gic 0 34 4>,
	<0 0 35 &gic 0 35 4>,
	<0 0 36 &gic 0 36 4>,
	<0 0 37 &gic 0 37 4>,
	<0 0 38 &gic 0 38 4>,
	<0 0 39 &gic 0 39 4>,
	<0 0 40 &gic 0 40 4>,
	<0 0 41 &gic 0 41 4>,
	<0 0 42 &gic 0 42 4>;
	};

	site2: hsb@40000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x40000000 0x3fef0000>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 3>;
	interrupt-map = <0 0 &gic 0 36 4>,
	<0 1 &gic 0 37 4>,
	<0 2 &gic 0 38 4>,
	<0 3 &gic 0 39 4>;
	};
	};
	diff --git a/sys/gnu/dts/arm/vexpress-v2p-ca15_a7.dts b/sys/gnu/dts/arm/vexpress-v2p-ca15_a7.dts
	index 1de0a658adf1..3ac95a179452 100644
	--- a/sys/gnu/dts/arm/vexpress-v2p-ca15_a7.dts
	+++ b/sys/gnu/dts/arm/vexpress-v2p-ca15_a7.dts
	@@ -1,691 +1,691 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* ARM Ltd. Versatile Express
	*
	* CoreTile Express A15x2 A7x3
	* Cortex-A15_A7 MPCore (V2P-CA15_A7)
	*
	* HBI-0249A
	*/

	/dts-v1/;
	#include "vexpress-v2m-rs1.dtsi"

	/ {
	model = "V2P-CA15_CA7";
	arm,hbi = <0x249>;
	arm,vexpress,site = <0xf>;
	compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	aliases {
	serial0 = &v2m_serial0;
	serial1 = &v2m_serial1;
	serial2 = &v2m_serial2;
	serial3 = &v2m_serial3;
	i2c0 = &v2m_i2c_dvi;
	i2c1 = &v2m_i2c_pcie;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <0>;
	cci-control-port = <&cci_control1>;
	cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
	capacity-dmips-mhz = <1024>;
	dynamic-power-coefficient = <990>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a15";
	reg = <1>;
	cci-control-port = <&cci_control1>;
	cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
	capacity-dmips-mhz = <1024>;
	dynamic-power-coefficient = <990>;
	};

	cpu2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x100>;
	cci-control-port = <&cci_control2>;
	cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
	capacity-dmips-mhz = <516>;
	dynamic-power-coefficient = <133>;
	};

	cpu3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x101>;
	cci-control-port = <&cci_control2>;
	cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
	capacity-dmips-mhz = <516>;
	dynamic-power-coefficient = <133>;
	};

	cpu4: cpu@4 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x102>;
	cci-control-port = <&cci_control2>;
	cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
	capacity-dmips-mhz = <516>;
	dynamic-power-coefficient = <133>;
	};

	idle-states {
	CLUSTER_SLEEP_BIG: cluster-sleep-big {
	compatible = "arm,idle-state";
	local-timer-stop;
	entry-latency-us = <1000>;
	exit-latency-us = <700>;
	min-residency-us = <2000>;
	};

	CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
	compatible = "arm,idle-state";
	local-timer-stop;
	entry-latency-us = <1000>;
	exit-latency-us = <500>;
	min-residency-us = <2500>;
	};
	};
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0 0x80000000 0 0x40000000>;
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	/* Chipselect 2 is physically at 0x18000000 */
	vram: vram@18000000 {
	/* 8 MB of designated video RAM */
	compatible = "shared-dma-pool";
	reg = <0 0x18000000 0 0x00800000>;
	no-map;
	};
	};

	wdt@2a490000 {
	compatible = "arm,sp805", "arm,primecell";
	reg = <0 0x2a490000 0 0x1000>;
	interrupts = <0 98 4>;
	clocks = <&oscclk6a>, <&oscclk6a>;
	clock-names = "wdogclk", "apb_pclk";
	};

	hdlcd@2b000000 {
	compatible = "arm,hdlcd";
	reg = <0 0x2b000000 0 0x1000>;
	interrupts = <0 85 4>;
	clocks = <&hdlcd_clk>;
	clock-names = "pxlclk";
	};

	memory-controller@2b0a0000 {
	compatible = "arm,pl341", "arm,primecell";
	reg = <0 0x2b0a0000 0 0x1000>;
	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";
	};

	gic: interrupt-controller@2c001000 {
	compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0 0x2c001000 0 0x1000>,
	<0 0x2c002000 0 0x2000>,
	<0 0x2c004000 0 0x2000>,
	<0 0x2c006000 0 0x2000>;
	interrupts = <1 9 0xf04>;
	};

	cci@2c090000 {
	compatible = "arm,cci-400";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0 0x2c090000 0 0x1000>;
	ranges = <0x0 0x0 0x2c090000 0x10000>;

	cci_control1: slave-if@4000 {
	compatible = "arm,cci-400-ctrl-if";
	interface-type = "ace";
	reg = <0x4000 0x1000>;
	};

	cci_control2: slave-if@5000 {
	compatible = "arm,cci-400-ctrl-if";
	interface-type = "ace";
	reg = <0x5000 0x1000>;
	};

	pmu@9000 {
	compatible = "arm,cci-400-pmu,r0";
	reg = <0x9000 0x5000>;
	interrupts = <0 105 4>,
	<0 101 4>,
	<0 102 4>,
	<0 103 4>,
	<0 104 4>;
	};
	};

	memory-controller@7ffd0000 {
	compatible = "arm,pl354", "arm,primecell";
	reg = <0 0x7ffd0000 0 0x1000>;
	interrupts = <0 86 4>,
	<0 87 4>;
	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";
	};

	dma@7ff00000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0 0x7ff00000 0 0x1000>;
	interrupts = <0 92 4>,
	<0 88 4>,
	<0 89 4>,
	<0 90 4>,
	<0 91 4>;
	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";
	};

	scc@7fff0000 {
	compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
	reg = <0 0x7fff0000 0 0x1000>;
	interrupts = <0 95 4>;
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <1 13 0xf08>,
	<1 14 0xf08>,
	<1 11 0xf08>,
	<1 10 0xf08>;
	};

	pmu-a15 {
	compatible = "arm,cortex-a15-pmu";
	interrupts = <0 68 4>,
	<0 69 4>;
	interrupt-affinity = <&cpu0>,
	<&cpu1>;
	};

	pmu-a7 {
	compatible = "arm,cortex-a7-pmu";
	interrupts = <0 128 4>,
	<0 129 4>,
	<0 130 4>;
	interrupt-affinity = <&cpu2>,
	<&cpu3>,
	<&cpu4>;
	};

	oscclk6a: oscclk6a {
	/* Reference 24MHz clock */
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "oscclk6a";
	};

	dcc {
	compatible = "arm,vexpress,config-bus";
	arm,vexpress,config-bridge = <&v2m_sysreg>;

	oscclk0 {
	/* A15 PLL 0 reference clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 0>;
	freq-range = <17000000 50000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk0";
	};

	oscclk1 {
	/* A15 PLL 1 reference clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 1>;
	freq-range = <17000000 50000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk1";
	};

	oscclk2 {
	/* A7 PLL 0 reference clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 2>;
	freq-range = <17000000 50000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk2";
	};

	oscclk3 {
	/* A7 PLL 1 reference clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 3>;
	freq-range = <17000000 50000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk3";
	};

	oscclk4 {
	/* External AXI master clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 4>;
	freq-range = <20000000 40000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk4";
	};

	hdlcd_clk: oscclk5 {
	/* HDLCD PLL reference clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 5>;
	freq-range = <23750000 165000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk5";
	};

	smbclk: oscclk6 {
	/* Static memory controller clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 6>;
	freq-range = <20000000 40000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk6";
	};

	oscclk7 {
	/* SYS PLL reference clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 7>;
	freq-range = <17000000 50000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk7";
	};

	oscclk8 {
	/* DDR2 PLL reference clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 8>;
	freq-range = <20000000 50000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk8";
	};

	volt-a15 {
	/* A15 CPU core voltage */
	compatible = "arm,vexpress-volt";
	arm,vexpress-sysreg,func = <2 0>;
	regulator-name = "A15 Vcore";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1050000>;
	regulator-always-on;
	label = "A15 Vcore";
	};

	volt-a7 {
	/* A7 CPU core voltage */
	compatible = "arm,vexpress-volt";
	arm,vexpress-sysreg,func = <2 1>;
	regulator-name = "A7 Vcore";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1050000>;
	regulator-always-on;
	label = "A7 Vcore";
	};

	amp-a15 {
	/* Total current for the two A15 cores */
	compatible = "arm,vexpress-amp";
	arm,vexpress-sysreg,func = <3 0>;
	label = "A15 Icore";
	};

	amp-a7 {
	/* Total current for the three A7 cores */
	compatible = "arm,vexpress-amp";
	arm,vexpress-sysreg,func = <3 1>;
	label = "A7 Icore";
	};

	temp-dcc {
	/* DCC internal temperature */
	compatible = "arm,vexpress-temp";
	arm,vexpress-sysreg,func = <4 0>;
	label = "DCC";
	};

	power-a15 {
	/* Total power for the two A15 cores */
	compatible = "arm,vexpress-power";
	arm,vexpress-sysreg,func = <12 0>;
	label = "A15 Pcore";
	};

	power-a7 {
	/* Total power for the three A7 cores */
	compatible = "arm,vexpress-power";
	arm,vexpress-sysreg,func = <12 1>;
	label = "A7 Pcore";
	};

	energy-a15 {
	/* Total energy for the two A15 cores */
	compatible = "arm,vexpress-energy";
	arm,vexpress-sysreg,func = <13 0>, <13 1>;
	label = "A15 Jcore";
	};

	energy-a7 {
	/* Total energy for the three A7 cores */
	compatible = "arm,vexpress-energy";
	arm,vexpress-sysreg,func = <13 2>, <13 3>;
	label = "A7 Jcore";
	};
	};

	etb@20010000 {
	compatible = "arm,coresight-etb10", "arm,primecell";
	reg = <0 0x20010000 0 0x1000>;

	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";
	in-ports {
	port {
	etb_in_port: endpoint {
	remote-endpoint = <&replicator_out_port0>;
	};
	};
	};
	};

	tpiu@20030000 {
	compatible = "arm,coresight-tpiu", "arm,primecell";
	reg = <0 0x20030000 0 0x1000>;

	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";
	in-ports {
	port {
	tpiu_in_port: endpoint {
	remote-endpoint = <&replicator_out_port1>;
	};
	};
	};
	};

	replicator {
	/* non-configurable replicators don't show up on the
	* AMBA bus. As such no need to add "arm,primecell".
	*/
	compatible = "arm,coresight-static-replicator";

	out-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	replicator_out_port0: endpoint {
	remote-endpoint = <&etb_in_port>;
	};
	};

	port@1 {
	reg = <1>;
	replicator_out_port1: endpoint {
	remote-endpoint = <&tpiu_in_port>;
	};
	};
	};

	in-ports {
	port {
	replicator_in_port0: endpoint {
	remote-endpoint = <&funnel_out_port0>;
	};
	};
	};
	};

	funnel@20040000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0 0x20040000 0 0x1000>;

	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";
	out-ports {
	port {
	funnel_out_port0: endpoint {
	remote-endpoint =
	<&replicator_in_port0>;
	};
	};
	};

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	funnel_in_port0: endpoint {
	remote-endpoint = <&ptm0_out_port>;
	};
	};

	port@1 {
	reg = <1>;
	funnel_in_port1: endpoint {
	remote-endpoint = <&ptm1_out_port>;
	};
	};

	port@2 {
	reg = <2>;
	funnel_in_port2: endpoint {
	remote-endpoint = <&etm0_out_port>;
	};
	};

	/* Input port #3 is for ITM, not supported here */

	port@4 {
	reg = <4>;
	funnel_in_port4: endpoint {
	remote-endpoint = <&etm1_out_port>;
	};
	};

	port@5 {
	reg = <5>;
	funnel_in_port5: endpoint {
	remote-endpoint = <&etm2_out_port>;
	};
	};
	};
	};

	ptm@2201c000 {
	compatible = "arm,coresight-etm3x", "arm,primecell";
	reg = <0 0x2201c000 0 0x1000>;

	cpu = <&cpu0>;
	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";
	out-ports {
	port {
	ptm0_out_port: endpoint {
	remote-endpoint = <&funnel_in_port0>;
	};
	};
	};
	};

	ptm@2201d000 {
	compatible = "arm,coresight-etm3x", "arm,primecell";
	reg = <0 0x2201d000 0 0x1000>;

	cpu = <&cpu1>;
	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";
	out-ports {
	port {
	ptm1_out_port: endpoint {
	remote-endpoint = <&funnel_in_port1>;
	};
	};
	};
	};

	etm@2203c000 {
	compatible = "arm,coresight-etm3x", "arm,primecell";
	reg = <0 0x2203c000 0 0x1000>;

	cpu = <&cpu2>;
	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";
	out-ports {
	port {
	etm0_out_port: endpoint {
	remote-endpoint = <&funnel_in_port2>;
	};
	};
	};
	};

	etm@2203d000 {
	compatible = "arm,coresight-etm3x", "arm,primecell";
	reg = <0 0x2203d000 0 0x1000>;

	cpu = <&cpu3>;
	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";
	out-ports {
	port {
	etm1_out_port: endpoint {
	remote-endpoint = <&funnel_in_port4>;
	};
	};
	};
	};

	etm@2203e000 {
	compatible = "arm,coresight-etm3x", "arm,primecell";
	reg = <0 0x2203e000 0 0x1000>;

	cpu = <&cpu4>;
	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";
	out-ports {
	port {
	etm2_out_port: endpoint {
	remote-endpoint = <&funnel_in_port5>;
	};
	};
	};
	};

	- smb: smb@8000000 {
	+ smb: bus@8000000 {
	compatible = "simple-bus";

	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0 0x08000000 0x04000000>,
	<1 0 0 0x14000000 0x04000000>,
	<2 0 0 0x18000000 0x04000000>,
	<3 0 0 0x1c000000 0x04000000>,
	<4 0 0 0x0c000000 0x04000000>,
	<5 0 0 0x10000000 0x04000000>;

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 63>;
	interrupt-map = <0 0 0 &gic 0 0 4>,
	<0 0 1 &gic 0 1 4>,
	<0 0 2 &gic 0 2 4>,
	<0 0 3 &gic 0 3 4>,
	<0 0 4 &gic 0 4 4>,
	<0 0 5 &gic 0 5 4>,
	<0 0 6 &gic 0 6 4>,
	<0 0 7 &gic 0 7 4>,
	<0 0 8 &gic 0 8 4>,
	<0 0 9 &gic 0 9 4>,
	<0 0 10 &gic 0 10 4>,
	<0 0 11 &gic 0 11 4>,
	<0 0 12 &gic 0 12 4>,
	<0 0 13 &gic 0 13 4>,
	<0 0 14 &gic 0 14 4>,
	<0 0 15 &gic 0 15 4>,
	<0 0 16 &gic 0 16 4>,
	<0 0 17 &gic 0 17 4>,
	<0 0 18 &gic 0 18 4>,
	<0 0 19 &gic 0 19 4>,
	<0 0 20 &gic 0 20 4>,
	<0 0 21 &gic 0 21 4>,
	<0 0 22 &gic 0 22 4>,
	<0 0 23 &gic 0 23 4>,
	<0 0 24 &gic 0 24 4>,
	<0 0 25 &gic 0 25 4>,
	<0 0 26 &gic 0 26 4>,
	<0 0 27 &gic 0 27 4>,
	<0 0 28 &gic 0 28 4>,
	<0 0 29 &gic 0 29 4>,
	<0 0 30 &gic 0 30 4>,
	<0 0 31 &gic 0 31 4>,
	<0 0 32 &gic 0 32 4>,
	<0 0 33 &gic 0 33 4>,
	<0 0 34 &gic 0 34 4>,
	<0 0 35 &gic 0 35 4>,
	<0 0 36 &gic 0 36 4>,
	<0 0 37 &gic 0 37 4>,
	<0 0 38 &gic 0 38 4>,
	<0 0 39 &gic 0 39 4>,
	<0 0 40 &gic 0 40 4>,
	<0 0 41 &gic 0 41 4>,
	<0 0 42 &gic 0 42 4>;
	};

	site2: hsb@40000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x40000000 0x3fef0000>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 3>;
	interrupt-map = <0 0 &gic 0 36 4>,
	<0 1 &gic 0 37 4>,
	<0 2 &gic 0 38 4>,
	<0 3 &gic 0 39 4>;
	};
	};

	&nor_flash {
	/*
	* Unfortunately, accessing the flash disturbs the CPU idle states
	* (suspend) and CPU hotplug of this platform. For this reason, flash
	* hardware access is disabled by default on this platform alone.
	*/
	status = "disabled";
	};
	diff --git a/sys/gnu/dts/arm/vexpress-v2p-ca5s.dts b/sys/gnu/dts/arm/vexpress-v2p-ca5s.dts
	index d5b47d526f9e..7aa64ae25779 100644
	--- a/sys/gnu/dts/arm/vexpress-v2p-ca5s.dts
	+++ b/sys/gnu/dts/arm/vexpress-v2p-ca5s.dts
	@@ -1,280 +1,280 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* ARM Ltd. Versatile Express
	*
	* CoreTile Express A5x2
	* Cortex-A5 MPCore (V2P-CA5s)
	*
	* HBI-0225B
	*/

	/dts-v1/;
	#include "vexpress-v2m-rs1.dtsi"

	/ {
	model = "V2P-CA5s";
	arm,hbi = <0x225>;
	arm,vexpress,site = <0xf>;
	compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	chosen { };

	aliases {
	serial0 = &v2m_serial0;
	serial1 = &v2m_serial1;
	serial2 = &v2m_serial2;
	serial3 = &v2m_serial3;
	i2c0 = &v2m_i2c_dvi;
	i2c1 = &v2m_i2c_pcie;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a5";
	reg = <0>;
	next-level-cache = <&L2>;
	};

	cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a5";
	reg = <1>;
	next-level-cache = <&L2>;
	};
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x40000000>;
	};

	reserved-memory {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	/* Chipselect 2 is physically at 0x18000000 */
	vram: vram@18000000 {
	/* 8 MB of designated video RAM */
	compatible = "shared-dma-pool";
	reg = <0x18000000 0x00800000>;
	no-map;
	};
	};

	hdlcd@2a110000 {
	compatible = "arm,hdlcd";
	reg = <0x2a110000 0x1000>;
	interrupts = <0 85 4>;
	clocks = <&hdlcd_clk>;
	clock-names = "pxlclk";
	};

	memory-controller@2a150000 {
	compatible = "arm,pl341", "arm,primecell";
	reg = <0x2a150000 0x1000>;
	clocks = <&axi_clk>;
	clock-names = "apb_pclk";
	};

	memory-controller@2a190000 {
	compatible = "arm,pl354", "arm,primecell";
	reg = <0x2a190000 0x1000>;
	interrupts = <0 86 4>,
	<0 87 4>;
	clocks = <&axi_clk>;
	clock-names = "apb_pclk";
	};

	scu@2c000000 {
	compatible = "arm,cortex-a5-scu";
	reg = <0x2c000000 0x58>;
	};

	timer@2c000600 {
	compatible = "arm,cortex-a5-twd-timer";
	reg = <0x2c000600 0x20>;
	interrupts = <1 13 0x304>;
	};

	timer@2c000200 {
	compatible = "arm,cortex-a5-global-timer",
	"arm,cortex-a9-global-timer";
	reg = <0x2c000200 0x20>;
	interrupts = <1 11 0x304>;
	clocks = <&cpu_clk>;
	};

	watchdog@2c000620 {
	compatible = "arm,cortex-a5-twd-wdt";
	reg = <0x2c000620 0x20>;
	interrupts = <1 14 0x304>;
	};

	gic: interrupt-controller@2c001000 {
	compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x2c001000 0x1000>,
	<0x2c000100 0x100>;
	};

	L2: cache-controller@2c0f0000 {
	compatible = "arm,pl310-cache";
	reg = <0x2c0f0000 0x1000>;
	interrupts = <0 84 4>;
	cache-level = <2>;
	};

	pmu {
	compatible = "arm,cortex-a5-pmu";
	interrupts = <0 68 4>,
	<0 69 4>;
	};

	dcc {
	compatible = "arm,vexpress,config-bus";
	arm,vexpress,config-bridge = <&v2m_sysreg>;

	cpu_clk: oscclk0 {
	/* CPU and internal AXI reference clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 0>;
	freq-range = <50000000 100000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk0";
	};

	axi_clk: oscclk1 {
	/* Multiplexed AXI master clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 1>;
	freq-range = <5000000 50000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk1";
	};

	oscclk2 {
	/* DDR2 */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 2>;
	freq-range = <80000000 120000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk2";
	};

	hdlcd_clk: oscclk3 {
	/* HDLCD */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 3>;
	freq-range = <23750000 165000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk3";
	};

	oscclk4 {
	/* Test chip gate configuration */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 4>;
	freq-range = <80000000 80000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk4";
	};

	smbclk: oscclk5 {
	/* SMB clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 5>;
	freq-range = <25000000 60000000>;
	#clock-cells = <0>;
	clock-output-names = "oscclk5";
	};

	temp-dcc {
	/* DCC internal operating temperature */
	compatible = "arm,vexpress-temp";
	arm,vexpress-sysreg,func = <4 0>;
	label = "DCC";
	};
	};

	- smb: smb@8000000 {
	+ smb: bus@8000000 {
	compatible = "simple-bus";

	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0x08000000 0x04000000>,
	<1 0 0x14000000 0x04000000>,
	<2 0 0x18000000 0x04000000>,
	<3 0 0x1c000000 0x04000000>,
	<4 0 0x0c000000 0x04000000>,
	<5 0 0x10000000 0x04000000>;

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 63>;
	interrupt-map = <0 0 0 &gic 0 0 4>,
	<0 0 1 &gic 0 1 4>,
	<0 0 2 &gic 0 2 4>,
	<0 0 3 &gic 0 3 4>,
	<0 0 4 &gic 0 4 4>,
	<0 0 5 &gic 0 5 4>,
	<0 0 6 &gic 0 6 4>,
	<0 0 7 &gic 0 7 4>,
	<0 0 8 &gic 0 8 4>,
	<0 0 9 &gic 0 9 4>,
	<0 0 10 &gic 0 10 4>,
	<0 0 11 &gic 0 11 4>,
	<0 0 12 &gic 0 12 4>,
	<0 0 13 &gic 0 13 4>,
	<0 0 14 &gic 0 14 4>,
	<0 0 15 &gic 0 15 4>,
	<0 0 16 &gic 0 16 4>,
	<0 0 17 &gic 0 17 4>,
	<0 0 18 &gic 0 18 4>,
	<0 0 19 &gic 0 19 4>,
	<0 0 20 &gic 0 20 4>,
	<0 0 21 &gic 0 21 4>,
	<0 0 22 &gic 0 22 4>,
	<0 0 23 &gic 0 23 4>,
	<0 0 24 &gic 0 24 4>,
	<0 0 25 &gic 0 25 4>,
	<0 0 26 &gic 0 26 4>,
	<0 0 27 &gic 0 27 4>,
	<0 0 28 &gic 0 28 4>,
	<0 0 29 &gic 0 29 4>,
	<0 0 30 &gic 0 30 4>,
	<0 0 31 &gic 0 31 4>,
	<0 0 32 &gic 0 32 4>,
	<0 0 33 &gic 0 33 4>,
	<0 0 34 &gic 0 34 4>,
	<0 0 35 &gic 0 35 4>,
	<0 0 36 &gic 0 36 4>,
	<0 0 37 &gic 0 37 4>,
	<0 0 38 &gic 0 38 4>,
	<0 0 39 &gic 0 39 4>,
	<0 0 40 &gic 0 40 4>,
	<0 0 41 &gic 0 41 4>,
	<0 0 42 &gic 0 42 4>;
	};

	site2: hsb@40000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x40000000 0x40000000>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 3>;
	interrupt-map = <0 0 &gic 0 36 4>,
	<0 1 &gic 0 37 4>,
	<0 2 &gic 0 38 4>,
	<0 3 &gic 0 39 4>;
	};
	};
	diff --git a/sys/gnu/dts/arm/vexpress-v2p-ca9.dts b/sys/gnu/dts/arm/vexpress-v2p-ca9.dts
	index d796efaadbe3..623246f37448 100644
	--- a/sys/gnu/dts/arm/vexpress-v2p-ca9.dts
	+++ b/sys/gnu/dts/arm/vexpress-v2p-ca9.dts
	@@ -1,368 +1,368 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* ARM Ltd. Versatile Express
	*
	* CoreTile Express A9x4
	* Cortex-A9 MPCore (V2P-CA9)
	*
	* HBI-0191B
	*/

	/dts-v1/;
	#include "vexpress-v2m.dtsi"

	/ {
	model = "V2P-CA9";
	arm,hbi = <0x191>;
	arm,vexpress,site = <0xf>;
	compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	chosen { };

	aliases {
	serial0 = &v2m_serial0;
	serial1 = &v2m_serial1;
	serial2 = &v2m_serial2;
	serial3 = &v2m_serial3;
	i2c0 = &v2m_i2c_dvi;
	i2c1 = &v2m_i2c_pcie;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	A9_0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <0>;
	next-level-cache = <&L2>;
	};

	A9_1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <1>;
	next-level-cache = <&L2>;
	};

	A9_2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <2>;
	next-level-cache = <&L2>;
	};

	A9_3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	reg = <3>;
	next-level-cache = <&L2>;
	};
	};

	memory@60000000 {
	device_type = "memory";
	reg = <0x60000000 0x40000000>;
	};

	reserved-memory {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	/* Chipselect 3 is physically at 0x4c000000 */
	vram: vram@4c000000 {
	/* 8 MB of designated video RAM */
	compatible = "shared-dma-pool";
	reg = <0x4c000000 0x00800000>;
	no-map;
	};
	};

	clcd@10020000 {
	compatible = "arm,pl111", "arm,primecell";
	reg = <0x10020000 0x1000>;
	interrupt-names = "combined";
	interrupts = <0 44 4>;
	clocks = <&oscclk1>, <&oscclk2>;
	clock-names = "clcdclk", "apb_pclk";
	/* 1024x768 16bpp @65MHz */
	max-memory-bandwidth = <95000000>;

	port {
	clcd_pads_ct: endpoint {
	remote-endpoint = <&dvi_bridge_in_ct>;
	arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
	};
	};
	};

	memory-controller@100e0000 {
	compatible = "arm,pl341", "arm,primecell";
	reg = <0x100e0000 0x1000>;
	clocks = <&oscclk2>;
	clock-names = "apb_pclk";
	};

	memory-controller@100e1000 {
	compatible = "arm,pl354", "arm,primecell";
	reg = <0x100e1000 0x1000>;
	interrupts = <0 45 4>,
	<0 46 4>;
	clocks = <&oscclk2>;
	clock-names = "apb_pclk";
	};

	timer@100e4000 {
	compatible = "arm,sp804", "arm,primecell";
	reg = <0x100e4000 0x1000>;
	interrupts = <0 48 4>,
	<0 49 4>;
	clocks = <&oscclk2>, <&oscclk2>;
	clock-names = "timclk", "apb_pclk";
	status = "disabled";
	};

	watchdog@100e5000 {
	compatible = "arm,sp805", "arm,primecell";
	reg = <0x100e5000 0x1000>;
	interrupts = <0 51 4>;
	clocks = <&oscclk2>, <&oscclk2>;
	clock-names = "wdogclk", "apb_pclk";
	};

	scu@1e000000 {
	compatible = "arm,cortex-a9-scu";
	reg = <0x1e000000 0x58>;
	};

	timer@1e000600 {
	compatible = "arm,cortex-a9-twd-timer";
	reg = <0x1e000600 0x20>;
	interrupts = <1 13 0xf04>;
	};

	watchdog@1e000620 {
	compatible = "arm,cortex-a9-twd-wdt";
	reg = <0x1e000620 0x20>;
	interrupts = <1 14 0xf04>;
	};

	gic: interrupt-controller@1e001000 {
	compatible = "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x1e001000 0x1000>,
	<0x1e000100 0x100>;
	};

	L2: cache-controller@1e00a000 {
	compatible = "arm,pl310-cache";
	reg = <0x1e00a000 0x1000>;
	interrupts = <0 43 4>;
	cache-unified;
	cache-level = <2>;
	arm,data-latency = <1 1 1>;
	arm,tag-latency = <1 1 1>;
	};

	pmu {
	compatible = "arm,cortex-a9-pmu";
	interrupts = <0 60 4>,
	<0 61 4>,
	<0 62 4>,
	<0 63 4>;
	interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;

	};

	dcc {
	compatible = "arm,vexpress,config-bus";
	arm,vexpress,config-bridge = <&v2m_sysreg>;

	oscclk0: extsaxiclk {
	/* ACLK clock to the AXI master port on the test chip */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 0>;
	freq-range = <30000000 50000000>;
	#clock-cells = <0>;
	clock-output-names = "extsaxiclk";
	};

	oscclk1: clcdclk {
	/* Reference clock for the CLCD */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 1>;
	freq-range = <10000000 80000000>;
	#clock-cells = <0>;
	clock-output-names = "clcdclk";
	};

	smbclk: oscclk2: tcrefclk {
	/* Reference clock for the test chip internal PLLs */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 2>;
	freq-range = <33000000 100000000>;
	#clock-cells = <0>;
	clock-output-names = "tcrefclk";
	};

	volt-vd10 {
	/* Test Chip internal logic voltage */
	compatible = "arm,vexpress-volt";
	arm,vexpress-sysreg,func = <2 0>;
	regulator-name = "VD10";
	regulator-always-on;
	label = "VD10";
	};

	volt-vd10-s2 {
	/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
	compatible = "arm,vexpress-volt";
	arm,vexpress-sysreg,func = <2 1>;
	regulator-name = "VD10_S2";
	regulator-always-on;
	label = "VD10_S2";
	};

	volt-vd10-s3 {
	/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
	compatible = "arm,vexpress-volt";
	arm,vexpress-sysreg,func = <2 2>;
	regulator-name = "VD10_S3";
	regulator-always-on;
	label = "VD10_S3";
	};

	volt-vcc1v8 {
	/* DDR2 SDRAM and Test Chip DDR2 I/O supply */
	compatible = "arm,vexpress-volt";
	arm,vexpress-sysreg,func = <2 3>;
	regulator-name = "VCC1V8";
	regulator-always-on;
	label = "VCC1V8";
	};

	volt-ddr2vtt {
	/* DDR2 SDRAM VTT termination voltage */
	compatible = "arm,vexpress-volt";
	arm,vexpress-sysreg,func = <2 4>;
	regulator-name = "DDR2VTT";
	regulator-always-on;
	label = "DDR2VTT";
	};

	volt-vcc3v3 {
	/* Local board supply for miscellaneous logic external to the Test Chip */
	arm,vexpress-sysreg,func = <2 5>;
	compatible = "arm,vexpress-volt";
	regulator-name = "VCC3V3";
	regulator-always-on;
	label = "VCC3V3";
	};

	amp-vd10-s2 {
	/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
	compatible = "arm,vexpress-amp";
	arm,vexpress-sysreg,func = <3 0>;
	label = "VD10_S2";
	};

	amp-vd10-s3 {
	/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
	compatible = "arm,vexpress-amp";
	arm,vexpress-sysreg,func = <3 1>;
	label = "VD10_S3";
	};

	power-vd10-s2 {
	/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
	compatible = "arm,vexpress-power";
	arm,vexpress-sysreg,func = <12 0>;
	label = "PVD10_S2";
	};

	power-vd10-s3 {
	/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
	compatible = "arm,vexpress-power";
	arm,vexpress-sysreg,func = <12 1>;
	label = "PVD10_S3";
	};
	};

	- smb: smb@4000000 {
	+ smb: bus@4000000 {
	compatible = "simple-bus";

	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0x40000000 0x04000000>,
	<1 0 0x44000000 0x04000000>,
	<2 0 0x48000000 0x04000000>,
	<3 0 0x4c000000 0x04000000>,
	<7 0 0x10000000 0x00020000>;

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 63>;
	interrupt-map = <0 0 0 &gic 0 0 4>,
	<0 0 1 &gic 0 1 4>,
	<0 0 2 &gic 0 2 4>,
	<0 0 3 &gic 0 3 4>,
	<0 0 4 &gic 0 4 4>,
	<0 0 5 &gic 0 5 4>,
	<0 0 6 &gic 0 6 4>,
	<0 0 7 &gic 0 7 4>,
	<0 0 8 &gic 0 8 4>,
	<0 0 9 &gic 0 9 4>,
	<0 0 10 &gic 0 10 4>,
	<0 0 11 &gic 0 11 4>,
	<0 0 12 &gic 0 12 4>,
	<0 0 13 &gic 0 13 4>,
	<0 0 14 &gic 0 14 4>,
	<0 0 15 &gic 0 15 4>,
	<0 0 16 &gic 0 16 4>,
	<0 0 17 &gic 0 17 4>,
	<0 0 18 &gic 0 18 4>,
	<0 0 19 &gic 0 19 4>,
	<0 0 20 &gic 0 20 4>,
	<0 0 21 &gic 0 21 4>,
	<0 0 22 &gic 0 22 4>,
	<0 0 23 &gic 0 23 4>,
	<0 0 24 &gic 0 24 4>,
	<0 0 25 &gic 0 25 4>,
	<0 0 26 &gic 0 26 4>,
	<0 0 27 &gic 0 27 4>,
	<0 0 28 &gic 0 28 4>,
	<0 0 29 &gic 0 29 4>,
	<0 0 30 &gic 0 30 4>,
	<0 0 31 &gic 0 31 4>,
	<0 0 32 &gic 0 32 4>,
	<0 0 33 &gic 0 33 4>,
	<0 0 34 &gic 0 34 4>,
	<0 0 35 &gic 0 35 4>,
	<0 0 36 &gic 0 36 4>,
	<0 0 37 &gic 0 37 4>,
	<0 0 38 &gic 0 38 4>,
	<0 0 39 &gic 0 39 4>,
	<0 0 40 &gic 0 40 4>,
	<0 0 41 &gic 0 41 4>,
	<0 0 42 &gic 0 42 4>;
	};

	site2: hsb@e0000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0xe0000000 0x20000000>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 3>;
	interrupt-map = <0 0 &gic 0 36 4>,
	<0 1 &gic 0 37 4>,
	<0 2 &gic 0 38 4>,
	<0 3 &gic 0 39 4>;
	};
	};
	diff --git a/sys/gnu/dts/arm/vf-colibri-eval-v3.dtsi b/sys/gnu/dts/arm/vf-colibri-eval-v3.dtsi
	index e2da122a63f4..c12a1b8bc086 100644
	--- a/sys/gnu/dts/arm/vf-colibri-eval-v3.dtsi
	+++ b/sys/gnu/dts/arm/vf-colibri-eval-v3.dtsi
	@@ -1,188 +1,152 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2014 Toradex AG
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License
	- * version 2 as published by the Free Software Foundation.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	+ * Copyright 2014-2020 Toradex
	*/

	/ {
	chosen {
	stdout-path = "serial0:115200n8";
	};

	clk16m: clk16m {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <16000000>;
	};

	panel: panel {
	compatible = "edt,et057090dhu";
	backlight = <&bl>;

	port {
	panel_in: endpoint {
	remote-endpoint = <&dcu_out>;
	};
	};
	};

	reg_3v3: regulator-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	reg_5v0: regulator-5v0 {
	compatible = "regulator-fixed";
	regulator-name = "5V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	};

	reg_usbh_vbus: regulator-usbh-vbus {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbh1_reg>;
	regulator-name = "VCC_USB[1-4]";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; /* USBH_PEN resp. USBH_P_EN */
	vin-supply = <&reg_5v0>;
	};
	};

	&bl {
	brightness-levels = <0 4 8 16 32 64 128 255>;
	default-brightness-level = <6>;
	power-supply = <&reg_3v3>;
	status = "okay";
	};

	&dcu0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dcu0_1>;
	status = "okay";

	port {
	dcu_out: endpoint {
	remote-endpoint = <&panel_in>;
	};
	};
	};

	&dspi1 {
	status = "okay";

	mcp2515can: can@0 {
	compatible = "microchip,mcp2515";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can_int>;
	reg = <0>;
	clocks = <&clk16m>;
	spi-max-frequency = <10000000>;
	interrupt-parent = <&gpio1>;
	interrupts = <11 IRQ_TYPE_EDGE_RISING>;
	};
	};

	&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	status = "okay";
	};

	&fec1 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";
	};

	&i2c0 {
	status = "okay";

	/* M41T0M6 real time clock on carrier board */
	rtc: m41t0m6@68 {
	compatible = "st,m41t0";
	reg = <0x68>;
	};
	};

	&pwm0 {
	status = "okay";
	};

	&pwm1 {
	status = "okay";
	};

	&reg_module_3v3 {
	vin-supply = <&reg_3v3>;
	};

	&tcon0 {
	status = "okay";
	};

	&uart0 {
	status = "okay";
	};

	&uart1 {
	status = "okay";
	};

	&uart2 {
	status = "okay";
	};

	&usbh1 {
	vbus-supply = <&reg_usbh_vbus>;
	};

	&iomuxc {
	vf610-colibri {
	pinctrl_can_int: can_int {
	fsl,pins = <
	VF610_PAD_PTB21__GPIO_43 0x22ed
	>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/vf-colibri.dtsi b/sys/gnu/dts/arm/vf-colibri.dtsi
	index fba37b8756f7..cc1e069c44e6 100644
	--- a/sys/gnu/dts/arm/vf-colibri.dtsi
	+++ b/sys/gnu/dts/arm/vf-colibri.dtsi
	@@ -1,385 +1,350 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2014 Toradex AG
	+ * Copyright 2014-2020 Toradex
	*
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License
	- * version 2 as published by the Free Software Foundation.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	*/

	/ {
	aliases {
	ethernet0 = &fec1;
	ethernet1 = &fec0;
	};

	bl: backlight {
	compatible = "pwm-backlight";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_bl_on>;
	pwms = <&pwm0 0 5000000 0>;
	enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
	status = "disabled";
	};

	reg_module_3v3: regulator-module-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	reg_module_3v3_avdd: regulator-module-3v3-avdd {
	compatible = "regulator-fixed";
	regulator-name = "+V3.3_AVDD_AUDIO";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};
	};

	&adc0 {
	status = "okay";
	vref-supply = <&reg_module_3v3_avdd>;
	};

	&adc1 {
	status = "okay";
	vref-supply = <&reg_module_3v3_avdd>;
	};

	&can0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan0>;
	status = "disabled";
	};

	&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "disabled";
	};

	&clks {
	assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
	<&clks VF610_CLK_ENET_TS_SEL>;
	assigned-clock-parents = <&clks VF610_CLK_ENET_50M>,
	<&clks VF610_CLK_ENET_50M>;
	};

	&dspi1 {
	bus-num = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dspi1>;
	};

	&edma0 {
	status = "okay";
	};

	&edma1 {
	status = "okay";
	};

	&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
	disable-wp;
	};

	&fec1 {
	phy-mode = "rmii";
	phy-supply = <&reg_module_3v3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	};

	&i2c0 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c0>;
	pinctrl-1 = <&pinctrl_i2c0_gpio>;
	scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	};

	&nfc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nfc>;
	status = "okay";

	nand@0 {
	compatible = "fsl,vf610-nfc-nandcs";
	reg = <0>;
	#address-cells = <1>;
	#size-cells = <1>;
	nand-bus-width = <8>;
	nand-ecc-mode = "hw";
	nand-ecc-strength = <32>;
	nand-ecc-step-size = <2048>;
	nand-on-flash-bbt;
	};
	};

	&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm0>;
	};

	&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	};

	&usbdev0 {
	disable-over-current;
	status = "okay";
	};

	&usbh1 {
	disable-over-current;
	status = "okay";
	};

	&usbmisc0 {
	status = "okay";
	};

	&usbmisc1 {
	status = "okay";
	};

	&usbphy0 {
	status = "okay";
	};

	&usbphy1 {
	status = "okay";
	};

	&iomuxc {
	vf610-colibri {
	pinctrl_flexcan0: can0grp {
	fsl,pins = <
	VF610_PAD_PTB14__CAN0_RX 0x31F1
	VF610_PAD_PTB15__CAN0_TX 0x31F2
	>;
	};

	pinctrl_flexcan1: can1grp {
	fsl,pins = <
	VF610_PAD_PTB16__CAN1_RX 0x31F1
	VF610_PAD_PTB17__CAN1_TX 0x31F2
	>;
	};

	pinctrl_gpio_ext: gpio_ext {
	fsl,pins = <
	VF610_PAD_PTD10__GPIO_89 0x22ed /* EXT_IO_0 */
	VF610_PAD_PTD9__GPIO_88 0x22ed /* EXT_IO_1 */
	VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */
	>;
	};

	pinctrl_dcu0_1: dcu0grp_1 {
	fsl,pins = <
	VF610_PAD_PTE0__DCU0_HSYNC 0x1902
	VF610_PAD_PTE1__DCU0_VSYNC 0x1902
	VF610_PAD_PTE2__DCU0_PCLK 0x1902
	VF610_PAD_PTE4__DCU0_DE 0x1902
	VF610_PAD_PTE5__DCU0_R0 0x1902
	VF610_PAD_PTE6__DCU0_R1 0x1902
	VF610_PAD_PTE7__DCU0_R2 0x1902
	VF610_PAD_PTE8__DCU0_R3 0x1902
	VF610_PAD_PTE9__DCU0_R4 0x1902
	VF610_PAD_PTE10__DCU0_R5 0x1902
	VF610_PAD_PTE11__DCU0_R6 0x1902
	VF610_PAD_PTE12__DCU0_R7 0x1902
	VF610_PAD_PTE13__DCU0_G0 0x1902
	VF610_PAD_PTE14__DCU0_G1 0x1902
	VF610_PAD_PTE15__DCU0_G2 0x1902
	VF610_PAD_PTE16__DCU0_G3 0x1902
	VF610_PAD_PTE17__DCU0_G4 0x1902
	VF610_PAD_PTE18__DCU0_G5 0x1902
	VF610_PAD_PTE19__DCU0_G6 0x1902
	VF610_PAD_PTE20__DCU0_G7 0x1902
	VF610_PAD_PTE21__DCU0_B0 0x1902
	VF610_PAD_PTE22__DCU0_B1 0x1902
	VF610_PAD_PTE23__DCU0_B2 0x1902
	VF610_PAD_PTE24__DCU0_B3 0x1902
	VF610_PAD_PTE25__DCU0_B4 0x1902
	VF610_PAD_PTE26__DCU0_B5 0x1902
	VF610_PAD_PTE27__DCU0_B6 0x1902
	VF610_PAD_PTE28__DCU0_B7 0x1902
	>;
	};

	pinctrl_dspi1: dspi1grp {
	fsl,pins = <
	VF610_PAD_PTD5__DSPI1_CS0 0x33e2
	VF610_PAD_PTD6__DSPI1_SIN 0x33e1
	VF610_PAD_PTD7__DSPI1_SOUT 0x33e2
	VF610_PAD_PTD8__DSPI1_SCK 0x33e2
	>;
	};

	pinctrl_esdhc1: esdhc1grp {
	fsl,pins = <
	VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
	VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
	VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
	VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
	VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
	VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
	VF610_PAD_PTB20__GPIO_42 0x219d
	>;
	};

	pinctrl_fec1: fec1grp {
	fsl,pins = <
	VF610_PAD_PTA6__RMII_CLKOUT 0x30d2
	VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
	VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
	VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
	VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
	VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
	VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
	VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
	VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
	VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
	>;
	};

	pinctrl_gpio_bl_on: gpio_bl_on {
	fsl,pins = <
	VF610_PAD_PTC0__GPIO_45 0x22ef
	>;
	};

	pinctrl_i2c0: i2c0grp {
	fsl,pins = <
	VF610_PAD_PTB14__I2C0_SCL 0x37ff
	VF610_PAD_PTB15__I2C0_SDA 0x37ff
	>;
	};

	pinctrl_i2c0_gpio: i2c0gpiogrp {
	fsl,pins = <
	VF610_PAD_PTB14__GPIO_36 0x37ff
	VF610_PAD_PTB15__GPIO_37 0x37ff
	>;
	};

	pinctrl_nfc: nfcgrp {
	fsl,pins = <
	VF610_PAD_PTD23__NF_IO7 0x28df
	VF610_PAD_PTD22__NF_IO6 0x28df
	VF610_PAD_PTD21__NF_IO5 0x28df
	VF610_PAD_PTD20__NF_IO4 0x28df
	VF610_PAD_PTD19__NF_IO3 0x28df
	VF610_PAD_PTD18__NF_IO2 0x28df
	VF610_PAD_PTD17__NF_IO1 0x28df
	VF610_PAD_PTD16__NF_IO0 0x28df
	VF610_PAD_PTB24__NF_WE_B 0x28c2
	VF610_PAD_PTB25__NF_CE0_B 0x28c2
	VF610_PAD_PTB27__NF_RE_B 0x28c2
	VF610_PAD_PTC26__NF_RB_B 0x283d
	VF610_PAD_PTC27__NF_ALE 0x28c2
	VF610_PAD_PTC28__NF_CLE 0x28c2
	>;
	};

	pinctrl_pwm0: pwm0grp {
	fsl,pins = <
	VF610_PAD_PTB0__FTM0_CH0 0x1182
	VF610_PAD_PTB1__FTM0_CH1 0x1182
	>;
	};

	pinctrl_pwm1: pwm1grp {
	fsl,pins = <
	VF610_PAD_PTB8__FTM1_CH0 0x1182
	VF610_PAD_PTB9__FTM1_CH1 0x1182
	>;
	};

	pinctrl_uart0: uart0grp {
	fsl,pins = <
	VF610_PAD_PTB10__UART0_TX 0x21a2
	VF610_PAD_PTB11__UART0_RX 0x21a1
	VF610_PAD_PTB12__UART0_RTS 0x21a2
	VF610_PAD_PTB13__UART0_CTS 0x21a1
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	VF610_PAD_PTB4__UART1_TX 0x21a2
	VF610_PAD_PTB5__UART1_RX 0x21a1
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	VF610_PAD_PTD0__UART2_TX 0x21a2
	VF610_PAD_PTD1__UART2_RX 0x21a1
	VF610_PAD_PTD2__UART2_RTS 0x21a2
	VF610_PAD_PTD3__UART2_CTS 0x21a1
	>;
	};

	pinctrl_usbh1_reg: gpio_usb_vbus {
	fsl,pins = <
	VF610_PAD_PTD4__GPIO_83 0x22ed
	>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/vf500-colibri-eval-v3.dts b/sys/gnu/dts/arm/vf500-colibri-eval-v3.dts
	index 076998968fb5..088964f8dc4b 100644
	--- a/sys/gnu/dts/arm/vf500-colibri-eval-v3.dts
	+++ b/sys/gnu/dts/arm/vf500-colibri-eval-v3.dts
	@@ -1,54 +1,18 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2014 Toradex AG
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License
	- * version 2 as published by the Free Software Foundation.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	+ * Copyright 2014-2020 Toradex
	*/

	/dts-v1/;
	#include "vf500-colibri.dtsi"
	#include "vf-colibri-eval-v3.dtsi"

	/ {
	model = "Toradex Colibri VF50 on Colibri Evaluation Board";
	compatible = "toradex,vf500-colibri_vf50-on-eval", "toradex,vf500-colibri_vf50", "fsl,vf500";
	};

	&touchscreen {
	vf50-ts-min-pressure = <200>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/vf500-colibri.dtsi b/sys/gnu/dts/arm/vf500-colibri.dtsi
	index 92255f8893ce..8af7ed56e653 100644
	--- a/sys/gnu/dts/arm/vf500-colibri.dtsi
	+++ b/sys/gnu/dts/arm/vf500-colibri.dtsi
	@@ -1,105 +1,69 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2014 Toradex AG
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License
	- * version 2 as published by the Free Software Foundation.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	+ * Copyright 2014-2020 Toradex
	*/

	#include "vf500.dtsi"
	#include "vf-colibri.dtsi"

	/ {
	model = "Toradex Colibri VF50 COM";
	compatible = "toradex,vf500-colibri_vf50", "fsl,vf500";

	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x8000000>;
	};

	touchscreen: vf50-touchscreen {
	compatible = "toradex,vf50-touchscreen";
	io-channels = <&adc1 0>,<&adc0 0>,
	<&adc0 1>,<&adc1 2>;
	xp-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
	xm-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
	yp-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
	ym-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
	interrupt-parent = <&gpio0>;
	interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "idle","default","gpios";
	pinctrl-0 = <&pinctrl_touchctrl_idle>;
	pinctrl-1 = <&pinctrl_touchctrl_default>;
	pinctrl-2 = <&pinctrl_touchctrl_gpios>;
	vf50-ts-min-pressure = <200>;
	status = "disabled";
	};
	};

	&nfc {
	assigned-clocks = <&clks VF610_CLK_NFC>;
	assigned-clock-rates = <33000000>;
	};

	&iomuxc {
	vf610-colibri {
	pinctrl_touchctrl_idle: touchctrl_idle {
	fsl,pins = <
	VF610_PAD_PTA18__GPIO_8 0x006d
	VF610_PAD_PTA19__GPIO_9 0x006c
	>;
	};

	pinctrl_touchctrl_default: touchctrl_default {
	fsl,pins = <
	VF610_PAD_PTA18__ADC0_SE0 0x0040
	VF610_PAD_PTA19__ADC0_SE1 0x0040
	VF610_PAD_PTA16__ADC1_SE0 0x0040
	VF610_PAD_PTB2__ADC1_SE2 0x0040
	>;
	};

	pinctrl_touchctrl_gpios: touchctrl_gpios {
	fsl,pins = <
	VF610_PAD_PTA23__GPIO_13 0x22e9
	VF610_PAD_PTB23__GPIO_93 0x22e9
	VF610_PAD_PTA22__GPIO_12 0x22e9
	VF610_PAD_PTA11__GPIO_4 0x22e9
	>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/vf500.dtsi b/sys/gnu/dts/arm/vf500.dtsi
	index b0ec475017ad..0c0dd442300a 100644
	--- a/sys/gnu/dts/arm/vf500.dtsi
	+++ b/sys/gnu/dts/arm/vf500.dtsi
	@@ -1,64 +1,64 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	//
	// Copyright 2013 Freescale Semiconductor, Inc.

	#include "vfxxx.dtsi"
	#include <dt-bindings/interrupt-controller/arm-gic.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };
	aliases { };

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	a5_cpu: cpu@0 {
	compatible = "arm,cortex-a5";
	device_type = "cpu";
	reg = <0x0>;
	};
	};

	soc {
	- aips-bus@40000000 {
	+ bus@40000000 {

	intc: interrupt-controller@40003000 {
	compatible = "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	interrupt-controller;
	interrupt-parent = <&intc>;
	reg = <0x40003000 0x1000>,
	<0x40002100 0x100>;
	};

	global_timer: timer@40002200 {
	compatible = "arm,cortex-a9-global-timer";
	reg = <0x40002200 0x20>;
	interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
	interrupt-parent = <&intc>;
	clocks = <&clks VF610_CLK_PLATFORM_BUS>;
	};
	};

	- aips-bus@40080000 {
	+ bus@40080000 {
	pmu@40089000 {
	compatible = "arm,cortex-a5-pmu";
	interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&a5_cpu>;
	reg = <0x40089000 0x1000>;
	};
	};

	};
	};

	&mscm_ir {
	interrupt-parent = <&intc>;
	};

	&wdoga5 {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm/vf610-colibri-eval-v3.dts b/sys/gnu/dts/arm/vf610-colibri-eval-v3.dts
	index ef9b4d6209f6..fb661e8a2dc6 100644
	--- a/sys/gnu/dts/arm/vf610-colibri-eval-v3.dts
	+++ b/sys/gnu/dts/arm/vf610-colibri-eval-v3.dts
	@@ -1,49 +1,13 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2014 Toradex AG
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License
	- * version 2 as published by the Free Software Foundation.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	+ * Copyright 2014-2020 Toradex
	*/

	/dts-v1/;
	#include "vf610-colibri.dtsi"
	#include "vf-colibri-eval-v3.dtsi"

	/ {
	model = "Toradex Colibri VF61 on Colibri Evaluation Board";
	compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610";
	};
	diff --git a/sys/gnu/dts/arm/vf610-colibri.dtsi b/sys/gnu/dts/arm/vf610-colibri.dtsi
	index 05c9a39509b8..607cec2df861 100644
	--- a/sys/gnu/dts/arm/vf610-colibri.dtsi
	+++ b/sys/gnu/dts/arm/vf610-colibri.dtsi
	@@ -1,58 +1,22 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	- * Copyright 2014 Toradex AG
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License
	- * version 2 as published by the Free Software Foundation.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	+ * Copyright 2014-2020 Toradex
	*/

	#include "vf610.dtsi"
	#include "vf-colibri.dtsi"

	/ {
	model = "Toradex Colibri VF61 COM";
	compatible = "toradex,vf610-colibri_vf61", "fsl,vf610";

	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x10000000>;
	};
	};

	&nfc {
	assigned-clocks = <&clks VF610_CLK_NFC>;
	assigned-clock-rates = <50000000>;
	};
	diff --git a/sys/gnu/dts/arm/vf610-zii-cfu1.dts b/sys/gnu/dts/arm/vf610-zii-cfu1.dts
	index 28732249cfc0..ce1920c052fc 100644
	--- a/sys/gnu/dts/arm/vf610-zii-cfu1.dts
	+++ b/sys/gnu/dts/arm/vf610-zii-cfu1.dts
	@@ -1,359 +1,367 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)

	/*
	* Copyright (C) 2018 Zodiac Inflight Innovations
	*/

	/dts-v1/;
	#include "vf610.dtsi"

	/ {
	model = "ZII VF610 CFU1 Board";
	compatible = "zii,vf610cfu1", "zii,vf610dev", "fsl,vf610";

	chosen {
	stdout-path = &uart0;
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x20000000>;
	};

	gpio-leds {
	compatible = "gpio-leds";
	pinctrl-0 = <&pinctrl_leds_debug>;
	pinctrl-names = "default";

	led-debug {
	label = "zii:green:debug1";
	gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	};

	led-fail {
	label = "zii:red:fail";
	gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
	default-state = "off";
	};

	led-status {
	label = "zii:green:status";
	gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	led-debug-a {
	label = "zii:green:debug_a";
	gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};

	led-debug-b {
	label = "zii:green:debug_b";
	gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};
	};

	reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
	compatible = "regulator-fixed";
	regulator-name = "vcc_3v3_mcu";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	sff: sfp {
	compatible = "sff,sff";
	pinctrl-0 = <&pinctrl_optical>;
	pinctrl-names = "default";
	i2c-bus = <&i2c0>;
	los-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
	tx-disable-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
	};
	+
	+ supply-voltage-monitor {
	+ compatible = "iio-hwmon";
	+ io-channels = <&adc0 8>, /* 28VDC_IN */
	+ <&adc0 9>, /* +3.3V */
	+ <&adc1 8>, /* VCC_1V5 */
	+ <&adc1 9>; /* VCC_1V2 */
	+ };
	};

	&adc0 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
	};

	&adc1 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
	};

	&dspi1 {
	bus-num = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dspi1>;
	/*
	* Some CFU1s come with SPI-NOR chip DNPed, so we leave this
	* node disabled by default and rely on bootloader to enable
	* it when appropriate.
	*/
	status = "disabled";

	flash@0 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "m25p128", "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <50000000>;

	partition@0 {
	label = "m25p128-0";
	reg = <0x0 0x01000000>;
	};
	};
	};

	&edma0 {
	status = "okay";
	};

	&edma1 {
	status = "okay";
	};

	&esdhc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc0>;
	bus-width = <8>;
	non-removable;
	no-1-8-v;
	keep-power-in-suspend;
	no-sdio;
	no-sd;
	status = "okay";
	};

	&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	no-sdio;
	status = "okay";
	};

	&fec1 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";

	fixed-link {
	speed = <100>;
	full-duplex;
	};

	mdio1: mdio {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	switch0: switch0@0 {
	compatible = "marvell,mv88e6085";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_switch>;
	reg = <0>;
	eeprom-length = <512>;
	interrupt-parent = <&gpio3>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	label = "eth_cu_1000_1";
	};

	port@1 {
	reg = <1>;
	label = "eth_cu_1000_2";
	};

	port@2 {
	reg = <2>;
	label = "eth_cu_1000_3";
	};

	port@5 {
	reg = <5>;
	label = "eth_fc_1000_1";
	phy-mode = "1000base-x";
	managed = "in-band-status";
	sfp = <&sff>;
	};

	port@6 {
	reg = <6>;
	label = "cpu";
	ethernet = <&fec1>;

	fixed-link {
	speed = <100>;
	full-duplex;
	};
	};
	};
	};
	};
	};

	&i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	status = "okay";

	io-expander@22 {
	compatible = "nxp,pca9554";
	reg = <0x22>;
	gpio-controller;
	};

	lm75@48 {
	compatible = "national,lm75";
	reg = <0x48>;
	};

	eeprom@52 {
	compatible = "atmel,24c04";
	reg = <0x52>;
	label = "nvm";
	};

	eeprom@54 {
	compatible = "atmel,24c04";
	reg = <0x54>;
	label = "nameplate";
	};
	};

	&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	watchdog@38 {
	compatible = "zii,rave-wdt";
	reg = <0x38>;
	};
	};

	&snvsrtc {
	status = "disabled";
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	status = "okay";
	};

	&iomuxc {
	pinctrl_dspi1: dspi1grp {
	fsl,pins = <
	VF610_PAD_PTD5__DSPI1_CS0 0x1182
	VF610_PAD_PTC6__DSPI1_SIN 0x1181
	VF610_PAD_PTC7__DSPI1_SOUT 0x1182
	VF610_PAD_PTC8__DSPI1_SCK 0x1182
	>;
	};

	pinctrl_esdhc0: esdhc0grp {
	fsl,pins = <
	VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
	VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
	VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
	VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
	VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
	VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
	VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
	VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
	VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
	VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
	>;
	};

	pinctrl_esdhc1: esdhc1grp {
	fsl,pins = <
	VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
	VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
	VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
	VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
	VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
	VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
	>;
	};

	pinctrl_fec1: fec1grp {
	fsl,pins = <
	VF610_PAD_PTA6__RMII_CLKIN 0x30d1
	VF610_PAD_PTC9__ENET_RMII1_MDC 0x30fe
	VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
	VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
	VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
	VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
	VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
	VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
	VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
	VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
	>;
	};

	pinctrl_i2c0: i2c0grp {
	fsl,pins = <
	VF610_PAD_PTB14__I2C0_SCL 0x37ff
	VF610_PAD_PTB15__I2C0_SDA 0x37ff
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	VF610_PAD_PTB16__I2C1_SCL 0x37ff
	VF610_PAD_PTB17__I2C1_SDA 0x37ff
	>;
	};

	pinctrl_leds_debug: pinctrl-leds-debug {
	fsl,pins = <
	VF610_PAD_PTD3__GPIO_82 0x31c2
	VF610_PAD_PTE3__GPIO_108 0x31c2
	VF610_PAD_PTE4__GPIO_109 0x31c2
	VF610_PAD_PTE5__GPIO_110 0x31c2
	VF610_PAD_PTE6__GPIO_111 0x31c2
	>;
	};

	pinctrl_optical: optical-grp {
	fsl,pins = <
	/* SFF SD input */
	VF610_PAD_PTE27__GPIO_132 0x3061

	/* SFF Transmit disable output */
	VF610_PAD_PTE13__GPIO_118 0x3043
	>;
	};

	pinctrl_switch: switch-grp {
	fsl,pins = <
	VF610_PAD_PTB28__GPIO_98 0x3061
	VF610_PAD_PTE2__GPIO_107 0x1042
	>;
	};

	pinctrl_uart0: uart0grp {
	fsl,pins = <
	VF610_PAD_PTB10__UART0_TX 0x21a2
	VF610_PAD_PTB11__UART0_RX 0x21a1
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/vf610-zii-dev.dtsi b/sys/gnu/dts/arm/vf610-zii-dev.dtsi
	index a1b4ccee2a10..95d0060fb56c 100644
	--- a/sys/gnu/dts/arm/vf610-zii-dev.dtsi
	+++ b/sys/gnu/dts/arm/vf610-zii-dev.dtsi
	@@ -1,440 +1,448 @@
	/*
	* Copyright (C) 2015, 2016 Zodiac Inflight Innovations
	*
	* Based on an original 'vf610-twr.dts' which is Copyright 2015,
	* Freescale Semiconductor, Inc.
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License
	* version 2 as published by the Free Software Foundation.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include "vf610.dtsi"

	/ {
	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x20000000>;
	};

	gpio-leds {
	compatible = "gpio-leds";
	pinctrl-0 = <&pinctrl_leds_debug>;
	pinctrl-names = "default";

	debug {
	label = "zii:green:debug1";
	gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	};
	};

	reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
	compatible = "regulator-fixed";
	regulator-name = "vcc_3v3_mcu";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	usb0_vbus: regulator-usb0-vbus {
	compatible = "regulator-fixed";
	pinctrl-0 = <&pinctrl_usb_vbus>;
	regulator-name = "usb_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	enable-active-high;
	regulator-always-on;
	regulator-boot-on;
	gpio = <&gpio0 6 0>;
	};
	+
	+ supply-voltage-monitor {
	+ compatible = "iio-hwmon";
	+ io-channels = <&adc0 8>, /* VCC_1V5 */
	+ <&adc0 9>, /* VCC_1V8 */
	+ <&adc1 8>, /* VCC_1V0 */
	+ <&adc1 9>; /* VCC_1V2 */
	+ };
	};

	&adc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc0_ad5>;
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
	};

	&edma0 {
	status = "okay";
	};

	&edma1 {
	status = "okay";
	};

	&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	status = "okay";
	};

	&fec0 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec0>;
	status = "okay";
	};

	&fec1 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";

	fixed-link {
	speed = <100>;
	full-duplex;
	};

	mdio1: mdio {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";
	};
	};

	&i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c0>;
	pinctrl-1 = <&pinctrl_i2c0_gpio>;
	scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
	status = "okay";

	lm75@48 {
	compatible = "national,lm75";
	reg = <0x48>;
	};

	eeprom@50 {
	compatible = "atmel,24c04";
	reg = <0x50>;
	};

	eeprom@52 {
	compatible = "atmel,24c04";
	reg = <0x52>;
	};

	ds1682@6b {
	compatible = "dallas,ds1682";
	reg = <0x6b>;
	};
	};

	&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
	};

	&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
	};

	&qspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi0>;
	status = "okay";

	/*
	* Attached MT25QL02 can go up to 90Mhz in DTR and 166 in STR
	* modes, so, spi-max-frequency is limited to 90MHz
	*/
	flash@0 {
	compatible = "jedec,spi-nor";
	#address-cells = <1>;
	#size-cells = <1>;
	spi-max-frequency = <90000000>;
	spi-rx-bus-width = <4>;
	reg = <0>;
	m25p,fast-read;
	};

	flash@2 {
	compatible = "jedec,spi-nor";
	#address-cells = <1>;
	#size-cells = <1>;
	spi-max-frequency = <90000000>;
	spi-rx-bus-width = <4>;
	reg = <2>;
	m25p,fast-read;
	};
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	status = "okay";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
	};

	&usbdev0 {
	disable-over-current;
	vbus-supply = <&usb0_vbus>;
	dr_mode = "host";
	status = "okay";
	};

	&usbh1 {
	disable-over-current;
	status = "okay";
	};

	&usbmisc0 {
	status = "okay";
	};

	&usbmisc1 {
	status = "okay";
	};

	&usbphy0 {
	status = "okay";
	};

	&usbphy1 {
	status = "okay";
	};

	&tempsensor {
	io-channels = <&adc0 16>;
	};

	&iomuxc {
	pinctrl_adc0_ad5: adc0ad5grp {
	fsl,pins = <
	VF610_PAD_PTC30__ADC0_SE5 0x00a1
	>;
	};

	pinctrl_dspi0: dspi0grp {
	fsl,pins = <
	VF610_PAD_PTB18__DSPI0_CS1 0x1182
	VF610_PAD_PTB19__DSPI0_CS0 0x1182
	VF610_PAD_PTB20__DSPI0_SIN 0x1181
	VF610_PAD_PTB21__DSPI0_SOUT 0x1182
	VF610_PAD_PTB22__DSPI0_SCK 0x1182
	>;
	};

	pinctrl_dspi2: dspi2grp {
	fsl,pins = <
	VF610_PAD_PTD31__DSPI2_CS1 0x1182
	VF610_PAD_PTD30__DSPI2_CS0 0x1182
	VF610_PAD_PTD29__DSPI2_SIN 0x1181
	VF610_PAD_PTD28__DSPI2_SOUT 0x1182
	VF610_PAD_PTD27__DSPI2_SCK 0x1182
	>;
	};

	pinctrl_esdhc1: esdhc1grp {
	fsl,pins = <
	VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
	VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
	VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
	VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
	VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
	VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
	VF610_PAD_PTA7__GPIO_134 0x219d
	>;
	};

	pinctrl_fec0: fec0grp {
	fsl,pins = <
	VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d2
	VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d3
	VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
	VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
	VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
	VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
	VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
	VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
	VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
	>;
	};

	pinctrl_fec1: fec1grp {
	fsl,pins = <
	VF610_PAD_PTA6__RMII_CLKIN 0x30d1
	VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
	VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
	VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
	VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
	VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
	VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
	VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
	VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
	VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
	>;
	};

	pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
	fsl,pins = <
	VF610_PAD_PTB22__GPIO_44 0x33e2
	VF610_PAD_PTB21__GPIO_43 0x33e2
	VF610_PAD_PTB20__GPIO_42 0x33e1
	VF610_PAD_PTB19__GPIO_41 0x33e2
	VF610_PAD_PTB18__GPIO_40 0x33e2
	>;
	};

	pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
	fsl,pins = <
	VF610_PAD_PTB5__GPIO_27 0x219d
	>;
	};

	pinctrl_gpio_switch1: pinctrl-gpio-switch1 {
	fsl,pins = <
	VF610_PAD_PTB4__GPIO_26 0x219d
	>;
	};

	pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset {
	fsl,pins = <
	VF610_PAD_PTE14__GPIO_119 0x31c2
	>;
	};

	pinctrl_i2c0: i2c0grp {
	fsl,pins = <
	VF610_PAD_PTB14__I2C0_SCL 0x37ff
	VF610_PAD_PTB15__I2C0_SDA 0x37ff
	>;
	};

	pinctrl_i2c0_gpio: i2c0grp-gpio {
	fsl,pins = <
	VF610_PAD_PTB14__GPIO_36 0x31c2
	VF610_PAD_PTB15__GPIO_37 0x31c2
	>;
	};


	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	VF610_PAD_PTB16__I2C1_SCL 0x37ff
	VF610_PAD_PTB17__I2C1_SDA 0x37ff
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	VF610_PAD_PTA22__I2C2_SCL 0x37ff
	VF610_PAD_PTA23__I2C2_SDA 0x37ff
	>;
	};

	pinctrl_leds_debug: pinctrl-leds-debug {
	fsl,pins = <
	VF610_PAD_PTD20__GPIO_74 0x31c2
	>;
	};

	pinctrl_qspi0: qspi0grp {
	fsl,pins = <
	VF610_PAD_PTD0__QSPI0_A_QSCK 0x38c2
	VF610_PAD_PTD1__QSPI0_A_CS0 0x38c2
	VF610_PAD_PTD2__QSPI0_A_DATA3 0x38c3
	VF610_PAD_PTD3__QSPI0_A_DATA2 0x38c3
	VF610_PAD_PTD4__QSPI0_A_DATA1 0x38c3
	VF610_PAD_PTD5__QSPI0_A_DATA0 0x38c3
	VF610_PAD_PTD7__QSPI0_B_QSCK 0x38c2
	VF610_PAD_PTD8__QSPI0_B_CS0 0x38c2
	VF610_PAD_PTD9__QSPI0_B_DATA3 0x38c3
	VF610_PAD_PTD10__QSPI0_B_DATA2 0x38c3
	VF610_PAD_PTD11__QSPI0_B_DATA1 0x38c3
	VF610_PAD_PTD12__QSPI0_B_DATA0 0x38c3
	>;
	};

	pinctrl_uart0: uart0grp {
	fsl,pins = <
	VF610_PAD_PTB10__UART0_TX 0x21a2
	VF610_PAD_PTB11__UART0_RX 0x21a1
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	VF610_PAD_PTB23__UART1_TX 0x21a2
	VF610_PAD_PTB24__UART1_RX 0x21a1
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	VF610_PAD_PTD23__UART2_TX 0x21a2
	VF610_PAD_PTD22__UART2_RX 0x21a1
	>;
	};

	pinctrl_usb_vbus: pinctrl-usb-vbus {
	fsl,pins = <
	VF610_PAD_PTA16__GPIO_6 0x31c2
	>;
	};

	pinctrl_usb0_host: usb0-host-grp {
	fsl,pins = <
	VF610_PAD_PTD6__GPIO_85 0x0062
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/vf610-zii-spb4.dts b/sys/gnu/dts/arm/vf610-zii-spb4.dts
	index 77e1484211e4..55b4201e27f6 100644
	--- a/sys/gnu/dts/arm/vf610-zii-spb4.dts
	+++ b/sys/gnu/dts/arm/vf610-zii-spb4.dts
	@@ -1,352 +1,360 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)

	/*
	* Device tree file for ZII's SPB4 board
	*
	* SPB - Seat Power Box
	*
	* Copyright (C) 2019 Zodiac Inflight Innovations
	*/

	/dts-v1/;
	#include "vf610.dtsi"

	/ {
	model = "ZII VF610 SPB4 Board";
	compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610";

	chosen {
	stdout-path = &uart0;
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x20000000>;
	};

	gpio-leds {
	compatible = "gpio-leds";
	pinctrl-0 = <&pinctrl_leds_debug>;
	pinctrl-names = "default";

	led-debug {
	label = "zii:green:debug1";
	gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	};
	};

	reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
	compatible = "regulator-fixed";
	regulator-name = "vcc_3v3_mcu";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};
	+
	+ supply-voltage-monitor {
	+ compatible = "iio-hwmon";
	+ io-channels = <&adc0 8>, /* 28V_SW */
	+ <&adc0 9>, /* +3.3V */
	+ <&adc1 8>, /* VCC_1V5 */
	+ <&adc1 9>; /* VCC_1V2 */
	+ };
	};

	&adc0 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
	};

	&adc1 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
	};

	&dspi1 {
	bus-num = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dspi1>;
	status = "okay";

	flash@0 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "m25p128", "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <50000000>;
	};
	};

	&edma0 {
	status = "okay";
	};

	&edma1 {
	status = "okay";
	};

	&esdhc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc0>;
	bus-width = <8>;
	non-removable;
	no-1-8-v;
	keep-power-in-suspend;
	no-sdio;
	no-sd;
	status = "okay";
	};

	&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	no-sdio;
	status = "okay";
	};

	&fec1 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";

	fixed-link {
	speed = <100>;
	full-duplex;
	};

	mdio1: mdio {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	switch0: switch0@0 {
	compatible = "marvell,mv88e6190";
	pinctrl-0 = <&pinctrl_gpio_switch0>;
	pinctrl-names = "default";
	reg = <0>;
	eeprom-length = <65536>;
	reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
	interrupt-parent = <&gpio3>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;
	#interrupt-cells = <2>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	label = "cpu";
	ethernet = <&fec1>;

	fixed-link {
	speed = <100>;
	full-duplex;
	};
	};

	port@1 {
	reg = <1>;
	label = "eth_cu_1000_1";
	};

	port@2 {
	reg = <2>;
	label = "eth_cu_1000_2";
	};

	port@3 {
	reg = <3>;
	label = "eth_cu_1000_3";
	};

	port@4 {
	reg = <4>;
	label = "eth_cu_1000_4";
	};

	port@5 {
	reg = <5>;
	label = "eth_cu_1000_5";
	};

	port@6 {
	reg = <6>;
	label = "eth_cu_1000_6";
	};
	};
	};
	};
	};

	&i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	status = "okay";

	io-expander@22 {
	compatible = "nxp,pca9554";
	reg = <0x22>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	eeprom@50 {
	compatible = "atmel,24c04";
	reg = <0x50>;
	label = "nameplate";
	};

	eeprom@52 {
	compatible = "atmel,24c04";
	reg = <0x52>;
	};
	};

	&snvsrtc {
	status = "disabled";
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	status = "okay";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";

	rave-sp {
	compatible = "zii,rave-sp-rdu2";
	current-speed = <1000000>;
	#address-cells = <1>;
	#size-cells = <1>;

	watchdog {
	compatible = "zii,rave-sp-watchdog";
	};

	eeprom@a3 {
	compatible = "zii,rave-sp-eeprom";
	reg = <0xa3 0x4000>;
	#address-cells = <1>;
	#size-cells = <1>;
	zii,eeprom-name = "main-eeprom";
	};
	};
	};

	&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
	};

	&wdoga5 {
	status = "disabled";
	};

	&iomuxc {
	pinctrl_dspi1: dspi1grp {
	fsl,pins = <
	VF610_PAD_PTD5__DSPI1_CS0 0x1182
	VF610_PAD_PTD4__DSPI1_CS1 0x1182
	VF610_PAD_PTC6__DSPI1_SIN 0x1181
	VF610_PAD_PTC7__DSPI1_SOUT 0x1182
	VF610_PAD_PTC8__DSPI1_SCK 0x1182
	>;
	};

	pinctrl_esdhc0: esdhc0grp {
	fsl,pins = <
	VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
	VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
	VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
	VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
	VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
	VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
	VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
	VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
	VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
	VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
	>;
	};

	pinctrl_esdhc1: esdhc1grp {
	fsl,pins = <
	VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
	VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
	VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
	VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
	VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
	VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
	>;
	};

	pinctrl_fec1: fec1grp {
	fsl,pins = <
	VF610_PAD_PTA6__RMII_CLKIN 0x30d1
	VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
	VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
	VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
	VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
	VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
	VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
	VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
	VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
	VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
	>;
	};

	pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
	fsl,pins = <
	VF610_PAD_PTE2__GPIO_107 0x31c2
	VF610_PAD_PTB28__GPIO_98 0x219d
	>;
	};

	pinctrl_i2c0: i2c0grp {
	fsl,pins = <
	VF610_PAD_PTB14__I2C0_SCL 0x37ff
	VF610_PAD_PTB15__I2C0_SDA 0x37ff
	>;
	};

	pinctrl_leds_debug: pinctrl-leds-debug {
	fsl,pins = <
	VF610_PAD_PTD3__GPIO_82 0x31c2
	>;
	};

	pinctrl_uart0: uart0grp {
	fsl,pins = <
	VF610_PAD_PTB10__UART0_TX 0x21a2
	VF610_PAD_PTB11__UART0_RX 0x21a1
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	VF610_PAD_PTB23__UART1_TX 0x21a2
	VF610_PAD_PTB24__UART1_RX 0x21a1
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	VF610_PAD_PTD0__UART2_TX 0x21a2
	VF610_PAD_PTD1__UART2_RX 0x21a1
	>;
	};

	pinctrl_uart3: uart3grp {
	fsl,pins = <
	VF610_PAD_PTA30__UART3_TX 0x21a2
	VF610_PAD_PTA31__UART3_RX 0x21a1
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/vf610-zii-ssmb-dtu.dts b/sys/gnu/dts/arm/vf610-zii-ssmb-dtu.dts
	index 847c5858fea1..a6c22a79779e 100644
	--- a/sys/gnu/dts/arm/vf610-zii-ssmb-dtu.dts
	+++ b/sys/gnu/dts/arm/vf610-zii-ssmb-dtu.dts
	@@ -1,314 +1,322 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)

	/*
	* Device tree file for ZII's SSMB DTU board
	*
	* SSMB - SPU3 Switch Management Board
	* DTU - Digital Tapping Unit
	*
	* Copyright (C) 2015-2019 Zodiac Inflight Innovations
	*
	* Based on an original 'vf610-twr.dts' which is Copyright 2015,
	* Freescale Semiconductor, Inc.
	*/

	/dts-v1/;
	#include "vf610.dtsi"

	/ {
	model = "ZII VF610 SSMB DTU Board";
	compatible = "zii,vf610dtu", "zii,vf610dev", "fsl,vf610";

	chosen {
	stdout-path = &uart0;
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x20000000>;
	};

	gpio-leds {
	compatible = "gpio-leds";
	pinctrl-0 = <&pinctrl_leds_debug>;
	pinctrl-names = "default";

	led-debug {
	label = "zii:green:debug1";
	gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	};
	};

	reg_vcc_3v3_mcu: regulator {
	compatible = "regulator-fixed";
	regulator-name = "vcc_3v3_mcu";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};
	+
	+ supply-voltage-monitor {
	+ compatible = "iio-hwmon";
	+ io-channels = <&adc0 8>, /* 12V_MAIN */
	+ <&adc0 9>, /* +3.3V */
	+ <&adc1 8>, /* VCC_1V5 */
	+ <&adc1 9>; /* VCC_1V2 */
	+ };
	};

	&adc0 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
	};

	&adc1 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
	};

	&edma0 {
	status = "okay";
	};

	&edma1 {
	status = "okay";
	};

	&esdhc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc0>;
	bus-width = <8>;
	non-removable;
	no-1-8-v;
	keep-power-in-suspend;
	status = "okay";
	};

	&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	status = "okay";
	};

	&fec1 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";

	fixed-link {
	speed = <100>;
	full-duplex;
	};

	mdio1: mdio {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	switch0: switch0@0 {
	compatible = "marvell,mv88e6190";
	pinctrl-0 = <&pinctrl_gpio_switch0>;
	pinctrl-names = "default";
	reg = <0>;
	eeprom-length = <65536>;
	reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
	interrupt-parent = <&gpio3>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;
	#interrupt-cells = <2>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	label = "cpu";
	ethernet = <&fec1>;

	fixed-link {
	speed = <100>;
	full-duplex;
	};
	};

	port@1 {
	reg = <1>;
	label = "eth_cu_100_3";
	};

	port@5 {
	reg = <5>;
	label = "eth_cu_1000_4";
	};

	port@6 {
	reg = <6>;
	label = "eth_cu_1000_5";
	};

	port@8 {
	reg = <8>;
	label = "eth_cu_1000_1";
	};

	port@9 {
	reg = <9>;
	label = "eth_cu_1000_2";
	phy-handle = <&phy9>;
	phy-mode = "sgmii";
	managed = "in-band-status";
	};
	};

	mdio1 {
	compatible = "marvell,mv88e6xxx-mdio-external";
	#address-cells = <1>;
	#size-cells = <0>;

	phy9: phy9@0 {
	compatible = "ethernet-phy-ieee802.3-c45";
	pinctrl-0 = <&pinctrl_gpio_phy9>;
	pinctrl-names = "default";
	interrupt-parent = <&gpio2>;
	interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
	reg = <0>;
	};
	};
	};
	};
	};

	&i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	status = "okay";

	gpio6: gpio-expander@22 {
	compatible = "nxp,pca9554";
	reg = <0x22>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	/* On SSMB */
	temperature-sensor@48 {
	compatible = "national,lm75";
	reg = <0x48>;
	};

	/* On DSB */
	temperature-sensor@4d {
	compatible = "national,lm75";
	reg = <0x4d>;
	};

	eeprom@50 {
	compatible = "atmel,24c04";
	reg = <0x50>;
	label = "nameplate";
	};

	eeprom@52 {
	compatible = "atmel,24c04";
	reg = <0x52>;
	};
	};

	&snvsrtc {
	status = "disabled";
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	status = "okay";
	};

	&iomuxc {
	pinctrl_dspi1: dspi1grp {
	fsl,pins = <
	VF610_PAD_PTD5__DSPI1_CS0 0x1182
	VF610_PAD_PTD4__DSPI1_CS1 0x1182
	VF610_PAD_PTC6__DSPI1_SIN 0x1181
	VF610_PAD_PTC7__DSPI1_SOUT 0x1182
	VF610_PAD_PTC8__DSPI1_SCK 0x1182
	>;
	};

	pinctrl_esdhc0: esdhc0grp {
	fsl,pins = <
	VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
	VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
	VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
	VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
	VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
	VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
	VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
	VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
	VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
	VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
	>;
	};

	pinctrl_esdhc1: esdhc1grp {
	fsl,pins = <
	VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
	VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
	VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
	VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
	VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
	VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
	>;
	};

	pinctrl_fec1: fec1grp {
	fsl,pins = <
	VF610_PAD_PTA6__RMII_CLKIN 0x30d1
	VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
	VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
	VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
	VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
	VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
	VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
	VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
	VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
	VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
	>;
	};

	pinctrl_gpio_phy9: pinctrl-gpio-phy9 {
	fsl,pins = <
	VF610_PAD_PTB24__GPIO_94 0x219d
	>;
	};

	pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
	fsl,pins = <
	VF610_PAD_PTE2__GPIO_107 0x31c2
	VF610_PAD_PTB28__GPIO_98 0x219d
	>;
	};

	pinctrl_i2c0: i2c0grp {
	fsl,pins = <
	VF610_PAD_PTB14__I2C0_SCL 0x37ff
	VF610_PAD_PTB15__I2C0_SDA 0x37ff
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	VF610_PAD_PTB16__I2C1_SCL 0x37ff
	VF610_PAD_PTB17__I2C1_SDA 0x37ff
	>;
	};

	pinctrl_leds_debug: pinctrl-leds-debug {
	fsl,pins = <
	VF610_PAD_PTD3__GPIO_82 0x31c2
	>;
	};

	pinctrl_uart0: uart0grp {
	fsl,pins = <
	VF610_PAD_PTB10__UART0_TX 0x21a2
	VF610_PAD_PTB11__UART0_RX 0x21a1
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/vf610-zii-ssmb-spu3.dts b/sys/gnu/dts/arm/vf610-zii-ssmb-spu3.dts
	index 453fce80f858..3d05c894bdc0 100644
	--- a/sys/gnu/dts/arm/vf610-zii-ssmb-spu3.dts
	+++ b/sys/gnu/dts/arm/vf610-zii-ssmb-spu3.dts
	@@ -1,352 +1,360 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)

	/*
	* Device tree file for ZII's SSMB SPU3 board
	*
	* SSMB - SPU3 Switch Management Board
	* SPU - Seat Power Unit
	*
	* Copyright (C) 2015, 2016 Zodiac Inflight Innovations
	*
	* Based on an original 'vf610-twr.dts' which is Copyright 2015,
	* Freescale Semiconductor, Inc.
	*/

	/dts-v1/;
	#include "vf610.dtsi"

	/ {
	model = "ZII VF610 SSMB SPU3 Board";
	compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610";

	chosen {
	stdout-path = &uart0;
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0x80000000 0x20000000>;
	};

	gpio-leds {
	compatible = "gpio-leds";
	pinctrl-0 = <&pinctrl_leds_debug>;
	pinctrl-names = "default";

	led-debug {
	label = "zii:green:debug1";
	gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	};
	};

	reg_vcc_3v3_mcu: regulator {
	compatible = "regulator-fixed";
	regulator-name = "vcc_3v3_mcu";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};
	+
	+ supply-voltage-monitor {
	+ compatible = "iio-hwmon";
	+ io-channels = <&adc0 8>, /* 12V_MAIN */
	+ <&adc0 9>, /* +3.3V */
	+ <&adc1 8>, /* VCC_1V5 */
	+ <&adc1 9>; /* VCC_1V2 */
	+ };
	};

	&adc0 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
	};

	&adc1 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
	};

	&dspi1 {
	bus-num = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dspi1>;
	/*
	* Some SPU3s come with SPI-NOR chip DNPed, so we leave this
	* node disabled by default and rely on bootloader to enable
	* it when appropriate.
	*/
	status = "disabled";

	flash@0 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "m25p128", "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <50000000>;

	partition@0 {
	label = "m25p128-0";
	reg = <0x0 0x01000000>;
	};
	};
	};

	&edma0 {
	status = "okay";
	};

	&edma1 {
	status = "okay";
	};

	&esdhc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc0>;
	bus-width = <8>;
	non-removable;
	no-1-8-v;
	keep-power-in-suspend;
	no-sdio;
	no-sd;
	status = "okay";
	};

	&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	no-sdio;
	status = "okay";
	};

	&fec1 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";

	fixed-link {
	speed = <100>;
	full-duplex;
	};

	mdio1: mdio {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	switch0: switch0@0 {
	compatible = "marvell,mv88e6190";
	pinctrl-0 = <&pinctrl_gpio_switch0>;
	pinctrl-names = "default";
	reg = <0>;
	eeprom-length = <65536>;
	reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
	interrupt-parent = <&gpio3>;
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;
	#interrupt-cells = <2>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	label = "cpu";
	ethernet = <&fec1>;

	fixed-link {
	speed = <100>;
	full-duplex;
	};
	};

	port@1 {
	reg = <1>;
	label = "eth_cu_1000_1";
	};

	port@2 {
	reg = <2>;
	label = "eth_cu_1000_2";
	};

	port@3 {
	reg = <3>;
	label = "eth_cu_1000_3";
	};

	port@4 {
	reg = <4>;
	label = "eth_cu_1000_4";
	};

	port@5 {
	reg = <5>;
	label = "eth_cu_1000_5";
	};

	port@6 {
	reg = <6>;
	label = "eth_cu_1000_6";
	};
	};
	};
	};
	};

	&i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	status = "okay";

	gpio6: io-expander@22 {
	compatible = "nxp,pca9554";
	reg = <0x22>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	lm75@48 {
	compatible = "national,lm75";
	reg = <0x48>;
	};

	eeprom@50 {
	compatible = "atmel,24c04";
	reg = <0x50>;
	label = "nameplate";
	};

	eeprom@52 {
	compatible = "atmel,24c04";
	reg = <0x52>;
	};
	};

	&snvsrtc {
	status = "disabled";
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	status = "okay";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";

	rave-sp {
	compatible = "zii,rave-sp-rdu2";
	current-speed = <1000000>;
	#address-cells = <1>;
	#size-cells = <1>;

	watchdog {
	compatible = "zii,rave-sp-watchdog";
	};

	eeprom@a3 {
	compatible = "zii,rave-sp-eeprom";
	reg = <0xa3 0x4000>;
	#address-cells = <1>;
	#size-cells = <1>;
	zii,eeprom-name = "main-eeprom";
	};
	};
	};

	&wdoga5 {
	status = "disabled";
	};

	&iomuxc {
	pinctrl_dspi1: dspi1grp {
	fsl,pins = <
	VF610_PAD_PTD5__DSPI1_CS0 0x1182
	VF610_PAD_PTD4__DSPI1_CS1 0x1182
	VF610_PAD_PTC6__DSPI1_SIN 0x1181
	VF610_PAD_PTC7__DSPI1_SOUT 0x1182
	VF610_PAD_PTC8__DSPI1_SCK 0x1182
	>;
	};

	pinctrl_esdhc0: esdhc0grp {
	fsl,pins = <
	VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
	VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
	VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
	VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
	VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
	VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
	VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
	VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
	VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
	VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
	>;
	};

	pinctrl_esdhc1: esdhc1grp {
	fsl,pins = <
	VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
	VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
	VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
	VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
	VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
	VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
	>;
	};

	pinctrl_fec1: fec1grp {
	fsl,pins = <
	VF610_PAD_PTA6__RMII_CLKIN 0x30d1
	VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
	VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
	VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
	VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
	VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
	VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
	VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
	VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
	VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
	>;
	};

	pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
	fsl,pins = <
	VF610_PAD_PTE2__GPIO_107 0x31c2
	VF610_PAD_PTB28__GPIO_98 0x219d
	>;
	};

	pinctrl_i2c0: i2c0grp {
	fsl,pins = <
	VF610_PAD_PTB14__I2C0_SCL 0x37ff
	VF610_PAD_PTB15__I2C0_SDA 0x37ff
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	VF610_PAD_PTB16__I2C1_SCL 0x37ff
	VF610_PAD_PTB17__I2C1_SDA 0x37ff
	>;
	};

	pinctrl_leds_debug: pinctrl-leds-debug {
	fsl,pins = <
	VF610_PAD_PTD3__GPIO_82 0x31c2
	>;
	};

	pinctrl_uart0: uart0grp {
	fsl,pins = <
	VF610_PAD_PTB10__UART0_TX 0x21a2
	VF610_PAD_PTB11__UART0_RX 0x21a1
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	VF610_PAD_PTB23__UART1_TX 0x21a2
	VF610_PAD_PTB24__UART1_RX 0x21a1
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm/vf610m4-colibri.dts b/sys/gnu/dts/arm/vf610m4-colibri.dts
	index d4bc0e3f2f11..2c2db47af441 100644
	--- a/sys/gnu/dts/arm/vf610m4-colibri.dts
	+++ b/sys/gnu/dts/arm/vf610m4-colibri.dts
	@@ -1,100 +1,63 @@
	+// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	* Device tree for Colibri VF61 Cortex-M4 support
	*
	* Copyright (C) 2015 Stefan Agner
	- *
	- * This file is dual-licensed: you can use it either under the terms
	- * of the GPL or the X11 license, at your option. Note that this dual
	- * licensing only applies to this file, and not this project as a
	- * whole.
	- *
	- * a) This file is free software; you can redistribute it and/or
	- * modify it under the terms of the GNU General Public License as
	- * published by the Free Software Foundation; either version 2 of the
	- * License, or (at your option) any later version.
	- *
	- * This file is distributed in the hope that it will be useful,
	- * but WITHOUT ANY WARRANTY; without even the implied warranty of
	- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	- * GNU General Public License for more details.
	- *
	- * Or, alternatively,
	- *
	- * b) Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or
	- * sell copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	*/

	/dts-v1/;
	#include "vf610m4.dtsi"

	/ {
	model = "VF610 Cortex-M4";
	compatible = "fsl,vf610m4";

	chosen {
	bootargs = "clk_ignore_unused init=/linuxrc rw";
	stdout-path = "serial2:115200";
	};

	memory@8c000000 {
	device_type = "memory";
	reg = <0x8c000000 0x3000000>;
	};
	};

	&gpio0 {
	status = "disabled";
	};

	&gpio1 {
	status = "disabled";
	};

	&gpio2 {
	status = "disabled";
	};

	&gpio3 {
	status = "disabled";
	};

	&gpio4 {
	status = "disabled";
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
	};

	&iomuxc {
	vf610-colibri {
	pinctrl_uart2: uart2grp {
	fsl,pins = <
	VF610_PAD_PTD0__UART2_TX 0x21a2
	VF610_PAD_PTD1__UART2_RX 0x21a1
	VF610_PAD_PTD2__UART2_RTS 0x21a2
	VF610_PAD_PTD3__UART2_CTS 0x21a1
	>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm/vfxxx.dtsi b/sys/gnu/dts/arm/vfxxx.dtsi
	index 028e0ec30e0c..2d547e7b21ad 100644
	--- a/sys/gnu/dts/arm/vfxxx.dtsi
	+++ b/sys/gnu/dts/arm/vfxxx.dtsi
	@@ -1,734 +1,734 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	//
	// Copyright 2013 Freescale Semiconductor, Inc.

	#include "vf610-pinfunc.h"
	#include <dt-bindings/clock/vf610-clock.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/gpio/gpio.h>

	/ {
	aliases {
	can0 = &can0;
	can1 = &can1;
	ethernet0 = &fec0;
	ethernet1 = &fec1;
	serial0 = &uart0;
	serial1 = &uart1;
	serial2 = &uart2;
	serial3 = &uart3;
	serial4 = &uart4;
	serial5 = &uart5;
	gpio0 = &gpio0;
	gpio1 = &gpio1;
	gpio2 = &gpio2;
	gpio3 = &gpio3;
	gpio4 = &gpio4;
	usbphy0 = &usbphy0;
	usbphy1 = &usbphy1;
	};

	fxosc: fxosc {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	};

	sxosc: sxosc {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};

	reboot: syscon-reboot {
	compatible = "syscon-reboot";
	regmap = <&src>;
	offset = <0x0>;
	mask = <0x1000>;
	};

	tempsensor: iio-hwmon {
	compatible = "iio-hwmon";
	io-channels = <&adc0 16>, <&adc1 16>;
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	interrupt-parent = <&mscm_ir>;
	ranges;

	- aips0: aips-bus@40000000 {
	+ aips0: bus@40000000 {
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x40000000 0x00070000>;
	ranges;

	mscm_cpucfg: cpucfg@40001000 {
	compatible = "fsl,vf610-mscm-cpucfg", "syscon";
	reg = <0x40001000 0x800>;
	};

	mscm_ir: interrupt-controller@40001800 {
	compatible = "fsl,vf610-mscm-ir";
	reg = <0x40001800 0x400>;
	fsl,cpucfg = <&mscm_cpucfg>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	edma0: dma-controller@40018000 {
	#dma-cells = <2>;
	compatible = "fsl,vf610-edma";
	reg = <0x40018000 0x2000>,
	<0x40024000 0x1000>,
	<0x40025000 0x1000>;
	dma-channels = <32>;
	interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
	<9 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "edma-tx", "edma-err";
	clock-names = "dmamux0", "dmamux1";
	clocks = <&clks VF610_CLK_DMAMUX0>,
	<&clks VF610_CLK_DMAMUX1>;
	status = "disabled";
	};

	can0: flexcan@40020000 {
	compatible = "fsl,vf610-flexcan";
	reg = <0x40020000 0x4000>;
	interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_FLEXCAN0>,
	<&clks VF610_CLK_FLEXCAN0>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart0: serial@40027000 {
	compatible = "fsl,vf610-lpuart";
	reg = <0x40027000 0x1000>;
	interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_UART0>;
	clock-names = "ipg";
	dmas = <&edma0 0 2>,
	<&edma0 0 3>;
	dma-names = "rx","tx";
	status = "disabled";
	};

	uart1: serial@40028000 {
	compatible = "fsl,vf610-lpuart";
	reg = <0x40028000 0x1000>;
	interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_UART1>;
	clock-names = "ipg";
	dmas = <&edma0 0 4>,
	<&edma0 0 5>;
	dma-names = "rx","tx";
	status = "disabled";
	};

	uart2: serial@40029000 {
	compatible = "fsl,vf610-lpuart";
	reg = <0x40029000 0x1000>;
	interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_UART2>;
	clock-names = "ipg";
	dmas = <&edma0 0 6>,
	<&edma0 0 7>;
	dma-names = "rx","tx";
	status = "disabled";
	};

	uart3: serial@4002a000 {
	compatible = "fsl,vf610-lpuart";
	reg = <0x4002a000 0x1000>;
	interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_UART3>;
	clock-names = "ipg";
	dmas = <&edma0 0 8>,
	<&edma0 0 9>;
	dma-names = "rx","tx";
	status = "disabled";
	};

	dspi0: spi@4002c000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,vf610-dspi";
	reg = <0x4002c000 0x1000>;
	interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_DSPI0>;
	clock-names = "dspi";
	spi-num-chipselects = <6>;
	dmas = <&edma1 1 12>,
	<&edma1 1 13>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	dspi1: spi@4002d000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,vf610-dspi";
	reg = <0x4002d000 0x1000>;
	interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_DSPI1>;
	clock-names = "dspi";
	spi-num-chipselects = <4>;
	dmas = <&edma1 1 14>,
	<&edma1 1 15>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	sai0: sai@4002f000 {
	compatible = "fsl,vf610-sai";
	reg = <0x4002f000 0x1000>;
	interrupts = <84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_SAI0>,
	<&clks VF610_CLK_SAI0_DIV>,
	<&clks 0>, <&clks 0>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dma-names = "tx", "rx";
	dmas = <&edma0 0 17>,
	<&edma0 0 16>;
	status = "disabled";
	};

	sai1: sai@40030000 {
	compatible = "fsl,vf610-sai";
	reg = <0x40030000 0x1000>;
	interrupts = <85 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_SAI1>,
	<&clks VF610_CLK_SAI1_DIV>,
	<&clks 0>, <&clks 0>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dma-names = "tx", "rx";
	dmas = <&edma0 0 19>,
	<&edma0 0 18>;
	status = "disabled";
	};

	sai2: sai@40031000 {
	compatible = "fsl,vf610-sai";
	reg = <0x40031000 0x1000>;
	interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_SAI2>,
	<&clks VF610_CLK_SAI2_DIV>,
	<&clks 0>, <&clks 0>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dma-names = "tx", "rx";
	dmas = <&edma0 0 21>,
	<&edma0 0 20>;
	status = "disabled";
	};

	sai3: sai@40032000 {
	compatible = "fsl,vf610-sai";
	reg = <0x40032000 0x1000>;
	interrupts = <87 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_SAI3>,
	<&clks VF610_CLK_SAI3_DIV>,
	<&clks 0>, <&clks 0>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dma-names = "tx", "rx";
	dmas = <&edma0 1 9>,
	<&edma0 1 8>;
	status = "disabled";
	};

	pit: pit@40037000 {
	compatible = "fsl,vf610-pit";
	reg = <0x40037000 0x1000>;
	interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_PIT>;
	clock-names = "pit";
	};

	pwm0: pwm@40038000 {
	compatible = "fsl,vf610-ftm-pwm";
	#pwm-cells = <3>;
	reg = <0x40038000 0x1000>;
	clock-names = "ftm_sys", "ftm_ext",
	"ftm_fix", "ftm_cnt_clk_en";
	clocks = <&clks VF610_CLK_FTM0>,
	<&clks VF610_CLK_FTM0_EXT_SEL>,
	<&clks VF610_CLK_FTM0_FIX_SEL>,
	<&clks VF610_CLK_FTM0_EXT_FIX_EN>;
	status = "disabled";
	};

	pwm1: pwm@40039000 {
	compatible = "fsl,vf610-ftm-pwm";
	#pwm-cells = <3>;
	reg = <0x40039000 0x1000>;
	clock-names = "ftm_sys", "ftm_ext",
	"ftm_fix", "ftm_cnt_clk_en";
	clocks = <&clks VF610_CLK_FTM1>,
	<&clks VF610_CLK_FTM1_EXT_SEL>,
	<&clks VF610_CLK_FTM1_FIX_SEL>,
	<&clks VF610_CLK_FTM1_EXT_FIX_EN>;
	status = "disabled";
	};

	adc0: adc@4003b000 {
	compatible = "fsl,vf610-adc";
	reg = <0x4003b000 0x1000>;
	interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_ADC0>;
	clock-names = "adc";
	#io-channel-cells = <1>;
	status = "disabled";
	fsl,adck-max-frequency = <30000000>, <40000000>,
	<20000000>;
	};

	tcon0: timing-controller@4003d000 {
	compatible = "fsl,vf610-tcon";
	reg = <0x4003d000 0x1000>;
	clocks = <&clks VF610_CLK_TCON0>;
	clock-names = "ipg";
	status = "disabled";
	};

	wdoga5: wdog@4003e000 {
	compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
	reg = <0x4003e000 0x1000>;
	interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_WDT>;
	clock-names = "wdog";
	status = "disabled";
	};

	qspi0: spi@40044000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,vf610-qspi";
	reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
	reg-names = "QuadSPI", "QuadSPI-memory";
	interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_QSPI0_EN>,
	<&clks VF610_CLK_QSPI0>;
	clock-names = "qspi_en", "qspi";
	status = "disabled";
	};

	iomuxc: iomuxc@40048000 {
	compatible = "fsl,vf610-iomuxc";
	reg = <0x40048000 0x1000>;
	};

	gpio0: gpio@40049000 {
	compatible = "fsl,vf610-gpio";
	reg = <0x40049000 0x1000 0x400ff000 0x40>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 0 32>;
	};

	gpio1: gpio@4004a000 {
	compatible = "fsl,vf610-gpio";
	reg = <0x4004a000 0x1000 0x400ff040 0x40>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 32 32>;
	};

	gpio2: gpio@4004b000 {
	compatible = "fsl,vf610-gpio";
	reg = <0x4004b000 0x1000 0x400ff080 0x40>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 64 32>;
	};

	gpio3: gpio@4004c000 {
	compatible = "fsl,vf610-gpio";
	reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 96 32>;
	};

	gpio4: gpio@4004d000 {
	compatible = "fsl,vf610-gpio";
	reg = <0x4004d000 0x1000 0x400ff100 0x40>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 128 7>;
	};

	anatop: anatop@40050000 {
	compatible = "fsl,vf610-anatop", "syscon";
	reg = <0x40050000 0x400>;
	};

	usbphy0: usbphy@40050800 {
	compatible = "fsl,vf610-usbphy";
	reg = <0x40050800 0x400>;
	interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_USBPHY0>;
	fsl,anatop = <&anatop>;
	status = "disabled";
	};

	usbphy1: usbphy@40050c00 {
	compatible = "fsl,vf610-usbphy";
	reg = <0x40050c00 0x400>;
	interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_USBPHY1>;
	fsl,anatop = <&anatop>;
	status = "disabled";
	};

	dcu0: dcu@40058000 {
	compatible = "fsl,vf610-dcu";
	reg = <0x40058000 0x1200>;
	interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_DCU0>,
	<&clks VF610_CLK_DCU0_DIV>;
	clock-names = "dcu", "pix";
	fsl,tcon = <&tcon0>;
	status = "disabled";
	};

	i2c0: i2c@40066000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,vf610-i2c";
	reg = <0x40066000 0x1000>;
	interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_I2C0>;
	clock-names = "ipg";
	dmas = <&edma0 0 50>,
	<&edma0 0 51>;
	dma-names = "rx","tx";
	status = "disabled";
	};

	i2c1: i2c@40067000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,vf610-i2c";
	reg = <0x40067000 0x1000>;
	interrupts = <72 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_I2C1>;
	clock-names = "ipg";
	dmas = <&edma0 0 52>,
	<&edma0 0 53>;
	dma-names = "rx","tx";
	status = "disabled";
	};

	clks: ccm@4006b000 {
	compatible = "fsl,vf610-ccm";
	reg = <0x4006b000 0x1000>;
	clocks = <&sxosc>, <&fxosc>;
	clock-names = "sxosc", "fxosc";
	#clock-cells = <1>;
	};

	usbdev0: usb@40034000 {
	compatible = "fsl,vf610-usb", "fsl,imx27-usb";
	reg = <0x40034000 0x800>;
	interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_USBC0>;
	fsl,usbphy = <&usbphy0>;
	fsl,usbmisc = <&usbmisc0 0>;
	dr_mode = "peripheral";
	status = "disabled";
	};

	usbmisc0: usb@40034800 {
	#index-cells = <1>;
	compatible = "fsl,vf610-usbmisc";
	reg = <0x40034800 0x200>;
	clocks = <&clks VF610_CLK_USBC0>;
	status = "disabled";
	};

	src: src@4006e000 {
	compatible = "fsl,vf610-src", "syscon";
	reg = <0x4006e000 0x1000>;
	interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	- aips1: aips-bus@40080000 {
	+ aips1: bus@40080000 {
	compatible = "fsl,aips-bus", "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x40080000 0x0007f000>;
	ranges;

	edma1: dma-controller@40098000 {
	#dma-cells = <2>;
	compatible = "fsl,vf610-edma";
	reg = <0x40098000 0x2000>,
	<0x400a1000 0x1000>,
	<0x400a2000 0x1000>;
	dma-channels = <32>;
	interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
	<11 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "edma-tx", "edma-err";
	clock-names = "dmamux0", "dmamux1";
	clocks = <&clks VF610_CLK_DMAMUX2>,
	<&clks VF610_CLK_DMAMUX3>;
	status = "disabled";
	};

	ocotp: ocotp@400a5000 {
	compatible = "fsl,vf610-ocotp";
	reg = <0x400a5000 0x1000>;
	clocks = <&clks VF610_CLK_OCOTP>;
	};

	snvs0: snvs@400a7000 {
	compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
	reg = <0x400a7000 0x2000>;

	snvsrtc: snvs-rtc-lp {
	compatible = "fsl,sec-v4.0-mon-rtc-lp";
	regmap = <&snvs0>;
	offset = <0x34>;
	interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_SNVS>;
	clock-names = "snvs-rtc";
	};
	};

	uart4: serial@400a9000 {
	compatible = "fsl,vf610-lpuart";
	reg = <0x400a9000 0x1000>;
	interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_UART4>;
	clock-names = "ipg";
	status = "disabled";
	};

	uart5: serial@400aa000 {
	compatible = "fsl,vf610-lpuart";
	reg = <0x400aa000 0x1000>;
	interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_UART5>;
	clock-names = "ipg";
	status = "disabled";
	};

	dspi2: spi@400ac000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,vf610-dspi";
	reg = <0x400ac000 0x1000>;
	interrupts = <69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_DSPI2>;
	clock-names = "dspi";
	spi-num-chipselects = <2>;
	dmas = <&edma1 0 10>,
	<&edma1 0 11>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	dspi3: spi@400ad000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,vf610-dspi";
	reg = <0x400ad000 0x1000>;
	interrupts = <70 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_DSPI3>;
	clock-names = "dspi";
	spi-num-chipselects = <2>;
	dmas = <&edma1 0 12>,
	<&edma1 0 13>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	adc1: adc@400bb000 {
	compatible = "fsl,vf610-adc";
	reg = <0x400bb000 0x1000>;
	interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_ADC1>;
	clock-names = "adc";
	#io-channel-cells = <1>;
	status = "disabled";
	fsl,adck-max-frequency = <30000000>, <40000000>,
	<20000000>;
	};

	esdhc0: esdhc@400b1000 {
	compatible = "fsl,imx53-esdhc";
	reg = <0x400b1000 0x1000>;
	interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_IPG_BUS>,
	<&clks VF610_CLK_PLATFORM_BUS>,
	<&clks VF610_CLK_ESDHC0>;
	clock-names = "ipg", "ahb", "per";
	status = "disabled";
	};

	esdhc1: esdhc@400b2000 {
	compatible = "fsl,imx53-esdhc";
	reg = <0x400b2000 0x1000>;
	interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_IPG_BUS>,
	<&clks VF610_CLK_PLATFORM_BUS>,
	<&clks VF610_CLK_ESDHC1>;
	clock-names = "ipg", "ahb", "per";
	status = "disabled";
	};

	usbh1: usb@400b4000 {
	compatible = "fsl,vf610-usb", "fsl,imx27-usb";
	reg = <0x400b4000 0x800>;
	interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_USBC1>;
	fsl,usbphy = <&usbphy1>;
	fsl,usbmisc = <&usbmisc1 0>;
	dr_mode = "host";
	status = "disabled";
	};

	usbmisc1: usb@400b4800 {
	#index-cells = <1>;
	compatible = "fsl,vf610-usbmisc";
	reg = <0x400b4800 0x200>;
	clocks = <&clks VF610_CLK_USBC1>;
	status = "disabled";
	};

	ftm: ftm@400b8000 {
	compatible = "fsl,ftm-timer";
	reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
	interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "ftm-evt", "ftm-src",
	"ftm-evt-counter-en", "ftm-src-counter-en";
	clocks = <&clks VF610_CLK_FTM2>,
	<&clks VF610_CLK_FTM3>,
	<&clks VF610_CLK_FTM2_EXT_FIX_EN>,
	<&clks VF610_CLK_FTM3_EXT_FIX_EN>;
	status = "disabled";
	};

	qspi1: spi@400c4000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,vf610-qspi";
	reg = <0x400c4000 0x1000>, <0x50000000 0x10000000>;
	reg-names = "QuadSPI", "QuadSPI-memory";
	interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_QSPI1_EN>,
	<&clks VF610_CLK_QSPI1>;
	clock-names = "qspi_en", "qspi";
	status = "disabled";
	};

	dac0: dac@400cc000 {
	compatible = "fsl,vf610-dac";
	reg = <0x400cc000 1000>;
	interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "dac";
	clocks = <&clks VF610_CLK_DAC0>;
	status = "disabled";
	};

	dac1: dac@400cd000 {
	compatible = "fsl,vf610-dac";
	reg = <0x400cd000 1000>;
	interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "dac";
	clocks = <&clks VF610_CLK_DAC1>;
	status = "disabled";
	};

	fec0: ethernet@400d0000 {
	compatible = "fsl,mvf600-fec";
	reg = <0x400d0000 0x1000>;
	interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_ENET0>,
	<&clks VF610_CLK_ENET0>,
	<&clks VF610_CLK_ENET>;
	clock-names = "ipg", "ahb", "ptp";
	status = "disabled";
	};

	fec1: ethernet@400d1000 {
	compatible = "fsl,mvf600-fec";
	reg = <0x400d1000 0x1000>;
	interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_ENET1>,
	<&clks VF610_CLK_ENET1>,
	<&clks VF610_CLK_ENET>;
	clock-names = "ipg", "ahb", "ptp";
	status = "disabled";
	};

	can1: flexcan@400d4000 {
	compatible = "fsl,vf610-flexcan";
	reg = <0x400d4000 0x4000>;
	interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_FLEXCAN1>,
	<&clks VF610_CLK_FLEXCAN1>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	nfc: nand@400e0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,vf610-nfc";
	reg = <0x400e0000 0x4000>;
	interrupts = <83 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_NFC>;
	clock-names = "nfc";
	status = "disabled";
	};

	i2c2: i2c@400e6000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,vf610-i2c";
	reg = <0x400e6000 0x1000>;
	interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_I2C2>;
	clock-names = "ipg";
	dmas = <&edma0 1 36>,
	<&edma0 1 37>;
	dma-names = "rx","tx";
	status = "disabled";
	};

	i2c3: i2c@400e7000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,vf610-i2c";
	reg = <0x400e7000 0x1000>;
	interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks VF610_CLK_I2C3>;
	clock-names = "ipg";
	dmas = <&edma0 1 38>,
	<&edma0 1 39>;
	dma-names = "rx","tx";
	status = "disabled";
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-olinuxino.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-olinuxino.dts
	index 6dfafa1c879b..5fa9ca0191a8 100644
	--- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-olinuxino.dts
	+++ b/sys/gnu/dts/arm64/allwinner/sun50i-a64-olinuxino.dts
	@@ -1,321 +1,338 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	// Copyright (C) 2017 Jagan Teki <jteki@openedev.com>

	/dts-v1/;

	#include "sun50i-a64.dtsi"
	#include "sun50i-a64-cpu-opp.dtsi"

	#include <dt-bindings/gpio/gpio.h>

	/ {
	model = "Olimex A64-Olinuxino";
	compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64";

	aliases {
	ethernet0 = &emac;
	serial0 = &uart0;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	hdmi-connector {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con_in: endpoint {
	remote-endpoint = <&hdmi_out_con>;
	};
	};
	};

	reg_usb1_vbus: usb1-vbus {
	compatible = "regulator-fixed";
	regulator-name = "usb1-vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-boot-on;
	enable-active-high;
	gpio = <&pio 6 9 GPIO_ACTIVE_HIGH>; /* PG9 */
	status = "okay";
	};

	wifi_pwrseq: wifi_pwrseq {
	compatible = "mmc-pwrseq-simple";
	reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
	};
	};

	&cpu0 {
	cpu-supply = <&reg_dcdc2>;
	};

	&cpu1 {
	cpu-supply = <&reg_dcdc2>;
	};

	&cpu2 {
	cpu-supply = <&reg_dcdc2>;
	};

	&cpu3 {
	cpu-supply = <&reg_dcdc2>;
	};

	&de {
	status = "okay";
	};

	&ehci0 {
	status = "okay";
	};

	&ehci1 {
	status = "okay";
	};

	&emac {
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins>;
	phy-mode = "rgmii";
	phy-handle = <&ext_rgmii_phy>;
	phy-supply = <&reg_dcdc1>;
	allwinner,tx-delay-ps = <600>;
	status = "okay";
	};

	&hdmi {
	hvcc-supply = <&reg_dldo1>;
	status = "okay";
	};

	&hdmi_out {
	hdmi_out_con: endpoint {
	remote-endpoint = <&hdmi_con_in>;
	};
	};

	&mdio {
	ext_rgmii_phy: ethernet-phy@1 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <1>;
	};
	};

	&mmc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	vmmc-supply = <&reg_dcdc1>;
	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
	disable-wp;
	bus-width = <4>;
	status = "okay";
	};

	&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	vmmc-supply = <&reg_dcdc1>;
	vqmmc-supply = <&reg_dldo4>;
	mmc-pwrseq = <&wifi_pwrseq>;
	bus-width = <4>;
	non-removable;
	status = "okay";

	rtl8723bs: wifi@1 {
	reg = <1>;
	interrupt-parent = <&r_pio>;
	interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
	interrupt-names = "host-wake";
	};
	};

	&ohci0 {
	status = "okay";
	};

	&ohci1 {
	status = "okay";
	};

	&pio {
	vcc-pc-supply = <&reg_dcdc1>;
	vcc-pd-supply = <&reg_dcdc1>;
	vcc-pe-supply = <&reg_aldo1>;
	vcc-pg-supply = <&reg_dldo4>;
	};

	&r_pio {
	/*
	* FIXME: We can't add that supply for now since it would
	* create a circular dependency between pinctrl, the regulator
	* and the RSB Bus.
	*
	* vcc-pl-supply = <&reg_aldo2>;
	*/
	};

	+&pio {
	+ vcc-pa-supply = <&reg_dcdc1>;
	+ vcc-pb-supply = <&reg_dcdc1>;
	+ vcc-pc-supply = <&reg_dcdc1>;
	+ vcc-pd-supply = <&reg_dcdc1>;
	+ vcc-pe-supply = <&reg_aldo1>;
	+ vcc-pf-supply = <&reg_dcdc1>;
	+ vcc-pg-supply = <&reg_dldo4>;
	+ vcc-ph-supply = <&reg_dcdc1>;
	+};
	+
	&r_rsb {
	status = "okay";

	axp803: pmic@3a3 {
	compatible = "x-powers,axp803";
	reg = <0x3a3>;
	interrupt-parent = <&r_intc>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
	};
	};

	+/* VCC-PL is powered by aldo2 but we cannot add it as the RSB */
	+/* interface used to talk to the PMIC in on the PL pins */
	+/* &r_pio { */
	+/* vcc-pl-supply = <&reg_aldo2>; */
	+/* }; */
	+
	#include "axp803.dtsi"

	&ac_power_supply {
	status = "okay";
	};

	&battery_power_supply {
	status = "okay";
	};

	&reg_aldo1 {
	regulator-always-on;
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-name = "vcc-pe";
	};

	&reg_aldo2 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-pl";
	};

	&reg_aldo3 {
	regulator-always-on;
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-name = "vcc-pll-avcc";
	};

	&reg_dcdc1 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-3v3";
	};

	&reg_dcdc2 {
	regulator-always-on;
	regulator-min-microvolt = <1040000>;
	regulator-max-microvolt = <1300000>;
	regulator-name = "vdd-cpux";
	};

	/* DCDC3 is polyphased with DCDC2 */

	/*
	* The board uses DDR3L DRAM chips. 1.36V is the closest to the nominal
	* 1.35V that the PMIC can drive.
	*/
	&reg_dcdc5 {
	regulator-always-on;
	regulator-min-microvolt = <1360000>;
	regulator-max-microvolt = <1360000>;
	regulator-name = "vcc-ddr3";
	};

	&reg_dcdc6 {
	regulator-always-on;
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-name = "vdd-sys";
	};

	&reg_dldo1 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-hdmi";
	};

	&reg_dldo2 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-mipi";
	};

	&reg_dldo3 {
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-name = "vcc-avdd-csi";
	};

	&reg_dldo4 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-wifi-io";
	};

	&reg_drivevbus {
	regulator-name = "usb0-vbus";
	status = "okay";
	};

	&reg_eldo1 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "cpvdd";
	};

	&reg_eldo2 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc-dvdd-csi";
	};

	&reg_fldo1 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-name = "vcc-1v2-hsic";
	};

	/*
	* The A64 chip cannot work without this regulator off, although
	* it seems to be only driving the AR100 core.
	* Maybe we don't still know well about CPUs domain.
	*/
	&reg_fldo2 {
	regulator-always-on;
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-name = "vdd-cpus";
	};

	&reg_rtc_ldo {
	regulator-name = "vcc-rtc";
	};

	&simplefb_hdmi {
	vcc-hdmi-supply = <&reg_dldo1>;
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pb_pins>;
	status = "okay";
	};

	&usb_otg {
	dr_mode = "otg";
	status = "okay";
	};

	&usbphy {
	status = "okay";
	usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
	usb0_vbus-supply = <&reg_drivevbus>;
	usb1_vbus-supply = <&reg_usb1_vbus>;
	};
	diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinebook.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinebook.dts
	index 3d894b208901..64b1c54f87c0 100644
	--- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinebook.dts
	+++ b/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinebook.dts
	@@ -1,367 +1,419 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
	// Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>

	/dts-v1/;

	#include "sun50i-a64.dtsi"
	#include "sun50i-a64-cpu-opp.dtsi"

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/gpio-keys.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/pwm/pwm.h>

	/ {
	model = "Pinebook";
	compatible = "pine64,pinebook", "allwinner,sun50i-a64";

	aliases {
	serial0 = &uart0;
	ethernet0 = &rtl8723cs;
	};

	- vdd_bl: regulator@0 {
	- compatible = "regulator-fixed";
	- regulator-name = "bl-3v3";
	- regulator-min-microvolt = <3300000>;
	- regulator-max-microvolt = <3300000>;
	- gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
	- enable-active-high;
	- };
	-
	backlight: backlight {
	compatible = "pwm-backlight";
	pwms = <&pwm 0 50000 0>;
	brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
	default-brightness-level = <2>;
	enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
	- power-supply = <&vdd_bl>;
	+ power-supply = <&reg_vbklt>;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	-
	- framebuffer-lcd {
	- panel-supply = <&reg_dc1sw>;
	- dvdd25-supply = <&reg_dldo2>;
	- dvdd12-supply = <&reg_fldo1>;
	- };
	};

	gpio_keys {
	compatible = "gpio-keys";

	lid_switch {
	label = "Lid Switch";
	gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */
	linux,input-type = <EV_SW>;
	linux,code = <SW_LID>;
	linux,can-disable;
	wakeup-source;
	wakeup-event-action = <EV_ACT_DEASSERTED>;
	};
	};

	- reg_vcc3v3: vcc3v3 {
	+ panel_edp: panel-edp {
	+ compatible = "neweast,wjfh116008a";
	+ backlight = <&backlight>;
	+ power-supply = <&reg_dc1sw>;
	+
	+ port {
	+ panel_edp_in: endpoint {
	+ remote-endpoint = <&anx6345_out_edp>;
	+ };
	+ };
	+ };
	+
	+ reg_vbklt: vbklt {
	+ compatible = "regulator-fixed";
	+ regulator-name = "vbklt";
	+ regulator-min-microvolt = <18000000>;
	+ regulator-max-microvolt = <18000000>;
	+ gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
	+ enable-active-high;
	+ };
	+
	+ reg_vcc5v0: vcc5v0 {
	compatible = "regulator-fixed";
	- regulator-name = "vcc3v3";
	- regulator-min-microvolt = <3300000>;
	- regulator-max-microvolt = <3300000>;
	+ regulator-name = "vcc5v0";
	+ regulator-min-microvolt = <5000000>;
	+ regulator-max-microvolt = <5000000>;
	+ gpio = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;
	+ enable-active-high;
	};

	wifi_pwrseq: wifi_pwrseq {
	compatible = "mmc-pwrseq-simple";
	reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
	};

	speaker_amp: audio-amplifier {
	compatible = "simple-audio-amplifier";
	- /*
	- * TODO This is actually a fixed regulator controlled by
	- * the GPIO line on the PMIC. This should be corrected
	- * once GPIO support is added for this PMIC.
	- */
	- VCC-supply = <&reg_ldo_io0>;
	+ VCC-supply = <&reg_vcc5v0>;
	enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
	sound-name-prefix = "Speaker Amp";
	};

	};

	&codec {
	status = "okay";
	};

	&codec_analog {
	cpvdd-supply = <&reg_eldo1>;
	status = "okay";
	};

	&cpu0 {
	cpu-supply = <&reg_dcdc2>;
	};

	&cpu1 {
	cpu-supply = <&reg_dcdc2>;
	};

	&cpu2 {
	cpu-supply = <&reg_dcdc2>;
	};

	&cpu3 {
	cpu-supply = <&reg_dcdc2>;
	};

	&dai {
	status = "okay";
	};

	+&de {
	+ status = "okay";
	+};
	+
	&ehci0 {
	phys = <&usbphy 0>;
	phy-names = "usb";
	status = "okay";
	};

	&ehci1 {
	status = "okay";
	};

	+&mixer0 {
	+ status = "okay";
	+};
	+
	&mmc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	vmmc-supply = <&reg_dcdc1>;
	- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
	+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
	disable-wp;
	bus-width = <4>;
	status = "okay";
	};

	&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	vmmc-supply = <&reg_dldo4>;
	vqmmc-supply = <&reg_eldo1>;
	mmc-pwrseq = <&wifi_pwrseq>;
	bus-width = <4>;
	non-removable;
	status = "okay";

	rtl8723cs: wifi@1 {
	reg = <1>;
	};
	};

	&mmc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>;
	vmmc-supply = <&reg_dcdc1>;
	vqmmc-supply = <&reg_eldo1>;
	bus-width = <8>;
	non-removable;
	cap-mmc-hw-reset;
	mmc-hs200-1_8v;
	status = "okay";
	};

	&ohci0 {
	phys = <&usbphy 0>;
	phy-names = "usb";
	status = "okay";
	};

	&ohci1 {
	status = "okay";
	};

	+&pio {
	+ vcc-pc-supply = <&reg_eldo1>;
	+ vcc-pd-supply = <&reg_dcdc1>;
	+ vcc-pe-supply = <&reg_aldo1>;
	+ vcc-pg-supply = <&reg_eldo1>;
	+};
	+
	&pwm {
	status = "okay";
	};

	+&r_i2c {
	+ clock-frequency = <100000>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&r_i2c_pl89_pins>;
	+ status = "okay";
	+
	+ anx6345: anx6345@38 {
	+ compatible = "analogix,anx6345";
	+ reg = <0x38>;
	+ reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
	+ dvdd25-supply = <&reg_dldo2>;
	+ dvdd12-supply = <&reg_fldo1>;
	+
	+ ports {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ anx6345_in: port@0 {
	+ reg = <0>;
	+ anx6345_in_tcon0: endpoint {
	+ remote-endpoint = <&tcon0_out_anx6345>;
	+ };
	+ };
	+
	+ anx6345_out: port@1 {
	+ reg = <1>;
	+ anx6345_out_edp: endpoint {
	+ remote-endpoint = <&panel_edp_in>;
	+ };
	+ };
	+ };
	+ };
	+};
	+
	+&r_pio {
	+ /*
	+ * FIXME: We can't add that supply for now since it would
	+ * create a circular dependency between pinctrl, the regulator
	+ * and the RSB Bus.
	+ *
	+ * vcc-pl-supply = <&reg_aldo2>;
	+ */
	+};
	+
	&r_rsb {
	status = "okay";

	axp803: pmic@3a3 {
	compatible = "x-powers,axp803";
	reg = <0x3a3>;
	interrupt-parent = <&r_intc>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	};
	};

	-/* The ANX6345 eDP-bridge is on r_i2c */
	-&r_i2c {
	- clock-frequency = <100000>;
	- pinctrl-names = "default";
	- pinctrl-0 = <&r_i2c_pl89_pins>;
	- status = "okay";
	-};
	-
	#include "axp803.dtsi"

	&ac_power_supply {
	status = "okay";
	};

	&battery_power_supply {
	status = "okay";
	};

	&reg_aldo1 {
	- regulator-min-microvolt = <2800000>;
	- regulator-max-microvolt = <2800000>;
	- regulator-name = "vcc-csi";
	+ regulator-name = "vcc-pe";
	};

	&reg_aldo2 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-pl";
	};

	&reg_aldo3 {
	regulator-always-on;
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-pll-avcc";
	};

	&reg_dc1sw {
	regulator-name = "vcc-lcd";
	};

	&reg_dcdc1 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-3v3";
	};

	&reg_dcdc2 {
	regulator-always-on;
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1300000>;
	regulator-name = "vdd-cpux";
	};

	/* DCDC3 is polyphased with DCDC2 */

	&reg_dcdc5 {
	regulator-always-on;
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-name = "vcc-dram";
	};

	&reg_dcdc6 {
	regulator-always-on;
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-name = "vdd-sys";
	};

	&reg_dldo1 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-hdmi";
	};

	&reg_dldo2 {
	regulator-min-microvolt = <2500000>;
	regulator-max-microvolt = <2500000>;
	regulator-name = "vcc-edp";
	};

	-&reg_dldo3 {
	- regulator-min-microvolt = <3300000>;
	- regulator-max-microvolt = <3300000>;
	- regulator-name = "avdd-csi";
	-};
	-
	&reg_dldo4 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-wifi";
	};

	&reg_eldo1 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "cpvdd";
	};

	-&reg_eldo3 {
	- regulator-min-microvolt = <1800000>;
	- regulator-max-microvolt = <1800000>;
	- regulator-name = "vdd-1v8-csi";
	-};
	-
	&reg_fldo1 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-name = "vcc-1v2-hsic";
	};

	&reg_fldo2 {
	regulator-always-on;
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-name = "vdd-cpus";
	};

	-&reg_ldo_io0 {
	- regulator-min-microvolt = <3300000>;
	- regulator-max-microvolt = <3300000>;
	- regulator-name = "vcc-usb";
	- status = "okay";
	-};
	-
	&reg_rtc_ldo {
	regulator-name = "vcc-rtc";
	};

	+&simplefb_lcd {
	+ panel-supply = <&reg_dc1sw>;
	+ dvdd25-supply = <&reg_dldo2>;
	+ dvdd12-supply = <&reg_fldo1>;
	+};
	+
	&simplefb_hdmi {
	vcc-hdmi-supply = <&reg_dldo1>;
	};

	&sound {
	status = "okay";
	simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
	simple-audio-card,widgets = "Microphone", "Internal Microphone Left",
	"Microphone", "Internal Microphone Right",
	"Headphone", "Headphone Jack",
	"Speaker", "Internal Speaker";
	simple-audio-card,routing =
	"Left DAC", "AIF1 Slot 0 Left",
	"Right DAC", "AIF1 Slot 0 Right",
	"Speaker Amp INL", "LINEOUT",
	"Speaker Amp INR", "LINEOUT",
	"Internal Speaker", "Speaker Amp OUTL",
	"Internal Speaker", "Speaker Amp OUTR",
	"Headphone Jack", "HP",
	"AIF1 Slot 0 Left ADC", "Left ADC",
	"AIF1 Slot 0 Right ADC", "Right ADC",
	"Internal Microphone Left", "MBIAS",
	"MIC1", "Internal Microphone Left",
	"Internal Microphone Right", "HBIAS",
	"MIC2", "Internal Microphone Right";
	};

	+&tcon0 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&lcd_rgb666_pins>;
	+
	+ status = "okay";
	+};
	+
	+&tcon0_out {
	+ tcon0_out_anx6345: endpoint {
	+ remote-endpoint = <&anx6345_in_tcon0>;
	+ };
	+};
	+
	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pb_pins>;
	status = "okay";
	};

	&usb_otg {
	dr_mode = "host";
	};

	&usbphy {
	- usb0_vbus-supply = <&reg_ldo_io0>;
	- usb1_vbus-supply = <&reg_ldo_io0>;
	+ usb0_vbus-supply = <&reg_vcc5v0>;
	+ usb1_vbus-supply = <&reg_vcc5v0>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinephone-1.0.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinephone-1.0.dts
	new file mode 100644
	index 000000000000..0c42272106af
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinephone-1.0.dts
	@@ -0,0 +1,11 @@
	+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	+// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
	+
	+/dts-v1/;
	+
	+#include "sun50i-a64-pinephone.dtsi"
	+
	+/ {
	+ model = "Pine64 PinePhone Developer Batch (1.0)";
	+ compatible = "pine64,pinephone-1.0", "allwinner,sun50i-a64";
	+};
	diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinephone-1.1.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinephone-1.1.dts
	new file mode 100644
	index 000000000000..06a775c41664
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinephone-1.1.dts
	@@ -0,0 +1,11 @@
	+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	+// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
	+
	+/dts-v1/;
	+
	+#include "sun50i-a64-pinephone.dtsi"
	+
	+/ {
	+ model = "Pine64 PinePhone Braveheart (1.1)";
	+ compatible = "pine64,pinephone-1.1", "allwinner,sun50i-a64";
	+};
	diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinebook.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinephone.dtsi
	similarity index 55%
	copy from sys/gnu/dts/arm64/allwinner/sun50i-a64-pinebook.dts
	copy to sys/gnu/dts/arm64/allwinner/sun50i-a64-pinephone.dtsi
	index 3d894b208901..cefda145c3c9 100644
	--- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinebook.dts
	+++ b/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinephone.dtsi
	@@ -1,367 +1,379 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	-// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
	-// Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>
	-
	-/dts-v1/;
	+// Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.xyz>
	+// Copyright (C) 2020 Martijn Braam <martijn@brixit.nl>
	+// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>

	#include "sun50i-a64.dtsi"
	#include "sun50i-a64-cpu-opp.dtsi"

	#include <dt-bindings/gpio/gpio.h>
	-#include <dt-bindings/input/gpio-keys.h>
	#include <dt-bindings/input/input.h>
	+#include <dt-bindings/leds/common.h>
	#include <dt-bindings/pwm/pwm.h>

	/ {
	- model = "Pinebook";
	- compatible = "pine64,pinebook", "allwinner,sun50i-a64";
	-
	aliases {
	serial0 = &uart0;
	- ethernet0 = &rtl8723cs;
	- };
	-
	- vdd_bl: regulator@0 {
	- compatible = "regulator-fixed";
	- regulator-name = "bl-3v3";
	- regulator-min-microvolt = <3300000>;
	- regulator-max-microvolt = <3300000>;
	- gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
	- enable-active-high;
	- };
	-
	- backlight: backlight {
	- compatible = "pwm-backlight";
	- pwms = <&pwm 0 50000 0>;
	- brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
	- default-brightness-level = <2>;
	- enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
	- power-supply = <&vdd_bl>;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	-
	- framebuffer-lcd {
	- panel-supply = <&reg_dc1sw>;
	- dvdd25-supply = <&reg_dldo2>;
	- dvdd12-supply = <&reg_fldo1>;
	- };
	};

	- gpio_keys {
	- compatible = "gpio-keys";
	-
	- lid_switch {
	- label = "Lid Switch";
	- gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */
	- linux,input-type = <EV_SW>;
	- linux,code = <SW_LID>;
	- linux,can-disable;
	- wakeup-source;
	- wakeup-event-action = <EV_ACT_DEASSERTED>;
	+ leds {
	+ compatible = "gpio-leds";
	+
	+ blue {
	+ function = LED_FUNCTION_INDICATOR;
	+ color = <LED_COLOR_ID_BLUE>;
	+ gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
	};
	- };

	- reg_vcc3v3: vcc3v3 {
	- compatible = "regulator-fixed";
	- regulator-name = "vcc3v3";
	- regulator-min-microvolt = <3300000>;
	- regulator-max-microvolt = <3300000>;
	- };
	+ green {
	+ function = LED_FUNCTION_INDICATOR;
	+ color = <LED_COLOR_ID_GREEN>;
	+ gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */
	+ };

	- wifi_pwrseq: wifi_pwrseq {
	- compatible = "mmc-pwrseq-simple";
	- reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
	+ red {
	+ function = LED_FUNCTION_INDICATOR;
	+ color = <LED_COLOR_ID_RED>;
	+ gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
	+ };
	};

	speaker_amp: audio-amplifier {
	compatible = "simple-audio-amplifier";
	- /*
	- * TODO This is actually a fixed regulator controlled by
	- * the GPIO line on the PMIC. This should be corrected
	- * once GPIO support is added for this PMIC.
	- */
	- VCC-supply = <&reg_ldo_io0>;
	- enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
	+ enable-gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */
	sound-name-prefix = "Speaker Amp";
	};

	+ vibrator {
	+ compatible = "gpio-vibrator";
	+ enable-gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
	+ vcc-supply = <&reg_dcdc1>;
	+ };
	};

	&codec {
	status = "okay";
	};

	&codec_analog {
	cpvdd-supply = <&reg_eldo1>;
	status = "okay";
	};

	&cpu0 {
	cpu-supply = <&reg_dcdc2>;
	};

	&cpu1 {
	cpu-supply = <&reg_dcdc2>;
	};

	&cpu2 {
	cpu-supply = <&reg_dcdc2>;
	};

	&cpu3 {
	cpu-supply = <&reg_dcdc2>;
	};

	&dai {
	status = "okay";
	};

	&ehci0 {
	- phys = <&usbphy 0>;
	- phy-names = "usb";
	status = "okay";
	};

	&ehci1 {
	status = "okay";
	};

	+&i2c1 {
	+ status = "okay";
	+
	+ /* Magnetometer */
	+ lis3mdl@1e {
	+ compatible = "st,lis3mdl-magn";
	+ reg = <0x1e>;
	+ vdd-supply = <&reg_dldo1>;
	+ vddio-supply = <&reg_dldo1>;
	+ };
	+
	+ /* Accelerometer/gyroscope */
	+ mpu6050@68 {
	+ compatible = "invensense,mpu6050";
	+ reg = <0x68>;
	+ interrupt-parent = <&pio>;
	+ interrupts = <7 5 IRQ_TYPE_EDGE_RISING>; /* PH5 */
	+ vdd-supply = <&reg_dldo1>;
	+ vddio-supply = <&reg_dldo1>;
	+ };
	+};
	+
	+/* Connected to pogo pins (external spring based pinheader for user addons) */
	+&i2c2 {
	+ status = "okay";
	+};
	+
	+&lradc {
	+ vref-supply = <&reg_aldo3>;
	+ status = "okay";
	+
	+ button-200 {
	+ label = "Volume Up";
	+ linux,code = <KEY_VOLUMEUP>;
	+ channel = <0>;
	+ voltage = <200000>;
	+ };
	+
	+ button-400 {
	+ label = "Volume Down";
	+ linux,code = <KEY_VOLUMEDOWN>;
	+ channel = <0>;
	+ voltage = <400000>;
	+ };
	+};
	+
	&mmc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	vmmc-supply = <&reg_dcdc1>;
	- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
	+ vqmmc-supply = <&reg_dcdc1>;
	+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
	disable-wp;
	bus-width = <4>;
	status = "okay";
	};

	-&mmc1 {
	- pinctrl-names = "default";
	- pinctrl-0 = <&mmc1_pins>;
	- vmmc-supply = <&reg_dldo4>;
	- vqmmc-supply = <&reg_eldo1>;
	- mmc-pwrseq = <&wifi_pwrseq>;
	- bus-width = <4>;
	- non-removable;
	- status = "okay";
	-
	- rtl8723cs: wifi@1 {
	- reg = <1>;
	- };
	-};
	-
	&mmc2 {
	pinctrl-names = "default";
	- pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>;
	+ pinctrl-0 = <&mmc2_pins>;
	vmmc-supply = <&reg_dcdc1>;
	- vqmmc-supply = <&reg_eldo1>;
	+ vqmmc-supply = <&reg_dcdc1>;
	bus-width = <8>;
	non-removable;
	cap-mmc-hw-reset;
	- mmc-hs200-1_8v;
	status = "okay";
	};

	&ohci0 {
	- phys = <&usbphy 0>;
	- phy-names = "usb";
	status = "okay";
	};

	&ohci1 {
	status = "okay";
	};

	-&pwm {
	- status = "okay";
	+&pio {
	+ vcc-pb-supply = <&reg_dcdc1>;
	+ vcc-pc-supply = <&reg_dcdc1>;
	+ vcc-pd-supply = <&reg_dcdc1>;
	+ vcc-pe-supply = <&reg_aldo1>;
	+ vcc-pf-supply = <&reg_dcdc1>;
	+ vcc-pg-supply = <&reg_dldo4>;
	+ vcc-ph-supply = <&reg_dcdc1>;
	+};
	+
	+&r_pio {
	+ /*
	+ * FIXME: We can't add that supply for now since it would
	+ * create a circular dependency between pinctrl, the regulator
	+ * and the RSB Bus.
	+ *
	+ * vcc-pl-supply = <&reg_aldo2>;
	+ */
	};

	&r_rsb {
	status = "okay";

	axp803: pmic@3a3 {
	compatible = "x-powers,axp803";
	reg = <0x3a3>;
	interrupt-parent = <&r_intc>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	};
	};

	-/* The ANX6345 eDP-bridge is on r_i2c */
	-&r_i2c {
	- clock-frequency = <100000>;
	- pinctrl-names = "default";
	- pinctrl-0 = <&r_i2c_pl89_pins>;
	- status = "okay";
	-};
	-
	#include "axp803.dtsi"

	&ac_power_supply {
	status = "okay";
	};

	&battery_power_supply {
	status = "okay";
	};

	&reg_aldo1 {
	- regulator-min-microvolt = <2800000>;
	- regulator-max-microvolt = <2800000>;
	- regulator-name = "vcc-csi";
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+ regulator-name = "dovdd-csi";
	};

	&reg_aldo2 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	- regulator-max-microvolt = <3300000>;
	+ regulator-max-microvolt = <1800000>;
	regulator-name = "vcc-pl";
	};

	&reg_aldo3 {
	regulator-always-on;
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-pll-avcc";
	};

	-&reg_dc1sw {
	- regulator-name = "vcc-lcd";
	-};
	-
	&reg_dcdc1 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-3v3";
	};

	&reg_dcdc2 {
	regulator-always-on;
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1300000>;
	regulator-name = "vdd-cpux";
	};

	/* DCDC3 is polyphased with DCDC2 */

	&reg_dcdc5 {
	regulator-always-on;
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-name = "vcc-dram";
	};

	&reg_dcdc6 {
	regulator-always-on;
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-name = "vdd-sys";
	};

	&reg_dldo1 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	- regulator-name = "vcc-hdmi";
	+ regulator-name = "vcc-dsi-sensor";
	};

	&reg_dldo2 {
	- regulator-min-microvolt = <2500000>;
	- regulator-max-microvolt = <2500000>;
	- regulator-name = "vcc-edp";
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+ regulator-name = "vcc-mipi-io";
	};

	&reg_dldo3 {
	- regulator-min-microvolt = <3300000>;
	- regulator-max-microvolt = <3300000>;
	+ regulator-min-microvolt = <2800000>;
	+ regulator-max-microvolt = <2800000>;
	regulator-name = "avdd-csi";
	};

	&reg_dldo4 {
	- regulator-min-microvolt = <3300000>;
	+ regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	- regulator-name = "vcc-wifi";
	+ regulator-name = "vcc-wifi-io";
	};

	&reg_eldo1 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	- regulator-name = "cpvdd";
	+ regulator-name = "vcc-lpddr";
	};

	&reg_eldo3 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	- regulator-name = "vdd-1v8-csi";
	+ regulator-name = "dvdd-1v8-csi";
	};

	&reg_fldo1 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-name = "vcc-1v2-hsic";
	};

	&reg_fldo2 {
	regulator-always-on;
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-name = "vdd-cpus";
	};

	&reg_ldo_io0 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	- regulator-name = "vcc-usb";
	+ regulator-name = "vcc-lcd-ctp-stk";
	status = "okay";
	};

	-&reg_rtc_ldo {
	- regulator-name = "vcc-rtc";
	+&reg_ldo_io1 {
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+ regulator-name = "vcc-1v8-typec";
	+ status = "okay";
	};

	-&simplefb_hdmi {
	- vcc-hdmi-supply = <&reg_dldo1>;
	+&reg_rtc_ldo {
	+ regulator-name = "vcc-rtc";
	};

	&sound {
	status = "okay";
	simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
	- simple-audio-card,widgets = "Microphone", "Internal Microphone Left",
	- "Microphone", "Internal Microphone Right",
	+ simple-audio-card,widgets = "Microphone", "Headset Microphone",
	+ "Microphone", "Internal Microphone",
	"Headphone", "Headphone Jack",
	+ "Speaker", "Internal Earpiece",
	"Speaker", "Internal Speaker";
	simple-audio-card,routing =
	- "Left DAC", "AIF1 Slot 0 Left",
	- "Right DAC", "AIF1 Slot 0 Right",
	- "Speaker Amp INL", "LINEOUT",
	- "Speaker Amp INR", "LINEOUT",
	+ "Headphone Jack", "HP",
	+ "Internal Earpiece", "EARPIECE",
	"Internal Speaker", "Speaker Amp OUTL",
	"Internal Speaker", "Speaker Amp OUTR",
	- "Headphone Jack", "HP",
	+ "Speaker Amp INL", "LINEOUT",
	+ "Speaker Amp INR", "LINEOUT",
	+ "Left DAC", "AIF1 Slot 0 Left",
	+ "Right DAC", "AIF1 Slot 0 Right",
	"AIF1 Slot 0 Left ADC", "Left ADC",
	"AIF1 Slot 0 Right ADC", "Right ADC",
	- "Internal Microphone Left", "MBIAS",
	- "MIC1", "Internal Microphone Left",
	- "Internal Microphone Right", "HBIAS",
	- "MIC2", "Internal Microphone Right";
	+ "Internal Microphone", "MBIAS",
	+ "MIC1", "Internal Microphone",
	+ "Headset Microphone", "HBIAS",
	+ "MIC2", "Headset Microphone";
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pb_pins>;
	status = "okay";
	};

	+/* Connected to the modem (hardware flow control can't be used) */
	+&uart3 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&uart3_pins>;
	+ status = "okay";
	+};
	+
	&usb_otg {
	- dr_mode = "host";
	+ dr_mode = "peripheral";
	+ status = "okay";
	+};
	+
	+&usb_power_supply {
	+ status = "okay";
	};

	&usbphy {
	- usb0_vbus-supply = <&reg_ldo_io0>;
	- usb1_vbus-supply = <&reg_ldo_io0>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinebook.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinetab.dts
	similarity index 61%
	copy from sys/gnu/dts/arm64/allwinner/sun50i-a64-pinebook.dts
	copy to sys/gnu/dts/arm64/allwinner/sun50i-a64-pinetab.dts
	index 3d894b208901..dc4ab6b434f9 100644
	--- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinebook.dts
	+++ b/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinetab.dts
	@@ -1,367 +1,460 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	-// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
	-// Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>
	+/*
	+ * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.xyz>
	+ *
	+ */

	/dts-v1/;

	#include "sun50i-a64.dtsi"
	#include "sun50i-a64-cpu-opp.dtsi"

	#include <dt-bindings/gpio/gpio.h>
	-#include <dt-bindings/input/gpio-keys.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/pwm/pwm.h>

	/ {
	- model = "Pinebook";
	- compatible = "pine64,pinebook", "allwinner,sun50i-a64";
	+ model = "PineTab";
	+ compatible = "pine64,pinetab", "allwinner,sun50i-a64";

	aliases {
	serial0 = &uart0;
	ethernet0 = &rtl8723cs;
	};

	- vdd_bl: regulator@0 {
	- compatible = "regulator-fixed";
	- regulator-name = "bl-3v3";
	- regulator-min-microvolt = <3300000>;
	- regulator-max-microvolt = <3300000>;
	- gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
	- enable-active-high;
	- };
	-
	backlight: backlight {
	compatible = "pwm-backlight";
	- pwms = <&pwm 0 50000 0>;
	- brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
	- default-brightness-level = <2>;
	+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
	+ brightness-levels = <0 16 18 20 22 24 26 29 32 35 38 42 46 51 56 62 68 75 83 91 100>;
	+ default-brightness-level = <15>;
	enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
	power-supply = <&vdd_bl>;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	+ };

	- framebuffer-lcd {
	- panel-supply = <&reg_dc1sw>;
	- dvdd25-supply = <&reg_dldo2>;
	- dvdd12-supply = <&reg_fldo1>;
	+ i2c-csi {
	+ compatible = "i2c-gpio";
	+ sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; /* PE13 */
	+ scl-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */
	+ i2c-gpio,delay-us = <5>;
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ /* Rear camera */
	+ ov5640: camera@3c {
	+ compatible = "ovti,ov5640";
	+ reg = <0x3c>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&csi_mclk_pin>;
	+ clocks = <&ccu CLK_CSI_MCLK>;
	+ clock-names = "xclk";
	+
	+ AVDD-supply = <&reg_dldo3>;
	+ DOVDD-supply = <&reg_aldo1>;
	+ DVDD-supply = <&reg_eldo3>;
	+ reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* PE14 */
	+ powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */
	+
	+ port {
	+ ov5640_ep: endpoint {
	+ remote-endpoint = <&csi_ep>;
	+ bus-width = <8>;
	+ hsync-active = <1>; /* Active high */
	+ vsync-active = <0>; /* Active low */
	+ data-active = <1>; /* Active high */
	+ pclk-sample = <1>; /* Rising */
	+ };
	+ };
	};
	};

	- gpio_keys {
	- compatible = "gpio-keys";
	-
	- lid_switch {
	- label = "Lid Switch";
	- gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */
	- linux,input-type = <EV_SW>;
	- linux,code = <SW_LID>;
	- linux,can-disable;
	- wakeup-source;
	- wakeup-event-action = <EV_ACT_DEASSERTED>;
	- };
	+ speaker_amp: audio-amplifier {
	+ compatible = "simple-audio-amplifier";
	+ enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
	+ sound-name-prefix = "Speaker Amp";
	};

	- reg_vcc3v3: vcc3v3 {
	+ vdd_bl: regulator@0 {
	compatible = "regulator-fixed";
	- regulator-name = "vcc3v3";
	+ regulator-name = "bl-3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	+ gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
	+ enable-active-high;
	};

	wifi_pwrseq: wifi_pwrseq {
	compatible = "mmc-pwrseq-simple";
	reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
	+ post-power-on-delay-ms = <200>;
	};
	-
	- speaker_amp: audio-amplifier {
	- compatible = "simple-audio-amplifier";
	- /*
	- * TODO This is actually a fixed regulator controlled by
	- * the GPIO line on the PMIC. This should be corrected
	- * once GPIO support is added for this PMIC.
	- */
	- VCC-supply = <&reg_ldo_io0>;
	- enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
	- sound-name-prefix = "Speaker Amp";
	- };
	-
	};

	&codec {
	status = "okay";
	};

	&codec_analog {
	cpvdd-supply = <&reg_eldo1>;
	status = "okay";
	};

	&cpu0 {
	cpu-supply = <&reg_dcdc2>;
	};

	&cpu1 {
	cpu-supply = <&reg_dcdc2>;
	};

	&cpu2 {
	cpu-supply = <&reg_dcdc2>;
	};

	&cpu3 {
	cpu-supply = <&reg_dcdc2>;
	};

	+&csi {
	+ status = "okay";
	+
	+ port {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ csi_ep: endpoint {
	+ remote-endpoint = <&ov5640_ep>;
	+ bus-width = <8>;
	+ hsync-active = <1>; /* Active high */
	+ vsync-active = <0>; /* Active low */
	+ data-active = <1>; /* Active high */
	+ pclk-sample = <1>; /* Rising */
	+ };
	+ };
	+};
	+
	&dai {
	status = "okay";
	};

	+&de {
	+ status = "okay";
	+};
	+
	+&dphy {
	+ status = "okay";
	+};
	+
	+&dsi {
	+ vcc-dsi-supply = <&reg_dldo1>;
	+ status = "okay";
	+
	+ panel@0 {
	+ compatible = "feixin,k101-im2ba02";
	+ reg = <0>;
	+ avdd-supply = <&reg_dc1sw>;
	+ dvdd-supply = <&reg_dc1sw>;
	+ cvdd-supply = <&reg_ldo_io1>;
	+ reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
	+ backlight = <&backlight>;
	+ };
	+};
	+
	&ehci0 {
	- phys = <&usbphy 0>;
	- phy-names = "usb";
	status = "okay";
	};

	&ehci1 {
	status = "okay";
	};

	+&i2c0 {
	+ status = "okay";
	+
	+ touchscreen@5d {
	+ compatible = "goodix,gt9271";
	+ reg = <0x5d>;
	+ interrupt-parent = <&pio>;
	+ interrupts = <7 4 IRQ_TYPE_LEVEL_HIGH>; /* PH4 */
	+ irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
	+ reset-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
	+ AVDD28-supply = <&reg_ldo_io1>;
	+ };
	+};
	+
	+&i2c0_pins {
	+ bias-pull-up;
	+};
	+
	+&i2c1 {
	+ status = "okay";
	+
	+ /* TODO: add Bochs BMA223 accelerometer here */
	+};
	+
	+&lradc {
	+ vref-supply = <&reg_aldo3>;
	+ status = "okay";
	+
	+ button-200 {
	+ label = "Volume Up";
	+ linux,code = <KEY_VOLUMEUP>;
	+ channel = <0>;
	+ voltage = <200000>;
	+ };
	+
	+ button-400 {
	+ label = "Volume Down";
	+ linux,code = <KEY_VOLUMEDOWN>;
	+ channel = <0>;
	+ voltage = <400000>;
	+ };
	+};
	+
	+&mixer1 {
	+ status = "okay";
	+};
	+
	&mmc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	vmmc-supply = <&reg_dcdc1>;
	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
	disable-wp;
	bus-width = <4>;
	status = "okay";
	};

	&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	vmmc-supply = <&reg_dldo4>;
	vqmmc-supply = <&reg_eldo1>;
	mmc-pwrseq = <&wifi_pwrseq>;
	bus-width = <4>;
	non-removable;
	status = "okay";

	rtl8723cs: wifi@1 {
	reg = <1>;
	};
	};

	&mmc2 {
	pinctrl-names = "default";
	- pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>;
	+ pinctrl-0 = <&mmc2_pins>;
	vmmc-supply = <&reg_dcdc1>;
	- vqmmc-supply = <&reg_eldo1>;
	+ vqmmc-supply = <&reg_dcdc1>;
	bus-width = <8>;
	non-removable;
	cap-mmc-hw-reset;
	- mmc-hs200-1_8v;
	status = "okay";
	};

	&ohci0 {
	- phys = <&usbphy 0>;
	- phy-names = "usb";
	- status = "okay";
	-};
	-
	-&ohci1 {
	status = "okay";
	};

	&pwm {
	status = "okay";
	};

	&r_rsb {
	status = "okay";

	axp803: pmic@3a3 {
	compatible = "x-powers,axp803";
	reg = <0x3a3>;
	interrupt-parent = <&r_intc>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	+ x-powers,drive-vbus-en;
	};
	};

	-/* The ANX6345 eDP-bridge is on r_i2c */
	-&r_i2c {
	- clock-frequency = <100000>;
	- pinctrl-names = "default";
	- pinctrl-0 = <&r_i2c_pl89_pins>;
	- status = "okay";
	-};
	-
	#include "axp803.dtsi"

	&ac_power_supply {
	status = "okay";
	};

	&battery_power_supply {
	status = "okay";
	};

	&reg_aldo1 {
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	- regulator-name = "vcc-csi";
	+ regulator-name = "dovdd-csi";
	};

	&reg_aldo2 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-pl";
	};

	&reg_aldo3 {
	regulator-always-on;
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-pll-avcc";
	};

	&reg_dc1sw {
	regulator-name = "vcc-lcd";
	};

	&reg_dcdc1 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-3v3";
	};

	&reg_dcdc2 {
	regulator-always-on;
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1300000>;
	regulator-name = "vdd-cpux";
	};

	/* DCDC3 is polyphased with DCDC2 */

	&reg_dcdc5 {
	regulator-always-on;
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-name = "vcc-dram";
	};

	&reg_dcdc6 {
	regulator-always-on;
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-name = "vdd-sys";
	};

	&reg_dldo1 {
	+ regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	- regulator-name = "vcc-hdmi";
	-};
	-
	-&reg_dldo2 {
	- regulator-min-microvolt = <2500000>;
	- regulator-max-microvolt = <2500000>;
	- regulator-name = "vcc-edp";
	+ regulator-name = "vcc-hdmi-dsi-sensor";
	};

	&reg_dldo3 {
	- regulator-min-microvolt = <3300000>;
	- regulator-max-microvolt = <3300000>;
	+ regulator-min-microvolt = <2800000>;
	+ regulator-max-microvolt = <2800000>;
	regulator-name = "avdd-csi";
	};

	&reg_dldo4 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-wifi";
	};

	+&reg_drivevbus {
	+ regulator-name = "usb0-vbus";
	+ status = "okay";
	+};
	+
	&reg_eldo1 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "cpvdd";
	};

	+&reg_eldo2 {
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+ regulator-name = "vcca-1v8";
	+};
	+
	&reg_eldo3 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	- regulator-name = "vdd-1v8-csi";
	+ regulator-name = "dvdd-1v8-csi";
	};

	&reg_fldo1 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-name = "vcc-1v2-hsic";
	};

	&reg_fldo2 {
	regulator-always-on;
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-name = "vdd-cpus";
	};

	&reg_ldo_io0 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-usb";
	status = "okay";
	};

	-&reg_rtc_ldo {
	- regulator-name = "vcc-rtc";
	+&reg_ldo_io1 {
	+ regulator-min-microvolt = <3300000>;
	+ regulator-max-microvolt = <3300000>;
	+ regulator-enable-ramp-delay = <3500000>;
	+ regulator-name = "vcc-touchscreen";
	+ status = "okay";
	};

	-&simplefb_hdmi {
	- vcc-hdmi-supply = <&reg_dldo1>;
	+&reg_rtc_ldo {
	+ regulator-name = "vcc-rtc";
	};

	&sound {
	status = "okay";
	simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
	simple-audio-card,widgets = "Microphone", "Internal Microphone Left",
	"Microphone", "Internal Microphone Right",
	"Headphone", "Headphone Jack",
	"Speaker", "Internal Speaker";
	simple-audio-card,routing =
	"Left DAC", "AIF1 Slot 0 Left",
	"Right DAC", "AIF1 Slot 0 Right",
	"Speaker Amp INL", "LINEOUT",
	"Speaker Amp INR", "LINEOUT",
	"Internal Speaker", "Speaker Amp OUTL",
	"Internal Speaker", "Speaker Amp OUTR",
	"Headphone Jack", "HP",
	"AIF1 Slot 0 Left ADC", "Left ADC",
	"AIF1 Slot 0 Right ADC", "Right ADC",
	"Internal Microphone Left", "MBIAS",
	"MIC1", "Internal Microphone Left",
	"Internal Microphone Right", "HBIAS",
	"MIC2", "Internal Microphone Right";
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pb_pins>;
	status = "okay";
	};

	&usb_otg {
	- dr_mode = "host";
	+ dr_mode = "otg";
	+ status = "okay";
	+};
	+
	+&usb_power_supply {
	+ status = "okay";
	};

	&usbphy {
	- usb0_vbus-supply = <&reg_ldo_io0>;
	+ usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
	+ usb0_vbus_power-supply = <&usb_power_supply>;
	+ usb0_vbus-supply = <&reg_drivevbus>;
	usb1_vbus-supply = <&reg_ldo_io0>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64.dtsi b/sys/gnu/dts/arm64/allwinner/sun50i-a64.dtsi
	index 862b47dc9dc9..c26cc1fcaffd 100644
	--- a/sys/gnu/dts/arm64/allwinner/sun50i-a64.dtsi
	+++ b/sys/gnu/dts/arm64/allwinner/sun50i-a64.dtsi
	@@ -1,1279 +1,1301 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	// Copyright (C) 2016 ARM Ltd.
	// based on the Allwinner H3 dtsi:
	// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>

	#include <dt-bindings/clock/sun50i-a64-ccu.h>
	#include <dt-bindings/clock/sun8i-de2.h>
	#include <dt-bindings/clock/sun8i-r-ccu.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/reset/sun50i-a64-ccu.h>
	#include <dt-bindings/reset/sun8i-de2.h>
	#include <dt-bindings/reset/sun8i-r-ccu.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	chosen {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	simplefb_lcd: framebuffer-lcd {
	compatible = "allwinner,simple-framebuffer",
	"simple-framebuffer";
	allwinner,pipeline = "mixer0-lcd0";
	clocks = <&ccu CLK_TCON0>,
	<&display_clocks CLK_MIXER0>;
	status = "disabled";
	};

	simplefb_hdmi: framebuffer-hdmi {
	compatible = "allwinner,simple-framebuffer",
	"simple-framebuffer";
	allwinner,pipeline = "mixer1-lcd1-hdmi";
	clocks = <&display_clocks CLK_MIXER1>,
	<&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
	status = "disabled";
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a53";
	device_type = "cpu";
	reg = <0>;
	enable-method = "psci";
	next-level-cache = <&L2>;
	clocks = <&ccu 21>;
	clock-names = "cpu";
	#cooling-cells = <2>;
	};

	cpu1: cpu@1 {
	compatible = "arm,cortex-a53";
	device_type = "cpu";
	reg = <1>;
	enable-method = "psci";
	next-level-cache = <&L2>;
	clocks = <&ccu 21>;
	clock-names = "cpu";
	#cooling-cells = <2>;
	};

	cpu2: cpu@2 {
	compatible = "arm,cortex-a53";
	device_type = "cpu";
	reg = <2>;
	enable-method = "psci";
	next-level-cache = <&L2>;
	clocks = <&ccu 21>;
	clock-names = "cpu";
	#cooling-cells = <2>;
	};

	cpu3: cpu@3 {
	compatible = "arm,cortex-a53";
	device_type = "cpu";
	reg = <3>;
	enable-method = "psci";
	next-level-cache = <&L2>;
	clocks = <&ccu 21>;
	clock-names = "cpu";
	#cooling-cells = <2>;
	};

	L2: l2-cache {
	compatible = "cache";
	cache-level = <2>;
	};
	};

	de: display-engine {
	compatible = "allwinner,sun50i-a64-display-engine";
	allwinner,pipelines = <&mixer0>,
	<&mixer1>;
	status = "disabled";
	};

	osc24M: osc24M_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-output-names = "osc24M";
	};

	osc32k: osc32k_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	clock-output-names = "ext-osc32k";
	};

	pmu {
	compatible = "arm,cortex-a53-pmu";
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	sound: sound {
	compatible = "simple-audio-card";
	simple-audio-card,name = "sun50i-a64-audio";
	simple-audio-card,format = "i2s";
	simple-audio-card,frame-master = <&cpudai>;
	simple-audio-card,bitclock-master = <&cpudai>;
	simple-audio-card,mclk-fs = <128>;
	simple-audio-card,aux-devs = <&codec_analog>;
	simple-audio-card,routing =
	"Left DAC", "AIF1 Slot 0 Left",
	"Right DAC", "AIF1 Slot 0 Right",
	"AIF1 Slot 0 Left ADC", "Left ADC",
	"AIF1 Slot 0 Right ADC", "Right ADC";
	status = "disabled";

	cpudai: simple-audio-card,cpu {
	sound-dai = <&dai>;
	};

	link_codec: simple-audio-card,codec {
	sound-dai = <&codec>;
	};
	};

	- sound_spdif {
	- compatible = "simple-audio-card";
	- simple-audio-card,name = "On-board SPDIF";
	-
	- simple-audio-card,cpu {
	- sound-dai = <&spdif>;
	- };
	-
	- simple-audio-card,codec {
	- sound-dai = <&spdif_out>;
	- };
	- };
	-
	- spdif_out: spdif-out {
	- #sound-dai-cells = <0>;
	- compatible = "linux,spdif-dit";
	- };
	-
	timer {
	compatible = "arm,armv8-timer";
	allwinner,erratum-unknown1;
	interrupts = <GIC_PPI 13
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 14
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 11
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 10
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	thermal-zones {
	cpu_thermal: cpu0-thermal {
	/* milliseconds */
	polling-delay-passive = <0>;
	polling-delay = <0>;
	thermal-sensors = <&ths 0>;

	cooling-maps {
	map0 {
	trip = <&cpu_alert0>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu_alert1>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};

	trips {
	cpu_alert0: cpu_alert0 {
	/* milliCelsius */
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu_alert1: cpu_alert1 {
	/* milliCelsius */
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};

	cpu_crit: cpu_crit {
	/* milliCelsius */
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	gpu0_thermal: gpu0-thermal {
	/* milliseconds */
	polling-delay-passive = <0>;
	polling-delay = <0>;
	thermal-sensors = <&ths 1>;
	};

	gpu1_thermal: gpu1-thermal {
	/* milliseconds */
	polling-delay-passive = <0>;
	polling-delay = <0>;
	thermal-sensors = <&ths 2>;
	};
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	bus@1000000 {
	compatible = "allwinner,sun50i-a64-de2";
	reg = <0x1000000 0x400000>;
	allwinner,sram = <&de2_sram 1>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x1000000 0x400000>;

	display_clocks: clock@0 {
	compatible = "allwinner,sun50i-a64-de2-clk";
	- reg = <0x0 0x100000>;
	+ reg = <0x0 0x10000>;
	clocks = <&ccu CLK_BUS_DE>,
	<&ccu CLK_DE>;
	clock-names = "bus",
	"mod";
	resets = <&ccu RST_BUS_DE>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	+ rotate: rotate@20000 {
	+ compatible = "allwinner,sun50i-a64-de2-rotate",
	+ "allwinner,sun8i-a83t-de2-rotate";
	+ reg = <0x20000 0x10000>;
	+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&display_clocks CLK_BUS_ROT>,
	+ <&display_clocks CLK_ROT>;
	+ clock-names = "bus",
	+ "mod";
	+ resets = <&display_clocks RST_ROT>;
	+ };
	+
	mixer0: mixer@100000 {
	compatible = "allwinner,sun50i-a64-de2-mixer-0";
	reg = <0x100000 0x100000>;
	clocks = <&display_clocks CLK_BUS_MIXER0>,
	<&display_clocks CLK_MIXER0>;
	clock-names = "bus",
	"mod";
	resets = <&display_clocks RST_MIXER0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	mixer0_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	mixer0_out_tcon0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&tcon0_in_mixer0>;
	};

	mixer0_out_tcon1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&tcon1_in_mixer0>;
	};
	};
	};
	};

	mixer1: mixer@200000 {
	compatible = "allwinner,sun50i-a64-de2-mixer-1";
	reg = <0x200000 0x100000>;
	clocks = <&display_clocks CLK_BUS_MIXER1>,
	<&display_clocks CLK_MIXER1>;
	clock-names = "bus",
	"mod";
	resets = <&display_clocks RST_MIXER1>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	mixer1_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	mixer1_out_tcon0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&tcon0_in_mixer1>;
	};

	mixer1_out_tcon1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&tcon1_in_mixer1>;
	};
	};
	};
	};
	};

	syscon: syscon@1c00000 {
	compatible = "allwinner,sun50i-a64-system-control";
	reg = <0x01c00000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	sram_c: sram@18000 {
	compatible = "mmio-sram";
	reg = <0x00018000 0x28000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x00018000 0x28000>;

	de2_sram: sram-section@0 {
	compatible = "allwinner,sun50i-a64-sram-c";
	reg = <0x0000 0x28000>;
	};
	};

	sram_c1: sram@1d00000 {
	compatible = "mmio-sram";
	reg = <0x01d00000 0x40000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x01d00000 0x40000>;

	ve_sram: sram-section@0 {
	compatible = "allwinner,sun50i-a64-sram-c1",
	"allwinner,sun4i-a10-sram-c1";
	reg = <0x000000 0x40000>;
	};
	};
	};

	dma: dma-controller@1c02000 {
	compatible = "allwinner,sun50i-a64-dma";
	reg = <0x01c02000 0x1000>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_DMA>;
	dma-channels = <8>;
	dma-requests = <27>;
	resets = <&ccu RST_BUS_DMA>;
	#dma-cells = <1>;
	};

	tcon0: lcd-controller@1c0c000 {
	compatible = "allwinner,sun50i-a64-tcon-lcd",
	"allwinner,sun8i-a83t-tcon-lcd";
	reg = <0x01c0c000 0x1000>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
	clock-names = "ahb", "tcon-ch0";
	clock-output-names = "tcon-pixel-clock";
	#clock-cells = <0>;
	resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
	reset-names = "lcd", "lvds";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon0_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	tcon0_in_mixer0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&mixer0_out_tcon0>;
	};

	tcon0_in_mixer1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&mixer1_out_tcon0>;
	};
	};

	tcon0_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	tcon0_out_dsi: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&dsi_in_tcon0>;
	allwinner,tcon-channel = <1>;
	};
	};
	};
	};

	tcon1: lcd-controller@1c0d000 {
	compatible = "allwinner,sun50i-a64-tcon-tv",
	"allwinner,sun8i-a83t-tcon-tv";
	reg = <0x01c0d000 0x1000>;
	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
	clock-names = "ahb", "tcon-ch1";
	resets = <&ccu RST_BUS_TCON1>;
	reset-names = "lcd";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon1_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	tcon1_in_mixer0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&mixer0_out_tcon1>;
	};

	tcon1_in_mixer1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&mixer1_out_tcon1>;
	};
	};

	tcon1_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	tcon1_out_hdmi: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&hdmi_in_tcon1>;
	};
	};
	};
	};

	video-codec@1c0e000 {
	compatible = "allwinner,sun50i-a64-video-engine";
	reg = <0x01c0e000 0x1000>;
	clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
	<&ccu CLK_DRAM_VE>;
	clock-names = "ahb", "mod", "ram";
	resets = <&ccu RST_BUS_VE>;
	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	allwinner,sram = <&ve_sram 1>;
	};

	mmc0: mmc@1c0f000 {
	compatible = "allwinner,sun50i-a64-mmc";
	reg = <0x01c0f000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
	clock-names = "ahb", "mmc";
	resets = <&ccu RST_BUS_MMC0>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	max-frequency = <150000000>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc1: mmc@1c10000 {
	compatible = "allwinner,sun50i-a64-mmc";
	reg = <0x01c10000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
	clock-names = "ahb", "mmc";
	resets = <&ccu RST_BUS_MMC1>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	max-frequency = <150000000>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc2: mmc@1c11000 {
	compatible = "allwinner,sun50i-a64-emmc";
	reg = <0x01c11000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
	clock-names = "ahb", "mmc";
	resets = <&ccu RST_BUS_MMC2>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	max-frequency = <200000000>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	sid: eeprom@1c14000 {
	compatible = "allwinner,sun50i-a64-sid";
	reg = <0x1c14000 0x400>;
	#address-cells = <1>;
	#size-cells = <1>;

	ths_calibration: thermal-sensor-calibration@34 {
	reg = <0x34 0x8>;
	};
	};

	crypto: crypto@1c15000 {
	compatible = "allwinner,sun50i-a64-crypto";
	reg = <0x01c15000 0x1000>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
	clock-names = "bus", "mod";
	resets = <&ccu RST_BUS_CE>;
	};

	usb_otg: usb@1c19000 {
	compatible = "allwinner,sun8i-a33-musb";
	reg = <0x01c19000 0x0400>;
	clocks = <&ccu CLK_BUS_OTG>;
	resets = <&ccu RST_BUS_OTG>;
	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "mc";
	phys = <&usbphy 0>;
	phy-names = "usb";
	extcon = <&usbphy 0>;
	dr_mode = "otg";
	status = "disabled";
	};

	usbphy: phy@1c19400 {
	compatible = "allwinner,sun50i-a64-usb-phy";
	reg = <0x01c19400 0x14>,
	<0x01c1a800 0x4>,
	<0x01c1b800 0x4>;
	reg-names = "phy_ctrl",
	"pmu0",
	"pmu1";
	clocks = <&ccu CLK_USB_PHY0>,
	<&ccu CLK_USB_PHY1>;
	clock-names = "usb0_phy",
	"usb1_phy";
	resets = <&ccu RST_USB_PHY0>,
	<&ccu RST_USB_PHY1>;
	reset-names = "usb0_reset",
	"usb1_reset";
	status = "disabled";
	#phy-cells = <1>;
	};

	ehci0: usb@1c1a000 {
	compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
	reg = <0x01c1a000 0x100>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_OHCI0>,
	<&ccu CLK_BUS_EHCI0>,
	<&ccu CLK_USB_OHCI0>;
	resets = <&ccu RST_BUS_OHCI0>,
	<&ccu RST_BUS_EHCI0>;
	status = "disabled";
	};

	ohci0: usb@1c1a400 {
	compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
	reg = <0x01c1a400 0x100>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_OHCI0>,
	<&ccu CLK_USB_OHCI0>;
	resets = <&ccu RST_BUS_OHCI0>;
	status = "disabled";
	};

	ehci1: usb@1c1b000 {
	compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
	reg = <0x01c1b000 0x100>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_OHCI1>,
	<&ccu CLK_BUS_EHCI1>,
	<&ccu CLK_USB_OHCI1>;
	resets = <&ccu RST_BUS_OHCI1>,
	<&ccu RST_BUS_EHCI1>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	ohci1: usb@1c1b400 {
	compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
	reg = <0x01c1b400 0x100>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_OHCI1>,
	<&ccu CLK_USB_OHCI1>;
	resets = <&ccu RST_BUS_OHCI1>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	ccu: clock@1c20000 {
	compatible = "allwinner,sun50i-a64-ccu";
	reg = <0x01c20000 0x400>;
	clocks = <&osc24M>, <&rtc 0>;
	clock-names = "hosc", "losc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pio: pinctrl@1c20800 {
	compatible = "allwinner,sun50i-a64-pinctrl";
	reg = <0x01c20800 0x400>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
	clock-names = "apb", "hosc", "losc";
	gpio-controller;
	#gpio-cells = <3>;
	interrupt-controller;
	#interrupt-cells = <3>;

	csi_pins: csi-pins {
	pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
	"PE7", "PE8", "PE9", "PE10", "PE11";
	function = "csi";
	};

	/omit-if-no-ref/
	csi_mclk_pin: csi-mclk-pin {
	pins = "PE1";
	function = "csi";
	};

	i2c0_pins: i2c0-pins {
	pins = "PH0", "PH1";
	function = "i2c0";
	};

	i2c1_pins: i2c1-pins {
	pins = "PH2", "PH3";
	function = "i2c1";
	};

	+ i2c2_pins: i2c2-pins {
	+ pins = "PE14", "PE15";
	+ function = "i2c2";
	+ };
	+
	/omit-if-no-ref/
	lcd_rgb666_pins: lcd-rgb666-pins {
	pins = "PD0", "PD1", "PD2", "PD3", "PD4",
	"PD5", "PD6", "PD7", "PD8", "PD9",
	"PD10", "PD11", "PD12", "PD13",
	"PD14", "PD15", "PD16", "PD17",
	"PD18", "PD19", "PD20", "PD21";
	function = "lcd0";
	};

	mmc0_pins: mmc0-pins {
	pins = "PF0", "PF1", "PF2", "PF3",
	"PF4", "PF5";
	function = "mmc0";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc1_pins: mmc1-pins {
	pins = "PG0", "PG1", "PG2", "PG3",
	"PG4", "PG5";
	function = "mmc1";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc2_pins: mmc2-pins {
	pins = "PC5", "PC6", "PC8", "PC9",
	"PC10","PC11", "PC12", "PC13",
	"PC14", "PC15", "PC16";
	function = "mmc2";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc2_ds_pin: mmc2-ds-pin {
	pins = "PC1";
	function = "mmc2";
	drive-strength = <30>;
	bias-pull-up;
	};

	pwm_pin: pwm-pin {
	pins = "PD22";
	function = "pwm";
	};

	rmii_pins: rmii-pins {
	pins = "PD10", "PD11", "PD13", "PD14", "PD17",
	"PD18", "PD19", "PD20", "PD22", "PD23";
	function = "emac";
	drive-strength = <40>;
	};

	rgmii_pins: rgmii-pins {
	pins = "PD8", "PD9", "PD10", "PD11", "PD12",
	"PD13", "PD15", "PD16", "PD17", "PD18",
	"PD19", "PD20", "PD21", "PD22", "PD23";
	function = "emac";
	drive-strength = <40>;
	};

	spdif_tx_pin: spdif-tx-pin {
	pins = "PH8";
	function = "spdif";
	};

	spi0_pins: spi0-pins {
	pins = "PC0", "PC1", "PC2", "PC3";
	function = "spi0";
	};

	spi1_pins: spi1-pins {
	pins = "PD0", "PD1", "PD2", "PD3";
	function = "spi1";
	};

	uart0_pb_pins: uart0-pb-pins {
	pins = "PB8", "PB9";
	function = "uart0";
	};

	uart1_pins: uart1-pins {
	pins = "PG6", "PG7";
	function = "uart1";
	};

	uart1_rts_cts_pins: uart1-rts-cts-pins {
	pins = "PG8", "PG9";
	function = "uart1";
	};

	uart2_pins: uart2-pins {
	pins = "PB0", "PB1";
	function = "uart2";
	};

	uart3_pins: uart3-pins {
	pins = "PD0", "PD1";
	function = "uart3";
	};

	uart4_pins: uart4-pins {
	pins = "PD2", "PD3";
	function = "uart4";
	};

	uart4_rts_cts_pins: uart4-rts-cts-pins {
	pins = "PD4", "PD5";
	function = "uart4";
	};
	};

	spdif: spdif@1c21000 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun50i-a64-spdif",
	"allwinner,sun8i-h3-spdif";
	reg = <0x01c21000 0x400>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
	resets = <&ccu RST_BUS_SPDIF>;
	clock-names = "apb", "spdif";
	dmas = <&dma 2>;
	dma-names = "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&spdif_tx_pin>;
	status = "disabled";
	};

	lradc: lradc@1c21800 {
	compatible = "allwinner,sun50i-a64-lradc",
	"allwinner,sun8i-a83t-r-lradc";
	reg = <0x01c21800 0x400>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2s0: i2s@1c22000 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun50i-a64-i2s",
	"allwinner,sun8i-h3-i2s";
	reg = <0x01c22000 0x400>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
	clock-names = "apb", "mod";
	resets = <&ccu RST_BUS_I2S0>;
	dma-names = "rx", "tx";
	dmas = <&dma 3>, <&dma 3>;
	status = "disabled";
	};

	i2s1: i2s@1c22400 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun50i-a64-i2s",
	"allwinner,sun8i-h3-i2s";
	reg = <0x01c22400 0x400>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
	clock-names = "apb", "mod";
	resets = <&ccu RST_BUS_I2S1>;
	dma-names = "rx", "tx";
	dmas = <&dma 4>, <&dma 4>;
	status = "disabled";
	};

	dai: dai@1c22c00 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun50i-a64-codec-i2s";
	reg = <0x01c22c00 0x200>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
	clock-names = "apb", "mod";
	resets = <&ccu RST_BUS_CODEC>;
	dmas = <&dma 15>, <&dma 15>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	codec: codec@1c22e00 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun8i-a33-codec";
	reg = <0x01c22e00 0x600>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
	clock-names = "bus", "mod";
	status = "disabled";
	};

	ths: thermal-sensor@1c25000 {
	compatible = "allwinner,sun50i-a64-ths";
	reg = <0x01c25000 0x100>;
	clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
	clock-names = "bus", "mod";
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&ccu RST_BUS_THS>;
	nvmem-cells = <&ths_calibration>;
	nvmem-cell-names = "calibration";
	#thermal-sensor-cells = <1>;
	};

	uart0: serial@1c28000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28000 0x400>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART0>;
	resets = <&ccu RST_BUS_UART0>;
	status = "disabled";
	};

	uart1: serial@1c28400 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28400 0x400>;
	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART1>;
	resets = <&ccu RST_BUS_UART1>;
	status = "disabled";
	};

	uart2: serial@1c28800 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28800 0x400>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART2>;
	resets = <&ccu RST_BUS_UART2>;
	status = "disabled";
	};

	uart3: serial@1c28c00 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28c00 0x400>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART3>;
	resets = <&ccu RST_BUS_UART3>;
	status = "disabled";
	};

	uart4: serial@1c29000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c29000 0x400>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART4>;
	resets = <&ccu RST_BUS_UART4>;
	status = "disabled";
	};

	i2c0: i2c@1c2ac00 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2ac00 0x400>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C0>;
	resets = <&ccu RST_BUS_I2C0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c1: i2c@1c2b000 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2b000 0x400>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C1>;
	resets = <&ccu RST_BUS_I2C1>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c2: i2c@1c2b400 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2b400 0x400>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C2>;
	resets = <&ccu RST_BUS_I2C2>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&i2c2_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	-
	spi0: spi@1c68000 {
	compatible = "allwinner,sun8i-h3-spi";
	reg = <0x01c68000 0x1000>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
	clock-names = "ahb", "mod";
	dmas = <&dma 23>, <&dma 23>;
	dma-names = "rx", "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pins>;
	resets = <&ccu RST_BUS_SPI0>;
	status = "disabled";
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	spi1: spi@1c69000 {
	compatible = "allwinner,sun8i-h3-spi";
	reg = <0x01c69000 0x1000>;
	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
	clock-names = "ahb", "mod";
	dmas = <&dma 24>, <&dma 24>;
	dma-names = "rx", "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_pins>;
	resets = <&ccu RST_BUS_SPI1>;
	status = "disabled";
	num-cs = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	emac: ethernet@1c30000 {
	compatible = "allwinner,sun50i-a64-emac";
	syscon = <&syscon>;
	reg = <0x01c30000 0x10000>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	resets = <&ccu RST_BUS_EMAC>;
	reset-names = "stmmaceth";
	clocks = <&ccu CLK_BUS_EMAC>;
	clock-names = "stmmaceth";
	status = "disabled";

	mdio: mdio {
	compatible = "snps,dwmac-mdio";
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	mali: gpu@1c40000 {
	compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
	reg = <0x01c40000 0x10000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gp",
	"gpmmu",
	"pp0",
	"ppmmu0",
	"pp1",
	"ppmmu1",
	"pmu";
	clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
	clock-names = "bus", "core";
	resets = <&ccu RST_BUS_GPU>;
	};

	gic: interrupt-controller@1c81000 {
	compatible = "arm,gic-400";
	reg = <0x01c81000 0x1000>,
	<0x01c82000 0x2000>,
	<0x01c84000 0x2000>,
	<0x01c86000 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	interrupt-controller;
	#interrupt-cells = <3>;
	};

	pwm: pwm@1c21400 {
	compatible = "allwinner,sun50i-a64-pwm",
	"allwinner,sun5i-a13-pwm";
	reg = <0x01c21400 0x400>;
	clocks = <&osc24M>;
	pinctrl-names = "default";
	pinctrl-0 = <&pwm_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	+ mbus: dram-controller@1c62000 {
	+ compatible = "allwinner,sun50i-a64-mbus";
	+ reg = <0x01c62000 0x1000>;
	+ clocks = <&ccu 112>;
	+ dma-ranges = <0x00000000 0x40000000 0xc0000000>;
	+ #interconnect-cells = <1>;
	+ };
	+
	csi: csi@1cb0000 {
	compatible = "allwinner,sun50i-a64-csi";
	reg = <0x01cb0000 0x1000>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_CSI>,
	<&ccu CLK_CSI_SCLK>,
	<&ccu CLK_DRAM_CSI>;
	clock-names = "bus", "mod", "ram";
	resets = <&ccu RST_BUS_CSI>;
	pinctrl-names = "default";
	pinctrl-0 = <&csi_pins>;
	status = "disabled";
	};

	dsi: dsi@1ca0000 {
	compatible = "allwinner,sun50i-a64-mipi-dsi";
	reg = <0x01ca0000 0x1000>;
	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_MIPI_DSI>;
	resets = <&ccu RST_BUS_MIPI_DSI>;
	phys = <&dphy>;
	phy-names = "dphy";
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;

	port {
	dsi_in_tcon0: endpoint {
	remote-endpoint = <&tcon0_out_dsi>;
	};
	};
	};

	dphy: d-phy@1ca1000 {
	compatible = "allwinner,sun50i-a64-mipi-dphy",
	"allwinner,sun6i-a31-mipi-dphy";
	reg = <0x01ca1000 0x1000>;
	clocks = <&ccu CLK_BUS_MIPI_DSI>,
	<&ccu CLK_DSI_DPHY>;
	clock-names = "bus", "mod";
	resets = <&ccu RST_BUS_MIPI_DSI>;
	status = "disabled";
	#phy-cells = <0>;
	};

	+ deinterlace: deinterlace@1e00000 {
	+ compatible = "allwinner,sun50i-a64-deinterlace",
	+ "allwinner,sun8i-h3-deinterlace";
	+ reg = <0x01e00000 0x20000>;
	+ clocks = <&ccu CLK_BUS_DEINTERLACE>,
	+ <&ccu CLK_DEINTERLACE>,
	+ <&ccu CLK_DRAM_DEINTERLACE>;
	+ clock-names = "bus", "mod", "ram";
	+ resets = <&ccu RST_BUS_DEINTERLACE>;
	+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	+ interconnects = <&mbus 9>;
	+ interconnect-names = "dma-mem";
	+ };
	+
	hdmi: hdmi@1ee0000 {
	compatible = "allwinner,sun50i-a64-dw-hdmi",
	"allwinner,sun8i-a83t-dw-hdmi";
	reg = <0x01ee0000 0x10000>;
	reg-io-width = <1>;
	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
	<&ccu CLK_HDMI>;
	clock-names = "iahb", "isfr", "tmds";
	resets = <&ccu RST_BUS_HDMI1>;
	reset-names = "ctrl";
	phys = <&hdmi_phy>;
	phy-names = "phy";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	hdmi_in: port@0 {
	reg = <0>;

	hdmi_in_tcon1: endpoint {
	remote-endpoint = <&tcon1_out_hdmi>;
	};
	};

	hdmi_out: port@1 {
	reg = <1>;
	};
	};
	};

	hdmi_phy: hdmi-phy@1ef0000 {
	compatible = "allwinner,sun50i-a64-hdmi-phy";
	reg = <0x01ef0000 0x10000>;
	clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
	<&ccu CLK_PLL_VIDEO0>;
	clock-names = "bus", "mod", "pll-0";
	resets = <&ccu RST_BUS_HDMI0>;
	reset-names = "phy";
	#phy-cells = <0>;
	};

	rtc: rtc@1f00000 {
	compatible = "allwinner,sun50i-a64-rtc",
	"allwinner,sun8i-h3-rtc";
	reg = <0x01f00000 0x400>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	clock-output-names = "osc32k", "osc32k-out", "iosc";
	clocks = <&osc32k>;
	#clock-cells = <1>;
	};

	r_intc: interrupt-controller@1f00c00 {
	compatible = "allwinner,sun50i-a64-r-intc",
	"allwinner,sun6i-a31-r-intc";
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x01f00c00 0x400>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	};

	r_ccu: clock@1f01400 {
	compatible = "allwinner,sun50i-a64-r-ccu";
	reg = <0x01f01400 0x100>;
	clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
	<&ccu CLK_PLL_PERIPH0>;
	clock-names = "hosc", "losc", "iosc", "pll-periph";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	codec_analog: codec-analog@1f015c0 {
	compatible = "allwinner,sun50i-a64-codec-analog";
	reg = <0x01f015c0 0x4>;
	status = "disabled";
	};

	r_i2c: i2c@1f02400 {
	compatible = "allwinner,sun50i-a64-i2c",
	"allwinner,sun6i-a31-i2c";
	reg = <0x01f02400 0x400>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&r_ccu CLK_APB0_I2C>;
	resets = <&r_ccu RST_APB0_I2C>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	r_ir: ir@1f02000 {
	compatible = "allwinner,sun50i-a64-ir",
	"allwinner,sun6i-a31-ir";
	reg = <0x01f02000 0x400>;
	clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
	clock-names = "apb", "ir";
	resets = <&r_ccu RST_APB0_IR>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&r_ir_rx_pin>;
	status = "disabled";
	};

	r_pwm: pwm@1f03800 {
	compatible = "allwinner,sun50i-a64-pwm",
	"allwinner,sun5i-a13-pwm";
	reg = <0x01f03800 0x400>;
	clocks = <&osc24M>;
	pinctrl-names = "default";
	pinctrl-0 = <&r_pwm_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	r_pio: pinctrl@1f02c00 {
	compatible = "allwinner,sun50i-a64-r-pinctrl";
	reg = <0x01f02c00 0x400>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
	clock-names = "apb", "hosc", "losc";
	gpio-controller;
	#gpio-cells = <3>;
	interrupt-controller;
	#interrupt-cells = <3>;

	r_i2c_pl89_pins: r-i2c-pl89-pins {
	pins = "PL8", "PL9";
	function = "s_i2c";
	};

	r_ir_rx_pin: r-ir-rx-pin {
	pins = "PL11";
	function = "s_cir_rx";
	};

	r_pwm_pin: r-pwm-pin {
	pins = "PL10";
	function = "s_pwm";
	};

	r_rsb_pins: r-rsb-pins {
	pins = "PL0", "PL1";
	function = "s_rsb";
	};
	};

	r_rsb: rsb@1f03400 {
	compatible = "allwinner,sun8i-a23-rsb";
	reg = <0x01f03400 0x400>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&r_ccu 6>;
	clock-frequency = <3000000>;
	resets = <&r_ccu 2>;
	pinctrl-names = "default";
	pinctrl-0 = <&r_rsb_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	wdt0: watchdog@1c20ca0 {
	compatible = "allwinner,sun50i-a64-wdt",
	"allwinner,sun6i-a31-wdt";
	reg = <0x01c20ca0 0x20>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc24M>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h5-orangepi-pc2.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h5-orangepi-pc2.dts
	index 70b5f0998421..7d7aad18f078 100644
	--- a/sys/gnu/dts/arm64/allwinner/sun50i-h5-orangepi-pc2.dts
	+++ b/sys/gnu/dts/arm64/allwinner/sun50i-h5-orangepi-pc2.dts
	@@ -1,211 +1,232 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	// Copyright (C) 2016 ARM Ltd.

	/dts-v1/;
	#include "sun50i-h5.dtsi"

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/pinctrl/sun4i-a10.h>

	/ {
	model = "Xunlong Orange Pi PC 2";
	compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";

	reg_vcc3v3: vcc3v3 {
	compatible = "regulator-fixed";
	regulator-name = "vcc3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	aliases {
	ethernet0 = &emac;
	serial0 = &uart0;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	connector {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con_in: endpoint {
	remote-endpoint = <&hdmi_out_con>;
	};
	};
	};

	leds {
	compatible = "gpio-leds";

	pwr {
	label = "orangepi:green:pwr";
	gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
	default-state = "on";
	};

	status {
	label = "orangepi:red:status";
	gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
	};
	};

	r-gpio-keys {
	compatible = "gpio-keys";

	sw4 {
	label = "sw4";
	linux,code = <BTN_0>;
	gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
	+ wakeup-source;
	};
	};

	reg_gmac_3v3: gmac-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "gmac-3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	startup-delay-us = <100000>;
	enable-active-high;
	gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
	};

	reg_usb0_vbus: usb0-vbus {
	compatible = "regulator-fixed";
	regulator-name = "usb0-vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	enable-active-high;
	gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
	status = "okay";
	};
	};

	&codec {
	allwinner,audio-routing =
	"Line Out", "LINEOUT",
	"MIC1", "Mic",
	"Mic", "MBIAS";
	status = "okay";
	};

	+&cpu0 {
	+ cpu-supply = <&reg_vdd_cpux>;
	+};
	+
	&de {
	status = "okay";
	};

	&ehci0 {
	status = "okay";
	};

	&ehci1 {
	status = "okay";
	};

	&ehci2 {
	status = "okay";
	};

	&ehci3 {
	status = "okay";
	};

	&emac {
	pinctrl-names = "default";
	pinctrl-0 = <&emac_rgmii_pins>;
	phy-supply = <&reg_gmac_3v3>;
	phy-handle = <&ext_rgmii_phy>;
	phy-mode = "rgmii";
	status = "okay";
	};

	&external_mdio {
	ext_rgmii_phy: ethernet-phy@1 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <1>;
	};
	};

	&hdmi {
	status = "okay";
	};

	&hdmi_out {
	hdmi_out_con: endpoint {
	remote-endpoint = <&hdmi_con_in>;
	};
	};

	&ir {
	pinctrl-names = "default";
	pinctrl-0 = <&r_ir_rx_pin>;
	status = "okay";
	};

	&mmc0 {
	vmmc-supply = <&reg_vcc3v3>;
	bus-width = <4>;
	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
	status = "okay";
	};

	&ohci0 {
	status = "okay";
	};

	&ohci1 {
	status = "okay";
	};

	&ohci2 {
	status = "okay";
	};

	&ohci3 {
	status = "okay";
	};

	+&r_i2c {
	+ status = "okay";
	+
	+ reg_vdd_cpux: regulator@65 {
	+ compatible = "silergy,sy8106a";
	+ reg = <0x65>;
	+ regulator-name = "vdd-cpux";
	+ silergy,fixed-microvolt = <1100000>;
	+ regulator-min-microvolt = <1000000>;
	+ regulator-max-microvolt = <1400000>;
	+ regulator-ramp-delay = <200>;
	+ regulator-boot-on;
	+ regulator-always-on;
	+ };
	+};
	+
	&spi0 {
	status = "okay";

	flash@0 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <40000000>;
	};
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pa_pins>;
	status = "okay";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
	status = "disabled";
	};

	&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;
	status = "disabled";
	};

	&usb_otg {
	dr_mode = "otg";
	status = "okay";
	};

	&usbphy {
	/* USB Type-A ports' VBUS is always on */
	usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
	usb0_vbus-supply = <&reg_usb0_vbus>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h5.dtsi b/sys/gnu/dts/arm64/allwinner/sun50i-h5.dtsi
	index 9893aa64dd0b..4462a68c0681 100644
	--- a/sys/gnu/dts/arm64/allwinner/sun50i-h5.dtsi
	+++ b/sys/gnu/dts/arm64/allwinner/sun50i-h5.dtsi
	@@ -1,221 +1,220 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	// Copyright (C) 2016 ARM Ltd.

	#include <arm/sunxi-h3-h5.dtsi>

	/ {
	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a53";
	device_type = "cpu";
	reg = <0>;
	enable-method = "psci";
	};

	cpu1: cpu@1 {
	compatible = "arm,cortex-a53";
	device_type = "cpu";
	reg = <1>;
	enable-method = "psci";
	};

	cpu2: cpu@2 {
	compatible = "arm,cortex-a53";
	device_type = "cpu";
	reg = <2>;
	enable-method = "psci";
	};

	cpu3: cpu@3 {
	compatible = "arm,cortex-a53";
	device_type = "cpu";
	reg = <3>;
	enable-method = "psci";
	};
	};

	pmu {
	- compatible = "arm,cortex-a53-pmu",
	- "arm,armv8-pmuv3";
	+ compatible = "arm,cortex-a53-pmu";
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	soc {
	syscon: system-control@1c00000 {
	compatible = "allwinner,sun50i-h5-system-control";
	reg = <0x01c00000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	sram_c1: sram@18000 {
	compatible = "mmio-sram";
	reg = <0x00018000 0x1c000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x00018000 0x1c000>;

	ve_sram: sram-section@0 {
	compatible = "allwinner,sun50i-h5-sram-c1",
	"allwinner,sun4i-a10-sram-c1";
	reg = <0x000000 0x1c000>;
	};
	};
	};

	video-codec@1c0e000 {
	compatible = "allwinner,sun50i-h5-video-engine";
	reg = <0x01c0e000 0x1000>;
	clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
	<&ccu CLK_DRAM_VE>;
	clock-names = "ahb", "mod", "ram";
	resets = <&ccu RST_BUS_VE>;
	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	allwinner,sram = <&ve_sram 1>;
	};

	crypto: crypto@1c15000 {
	compatible = "allwinner,sun50i-h5-crypto";
	reg = <0x01c15000 0x1000>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
	clock-names = "bus", "mod";
	resets = <&ccu RST_BUS_CE>;
	};

	mali: gpu@1e80000 {
	compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
	reg = <0x01e80000 0x30000>;
	/*
	* While the datasheet lists an interrupt for the
	* PMU, the actual silicon does not have the PMU
	* block. Reads all return zero, and writes are
	* ignored.
	*/
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gp",
	"gpmmu",
	"pp",
	"pp0",
	"ppmmu0",
	"pp1",
	"ppmmu1",
	"pp2",
	"ppmmu2",
	"pp3",
	"ppmmu3",
	"pmu";
	clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
	clock-names = "bus", "core";
	resets = <&ccu RST_BUS_GPU>;

	assigned-clocks = <&ccu CLK_GPU>;
	assigned-clock-rates = <384000000>;
	};

	ths: thermal-sensor@1c25000 {
	compatible = "allwinner,sun50i-h5-ths";
	reg = <0x01c25000 0x400>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&ccu RST_BUS_THS>;
	clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
	clock-names = "bus", "mod";
	nvmem-cells = <&ths_calibration>;
	nvmem-cell-names = "calibration";
	#thermal-sensor-cells = <1>;
	};
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	polling-delay-passive = <0>;
	polling-delay = <0>;
	thermal-sensors = <&ths 0>;
	};

	gpu_thermal {
	polling-delay-passive = <0>;
	polling-delay = <0>;
	thermal-sensors = <&ths 1>;
	};
	};
	};

	&ccu {
	compatible = "allwinner,sun50i-h5-ccu";
	};

	&display_clocks {
	compatible = "allwinner,sun50i-h5-de2-clk";
	};

	&mmc0 {
	compatible = "allwinner,sun50i-h5-mmc",
	"allwinner,sun50i-a64-mmc";
	clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
	clock-names = "ahb", "mmc";
	};

	&mmc1 {
	compatible = "allwinner,sun50i-h5-mmc",
	"allwinner,sun50i-a64-mmc";
	clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
	clock-names = "ahb", "mmc";
	};

	&mmc2 {
	compatible = "allwinner,sun50i-h5-emmc",
	"allwinner,sun50i-a64-emmc";
	clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
	clock-names = "ahb", "mmc";
	};

	&pio {
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	compatible = "allwinner,sun50i-h5-pinctrl";
	};

	&rtc {
	compatible = "allwinner,sun50i-h5-rtc";
	};

	&sid {
	compatible = "allwinner,sun50i-h5-sid";
	};
	diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h6-beelink-gs1.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h6-beelink-gs1.dts
	index df6d872c34e2..8f09d209359b 100644
	--- a/sys/gnu/dts/arm64/allwinner/sun50i-h6-beelink-gs1.dts
	+++ b/sys/gnu/dts/arm64/allwinner/sun50i-h6-beelink-gs1.dts
	@@ -1,300 +1,311 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	// Copyright (C) 2019 Clément Péron <peron.clem@gmail.com>

	/dts-v1/;

	#include "sun50i-h6.dtsi"

	#include <dt-bindings/gpio/gpio.h>

	/ {
	model = "Beelink GS1";
	compatible = "azw,beelink-gs1", "allwinner,sun50i-h6";

	aliases {
	ethernet0 = &emac;
	serial0 = &uart0;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	connector {
	compatible = "hdmi-connector";
	type = "a";
	ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */

	port {
	hdmi_con_in: endpoint {
	remote-endpoint = <&hdmi_out_con>;
	};
	};
	};

	+ ext_osc32k: ext_osc32k_clk {
	+ #clock-cells = <0>;
	+ compatible = "fixed-clock";
	+ clock-frequency = <32768>;
	+ clock-output-names = "ext_osc32k";
	+ };
	+
	leds {
	compatible = "gpio-leds";

	power {
	label = "beelink:white:power";
	gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
	default-state = "on";
	};
	};

	reg_vcc5v: vcc5v {
	/* board wide 5V supply directly from the DC jack */
	compatible = "regulator-fixed";
	regulator-name = "vcc-5v";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	sound-spdif {
	compatible = "simple-audio-card";
	simple-audio-card,name = "sun50i-h6-spdif";

	simple-audio-card,cpu {
	sound-dai = <&spdif>;
	};

	simple-audio-card,codec {
	sound-dai = <&spdif_out>;
	};
	};

	spdif_out: spdif-out {
	#sound-dai-cells = <0>;
	compatible = "linux,spdif-dit";
	};
	};

	&de {
	status = "okay";
	};

	&dwc3 {
	status = "okay";
	};

	&ehci0 {
	status = "okay";
	};

	&emac {
	pinctrl-names = "default";
	pinctrl-0 = <&ext_rgmii_pins>;
	phy-mode = "rgmii";
	phy-handle = <&ext_rgmii_phy>;
	phy-supply = <&reg_aldo2>;
	status = "okay";
	};

	&gpu {
	mali-supply = <&reg_dcdcc>;
	status = "okay";
	};

	&hdmi {
	status = "okay";
	};

	&hdmi_out {
	hdmi_out_con: endpoint {
	remote-endpoint = <&hdmi_con_in>;
	};
	};

	&mdio {
	ext_rgmii_phy: ethernet-phy@1 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <1>;
	};
	};

	&mmc0 {
	vmmc-supply = <&reg_cldo1>;
	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	status = "okay";
	};

	&mmc2 {
	vmmc-supply = <&reg_cldo1>;
	vqmmc-supply = <&reg_bldo2>;
	non-removable;
	cap-mmc-hw-reset;
	bus-width = <8>;
	status = "okay";
	};

	&ohci0 {
	status = "okay";
	};

	&pio {
	vcc-pd-supply = <&reg_cldo1>;
	vcc-pg-supply = <&reg_aldo1>;
	};

	&r_i2c {
	status = "okay";

	axp805: pmic@36 {
	compatible = "x-powers,axp805", "x-powers,axp806";
	reg = <0x36>;
	interrupt-parent = <&r_intc>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;
	#interrupt-cells = <1>;
	x-powers,self-working-mode;
	vina-supply = <&reg_vcc5v>;
	vinb-supply = <&reg_vcc5v>;
	vinc-supply = <&reg_vcc5v>;
	vind-supply = <&reg_vcc5v>;
	vine-supply = <&reg_vcc5v>;
	aldoin-supply = <&reg_vcc5v>;
	bldoin-supply = <&reg_vcc5v>;
	cldoin-supply = <&reg_vcc5v>;

	regulators {
	reg_aldo1: aldo1 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-pl";
	};

	reg_aldo2: aldo2 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-ac200";
	regulator-enable-ramp-delay = <100000>;
	};

	reg_aldo3: aldo3 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc25-dram";
	};

	reg_bldo1: bldo1 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc-bias-pll";
	};

	reg_bldo2: bldo2 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc-efuse-pcie-hdmi-io";
	};

	reg_bldo3: bldo3 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc-dcxoio";
	};

	bldo4 {
	/* unused */
	};

	reg_cldo1: cldo1 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-3v3";
	};

	reg_cldo2: cldo2 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-wifi-1";
	};

	reg_cldo3: cldo3 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-wifi-2";
	};

	reg_dcdca: dcdca {
	regulator-always-on;
	regulator-min-microvolt = <810000>;
	regulator-max-microvolt = <1080000>;
	regulator-name = "vdd-cpu";
	};

	reg_dcdcc: dcdcc {
	regulator-enable-ramp-delay = <32000>;
	regulator-min-microvolt = <810000>;
	regulator-max-microvolt = <1080000>;
	regulator-name = "vdd-gpu";
	};

	reg_dcdcd: dcdcd {
	regulator-always-on;
	regulator-min-microvolt = <960000>;
	regulator-max-microvolt = <960000>;
	regulator-name = "vdd-sys";
	};

	reg_dcdce: dcdce {
	regulator-always-on;
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-name = "vcc-dram";
	};

	sw {
	/* unused */
	};
	};
	};
	};

	&r_ir {
	linux,rc-map-name = "rc-beelink-gs1";
	status = "okay";
	};

	&r_pio {
	/*
	* PL0 and PL1 are used for PMIC I2C
	* don't enable the pl-supply else
	* it will fail at boot
	*
	* vcc-pl-supply = <&reg_aldo1>;
	*/
	vcc-pm-supply = <&reg_aldo1>;
	};

	+&rtc {
	+ clocks = <&ext_osc32k>;
	+};
	+
	&spdif {
	status = "okay";
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_ph_pins>;
	status = "okay";
	};

	&usb2otg {
	dr_mode = "host";
	status = "okay";
	};

	&usb2phy {
	usb0_vbus-supply = <&reg_vcc5v>;
	status = "okay";
	};

	&usb3phy {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi-3.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi-3.dts
	index c311eee52a35..47f579610dcc 100644
	--- a/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi-3.dts
	+++ b/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi-3.dts
	@@ -1,322 +1,342 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	// Copyright (C) 2019 Ondřej Jirman <megous@megous.com>

	/dts-v1/;

	#include "sun50i-h6.dtsi"

	#include <dt-bindings/gpio/gpio.h>

	/ {
	model = "OrangePi 3";
	compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6";

	aliases {
	serial0 = &uart0;
	serial1 = &uart1;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	connector {
	compatible = "hdmi-connector";
	ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
	type = "a";

	port {
	hdmi_con_in: endpoint {
	remote-endpoint = <&hdmi_out_con>;
	};
	};
	};

	+ ext_osc32k: ext_osc32k_clk {
	+ #clock-cells = <0>;
	+ compatible = "fixed-clock";
	+ clock-frequency = <32768>;
	+ clock-output-names = "ext_osc32k";
	+ };
	+
	leds {
	compatible = "gpio-leds";

	power {
	label = "orangepi:red:power";
	gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
	default-state = "on";
	};

	status {
	label = "orangepi:green:status";
	gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
	};
	};

	reg_vcc5v: vcc5v {
	/* board wide 5V supply directly from the DC jack */
	compatible = "regulator-fixed";
	regulator-name = "vcc-5v";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	reg_vcc33_wifi: vcc33-wifi {
	/* Always on 3.3V regulator for WiFi and BT */
	compatible = "regulator-fixed";
	regulator-name = "vcc33-wifi";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	vin-supply = <&reg_vcc5v>;
	};

	reg_vcc_wifi_io: vcc-wifi-io {
	/* Always on 1.8V/300mA regulator for WiFi and BT IO */
	compatible = "regulator-fixed";
	regulator-name = "vcc-wifi-io";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	vin-supply = <&reg_vcc33_wifi>;
	};

	wifi_pwrseq: wifi-pwrseq {
	compatible = "mmc-pwrseq-simple";
	clocks = <&rtc 1>;
	clock-names = "ext_clock";
	reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
	post-power-on-delay-ms = <200>;
	};
	};

	&cpu0 {
	cpu-supply = <&reg_dcdca>;
	};

	&de {
	status = "okay";
	};

	&dwc3 {
	status = "okay";
	};

	&ehci0 {
	status = "okay";
	};

	&ehci3 {
	status = "okay";
	};

	&gpu {
	mali-supply = <&reg_dcdcc>;
	status = "okay";
	};

	&hdmi {
	status = "okay";
	};

	&hdmi_out {
	hdmi_out_con: endpoint {
	remote-endpoint = <&hdmi_con_in>;
	};
	};

	&mmc0 {
	vmmc-supply = <&reg_cldo1>;
	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
	bus-width = <4>;
	status = "okay";
	};

	&mmc1 {
	vmmc-supply = <&reg_vcc33_wifi>;
	vqmmc-supply = <&reg_vcc_wifi_io>;
	mmc-pwrseq = <&wifi_pwrseq>;
	bus-width = <4>;
	non-removable;
	status = "okay";

	brcm: sdio-wifi@1 {
	reg = <1>;
	compatible = "brcm,bcm4329-fmac";
	interrupt-parent = <&r_pio>;
	interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */
	interrupt-names = "host-wake";
	};
	};

	+&mmc2 {
	+ vmmc-supply = <&reg_cldo1>;
	+ vqmmc-supply = <&reg_bldo2>;
	+ cap-mmc-hw-reset;
	+ non-removable;
	+ bus-width = <8>;
	+ status = "okay";
	+};
	+
	&ohci0 {
	status = "okay";
	};

	&ohci3 {
	status = "okay";
	};

	&pio {
	vcc-pc-supply = <&reg_bldo2>;
	vcc-pd-supply = <&reg_cldo1>;
	vcc-pg-supply = <&reg_vcc_wifi_io>;
	};

	&r_i2c {
	status = "okay";

	axp805: pmic@36 {
	compatible = "x-powers,axp805", "x-powers,axp806";
	reg = <0x36>;
	interrupt-parent = <&r_intc>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;
	#interrupt-cells = <1>;
	x-powers,self-working-mode;
	vina-supply = <&reg_vcc5v>;
	vinb-supply = <&reg_vcc5v>;
	vinc-supply = <&reg_vcc5v>;
	vind-supply = <&reg_vcc5v>;
	vine-supply = <&reg_vcc5v>;
	aldoin-supply = <&reg_vcc5v>;
	bldoin-supply = <&reg_vcc5v>;
	cldoin-supply = <&reg_vcc5v>;

	regulators {
	reg_aldo1: aldo1 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-pl-led-ir";
	};

	reg_aldo2: aldo2 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc33-audio-tv-ephy-mac";
	};

	/* ALDO3 is shorted to CLDO1 */
	reg_aldo3: aldo3 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1";
	};

	reg_bldo1: bldo1 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc18-dram-bias-pll";
	};

	reg_bldo2: bldo2 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc-efuse-pcie-hdmi-pc";
	};

	bldo3 {
	/* unused */
	};

	bldo4 {
	/* unused */
	};

	reg_cldo1: cldo1 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2";
	};

	cldo2 {
	/* unused */
	};

	cldo3 {
	/* unused */
	};

	reg_dcdca: dcdca {
	regulator-always-on;
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1160000>;
	regulator-name = "vdd-cpu";
	};

	reg_dcdcc: dcdcc {
	regulator-enable-ramp-delay = <32000>;
	regulator-min-microvolt = <810000>;
	regulator-max-microvolt = <1080000>;
	regulator-name = "vdd-gpu";
	};

	reg_dcdcd: dcdcd {
	regulator-always-on;
	regulator-min-microvolt = <960000>;
	regulator-max-microvolt = <960000>;
	regulator-name = "vdd-sys";
	};

	reg_dcdce: dcdce {
	regulator-always-on;
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-name = "vcc-dram";
	};

	sw {
	/* unused */
	};
	};
	};
	};

	&r_ir {
	status = "okay";
	};

	+&rtc {
	+ clocks = <&ext_osc32k>;
	+};
	+
	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_ph_pins>;
	status = "okay";
	};

	/* There's the BT part of the AP6256 connected to that UART */
	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
	uart-has-rtscts;
	status = "okay";

	bluetooth {
	compatible = "brcm,bcm4345c5";
	clocks = <&rtc 1>;
	clock-names = "lpo";
	device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */
	host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */
	shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */
	max-speed = <1500000>;
	};
	};

	&usb2otg {
	/*
	* This board doesn't have a controllable VBUS even though it
	* does have an ID pin. Using it as anything but a USB host is
	* unsafe.
	*/
	dr_mode = "host";
	status = "okay";
	};

	&usb2phy {
	usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
	usb0_vbus-supply = <&reg_vcc5v>;
	usb3_vbus-supply = <&reg_vcc5v>;
	status = "okay";
	};

	&usb3phy {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi-one-plus.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi-one-plus.dts
	index 83aab7368889..fceb298bfd53 100644
	--- a/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi-one-plus.dts
	+++ b/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi-one-plus.dts
	@@ -1,10 +1,43 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	// Copyright (C) 2018 Amarula Solutions
	// Author: Jagan Teki <jagan@amarulasolutions.com>

	#include "sun50i-h6-orangepi.dtsi"

	/ {
	model = "OrangePi One Plus";
	compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
	+
	+ aliases {
	+ ethernet0 = &emac;
	+ };
	+
	+ reg_gmac_3v3: gmac-3v3 {
	+ compatible = "regulator-fixed";
	+ regulator-name = "vcc-gmac-3v3";
	+ regulator-min-microvolt = <3300000>;
	+ regulator-max-microvolt = <3300000>;
	+ startup-delay-us = <100000>;
	+ enable-active-high;
	+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
	+ vin-supply = <&reg_aldo2>;
	+ };
	+};
	+
	+&emac {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&ext_rgmii_pins>;
	+ phy-mode = "rgmii";
	+ phy-handle = <&ext_rgmii_phy>;
	+ phy-supply = <&reg_gmac_3v3>;
	+ allwinner,rx-delay-ps = <200>;
	+ allwinner,tx-delay-ps = <200>;
	+ status = "okay";
	+};
	+
	+&mdio {
	+ ext_rgmii_phy: ethernet-phy@1 {
	+ compatible = "ethernet-phy-ieee802.3-c22";
	+ reg = <1>;
	+ };
	};
	diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi.dtsi b/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi.dtsi
	index 37f4c57597d4..9287976c4a50 100644
	--- a/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi.dtsi
	+++ b/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi.dtsi
	@@ -1,216 +1,253 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	// Copyright (C) 2018 Amarula Solutions
	// Author: Jagan Teki <jagan@amarulasolutions.com>

	/dts-v1/;

	#include "sun50i-h6.dtsi"

	#include <dt-bindings/gpio/gpio.h>

	/ {
	model = "OrangePi One Plus";
	compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";

	aliases {
	serial0 = &uart0;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	+ connector {
	+ compatible = "hdmi-connector";
	+ type = "a";
	+ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
	+
	+ port {
	+ hdmi_con_in: endpoint {
	+ remote-endpoint = <&hdmi_out_con>;
	+ };
	+ };
	+ };
	+
	+ ext_osc32k: ext_osc32k_clk {
	+ #clock-cells = <0>;
	+ compatible = "fixed-clock";
	+ clock-frequency = <32768>;
	+ clock-output-names = "ext_osc32k";
	+ };
	+
	leds {
	compatible = "gpio-leds";

	power {
	label = "orangepi:red:power";
	gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
	default-state = "on";
	};

	status {
	label = "orangepi:green:status";
	gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
	};
	};

	reg_vcc5v: vcc5v {
	/* board wide 5V supply directly from the DC jack */
	compatible = "regulator-fixed";
	regulator-name = "vcc-5v";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};
	};

	+&de {
	+ status = "okay";
	+};
	+
	&ehci0 {
	status = "okay";
	};

	&ehci3 {
	status = "okay";
	};

	&gpu {
	mali-supply = <&reg_dcdcc>;
	status = "okay";
	};

	+&hdmi {
	+ status = "okay";
	+};
	+
	+&hdmi_out {
	+ hdmi_out_con: endpoint {
	+ remote-endpoint = <&hdmi_con_in>;
	+ };
	+};
	+
	&mmc0 {
	vmmc-supply = <&reg_cldo1>;
	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	status = "okay";
	};

	&ohci0 {
	status = "okay";
	};

	&ohci3 {
	status = "okay";
	};

	&r_i2c {
	status = "okay";

	axp805: pmic@36 {
	compatible = "x-powers,axp805", "x-powers,axp806";
	reg = <0x36>;
	interrupt-parent = <&r_intc>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;
	#interrupt-cells = <1>;
	x-powers,self-working-mode;
	vina-supply = <&reg_vcc5v>;
	vinb-supply = <&reg_vcc5v>;
	vinc-supply = <&reg_vcc5v>;
	vind-supply = <&reg_vcc5v>;
	vine-supply = <&reg_vcc5v>;
	aldoin-supply = <&reg_vcc5v>;
	bldoin-supply = <&reg_vcc5v>;
	cldoin-supply = <&reg_vcc5v>;

	regulators {
	reg_aldo1: aldo1 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-pl";
	};

	reg_aldo2: aldo2 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-ac200";
	};

	reg_aldo3: aldo3 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc25-dram";
	};

	reg_bldo1: bldo1 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc-bias-pll";
	};

	reg_bldo2: bldo2 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc-efuse-pcie-hdmi-io";
	};

	reg_bldo3: bldo3 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc-dcxoio";
	};

	bldo4 {
	/* unused */
	};

	reg_cldo1: cldo1 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-3v3";
	};

	reg_cldo2: cldo2 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-wifi-1";
	};

	reg_cldo3: cldo3 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-wifi-2";
	};

	reg_dcdca: dcdca {
	regulator-always-on;
	regulator-min-microvolt = <810000>;
	regulator-max-microvolt = <1080000>;
	regulator-name = "vdd-cpu";
	};

	reg_dcdcc: dcdcc {
	regulator-enable-ramp-delay = <32000>;
	regulator-min-microvolt = <810000>;
	regulator-max-microvolt = <1080000>;
	regulator-name = "vdd-gpu";
	};

	reg_dcdcd: dcdcd {
	regulator-always-on;
	regulator-min-microvolt = <960000>;
	regulator-max-microvolt = <960000>;
	regulator-name = "vdd-sys";
	};

	reg_dcdce: dcdce {
	regulator-always-on;
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-name = "vcc-dram";
	};

	sw {
	/* unused */
	};
	};
	};
	};

	&r_ir {
	status = "okay";
	};

	+&rtc {
	+ clocks = <&ext_osc32k>;
	+};
	+
	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_ph_pins>;
	status = "okay";
	};

	&usb2otg {
	dr_mode = "otg";
	status = "okay";
	};

	&usb2phy {
	usb0_id_det-gpios = <&pio 2 6 GPIO_ACTIVE_HIGH>; /* PC6 */
	usb0_vbus-supply = <&reg_vcc5v>;
	usb3_vbus-supply = <&reg_vcc5v>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h6-pine-h64.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h6-pine-h64.dts
	index d1c2aa5b3a20..b0642d841933 100644
	--- a/sys/gnu/dts/arm64/allwinner/sun50i-h6-pine-h64.dts
	+++ b/sys/gnu/dts/arm64/allwinner/sun50i-h6-pine-h64.dts
	@@ -1,296 +1,326 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	// Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>

	/dts-v1/;

	#include "sun50i-h6.dtsi"

	#include <dt-bindings/gpio/gpio.h>

	/ {
	model = "Pine H64 model A";
	compatible = "pine64,pine-h64", "allwinner,sun50i-h6";

	aliases {
	ethernet0 = &emac;
	serial0 = &uart0;
	+ spi0 = &spi0;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	+ ext_osc32k: ext_osc32k_clk {
	+ #clock-cells = <0>;
	+ compatible = "fixed-clock";
	+ clock-frequency = <32768>;
	+ clock-output-names = "ext_osc32k";
	+ };
	+
	hdmi_connector: connector {
	compatible = "hdmi-connector";
	type = "a";
	ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */

	port {
	hdmi_con_in: endpoint {
	remote-endpoint = <&hdmi_out_con>;
	};
	};
	};

	leds {
	compatible = "gpio-leds";

	heartbeat {
	label = "pine-h64:green:heartbeat";
	gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
	};

	link {
	label = "pine-h64:white:link";
	gpios = <&r_pio 0 3 GPIO_ACTIVE_HIGH>; /* PL3 */
	};

	status {
	label = "pine-h64:blue:status";
	gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
	};
	};

	reg_gmac_3v3: gmac-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "vcc-gmac-3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	startup-delay-us = <100000>;
	gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	reg_usb_vbus: vbus {
	compatible = "regulator-fixed";
	regulator-name = "usb-vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	startup-delay-us = <100000>;
	gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};
	};

	&emac {
	pinctrl-names = "default";
	pinctrl-0 = <&ext_rgmii_pins>;
	phy-mode = "rgmii";
	phy-handle = <&ext_rgmii_phy>;
	phy-supply = <&reg_gmac_3v3>;
	allwinner,rx-delay-ps = <200>;
	allwinner,tx-delay-ps = <200>;
	status = "okay";
	};

	&mdio {
	ext_rgmii_phy: ethernet-phy@1 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <1>;
	};
	};

	&de {
	status = "okay";
	};

	&gpu {
	mali-supply = <&reg_dcdcc>;
	status = "okay";
	};

	&hdmi {
	status = "okay";
	};

	&hdmi_out {
	hdmi_out_con: endpoint {
	remote-endpoint = <&hdmi_con_in>;
	};
	};

	&ehci0 {
	status = "okay";
	};

	&ehci3 {
	status = "okay";
	};

	&mmc0 {
	vmmc-supply = <&reg_cldo1>;
	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	status = "okay";
	};

	&mmc2 {
	vmmc-supply = <&reg_cldo1>;
	vqmmc-supply = <&reg_bldo2>;
	non-removable;
	cap-mmc-hw-reset;
	bus-width = <8>;
	status = "okay";
	};

	&ohci0 {
	status = "okay";
	};

	&ohci3 {
	status = "okay";
	};

	&pio {
	vcc-pc-supply = <&reg_bldo2>;
	vcc-pd-supply = <&reg_cldo1>;
	vcc-pg-supply = <&reg_aldo1>;
	};

	&r_i2c {
	status = "okay";

	axp805: pmic@36 {
	compatible = "x-powers,axp805", "x-powers,axp806";
	reg = <0x36>;
	interrupt-parent = <&r_intc>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;
	#interrupt-cells = <1>;
	x-powers,self-working-mode;

	regulators {
	reg_aldo1: aldo1 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-pl";
	};

	reg_aldo2: aldo2 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-ac200";
	regulator-enable-ramp-delay = <100000>;
	};

	reg_aldo3: aldo3 {
	/* This regulator is connected with CLDO1 */
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-3v3-1";
	};

	reg_bldo1: bldo1 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc-bias-pll";
	};

	reg_bldo2: bldo2 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc-efuse-pcie-hdmi-io";
	};

	reg_bldo3: bldo3 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc-dcxoio";
	};

	bldo4 {
	/* unused */
	};

	reg_cldo1: cldo1 {
	/* This regulator is connected with ALDO3 */
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-3v3-2";
	};

	reg_cldo2: cldo2 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-wifi-1";
	};

	reg_cldo3: cldo3 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-wifi-2";
	};

	reg_dcdca: dcdca {
	regulator-always-on;
	regulator-min-microvolt = <810000>;
	regulator-max-microvolt = <1080000>;
	regulator-name = "vdd-cpu";
	};

	reg_dcdcc: dcdcc {
	regulator-enable-ramp-delay = <32000>;
	regulator-min-microvolt = <810000>;
	regulator-max-microvolt = <1080000>;
	regulator-name = "vdd-gpu";
	};

	reg_dcdcd: dcdcd {
	regulator-always-on;
	regulator-min-microvolt = <960000>;
	regulator-max-microvolt = <960000>;
	regulator-name = "vdd-sys";
	};

	reg_dcdce: dcdce {
	regulator-always-on;
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-name = "vcc-dram";
	};

	sw {
	/* unused */
	};
	};
	};

	pcf8563: rtc@51 {
	compatible = "nxp,pcf8563";
	reg = <0x51>;
	interrupt-parent = <&r_intc>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	#clock-cells = <0>;
	};
	};

	&r_ir {
	status = "okay";
	};

	&r_pio {
	vcc-pm-supply = <&reg_aldo1>;
	};

	+&rtc {
	+ clocks = <&ext_osc32k>;
	+};
	+
	+/*
	+ * The CS pin is shared with the MMC2 CMD pin, so we cannot have the SPI
	+ * flash and eMMC at the same time, as one of them would fail probing.
	+ * Disable SPI0 in here, to prefer the more useful eMMC. U-Boot can
	+ * fix this up in no eMMC is connected.
	+ */
	+&spi0 {
	+ pinctrl-0 = <&spi0_pins>, <&spi0_cs_pin>;
	+ pinctrl-names = "default";
	+ status = "disabled";
	+
	+ flash@0 {
	+ compatible = "winbond,w25q128", "jedec,spi-nor";
	+ reg = <0>;
	+ spi-max-frequency = <4000000>;
	+ };
	+};
	+
	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_ph_pins>;
	status = "okay";
	};

	&usb2otg {
	dr_mode = "host";
	status = "okay";
	};

	&usb2phy {
	usb0_vbus-supply = <&reg_usb_vbus>;
	usb3_vbus-supply = <&reg_usb_vbus>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h6.dtsi b/sys/gnu/dts/arm64/allwinner/sun50i-h6.dtsi
	index 3329283e38ab..b9ab7d8fa8af 100644
	--- a/sys/gnu/dts/arm64/allwinner/sun50i-h6.dtsi
	+++ b/sys/gnu/dts/arm64/allwinner/sun50i-h6.dtsi
	@@ -1,911 +1,957 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/sun50i-h6-ccu.h>
	#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
	#include <dt-bindings/clock/sun8i-de2.h>
	#include <dt-bindings/clock/sun8i-tcon-top.h>
	#include <dt-bindings/reset/sun50i-h6-ccu.h>
	#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
	#include <dt-bindings/reset/sun8i-de2.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a53";
	device_type = "cpu";
	reg = <0>;
	enable-method = "psci";
	};

	cpu1: cpu@1 {
	compatible = "arm,cortex-a53";
	device_type = "cpu";
	reg = <1>;
	enable-method = "psci";
	};

	cpu2: cpu@2 {
	compatible = "arm,cortex-a53";
	device_type = "cpu";
	reg = <2>;
	enable-method = "psci";
	};

	cpu3: cpu@3 {
	compatible = "arm,cortex-a53";
	device_type = "cpu";
	reg = <3>;
	enable-method = "psci";
	};
	};

	de: display-engine {
	compatible = "allwinner,sun50i-h6-display-engine";
	allwinner,pipelines = <&mixer0>;
	status = "disabled";
	};

	osc24M: osc24M_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-output-names = "osc24M";
	};

	- ext_osc32k: ext_osc32k_clk {
	- #clock-cells = <0>;
	- compatible = "fixed-clock";
	- clock-frequency = <32768>;
	- clock-output-names = "ext_osc32k";
	- };
	-
	pmu {
	- compatible = "arm,cortex-a53-pmu",
	- "arm,armv8-pmuv3";
	+ compatible = "arm,cortex-a53-pmu";
	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 14
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 11
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 10
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	bus@1000000 {
	compatible = "allwinner,sun50i-h6-de3",
	"allwinner,sun50i-a64-de2";
	reg = <0x1000000 0x400000>;
	allwinner,sram = <&de2_sram 1>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x1000000 0x400000>;

	display_clocks: clock@0 {
	compatible = "allwinner,sun50i-h6-de3-clk";
	reg = <0x0 0x10000>;
	clocks = <&ccu CLK_DE>,
	<&ccu CLK_BUS_DE>;
	clock-names = "mod",
	"bus";
	resets = <&ccu RST_BUS_DE>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	mixer0: mixer@100000 {
	compatible = "allwinner,sun50i-h6-de3-mixer-0";
	reg = <0x100000 0x100000>;
	clocks = <&display_clocks CLK_BUS_MIXER0>,
	<&display_clocks CLK_MIXER0>;
	clock-names = "bus",
	"mod";
	resets = <&display_clocks RST_MIXER0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	mixer0_out: port@1 {
	reg = <1>;

	mixer0_out_tcon_top_mixer0: endpoint {
	remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
	};
	};
	};
	};
	};

	video-codec@1c0e000 {
	compatible = "allwinner,sun50i-h6-video-engine";
	reg = <0x01c0e000 0x2000>;
	clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
	<&ccu CLK_MBUS_VE>;
	clock-names = "ahb", "mod", "ram";
	resets = <&ccu RST_BUS_VE>;
	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	allwinner,sram = <&ve_sram 1>;
	};

	gpu: gpu@1800000 {
	compatible = "allwinner,sun50i-h6-mali",
	"arm,mali-t720";
	reg = <0x01800000 0x4000>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "job", "mmu", "gpu";
	clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
	clock-names = "core", "bus";
	resets = <&ccu RST_BUS_GPU>;
	status = "disabled";
	};

	crypto: crypto@1904000 {
	compatible = "allwinner,sun50i-h6-crypto";
	reg = <0x01904000 0x1000>;
	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>;
	clock-names = "bus", "mod", "ram";
	resets = <&ccu RST_BUS_CE>;
	};

	syscon: syscon@3000000 {
	compatible = "allwinner,sun50i-h6-system-control",
	"allwinner,sun50i-a64-system-control";
	reg = <0x03000000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	sram_c: sram@28000 {
	compatible = "mmio-sram";
	reg = <0x00028000 0x1e000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x00028000 0x1e000>;

	de2_sram: sram-section@0 {
	compatible = "allwinner,sun50i-h6-sram-c",
	"allwinner,sun50i-a64-sram-c";
	reg = <0x0000 0x1e000>;
	};
	};

	sram_c1: sram@1a00000 {
	compatible = "mmio-sram";
	reg = <0x01a00000 0x200000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x01a00000 0x200000>;

	ve_sram: sram-section@0 {
	compatible = "allwinner,sun50i-h6-sram-c1",
	"allwinner,sun4i-a10-sram-c1";
	reg = <0x000000 0x200000>;
	};
	};
	};

	ccu: clock@3001000 {
	compatible = "allwinner,sun50i-h6-ccu";
	reg = <0x03001000 0x1000>;
	clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
	clock-names = "hosc", "losc", "iosc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	dma: dma-controller@3002000 {
	compatible = "allwinner,sun50i-h6-dma";
	reg = <0x03002000 0x1000>;
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
	clock-names = "bus", "mbus";
	dma-channels = <16>;
	dma-requests = <46>;
	resets = <&ccu RST_BUS_DMA>;
	#dma-cells = <1>;
	};

	sid: efuse@3006000 {
	compatible = "allwinner,sun50i-h6-sid";
	reg = <0x03006000 0x400>;
	#address-cells = <1>;
	#size-cells = <1>;

	ths_calibration: thermal-sensor-calibration@14 {
	reg = <0x14 0x8>;
	};
	};

	watchdog: watchdog@30090a0 {
	compatible = "allwinner,sun50i-h6-wdt",
	"allwinner,sun6i-a31-wdt";
	reg = <0x030090a0 0x20>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc24M>;
	/* Broken on some H6 boards */
	status = "disabled";
	};

	pwm: pwm@300a000 {
	compatible = "allwinner,sun50i-h6-pwm";
	reg = <0x0300a000 0x400>;
	clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
	clock-names = "mod", "bus";
	resets = <&ccu RST_BUS_PWM>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pio: pinctrl@300b000 {
	compatible = "allwinner,sun50i-h6-pinctrl";
	reg = <0x0300b000 0x400>;
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
	clock-names = "apb", "hosc", "losc";
	gpio-controller;
	#gpio-cells = <3>;
	interrupt-controller;
	#interrupt-cells = <3>;

	ext_rgmii_pins: rgmii-pins {
	pins = "PD0", "PD1", "PD2", "PD3", "PD4",
	"PD5", "PD7", "PD8", "PD9", "PD10",
	"PD11", "PD12", "PD13", "PD19", "PD20";
	function = "emac";
	drive-strength = <40>;
	};

	hdmi_pins: hdmi-pins {
	pins = "PH8", "PH9", "PH10";
	function = "hdmi";
	};

	i2c0_pins: i2c0-pins {
	pins = "PD25", "PD26";
	function = "i2c0";
	};

	i2c1_pins: i2c1-pins {
	pins = "PH5", "PH6";
	function = "i2c1";
	};

	i2c2_pins: i2c2-pins {
	pins = "PD23", "PD24";
	function = "i2c2";
	};

	mmc0_pins: mmc0-pins {
	pins = "PF0", "PF1", "PF2", "PF3",
	"PF4", "PF5";
	function = "mmc0";
	drive-strength = <30>;
	bias-pull-up;
	};

	/omit-if-no-ref/
	mmc1_pins: mmc1-pins {
	pins = "PG0", "PG1", "PG2", "PG3",
	"PG4", "PG5";
	function = "mmc1";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc2_pins: mmc2-pins {
	pins = "PC1", "PC4", "PC5", "PC6",
	"PC7", "PC8", "PC9", "PC10",
	"PC11", "PC12", "PC13", "PC14";
	function = "mmc2";
	drive-strength = <30>;
	bias-pull-up;
	};

	+ /omit-if-no-ref/
	+ spi0_pins: spi0-pins {
	+ pins = "PC0", "PC2", "PC3";
	+ function = "spi0";
	+ };
	+
	+ /* pin shared with MMC2-CMD (eMMC) */
	+ /omit-if-no-ref/
	+ spi0_cs_pin: spi0-cs-pin {
	+ pins = "PC5";
	+ function = "spi0";
	+ };
	+
	+ /omit-if-no-ref/
	+ spi1_pins: spi1-pins {
	+ pins = "PH4", "PH5", "PH6";
	+ function = "spi1";
	+ };
	+
	+ /omit-if-no-ref/
	+ spi1_cs_pin: spi1-cs-pin {
	+ pins = "PH3";
	+ function = "spi1";
	+ };
	+
	spdif_tx_pin: spdif-tx-pin {
	pins = "PH7";
	function = "spdif";
	};

	uart0_ph_pins: uart0-ph-pins {
	pins = "PH0", "PH1";
	function = "uart0";
	};

	uart1_pins: uart1-pins {
	pins = "PG6", "PG7";
	function = "uart1";
	};

	uart1_rts_cts_pins: uart1-rts-cts-pins {
	pins = "PG8", "PG9";
	function = "uart1";
	};
	};

	gic: interrupt-controller@3021000 {
	compatible = "arm,gic-400";
	reg = <0x03021000 0x1000>,
	<0x03022000 0x2000>,
	<0x03024000 0x2000>,
	<0x03026000 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	interrupt-controller;
	#interrupt-cells = <3>;
	};

	mmc0: mmc@4020000 {
	compatible = "allwinner,sun50i-h6-mmc",
	"allwinner,sun50i-a64-mmc";
	reg = <0x04020000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
	clock-names = "ahb", "mmc";
	resets = <&ccu RST_BUS_MMC0>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc1: mmc@4021000 {
	compatible = "allwinner,sun50i-h6-mmc",
	"allwinner,sun50i-a64-mmc";
	reg = <0x04021000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
	clock-names = "ahb", "mmc";
	resets = <&ccu RST_BUS_MMC1>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc2: mmc@4022000 {
	compatible = "allwinner,sun50i-h6-emmc",
	"allwinner,sun50i-a64-emmc";
	reg = <0x04022000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
	clock-names = "ahb", "mmc";
	resets = <&ccu RST_BUS_MMC2>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	uart0: serial@5000000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x05000000 0x400>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART0>;
	resets = <&ccu RST_BUS_UART0>;
	status = "disabled";
	};

	uart1: serial@5000400 {
	compatible = "snps,dw-apb-uart";
	reg = <0x05000400 0x400>;
	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART1>;
	resets = <&ccu RST_BUS_UART1>;
	status = "disabled";
	};

	uart2: serial@5000800 {
	compatible = "snps,dw-apb-uart";
	reg = <0x05000800 0x400>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART2>;
	resets = <&ccu RST_BUS_UART2>;
	status = "disabled";
	};

	uart3: serial@5000c00 {
	compatible = "snps,dw-apb-uart";
	reg = <0x05000c00 0x400>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART3>;
	resets = <&ccu RST_BUS_UART3>;
	status = "disabled";
	};

	i2c0: i2c@5002000 {
	compatible = "allwinner,sun50i-h6-i2c",
	"allwinner,sun6i-a31-i2c";
	reg = <0x05002000 0x400>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C0>;
	resets = <&ccu RST_BUS_I2C0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c1: i2c@5002400 {
	compatible = "allwinner,sun50i-h6-i2c",
	"allwinner,sun6i-a31-i2c";
	reg = <0x05002400 0x400>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C1>;
	resets = <&ccu RST_BUS_I2C1>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c2: i2c@5002800 {
	compatible = "allwinner,sun50i-h6-i2c",
	"allwinner,sun6i-a31-i2c";
	reg = <0x05002800 0x400>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C2>;
	resets = <&ccu RST_BUS_I2C2>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	+ spi0: spi@5010000 {
	+ compatible = "allwinner,sun50i-h6-spi",
	+ "allwinner,sun8i-h3-spi";
	+ reg = <0x05010000 0x1000>;
	+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
	+ clock-names = "ahb", "mod";
	+ dmas = <&dma 22>, <&dma 22>;
	+ dma-names = "rx", "tx";
	+ resets = <&ccu RST_BUS_SPI0>;
	+ status = "disabled";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ };
	+
	+ spi1: spi@5011000 {
	+ compatible = "allwinner,sun50i-h6-spi",
	+ "allwinner,sun8i-h3-spi";
	+ reg = <0x05011000 0x1000>;
	+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
	+ clock-names = "ahb", "mod";
	+ dmas = <&dma 23>, <&dma 23>;
	+ dma-names = "rx", "tx";
	+ resets = <&ccu RST_BUS_SPI1>;
	+ status = "disabled";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ };
	+
	emac: ethernet@5020000 {
	compatible = "allwinner,sun50i-h6-emac",
	"allwinner,sun50i-a64-emac";
	syscon = <&syscon>;
	reg = <0x05020000 0x10000>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	resets = <&ccu RST_BUS_EMAC>;
	reset-names = "stmmaceth";
	clocks = <&ccu CLK_BUS_EMAC>;
	clock-names = "stmmaceth";
	status = "disabled";

	mdio: mdio {
	compatible = "snps,dwmac-mdio";
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	spdif: spdif@5093000 {
	#sound-dai-cells = <0>;
	compatible = "allwinner,sun50i-h6-spdif";
	reg = <0x05093000 0x400>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
	clock-names = "apb", "spdif";
	resets = <&ccu RST_BUS_SPDIF>;
	dmas = <&dma 2>;
	dma-names = "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&spdif_tx_pin>;
	status = "disabled";
	};

	usb2otg: usb@5100000 {
	compatible = "allwinner,sun50i-h6-musb",
	"allwinner,sun8i-a33-musb";
	reg = <0x05100000 0x0400>;
	clocks = <&ccu CLK_BUS_OTG>;
	resets = <&ccu RST_BUS_OTG>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "mc";
	phys = <&usb2phy 0>;
	phy-names = "usb";
	extcon = <&usb2phy 0>;
	status = "disabled";
	};

	usb2phy: phy@5100400 {
	compatible = "allwinner,sun50i-h6-usb-phy";
	reg = <0x05100400 0x24>,
	<0x05101800 0x4>,
	<0x05311800 0x4>;
	reg-names = "phy_ctrl",
	"pmu0",
	"pmu3";
	clocks = <&ccu CLK_USB_PHY0>,
	<&ccu CLK_USB_PHY3>;
	clock-names = "usb0_phy",
	"usb3_phy";
	resets = <&ccu RST_USB_PHY0>,
	<&ccu RST_USB_PHY3>;
	reset-names = "usb0_reset",
	"usb3_reset";
	status = "disabled";
	#phy-cells = <1>;
	};

	ehci0: usb@5101000 {
	compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
	reg = <0x05101000 0x100>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_OHCI0>,
	<&ccu CLK_BUS_EHCI0>,
	<&ccu CLK_USB_OHCI0>;
	resets = <&ccu RST_BUS_OHCI0>,
	<&ccu RST_BUS_EHCI0>;
	status = "disabled";
	};

	ohci0: usb@5101400 {
	compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
	reg = <0x05101400 0x100>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_OHCI0>,
	<&ccu CLK_USB_OHCI0>;
	resets = <&ccu RST_BUS_OHCI0>;
	status = "disabled";
	};

	dwc3: dwc3@5200000 {
	compatible = "snps,dwc3";
	reg = <0x05200000 0x10000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_XHCI>,
	<&ccu CLK_BUS_XHCI>,
	<&rtc 0>;
	clock-names = "ref", "bus_early", "suspend";
	resets = <&ccu RST_BUS_XHCI>;
	/*
	* The datasheet of the chip doesn't declare the
	* peripheral function, and there's no boards known
	* to have a USB Type-B port routed to the port.
	* In addition, no one has tested the peripheral
	* function yet.
	* So set the dr_mode to "host" in the DTSI file.
	*/
	dr_mode = "host";
	phys = <&usb3phy>;
	phy-names = "usb3-phy";
	status = "disabled";
	};

	usb3phy: phy@5210000 {
	compatible = "allwinner,sun50i-h6-usb3-phy";
	reg = <0x5210000 0x10000>;
	clocks = <&ccu CLK_USB_PHY1>;
	resets = <&ccu RST_USB_PHY1>;
	#phy-cells = <0>;
	status = "disabled";
	};

	ehci3: usb@5311000 {
	compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
	reg = <0x05311000 0x100>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_OHCI3>,
	<&ccu CLK_BUS_EHCI3>,
	<&ccu CLK_USB_OHCI3>;
	resets = <&ccu RST_BUS_OHCI3>,
	<&ccu RST_BUS_EHCI3>;
	phys = <&usb2phy 3>;
	phy-names = "usb";
	status = "disabled";
	};

	ohci3: usb@5311400 {
	compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
	reg = <0x05311400 0x100>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_OHCI3>,
	<&ccu CLK_USB_OHCI3>;
	resets = <&ccu RST_BUS_OHCI3>;
	phys = <&usb2phy 3>;
	phy-names = "usb";
	status = "disabled";
	};

	hdmi: hdmi@6000000 {
	compatible = "allwinner,sun50i-h6-dw-hdmi";
	reg = <0x06000000 0x10000>;
	reg-io-width = <1>;
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
	<&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
	<&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
	clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
	"hdcp-bus";
	resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
	reset-names = "ctrl", "hdcp";
	phys = <&hdmi_phy>;
	phy-names = "phy";
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_pins>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	hdmi_in: port@0 {
	reg = <0>;

	hdmi_in_tcon_top: endpoint {
	remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
	};
	};

	hdmi_out: port@1 {
	reg = <1>;
	};
	};
	};

	hdmi_phy: hdmi-phy@6010000 {
	compatible = "allwinner,sun50i-h6-hdmi-phy";
	reg = <0x06010000 0x10000>;
	clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
	clock-names = "bus", "mod";
	resets = <&ccu RST_BUS_HDMI>;
	reset-names = "phy";
	#phy-cells = <0>;
	};

	tcon_top: tcon-top@6510000 {
	compatible = "allwinner,sun50i-h6-tcon-top";
	reg = <0x06510000 0x1000>;
	clocks = <&ccu CLK_BUS_TCON_TOP>,
	<&ccu CLK_TCON_TV0>;
	clock-names = "bus",
	"tcon-tv0";
	clock-output-names = "tcon-top-tv0";
	resets = <&ccu RST_BUS_TCON_TOP>;
	#clock-cells = <1>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon_top_mixer0_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	tcon_top_mixer0_in_mixer0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
	};
	};

	tcon_top_mixer0_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	tcon_top_mixer0_out_tcon_tv: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
	};
	};

	tcon_top_hdmi_in: port@4 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <4>;

	tcon_top_hdmi_in_tcon_tv: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&tcon_tv_out_tcon_top>;
	};
	};

	tcon_top_hdmi_out: port@5 {
	reg = <5>;

	tcon_top_hdmi_out_hdmi: endpoint {
	remote-endpoint = <&hdmi_in_tcon_top>;
	};
	};
	};
	};

	tcon_tv: lcd-controller@6515000 {
	compatible = "allwinner,sun50i-h6-tcon-tv",
	"allwinner,sun8i-r40-tcon-tv";
	reg = <0x06515000 0x1000>;
	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_TCON_TV0>,
	<&tcon_top CLK_TCON_TOP_TV0>;
	clock-names = "ahb",
	"tcon-ch1";
	resets = <&ccu RST_BUS_TCON_TV0>;
	reset-names = "lcd";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon_tv_in: port@0 {
	reg = <0>;

	tcon_tv_in_tcon_top_mixer0: endpoint {
	remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
	};
	};

	tcon_tv_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	tcon_tv_out_tcon_top: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
	};
	};
	};
	};

	rtc: rtc@7000000 {
	compatible = "allwinner,sun50i-h6-rtc";
	reg = <0x07000000 0x400>;
	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	clock-output-names = "osc32k", "osc32k-out", "iosc";
	- clocks = <&ext_osc32k>;
	#clock-cells = <1>;
	};

	r_ccu: clock@7010000 {
	compatible = "allwinner,sun50i-h6-r-ccu";
	reg = <0x07010000 0x400>;
	clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
	<&ccu CLK_PLL_PERIPH0>;
	clock-names = "hosc", "losc", "iosc", "pll-periph";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	r_watchdog: watchdog@7020400 {
	compatible = "allwinner,sun50i-h6-wdt",
	"allwinner,sun6i-a31-wdt";
	reg = <0x07020400 0x20>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc24M>;
	};

	r_intc: interrupt-controller@7021000 {
	compatible = "allwinner,sun50i-h6-r-intc",
	"allwinner,sun6i-a31-r-intc";
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x07021000 0x400>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	};

	r_pio: pinctrl@7022000 {
	compatible = "allwinner,sun50i-h6-r-pinctrl";
	reg = <0x07022000 0x400>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
	clock-names = "apb", "hosc", "losc";
	gpio-controller;
	#gpio-cells = <3>;
	interrupt-controller;
	#interrupt-cells = <3>;

	r_i2c_pins: r-i2c-pins {
	pins = "PL0", "PL1";
	function = "s_i2c";
	};

	r_ir_rx_pin: r-ir-rx-pin {
	pins = "PL9";
	function = "s_cir_rx";
	};
	};

	r_ir: ir@7040000 {
	compatible = "allwinner,sun50i-h6-ir",
	"allwinner,sun6i-a31-ir";
	reg = <0x07040000 0x400>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&r_ccu CLK_R_APB1_IR>,
	<&r_ccu CLK_IR>;
	clock-names = "apb", "ir";
	resets = <&r_ccu RST_R_APB1_IR>;
	pinctrl-names = "default";
	pinctrl-0 = <&r_ir_rx_pin>;
	status = "disabled";
	};

	r_i2c: i2c@7081400 {
	compatible = "allwinner,sun50i-h6-i2c",
	"allwinner,sun6i-a31-i2c";
	reg = <0x07081400 0x400>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&r_ccu CLK_R_APB2_I2C>;
	resets = <&r_ccu RST_R_APB2_I2C>;
	pinctrl-names = "default";
	pinctrl-0 = <&r_i2c_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	ths: thermal-sensor@5070400 {
	compatible = "allwinner,sun50i-h6-ths";
	reg = <0x05070400 0x100>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_THS>;
	clock-names = "bus";
	resets = <&ccu RST_BUS_THS>;
	nvmem-cells = <&ths_calibration>;
	nvmem-cell-names = "calibration";
	#thermal-sensor-cells = <1>;
	};
	};

	thermal-zones {
	cpu-thermal {
	polling-delay-passive = <0>;
	polling-delay = <0>;
	thermal-sensors = <&ths 0>;
	};

	gpu-thermal {
	polling-delay-passive = <0>;
	polling-delay = <0>;
	thermal-sensors = <&ths 1>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/altera/socfpga_stratix10_socdk.dts b/sys/gnu/dts/arm64/altera/socfpga_stratix10_socdk.dts
	index fb11ef05d556..f6c4a15079d3 100644
	--- a/sys/gnu/dts/arm64/altera/socfpga_stratix10_socdk.dts
	+++ b/sys/gnu/dts/arm64/altera/socfpga_stratix10_socdk.dts
	@@ -1,190 +1,190 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright Altera Corporation (C) 2015. All rights reserved.
	*/

	#include "socfpga_stratix10.dtsi"

	/ {
	model = "SoCFPGA Stratix 10 SoCDK";

	aliases {
	serial0 = &uart0;
	ethernet0 = &gmac0;
	ethernet1 = &gmac1;
	ethernet2 = &gmac2;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	leds {
	compatible = "gpio-leds";
	hps0 {
	label = "hps_led0";
	gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
	};

	hps1 {
	label = "hps_led1";
	gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
	};

	hps2 {
	label = "hps_led2";
	gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
	};
	};

	memory {
	device_type = "memory";
	/* We expect the bootloader to fill in the reg */
	reg = <0 0 0 0>;
	};

	ref_033v: 033-v-ref {
	compatible = "regulator-fixed";
	regulator-name = "0.33V";
	regulator-min-microvolt = <330000>;
	regulator-max-microvolt = <330000>;
	};

	soc {
	clocks {
	osc1 {
	clock-frequency = <25000000>;
	};
	};

	eccmgr {
	sdmmca-ecc@ff8c8c00 {
	compatible = "altr,socfpga-s10-sdmmc-ecc",
	"altr,socfpga-sdmmc-ecc";
	reg = <0xff8c8c00 0x100>;
	altr,ecc-parent = <&mmc>;
	interrupts = <14 4>,
	<15 4>;
	};
	};
	};
	};

	&gpio1 {
	status = "okay";
	};

	&gmac0 {
	status = "okay";
	phy-mode = "rgmii";
	phy-handle = <&phy0>;

	max-frame-size = <9000>;

	mdio0 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,dwmac-mdio";
	phy0: ethernet-phy@0 {
	reg = <4>;

	txd0-skew-ps = <0>; /* -420ps */
	txd1-skew-ps = <0>; /* -420ps */
	txd2-skew-ps = <0>; /* -420ps */
	txd3-skew-ps = <0>; /* -420ps */
	rxd0-skew-ps = <420>; /* 0ps */
	rxd1-skew-ps = <420>; /* 0ps */
	rxd2-skew-ps = <420>; /* 0ps */
	rxd3-skew-ps = <420>; /* 0ps */
	txen-skew-ps = <0>; /* -420ps */
	txc-skew-ps = <900>; /* 0ps */
	rxdv-skew-ps = <420>; /* 0ps */
	rxc-skew-ps = <1680>; /* 780ps */
	};
	};
	};

	&mmc {
	status = "okay";
	cap-sd-highspeed;
	cap-mmc-highspeed;
	broken-cd;
	bus-width = <4>;
	};

	&uart0 {
	status = "okay";
	};

	&usb0 {
	status = "okay";
	disable-over-current;
	};

	&watchdog0 {
	status = "okay";
	};

	&i2c1 {
	status = "okay";
	clock-frequency = <100000>;
	i2c-sda-falling-time-ns = <890>; /* hcnt */
	i2c-sdl-falling-time-ns = <890>; /* lcnt */

	adc@14 {
	compatible = "lltc,ltc2497";
	reg = <0x14>;
	vref-supply = <&ref_033v>;
	};

	temp@4c {
	compatible = "maxim,max1619";
	reg = <0x4c>;
	};

	eeprom@51 {
	compatible = "atmel,24c32";
	reg = <0x51>;
	pagesize = <32>;
	};

	rtc@68 {
	compatible = "dallas,ds1339";
	reg = <0x68>;
	};
	};

	&qspi {
	flash@0 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "n25q00a";
	reg = <0>;
	spi-max-frequency = <100000000>;

	m25p,fast-read;
	cdns,page-size = <256>;
	cdns,block-size = <16>;
	cdns,read-delay = <1>;
	cdns,tshsl-ns = <50>;
	cdns,tsd2d-ns = <50>;
	cdns,tchsh-ns = <4>;
	cdns,tslch-ns = <4>;

	partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	qspi_boot: partition@0 {
	label = "Boot and fpga data";
	- reg = <0x0 0x034B0000>;
	+ reg = <0x0 0x03FE0000>;
	};

	- qspi_rootfs: partition@4000000 {
	+ qspi_rootfs: partition@3FE0000 {
	label = "Root Filesystem - JFFS2";
	- reg = <0x034B0000 0x0EB50000>;
	+ reg = <0x03FE0000 0x0C020000>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-a1.dtsi b/sys/gnu/dts/arm64/amlogic/meson-a1.dtsi
	index 4dec518c4dde..755b4ad15184 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-a1.dtsi
	+++ b/sys/gnu/dts/arm64/amlogic/meson-a1.dtsi
	@@ -1,155 +1,161 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
	*/

	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/gpio/meson-a1-gpio.h>

	/ {
	compatible = "amlogic,a1";

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a35";
	reg = <0x0 0x0>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a35";
	reg = <0x0 0x1>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	};

	l2: l2-cache0 {
	compatible = "cache";
	};
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	linux,cma {
	compatible = "shared-dma-pool";
	reusable;
	size = <0x0 0x800000>;
	alignment = <0x0 0x400000>;
	linux,cma-default;
	};
	};

	sm: secure-monitor {
	compatible = "amlogic,meson-gxbb-sm";
	+
	+ pwrc: power-controller {
	+ compatible = "amlogic,meson-a1-pwrc";
	+ #power-domain-cells = <1>;
	+ status = "okay";
	+ };
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	apb: bus@fe000000 {
	compatible = "simple-bus";
	reg = <0x0 0xfe000000 0x0 0x1000000>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;


	reset: reset-controller@0 {
	compatible = "amlogic,meson-a1-reset";
	reg = <0x0 0x0 0x0 0x8c>;
	#reset-cells = <1>;
	};

	periphs_pinctrl: pinctrl@0400 {
	compatible = "amlogic,meson-a1-periphs-pinctrl";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	gpio: bank@0400 {
	reg = <0x0 0x0400 0x0 0x003c>,
	<0x0 0x0480 0x0 0x0118>;
	reg-names = "mux", "gpio";
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&periphs_pinctrl 0 0 62>;
	};

	};

	uart_AO: serial@1c00 {
	compatible = "amlogic,meson-gx-uart",
	"amlogic,meson-ao-uart";
	reg = <0x0 0x1c00 0x0 0x18>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
	clocks = <&xtal>, <&xtal>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
	status = "disabled";
	};

	uart_AO_B: serial@2000 {
	compatible = "amlogic,meson-gx-uart",
	"amlogic,meson-ao-uart";
	reg = <0x0 0x2000 0x0 0x18>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
	clocks = <&xtal>, <&xtal>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
	status = "disabled";
	};
	};

	gic: interrupt-controller@ff901000 {
	compatible = "arm,gic-400";
	reg = <0x0 0xff901000 0x0 0x1000>,
	<0x0 0xff902000 0x0 0x2000>,
	<0x0 0xff904000 0x0 0x2000>,
	<0x0 0xff906000 0x0 0x2000>;
	interrupt-controller;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>;
	#interrupt-cells = <3>;
	#address-cells = <0>;
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13
	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14
	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11
	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10
	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	xtal: xtal-clk {
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-output-names = "xtal";
	#clock-cells = <0>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-axg-s400.dts b/sys/gnu/dts/arm64/amlogic/meson-axg-s400.dts
	index 4cd2d5951822..cb1360ae1211 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-axg-s400.dts
	+++ b/sys/gnu/dts/arm64/amlogic/meson-axg-s400.dts
	@@ -1,586 +1,586 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
	*/

	/dts-v1/;

	#include "meson-axg.dtsi"
	#include <dt-bindings/input/input.h>

	/ {
	compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg";
	model = "Amlogic Meson AXG S400 Development Board";

	adc_keys {
	compatible = "adc-keys";
	io-channels = <&saradc 0>;
	io-channel-names = "buttons";
	keyup-threshold-microvolt = <1800000>;

	button-next {
	label = "Next";
	linux,code = <KEY_NEXT>;
	press-threshold-microvolt = <1116000>; /* 62% */
	};

	button-prev {
	label = "Previous";
	linux,code = <KEY_PREVIOUS>;
	press-threshold-microvolt = <900000>; /* 50% */
	};

	button-wifi {
	label = "Wifi";
	linux,code = <KEY_WLAN>;
	press-threshold-microvolt = <684000>; /* 38% */
	};

	button-up {
	label = "Volume Up";
	linux,code = <KEY_VOLUMEUP>;
	press-threshold-microvolt = <468000>; /* 26% */
	};

	button-down {
	label = "Volume Down";
	linux,code = <KEY_VOLUMEDOWN>;
	press-threshold-microvolt = <252000>; /* 14% */
	};

	button-voice {
	label = "Voice";
	linux,code = <KEY_VOICECOMMAND>;
	press-threshold-microvolt = <0>; /* 0% */
	};
	};

	aliases {
	serial0 = &uart_AO;
	serial1 = &uart_A;
	};

	linein: audio-codec-0 {
	#sound-dai-cells = <0>;
	compatible = "everest,es7241";
	VDDA-supply = <&vcc_3v3>;
	VDDP-supply = <&vcc_3v3>;
	VDDD-supply = <&vcc_3v3>;
	status = "okay";
	sound-name-prefix = "Linein";
	};

	lineout: audio-codec-1 {
	#sound-dai-cells = <0>;
	compatible = "everest,es7154";
	VDD-supply = <&vcc_3v3>;
	PVDD-supply = <&vcc_5v>;
	status = "okay";
	sound-name-prefix = "Lineout";
	};

	spdif_dit: audio-codec-2 {
	#sound-dai-cells = <0>;
	compatible = "linux,spdif-dit";
	status = "okay";
	sound-name-prefix = "DIT";
	};

	dmics: audio-codec-3 {
	#sound-dai-cells = <0>;
	compatible = "dmic-codec";
	num-channels = <7>;
	wakeup-delay-ms = <50>;
	status = "okay";
	sound-name-prefix = "MIC";
	};

	spdif_dir: audio-codec-4 {
	#sound-dai-cells = <0>;
	compatible = "linux,spdif-dir";
	status = "okay";
	sound-name-prefix = "DIR";
	};

	emmc_pwrseq: emmc-pwrseq {
	compatible = "mmc-pwrseq-emmc";
	reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@0 {
	device_type = "memory";
	reg = <0x0 0x0 0x0 0x40000000>;
	};

	main_12v: regulator-main_12v {
	compatible = "regulator-fixed";
	regulator-name = "12V";
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	regulator-always-on;
	};

	vcc_3v3: regulator-vcc_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VCC_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vddao_3v3>;
	regulator-always-on;
	};

	vcc_5v: regulator-vcc_5v {
	compatible = "regulator-fixed";
	regulator-name = "VCC5V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&main_12v>;

	gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vddao_3v3: regulator-vddao_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VDDAO_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&main_12v>;
	regulator-always-on;
	};

	vddio_ao18: regulator-vddio_ao18 {
	compatible = "regulator-fixed";
	regulator-name = "VDDIO_AO18";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vddao_3v3>;
	regulator-always-on;
	};

	vddio_boot: regulator-vddio_boot {
	compatible = "regulator-fixed";
	regulator-name = "VDDIO_BOOT";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vddao_3v3>;
	regulator-always-on;
	};

	usb_pwr: regulator-usb_pwr {
	compatible = "regulator-fixed";
	regulator-name = "USB_PWR";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&vcc_5v>;

	gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
	clocks = <&wifi32k>;
	clock-names = "ext_clock";
	};

	speaker-leds {
	compatible = "gpio-leds";

	aled1 {
	label = "speaker:aled1";
	gpios = <&gpio_speaker 7 0>;
	};

	aled2 {
	label = "speaker:aled2";
	gpios = <&gpio_speaker 6 0>;
	};

	aled3 {
	label = "speaker:aled3";
	gpios = <&gpio_speaker 5 0>;
	};

	aled4 {
	label = "speaker:aled4";
	gpios = <&gpio_speaker 4 0>;
	};

	aled5 {
	label = "speaker:aled5";
	gpios = <&gpio_speaker 3 0>;
	};

	aled6 {
	label = "speaker:aled6";
	gpios = <&gpio_speaker 2 0>;
	};
	};

	sound {
	compatible = "amlogic,axg-sound-card";
	model = "AXG-S400";
	audio-aux-devs = <&tdmin_a>, <&tdmin_b>, <&tdmin_c>,
	<&tdmin_lb>, <&tdmout_c>;
	audio-widgets = "Line", "Lineout",
	"Line", "Linein",
	"Speaker", "Speaker1 Left",
	"Speaker", "Speaker1 Right";
	audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2",
	"SPDIFOUT IN 0", "FRDDR_A OUT 3",
	"TDMOUT_C IN 1", "FRDDR_B OUT 2",
	"SPDIFOUT IN 1", "FRDDR_B OUT 3",
	"TDMOUT_C IN 2", "FRDDR_C OUT 2",
	"SPDIFOUT IN 2", "FRDDR_C OUT 3",
	"TDM_C Playback", "TDMOUT_C OUT",
	"TDMIN_A IN 2", "TDM_C Capture",
	"TDMIN_A IN 5", "TDM_C Loopback",
	"TDMIN_B IN 2", "TDM_C Capture",
	"TDMIN_B IN 5", "TDM_C Loopback",
	"TDMIN_C IN 2", "TDM_C Capture",
	"TDMIN_C IN 5", "TDM_C Loopback",
	"TDMIN_LB IN 2", "TDM_C Loopback",
	"TDMIN_LB IN 5", "TDM_C Capture",
	"TODDR_A IN 0", "TDMIN_A OUT",
	"TODDR_B IN 0", "TDMIN_A OUT",
	"TODDR_C IN 0", "TDMIN_A OUT",
	"TODDR_A IN 1", "TDMIN_B OUT",
	"TODDR_B IN 1", "TDMIN_B OUT",
	"TODDR_C IN 1", "TDMIN_B OUT",
	"TODDR_A IN 2", "TDMIN_C OUT",
	"TODDR_B IN 2", "TDMIN_C OUT",
	"TODDR_C IN 2", "TDMIN_C OUT",
	"TODDR_A IN 3", "SPDIFIN Capture",
	"TODDR_B IN 3", "SPDIFIN Capture",
	"TODDR_C IN 3", "SPDIFIN Capture",
	"TODDR_A IN 4", "PDM Capture",
	"TODDR_B IN 4", "PDM Capture",
	"TODDR_C IN 4", "PDM Capture",
	"TODDR_A IN 6", "TDMIN_LB OUT",
	"TODDR_B IN 6", "TDMIN_LB OUT",
	"TODDR_C IN 6", "TDMIN_LB OUT",
	"Lineout", "Lineout AOUTL",
	"Lineout", "Lineout AOUTR",
	"Speaker1 Left", "SPK1 OUT_A",
	"Speaker1 Left", "SPK1 OUT_B",
	"Speaker1 Right", "SPK1 OUT_C",
	"Speaker1 Right", "SPK1 OUT_D",
	"Linein AINL", "Linein",
	"Linein AINR", "Linein";
	assigned-clocks = <&clkc CLKID_HIFI_PLL>,
	<&clkc CLKID_MPLL0>,
	<&clkc CLKID_MPLL1>;
	assigned-clock-parents = <0>, <0>, <0>;
	assigned-clock-rates = <589824000>,
	<270950400>,
	<393216000>;
	status = "okay";

	dai-link-0 {
	sound-dai = <&frddr_a>;
	};

	dai-link-1 {
	sound-dai = <&frddr_b>;
	};

	dai-link-2 {
	sound-dai = <&frddr_c>;
	};

	dai-link-3 {
	sound-dai = <&toddr_a>;
	};

	dai-link-4 {
	sound-dai = <&toddr_b>;
	};

	dai-link-5 {
	sound-dai = <&toddr_c>;
	};

	dai-link-6 {
	sound-dai = <&tdmif_c>;
	dai-format = "i2s";
	dai-tdm-slot-tx-mask-2 = <1 1>;
	dai-tdm-slot-rx-mask-1 = <1 1>;
	mclk-fs = <256>;

	- codec@0 {
	+ codec-0 {
	sound-dai = <&lineout>;
	};

	- codec@1 {
	+ codec-1 {
	sound-dai = <&speaker_amp1>;
	};

	- codec@2 {
	+ codec-2 {
	sound-dai = <&linein>;
	};

	};

	dai-link-7 {
	sound-dai = <&spdifout>;

	codec {
	sound-dai = <&spdif_dit>;
	};
	};

	dai-link-8 {
	sound-dai = <&spdifin>;

	codec {
	sound-dai = <&spdif_dir>;
	};
	};

	dai-link-9 {
	sound-dai = <&pdm>;

	codec {
	sound-dai = <&dmics>;
	};
	};
	};

	wifi32k: wifi32k {
	compatible = "pwm-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
	};
	};

	&ethmac {
	status = "okay";
	pinctrl-0 = <&eth_rgmii_y_pins>;
	pinctrl-names = "default";
	phy-handle = <&eth_phy0>;
	phy-mode = "rgmii";

	mdio {
	compatible = "snps,dwmac-mdio";
	#address-cells = <1>;
	#size-cells = <0>;

	eth_phy0: ethernet-phy@0 {
	/* Realtek RTL8211F (0x001cc916) */
	reg = <0>;
	interrupt-parent = <&gpio_intc>;
	interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
	eee-broken-1000t;
	};
	};
	};

	&frddr_a {
	status = "okay";
	};

	&frddr_b {
	status = "okay";
	};

	&frddr_c {
	status = "okay";
	};

	&ir {
	status = "okay";
	pinctrl-0 = <&remote_input_ao_pins>;
	pinctrl-names = "default";
	};

	&i2c1 {
	status = "okay";
	pinctrl-0 = <&i2c1_z_pins>;
	pinctrl-names = "default";

	speaker_amp1: audio-codec@1b {
	compatible = "ti,tas5707";
	reg = <0x1b>;
	reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
	#sound-dai-cells = <0>;
	AVDD-supply = <&vcc_3v3>;
	DVDD-supply = <&vcc_3v3>;
	PVDD_A-supply = <&main_12v>;
	PVDD_B-supply = <&main_12v>;
	PVDD_C-supply = <&main_12v>;
	PVDD_D-supply = <&main_12v>;
	sound-name-prefix = "SPK1";
	};
	};

	&i2c_AO {
	status = "okay";
	pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>;
	pinctrl-names = "default";

	gpio_speaker: gpio-controller@1f {
	compatible = "nxp,pca9557";
	reg = <0x1f>;
	gpio-controller;
	#gpio-cells = <2>;
	vcc-supply = <&vddao_3v3>;
	};
	};

	&pdm {
	pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>,
	<&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>;
	pinctrl-names = "default";
	status = "okay";
	};

	&pwm_ab {
	status = "okay";
	pinctrl-0 = <&pwm_a_x20_pins>;
	pinctrl-names = "default";
	};

	&saradc {
	status = "okay";
	vref-supply = <&vddio_ao18>;
	};

	/* wifi module */
	&sd_emmc_b {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	pinctrl-0 = <&sdio_pins>;
	pinctrl-1 = <&sdio_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <4>;
	cap-sd-highspeed;
	sd-uhs-sdr104;
	max-frequency = <200000000>;
	non-removable;
	disable-wp;

	mmc-pwrseq = <&sdio_pwrseq>;

	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vddio_boot>;

	brcmf: wifi@1 {
	reg = <1>;
	compatible = "brcm,bcm4329-fmac";
	};
	};

	/* emmc storage */
	&sd_emmc_c {
	status = "okay";
	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
	pinctrl-1 = <&emmc_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <8>;
	cap-mmc-highspeed;
	max-frequency = <200000000>;
	non-removable;
	disable-wp;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;

	mmc-pwrseq = <&emmc_pwrseq>;

	vmmc-supply = <&vcc_3v3>;
	vqmmc-supply = <&vddio_boot>;
	};

	&spdifin {
	pinctrl-0 = <&spdif_in_a19_pins>;
	pinctrl-names = "default";
	status = "okay";
	};

	&spdifout {
	pinctrl-0 = <&spdif_out_a20_pins>;
	pinctrl-names = "default";
	status = "okay";
	};

	&tdmif_a {
	pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>,
	<&tdma_din0_pins>, <&tdma_dout0_x15_pins>;
	pinctrl-names = "default";
	status = "okay";
	};

	&tdmif_b {
	pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>,
	<&tdmb_din3_pins>, <&mclk_b_pins>;
	pinctrl-names = "default";
	status = "okay";
	};

	&tdmif_c {
	pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>,
	<&tdmc_din1_pins>, <&tdmc_dout2_pins>,
	<&mclk_c_pins>;
	pinctrl-names = "default";
	status = "okay";
	};

	&tdmin_a {
	status = "okay";
	};

	&tdmin_b {
	status = "okay";
	};

	&tdmin_c {
	status = "okay";
	};

	&tdmin_lb {
	status = "okay";
	};

	&tdmout_c {
	status = "okay";
	};

	&toddr_a {
	status = "okay";
	};

	&toddr_b {
	status = "okay";
	};

	&toddr_c {
	status = "okay";
	};

	&uart_A {
	status = "okay";
	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
	pinctrl-names = "default";
	uart-has-rtscts;

	bluetooth {
	compatible = "brcm,bcm43438-bt";
	shutdown-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>;
	};
	};

	&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12-common.dtsi b/sys/gnu/dts/arm64/amlogic/meson-g12-common.dtsi
	index abe04f4ad7d8..c0aef7d69117 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-g12-common.dtsi
	+++ b/sys/gnu/dts/arm64/amlogic/meson-g12-common.dtsi
	@@ -1,2275 +1,2391 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
	*/

	#include <dt-bindings/phy/phy.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/clock/g12a-clkc.h>
	#include <dt-bindings/clock/g12a-aoclkc.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	simplefb_cvbs: framebuffer-cvbs {
	compatible = "amlogic,simple-framebuffer",
	"simple-framebuffer";
	amlogic,pipeline = "vpu-cvbs";
	clocks = <&clkc CLKID_HDMI>,
	<&clkc CLKID_HTX_PCLK>,
	<&clkc CLKID_VPU_INTR>;
	status = "disabled";
	};

	simplefb_hdmi: framebuffer-hdmi {
	compatible = "amlogic,simple-framebuffer",
	"simple-framebuffer";
	amlogic,pipeline = "vpu-hdmi";
	clocks = <&clkc CLKID_HDMI>,
	<&clkc CLKID_HTX_PCLK>,
	<&clkc CLKID_VPU_INTR>;
	status = "disabled";
	};
	};

	efuse: efuse {
	compatible = "amlogic,meson-gxbb-efuse";
	clocks = <&clkc CLKID_EFUSE>;
	#address-cells = <1>;
	#size-cells = <1>;
	read-only;
	secure-monitor = <&sm>;
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
	secmon_reserved: secmon@5000000 {
	reg = <0x0 0x05000000 0x0 0x300000>;
	no-map;
	};

	linux,cma {
	compatible = "shared-dma-pool";
	reusable;
	size = <0x0 0x10000000>;
	alignment = <0x0 0x400000>;
	linux,cma-default;
	};
	};

	sm: secure-monitor {
	compatible = "amlogic,meson-gxbb-sm";
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	pcie: pcie@fc000000 {
	compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
	reg = <0x0 0xfc000000 0x0 0x400000
	0x0 0xff648000 0x0 0x2000
	0x0 0xfc400000 0x0 0x200000>;
	reg-names = "elbi", "cfg", "config";
	interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
	bus-range = <0x0 0xff>;
	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000
	0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;

	clocks = <&clkc CLKID_PCIE_PHY
	&clkc CLKID_PCIE_COMB
	&clkc CLKID_PCIE_PLL>;
	clock-names = "general",
	"pclk",
	"port";
	resets = <&reset RESET_PCIE_CTRL_A>,
	<&reset RESET_PCIE_APB>;
	reset-names = "port",
	"apb";
	num-lanes = <1>;
	phys = <&usb3_pcie_phy PHY_TYPE_PCIE>;
	phy-names = "pcie";
	status = "disabled";
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	polling-delay = <1000>;
	polling-delay-passive = <100>;
	thermal-sensors = <&cpu_temp>;

	trips {
	cpu_passive: cpu-passive {
	temperature = <85000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "passive";
	};

	cpu_hot: cpu-hot {
	temperature = <95000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "hot";
	};

	cpu_critical: cpu-critical {
	temperature = <110000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "critical";
	};
	};
	};

	ddr_thermal: ddr-thermal {
	polling-delay = <1000>;
	polling-delay-passive = <100>;
	thermal-sensors = <&ddr_temp>;

	trips {
	ddr_passive: ddr-passive {
	temperature = <85000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "passive";
	};

	ddr_critical: ddr-critical {
	temperature = <110000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "critical";
	};
	};

	cooling-maps {
	map {
	trip = <&ddr_passive>;
	cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};
	};

	ethmac: ethernet@ff3f0000 {
	compatible = "amlogic,meson-axg-dwmac",
	"snps,dwmac-3.70a",
	"snps,dwmac";
	reg = <0x0 0xff3f0000 0x0 0x10000>,
	<0x0 0xff634540 0x0 0x8>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	clocks = <&clkc CLKID_ETH>,
	<&clkc CLKID_FCLK_DIV2>,
	<&clkc CLKID_MPLL2>;
	clock-names = "stmmaceth", "clkin0", "clkin1";
	rx-fifo-depth = <4096>;
	tx-fifo-depth = <2048>;
	status = "disabled";

	mdio0: mdio {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,dwmac-mdio";
	};
	};

	apb: bus@ff600000 {
	compatible = "simple-bus";
	reg = <0x0 0xff600000 0x0 0x200000>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;

	hdmi_tx: hdmi-tx@0 {
	compatible = "amlogic,meson-g12a-dw-hdmi";
	reg = <0x0 0x0 0x0 0x10000>;
	interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
	resets = <&reset RESET_HDMITX_CAPB3>,
	<&reset RESET_HDMITX_PHY>,
	<&reset RESET_HDMITX>;
	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
	clocks = <&clkc CLKID_HDMI>,
	<&clkc CLKID_HTX_PCLK>,
	<&clkc CLKID_VPU_INTR>;
	clock-names = "isfr", "iahb", "venci";
	#address-cells = <1>;
	#size-cells = <0>;
	#sound-dai-cells = <0>;
	status = "disabled";

	/* VPU VENC Input */
	hdmi_tx_venc_port: port@0 {
	reg = <0>;

	hdmi_tx_in: endpoint {
	remote-endpoint = <&hdmi_tx_out>;
	};
	};

	/* TMDS Output */
	hdmi_tx_tmds_port: port@1 {
	reg = <1>;
	};
	};

	apb_efuse: bus@30000 {
	compatible = "simple-bus";
	reg = <0x0 0x30000 0x0 0x2000>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;

	hwrng: rng@218 {
	compatible = "amlogic,meson-rng";
	reg = <0x0 0x218 0x0 0x4>;
	};
	};

	periphs: bus@34400 {
	compatible = "simple-bus";
	reg = <0x0 0x34400 0x0 0x400>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;

	periphs_pinctrl: pinctrl@40 {
	compatible = "amlogic,meson-g12a-periphs-pinctrl";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	gpio: bank@40 {
	reg = <0x0 0x40 0x0 0x4c>,
	<0x0 0xe8 0x0 0x18>,
	<0x0 0x120 0x0 0x18>,
	<0x0 0x2c0 0x0 0x40>,
	<0x0 0x340 0x0 0x1c>;
	reg-names = "gpio",
	"pull",
	"pull-enable",
	"mux",
	"ds";
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&periphs_pinctrl 0 0 86>;
	};

	cec_ao_a_h_pins: cec_ao_a_h {
	mux {
	groups = "cec_ao_a_h";
	function = "cec_ao_a_h";
	bias-disable;
	};
	};

	cec_ao_b_h_pins: cec_ao_b_h {
	mux {
	groups = "cec_ao_b_h";
	function = "cec_ao_b_h";
	bias-disable;
	};
	};

	- emmc_pins: emmc {
	+ emmc_ctrl_pins: emmc-ctrl {
	mux-0 {
	- groups = "emmc_nand_d0",
	- "emmc_nand_d1",
	- "emmc_nand_d2",
	- "emmc_nand_d3",
	- "emmc_nand_d4",
	- "emmc_nand_d5",
	- "emmc_nand_d6",
	- "emmc_nand_d7",
	- "emmc_cmd";
	+ groups = "emmc_cmd";
	function = "emmc";
	bias-pull-up;
	drive-strength-microamp = <4000>;
	};

	mux-1 {
	groups = "emmc_clk";
	function = "emmc";
	bias-disable;
	drive-strength-microamp = <4000>;
	};
	};

	+ emmc_data_4b_pins: emmc-data-4b {
	+ mux-0 {
	+ groups = "emmc_nand_d0",
	+ "emmc_nand_d1",
	+ "emmc_nand_d2",
	+ "emmc_nand_d3";
	+ function = "emmc";
	+ bias-pull-up;
	+ drive-strength-microamp = <4000>;
	+ };
	+ };
	+
	+ emmc_data_8b_pins: emmc-data-8b {
	+ mux-0 {
	+ groups = "emmc_nand_d0",
	+ "emmc_nand_d1",
	+ "emmc_nand_d2",
	+ "emmc_nand_d3",
	+ "emmc_nand_d4",
	+ "emmc_nand_d5",
	+ "emmc_nand_d6",
	+ "emmc_nand_d7";
	+ function = "emmc";
	+ bias-pull-up;
	+ drive-strength-microamp = <4000>;
	+ };
	+ };
	+
	emmc_ds_pins: emmc-ds {
	mux {
	groups = "emmc_nand_ds";
	function = "emmc";
	bias-pull-down;
	drive-strength-microamp = <4000>;
	};
	};

	emmc_clk_gate_pins: emmc_clk_gate {
	mux {
	groups = "BOOT_8";
	function = "gpio_periphs";
	bias-pull-down;
	drive-strength-microamp = <4000>;
	};
	};

	hdmitx_ddc_pins: hdmitx_ddc {
	mux {
	groups = "hdmitx_sda",
	"hdmitx_sck";
	function = "hdmitx";
	bias-disable;
	drive-strength-microamp = <4000>;
	};
	};

	hdmitx_hpd_pins: hdmitx_hpd {
	mux {
	groups = "hdmitx_hpd_in";
	function = "hdmitx";
	bias-disable;
	};
	};


	i2c0_sda_c_pins: i2c0-sda-c {
	mux {
	groups = "i2c0_sda_c";
	function = "i2c0";
	bias-disable;
	drive-strength-microamp = <3000>;

	};
	};

	i2c0_sck_c_pins: i2c0-sck-c {
	mux {
	groups = "i2c0_sck_c";
	function = "i2c0";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c0_sda_z0_pins: i2c0-sda-z0 {
	mux {
	groups = "i2c0_sda_z0";
	function = "i2c0";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c0_sck_z1_pins: i2c0-sck-z1 {
	mux {
	groups = "i2c0_sck_z1";
	function = "i2c0";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c0_sda_z7_pins: i2c0-sda-z7 {
	mux {
	groups = "i2c0_sda_z7";
	function = "i2c0";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c0_sda_z8_pins: i2c0-sda-z8 {
	mux {
	groups = "i2c0_sda_z8";
	function = "i2c0";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c1_sda_x_pins: i2c1-sda-x {
	mux {
	groups = "i2c1_sda_x";
	function = "i2c1";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c1_sck_x_pins: i2c1-sck-x {
	mux {
	groups = "i2c1_sck_x";
	function = "i2c1";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c1_sda_h2_pins: i2c1-sda-h2 {
	mux {
	groups = "i2c1_sda_h2";
	function = "i2c1";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c1_sck_h3_pins: i2c1-sck-h3 {
	mux {
	groups = "i2c1_sck_h3";
	function = "i2c1";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c1_sda_h6_pins: i2c1-sda-h6 {
	mux {
	groups = "i2c1_sda_h6";
	function = "i2c1";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c1_sck_h7_pins: i2c1-sck-h7 {
	mux {
	groups = "i2c1_sck_h7";
	function = "i2c1";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c2_sda_x_pins: i2c2-sda-x {
	mux {
	groups = "i2c2_sda_x";
	function = "i2c2";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c2_sck_x_pins: i2c2-sck-x {
	mux {
	groups = "i2c2_sck_x";
	function = "i2c2";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c2_sda_z_pins: i2c2-sda-z {
	mux {
	groups = "i2c2_sda_z";
	function = "i2c2";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c2_sck_z_pins: i2c2-sck-z {
	mux {
	groups = "i2c2_sck_z";
	function = "i2c2";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c3_sda_h_pins: i2c3-sda-h {
	mux {
	groups = "i2c3_sda_h";
	function = "i2c3";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c3_sck_h_pins: i2c3-sck-h {
	mux {
	groups = "i2c3_sck_h";
	function = "i2c3";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c3_sda_a_pins: i2c3-sda-a {
	mux {
	groups = "i2c3_sda_a";
	function = "i2c3";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c3_sck_a_pins: i2c3-sck-a {
	mux {
	groups = "i2c3_sck_a";
	function = "i2c3";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	mclk0_a_pins: mclk0-a {
	mux {
	groups = "mclk0_a";
	function = "mclk0";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	mclk1_a_pins: mclk1-a {
	mux {
	groups = "mclk1_a";
	function = "mclk1";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	mclk1_x_pins: mclk1-x {
	mux {
	groups = "mclk1_x";
	function = "mclk1";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	mclk1_z_pins: mclk1-z {
	mux {
	groups = "mclk1_z";
	function = "mclk1";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	+ nor_pins: nor {
	+ mux {
	+ groups = "nor_d",
	+ "nor_q",
	+ "nor_c",
	+ "nor_cs";
	+ function = "nor";
	+ bias-disable;
	+ };
	+ };
	+
	pdm_din0_a_pins: pdm-din0-a {
	mux {
	groups = "pdm_din0_a";
	function = "pdm";
	bias-disable;
	};
	};

	pdm_din0_c_pins: pdm-din0-c {
	mux {
	groups = "pdm_din0_c";
	function = "pdm";
	bias-disable;
	};
	};

	pdm_din0_x_pins: pdm-din0-x {
	mux {
	groups = "pdm_din0_x";
	function = "pdm";
	bias-disable;
	};
	};

	pdm_din0_z_pins: pdm-din0-z {
	mux {
	groups = "pdm_din0_z";
	function = "pdm";
	bias-disable;
	};
	};

	pdm_din1_a_pins: pdm-din1-a {
	mux {
	groups = "pdm_din1_a";
	function = "pdm";
	bias-disable;
	};
	};

	pdm_din1_c_pins: pdm-din1-c {
	mux {
	groups = "pdm_din1_c";
	function = "pdm";
	bias-disable;
	};
	};

	pdm_din1_x_pins: pdm-din1-x {
	mux {
	groups = "pdm_din1_x";
	function = "pdm";
	bias-disable;
	};
	};

	pdm_din1_z_pins: pdm-din1-z {
	mux {
	groups = "pdm_din1_z";
	function = "pdm";
	bias-disable;
	};
	};

	pdm_din2_a_pins: pdm-din2-a {
	mux {
	groups = "pdm_din2_a";
	function = "pdm";
	bias-disable;
	};
	};

	pdm_din2_c_pins: pdm-din2-c {
	mux {
	groups = "pdm_din2_c";
	function = "pdm";
	bias-disable;
	};
	};

	pdm_din2_x_pins: pdm-din2-x {
	mux {
	groups = "pdm_din2_x";
	function = "pdm";
	bias-disable;
	};
	};

	pdm_din2_z_pins: pdm-din2-z {
	mux {
	groups = "pdm_din2_z";
	function = "pdm";
	bias-disable;
	};
	};

	pdm_din3_a_pins: pdm-din3-a {
	mux {
	groups = "pdm_din3_a";
	function = "pdm";
	bias-disable;
	};
	};

	pdm_din3_c_pins: pdm-din3-c {
	mux {
	groups = "pdm_din3_c";
	function = "pdm";
	bias-disable;
	};
	};

	pdm_din3_x_pins: pdm-din3-x {
	mux {
	groups = "pdm_din3_x";
	function = "pdm";
	bias-disable;
	};
	};

	pdm_din3_z_pins: pdm-din3-z {
	mux {
	groups = "pdm_din3_z";
	function = "pdm";
	bias-disable;
	};
	};

	pdm_dclk_a_pins: pdm-dclk-a {
	mux {
	groups = "pdm_dclk_a";
	function = "pdm";
	bias-disable;
	drive-strength-microamp = <500>;
	};
	};

	pdm_dclk_c_pins: pdm-dclk-c {
	mux {
	groups = "pdm_dclk_c";
	function = "pdm";
	bias-disable;
	drive-strength-microamp = <500>;
	};
	};

	pdm_dclk_x_pins: pdm-dclk-x {
	mux {
	groups = "pdm_dclk_x";
	function = "pdm";
	bias-disable;
	drive-strength-microamp = <500>;
	};
	};

	pdm_dclk_z_pins: pdm-dclk-z {
	mux {
	groups = "pdm_dclk_z";
	function = "pdm";
	bias-disable;
	drive-strength-microamp = <500>;
	};
	};

	pwm_a_pins: pwm-a {
	mux {
	groups = "pwm_a";
	function = "pwm_a";
	bias-disable;
	};
	};

	pwm_b_x7_pins: pwm-b-x7 {
	mux {
	groups = "pwm_b_x7";
	function = "pwm_b";
	bias-disable;
	};
	};

	pwm_b_x19_pins: pwm-b-x19 {
	mux {
	groups = "pwm_b_x19";
	function = "pwm_b";
	bias-disable;
	};
	};

	pwm_c_c_pins: pwm-c-c {
	mux {
	groups = "pwm_c_c";
	function = "pwm_c";
	bias-disable;
	};
	};

	pwm_c_x5_pins: pwm-c-x5 {
	mux {
	groups = "pwm_c_x5";
	function = "pwm_c";
	bias-disable;
	};
	};

	pwm_c_x8_pins: pwm-c-x8 {
	mux {
	groups = "pwm_c_x8";
	function = "pwm_c";
	bias-disable;
	};
	};

	pwm_d_x3_pins: pwm-d-x3 {
	mux {
	groups = "pwm_d_x3";
	function = "pwm_d";
	bias-disable;
	};
	};

	pwm_d_x6_pins: pwm-d-x6 {
	mux {
	groups = "pwm_d_x6";
	function = "pwm_d";
	bias-disable;
	};
	};

	pwm_e_pins: pwm-e {
	mux {
	groups = "pwm_e";
	function = "pwm_e";
	bias-disable;
	};
	};

	pwm_f_x_pins: pwm-f-x {
	mux {
	groups = "pwm_f_x";
	function = "pwm_f";
	bias-disable;
	};
	};

	pwm_f_h_pins: pwm-f-h {
	mux {
	groups = "pwm_f_h";
	function = "pwm_f";
	bias-disable;
	};
	};

	sdcard_c_pins: sdcard_c {
	mux-0 {
	groups = "sdcard_d0_c",
	"sdcard_d1_c",
	"sdcard_d2_c",
	"sdcard_d3_c",
	"sdcard_cmd_c";
	function = "sdcard";
	bias-pull-up;
	drive-strength-microamp = <4000>;
	};

	mux-1 {
	groups = "sdcard_clk_c";
	function = "sdcard";
	bias-disable;
	drive-strength-microamp = <4000>;
	};
	};

	sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
	mux {
	groups = "GPIOC_4";
	function = "gpio_periphs";
	bias-pull-down;
	drive-strength-microamp = <4000>;
	};
	};

	sdcard_z_pins: sdcard_z {
	mux-0 {
	groups = "sdcard_d0_z",
	"sdcard_d1_z",
	"sdcard_d2_z",
	"sdcard_d3_z",
	"sdcard_cmd_z";
	function = "sdcard";
	bias-pull-up;
	drive-strength-microamp = <4000>;
	};

	mux-1 {
	groups = "sdcard_clk_z";
	function = "sdcard";
	bias-disable;
	drive-strength-microamp = <4000>;
	};
	};

	sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
	mux {
	groups = "GPIOZ_6";
	function = "gpio_periphs";
	bias-pull-down;
	drive-strength-microamp = <4000>;
	};
	};

	sdio_pins: sdio {
	mux {
	groups = "sdio_d0",
	"sdio_d1",
	"sdio_d2",
	"sdio_d3",
	"sdio_clk",
	"sdio_cmd";
	function = "sdio";
	bias-disable;
	drive-strength-microamp = <4000>;
	};
	};

	sdio_clk_gate_pins: sdio_clk_gate {
	mux {
	groups = "GPIOX_4";
	function = "gpio_periphs";
	bias-pull-down;
	drive-strength-microamp = <4000>;
	};
	};

	spdif_in_a10_pins: spdif-in-a10 {
	mux {
	groups = "spdif_in_a10";
	function = "spdif_in";
	bias-disable;
	};
	};

	spdif_in_a12_pins: spdif-in-a12 {
	mux {
	groups = "spdif_in_a12";
	function = "spdif_in";
	bias-disable;
	};
	};

	spdif_in_h_pins: spdif-in-h {
	mux {
	groups = "spdif_in_h";
	function = "spdif_in";
	bias-disable;
	};
	};

	spdif_out_h_pins: spdif-out-h {
	mux {
	groups = "spdif_out_h";
	function = "spdif_out";
	drive-strength-microamp = <500>;
	bias-disable;
	};
	};

	spdif_out_a11_pins: spdif-out-a11 {
	mux {
	groups = "spdif_out_a11";
	function = "spdif_out";
	drive-strength-microamp = <500>;
	bias-disable;
	};
	};

	spdif_out_a13_pins: spdif-out-a13 {
	mux {
	groups = "spdif_out_a13";
	function = "spdif_out";
	drive-strength-microamp = <500>;
	bias-disable;
	};
	};

	+ spicc0_x_pins: spicc0-x {
	+ mux {
	+ groups = "spi0_mosi_x",
	+ "spi0_miso_x",
	+ "spi0_clk_x";
	+ function = "spi0";
	+ drive-strength-microamp = <4000>;
	+ bias-disable;
	+ };
	+ };
	+
	+ spicc0_ss0_x_pins: spicc0-ss0-x {
	+ mux {
	+ groups = "spi0_ss0_x";
	+ function = "spi0";
	+ drive-strength-microamp = <4000>;
	+ bias-disable;
	+ };
	+ };
	+
	+ spicc0_c_pins: spicc0-c {
	+ mux {
	+ groups = "spi0_mosi_c",
	+ "spi0_miso_c",
	+ "spi0_ss0_c",
	+ "spi0_clk_c";
	+ function = "spi0";
	+ drive-strength-microamp = <4000>;
	+ bias-disable;
	+ };
	+ };
	+
	+ spicc1_pins: spicc1 {
	+ mux {
	+ groups = "spi1_mosi",
	+ "spi1_miso",
	+ "spi1_clk";
	+ function = "spi1";
	+ drive-strength-microamp = <4000>;
	+ };
	+ };
	+
	+ spicc1_ss0_pins: spicc1-ss0 {
	+ mux {
	+ groups = "spi1_ss0";
	+ function = "spi1";
	+ drive-strength-microamp = <4000>;
	+ bias-disable;
	+ };
	+ };
	+
	tdm_a_din0_pins: tdm-a-din0 {
	mux {
	groups = "tdm_a_din0";
	function = "tdm_a";
	bias-disable;
	};
	};


	tdm_a_din1_pins: tdm-a-din1 {
	mux {
	groups = "tdm_a_din1";
	function = "tdm_a";
	bias-disable;
	};
	};

	tdm_a_dout0_pins: tdm-a-dout0 {
	mux {
	groups = "tdm_a_dout0";
	function = "tdm_a";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_a_dout1_pins: tdm-a-dout1 {
	mux {
	groups = "tdm_a_dout1";
	function = "tdm_a";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_a_fs_pins: tdm-a-fs {
	mux {
	groups = "tdm_a_fs";
	function = "tdm_a";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_a_sclk_pins: tdm-a-sclk {
	mux {
	groups = "tdm_a_sclk";
	function = "tdm_a";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_a_slv_fs_pins: tdm-a-slv-fs {
	mux {
	groups = "tdm_a_slv_fs";
	function = "tdm_a";
	bias-disable;
	};
	};


	tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
	mux {
	groups = "tdm_a_slv_sclk";
	function = "tdm_a";
	bias-disable;
	};
	};

	tdm_b_din0_pins: tdm-b-din0 {
	mux {
	groups = "tdm_b_din0";
	function = "tdm_b";
	bias-disable;
	};
	};

	tdm_b_din1_pins: tdm-b-din1 {
	mux {
	groups = "tdm_b_din1";
	function = "tdm_b";
	bias-disable;
	};
	};

	tdm_b_din2_pins: tdm-b-din2 {
	mux {
	groups = "tdm_b_din2";
	function = "tdm_b";
	bias-disable;
	};
	};

	tdm_b_din3_a_pins: tdm-b-din3-a {
	mux {
	groups = "tdm_b_din3_a";
	function = "tdm_b";
	bias-disable;
	};
	};

	tdm_b_din3_h_pins: tdm-b-din3-h {
	mux {
	groups = "tdm_b_din3_h";
	function = "tdm_b";
	bias-disable;
	};
	};

	tdm_b_dout0_pins: tdm-b-dout0 {
	mux {
	groups = "tdm_b_dout0";
	function = "tdm_b";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_b_dout1_pins: tdm-b-dout1 {
	mux {
	groups = "tdm_b_dout1";
	function = "tdm_b";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_b_dout2_pins: tdm-b-dout2 {
	mux {
	groups = "tdm_b_dout2";
	function = "tdm_b";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_b_dout3_a_pins: tdm-b-dout3-a {
	mux {
	groups = "tdm_b_dout3_a";
	function = "tdm_b";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_b_dout3_h_pins: tdm-b-dout3-h {
	mux {
	groups = "tdm_b_dout3_h";
	function = "tdm_b";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_b_fs_pins: tdm-b-fs {
	mux {
	groups = "tdm_b_fs";
	function = "tdm_b";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_b_sclk_pins: tdm-b-sclk {
	mux {
	groups = "tdm_b_sclk";
	function = "tdm_b";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_b_slv_fs_pins: tdm-b-slv-fs {
	mux {
	groups = "tdm_b_slv_fs";
	function = "tdm_b";
	bias-disable;
	};
	};

	tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
	mux {
	groups = "tdm_b_slv_sclk";
	function = "tdm_b";
	bias-disable;
	};
	};

	tdm_c_din0_a_pins: tdm-c-din0-a {
	mux {
	groups = "tdm_c_din0_a";
	function = "tdm_c";
	bias-disable;
	};
	};

	tdm_c_din0_z_pins: tdm-c-din0-z {
	mux {
	groups = "tdm_c_din0_z";
	function = "tdm_c";
	bias-disable;
	};
	};

	tdm_c_din1_a_pins: tdm-c-din1-a {
	mux {
	groups = "tdm_c_din1_a";
	function = "tdm_c";
	bias-disable;
	};
	};

	tdm_c_din1_z_pins: tdm-c-din1-z {
	mux {
	groups = "tdm_c_din1_z";
	function = "tdm_c";
	bias-disable;
	};
	};

	tdm_c_din2_a_pins: tdm-c-din2-a {
	mux {
	groups = "tdm_c_din2_a";
	function = "tdm_c";
	bias-disable;
	};
	};

	eth_leds_pins: eth-leds {
	mux {
	groups = "eth_link_led",
	"eth_act_led";
	function = "eth";
	bias-disable;
	};
	};

	eth_pins: eth {
	mux {
	groups = "eth_mdio",
	"eth_mdc",
	"eth_rgmii_rx_clk",
	"eth_rx_dv",
	"eth_rxd0",
	"eth_rxd1",
	"eth_txen",
	"eth_txd0",
	"eth_txd1";
	function = "eth";
	drive-strength-microamp = <4000>;
	bias-disable;
	};
	};

	eth_rgmii_pins: eth-rgmii {
	mux {
	groups = "eth_rxd2_rgmii",
	"eth_rxd3_rgmii",
	"eth_rgmii_tx_clk",
	"eth_txd2_rgmii",
	"eth_txd3_rgmii";
	function = "eth";
	drive-strength-microamp = <4000>;
	bias-disable;
	};
	};

	tdm_c_din2_z_pins: tdm-c-din2-z {
	mux {
	groups = "tdm_c_din2_z";
	function = "tdm_c";
	bias-disable;
	};
	};

	tdm_c_din3_a_pins: tdm-c-din3-a {
	mux {
	groups = "tdm_c_din3_a";
	function = "tdm_c";
	bias-disable;
	};
	};

	tdm_c_din3_z_pins: tdm-c-din3-z {
	mux {
	groups = "tdm_c_din3_z";
	function = "tdm_c";
	bias-disable;
	};
	};

	tdm_c_dout0_a_pins: tdm-c-dout0-a {
	mux {
	groups = "tdm_c_dout0_a";
	function = "tdm_c";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_c_dout0_z_pins: tdm-c-dout0-z {
	mux {
	groups = "tdm_c_dout0_z";
	function = "tdm_c";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_c_dout1_a_pins: tdm-c-dout1-a {
	mux {
	groups = "tdm_c_dout1_a";
	function = "tdm_c";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_c_dout1_z_pins: tdm-c-dout1-z {
	mux {
	groups = "tdm_c_dout1_z";
	function = "tdm_c";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_c_dout2_a_pins: tdm-c-dout2-a {
	mux {
	groups = "tdm_c_dout2_a";
	function = "tdm_c";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_c_dout2_z_pins: tdm-c-dout2-z {
	mux {
	groups = "tdm_c_dout2_z";
	function = "tdm_c";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_c_dout3_a_pins: tdm-c-dout3-a {
	mux {
	groups = "tdm_c_dout3_a";
	function = "tdm_c";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_c_dout3_z_pins: tdm-c-dout3-z {
	mux {
	groups = "tdm_c_dout3_z";
	function = "tdm_c";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_c_fs_a_pins: tdm-c-fs-a {
	mux {
	groups = "tdm_c_fs_a";
	function = "tdm_c";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_c_fs_z_pins: tdm-c-fs-z {
	mux {
	groups = "tdm_c_fs_z";
	function = "tdm_c";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_c_sclk_a_pins: tdm-c-sclk-a {
	mux {
	groups = "tdm_c_sclk_a";
	function = "tdm_c";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_c_sclk_z_pins: tdm-c-sclk-z {
	mux {
	groups = "tdm_c_sclk_z";
	function = "tdm_c";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
	mux {
	groups = "tdm_c_slv_fs_a";
	function = "tdm_c";
	bias-disable;
	};
	};

	tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
	mux {
	groups = "tdm_c_slv_fs_z";
	function = "tdm_c";
	bias-disable;
	};
	};

	tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
	mux {
	groups = "tdm_c_slv_sclk_a";
	function = "tdm_c";
	bias-disable;
	};
	};

	tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
	mux {
	groups = "tdm_c_slv_sclk_z";
	function = "tdm_c";
	bias-disable;
	};
	};

	uart_a_pins: uart-a {
	mux {
	groups = "uart_a_tx",
	"uart_a_rx";
	function = "uart_a";
	bias-disable;
	};
	};

	uart_a_cts_rts_pins: uart-a-cts-rts {
	mux {
	groups = "uart_a_cts",
	"uart_a_rts";
	function = "uart_a";
	bias-disable;
	};
	};

	uart_b_pins: uart-b {
	mux {
	groups = "uart_b_tx",
	"uart_b_rx";
	function = "uart_b";
	bias-disable;
	};
	};

	uart_c_pins: uart-c {
	mux {
	groups = "uart_c_tx",
	"uart_c_rx";
	function = "uart_c";
	bias-disable;
	};
	};

	uart_c_cts_rts_pins: uart-c-cts-rts {
	mux {
	groups = "uart_c_cts",
	"uart_c_rts";
	function = "uart_c";
	bias-disable;
	};
	};
	};
	};

	cpu_temp: temperature-sensor@34800 {
	compatible = "amlogic,g12a-cpu-thermal",
	"amlogic,g12a-thermal";
	reg = <0x0 0x34800 0x0 0x50>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc CLKID_TS>;
	#thermal-sensor-cells = <0>;
	amlogic,ao-secure = <&sec_AO>;
	};

	ddr_temp: temperature-sensor@34c00 {
	compatible = "amlogic,g12a-ddr-thermal",
	"amlogic,g12a-thermal";
	reg = <0x0 0x34c00 0x0 0x50>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc CLKID_TS>;
	#thermal-sensor-cells = <0>;
	amlogic,ao-secure = <&sec_AO>;
	};

	usb2_phy0: phy@36000 {
	compatible = "amlogic,g12a-usb2-phy";
	reg = <0x0 0x36000 0x0 0x2000>;
	clocks = <&xtal>;
	clock-names = "xtal";
	resets = <&reset RESET_USB_PHY20>;
	reset-names = "phy";
	#phy-cells = <0>;
	};

	dmc: bus@38000 {
	compatible = "simple-bus";
	reg = <0x0 0x38000 0x0 0x400>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;

	canvas: video-lut@48 {
	compatible = "amlogic,canvas";
	reg = <0x0 0x48 0x0 0x14>;
	};
	};

	usb2_phy1: phy@3a000 {
	compatible = "amlogic,g12a-usb2-phy";
	reg = <0x0 0x3a000 0x0 0x2000>;
	clocks = <&xtal>;
	clock-names = "xtal";
	resets = <&reset RESET_USB_PHY21>;
	reset-names = "phy";
	#phy-cells = <0>;
	};

	hiu: bus@3c000 {
	compatible = "simple-bus";
	reg = <0x0 0x3c000 0x0 0x1400>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;

	hhi: system-controller@0 {
	compatible = "amlogic,meson-gx-hhi-sysctrl",
	"simple-mfd", "syscon";
	reg = <0 0 0 0x400>;

	clkc: clock-controller {
	compatible = "amlogic,g12a-clkc";
	#clock-cells = <1>;
	clocks = <&xtal>;
	clock-names = "xtal";
	};

	pwrc: power-controller {
	compatible = "amlogic,meson-g12a-pwrc";
	#power-domain-cells = <1>;
	amlogic,ao-sysctrl = <&rti>;
	resets = <&reset RESET_VIU>,
	<&reset RESET_VENC>,
	<&reset RESET_VCBUS>,
	<&reset RESET_BT656>,
	<&reset RESET_RDMA>,
	<&reset RESET_VENCI>,
	<&reset RESET_VENCP>,
	<&reset RESET_VDAC>,
	<&reset RESET_VDI6>,
	<&reset RESET_VENCL>,
	<&reset RESET_VID_LOCK>;
	reset-names = "viu", "venc", "vcbus", "bt656",
	"rdma", "venci", "vencp", "vdac",
	"vdi6", "vencl", "vid_lock";
	clocks = <&clkc CLKID_VPU>,
	<&clkc CLKID_VAPB>;
	clock-names = "vpu", "vapb";
	/*
	* VPU clocking is provided by two identical clock paths
	* VPU_0 and VPU_1 muxed to a single clock by a glitch
	* free mux to safely change frequency while running.
	* Same for VAPB but with a final gate after the glitch free mux.
	*/
	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
	<&clkc CLKID_VPU_0>,
	<&clkc CLKID_VPU>, /* Glitch free mux */
	<&clkc CLKID_VAPB_0_SEL>,
	<&clkc CLKID_VAPB_0>,
	<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
	<0>, /* Do Nothing */
	<&clkc CLKID_VPU_0>,
	<&clkc CLKID_FCLK_DIV4>,
	<0>, /* Do Nothing */
	<&clkc CLKID_VAPB_0>;
	assigned-clock-rates = <0>, /* Do Nothing */
	<666666666>,
	<0>, /* Do Nothing */
	<0>, /* Do Nothing */
	<250000000>,
	<0>; /* Do Nothing */
	};
	};
	};

	usb3_pcie_phy: phy@46000 {
	compatible = "amlogic,g12a-usb3-pcie-phy";
	reg = <0x0 0x46000 0x0 0x2000>;
	clocks = <&clkc CLKID_PCIE_PLL>;
	clock-names = "ref_clk";
	resets = <&reset RESET_PCIE_PHY>;
	reset-names = "phy";
	assigned-clocks = <&clkc CLKID_PCIE_PLL>;
	assigned-clock-rates = <100000000>;
	#phy-cells = <1>;
	};

	eth_phy: mdio-multiplexer@4c000 {
	compatible = "amlogic,g12a-mdio-mux";
	reg = <0x0 0x4c000 0x0 0xa4>;
	clocks = <&clkc CLKID_ETH_PHY>,
	<&xtal>,
	<&clkc CLKID_MPLL_50M>;
	clock-names = "pclk", "clkin0", "clkin1";
	mdio-parent-bus = <&mdio0>;
	#address-cells = <1>;
	#size-cells = <0>;

	ext_mdio: mdio@0 {
	reg = <0>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	int_mdio: mdio@1 {
	reg = <1>;
	#address-cells = <1>;
	#size-cells = <0>;

	internal_ephy: ethernet_phy@8 {
	compatible = "ethernet-phy-id0180.3301",
	"ethernet-phy-ieee802.3-c22";
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	reg = <8>;
	max-speed = <100>;
	};
	};
	};
	};

	aobus: bus@ff800000 {
	compatible = "simple-bus";
	reg = <0x0 0xff800000 0x0 0x100000>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;

	rti: sys-ctrl@0 {
	compatible = "amlogic,meson-gx-ao-sysctrl",
	"simple-mfd", "syscon";
	reg = <0x0 0x0 0x0 0x100>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;

	clkc_AO: clock-controller {
	compatible = "amlogic,meson-g12a-aoclkc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	clocks = <&xtal>, <&clkc CLKID_CLK81>;
	clock-names = "xtal", "mpeg-clk";
	};

	ao_pinctrl: pinctrl@14 {
	compatible = "amlogic,meson-g12a-aobus-pinctrl";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	gpio_ao: bank@14 {
	reg = <0x0 0x14 0x0 0x8>,
	<0x0 0x1c 0x0 0x8>,
	<0x0 0x24 0x0 0x14>;
	reg-names = "mux",
	"ds",
	"gpio";
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&ao_pinctrl 0 0 15>;
	};

	i2c_ao_sck_pins: i2c_ao_sck_pins {
	mux {
	groups = "i2c_ao_sck";
	function = "i2c_ao";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c_ao_sda_pins: i2c_ao_sda {
	mux {
	groups = "i2c_ao_sda";
	function = "i2c_ao";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c_ao_sck_e_pins: i2c_ao_sck_e {
	mux {
	groups = "i2c_ao_sck_e";
	function = "i2c_ao";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	i2c_ao_sda_e_pins: i2c_ao_sda_e {
	mux {
	groups = "i2c_ao_sda_e";
	function = "i2c_ao";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	mclk0_ao_pins: mclk0-ao {
	mux {
	groups = "mclk0_ao";
	function = "mclk0_ao";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_ao_b_din0_pins: tdm-ao-b-din0 {
	mux {
	groups = "tdm_ao_b_din0";
	function = "tdm_ao_b";
	bias-disable;
	};
	};

	spdif_ao_out_pins: spdif-ao-out {
	mux {
	groups = "spdif_ao_out";
	function = "spdif_ao_out";
	drive-strength-microamp = <500>;
	bias-disable;
	};
	};

	tdm_ao_b_din1_pins: tdm-ao-b-din1 {
	mux {
	groups = "tdm_ao_b_din1";
	function = "tdm_ao_b";
	bias-disable;
	};
	};

	tdm_ao_b_din2_pins: tdm-ao-b-din2 {
	mux {
	groups = "tdm_ao_b_din2";
	function = "tdm_ao_b";
	bias-disable;
	};
	};

	tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
	mux {
	groups = "tdm_ao_b_dout0";
	function = "tdm_ao_b";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
	mux {
	groups = "tdm_ao_b_dout1";
	function = "tdm_ao_b";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
	mux {
	groups = "tdm_ao_b_dout2";
	function = "tdm_ao_b";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_ao_b_fs_pins: tdm-ao-b-fs {
	mux {
	groups = "tdm_ao_b_fs";
	function = "tdm_ao_b";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
	mux {
	groups = "tdm_ao_b_sclk";
	function = "tdm_ao_b";
	bias-disable;
	drive-strength-microamp = <3000>;
	};
	};

	tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
	mux {
	groups = "tdm_ao_b_slv_fs";
	function = "tdm_ao_b";
	bias-disable;
	};
	};

	tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
	mux {
	groups = "tdm_ao_b_slv_sclk";
	function = "tdm_ao_b";
	bias-disable;
	};
	};

	uart_ao_a_pins: uart-a-ao {
	mux {
	groups = "uart_ao_a_tx",
	"uart_ao_a_rx";
	function = "uart_ao_a";
	bias-disable;
	};
	};

	uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
	mux {
	groups = "uart_ao_a_cts",
	"uart_ao_a_rts";
	function = "uart_ao_a";
	bias-disable;
	};
	};

	pwm_a_e_pins: pwm-a-e {
	mux {
	groups = "pwm_a_e";
	function = "pwm_a_e";
	bias-disable;
	};
	};

	pwm_ao_a_pins: pwm-ao-a {
	mux {
	groups = "pwm_ao_a";
	function = "pwm_ao_a";
	bias-disable;
	};
	};

	pwm_ao_b_pins: pwm-ao-b {
	mux {
	groups = "pwm_ao_b";
	function = "pwm_ao_b";
	bias-disable;
	};
	};

	pwm_ao_c_4_pins: pwm-ao-c-4 {
	mux {
	groups = "pwm_ao_c_4";
	function = "pwm_ao_c";
	bias-disable;
	};
	};

	pwm_ao_c_6_pins: pwm-ao-c-6 {
	mux {
	groups = "pwm_ao_c_6";
	function = "pwm_ao_c";
	bias-disable;
	};
	};

	pwm_ao_d_5_pins: pwm-ao-d-5 {
	mux {
	groups = "pwm_ao_d_5";
	function = "pwm_ao_d";
	bias-disable;
	};
	};

	pwm_ao_d_10_pins: pwm-ao-d-10 {
	mux {
	groups = "pwm_ao_d_10";
	function = "pwm_ao_d";
	bias-disable;
	};
	};

	pwm_ao_d_e_pins: pwm-ao-d-e {
	mux {
	groups = "pwm_ao_d_e";
	function = "pwm_ao_d";
	};
	};

	remote_input_ao_pins: remote-input-ao {
	mux {
	groups = "remote_ao_input";
	function = "remote_ao_input";
	bias-disable;
	};
	};
	};
	};

	vrtc: rtc@0a8 {
	compatible = "amlogic,meson-vrtc";
	reg = <0x0 0x000a8 0x0 0x4>;
	};

	cec_AO: cec@100 {
	compatible = "amlogic,meson-gx-ao-cec";
	reg = <0x0 0x00100 0x0 0x14>;
	interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc_AO CLKID_AO_CEC>;
	clock-names = "core";
	status = "disabled";
	};

	sec_AO: ao-secure@140 {
	compatible = "amlogic,meson-gx-ao-secure", "syscon";
	reg = <0x0 0x140 0x0 0x140>;
	amlogic,has-chip-id;
	};

	cecb_AO: cec@280 {
	compatible = "amlogic,meson-g12a-ao-cec";
	reg = <0x0 0x00280 0x0 0x1c>;
	interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
	clock-names = "oscin";
	status = "disabled";
	};

	pwm_AO_cd: pwm@2000 {
	compatible = "amlogic,meson-g12a-ao-pwm-cd";
	reg = <0x0 0x2000 0x0 0x20>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	uart_AO: serial@3000 {
	compatible = "amlogic,meson-gx-uart",
	"amlogic,meson-ao-uart";
	reg = <0x0 0x3000 0x0 0x18>;
	interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
	status = "disabled";
	};

	uart_AO_B: serial@4000 {
	compatible = "amlogic,meson-gx-uart",
	"amlogic,meson-ao-uart";
	reg = <0x0 0x4000 0x0 0x18>;
	interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
	status = "disabled";
	};

	i2c_AO: i2c@5000 {
	compatible = "amlogic,meson-axg-i2c";
	status = "disabled";
	reg = <0x0 0x05000 0x0 0x20>;
	interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&clkc CLKID_I2C>;
	};

	pwm_AO_ab: pwm@7000 {
	compatible = "amlogic,meson-g12a-ao-pwm-ab";
	reg = <0x0 0x7000 0x0 0x20>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	ir: ir@8000 {
	compatible = "amlogic,meson-gxbb-ir";
	reg = <0x0 0x8000 0x0 0x20>;
	interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
	status = "disabled";
	};

	saradc: adc@9000 {
	compatible = "amlogic,meson-g12a-saradc",
	"amlogic,meson-saradc";
	reg = <0x0 0x9000 0x0 0x48>;
	#io-channel-cells = <1>;
	interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
	clocks = <&xtal>,
	<&clkc_AO CLKID_AO_SAR_ADC>,
	<&clkc_AO CLKID_AO_SAR_ADC_CLK>,
	<&clkc_AO CLKID_AO_SAR_ADC_SEL>;
	clock-names = "clkin", "core", "adc_clk", "adc_sel";
	status = "disabled";
	};
	};

	vdec: video-decoder@ff620000 {
	compatible = "amlogic,g12a-vdec";
	reg = <0x0 0xff620000 0x0 0x10000>,
	<0x0 0xffd0e180 0x0 0xe4>;
	reg-names = "dos", "esparser";
	interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "vdec", "esparser";

	amlogic,ao-sysctrl = <&rti>;
	amlogic,canvas = <&canvas>;

	clocks = <&clkc CLKID_PARSER>,
	<&clkc CLKID_DOS>,
	<&clkc CLKID_VDEC_1>,
	<&clkc CLKID_VDEC_HEVC>,
	<&clkc CLKID_VDEC_HEVCF>;
	clock-names = "dos_parser", "dos", "vdec_1",
	"vdec_hevc", "vdec_hevcf";
	resets = <&reset RESET_PARSER>;
	reset-names = "esparser";
	};

	vpu: vpu@ff900000 {
	compatible = "amlogic,meson-g12a-vpu";
	reg = <0x0 0xff900000 0x0 0x100000>,
	<0x0 0xff63c000 0x0 0x1000>;
	reg-names = "vpu", "hhi";
	interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
	#address-cells = <1>;
	#size-cells = <0>;
	amlogic,canvas = <&canvas>;

	/* CVBS VDAC output port */
	cvbs_vdac_port: port@0 {
	reg = <0>;
	};

	/* HDMI-TX output port */
	hdmi_tx_port: port@1 {
	reg = <1>;

	hdmi_tx_out: endpoint {
	remote-endpoint = <&hdmi_tx_in>;
	};
	};
	};

	gic: interrupt-controller@ffc01000 {
	compatible = "arm,gic-400";
	reg = <0x0 0xffc01000 0 0x1000>,
	<0x0 0xffc02000 0 0x2000>,
	<0x0 0xffc04000 0 0x2000>,
	<0x0 0xffc06000 0 0x2000>;
	interrupt-controller;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>;
	#interrupt-cells = <3>;
	#address-cells = <0>;
	};

	cbus: bus@ffd00000 {
	compatible = "simple-bus";
	reg = <0x0 0xffd00000 0x0 0x100000>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;

	reset: reset-controller@1004 {
	compatible = "amlogic,meson-axg-reset";
	reg = <0x0 0x1004 0x0 0x9c>;
	#reset-cells = <1>;
	};

	gpio_intc: interrupt-controller@f080 {
	compatible = "amlogic,meson-g12a-gpio-intc",
	"amlogic,meson-gpio-intc";
	reg = <0x0 0xf080 0x0 0x10>;
	interrupt-controller;
	#interrupt-cells = <2>;
	amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
	};

	+ spicc0: spi@13000 {
	+ compatible = "amlogic,meson-g12a-spicc";
	+ reg = <0x0 0x13000 0x0 0x44>;
	+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clkc CLKID_SPICC0>,
	+ <&clkc CLKID_SPICC0_SCLK>;
	+ clock-names = "core", "pclk";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ status = "disabled";
	+ };
	+
	+ spicc1: spi@15000 {
	+ compatible = "amlogic,meson-g12a-spicc";
	+ reg = <0x0 0x15000 0x0 0x44>;
	+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clkc CLKID_SPICC1>,
	+ <&clkc CLKID_SPICC1_SCLK>;
	+ clock-names = "core", "pclk";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ status = "disabled";
	+ };
	+
	+ spifc: spi@14000 {
	+ compatible = "amlogic,meson-gxbb-spifc";
	+ status = "disabled";
	+ reg = <0x0 0x14000 0x0 0x80>;
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ clocks = <&clkc CLKID_CLK81>;
	+ };
	+
	pwm_ef: pwm@19000 {
	compatible = "amlogic,meson-g12a-ee-pwm";
	reg = <0x0 0x19000 0x0 0x20>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm_cd: pwm@1a000 {
	compatible = "amlogic,meson-g12a-ee-pwm";
	reg = <0x0 0x1a000 0x0 0x20>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm_ab: pwm@1b000 {
	compatible = "amlogic,meson-g12a-ee-pwm";
	reg = <0x0 0x1b000 0x0 0x20>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	i2c3: i2c@1c000 {
	compatible = "amlogic,meson-axg-i2c";
	status = "disabled";
	reg = <0x0 0x1c000 0x0 0x20>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&clkc CLKID_I2C>;
	};

	i2c2: i2c@1d000 {
	compatible = "amlogic,meson-axg-i2c";
	status = "disabled";
	reg = <0x0 0x1d000 0x0 0x20>;
	interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&clkc CLKID_I2C>;
	};

	i2c1: i2c@1e000 {
	compatible = "amlogic,meson-axg-i2c";
	status = "disabled";
	reg = <0x0 0x1e000 0x0 0x20>;
	interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&clkc CLKID_I2C>;
	};

	i2c0: i2c@1f000 {
	compatible = "amlogic,meson-axg-i2c";
	status = "disabled";
	reg = <0x0 0x1f000 0x0 0x20>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&clkc CLKID_I2C>;
	};

	clk_msr: clock-measure@18000 {
	compatible = "amlogic,meson-g12a-clk-measure";
	reg = <0x0 0x18000 0x0 0x10>;
	};

	uart_C: serial@22000 {
	compatible = "amlogic,meson-gx-uart";
	reg = <0x0 0x22000 0x0 0x18>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
	status = "disabled";
	};

	uart_B: serial@23000 {
	compatible = "amlogic,meson-gx-uart";
	reg = <0x0 0x23000 0x0 0x18>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
	status = "disabled";
	};

	uart_A: serial@24000 {
	compatible = "amlogic,meson-gx-uart";
	reg = <0x0 0x24000 0x0 0x18>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
	status = "disabled";
	};
	};

	sd_emmc_a: sd@ffe03000 {
	compatible = "amlogic,meson-axg-mmc";
	reg = <0x0 0xffe03000 0x0 0x800>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
	status = "disabled";
	clocks = <&clkc CLKID_SD_EMMC_A>,
	<&clkc CLKID_SD_EMMC_A_CLK0>,
	<&clkc CLKID_FCLK_DIV2>;
	clock-names = "core", "clkin0", "clkin1";
	resets = <&reset RESET_SD_EMMC_A>;
	};

	sd_emmc_b: sd@ffe05000 {
	compatible = "amlogic,meson-axg-mmc";
	reg = <0x0 0xffe05000 0x0 0x800>;
	interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
	status = "disabled";
	clocks = <&clkc CLKID_SD_EMMC_B>,
	<&clkc CLKID_SD_EMMC_B_CLK0>,
	<&clkc CLKID_FCLK_DIV2>;
	clock-names = "core", "clkin0", "clkin1";
	resets = <&reset RESET_SD_EMMC_B>;
	};

	sd_emmc_c: mmc@ffe07000 {
	compatible = "amlogic,meson-axg-mmc";
	reg = <0x0 0xffe07000 0x0 0x800>;
	interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
	status = "disabled";
	clocks = <&clkc CLKID_SD_EMMC_C>,
	<&clkc CLKID_SD_EMMC_C_CLK0>,
	<&clkc CLKID_FCLK_DIV2>;
	clock-names = "core", "clkin0", "clkin1";
	resets = <&reset RESET_SD_EMMC_C>;
	};

	usb: usb@ffe09000 {
	status = "disabled";
	compatible = "amlogic,meson-g12a-usb-ctrl";
	reg = <0x0 0xffe09000 0x0 0xa0>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	clocks = <&clkc CLKID_USB>;
	resets = <&reset RESET_USB>;

	dr_mode = "otg";

	phys = <&usb2_phy0>, <&usb2_phy1>,
	<&usb3_pcie_phy PHY_TYPE_USB3>;
	phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";

	dwc2: usb@ff400000 {
	compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
	reg = <0x0 0xff400000 0x0 0x40000>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
	- clock-names = "ddr";
	+ clock-names = "otg";
	phys = <&usb2_phy1>;
	phy-names = "usb2-phy";
	dr_mode = "peripheral";
	g-rx-fifo-size = <192>;
	g-np-tx-fifo-size = <128>;
	g-tx-fifo-size = <128 128 16 16 16>;
	};

	dwc3: usb@ff500000 {
	compatible = "snps,dwc3";
	reg = <0x0 0xff500000 0x0 0x100000>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	dr_mode = "host";
	snps,dis_u2_susphy_quirk;
	snps,quirk-frame-length-adjustment;
	+ snps,parkmode-disable-ss-quirk;
	};
	};

	mali: gpu@ffe40000 {
	compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
	reg = <0x0 0xffe40000 0x0 0x40000>;
	interrupt-parent = <&gic>;
	interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "job", "mmu", "gpu";
	clocks = <&clkc CLKID_MALI>;
	resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;

	/*
	* Mali clocking is provided by two identical clock paths
	* MALI_0 and MALI_1 muxed to a single clock by a glitch
	* free mux to safely change frequency while running.
	*/
	assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
	<&clkc CLKID_MALI_0>,
	<&clkc CLKID_MALI>; /* Glitch free mux */
	assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
	<0>, /* Do Nothing */
	<&clkc CLKID_MALI_0>;
	assigned-clock-rates = <0>, /* Do Nothing */
	<800000000>,
	<0>; /* Do Nothing */
	#cooling-cells = <2>;
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13
	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14
	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11
	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10
	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>;
	arm,no-tick-in-suspend;
	};

	xtal: xtal-clk {
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-output-names = "xtal";
	#clock-cells = <0>;
	};

	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12.dtsi b/sys/gnu/dts/arm64/amlogic/meson-g12.dtsi
	index 03054c478896..55d39020ec72 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-g12.dtsi
	+++ b/sys/gnu/dts/arm64/amlogic/meson-g12.dtsi
	@@ -1,398 +1,399 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2019 BayLibre, SAS
	* Author: Jerome Brunet <jbrunet@baylibre.com>
	*/

	#include "meson-g12-common.dtsi"
	#include <dt-bindings/clock/axg-audio-clkc.h>
	#include <dt-bindings/power/meson-g12a-power.h>
	#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
	#include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>

	/ {
	tdmif_a: audio-controller-0 {
	compatible = "amlogic,axg-tdm-iface";
	#sound-dai-cells = <0>;
	sound-name-prefix = "TDM_A";
	clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
	<&clkc_audio AUD_CLKID_MST_A_SCLK>,
	<&clkc_audio AUD_CLKID_MST_A_LRCLK>;
	clock-names = "mclk", "sclk", "lrclk";
	status = "disabled";
	};

	tdmif_b: audio-controller-1 {
	compatible = "amlogic,axg-tdm-iface";
	#sound-dai-cells = <0>;
	sound-name-prefix = "TDM_B";
	clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
	<&clkc_audio AUD_CLKID_MST_B_SCLK>,
	<&clkc_audio AUD_CLKID_MST_B_LRCLK>;
	clock-names = "mclk", "sclk", "lrclk";
	status = "disabled";
	};

	tdmif_c: audio-controller-2 {
	compatible = "amlogic,axg-tdm-iface";
	#sound-dai-cells = <0>;
	sound-name-prefix = "TDM_C";
	clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
	<&clkc_audio AUD_CLKID_MST_C_SCLK>,
	<&clkc_audio AUD_CLKID_MST_C_LRCLK>;
	clock-names = "mclk", "sclk", "lrclk";
	status = "disabled";
	};
	};

	&apb {
	pdm: audio-controller@40000 {
	compatible = "amlogic,g12a-pdm",
	"amlogic,axg-pdm";
	reg = <0x0 0x40000 0x0 0x34>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "PDM";
	clocks = <&clkc_audio AUD_CLKID_PDM>,
	<&clkc_audio AUD_CLKID_PDM_DCLK>,
	<&clkc_audio AUD_CLKID_PDM_SYSCLK>;
	clock-names = "pclk", "dclk", "sysclk";
	+ resets = <&clkc_audio AUD_RESET_PDM>;
	status = "disabled";
	};

	audio: bus@42000 {
	compatible = "simple-bus";
	reg = <0x0 0x42000 0x0 0x2000>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>;

	clkc_audio: clock-controller@0 {
	status = "disabled";
	compatible = "amlogic,g12a-audio-clkc";
	reg = <0x0 0x0 0x0 0xb4>;
	#clock-cells = <1>;
	#reset-cells = <1>;

	clocks = <&clkc CLKID_AUDIO>,
	<&clkc CLKID_MPLL0>,
	<&clkc CLKID_MPLL1>,
	<&clkc CLKID_MPLL2>,
	<&clkc CLKID_MPLL3>,
	<&clkc CLKID_HIFI_PLL>,
	<&clkc CLKID_FCLK_DIV3>,
	<&clkc CLKID_FCLK_DIV4>,
	<&clkc CLKID_GP0_PLL>;
	clock-names = "pclk",
	"mst_in0",
	"mst_in1",
	"mst_in2",
	"mst_in3",
	"mst_in4",
	"mst_in5",
	"mst_in6",
	"mst_in7";

	resets = <&reset RESET_AUDIO>;
	};

	toddr_a: audio-controller@100 {
	compatible = "amlogic,g12a-toddr",
	"amlogic,axg-toddr";
	reg = <0x0 0x100 0x0 0x2c>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "TODDR_A";
	interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
	resets = <&arb AXG_ARB_TODDR_A>,
	<&clkc_audio AUD_RESET_TODDR_A>;
	reset-names = "arb", "rst";
	amlogic,fifo-depth = <512>;
	status = "disabled";
	};

	toddr_b: audio-controller@140 {
	compatible = "amlogic,g12a-toddr",
	"amlogic,axg-toddr";
	reg = <0x0 0x140 0x0 0x2c>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "TODDR_B";
	interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
	resets = <&arb AXG_ARB_TODDR_B>,
	<&clkc_audio AUD_RESET_TODDR_B>;
	reset-names = "arb", "rst";
	amlogic,fifo-depth = <256>;
	status = "disabled";
	};

	toddr_c: audio-controller@180 {
	compatible = "amlogic,g12a-toddr",
	"amlogic,axg-toddr";
	reg = <0x0 0x180 0x0 0x2c>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "TODDR_C";
	interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
	resets = <&arb AXG_ARB_TODDR_C>,
	<&clkc_audio AUD_RESET_TODDR_C>;
	reset-names = "arb", "rst";
	amlogic,fifo-depth = <256>;
	status = "disabled";
	};

	frddr_a: audio-controller@1c0 {
	compatible = "amlogic,g12a-frddr",
	"amlogic,axg-frddr";
	reg = <0x0 0x1c0 0x0 0x2c>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "FRDDR_A";
	interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
	resets = <&arb AXG_ARB_FRDDR_A>,
	<&clkc_audio AUD_RESET_FRDDR_A>;
	reset-names = "arb", "rst";
	amlogic,fifo-depth = <512>;
	status = "disabled";
	};

	frddr_b: audio-controller@200 {
	compatible = "amlogic,g12a-frddr",
	"amlogic,axg-frddr";
	reg = <0x0 0x200 0x0 0x2c>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "FRDDR_B";
	interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
	resets = <&arb AXG_ARB_FRDDR_B>,
	<&clkc_audio AUD_RESET_FRDDR_B>;
	reset-names = "arb", "rst";
	amlogic,fifo-depth = <256>;
	status = "disabled";
	};

	frddr_c: audio-controller@240 {
	compatible = "amlogic,g12a-frddr",
	"amlogic,axg-frddr";
	reg = <0x0 0x240 0x0 0x2c>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "FRDDR_C";
	interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
	resets = <&arb AXG_ARB_FRDDR_C>,
	<&clkc_audio AUD_RESET_FRDDR_C>;
	reset-names = "arb", "rst";
	amlogic,fifo-depth = <256>;
	status = "disabled";
	};

	arb: reset-controller@280 {
	status = "disabled";
	compatible = "amlogic,meson-axg-audio-arb";
	reg = <0x0 0x280 0x0 0x4>;
	#reset-cells = <1>;
	clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
	};

	tdmin_a: audio-controller@300 {
	compatible = "amlogic,g12a-tdmin",
	"amlogic,axg-tdmin";
	reg = <0x0 0x300 0x0 0x40>;
	sound-name-prefix = "TDMIN_A";
	resets = <&clkc_audio AUD_RESET_TDMIN_A>;
	clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
	<&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
	<&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
	<&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
	<&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
	clock-names = "pclk", "sclk", "sclk_sel",
	"lrclk", "lrclk_sel";
	status = "disabled";
	};

	tdmin_b: audio-controller@340 {
	compatible = "amlogic,g12a-tdmin",
	"amlogic,axg-tdmin";
	reg = <0x0 0x340 0x0 0x40>;
	sound-name-prefix = "TDMIN_B";
	resets = <&clkc_audio AUD_RESET_TDMIN_B>;
	clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
	<&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
	<&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
	<&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
	<&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
	clock-names = "pclk", "sclk", "sclk_sel",
	"lrclk", "lrclk_sel";
	status = "disabled";
	};

	tdmin_c: audio-controller@380 {
	compatible = "amlogic,g12a-tdmin",
	"amlogic,axg-tdmin";
	reg = <0x0 0x380 0x0 0x40>;
	sound-name-prefix = "TDMIN_C";
	resets = <&clkc_audio AUD_RESET_TDMIN_C>;
	clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
	<&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
	<&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
	<&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
	<&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
	clock-names = "pclk", "sclk", "sclk_sel",
	"lrclk", "lrclk_sel";
	status = "disabled";
	};

	tdmin_lb: audio-controller@3c0 {
	compatible = "amlogic,g12a-tdmin",
	"amlogic,axg-tdmin";
	reg = <0x0 0x3c0 0x0 0x40>;
	sound-name-prefix = "TDMIN_LB";
	resets = <&clkc_audio AUD_RESET_TDMIN_LB>;
	clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
	<&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
	<&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
	<&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
	<&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
	clock-names = "pclk", "sclk", "sclk_sel",
	"lrclk", "lrclk_sel";
	status = "disabled";
	};

	spdifin: audio-controller@400 {
	compatible = "amlogic,g12a-spdifin",
	"amlogic,axg-spdifin";
	reg = <0x0 0x400 0x0 0x30>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "SPDIFIN";
	interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
	<&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
	clock-names = "pclk", "refclk";
	resets = <&clkc_audio AUD_RESET_SPDIFIN>;
	status = "disabled";
	};

	spdifout: audio-controller@480 {
	compatible = "amlogic,g12a-spdifout",
	"amlogic,axg-spdifout";
	reg = <0x0 0x480 0x0 0x50>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "SPDIFOUT";
	clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
	<&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
	clock-names = "pclk", "mclk";
	resets = <&clkc_audio AUD_RESET_SPDIFOUT>;
	status = "disabled";
	};

	tdmout_a: audio-controller@500 {
	compatible = "amlogic,g12a-tdmout";
	reg = <0x0 0x500 0x0 0x40>;
	sound-name-prefix = "TDMOUT_A";
	resets = <&clkc_audio AUD_RESET_TDMOUT_A>;
	clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
	<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
	<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
	<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
	<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
	clock-names = "pclk", "sclk", "sclk_sel",
	"lrclk", "lrclk_sel";
	status = "disabled";
	};

	tdmout_b: audio-controller@540 {
	compatible = "amlogic,g12a-tdmout";
	reg = <0x0 0x540 0x0 0x40>;
	sound-name-prefix = "TDMOUT_B";
	resets = <&clkc_audio AUD_RESET_TDMOUT_B>;
	clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
	<&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
	<&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
	<&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
	<&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
	clock-names = "pclk", "sclk", "sclk_sel",
	"lrclk", "lrclk_sel";
	status = "disabled";
	};

	tdmout_c: audio-controller@580 {
	compatible = "amlogic,g12a-tdmout";
	reg = <0x0 0x580 0x0 0x40>;
	sound-name-prefix = "TDMOUT_C";
	resets = <&clkc_audio AUD_RESET_TDMOUT_C>;
	clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
	<&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
	<&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
	<&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
	<&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
	clock-names = "pclk", "sclk", "sclk_sel",
	"lrclk", "lrclk_sel";
	status = "disabled";
	};

	spdifout_b: audio-controller@680 {
	compatible = "amlogic,g12a-spdifout",
	"amlogic,axg-spdifout";
	reg = <0x0 0x680 0x0 0x50>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "SPDIFOUT_B";
	clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>,
	<&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>;
	clock-names = "pclk", "mclk";
	resets = <&clkc_audio AUD_RESET_SPDIFOUT_B>;
	status = "disabled";
	};

	tohdmitx: audio-controller@744 {
	compatible = "amlogic,g12a-tohdmitx";
	reg = <0x0 0x744 0x0 0x4>;
	#sound-dai-cells = <1>;
	sound-name-prefix = "TOHDMITX";
	resets = <&clkc_audio AUD_RESET_TOHDMITX>;
	status = "disabled";
	};
	};
	};

	&cpu_thermal {
	cooling-maps {
	map0 {
	trip = <&cpu_passive>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu_hot>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	&ethmac {
	power-domains = <&pwrc PWRC_G12A_ETH_ID>;
	};

	&vpu {
	power-domains = <&pwrc PWRC_G12A_VPU_ID>;
	};

	&sd_emmc_a {
	amlogic,dram-access-quirk;
	};

	&simplefb_cvbs {
	power-domains = <&pwrc PWRC_G12A_VPU_ID>;
	};

	&simplefb_hdmi {
	power-domains = <&pwrc PWRC_G12A_VPU_ID>;
	};

	diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12a-sei510.dts b/sys/gnu/dts/arm64/amlogic/meson-g12a-sei510.dts
	index 2ac9e3a43b96..b00d0468c753 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-g12a-sei510.dts
	+++ b/sys/gnu/dts/arm64/amlogic/meson-g12a-sei510.dts
	@@ -1,566 +1,566 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2019 BayLibre SAS. All rights reserved.
	*/

	/dts-v1/;

	#include "meson-g12a.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/gpio/meson-g12a-gpio.h>
	#include <dt-bindings/sound/meson-g12a-tohdmitx.h>

	/ {
	compatible = "seirobotics,sei510", "amlogic,g12a";
	model = "SEI Robotics SEI510";

	adc_keys {
	compatible = "adc-keys";
	io-channels = <&saradc 0>;
	io-channel-names = "buttons";
	keyup-threshold-microvolt = <1800000>;

	button-onoff {
	label = "On/Off";
	linux,code = <KEY_POWER>;
	press-threshold-microvolt = <1700000>;
	};
	};

	aliases {
	serial0 = &uart_AO;
	ethernet0 = &ethmac;
	};

	mono_dac: audio-codec-0 {
	compatible = "maxim,max98357a";
	#sound-dai-cells = <0>;
	sound-name-prefix = "U16";
	sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>;
	};

	dmics: audio-codec-1 {
	#sound-dai-cells = <0>;
	compatible = "dmic-codec";
	num-channels = <2>;
	wakeup-delay-ms = <50>;
	status = "okay";
	sound-name-prefix = "MIC";
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	cvbs-connector {
	compatible = "composite-video-connector";

	port {
	cvbs_connector_in: endpoint {
	remote-endpoint = <&cvbs_vdac_out>;
	};
	};
	};

	emmc_pwrseq: emmc-pwrseq {
	compatible = "mmc-pwrseq-emmc";
	reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
	};

	hdmi-connector {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_connector_in: endpoint {
	remote-endpoint = <&hdmi_tx_tmds_out>;
	};
	};
	};

	memory@0 {
	device_type = "memory";
	reg = <0x0 0x0 0x0 0x40000000>;
	};

	ao_5v: regulator-ao_5v {
	compatible = "regulator-fixed";
	regulator-name = "AO_5V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&dc_in>;
	regulator-always-on;
	};

	dc_in: regulator-dc_in {
	compatible = "regulator-fixed";
	regulator-name = "DC_IN";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	emmc_1v8: regulator-emmc_1v8 {
	compatible = "regulator-fixed";
	regulator-name = "EMMC_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vddao_3v3>;
	regulator-always-on;
	};

	vddao_3v3: regulator-vddao_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VDDAO_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&dc_in>;
	regulator-always-on;
	};

	vddao_3v3_t: regultor-vddao_3v3_t {
	compatible = "regulator-fixed";
	regulator-name = "VDDAO_3V3_T";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vddao_3v3>;
	gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
	enable-active-high;
	};

	vddcpu: regulator-vddcpu {
	/*
	* SY8120B1ABC DC/DC Regulator.
	*/
	compatible = "pwm-regulator";

	regulator-name = "VDDCPU";
	regulator-min-microvolt = <721000>;
	regulator-max-microvolt = <1022000>;

	vin-supply = <&dc_in>;

	pwms = <&pwm_AO_cd 1 1250 0>;
	pwm-dutycycle-range = <100 0>;

	regulator-boot-on;
	regulator-always-on;
	};

	vddio_ao1v8: regulator-vddio_ao1v8 {
	compatible = "regulator-fixed";
	regulator-name = "VDDIO_AO1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vddao_3v3>;
	regulator-always-on;
	};

	reserved-memory {
	/* TEE Reserved Memory */
	bl32_reserved: bl32@5000000 {
	reg = <0x0 0x05300000 0x0 0x2000000>;
	no-map;
	};
	};

	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
	clocks = <&wifi32k>;
	clock-names = "ext_clock";
	};

	wifi32k: wifi32k {
	compatible = "pwm-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
	};

	sound {
	compatible = "amlogic,axg-sound-card";
	model = "G12A-SEI510";
	audio-aux-devs = <&tdmout_a>, <&tdmout_b>,
	<&tdmin_a>, <&tdmin_b>;
	audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
	"TDMOUT_A IN 1", "FRDDR_B OUT 0",
	"TDMOUT_A IN 2", "FRDDR_C OUT 0",
	"TDM_A Playback", "TDMOUT_A OUT",
	"TDMOUT_B IN 0", "FRDDR_A OUT 1",
	"TDMOUT_B IN 1", "FRDDR_B OUT 1",
	"TDMOUT_B IN 2", "FRDDR_C OUT 1",
	"TDM_B Playback", "TDMOUT_B OUT",
	"TODDR_A IN 4", "PDM Capture",
	"TODDR_B IN 4", "PDM Capture",
	"TODDR_C IN 4", "PDM Capture",
	"TDMIN_A IN 0", "TDM_A Capture",
	"TDMIN_A IN 3", "TDM_A Loopback",
	"TDMIN_B IN 0", "TDM_A Capture",
	"TDMIN_B IN 3", "TDM_A Loopback",
	"TDMIN_A IN 1", "TDM_B Capture",
	"TDMIN_A IN 4", "TDM_B Loopback",
	"TDMIN_B IN 1", "TDM_B Capture",
	"TDMIN_B IN 4", "TDM_B Loopback",
	"TODDR_A IN 0", "TDMIN_A OUT",
	"TODDR_B IN 0", "TDMIN_A OUT",
	"TODDR_C IN 0", "TDMIN_A OUT",
	"TODDR_A IN 1", "TDMIN_B OUT",
	"TODDR_B IN 1", "TDMIN_B OUT",
	"TODDR_C IN 1", "TDMIN_B OUT";

	assigned-clocks = <&clkc CLKID_MPLL2>,
	<&clkc CLKID_MPLL0>,
	<&clkc CLKID_MPLL1>;
	assigned-clock-parents = <0>, <0>, <0>;
	assigned-clock-rates = <294912000>,
	<270950400>,
	<393216000>;
	status = "okay";

	dai-link-0 {
	sound-dai = <&frddr_a>;
	};

	dai-link-1 {
	sound-dai = <&frddr_b>;
	};

	dai-link-2 {
	sound-dai = <&frddr_c>;
	};

	dai-link-3 {
	sound-dai = <&toddr_a>;
	};

	dai-link-4 {
	sound-dai = <&toddr_b>;
	};

	dai-link-5 {
	sound-dai = <&toddr_c>;
	};

	/* internal speaker interface */
	dai-link-6 {
	sound-dai = <&tdmif_a>;
	dai-format = "i2s";
	dai-tdm-slot-tx-mask-0 = <1 1>;
	mclk-fs = <256>;

	codec-0 {
	sound-dai = <&mono_dac>;
	};

	codec-1 {
	sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
	};
	};

	/* 8ch hdmi interface */
	dai-link-7 {
	sound-dai = <&tdmif_b>;
	dai-format = "i2s";
	dai-tdm-slot-tx-mask-0 = <1 1>;
	dai-tdm-slot-tx-mask-1 = <1 1>;
	dai-tdm-slot-tx-mask-2 = <1 1>;
	dai-tdm-slot-tx-mask-3 = <1 1>;
	mclk-fs = <256>;

	- codec@0 {
	+ codec {
	sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
	};
	};

	/* internal digital mics */
	dai-link-8 {
	sound-dai = <&pdm>;

	codec {
	sound-dai = <&dmics>;
	};
	};

	/* hdmi glue */
	dai-link-9 {
	sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;

	codec {
	sound-dai = <&hdmi_tx>;
	};
	};
	};
	};

	&arb {
	status = "okay";
	};

	&cec_AO {
	pinctrl-0 = <&cec_ao_a_h_pins>;
	pinctrl-names = "default";
	status = "disabled";
	hdmi-phandle = <&hdmi_tx>;
	};

	&cecb_AO {
	pinctrl-0 = <&cec_ao_b_h_pins>;
	pinctrl-names = "default";
	status = "okay";
	hdmi-phandle = <&hdmi_tx>;
	};

	&clkc_audio {
	status = "okay";
	};

	&cpu0 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cpu1 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cpu2 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cpu3 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cvbs_vdac_port {
	cvbs_vdac_out: endpoint {
	remote-endpoint = <&cvbs_connector_in>;
	};
	};

	&ethmac {
	status = "okay";
	phy-handle = <&internal_ephy>;
	phy-mode = "rmii";
	};

	&frddr_a {
	status = "okay";
	};

	&frddr_b {
	status = "okay";
	};

	&frddr_c {
	status = "okay";
	};

	&hdmi_tx {
	status = "okay";
	pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
	pinctrl-names = "default";
	};

	&hdmi_tx_tmds_port {
	hdmi_tx_tmds_out: endpoint {
	remote-endpoint = <&hdmi_connector_in>;
	};
	};

	&i2c3 {
	status = "okay";
	pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
	pinctrl-names = "default";
	};

	&ir {
	status = "okay";
	pinctrl-0 = <&remote_input_ao_pins>;
	pinctrl-names = "default";
	};

	&pwm_AO_cd {
	pinctrl-0 = <&pwm_ao_d_e_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>;
	clock-names = "clkin1";
	status = "okay";
	};

	&pwm_ef {
	status = "okay";
	pinctrl-0 = <&pwm_e_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>;
	clock-names = "clkin0";
	};

	&pdm {
	pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_din1_z_pins>,
	<&pdm_din2_z_pins>, <&pdm_din3_z_pins>,
	<&pdm_dclk_z_pins>;
	pinctrl-names = "default";
	status = "okay";
	};

	&saradc {
	status = "okay";
	vref-supply = <&vddio_ao1v8>;
	};

	/* SDIO */
	&sd_emmc_a {
	status = "okay";
	pinctrl-0 = <&sdio_pins>;
	pinctrl-1 = <&sdio_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";
	#address-cells = <1>;
	#size-cells = <0>;

	bus-width = <4>;
	cap-sd-highspeed;
	sd-uhs-sdr50;
	max-frequency = <100000000>;

	non-removable;
	disable-wp;

	/* WiFi firmware requires power to be kept while in suspend */
	keep-power-in-suspend;

	mmc-pwrseq = <&sdio_pwrseq>;

	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vddio_ao1v8>;

	brcmf: wifi@1 {
	reg = <1>;
	compatible = "brcm,bcm4329-fmac";
	};
	};

	/* SD card */
	&sd_emmc_b {
	status = "okay";
	pinctrl-0 = <&sdcard_c_pins>;
	pinctrl-1 = <&sdcard_clk_gate_c_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <4>;
	cap-sd-highspeed;
	max-frequency = <50000000>;
	disable-wp;

	cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vddao_3v3>;
	};

	/* eMMC */
	&sd_emmc_c {
	status = "okay";
	- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
	+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
	pinctrl-1 = <&emmc_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <8>;
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	max-frequency = <200000000>;
	non-removable;
	disable-wp;

	mmc-pwrseq = <&emmc_pwrseq>;
	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&emmc_1v8>;
	};

	&tdmif_a {
	pinctrl-0 = <&tdm_a_dout0_pins>, <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>;
	pinctrl-names = "default";
	status = "okay";

	assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD0>,
	<&clkc_audio AUD_CLKID_TDM_LRCLK_PAD0>;
	assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_A_SCLK>,
	<&clkc_audio AUD_CLKID_MST_A_LRCLK>;
	assigned-clock-rates = <0>, <0>;
	};

	&tdmif_b {
	status = "okay";
	};

	&tdmin_a {
	status = "okay";
	};

	&tdmin_b {
	status = "okay";
	};

	&tdmout_a {
	status = "okay";
	};

	&tdmout_b {
	status = "okay";
	};

	&toddr_a {
	status = "okay";
	};

	&toddr_b {
	status = "okay";
	};

	&toddr_c {
	status = "okay";
	};

	&tohdmitx {
	status = "okay";
	};

	&uart_A {
	status = "okay";
	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
	pinctrl-names = "default";
	uart-has-rtscts;

	bluetooth {
	compatible = "brcm,bcm43438-bt";
	shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
	max-speed = <2000000>;
	clocks = <&wifi32k>;
	clock-names = "lpo";
	vbat-supply = <&vddao_3v3>;
	vddio-supply = <&vddio_ao1v8>;
	};
	};

	&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
	};

	&usb {
	status = "okay";
	dr_mode = "host";
	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12a-u200.dts b/sys/gnu/dts/arm64/amlogic/meson-g12a-u200.dts
	index 2a324f0136e3..a26bfe72550f 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-g12a-u200.dts
	+++ b/sys/gnu/dts/arm64/amlogic/meson-g12a-u200.dts
	@@ -1,308 +1,308 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
	*/

	/dts-v1/;

	#include "meson-g12a.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/gpio/meson-g12a-gpio.h>

	/ {
	compatible = "amlogic,u200", "amlogic,g12a";
	model = "Amlogic Meson G12A U200 Development Board";

	aliases {
	serial0 = &uart_AO;
	ethernet0 = &ethmac;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	cvbs-connector {
	compatible = "composite-video-connector";

	port {
	cvbs_connector_in: endpoint {
	remote-endpoint = <&cvbs_vdac_out>;
	};
	};
	};

	emmc_pwrseq: emmc-pwrseq {
	compatible = "mmc-pwrseq-emmc";
	reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
	};

	hdmi-connector {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_connector_in: endpoint {
	remote-endpoint = <&hdmi_tx_tmds_out>;
	};
	};
	};

	memory@0 {
	device_type = "memory";
	reg = <0x0 0x0 0x0 0x40000000>;
	};

	flash_1v8: regulator-flash_1v8 {
	compatible = "regulator-fixed";
	regulator-name = "FLASH_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vcc_3v3>;
	regulator-always-on;
	};

	main_12v: regulator-main_12v {
	compatible = "regulator-fixed";
	regulator-name = "12V";
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	regulator-always-on;
	};

	usb_pwr_en: regulator-usb_pwr_en {
	compatible = "regulator-fixed";
	regulator-name = "USB_PWR_EN";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&vcc_5v>;

	gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vcc_1v8: regulator-vcc_1v8 {
	compatible = "regulator-fixed";
	regulator-name = "VCC_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vcc_3v3>;
	regulator-always-on;
	};

	vcc_3v3: regulator-vcc_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VCC_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vddao_3v3>;
	regulator-always-on;
	/* FIXME: actually controlled by VDDCPU_B_EN */
	};

	vcc_5v: regulator-vcc_5v {
	compatible = "regulator-fixed";
	regulator-name = "VCC_5V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&main_12v>;

	gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
	enable-active-high;
	};

	vddao_1v8: regulator-vddao_1v8 {
	compatible = "regulator-fixed";
	regulator-name = "VDDAO_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vddao_3v3>;
	regulator-always-on;
	};

	vddao_3v3: regulator-vddao_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VDDAO_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&main_12v>;
	regulator-always-on;
	};

	vddcpu: regulator-vddcpu {
	/*
	* MP8756GD Regulator.
	*/
	compatible = "pwm-regulator";

	regulator-name = "VDDCPU";
	regulator-min-microvolt = <721000>;
	regulator-max-microvolt = <1022000>;

	vin-supply = <&main_12v>;

	pwms = <&pwm_AO_cd 1 1250 0>;
	pwm-dutycycle-range = <100 0>;

	regulator-boot-on;
	regulator-always-on;
	};
	};

	&cec_AO {
	pinctrl-0 = <&cec_ao_a_h_pins>;
	pinctrl-names = "default";
	status = "disabled";
	hdmi-phandle = <&hdmi_tx>;
	};

	&cecb_AO {
	pinctrl-0 = <&cec_ao_b_h_pins>;
	pinctrl-names = "default";
	status = "okay";
	hdmi-phandle = <&hdmi_tx>;
	};

	&cpu0 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cpu1 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cpu2 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cpu3 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cvbs_vdac_port {
	cvbs_vdac_out: endpoint {
	remote-endpoint = <&cvbs_connector_in>;
	};
	};

	&ethmac {
	status = "okay";
	phy-handle = <&internal_ephy>;
	phy-mode = "rmii";
	};

	&hdmi_tx {
	status = "okay";
	pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
	pinctrl-names = "default";
	hdmi-supply = <&vcc_5v>;
	};

	&hdmi_tx_tmds_port {
	hdmi_tx_tmds_out: endpoint {
	remote-endpoint = <&hdmi_connector_in>;
	};
	};

	&ir {
	status = "okay";
	pinctrl-0 = <&remote_input_ao_pins>;
	pinctrl-names = "default";
	};

	/* i2c Touch */
	&i2c0 {
	status = "okay";
	pinctrl-0 = <&i2c0_sda_z0_pins>, <&i2c0_sck_z1_pins>;
	pinctrl-names = "default";
	};

	/* i2c CM */
	&i2c2 {
	status = "okay";
	pinctrl-0 = <&i2c2_sda_z_pins>, <&i2c2_sck_z_pins>;
	pinctrl-names = "default";
	};

	/* i2c Audio */
	&i2c3 {
	status = "okay";
	pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
	pinctrl-names = "default";
	};

	&pwm_AO_cd {
	pinctrl-0 = <&pwm_ao_d_e_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>;
	clock-names = "clkin1";
	status = "okay";
	};

	/* SD card */
	&sd_emmc_b {
	status = "okay";
	pinctrl-0 = <&sdcard_c_pins>;
	pinctrl-1 = <&sdcard_clk_gate_c_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <4>;
	cap-sd-highspeed;
	max-frequency = <50000000>;
	disable-wp;

	cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vddao_3v3>;
	};

	/* eMMC */
	&sd_emmc_c {
	status = "okay";
	- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
	+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
	pinctrl-1 = <&emmc_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <8>;
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	max-frequency = <200000000>;
	non-removable;
	disable-wp;

	mmc-pwrseq = <&emmc_pwrseq>;
	vmmc-supply = <&vcc_3v3>;
	vqmmc-supply = <&flash_1v8>;
	};

	&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
	};

	&usb {
	status = "okay";
	vbus-supply = <&usb_pwr_en>;
	};

	&usb2_phy0 {
	phy-supply = <&vcc_5v>;
	};

	&usb2_phy1 {
	phy-supply = <&vcc_5v>;
	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12a-x96-max.dts b/sys/gnu/dts/arm64/amlogic/meson-g12a-x96-max.dts
	index 4f2596d82989..1b07c8c06eac 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-g12a-x96-max.dts
	+++ b/sys/gnu/dts/arm64/amlogic/meson-g12a-x96-max.dts
	@@ -1,481 +1,481 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2018 BayLibre SAS. All rights reserved.
	*/

	/dts-v1/;

	#include "meson-g12a.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/gpio/meson-g12a-gpio.h>
	#include <dt-bindings/sound/meson-g12a-tohdmitx.h>

	/ {
	compatible = "amediatech,x96-max", "amlogic,g12a";
	model = "Shenzhen Amediatech Technology Co., Ltd X96 Max";

	aliases {
	serial0 = &uart_AO;
	ethernet0 = &ethmac;
	};

	spdif_dit: audio-codec-1 {
	#sound-dai-cells = <0>;
	compatible = "linux,spdif-dit";
	status = "okay";
	sound-name-prefix = "DIT";
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};
	memory@0 {
	device_type = "memory";
	reg = <0x0 0x0 0x0 0x40000000>;
	};

	cvbs-connector {
	compatible = "composite-video-connector";

	port {
	cvbs_connector_in: endpoint {
	remote-endpoint = <&cvbs_vdac_out>;
	};
	};
	};

	hdmi-connector {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_connector_in: endpoint {
	remote-endpoint = <&hdmi_tx_tmds_out>;
	};
	};
	};

	emmc_pwrseq: emmc-pwrseq {
	compatible = "mmc-pwrseq-emmc";
	reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
	};

	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
	clocks = <&wifi32k>;
	clock-names = "ext_clock";
	};

	flash_1v8: regulator-flash_1v8 {
	compatible = "regulator-fixed";
	regulator-name = "FLASH_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vcc_3v3>;
	regulator-always-on;
	};

	dc_in: regulator-dc_in {
	compatible = "regulator-fixed";
	regulator-name = "DC_IN";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	vcc_1v8: regulator-vcc_1v8 {
	compatible = "regulator-fixed";
	regulator-name = "VCC_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vcc_3v3>;
	regulator-always-on;
	};

	vcc_3v3: regulator-vcc_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VCC_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vddao_3v3>;
	regulator-always-on;
	/* FIXME: actually controlled by VDDCPU_B_EN */
	};

	vcc_5v: regulator-vcc_5v {
	compatible = "regulator-fixed";
	regulator-name = "VCC_5V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&dc_in>;

	gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
	enable-active-low;
	};

	vddao_1v8: regulator-vddao_1v8 {
	compatible = "regulator-fixed";
	regulator-name = "VDDAO_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vddao_3v3>;
	regulator-always-on;
	};

	vddao_3v3: regulator-vddao_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VDDAO_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&dc_in>;
	regulator-always-on;
	};

	vddcpu: regulator-vddcpu {
	compatible = "pwm-regulator";

	regulator-name = "VDDCPU";
	regulator-min-microvolt = <721000>;
	regulator-max-microvolt = <1022000>;

	vin-supply = <&dc_in>;

	pwms = <&pwm_AO_cd 1 1250 0>;
	pwm-dutycycle-range = <100 0>;

	regulator-boot-on;
	regulator-always-on;
	};

	sound {
	compatible = "amlogic,axg-sound-card";
	model = "G12A-X96-MAX";
	audio-aux-devs = <&tdmout_b>;
	audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
	"TDMOUT_B IN 1", "FRDDR_B OUT 1",
	"TDMOUT_B IN 2", "FRDDR_C OUT 1",
	"TDM_B Playback", "TDMOUT_B OUT",
	"SPDIFOUT IN 0", "FRDDR_A OUT 3",
	"SPDIFOUT IN 1", "FRDDR_B OUT 3",
	"SPDIFOUT IN 2", "FRDDR_C OUT 3";

	assigned-clocks = <&clkc CLKID_MPLL2>,
	<&clkc CLKID_MPLL0>,
	<&clkc CLKID_MPLL1>;
	assigned-clock-parents = <0>, <0>, <0>;
	assigned-clock-rates = <294912000>,
	<270950400>,
	<393216000>;
	status = "okay";

	dai-link-0 {
	sound-dai = <&frddr_a>;
	};

	dai-link-1 {
	sound-dai = <&frddr_b>;
	};

	dai-link-2 {
	sound-dai = <&frddr_c>;
	};

	/* 8ch hdmi interface */
	dai-link-3 {
	sound-dai = <&tdmif_b>;
	dai-format = "i2s";
	dai-tdm-slot-tx-mask-0 = <1 1>;
	dai-tdm-slot-tx-mask-1 = <1 1>;
	dai-tdm-slot-tx-mask-2 = <1 1>;
	dai-tdm-slot-tx-mask-3 = <1 1>;
	mclk-fs = <256>;

	codec {
	sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
	};
	};

	/* spdif hdmi or toslink interface */
	dai-link-4 {
	sound-dai = <&spdifout>;

	codec-0 {
	sound-dai = <&spdif_dit>;
	};

	codec-1 {
	sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>;
	};
	};

	/* spdif hdmi interface */
	dai-link-5 {
	sound-dai = <&spdifout_b>;

	codec {
	sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>;
	};
	};

	/* hdmi glue */
	dai-link-6 {
	sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;

	codec {
	sound-dai = <&hdmi_tx>;
	};
	};
	};

	wifi32k: wifi32k {
	compatible = "pwm-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
	};
	};

	&arb {
	status = "okay";
	};

	&cec_AO {
	pinctrl-0 = <&cec_ao_a_h_pins>;
	pinctrl-names = "default";
	status = "disabled";
	hdmi-phandle = <&hdmi_tx>;
	};

	&cecb_AO {
	pinctrl-0 = <&cec_ao_b_h_pins>;
	pinctrl-names = "default";
	status = "okay";
	hdmi-phandle = <&hdmi_tx>;
	};

	&clkc_audio {
	status = "okay";
	};

	&cpu0 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cpu1 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cpu2 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cpu3 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cvbs_vdac_port {
	cvbs_vdac_out: endpoint {
	remote-endpoint = <&cvbs_connector_in>;
	};
	};

	&frddr_a {
	status = "okay";
	};

	&frddr_b {
	status = "okay";
	};

	&frddr_c {
	status = "okay";
	};

	&hdmi_tx {
	status = "okay";
	pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
	pinctrl-names = "default";
	hdmi-supply = <&vcc_5v>;
	};

	&hdmi_tx_tmds_port {
	hdmi_tx_tmds_out: endpoint {
	remote-endpoint = <&hdmi_connector_in>;
	};
	};

	&ir {
	status = "okay";
	pinctrl-0 = <&remote_input_ao_pins>;
	pinctrl-names = "default";
	linux,rc-map-name = "rc-x96max";
	};

	&pwm_AO_cd {
	pinctrl-0 = <&pwm_ao_d_e_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>;
	clock-names = "clkin1";
	status = "okay";
	};

	&ext_mdio {
	external_phy: ethernet-phy@0 {
	/* Realtek RTL8211F (0x001cc916) */
	reg = <0>;
	max-speed = <1000>;
	eee-broken-1000t;

	reset-assert-us = <10000>;
	reset-deassert-us = <30000>;
	reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW \| GPIO_OPEN_DRAIN)>;

	interrupt-parent = <&gpio_intc>;
	/* MAC_INTR on GPIOZ_14 */
	interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
	};
	};

	&ethmac {
	pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
	pinctrl-names = "default";
	status = "okay";
	phy-mode = "rgmii";
	phy-handle = <&external_phy>;
	amlogic,tx-delay-ns = <2>;
	};

	&pwm_ef {
	status = "okay";
	pinctrl-0 = <&pwm_e_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>;
	clock-names = "clkin0";
	};

	&uart_A {
	status = "okay";
	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
	pinctrl-names = "default";
	uart-has-rtscts;

	bluetooth {
	compatible = "brcm,bcm43438-bt";
	shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
	max-speed = <2000000>;
	clocks = <&wifi32k>;
	clock-names = "lpo";
	};
	};

	&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
	};

	&usb {
	status = "okay";
	dr_mode = "host";
	};

	/* SDIO */
	&sd_emmc_a {
	status = "okay";
	pinctrl-0 = <&sdio_pins>;
	pinctrl-1 = <&sdio_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";
	#address-cells = <1>;
	#size-cells = <0>;

	bus-width = <4>;
	cap-sd-highspeed;
	sd-uhs-sdr50;
	max-frequency = <100000000>;

	non-removable;
	disable-wp;

	/* WiFi firmware requires power to be kept while in suspend */
	keep-power-in-suspend;

	mmc-pwrseq = <&sdio_pwrseq>;

	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vddao_1v8>;

	brcmf: wifi@1 {
	reg = <1>;
	compatible = "brcm,bcm4329-fmac";
	};
	};

	/* SD card */
	&sd_emmc_b {
	status = "okay";
	pinctrl-0 = <&sdcard_c_pins>;
	pinctrl-1 = <&sdcard_clk_gate_c_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <4>;
	cap-sd-highspeed;
	max-frequency = <100000000>;
	disable-wp;

	cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vddao_3v3>;
	};

	/* eMMC */
	&sd_emmc_c {
	status = "okay";
	- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
	+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
	pinctrl-1 = <&emmc_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <8>;
	cap-mmc-highspeed;
	max-frequency = <100000000>;
	non-removable;
	disable-wp;

	mmc-pwrseq = <&emmc_pwrseq>;
	vmmc-supply = <&vcc_3v3>;
	vqmmc-supply = <&flash_1v8>;
	};

	&spdifout {
	pinctrl-0 = <&spdif_out_h_pins>;
	pinctrl-names = "default";
	status = "okay";
	};

	&spdifout_b {
	status = "okay";
	};

	&tdmif_b {
	status = "okay";
	};

	&tdmout_b {
	status = "okay";
	};

	&tohdmitx {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12b-khadas-vim3.dtsi b/sys/gnu/dts/arm64/amlogic/meson-g12b-khadas-vim3.dtsi
	index 554863429aa6..c6c8caed8327 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-g12b-khadas-vim3.dtsi
	+++ b/sys/gnu/dts/arm64/amlogic/meson-g12b-khadas-vim3.dtsi
	@@ -1,189 +1,195 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2019 BayLibre, SAS
	* Author: Neil Armstrong <narmstrong@baylibre.com>
	* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
	*/

	#include <dt-bindings/sound/meson-g12a-tohdmitx.h>

	/ {
	+ model = "Khadas VIM3";
	+
	vddcpu_a: regulator-vddcpu-a {
	/*
	* MP8756GD Regulator.
	*/
	compatible = "pwm-regulator";

	regulator-name = "VDDCPU_A";
	regulator-min-microvolt = <690000>;
	regulator-max-microvolt = <1050000>;

	vin-supply = <&dc_in>;

	pwms = <&pwm_ab 0 1250 0>;
	pwm-dutycycle-range = <100 0>;

	regulator-boot-on;
	regulator-always-on;
	};

	vddcpu_b: regulator-vddcpu-b {
	/*
	* Silergy SY8030DEC Regulator.
	*/
	compatible = "pwm-regulator";

	regulator-name = "VDDCPU_B";
	regulator-min-microvolt = <690000>;
	regulator-max-microvolt = <1050000>;

	vin-supply = <&vsys_3v3>;

	pwms = <&pwm_AO_cd 1 1250 0>;
	pwm-dutycycle-range = <100 0>;

	regulator-boot-on;
	regulator-always-on;
	};

	sound {
	compatible = "amlogic,axg-sound-card";
	- model = "G12A-KHADAS-VIM3";
	+ model = "G12B-KHADAS-VIM3";
	audio-aux-devs = <&tdmout_b>;
	audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
	"TDMOUT_B IN 1", "FRDDR_B OUT 1",
	"TDMOUT_B IN 2", "FRDDR_C OUT 1",
	"TDM_B Playback", "TDMOUT_B OUT";

	assigned-clocks = <&clkc CLKID_MPLL2>,
	<&clkc CLKID_MPLL0>,
	<&clkc CLKID_MPLL1>;
	assigned-clock-parents = <0>, <0>, <0>;
	assigned-clock-rates = <294912000>,
	<270950400>,
	<393216000>;
	status = "okay";

	dai-link-0 {
	sound-dai = <&frddr_a>;
	};

	dai-link-1 {
	sound-dai = <&frddr_b>;
	};

	dai-link-2 {
	sound-dai = <&frddr_c>;
	};

	/* 8ch hdmi interface */
	dai-link-3 {
	sound-dai = <&tdmif_b>;
	dai-format = "i2s";
	dai-tdm-slot-tx-mask-0 = <1 1>;
	dai-tdm-slot-tx-mask-1 = <1 1>;
	dai-tdm-slot-tx-mask-2 = <1 1>;
	dai-tdm-slot-tx-mask-3 = <1 1>;
	mclk-fs = <256>;

	codec {
	sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
	};
	};

	/* hdmi glue */
	dai-link-4 {
	sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;

	codec {
	sound-dai = <&hdmi_tx>;
	};
	};
	};
	};

	&arb {
	status = "okay";
	};

	&clkc_audio {
	status = "okay";
	};

	&cpu0 {
	cpu-supply = <&vddcpu_b>;
	operating-points-v2 = <&cpu_opp_table_0>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cpu1 {
	cpu-supply = <&vddcpu_b>;
	operating-points-v2 = <&cpu_opp_table_0>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cpu100 {
	cpu-supply = <&vddcpu_a>;
	operating-points-v2 = <&cpub_opp_table_1>;
	clocks = <&clkc CLKID_CPUB_CLK>;
	clock-latency = <50000>;
	};

	&cpu101 {
	cpu-supply = <&vddcpu_a>;
	operating-points-v2 = <&cpub_opp_table_1>;
	clocks = <&clkc CLKID_CPUB_CLK>;
	clock-latency = <50000>;
	};

	&cpu102 {
	cpu-supply = <&vddcpu_a>;
	operating-points-v2 = <&cpub_opp_table_1>;
	clocks = <&clkc CLKID_CPUB_CLK>;
	clock-latency = <50000>;
	};

	&cpu103 {
	cpu-supply = <&vddcpu_a>;
	operating-points-v2 = <&cpub_opp_table_1>;
	clocks = <&clkc CLKID_CPUB_CLK>;
	clock-latency = <50000>;
	};

	+&frddr_a {
	+ status = "okay";
	+};
	+
	&frddr_b {
	status = "okay";
	};

	&frddr_c {
	status = "okay";
	};

	&pwm_ab {
	pinctrl-0 = <&pwm_a_e_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>;
	clock-names = "clkin0";
	status = "okay";
	};

	&pwm_AO_cd {
	pinctrl-0 = <&pwm_ao_d_e_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>;
	clock-names = "clkin1";
	status = "okay";
	};

	&tdmif_b {
	status = "okay";
	};

	&tdmout_b {
	status = "okay";
	};

	&tohdmitx {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12b-odroid-n2.dts b/sys/gnu/dts/arm64/amlogic/meson-g12b-odroid-n2.dts
	index 0e54c1dc2842..169ea283d4ee 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-g12b-odroid-n2.dts
	+++ b/sys/gnu/dts/arm64/amlogic/meson-g12b-odroid-n2.dts
	@@ -1,484 +1,505 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2019 BayLibre, SAS
	* Author: Neil Armstrong <narmstrong@baylibre.com>
	*/

	/dts-v1/;

	#include "meson-g12b-s922x.dtsi"
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/gpio/meson-g12a-gpio.h>
	#include <dt-bindings/sound/meson-g12a-tohdmitx.h>

	/ {
	compatible = "hardkernel,odroid-n2", "amlogic,s922x", "amlogic,g12b";
	model = "Hardkernel ODROID-N2";

	aliases {
	serial0 = &uart_AO;
	ethernet0 = &ethmac;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@0 {
	device_type = "memory";
	reg = <0x0 0x0 0x0 0x40000000>;
	};

	emmc_pwrseq: emmc-pwrseq {
	compatible = "mmc-pwrseq-emmc";
	reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
	};

	leds {
	compatible = "gpio-leds";

	blue {
	label = "n2:blue";
	gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	};
	};

	tflash_vdd: regulator-tflash_vdd {
	compatible = "regulator-fixed";

	regulator-name = "TFLASH_VDD";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	regulator-always-on;
	};

	tf_io: gpio-regulator-tf_io {
	compatible = "regulator-gpio";

	regulator-name = "TF_IO";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
	gpios-states = <0>;

	states = <3300000 0>,
	<1800000 1>;
	};

	flash_1v8: regulator-flash_1v8 {
	compatible = "regulator-fixed";
	regulator-name = "FLASH_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vcc_3v3>;
	regulator-always-on;
	};

	main_12v: regulator-main_12v {
	compatible = "regulator-fixed";
	regulator-name = "12V";
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	regulator-always-on;
	};

	vcc_5v: regulator-vcc_5v {
	compatible = "regulator-fixed";
	regulator-name = "5V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	vin-supply = <&main_12v>;
	};

	vcc_1v8: regulator-vcc_1v8 {
	compatible = "regulator-fixed";
	regulator-name = "VCC_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vcc_3v3>;
	regulator-always-on;
	};

	vcc_3v3: regulator-vcc_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VCC_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vddao_3v3>;
	regulator-always-on;
	/* FIXME: actually controlled by VDDCPU_B_EN */
	};

	vddcpu_a: regulator-vddcpu-a {
	/*
	* MP8756GD Regulator.
	*/
	compatible = "pwm-regulator";

	regulator-name = "VDDCPU_A";
	regulator-min-microvolt = <721000>;
	regulator-max-microvolt = <1022000>;

	vin-supply = <&main_12v>;

	pwms = <&pwm_ab 0 1250 0>;
	pwm-dutycycle-range = <100 0>;

	regulator-boot-on;
	regulator-always-on;
	};

	vddcpu_b: regulator-vddcpu-b {
	/*
	* Silergy SY8120B1ABC Regulator.
	*/
	compatible = "pwm-regulator";

	regulator-name = "VDDCPU_B";
	regulator-min-microvolt = <721000>;
	regulator-max-microvolt = <1022000>;

	vin-supply = <&main_12v>;

	pwms = <&pwm_AO_cd 1 1250 0>;
	pwm-dutycycle-range = <100 0>;

	regulator-boot-on;
	regulator-always-on;
	};

	hub_5v: regulator-hub_5v {
	compatible = "regulator-fixed";
	regulator-name = "HUB_5V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&vcc_5v>;

	/* Connected to the Hub CHIPENABLE, LOW sets low power state */
	gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	usb_pwr_en: regulator-usb_pwr_en {
	compatible = "regulator-fixed";
	regulator-name = "USB_PWR_EN";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&vcc_5v>;

	/* Connected to the microUSB port power enable */
	gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vddao_1v8: regulator-vddao_1v8 {
	compatible = "regulator-fixed";
	regulator-name = "VDDAO_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vddao_3v3>;
	regulator-always-on;
	};

	vddao_3v3: regulator-vddao_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VDDAO_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&main_12v>;
	regulator-always-on;
	};

	hdmi-connector {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_connector_in: endpoint {
	remote-endpoint = <&hdmi_tx_tmds_out>;
	};
	};
	};

	sound {
	compatible = "amlogic,axg-sound-card";
	- model = "G12A-ODROIDN2";
	+ model = "G12B-ODROID-N2";
	audio-aux-devs = <&tdmout_b>;
	audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
	"TDMOUT_B IN 1", "FRDDR_B OUT 1",
	"TDMOUT_B IN 2", "FRDDR_C OUT 1",
	"TDM_B Playback", "TDMOUT_B OUT";

	assigned-clocks = <&clkc CLKID_MPLL2>,
	<&clkc CLKID_MPLL0>,
	<&clkc CLKID_MPLL1>;
	assigned-clock-parents = <0>, <0>, <0>;
	assigned-clock-rates = <294912000>,
	<270950400>,
	<393216000>;
	status = "okay";

	dai-link-0 {
	sound-dai = <&frddr_a>;
	};

	dai-link-1 {
	sound-dai = <&frddr_b>;
	};

	dai-link-2 {
	sound-dai = <&frddr_c>;
	};

	/* 8ch hdmi interface */
	dai-link-3 {
	sound-dai = <&tdmif_b>;
	dai-format = "i2s";
	dai-tdm-slot-tx-mask-0 = <1 1>;
	dai-tdm-slot-tx-mask-1 = <1 1>;
	dai-tdm-slot-tx-mask-2 = <1 1>;
	dai-tdm-slot-tx-mask-3 = <1 1>;
	mclk-fs = <256>;

	codec {
	sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
	};
	};

	/* hdmi glue */
	dai-link-4 {
	sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;

	codec {
	sound-dai = <&hdmi_tx>;
	};
	};
	};
	};

	&arb {
	status = "okay";
	};

	&cec_AO {
	pinctrl-0 = <&cec_ao_a_h_pins>;
	pinctrl-names = "default";
	status = "disabled";
	hdmi-phandle = <&hdmi_tx>;
	};

	&cecb_AO {
	pinctrl-0 = <&cec_ao_b_h_pins>;
	pinctrl-names = "default";
	status = "okay";
	hdmi-phandle = <&hdmi_tx>;
	};

	&clkc_audio {
	status = "okay";
	};

	&cpu0 {
	cpu-supply = <&vddcpu_b>;
	operating-points-v2 = <&cpu_opp_table_0>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cpu1 {
	cpu-supply = <&vddcpu_b>;
	operating-points-v2 = <&cpu_opp_table_0>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cpu100 {
	cpu-supply = <&vddcpu_a>;
	operating-points-v2 = <&cpub_opp_table_1>;
	clocks = <&clkc CLKID_CPUB_CLK>;
	clock-latency = <50000>;
	};

	&cpu101 {
	cpu-supply = <&vddcpu_a>;
	operating-points-v2 = <&cpub_opp_table_1>;
	clocks = <&clkc CLKID_CPUB_CLK>;
	clock-latency = <50000>;
	};

	&cpu102 {
	cpu-supply = <&vddcpu_a>;
	operating-points-v2 = <&cpub_opp_table_1>;
	clocks = <&clkc CLKID_CPUB_CLK>;
	clock-latency = <50000>;
	};

	&cpu103 {
	cpu-supply = <&vddcpu_a>;
	operating-points-v2 = <&cpub_opp_table_1>;
	clocks = <&clkc CLKID_CPUB_CLK>;
	clock-latency = <50000>;
	};

	&ext_mdio {
	external_phy: ethernet-phy@0 {
	/* Realtek RTL8211F (0x001cc916) */
	reg = <0>;
	max-speed = <1000>;

	reset-assert-us = <10000>;
	reset-deassert-us = <30000>;
	reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW \| GPIO_OPEN_DRAIN)>;

	interrupt-parent = <&gpio_intc>;
	/* MAC_INTR on GPIOZ_14 */
	interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
	};
	};

	&ethmac {
	pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
	pinctrl-names = "default";
	status = "okay";
	phy-mode = "rgmii";
	phy-handle = <&external_phy>;
	amlogic,tx-delay-ns = <2>;
	};

	&frddr_a {
	status = "okay";
	};

	&frddr_b {
	status = "okay";
	};

	&frddr_c {
	status = "okay";
	};

	&gpio {
	/*
	* WARNING: The USB Hub on the Odroid-N2 needs a reset signal
	* to be turned high in order to be detected by the USB Controller
	* This signal should be handled by a USB specific power sequence
	* in order to reset the Hub when USB bus is powered down.
	*/
	usb-hub {
	gpio-hog;
	gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
	output-high;
	line-name = "usb-hub-reset";
	};
	};

	&hdmi_tx {
	status = "okay";
	pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
	pinctrl-names = "default";
	hdmi-supply = <&vcc_5v>;
	};

	&hdmi_tx_tmds_port {
	hdmi_tx_tmds_out: endpoint {
	remote-endpoint = <&hdmi_connector_in>;
	};
	};

	&ir {
	status = "okay";
	pinctrl-0 = <&remote_input_ao_pins>;
	pinctrl-names = "default";
	linux,rc-map-name = "rc-odroid";
	};

	&pwm_ab {
	pinctrl-0 = <&pwm_a_e_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>;
	clock-names = "clkin0";
	status = "okay";
	};

	&pwm_AO_cd {
	pinctrl-0 = <&pwm_ao_d_e_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>;
	clock-names = "clkin1";
	status = "okay";
	};

	/* SD card */
	&sd_emmc_b {
	status = "okay";
	pinctrl-0 = <&sdcard_c_pins>;
	pinctrl-1 = <&sdcard_clk_gate_c_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <4>;
	cap-sd-highspeed;
	max-frequency = <50000000>;
	disable-wp;

	cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&tflash_vdd>;
	vqmmc-supply = <&tf_io>;

	};

	/* eMMC */
	&sd_emmc_c {
	status = "okay";
	- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
	+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
	pinctrl-1 = <&emmc_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <8>;
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	max-frequency = <200000000>;
	disable-wp;

	mmc-pwrseq = <&emmc_pwrseq>;
	vmmc-supply = <&vcc_3v3>;
	vqmmc-supply = <&flash_1v8>;
	};

	+/*
	+ * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins
	+ * and eMMC Data 4 to 7 pins.
	+ * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,
	+ * and change bus-width to 4 then spifc can be enabled.
	+ * The SW1 slide should also be set to the correct position.
	+ */
	+&spifc {
	+ status = "disabled";
	+ pinctrl-0 = <&nor_pins>;
	+ pinctrl-names = "default";
	+
	+ mx25u64: spi-flash@0 {
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ compatible = "mxicy,mx25u6435f", "jedec,spi-nor";
	+ reg = <0>;
	+ spi-max-frequency = <104000000>;
	+ };
	+};
	+
	&tdmif_b {
	status = "okay";
	};

	&tdmout_b {
	status = "okay";
	};

	&tohdmitx {
	status = "okay";
	};

	&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
	};

	&usb {
	status = "okay";
	vbus-supply = <&usb_pwr_en>;
	};

	&usb2_phy0 {
	phy-supply = <&vcc_5v>;
	};

	&usb2_phy1 {
	/* Enable the hub which is connected to this port */
	phy-supply = <&hub_5v>;
	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12b-ugoos-am6.dts b/sys/gnu/dts/arm64/amlogic/meson-g12b-ugoos-am6.dts
	index ccd0bced01e8..06c5430eb92d 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-g12b-ugoos-am6.dts
	+++ b/sys/gnu/dts/arm64/amlogic/meson-g12b-ugoos-am6.dts
	@@ -1,557 +1,557 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2019 BayLibre, SAS
	* Author: Neil Armstrong <narmstrong@baylibre.com>
	* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
	*/

	/dts-v1/;

	#include "meson-g12b.dtsi"
	#include "meson-g12b-s922x.dtsi"
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/gpio/meson-g12a-gpio.h>
	#include <dt-bindings/sound/meson-g12a-tohdmitx.h>

	/ {
	compatible = "ugoos,am6", "amlogic,g12b";
	model = "Ugoos AM6";

	aliases {
	serial0 = &uart_AO;
	ethernet0 = &ethmac;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@0 {
	device_type = "memory";
	reg = <0x0 0x0 0x0 0x40000000>;
	};

	emmc_pwrseq: emmc-pwrseq {
	compatible = "mmc-pwrseq-emmc";
	reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
	};

	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
	clocks = <&wifi32k>;
	clock-names = "ext_clock";
	};

	spdif_dit: audio-codec-1 {
	#sound-dai-cells = <0>;
	compatible = "linux,spdif-dit";
	status = "okay";
	sound-name-prefix = "DIT";
	};

	flash_1v8: regulator-flash_1v8 {
	compatible = "regulator-fixed";
	regulator-name = "FLASH_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vcc_3v3>;
	regulator-always-on;
	};

	main_12v: regulator-main_12v {
	compatible = "regulator-fixed";
	regulator-name = "12V";
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	regulator-always-on;
	};

	vcc_5v: regulator-vcc_5v {
	compatible = "regulator-fixed";
	regulator-name = "VCC_5V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&main_12v>;

	gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
	enable-active-high;
	};

	vcc_1v8: regulator-vcc_1v8 {
	compatible = "regulator-fixed";
	regulator-name = "VCC_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vcc_3v3>;
	regulator-always-on;
	};

	vcc_3v3: regulator-vcc_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VCC_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vddao_3v3>;
	regulator-always-on;
	/* FIXME: actually controlled by VDDCPU_B_EN */
	};

	vddcpu_a: regulator-vddcpu-a {
	/*
	* MP1653 Regulator.
	*/
	compatible = "pwm-regulator";

	regulator-name = "VDDCPU_A";
	regulator-min-microvolt = <721000>;
	regulator-max-microvolt = <1022000>;

	vin-supply = <&main_12v>;

	pwms = <&pwm_ab 0 1250 0>;
	pwm-dutycycle-range = <100 0>;

	regulator-boot-on;
	regulator-always-on;
	};

	vddcpu_b: regulator-vddcpu-b {
	/*
	* MP1652 Regulator.
	*/
	compatible = "pwm-regulator";

	regulator-name = "VDDCPU_B";
	regulator-min-microvolt = <721000>;
	regulator-max-microvolt = <1022000>;

	vin-supply = <&main_12v>;

	pwms = <&pwm_AO_cd 1 1250 0>;
	pwm-dutycycle-range = <100 0>;

	regulator-boot-on;
	regulator-always-on;
	};

	usb1_pow: regulator-usb1-pow {
	compatible = "regulator-fixed";
	regulator-name = "USB1_POW";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&vcc_5v>;

	/* connected to SY6280A Power Switch */
	gpio = <&gpio GPIOA_8 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	usb_pwr_en: regulator-usb-pwr-en {
	compatible = "regulator-fixed";
	regulator-name = "USB_PWR_EN";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&vcc_5v>;

	/* Connected to USB3 Type-A Port power enable */
	gpio = <&gpio GPIOAO_7 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vddao_1v8: regulator-vddao-1v8 {
	compatible = "regulator-fixed";
	regulator-name = "VDDAO_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vddao_3v3>;
	regulator-always-on;
	};

	vddao_3v3: regulator-vddao-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VDDAO_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&main_12v>;
	regulator-always-on;
	};

	cvbs-connector {
	compatible = "composite-video-connector";

	port {
	cvbs_connector_in: endpoint {
	remote-endpoint = <&cvbs_vdac_out>;
	};
	};
	};

	hdmi-connector {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_connector_in: endpoint {
	remote-endpoint = <&hdmi_tx_tmds_out>;
	};
	};
	};

	sound {
	compatible = "amlogic,axg-sound-card";
	model = "G12B-UGOOS-AM6";
	audio-aux-devs = <&tdmout_b>;
	audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
	"TDMOUT_B IN 1", "FRDDR_B OUT 1",
	"TDMOUT_B IN 2", "FRDDR_C OUT 1",
	"TDM_B Playback", "TDMOUT_B OUT",
	"SPDIFOUT IN 0", "FRDDR_A OUT 3",
	"SPDIFOUT IN 1", "FRDDR_B OUT 3",
	"SPDIFOUT IN 2", "FRDDR_C OUT 3";

	assigned-clocks = <&clkc CLKID_MPLL2>,
	<&clkc CLKID_MPLL0>,
	<&clkc CLKID_MPLL1>;
	assigned-clock-parents = <0>, <0>, <0>;
	assigned-clock-rates = <294912000>,
	<270950400>,
	<393216000>;
	status = "okay";

	dai-link-0 {
	sound-dai = <&frddr_a>;
	};

	dai-link-1 {
	sound-dai = <&frddr_b>;
	};

	dai-link-2 {
	sound-dai = <&frddr_c>;
	};

	/* 8ch hdmi interface */
	dai-link-3 {
	sound-dai = <&tdmif_b>;
	dai-format = "i2s";
	dai-tdm-slot-tx-mask-0 = <1 1>;
	dai-tdm-slot-tx-mask-1 = <1 1>;
	dai-tdm-slot-tx-mask-2 = <1 1>;
	dai-tdm-slot-tx-mask-3 = <1 1>;
	mclk-fs = <256>;

	codec {
	sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
	};
	};

	/* spdif hdmi or toslink interface */
	dai-link-4 {
	sound-dai = <&spdifout>;

	codec-0 {
	sound-dai = <&spdif_dit>;
	};

	codec-1 {
	sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>;
	};
	};

	/* spdif hdmi interface */
	dai-link-5 {
	sound-dai = <&spdifout_b>;

	codec {
	sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>;
	};
	};

	/* hdmi glue */
	dai-link-6 {
	sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;

	codec {
	sound-dai = <&hdmi_tx>;
	};
	};
	};

	wifi32k: wifi32k {
	compatible = "pwm-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
	};
	};

	&arb {
	status = "okay";
	};

	&cec_AO {
	pinctrl-0 = <&cec_ao_a_h_pins>;
	pinctrl-names = "default";
	status = "disabled";
	hdmi-phandle = <&hdmi_tx>;
	};

	&cecb_AO {
	pinctrl-0 = <&cec_ao_b_h_pins>;
	pinctrl-names = "default";
	status = "okay";
	hdmi-phandle = <&hdmi_tx>;
	};

	&clkc_audio {
	status = "okay";
	};

	&cpu0 {
	cpu-supply = <&vddcpu_b>;
	operating-points-v2 = <&cpu_opp_table_0>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cpu1 {
	cpu-supply = <&vddcpu_b>;
	operating-points-v2 = <&cpu_opp_table_0>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cpu100 {
	cpu-supply = <&vddcpu_a>;
	operating-points-v2 = <&cpub_opp_table_1>;
	clocks = <&clkc CLKID_CPUB_CLK>;
	clock-latency = <50000>;
	};

	&cpu101 {
	cpu-supply = <&vddcpu_a>;
	operating-points-v2 = <&cpub_opp_table_1>;
	clocks = <&clkc CLKID_CPUB_CLK>;
	clock-latency = <50000>;
	};

	&cpu102 {
	cpu-supply = <&vddcpu_a>;
	operating-points-v2 = <&cpub_opp_table_1>;
	clocks = <&clkc CLKID_CPUB_CLK>;
	clock-latency = <50000>;
	};

	&cpu103 {
	cpu-supply = <&vddcpu_a>;
	operating-points-v2 = <&cpub_opp_table_1>;
	clocks = <&clkc CLKID_CPUB_CLK>;
	clock-latency = <50000>;
	};

	&cvbs_vdac_port {
	cvbs_vdac_out: endpoint {
	remote-endpoint = <&cvbs_connector_in>;
	};
	};

	&ext_mdio {
	external_phy: ethernet-phy@0 {
	/* Realtek RTL8211F (0x001cc916) */
	reg = <0>;
	max-speed = <1000>;

	reset-assert-us = <10000>;
	reset-deassert-us = <30000>;
	reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW \| GPIO_OPEN_DRAIN)>;

	interrupt-parent = <&gpio_intc>;
	/* MAC_INTR on GPIOZ_14 */
	interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
	};
	};

	&ethmac {
	pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
	pinctrl-names = "default";
	status = "okay";
	phy-mode = "rgmii";
	phy-handle = <&external_phy>;
	amlogic,tx-delay-ns = <2>;
	};

	&frddr_a {
	status = "okay";
	};

	&frddr_b {
	status = "okay";
	};

	&frddr_c {
	status = "okay";
	};

	&hdmi_tx {
	status = "okay";
	pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
	pinctrl-names = "default";
	hdmi-supply = <&vcc_5v>;
	};

	&hdmi_tx_tmds_port {
	hdmi_tx_tmds_out: endpoint {
	remote-endpoint = <&hdmi_connector_in>;
	};
	};

	&ir {
	status = "okay";
	pinctrl-0 = <&remote_input_ao_pins>;
	pinctrl-names = "default";
	linux,rc-map-name = "rc-khadas";
	};

	&pwm_ab {
	pinctrl-0 = <&pwm_a_e_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>;
	clock-names = "clkin0";
	status = "okay";
	};

	&pwm_AO_cd {
	pinctrl-0 = <&pwm_ao_d_e_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>;
	clock-names = "clkin1";
	status = "okay";
	};

	&pwm_ef {
	pinctrl-0 = <&pwm_e_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>;
	clock-names = "clkin0";
	status = "okay";
	};

	/* SDIO */
	&sd_emmc_a {
	status = "okay";
	pinctrl-0 = <&sdio_pins>;
	pinctrl-1 = <&sdio_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";
	#address-cells = <1>;
	#size-cells = <0>;

	bus-width = <4>;
	cap-sd-highspeed;
	sd-uhs-sdr50;
	max-frequency = <100000000>;

	non-removable;
	disable-wp;

	mmc-pwrseq = <&sdio_pwrseq>;

	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vddao_1v8>;

	brcmf: wifi@1 {
	reg = <1>;
	compatible = "brcm,bcm4329-fmac";
	};
	};

	/* SD card */
	&sd_emmc_b {
	status = "okay";
	pinctrl-0 = <&sdcard_c_pins>;
	pinctrl-1 = <&sdcard_clk_gate_c_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <4>;
	cap-sd-highspeed;
	max-frequency = <50000000>;
	disable-wp;

	cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vddao_3v3>;
	};

	/* eMMC */
	&sd_emmc_c {
	status = "okay";
	- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
	+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
	pinctrl-1 = <&emmc_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <8>;
	cap-mmc-highspeed;
	max-frequency = <100000000>;
	disable-wp;

	mmc-pwrseq = <&emmc_pwrseq>;
	vmmc-supply = <&vcc_3v3>;
	vqmmc-supply = <&flash_1v8>;
	};

	&spdifout {
	pinctrl-0 = <&spdif_out_h_pins>;
	pinctrl-names = "default";
	status = "okay";
	};

	&spdifout_b {
	status = "okay";
	};

	&tdmif_b {
	status = "okay";
	};

	&tdmout_b {
	status = "okay";
	};

	&tohdmitx {
	status = "okay";
	};

	&uart_A {
	status = "okay";
	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
	pinctrl-names = "default";
	uart-has-rtscts;

	bluetooth {
	compatible = "brcm,bcm43438-bt";
	shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
	max-speed = <2000000>;
	clocks = <&wifi32k>;
	clock-names = "lpo";
	};
	};

	&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
	};

	&usb {
	status = "okay";
	dr_mode = "host";
	- vbus-regulator = <&usb_pwr_en>;
	+ vbus-supply = <&usb_pwr_en>;
	};

	&usb2_phy0 {
	phy-supply = <&usb1_pow>;
	};

	&usb2_phy1 {
	phy-supply = <&usb1_pow>;
	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-gx.dtsi b/sys/gnu/dts/arm64/amlogic/meson-gx.dtsi
	index 40db06e28b66..03f79fe045b7 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-gx.dtsi
	+++ b/sys/gnu/dts/arm64/amlogic/meson-gx.dtsi
	@@ -1,594 +1,646 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2016 Andreas Färber
	*
	* Copyright (c) 2016 BayLibre, SAS.
	* Author: Neil Armstrong <narmstrong@baylibre.com>
	*
	* Copyright (c) 2016 Endless Computers, Inc.
	* Author: Carlo Caione <carlo@endlessm.com>
	*/

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	+#include <dt-bindings/thermal/thermal.h>

	/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	/* 16 MiB reserved for Hardware ROM Firmware */
	hwrom_reserved: hwrom@0 {
	reg = <0x0 0x0 0x0 0x1000000>;
	no-map;
	};

	/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
	secmon_reserved: secmon@10000000 {
	reg = <0x0 0x10000000 0x0 0x200000>;
	no-map;
	};

	/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
	secmon_reserved_alt: secmon@5000000 {
	reg = <0x0 0x05000000 0x0 0x300000>;
	no-map;
	};

	linux,cma {
	compatible = "shared-dma-pool";
	reusable;
	size = <0x0 0x10000000>;
	alignment = <0x0 0x400000>;
	linux,cma-default;
	};
	};

	chosen {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	simplefb_cvbs: framebuffer-cvbs {
	compatible = "amlogic,simple-framebuffer",
	"simple-framebuffer";
	amlogic,pipeline = "vpu-cvbs";
	power-domains = <&pwrc_vpu>;
	status = "disabled";
	};

	simplefb_hdmi: framebuffer-hdmi {
	compatible = "amlogic,simple-framebuffer",
	"simple-framebuffer";
	amlogic,pipeline = "vpu-hdmi";
	power-domains = <&pwrc_vpu>;
	status = "disabled";
	};
	};

	cpus {
	#address-cells = <0x2>;
	#size-cells = <0x0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x0>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	clocks = <&scpi_dvfs 0>;
	+ #cooling-cells = <2>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x1>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	clocks = <&scpi_dvfs 0>;
	+ #cooling-cells = <2>;
	};

	cpu2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x2>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	clocks = <&scpi_dvfs 0>;
	+ #cooling-cells = <2>;
	};

	cpu3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x3>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	clocks = <&scpi_dvfs 0>;
	+ #cooling-cells = <2>;
	};

	l2: l2-cache0 {
	compatible = "cache";
	};
	};

	+ thermal-zones {
	+ cpu-thermal {
	+ polling-delay-passive = <250>; /* milliseconds */
	+ polling-delay = <1000>; /* milliseconds */
	+
	+ thermal-sensors = <&scpi_sensors 0>;
	+
	+ trips {
	+ cpu_passive: cpu-passive {
	+ temperature = <80000>; /* millicelsius */
	+ hysteresis = <2000>; /* millicelsius */
	+ type = "passive";
	+ };
	+
	+ cpu_hot: cpu-hot {
	+ temperature = <90000>; /* millicelsius */
	+ hysteresis = <2000>; /* millicelsius */
	+ type = "hot";
	+ };
	+
	+ cpu_critical: cpu-critical {
	+ temperature = <110000>; /* millicelsius */
	+ hysteresis = <2000>; /* millicelsius */
	+ type = "critical";
	+ };
	+ };
	+
	+ cpu_cooling_maps: cooling-maps {
	+ map0 {
	+ trip = <&cpu_passive>;
	+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	+ };
	+
	+ map1 {
	+ trip = <&cpu_hot>;
	+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	+ };
	+ };
	+ };
	+ };
	+
	arm-pmu {
	compatible = "arm,cortex-a53-pmu";
	interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13
	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14
	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11
	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10
	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	xtal: xtal-clk {
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-output-names = "xtal";
	#clock-cells = <0>;
	};

	firmware {
	sm: secure-monitor {
	compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
	};
	};

	efuse: efuse {
	compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
	#address-cells = <1>;
	#size-cells = <1>;
	read-only;
	secure-monitor = <&sm>;

	sn: sn@14 {
	reg = <0x14 0x10>;
	};

	eth_mac: eth_mac@34 {
	reg = <0x34 0x10>;
	};

	bid: bid@46 {
	reg = <0x46 0x30>;
	};
	};

	scpi {
	compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
	mboxes = <&mailbox 1 &mailbox 2>;
	shmem = <&cpu_scp_lpri &cpu_scp_hpri>;

	scpi_clocks: clocks {
	compatible = "arm,scpi-clocks";

	scpi_dvfs: scpi_clocks@0 {
	compatible = "arm,scpi-dvfs-clocks";
	#clock-cells = <1>;
	clock-indices = <0>;
	clock-output-names = "vcpu";
	};
	};

	scpi_sensors: sensors {
	compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
	#thermal-sensor-cells = <1>;
	};
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	cbus: bus@c1100000 {
	compatible = "simple-bus";
	reg = <0x0 0xc1100000 0x0 0x100000>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;

	gpio_intc: interrupt-controller@9880 {
	compatible = "amlogic,meson-gpio-intc";
	reg = <0x0 0x9880 0x0 0x10>;
	interrupt-controller;
	#interrupt-cells = <2>;
	amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
	status = "disabled";
	};

	reset: reset-controller@4404 {
	compatible = "amlogic,meson-gxbb-reset";
	reg = <0x0 0x04404 0x0 0x9c>;
	#reset-cells = <1>;
	};

	uart_A: serial@84c0 {
	compatible = "amlogic,meson-gx-uart";
	reg = <0x0 0x84c0 0x0 0x18>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
	status = "disabled";
	};

	uart_B: serial@84dc {
	compatible = "amlogic,meson-gx-uart";
	reg = <0x0 0x84dc 0x0 0x18>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
	status = "disabled";
	};

	i2c_A: i2c@8500 {
	compatible = "amlogic,meson-gxbb-i2c";
	reg = <0x0 0x08500 0x0 0x20>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	pwm_ab: pwm@8550 {
	compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
	reg = <0x0 0x08550 0x0 0x10>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm_cd: pwm@8650 {
	compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
	reg = <0x0 0x08650 0x0 0x10>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	saradc: adc@8680 {
	compatible = "amlogic,meson-saradc";
	reg = <0x0 0x8680 0x0 0x34>;
	#io-channel-cells = <1>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
	status = "disabled";
	};

	pwm_ef: pwm@86c0 {
	compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
	reg = <0x0 0x086c0 0x0 0x10>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	uart_C: serial@8700 {
	compatible = "amlogic,meson-gx-uart";
	reg = <0x0 0x8700 0x0 0x18>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
	status = "disabled";
	};

	clock-measure@8758 {
	compatible = "amlogic,meson-gx-clk-measure";
	reg = <0x0 0x8758 0x0 0x10>;
	};

	i2c_B: i2c@87c0 {
	compatible = "amlogic,meson-gxbb-i2c";
	reg = <0x0 0x087c0 0x0 0x20>;
	interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c_C: i2c@87e0 {
	compatible = "amlogic,meson-gxbb-i2c";
	reg = <0x0 0x087e0 0x0 0x20>;
	interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spicc: spi@8d80 {
	compatible = "amlogic,meson-gx-spicc";
	reg = <0x0 0x08d80 0x0 0x80>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spifc: spi@8c80 {
	compatible = "amlogic,meson-gxbb-spifc";
	reg = <0x0 0x08c80 0x0 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	watchdog@98d0 {
	compatible = "amlogic,meson-gxbb-wdt";
	reg = <0x0 0x098d0 0x0 0x10>;
	clocks = <&xtal>;
	};
	};

	gic: interrupt-controller@c4301000 {
	compatible = "arm,gic-400";
	reg = <0x0 0xc4301000 0 0x1000>,
	<0x0 0xc4302000 0 0x2000>,
	<0x0 0xc4304000 0 0x2000>,
	<0x0 0xc4306000 0 0x2000>;
	interrupt-controller;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>;
	#interrupt-cells = <3>;
	#address-cells = <0>;
	};

	sram: sram@c8000000 {
	compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram";
	reg = <0x0 0xc8000000 0x0 0x14000>;

	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x0 0xc8000000 0x14000>;

	cpu_scp_lpri: scp-shmem@0 {
	compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
	reg = <0x13000 0x400>;
	};

	cpu_scp_hpri: scp-shmem@200 {
	compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
	reg = <0x13400 0x400>;
	};
	};

	aobus: bus@c8100000 {
	compatible = "simple-bus";
	reg = <0x0 0xc8100000 0x0 0x100000>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;

	sysctrl_AO: sys-ctrl@0 {
	compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
	reg = <0x0 0x0 0x0 0x100>;

	pwrc_vpu: power-controller-vpu {
	compatible = "amlogic,meson-gx-pwrc-vpu";
	#power-domain-cells = <0>;
	amlogic,hhi-sysctrl = <&sysctrl>;
	};

	clkc_AO: clock-controller {
	compatible = "amlogic,meson-gx-aoclkc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};
	};

	cec_AO: cec@100 {
	compatible = "amlogic,meson-gx-ao-cec";
	reg = <0x0 0x00100 0x0 0x14>;
	interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
	status = "disabled";
	};

	sec_AO: ao-secure@140 {
	compatible = "amlogic,meson-gx-ao-secure", "syscon";
	reg = <0x0 0x140 0x0 0x140>;
	amlogic,has-chip-id;
	};

	uart_AO: serial@4c0 {
	compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
	reg = <0x0 0x004c0 0x0 0x18>;
	interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
	status = "disabled";
	};

	uart_AO_B: serial@4e0 {
	compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
	reg = <0x0 0x004e0 0x0 0x18>;
	interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
	status = "disabled";
	};

	i2c_AO: i2c@500 {
	compatible = "amlogic,meson-gxbb-i2c";
	reg = <0x0 0x500 0x0 0x20>;
	interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	pwm_AO_ab: pwm@550 {
	compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm";
	reg = <0x0 0x00550 0x0 0x10>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	ir: ir@580 {
	compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
	reg = <0x0 0x00580 0x0 0x40>;
	interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
	status = "disabled";
	};
	};

	vdec: video-codec@c8820000 {
	compatible = "amlogic,gx-vdec";
	reg = <0x0 0xc8820000 0x0 0x10000>,
	<0x0 0xc110a580 0x0 0xe4>;
	reg-names = "dos", "esparser";

	interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "vdec", "esparser";

	amlogic,ao-sysctrl = <&sysctrl_AO>;
	amlogic,canvas = <&canvas>;
	};

	periphs: bus@c8834000 {
	compatible = "simple-bus";
	reg = <0x0 0xc8834000 0x0 0x2000>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;

	hwrng: rng {
	compatible = "amlogic,meson-rng";
	reg = <0x0 0x0 0x0 0x4>;
	};
	};

	dmcbus: bus@c8838000 {
	compatible = "simple-bus";
	reg = <0x0 0xc8838000 0x0 0x400>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>;

	canvas: video-lut@48 {
	compatible = "amlogic,canvas";
	reg = <0x0 0x48 0x0 0x14>;
	};
	};

	hiubus: bus@c883c000 {
	compatible = "simple-bus";
	reg = <0x0 0xc883c000 0x0 0x2000>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;

	sysctrl: system-controller@0 {
	compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";
	reg = <0 0 0 0x400>;
	};

	mailbox: mailbox@404 {
	compatible = "amlogic,meson-gxbb-mhu";
	reg = <0 0x404 0 0x4c>;
	interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
	#mbox-cells = <1>;
	};
	};

	ethmac: ethernet@c9410000 {
	compatible = "amlogic,meson-gxbb-dwmac",
	"snps,dwmac-3.70a",
	"snps,dwmac";
	reg = <0x0 0xc9410000 0x0 0x10000>,
	<0x0 0xc8834540 0x0 0x4>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	rx-fifo-depth = <4096>;
	tx-fifo-depth = <2048>;
	status = "disabled";
	};

	apb: apb@d0000000 {
	compatible = "simple-bus";
	reg = <0x0 0xd0000000 0x0 0x200000>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;

	sd_emmc_a: mmc@70000 {
	compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
	reg = <0x0 0x70000 0x0 0x800>;
	interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
	status = "disabled";
	};

	sd_emmc_b: mmc@72000 {
	compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
	reg = <0x0 0x72000 0x0 0x800>;
	interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
	status = "disabled";
	};

	sd_emmc_c: mmc@74000 {
	compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
	reg = <0x0 0x74000 0x0 0x800>;
	interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
	status = "disabled";
	};
	};

	vpu: vpu@d0100000 {
	compatible = "amlogic,meson-gx-vpu";
	reg = <0x0 0xd0100000 0x0 0x100000>,
	<0x0 0xc883c000 0x0 0x1000>;
	reg-names = "vpu", "hhi";
	interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
	#address-cells = <1>;
	#size-cells = <0>;
	amlogic,canvas = <&canvas>;

	/* CVBS VDAC output port */
	cvbs_vdac_port: port@0 {
	reg = <0>;
	};

	/* HDMI-TX output port */
	hdmi_tx_port: port@1 {
	reg = <1>;

	hdmi_tx_out: endpoint {
	remote-endpoint = <&hdmi_tx_in>;
	};
	};
	};

	hdmi_tx: hdmi-tx@c883a000 {
	compatible = "amlogic,meson-gx-dw-hdmi";
	reg = <0x0 0xc883a000 0x0 0x1c>;
	interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";

	/* VPU VENC Input */
	hdmi_tx_venc_port: port@0 {
	reg = <0>;

	hdmi_tx_in: endpoint {
	remote-endpoint = <&hdmi_tx_out>;
	};
	};

	/* TMDS Output */
	hdmi_tx_tmds_port: port@1 {
	reg = <1>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb-kii-pro.dts b/sys/gnu/dts/arm64/amlogic/meson-gxbb-kii-pro.dts
	index 2f1f829450a2..6c9cc45fb417 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-gxbb-kii-pro.dts
	+++ b/sys/gnu/dts/arm64/amlogic/meson-gxbb-kii-pro.dts
	@@ -1,78 +1,82 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2019 Mohammad Rasim <mohammad.rasim96@gmail.com>
	*/

	/dts-v1/;

	#include "meson-gxbb-p20x.dtsi"

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/leds/common.h>
	/ {
	compatible = "videostrong,kii-pro", "amlogic,p201", "amlogic,s905", "amlogic,meson-gxbb";
	model = "Videostrong KII Pro";

	leds {
	compatible = "gpio-leds";
	status {
	gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
	default-state = "off";
	color = <LED_COLOR_ID_RED>;
	function = LED_FUNCTION_STATUS;
	};
	};

	gpio-keys-polled {
	compatible = "gpio-keys-polled";
	#address-cells = <1>;
	#size-cells = <0>;
	poll-interval = <20>;

	button-reset {
	label = "reset";
	linux,code = <KEY_POWER>;
	gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
	};
	};

	};



	&uart_A {
	status = "okay";
	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
	pinctrl-names = "default";
	uart-has-rtscts;

	bluetooth {
	compatible = "brcm,bcm4335a0";
	};
	};



	&ethmac {
	status = "okay";
	pinctrl-0 = <&eth_rmii_pins>;
	pinctrl-names = "default";

	phy-handle = <&eth_phy0>;
	phy-mode = "rmii";

	mdio {
	compatible = "snps,dwmac-mdio";
	#address-cells = <1>;
	#size-cells = <0>;

	eth_phy0: ethernet-phy@0 {
	/* IC Plus IP101GR (0x02430c54) */
	reg = <0>;
	reset-assert-us = <10000>;
	reset-deassert-us = <10000>;
	reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
	};
	};
	};
	+
	+&ir {
	+ linux,rc-map-name = "rc-videostrong-kii-pro";
	+};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb-odroidc2.dts b/sys/gnu/dts/arm64/amlogic/meson-gxbb-odroidc2.dts
	index 6ded279c40c8..b46ef985bb44 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-gxbb-odroidc2.dts
	+++ b/sys/gnu/dts/arm64/amlogic/meson-gxbb-odroidc2.dts
	@@ -1,377 +1,378 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2016 Andreas Färber
	* Copyright (c) 2016 BayLibre, Inc.
	* Author: Kevin Hilman <khilman@kernel.org>
	*/

	/dts-v1/;

	#include "meson-gxbb.dtsi"
	#include <dt-bindings/gpio/gpio.h>

	/ {
	compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
	model = "Hardkernel ODROID-C2";

	aliases {
	serial0 = &uart_AO;
	ethernet0 = &ethmac;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@0 {
	device_type = "memory";
	reg = <0x0 0x0 0x0 0x80000000>;
	};

	usb_otg_pwr: regulator-usb-pwrs {
	compatible = "regulator-fixed";

	regulator-name = "USB_OTG_PWR";

	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;

	/*
	* signal name from schematics: PWREN
	*/
	gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	/*
	* signal name from schematics: USB_POWER
	*/
	vin-supply = <&p5v0>;
	};

	leds {
	compatible = "gpio-leds";
	blue {
	label = "c2:blue:alive";
	gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
	linux,default-trigger = "heartbeat";
	default-state = "off";
	};
	};

	p5v0: regulator-p5v0 {
	compatible = "regulator-fixed";

	regulator-name = "P5V0";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	hdmi_p5v0: regulator-hdmi_p5v0 {
	compatible = "regulator-fixed";
	regulator-name = "HDMI_P5V0";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	/* AP2331SA-7 */
	vin-supply = <&p5v0>;
	};

	tflash_vdd: regulator-tflash_vdd {
	compatible = "regulator-fixed";

	regulator-name = "TFLASH_VDD";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	/*
	* signal name from schematics: TFLASH_VDD_EN
	*/
	gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	/* U16 RT9179GB */
	vin-supply = <&vddio_ao3v3>;
	};

	tf_io: gpio-regulator-tf_io {
	compatible = "regulator-gpio";

	regulator-name = "TF_IO";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	/*
	* signal name from schematics: TF_3V3N_1V8_EN
	*/
	gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
	gpios-states = <0>;

	states = <3300000 0>,
	<1800000 1>;
	/* U12/U13 RT9179GB */
	vin-supply = <&vddio_ao3v3>;
	};

	vcc1v8: regulator-vcc1v8 {
	compatible = "regulator-fixed";
	regulator-name = "VCC1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	/* U18 RT9179GB */
	vin-supply = <&vddio_ao3v3>;
	};

	vcc3v3: regulator-vcc3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VCC3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	vddio_ao1v8: regulator-vddio-ao1v8 {
	compatible = "regulator-fixed";
	regulator-name = "VDDIO_AO1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	/* U17 RT9179GB */
	vin-supply = <&p5v0>;
	};

	vddio_ao3v3: regulator-vddio-ao3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VDDIO_AO3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	/* U11 MP2161GJ-C499 */
	vin-supply = <&p5v0>;
	};

	ddr3_1v5: regulator-ddr3_1v5 {
	compatible = "regulator-fixed";
	regulator-name = "DDR3_1V5";
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;
	/* U15 MP2161GJ-C499 */
	vin-supply = <&p5v0>;
	};

	emmc_pwrseq: emmc-pwrseq {
	compatible = "mmc-pwrseq-emmc";
	reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
	};

	hdmi-connector {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_connector_in: endpoint {
	remote-endpoint = <&hdmi_tx_tmds_out>;
	};
	};
	};
	};

	&cec_AO {
	status = "okay";
	pinctrl-0 = <&ao_cec_pins>;
	pinctrl-names = "default";
	hdmi-phandle = <&hdmi_tx>;
	};

	&ethmac {
	status = "okay";
	pinctrl-0 = <&eth_rgmii_pins>;
	pinctrl-names = "default";
	phy-handle = <&eth_phy0>;
	phy-mode = "rgmii";

	amlogic,tx-delay-ns = <2>;

	mdio {
	compatible = "snps,dwmac-mdio";
	#address-cells = <1>;
	#size-cells = <0>;

	eth_phy0: ethernet-phy@0 {
	/* Realtek RTL8211F (0x001cc916) */
	reg = <0>;

	reset-assert-us = <10000>;
	reset-deassert-us = <30000>;
	reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;

	interrupt-parent = <&gpio_intc>;
	/* MAC_INTR on GPIOZ_15 */
	interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
	};
	};
	};

	&gpio_ao {
	/*
	* WARNING: The USB Hub on the Odroid-C2 needs a reset signal
	* to be turned high in order to be detected by the USB Controller
	* This signal should be handled by a USB specific power sequence
	* in order to reset the Hub when USB bus is powered down.
	*/
	usb-hub {
	gpio-hog;
	gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
	output-high;
	line-name = "usb-hub-reset";
	};
	};

	&hdmi_tx {
	status = "okay";
	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
	pinctrl-names = "default";
	hdmi-supply = <&hdmi_p5v0>;
	};

	&hdmi_tx_tmds_port {
	hdmi_tx_tmds_out: endpoint {
	remote-endpoint = <&hdmi_connector_in>;
	};
	};

	&i2c_A {
	status = "okay";
	pinctrl-0 = <&i2c_a_pins>;
	pinctrl-names = "default";
	};

	&ir {
	status = "okay";
	pinctrl-0 = <&remote_input_ao_pins>;
	pinctrl-names = "default";
	+ linux,rc-map-name = "rc-odroid";
	};

	&gpio_ao {
	gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En",
	"USB HUB nRESET", "USB OTG Power En",
	"J7 Header Pin2", "IR In", "J7 Header Pin4",
	"J7 Header Pin6", "J7 Header Pin5", "J7 Header Pin7",
	"HDMI CEC", "SYS LED",
	/* GPIO_TEST_N */
	"";
	};

	&gpio {
	gpio-line-names = /* Bank GPIOZ */
	"Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
	"Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2",
	"Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
	"Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
	"Eth PHY nRESET", "Eth PHY Intc",
	/* Bank GPIOH */
	"HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", "",
	/* Bank BOOT */
	"eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
	"eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
	"eMMC Reset", "eMMC CMD",
	"", "", "", "", "", "", "",
	/* Bank CARD */
	"SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
	"SDCard D3", "SDCard D2", "SDCard Det",
	/* Bank GPIODV */
	"", "", "", "", "", "", "", "", "", "", "", "", "",
	"", "", "", "", "", "", "", "", "", "", "",
	"I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
	"PWM D", "PWM B",
	/* Bank GPIOY */
	"Revision Bit0", "Revision Bit1", "",
	"J2 Header Pin35", "", "", "", "J2 Header Pin36",
	"J2 Header Pin31", "", "", "", "TF VDD En",
	"J2 Header Pin32", "J2 Header Pin26", "", "",
	/* Bank GPIOX */
	"J2 Header Pin29", "J2 Header Pin24",
	"J2 Header Pin23", "J2 Header Pin22",
	"J2 Header Pin21", "J2 Header Pin18",
	"J2 Header Pin33", "J2 Header Pin19",
	"J2 Header Pin16", "J2 Header Pin15",
	"J2 Header Pin12", "J2 Header Pin13",
	"J2 Header Pin8", "J2 Header Pin10",
	"", "", "", "", "",
	"J2 Header Pin11", "", "J2 Header Pin7", "",
	/* Bank GPIOCLK */
	"", "", "", "";
	};

	&saradc {
	status = "okay";
	vref-supply = <&vcc1v8>;
	};

	&scpi_clocks {
	status = "disabled";
	};

	/* SD */
	&sd_emmc_b {
	status = "okay";
	pinctrl-0 = <&sdcard_pins>;
	pinctrl-1 = <&sdcard_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <4>;
	cap-sd-highspeed;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-ddr50;
	max-frequency = <100000000>;
	disable-wp;

	cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;

	vmmc-supply = <&tflash_vdd>;
	vqmmc-supply = <&tf_io>;
	};

	/* eMMC */
	&sd_emmc_c {
	status = "okay";
	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
	pinctrl-1 = <&emmc_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <8>;
	max-frequency = <200000000>;
	non-removable;
	disable-wp;
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;

	mmc-pwrseq = <&emmc_pwrseq>;
	vmmc-supply = <&vcc3v3>;
	vqmmc-supply = <&vcc1v8>;
	};

	&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
	};

	&usb0_phy {
	status = "disabled";
	phy-supply = <&usb_otg_pwr>;
	};

	&usb1_phy {
	status = "okay";
	phy-supply = <&usb_otg_pwr>;
	};

	&usb0 {
	status = "disabled";
	};

	&usb1 {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb-vega-s95.dtsi b/sys/gnu/dts/arm64/amlogic/meson-gxbb-vega-s95.dtsi
	index 5eab3dfdbd55..45cb83625951 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-gxbb-vega-s95.dtsi
	+++ b/sys/gnu/dts/arm64/amlogic/meson-gxbb-vega-s95.dtsi
	@@ -1,273 +1,276 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2016 Andreas Färber
	*/

	#include "meson-gxbb.dtsi"

	/ {
	compatible = "tronsmart,vega-s95", "amlogic,meson-gxbb";

	aliases {
	serial0 = &uart_AO;
	ethernet0 = &ethmac;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	leds {
	compatible = "gpio-leds";

	blue {
	label = "vega-s95:blue:on";
	gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
	default-state = "on";
	panic-indicator;
	};
	};

	usb_pwr: regulator-usb-pwrs {
	compatible = "regulator-fixed";

	regulator-name = "USB_PWR";

	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;

	gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vddio_boot: regulator-vddio_boot {
	compatible = "regulator-fixed";
	regulator-name = "VDDIO_BOOT";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	vddao_3v3: regulator-vddao_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VDDAO_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	vddio_ao18: regulator-vddio_ao18 {
	compatible = "regulator-fixed";
	regulator-name = "VDDIO_AO18";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	vcc_3v3: regulator-vcc_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VCC_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	emmc_pwrseq: emmc-pwrseq {
	compatible = "mmc-pwrseq-emmc";
	reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
	};

	wifi32k: wifi32k {
	compatible = "pwm-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
	};

	hdmi-connector {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_connector_in: endpoint {
	remote-endpoint = <&hdmi_tx_tmds_out>;
	};
	};
	};

	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
	clocks = <&wifi32k>;
	clock-names = "ext_clock";
	};
	};

	&cec_AO {
	status = "okay";
	pinctrl-0 = <&ao_cec_pins>;
	pinctrl-names = "default";
	hdmi-phandle = <&hdmi_tx>;
	};

	&ethmac {
	status = "okay";
	pinctrl-0 = <&eth_rgmii_pins>;
	pinctrl-names = "default";

	phy-handle = <&eth_phy0>;
	phy-mode = "rgmii";

	amlogic,tx-delay-ns = <2>;

	mdio {
	compatible = "snps,dwmac-mdio";
	#address-cells = <1>;
	#size-cells = <0>;

	eth_phy0: ethernet-phy@0 {
	/* Realtek RTL8211F (0x001cc916) */
	reg = <0>;

	reset-assert-us = <10000>;
	reset-deassert-us = <30000>;
	reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;

	interrupt-parent = <&gpio_intc>;
	/* MAC_INTR on GPIOZ_15 */
	interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
	};
	};
	};

	&hdmi_tx {
	status = "okay";
	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
	pinctrl-names = "default";
	};

	&hdmi_tx_tmds_port {
	hdmi_tx_tmds_out: endpoint {
	remote-endpoint = <&hdmi_connector_in>;
	};
	};

	&ir {
	status = "okay";
	pinctrl-0 = <&remote_input_ao_pins>;
	pinctrl-names = "default";
	linux,rc-map-name = "rc-vega-s9x";
	};

	&pwm_ef {
	status = "okay";
	pinctrl-0 = <&pwm_e_pins>;
	pinctrl-names = "default";
	clocks = <&clkc CLKID_FCLK_DIV4>;
	clock-names = "clkin0";
	};

	&saradc {
	status = "okay";
	vref-supply = <&vddio_ao18>;
	};

	/* Wireless SDIO Module */
	&sd_emmc_a {
	status = "okay";
	pinctrl-0 = <&sdio_pins>;
	pinctrl-1 = <&sdio_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";
	#address-cells = <1>;
	#size-cells = <0>;

	bus-width = <4>;
	cap-sd-highspeed;
	max-frequency = <50000000>;

	non-removable;
	disable-wp;

	/* WiFi firmware requires power to be kept while in suspend */
	keep-power-in-suspend;

	mmc-pwrseq = <&sdio_pwrseq>;

	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vddio_boot>;

	brcmf: wifi@1 {
	reg = <1>;
	compatible = "brcm,bcm4329-fmac";
	};
	};

	/* SD card */
	&sd_emmc_b {
	status = "okay";
	pinctrl-0 = <&sdcard_pins>;
	pinctrl-1 = <&sdcard_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <4>;
	cap-sd-highspeed;
	max-frequency = <50000000>;
	disable-wp;

	cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;

	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vcc_3v3>;
	};

	/* eMMC */
	&sd_emmc_c {
	status = "okay";
	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
	pinctrl-1 = <&emmc_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <8>;
	cap-mmc-highspeed;
	max-frequency = <200000000>;
	non-removable;
	disable-wp;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;

	mmc-pwrseq = <&emmc_pwrseq>;
	vmmc-supply = <&vcc_3v3>;
	vqmmc-supply = <&vddio_boot>;
	};

	/* This is connected to the Bluetooth module: */
	&uart_A {
	status = "okay";
	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
	pinctrl-names = "default";

	bluetooth {
	compatible = "brcm,bcm43438-bt";
	shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>;
	+ max-speed = <2000000>;
	+ clocks = <&wifi32k>;
	+ clock-names = "lpo";
	};
	};

	/* This UART is brought out to the DB9 connector */
	&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
	};

	&usb0_phy {
	status = "okay";
	phy-supply = <&usb_pwr>;
	};

	&usb1_phy {
	status = "okay";
	};

	&usb0 {
	status = "okay";
	};

	&usb1 {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-p212.dtsi b/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-p212.dtsi
	index 43eb7d149e36..6ac678f88bd8 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-p212.dtsi
	+++ b/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-p212.dtsi
	@@ -1,200 +1,207 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
	* Based on meson-gx-p23x-q20x.dtsi:
	* - Copyright (c) 2016 Endless Computers, Inc.
	* Author: Carlo Caione <carlo@endlessm.com>
	* - Copyright (c) 2016 BayLibre, SAS.
	* Author: Neil Armstrong <narmstrong@baylibre.com>
	*/

	/* Common DTSI for devices which are based on the P212 reference board. */

	#include "meson-gxl-s905x.dtsi"

	/ {
	aliases {
	serial0 = &uart_AO;
	- serial1 = &uart_A;
	ethernet0 = &ethmac;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@0 {
	device_type = "memory";
	reg = <0x0 0x0 0x0 0x80000000>;
	};

	hdmi_5v: regulator-hdmi-5v {
	compatible = "regulator-fixed";

	regulator-name = "HDMI_5V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;

	gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	regulator-always-on;
	};

	vddio_boot: regulator-vddio_boot {
	compatible = "regulator-fixed";
	regulator-name = "VDDIO_BOOT";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	vddao_3v3: regulator-vddao_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VDDAO_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	vddio_ao18: regulator-vddio_ao18 {
	compatible = "regulator-fixed";
	regulator-name = "VDDIO_AO18";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	vcc_3v3: regulator-vcc_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VCC_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	emmc_pwrseq: emmc-pwrseq {
	compatible = "mmc-pwrseq-emmc";
	reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
	};

	wifi32k: wifi32k {
	compatible = "pwm-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
	};

	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
	clocks = <&wifi32k>;
	clock-names = "ext_clock";
	};
	};

	&ethmac {
	status = "okay";
	};

	&ir {
	status = "okay";
	pinctrl-0 = <&remote_input_ao_pins>;
	pinctrl-names = "default";
	};

	&saradc {
	status = "okay";
	vref-supply = <&vddio_ao18>;
	};

	/* Wireless SDIO Module */
	&sd_emmc_a {
	status = "okay";
	pinctrl-0 = <&sdio_pins>;
	pinctrl-1 = <&sdio_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";
	#address-cells = <1>;
	#size-cells = <0>;

	bus-width = <4>;
	cap-sd-highspeed;
	max-frequency = <50000000>;

	non-removable;
	disable-wp;

	/* WiFi firmware requires power to be kept while in suspend */
	keep-power-in-suspend;

	mmc-pwrseq = <&sdio_pwrseq>;

	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vddio_boot>;
	};

	/* SD card */
	&sd_emmc_b {
	status = "okay";
	pinctrl-0 = <&sdcard_pins>;
	pinctrl-1 = <&sdcard_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <4>;
	cap-sd-highspeed;
	max-frequency = <50000000>;
	disable-wp;

	cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;

	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vddio_boot>;
	};

	/* eMMC */
	&sd_emmc_c {
	status = "okay";
	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
	pinctrl-1 = <&emmc_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <8>;
	cap-mmc-highspeed;
	max-frequency = <200000000>;
	non-removable;
	disable-wp;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;

	mmc-pwrseq = <&emmc_pwrseq>;
	vmmc-supply = <&vcc_3v3>;
	vqmmc-supply = <&vddio_boot>;
	};

	&pwm_ef {
	status = "okay";
	pinctrl-0 = <&pwm_e_pins>;
	pinctrl-names = "default";
	clocks = <&clkc CLKID_FCLK_DIV4>;
	clock-names = "clkin0";
	};

	/* This is connected to the Bluetooth module: */
	&uart_A {
	status = "okay";
	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
	pinctrl-names = "default";
	uart-has-rtscts;
	+
	+ bluetooth {
	+ compatible = "brcm,bcm43438-bt";
	+ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
	+ max-speed = <2000000>;
	+ clocks = <&wifi32k>;
	+ clock-names = "lpo";
	+ };
	};

	&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
	};

	&usb0 {
	status = "okay";
	};

	&usb2_phy0 {
	/*
	* HDMI_5V is also used as supply for the USB VBUS.
	*/
	phy-supply = <&hdmi_5v>;
	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxm-khadas-vim2.dts b/sys/gnu/dts/arm64/amlogic/meson-gxm-khadas-vim2.dts
	index d5dc12878dfe..27eeab71ec77 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-gxm-khadas-vim2.dts
	+++ b/sys/gnu/dts/arm64/amlogic/meson-gxm-khadas-vim2.dts
	@@ -1,442 +1,385 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
	* Copyright (c) 2017 BayLibre, SAS
	* Author: Neil Armstrong <narmstrong@baylibre.com>
	*/

	/dts-v1/;

	#include <dt-bindings/input/input.h>
	-#include <dt-bindings/thermal/thermal.h>

	#include "meson-gxm.dtsi"

	/ {
	compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
	model = "Khadas VIM2";

	aliases {
	serial0 = &uart_AO;
	serial2 = &uart_AO_B;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@0 {
	device_type = "memory";
	reg = <0x0 0x0 0x0 0x80000000>;
	};

	adc-keys {
	compatible = "adc-keys";
	io-channels = <&saradc 0>;
	io-channel-names = "buttons";
	keyup-threshold-microvolt = <1710000>;

	button-function {
	label = "Function";
	linux,code = <KEY_FN>;
	press-threshold-microvolt = <10000>;
	};
	};

	emmc_pwrseq: emmc-pwrseq {
	compatible = "mmc-pwrseq-emmc";
	reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
	};

	gpio_fan: gpio-fan {
	compatible = "gpio-fan";
	gpios = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH
	&gpio GPIODV_15 GPIO_ACTIVE_HIGH>;
	/* Dummy RPM values since fan is optional */
	gpio-fan,speed-map = <0 0
	1 1
	2 2
	3 3>;
	#cooling-cells = <2>;
	};

	gpio-keys-polled {
	compatible = "gpio-keys-polled";
	poll-interval = <100>;

	power-button {
	label = "power";
	linux,code = <KEY_POWER>;
	gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
	};
	};

	hdmi-connector {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_connector_in: endpoint {
	remote-endpoint = <&hdmi_tx_tmds_out>;
	};
	};
	};

	pwmleds {
	compatible = "pwm-leds";

	power {
	label = "vim:red:power";
	pwms = <&pwm_AO_ab 1 7812500 0>;
	max-brightness = <255>;
	linux,default-trigger = "default-on";
	};
	};

	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
	clocks = <&wifi32k>;
	clock-names = "ext_clock";
	};

	- thermal-zones {
	- cpu-thermal {
	- polling-delay-passive = <250>; /* milliseconds */
	- polling-delay = <1000>; /* milliseconds */
	-
	- thermal-sensors = <&scpi_sensors 0>;
	-
	- trips {
	- cpu_alert0: cpu-alert0 {
	- temperature = <70000>; /* millicelsius */
	- hysteresis = <2000>; /* millicelsius */
	- type = "active";
	- };
	-
	- cpu_alert1: cpu-alert1 {
	- temperature = <80000>; /* millicelsius */
	- hysteresis = <2000>; /* millicelsius */
	- type = "passive";
	- };
	- };
	-
	- cooling-maps {
	- map0 {
	- trip = <&cpu_alert0>;
	- cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>;
	- };
	-
	- map1 {
	- trip = <&cpu_alert1>;
	- cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>,
	- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	- <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	- <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	- <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	- <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	- };
	- };
	- };
	- };
	-
	hdmi_5v: regulator-hdmi-5v {
	compatible = "regulator-fixed";

	regulator-name = "HDMI_5V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;

	gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	regulator-always-on;
	};

	vcc_3v3: regulator-vcc_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VCC_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	vddio_ao18: regulator-vddio_ao18 {
	compatible = "regulator-fixed";
	regulator-name = "VDDIO_AO18";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	vddio_boot: regulator-vddio_boot {
	compatible = "regulator-fixed";
	regulator-name = "VDDIO_BOOT";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	vddao_3v3: regulator-vddao_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VDDAO_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	wifi32k: wifi32k {
	compatible = "pwm-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
	};
	};

	&cec_AO {
	status = "okay";
	pinctrl-0 = <&ao_cec_pins>;
	pinctrl-names = "default";
	hdmi-phandle = <&hdmi_tx>;
	};

	-&cpu0 {
	- #cooling-cells = <2>;
	-};
	-
	-&cpu1 {
	- #cooling-cells = <2>;
	-};
	-
	-&cpu2 {
	- #cooling-cells = <2>;
	-};
	-
	-&cpu3 {
	- #cooling-cells = <2>;
	-};
	-
	-&cpu4 {
	- #cooling-cells = <2>;
	-};

	-&cpu5 {
	- #cooling-cells = <2>;
	-};
	-
	-&cpu6 {
	- #cooling-cells = <2>;
	-};
	+&cpu_cooling_maps {
	+ map0 {
	+ cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>;
	+ };

	-&cpu7 {
	- #cooling-cells = <2>;
	+ map1 {
	+ cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>,
	+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	+ };
	};

	&ethmac {
	pinctrl-0 = <&eth_pins>;
	pinctrl-names = "default";

	/* Select external PHY by default */
	phy-handle = <&external_phy>;

	amlogic,tx-delay-ns = <2>;

	/* External PHY is in RGMII */
	phy-mode = "rgmii";

	status = "okay";
	};

	&external_mdio {
	external_phy: ethernet-phy@0 {
	/* Realtek RTL8211F (0x001cc916) */
	reg = <0>;

	reset-assert-us = <10000>;
	reset-deassert-us = <30000>;
	reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;

	interrupt-parent = <&gpio_intc>;
	/* MAC_INTR on GPIOZ_15 */
	interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
	};
	};

	&hdmi_tx {
	status = "okay";
	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
	pinctrl-names = "default";
	hdmi-supply = <&hdmi_5v>;
	};

	&hdmi_tx_tmds_port {
	hdmi_tx_tmds_out: endpoint {
	remote-endpoint = <&hdmi_connector_in>;
	};
	};

	&i2c_A {
	status = "okay";
	pinctrl-0 = <&i2c_a_pins>;
	pinctrl-names = "default";
	};

	&i2c_B {
	status = "okay";
	pinctrl-0 = <&i2c_b_pins>;
	pinctrl-names = "default";

	rtc: rtc@51 {
	/* has to be enabled manually when a battery is connected: */
	status = "disabled";
	compatible = "haoyu,hym8563";
	reg = <0x51>;
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "xin32k";
	};
	};

	&ir {
	status = "okay";
	pinctrl-0 = <&remote_input_ao_pins>;
	pinctrl-names = "default";
	linux,rc-map-name = "rc-khadas";
	};

	&pwm_AO_ab {
	status = "okay";
	pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
	pinctrl-names = "default";
	clocks = <&clkc CLKID_FCLK_DIV4>;
	clock-names = "clkin0";
	};

	&pwm_ef {
	status = "okay";
	pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>;
	pinctrl-names = "default";
	clocks = <&clkc CLKID_FCLK_DIV4>;
	clock-names = "clkin0";
	};

	&sd_emmc_a {
	status = "okay";
	pinctrl-0 = <&sdio_pins>;
	pinctrl-1 = <&sdio_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";
	#address-cells = <1>;
	#size-cells = <0>;

	bus-width = <4>;
	max-frequency = <60000000>;

	non-removable;
	disable-wp;

	/* WiFi firmware requires power to be kept while in suspend */
	keep-power-in-suspend;

	mmc-pwrseq = <&sdio_pwrseq>;

	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vddio_boot>;

	brcmf: wifi@1 {
	reg = <1>;
	compatible = "brcm,bcm4329-fmac";
	};
	};

	/* SD card */
	&sd_emmc_b {
	status = "okay";
	pinctrl-0 = <&sdcard_pins>;
	pinctrl-1 = <&sdcard_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <4>;
	cap-sd-highspeed;
	max-frequency = <50000000>;
	disable-wp;

	cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;

	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vddio_boot>;
	};

	/* eMMC */
	&sd_emmc_c {
	status = "okay";
	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
	pinctrl-1 = <&emmc_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <8>;
	cap-mmc-highspeed;
	max-frequency = <200000000>;
	non-removable;
	disable-wp;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;

	mmc-pwrseq = <&emmc_pwrseq>;
	vmmc-supply = <&vcc_3v3>;
	vqmmc-supply = <&vddio_boot>;
	};

	/*
	* EMMC_DS pin is shared between SPI NOR CS and eMMC Data Strobe
	* Remove emmc_ds_pins from sd_emmc_c pinctrl-0 then spifc can be enabled
	*/
	&spifc {
	status = "disabled";
	pinctrl-0 = <&nor_pins>;
	pinctrl-names = "default";

	w25q32: spi-flash@0 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "winbond,w25q16", "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <3000000>;
	};
	};

	/* This one is connected to the Bluetooth module */
	&uart_A {
	status = "okay";
	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
	pinctrl-names = "default";
	uart-has-rtscts;

	bluetooth {
	compatible = "brcm,bcm43438-bt";
	shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
	max-speed = <2000000>;
	clocks = <&wifi32k>;
	clock-names = "lpo";
	};
	};

	/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */
	&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
	};

	/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */
	&uart_AO_B {
	status = "okay";
	pinctrl-0 = <&uart_ao_b_pins>;
	pinctrl-names = "default";
	};

	&saradc {
	status = "okay";
	vref-supply = <&vddio_ao18>;
	};

	&usb0 {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxm.dtsi b/sys/gnu/dts/arm64/amlogic/meson-gxm.dtsi
	index 5ff64a0d2dcf..b6f89f108e28 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-gxm.dtsi
	+++ b/sys/gnu/dts/arm64/amlogic/meson-gxm.dtsi
	@@ -1,150 +1,178 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2016 Endless Computers, Inc.
	* Author: Carlo Caione <carlo@endlessm.com>
	*/

	#include "meson-gxl.dtsi"

	/ {
	compatible = "amlogic,meson-gxm";

	cpus {
	cpu-map {
	cluster0 {
	core0 {
	cpu = <&cpu0>;
	};
	core1 {
	cpu = <&cpu1>;
	};
	core2 {
	cpu = <&cpu2>;
	};
	core3 {
	cpu = <&cpu3>;
	};
	};

	cluster1 {
	core0 {
	cpu = <&cpu4>;
	};
	core1 {
	cpu = <&cpu5>;
	};
	core2 {
	cpu = <&cpu6>;
	};
	core3 {
	cpu = <&cpu7>;
	};
	};
	};

	cpu4: cpu@100 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x100>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	clocks = <&scpi_dvfs 1>;
	+ #cooling-cells = <2>;
	};

	cpu5: cpu@101 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x101>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	clocks = <&scpi_dvfs 1>;
	+ #cooling-cells = <2>;
	};

	cpu6: cpu@102 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x102>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	clocks = <&scpi_dvfs 1>;
	+ #cooling-cells = <2>;
	};

	cpu7: cpu@103 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x103>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	clocks = <&scpi_dvfs 1>;
	+ #cooling-cells = <2>;
	};
	};
	};

	&apb {
	usb2_phy2: phy@78040 {
	compatible = "amlogic,meson-gxl-usb2-phy";
	#phy-cells = <0>;
	reg = <0x0 0x78040 0x0 0x20>;
	clocks = <&clkc CLKID_USB>;
	clock-names = "phy";
	resets = <&reset RESET_USB_OTG>;
	reset-names = "phy";
	status = "okay";
	};

	mali: gpu@c0000 {
	compatible = "amlogic,meson-gxm-mali", "arm,mali-t820";
	reg = <0x0 0xc0000 0x0 0x40000>;
	interrupt-parent = <&gic>;
	interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "job", "mmu", "gpu";
	clocks = <&clkc CLKID_MALI>;
	resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>;

	/*
	* Mali clocking is provided by two identical clock paths
	* MALI_0 and MALI_1 muxed to a single clock by a glitch
	* free mux to safely change frequency while running.
	*/
	assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
	<&clkc CLKID_MALI_0>,
	<&clkc CLKID_MALI>; /* Glitch free mux */
	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
	<0>, /* Do Nothing */
	<&clkc CLKID_MALI_0>;
	assigned-clock-rates = <0>, /* Do Nothing */
	<666666666>,
	<0>; /* Do Nothing */
	};
	};

	&clkc_AO {
	compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc";
	};

	+&cpu_cooling_maps {
	+ map0 {
	+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	+ };
	+
	+ map1 {
	+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	+ };
	+};
	+
	&saradc {
	compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc";
	};

	&scpi_dvfs {
	clock-indices = <0 1>;
	clock-output-names = "vbig", "vlittle";
	};

	&vpu {
	compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu";
	};

	&hdmi_tx {
	compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
	};

	&dwc3 {
	phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
	};

	&vdec {
	compatible = "amlogic,gxm-vdec", "amlogic,gx-vdec";
	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-khadas-vim3.dtsi b/sys/gnu/dts/arm64/amlogic/meson-khadas-vim3.dtsi
	index 90815fa25ec6..094ecf2222bb 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-khadas-vim3.dtsi
	+++ b/sys/gnu/dts/arm64/amlogic/meson-khadas-vim3.dtsi
	@@ -1,367 +1,385 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2019 BayLibre, SAS
	* Author: Neil Armstrong <narmstrong@baylibre.com>
	* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
	*/

	#include <dt-bindings/input/input.h>
	#include <dt-bindings/gpio/meson-g12a-gpio.h>

	/ {
	- model = "Khadas VIM3";
	-
	aliases {
	serial0 = &uart_AO;
	ethernet0 = &ethmac;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@0 {
	device_type = "memory";
	reg = <0x0 0x0 0x0 0x80000000>;
	};

	adc-keys {
	compatible = "adc-keys";
	io-channels = <&saradc 2>;
	io-channel-names = "buttons";
	keyup-threshold-microvolt = <1710000>;

	button-function {
	label = "Function";
	linux,code = <KEY_FN>;
	press-threshold-microvolt = <10000>;
	};
	};

	leds {
	compatible = "gpio-leds";

	white {
	label = "vim3:white:sys";
	gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
	linux,default-trigger = "heartbeat";
	};

	red {
	label = "vim3:red";
	gpios = <&gpio_expander 5 GPIO_ACTIVE_LOW>;
	};
	};

	emmc_pwrseq: emmc-pwrseq {
	compatible = "mmc-pwrseq-emmc";
	reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
	};

	gpio-keys-polled {
	compatible = "gpio-keys-polled";
	poll-interval = <100>;

	power-button {
	label = "power";
	linux,code = <KEY_POWER>;
	gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>;
	};
	};

	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
	clocks = <&wifi32k>;
	clock-names = "ext_clock";
	};

	dc_in: regulator-dc_in {
	compatible = "regulator-fixed";
	regulator-name = "DC_IN";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	vcc_5v: regulator-vcc_5v {
	compatible = "regulator-fixed";
	regulator-name = "VCC_5V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&dc_in>;

	gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
	enable-active-high;
	};

	vcc_1v8: regulator-vcc_1v8 {
	compatible = "regulator-fixed";
	regulator-name = "VCC_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vcc_3v3>;
	regulator-always-on;
	};

	vcc_3v3: regulator-vcc_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VCC_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vsys_3v3>;
	regulator-always-on;
	/* FIXME: actually controlled by VDDCPU_B_EN */
	};

	vddao_1v8: regulator-vddao_1v8 {
	compatible = "regulator-fixed";
	regulator-name = "VDDIO_AO1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vsys_3v3>;
	regulator-always-on;
	};

	emmc_1v8: regulator-emmc_1v8 {
	compatible = "regulator-fixed";
	regulator-name = "EMMC_AO1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vcc_3v3>;
	regulator-always-on;
	};

	vsys_3v3: regulator-vsys_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VSYS_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&dc_in>;
	regulator-always-on;
	};

	usb_pwr: regulator-usb_pwr {
	compatible = "regulator-fixed";
	regulator-name = "USB_PWR";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&vcc_5v>;

	gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	hdmi-connector {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_connector_in: endpoint {
	remote-endpoint = <&hdmi_tx_tmds_out>;
	};
	};
	};

	wifi32k: wifi32k {
	compatible = "pwm-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
	};
	};

	&cec_AO {
	pinctrl-0 = <&cec_ao_a_h_pins>;
	pinctrl-names = "default";
	status = "disabled";
	hdmi-phandle = <&hdmi_tx>;
	};

	&cecb_AO {
	pinctrl-0 = <&cec_ao_b_h_pins>;
	pinctrl-names = "default";
	status = "okay";
	hdmi-phandle = <&hdmi_tx>;
	};

	&ext_mdio {
	external_phy: ethernet-phy@0 {
	/* Realtek RTL8211F (0x001cc916) */
	reg = <0>;
	max-speed = <1000>;

	interrupt-parent = <&gpio_intc>;
	/* MAC_INTR on GPIOZ_14 */
	interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
	};
	};

	&ethmac {
	pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
	pinctrl-names = "default";
	status = "okay";
	phy-mode = "rgmii";
	phy-handle = <&external_phy>;
	amlogic,tx-delay-ns = <2>;
	};

	&hdmi_tx {
	status = "okay";
	pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
	pinctrl-names = "default";
	hdmi-supply = <&vcc_5v>;
	};

	&hdmi_tx_tmds_port {
	hdmi_tx_tmds_out: endpoint {
	remote-endpoint = <&hdmi_connector_in>;
	};
	};

	&i2c_AO {
	status = "okay";
	pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>;
	pinctrl-names = "default";

	gpio_expander: gpio-controller@20 {
	compatible = "ti,tca6408";
	reg = <0x20>;
	vcc-supply = <&vcc_3v3>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	rtc@51 {
	compatible = "haoyu,hym8563";
	reg = <0x51>;
	#clock-cells = <0>;
	};
	};

	&ir {
	status = "okay";
	pinctrl-0 = <&remote_input_ao_pins>;
	pinctrl-names = "default";
	linux,rc-map-name = "rc-khadas";
	};

	&pcie {
	reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>;
	};

	&pwm_ef {
	status = "okay";
	pinctrl-0 = <&pwm_e_pins>;
	pinctrl-names = "default";
	};

	&saradc {
	status = "okay";
	vref-supply = <&vddao_1v8>;
	};

	/* SDIO */
	&sd_emmc_a {
	status = "okay";
	pinctrl-0 = <&sdio_pins>;
	pinctrl-1 = <&sdio_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";
	#address-cells = <1>;
	#size-cells = <0>;

	bus-width = <4>;
	cap-sd-highspeed;
	sd-uhs-sdr50;
	max-frequency = <100000000>;

	non-removable;
	disable-wp;

	/* WiFi firmware requires power to be kept while in suspend */
	keep-power-in-suspend;

	mmc-pwrseq = <&sdio_pwrseq>;

	vmmc-supply = <&vsys_3v3>;
	vqmmc-supply = <&vddao_1v8>;

	brcmf: wifi@1 {
	reg = <1>;
	compatible = "brcm,bcm4329-fmac";
	};
	};

	/* SD card */
	&sd_emmc_b {
	status = "okay";
	pinctrl-0 = <&sdcard_c_pins>;
	pinctrl-1 = <&sdcard_clk_gate_c_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <4>;
	cap-sd-highspeed;
	max-frequency = <50000000>;
	disable-wp;

	cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&vsys_3v3>;
	vqmmc-supply = <&vsys_3v3>;
	};

	/* eMMC */
	&sd_emmc_c {
	status = "okay";
	- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
	+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
	pinctrl-1 = <&emmc_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <8>;
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	max-frequency = <200000000>;
	disable-wp;

	mmc-pwrseq = <&emmc_pwrseq>;
	vmmc-supply = <&vcc_3v3>;
	vqmmc-supply = <&emmc_1v8>;
	};

	+/*
	+ * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR CS
	+ * and eMMC Data 4 to 7 pins.
	+ * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,
	+ * and change bus-width to 4 then spifc can be enabled.
	+ */
	+&spifc {
	+ status = "disabled";
	+ pinctrl-0 = <&nor_pins>;
	+ pinctrl-names = "default";
	+
	+ w25q32: spi-flash@0 {
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ compatible = "winbond,w25q128fw", "jedec,spi-nor";
	+ reg = <0>;
	+ spi-max-frequency = <104000000>;
	+ };
	+};
	+
	&uart_A {
	status = "okay";
	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
	pinctrl-names = "default";
	uart-has-rtscts;

	bluetooth {
	compatible = "brcm,bcm43438-bt";
	shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
	max-speed = <2000000>;
	clocks = <&wifi32k>;
	clock-names = "lpo";
	};
	};

	&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
	};

	&usb2_phy0 {
	phy-supply = <&dc_in>;
	};

	&usb2_phy1 {
	phy-supply = <&usb_pwr>;
	};

	&usb3_pcie_phy {
	phy-supply = <&usb_pwr>;
	};

	&usb {
	status = "okay";
	dr_mode = "peripheral";
	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-sm1-sei610.dts b/sys/gnu/dts/arm64/amlogic/meson-sm1-sei610.dts
	index cb1b48f5b8b1..dfb2438851c0 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-sm1-sei610.dts
	+++ b/sys/gnu/dts/arm64/amlogic/meson-sm1-sei610.dts
	@@ -1,616 +1,616 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2019 BayLibre SAS. All rights reserved.
	*/

	/dts-v1/;

	#include "meson-sm1.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/gpio/meson-g12a-gpio.h>
	#include <dt-bindings/sound/meson-g12a-tohdmitx.h>

	/ {
	compatible = "seirobotics,sei610", "amlogic,sm1";
	model = "SEI Robotics SEI610";

	aliases {
	serial0 = &uart_AO;
	ethernet0 = &ethmac;
	};

	mono_dac: audio-codec-0 {
	compatible = "maxim,max98357a";
	#sound-dai-cells = <0>;
	sound-name-prefix = "U16";
	sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>;
	};

	dmics: audio-codec-1 {
	#sound-dai-cells = <0>;
	compatible = "dmic-codec";
	num-channels = <2>;
	wakeup-delay-ms = <50>;
	status = "okay";
	sound-name-prefix = "MIC";
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	emmc_pwrseq: emmc-pwrseq {
	compatible = "mmc-pwrseq-emmc";
	reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
	};

	gpio-keys {
	compatible = "gpio-keys";

	key1 {
	label = "A";
	linux,code = <BTN_0>;
	gpios = <&gpio GPIOH_6 GPIO_ACTIVE_LOW>;
	interrupt-parent = <&gpio_intc>;
	interrupts = <34 IRQ_TYPE_EDGE_BOTH>;
	};

	key2 {
	label = "B";
	linux,code = <BTN_1>;
	gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>;
	interrupt-parent = <&gpio_intc>;
	interrupts = <35 IRQ_TYPE_EDGE_BOTH>;
	};

	key3 {
	label = "C";
	linux,code = <BTN_2>;
	gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
	interrupt-parent = <&gpio_intc>;
	interrupts = <2 IRQ_TYPE_EDGE_BOTH>;
	};

	mic_mute {
	label = "MicMute";
	linux,code = <SW_MUTE_DEVICE>;
	linux,input-type = <EV_SW>;
	gpios = <&gpio_ao GPIOE_2 GPIO_ACTIVE_LOW>;
	interrupt-parent = <&gpio_intc>;
	interrupts = <99 IRQ_TYPE_EDGE_BOTH>;
	};

	power_key {
	label = "PowerKey";
	linux,code = <KEY_POWER>;
	gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
	interrupt-parent = <&gpio_intc>;
	interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
	};
	};

	hdmi-connector {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_connector_in: endpoint {
	remote-endpoint = <&hdmi_tx_tmds_out>;
	};
	};
	};

	leds {
	compatible = "gpio-leds";

	bluetooth {
	label = "sei610:blue:bt";
	gpios = <&gpio GPIOC_7 (GPIO_ACTIVE_LOW \| GPIO_OPEN_DRAIN)>;
	default-state = "off";
	};
	};

	pwmleds {
	compatible = "pwm-leds";

	power {
	label = "sei610:red:power";
	pwms = <&pwm_AO_ab 0 30518 0>;
	max-brightness = <255>;
	linux,default-trigger = "default-on";
	active-low;
	};
	};

	memory@0 {
	device_type = "memory";
	reg = <0x0 0x0 0x0 0x40000000>;
	};

	ao_5v: regulator-ao_5v {
	compatible = "regulator-fixed";
	regulator-name = "AO_5V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&dc_in>;
	regulator-always-on;
	};

	dc_in: regulator-dc_in {
	compatible = "regulator-fixed";
	regulator-name = "DC_IN";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	emmc_1v8: regulator-emmc_1v8 {
	compatible = "regulator-fixed";
	regulator-name = "EMMC_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vddao_3v3>;
	regulator-always-on;
	};

	vddao_3v3: regulator-vddao_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "VDDAO_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&dc_in>;
	regulator-always-on;
	};

	/* Used by Tuner, RGB Led & IR Emitter LED array */
	vddao_3v3_t: regulator-vddao_3v3_t {
	compatible = "regulator-fixed";
	regulator-name = "VDDAO_3V3_T";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vddao_3v3>;
	gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
	enable-active-low;
	regulator-always-on;
	};

	vddcpu: regulator-vddcpu {
	/*
	* SY8120B1ABC DC/DC Regulator.
	*/
	compatible = "pwm-regulator";

	regulator-name = "VDDCPU";
	regulator-min-microvolt = <690000>;
	regulator-max-microvolt = <1050000>;

	vin-supply = <&dc_in>;

	pwms = <&pwm_AO_cd 1 1500 0>;
	pwm-dutycycle-range = <100 0>;

	regulator-boot-on;
	regulator-always-on;
	};

	vddio_ao1v8: regulator-vddio_ao1v8 {
	compatible = "regulator-fixed";
	regulator-name = "VDDIO_AO1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vddao_3v3>;
	regulator-always-on;
	};

	reserved-memory {
	/* TEE Reserved Memory */
	bl32_reserved: bl32@5000000 {
	reg = <0x0 0x05300000 0x0 0x2000000>;
	no-map;
	};
	};

	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
	clocks = <&wifi32k>;
	clock-names = "ext_clock";
	};

	sound {
	compatible = "amlogic,axg-sound-card";
	model = "SM1-SEI610";
	audio-aux-devs = <&tdmout_a>, <&tdmout_b>,
	<&tdmin_a>, <&tdmin_b>;
	audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
	"TDMOUT_A IN 1", "FRDDR_B OUT 0",
	"TDMOUT_A IN 2", "FRDDR_C OUT 0",
	"TDM_A Playback", "TDMOUT_A OUT",
	"TDMOUT_B IN 0", "FRDDR_A OUT 1",
	"TDMOUT_B IN 1", "FRDDR_B OUT 1",
	"TDMOUT_B IN 2", "FRDDR_C OUT 1",
	"TDM_B Playback", "TDMOUT_B OUT",
	"TODDR_A IN 4", "PDM Capture",
	"TODDR_B IN 4", "PDM Capture",
	"TODDR_C IN 4", "PDM Capture",
	"TDMIN_A IN 0", "TDM_A Capture",
	"TDMIN_A IN 3", "TDM_A Loopback",
	"TDMIN_B IN 0", "TDM_A Capture",
	"TDMIN_B IN 3", "TDM_A Loopback",
	"TDMIN_A IN 1", "TDM_B Capture",
	"TDMIN_A IN 4", "TDM_B Loopback",
	"TDMIN_B IN 1", "TDM_B Capture",
	"TDMIN_B IN 4", "TDM_B Loopback",
	"TODDR_A IN 0", "TDMIN_A OUT",
	"TODDR_B IN 0", "TDMIN_A OUT",
	"TODDR_C IN 0", "TDMIN_A OUT",
	"TODDR_A IN 1", "TDMIN_B OUT",
	"TODDR_B IN 1", "TDMIN_B OUT",
	"TODDR_C IN 1", "TDMIN_B OUT";

	assigned-clocks = <&clkc CLKID_MPLL2>,
	<&clkc CLKID_MPLL0>,
	<&clkc CLKID_MPLL1>;
	assigned-clock-parents = <0>, <0>, <0>;
	assigned-clock-rates = <294912000>,
	<270950400>,
	<393216000>;
	status = "okay";

	dai-link-0 {
	sound-dai = <&frddr_a>;
	};

	dai-link-1 {
	sound-dai = <&frddr_b>;
	};

	dai-link-2 {
	sound-dai = <&frddr_c>;
	};

	dai-link-3 {
	sound-dai = <&toddr_a>;
	};

	dai-link-4 {
	sound-dai = <&toddr_b>;
	};

	dai-link-5 {
	sound-dai = <&toddr_c>;
	};

	/* internal speaker interface */
	dai-link-6 {
	sound-dai = <&tdmif_a>;
	dai-format = "i2s";
	dai-tdm-slot-tx-mask-0 = <1 1>;
	mclk-fs = <256>;

	codec-0 {
	sound-dai = <&mono_dac>;
	};

	codec-1 {
	sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
	};
	};

	/* 8ch hdmi interface */
	dai-link-7 {
	sound-dai = <&tdmif_b>;
	dai-format = "i2s";
	dai-tdm-slot-tx-mask-0 = <1 1>;
	dai-tdm-slot-tx-mask-1 = <1 1>;
	dai-tdm-slot-tx-mask-2 = <1 1>;
	dai-tdm-slot-tx-mask-3 = <1 1>;
	mclk-fs = <256>;

	codec {
	sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
	};
	};

	/* internal digital mics */
	dai-link-8 {
	sound-dai = <&pdm>;

	codec {
	sound-dai = <&dmics>;
	};
	};

	/* hdmi glue */
	dai-link-9 {
	sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;

	codec {
	sound-dai = <&hdmi_tx>;
	};
	};
	};

	wifi32k: wifi32k {
	compatible = "pwm-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
	};
	};

	&arb {
	status = "okay";
	};

	&cec_AO {
	pinctrl-0 = <&cec_ao_a_h_pins>;
	pinctrl-names = "default";
	status = "disabled";
	hdmi-phandle = <&hdmi_tx>;
	};

	&cecb_AO {
	pinctrl-0 = <&cec_ao_b_h_pins>;
	pinctrl-names = "default";
	status = "okay";
	hdmi-phandle = <&hdmi_tx>;
	};

	&clkc_audio {
	status = "okay";
	};

	&cpu0 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
	};

	&cpu1 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU1_CLK>;
	clock-latency = <50000>;
	};

	&cpu2 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU2_CLK>;
	clock-latency = <50000>;
	};

	&cpu3 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU3_CLK>;
	clock-latency = <50000>;
	};

	&ethmac {
	status = "okay";
	phy-handle = <&internal_ephy>;
	phy-mode = "rmii";
	};

	&frddr_a {
	status = "okay";
	};

	&frddr_b {
	status = "okay";
	};

	&frddr_c {
	status = "okay";
	};

	&hdmi_tx {
	status = "okay";
	pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
	pinctrl-names = "default";
	};

	&hdmi_tx_tmds_port {
	hdmi_tx_tmds_out: endpoint {
	remote-endpoint = <&hdmi_connector_in>;
	};
	};

	&i2c3 {
	status = "okay";
	pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
	pinctrl-names = "default";
	};

	&ir {
	status = "okay";
	pinctrl-0 = <&remote_input_ao_pins>;
	pinctrl-names = "default";
	};

	&pdm {
	pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_dclk_z_pins>;
	pinctrl-names = "default";
	status = "okay";
	};

	&pwm_AO_ab {
	status = "okay";
	pinctrl-0 = <&pwm_ao_a_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>;
	clock-names = "clkin0";
	};

	&pwm_AO_cd {
	pinctrl-0 = <&pwm_ao_d_e_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>;
	clock-names = "clkin1";
	status = "okay";
	};

	&pwm_ef {
	status = "okay";
	pinctrl-0 = <&pwm_e_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>;
	clock-names = "clkin0";
	};

	&saradc {
	status = "okay";
	vref-supply = <&vddio_ao1v8>;
	};

	/* SDIO */
	&sd_emmc_a {
	status = "okay";
	pinctrl-0 = <&sdio_pins>;
	pinctrl-1 = <&sdio_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";
	#address-cells = <1>;
	#size-cells = <0>;

	bus-width = <4>;
	cap-sd-highspeed;
	sd-uhs-sdr50;
	max-frequency = <100000000>;

	non-removable;
	disable-wp;

	/* WiFi firmware requires power to be kept while in suspend */
	keep-power-in-suspend;

	mmc-pwrseq = <&sdio_pwrseq>;

	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vddio_ao1v8>;

	brcmf: wifi@1 {
	reg = <1>;
	compatible = "brcm,bcm4329-fmac";
	};
	};

	/* SD card */
	&sd_emmc_b {
	status = "okay";
	pinctrl-0 = <&sdcard_c_pins>;
	pinctrl-1 = <&sdcard_clk_gate_c_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <4>;
	cap-sd-highspeed;
	max-frequency = <50000000>;
	disable-wp;

	cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vddao_3v3>;
	};

	/* eMMC */
	&sd_emmc_c {
	status = "okay";
	- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
	+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
	pinctrl-1 = <&emmc_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <8>;
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	max-frequency = <200000000>;
	non-removable;
	disable-wp;

	mmc-pwrseq = <&emmc_pwrseq>;
	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&emmc_1v8>;
	};

	&tdmif_a {
	pinctrl-0 = <&tdm_a_dout0_pins>, <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>;
	pinctrl-names = "default";
	status = "okay";

	assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD0>,
	<&clkc_audio AUD_CLKID_TDM_LRCLK_PAD0>;
	assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_A_SCLK>,
	<&clkc_audio AUD_CLKID_MST_A_LRCLK>;
	assigned-clock-rates = <0>, <0>;
	};

	&tdmif_b {
	status = "okay";
	};

	&tdmin_a {
	status = "okay";
	};

	&tdmin_b {
	status = "okay";
	};

	&tdmout_a {
	status = "okay";
	};

	&tdmout_b {
	status = "okay";
	};

	&toddr_a {
	status = "okay";
	};

	&toddr_b {
	status = "okay";
	};

	&toddr_c {
	status = "okay";
	};

	&tohdmitx {
	status = "okay";
	};

	&uart_A {
	status = "okay";
	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
	pinctrl-names = "default";
	uart-has-rtscts;

	bluetooth {
	compatible = "brcm,bcm43438-bt";
	interrupt-parent = <&gpio_intc>;
	interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "host-wakeup";
	shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
	max-speed = <2000000>;
	clocks = <&wifi32k>;
	clock-names = "lpo";
	vbat-supply = <&vddao_3v3>;
	vddio-supply = <&vddio_ao1v8>;
	};
	};

	/* Exposed via the on-board USB to Serial FT232RL IC */
	&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
	};

	&usb {
	status = "okay";
	dr_mode = "otg";
	};
	diff --git a/sys/gnu/dts/arm64/amlogic/meson-sm1.dtsi b/sys/gnu/dts/arm64/amlogic/meson-sm1.dtsi
	index d847a3fcbc85..d4ec735fb1a5 100644
	--- a/sys/gnu/dts/arm64/amlogic/meson-sm1.dtsi
	+++ b/sys/gnu/dts/arm64/amlogic/meson-sm1.dtsi
	@@ -1,503 +1,504 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2019 BayLibre, SAS
	* Author: Neil Armstrong <narmstrong@baylibre.com>
	*/

	#include "meson-g12-common.dtsi"
	#include <dt-bindings/clock/axg-audio-clkc.h>
	#include <dt-bindings/power/meson-sm1-power.h>
	#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
	#include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>

	/ {
	compatible = "amlogic,sm1";

	tdmif_a: audio-controller-0 {
	compatible = "amlogic,axg-tdm-iface";
	#sound-dai-cells = <0>;
	sound-name-prefix = "TDM_A";
	clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
	<&clkc_audio AUD_CLKID_MST_A_SCLK>,
	<&clkc_audio AUD_CLKID_MST_A_LRCLK>;
	clock-names = "mclk", "sclk", "lrclk";
	status = "disabled";
	};

	tdmif_b: audio-controller-1 {
	compatible = "amlogic,axg-tdm-iface";
	#sound-dai-cells = <0>;
	sound-name-prefix = "TDM_B";
	clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
	<&clkc_audio AUD_CLKID_MST_B_SCLK>,
	<&clkc_audio AUD_CLKID_MST_B_LRCLK>;
	clock-names = "mclk", "sclk", "lrclk";
	status = "disabled";
	};

	tdmif_c: audio-controller-2 {
	compatible = "amlogic,axg-tdm-iface";
	#sound-dai-cells = <0>;
	sound-name-prefix = "TDM_C";
	clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
	<&clkc_audio AUD_CLKID_MST_C_SCLK>,
	<&clkc_audio AUD_CLKID_MST_C_LRCLK>;
	clock-names = "mclk", "sclk", "lrclk";
	status = "disabled";
	};

	cpus {
	#address-cells = <0x2>;
	#size-cells = <0x0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a55";
	reg = <0x0 0x0>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a55";
	reg = <0x0 0x1>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	};

	cpu2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a55";
	reg = <0x0 0x2>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	};

	cpu3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a55";
	reg = <0x0 0x3>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	};

	l2: l2-cache0 {
	compatible = "cache";
	};
	};

	cpu_opp_table: opp-table {
	compatible = "operating-points-v2";
	opp-shared;

	opp-100000000 {
	opp-hz = /bits/ 64 <100000000>;
	opp-microvolt = <730000>;
	};

	opp-250000000 {
	opp-hz = /bits/ 64 <250000000>;
	opp-microvolt = <730000>;
	};

	opp-500000000 {
	opp-hz = /bits/ 64 <500000000>;
	opp-microvolt = <730000>;
	};

	opp-667000000 {
	opp-hz = /bits/ 64 <666666666>;
	opp-microvolt = <750000>;
	};

	opp-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	opp-microvolt = <770000>;
	};

	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	opp-microvolt = <780000>;
	};

	opp-1404000000 {
	opp-hz = /bits/ 64 <1404000000>;
	opp-microvolt = <790000>;
	};

	opp-1512000000 {
	opp-hz = /bits/ 64 <1500000000>;
	opp-microvolt = <800000>;
	};

	opp-1608000000 {
	opp-hz = /bits/ 64 <1608000000>;
	opp-microvolt = <810000>;
	};

	opp-1704000000 {
	opp-hz = /bits/ 64 <1704000000>;
	opp-microvolt = <850000>;
	};

	opp-1800000000 {
	opp-hz = /bits/ 64 <1800000000>;
	opp-microvolt = <900000>;
	};

	opp-1908000000 {
	opp-hz = /bits/ 64 <1908000000>;
	opp-microvolt = <950000>;
	};
	};
	};

	&apb {
	audio: bus@60000 {
	compatible = "simple-bus";
	reg = <0x0 0x60000 0x0 0x1000>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x0 0x0 0x0 0x60000 0x0 0x1000>;

	clkc_audio: clock-controller@0 {
	status = "disabled";
	compatible = "amlogic,sm1-audio-clkc";
	reg = <0x0 0x0 0x0 0xb4>;
	#clock-cells = <1>;
	#reset-cells = <1>;

	clocks = <&clkc CLKID_AUDIO>,
	<&clkc CLKID_MPLL0>,
	<&clkc CLKID_MPLL1>,
	<&clkc CLKID_MPLL2>,
	<&clkc CLKID_MPLL3>,
	<&clkc CLKID_HIFI_PLL>,
	<&clkc CLKID_FCLK_DIV3>,
	<&clkc CLKID_FCLK_DIV4>,
	<&clkc CLKID_FCLK_DIV5>;
	clock-names = "pclk",
	"mst_in0",
	"mst_in1",
	"mst_in2",
	"mst_in3",
	"mst_in4",
	"mst_in5",
	"mst_in6",
	"mst_in7";

	resets = <&reset RESET_AUDIO>;
	};

	toddr_a: audio-controller@100 {
	compatible = "amlogic,sm1-toddr",
	"amlogic,axg-toddr";
	reg = <0x0 0x100 0x0 0x2c>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "TODDR_A";
	interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
	resets = <&arb AXG_ARB_TODDR_A>,
	<&clkc_audio AUD_RESET_TODDR_A>;
	reset-names = "arb", "rst";
	amlogic,fifo-depth = <8192>;
	status = "disabled";
	};

	toddr_b: audio-controller@140 {
	compatible = "amlogic,sm1-toddr",
	"amlogic,axg-toddr";
	reg = <0x0 0x140 0x0 0x2c>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "TODDR_B";
	interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
	resets = <&arb AXG_ARB_TODDR_B>,
	<&clkc_audio AUD_RESET_TODDR_B>;
	reset-names = "arb", "rst";
	amlogic,fifo-depth = <256>;
	status = "disabled";
	};

	toddr_c: audio-controller@180 {
	compatible = "amlogic,sm1-toddr",
	"amlogic,axg-toddr";
	reg = <0x0 0x180 0x0 0x2c>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "TODDR_C";
	interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
	resets = <&arb AXG_ARB_TODDR_C>,
	<&clkc_audio AUD_RESET_TODDR_C>;
	reset-names = "arb", "rst";
	amlogic,fifo-depth = <256>;
	status = "disabled";
	};

	frddr_a: audio-controller@1c0 {
	compatible = "amlogic,sm1-frddr",
	"amlogic,axg-frddr";
	reg = <0x0 0x1c0 0x0 0x2c>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "FRDDR_A";
	interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
	resets = <&arb AXG_ARB_FRDDR_A>,
	<&clkc_audio AUD_RESET_FRDDR_A>;
	reset-names = "arb", "rst";
	amlogic,fifo-depth = <512>;
	status = "disabled";
	};

	frddr_b: audio-controller@200 {
	compatible = "amlogic,sm1-frddr",
	"amlogic,axg-frddr";
	reg = <0x0 0x200 0x0 0x2c>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "FRDDR_B";
	interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
	resets = <&arb AXG_ARB_FRDDR_B>,
	<&clkc_audio AUD_RESET_FRDDR_B>;
	reset-names = "arb", "rst";
	amlogic,fifo-depth = <256>;
	status = "disabled";
	};

	frddr_c: audio-controller@240 {
	compatible = "amlogic,sm1-frddr",
	"amlogic,axg-frddr";
	reg = <0x0 0x240 0x0 0x2c>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "FRDDR_C";
	interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
	resets = <&arb AXG_ARB_FRDDR_C>,
	<&clkc_audio AUD_RESET_FRDDR_C>;
	reset-names = "arb", "rst";
	amlogic,fifo-depth = <256>;
	status = "disabled";
	};

	arb: reset-controller@280 {
	status = "disabled";
	compatible = "amlogic,meson-sm1-audio-arb";
	reg = <0x0 0x280 0x0 0x4>;
	#reset-cells = <1>;
	clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
	};

	tdmin_a: audio-controller@300 {
	compatible = "amlogic,sm1-tdmin",
	"amlogic,axg-tdmin";
	reg = <0x0 0x300 0x0 0x40>;
	sound-name-prefix = "TDMIN_A";
	resets = <&clkc_audio AUD_RESET_TDMIN_A>;
	clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
	<&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
	<&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
	<&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
	<&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
	clock-names = "pclk", "sclk", "sclk_sel",
	"lrclk", "lrclk_sel";
	status = "disabled";
	};

	tdmin_b: audio-controller@340 {
	compatible = "amlogic,sm1-tdmin",
	"amlogic,axg-tdmin";
	reg = <0x0 0x340 0x0 0x40>;
	sound-name-prefix = "TDMIN_B";
	resets = <&clkc_audio AUD_RESET_TDMIN_B>;
	clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
	<&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
	<&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
	<&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
	<&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
	clock-names = "pclk", "sclk", "sclk_sel",
	"lrclk", "lrclk_sel";
	status = "disabled";
	};

	tdmin_c: audio-controller@380 {
	compatible = "amlogic,sm1-tdmin",
	"amlogic,axg-tdmin";
	reg = <0x0 0x380 0x0 0x40>;
	sound-name-prefix = "TDMIN_C";
	resets = <&clkc_audio AUD_RESET_TDMIN_C>;
	clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
	<&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
	<&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
	<&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
	<&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
	clock-names = "pclk", "sclk", "sclk_sel",
	"lrclk", "lrclk_sel";
	status = "disabled";
	};

	tdmin_lb: audio-controller@3c0 {
	compatible = "amlogic,sm1-tdmin",
	"amlogic,axg-tdmin";
	reg = <0x0 0x3c0 0x0 0x40>;
	sound-name-prefix = "TDMIN_LB";
	resets = <&clkc_audio AUD_RESET_TDMIN_LB>;
	clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
	<&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
	<&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
	<&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
	<&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
	clock-names = "pclk", "sclk", "sclk_sel",
	"lrclk", "lrclk_sel";
	status = "disabled";
	};

	tdmout_a: audio-controller@500 {
	compatible = "amlogic,sm1-tdmout";
	reg = <0x0 0x500 0x0 0x40>;
	sound-name-prefix = "TDMOUT_A";
	resets = <&clkc_audio AUD_RESET_TDMOUT_A>;
	clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
	<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
	<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
	<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
	<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
	clock-names = "pclk", "sclk", "sclk_sel",
	"lrclk", "lrclk_sel";
	status = "disabled";
	};

	tdmout_b: audio-controller@540 {
	compatible = "amlogic,sm1-tdmout";
	reg = <0x0 0x540 0x0 0x40>;
	sound-name-prefix = "TDMOUT_B";
	resets = <&clkc_audio AUD_RESET_TDMOUT_B>;
	clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
	<&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
	<&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
	<&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
	<&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
	clock-names = "pclk", "sclk", "sclk_sel",
	"lrclk", "lrclk_sel";
	status = "disabled";
	};

	tdmout_c: audio-controller@580 {
	compatible = "amlogic,sm1-tdmout";
	reg = <0x0 0x580 0x0 0x40>;
	sound-name-prefix = "TDMOUT_C";
	resets = <&clkc_audio AUD_RESET_TDMOUT_C>;
	clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
	<&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
	<&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
	<&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
	<&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
	clock-names = "pclk", "sclk", "sclk_sel",
	"lrclk", "lrclk_sel";
	status = "disabled";
	};

	tohdmitx: audio-controller@744 {
	compatible = "amlogic,sm1-tohdmitx",
	"amlogic,g12a-tohdmitx";
	reg = <0x0 0x744 0x0 0x4>;
	#sound-dai-cells = <1>;
	sound-name-prefix = "TOHDMITX";
	resets = <&clkc_audio AUD_RESET_TOHDMITX>;
	status = "disabled";
	};

	toddr_d: audio-controller@840 {
	compatible = "amlogic,sm1-toddr",
	"amlogic,axg-toddr";
	reg = <0x0 0x840 0x0 0x2c>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "TODDR_D";
	interrupts = <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc_audio AUD_CLKID_TODDR_D>;
	resets = <&arb AXG_ARB_TODDR_D>,
	<&clkc_audio AUD_RESET_TODDR_D>;
	reset-names = "arb", "rst";
	amlogic,fifo-depth = <256>;
	status = "disabled";
	};

	frddr_d: audio-controller@880 {
	compatible = "amlogic,sm1-frddr",
	"amlogic,axg-frddr";
	reg = <0x0 0x880 0x0 0x2c>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "FRDDR_D";
	interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clkc_audio AUD_CLKID_FRDDR_D>;
	resets = <&arb AXG_ARB_FRDDR_D>,
	<&clkc_audio AUD_RESET_FRDDR_D>;
	reset-names = "arb", "rst";
	amlogic,fifo-depth = <256>;
	status = "disabled";
	};
	};

	pdm: audio-controller@61000 {
	compatible = "amlogic,sm1-pdm",
	"amlogic,axg-pdm";
	reg = <0x0 0x61000 0x0 0x34>;
	#sound-dai-cells = <0>;
	sound-name-prefix = "PDM";
	clocks = <&clkc_audio AUD_CLKID_PDM>,
	<&clkc_audio AUD_CLKID_PDM_DCLK>,
	<&clkc_audio AUD_CLKID_PDM_SYSCLK>;
	clock-names = "pclk", "dclk", "sysclk";
	+ resets = <&clkc_audio AUD_RESET_PDM>;
	status = "disabled";
	};
	};

	&cecb_AO {
	compatible = "amlogic,meson-sm1-ao-cec";
	};

	&clk_msr {
	compatible = "amlogic,meson-sm1-clk-measure";
	};


	&clkc {
	compatible = "amlogic,sm1-clkc";
	};

	&ethmac {
	power-domains = <&pwrc PWRC_SM1_ETH_ID>;
	};

	&gpio_intc {
	compatible = "amlogic,meson-sm1-gpio-intc",
	"amlogic,meson-gpio-intc";
	};

	&pcie {
	power-domains = <&pwrc PWRC_SM1_PCIE_ID>;
	};

	&pwrc {
	compatible = "amlogic,meson-sm1-pwrc";
	};

	&simplefb_cvbs {
	power-domains = <&pwrc PWRC_SM1_VPU_ID>;
	};

	&simplefb_hdmi {
	power-domains = <&pwrc PWRC_SM1_VPU_ID>;
	};

	&vdec {
	compatible = "amlogic,sm1-vdec";
	};

	&vpu {
	power-domains = <&pwrc PWRC_SM1_VPU_ID>;
	};

	&usb {
	power-domains = <&pwrc PWRC_SM1_USB_ID>;
	};
	diff --git a/sys/gnu/dts/arm64/arm/foundation-v8.dtsi b/sys/gnu/dts/arm64/arm/foundation-v8.dtsi
	index 3f78373f708a..12f039fa3dad 100644
	--- a/sys/gnu/dts/arm64/arm/foundation-v8.dtsi
	+++ b/sys/gnu/dts/arm64/arm/foundation-v8.dtsi
	@@ -1,231 +1,231 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* ARM Ltd.
	*
	* ARMv8 Foundation model DTS
	*/

	/dts-v1/;

	#include <dt-bindings/interrupt-controller/arm-gic.h>

	/memreserve/ 0x80000000 0x00010000;

	/ {
	model = "Foundation-v8A";
	compatible = "arm,foundation-aarch64", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	aliases {
	serial0 = &v2m_serial0;
	serial1 = &v2m_serial1;
	serial2 = &v2m_serial2;
	serial3 = &v2m_serial3;
	};

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x0>;
	next-level-cache = <&L2_0>;
	};
	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x1>;
	next-level-cache = <&L2_0>;
	};
	cpu2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x2>;
	next-level-cache = <&L2_0>;
	};
	cpu3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x3>;
	next-level-cache = <&L2_0>;
	};

	L2_0: l2-cache0 {
	compatible = "cache";
	};
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0x00000000 0x80000000 0 0x80000000>,
	<0x00000008 0x80000000 0 0x80000000>;
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	clock-frequency = <100000000>;
	};

	pmu {
	compatible = "arm,armv8-pmuv3";
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	};

	watchdog@2a440000 {
	compatible = "arm,sbsa-gwdt";
	reg = <0x0 0x2a440000 0 0x1000>,
	<0x0 0x2a450000 0 0x1000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	timeout-sec = <30>;
	};

	- smb@8000000 {
	+ bus@8000000 {
	compatible = "arm,vexpress,v2m-p1", "simple-bus";
	arm,v2m-memory-map = "rs1";
	#address-cells = <2>; /* SMB chipselect number and offset */
	#size-cells = <1>;

	ranges = <0 0 0 0x08000000 0x04000000>,
	<1 0 0 0x14000000 0x04000000>,
	<2 0 0 0x18000000 0x04000000>,
	<3 0 0 0x1c000000 0x04000000>,
	<4 0 0 0x0c000000 0x04000000>,
	<5 0 0 0x10000000 0x04000000>;

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 63>;
	interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;

	ethernet@2,02000000 {
	compatible = "smsc,lan91c111";
	reg = <2 0x02000000 0x10000>;
	interrupts = <15>;
	};

	v2m_clk24mhz: clk24mhz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "v2m:clk24mhz";
	};

	v2m_refclk1mhz: refclk1mhz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <1000000>;
	clock-output-names = "v2m:refclk1mhz";
	};

	v2m_refclk32khz: refclk32khz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "v2m:refclk32khz";
	};

	iofpga@3,00000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 3 0 0x200000>;

	v2m_sysreg: sysreg@10000 {
	compatible = "arm,vexpress-sysreg";
	reg = <0x010000 0x1000>;
	};

	v2m_serial0: uart@90000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x090000 0x1000>;
	interrupts = <5>;
	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
	clock-names = "uartclk", "apb_pclk";
	};

	v2m_serial1: uart@a0000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x0a0000 0x1000>;
	interrupts = <6>;
	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
	clock-names = "uartclk", "apb_pclk";
	};

	v2m_serial2: uart@b0000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x0b0000 0x1000>;
	interrupts = <7>;
	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
	clock-names = "uartclk", "apb_pclk";
	};

	v2m_serial3: uart@c0000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x0c0000 0x1000>;
	interrupts = <8>;
	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
	clock-names = "uartclk", "apb_pclk";
	};

	virtio-block@130000 {
	compatible = "virtio,mmio";
	reg = <0x130000 0x200>;
	interrupts = <42>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/arm/fvp-base-revc.dts b/sys/gnu/dts/arm64/arm/fvp-base-revc.dts
	index 335fff762451..66381d89c1ce 100644
	--- a/sys/gnu/dts/arm64/arm/fvp-base-revc.dts
	+++ b/sys/gnu/dts/arm64/arm/fvp-base-revc.dts
	@@ -1,269 +1,269 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* ARM Ltd. Fast Models
	*
	* Architecture Envelope Model (AEM) ARMv8-A
	* ARMAEMv8AMPCT
	*
	* FVP Base RevC
	*/

	/dts-v1/;

	#include <dt-bindings/interrupt-controller/arm-gic.h>

	/memreserve/ 0x80000000 0x00010000;

	#include "rtsm_ve-motherboard.dtsi"
	#include "rtsm_ve-motherboard-rs2.dtsi"

	/ {
	model = "FVP Base RevC";
	compatible = "arm,fvp-base-revc", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	aliases {
	serial0 = &v2m_serial0;
	serial1 = &v2m_serial1;
	serial2 = &v2m_serial2;
	serial3 = &v2m_serial3;
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x000>;
	enable-method = "psci";
	};
	cpu1: cpu@100 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x100>;
	enable-method = "psci";
	};
	cpu2: cpu@200 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x200>;
	enable-method = "psci";
	};
	cpu3: cpu@300 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x300>;
	enable-method = "psci";
	};
	cpu4: cpu@10000 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x10000>;
	enable-method = "psci";
	};
	cpu5: cpu@10100 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x10100>;
	enable-method = "psci";
	};
	cpu6: cpu@10200 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x10200>;
	enable-method = "psci";
	};
	cpu7: cpu@10300 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x10300>;
	enable-method = "psci";
	};
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0x00000000 0x80000000 0 0x80000000>,
	<0x00000008 0x80000000 0 0x80000000>;
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	/* Chipselect 2,00000000 is physically at 0x18000000 */
	vram: vram@18000000 {
	/* 8 MB of designated video RAM */
	compatible = "shared-dma-pool";
	reg = <0x00000000 0x18000000 0 0x00800000>;
	no-map;
	};
	};

	gic: interrupt-controller@2f000000 {
	compatible = "arm,gic-v3";
	#interrupt-cells = <3>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	interrupt-controller;
	reg = <0x0 0x2f000000 0 0x10000>, // GICD
	<0x0 0x2f100000 0 0x200000>, // GICR
	<0x0 0x2c000000 0 0x2000>, // GICC
	<0x0 0x2c010000 0 0x2000>, // GICH
	<0x0 0x2c02f000 0 0x2000>; // GICV
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

	its: its@2f020000 {
	#msi-cells = <1>;
	compatible = "arm,gic-v3-its";
	reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
	msi-controller;
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	pmu {
	compatible = "arm,armv8-pmuv3";
	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	spe-pmu {
	compatible = "arm,statistical-profiling-extension-v1";
	interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
	};

	pci: pci@40000000 {
	#address-cells = <0x3>;
	#size-cells = <0x2>;
	#interrupt-cells = <0x1>;
	compatible = "pci-host-ecam-generic";
	device_type = "pci";
	bus-range = <0x0 0x1>;
	reg = <0x0 0x40000000 0x0 0x10000000>;
	ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>;
	interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
	msi-map = <0x0 &its 0x0 0x10000>;
	iommu-map = <0x0 &smmu 0x0 0x10000>;

	dma-coherent;
	};

	smmu: smmu@2b400000 {
	compatible = "arm,smmu-v3";
	reg = <0x0 0x2b400000 0x0 0x100000>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
	dma-coherent;
	#iommu-cells = <1>;
	msi-parent = <&its 0x10000>;
	};

	panel {
	compatible = "arm,rtsm-display", "panel-dpi";
	port {
	panel_in: endpoint {
	remote-endpoint = <&clcd_pads>;
	};
	};

	panel-timing {
	clock-frequency = <63500127>;
	hactive = <1024>;
	hback-porch = <152>;
	hfront-porch = <48>;
	hsync-len = <104>;
	vactive = <768>;
	vback-porch = <23>;
	vfront-porch = <3>;
	vsync-len = <4>;
	};
	};

	- smb@8000000 {
	+ bus@8000000 {
	compatible = "simple-bus";

	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0 0x08000000 0x04000000>,
	<1 0 0 0x14000000 0x04000000>,
	<2 0 0 0x18000000 0x04000000>,
	<3 0 0 0x1c000000 0x04000000>,
	<4 0 0 0x0c000000 0x04000000>,
	<5 0 0 0x10000000 0x04000000>;

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 63>;
	interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/arm/juno-base.dtsi b/sys/gnu/dts/arm64/arm/juno-base.dtsi
	index 1f3c80aafbd7..f5889281545f 100644
	--- a/sys/gnu/dts/arm64/arm/juno-base.dtsi
	+++ b/sys/gnu/dts/arm64/arm/juno-base.dtsi
	@@ -1,840 +1,840 @@
	// SPDX-License-Identifier: GPL-2.0
	#include "juno-clocks.dtsi"
	#include "juno-motherboard.dtsi"

	/ {
	/*
	* Devices shared by all Juno boards
	*/

	memtimer: timer@2a810000 {
	compatible = "arm,armv7-timer-mem";
	reg = <0x0 0x2a810000 0x0 0x10000>;
	clock-frequency = <50000000>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "disabled";
	frame@2a830000 {
	frame-number = <1>;
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x0 0x2a830000 0x0 0x10000>;
	};
	};

	mailbox: mhu@2b1f0000 {
	compatible = "arm,mhu", "arm,primecell";
	reg = <0x0 0x2b1f0000 0x0 0x1000>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "mhu_lpri_rx",
	"mhu_hpri_rx";
	#mbox-cells = <1>;
	clocks = <&soc_refclk100mhz>;
	clock-names = "apb_pclk";
	};

	smmu_gpu: iommu@2b400000 {
	compatible = "arm,mmu-400", "arm,smmu-v1";
	reg = <0x0 0x2b400000 0x0 0x10000>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	#global-interrupts = <1>;
	power-domains = <&scpi_devpd 1>;
	dma-coherent;
	status = "disabled";
	};

	smmu_pcie: iommu@2b500000 {
	compatible = "arm,mmu-401", "arm,smmu-v1";
	reg = <0x0 0x2b500000 0x0 0x10000>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	#global-interrupts = <1>;
	dma-coherent;
	status = "disabled";
	};

	smmu_etr: iommu@2b600000 {
	compatible = "arm,mmu-401", "arm,smmu-v1";
	reg = <0x0 0x2b600000 0x0 0x10000>;
	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	#global-interrupts = <1>;
	dma-coherent;
	power-domains = <&scpi_devpd 0>;
	};

	gic: interrupt-controller@2c010000 {
	compatible = "arm,gic-400", "arm,cortex-a15-gic";
	reg = <0x0 0x2c010000 0 0x1000>,
	<0x0 0x2c02f000 0 0x2000>,
	<0x0 0x2c04f000 0 0x2000>,
	<0x0 0x2c06f000 0 0x2000>;
	#address-cells = <2>;
	#interrupt-cells = <3>;
	#size-cells = <2>;
	interrupt-controller;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_HIGH)>;
	ranges = <0 0 0 0x2c1c0000 0 0x40000>;

	v2m_0: v2m@0 {
	compatible = "arm,gic-v2m-frame";
	msi-controller;
	reg = <0 0 0 0x10000>;
	};

	v2m@10000 {
	compatible = "arm,gic-v2m-frame";
	msi-controller;
	reg = <0 0x10000 0 0x10000>;
	};

	v2m@20000 {
	compatible = "arm,gic-v2m-frame";
	msi-controller;
	reg = <0 0x20000 0 0x10000>;
	};

	v2m@30000 {
	compatible = "arm,gic-v2m-frame";
	msi-controller;
	reg = <0 0x30000 0 0x10000>;
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	/*
	* Juno TRMs specify the size for these coresight components as 64K.
	* The actual size is just 4K though 64K is reserved. Access to the
	* unmapped reserved region results in a DECERR response.
	*/
	etf@20010000 { /* etf0 */
	compatible = "arm,coresight-tmc", "arm,primecell";
	reg = <0 0x20010000 0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;

	in-ports {
	port {
	etf0_in_port: endpoint {
	remote-endpoint = <&main_funnel_out_port>;
	};
	};
	};

	out-ports {
	port {
	etf0_out_port: endpoint {
	};
	};
	};
	};

	tpiu@20030000 {
	compatible = "arm,coresight-tpiu", "arm,primecell";
	reg = <0 0x20030000 0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;
	in-ports {
	port {
	tpiu_in_port: endpoint {
	remote-endpoint = <&replicator_out_port0>;
	};
	};
	};
	};

	/* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
	main_funnel: funnel@20040000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0 0x20040000 0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;

	out-ports {
	port {
	main_funnel_out_port: endpoint {
	remote-endpoint = <&etf0_in_port>;
	};
	};
	};

	main_funnel_in_ports: in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	main_funnel_in_port0: endpoint {
	remote-endpoint = <&cluster0_funnel_out_port>;
	};
	};

	port@1 {
	reg = <1>;
	main_funnel_in_port1: endpoint {
	remote-endpoint = <&cluster1_funnel_out_port>;
	};
	};
	};
	};

	etr@20070000 {
	compatible = "arm,coresight-tmc", "arm,primecell";
	reg = <0 0x20070000 0 0x1000>;
	iommus = <&smmu_etr 0>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;
	arm,scatter-gather;
	in-ports {
	port {
	etr_in_port: endpoint {
	remote-endpoint = <&replicator_out_port1>;
	};
	};
	};
	};

	stm@20100000 {
	compatible = "arm,coresight-stm", "arm,primecell";
	reg = <0 0x20100000 0 0x1000>,
	<0 0x28000000 0 0x1000000>;
	reg-names = "stm-base", "stm-stimulus-base";

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;
	out-ports {
	port {
	stm_out_port: endpoint {
	};
	};
	};
	};

	replicator@20120000 {
	compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
	reg = <0 0x20120000 0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;

	out-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	/* replicator output ports */
	port@0 {
	reg = <0>;
	replicator_out_port0: endpoint {
	remote-endpoint = <&tpiu_in_port>;
	};
	};

	port@1 {
	reg = <1>;
	replicator_out_port1: endpoint {
	remote-endpoint = <&etr_in_port>;
	};
	};
	};
	in-ports {
	port {
	replicator_in_port0: endpoint {
	};
	};
	};
	};

	cpu_debug0: cpu-debug@22010000 {
	compatible = "arm,coresight-cpu-debug", "arm,primecell";
	reg = <0x0 0x22010000 0x0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;
	};

	etm0: etm@22040000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0 0x22040000 0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;
	out-ports {
	port {
	cluster0_etm0_out_port: endpoint {
	remote-endpoint = <&cluster0_funnel_in_port0>;
	};
	};
	};
	};

	funnel@220c0000 { /* cluster0 funnel */
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0 0x220c0000 0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;
	out-ports {
	port {
	cluster0_funnel_out_port: endpoint {
	remote-endpoint = <&main_funnel_in_port0>;
	};
	};
	};

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	cluster0_funnel_in_port0: endpoint {
	remote-endpoint = <&cluster0_etm0_out_port>;
	};
	};

	port@1 {
	reg = <1>;
	cluster0_funnel_in_port1: endpoint {
	remote-endpoint = <&cluster0_etm1_out_port>;
	};
	};
	};
	};

	cpu_debug1: cpu-debug@22110000 {
	compatible = "arm,coresight-cpu-debug", "arm,primecell";
	reg = <0x0 0x22110000 0x0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;
	};

	etm1: etm@22140000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0 0x22140000 0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;
	out-ports {
	port {
	cluster0_etm1_out_port: endpoint {
	remote-endpoint = <&cluster0_funnel_in_port1>;
	};
	};
	};
	};

	cpu_debug2: cpu-debug@23010000 {
	compatible = "arm,coresight-cpu-debug", "arm,primecell";
	reg = <0x0 0x23010000 0x0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;
	};

	etm2: etm@23040000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0 0x23040000 0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;
	out-ports {
	port {
	cluster1_etm0_out_port: endpoint {
	remote-endpoint = <&cluster1_funnel_in_port0>;
	};
	};
	};
	};

	funnel@230c0000 { /* cluster1 funnel */
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0 0x230c0000 0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;
	out-ports {
	port {
	cluster1_funnel_out_port: endpoint {
	remote-endpoint = <&main_funnel_in_port1>;
	};
	};
	};

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	cluster1_funnel_in_port0: endpoint {
	remote-endpoint = <&cluster1_etm0_out_port>;
	};
	};

	port@1 {
	reg = <1>;
	cluster1_funnel_in_port1: endpoint {
	remote-endpoint = <&cluster1_etm1_out_port>;
	};
	};
	port@2 {
	reg = <2>;
	cluster1_funnel_in_port2: endpoint {
	remote-endpoint = <&cluster1_etm2_out_port>;
	};
	};
	port@3 {
	reg = <3>;
	cluster1_funnel_in_port3: endpoint {
	remote-endpoint = <&cluster1_etm3_out_port>;
	};
	};
	};
	};

	cpu_debug3: cpu-debug@23110000 {
	compatible = "arm,coresight-cpu-debug", "arm,primecell";
	reg = <0x0 0x23110000 0x0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;
	};

	etm3: etm@23140000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0 0x23140000 0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;
	out-ports {
	port {
	cluster1_etm1_out_port: endpoint {
	remote-endpoint = <&cluster1_funnel_in_port1>;
	};
	};
	};
	};

	cpu_debug4: cpu-debug@23210000 {
	compatible = "arm,coresight-cpu-debug", "arm,primecell";
	reg = <0x0 0x23210000 0x0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;
	};

	etm4: etm@23240000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0 0x23240000 0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;
	out-ports {
	port {
	cluster1_etm2_out_port: endpoint {
	remote-endpoint = <&cluster1_funnel_in_port2>;
	};
	};
	};
	};

	cpu_debug5: cpu-debug@23310000 {
	compatible = "arm,coresight-cpu-debug", "arm,primecell";
	reg = <0x0 0x23310000 0x0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;
	};

	etm5: etm@23340000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0 0x23340000 0 0x1000>;

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	power-domains = <&scpi_devpd 0>;
	out-ports {
	port {
	cluster1_etm3_out_port: endpoint {
	remote-endpoint = <&cluster1_funnel_in_port3>;
	};
	};
	};
	};

	gpu: gpu@2d000000 {
	compatible = "arm,juno-mali", "arm,mali-t624";
	reg = <0 0x2d000000 0 0x10000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gpu", "job", "mmu";
	clocks = <&scpi_dvfs 2>;
	power-domains = <&scpi_devpd 1>;
	dma-coherent;
	/* The SMMU is only really of interest to bare-metal hypervisors */
	/* iommus = <&smmu_gpu 0>; */
	status = "disabled";
	};

	sram: sram@2e000000 {
	compatible = "arm,juno-sram-ns", "mmio-sram";
	reg = <0x0 0x2e000000 0x0 0x8000>;

	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x0 0x2e000000 0x8000>;

	cpu_scp_lpri: scp-shmem@0 {
	compatible = "arm,juno-scp-shmem";
	reg = <0x0 0x200>;
	};

	cpu_scp_hpri: scp-shmem@200 {
	compatible = "arm,juno-scp-shmem";
	reg = <0x200 0x200>;
	};
	};

	pcie_ctlr: pcie@40000000 {
	compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
	device_type = "pci";
	reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
	bus-range = <0 255>;
	linux,pci-domain = <0>;
	#address-cells = <3>;
	#size-cells = <2>;
	dma-coherent;
	ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
	<0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
	<0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 2 &gic 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 3 &gic 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 4 &gic 0 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
	msi-parent = <&v2m_0>;
	status = "disabled";
	iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
	iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
	};

	scpi {
	compatible = "arm,scpi";
	mboxes = <&mailbox 1>;
	shmem = <&cpu_scp_hpri>;

	clocks {
	compatible = "arm,scpi-clocks";

	scpi_dvfs: scpi-dvfs {
	compatible = "arm,scpi-dvfs-clocks";
	#clock-cells = <1>;
	clock-indices = <0>, <1>, <2>;
	clock-output-names = "atlclk", "aplclk","gpuclk";
	};
	scpi_clk: scpi-clk {
	compatible = "arm,scpi-variable-clocks";
	#clock-cells = <1>;
	clock-indices = <3>;
	clock-output-names = "pxlclk";
	};
	};

	scpi_devpd: scpi-power-domains {
	compatible = "arm,scpi-power-domains";
	num-domains = <2>;
	#power-domain-cells = <1>;
	};

	scpi_sensors0: sensors {
	compatible = "arm,scpi-sensors";
	#thermal-sensor-cells = <1>;
	};
	};

	thermal-zones {
	pmic {
	polling-delay = <1000>;
	polling-delay-passive = <100>;
	thermal-sensors = <&scpi_sensors0 0>;
	};

	soc {
	polling-delay = <1000>;
	polling-delay-passive = <100>;
	thermal-sensors = <&scpi_sensors0 3>;
	};

	big_cluster_thermal_zone: big-cluster {
	polling-delay = <1000>;
	polling-delay-passive = <100>;
	thermal-sensors = <&scpi_sensors0 21>;
	status = "disabled";
	};

	little_cluster_thermal_zone: little-cluster {
	polling-delay = <1000>;
	polling-delay-passive = <100>;
	thermal-sensors = <&scpi_sensors0 22>;
	status = "disabled";
	};

	gpu0_thermal_zone: gpu0 {
	polling-delay = <1000>;
	polling-delay-passive = <100>;
	thermal-sensors = <&scpi_sensors0 23>;
	status = "disabled";
	};

	gpu1_thermal_zone: gpu1 {
	polling-delay = <1000>;
	polling-delay-passive = <100>;
	thermal-sensors = <&scpi_sensors0 24>;
	status = "disabled";
	};
	};

	smmu_dma: iommu@7fb00000 {
	compatible = "arm,mmu-401", "arm,smmu-v1";
	reg = <0x0 0x7fb00000 0x0 0x10000>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	#global-interrupts = <1>;
	dma-coherent;
	status = "disabled";
	};

	smmu_hdlcd1: iommu@7fb10000 {
	compatible = "arm,mmu-401", "arm,smmu-v1";
	reg = <0x0 0x7fb10000 0x0 0x10000>;
	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	#global-interrupts = <1>;
	};

	smmu_hdlcd0: iommu@7fb20000 {
	compatible = "arm,mmu-401", "arm,smmu-v1";
	reg = <0x0 0x7fb20000 0x0 0x10000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	#global-interrupts = <1>;
	};

	smmu_usb: iommu@7fb30000 {
	compatible = "arm,mmu-401", "arm,smmu-v1";
	reg = <0x0 0x7fb30000 0x0 0x10000>;
	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	#global-interrupts = <1>;
	dma-coherent;
	};

	dma@7ff00000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x0 0x7ff00000 0 0x1000>;
	#dma-cells = <1>;
	#dma-channels = <8>;
	#dma-requests = <32>;
	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
	iommus = <&smmu_dma 0>,
	<&smmu_dma 1>,
	<&smmu_dma 2>,
	<&smmu_dma 3>,
	<&smmu_dma 4>,
	<&smmu_dma 5>,
	<&smmu_dma 6>,
	<&smmu_dma 7>,
	<&smmu_dma 8>;
	clocks = <&soc_faxiclk>;
	clock-names = "apb_pclk";
	};

	hdlcd@7ff50000 {
	compatible = "arm,hdlcd";
	reg = <0 0x7ff50000 0 0x1000>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	iommus = <&smmu_hdlcd1 0>;
	clocks = <&scpi_clk 3>;
	clock-names = "pxlclk";

	port {
	hdlcd1_output: endpoint {
	remote-endpoint = <&tda998x_1_input>;
	};
	};
	};

	hdlcd@7ff60000 {
	compatible = "arm,hdlcd";
	reg = <0 0x7ff60000 0 0x1000>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	iommus = <&smmu_hdlcd0 0>;
	clocks = <&scpi_clk 3>;
	clock-names = "pxlclk";

	port {
	hdlcd0_output: endpoint {
	remote-endpoint = <&tda998x_0_input>;
	};
	};
	};

	soc_uart0: uart@7ff80000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x0 0x7ff80000 0x0 0x1000>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
	clock-names = "uartclk", "apb_pclk";
	};

	i2c@7ffa0000 {
	compatible = "snps,designware-i2c";
	reg = <0x0 0x7ffa0000 0x0 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <400000>;
	i2c-sda-hold-time-ns = <500>;
	clocks = <&soc_smc50mhz>;

	hdmi-transmitter@70 {
	compatible = "nxp,tda998x";
	reg = <0x70>;
	port {
	tda998x_0_input: endpoint {
	remote-endpoint = <&hdlcd0_output>;
	};
	};
	};

	hdmi-transmitter@71 {
	compatible = "nxp,tda998x";
	reg = <0x71>;
	port {
	tda998x_1_input: endpoint {
	remote-endpoint = <&hdlcd1_output>;
	};
	};
	};
	};

	ohci@7ffb0000 {
	compatible = "generic-ohci";
	reg = <0x0 0x7ffb0000 0x0 0x10000>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	iommus = <&smmu_usb 0>;
	clocks = <&soc_usb48mhz>;
	};

	ehci@7ffc0000 {
	compatible = "generic-ehci";
	reg = <0x0 0x7ffc0000 0x0 0x10000>;
	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	iommus = <&smmu_usb 0>;
	clocks = <&soc_usb48mhz>;
	};

	memory-controller@7ffd0000 {
	compatible = "arm,pl354", "arm,primecell";
	reg = <0 0x7ffd0000 0 0x1000>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	};

	memory@80000000 {
	device_type = "memory";
	/* last 16MB of the first memory area is reserved for secure world use by firmware */
	reg = <0x00000000 0x80000000 0x0 0x7f000000>,
	<0x00000008 0x80000000 0x1 0x80000000>;
	};

	- smb@8000000 {
	+ bus@8000000 {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0 0x08000000 0x04000000>,
	<1 0 0 0x14000000 0x04000000>,
	<2 0 0 0x18000000 0x04000000>,
	<3 0 0 0x1c000000 0x04000000>,
	<4 0 0 0x0c000000 0x04000000>,
	<5 0 0 0x10000000 0x04000000>;

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 15>;
	interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 1 &gic 0 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 2 &gic 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 3 &gic 0 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 4 &gic 0 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 5 &gic 0 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 6 &gic 0 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 7 &gic 0 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 8 &gic 0 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 9 &gic 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 10 &gic 0 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 11 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 12 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	};

	site2: tlx@60000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0x60000000 0x10000000>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0>;
	interrupt-map = <0 0 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/arm/juno-motherboard.dtsi b/sys/gnu/dts/arm64/arm/juno-motherboard.dtsi
	index 9f60dacb4f80..e3983ded3c3c 100644
	--- a/sys/gnu/dts/arm64/arm/juno-motherboard.dtsi
	+++ b/sys/gnu/dts/arm64/arm/juno-motherboard.dtsi
	@@ -1,295 +1,295 @@
	/*
	* ARM Juno Platform motherboard peripherals
	*
	* Copyright (c) 2013-2014 ARM Ltd
	*
	* This file is licensed under a dual GPLv2 or BSD license.
	*
	*/

	/ {
	- smb@8000000 {
	+ bus@8000000 {
	mb_clk24mhz: clk24mhz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "juno_mb:clk24mhz";
	};

	mb_clk25mhz: clk25mhz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <25000000>;
	clock-output-names = "juno_mb:clk25mhz";
	};

	v2m_refclk1mhz: refclk1mhz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <1000000>;
	clock-output-names = "juno_mb:refclk1mhz";
	};

	v2m_refclk32khz: refclk32khz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "juno_mb:refclk32khz";
	};

	motherboard {
	compatible = "arm,vexpress,v2p-p1", "simple-bus";
	#address-cells = <2>; /* SMB chipselect number and offset */
	#size-cells = <1>;
	#interrupt-cells = <1>;
	ranges;
	model = "V2M-Juno";
	arm,hbi = <0x252>;
	arm,vexpress,site = <0>;
	arm,v2m-memory-map = "rs1";

	mb_fixed_3v3: mcc-sb-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "MCC_SB_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	gpio-keys {
	compatible = "gpio-keys";

	power-button {
	debounce-interval = <50>;
	wakeup-source;
	linux,code = <116>;
	label = "POWER";
	gpios = <&iofpga_gpio0 0 0x4>;
	};
	home-button {
	debounce-interval = <50>;
	wakeup-source;
	linux,code = <102>;
	label = "HOME";
	gpios = <&iofpga_gpio0 1 0x4>;
	};
	rlock-button {
	debounce-interval = <50>;
	wakeup-source;
	linux,code = <152>;
	label = "RLOCK";
	gpios = <&iofpga_gpio0 2 0x4>;
	};
	vol-up-button {
	debounce-interval = <50>;
	wakeup-source;
	linux,code = <115>;
	label = "VOL+";
	gpios = <&iofpga_gpio0 3 0x4>;
	};
	vol-down-button {
	debounce-interval = <50>;
	wakeup-source;
	linux,code = <114>;
	label = "VOL-";
	gpios = <&iofpga_gpio0 4 0x4>;
	};
	nmi-button {
	debounce-interval = <50>;
	wakeup-source;
	linux,code = <99>;
	label = "NMI";
	gpios = <&iofpga_gpio0 5 0x4>;
	};
	};

	flash@0,00000000 {
	/* 2 * 32MiB NOR Flash memory mounted on CS0 */
	compatible = "arm,vexpress-flash", "cfi-flash";
	reg = <0 0x00000000 0x04000000>;
	bank-width = <4>;
	/*
	* Unfortunately, accessing the flash disturbs
	* the CPU idle states (suspend) and CPU
	* hotplug of the platform. For this reason,
	* flash hardware access is disabled by default.
	*/
	status = "disabled";
	partitions {
	compatible = "arm,arm-firmware-suite";
	};
	};

	ethernet@2,00000000 {
	compatible = "smsc,lan9118", "smsc,lan9115";
	reg = <2 0x00000000 0x10000>;
	interrupts = <3>;
	phy-mode = "mii";
	reg-io-width = <4>;
	smsc,irq-active-high;
	smsc,irq-push-pull;
	clocks = <&mb_clk25mhz>;
	vdd33a-supply = <&mb_fixed_3v3>;
	vddvario-supply = <&mb_fixed_3v3>;
	};

	iofpga@3,00000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 3 0 0x200000>;

	v2m_sysctl: sysctl@20000 {
	compatible = "arm,sp810", "arm,primecell";
	reg = <0x020000 0x1000>;
	clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
	clock-names = "refclk", "timclk", "apb_pclk";
	#clock-cells = <1>;
	clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
	assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
	assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
	};

	apbregs@10000 {
	compatible = "syscon", "simple-mfd";
	reg = <0x010000 0x1000>;

	led0 {
	compatible = "register-bit-led";
	offset = <0x08>;
	mask = <0x01>;
	label = "vexpress:0";
	linux,default-trigger = "heartbeat";
	default-state = "on";
	};
	led1 {
	compatible = "register-bit-led";
	offset = <0x08>;
	mask = <0x02>;
	label = "vexpress:1";
	linux,default-trigger = "mmc0";
	default-state = "off";
	};
	led2 {
	compatible = "register-bit-led";
	offset = <0x08>;
	mask = <0x04>;
	label = "vexpress:2";
	linux,default-trigger = "cpu0";
	default-state = "off";
	};
	led3 {
	compatible = "register-bit-led";
	offset = <0x08>;
	mask = <0x08>;
	label = "vexpress:3";
	linux,default-trigger = "cpu1";
	default-state = "off";
	};
	led4 {
	compatible = "register-bit-led";
	offset = <0x08>;
	mask = <0x10>;
	label = "vexpress:4";
	linux,default-trigger = "cpu2";
	default-state = "off";
	};
	led5 {
	compatible = "register-bit-led";
	offset = <0x08>;
	mask = <0x20>;
	label = "vexpress:5";
	linux,default-trigger = "cpu3";
	default-state = "off";
	};
	led6 {
	compatible = "register-bit-led";
	offset = <0x08>;
	mask = <0x40>;
	label = "vexpress:6";
	default-state = "off";
	};
	led7 {
	compatible = "register-bit-led";
	offset = <0x08>;
	mask = <0x80>;
	label = "vexpress:7";
	default-state = "off";
	};
	};

	mmci@50000 {
	compatible = "arm,pl180", "arm,primecell";
	reg = <0x050000 0x1000>;
	interrupts = <5>;
	/* cd-gpios = <&v2m_mmc_gpios 0 0>;
	wp-gpios = <&v2m_mmc_gpios 1 0>; */
	max-frequency = <12000000>;
	vmmc-supply = <&mb_fixed_3v3>;
	clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
	clock-names = "mclk", "apb_pclk";
	};

	kmi@60000 {
	compatible = "arm,pl050", "arm,primecell";
	reg = <0x060000 0x1000>;
	interrupts = <8>;
	clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
	clock-names = "KMIREFCLK", "apb_pclk";
	};

	kmi@70000 {
	compatible = "arm,pl050", "arm,primecell";
	reg = <0x070000 0x1000>;
	interrupts = <8>;
	clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
	clock-names = "KMIREFCLK", "apb_pclk";
	};

	wdt@f0000 {
	compatible = "arm,sp805", "arm,primecell";
	reg = <0x0f0000 0x10000>;
	interrupts = <7>;
	clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
	clock-names = "wdogclk", "apb_pclk";
	};

	v2m_timer01: timer@110000 {
	compatible = "arm,sp804", "arm,primecell";
	reg = <0x110000 0x10000>;
	interrupts = <9>;
	clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
	clock-names = "timclken1", "timclken2", "apb_pclk";
	};

	v2m_timer23: timer@120000 {
	compatible = "arm,sp804", "arm,primecell";
	reg = <0x120000 0x10000>;
	interrupts = <9>;
	clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
	clock-names = "timclken1", "timclken2", "apb_pclk";
	};

	rtc@170000 {
	compatible = "arm,pl031", "arm,primecell";
	reg = <0x170000 0x10000>;
	interrupts = <0>;
	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	};

	iofpga_gpio0: gpio@1d0000 {
	compatible = "arm,pl061", "arm,primecell";
	reg = <0x1d0000 0x1000>;
	interrupts = <6>;
	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/arm/rtsm_ve-aemv8a.dts b/sys/gnu/dts/arm64/arm/rtsm_ve-aemv8a.dts
	index 6e685d883303..c5d15cbd8cf6 100644
	--- a/sys/gnu/dts/arm64/arm/rtsm_ve-aemv8a.dts
	+++ b/sys/gnu/dts/arm64/arm/rtsm_ve-aemv8a.dts
	@@ -1,193 +1,193 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* ARM Ltd. Fast Models
	*
	* Architecture Envelope Model (AEM) ARMv8-A
	* ARMAEMv8AMPCT
	*
	* RTSM_VE_AEMv8A.lisa
	*/

	/dts-v1/;

	#include <dt-bindings/interrupt-controller/arm-gic.h>

	/memreserve/ 0x80000000 0x00010000;

	#include "rtsm_ve-motherboard.dtsi"

	/ {
	model = "RTSM_VE_AEMv8A";
	compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	aliases {
	serial0 = &v2m_serial0;
	serial1 = &v2m_serial1;
	serial2 = &v2m_serial2;
	serial3 = &v2m_serial3;
	};

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x0>;
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x8000fff8>;
	next-level-cache = <&L2_0>;
	};
	cpu@1 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x1>;
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x8000fff8>;
	next-level-cache = <&L2_0>;
	};
	cpu@2 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x2>;
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x8000fff8>;
	next-level-cache = <&L2_0>;
	};
	cpu@3 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x3>;
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x8000fff8>;
	next-level-cache = <&L2_0>;
	};

	L2_0: l2-cache0 {
	compatible = "cache";
	};
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0x00000000 0x80000000 0 0x80000000>,
	<0x00000008 0x80000000 0 0x80000000>;
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	/* Chipselect 2,00000000 is physically at 0x18000000 */
	vram: vram@18000000 {
	/* 8 MB of designated video RAM */
	compatible = "shared-dma-pool";
	reg = <0x00000000 0x18000000 0 0x00800000>;
	no-map;
	};
	};

	gic: interrupt-controller@2c001000 {
	compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x0 0x2c001000 0 0x1000>,
	<0x0 0x2c002000 0 0x2000>,
	<0x0 0x2c004000 0 0x2000>,
	<0x0 0x2c006000 0 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	clock-frequency = <100000000>;
	};

	pmu {
	compatible = "arm,armv8-pmuv3";
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	};

	panel {
	compatible = "arm,rtsm-display";
	port {
	panel_in: endpoint {
	remote-endpoint = <&clcd_pads>;
	};
	};
	};

	- smb@8000000 {
	+ bus@8000000 {
	compatible = "simple-bus";

	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0 0x08000000 0x04000000>,
	<1 0 0 0x14000000 0x04000000>,
	<2 0 0 0x18000000 0x04000000>,
	<3 0 0 0x1c000000 0x04000000>,
	<4 0 0 0x0c000000 0x04000000>,
	<5 0 0 0x10000000 0x04000000>;

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 63>;
	interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/arm/rtsm_ve-motherboard-rs2.dtsi b/sys/gnu/dts/arm64/arm/rtsm_ve-motherboard-rs2.dtsi
	index 57b0b9d7f3fa..60703b5763c6 100644
	--- a/sys/gnu/dts/arm64/arm/rtsm_ve-motherboard-rs2.dtsi
	+++ b/sys/gnu/dts/arm64/arm/rtsm_ve-motherboard-rs2.dtsi
	@@ -1,27 +1,27 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* ARM Ltd. Fast Models
	*
	* "rs2" extension for the v2m motherboard
	*/
	/ {
	- smb@8000000 {
	+ bus@8000000 {
	motherboard {
	arm,v2m-memory-map = "rs2";

	iofpga@3,00000000 {
	virtio-p9@140000 {
	compatible = "virtio,mmio";
	reg = <0x140000 0x200>;
	interrupts = <43>;
	};

	virtio-net@150000 {
	compatible = "virtio,mmio";
	reg = <0x150000 0x200>;
	interrupts = <44>;
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/arm/rtsm_ve-motherboard.dtsi b/sys/gnu/dts/arm64/arm/rtsm_ve-motherboard.dtsi
	index 03a7bf079c8f..e333c8d2d0e4 100644
	--- a/sys/gnu/dts/arm64/arm/rtsm_ve-motherboard.dtsi
	+++ b/sys/gnu/dts/arm64/arm/rtsm_ve-motherboard.dtsi
	@@ -1,250 +1,250 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* ARM Ltd. Fast Models
	*
	* Versatile Express (VE) system model
	* Motherboard component
	*
	* VEMotherBoard.lisa
	*/
	/ {
	- smb@8000000 {
	+ bus@8000000 {
	motherboard {
	arm,v2m-memory-map = "rs1";
	compatible = "arm,vexpress,v2m-p1", "simple-bus";
	#address-cells = <2>; /* SMB chipselect number and offset */
	#size-cells = <1>;
	#interrupt-cells = <1>;
	ranges;

	flash@0,00000000 {
	compatible = "arm,vexpress-flash", "cfi-flash";
	reg = <0 0x00000000 0x04000000>,
	<4 0x00000000 0x04000000>;
	bank-width = <4>;
	};

	ethernet@2,02000000 {
	compatible = "smsc,lan91c111";
	reg = <2 0x02000000 0x10000>;
	interrupts = <15>;
	};

	v2m_clk24mhz: clk24mhz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "v2m:clk24mhz";
	};

	v2m_refclk1mhz: refclk1mhz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <1000000>;
	clock-output-names = "v2m:refclk1mhz";
	};

	v2m_refclk32khz: refclk32khz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "v2m:refclk32khz";
	};

	iofpga@3,00000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 3 0 0x200000>;

	v2m_sysreg: sysreg@10000 {
	compatible = "arm,vexpress-sysreg";
	reg = <0x010000 0x1000>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	v2m_sysctl: sysctl@20000 {
	compatible = "arm,sp810", "arm,primecell";
	reg = <0x020000 0x1000>;
	clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
	clock-names = "refclk", "timclk", "apb_pclk";
	#clock-cells = <1>;
	clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
	assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
	assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
	};

	aaci@40000 {
	compatible = "arm,pl041", "arm,primecell";
	reg = <0x040000 0x1000>;
	interrupts = <11>;
	clocks = <&v2m_clk24mhz>;
	clock-names = "apb_pclk";
	};

	mmci@50000 {
	compatible = "arm,pl180", "arm,primecell";
	reg = <0x050000 0x1000>;
	interrupts = <9>, <10>;
	cd-gpios = <&v2m_sysreg 0 0>;
	wp-gpios = <&v2m_sysreg 1 0>;
	max-frequency = <12000000>;
	vmmc-supply = <&v2m_fixed_3v3>;
	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
	clock-names = "mclk", "apb_pclk";
	};

	kmi@60000 {
	compatible = "arm,pl050", "arm,primecell";
	reg = <0x060000 0x1000>;
	interrupts = <12>;
	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
	clock-names = "KMIREFCLK", "apb_pclk";
	};

	kmi@70000 {
	compatible = "arm,pl050", "arm,primecell";
	reg = <0x070000 0x1000>;
	interrupts = <13>;
	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
	clock-names = "KMIREFCLK", "apb_pclk";
	};

	v2m_serial0: uart@90000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x090000 0x1000>;
	interrupts = <5>;
	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
	clock-names = "uartclk", "apb_pclk";
	};

	v2m_serial1: uart@a0000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x0a0000 0x1000>;
	interrupts = <6>;
	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
	clock-names = "uartclk", "apb_pclk";
	};

	v2m_serial2: uart@b0000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x0b0000 0x1000>;
	interrupts = <7>;
	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
	clock-names = "uartclk", "apb_pclk";
	};

	v2m_serial3: uart@c0000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x0c0000 0x1000>;
	interrupts = <8>;
	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
	clock-names = "uartclk", "apb_pclk";
	};

	wdt@f0000 {
	compatible = "arm,sp805", "arm,primecell";
	reg = <0x0f0000 0x1000>;
	interrupts = <0>;
	clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
	clock-names = "wdogclk", "apb_pclk";
	};

	v2m_timer01: timer@110000 {
	compatible = "arm,sp804", "arm,primecell";
	reg = <0x110000 0x1000>;
	interrupts = <2>;
	clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
	clock-names = "timclken1", "timclken2", "apb_pclk";
	};

	v2m_timer23: timer@120000 {
	compatible = "arm,sp804", "arm,primecell";
	reg = <0x120000 0x1000>;
	interrupts = <3>;
	clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
	clock-names = "timclken1", "timclken2", "apb_pclk";
	};

	virtio-block@130000 {
	compatible = "virtio,mmio";
	reg = <0x130000 0x200>;
	interrupts = <42>;
	};

	rtc@170000 {
	compatible = "arm,pl031", "arm,primecell";
	reg = <0x170000 0x1000>;
	interrupts = <4>;
	clocks = <&v2m_clk24mhz>;
	clock-names = "apb_pclk";
	};

	clcd@1f0000 {
	compatible = "arm,pl111", "arm,primecell";
	reg = <0x1f0000 0x1000>;
	interrupt-names = "combined";
	interrupts = <14>;
	clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
	clock-names = "clcdclk", "apb_pclk";
	memory-region = <&vram>;

	port {
	clcd_pads: endpoint {
	remote-endpoint = <&panel_in>;
	arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
	};
	};
	};
	};

	v2m_fixed_3v3: v2m-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	mcc {
	compatible = "arm,vexpress,config-bus";
	arm,vexpress,config-bridge = <&v2m_sysreg>;

	v2m_oscclk1: oscclk1 {
	/* CLCD clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 1>;
	freq-range = <23750000 63500000>;
	#clock-cells = <0>;
	clock-output-names = "v2m:oscclk1";
	};

	reset {
	compatible = "arm,vexpress-reset";
	arm,vexpress-sysreg,func = <5 0>;
	};

	muxfpga {
	compatible = "arm,vexpress-muxfpga";
	arm,vexpress-sysreg,func = <7 0>;
	};

	shutdown {
	compatible = "arm,vexpress-shutdown";
	arm,vexpress-sysreg,func = <8 0>;
	};

	reboot {
	compatible = "arm,vexpress-reboot";
	arm,vexpress-sysreg,func = <9 0>;
	};

	dvimode {
	compatible = "arm,vexpress-dvimode";
	arm,vexpress-sysreg,func = <11 0>;
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts b/sys/gnu/dts/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts
	index 22383c26bb03..d859914500a7 100644
	--- a/sys/gnu/dts/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts
	+++ b/sys/gnu/dts/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts
	@@ -1,205 +1,205 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* ARM Ltd. Versatile Express
	*
	* LogicTile Express 20MG
	* V2F-1XV7
	*
	* Cortex-A53 (2 cores) Soft Macrocell Model
	*
	* HBI-0247C
	*/

	/dts-v1/;

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include "vexpress-v2m-rs1.dtsi"

	/ {
	model = "V2F-1XV7 Cortex-A53x2 SMM";
	arm,hbi = <0x247>;
	arm,vexpress,site = <0xf>;
	compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen {
	stdout-path = "serial0:38400n8";
	};

	aliases {
	serial0 = &v2m_serial0;
	serial1 = &v2m_serial1;
	serial2 = &v2m_serial2;
	serial3 = &v2m_serial3;
	i2c0 = &v2m_i2c_dvi;
	i2c1 = &v2m_i2c_pcie;
	};

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0 0>;
	next-level-cache = <&L2_0>;
	};

	cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0 1>;
	next-level-cache = <&L2_0>;
	};

	L2_0: l2-cache0 {
	compatible = "cache";
	};
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	/* Chipselect 2 is physically at 0x18000000 */
	vram: vram@18000000 {
	/* 8 MB of designated video RAM */
	compatible = "shared-dma-pool";
	reg = <0 0x18000000 0 0x00800000>;
	no-map;
	};
	};

	gic: interrupt-controller@2c001000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0 0x2c001000 0 0x1000>,
	<0 0x2c002000 0 0x2000>,
	<0 0x2c004000 0 0x2000>,
	<0 0x2c006000 0 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
	compatible = "arm,armv8-pmuv3";
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	};

	dcc {
	compatible = "arm,vexpress,config-bus";
	arm,vexpress,config-bridge = <&v2m_sysreg>;

	smbclk: smclk {
	/* SMC clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 4>;
	freq-range = <40000000 40000000>;
	#clock-cells = <0>;
	clock-output-names = "smclk";
	};

	volt-vio {
	/* VIO to expansion board above */
	compatible = "arm,vexpress-volt";
	arm,vexpress-sysreg,func = <2 0>;
	regulator-name = "VIO_UP";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	volt-12v {
	/* 12V from power connector J6 */
	compatible = "arm,vexpress-volt";
	arm,vexpress-sysreg,func = <2 1>;
	regulator-name = "12";
	regulator-always-on;
	};

	temp-fpga {
	/* FPGA temperature */
	compatible = "arm,vexpress-temp";
	arm,vexpress-sysreg,func = <4 0>;
	label = "FPGA";
	};
	};

	- smb: smb@8000000 {
	+ smb: bus@8000000 {
	compatible = "simple-bus";

	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0 0x08000000 0x04000000>,
	<1 0 0 0x14000000 0x04000000>,
	<2 0 0 0x18000000 0x04000000>,
	<3 0 0 0x1c000000 0x04000000>,
	<4 0 0 0x0c000000 0x04000000>,
	<5 0 0 0x10000000 0x04000000>;

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 63>;
	interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/arm/vexpress-v2m-rs1.dtsi b/sys/gnu/dts/arm64/arm/vexpress-v2m-rs1.dtsi
	index dfae90adbb7c..5c183483ec3b 100644
	--- a/sys/gnu/dts/arm64/arm/vexpress-v2m-rs1.dtsi
	+++ b/sys/gnu/dts/arm64/arm/vexpress-v2m-rs1.dtsi
	@@ -1,441 +1,441 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* ARM Ltd. Versatile Express
	*
	* Motherboard Express uATX
	* V2M-P1
	*
	* HBI-0190D
	*
	* RS1 memory map ("ARM Cortex-A Series memory map" in the board's
	* Technical Reference Manual)
	*
	* WARNING! The hardware described in this file is independent from the
	* original variant (vexpress-v2m.dtsi), but there is a strong
	* correspondence between the two configurations.
	*
	* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
	* CHANGES TO vexpress-v2m.dtsi!
	*/

	/ {
	- smb@8000000 {
	+ bus@8000000 {
	motherboard {
	model = "V2M-P1";
	arm,hbi = <0x190>;
	arm,vexpress,site = <0>;
	arm,v2m-memory-map = "rs1";
	compatible = "arm,vexpress,v2m-p1", "simple-bus";
	#address-cells = <2>; /* SMB chipselect number and offset */
	#size-cells = <1>;
	#interrupt-cells = <1>;
	ranges;

	nor_flash: flash@0,00000000 {
	compatible = "arm,vexpress-flash", "cfi-flash";
	reg = <0 0x00000000 0x04000000>,
	<4 0x00000000 0x04000000>;
	bank-width = <4>;
	partitions {
	compatible = "arm,arm-firmware-suite";
	};
	};

	psram@1,00000000 {
	compatible = "arm,vexpress-psram", "mtd-ram";
	reg = <1 0x00000000 0x02000000>;
	bank-width = <4>;
	};

	ethernet@2,02000000 {
	compatible = "smsc,lan9118", "smsc,lan9115";
	reg = <2 0x02000000 0x10000>;
	interrupts = <15>;
	phy-mode = "mii";
	reg-io-width = <4>;
	smsc,irq-active-high;
	smsc,irq-push-pull;
	vdd33a-supply = <&v2m_fixed_3v3>;
	vddvario-supply = <&v2m_fixed_3v3>;
	};

	usb@2,03000000 {
	compatible = "nxp,usb-isp1761";
	reg = <2 0x03000000 0x20000>;
	interrupts = <16>;
	port1-otg;
	};

	iofpga@3,00000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 3 0 0x200000>;

	v2m_sysreg: sysreg@10000 {
	compatible = "arm,vexpress-sysreg";
	reg = <0x010000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x10000 0x1000>;

	v2m_led_gpios: gpio@8 {
	compatible = "arm,vexpress-sysreg,sys_led";
	reg = <0x008 4>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	v2m_mmc_gpios: gpio@48 {
	compatible = "arm,vexpress-sysreg,sys_mci";
	reg = <0x048 4>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	v2m_flash_gpios: gpio@4c {
	compatible = "arm,vexpress-sysreg,sys_flash";
	reg = <0x04c 4>;
	gpio-controller;
	#gpio-cells = <2>;
	};
	};

	v2m_sysctl: sysctl@20000 {
	compatible = "arm,sp810", "arm,primecell";
	reg = <0x020000 0x1000>;
	clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
	clock-names = "refclk", "timclk", "apb_pclk";
	#clock-cells = <1>;
	clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
	assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
	assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
	};

	/* PCI-E I2C bus */
	v2m_i2c_pcie: i2c@30000 {
	compatible = "arm,versatile-i2c";
	reg = <0x030000 0x1000>;

	#address-cells = <1>;
	#size-cells = <0>;

	pcie-switch@60 {
	compatible = "idt,89hpes32h8";
	reg = <0x60>;
	};
	};

	aaci@40000 {
	compatible = "arm,pl041", "arm,primecell";
	reg = <0x040000 0x1000>;
	interrupts = <11>;
	clocks = <&smbclk>;
	clock-names = "apb_pclk";
	};

	mmci@50000 {
	compatible = "arm,pl180", "arm,primecell";
	reg = <0x050000 0x1000>;
	interrupts = <9>, <10>;
	cd-gpios = <&v2m_mmc_gpios 0 0>;
	wp-gpios = <&v2m_mmc_gpios 1 0>;
	max-frequency = <12000000>;
	vmmc-supply = <&v2m_fixed_3v3>;
	clocks = <&v2m_clk24mhz>, <&smbclk>;
	clock-names = "mclk", "apb_pclk";
	};

	kmi@60000 {
	compatible = "arm,pl050", "arm,primecell";
	reg = <0x060000 0x1000>;
	interrupts = <12>;
	clocks = <&v2m_clk24mhz>, <&smbclk>;
	clock-names = "KMIREFCLK", "apb_pclk";
	};

	kmi@70000 {
	compatible = "arm,pl050", "arm,primecell";
	reg = <0x070000 0x1000>;
	interrupts = <13>;
	clocks = <&v2m_clk24mhz>, <&smbclk>;
	clock-names = "KMIREFCLK", "apb_pclk";
	};

	v2m_serial0: uart@90000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x090000 0x1000>;
	interrupts = <5>;
	clocks = <&v2m_oscclk2>, <&smbclk>;
	clock-names = "uartclk", "apb_pclk";
	};

	v2m_serial1: uart@a0000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x0a0000 0x1000>;
	interrupts = <6>;
	clocks = <&v2m_oscclk2>, <&smbclk>;
	clock-names = "uartclk", "apb_pclk";
	};

	v2m_serial2: uart@b0000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x0b0000 0x1000>;
	interrupts = <7>;
	clocks = <&v2m_oscclk2>, <&smbclk>;
	clock-names = "uartclk", "apb_pclk";
	};

	v2m_serial3: uart@c0000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0x0c0000 0x1000>;
	interrupts = <8>;
	clocks = <&v2m_oscclk2>, <&smbclk>;
	clock-names = "uartclk", "apb_pclk";
	};

	wdt@f0000 {
	compatible = "arm,sp805", "arm,primecell";
	reg = <0x0f0000 0x1000>;
	interrupts = <0>;
	clocks = <&v2m_refclk32khz>, <&smbclk>;
	clock-names = "wdogclk", "apb_pclk";
	};

	v2m_timer01: timer@110000 {
	compatible = "arm,sp804", "arm,primecell";
	reg = <0x110000 0x1000>;
	interrupts = <2>;
	clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
	clock-names = "timclken1", "timclken2", "apb_pclk";
	};

	v2m_timer23: timer@120000 {
	compatible = "arm,sp804", "arm,primecell";
	reg = <0x120000 0x1000>;
	interrupts = <3>;
	clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
	clock-names = "timclken1", "timclken2", "apb_pclk";
	};

	/* DVI I2C bus */
	v2m_i2c_dvi: i2c@160000 {
	compatible = "arm,versatile-i2c";
	reg = <0x160000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;

	dvi-transmitter@39 {
	compatible = "sil,sii9022-tpi", "sil,sii9022";
	reg = <0x39>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	dvi_bridge_in: endpoint {
	remote-endpoint = <&clcd_pads>;
	};
	};
	};
	};

	dvi-transmitter@60 {
	compatible = "sil,sii9022-cpi", "sil,sii9022";
	reg = <0x60>;
	};
	};

	rtc@170000 {
	compatible = "arm,pl031", "arm,primecell";
	reg = <0x170000 0x1000>;
	interrupts = <4>;
	clocks = <&smbclk>;
	clock-names = "apb_pclk";
	};

	compact-flash@1a0000 {
	compatible = "arm,vexpress-cf", "ata-generic";
	reg = <0x1a0000 0x100
	0x1a0100 0xf00>;
	reg-shift = <2>;
	};

	clcd@1f0000 {
	compatible = "arm,pl111", "arm,primecell";
	reg = <0x1f0000 0x1000>;
	interrupt-names = "combined";
	interrupts = <14>;
	clocks = <&v2m_oscclk1>, <&smbclk>;
	clock-names = "clcdclk", "apb_pclk";
	/* 800x600 16bpp @36MHz works fine */
	max-memory-bandwidth = <54000000>;
	memory-region = <&vram>;

	port {
	clcd_pads: endpoint {
	remote-endpoint = <&dvi_bridge_in>;
	arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
	};
	};
	};
	};

	v2m_fixed_3v3: fixed-regulator-0 {
	compatible = "regulator-fixed";
	regulator-name = "3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	v2m_clk24mhz: clk24mhz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "v2m:clk24mhz";
	};

	v2m_refclk1mhz: refclk1mhz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <1000000>;
	clock-output-names = "v2m:refclk1mhz";
	};

	v2m_refclk32khz: refclk32khz {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "v2m:refclk32khz";
	};

	leds {
	compatible = "gpio-leds";

	user1 {
	label = "v2m:green:user1";
	gpios = <&v2m_led_gpios 0 0>;
	linux,default-trigger = "heartbeat";
	};

	user2 {
	label = "v2m:green:user2";
	gpios = <&v2m_led_gpios 1 0>;
	linux,default-trigger = "mmc0";
	};

	user3 {
	label = "v2m:green:user3";
	gpios = <&v2m_led_gpios 2 0>;
	linux,default-trigger = "cpu0";
	};

	user4 {
	label = "v2m:green:user4";
	gpios = <&v2m_led_gpios 3 0>;
	linux,default-trigger = "cpu1";
	};

	user5 {
	label = "v2m:green:user5";
	gpios = <&v2m_led_gpios 4 0>;
	linux,default-trigger = "cpu2";
	};

	user6 {
	label = "v2m:green:user6";
	gpios = <&v2m_led_gpios 5 0>;
	linux,default-trigger = "cpu3";
	};

	user7 {
	label = "v2m:green:user7";
	gpios = <&v2m_led_gpios 6 0>;
	linux,default-trigger = "cpu4";
	};

	user8 {
	label = "v2m:green:user8";
	gpios = <&v2m_led_gpios 7 0>;
	linux,default-trigger = "cpu5";
	};
	};

	mcc {
	compatible = "arm,vexpress,config-bus";
	arm,vexpress,config-bridge = <&v2m_sysreg>;

	oscclk0 {
	/* MCC static memory clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 0>;
	freq-range = <25000000 60000000>;
	#clock-cells = <0>;
	clock-output-names = "v2m:oscclk0";
	};

	v2m_oscclk1: oscclk1 {
	/* CLCD clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 1>;
	freq-range = <23750000 65000000>;
	#clock-cells = <0>;
	clock-output-names = "v2m:oscclk1";
	};

	v2m_oscclk2: oscclk2 {
	/* IO FPGA peripheral clock */
	compatible = "arm,vexpress-osc";
	arm,vexpress-sysreg,func = <1 2>;
	freq-range = <24000000 24000000>;
	#clock-cells = <0>;
	clock-output-names = "v2m:oscclk2";
	};

	volt-vio {
	/* Logic level voltage */
	compatible = "arm,vexpress-volt";
	arm,vexpress-sysreg,func = <2 0>;
	regulator-name = "VIO";
	regulator-always-on;
	label = "VIO";
	};

	temp-mcc {
	/* MCC internal operating temperature */
	compatible = "arm,vexpress-temp";
	arm,vexpress-sysreg,func = <4 0>;
	label = "MCC";
	};

	reset {
	compatible = "arm,vexpress-reset";
	arm,vexpress-sysreg,func = <5 0>;
	};

	muxfpga {
	compatible = "arm,vexpress-muxfpga";
	arm,vexpress-sysreg,func = <7 0>;
	};

	shutdown {
	compatible = "arm,vexpress-shutdown";
	arm,vexpress-sysreg,func = <8 0>;
	};

	reboot {
	compatible = "arm,vexpress-reboot";
	arm,vexpress-sysreg,func = <9 0>;
	};

	dvimode {
	compatible = "arm,vexpress-dvimode";
	arm,vexpress-sysreg,func = <11 0>;
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts
	new file mode 100644
	index 000000000000..4b4cc6a1573d
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts
	@@ -0,0 +1,91 @@
	+// SPDX-License-Identifier: GPL-2.0+
	+/*
	+ * Device Tree File for the Kontron KBox A-230-LS.
	+ *
	+ * This consists of a Kontron SMARC-sAL28 (Dual PHY) and a special
	+ * carrier (s1914).
	+ *
	+ * Copyright (C) 2019 Michael Walle <michael@walle.cc>
	+ *
	+ */
	+
	+/dts-v1/;
	+#include "fsl-ls1028a-kontron-sl28-var4.dts"
	+
	+/ {
	+ model = "Kontron KBox A-230-LS";
	+ compatible = "kontron,kbox-a-230-ls", "kontron,sl28-var4",
	+ "kontron,sl28", "fsl,ls1028a";
	+};
	+
	+&enetc_mdio_pf3 {
	+ /* BCM54140 QSGMII quad PHY */
	+ qsgmii_phy0: ethernet-phy@7 {
	+ reg = <7>;
	+ };
	+
	+ qsgmii_phy1: ethernet-phy@8 {
	+ reg = <8>;
	+ };
	+
	+ qsgmii_phy2: ethernet-phy@9 {
	+ reg = <9>;
	+ };
	+
	+ qsgmii_phy3: ethernet-phy@10 {
	+ reg = <10>;
	+ };
	+};
	+
	+&enetc_port2 {
	+ status = "okay";
	+};
	+
	+&i2c3 {
	+ eeprom@57 {
	+ compatible = "atmel,24c32";
	+ reg = <0x57>;
	+ pagesize = <32>;
	+ };
	+};
	+
	+&mscc_felix {
	+ status = "okay";
	+};
	+
	+&mscc_felix_port0 {
	+ label = "swp0";
	+ managed = "in-band-status";
	+ phy-handle = <&qsgmii_phy0>;
	+ phy-mode = "qsgmii";
	+ status = "okay";
	+};
	+
	+&mscc_felix_port1 {
	+ label = "swp1";
	+ managed = "in-band-status";
	+ phy-handle = <&qsgmii_phy1>;
	+ phy-mode = "qsgmii";
	+ status = "okay";
	+};
	+
	+&mscc_felix_port2 {
	+ label = "swp2";
	+ managed = "in-band-status";
	+ phy-handle = <&qsgmii_phy2>;
	+ phy-mode = "qsgmii";
	+ status = "okay";
	+};
	+
	+&mscc_felix_port3 {
	+ label = "swp3";
	+ managed = "in-band-status";
	+ phy-handle = <&qsgmii_phy3>;
	+ phy-mode = "qsgmii";
	+ status = "okay";
	+};
	+
	+&mscc_felix_port4 {
	+ ethernet = <&enetc_port2>;
	+ status = "okay";
	+};
	diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1028a-kontron-sl28-var2.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1028a-kontron-sl28-var2.dts
	new file mode 100644
	index 000000000000..901b5b161def
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/freescale/fsl-ls1028a-kontron-sl28-var2.dts
	@@ -0,0 +1,72 @@
	+// SPDX-License-Identifier: GPL-2.0+
	+/*
	+ * Device Tree file for the Kontron SMARC-sAL28 board.
	+ *
	+ * This is for the network variant 2 which has two ethernet ports. These
	+ * ports are connected to the internal switch.
	+ *
	+ * Copyright (C) 2020 Michael Walle <michael@walle.cc>
	+ *
	+ */
	+
	+/dts-v1/;
	+#include "fsl-ls1028a-kontron-sl28.dts"
	+
	+/ {
	+ model = "Kontron SMARC-sAL28 (TSN-on-module)";
	+ compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a";
	+};
	+
	+&enetc_mdio_pf3 {
	+ phy0: ethernet-phy@5 {
	+ reg = <0x5>;
	+ eee-broken-1000t;
	+ eee-broken-100tx;
	+ };
	+
	+ phy1: ethernet-phy@4 {
	+ reg = <0x4>;
	+ eee-broken-1000t;
	+ eee-broken-100tx;
	+ };
	+};
	+
	+&enetc_port0 {
	+ status = "disabled";
	+ /*
	+ * In the base device tree the PHY was registered in the mdio
	+ * subnode as it is PHY for this port. On this module this PHY
	+ * is connected to a switch port instead and registered above.
	+ * Therefore, delete the mdio subnode as well as the phy-handle
	+ * property here.
	+ */
	+ /delete-property/ phy-handle;
	+ /delete-node/ mdio;
	+};
	+
	+&enetc_port2 {
	+ status = "okay";
	+};
	+
	+&mscc_felix {
	+ status = "okay";
	+};
	+
	+&mscc_felix_port0 {
	+ label = "gbe0";
	+ phy-handle = <&phy0>;
	+ phy-mode = "sgmii";
	+ status = "okay";
	+};
	+
	+&mscc_felix_port1 {
	+ label = "gbe1";
	+ phy-handle = <&phy1>;
	+ phy-mode = "sgmii";
	+ status = "okay";
	+};
	+
	+&mscc_felix_port4 {
	+ ethernet = <&enetc_port2>;
	+ status = "okay";
	+};
	diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts
	new file mode 100644
	index 000000000000..0973a6a45217
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts
	@@ -0,0 +1,117 @@
	+// SPDX-License-Identifier: GPL-2.0+
	+/*
	+ * Device Tree file for the Kontron SMARC-sAL28 board on a SMARC Eval 2.0
	+ * carrier (ADS2).
	+ *
	+ * Copyright (C) 2019 Michael Walle <michael@walle.cc>
	+ *
	+ */
	+
	+/dts-v1/;
	+#include "fsl-ls1028a-kontron-sl28.dts"
	+
	+/ {
	+ model = "Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier";
	+ compatible = "kontron,sl28-var3-ads2", "kontron,sl28-var3",
	+ "kontron,sl28", "fsl,ls1028a";
	+
	+ sound {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ compatible = "simple-audio-card";
	+ simple-audio-card,widgets =
	+ "Headphone", "Headphone Jack",
	+ "Line", "Line Out Jack",
	+ "Microphone", "Microphone Jack",
	+ "Line", "Line In Jack";
	+ simple-audio-card,routing =
	+ "Line Out Jack", "LINEOUTR",
	+ "Line Out Jack", "LINEOUTL",
	+ "Headphone Jack", "HPOUTR",
	+ "Headphone Jack", "HPOUTL",
	+ "IN1L", "Line In Jack",
	+ "IN1R", "Line In Jack",
	+ "Microphone Jack", "MICBIAS",
	+ "IN2L", "Microphone Jack",
	+ "IN2R", "Microphone Jack";
	+ simple-audio-card,mclk-fs = <256>;
	+
	+ simple-audio-card,dai-link@0 {
	+ reg = <0>;
	+ bitclock-master = <&dailink0_master>;
	+ frame-master = <&dailink0_master>;
	+ format = "i2s";
	+
	+ cpu {
	+ sound-dai = <&sai6>;
	+ };
	+
	+ dailink0_master: codec {
	+ sound-dai = <&wm8904>;
	+ };
	+ };
	+
	+ simple-audio-card,dai-link@1 {
	+ reg = <1>;
	+ bitclock-master = <&dailink1_master>;
	+ frame-master = <&dailink1_master>;
	+ format = "i2s";
	+
	+ cpu {
	+ sound-dai = <&sai5>;
	+ };
	+
	+ dailink1_master: codec {
	+ sound-dai = <&wm8904>;
	+ };
	+ };
	+ };
	+};
	+
	+&dspi2 {
	+ flash@0 {
	+ compatible = "jedec,spi-nor";
	+ m25p,fast-read;
	+ spi-max-frequency = <100000000>;
	+ reg = <0>;
	+ };
	+};
	+
	+&i2c3 {
	+ eeprom@57 {
	+ compatible = "atmel,24c64";
	+ reg = <0x57>;
	+ pagesize = <32>;
	+ };
	+};
	+
	+&i2c4 {
	+ status = "okay";
	+
	+ wm8904: audio-codec@1a {
	+ #sound-dai-cells = <0>;
	+ compatible = "wlf,wm8904";
	+ reg = <0x1a>;
	+ clocks = <&mclk>;
	+ clock-names = "mclk";
	+ assigned-clocks = <&mclk>;
	+ assigned-clock-rates = <1250000>;
	+ };
	+};
	+
	+&sai5 {
	+ status = "okay";
	+};
	+
	+&sai6 {
	+ status = "okay";
	+};
	+
	+&soc {
	+ mclk: clock-mclk@f130080 {
	+ compatible = "fsl,vf610-sai-clock";
	+ reg = <0x0 0xf130080 0x0 0x80>;
	+ clocks = <&clockgen 4 1>;
	+ #clock-cells = <0>;
	+ };
	+};
	diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1028a-kontron-sl28-var4.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1028a-kontron-sl28-var4.dts
	new file mode 100644
	index 000000000000..df212ed5bb94
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/freescale/fsl-ls1028a-kontron-sl28-var4.dts
	@@ -0,0 +1,51 @@
	+// SPDX-License-Identifier: GPL-2.0+
	+/*
	+ * Device Tree file for the Kontron SMARC-sAL28 board.
	+ *
	+ * This is for the network variant 4 which has two ethernet ports. It
	+ * extends the base and provides one more port connected via RGMII.
	+ *
	+ * Copyright (C) 2019 Michael Walle <michael@walle.cc>
	+ *
	+ */
	+
	+/dts-v1/;
	+#include "fsl-ls1028a-kontron-sl28.dts"
	+#include <dt-bindings/net/qca-ar803x.h>
	+
	+/ {
	+ model = "Kontron SMARC-sAL28 (Dual PHY)";
	+ compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
	+};
	+
	+&enetc_port1 {
	+ phy-handle = <&phy1>;
	+ phy-connection-type = "rgmii-id";
	+ status = "okay";
	+
	+ mdio {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ phy1: ethernet-phy@4 {
	+ reg = <0x4>;
	+ eee-broken-1000t;
	+ eee-broken-100tx;
	+
	+ qca,clk-out-frequency = <125000000>;
	+ qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
	+
	+ vddio-supply = <&vddh>;
	+
	+ vddio: vddio-regulator {
	+ regulator-name = "VDDIO";
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+ };
	+
	+ vddh: vddh-regulator {
	+ regulator-name = "VDDH";
	+ };
	+ };
	+ };
	+};
	diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1028a-kontron-sl28.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1028a-kontron-sl28.dts
	new file mode 100644
	index 000000000000..1648a04ea79f
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/freescale/fsl-ls1028a-kontron-sl28.dts
	@@ -0,0 +1,187 @@
	+// SPDX-License-Identifier: GPL-2.0+
	+/*
	+ * Device Tree file for the Kontron SMARC-sAL28 board.
	+ *
	+ * Copyright (C) 2019 Michael Walle <michael@walle.cc>
	+ *
	+ */
	+
	+/dts-v1/;
	+#include "fsl-ls1028a.dtsi"
	+
	+/ {
	+ model = "Kontron SMARC-sAL28";
	+ compatible = "kontron,sl28", "fsl,ls1028a";
	+
	+ aliases {
	+ crypto = &crypto;
	+ serial0 = &duart0;
	+ serial1 = &duart1;
	+ spi0 = &fspi;
	+ spi1 = &dspi2;
	+ };
	+
	+ chosen {
	+ stdout-path = "serial0:115200n8";
	+ };
	+};
	+
	+&dspi2 {
	+ status = "okay";
	+};
	+
	+&duart0 {
	+ status = "okay";
	+};
	+
	+&duart1 {
	+ status = "okay";
	+};
	+
	+&enetc_port0 {
	+ phy-handle = <&phy0>;
	+ phy-connection-type = "sgmii";
	+ status = "okay";
	+
	+ mdio {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ phy0: ethernet-phy@5 {
	+ reg = <0x5>;
	+ eee-broken-1000t;
	+ eee-broken-100tx;
	+ };
	+ };
	+};
	+
	+&esdhc {
	+ sd-uhs-sdr104;
	+ sd-uhs-sdr50;
	+ sd-uhs-sdr25;
	+ sd-uhs-sdr12;
	+ status = "okay";
	+};
	+
	+&esdhc1 {
	+ mmc-hs200-1_8v;
	+ mmc-hs400-1_8v;
	+ bus-width = <8>;
	+ status = "okay";
	+};
	+
	+&fspi {
	+ status = "okay";
	+
	+ flash@0 {
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ compatible = "jedec,spi-nor";
	+ m25p,fast-read;
	+ spi-max-frequency = <133000000>;
	+ reg = <0>;
	+ /* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */
	+ spi-rx-bus-width = <2>; /* 2 SPI Rx lines */
	+ spi-tx-bus-width = <1>; /* 1 SPI Tx line */
	+
	+ partition@0 {
	+ reg = <0x000000 0x010000>;
	+ label = "rcw";
	+ read-only;
	+ };
	+
	+ partition@10000 {
	+ reg = <0x010000 0x0f0000>;
	+ label = "failsafe bootloader";
	+ read-only;
	+ };
	+
	+ partition@100000 {
	+ reg = <0x100000 0x040000>;
	+ label = "failsafe DP firmware";
	+ read-only;
	+ };
	+
	+ partition@140000 {
	+ reg = <0x140000 0x0a0000>;
	+ label = "failsafe trusted firmware";
	+ read-only;
	+ };
	+
	+ partition@1e0000 {
	+ reg = <0x1e0000 0x020000>;
	+ label = "reserved";
	+ read-only;
	+ };
	+
	+ partition@200000 {
	+ reg = <0x200000 0x010000>;
	+ label = "configuration store";
	+ };
	+
	+ partition@210000 {
	+ reg = <0x210000 0x0f0000>;
	+ label = "bootloader";
	+ };
	+
	+ partition@300000 {
	+ reg = <0x300000 0x040000>;
	+ label = "DP firmware";
	+ };
	+
	+ partition@340000 {
	+ reg = <0x340000 0x0a0000>;
	+ label = "trusted firmware";
	+ };
	+
	+ partition@3e0000 {
	+ reg = <0x3e0000 0x020000>;
	+ label = "bootloader environment";
	+ };
	+ };
	+};
	+
	+&gpio1 {
	+ gpio-line-names =
	+ "", "", "", "", "", "", "", "",
	+ "", "", "", "", "", "", "", "",
	+ "", "", "", "", "", "", "TDO", "TCK",
	+ "", "", "", "", "", "", "", "";
	+};
	+
	+&gpio2 {
	+ gpio-line-names =
	+ "", "", "", "", "", "", "TMS", "TDI",
	+ "", "", "", "", "", "", "", "",
	+ "", "", "", "", "", "", "", "",
	+ "", "", "", "", "", "", "", "";
	+};
	+
	+&i2c0 {
	+ status = "okay";
	+
	+ rtc@32 {
	+ compatible = "microcrystal,rv8803";
	+ reg = <0x32>;
	+ };
	+
	+ eeprom@50 {
	+ compatible = "atmel,24c32";
	+ reg = <0x50>;
	+ pagesize = <32>;
	+ };
	+};
	+
	+&i2c3 {
	+ status = "okay";
	+};
	+
	+&i2c4 {
	+ status = "okay";
	+
	+ eeprom@50 {
	+ compatible = "atmel,24c32";
	+ reg = <0x50>;
	+ pagesize = <32>;
	+ };
	+};
	diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1028a-qds.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1028a-qds.dts
	index ca409d907b36..dd69c5b821e9 100644
	--- a/sys/gnu/dts/arm64/freescale/fsl-ls1028a-qds.dts
	+++ b/sys/gnu/dts/arm64/freescale/fsl-ls1028a-qds.dts
	@@ -1,236 +1,237 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Device Tree file for NXP LS1028A QDS Board.
	*
	* Copyright 2018 NXP
	*
	* Harninder Rai <harninder.rai@nxp.com>
	*
	*/

	/dts-v1/;

	#include "fsl-ls1028a.dtsi"

	/ {
	model = "LS1028A QDS Board";
	compatible = "fsl,ls1028a-qds", "fsl,ls1028a";

	aliases {
	crypto = &crypto;
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	serial0 = &duart0;
	serial1 = &duart1;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0x0 0x80000000 0x1 0x00000000>;
	};

	sys_mclk: clock-mclk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <25000000>;
	};

	reg_1p8v: regulator-1p8v {
	compatible = "regulator-fixed";
	regulator-name = "1P8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	sb_3v3: regulator-sb3v3 {
	compatible = "regulator-fixed";
	regulator-name = "3v3_vbus";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sound {
	compatible = "simple-audio-card";
	simple-audio-card,format = "i2s";
	simple-audio-card,widgets =
	"Microphone", "Microphone Jack",
	"Headphone", "Headphone Jack",
	"Speaker", "Speaker Ext",
	"Line", "Line In Jack";
	simple-audio-card,routing =
	"MIC_IN", "Microphone Jack",
	"Microphone Jack", "Mic Bias",
	"LINE_IN", "Line In Jack",
	"Headphone Jack", "HP_OUT",
	"Speaker Ext", "LINE_OUT";

	simple-audio-card,cpu {
	sound-dai = <&sai1>;
	frame-master;
	bitclock-master;
	};

	simple-audio-card,codec {
	sound-dai = <&sgtl5000>;
	frame-master;
	bitclock-master;
	system-clock-frequency = <25000000>;
	};
	};

	mdio-mux {
	compatible = "mdio-mux-multiplexer";
	mux-controls = <&mux 0>;
	mdio-parent-bus = <&enetc_mdio_pf3>;
	#address-cells=<1>;
	#size-cells = <0>;

	/* on-board RGMII PHY */
	mdio@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	qds_phy1: ethernet-phy@5 {
	/* Atheros 8035 */
	reg = <5>;
	};
	};
	};
	};

	&duart0 {
	status = "okay";
	};

	&duart1 {
	status = "okay";
	};

	&esdhc {
	status = "okay";
	};

	&esdhc1 {
	status = "okay";
	};

	&fspi {
	status = "okay";

	mt35xu02g0: flash@0 {
	compatible = "jedec,spi-nor";
	#address-cells = <1>;
	#size-cells = <1>;
	spi-max-frequency = <50000000>;
	/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
	spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
	spi-tx-bus-width = <1>; /* 1 SPI Tx line */
	reg = <0>;
	};
	};

	&i2c0 {
	status = "okay";

	i2c-mux@77 {
	compatible = "nxp,pca9547";
	reg = <0x77>;
	#address-cells = <1>;
	#size-cells = <0>;

	i2c@2 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x2>;

	current-monitor@40 {
	compatible = "ti,ina220";
	reg = <0x40>;
	shunt-resistor = <1000>;
	};

	current-monitor@41 {
	compatible = "ti,ina220";
	reg = <0x41>;
	shunt-resistor = <1000>;
	};
	};

	i2c@3 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x3>;

	temperature-sensor@4c {
	compatible = "nxp,sa56004";
	reg = <0x4c>;
	vcc-supply = <&sb_3v3>;
	};

	rtc@51 {
	compatible = "nxp,pcf2129";
	reg = <0x51>;
	};

	eeprom@56 {
	compatible = "atmel,24c512";
	reg = <0x56>;
	};

	eeprom@57 {
	compatible = "atmel,24c512";
	reg = <0x57>;
	};
	};

	i2c@5 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x5>;

	sgtl5000: audio-codec@a {
	#sound-dai-cells = <0>;
	compatible = "fsl,sgtl5000";
	reg = <0xa>;
	VDDA-supply = <&reg_1p8v>;
	VDDIO-supply = <&reg_1p8v>;
	clocks = <&sys_mclk>;
	};
	};
	};

	fpga@66 {
	compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
	"simple-mfd";
	reg = <0x66>;

	mux: mux-controller {
	compatible = "reg-mux";
	#mux-control-cells = <1>;
	mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */
	};
	};

	};

	&enetc_port1 {
	phy-handle = <&qds_phy1>;
	phy-connection-type = "rgmii-id";
	+ status = "okay";
	};

	&sai1 {
	status = "okay";
	};

	&sata {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1028a-rdb.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1028a-rdb.dts
	index afb55653850d..c2dc1232f93f 100644
	--- a/sys/gnu/dts/arm64/freescale/fsl-ls1028a-rdb.dts
	+++ b/sys/gnu/dts/arm64/freescale/fsl-ls1028a-rdb.dts
	@@ -1,207 +1,268 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Device Tree file for NXP LS1028A RDB Board.
	*
	* Copyright 2018 NXP
	*
	* Harninder Rai <harninder.rai@nxp.com>
	*
	*/

	/dts-v1/;
	#include "fsl-ls1028a.dtsi"

	/ {
	model = "LS1028A RDB Board";
	compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";

	aliases {
	crypto = &crypto;
	serial0 = &duart0;
	serial1 = &duart1;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0x0 0x80000000 0x1 0x0000000>;
	};

	sys_mclk: clock-mclk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <25000000>;
	};

	reg_1p8v: regulator-1p8v {
	compatible = "regulator-fixed";
	regulator-name = "1P8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	sb_3v3: regulator-sb3v3 {
	compatible = "regulator-fixed";
	regulator-name = "3v3_vbus";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	sound {
	compatible = "simple-audio-card";
	simple-audio-card,format = "i2s";
	simple-audio-card,widgets =
	"Microphone", "Microphone Jack",
	"Headphone", "Headphone Jack",
	"Speaker", "Speaker Ext",
	"Line", "Line In Jack";
	simple-audio-card,routing =
	"MIC_IN", "Microphone Jack",
	"Microphone Jack", "Mic Bias",
	"LINE_IN", "Line In Jack",
	"Headphone Jack", "HP_OUT",
	"Speaker Ext", "LINE_OUT";

	simple-audio-card,cpu {
	sound-dai = <&sai4>;
	frame-master;
	bitclock-master;
	};

	simple-audio-card,codec {
	sound-dai = <&sgtl5000>;
	frame-master;
	bitclock-master;
	system-clock-frequency = <25000000>;
	};
	};
	};

	&esdhc {
	sd-uhs-sdr104;
	sd-uhs-sdr50;
	sd-uhs-sdr25;
	sd-uhs-sdr12;
	status = "okay";
	};

	&esdhc1 {
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	bus-width = <8>;
	status = "okay";
	};

	&fspi {
	status = "okay";

	mt35xu02g0: flash@0 {
	compatible = "jedec,spi-nor";
	#address-cells = <1>;
	#size-cells = <1>;
	spi-max-frequency = <50000000>;
	/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
	spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
	spi-tx-bus-width = <1>; /* 1 SPI Tx line */
	reg = <0>;
	};
	};

	&i2c0 {
	status = "okay";

	i2c-mux@77 {
	compatible = "nxp,pca9847";
	reg = <0x77>;
	#address-cells = <1>;
	#size-cells = <0>;

	i2c@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x1>;

	sgtl5000: audio-codec@a {
	#sound-dai-cells = <0>;
	compatible = "fsl,sgtl5000";
	reg = <0xa>;
	VDDA-supply = <&reg_1p8v>;
	VDDIO-supply = <&reg_1p8v>;
	clocks = <&sys_mclk>;
	sclk-strength = <3>;
	};
	};

	i2c@2 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x02>;

	current-monitor@40 {
	compatible = "ti,ina220";
	reg = <0x40>;
	shunt-resistor = <500>;
	};
	};

	i2c@3 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x3>;

	temperature-sensor@4c {
	compatible = "nxp,sa56004";
	reg = <0x4c>;
	vcc-supply = <&sb_3v3>;
	};

	rtc@51 {
	compatible = "nxp,pcf2129";
	reg = <0x51>;
	};
	};
	};
	};

	&duart0 {
	status = "okay";
	};

	&duart1 {
	status = "okay";
	};

	+&enetc_mdio_pf3 {
	+ /* VSC8514 QSGMII quad PHY */
	+ qsgmii_phy0: ethernet-phy@10 {
	+ reg = <0x10>;
	+ };
	+
	+ qsgmii_phy1: ethernet-phy@11 {
	+ reg = <0x11>;
	+ };
	+
	+ qsgmii_phy2: ethernet-phy@12 {
	+ reg = <0x12>;
	+ };
	+
	+ qsgmii_phy3: ethernet-phy@13 {
	+ reg = <0x13>;
	+ };
	+};
	+
	&enetc_port0 {
	phy-handle = <&sgmii_phy0>;
	phy-connection-type = "sgmii";
	+ status = "okay";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;
	sgmii_phy0: ethernet-phy@2 {
	reg = <0x2>;
	};
	};
	};

	-&enetc_port1 {
	- status = "disabled";
	+&enetc_port2 {
	+ status = "okay";
	+};
	+
	+&mscc_felix {
	+ status = "okay";
	+};
	+
	+&mscc_felix_port0 {
	+ label = "swp0";
	+ managed = "in-band-status";
	+ phy-handle = <&qsgmii_phy0>;
	+ phy-mode = "qsgmii";
	+ status = "okay";
	+};
	+
	+&mscc_felix_port1 {
	+ label = "swp1";
	+ managed = "in-band-status";
	+ phy-handle = <&qsgmii_phy1>;
	+ phy-mode = "qsgmii";
	+ status = "okay";
	+};
	+
	+&mscc_felix_port2 {
	+ label = "swp2";
	+ managed = "in-band-status";
	+ phy-handle = <&qsgmii_phy2>;
	+ phy-mode = "qsgmii";
	+ status = "okay";
	+};
	+
	+&mscc_felix_port3 {
	+ label = "swp3";
	+ managed = "in-band-status";
	+ phy-handle = <&qsgmii_phy3>;
	+ phy-mode = "qsgmii";
	+ status = "okay";
	+};
	+
	+&mscc_felix_port4 {
	+ ethernet = <&enetc_port2>;
	+ status = "okay";
	};

	&sai4 {
	status = "okay";
	};

	&sata {
	status = "okay";
	};

	&usb1 {
	dr_mode = "otg";
	};
	diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1028a.dtsi b/sys/gnu/dts/arm64/freescale/fsl-ls1028a.dtsi
	index 55b71bb4baf8..13d0570c7ed6 100644
	--- a/sys/gnu/dts/arm64/freescale/fsl-ls1028a.dtsi
	+++ b/sys/gnu/dts/arm64/freescale/fsl-ls1028a.dtsi
	@@ -1,747 +1,1000 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Device Tree Include file for NXP Layerscape-1028A family SoC.
	*
	* Copyright 2018 NXP
	*
	* Harninder Rai <harninder.rai@nxp.com>
	*
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	compatible = "fsl,ls1028a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	reg = <0x0>;
	enable-method = "psci";
	clocks = <&clockgen 1 0>;
	next-level-cache = <&l2>;
	cpu-idle-states = <&CPU_PW20>;
	#cooling-cells = <2>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	reg = <0x1>;
	enable-method = "psci";
	clocks = <&clockgen 1 0>;
	next-level-cache = <&l2>;
	cpu-idle-states = <&CPU_PW20>;
	#cooling-cells = <2>;
	};

	l2: l2-cache {
	compatible = "cache";
	};
	};

	idle-states {
	/*
	* PSCI node is not added default, U-boot will add missing
	* parts if it determines to use PSCI.
	*/
	entry-method = "psci";

	CPU_PW20: cpu-pw20 {
	compatible = "arm,idle-state";
	idle-state-name = "PW20";
	arm,psci-suspend-param = <0x0>;
	entry-latency-us = <2000>;
	exit-latency-us = <2000>;
	min-residency-us = <6000>;
	};
	};

	sysclk: clock-sysclk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <100000000>;
	clock-output-names = "sysclk";
	};

	osc_27m: clock-osc-27m {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <27000000>;
	clock-output-names = "phy_27m";
	};

	dpclk: clock-controller@f1f0000 {
	compatible = "fsl,ls1028a-plldig";
	reg = <0x0 0xf1f0000 0x0 0xffff>;
	#clock-cells = <0>;
	clocks = <&osc_27m>;
	};

	reboot {
	compatible ="syscon-reboot";
	regmap = <&rst>;
	offset = <0xb0>;
	mask = <0x02>;
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
	compatible = "arm,cortex-a72-pmu";
	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	gic: interrupt-controller@6000000 {
	compatible= "arm,gic-v3";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */
	<0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
	#interrupt-cells= <3>;
	interrupt-controller;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) \|
	IRQ_TYPE_LEVEL_LOW)>;
	its: gic-its@6020000 {
	compatible = "arm,gic-v3-its";
	msi-controller;
	reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
	};
	};

	thermal-zones {
	core-cluster {
	polling-delay-passive = <1000>;
	polling-delay = <5000>;
	thermal-sensors = <&tmu 0>;

	trips {
	core_cluster_alert: core-cluster-alert {
	temperature = <85000>;
	hysteresis = <2000>;
	type = "passive";
	};

	core_cluster_crit: core-cluster-crit {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&core_cluster_alert>;
	cooling-device =
	<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};
	};

	soc: soc {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	ddr: memory-controller@1080000 {
	compatible = "fsl,qoriq-memory-controller";
	reg = <0x0 0x1080000 0x0 0x1000>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	big-endian;
	};

	dcfg: syscon@1e00000 {
	compatible = "fsl,ls1028a-dcfg", "syscon";
	reg = <0x0 0x1e00000 0x0 0x10000>;
	little-endian;
	};

	rst: syscon@1e60000 {
	compatible = "syscon";
	reg = <0x0 0x1e60000 0x0 0x10000>;
	little-endian;
	};

	scfg: syscon@1fc0000 {
	compatible = "fsl,ls1028a-scfg", "syscon";
	reg = <0x0 0x1fc0000 0x0 0x10000>;
	big-endian;
	};

	clockgen: clock-controller@1300000 {
	compatible = "fsl,ls1028a-clockgen";
	reg = <0x0 0x1300000 0x0 0xa0000>;
	#clock-cells = <2>;
	clocks = <&sysclk>;
	};

	i2c0: i2c@2000000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2000000 0x0 0x10000>;
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	status = "disabled";
	};

	i2c1: i2c@2010000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2010000 0x0 0x10000>;
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	status = "disabled";
	};

	i2c2: i2c@2020000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2020000 0x0 0x10000>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	status = "disabled";
	};

	i2c3: i2c@2030000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2030000 0x0 0x10000>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	status = "disabled";
	};

	i2c4: i2c@2040000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2040000 0x0 0x10000>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	status = "disabled";
	};

	i2c5: i2c@2050000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2050000 0x0 0x10000>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	status = "disabled";
	};

	i2c6: i2c@2060000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2060000 0x0 0x10000>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	status = "disabled";
	};

	i2c7: i2c@2070000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2070000 0x0 0x10000>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	status = "disabled";
	};

	fspi: spi@20c0000 {
	compatible = "nxp,lx2160a-fspi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x20c0000 0x0 0x10000>,
	<0x0 0x20000000 0x0 0x10000000>;
	reg-names = "fspi_base", "fspi_mmap";
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "fspi_en", "fspi";
	status = "disabled";
	};

	+ dspi0: spi@2100000 {
	+ compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ reg = <0x0 0x2100000 0x0 0x10000>;
	+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	+ clock-names = "dspi";
	+ clocks = <&clockgen 4 1>;
	+ spi-num-chipselects = <4>;
	+ little-endian;
	+ status = "disabled";
	+ };
	+
	+ dspi1: spi@2110000 {
	+ compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ reg = <0x0 0x2110000 0x0 0x10000>;
	+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	+ clock-names = "dspi";
	+ clocks = <&clockgen 4 1>;
	+ spi-num-chipselects = <4>;
	+ little-endian;
	+ status = "disabled";
	+ };
	+
	+ dspi2: spi@2120000 {
	+ compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ reg = <0x0 0x2120000 0x0 0x10000>;
	+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	+ clock-names = "dspi";
	+ clocks = <&clockgen 4 1>;
	+ spi-num-chipselects = <3>;
	+ little-endian;
	+ status = "disabled";
	+ };
	+
	esdhc: mmc@2140000 {
	compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
	reg = <0x0 0x2140000 0x0 0x10000>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <0>; /* fixed up by bootloader */
	clocks = <&clockgen 2 1>;
	voltage-ranges = <1800 1800 3300 3300>;
	sdhci,auto-cmd12;
	little-endian;
	bus-width = <4>;
	status = "disabled";
	};

	esdhc1: mmc@2150000 {
	compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
	reg = <0x0 0x2150000 0x0 0x10000>;
	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <0>; /* fixed up by bootloader */
	clocks = <&clockgen 2 1>;
	voltage-ranges = <1800 1800 3300 3300>;
	sdhci,auto-cmd12;
	broken-cd;
	little-endian;
	bus-width = <4>;
	status = "disabled";
	};

	duart0: serial@21c0500 {
	compatible = "fsl,ns16550", "ns16550a";
	reg = <0x00 0x21c0500 0x0 0x100>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 1>;
	status = "disabled";
	};

	duart1: serial@21c0600 {
	compatible = "fsl,ns16550", "ns16550a";
	reg = <0x00 0x21c0600 0x0 0x100>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 1>;
	status = "disabled";
	};

	+
	+ lpuart0: serial@2260000 {
	+ compatible = "fsl,ls1028a-lpuart";
	+ reg = <0x0 0x2260000 0x0 0x1000>;
	+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clockgen 4 1>;
	+ clock-names = "ipg";
	+ dma-names = "rx","tx";
	+ dmas = <&edma0 1 32>,
	+ <&edma0 1 33>;
	+ status = "disabled";
	+ };
	+
	+ lpuart1: serial@2270000 {
	+ compatible = "fsl,ls1028a-lpuart";
	+ reg = <0x0 0x2270000 0x0 0x1000>;
	+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clockgen 4 1>;
	+ clock-names = "ipg";
	+ dma-names = "rx","tx";
	+ dmas = <&edma0 1 30>,
	+ <&edma0 1 31>;
	+ status = "disabled";
	+ };
	+
	+ lpuart2: serial@2280000 {
	+ compatible = "fsl,ls1028a-lpuart";
	+ reg = <0x0 0x2280000 0x0 0x1000>;
	+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clockgen 4 1>;
	+ clock-names = "ipg";
	+ dma-names = "rx","tx";
	+ dmas = <&edma0 1 28>,
	+ <&edma0 1 29>;
	+ status = "disabled";
	+ };
	+
	+ lpuart3: serial@2290000 {
	+ compatible = "fsl,ls1028a-lpuart";
	+ reg = <0x0 0x2290000 0x0 0x1000>;
	+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clockgen 4 1>;
	+ clock-names = "ipg";
	+ dma-names = "rx","tx";
	+ dmas = <&edma0 1 26>,
	+ <&edma0 1 27>;
	+ status = "disabled";
	+ };
	+
	+ lpuart4: serial@22a0000 {
	+ compatible = "fsl,ls1028a-lpuart";
	+ reg = <0x0 0x22a0000 0x0 0x1000>;
	+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clockgen 4 1>;
	+ clock-names = "ipg";
	+ dma-names = "rx","tx";
	+ dmas = <&edma0 1 24>,
	+ <&edma0 1 25>;
	+ status = "disabled";
	+ };
	+
	+ lpuart5: serial@22b0000 {
	+ compatible = "fsl,ls1028a-lpuart";
	+ reg = <0x0 0x22b0000 0x0 0x1000>;
	+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clockgen 4 1>;
	+ clock-names = "ipg";
	+ dma-names = "rx","tx";
	+ dmas = <&edma0 1 22>,
	+ <&edma0 1 23>;
	+ status = "disabled";
	+ };
	+
	edma0: dma-controller@22c0000 {
	#dma-cells = <2>;
	- compatible = "fsl,ls1028a-edma";
	+ compatible = "fsl,ls1028a-edma", "fsl,vf610-edma";
	reg = <0x0 0x22c0000 0x0 0x10000>,
	<0x0 0x22d0000 0x0 0x10000>,
	<0x0 0x22e0000 0x0 0x10000>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "edma-tx", "edma-err";
	dma-channels = <32>;
	clock-names = "dmamux0", "dmamux1";
	clocks = <&clockgen 4 1>,
	<&clockgen 4 1>;
	};

	gpio1: gpio@2300000 {
	compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
	reg = <0x0 0x2300000 0x0 0x10000>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	little-endian;
	};

	gpio2: gpio@2310000 {
	compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
	reg = <0x0 0x2310000 0x0 0x10000>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	little-endian;
	};

	gpio3: gpio@2320000 {
	compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
	reg = <0x0 0x2320000 0x0 0x10000>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	little-endian;
	};

	usb0: usb@3100000 {
	compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
	reg = <0x0 0x3100000 0x0 0x10000>;
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	dr_mode = "host";
	snps,dis_rxdet_inp3_quirk;
	snps,quirk-frame-length-adjustment = <0x20>;
	snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
	};

	usb1: usb@3110000 {
	compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
	reg = <0x0 0x3110000 0x0 0x10000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	dr_mode = "host";
	snps,dis_rxdet_inp3_quirk;
	snps,quirk-frame-length-adjustment = <0x20>;
	snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
	};

	sata: sata@3200000 {
	compatible = "fsl,ls1028a-ahci";
	reg = <0x0 0x3200000 0x0 0x10000>,
	<0x7 0x100520 0x0 0x4>;
	reg-names = "ahci", "sata-ecc";
	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 1>;
	status = "disabled";
	};

	+ pcie@3400000 {
	+ compatible = "fsl,ls1028a-pcie";
	+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
	+ 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
	+ reg-names = "regs", "config";
	+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
	+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
	+ interrupt-names = "pme", "aer";
	+ #address-cells = <3>;
	+ #size-cells = <2>;
	+ device_type = "pci";
	+ dma-coherent;
	+ num-viewport = <8>;
	+ bus-range = <0x0 0xff>;
	+ ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
	+ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	+ msi-parent = <&its>;
	+ #interrupt-cells = <1>;
	+ interrupt-map-mask = <0 0 0 7>;
	+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	+ status = "disabled";
	+ };
	+
	+ pcie@3500000 {
	+ compatible = "fsl,ls1028a-pcie";
	+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
	+ 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
	+ reg-names = "regs", "config";
	+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	+ interrupt-names = "pme", "aer";
	+ #address-cells = <3>;
	+ #size-cells = <2>;
	+ device_type = "pci";
	+ dma-coherent;
	+ num-viewport = <8>;
	+ bus-range = <0x0 0xff>;
	+ ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
	+ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	+ msi-parent = <&its>;
	+ #interrupt-cells = <1>;
	+ interrupt-map-mask = <0 0 0 7>;
	+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	+ status = "disabled";
	+ };
	+
	smmu: iommu@5000000 {
	compatible = "arm,mmu-500";
	reg = <0 0x5000000 0 0x800000>;
	#global-interrupts = <8>;
	#iommu-cells = <1>;
	stream-match-mask = <0x7c00>;
	/* global secure fault */
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	/* combined secure interrupt */
	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	/* global non-secure fault */
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	/* combined non-secure interrupt */
	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	/* performance counter interrupts 0-7 */
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	/* per context interrupt, 64 interrupts */
	<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
	};

	crypto: crypto@8000000 {
	compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
	fsl,sec-era = <10>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x00 0x8000000 0x100000>;
	reg = <0x00 0x8000000 0x0 0x100000>;
	interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
	dma-coherent;

	sec_jr0: jr@10000 {
	compatible = "fsl,sec-v5.0-job-ring",
	"fsl,sec-v4.0-job-ring";
	reg = <0x10000 0x10000>;
	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
	};

	sec_jr1: jr@20000 {
	compatible = "fsl,sec-v5.0-job-ring",
	"fsl,sec-v4.0-job-ring";
	reg = <0x20000 0x10000>;
	interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
	};

	sec_jr2: jr@30000 {
	compatible = "fsl,sec-v5.0-job-ring",
	"fsl,sec-v4.0-job-ring";
	reg = <0x30000 0x10000>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
	};

	sec_jr3: jr@40000 {
	compatible = "fsl,sec-v5.0-job-ring",
	"fsl,sec-v4.0-job-ring";
	reg = <0x40000 0x10000>;
	interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	qdma: dma-controller@8380000 {
	compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma";
	reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
	<0x0 0x8390000 0x0 0x10000>, /* Status regs */
	<0x0 0x83a0000 0x0 0x40000>; /* Block regs */
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "qdma-error", "qdma-queue0",
	"qdma-queue1", "qdma-queue2", "qdma-queue3";
	dma-channels = <8>;
	block-number = <1>;
	block-offset = <0x10000>;
	fsl,dma-queues = <2>;
	status-sizes = <64>;
	queue-sizes = <64 64>;
	};

	cluster1_core0_watchdog: watchdog@c000000 {
	compatible = "arm,sp805", "arm,primecell";
	reg = <0x0 0xc000000 0x0 0x1000>;
	clocks = <&clockgen 4 15>, <&clockgen 4 15>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	cluster1_core1_watchdog: watchdog@c010000 {
	compatible = "arm,sp805", "arm,primecell";
	reg = <0x0 0xc010000 0x0 0x1000>;
	clocks = <&clockgen 4 15>, <&clockgen 4 15>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	sai1: audio-controller@f100000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,vf610-sai";
	reg = <0x0 0xf100000 0x0 0x10000>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 1>, <&clockgen 4 1>,
	<&clockgen 4 1>, <&clockgen 4 1>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dma-names = "tx", "rx";
	dmas = <&edma0 1 4>,
	<&edma0 1 3>;
	fsl,sai-asynchronous;
	status = "disabled";
	};

	sai2: audio-controller@f110000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,vf610-sai";
	reg = <0x0 0xf110000 0x0 0x10000>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 1>, <&clockgen 4 1>,
	<&clockgen 4 1>, <&clockgen 4 1>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dma-names = "tx", "rx";
	dmas = <&edma0 1 6>,
	<&edma0 1 5>;
	fsl,sai-asynchronous;
	status = "disabled";
	};

	sai3: audio-controller@f120000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,vf610-sai";
	reg = <0x0 0xf120000 0x0 0x10000>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 1>, <&clockgen 4 1>,
	<&clockgen 4 1>, <&clockgen 4 1>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dma-names = "tx", "rx";
	dmas = <&edma0 1 8>,
	<&edma0 1 7>;
	fsl,sai-asynchronous;
	status = "disabled";
	};

	sai4: audio-controller@f130000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,vf610-sai";
	reg = <0x0 0xf130000 0x0 0x10000>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 1>, <&clockgen 4 1>,
	<&clockgen 4 1>, <&clockgen 4 1>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dma-names = "tx", "rx";
	dmas = <&edma0 1 10>,
	<&edma0 1 9>;
	fsl,sai-asynchronous;
	status = "disabled";
	};

	sai5: audio-controller@f140000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,vf610-sai";
	reg = <0x0 0xf140000 0x0 0x10000>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 1>, <&clockgen 4 1>,
	<&clockgen 4 1>, <&clockgen 4 1>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dma-names = "tx", "rx";
	dmas = <&edma0 1 12>,
	<&edma0 1 11>;
	fsl,sai-asynchronous;
	status = "disabled";
	};

	sai6: audio-controller@f150000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,vf610-sai";
	reg = <0x0 0xf150000 0x0 0x10000>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 1>, <&clockgen 4 1>,
	<&clockgen 4 1>, <&clockgen 4 1>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dma-names = "tx", "rx";
	dmas = <&edma0 1 14>,
	<&edma0 1 13>;
	fsl,sai-asynchronous;
	status = "disabled";
	};

	tmu: tmu@1f80000 {
	compatible = "fsl,qoriq-tmu";
	reg = <0x0 0x1f80000 0x0 0x10000>;
	interrupts = <0 23 0x4>;
	fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
	fsl,tmu-calibration = <0x00000000 0x00000024
	0x00000001 0x0000002b
	0x00000002 0x00000031
	0x00000003 0x00000038
	0x00000004 0x0000003f
	0x00000005 0x00000045
	0x00000006 0x0000004c
	0x00000007 0x00000053
	0x00000008 0x00000059
	0x00000009 0x00000060
	0x0000000a 0x00000066
	0x0000000b 0x0000006d

	0x00010000 0x0000001c
	0x00010001 0x00000024
	0x00010002 0x0000002c
	0x00010003 0x00000035
	0x00010004 0x0000003d
	0x00010005 0x00000045
	0x00010006 0x0000004d
	0x00010007 0x00000055
	0x00010008 0x0000005e
	0x00010009 0x00000066
	0x0001000a 0x0000006e

	0x00020000 0x00000018
	0x00020001 0x00000022
	0x00020002 0x0000002d
	0x00020003 0x00000038
	0x00020004 0x00000043
	0x00020005 0x0000004d
	0x00020006 0x00000058
	0x00020007 0x00000063
	0x00020008 0x0000006e

	0x00030000 0x00000010
	0x00030001 0x0000001c
	0x00030002 0x00000029
	0x00030003 0x00000036
	0x00030004 0x00000042
	0x00030005 0x0000004f
	0x00030006 0x0000005b
	0x00030007 0x00000068>;
	little-endian;
	#thermal-sensor-cells = <1>;
	};

	pcie@1f0000000 { /* Integrated Endpoint Root Complex */
	compatible = "pci-host-ecam-generic";
	reg = <0x01 0xf0000000 0x0 0x100000>;
	#address-cells = <3>;
	#size-cells = <2>;
	- #interrupt-cells = <1>;
	msi-parent = <&its>;
	device_type = "pci";
	bus-range = <0x0 0x0>;
	dma-coherent;
	msi-map = <0 &its 0x17 0xe>;
	iommu-map = <0 &smmu 0x17 0xe>;
	/* PF0-6 BAR0 - non-prefetchable memory */
	ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000
	/* PF0-6 BAR2 - prefetchable memory */
	0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000
	/* PF0: VF0-1 BAR0 - non-prefetchable memory */
	0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000
	/* PF0: VF0-1 BAR2 - prefetchable memory */
	0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000
	/* PF1: VF0-1 BAR0 - non-prefetchable memory */
	0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000
	/* PF1: VF0-1 BAR2 - prefetchable memory */
	- 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>;
	+ 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000
	+ /* BAR4 (PF5) - non-prefetchable memory */
	+ 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>;

	enetc_port0: ethernet@0,0 {
	compatible = "fsl,enetc";
	reg = <0x000000 0 0 0 0>;
	+ status = "disabled";
	};
	+
	enetc_port1: ethernet@0,1 {
	compatible = "fsl,enetc";
	reg = <0x000100 0 0 0 0>;
	+ status = "disabled";
	+ };
	+
	+ enetc_port2: ethernet@0,2 {
	+ compatible = "fsl,enetc";
	+ reg = <0x000200 0 0 0 0>;
	+ phy-mode = "internal";
	+ status = "disabled";
	+
	+ fixed-link {
	+ speed = <1000>;
	+ full-duplex;
	+ };
	};
	+
	enetc_mdio_pf3: mdio@0,3 {
	compatible = "fsl,enetc-mdio";
	reg = <0x000300 0 0 0 0>;
	#address-cells = <1>;
	#size-cells = <0>;
	};
	+
	ethernet@0,4 {
	compatible = "fsl,enetc-ptp";
	reg = <0x000400 0 0 0 0>;
	clocks = <&clockgen 4 0>;
	little-endian;
	+ fsl,extts-fifo;
	+ };
	+
	+ mscc_felix: ethernet-switch@0,5 {
	+ reg = <0x000500 0 0 0 0>;
	+ /* IEP INT_B */
	+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	+ status = "disabled";
	+
	+ ports {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ /* External ports */
	+ mscc_felix_port0: port@0 {
	+ reg = <0>;
	+ status = "disabled";
	+ };
	+
	+ mscc_felix_port1: port@1 {
	+ reg = <1>;
	+ status = "disabled";
	+ };
	+
	+ mscc_felix_port2: port@2 {
	+ reg = <2>;
	+ status = "disabled";
	+ };
	+
	+ mscc_felix_port3: port@3 {
	+ reg = <3>;
	+ status = "disabled";
	+ };
	+
	+ /* Internal ports */
	+ mscc_felix_port4: port@4 {
	+ reg = <4>;
	+ phy-mode = "internal";
	+ status = "disabled";
	+
	+ fixed-link {
	+ speed = <2500>;
	+ full-duplex;
	+ };
	+ };
	+
	+ mscc_felix_port5: port@5 {
	+ reg = <5>;
	+ phy-mode = "internal";
	+ status = "disabled";
	+
	+ fixed-link {
	+ speed = <1000>;
	+ full-duplex;
	+ };
	+ };
	+ };
	+ };
	+
	+ enetc_port3: ethernet@0,6 {
	+ compatible = "fsl,enetc";
	+ reg = <0x000600 0 0 0 0>;
	+ phy-mode = "internal";
	+ status = "disabled";
	+
	+ fixed-link {
	+ speed = <1000>;
	+ full-duplex;
	+ };
	};
	};
	};

	malidp0: display@f080000 {
	compatible = "arm,mali-dp500";
	reg = <0x0 0xf080000 0x0 0x10000>;
	interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
	<0 223 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "DE", "SE";
	clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>,
	<&clockgen 2 2>;
	clock-names = "pxlclk", "mclk", "aclk", "pclk";
	arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
	arm,malidp-arqos-value = <0xd000d000>;

	port {
	dp0_out: endpoint {

	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1088a-rdb.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1088a-rdb.dts
	index 4d77b345cebd..5633e59febc3 100644
	--- a/sys/gnu/dts/arm64/freescale/fsl-ls1088a-rdb.dts
	+++ b/sys/gnu/dts/arm64/freescale/fsl-ls1088a-rdb.dts
	@@ -1,124 +1,125 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Device Tree file for NXP LS1088A RDB Board.
	*
	* Copyright 2017 NXP
	*
	* Harninder Rai <harninder.rai@nxp.com>
	*
	*/

	/dts-v1/;

	#include "fsl-ls1088a.dtsi"

	/ {
	model = "LS1088A RDB Board";
	compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
	};

	&i2c0 {
	status = "okay";

	i2c-switch@77 {
	compatible = "nxp,pca9547";
	reg = <0x77>;
	#address-cells = <1>;
	#size-cells = <0>;

	i2c@2 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x2>;

	ina220@40 {
	compatible = "ti,ina220";
	reg = <0x40>;
	shunt-resistor = <1000>;
	};
	};

	i2c@3 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x3>;

	temp-sensor@4c {
	compatible = "adi,adt7461a";
	reg = <0x4c>;
	};

	rtc@51 {
	compatible = "nxp,pcf2129";
	reg = <0x51>;
	/* IRQ10_B */
	interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
	};
	};
	};
	};

	&ifc {
	ranges = <0 0 0x5 0x30000000 0x00010000
	2 0 0x5 0x20000000 0x00010000>;
	status = "okay";

	nand@0,0 {
	compatible = "fsl,ifc-nand";
	reg = <0x0 0x0 0x10000>;
	};

	fpga: board-control@2,0 {
	compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
	reg = <0x2 0x0 0x0000100>;
	};
	};

	&duart0 {
	status = "okay";
	};

	&duart1 {
	status = "okay";
	};

	&esdhc {
	+ mmc-hs200-1_8v;
	status = "okay";
	};

	&qspi {
	status = "okay";

	s25fs512s0: flash@0 {
	compatible = "jedec,spi-nor";
	#address-cells = <1>;
	#size-cells = <1>;
	spi-max-frequency = <50000000>;
	spi-rx-bus-width = <4>;
	spi-tx-bus-width = <1>;
	reg = <0>;
	};

	s25fs512s1: flash@1 {
	compatible = "jedec,spi-nor";
	#address-cells = <1>;
	#size-cells = <1>;
	spi-max-frequency = <50000000>;
	spi-rx-bus-width = <4>;
	spi-tx-bus-width = <1>;
	reg = <1>;
	};
	};

	&sata {
	status = "okay";
	};

	&usb0 {
	status = "okay";
	};

	&usb1 {
	dr_mode = "otg";
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1088a.dtsi b/sys/gnu/dts/arm64/freescale/fsl-ls1088a.dtsi
	index 594566265e3d..36a799554620 100644
	--- a/sys/gnu/dts/arm64/freescale/fsl-ls1088a.dtsi
	+++ b/sys/gnu/dts/arm64/freescale/fsl-ls1088a.dtsi
	@@ -1,788 +1,792 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Device Tree Include file for NXP Layerscape-1088A family SoC.
	*
	* Copyright 2017 NXP
	*
	* Harninder Rai <harninder.rai@nxp.com>
	*
	*/
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	compatible = "fsl,ls1088a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	crypto = &crypto;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	/* We have 2 clusters having 4 Cortex-A53 cores each */
	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0>;
	clocks = <&clockgen 1 0>;
	cpu-idle-states = <&CPU_PH20>;
	#cooling-cells = <2>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x1>;
	clocks = <&clockgen 1 0>;
	cpu-idle-states = <&CPU_PH20>;
	#cooling-cells = <2>;
	};

	cpu2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x2>;
	clocks = <&clockgen 1 0>;
	cpu-idle-states = <&CPU_PH20>;
	#cooling-cells = <2>;
	};

	cpu3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x3>;
	clocks = <&clockgen 1 0>;
	cpu-idle-states = <&CPU_PH20>;
	#cooling-cells = <2>;
	};

	cpu4: cpu@100 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x100>;
	clocks = <&clockgen 1 1>;
	cpu-idle-states = <&CPU_PH20>;
	#cooling-cells = <2>;
	};

	cpu5: cpu@101 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x101>;
	clocks = <&clockgen 1 1>;
	cpu-idle-states = <&CPU_PH20>;
	#cooling-cells = <2>;
	};

	cpu6: cpu@102 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x102>;
	clocks = <&clockgen 1 1>;
	cpu-idle-states = <&CPU_PH20>;
	#cooling-cells = <2>;
	};

	cpu7: cpu@103 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x103>;
	clocks = <&clockgen 1 1>;
	cpu-idle-states = <&CPU_PH20>;
	#cooling-cells = <2>;
	};

	CPU_PH20: cpu-ph20 {
	compatible = "arm,idle-state";
	idle-state-name = "PH20";
	arm,psci-suspend-param = <0x0>;
	entry-latency-us = <1000>;
	exit-latency-us = <1000>;
	min-residency-us = <3000>;
	};
	};

	gic: interrupt-controller@6000000 {
	compatible = "arm,gic-v3";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
	<0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
	<0x0 0x0c0c0000 0 0x2000>, /* GICC */
	<0x0 0x0c0d0000 0 0x1000>, /* GICH */
	<0x0 0x0c0e0000 0 0x20000>; /* GICV */
	interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	its: gic-its@6020000 {
	compatible = "arm,gic-v3-its";
	msi-controller;
	reg = <0x0 0x6020000 0 0x20000>;
	};
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	polling-delay-passive = <1000>;
	polling-delay = <5000>;
	thermal-sensors = <&tmu 0>;

	trips {
	cpu_alert: cpu-alert {
	temperature = <85000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu_crit: cpu-crit {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu_alert>;
	cooling-device =
	<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
	<1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
	<1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
	<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	sysclk: sysclk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <100000000>;
	clock-output-names = "sysclk";
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;

	clockgen: clocking@1300000 {
	compatible = "fsl,ls1088a-clockgen";
	reg = <0 0x1300000 0 0xa0000>;
	#clock-cells = <2>;
	clocks = <&sysclk>;
	};

	dcfg: dcfg@1e00000 {
	compatible = "fsl,ls1088a-dcfg", "syscon";
	reg = <0x0 0x1e00000 0x0 0x10000>;
	little-endian;
	};

	tmu: tmu@1f80000 {
	compatible = "fsl,qoriq-tmu";
	reg = <0x0 0x1f80000 0x0 0x10000>;
	interrupts = <0 23 0x4>;
	fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
	fsl,tmu-calibration =
	/* Calibration data group 1 */
	<0x00000000 0x00000026
	0x00000001 0x0000002d
	0x00000002 0x00000032
	0x00000003 0x00000039
	0x00000004 0x0000003f
	0x00000005 0x00000046
	0x00000006 0x0000004d
	0x00000007 0x00000054
	0x00000008 0x0000005a
	0x00000009 0x00000061
	0x0000000a 0x0000006a
	0x0000000b 0x00000071
	/* Calibration data group 2 */
	0x00010000 0x00000025
	0x00010001 0x0000002c
	0x00010002 0x00000035
	0x00010003 0x0000003d
	0x00010004 0x00000045
	0x00010005 0x0000004e
	0x00010006 0x00000057
	0x00010007 0x00000061
	0x00010008 0x0000006b
	0x00010009 0x00000076
	/* Calibration data group 3 */
	0x00020000 0x00000029
	0x00020001 0x00000033
	0x00020002 0x0000003d
	0x00020003 0x00000049
	0x00020004 0x00000056
	0x00020005 0x00000061
	0x00020006 0x0000006d
	/* Calibration data group 4 */
	0x00030000 0x00000021
	0x00030001 0x0000002a
	0x00030002 0x0000003c
	0x00030003 0x0000004e>;
	little-endian;
	#thermal-sensor-cells = <1>;
	};

	dspi: spi@2100000 {
	compatible = "fsl,ls1088a-dspi",
	"fsl,ls1021a-v1.0-dspi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2100000 0x0 0x10000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "dspi";
	clocks = <&clockgen 4 1>;
	spi-num-chipselects = <6>;
	status = "disabled";
	};

	duart0: serial@21c0500 {
	compatible = "fsl,ns16550", "ns16550a";
	reg = <0x0 0x21c0500 0x0 0x100>;
	clocks = <&clockgen 4 3>;
	interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	duart1: serial@21c0600 {
	compatible = "fsl,ns16550", "ns16550a";
	reg = <0x0 0x21c0600 0x0 0x100>;
	clocks = <&clockgen 4 3>;
	interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	gpio0: gpio@2300000 {
	compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
	reg = <0x0 0x2300000 0x0 0x10000>;
	interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
	little-endian;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio1: gpio@2310000 {
	compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
	reg = <0x0 0x2310000 0x0 0x10000>;
	interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
	little-endian;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio@2320000 {
	compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
	reg = <0x0 0x2320000 0x0 0x10000>;
	interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
	little-endian;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio@2330000 {
	compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
	reg = <0x0 0x2330000 0x0 0x10000>;
	interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
	little-endian;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	ifc: ifc@2240000 {
	compatible = "fsl,ifc", "simple-bus";
	reg = <0x0 0x2240000 0x0 0x20000>;
	interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
	little-endian;
	#address-cells = <2>;
	#size-cells = <1>;
	status = "disabled";
	};

	i2c0: i2c@2000000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2000000 0x0 0x10000>;
	interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 7>;
	status = "disabled";
	};

	i2c1: i2c@2010000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2010000 0x0 0x10000>;
	interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 7>;
	status = "disabled";
	};

	i2c2: i2c@2020000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2020000 0x0 0x10000>;
	interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 7>;
	status = "disabled";
	};

	i2c3: i2c@2030000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2030000 0x0 0x10000>;
	interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 7>;
	status = "disabled";
	};

	qspi: spi@20c0000 {
	compatible = "fsl,ls2080a-qspi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x20c0000 0x0 0x10000>,
	<0x0 0x20000000 0x0 0x10000000>;
	reg-names = "QuadSPI", "QuadSPI-memory";
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "qspi_en", "qspi";
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	status = "disabled";
	};

	esdhc: esdhc@2140000 {
	compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
	reg = <0x0 0x2140000 0x0 0x10000>;
	interrupts = <0 28 0x4>; /* Level high type */
	clock-frequency = <0>;
	+ clocks = <&clockgen 2 1>;
	voltage-ranges = <1800 1800 3300 3300>;
	sdhci,auto-cmd12;
	little-endian;
	bus-width = <4>;
	status = "disabled";
	};

	usb0: usb3@3100000 {
	compatible = "snps,dwc3";
	reg = <0x0 0x3100000 0x0 0x10000>;
	interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
	dr_mode = "host";
	snps,quirk-frame-length-adjustment = <0x20>;
	snps,dis_rxdet_inp3_quirk;
	snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
	status = "disabled";
	};

	usb1: usb3@3110000 {
	compatible = "snps,dwc3";
	reg = <0x0 0x3110000 0x0 0x10000>;
	interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
	dr_mode = "host";
	snps,quirk-frame-length-adjustment = <0x20>;
	snps,dis_rxdet_inp3_quirk;
	status = "disabled";
	};

	sata: sata@3200000 {
	compatible = "fsl,ls1088a-ahci";
	reg = <0x0 0x3200000 0x0 0x10000>,
	<0x7 0x100520 0x0 0x4>;
	reg-names = "ahci", "sata-ecc";
	interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	dma-coherent;
	status = "disabled";
	};

	crypto: crypto@8000000 {
	compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
	fsl,sec-era = <8>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x00 0x8000000 0x100000>;
	reg = <0x00 0x8000000 0x0 0x100000>;
	interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
	dma-coherent;

	sec_jr0: jr@10000 {
	compatible = "fsl,sec-v5.0-job-ring",
	"fsl,sec-v4.0-job-ring";
	reg = <0x10000 0x10000>;
	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
	};

	sec_jr1: jr@20000 {
	compatible = "fsl,sec-v5.0-job-ring",
	"fsl,sec-v4.0-job-ring";
	reg = <0x20000 0x10000>;
	interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
	};

	sec_jr2: jr@30000 {
	compatible = "fsl,sec-v5.0-job-ring",
	"fsl,sec-v4.0-job-ring";
	reg = <0x30000 0x10000>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
	};

	sec_jr3: jr@40000 {
	compatible = "fsl,sec-v5.0-job-ring",
	"fsl,sec-v4.0-job-ring";
	reg = <0x40000 0x10000>;
	interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	pcie@3400000 {
	compatible = "fsl,ls1088a-pcie";
	reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
	0x20 0x00000000 0x0 0x00002000>; /* configuration space */
	reg-names = "regs", "config";
	interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
	interrupt-names = "aer";
	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	dma-coherent;
	num-viewport = <256>;
	bus-range = <0x0 0xff>;
	ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
	0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	msi-parent = <&its>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
	<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
	<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
	<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	status = "disabled";
	};

	pcie@3500000 {
	compatible = "fsl,ls1088a-pcie";
	reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
	0x28 0x00000000 0x0 0x00002000>; /* configuration space */
	reg-names = "regs", "config";
	interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
	interrupt-names = "aer";
	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	dma-coherent;
	num-viewport = <6>;
	bus-range = <0x0 0xff>;
	ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
	0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	msi-parent = <&its>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
	<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
	<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
	<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	status = "disabled";
	};

	pcie@3600000 {
	compatible = "fsl,ls1088a-pcie";
	reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
	0x30 0x00000000 0x0 0x00002000>; /* configuration space */
	reg-names = "regs", "config";
	interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
	interrupt-names = "aer";
	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	dma-coherent;
	num-viewport = <6>;
	bus-range = <0x0 0xff>;
	ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
	0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	msi-parent = <&its>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
	<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
	<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
	<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	status = "disabled";
	};

	smmu: iommu@5000000 {
	compatible = "arm,mmu-500";
	reg = <0 0x5000000 0 0x800000>;
	#iommu-cells = <1>;
	stream-match-mask = <0x7C00>;
	#global-interrupts = <12>;
	// global secure fault
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	// combined secure
	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	// global non-secure fault
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	// combined non-secure
	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	// performance counter interrupts 0-7
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	// per context interrupt, 64 interrupts
	<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
	};

	console@8340020 {
	compatible = "fsl,dpaa2-console";
	reg = <0x00000000 0x08340020 0 0x2>;
	};

	ptp-timer@8b95000 {
	compatible = "fsl,dpaa2-ptp";
	reg = <0x0 0x8b95000 0x0 0x100>;
	clocks = <&clockgen 4 0>;
	little-endian;
	fsl,extts-fifo;
	};

	cluster1_core0_watchdog: wdt@c000000 {
	compatible = "arm,sp805-wdt", "arm,primecell";
	reg = <0x0 0xc000000 0x0 0x1000>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	cluster1_core1_watchdog: wdt@c010000 {
	compatible = "arm,sp805-wdt", "arm,primecell";
	reg = <0x0 0xc010000 0x0 0x1000>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	cluster1_core2_watchdog: wdt@c020000 {
	compatible = "arm,sp805-wdt", "arm,primecell";
	reg = <0x0 0xc020000 0x0 0x1000>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	cluster1_core3_watchdog: wdt@c030000 {
	compatible = "arm,sp805-wdt", "arm,primecell";
	reg = <0x0 0xc030000 0x0 0x1000>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	cluster2_core0_watchdog: wdt@c100000 {
	compatible = "arm,sp805-wdt", "arm,primecell";
	reg = <0x0 0xc100000 0x0 0x1000>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	cluster2_core1_watchdog: wdt@c110000 {
	compatible = "arm,sp805-wdt", "arm,primecell";
	reg = <0x0 0xc110000 0x0 0x1000>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	cluster2_core2_watchdog: wdt@c120000 {
	compatible = "arm,sp805-wdt", "arm,primecell";
	reg = <0x0 0xc120000 0x0 0x1000>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	cluster2_core3_watchdog: wdt@c130000 {
	compatible = "arm,sp805-wdt", "arm,primecell";
	reg = <0x0 0xc130000 0x0 0x1000>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	fsl_mc: fsl-mc@80c000000 {
	compatible = "fsl,qoriq-mc";
	reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
	<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
	msi-parent = <&its>;
	iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
	dma-coherent;
	#address-cells = <3>;
	#size-cells = <1>;

	/*
	* Region type 0x0 - MC portals
	* Region type 0x1 - QBMAN portals
	*/
	ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
	0x1 0x0 0x0 0x8 0x18000000 0x8000000>;

	dpmacs {
	#address-cells = <1>;
	#size-cells = <0>;

	dpmac1: dpmac@1 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <1>;
	};

	dpmac2: dpmac@2 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <2>;
	};

	dpmac3: dpmac@3 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <3>;
	};

	dpmac4: dpmac@4 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <4>;
	};

	dpmac5: dpmac@5 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <5>;
	};

	dpmac6: dpmac@6 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <6>;
	};

	dpmac7: dpmac@7 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <7>;
	};

	dpmac8: dpmac@8 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <8>;
	};

	dpmac9: dpmac@9 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <9>;
	};

	dpmac10: dpmac@a {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0xa>;
	};
	};
	};
	};

	firmware {
	optee {
	compatible = "linaro,optee-tz";
	method = "smc";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls208xa.dtsi b/sys/gnu/dts/arm64/freescale/fsl-ls208xa.dtsi
	index f96d06da96be..3944ef16ec60 100644
	--- a/sys/gnu/dts/arm64/freescale/fsl-ls208xa.dtsi
	+++ b/sys/gnu/dts/arm64/freescale/fsl-ls208xa.dtsi
	@@ -1,784 +1,788 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Device Tree Include file for Freescale Layerscape-2080A family SoC.
	*
	* Copyright 2016 Freescale Semiconductor, Inc.
	* Copyright 2017 NXP
	*
	* Abhimanyu Saini <abhimanyu.saini@nxp.com>
	*
	*/

	#include <dt-bindings/thermal/thermal.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>

	/ {
	compatible = "fsl,ls2080a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	crypto = &crypto;
	serial0 = &serial0;
	serial1 = &serial1;
	serial2 = &serial2;
	serial3 = &serial3;
	};

	cpu: cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0x00000000 0x80000000 0 0x80000000>;
	/* DRAM space - 1, size : 2 GB DRAM */
	};

	sysclk: sysclk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <100000000>;
	clock-output-names = "sysclk";
	};

	gic: interrupt-controller@6000000 {
	compatible = "arm,gic-v3";
	reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
	<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
	<0x0 0x0c0c0000 0 0x2000>, /* GICC */
	<0x0 0x0c0d0000 0 0x1000>, /* GICH */
	<0x0 0x0c0e0000 0 0x20000>; /* GICV */
	#interrupt-cells = <3>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	interrupt-controller;
	interrupts = <1 9 0x4>;

	its: gic-its@6020000 {
	compatible = "arm,gic-v3-its";
	msi-controller;
	reg = <0x0 0x6020000 0 0x20000>;
	};
	};

	rstcr: syscon@1e60000 {
	compatible = "fsl,ls2080a-rstcr", "syscon";
	reg = <0x0 0x1e60000 0x0 0x4>;
	};

	reboot {
	compatible ="syscon-reboot";
	regmap = <&rstcr>;
	offset = <0x0>;
	mask = <0x2>;
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	polling-delay-passive = <1000>;
	polling-delay = <5000>;

	thermal-sensors = <&tmu 4>;

	trips {
	cpu_alert: cpu-alert {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu_crit: cpu-crit {
	temperature = <85000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu_alert>;
	cooling-device =
	<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
	<1 14 4>, /* Physical Non-Secure PPI, active-low */
	<1 11 4>, /* Virtual PPI, active-low */
	<1 10 4>; /* Hypervisor PPI, active-low */
	fsl,erratum-a008585;
	};

	pmu {
	compatible = "arm,armv8-pmuv3";
	interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;

	clockgen: clocking@1300000 {
	compatible = "fsl,ls2080a-clockgen";
	reg = <0 0x1300000 0 0xa0000>;
	#clock-cells = <2>;
	clocks = <&sysclk>;
	};

	dcfg: dcfg@1e00000 {
	compatible = "fsl,ls2080a-dcfg", "syscon";
	reg = <0x0 0x1e00000 0x0 0x10000>;
	little-endian;
	};

	tmu: tmu@1f80000 {
	compatible = "fsl,qoriq-tmu";
	reg = <0x0 0x1f80000 0x0 0x10000>;
	interrupts = <0 23 0x4>;
	fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
	fsl,tmu-calibration = <0x00000000 0x00000026
	0x00000001 0x0000002d
	0x00000002 0x00000032
	0x00000003 0x00000039
	0x00000004 0x0000003f
	0x00000005 0x00000046
	0x00000006 0x0000004d
	0x00000007 0x00000054
	0x00000008 0x0000005a
	0x00000009 0x00000061
	0x0000000a 0x0000006a
	0x0000000b 0x00000071

	0x00010000 0x00000025
	0x00010001 0x0000002c
	0x00010002 0x00000035
	0x00010003 0x0000003d
	0x00010004 0x00000045
	0x00010005 0x0000004e
	0x00010006 0x00000057
	0x00010007 0x00000061
	0x00010008 0x0000006b
	0x00010009 0x00000076

	0x00020000 0x00000029
	0x00020001 0x00000033
	0x00020002 0x0000003d
	0x00020003 0x00000049
	0x00020004 0x00000056
	0x00020005 0x00000061
	0x00020006 0x0000006d

	0x00030000 0x00000021
	0x00030001 0x0000002a
	0x00030002 0x0000003c
	0x00030003 0x0000004e>;
	little-endian;
	#thermal-sensor-cells = <1>;
	};

	serial0: serial@21c0500 {
	compatible = "fsl,ns16550", "ns16550a";
	reg = <0x0 0x21c0500 0x0 0x100>;
	clocks = <&clockgen 4 3>;
	interrupts = <0 32 0x4>; /* Level high type */
	};

	serial1: serial@21c0600 {
	compatible = "fsl,ns16550", "ns16550a";
	reg = <0x0 0x21c0600 0x0 0x100>;
	clocks = <&clockgen 4 3>;
	interrupts = <0 32 0x4>; /* Level high type */
	};

	serial2: serial@21d0500 {
	compatible = "fsl,ns16550", "ns16550a";
	reg = <0x0 0x21d0500 0x0 0x100>;
	clocks = <&clockgen 4 3>;
	interrupts = <0 33 0x4>; /* Level high type */
	};

	serial3: serial@21d0600 {
	compatible = "fsl,ns16550", "ns16550a";
	reg = <0x0 0x21d0600 0x0 0x100>;
	clocks = <&clockgen 4 3>;
	interrupts = <0 33 0x4>; /* Level high type */
	};

	cluster1_core0_watchdog: wdt@c000000 {
	compatible = "arm,sp805-wdt", "arm,primecell";
	reg = <0x0 0xc000000 0x0 0x1000>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	cluster1_core1_watchdog: wdt@c010000 {
	compatible = "arm,sp805-wdt", "arm,primecell";
	reg = <0x0 0xc010000 0x0 0x1000>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	cluster2_core0_watchdog: wdt@c100000 {
	compatible = "arm,sp805-wdt", "arm,primecell";
	reg = <0x0 0xc100000 0x0 0x1000>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	cluster2_core1_watchdog: wdt@c110000 {
	compatible = "arm,sp805-wdt", "arm,primecell";
	reg = <0x0 0xc110000 0x0 0x1000>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	cluster3_core0_watchdog: wdt@c200000 {
	compatible = "arm,sp805-wdt", "arm,primecell";
	reg = <0x0 0xc200000 0x0 0x1000>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	cluster3_core1_watchdog: wdt@c210000 {
	compatible = "arm,sp805-wdt", "arm,primecell";
	reg = <0x0 0xc210000 0x0 0x1000>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	cluster4_core0_watchdog: wdt@c300000 {
	compatible = "arm,sp805-wdt", "arm,primecell";
	reg = <0x0 0xc300000 0x0 0x1000>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	cluster4_core1_watchdog: wdt@c310000 {
	compatible = "arm,sp805-wdt", "arm,primecell";
	reg = <0x0 0xc310000 0x0 0x1000>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "apb_pclk", "wdog_clk";
	};

	crypto: crypto@8000000 {
	compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
	fsl,sec-era = <8>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x00 0x8000000 0x100000>;
	reg = <0x00 0x8000000 0x0 0x100000>;
	interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
	dma-coherent;

	sec_jr0: jr@10000 {
	compatible = "fsl,sec-v5.0-job-ring",
	"fsl,sec-v4.0-job-ring";
	reg = <0x10000 0x10000>;
	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
	};

	sec_jr1: jr@20000 {
	compatible = "fsl,sec-v5.0-job-ring",
	"fsl,sec-v4.0-job-ring";
	reg = <0x20000 0x10000>;
	interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
	};

	sec_jr2: jr@30000 {
	compatible = "fsl,sec-v5.0-job-ring",
	"fsl,sec-v4.0-job-ring";
	reg = <0x30000 0x10000>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
	};

	sec_jr3: jr@40000 {
	compatible = "fsl,sec-v5.0-job-ring",
	"fsl,sec-v4.0-job-ring";
	reg = <0x40000 0x10000>;
	interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	console@8340020 {
	compatible = "fsl,dpaa2-console";
	reg = <0x00000000 0x08340020 0 0x2>;
	};

	ptp-timer@8b95000 {
	compatible = "fsl,dpaa2-ptp";
	reg = <0x0 0x8b95000 0x0 0x100>;
	clocks = <&clockgen 4 1>;
	little-endian;
	fsl,extts-fifo;
	};

	fsl_mc: fsl-mc@80c000000 {
	compatible = "fsl,qoriq-mc";
	reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
	<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
	msi-parent = <&its>;
	iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
	dma-coherent;
	#address-cells = <3>;
	#size-cells = <1>;

	/*
	* Region type 0x0 - MC portals
	* Region type 0x1 - QBMAN portals
	*/
	ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
	0x1 0x0 0x0 0x8 0x18000000 0x8000000>;

	/*
	* Define the maximum number of MACs present on the SoC.
	*/
	dpmacs {
	#address-cells = <1>;
	#size-cells = <0>;

	dpmac1: dpmac@1 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x1>;
	};

	dpmac2: dpmac@2 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x2>;
	};

	dpmac3: dpmac@3 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x3>;
	};

	dpmac4: dpmac@4 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x4>;
	};

	dpmac5: dpmac@5 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x5>;
	};

	dpmac6: dpmac@6 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x6>;
	};

	dpmac7: dpmac@7 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x7>;
	};

	dpmac8: dpmac@8 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x8>;
	};

	dpmac9: dpmac@9 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x9>;
	};

	dpmac10: dpmac@a {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0xa>;
	};

	dpmac11: dpmac@b {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0xb>;
	};

	dpmac12: dpmac@c {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0xc>;
	};

	dpmac13: dpmac@d {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0xd>;
	};

	dpmac14: dpmac@e {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0xe>;
	};

	dpmac15: dpmac@f {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0xf>;
	};

	dpmac16: dpmac@10 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x10>;
	};
	};
	};

	smmu: iommu@5000000 {
	compatible = "arm,mmu-500";
	reg = <0 0x5000000 0 0x800000>;
	#global-interrupts = <12>;
	#iommu-cells = <1>;
	stream-match-mask = <0x7C00>;
	dma-coherent;
	interrupts = <0 13 4>, /* global secure fault */
	<0 14 4>, /* combined secure interrupt */
	<0 15 4>, /* global non-secure fault */
	<0 16 4>, /* combined non-secure interrupt */
	/* performance counter interrupts 0-7 */
	<0 211 4>, <0 212 4>,
	<0 213 4>, <0 214 4>,
	<0 215 4>, <0 216 4>,
	<0 217 4>, <0 218 4>,
	/* per context interrupt, 64 interrupts */
	<0 146 4>, <0 147 4>,
	<0 148 4>, <0 149 4>,
	<0 150 4>, <0 151 4>,
	<0 152 4>, <0 153 4>,
	<0 154 4>, <0 155 4>,
	<0 156 4>, <0 157 4>,
	<0 158 4>, <0 159 4>,
	<0 160 4>, <0 161 4>,
	<0 162 4>, <0 163 4>,
	<0 164 4>, <0 165 4>,
	<0 166 4>, <0 167 4>,
	<0 168 4>, <0 169 4>,
	<0 170 4>, <0 171 4>,
	<0 172 4>, <0 173 4>,
	<0 174 4>, <0 175 4>,
	<0 176 4>, <0 177 4>,
	<0 178 4>, <0 179 4>,
	<0 180 4>, <0 181 4>,
	<0 182 4>, <0 183 4>,
	<0 184 4>, <0 185 4>,
	<0 186 4>, <0 187 4>,
	<0 188 4>, <0 189 4>,
	<0 190 4>, <0 191 4>,
	<0 192 4>, <0 193 4>,
	<0 194 4>, <0 195 4>,
	<0 196 4>, <0 197 4>,
	<0 198 4>, <0 199 4>,
	<0 200 4>, <0 201 4>,
	<0 202 4>, <0 203 4>,
	<0 204 4>, <0 205 4>,
	<0 206 4>, <0 207 4>,
	<0 208 4>, <0 209 4>;
	};

	dspi: spi@2100000 {
	status = "disabled";
	compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2100000 0x0 0x10000>;
	interrupts = <0 26 0x4>; /* Level high type */
	clocks = <&clockgen 4 3>;
	clock-names = "dspi";
	spi-num-chipselects = <5>;
	bus-num = <0>;
	};

	esdhc: esdhc@2140000 {
	status = "disabled";
	compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
	reg = <0x0 0x2140000 0x0 0x10000>;
	interrupts = <0 28 0x4>; /* Level high type */
	clocks = <&clockgen 4 1>;
	voltage-ranges = <1800 1800 3300 3300>;
	sdhci,auto-cmd12;
	little-endian;
	bus-width = <4>;
	};

	gpio0: gpio@2300000 {
	compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
	reg = <0x0 0x2300000 0x0 0x10000>;
	interrupts = <0 36 0x4>; /* Level high type */
	gpio-controller;
	little-endian;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio1: gpio@2310000 {
	compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
	reg = <0x0 0x2310000 0x0 0x10000>;
	interrupts = <0 36 0x4>; /* Level high type */
	gpio-controller;
	little-endian;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio@2320000 {
	compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
	reg = <0x0 0x2320000 0x0 0x10000>;
	interrupts = <0 37 0x4>; /* Level high type */
	gpio-controller;
	little-endian;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio@2330000 {
	compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
	reg = <0x0 0x2330000 0x0 0x10000>;
	interrupts = <0 37 0x4>; /* Level high type */
	gpio-controller;
	little-endian;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	i2c0: i2c@2000000 {
	status = "disabled";
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2000000 0x0 0x10000>;
	interrupts = <0 34 0x4>; /* Level high type */
	clock-names = "i2c";
	clocks = <&clockgen 4 3>;
	};

	i2c1: i2c@2010000 {
	status = "disabled";
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2010000 0x0 0x10000>;
	interrupts = <0 34 0x4>; /* Level high type */
	clock-names = "i2c";
	clocks = <&clockgen 4 3>;
	};

	i2c2: i2c@2020000 {
	status = "disabled";
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2020000 0x0 0x10000>;
	interrupts = <0 35 0x4>; /* Level high type */
	clock-names = "i2c";
	clocks = <&clockgen 4 3>;
	};

	i2c3: i2c@2030000 {
	status = "disabled";
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2030000 0x0 0x10000>;
	interrupts = <0 35 0x4>; /* Level high type */
	clock-names = "i2c";
	clocks = <&clockgen 4 3>;
	};

	ifc: ifc@2240000 {
	compatible = "fsl,ifc", "simple-bus";
	reg = <0x0 0x2240000 0x0 0x20000>;
	interrupts = <0 21 0x4>; /* Level high type */
	little-endian;
	#address-cells = <2>;
	#size-cells = <1>;

	ranges = <0 0 0x5 0x80000000 0x08000000
	2 0 0x5 0x30000000 0x00010000
	3 0 0x5 0x20000000 0x00010000>;
	};

	qspi: spi@20c0000 {
	compatible = "fsl,ls2080a-qspi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x20c0000 0x0 0x10000>,
	<0x0 0x20000000 0x0 0x10000000>;
	reg-names = "QuadSPI", "QuadSPI-memory";
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "qspi_en", "qspi";
	status = "disabled";
	};

	pcie1: pcie@3400000 {
	compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
	reg-names = "regs", "config";
	interrupts = <0 108 0x4>; /* Level high type */
	interrupt-names = "intr";
	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	dma-coherent;
	num-viewport = <6>;
	bus-range = <0x0 0xff>;
	msi-parent = <&its>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
	<0000 0 0 2 &gic 0 0 0 110 4>,
	<0000 0 0 3 &gic 0 0 0 111 4>,
	<0000 0 0 4 &gic 0 0 0 112 4>;
	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	status = "disabled";
	};

	pcie2: pcie@3500000 {
	compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
	reg-names = "regs", "config";
	interrupts = <0 113 0x4>; /* Level high type */
	interrupt-names = "intr";
	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	dma-coherent;
	num-viewport = <6>;
	bus-range = <0x0 0xff>;
	msi-parent = <&its>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
	<0000 0 0 2 &gic 0 0 0 115 4>,
	<0000 0 0 3 &gic 0 0 0 116 4>,
	<0000 0 0 4 &gic 0 0 0 117 4>;
	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	status = "disabled";
	};

	pcie3: pcie@3600000 {
	compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
	reg-names = "regs", "config";
	interrupts = <0 118 0x4>; /* Level high type */
	interrupt-names = "intr";
	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	dma-coherent;
	num-viewport = <256>;
	bus-range = <0x0 0xff>;
	msi-parent = <&its>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
	<0000 0 0 2 &gic 0 0 0 120 4>,
	<0000 0 0 3 &gic 0 0 0 121 4>,
	<0000 0 0 4 &gic 0 0 0 122 4>;
	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	status = "disabled";
	};

	pcie4: pcie@3700000 {
	compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
	reg-names = "regs", "config";
	interrupts = <0 123 0x4>; /* Level high type */
	interrupt-names = "intr";
	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	dma-coherent;
	num-viewport = <6>;
	bus-range = <0x0 0xff>;
	msi-parent = <&its>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
	<0000 0 0 2 &gic 0 0 0 125 4>,
	<0000 0 0 3 &gic 0 0 0 126 4>,
	<0000 0 0 4 &gic 0 0 0 127 4>;
	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	status = "disabled";
	};

	sata0: sata@3200000 {
	status = "disabled";
	compatible = "fsl,ls2080a-ahci";
	reg = <0x0 0x3200000 0x0 0x10000>;
	interrupts = <0 133 0x4>; /* Level high type */
	clocks = <&clockgen 4 3>;
	dma-coherent;
	};

	sata1: sata@3210000 {
	status = "disabled";
	compatible = "fsl,ls2080a-ahci";
	reg = <0x0 0x3210000 0x0 0x10000>;
	interrupts = <0 136 0x4>; /* Level high type */
	clocks = <&clockgen 4 3>;
	dma-coherent;
	};

	usb0: usb3@3100000 {
	status = "disabled";
	compatible = "snps,dwc3";
	reg = <0x0 0x3100000 0x0 0x10000>;
	interrupts = <0 80 0x4>; /* Level high type */
	dr_mode = "host";
	snps,quirk-frame-length-adjustment = <0x20>;
	snps,dis_rxdet_inp3_quirk;
	snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
	};

	usb1: usb3@3110000 {
	status = "disabled";
	compatible = "snps,dwc3";
	reg = <0x0 0x3110000 0x0 0x10000>;
	interrupts = <0 81 0x4>; /* Level high type */
	dr_mode = "host";
	snps,quirk-frame-length-adjustment = <0x20>;
	snps,dis_rxdet_inp3_quirk;
	snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
	};

	ccn@4000000 {
	compatible = "arm,ccn-504";
	reg = <0x0 0x04000000 0x0 0x01000000>;
	interrupts = <0 12 4>;
	};
	};

	ddr1: memory-controller@1080000 {
	compatible = "fsl,qoriq-memory-controller";
	reg = <0x0 0x1080000 0x0 0x1000>;
	interrupts = <0 17 0x4>;
	little-endian;
	};

	ddr2: memory-controller@1090000 {
	compatible = "fsl,qoriq-memory-controller";
	reg = <0x0 0x1090000 0x0 0x1000>;
	interrupts = <0 18 0x4>;
	little-endian;
	};

	firmware {
	optee {
	compatible = "linaro,optee-tz";
	method = "smc";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-cex7.dtsi b/sys/gnu/dts/arm64/freescale/fsl-lx2160a-cex7.dtsi
	index 071e21678f77..d87d16460875 100644
	--- a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-cex7.dtsi
	+++ b/sys/gnu/dts/arm64/freescale/fsl-lx2160a-cex7.dtsi
	@@ -1,127 +1,164 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	//
	// Device Tree file for LX2160A-CEx7
	//
	// Copyright 2019 SolidRun Ltd.

	/dts-v1/;

	#include "fsl-lx2160a.dtsi"

	/ {
	model = "SolidRun LX2160A COM Express Type 7 module";
	compatible = "solidrun,lx2160a-cex7", "fsl,lx2160a";

	aliases {
	crypto = &crypto;
	};

	sb_3v3: regulator-sb3v3 {
	compatible = "regulator-fixed";
	regulator-name = "RT7290";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};

	&crypto {
	status = "okay";
	};

	&dpmac17 {
	phy-handle = <&rgmii_phy1>;
	phy-connection-type = "rgmii-id";
	};

	&emdio1 {
	status = "okay";

	rgmii_phy1: ethernet-phy@1 {
	reg = <1>;
	};
	};

	&esdhc1 {
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	bus-width = <8>;
	status = "okay";
	};

	&i2c0 {
	status = "okay";

	i2c-switch@77 {
	compatible = "nxp,pca9547";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x77>;

	+ i2c@0 {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ reg = <0>;
	+
	+ eeprom@50 {
	+ compatible = "atmel,24c512";
	+ reg = <0x50>;
	+ };
	+
	+ eeprom@51 {
	+ compatible = "atmel,spd";
	+ reg = <0x51>;
	+ };
	+
	+ eeprom@53 {
	+ compatible = "atmel,spd";
	+ reg = <0x53>;
	+ };
	+
	+ eeprom@57 {
	+ compatible = "atmel,24c02";
	+ reg = <0x57>;
	+ };
	+ };
	+
	i2c@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	fan-temperature-ctrlr@18 {
	compatible = "ti,amc6821";
	reg = <0x18>;
	cooling-min-state = <0>;
	cooling-max-state = <9>;
	#cooling-cells = <2>;
	};
	};

	+ i2c@2 {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ reg = <2>;
	+
	+ regulator@5c {
	+ compatible = "lltc,ltc3882";
	+ reg = <0x5c>;
	+ };
	+ };
	+
	i2c@3 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <3>;

	temperature-sensor@48 {
	compatible = "nxp,sa56004";
	reg = <0x48>;
	vcc-supply = <&sb_3v3>;
	};
	};
	};
	};

	&i2c2 {
	status = "okay";
	};

	&i2c4 {
	status = "okay";

	rtc@51 {
	compatible = "nxp,pcf2129";
	reg = <0x51>;
	// IRQ10_B
	interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	&fspi {
	status = "okay";

	flash@0 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "micron,m25p80";
	m25p,fast-read;
	spi-max-frequency = <50000000>;
	reg = <0>;
	/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
	spi-rx-bus-width = <8>;
	spi-tx-bus-width = <1>;
	};
	};

	&usb0 {
	status = "okay";
	};

	&usb1 {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-qds.dts b/sys/gnu/dts/arm64/freescale/fsl-lx2160a-qds.dts
	index 1a5acf62f23c..3b88e1efe4db 100644
	--- a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-qds.dts
	+++ b/sys/gnu/dts/arm64/freescale/fsl-lx2160a-qds.dts
	@@ -1,128 +1,143 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	//
	// Device Tree file for LX2160AQDS
	//
	// Copyright 2018 NXP

	/dts-v1/;

	#include "fsl-lx2160a.dtsi"

	/ {
	model = "NXP Layerscape LX2160AQDS";
	compatible = "fsl,lx2160a-qds", "fsl,lx2160a";

	aliases {
	crypto = &crypto;
	serial0 = &uart0;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	sb_3v3: regulator-sb3v3 {
	compatible = "regulator-fixed";
	regulator-name = "MC34717-3.3VSB";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};

	&crypto {
	status = "okay";
	};

	&esdhc0 {
	status = "okay";
	};

	&esdhc1 {
	status = "okay";
	};

	+&fspi {
	+ status = "okay";
	+
	+ mt35xu512aba0: flash@0 {
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ compatible = "jedec,spi-nor";
	+ m25p,fast-read;
	+ spi-max-frequency = <50000000>;
	+ reg = <0>;
	+ spi-rx-bus-width = <8>;
	+ spi-tx-bus-width = <8>;
	+ };
	+};
	+
	&i2c0 {
	status = "okay";

	i2c-mux@77 {
	compatible = "nxp,pca9547";
	reg = <0x77>;
	#address-cells = <1>;
	#size-cells = <0>;

	i2c@2 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x2>;

	power-monitor@40 {
	compatible = "ti,ina220";
	reg = <0x40>;
	shunt-resistor = <500>;
	};

	power-monitor@41 {
	compatible = "ti,ina220";
	reg = <0x41>;
	shunt-resistor = <1000>;
	};
	};

	i2c@3 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x3>;

	temperature-sensor@4c {
	compatible = "nxp,sa56004";
	reg = <0x4c>;
	vcc-supply = <&sb_3v3>;
	};

	temperature-sensor@4d {
	compatible = "nxp,sa56004";
	reg = <0x4d>;
	vcc-supply = <&sb_3v3>;
	};

	rtc@51 {
	compatible = "nxp,pcf2129";
	reg = <0x51>;
	};
	};
	};
	};

	&sata0 {
	status = "okay";
	};

	&sata1 {
	status = "okay";
	};

	&sata2 {
	status = "okay";
	};

	&sata3 {
	status = "okay";
	};

	&uart0 {
	status = "okay";
	};

	&uart1 {
	status = "okay";
	};

	&usb0 {
	status = "okay";
	};

	&usb1 {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-rdb.dts b/sys/gnu/dts/arm64/freescale/fsl-lx2160a-rdb.dts
	index 51615de102fe..22d0308eb13b 100644
	--- a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-rdb.dts
	+++ b/sys/gnu/dts/arm64/freescale/fsl-lx2160a-rdb.dts
	@@ -1,189 +1,189 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	//
	// Device Tree file for LX2160ARDB
	//
	// Copyright 2018 NXP

	/dts-v1/;

	#include "fsl-lx2160a.dtsi"

	/ {
	model = "NXP Layerscape LX2160ARDB";
	compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";

	aliases {
	crypto = &crypto;
	serial0 = &uart0;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	sb_3v3: regulator-sb3v3 {
	compatible = "regulator-fixed";
	regulator-name = "MC34717-3.3VSB";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};

	&crypto {
	status = "okay";
	};

	&dpmac17 {
	phy-handle = <&rgmii_phy1>;
	phy-connection-type = "rgmii-id";
	};

	&dpmac18 {
	phy-handle = <&rgmii_phy2>;
	phy-connection-type = "rgmii-id";
	};

	&emdio1 {
	status = "okay";

	rgmii_phy1: ethernet-phy@1 {
	/* AR8035 PHY */
	compatible = "ethernet-phy-id004d.d072";
	reg = <0x1>;
	eee-broken-1000t;
	};

	rgmii_phy2: ethernet-phy@2 {
	/* AR8035 PHY */
	compatible = "ethernet-phy-id004d.d072";
	reg = <0x2>;
	eee-broken-1000t;
	};
	};

	&esdhc0 {
	sd-uhs-sdr104;
	sd-uhs-sdr50;
	sd-uhs-sdr25;
	sd-uhs-sdr12;
	status = "okay";
	};

	&esdhc1 {
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	bus-width = <8>;
	status = "okay";
	};

	&fspi {
	status = "okay";

	mt35xu512aba0: flash@0 {
	#address-cells = <1>;
	#size-cells = <1>;
	- compatible = "spansion,m25p80";
	+ compatible = "jedec,spi-nor";
	m25p,fast-read;
	spi-max-frequency = <50000000>;
	reg = <0>;
	spi-rx-bus-width = <8>;
	spi-tx-bus-width = <8>;
	};

	mt35xu512aba1: flash@1 {
	#address-cells = <1>;
	#size-cells = <1>;
	- compatible = "spansion,m25p80";
	+ compatible = "jedec,spi-nor";
	m25p,fast-read;
	spi-max-frequency = <50000000>;
	reg = <1>;
	spi-rx-bus-width = <8>;
	spi-tx-bus-width = <8>;
	};
	};

	&i2c0 {
	status = "okay";

	i2c-mux@77 {
	compatible = "nxp,pca9547";
	reg = <0x77>;
	#address-cells = <1>;
	#size-cells = <0>;

	i2c@2 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x2>;

	power-monitor@40 {
	compatible = "ti,ina220";
	reg = <0x40>;
	shunt-resistor = <1000>;
	};
	};

	i2c@3 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x3>;

	temperature-sensor@4c {
	compatible = "nxp,sa56004";
	reg = <0x4c>;
	vcc-supply = <&sb_3v3>;
	};

	temperature-sensor@4d {
	compatible = "nxp,sa56004";
	reg = <0x4d>;
	vcc-supply = <&sb_3v3>;
	};
	};
	};
	};

	&i2c4 {
	status = "okay";

	rtc@51 {
	compatible = "nxp,pcf2129";
	reg = <0x51>;
	// IRQ10_B
	interrupts = <0 150 0x4>;
	};
	};

	&sata0 {
	status = "okay";
	};

	&sata1 {
	status = "okay";
	};

	&sata2 {
	status = "okay";
	};

	&sata3 {
	status = "okay";
	};

	&uart0 {
	status = "okay";
	};

	&uart1 {
	status = "okay";
	};

	&usb0 {
	status = "okay";
	};

	&usb1 {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/freescale/fsl-lx2160a.dtsi b/sys/gnu/dts/arm64/freescale/fsl-lx2160a.dtsi
	index e5ee5591e52b..ae1b113ab162 100644
	--- a/sys/gnu/dts/arm64/freescale/fsl-lx2160a.dtsi
	+++ b/sys/gnu/dts/arm64/freescale/fsl-lx2160a.dtsi
	@@ -1,1080 +1,1248 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	//
	// Device Tree Include file for Layerscape-LX2160A family SoC.
	//
	// Copyright 2018 NXP

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/thermal/thermal.h>

	/memreserve/ 0x80000000 0x00010000;

	/ {
	compatible = "fsl,lx2160a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	// 8 clusters having 2 Cortex-A72 cores each
	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x0>;
	clocks = <&clockgen 1 0>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <192>;
	next-level-cache = <&cluster0_l2>;
	cpu-idle-states = <&cpu_pw15>;
	#cooling-cells = <2>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x1>;
	clocks = <&clockgen 1 0>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <192>;
	next-level-cache = <&cluster0_l2>;
	cpu-idle-states = <&cpu_pw15>;
	#cooling-cells = <2>;
	};

	cpu100: cpu@100 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x100>;
	clocks = <&clockgen 1 1>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <192>;
	next-level-cache = <&cluster1_l2>;
	cpu-idle-states = <&cpu_pw15>;
	#cooling-cells = <2>;
	};

	cpu101: cpu@101 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x101>;
	clocks = <&clockgen 1 1>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <192>;
	next-level-cache = <&cluster1_l2>;
	cpu-idle-states = <&cpu_pw15>;
	#cooling-cells = <2>;
	};

	cpu200: cpu@200 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x200>;
	clocks = <&clockgen 1 2>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <192>;
	next-level-cache = <&cluster2_l2>;
	cpu-idle-states = <&cpu_pw15>;
	#cooling-cells = <2>;
	};

	cpu201: cpu@201 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x201>;
	clocks = <&clockgen 1 2>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <192>;
	next-level-cache = <&cluster2_l2>;
	cpu-idle-states = <&cpu_pw15>;
	#cooling-cells = <2>;
	};

	cpu300: cpu@300 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x300>;
	clocks = <&clockgen 1 3>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <192>;
	next-level-cache = <&cluster3_l2>;
	cpu-idle-states = <&cpu_pw15>;
	#cooling-cells = <2>;
	};

	cpu301: cpu@301 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x301>;
	clocks = <&clockgen 1 3>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <192>;
	next-level-cache = <&cluster3_l2>;
	cpu-idle-states = <&cpu_pw15>;
	#cooling-cells = <2>;
	};

	cpu400: cpu@400 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x400>;
	clocks = <&clockgen 1 4>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <192>;
	next-level-cache = <&cluster4_l2>;
	cpu-idle-states = <&cpu_pw15>;
	#cooling-cells = <2>;
	};

	cpu401: cpu@401 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x401>;
	clocks = <&clockgen 1 4>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <192>;
	next-level-cache = <&cluster4_l2>;
	cpu-idle-states = <&cpu_pw15>;
	#cooling-cells = <2>;
	};

	cpu500: cpu@500 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x500>;
	clocks = <&clockgen 1 5>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <192>;
	next-level-cache = <&cluster5_l2>;
	cpu-idle-states = <&cpu_pw15>;
	#cooling-cells = <2>;
	};

	cpu501: cpu@501 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x501>;
	clocks = <&clockgen 1 5>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <192>;
	next-level-cache = <&cluster5_l2>;
	cpu-idle-states = <&cpu_pw15>;
	#cooling-cells = <2>;
	};

	cpu600: cpu@600 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x600>;
	clocks = <&clockgen 1 6>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <192>;
	next-level-cache = <&cluster6_l2>;
	cpu-idle-states = <&cpu_pw15>;
	#cooling-cells = <2>;
	};

	cpu601: cpu@601 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x601>;
	clocks = <&clockgen 1 6>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <192>;
	next-level-cache = <&cluster6_l2>;
	cpu-idle-states = <&cpu_pw15>;
	#cooling-cells = <2>;
	};

	cpu700: cpu@700 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x700>;
	clocks = <&clockgen 1 7>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <192>;
	next-level-cache = <&cluster7_l2>;
	cpu-idle-states = <&cpu_pw15>;
	#cooling-cells = <2>;
	};

	cpu701: cpu@701 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x701>;
	clocks = <&clockgen 1 7>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <192>;
	next-level-cache = <&cluster7_l2>;
	cpu-idle-states = <&cpu_pw15>;
	#cooling-cells = <2>;
	};

	cluster0_l2: l2-cache0 {
	compatible = "cache";
	cache-size = <0x100000>;
	cache-line-size = <64>;
	cache-sets = <1024>;
	cache-level = <2>;
	};

	cluster1_l2: l2-cache1 {
	compatible = "cache";
	cache-size = <0x100000>;
	cache-line-size = <64>;
	cache-sets = <1024>;
	cache-level = <2>;
	};

	cluster2_l2: l2-cache2 {
	compatible = "cache";
	cache-size = <0x100000>;
	cache-line-size = <64>;
	cache-sets = <1024>;
	cache-level = <2>;
	};

	cluster3_l2: l2-cache3 {
	compatible = "cache";
	cache-size = <0x100000>;
	cache-line-size = <64>;
	cache-sets = <1024>;
	cache-level = <2>;
	};

	cluster4_l2: l2-cache4 {
	compatible = "cache";
	cache-size = <0x100000>;
	cache-line-size = <64>;
	cache-sets = <1024>;
	cache-level = <2>;
	};

	cluster5_l2: l2-cache5 {
	compatible = "cache";
	cache-size = <0x100000>;
	cache-line-size = <64>;
	cache-sets = <1024>;
	cache-level = <2>;
	};

	cluster6_l2: l2-cache6 {
	compatible = "cache";
	cache-size = <0x100000>;
	cache-line-size = <64>;
	cache-sets = <1024>;
	cache-level = <2>;
	};

	cluster7_l2: l2-cache7 {
	compatible = "cache";
	cache-size = <0x100000>;
	cache-line-size = <64>;
	cache-sets = <1024>;
	cache-level = <2>;
	};

	cpu_pw15: cpu-pw15 {
	compatible = "arm,idle-state";
	idle-state-name = "PW15";
	arm,psci-suspend-param = <0x0>;
	entry-latency-us = <2000>;
	exit-latency-us = <2000>;
	min-residency-us = <6000>;
	};
	};

	gic: interrupt-controller@6000000 {
	compatible = "arm,gic-v3";
	reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
	<0x0 0x06200000 0 0x200000>, // GICR (RD_base +
	// SGI_base)
	<0x0 0x0c0c0000 0 0x2000>, // GICC
	<0x0 0x0c0d0000 0 0x1000>, // GICH
	<0x0 0x0c0e0000 0 0x20000>; // GICV
	#interrupt-cells = <3>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	interrupt-controller;
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

	its: gic-its@6020000 {
	compatible = "arm,gic-v3-its";
	msi-controller;
	reg = <0x0 0x6020000 0 0x20000>;
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
	};

	pmu {
	compatible = "arm,cortex-a72-pmu";
	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	memory@80000000 {
	// DRAM space - 1, size : 2 GB DRAM
	device_type = "memory";
	reg = <0x00000000 0x80000000 0 0x80000000>;
	};

	ddr1: memory-controller@1080000 {
	compatible = "fsl,qoriq-memory-controller";
	reg = <0x0 0x1080000 0x0 0x1000>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	little-endian;
	};

	ddr2: memory-controller@1090000 {
	compatible = "fsl,qoriq-memory-controller";
	reg = <0x0 0x1090000 0x0 0x1000>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	little-endian;
	};

	// One clock unit-sysclk node which bootloader require during DT fix-up
	sysclk: sysclk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <100000000>; // fixed up by bootloader
	clock-output-names = "sysclk";
	};

	thermal-zones {
	core_thermal1: core-thermal1 {
	polling-delay-passive = <1000>;
	polling-delay = <5000>;
	thermal-sensors = <&tmu 0>;

	trips {
	core_cluster_alert: core-cluster-alert {
	temperature = <85000>;
	hysteresis = <2000>;
	type = "passive";
	};

	core_cluster_crit: core-cluster-crit {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&core_cluster_alert>;
	cooling-device =
	<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;

	crypto: crypto@8000000 {
	compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
	fsl,sec-era = <10>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x00 0x8000000 0x100000>;
	reg = <0x00 0x8000000 0x0 0x100000>;
	interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
	dma-coherent;
	status = "disabled";

	sec_jr0: jr@10000 {
	compatible = "fsl,sec-v5.0-job-ring",
	"fsl,sec-v4.0-job-ring";
	reg = <0x10000 0x10000>;
	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
	};

	sec_jr1: jr@20000 {
	compatible = "fsl,sec-v5.0-job-ring",
	"fsl,sec-v4.0-job-ring";
	reg = <0x20000 0x10000>;
	interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
	};

	sec_jr2: jr@30000 {
	compatible = "fsl,sec-v5.0-job-ring",
	"fsl,sec-v4.0-job-ring";
	reg = <0x30000 0x10000>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
	};

	sec_jr3: jr@40000 {
	compatible = "fsl,sec-v5.0-job-ring",
	"fsl,sec-v4.0-job-ring";
	reg = <0x40000 0x10000>;
	interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	clockgen: clock-controller@1300000 {
	compatible = "fsl,lx2160a-clockgen";
	reg = <0 0x1300000 0 0xa0000>;
	#clock-cells = <2>;
	clocks = <&sysclk>;
	};

	dcfg: syscon@1e00000 {
	compatible = "fsl,lx2160a-dcfg", "syscon";
	reg = <0x0 0x1e00000 0x0 0x10000>;
	little-endian;
	};

	tmu: tmu@1f80000 {
	compatible = "fsl,qoriq-tmu";
	reg = <0x0 0x1f80000 0x0 0x10000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	fsl,tmu-range = <0x800000e6 0x8001017d>;
	fsl,tmu-calibration =
	/* Calibration data group 1 */
	<0x00000000 0x00000035
	/* Calibration data group 2 */
	0x00010001 0x00000154>;
	little-endian;
	#thermal-sensor-cells = <1>;
	};

	i2c0: i2c@2000000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2000000 0x0 0x10000>;
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "i2c";
	clocks = <&clockgen 4 15>;
	scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
	status = "disabled";
	};

	i2c1: i2c@2010000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2010000 0x0 0x10000>;
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "i2c";
	clocks = <&clockgen 4 15>;
	status = "disabled";
	};

	i2c2: i2c@2020000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2020000 0x0 0x10000>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "i2c";
	clocks = <&clockgen 4 15>;
	status = "disabled";
	};

	i2c3: i2c@2030000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2030000 0x0 0x10000>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "i2c";
	clocks = <&clockgen 4 15>;
	status = "disabled";
	};

	i2c4: i2c@2040000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2040000 0x0 0x10000>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "i2c";
	clocks = <&clockgen 4 15>;
	scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
	status = "disabled";
	};

	i2c5: i2c@2050000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2050000 0x0 0x10000>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "i2c";
	clocks = <&clockgen 4 15>;
	status = "disabled";
	};

	i2c6: i2c@2060000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2060000 0x0 0x10000>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "i2c";
	clocks = <&clockgen 4 15>;
	status = "disabled";
	};

	i2c7: i2c@2070000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2070000 0x0 0x10000>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "i2c";
	clocks = <&clockgen 4 15>;
	status = "disabled";
	};

	fspi: spi@20c0000 {
	compatible = "nxp,lx2160a-fspi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x20c0000 0x0 0x10000>,
	<0x0 0x20000000 0x0 0x10000000>;
	reg-names = "fspi_base", "fspi_mmap";
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
	clock-names = "fspi_en", "fspi";
	status = "disabled";
	};

	esdhc0: esdhc@2140000 {
	compatible = "fsl,esdhc";
	reg = <0x0 0x2140000 0x0 0x10000>;
	interrupts = <0 28 0x4>; /* Level high type */
	clocks = <&clockgen 4 1>;
	dma-coherent;
	voltage-ranges = <1800 1800 3300 3300>;
	sdhci,auto-cmd12;
	little-endian;
	bus-width = <4>;
	status = "disabled";
	};

	esdhc1: esdhc@2150000 {
	compatible = "fsl,esdhc";
	reg = <0x0 0x2150000 0x0 0x10000>;
	interrupts = <0 63 0x4>; /* Level high type */
	clocks = <&clockgen 4 1>;
	dma-coherent;
	voltage-ranges = <1800 1800 3300 3300>;
	sdhci,auto-cmd12;
	broken-cd;
	little-endian;
	bus-width = <4>;
	status = "disabled";
	};

	uart0: serial@21c0000 {
	compatible = "arm,sbsa-uart","arm,pl011";
	reg = <0x0 0x21c0000 0x0 0x1000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	current-speed = <115200>;
	status = "disabled";
	};

	uart1: serial@21d0000 {
	compatible = "arm,sbsa-uart","arm,pl011";
	reg = <0x0 0x21d0000 0x0 0x1000>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	current-speed = <115200>;
	status = "disabled";
	};

	uart2: serial@21e0000 {
	compatible = "arm,sbsa-uart","arm,pl011";
	reg = <0x0 0x21e0000 0x0 0x1000>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	current-speed = <115200>;
	status = "disabled";
	};

	uart3: serial@21f0000 {
	compatible = "arm,sbsa-uart","arm,pl011";
	reg = <0x0 0x21f0000 0x0 0x1000>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	current-speed = <115200>;
	status = "disabled";
	};

	gpio0: gpio@2300000 {
	compatible = "fsl,qoriq-gpio";
	reg = <0x0 0x2300000 0x0 0x10000>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	little-endian;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio1: gpio@2310000 {
	compatible = "fsl,qoriq-gpio";
	reg = <0x0 0x2310000 0x0 0x10000>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	little-endian;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio@2320000 {
	compatible = "fsl,qoriq-gpio";
	reg = <0x0 0x2320000 0x0 0x10000>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	little-endian;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio@2330000 {
	compatible = "fsl,qoriq-gpio";
	reg = <0x0 0x2330000 0x0 0x10000>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	little-endian;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	watchdog@23a0000 {
	compatible = "arm,sbsa-gwdt";
	reg = <0x0 0x23a0000 0 0x1000>,
	<0x0 0x2390000 0 0x1000>;
	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
	timeout-sec = <30>;
	};

	usb0: usb@3100000 {
	compatible = "snps,dwc3";
	reg = <0x0 0x3100000 0x0 0x10000>;
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	dr_mode = "host";
	snps,quirk-frame-length-adjustment = <0x20>;
	snps,dis_rxdet_inp3_quirk;
	snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
	status = "disabled";
	};

	usb1: usb@3110000 {
	compatible = "snps,dwc3";
	reg = <0x0 0x3110000 0x0 0x10000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	dr_mode = "host";
	snps,quirk-frame-length-adjustment = <0x20>;
	snps,dis_rxdet_inp3_quirk;
	snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
	status = "disabled";
	};

	sata0: sata@3200000 {
	compatible = "fsl,lx2160a-ahci";
	reg = <0x0 0x3200000 0x0 0x10000>,
	<0x7 0x100520 0x0 0x4>;
	reg-names = "ahci", "sata-ecc";
	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	dma-coherent;
	status = "disabled";
	};

	sata1: sata@3210000 {
	compatible = "fsl,lx2160a-ahci";
	reg = <0x0 0x3210000 0x0 0x10000>,
	<0x7 0x100520 0x0 0x4>;
	reg-names = "ahci", "sata-ecc";
	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	dma-coherent;
	status = "disabled";
	};

	sata2: sata@3220000 {
	compatible = "fsl,lx2160a-ahci";
	reg = <0x0 0x3220000 0x0 0x10000>,
	<0x7 0x100520 0x0 0x4>;
	reg-names = "ahci", "sata-ecc";
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	dma-coherent;
	status = "disabled";
	};

	sata3: sata@3230000 {
	compatible = "fsl,lx2160a-ahci";
	reg = <0x0 0x3230000 0x0 0x10000>,
	<0x7 0x100520 0x0 0x4>;
	reg-names = "ahci", "sata-ecc";
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	dma-coherent;
	status = "disabled";
	};

	+ pcie@3400000 {
	+ compatible = "fsl,lx2160a-pcie";
	+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
	+ 0x80 0x00000000 0x0 0x00001000>; /* configuration space */
	+ reg-names = "csr_axi_slave", "config_axi_slave";
	+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
	+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
	+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
	+ interrupt-names = "aer", "pme", "intr";
	+ #address-cells = <3>;
	+ #size-cells = <2>;
	+ device_type = "pci";
	+ dma-coherent;
	+ apio-wins = <8>;
	+ ppio-wins = <8>;
	+ bus-range = <0x0 0xff>;
	+ ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	+ msi-parent = <&its>;
	+ #interrupt-cells = <1>;
	+ interrupt-map-mask = <0 0 0 7>;
	+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	+ status = "disabled";
	+ };
	+
	+ pcie@3500000 {
	+ compatible = "fsl,lx2160a-pcie";
	+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
	+ 0x88 0x00000000 0x0 0x00001000>; /* configuration space */
	+ reg-names = "csr_axi_slave", "config_axi_slave";
	+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
	+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
	+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
	+ interrupt-names = "aer", "pme", "intr";
	+ #address-cells = <3>;
	+ #size-cells = <2>;
	+ device_type = "pci";
	+ dma-coherent;
	+ apio-wins = <8>;
	+ ppio-wins = <8>;
	+ bus-range = <0x0 0xff>;
	+ ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	+ msi-parent = <&its>;
	+ #interrupt-cells = <1>;
	+ interrupt-map-mask = <0 0 0 7>;
	+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	+ status = "disabled";
	+ };
	+
	+ pcie@3600000 {
	+ compatible = "fsl,lx2160a-pcie";
	+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
	+ 0x90 0x00000000 0x0 0x00001000>; /* configuration space */
	+ reg-names = "csr_axi_slave", "config_axi_slave";
	+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
	+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
	+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
	+ interrupt-names = "aer", "pme", "intr";
	+ #address-cells = <3>;
	+ #size-cells = <2>;
	+ device_type = "pci";
	+ dma-coherent;
	+ apio-wins = <256>;
	+ ppio-wins = <24>;
	+ bus-range = <0x0 0xff>;
	+ ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	+ msi-parent = <&its>;
	+ #interrupt-cells = <1>;
	+ interrupt-map-mask = <0 0 0 7>;
	+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	+ status = "disabled";
	+ };
	+
	+ pcie@3700000 {
	+ compatible = "fsl,lx2160a-pcie";
	+ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
	+ 0x98 0x00000000 0x0 0x00001000>; /* configuration space */
	+ reg-names = "csr_axi_slave", "config_axi_slave";
	+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
	+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
	+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
	+ interrupt-names = "aer", "pme", "intr";
	+ #address-cells = <3>;
	+ #size-cells = <2>;
	+ device_type = "pci";
	+ dma-coherent;
	+ apio-wins = <8>;
	+ ppio-wins = <8>;
	+ bus-range = <0x0 0xff>;
	+ ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	+ msi-parent = <&its>;
	+ #interrupt-cells = <1>;
	+ interrupt-map-mask = <0 0 0 7>;
	+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	+ status = "disabled";
	+ };
	+
	+ pcie@3800000 {
	+ compatible = "fsl,lx2160a-pcie";
	+ reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
	+ 0xa0 0x00000000 0x0 0x00001000>; /* configuration space */
	+ reg-names = "csr_axi_slave", "config_axi_slave";
	+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
	+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
	+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
	+ interrupt-names = "aer", "pme", "intr";
	+ #address-cells = <3>;
	+ #size-cells = <2>;
	+ device_type = "pci";
	+ dma-coherent;
	+ apio-wins = <256>;
	+ ppio-wins = <24>;
	+ bus-range = <0x0 0xff>;
	+ ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	+ msi-parent = <&its>;
	+ #interrupt-cells = <1>;
	+ interrupt-map-mask = <0 0 0 7>;
	+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	+ status = "disabled";
	+ };
	+
	+ pcie@3900000 {
	+ compatible = "fsl,lx2160a-pcie";
	+ reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
	+ 0xa8 0x00000000 0x0 0x00001000>; /* configuration space */
	+ reg-names = "csr_axi_slave", "config_axi_slave";
	+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
	+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
	+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
	+ interrupt-names = "aer", "pme", "intr";
	+ #address-cells = <3>;
	+ #size-cells = <2>;
	+ device_type = "pci";
	+ dma-coherent;
	+ apio-wins = <8>;
	+ ppio-wins = <8>;
	+ bus-range = <0x0 0xff>;
	+ ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	+ msi-parent = <&its>;
	+ #interrupt-cells = <1>;
	+ interrupt-map-mask = <0 0 0 7>;
	+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	+ <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	+ status = "disabled";
	+ };
	+
	smmu: iommu@5000000 {
	compatible = "arm,mmu-500";
	reg = <0 0x5000000 0 0x800000>;
	#iommu-cells = <1>;
	#global-interrupts = <14>;
	// global secure fault
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	// combined secure
	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	// global non-secure fault
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	// combined non-secure
	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	// performance counter interrupts 0-9
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	// per context interrupt, 64 interrupts
	<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
	dma-coherent;
	};

	console@8340020 {
	compatible = "fsl,dpaa2-console";
	reg = <0x00000000 0x08340020 0 0x2>;
	};

	ptp-timer@8b95000 {
	compatible = "fsl,dpaa2-ptp";
	reg = <0x0 0x8b95000 0x0 0x100>;
	clocks = <&clockgen 4 1>;
	little-endian;
	fsl,extts-fifo;
	};

	/* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
	emdio1: mdio@8b96000 {
	compatible = "fsl,fman-memac-mdio";
	reg = <0x0 0x8b96000 0x0 0x1000>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	little-endian;
	status = "disabled";
	};

	emdio2: mdio@8b97000 {
	compatible = "fsl,fman-memac-mdio";
	reg = <0x0 0x8b97000 0x0 0x1000>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	little-endian;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	fsl_mc: fsl-mc@80c000000 {
	compatible = "fsl,qoriq-mc";
	reg = <0x00000008 0x0c000000 0 0x40>,
	<0x00000000 0x08340000 0 0x40000>;
	msi-parent = <&its>;
	/* iommu-map property is fixed up by u-boot */
	iommu-map = <0 &smmu 0 0>;
	dma-coherent;
	#address-cells = <3>;
	#size-cells = <1>;

	/*
	* Region type 0x0 - MC portals
	* Region type 0x1 - QBMAN portals
	*/
	ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
	0x1 0x0 0x0 0x8 0x18000000 0x8000000>;

	/*
	* Define the maximum number of MACs present on the SoC.
	*/
	dpmacs {
	#address-cells = <1>;
	#size-cells = <0>;

	dpmac1: dpmac@1 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x1>;
	};

	dpmac2: dpmac@2 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x2>;
	};

	dpmac3: dpmac@3 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x3>;
	};

	dpmac4: dpmac@4 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x4>;
	};

	dpmac5: dpmac@5 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x5>;
	};

	dpmac6: dpmac@6 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x6>;
	};

	dpmac7: dpmac@7 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x7>;
	};

	dpmac8: dpmac@8 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x8>;
	};

	dpmac9: dpmac@9 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x9>;
	};

	dpmac10: dpmac@a {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0xa>;
	};

	dpmac11: dpmac@b {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0xb>;
	};

	dpmac12: dpmac@c {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0xc>;
	};

	dpmac13: dpmac@d {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0xd>;
	};

	dpmac14: dpmac@e {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0xe>;
	};

	dpmac15: dpmac@f {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0xf>;
	};

	dpmac16: dpmac@10 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x10>;
	};

	dpmac17: dpmac@11 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x11>;
	};

	dpmac18: dpmac@12 {
	compatible = "fsl,qoriq-mc-dpmac";
	reg = <0x12>;
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/freescale/imx8mm-evk.dts b/sys/gnu/dts/arm64/freescale/imx8mm-evk.dts
	index 9e54747cf4e6..951e14a3de0e 100644
	--- a/sys/gnu/dts/arm64/freescale/imx8mm-evk.dts
	+++ b/sys/gnu/dts/arm64/freescale/imx8mm-evk.dts
	@@ -1,539 +1,541 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright 2019 NXP
	*/

	/dts-v1/;

	#include <dt-bindings/usb/pd.h>
	#include "imx8mm.dtsi"

	/ {
	model = "FSL i.MX8MM EVK board";
	compatible = "fsl,imx8mm-evk", "fsl,imx8mm";

	chosen {
	stdout-path = &uart2;
	};

	memory@40000000 {
	device_type = "memory";
	reg = <0x0 0x40000000 0 0x80000000>;
	};

	leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_led>;

	status {
	label = "status";
	gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
	default-state = "on";
	};
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
	regulator-name = "VSD_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	wm8524: audio-codec {
	#sound-dai-cells = <0>;
	compatible = "wlf,wm8524";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_wlf>;
	wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
	};

	sound-wm8524 {
	compatible = "simple-audio-card";
	simple-audio-card,name = "wm8524-audio";
	simple-audio-card,format = "i2s";
	simple-audio-card,frame-master = <&cpudai>;
	simple-audio-card,bitclock-master = <&cpudai>;
	simple-audio-card,widgets =
	"Line", "Left Line Out Jack",
	"Line", "Right Line Out Jack";
	simple-audio-card,routing =
	"Left Line Out Jack", "LINEVOUTL",
	"Right Line Out Jack", "LINEVOUTR";

	cpudai: simple-audio-card,cpu {
	sound-dai = <&sai3>;
	dai-tdm-slot-num = <2>;
	dai-tdm-slot-width = <32>;
	};

	simple-audio-card,codec {
	sound-dai = <&wm8524>;
	clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
	};
	};
	};

	&A53_0 {
	cpu-supply = <&buck2_reg>;
	};

	&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
	compatible = "operating-points-v2";

	opp-25M {
	opp-hz = /bits/ 64 <25000000>;
	};

	opp-100M {
	opp-hz = /bits/ 64 <100000000>;
	};

	opp-750M {
	opp-hz = /bits/ 64 <750000000>;
	};
	};
	};

	&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	+ phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
	+ phy-reset-duration = <10>;
	fsl,magic-packet;
	status = "okay";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy0: ethernet-phy@0 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <0>;
	};
	};
	};

	&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic@4b {
	compatible = "rohm,bd71847";
	reg = <0x4b>;
	pinctrl-0 = <&pinctrl_pmic>;
	interrupt-parent = <&gpio1>;
	interrupts = <3 GPIO_ACTIVE_LOW>;
	rohm,reset-snvs-powered;

	regulators {
	buck1_reg: BUCK1 {
	regulator-name = "BUCK1";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1300000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <1250>;
	};

	buck2_reg: BUCK2 {
	regulator-name = "BUCK2";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1300000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <1250>;
	rohm,dvs-run-voltage = <1000000>;
	rohm,dvs-idle-voltage = <900000>;
	};

	buck3_reg: BUCK3 {
	// BUCK5 in datasheet
	regulator-name = "BUCK3";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1350000>;
	regulator-boot-on;
	regulator-always-on;
	};

	buck4_reg: BUCK4 {
	// BUCK6 in datasheet
	regulator-name = "BUCK4";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	buck5_reg: BUCK5 {
	// BUCK7 in datasheet
	regulator-name = "BUCK5";
	regulator-min-microvolt = <1605000>;
	regulator-max-microvolt = <1995000>;
	regulator-boot-on;
	regulator-always-on;
	};

	buck6_reg: BUCK6 {
	// BUCK8 in datasheet
	regulator-name = "BUCK6";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1400000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo1_reg: LDO1 {
	regulator-name = "LDO1";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo2_reg: LDO2 {
	regulator-name = "LDO2";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <900000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo3_reg: LDO3 {
	regulator-name = "LDO3";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo4_reg: LDO4 {
	regulator-name = "LDO4";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo6_reg: LDO6 {
	regulator-name = "LDO6";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};
	};
	};

	&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	ptn5110: tcpc@50 {
	compatible = "nxp,ptn5110";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_typec1>;
	reg = <0x50>;
	interrupt-parent = <&gpio2>;
	interrupts = <11 8>;
	status = "okay";

	port {
	typec1_dr_sw: endpoint {
	remote-endpoint = <&usb1_drd_sw>;
	};
	};

	typec1_con: connector {
	compatible = "usb-c-connector";
	label = "USB-C";
	power-role = "dual";
	data-role = "dual";
	try-power-role = "sink";
	source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
	sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
	PDO_VAR(5000, 20000, 3000)>;
	op-sink-microwatt = <15000000>;
	self-powered;
	};
	};
	};

	&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	pca6416: gpio@20 {
	compatible = "ti,tca6416";
	reg = <0x20>;
	gpio-controller;
	#gpio-cells = <2>;
	};
	};

	&sai3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	status = "okay";
	};

	&snvs_pwrkey {
	status = "okay";
	};

	&uart2 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
	};

	&usbotg1 {
	dr_mode = "otg";
	hnp-disable;
	srp-disable;
	adp-disable;
	usb-role-switch;
	status = "okay";

	port {
	usb1_drd_sw: endpoint {
	remote-endpoint = <&typec1_dr_sw>;
	};
	};
	};

	&usdhc2 {
	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
	};

	&usdhc3 {
	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
	};

	&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
	};

	&iomuxc {
	pinctrl-names = "default";

	pinctrl_fec1: fec1grp {
	fsl,pins = <
	MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
	MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
	MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
	MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
	MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
	MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
	MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
	MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
	MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
	MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
	MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
	MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
	MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
	MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
	MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
	>;
	};

	pinctrl_gpio_led: gpioledgrp {
	fsl,pins = <
	MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
	>;
	};

	pinctrl_gpio_wlf: gpiowlfgrp {
	fsl,pins = <
	MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
	MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
	MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
	MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
	>;
	};

	pinctrl_pmic: pmicirq {
	fsl,pins = <
	MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
	>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
	fsl,pins = <
	MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
	>;
	};

	pinctrl_sai3: sai3grp {
	fsl,pins = <
	MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
	MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
	MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
	MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
	>;
	};

	pinctrl_typec1: typec1grp {
	fsl,pins = <
	MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
	MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
	>;
	};

	pinctrl_usdhc2_gpio: usdhc2grpgpio {
	fsl,pins = <
	MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
	>;
	};

	pinctrl_usdhc2: usdhc2grp {
	fsl,pins = <
	MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
	MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
	MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
	MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
	MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
	MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
	MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
	>;
	};

	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
	fsl,pins = <
	MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
	MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
	MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
	MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
	MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
	MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
	MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
	>;
	};

	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
	fsl,pins = <
	MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
	MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
	MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
	MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
	MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
	MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
	MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
	MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
	MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
	MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
	MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
	MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
	MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
	MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
	MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
	MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
	MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
	>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
	fsl,pins = <
	MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
	MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
	MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
	MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
	MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
	MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
	MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
	MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
	MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
	MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
	MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
	>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
	fsl,pins = <
	MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
	MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
	MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
	MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
	MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
	MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
	MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
	MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
	MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
	MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
	MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
	>;
	};

	pinctrl_wdog: wdoggrp {
	fsl,pins = <
	MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/freescale/imx8mm.dtsi b/sys/gnu/dts/arm64/freescale/imx8mm.dtsi
	index 1e5e11592f7b..8829628f757a 100644
	--- a/sys/gnu/dts/arm64/freescale/imx8mm.dtsi
	+++ b/sys/gnu/dts/arm64/freescale/imx8mm.dtsi
	@@ -1,903 +1,965 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright 2019 NXP
	*/

	#include <dt-bindings/clock/imx8mm-clock.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/thermal/thermal.h>

	#include "imx8mm-pinfunc.h"

	/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	ethernet0 = &fec1;
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	i2c2 = &i2c3;
	i2c3 = &i2c4;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	spi0 = &ecspi1;
	spi1 = &ecspi2;
	spi2 = &ecspi3;
	mmc0 = &usdhc1;
	mmc1 = &usdhc2;
	mmc2 = &usdhc3;
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	gpio3 = &gpio4;
	gpio4 = &gpio5;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	idle-states {
	entry-method = "psci";

	cpu_pd_wait: cpu-pd-wait {
	compatible = "arm,idle-state";
	arm,psci-suspend-param = <0x0010033>;
	local-timer-stop;
	entry-latency-us = <1000>;
	exit-latency-us = <700>;
	min-residency-us = <2700>;
	};
	};

	A53_0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0>;
	clock-latency = <61036>; /* two CLK32 periods */
	clocks = <&clk IMX8MM_CLK_ARM>;
	enable-method = "psci";
	next-level-cache = <&A53_L2>;
	operating-points-v2 = <&a53_opp_table>;
	nvmem-cells = <&cpu_speed_grade>;
	nvmem-cell-names = "speed_grade";
	cpu-idle-states = <&cpu_pd_wait>;
	+ #cooling-cells = <2>;
	};

	A53_1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x1>;
	clock-latency = <61036>; /* two CLK32 periods */
	clocks = <&clk IMX8MM_CLK_ARM>;
	enable-method = "psci";
	next-level-cache = <&A53_L2>;
	operating-points-v2 = <&a53_opp_table>;
	cpu-idle-states = <&cpu_pd_wait>;
	+ #cooling-cells = <2>;
	};

	A53_2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x2>;
	clock-latency = <61036>; /* two CLK32 periods */
	clocks = <&clk IMX8MM_CLK_ARM>;
	enable-method = "psci";
	next-level-cache = <&A53_L2>;
	operating-points-v2 = <&a53_opp_table>;
	cpu-idle-states = <&cpu_pd_wait>;
	+ #cooling-cells = <2>;
	};

	A53_3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x3>;
	clock-latency = <61036>; /* two CLK32 periods */
	clocks = <&clk IMX8MM_CLK_ARM>;
	enable-method = "psci";
	next-level-cache = <&A53_L2>;
	operating-points-v2 = <&a53_opp_table>;
	cpu-idle-states = <&cpu_pd_wait>;
	+ #cooling-cells = <2>;
	};

	A53_L2: l2-cache0 {
	compatible = "cache";
	};
	};

	a53_opp_table: opp-table {
	compatible = "operating-points-v2";
	opp-shared;

	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	opp-microvolt = <850000>;
	opp-supported-hw = <0xe>, <0x7>;
	clock-latency-ns = <150000>;
	opp-suspend;
	};

	opp-1600000000 {
	opp-hz = /bits/ 64 <1600000000>;
	opp-microvolt = <900000>;
	opp-supported-hw = <0xc>, <0x7>;
	clock-latency-ns = <150000>;
	opp-suspend;
	};

	opp-1800000000 {
	opp-hz = /bits/ 64 <1800000000>;
	opp-microvolt = <1000000>;
	opp-supported-hw = <0x8>, <0x3>;
	clock-latency-ns = <150000>;
	opp-suspend;
	};
	};

	osc_32k: clock-osc-32k {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "osc_32k";
	};

	osc_24m: clock-osc-24m {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "osc_24m";
	};

	clk_ext1: clock-ext1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <133000000>;
	clock-output-names = "clk_ext1";
	};

	clk_ext2: clock-ext2 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <133000000>;
	clock-output-names = "clk_ext2";
	};

	clk_ext3: clock-ext3 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <133000000>;
	clock-output-names = "clk_ext3";
	};

	clk_ext4: clock-ext4 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency= <133000000>;
	clock-output-names = "clk_ext4";
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	pmu {
	compatible = "arm,armv8-pmuv3";
	interrupts = <GIC_PPI 7
	(GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_HIGH)>;
	interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
	clock-frequency = <8000000>;
	arm,no-tick-in-suspend;
	};

	+ thermal-zones {
	+ cpu-thermal {
	+ polling-delay-passive = <250>;
	+ polling-delay = <2000>;
	+ thermal-sensors = <&tmu>;
	+ trips {
	+ cpu_alert0: trip0 {
	+ temperature = <85000>;
	+ hysteresis = <2000>;
	+ type = "passive";
	+ };
	+
	+ cpu_crit0: trip1 {
	+ temperature = <95000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	+ };
	+
	+ cooling-maps {
	+ map0 {
	+ trip = <&cpu_alert0>;
	+ cooling-device =
	+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	+ };
	+ };
	+ };
	+ };
	+
	usbphynop1: usbphynop1 {
	compatible = "usb-nop-xceiv";
	clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
	assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
	clock-names = "main_clk";
	};

	usbphynop2: usbphynop2 {
	compatible = "usb-nop-xceiv";
	clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
	assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
	clock-names = "main_clk";
	};

	soc@0 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x0 0x3e000000>;

	aips1: bus@30000000 {
	- compatible = "simple-bus";
	+ compatible = "fsl,aips-bus", "simple-bus";
	+ reg = <0x30000000 0x400000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x30000000 0x30000000 0x400000>;

	sai1: sai@30010000 {
	compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
	reg = <0x30010000 0x10000>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
	<&clk IMX8MM_CLK_SAI1_ROOT>,
	<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	sai2: sai@30020000 {
	compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
	reg = <0x30020000 0x10000>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
	<&clk IMX8MM_CLK_SAI2_ROOT>,
	<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	sai3: sai@30030000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
	reg = <0x30030000 0x10000>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
	<&clk IMX8MM_CLK_SAI3_ROOT>,
	<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	sai5: sai@30050000 {
	compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
	reg = <0x30050000 0x10000>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
	<&clk IMX8MM_CLK_SAI5_ROOT>,
	<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	sai6: sai@30060000 {
	compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
	reg = <0x30060000 0x10000>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
	<&clk IMX8MM_CLK_SAI6_ROOT>,
	<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	gpio1: gpio@30200000 {
	compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
	reg = <0x30200000 0x10000>;
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 10 30>;
	};

	gpio2: gpio@30210000 {
	compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
	reg = <0x30210000 0x10000>;
	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 40 21>;
	};

	gpio3: gpio@30220000 {
	compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
	reg = <0x30220000 0x10000>;
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 61 26>;
	};

	gpio4: gpio@30230000 {
	compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
	reg = <0x30230000 0x10000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 87 32>;
	};

	gpio5: gpio@30240000 {
	compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
	reg = <0x30240000 0x10000>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 119 30>;
	};

	+ tmu: tmu@30260000 {
	+ compatible = "fsl,imx8mm-tmu";
	+ reg = <0x30260000 0x10000>;
	+ clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
	+ #thermal-sensor-cells = <0>;
	+ };
	+
	wdog1: watchdog@30280000 {
	compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
	reg = <0x30280000 0x10000>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
	status = "disabled";
	};

	wdog2: watchdog@30290000 {
	compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
	reg = <0x30290000 0x10000>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
	status = "disabled";
	};

	wdog3: watchdog@302a0000 {
	compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
	reg = <0x302a0000 0x10000>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
	status = "disabled";
	};

	sdma2: dma-controller@302c0000 {
	compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
	reg = <0x302c0000 0x10000>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
	<&clk IMX8MM_CLK_SDMA2_ROOT>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
	};

	sdma3: dma-controller@302b0000 {
	compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
	reg = <0x302b0000 0x10000>;
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
	<&clk IMX8MM_CLK_SDMA3_ROOT>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
	};

	iomuxc: pinctrl@30330000 {
	compatible = "fsl,imx8mm-iomuxc";
	reg = <0x30330000 0x10000>;
	};

	gpr: iomuxc-gpr@30340000 {
	compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
	reg = <0x30340000 0x10000>;
	};

	ocotp: ocotp-ctrl@30350000 {
	compatible = "fsl,imx8mm-ocotp", "syscon";
	reg = <0x30350000 0x10000>;
	clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
	/* For nvmem subnodes */
	#address-cells = <1>;
	#size-cells = <1>;

	cpu_speed_grade: speed-grade@10 {
	reg = <0x10 4>;
	};
	};

	anatop: anatop@30360000 {
	compatible = "fsl,imx8mm-anatop", "syscon";
	reg = <0x30360000 0x10000>;
	};

	snvs: snvs@30370000 {
	compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
	reg = <0x30370000 0x10000>;

	snvs_rtc: snvs-rtc-lp {
	compatible = "fsl,sec-v4.0-mon-rtc-lp";
	regmap = <&snvs>;
	offset = <0x34>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
	clock-names = "snvs-rtc";
	};

	snvs_pwrkey: snvs-powerkey {
	compatible = "fsl,sec-v4.0-pwrkey";
	regmap = <&snvs>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
	+ clock-names = "snvs-pwrkey";
	linux,keycode = <KEY_POWER>;
	wakeup-source;
	status = "disabled";
	};
	};

	clk: clock-controller@30380000 {
	compatible = "fsl,imx8mm-ccm";
	reg = <0x30380000 0x10000>;
	#clock-cells = <1>;
	clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
	<&clk_ext3>, <&clk_ext4>;
	clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
	"clk_ext3", "clk_ext4";
	assigned-clocks = <&clk IMX8MM_CLK_NOC>,
	<&clk IMX8MM_CLK_AUDIO_AHB>,
	<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
	<&clk IMX8MM_SYS_PLL3>,
	<&clk IMX8MM_VIDEO_PLL1>,
	<&clk IMX8MM_AUDIO_PLL1>,
	<&clk IMX8MM_AUDIO_PLL2>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
	<&clk IMX8MM_SYS_PLL1_800M>;
	assigned-clock-rates = <0>,
	<400000000>,
	<400000000>,
	<750000000>,
	<594000000>,
	<393216000>,
	<361267200>;
	};

	src: reset-controller@30390000 {
	compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
	reg = <0x30390000 0x10000>;
	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	#reset-cells = <1>;
	};
	};

	aips2: bus@30400000 {
	- compatible = "simple-bus";
	+ compatible = "fsl,aips-bus", "simple-bus";
	+ reg = <0x30400000 0x400000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x30400000 0x30400000 0x400000>;

	pwm1: pwm@30660000 {
	compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
	reg = <0x30660000 0x10000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
	<&clk IMX8MM_CLK_PWM1_ROOT>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm2: pwm@30670000 {
	compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
	reg = <0x30670000 0x10000>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
	<&clk IMX8MM_CLK_PWM2_ROOT>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm3: pwm@30680000 {
	compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
	reg = <0x30680000 0x10000>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
	<&clk IMX8MM_CLK_PWM3_ROOT>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm4: pwm@30690000 {
	compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
	reg = <0x30690000 0x10000>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
	<&clk IMX8MM_CLK_PWM4_ROOT>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	system_counter: timer@306a0000 {
	compatible = "nxp,sysctr-timer";
	reg = <0x306a0000 0x20000>;
	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc_24m>;
	clock-names = "per";
	};
	};

	aips3: bus@30800000 {
	- compatible = "simple-bus";
	+ compatible = "fsl,aips-bus", "simple-bus";
	+ reg = <0x30800000 0x400000>;
	#address-cells = <1>;
	#size-cells = <1>;
	- ranges = <0x30800000 0x30800000 0x400000>;
	+ ranges = <0x30800000 0x30800000 0x400000>,
	+ <0x8000000 0x8000000 0x10000000>;

	ecspi1: spi@30820000 {
	compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x30820000 0x10000>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
	<&clk IMX8MM_CLK_ECSPI1_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	ecspi2: spi@30830000 {
	compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x30830000 0x10000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
	<&clk IMX8MM_CLK_ECSPI2_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	ecspi3: spi@30840000 {
	compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x30840000 0x10000>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
	<&clk IMX8MM_CLK_ECSPI3_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart1: serial@30860000 {
	compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
	reg = <0x30860000 0x10000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
	<&clk IMX8MM_CLK_UART1_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart3: serial@30880000 {
	compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
	reg = <0x30880000 0x10000>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
	<&clk IMX8MM_CLK_UART3_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart2: serial@30890000 {
	compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
	reg = <0x30890000 0x10000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
	<&clk IMX8MM_CLK_UART2_ROOT>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	crypto: crypto@30900000 {
	compatible = "fsl,sec-v4.0";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x30900000 0x40000>;
	ranges = <0 0x30900000 0x40000>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_AHB>,
	<&clk IMX8MM_CLK_IPG_ROOT>;
	clock-names = "aclk", "ipg";

	sec_jr0: jr@1000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x1000 0x1000>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	};

	sec_jr1: jr@2000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x2000 0x1000>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	};

	sec_jr2: jr@3000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x3000 0x1000>;
	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	i2c1: i2c@30a20000 {
	compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x30a20000 0x10000>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
	status = "disabled";
	};

	i2c2: i2c@30a30000 {
	compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x30a30000 0x10000>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
	status = "disabled";
	};

	i2c3: i2c@30a40000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
	reg = <0x30a40000 0x10000>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
	status = "disabled";
	};

	i2c4: i2c@30a50000 {
	compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x30a50000 0x10000>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
	status = "disabled";
	};

	uart4: serial@30a60000 {
	compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
	reg = <0x30a60000 0x10000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
	<&clk IMX8MM_CLK_UART4_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	usdhc1: mmc@30b40000 {
	compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
	reg = <0x30b40000 0x10000>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
	<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
	<&clk IMX8MM_CLK_USDHC1_ROOT>;
	clock-names = "ipg", "ahb", "per";
	fsl,tuning-start-tap = <20>;
	fsl,tuning-step= <2>;
	bus-width = <4>;
	status = "disabled";
	};

	usdhc2: mmc@30b50000 {
	compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
	reg = <0x30b50000 0x10000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
	<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
	<&clk IMX8MM_CLK_USDHC2_ROOT>;
	clock-names = "ipg", "ahb", "per";
	fsl,tuning-start-tap = <20>;
	fsl,tuning-step= <2>;
	bus-width = <4>;
	status = "disabled";
	};

	usdhc3: mmc@30b60000 {
	compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
	reg = <0x30b60000 0x10000>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
	<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
	<&clk IMX8MM_CLK_USDHC3_ROOT>;
	clock-names = "ipg", "ahb", "per";
	fsl,tuning-start-tap = <20>;
	fsl,tuning-step= <2>;
	bus-width = <4>;
	status = "disabled";
	};

	+ flexspi: spi@30bb0000 {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ compatible = "nxp,imx8mm-fspi";
	+ reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
	+ reg-names = "fspi_base", "fspi_mmap";
	+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
	+ <&clk IMX8MM_CLK_QSPI_ROOT>;
	+ clock-names = "fspi", "fspi_en";
	+ status = "disabled";
	+ };
	+
	sdma1: dma-controller@30bd0000 {
	compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
	reg = <0x30bd0000 0x10000>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
	<&clk IMX8MM_CLK_AHB>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
	};

	fec1: ethernet@30be0000 {
	compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
	reg = <0x30be0000 0x10000>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
	<&clk IMX8MM_CLK_ENET1_ROOT>,
	<&clk IMX8MM_CLK_ENET_TIMER>,
	<&clk IMX8MM_CLK_ENET_REF>,
	<&clk IMX8MM_CLK_ENET_PHY_REF>;
	clock-names = "ipg", "ahb", "ptp",
	"enet_clk_ref", "enet_out";
	assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
	<&clk IMX8MM_CLK_ENET_TIMER>,
	<&clk IMX8MM_CLK_ENET_REF>,
	<&clk IMX8MM_CLK_ENET_TIMER>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
	<&clk IMX8MM_SYS_PLL2_100M>,
	<&clk IMX8MM_SYS_PLL2_125M>;
	assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
	fsl,num-tx-queues = <3>;
	fsl,num-rx-queues = <3>;
	status = "disabled";
	};

	};

	aips4: bus@32c00000 {
	- compatible = "simple-bus";
	+ compatible = "fsl,aips-bus", "simple-bus";
	+ reg = <0x32c00000 0x400000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x32c00000 0x32c00000 0x400000>;

	usbotg1: usb@32e40000 {
	compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
	reg = <0x32e40000 0x200>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
	clock-names = "usb1_ctrl_root_clk";
	assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
	fsl,usbphy = <&usbphynop1>;
	fsl,usbmisc = <&usbmisc1 0>;
	status = "disabled";
	};

	usbmisc1: usbmisc@32e40200 {
	compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
	#index-cells = <1>;
	reg = <0x32e40200 0x200>;
	};

	usbotg2: usb@32e50000 {
	compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
	reg = <0x32e50000 0x200>;
	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
	clock-names = "usb1_ctrl_root_clk";
	assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
	fsl,usbphy = <&usbphynop2>;
	fsl,usbmisc = <&usbmisc2 0>;
	status = "disabled";
	};

	usbmisc2: usbmisc@32e50200 {
	compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
	#index-cells = <1>;
	reg = <0x32e50200 0x200>;
	};

	};

	dma_apbh: dma-controller@33000000 {
	compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
	reg = <0x33000000 0x2000>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
	#dma-cells = <1>;
	dma-channels = <4>;
	clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
	};

	gpmi: nand-controller@33002000{
	compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
	reg-names = "gpmi-nand", "bch";
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "bch";
	clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
	<&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
	clock-names = "gpmi_io", "gpmi_bch_apb";
	dmas = <&dma_apbh 0>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	gic: interrupt-controller@38800000 {
	compatible = "arm,gic-v3";
	reg = <0x38800000 0x10000>, /* GIC Dist */
	<0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
	#interrupt-cells = <3>;
	interrupt-controller;
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	ddrc: memory-controller@3d400000 {
	compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
	reg = <0x3d400000 0x400000>;
	clock-names = "core", "pll", "alt", "apb";
	clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
	<&clk IMX8MM_DRAM_PLL>,
	<&clk IMX8MM_CLK_DRAM_ALT>,
	<&clk IMX8MM_CLK_DRAM_APB>;
	};

	ddr-pmu@3d800000 {
	compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
	reg = <0x3d800000 0x400000>;
	- interrupt-parent = <&gic>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/freescale/imx8mn-evk.dtsi b/sys/gnu/dts/arm64/freescale/imx8mn-evk.dtsi
	index 0d2ec4a2c7f2..85fc0aa38c4f 100644
	--- a/sys/gnu/dts/arm64/freescale/imx8mn-evk.dtsi
	+++ b/sys/gnu/dts/arm64/freescale/imx8mn-evk.dtsi
	@@ -1,319 +1,340 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright 2019 NXP
	*/

	#include <dt-bindings/usb/pd.h>
	#include "imx8mn.dtsi"

	/ {
	chosen {
	stdout-path = &uart2;
	};

	gpio-leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_led>;

	status {
	label = "yellow:status";
	gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
	default-state = "on";
	};
	};

	memory@40000000 {
	device_type = "memory";
	reg = <0x0 0x40000000 0 0x80000000>;
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
	regulator-name = "VSD_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};
	};

	&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy0: ethernet-phy@0 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <0>;
	};
	};
	};

	&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
	};

	&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	ptn5110: tcpc@50 {
	compatible = "nxp,ptn5110";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_typec1>;
	reg = <0x50>;
	interrupt-parent = <&gpio2>;
	interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
	status = "okay";

	port {
	typec1_dr_sw: endpoint {
	remote-endpoint = <&usb1_drd_sw>;
	};
	};

	typec1_con: connector {
	compatible = "usb-c-connector";
	label = "USB-C";
	power-role = "dual";
	data-role = "dual";
	try-power-role = "sink";
	source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
	sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
	PDO_VAR(5000, 20000, 3000)>;
	op-sink-microwatt = <15000000>;
	self-powered;
	};
	};
	};

	+&i2c3 {
	+ clock-frequency = <400000>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_i2c3>;
	+ status = "okay";
	+
	+ pca6416: gpio@20 {
	+ compatible = "ti,tca6416";
	+ reg = <0x20>;
	+ gpio-controller;
	+ #gpio-cells = <2>;
	+ };
	+};
	+
	&snvs_pwrkey {
	status = "okay";
	};

	&uart2 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
	};

	&usbotg1 {
	dr_mode = "otg";
	hnp-disable;
	srp-disable;
	adp-disable;
	usb-role-switch;
	status = "okay";

	port {
	usb1_drd_sw: endpoint {
	remote-endpoint = <&typec1_dr_sw>;
	};
	};
	};

	&usdhc2 {
	assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
	};

	&usdhc3 {
	assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
	};

	&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
	};

	&iomuxc {
	pinctrl-names = "default";

	pinctrl_fec1: fec1grp {
	fsl,pins = <
	MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
	MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
	MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
	MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
	MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
	MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
	MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
	MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
	MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
	MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
	MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
	MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
	MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
	MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
	MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
	>;
	};

	pinctrl_gpio_led: gpioledgrp {
	fsl,pins = <
	MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
	MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
	>;
	};

	pinctrl_i2c2: i2c2grp {
	fsl,pins = <
	MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
	MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
	>;
	};

	+ pinctrl_i2c3: i2c3grp {
	+ fsl,pins = <
	+ MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
	+ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
	+ >;
	+ };
	+
	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
	fsl,pins = <
	MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
	>;
	};

	pinctrl_typec1: typec1grp {
	fsl,pins = <
	MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
	MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
	>;
	};

	pinctrl_usdhc2_gpio: usdhc2grpgpio {
	fsl,pins = <
	MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
	>;
	};

	pinctrl_usdhc2: usdhc2grp {
	fsl,pins = <
	MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
	MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
	MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
	MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
	MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
	MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
	MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
	>;
	};

	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
	fsl,pins = <
	MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
	MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
	MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
	MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
	MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
	MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
	MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
	>;
	};

	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
	fsl,pins = <
	MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
	MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
	MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
	MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
	MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
	MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
	MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
	>;
	};

	pinctrl_usdhc3: usdhc3grp {
	fsl,pins = <
	MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
	MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
	MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
	MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
	MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
	MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
	MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
	MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
	MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
	MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
	MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
	>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
	fsl,pins = <
	MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
	MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
	MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
	MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
	MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
	MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
	MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
	MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
	MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
	MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
	MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
	>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
	fsl,pins = <
	MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
	MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
	MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
	MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
	MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
	MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
	MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
	MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
	MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
	MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
	MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
	>;
	};

	pinctrl_wdog: wdoggrp {
	fsl,pins = <
	MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/freescale/imx8mn.dtsi b/sys/gnu/dts/arm64/freescale/imx8mn.dtsi
	index a44b5438e842..43971abe218b 100644
	--- a/sys/gnu/dts/arm64/freescale/imx8mn.dtsi
	+++ b/sys/gnu/dts/arm64/freescale/imx8mn.dtsi
	@@ -1,817 +1,874 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright 2019 NXP
	*/

	#include <dt-bindings/clock/imx8mn-clock.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	+#include <dt-bindings/thermal/thermal.h>

	#include "imx8mn-pinfunc.h"

	/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	ethernet0 = &fec1;
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	gpio3 = &gpio4;
	gpio4 = &gpio5;
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	i2c2 = &i2c3;
	i2c3 = &i2c4;
	mmc0 = &usdhc1;
	mmc1 = &usdhc2;
	mmc2 = &usdhc3;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	spi0 = &ecspi1;
	spi1 = &ecspi2;
	spi2 = &ecspi3;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	idle-states {
	entry-method = "psci";

	cpu_pd_wait: cpu-pd-wait {
	compatible = "arm,idle-state";
	arm,psci-suspend-param = <0x0010033>;
	local-timer-stop;
	entry-latency-us = <1000>;
	exit-latency-us = <700>;
	min-residency-us = <2700>;
	};
	};

	A53_0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0>;
	clock-latency = <61036>;
	clocks = <&clk IMX8MN_CLK_ARM>;
	enable-method = "psci";
	next-level-cache = <&A53_L2>;
	operating-points-v2 = <&a53_opp_table>;
	nvmem-cells = <&cpu_speed_grade>;
	nvmem-cell-names = "speed_grade";
	cpu-idle-states = <&cpu_pd_wait>;
	+ #cooling-cells = <2>;
	};

	A53_1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x1>;
	clock-latency = <61036>;
	clocks = <&clk IMX8MN_CLK_ARM>;
	enable-method = "psci";
	next-level-cache = <&A53_L2>;
	operating-points-v2 = <&a53_opp_table>;
	cpu-idle-states = <&cpu_pd_wait>;
	+ #cooling-cells = <2>;
	};

	A53_2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x2>;
	clock-latency = <61036>;
	clocks = <&clk IMX8MN_CLK_ARM>;
	enable-method = "psci";
	next-level-cache = <&A53_L2>;
	operating-points-v2 = <&a53_opp_table>;
	cpu-idle-states = <&cpu_pd_wait>;
	+ #cooling-cells = <2>;
	};

	A53_3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x3>;
	clock-latency = <61036>;
	clocks = <&clk IMX8MN_CLK_ARM>;
	enable-method = "psci";
	next-level-cache = <&A53_L2>;
	operating-points-v2 = <&a53_opp_table>;
	cpu-idle-states = <&cpu_pd_wait>;
	+ #cooling-cells = <2>;
	};

	A53_L2: l2-cache0 {
	compatible = "cache";
	};
	};

	a53_opp_table: opp-table {
	compatible = "operating-points-v2";
	opp-shared;

	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	- opp-microvolt = <850000>;
	+ opp-microvolt = <950000>;
	opp-supported-hw = <0xb00>, <0x7>;
	clock-latency-ns = <150000>;
	opp-suspend;
	};

	opp-1400000000 {
	opp-hz = /bits/ 64 <1400000000>;
	opp-microvolt = <950000>;
	opp-supported-hw = <0x300>, <0x7>;
	clock-latency-ns = <150000>;
	opp-suspend;
	};

	opp-1500000000 {
	opp-hz = /bits/ 64 <1500000000>;
	opp-microvolt = <1000000>;
	opp-supported-hw = <0x100>, <0x3>;
	clock-latency-ns = <150000>;
	opp-suspend;
	};
	};

	osc_32k: clock-osc-32k {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "osc_32k";
	};

	osc_24m: clock-osc-24m {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "osc_24m";
	};

	clk_ext1: clock-ext1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <133000000>;
	clock-output-names = "clk_ext1";
	};

	clk_ext2: clock-ext2 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <133000000>;
	clock-output-names = "clk_ext2";
	};

	clk_ext3: clock-ext3 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <133000000>;
	clock-output-names = "clk_ext3";
	};

	clk_ext4: clock-ext4 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency= <133000000>;
	clock-output-names = "clk_ext4";
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	+ thermal-zones {
	+ cpu-thermal {
	+ polling-delay-passive = <250>;
	+ polling-delay = <2000>;
	+ thermal-sensors = <&tmu>;
	+ trips {
	+ cpu_alert0: trip0 {
	+ temperature = <85000>;
	+ hysteresis = <2000>;
	+ type = "passive";
	+ };
	+
	+ cpu_crit0: trip1 {
	+ temperature = <95000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	+ };
	+
	+ cooling-maps {
	+ map0 {
	+ trip = <&cpu_alert0>;
	+ cooling-device =
	+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	+ };
	+ };
	+ };
	+ };
	+
	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>;
	clock-frequency = <8000000>;
	arm,no-tick-in-suspend;
	};

	soc@0 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x0 0x3e000000>;

	aips1: bus@30000000 {
	- compatible = "simple-bus";
	+ compatible = "fsl,aips-bus", "simple-bus";
	reg = <0x30000000 0x400000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	gpio1: gpio@30200000 {
	compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
	reg = <0x30200000 0x10000>;
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 10 30>;
	};

	gpio2: gpio@30210000 {
	compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
	reg = <0x30210000 0x10000>;
	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 40 21>;
	};

	gpio3: gpio@30220000 {
	compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
	reg = <0x30220000 0x10000>;
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 61 26>;
	};

	gpio4: gpio@30230000 {
	compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
	reg = <0x30230000 0x10000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 21 108 11>;
	};

	gpio5: gpio@30240000 {
	compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
	reg = <0x30240000 0x10000>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 119 30>;
	};

	+ tmu: tmu@30260000 {
	+ compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
	+ reg = <0x30260000 0x10000>;
	+ clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
	+ #thermal-sensor-cells = <0>;
	+ };
	+
	wdog1: watchdog@30280000 {
	compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
	reg = <0x30280000 0x10000>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
	status = "disabled";
	};

	wdog2: watchdog@30290000 {
	compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
	reg = <0x30290000 0x10000>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
	status = "disabled";
	};

	wdog3: watchdog@302a0000 {
	compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
	reg = <0x302a0000 0x10000>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
	status = "disabled";
	};

	sdma3: dma-controller@302b0000 {
	compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
	reg = <0x302b0000 0x10000>;
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
	<&clk IMX8MN_CLK_SDMA3_ROOT>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
	};

	sdma2: dma-controller@302c0000 {
	compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
	reg = <0x302c0000 0x10000>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
	<&clk IMX8MN_CLK_SDMA2_ROOT>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
	};

	iomuxc: pinctrl@30330000 {
	compatible = "fsl,imx8mn-iomuxc";
	reg = <0x30330000 0x10000>;
	};

	gpr: iomuxc-gpr@30340000 {
	compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
	reg = <0x30340000 0x10000>;
	};

	ocotp: ocotp-ctrl@30350000 {
	compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
	reg = <0x30350000 0x10000>;
	clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpu_speed_grade: speed-grade@10 {
	reg = <0x10 4>;
	};
	};

	anatop: anatop@30360000 {
	compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
	"syscon";
	reg = <0x30360000 0x10000>;
	};

	snvs: snvs@30370000 {
	compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
	reg = <0x30370000 0x10000>;

	snvs_rtc: snvs-rtc-lp {
	compatible = "fsl,sec-v4.0-mon-rtc-lp";
	regmap = <&snvs>;
	offset = <0x34>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
	clock-names = "snvs-rtc";
	};

	snvs_pwrkey: snvs-powerkey {
	compatible = "fsl,sec-v4.0-pwrkey";
	regmap = <&snvs>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
	+ clock-names = "snvs-pwrkey";
	linux,keycode = <KEY_POWER>;
	wakeup-source;
	status = "disabled";
	};
	};

	clk: clock-controller@30380000 {
	compatible = "fsl,imx8mn-ccm";
	reg = <0x30380000 0x10000>;
	#clock-cells = <1>;
	clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
	<&clk_ext3>, <&clk_ext4>;
	clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
	"clk_ext3", "clk_ext4";
	+ assigned-clocks = <&clk IMX8MN_CLK_NOC>,
	+ <&clk IMX8MN_CLK_AUDIO_AHB>,
	+ <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
	+ <&clk IMX8MN_SYS_PLL3>;
	+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL3_OUT>,
	+ <&clk IMX8MN_SYS_PLL1_800M>;
	+ assigned-clock-rates = <0>,
	+ <400000000>,
	+ <400000000>,
	+ <600000000>;
	};

	src: reset-controller@30390000 {
	compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
	reg = <0x30390000 0x10000>;
	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	#reset-cells = <1>;
	};
	};

	aips2: bus@30400000 {
	- compatible = "simple-bus";
	+ compatible = "fsl,aips-bus", "simple-bus";
	reg = <0x30400000 0x400000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	pwm1: pwm@30660000 {
	compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
	reg = <0x30660000 0x10000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
	<&clk IMX8MN_CLK_PWM1_ROOT>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm2: pwm@30670000 {
	compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
	reg = <0x30670000 0x10000>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
	<&clk IMX8MN_CLK_PWM2_ROOT>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm3: pwm@30680000 {
	compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
	reg = <0x30680000 0x10000>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
	<&clk IMX8MN_CLK_PWM3_ROOT>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm4: pwm@30690000 {
	compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
	reg = <0x30690000 0x10000>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
	<&clk IMX8MN_CLK_PWM4_ROOT>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	system_counter: timer@306a0000 {
	compatible = "nxp,sysctr-timer";
	reg = <0x306a0000 0x20000>;
	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc_24m>;
	clock-names = "per";
	};
	};

	aips3: bus@30800000 {
	- compatible = "simple-bus";
	+ compatible = "fsl,aips-bus", "simple-bus";
	reg = <0x30800000 0x400000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	ecspi1: spi@30820000 {
	compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x30820000 0x10000>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
	<&clk IMX8MN_CLK_ECSPI1_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	ecspi2: spi@30830000 {
	compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x30830000 0x10000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
	<&clk IMX8MN_CLK_ECSPI2_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	ecspi3: spi@30840000 {
	compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x30840000 0x10000>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
	<&clk IMX8MN_CLK_ECSPI3_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart1: serial@30860000 {
	compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
	reg = <0x30860000 0x10000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
	<&clk IMX8MN_CLK_UART1_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart3: serial@30880000 {
	compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
	reg = <0x30880000 0x10000>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
	<&clk IMX8MN_CLK_UART3_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart2: serial@30890000 {
	compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
	reg = <0x30890000 0x10000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
	<&clk IMX8MN_CLK_UART2_ROOT>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	crypto: crypto@30900000 {
	compatible = "fsl,sec-v4.0";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x30900000 0x40000>;
	ranges = <0 0x30900000 0x40000>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_AHB>,
	<&clk IMX8MN_CLK_IPG_ROOT>;
	clock-names = "aclk", "ipg";

	- sec_jr0: jr0@1000 {
	+ sec_jr0: jr@1000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x1000 0x1000>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	};

	- sec_jr1: jr1@2000 {
	+ sec_jr1: jr@2000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x2000 0x1000>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	};

	- sec_jr2: jr2@3000 {
	+ sec_jr2: jr@3000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x3000 0x1000>;
	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	i2c1: i2c@30a20000 {
	compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x30a20000 0x10000>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
	status = "disabled";
	};

	i2c2: i2c@30a30000 {
	compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x30a30000 0x10000>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
	status = "disabled";
	};

	i2c3: i2c@30a40000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
	reg = <0x30a40000 0x10000>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
	status = "disabled";
	};

	i2c4: i2c@30a50000 {
	compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x30a50000 0x10000>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
	status = "disabled";
	};

	uart4: serial@30a60000 {
	compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
	reg = <0x30a60000 0x10000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
	<&clk IMX8MN_CLK_UART4_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	usdhc1: mmc@30b40000 {
	compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
	reg = <0x30b40000 0x10000>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
	<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
	<&clk IMX8MN_CLK_USDHC1_ROOT>;
	clock-names = "ipg", "ahb", "per";
	fsl,tuning-start-tap = <20>;
	fsl,tuning-step= <2>;
	bus-width = <4>;
	status = "disabled";
	};

	usdhc2: mmc@30b50000 {
	compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
	reg = <0x30b50000 0x10000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
	<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
	<&clk IMX8MN_CLK_USDHC2_ROOT>;
	clock-names = "ipg", "ahb", "per";
	fsl,tuning-start-tap = <20>;
	fsl,tuning-step= <2>;
	bus-width = <4>;
	status = "disabled";
	};

	usdhc3: mmc@30b60000 {
	compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
	reg = <0x30b60000 0x10000>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
	<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
	<&clk IMX8MN_CLK_USDHC3_ROOT>;
	clock-names = "ipg", "ahb", "per";
	fsl,tuning-start-tap = <20>;
	fsl,tuning-step= <2>;
	bus-width = <4>;
	status = "disabled";
	};

	sdma1: dma-controller@30bd0000 {
	compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
	reg = <0x30bd0000 0x10000>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
	- <&clk IMX8MN_CLK_SDMA1_ROOT>;
	+ <&clk IMX8MN_CLK_AHB>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
	};

	fec1: ethernet@30be0000 {
	compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
	reg = <0x30be0000 0x10000>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
	<&clk IMX8MN_CLK_ENET1_ROOT>,
	<&clk IMX8MN_CLK_ENET_TIMER>,
	<&clk IMX8MN_CLK_ENET_REF>,
	<&clk IMX8MN_CLK_ENET_PHY_REF>;
	clock-names = "ipg", "ahb", "ptp",
	"enet_clk_ref", "enet_out";
	assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
	<&clk IMX8MN_CLK_ENET_TIMER>,
	<&clk IMX8MN_CLK_ENET_REF>,
	<&clk IMX8MN_CLK_ENET_TIMER>;
	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
	<&clk IMX8MN_SYS_PLL2_100M>,
	<&clk IMX8MN_SYS_PLL2_125M>;
	assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
	fsl,num-tx-queues = <3>;
	fsl,num-rx-queues = <3>;
	status = "disabled";
	};

	};

	aips4: bus@32c00000 {
	- compatible = "simple-bus";
	+ compatible = "fsl,aips-bus", "simple-bus";
	reg = <0x32c00000 0x400000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	usbotg1: usb@32e40000 {
	compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
	reg = <0x32e40000 0x200>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
	clock-names = "usb1_ctrl_root_clk";
	assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
	assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
	fsl,usbphy = <&usbphynop1>;
	fsl,usbmisc = <&usbmisc1 0>;
	status = "disabled";
	};

	usbmisc1: usbmisc@32e40200 {
	compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
	#index-cells = <1>;
	reg = <0x32e40200 0x200>;
	};

	usbotg2: usb@32e50000 {
	compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
	reg = <0x32e50000 0x200>;
	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
	clock-names = "usb1_ctrl_root_clk";
	assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
	<&clk IMX8MN_CLK_USB_CORE_REF>;
	assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
	<&clk IMX8MN_SYS_PLL1_100M>;
	fsl,usbphy = <&usbphynop2>;
	fsl,usbmisc = <&usbmisc2 0>;
	status = "disabled";
	};

	usbmisc2: usbmisc@32e50200 {
	compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
	#index-cells = <1>;
	reg = <0x32e50200 0x200>;
	};

	};

	dma_apbh: dma-controller@33000000 {
	compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
	reg = <0x33000000 0x2000>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
	#dma-cells = <1>;
	dma-channels = <4>;
	clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
	};

	gpmi: nand-controller@33002000 {
	compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
	reg-names = "gpmi-nand", "bch";
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "bch";
	clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
	<&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
	clock-names = "gpmi_io", "gpmi_bch_apb";
	dmas = <&dma_apbh 0>;
	dma-names = "rx-tx";
	status = "disabled";
	};

	gic: interrupt-controller@38800000 {
	compatible = "arm,gic-v3";
	reg = <0x38800000 0x10000>,
	<0x38880000 0xc0000>;
	#interrupt-cells = <3>;
	interrupt-controller;
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	ddrc: memory-controller@3d400000 {
	compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
	reg = <0x3d400000 0x400000>;
	clock-names = "core", "pll", "alt", "apb";
	clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
	<&clk IMX8MN_DRAM_PLL>,
	<&clk IMX8MN_CLK_DRAM_ALT>,
	<&clk IMX8MN_CLK_DRAM_APB>;
	};

	ddr-pmu@3d800000 {
	compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
	reg = <0x3d800000 0x400000>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	usbphynop1: usbphynop1 {
	compatible = "usb-nop-xceiv";
	clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
	assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
	clock-names = "main_clk";
	};

	usbphynop2: usbphynop2 {
	compatible = "usb-nop-xceiv";
	clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
	assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
	clock-names = "main_clk";
	};
	};
	diff --git a/sys/gnu/dts/arm64/freescale/imx8mp-evk.dts b/sys/gnu/dts/arm64/freescale/imx8mp-evk.dts
	new file mode 100644
	index 000000000000..3da1fff3d6fd
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/freescale/imx8mp-evk.dts
	@@ -0,0 +1,270 @@
	+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	+/*
	+ * Copyright 2019 NXP
	+ */
	+
	+/dts-v1/;
	+
	+#include "imx8mp.dtsi"
	+
	+/ {
	+ model = "NXP i.MX8MPlus EVK board";
	+ compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
	+
	+ chosen {
	+ stdout-path = &uart2;
	+ };
	+
	+ gpio-leds {
	+ compatible = "gpio-leds";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_gpio_led>;
	+
	+ status {
	+ label = "yellow:status";
	+ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
	+ default-state = "on";
	+ };
	+ };
	+
	+ memory@40000000 {
	+ device_type = "memory";
	+ reg = <0x0 0x40000000 0 0xc0000000>,
	+ <0x1 0x00000000 0 0xc0000000>;
	+ };
	+
	+ reg_usdhc2_vmmc: regulator-usdhc2 {
	+ compatible = "regulator-fixed";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
	+ regulator-name = "VSD_3V3";
	+ regulator-min-microvolt = <3300000>;
	+ regulator-max-microvolt = <3300000>;
	+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
	+ enable-active-high;
	+ };
	+};
	+
	+&fec {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_fec>;
	+ phy-mode = "rgmii-id";
	+ phy-handle = <&ethphy1>;
	+ fsl,magic-packet;
	+ status = "okay";
	+
	+ mdio {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ ethphy1: ethernet-phy@1 {
	+ compatible = "ethernet-phy-ieee802.3-c22";
	+ reg = <1>;
	+ eee-broken-1000t;
	+ reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
	+ };
	+ };
	+};
	+
	+&i2c3 {
	+ clock-frequency = <400000>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_i2c3>;
	+ status = "okay";
	+
	+ pca6416: gpio@20 {
	+ compatible = "ti,tca6416";
	+ reg = <0x20>;
	+ gpio-controller;
	+ #gpio-cells = <2>;
	+ };
	+};
	+
	+&snvs_pwrkey {
	+ status = "okay";
	+};
	+
	+&uart2 {
	+ /* console */
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_uart2>;
	+ status = "okay";
	+};
	+
	+&usdhc2 {
	+ assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
	+ assigned-clock-rates = <400000000>;
	+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
	+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	+ vmmc-supply = <&reg_usdhc2_vmmc>;
	+ bus-width = <4>;
	+ status = "okay";
	+};
	+
	+&usdhc3 {
	+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
	+ assigned-clock-rates = <400000000>;
	+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
	+ pinctrl-0 = <&pinctrl_usdhc3>;
	+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	+ bus-width = <8>;
	+ non-removable;
	+ status = "okay";
	+};
	+
	+&wdog1 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_wdog>;
	+ fsl,ext-reset-output;
	+ status = "okay";
	+};
	+
	+&iomuxc {
	+ pinctrl-names = "default";
	+
	+ pinctrl_fec: fecgrp {
	+ fsl,pins = <
	+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
	+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
	+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
	+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
	+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
	+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
	+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
	+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
	+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
	+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
	+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
	+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
	+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
	+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
	+ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
	+ >;
	+ };
	+
	+ pinctrl_gpio_led: gpioledgrp {
	+ fsl,pins = <
	+ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
	+ >;
	+ };
	+
	+ pinctrl_i2c3: i2c3grp {
	+ fsl,pins = <
	+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
	+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
	+ >;
	+ };
	+
	+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
	+ fsl,pins = <
	+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
	+ >;
	+ };
	+
	+ pinctrl_uart2: uart2grp {
	+ fsl,pins = <
	+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
	+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
	+ >;
	+ };
	+
	+ pinctrl_usdhc2: usdhc2grp {
	+ fsl,pins = <
	+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
	+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
	+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
	+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
	+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
	+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
	+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
	+ >;
	+ };
	+
	+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
	+ fsl,pins = <
	+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
	+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
	+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
	+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
	+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
	+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
	+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
	+ >;
	+ };
	+
	+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
	+ fsl,pins = <
	+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
	+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
	+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
	+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
	+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
	+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
	+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
	+ >;
	+ };
	+
	+ pinctrl_usdhc2_gpio: usdhc2grp-gpio {
	+ fsl,pins = <
	+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
	+ >;
	+ };
	+
	+ pinctrl_usdhc3: usdhc3grp {
	+ fsl,pins = <
	+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
	+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
	+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
	+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
	+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
	+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
	+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
	+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
	+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
	+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
	+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
	+ >;
	+ };
	+
	+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
	+ fsl,pins = <
	+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
	+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
	+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
	+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
	+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
	+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
	+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
	+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
	+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
	+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
	+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
	+ >;
	+ };
	+
	+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
	+ fsl,pins = <
	+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
	+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
	+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
	+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
	+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
	+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
	+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
	+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
	+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
	+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
	+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
	+ >;
	+ };
	+
	+ pinctrl_wdog: wdoggrp {
	+ fsl,pins = <
	+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
	+ >;
	+ };
	+};
	diff --git a/sys/gnu/dts/arm64/freescale/imx8mp-pinfunc.h b/sys/gnu/dts/arm64/freescale/imx8mp-pinfunc.h
	new file mode 100644
	index 000000000000..319ab34cab3e
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/freescale/imx8mp-pinfunc.h
	@@ -0,0 +1,931 @@
	+/* SPDX-License-Identifier: GPL-2.0+ */
	+/*
	+ * Copyright 2019 NXP
	+ */
	+
	+#ifndef __DTS_IMX8MP_PINFUNC_H
	+#define __DTS_IMX8MP_PINFUNC_H
	+
	+/*
	+ * The pin function ID is a tuple of
	+ * <mux_reg conf_reg input_reg mux_mode input_val>
	+ */
	+#define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO00__MEDIAMIX_ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO00__ANAMIX_REF_CLK_32K 0x014 0x274 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO00__SJC_FAIL 0x014 0x274 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO01__MEDIAMIX_ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO01__ANAMIX_REF_CLK_24M 0x018 0x278 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO01__SJC_ACTIVE 0x018 0x278 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO02__MEDIAMIX_ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_ANY 0x01C 0x27C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO02__SJC_DE_B 0x01C 0x27C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x020 0x280 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x020 0x280 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO03__MEDIAMIX_ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVENT00 0x020 0x280 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO03__ANAMIX_XTAL_OK 0x020 0x280 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO03__SJC_DONE 0x020 0x280 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x024 0x284 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x024 0x284 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO04__MEDIAMIX_ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVENT01 0x024 0x284 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO04__ANAMIX_XTAL_OK_LV 0x024 0x284 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO04__USDHC1_TEST_TRIG 0x024 0x284 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x028 0x288 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO05__M7_NMI 0x028 0x288 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO05__MEDIAMIX_ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY 0x028 0x288 0x554 0x5 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT 0x028 0x288 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO05__USDHC2_TEST_TRIG 0x028 0x288 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x02C 0x28C 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO06__ENET_QOS_MDC 0x02C 0x28C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO06__MEDIAMIX_ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x02C 0x28C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3 0x02C 0x28C 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO06__ECSPI1_TEST_TRIG 0x02C 0x28C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x030 0x290 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO07__ENET_QOS_MDIO 0x030 0x290 0x590 0x1 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO07__MEDIAMIX_ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 0x030 0x290 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4 0x030 0x290 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO07__ECSPI2_TEST_TRIG 0x030 0x290 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x034 0x294 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN 0x034 0x294 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT 0x034 0x294 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO08__MEDIAMIX_ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN 0x034 0x294 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO08__USDHC2_RESET_B 0x034 0x294 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO08__CCMSRCGPCMIX_WAIT 0x034 0x294 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO08__FLEXSPI_TEST_TRIG 0x034 0x294 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x038 0x298 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x038 0x298 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x038 0x298 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO09__MEDIAMIX_ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x038 0x298 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO09__AUDIOMIX_EXT_EVENT00 0x038 0x298 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO09__CCMSRCGPCMIX_STOP 0x038 0x298 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO09__RAWNAND_TEST_TRIG 0x038 0x298 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x03C 0x29C 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO10__HSIOMIX_usb1_OTG_ID 0x03C 0x29C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x03C 0x29C 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO10__OCOTP_FUSE_LATCHED 0x03C 0x29C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x040 0x2A0 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO11__HSIOMIX_usb2_OTG_ID 0x040 0x2A0 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x040 0x2A0 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELECT 0x040 0x2A0 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY 0x040 0x2A0 0x554 0x5 0x1
	+#define MX8MP_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_OUT0 0x040 0x2A0 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO11__CAAM_RNG_OSC_OBS 0x040 0x2A0 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x044 0x2A4 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO12__HSIOMIX_usb1_OTG_PWR 0x044 0x2A4 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO12__AUDIOMIX_EXT_EVENT01 0x044 0x2A4 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO12__CCMSRCGPCMIX_OUT1 0x044 0x2A4 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO12__CSU_CSU_ALARM_AUT00 0x044 0x2A4 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x048 0x2A8 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO13__HSIOMIX_usb1_OTG_OC 0x048 0x2A8 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x048 0x2A8 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO13__CCMSRCGPCMIX_OUT2 0x048 0x2A8 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO13__CSU_CSU_ALARM_AUT01 0x048 0x2A8 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04C 0x2AC 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO14__HSIOMIX_usb2_OTG_PWR 0x04C 0x2AC 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B 0x04C 0x2AC 0x608 0x4 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x04C 0x2AC 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO14__CCMSRCGPCMIX_CLKO1 0x04C 0x2AC 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO14__CSU_CSU_ALARM_AUT02 0x04C 0x2AC 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x050 0x2B0 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO15__HSIOMIX_usb2_OTG_OC 0x050 0x2B0 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP 0x050 0x2B0 0x634 0x4 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x050 0x2B0 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 0x050 0x2B0 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_GPIO1_IO15__CSU_CSU_INT_DEB 0x050 0x2B0 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x054 0x2B4 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00 0x054 0x2B4 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 0x054 0x2B4 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE 0x054 0x2B4 0x630 0x6 0x0
	+#define MX8MP_IOMUXC_ENET_MDC__SIM_M_HADDR15 0x054 0x2B4 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x058 0x2B8 0x590 0x0 0x1
	+#define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC 0x058 0x2B8 0x528 0x2 0x0
	+#define MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 0x058 0x2B8 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5 0x058 0x2B8 0x624 0x6 0x0
	+#define MX8MP_IOMUXC_ENET_MDIO__SIM_M_HADDR16 0x058 0x2B8 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x05C 0x2BC 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK 0x05C 0x2BC 0x524 0x2 0x0
	+#define MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x05C 0x2BC 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6 0x05C 0x2BC 0x628 0x6 0x0
	+#define MX8MP_IOMUXC_ENET_TD3__SIM_M_HADDR17 0x05C 0x2BC 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x060 0x2C0 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x060 0x2C0 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00 0x060 0x2C0 0x51C 0x2 0x0
	+#define MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x060 0x2C0 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7 0x060 0x2C0 0x62C 0x6 0x0
	+#define MX8MP_IOMUXC_ENET_TD2__SIM_M_HADDR18 0x060 0x2C0 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x064 0x2C4 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC 0x064 0x2C4 0x520 0x2 0x0
	+#define MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x064 0x2C4 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ENET_TD1__USDHC3_CD_B 0x064 0x2C4 0x608 0x6 0x1
	+#define MX8MP_IOMUXC_ENET_TD1__SIM_M_HADDR19 0x064 0x2C4 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x068 0x2C8 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK 0x068 0x2C8 0x518 0x2 0x0
	+#define MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x068 0x2C8 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ENET_TD0__USDHC3_WP 0x068 0x2C8 0x634 0x6 0x1
	+#define MX8MP_IOMUXC_ENET_TD0__SIM_M_HADDR20 0x068 0x2C8 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x06C 0x2CC 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK 0x06C 0x2CC 0x514 0x2 0x0
	+#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SPDIF_OUT 0x06C 0x2CC 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x06C 0x2CC 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0 0x06C 0x2CC 0x610 0x6 0x0
	+#define MX8MP_IOMUXC_ENET_TX_CTL__SIM_M_HADDR21 0x06C 0x2CC 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x070 0x2D0 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER 0x070 0x2D0 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00 0x070 0x2D0 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x070 0x2D0 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1 0x070 0x2D0 0x614 0x6 0x0
	+#define MX8MP_IOMUXC_ENET_TXC__SIM_M_HADDR22 0x070 0x2D0 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x074 0x2D4 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC 0x074 0x2D4 0x540 0x2 0x0
	+#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03 0x074 0x2D4 0x4CC 0x3 0x1
	+#define MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x074 0x2D4 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2 0x074 0x2D4 0x618 0x6 0x0
	+#define MX8MP_IOMUXC_ENET_RX_CTL__SIM_M_HADDR23 0x074 0x2D4 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x078 0x2D8 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x078 0x2D8 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK 0x078 0x2D8 0x53C 0x2 0x0
	+#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_BIT_STREAM02 0x078 0x2D8 0x4C8 0x3 0x1
	+#define MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x078 0x2D8 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3 0x078 0x2D8 0x61C 0x6 0x0
	+#define MX8MP_IOMUXC_ENET_RXC__SIM_M_HADDR24 0x078 0x2D8 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x07C 0x2DC 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 0x07C 0x2DC 0x534 0x2 0x0
	+#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_BIT_STREAM01 0x07C 0x2DC 0x4C4 0x3 0x1
	+#define MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x07C 0x2DC 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4 0x07C 0x2DC 0x620 0x6 0x0
	+#define MX8MP_IOMUXC_ENET_RD0__SIM_M_HADDR25 0x07C 0x2DC 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x080 0x2E0 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC 0x080 0x2E0 0x538 0x2 0x0
	+#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_BIT_STREAM00 0x080 0x2E0 0x4C0 0x3 0x1
	+#define MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x080 0x2E0 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ENET_RD1__USDHC3_RESET_B 0x080 0x2E0 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_ENET_RD1__SIM_M_HADDR26 0x080 0x2E0 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x084 0x2E4 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK 0x084 0x2E4 0x530 0x2 0x0
	+#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_CLK 0x084 0x2E4 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x084 0x2E4 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK 0x084 0x2E4 0x604 0x6 0x0
	+#define MX8MP_IOMUXC_ENET_RD2__SIM_M_HADDR27 0x084 0x2E4 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x088 0x2E8 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SAI7_MCLK 0x088 0x2E8 0x52C 0x2 0x0
	+#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SPDIF_IN 0x088 0x2E8 0x544 0x3 0x0
	+#define MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x088 0x2E8 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD 0x088 0x2E8 0x60C 0x6 0x0
	+#define MX8MP_IOMUXC_ENET_RD3__SIM_M_HADDR28 0x088 0x2E8 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x08C 0x2EC 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD1_CLK__ENET1_MDC 0x08C 0x2EC 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SD1_CLK__I2C5_SCL 0x08C 0x2EC 0x5C4 0x3 0x0
	+#define MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x08C 0x2EC 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_CLK__UART1_DTE_RX 0x08C 0x2EC 0x5E8 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x08C 0x2EC 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD1_CLK__SIM_M_HADDR29 0x08C 0x2EC 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x090 0x2F0 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD1_CMD__ENET1_MDIO 0x090 0x2F0 0x57C 0x1 0x0
	+#define MX8MP_IOMUXC_SD1_CMD__I2C5_SDA 0x090 0x2F0 0x5C8 0x3 0x0
	+#define MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x090 0x2F0 0x5E8 0x4 0x1
	+#define MX8MP_IOMUXC_SD1_CMD__UART1_DTE_TX 0x090 0x2F0 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x090 0x2F0 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD1_CMD__SIM_M_HADDR30 0x090 0x2F0 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x094 0x2F4 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1 0x094 0x2F4 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x094 0x2F4 0x5CC 0x3 0x0
	+#define MX8MP_IOMUXC_SD1_DATA0__UART1_DCE_RTS 0x094 0x2F4 0x5E4 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_DATA0__UART1_DTE_CTS 0x094 0x2F4 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x094 0x2F4 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD1_DATA0__SIM_M_HADDR31 0x094 0x2F4 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x098 0x2F8 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0 0x098 0x2F8 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x098 0x2F8 0x5D0 0x3 0x0
	+#define MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x098 0x2F8 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_DATA1__UART1_DTE_RTS 0x098 0x2F8 0x5E4 0x4 0x1
	+#define MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x098 0x2F8 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD1_DATA1__SIM_M_HBURST00 0x098 0x2F8 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x09C 0x2FC 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0 0x09C 0x2FC 0x580 0x1 0x0
	+#define MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL 0x09C 0x2FC 0x5BC 0x3 0x0
	+#define MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x09C 0x2FC 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_DATA2__UART2_DTE_RX 0x09C 0x2FC 0x5F0 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x09C 0x2FC 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD1_DATA2__SIM_M_HBURST01 0x09C 0x2FC 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x0A0 0x300 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1 0x0A0 0x300 0x584 0x1 0x0
	+#define MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA 0x0A0 0x300 0x5C0 0x3 0x0
	+#define MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x0A0 0x300 0x5F0 0x4 0x1
	+#define MX8MP_IOMUXC_SD1_DATA3__UART2_DTE_TX 0x0A0 0x300 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x0A0 0x300 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD1_DATA3__SIM_M_HBURST02 0x0A0 0x300 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x0A4 0x304 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD1_DATA4__ENET1_RGMII_TX_CTL 0x0A4 0x304 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL 0x0A4 0x304 0x5A4 0x3 0x0
	+#define MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x0A4 0x304 0x5EC 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS 0x0A4 0x304 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x0A4 0x304 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD1_DATA4__SIM_M_HRESP 0x0A4 0x304 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x0A8 0x308 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD1_DATA5__ENET1_TX_ER 0x0A8 0x308 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x0A8 0x308 0x5A8 0x3 0x0
	+#define MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x0A8 0x308 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS 0x0A8 0x308 0x5EC 0x4 0x1
	+#define MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x0A8 0x308 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD1_DATA5__TPSMP_HDATA05 0x0A8 0x308 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x0AC 0x30C 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD1_DATA6__ENET1_RGMII_RX_CTL 0x0AC 0x30C 0x588 0x1 0x0
	+#define MX8MP_IOMUXC_SD1_DATA6__I2C2_SCL 0x0AC 0x30C 0x5AC 0x3 0x0
	+#define MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x0AC 0x30C 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX 0x0AC 0x30C 0x5F8 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x0AC 0x30C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD1_DATA6__TPSMP_HDATA06 0x0AC 0x30C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x0B0 0x310 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD1_DATA7__ENET1_RX_ER 0x0B0 0x310 0x58C 0x1 0x0
	+#define MX8MP_IOMUXC_SD1_DATA7__I2C2_SDA 0x0B0 0x310 0x5B0 0x3 0x0
	+#define MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x0B0 0x310 0x5F8 0x4 0x1
	+#define MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX 0x0B0 0x310 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x0B0 0x310 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD1_DATA7__TPSMP_HDATA07 0x0B0 0x310 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x0B4 0x314 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD1_RESET_B__ENET1_TX_CLK 0x0B4 0x314 0x578 0x1 0x0
	+#define MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x0B4 0x314 0x5B4 0x3 0x0
	+#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x0B4 0x314 0x5F4 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS 0x0B4 0x314 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x0B4 0x314 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD1_RESET_B__ECSPI3_TEST_TRIG 0x0B4 0x314 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x0B8 0x318 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x0B8 0x318 0x5B8 0x3 0x0
	+#define MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x0B8 0x318 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS 0x0B8 0x318 0x5F4 0x4 0x1
	+#define MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x0B8 0x318 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD1_STROBE__USDHC3_TEST_TRIG 0x0B8 0x318 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x0BC 0x31C 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0BC 0x31C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK 0x0BC 0x31C 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x0C0 0x320 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD2_CLK__ECSPI2_SCLK 0x0C0 0x320 0x568 0x2 0x0
	+#define MX8MP_IOMUXC_SD2_CLK__UART4_DCE_RX 0x0C0 0x320 0x600 0x3 0x0
	+#define MX8MP_IOMUXC_SD2_CLK__UART4_DTE_TX 0x0C0 0x320 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x0C0 0x320 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0C0 0x320 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_SD2_CLK__OBSERVE_MUX_OUT00 0x0C0 0x320 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x0C4 0x324 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD2_CMD__ECSPI2_MOSI 0x0C4 0x324 0x570 0x2 0x0
	+#define MX8MP_IOMUXC_SD2_CMD__UART4_DCE_TX 0x0C4 0x324 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SD2_CMD__UART4_DTE_RX 0x0C4 0x324 0x600 0x3 0x1
	+#define MX8MP_IOMUXC_SD2_CMD__AUDIOMIX_CLK 0x0C4 0x324 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x0C4 0x324 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0C4 0x324 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_SD2_CMD__OBSERVE_MUX_OUT01 0x0C4 0x324 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x0C8 0x328 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD2_DATA0__I2C4_SDA 0x0C8 0x328 0x5C0 0x2 0x1
	+#define MX8MP_IOMUXC_SD2_DATA0__UART2_DCE_RX 0x0C8 0x328 0x5F0 0x3 0x2
	+#define MX8MP_IOMUXC_SD2_DATA0__UART2_DTE_TX 0x0C8 0x328 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_BIT_STREAM00 0x0C8 0x328 0x4C0 0x4 0x2
	+#define MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x0C8 0x328 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x0C8 0x328 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_SD2_DATA0__OBSERVE_MUX_OUT02 0x0C8 0x328 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x0CC 0x32C 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD2_DATA1__I2C4_SCL 0x0CC 0x32C 0x5BC 0x2 0x1
	+#define MX8MP_IOMUXC_SD2_DATA1__UART2_DCE_TX 0x0CC 0x32C 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SD2_DATA1__UART2_DTE_RX 0x0CC 0x32C 0x5F0 0x3 0x3
	+#define MX8MP_IOMUXC_SD2_DATA1__AUDIOMIX_BIT_STREAM01 0x0CC 0x32C 0x4C4 0x4 0x1
	+#define MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x0CC 0x32C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0CC 0x32C 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_SD2_DATA1__OBSERVE_MUX_OUT03 0x0CC 0x32C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x0D0 0x330 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD2_DATA2__ECSPI2_SS0 0x0D0 0x330 0x574 0x2 0x0
	+#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_SPDIF_OUT 0x0D0 0x330 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_BIT_STREAM02 0x0D0 0x330 0x4C8 0x4 0x1
	+#define MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x0D0 0x330 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0D0 0x330 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_SD2_DATA2__OBSERVE_MUX_OUT04 0x0D0 0x330 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x0D4 0x334 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD2_DATA3__ECSPI2_MISO 0x0D4 0x334 0x56C 0x2 0x0
	+#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF_IN 0x0D4 0x334 0x544 0x3 0x1
	+#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x2
	+#define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x0D4 0x334 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0D4 0x334 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x0D8 0x338 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0D8 0x338 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x0D8 0x338 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x0DC 0x33C 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x0DC 0x33C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI 0x0DC 0x33C 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_SD2_WP__SIM_M_HMASTLOCK 0x0DC 0x33C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_ALE__RAWNAND_ALE 0x0E0 0x340 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x0E0 0x340 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK 0x0E0 0x340 0x4E8 0x2 0x0
	+#define MX8MP_IOMUXC_NAND_ALE__MEDIAMIX_ISP_FL_TRIG_0 0x0E0 0x340 0x5D4 0x3 0x1
	+#define MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX 0x0E0 0x340 0x5F8 0x4 0x2
	+#define MX8MP_IOMUXC_NAND_ALE__UART3_DTE_TX 0x0E0 0x340 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x0E0 0x340 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_ALE__CORESIGHT_TRACE_CLK 0x0E0 0x340 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_ALE__SIM_M_HPROT00 0x0E0 0x340 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_CE0_B__RAWNAND_CE0_B 0x0E4 0x344 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x0E4 0x344 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00 0x0E4 0x344 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_NAND_CE0_B__MEDIAMIX_ISP_SHUTTER_TRIG_0 0x0E4 0x344 0x5DC 0x3 0x1
	+#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX 0x0E4 0x344 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DTE_RX 0x0E4 0x344 0x5F8 0x4 0x3
	+#define MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x0E4 0x344 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_CE0_B__CORESIGHT_TRACE_CTL 0x0E4 0x344 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_CE0_B__SIM_M_HPROT01 0x0E4 0x344 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_CE1_B__RAWNAND_CE1_B 0x0E8 0x348 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_CE1_B__FLEXSPI_A_SS1_B 0x0E8 0x348 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x0E8 0x348 0x630 0x2 0x1
	+#define MX8MP_IOMUXC_NAND_CE1_B__I2C4_SCL 0x0E8 0x348 0x5BC 0x4 0x2
	+#define MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x0E8 0x348 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_CE1_B__CORESIGHT_TRACE00 0x0E8 0x348 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_CE1_B__SIM_M_HPROT02 0x0E8 0x348 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_CE2_B__RAWNAND_CE2_B 0x0EC 0x34C 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_CE2_B__FLEXSPI_B_SS0_B 0x0EC 0x34C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x0EC 0x34C 0x624 0x2 0x1
	+#define MX8MP_IOMUXC_NAND_CE2_B__I2C4_SDA 0x0EC 0x34C 0x5C0 0x4 0x2
	+#define MX8MP_IOMUXC_NAND_CE2_B__GPIO3_IO03 0x0EC 0x34C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_CE2_B__CORESIGHT_TRACE01 0x0EC 0x34C 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_CE2_B__SIM_M_HPROT03 0x0EC 0x34C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_CE3_B__RAWNAND_CE3_B 0x0F0 0x350 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_CE3_B__FLEXSPI_B_SS1_B 0x0F0 0x350 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x0F0 0x350 0x628 0x2 0x1
	+#define MX8MP_IOMUXC_NAND_CE3_B__I2C3_SDA 0x0F0 0x350 0x5B8 0x4 0x1
	+#define MX8MP_IOMUXC_NAND_CE3_B__GPIO3_IO04 0x0F0 0x350 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_CE3_B__CORESIGHT_TRACE02 0x0F0 0x350 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_CE3_B__SIM_M_HADDR00 0x0F0 0x350 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_CLE__RAWNAND_CLE 0x0F4 0x354 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_CLE__FLEXSPI_B_SCLK 0x0F4 0x354 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x0F4 0x354 0x62C 0x2 0x1
	+#define MX8MP_IOMUXC_NAND_CLE__UART4_DCE_RX 0x0F4 0x354 0x600 0x4 0x2
	+#define MX8MP_IOMUXC_NAND_CLE__UART4_DTE_TX 0x0F4 0x354 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_NAND_CLE__GPIO3_IO05 0x0F4 0x354 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_CLE__CORESIGHT_TRACE03 0x0F4 0x354 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_CLE__SIM_M_HADDR01 0x0F4 0x354 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_DATA00__RAWNAND_DATA00 0x0F8 0x358 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x0F8 0x358 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00 0x0F8 0x358 0x4E4 0x2 0x0
	+#define MX8MP_IOMUXC_NAND_DATA00__MEDIAMIX_ISP_FLASH_TRIG_0 0x0F8 0x358 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX 0x0F8 0x358 0x600 0x4 0x3
	+#define MX8MP_IOMUXC_NAND_DATA00__UART4_DTE_TX 0x0F8 0x358 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x0F8 0x358 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_DATA00__CORESIGHT_TRACE04 0x0F8 0x358 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_DATA00__SIM_M_HADDR02 0x0F8 0x358 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_DATA01__RAWNAND_DATA01 0x0FC 0x35C 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x0FC 0x35C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC 0x0FC 0x35C 0x4EC 0x2 0x0
	+#define MX8MP_IOMUXC_NAND_DATA01__MEDIAMIX_ISP_PRELIGHT_TRIG_0 0x0FC 0x35C 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_NAND_DATA01__UART4_DCE_TX 0x0FC 0x35C 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_NAND_DATA01__UART4_DTE_RX 0x0FC 0x35C 0x600 0x4 0x4
	+#define MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x0FC 0x35C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_DATA01__CORESIGHT_TRACE05 0x0FC 0x35C 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_DATA01__SIM_M_HADDR03 0x0FC 0x35C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_DATA02__RAWNAND_DATA02 0x100 0x360 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x100 0x360 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_NAND_DATA02__USDHC3_CD_B 0x100 0x360 0x608 0x2 0x2
	+#define MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x100 0x360 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_NAND_DATA02__UART4_DTE_RTS 0x100 0x360 0x5FC 0x3 0x0
	+#define MX8MP_IOMUXC_NAND_DATA02__I2C4_SDA 0x100 0x360 0x5C0 0x4 0x3
	+#define MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x100 0x360 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_DATA02__CORESIGHT_TRACE06 0x100 0x360 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_DATA02__SIM_M_HADDR04 0x100 0x360 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_DATA03__RAWNAND_DATA03 0x104 0x364 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x104 0x364 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_NAND_DATA03__USDHC3_WP 0x104 0x364 0x634 0x2 0x2
	+#define MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x104 0x364 0x5FC 0x3 0x1
	+#define MX8MP_IOMUXC_NAND_DATA03__UART4_DTE_CTS 0x104 0x364 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_NAND_DATA03__MEDIAMIX_ISP_FL_TRIG_1 0x104 0x364 0x5D8 0x4 0x1
	+#define MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x104 0x364 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_DATA03__CORESIGHT_TRACE07 0x104 0x364 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_DATA03__SIM_M_HADDR05 0x104 0x364 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_DATA04__RAWNAND_DATA04 0x108 0x368 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_B_DATA00 0x108 0x368 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x108 0x368 0x610 0x2 0x1
	+#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_A_DATA04 0x108 0x368 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_NAND_DATA04__MEDIAMIX_ISP_SHUTTER_TRIG_1 0x108 0x368 0x5E0 0x4 0x1
	+#define MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10 0x108 0x368 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_DATA04__CORESIGHT_TRACE08 0x108 0x368 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_DATA04__SIM_M_HADDR06 0x108 0x368 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_DATA05__RAWNAND_DATA05 0x10C 0x36C 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_B_DATA01 0x10C 0x36C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x10C 0x36C 0x614 0x2 0x1
	+#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_A_DATA05 0x10C 0x36C 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_NAND_DATA05__MEDIAMIX_ISP_FLASH_TRIG_1 0x10C 0x36C 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11 0x10C 0x36C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_DATA05__CORESIGHT_TRACE09 0x10C 0x36C 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_DATA05__SIM_M_HADDR07 0x10C 0x36C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_DATA06__RAWNAND_DATA06 0x110 0x370 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_B_DATA02 0x110 0x370 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x110 0x370 0x618 0x2 0x1
	+#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_A_DATA06 0x110 0x370 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_NAND_DATA06__MEDIAMIX_ISP_PRELIGHT_TRIG_1 0x110 0x370 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12 0x110 0x370 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_DATA06__CORESIGHT_TRACE10 0x110 0x370 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_DATA06__SIM_M_HADDR08 0x110 0x370 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_DATA07__RAWNAND_DATA07 0x114 0x374 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_B_DATA03 0x114 0x374 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x114 0x374 0x61C 0x2 0x1
	+#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_A_DATA07 0x114 0x374 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_NAND_DATA07__MEDIAMIX_ISP_SHUTTER_OPEN_1 0x114 0x374 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13 0x114 0x374 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_DATA07__CORESIGHT_TRACE11 0x114 0x374 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_DATA07__SIM_M_HADDR09 0x114 0x374 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_DQS__RAWNAND_DQS 0x118 0x378 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x118 0x378 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_NAND_DQS__AUDIOMIX_SAI3_MCLK 0x118 0x378 0x4E0 0x2 0x0
	+#define MX8MP_IOMUXC_NAND_DQS__MEDIAMIX_ISP_SHUTTER_OPEN_0 0x118 0x378 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_NAND_DQS__I2C3_SCL 0x118 0x378 0x5B4 0x4 0x1
	+#define MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x118 0x378 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_DQS__CORESIGHT_TRACE12 0x118 0x378 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_DQS__SIM_M_HADDR10 0x118 0x378 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_RE_B__RAWNAND_RE_B 0x11C 0x37C 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_RE_B__FLEXSPI_B_DQS 0x11C 0x37C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x11C 0x37C 0x620 0x2 0x1
	+#define MX8MP_IOMUXC_NAND_RE_B__UART4_DCE_TX 0x11C 0x37C 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_NAND_RE_B__UART4_DTE_RX 0x11C 0x37C 0x600 0x4 0x5
	+#define MX8MP_IOMUXC_NAND_RE_B__GPIO3_IO15 0x11C 0x37C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_RE_B__CORESIGHT_TRACE13 0x11C 0x37C 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_RE_B__SIM_M_HADDR11 0x11C 0x37C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_READY_B__RAWNAND_READY_B 0x120 0x380 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x120 0x380 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_NAND_READY_B__I2C3_SCL 0x120 0x380 0x5B4 0x4 0x2
	+#define MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x120 0x380 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_READY_B__CORESIGHT_TRACE14 0x120 0x380 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_READY_B__SIM_M_HADDR12 0x120 0x380 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_WE_B__RAWNAND_WE_B 0x124 0x384 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x124 0x384 0x604 0x2 0x1
	+#define MX8MP_IOMUXC_NAND_WE_B__I2C3_SDA 0x124 0x384 0x5B8 0x4 0x2
	+#define MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 0x124 0x384 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_WE_B__CORESIGHT_TRACE15 0x124 0x384 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_WE_B__SIM_M_HADDR13 0x124 0x384 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_NAND_WP_B__RAWNAND_WP_B 0x128 0x388 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x128 0x388 0x60C 0x2 0x1
	+#define MX8MP_IOMUXC_NAND_WP_B__I2C4_SCL 0x128 0x388 0x5BC 0x4 0x3
	+#define MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18 0x128 0x388 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_NAND_WP_B__CORESIGHT_EVENTO 0x128 0x388 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_NAND_WP_B__SIM_M_HADDR14 0x128 0x388 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x12C 0x38C 0x508 0x0 0x0
	+#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x12C 0x38C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x12C 0x38C 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x12C 0x38C 0x5CC 0x3 0x1
	+#define MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x12C 0x38C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI5_RX_BCLK 0x130 0x390 0x4F4 0x0 0x0
	+#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01 0x130 0x390 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x130 0x390 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x130 0x390 0x5D0 0x3 0x1
	+#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_CLK 0x130 0x390 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x130 0x390 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x134 0x394 0x4F8 0x0 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 0x134 0x394 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x134 0x394 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x134 0x394 0x5C4 0x3 0x1
	+#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_BIT_STREAM00 0x134 0x394 0x4C0 0x4 0x3
	+#define MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x134 0x394 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x138 0x398 0x4FC 0x0 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 0x138 0x398 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x138 0x398 0x4D8 0x2 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x138 0x398 0x510 0x3 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_BIT_STREAM01 0x138 0x398 0x4C4 0x4 0x3
	+#define MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x138 0x398 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x138 0x398 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x13C 0x39C 0x500 0x0 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 0x13C 0x39C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC 0x13C 0x39C 0x4D8 0x2 0x1
	+#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x13C 0x39C 0x50C 0x3 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_BIT_STREAM02 0x13C 0x39C 0x4C8 0x4 0x3
	+#define MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x13C 0x39C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x13C 0x39C 0x54C 0x6 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x140 0x3A0 0x504 0x0 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 0x140 0x3A0 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC 0x140 0x3A0 0x4D8 0x2 0x2
	+#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x140 0x3A0 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_BIT_STREAM03 0x140 0x3A0 0x4CC 0x4 0x3
	+#define MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x140 0x3A0 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x140 0x3A0 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x144 0x3A4 0x4F0 0x0 0x0
	+#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x144 0x3A4 0x4D4 0x1 0x0
	+#define MX8MP_IOMUXC_SAI5_MCLK__PWM1_OUT 0x144 0x3A4 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x144 0x3A4 0x5C8 0x3 0x1
	+#define MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x144 0x3A4 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x144 0x3A4 0x550 0x6 0x0
	+#define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC 0x148 0x3A8 0x4D0 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x148 0x3A8 0x508 0x1 0x1
	+#define MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x148 0x3A8 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x148 0x3A8 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK 0x14C 0x3AC 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI5_RX_BCLK 0x14C 0x3AC 0x4F4 0x1 0x1
	+#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_CLK 0x14C 0x3AC 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x14C 0x3AC 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x14C 0x3AC 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x150 0x3B0 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x150 0x3B0 0x4F8 0x1 0x1
	+#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 0x150 0x3B0 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_BIT_STREAM00 0x150 0x3B0 0x4C0 0x3 0x4
	+#define MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x150 0x3B0 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x150 0x3B0 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 0x154 0x3B4 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x154 0x3B4 0x4FC 0x1 0x1
	+#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_BIT_STREAM01 0x154 0x3B4 0x4C4 0x3 0x4
	+#define MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x154 0x3B4 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x154 0x3B4 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 0x158 0x3B8 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x158 0x3B8 0x500 0x1 0x1
	+#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_BIT_STREAM02 0x158 0x3B8 0x4C8 0x3 0x4
	+#define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x158 0x3B8 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x158 0x3B8 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 0x15C 0x3BC 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x15C 0x3BC 0x504 0x1 0x1
	+#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_BIT_STREAM03 0x15C 0x3BC 0x4CC 0x3 0x4
	+#define MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x15C 0x3BC 0x57C 0x4 0x1
	+#define MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x15C 0x3BC 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 0x160 0x3C0 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK 0x160 0x3C0 0x524 0x1 0x1
	+#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_RX_BCLK 0x160 0x3C0 0x518 0x2 0x1
	+#define MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x160 0x3C0 0x580 0x4 0x1
	+#define MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06 0x160 0x3C0 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_DATA05 0x164 0x3C4 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_TX_DATA00 0x164 0x3C4 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 0x164 0x3C4 0x51C 0x2 0x1
	+#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_SYNC 0x164 0x3C4 0x4D0 0x3 0x1
	+#define MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x164 0x3C4 0x584 0x4 0x1
	+#define MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 0x164 0x3C4 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI1_RX_DATA06 0x168 0x3C8 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_TX_SYNC 0x168 0x3C8 0x528 0x1 0x1
	+#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_RX_SYNC 0x168 0x3C8 0x520 0x2 0x1
	+#define MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x168 0x3C8 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x168 0x3C8 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_RX_DATA07 0x16C 0x3CC 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI6_MCLK 0x16C 0x3CC 0x514 0x1 0x1
	+#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_SYNC 0x16C 0x3CC 0x4D8 0x2 0x3
	+#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_DATA04 0x16C 0x3CC 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x16C 0x3CC 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x16C 0x3CC 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0x170 0x3D0 0x4D8 0x0 0x4
	+#define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI5_TX_SYNC 0x170 0x3D0 0x510 0x1 0x1
	+#define MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x170 0x3D0 0x588 0x4 0x1
	+#define MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10 0x170 0x3D0 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0x174 0x3D4 0x4D4 0x0 0x1
	+#define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI5_TX_BCLK 0x174 0x3D4 0x50C 0x1 0x1
	+#define MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x174 0x3D4 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x174 0x3D4 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0x178 0x3D8 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI5_TX_DATA00 0x178 0x3D8 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x178 0x3D8 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x178 0x3D8 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0x17C 0x3DC 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI5_TX_DATA01 0x17C 0x3DC 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x17C 0x3DC 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x17C 0x3DC 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0x180 0x3E0 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI5_TX_DATA02 0x180 0x3E0 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x180 0x3E0 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x180 0x3E0 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0x184 0x3E4 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI5_TX_DATA03 0x184 0x3E4 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x184 0x3E4 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x184 0x3E4 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0x188 0x3E8 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_RX_BCLK 0x188 0x3E8 0x518 0x1 0x2
	+#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_TX_BCLK 0x188 0x3E8 0x524 0x2 0x2
	+#define MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x188 0x3E8 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x188 0x3E8 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0x18C 0x3EC 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_RX_DATA00 0x18C 0x3EC 0x51C 0x1 0x2
	+#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 0x18C 0x3EC 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x18C 0x3EC 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x18C 0x3EC 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0x190 0x3F0 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_RX_SYNC 0x190 0x3F0 0x520 0x1 0x2
	+#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC 0x190 0x3F0 0x528 0x2 0x2
	+#define MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x190 0x3F0 0x58C 0x4 0x1
	+#define MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x190 0x3F0 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0x194 0x3F4 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK 0x194 0x3F4 0x514 0x1 0x2
	+#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_CLK 0x194 0x3F4 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER 0x194 0x3F4 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x194 0x3F4 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x198 0x3F8 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI5_MCLK 0x198 0x3F8 0x4F0 0x1 0x1
	+#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x198 0x3F8 0x4D4 0x2 0x2
	+#define MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x198 0x3F8 0x578 0x4 0x1
	+#define MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x198 0x3F8 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC 0x19C 0x3FC 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC 0x19C 0x3FC 0x510 0x1 0x2
	+#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_DATA01 0x19C 0x3FC 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x19C 0x3FC 0x4DC 0x3 0x0
	+#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x19C 0x3FC 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DTE_RX 0x19C 0x3FC 0x5E8 0x4 0x2
	+#define MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19C 0x3FC 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_BIT_STREAM02 0x19C 0x3FC 0x4C8 0x6 0x5
	+#define MX8MP_IOMUXC_SAI2_RXFS__SIM_M_HSIZE00 0x19C 0x3FC 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK 0x1A0 0x400 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x1A0 0x400 0x50C 0x1 0x2
	+#define MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x1A0 0x400 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x1A0 0x400 0x5E8 0x4 0x3
	+#define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX 0x1A0 0x400 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1A0 0x400 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_BIT_STREAM01 0x1A0 0x400 0x4C4 0x6 0x5
	+#define MX8MP_IOMUXC_SAI2_RXC__SIM_M_HSIZE01 0x1A0 0x400 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0x1A4 0x404 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x1A4 0x404 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x1A4 0x404 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_TX_DATA01 0x1A4 0x404 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1A4 0x404 0x5E4 0x4 0x2
	+#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x1A4 0x404 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x1A4 0x404 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_BIT_STREAM03 0x1A4 0x404 0x4CC 0x6 0x5
	+#define MX8MP_IOMUXC_SAI2_RXD0__SIM_M_HSIZE02 0x1A4 0x404 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0x1A8 0x408 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 0x1A8 0x408 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT 0x1A8 0x408 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1A8 0x408 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1A8 0x408 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x1A8 0x408 0x5E4 0x4 0x3
	+#define MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x1A8 0x408 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_BIT_STREAM02 0x1A8 0x408 0x4C8 0x6 0x6
	+#define MX8MP_IOMUXC_SAI2_TXFS__SIM_M_HWRITE 0x1A8 0x408 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0x1AC 0x40C 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 0x1AC 0x40C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x1AC 0x40C 0x54C 0x3 0x1
	+#define MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1AC 0x40C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_BIT_STREAM01 0x1AC 0x40C 0x4C4 0x6 0x6
	+#define MX8MP_IOMUXC_SAI2_TXC__SIM_M_HREADYOUT 0x1AC 0x40C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0x1B0 0x410 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 0x1B0 0x410 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1B0 0x410 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x1B0 0x410 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN 0x1B0 0x410 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x1B0 0x410 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE04 0x1B0 0x410 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_SAI2_TXD0__TPSMP_CLK 0x1B0 0x410 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0x1B4 0x414 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK 0x1B4 0x414 0x4F0 0x1 0x2
	+#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN 0x1B4 0x414 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x1B4 0x414 0x550 0x3 0x1
	+#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN 0x1B4 0x414 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x1B4 0x414 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI3_MCLK 0x1B4 0x414 0x4E0 0x6 0x1
	+#define MX8MP_IOMUXC_SAI2_MCLK__TPSMP_HDATA_DIR 0x1B4 0x414 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0x1B8 0x418 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x1B8 0x418 0x4DC 0x1 0x1
	+#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x1B8 0x418 0x508 0x2 0x2
	+#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 0x1B8 0x418 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF_IN 0x1B8 0x418 0x544 0x4 0x2
	+#define MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1B8 0x418 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_BIT_STREAM00 0x1B8 0x418 0x4C0 0x6 0x5
	+#define MX8MP_IOMUXC_SAI3_RXFS__TPSMP_HTRANS00 0x1B8 0x418 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0x1BC 0x41C 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 0x1BC 0x41C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK 0x1BC 0x41C 0x4F4 0x2 0x2
	+#define MX8MP_IOMUXC_SAI3_RXC__GPT1_CLK 0x1BC 0x41C 0x59C 0x3 0x0
	+#define MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x1BC 0x41C 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI3_RXC__UART2_DTE_RTS 0x1BC 0x41C 0x5EC 0x4 0x2
	+#define MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1BC 0x41C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_CLK 0x1BC 0x41C 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_SAI3_RXC__TPSMP_HTRANS01 0x1BC 0x41C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1C0 0x420 0x4E4 0x0 0x1
	+#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03 0x1C0 0x420 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0x1C0 0x420 0x4F8 0x2 0x2
	+#define MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x1C0 0x420 0x5EC 0x4 0x3
	+#define MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS 0x1C0 0x420 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x1C0 0x420 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_BIT_STREAM01 0x1C0 0x420 0x4C4 0x6 0x7
	+#define MX8MP_IOMUXC_SAI3_RXD__TPSMP_HDATA00 0x1C0 0x420 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1C4 0x424 0x4EC 0x0 0x1
	+#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1C4 0x424 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01 0x1C4 0x424 0x4FC 0x2 0x2
	+#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 0x1C4 0x424 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x1C4 0x424 0x5F0 0x4 0x4
	+#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x1C4 0x424 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x1C4 0x424 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_BIT_STREAM03 0x1C4 0x424 0x4CC 0x6 0x6
	+#define MX8MP_IOMUXC_SAI3_TXFS__TPSMP_HDATA01 0x1C4 0x424 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1C8 0x428 0x4E8 0x0 0x1
	+#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 0x1C8 0x428 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02 0x1C8 0x428 0x500 0x2 0x2
	+#define MX8MP_IOMUXC_SAI3_TXC__GPT1_CAPTURE1 0x1C8 0x428 0x594 0x3 0x0
	+#define MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x1C8 0x428 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x1C8 0x428 0x5F0 0x4 0x5
	+#define MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x1C8 0x428 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_BIT_STREAM02 0x1C8 0x428 0x4C8 0x6 0x7
	+#define MX8MP_IOMUXC_SAI3_TXC__TPSMP_HDATA02 0x1C8 0x428 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x1CC 0x42C 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 0x1CC 0x42C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03 0x1CC 0x42C 0x504 0x2 0x2
	+#define MX8MP_IOMUXC_SAI3_TXD__GPT1_CAPTURE2 0x1CC 0x42C 0x598 0x3 0x0
	+#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SPDIF_EXT_CLK 0x1CC 0x42C 0x548 0x4 0x0
	+#define MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x1CC 0x42C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE05 0x1CC 0x42C 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_SAI3_TXD__TPSMP_HDATA03 0x1CC 0x42C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x1D0 0x430 0x4E0 0x0 0x2
	+#define MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x1D0 0x430 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK 0x1D0 0x430 0x4F0 0x2 0x3
	+#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF_OUT 0x1D0 0x430 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1D0 0x430 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF_IN 0x1D0 0x430 0x544 0x6 0x3
	+#define MX8MP_IOMUXC_SAI3_MCLK__TPSMP_HDATA04 0x1D0 0x430 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF_OUT 0x1D4 0x434 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x1D4 0x434 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x1D4 0x434 0x5C4 0x2 0x2
	+#define MX8MP_IOMUXC_SPDIF_TX__GPT1_COMPARE1 0x1D4 0x434 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x1D4 0x434 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x1D4 0x434 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF_IN 0x1D8 0x438 0x544 0x0 0x4
	+#define MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x1D8 0x438 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x1D8 0x438 0x5C8 0x2 0x2
	+#define MX8MP_IOMUXC_SPDIF_RX__GPT1_COMPARE2 0x1D8 0x438 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x1D8 0x438 0x54C 0x4 0x2
	+#define MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1D8 0x438 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPT1_COMPARE3 0x1DC 0x43C 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x1DC 0x43C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF_EXT_CLK 0x1DC 0x43C 0x548 0x0 0x1
	+#define MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x1DC 0x43C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1E0 0x440 0x558 0x0 0x0
	+#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x1E0 0x440 0x5F8 0x1 0x4
	+#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DTE_TX 0x1E0 0x440 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL 0x1E0 0x440 0x5A4 0x2 0x1
	+#define MX8MP_IOMUXC_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC 0x1E0 0x440 0x538 0x3 0x1
	+#define MX8MP_IOMUXC_ECSPI1_SCLK__GPIO5_IO06 0x1E0 0x440 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ECSPI1_SCLK__TPSMP_HDATA08 0x1E0 0x440 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1E4 0x444 0x560 0x0 0x0
	+#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x1E4 0x444 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DTE_RX 0x1E4 0x444 0x5F8 0x1 0x5
	+#define MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA 0x1E4 0x444 0x5A8 0x2 0x1
	+#define MX8MP_IOMUXC_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK 0x1E4 0x444 0x530 0x3 0x1
	+#define MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x1E4 0x444 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ECSPI1_MOSI__TPSMP_HDATA09 0x1E4 0x444 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1E8 0x448 0x55C 0x0 0x0
	+#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x1E8 0x448 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DTE_RTS 0x1E8 0x448 0x5F4 0x1 0x2
	+#define MX8MP_IOMUXC_ECSPI1_MISO__I2C2_SCL 0x1E8 0x448 0x5AC 0x2 0x1
	+#define MX8MP_IOMUXC_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00 0x1E8 0x448 0x534 0x3 0x1
	+#define MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x1E8 0x448 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ECSPI1_MISO__TPSMP_HDATA10 0x1E8 0x448 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x1EC 0x44C 0x564 0x0 0x0
	+#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x1EC 0x44C 0x5F4 0x1 0x3
	+#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DTE_CTS 0x1EC 0x44C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_ECSPI1_SS0__I2C2_SDA 0x1EC 0x44C 0x5B0 0x2 0x1
	+#define MX8MP_IOMUXC_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC 0x1EC 0x44C 0x540 0x3 0x1
	+#define MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1EC 0x44C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ECSPI1_SS0__TPSMP_HDATA11 0x1EC 0x44C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1F0 0x450 0x568 0x0 0x1
	+#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1F0 0x450 0x600 0x1 0x6
	+#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DTE_TX 0x1F0 0x450 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_ECSPI2_SCLK__I2C3_SCL 0x1F0 0x450 0x5B4 0x2 0x3
	+#define MX8MP_IOMUXC_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK 0x1F0 0x450 0x53C 0x3 0x1
	+#define MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1F0 0x450 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ECSPI2_SCLK__TPSMP_HDATA12 0x1F0 0x450 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1F4 0x454 0x570 0x0 0x1
	+#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1F4 0x454 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DTE_RX 0x1F4 0x454 0x600 0x1 0x7
	+#define MX8MP_IOMUXC_ECSPI2_MOSI__I2C3_SDA 0x1F4 0x454 0x5B8 0x2 0x3
	+#define MX8MP_IOMUXC_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00 0x1F4 0x454 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1F4 0x454 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ECSPI2_MOSI__TPSMP_HDATA13 0x1F4 0x454 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1F8 0x458 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ECSPI2_MISO__TPSMP_HDATA14 0x1F8 0x458 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1F8 0x458 0x56C 0x0 0x1
	+#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1F8 0x458 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DTE_RTS 0x1F8 0x458 0x5FC 0x1 0x2
	+#define MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x1F8 0x458 0x5BC 0x2 0x4
	+#define MX8MP_IOMUXC_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK 0x1F8 0x458 0x52C 0x3 0x1
	+#define MX8MP_IOMUXC_ECSPI2_MISO__CCMSRCGPCMIX_CLKO1 0x1F8 0x458 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x1FC 0x45C 0x574 0x0 0x1
	+#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1FC 0x45C 0x5FC 0x1 0x3
	+#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DTE_CTS 0x1FC 0x45C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x1FC 0x45C 0x5C0 0x2 0x4
	+#define MX8MP_IOMUXC_ECSPI2_SS0__CCMSRCGPCMIX_CLKO2 0x1FC 0x45C 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1FC 0x45C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_ECSPI2_SS0__TPSMP_HDATA15 0x1FC 0x45C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x200 0x460 0x5A4 0x0 0x2
	+#define MX8MP_IOMUXC_I2C1_SCL__ENET_QOS_MDC 0x200 0x460 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x200 0x460 0x558 0x3 0x1
	+#define MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x200 0x460 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_I2C1_SCL__TPSMP_HDATA16 0x200 0x460 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x204 0x464 0x5A8 0x0 0x2
	+#define MX8MP_IOMUXC_I2C1_SDA__ENET_QOS_MDIO 0x204 0x464 0x590 0x1 0x2
	+#define MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x204 0x464 0x560 0x3 0x1
	+#define MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x204 0x464 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_I2C1_SDA__TPSMP_HDATA17 0x204 0x464 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x208 0x468 0x5AC 0x0 0x2
	+#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_IN 0x208 0x468 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_I2C2_SCL__USDHC3_CD_B 0x208 0x468 0x608 0x2 0x3
	+#define MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x208 0x468 0x55C 0x3 0x1
	+#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN 0x208 0x468 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x208 0x468 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_I2C2_SCL__TPSMP_HDATA18 0x208 0x468 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x20C 0x46C 0x5B0 0x0 0x2
	+#define MX8MP_IOMUXC_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT 0x20C 0x46C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_I2C2_SDA__USDHC3_WP 0x20C 0x46C 0x634 0x2 0x3
	+#define MX8MP_IOMUXC_I2C2_SDA__ECSPI1_SS0 0x20C 0x46C 0x564 0x3 0x1
	+#define MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x20C 0x46C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_I2C2_SDA__TPSMP_HDATA19 0x20C 0x46C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x210 0x470 0x5B4 0x0 0x4
	+#define MX8MP_IOMUXC_I2C3_SCL__PWM4_OUT 0x210 0x470 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x210 0x470 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_I2C3_SCL__ECSPI2_SCLK 0x210 0x470 0x568 0x3 0x2
	+#define MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x210 0x470 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_I2C3_SCL__TPSMP_HDATA20 0x210 0x470 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x214 0x474 0x5B8 0x0 0x4
	+#define MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x214 0x474 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x214 0x474 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_I2C3_SDA__ECSPI2_MOSI 0x214 0x474 0x570 0x3 0x2
	+#define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x214 0x474 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_I2C3_SDA__TPSMP_HDATA21 0x214 0x474 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x218 0x478 0x5BC 0x0 0x5
	+#define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT 0x218 0x478 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_I2C4_SCL__HSIOMIX_PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x2 0x0
	+#define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO 0x218 0x478 0x56C 0x3 0x2
	+#define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x218 0x478 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_I2C4_SCL__TPSMP_HDATA22 0x218 0x478 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x21C 0x47C 0x5C0 0x0 0x5
	+#define MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x21C 0x47C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_I2C4_SDA__ECSPI2_SS0 0x21C 0x47C 0x574 0x3 0x2
	+#define MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x21C 0x47C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_I2C4_SDA__TPSMP_HDATA23 0x21C 0x47C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x220 0x480 0x5E8 0x0 0x4
	+#define MX8MP_IOMUXC_UART1_RXD__UART1_DTE_TX 0x220 0x480 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x220 0x480 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x220 0x480 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_UART1_RXD__TPSMP_HDATA24 0x220 0x480 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x224 0x484 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_UART1_TXD__UART1_DTE_RX 0x224 0x484 0x5E8 0x0 0x5
	+#define MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x224 0x484 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x224 0x484 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_UART1_TXD__TPSMP_HDATA25 0x224 0x484 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x228 0x488 0x5F0 0x0 0x6
	+#define MX8MP_IOMUXC_UART2_RXD__UART2_DTE_TX 0x228 0x488 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x228 0x488 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_UART2_RXD__GPT1_COMPARE3 0x228 0x488 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x228 0x488 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_UART2_RXD__TPSMP_HDATA26 0x228 0x488 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x22C 0x48C 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_UART2_TXD__UART2_DTE_RX 0x22C 0x48C 0x5F0 0x0 0x7
	+#define MX8MP_IOMUXC_UART2_TXD__ECSPI3_SS0 0x22C 0x48C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_UART2_TXD__GPT1_COMPARE2 0x22C 0x48C 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x22C 0x48C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_UART2_TXD__TPSMP_HDATA27 0x22C 0x48C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x230 0x490 0x5F8 0x0 0x6
	+#define MX8MP_IOMUXC_UART3_RXD__UART3_DTE_TX 0x230 0x490 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x230 0x490 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x230 0x490 0x5E4 0x1 0x4
	+#define MX8MP_IOMUXC_UART3_RXD__USDHC3_RESET_B 0x230 0x490 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_UART3_RXD__GPT1_CAPTURE2 0x230 0x490 0x598 0x3 0x1
	+#define MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x230 0x490 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x230 0x490 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_UART3_RXD__TPSMP_HDATA28 0x230 0x490 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x234 0x494 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_UART3_TXD__UART3_DTE_RX 0x234 0x494 0x5F8 0x0 0x7
	+#define MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x234 0x494 0x5E4 0x1 0x5
	+#define MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 0x234 0x494 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_UART3_TXD__USDHC3_VSELECT 0x234 0x494 0x000 0x2 0x0
	+#define MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x234 0x494 0x59C 0x3 0x1
	+#define MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x234 0x494 0x550 0x4 0x2
	+#define MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x234 0x494 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_UART3_TXD__TPSMP_HDATA29 0x234 0x494 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x238 0x498 0x600 0x0 0x8
	+#define MX8MP_IOMUXC_UART4_RXD__UART4_DTE_TX 0x238 0x498 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x238 0x498 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_UART4_RXD__UART2_DTE_RTS 0x238 0x498 0x5EC 0x1 0x4
	+#define MX8MP_IOMUXC_UART4_RXD__HSIOMIX_PCIE_CLKREQ_B 0x238 0x498 0x5A0 0x2 0x1
	+#define MX8MP_IOMUXC_UART4_RXD__GPT1_COMPARE1 0x238 0x498 0x000 0x3 0x0
	+#define MX8MP_IOMUXC_UART4_RXD__I2C6_SCL 0x238 0x498 0x5CC 0x4 0x2
	+#define MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x238 0x498 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_UART4_RXD__TPSMP_HDATA30 0x238 0x498 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x23C 0x49C 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_UART4_TXD__UART4_DTE_RX 0x23C 0x49C 0x600 0x0 0x9
	+#define MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x23C 0x49C 0x5EC 0x1 0x5
	+#define MX8MP_IOMUXC_UART4_TXD__UART2_DTE_CTS 0x23C 0x49C 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_UART4_TXD__GPT1_CAPTURE1 0x23C 0x49C 0x594 0x3 0x1
	+#define MX8MP_IOMUXC_UART4_TXD__I2C6_SDA 0x23C 0x49C 0x5D0 0x4 0x2
	+#define MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x23C 0x49C 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_UART4_TXD__TPSMP_HDATA31 0x23C 0x49C 0x000 0x7 0x0
	+#define MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_EARC_SCL 0x240 0x4A0 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x240 0x4A0 0x5C4 0x3 0x3
	+#define MX8MP_IOMUXC_HDMI_DDC_SCL__CAN1_TX 0x240 0x4A0 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x240 0x4A0 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_HDMI_DDC_SCL__AUDIOMIX_test_out00 0x240 0x4A0 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_EARC_SDA 0x244 0x4A4 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x244 0x4A4 0x5C8 0x3 0x3
	+#define MX8MP_IOMUXC_HDMI_DDC_SDA__CAN1_RX 0x244 0x4A4 0x54C 0x4 0x3
	+#define MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x244 0x4A4 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_HDMI_DDC_SDA__AUDIOMIX_test_out01 0x244 0x4A4 0x000 0x6 0x0
	+#define MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_EARC_CEC 0x248 0x4A8 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x248 0x4A8 0x5CC 0x3 0x3
	+#define MX8MP_IOMUXC_HDMI_CEC__CAN2_TX 0x248 0x4A8 0x000 0x4 0x0
	+#define MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x248 0x4A8 0x000 0x5 0x0
	+#define MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_EARC_DC_HPD 0x24C 0x4AC 0x000 0x0 0x0
	+#define MX8MP_IOMUXC_HDMI_HPD__AUDIOMIX_EARC_HDMI_HPD_O 0x24C 0x4AC 0x000 0x1 0x0
	+#define MX8MP_IOMUXC_HDMI_HPD__I2C6_SDA 0x24C 0x4AC 0x5D0 0x3 0x3
	+#define MX8MP_IOMUXC_HDMI_HPD__CAN2_RX 0x24C 0x4AC 0x550 0x4 0x3
	+#define MX8MP_IOMUXC_HDMI_HPD__GPIO3_IO29 0x24C 0x4AC 0x000 0x5 0x0
	+
	+#endif /* __DTS_IMX8MP_PINFUNC_H */
	diff --git a/sys/gnu/dts/arm64/freescale/imx8mn.dtsi b/sys/gnu/dts/arm64/freescale/imx8mp.dtsi
	similarity index 52%
	copy from sys/gnu/dts/arm64/freescale/imx8mn.dtsi
	copy to sys/gnu/dts/arm64/freescale/imx8mp.dtsi
	index a44b5438e842..9f6ba763238d 100644
	--- a/sys/gnu/dts/arm64/freescale/imx8mn.dtsi
	+++ b/sys/gnu/dts/arm64/freescale/imx8mp.dtsi
	@@ -1,817 +1,654 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright 2019 NXP
	*/

	-#include <dt-bindings/clock/imx8mn-clock.h>
	+#include <dt-bindings/clock/imx8mp-clock.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>

	-#include "imx8mn-pinfunc.h"
	+#include "imx8mp-pinfunc.h"

	/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	- ethernet0 = &fec1;
	+ ethernet0 = &fec;
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	gpio3 = &gpio4;
	gpio4 = &gpio5;
	- i2c0 = &i2c1;
	- i2c1 = &i2c2;
	- i2c2 = &i2c3;
	- i2c3 = &i2c4;
	mmc0 = &usdhc1;
	mmc1 = &usdhc2;
	mmc2 = &usdhc3;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	- spi0 = &ecspi1;
	- spi1 = &ecspi2;
	- spi2 = &ecspi3;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	- idle-states {
	- entry-method = "psci";
	-
	- cpu_pd_wait: cpu-pd-wait {
	- compatible = "arm,idle-state";
	- arm,psci-suspend-param = <0x0010033>;
	- local-timer-stop;
	- entry-latency-us = <1000>;
	- exit-latency-us = <700>;
	- min-residency-us = <2700>;
	- };
	- };
	-
	A53_0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0>;
	clock-latency = <61036>;
	- clocks = <&clk IMX8MN_CLK_ARM>;
	+ clocks = <&clk IMX8MP_CLK_ARM>;
	enable-method = "psci";
	next-level-cache = <&A53_L2>;
	- operating-points-v2 = <&a53_opp_table>;
	- nvmem-cells = <&cpu_speed_grade>;
	- nvmem-cell-names = "speed_grade";
	- cpu-idle-states = <&cpu_pd_wait>;
	};

	A53_1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x1>;
	clock-latency = <61036>;
	- clocks = <&clk IMX8MN_CLK_ARM>;
	+ clocks = <&clk IMX8MP_CLK_ARM>;
	enable-method = "psci";
	next-level-cache = <&A53_L2>;
	- operating-points-v2 = <&a53_opp_table>;
	- cpu-idle-states = <&cpu_pd_wait>;
	};

	A53_2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x2>;
	clock-latency = <61036>;
	- clocks = <&clk IMX8MN_CLK_ARM>;
	+ clocks = <&clk IMX8MP_CLK_ARM>;
	enable-method = "psci";
	next-level-cache = <&A53_L2>;
	- operating-points-v2 = <&a53_opp_table>;
	- cpu-idle-states = <&cpu_pd_wait>;
	};

	A53_3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x3>;
	clock-latency = <61036>;
	- clocks = <&clk IMX8MN_CLK_ARM>;
	+ clocks = <&clk IMX8MP_CLK_ARM>;
	enable-method = "psci";
	next-level-cache = <&A53_L2>;
	- operating-points-v2 = <&a53_opp_table>;
	- cpu-idle-states = <&cpu_pd_wait>;
	};

	A53_L2: l2-cache0 {
	compatible = "cache";
	};
	};

	- a53_opp_table: opp-table {
	- compatible = "operating-points-v2";
	- opp-shared;
	-
	- opp-1200000000 {
	- opp-hz = /bits/ 64 <1200000000>;
	- opp-microvolt = <850000>;
	- opp-supported-hw = <0xb00>, <0x7>;
	- clock-latency-ns = <150000>;
	- opp-suspend;
	- };
	-
	- opp-1400000000 {
	- opp-hz = /bits/ 64 <1400000000>;
	- opp-microvolt = <950000>;
	- opp-supported-hw = <0x300>, <0x7>;
	- clock-latency-ns = <150000>;
	- opp-suspend;
	- };
	-
	- opp-1500000000 {
	- opp-hz = /bits/ 64 <1500000000>;
	- opp-microvolt = <1000000>;
	- opp-supported-hw = <0x100>, <0x3>;
	- clock-latency-ns = <150000>;
	- opp-suspend;
	- };
	- };
	-
	osc_32k: clock-osc-32k {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "osc_32k";
	};

	osc_24m: clock-osc-24m {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "osc_24m";
	};

	clk_ext1: clock-ext1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <133000000>;
	clock-output-names = "clk_ext1";
	};

	clk_ext2: clock-ext2 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <133000000>;
	clock-output-names = "clk_ext2";
	};

	clk_ext3: clock-ext3 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <133000000>;
	clock-output-names = "clk_ext3";
	};

	clk_ext4: clock-ext4 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency= <133000000>;
	clock-output-names = "clk_ext4";
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>;
	clock-frequency = <8000000>;
	arm,no-tick-in-suspend;
	};

	soc@0 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x0 0x3e000000>;

	aips1: bus@30000000 {
	- compatible = "simple-bus";
	+ compatible = "fsl,aips-bus", "simple-bus";
	reg = <0x30000000 0x400000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	gpio1: gpio@30200000 {
	- compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
	+ compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
	reg = <0x30200000 0x10000>;
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	- gpio-ranges = <&iomuxc 0 10 30>;
	+ gpio-ranges = <&iomuxc 0 5 30>;
	};

	gpio2: gpio@30210000 {
	- compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
	+ compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
	reg = <0x30210000 0x10000>;
	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	- gpio-ranges = <&iomuxc 0 40 21>;
	+ gpio-ranges = <&iomuxc 0 35 21>;
	};

	gpio3: gpio@30220000 {
	- compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
	+ compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
	reg = <0x30220000 0x10000>;
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	- gpio-ranges = <&iomuxc 0 61 26>;
	+ gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>;
	};

	gpio4: gpio@30230000 {
	- compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
	+ compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
	reg = <0x30230000 0x10000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	- gpio-ranges = <&iomuxc 21 108 11>;
	+ gpio-ranges = <&iomuxc 0 82 32>;
	};

	gpio5: gpio@30240000 {
	- compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
	+ compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
	reg = <0x30240000 0x10000>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	- gpio-ranges = <&iomuxc 0 119 30>;
	+ gpio-ranges = <&iomuxc 0 114 30>;
	};

	wdog1: watchdog@30280000 {
	- compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
	+ compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
	reg = <0x30280000 0x10000>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
	- status = "disabled";
	- };
	-
	- wdog2: watchdog@30290000 {
	- compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
	- reg = <0x30290000 0x10000>;
	- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
	- status = "disabled";
	- };
	-
	- wdog3: watchdog@302a0000 {
	- compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
	- reg = <0x302a0000 0x10000>;
	- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
	status = "disabled";
	};

	- sdma3: dma-controller@302b0000 {
	- compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
	- reg = <0x302b0000 0x10000>;
	- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
	- <&clk IMX8MN_CLK_SDMA3_ROOT>;
	- clock-names = "ipg", "ahb";
	- #dma-cells = <3>;
	- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
	- };
	-
	- sdma2: dma-controller@302c0000 {
	- compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
	- reg = <0x302c0000 0x10000>;
	- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
	- <&clk IMX8MN_CLK_SDMA2_ROOT>;
	- clock-names = "ipg", "ahb";
	- #dma-cells = <3>;
	- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
	- };
	-
	iomuxc: pinctrl@30330000 {
	- compatible = "fsl,imx8mn-iomuxc";
	+ compatible = "fsl,imx8mp-iomuxc";
	reg = <0x30330000 0x10000>;
	};

	gpr: iomuxc-gpr@30340000 {
	- compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
	+ compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
	reg = <0x30340000 0x10000>;
	};

	ocotp: ocotp-ctrl@30350000 {
	- compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
	+ compatible = "fsl,imx8mp-ocotp", "syscon";
	reg = <0x30350000 0x10000>;
	- clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
	+ /* For nvmem subnodes */
	#address-cells = <1>;
	#size-cells = <1>;

	cpu_speed_grade: speed-grade@10 {
	reg = <0x10 4>;
	};
	};

	anatop: anatop@30360000 {
	- compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
	+ compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
	"syscon";
	reg = <0x30360000 0x10000>;
	};

	snvs: snvs@30370000 {
	compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
	reg = <0x30370000 0x10000>;

	snvs_rtc: snvs-rtc-lp {
	compatible = "fsl,sec-v4.0-mon-rtc-lp";
	- regmap = <&snvs>;
	+ regmap =<&snvs>;
	offset = <0x34>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
	clock-names = "snvs-rtc";
	};

	snvs_pwrkey: snvs-powerkey {
	compatible = "fsl,sec-v4.0-pwrkey";
	regmap = <&snvs>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
	+ clock-names = "snvs-pwrkey";
	linux,keycode = <KEY_POWER>;
	wakeup-source;
	status = "disabled";
	};
	};

	clk: clock-controller@30380000 {
	- compatible = "fsl,imx8mn-ccm";
	+ compatible = "fsl,imx8mp-ccm";
	reg = <0x30380000 0x10000>;
	#clock-cells = <1>;
	clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
	<&clk_ext3>, <&clk_ext4>;
	clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
	"clk_ext3", "clk_ext4";
	+ assigned-clocks = <&clk IMX8MP_CLK_NOC>,
	+ <&clk IMX8MP_CLK_NOC_IO>,
	+ <&clk IMX8MP_CLK_GIC>,
	+ <&clk IMX8MP_CLK_AUDIO_AHB>,
	+ <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
	+ <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
	+ <&clk IMX8MP_AUDIO_PLL1>,
	+ <&clk IMX8MP_AUDIO_PLL2>;
	+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
	+ <&clk IMX8MP_SYS_PLL1_800M>,
	+ <&clk IMX8MP_SYS_PLL2_500M>,
	+ <&clk IMX8MP_SYS_PLL1_800M>,
	+ <&clk IMX8MP_SYS_PLL1_800M>;
	+ assigned-clock-rates = <1000000000>,
	+ <800000000>,
	+ <500000000>,
	+ <400000000>,
	+ <800000000>,
	+ <400000000>,
	+ <393216000>,
	+ <361267200>;
	};

	src: reset-controller@30390000 {
	- compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
	+ compatible = "fsl,imx8mp-src", "syscon";
	reg = <0x30390000 0x10000>;
	- interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	#reset-cells = <1>;
	};
	};

	aips2: bus@30400000 {
	- compatible = "simple-bus";
	+ compatible = "fsl,aips-bus", "simple-bus";
	reg = <0x30400000 0x400000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	pwm1: pwm@30660000 {
	- compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
	+ compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
	reg = <0x30660000 0x10000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
	- <&clk IMX8MN_CLK_PWM1_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
	+ <&clk IMX8MP_CLK_PWM1_ROOT>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm2: pwm@30670000 {
	- compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
	+ compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
	reg = <0x30670000 0x10000>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
	- <&clk IMX8MN_CLK_PWM2_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
	+ <&clk IMX8MP_CLK_PWM2_ROOT>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm3: pwm@30680000 {
	- compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
	+ compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
	reg = <0x30680000 0x10000>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
	- <&clk IMX8MN_CLK_PWM3_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
	+ <&clk IMX8MP_CLK_PWM3_ROOT>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm4: pwm@30690000 {
	- compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
	+ compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
	reg = <0x30690000 0x10000>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
	- <&clk IMX8MN_CLK_PWM4_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
	+ <&clk IMX8MP_CLK_PWM4_ROOT>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	system_counter: timer@306a0000 {
	compatible = "nxp,sysctr-timer";
	reg = <0x306a0000 0x20000>;
	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc_24m>;
	clock-names = "per";
	};
	};

	aips3: bus@30800000 {
	- compatible = "simple-bus";
	+ compatible = "fsl,aips-bus", "simple-bus";
	reg = <0x30800000 0x400000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	ecspi1: spi@30820000 {
	- compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
	#address-cells = <1>;
	#size-cells = <0>;
	+ compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
	reg = <0x30820000 0x10000>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
	- <&clk IMX8MN_CLK_ECSPI1_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
	+ <&clk IMX8MP_CLK_ECSPI1_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	ecspi2: spi@30830000 {
	- compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
	#address-cells = <1>;
	#size-cells = <0>;
	+ compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
	reg = <0x30830000 0x10000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
	- <&clk IMX8MN_CLK_ECSPI2_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
	+ <&clk IMX8MP_CLK_ECSPI2_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	ecspi3: spi@30840000 {
	- compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
	#address-cells = <1>;
	#size-cells = <0>;
	+ compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
	reg = <0x30840000 0x10000>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
	- <&clk IMX8MN_CLK_ECSPI3_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
	+ <&clk IMX8MP_CLK_ECSPI3_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart1: serial@30860000 {
	- compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
	+ compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
	reg = <0x30860000 0x10000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
	- <&clk IMX8MN_CLK_UART1_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
	+ <&clk IMX8MP_CLK_UART1_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart3: serial@30880000 {
	- compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
	+ compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
	reg = <0x30880000 0x10000>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
	- <&clk IMX8MN_CLK_UART3_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
	+ <&clk IMX8MP_CLK_UART3_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uart2: serial@30890000 {
	- compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
	+ compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
	reg = <0x30890000 0x10000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
	- <&clk IMX8MN_CLK_UART2_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
	+ <&clk IMX8MP_CLK_UART2_ROOT>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	crypto: crypto@30900000 {
	compatible = "fsl,sec-v4.0";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x30900000 0x40000>;
	ranges = <0 0x30900000 0x40000>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_AHB>,
	- <&clk IMX8MN_CLK_IPG_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_AHB>,
	+ <&clk IMX8MP_CLK_IPG_ROOT>;
	clock-names = "aclk", "ipg";

	- sec_jr0: jr0@1000 {
	- compatible = "fsl,sec-v4.0-job-ring";
	- reg = <0x1000 0x1000>;
	- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	+ sec_jr0: jr@1000 {
	+ compatible = "fsl,sec-v4.0-job-ring";
	+ reg = <0x1000 0x1000>;
	+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	};

	- sec_jr1: jr1@2000 {
	- compatible = "fsl,sec-v4.0-job-ring";
	- reg = <0x2000 0x1000>;
	- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	+ sec_jr1: jr@2000 {
	+ compatible = "fsl,sec-v4.0-job-ring";
	+ reg = <0x2000 0x1000>;
	+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	};

	- sec_jr2: jr2@3000 {
	- compatible = "fsl,sec-v4.0-job-ring";
	- reg = <0x3000 0x1000>;
	- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	+ sec_jr2: jr@3000 {
	+ compatible = "fsl,sec-v4.0-job-ring";
	+ reg = <0x3000 0x1000>;
	+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	i2c1: i2c@30a20000 {
	- compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
	+ compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x30a20000 0x10000>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
	status = "disabled";
	};

	i2c2: i2c@30a30000 {
	- compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
	+ compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x30a30000 0x10000>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
	status = "disabled";
	};

	i2c3: i2c@30a40000 {
	+ compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	- compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
	reg = <0x30a40000 0x10000>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
	status = "disabled";
	};

	i2c4: i2c@30a50000 {
	- compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
	+ compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x30a50000 0x10000>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
	status = "disabled";
	};

	uart4: serial@30a60000 {
	- compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
	+ compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
	reg = <0x30a60000 0x10000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
	- <&clk IMX8MN_CLK_UART4_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
	+ <&clk IMX8MP_CLK_UART4_ROOT>;
	clock-names = "ipg", "per";
	dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	+ i2c5: i2c@30ad0000 {
	+ compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ reg = <0x30ad0000 0x10000>;
	+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
	+ status = "disabled";
	+ };
	+
	+ i2c6: i2c@30ae0000 {
	+ compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ reg = <0x30ae0000 0x10000>;
	+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
	+ status = "disabled";
	+ };
	+
	usdhc1: mmc@30b40000 {
	- compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
	+ compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
	reg = <0x30b40000 0x10000>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
	- <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
	- <&clk IMX8MN_CLK_USDHC1_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_DUMMY>,
	+ <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
	+ <&clk IMX8MP_CLK_USDHC1_ROOT>;
	clock-names = "ipg", "ahb", "per";
	fsl,tuning-start-tap = <20>;
	fsl,tuning-step= <2>;
	bus-width = <4>;
	status = "disabled";
	};

	usdhc2: mmc@30b50000 {
	- compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
	+ compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
	reg = <0x30b50000 0x10000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
	- <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
	- <&clk IMX8MN_CLK_USDHC2_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_DUMMY>,
	+ <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
	+ <&clk IMX8MP_CLK_USDHC2_ROOT>;
	clock-names = "ipg", "ahb", "per";
	fsl,tuning-start-tap = <20>;
	fsl,tuning-step= <2>;
	bus-width = <4>;
	status = "disabled";
	};

	usdhc3: mmc@30b60000 {
	- compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
	+ compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
	reg = <0x30b60000 0x10000>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
	- <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
	- <&clk IMX8MN_CLK_USDHC3_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_DUMMY>,
	+ <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
	+ <&clk IMX8MP_CLK_USDHC3_ROOT>;
	clock-names = "ipg", "ahb", "per";
	fsl,tuning-start-tap = <20>;
	fsl,tuning-step= <2>;
	bus-width = <4>;
	status = "disabled";
	};

	sdma1: dma-controller@30bd0000 {
	- compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
	+ compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
	reg = <0x30bd0000 0x10000>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
	- <&clk IMX8MN_CLK_SDMA1_ROOT>;
	+ clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
	+ <&clk IMX8MP_CLK_SDMA1_ROOT>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
	};

	- fec1: ethernet@30be0000 {
	- compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
	+ fec: ethernet@30be0000 {
	+ compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec";
	reg = <0x30be0000 0x10000>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
	- <&clk IMX8MN_CLK_ENET1_ROOT>,
	- <&clk IMX8MN_CLK_ENET_TIMER>,
	- <&clk IMX8MN_CLK_ENET_REF>,
	- <&clk IMX8MN_CLK_ENET_PHY_REF>;
	+ clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
	+ <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
	+ <&clk IMX8MP_CLK_ENET_TIMER>,
	+ <&clk IMX8MP_CLK_ENET_REF>,
	+ <&clk IMX8MP_CLK_ENET_PHY_REF>;
	clock-names = "ipg", "ahb", "ptp",
	"enet_clk_ref", "enet_out";
	- assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
	- <&clk IMX8MN_CLK_ENET_TIMER>,
	- <&clk IMX8MN_CLK_ENET_REF>,
	- <&clk IMX8MN_CLK_ENET_TIMER>;
	- assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
	- <&clk IMX8MN_SYS_PLL2_100M>,
	- <&clk IMX8MN_SYS_PLL2_125M>;
	+ assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
	+ <&clk IMX8MP_CLK_ENET_TIMER>,
	+ <&clk IMX8MP_CLK_ENET_REF>,
	+ <&clk IMX8MP_CLK_ENET_TIMER>;
	+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
	+ <&clk IMX8MP_SYS_PLL2_100M>,
	+ <&clk IMX8MP_SYS_PLL2_125M>;
	assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
	fsl,num-tx-queues = <3>;
	fsl,num-rx-queues = <3>;
	status = "disabled";
	};
	-
	- };
	-
	- aips4: bus@32c00000 {
	- compatible = "simple-bus";
	- reg = <0x32c00000 0x400000>;
	- #address-cells = <1>;
	- #size-cells = <1>;
	- ranges;
	-
	- usbotg1: usb@32e40000 {
	- compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
	- reg = <0x32e40000 0x200>;
	- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
	- clock-names = "usb1_ctrl_root_clk";
	- assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
	- assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
	- fsl,usbphy = <&usbphynop1>;
	- fsl,usbmisc = <&usbmisc1 0>;
	- status = "disabled";
	- };
	-
	- usbmisc1: usbmisc@32e40200 {
	- compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
	- #index-cells = <1>;
	- reg = <0x32e40200 0x200>;
	- };
	-
	- usbotg2: usb@32e50000 {
	- compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
	- reg = <0x32e50000 0x200>;
	- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
	- clock-names = "usb1_ctrl_root_clk";
	- assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
	- <&clk IMX8MN_CLK_USB_CORE_REF>;
	- assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
	- <&clk IMX8MN_SYS_PLL1_100M>;
	- fsl,usbphy = <&usbphynop2>;
	- fsl,usbmisc = <&usbmisc2 0>;
	- status = "disabled";
	- };
	-
	- usbmisc2: usbmisc@32e50200 {
	- compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
	- #index-cells = <1>;
	- reg = <0x32e50200 0x200>;
	- };
	-
	- };
	-
	- dma_apbh: dma-controller@33000000 {
	- compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
	- reg = <0x33000000 0x2000>;
	- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	- interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
	- #dma-cells = <1>;
	- dma-channels = <4>;
	- clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
	- };
	-
	- gpmi: nand-controller@33002000 {
	- compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
	- #address-cells = <1>;
	- #size-cells = <1>;
	- reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
	- reg-names = "gpmi-nand", "bch";
	- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	- interrupt-names = "bch";
	- clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
	- <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
	- clock-names = "gpmi_io", "gpmi_bch_apb";
	- dmas = <&dma_apbh 0>;
	- dma-names = "rx-tx";
	- status = "disabled";
	};

	gic: interrupt-controller@38800000 {
	compatible = "arm,gic-v3";
	reg = <0x38800000 0x10000>,
	<0x38880000 0xc0000>;
	#interrupt-cells = <3>;
	interrupt-controller;
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	+ interrupt-parent = <&gic>;
	};
	-
	- ddrc: memory-controller@3d400000 {
	- compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
	- reg = <0x3d400000 0x400000>;
	- clock-names = "core", "pll", "alt", "apb";
	- clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
	- <&clk IMX8MN_DRAM_PLL>,
	- <&clk IMX8MN_CLK_DRAM_ALT>,
	- <&clk IMX8MN_CLK_DRAM_APB>;
	- };
	-
	- ddr-pmu@3d800000 {
	- compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
	- reg = <0x3d800000 0x400000>;
	- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	- };
	- };
	-
	- usbphynop1: usbphynop1 {
	- compatible = "usb-nop-xceiv";
	- clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
	- assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
	- assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
	- clock-names = "main_clk";
	- };
	-
	- usbphynop2: usbphynop2 {
	- compatible = "usb-nop-xceiv";
	- clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
	- assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
	- assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
	- clock-names = "main_clk";
	};
	};
	diff --git a/sys/gnu/dts/arm64/freescale/imx8mq-evk.dts b/sys/gnu/dts/arm64/freescale/imx8mq-evk.dts
	index 94066d49d6ed..c9241abf0df3 100644
	--- a/sys/gnu/dts/arm64/freescale/imx8mq-evk.dts
	+++ b/sys/gnu/dts/arm64/freescale/imx8mq-evk.dts
	@@ -1,529 +1,531 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	/*
	* Copyright 2017 NXP
	* Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
	*/

	/dts-v1/;

	#include "imx8mq.dtsi"

	/ {
	model = "NXP i.MX8MQ EVK";
	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";

	chosen {
	stdout-path = &uart1;
	};

	memory@40000000 {
	device_type = "memory";
	reg = <0x00000000 0x40000000 0 0xc0000000>;
	};

	pcie0_refclk: pcie0-refclk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <100000000>;
	};

	reg_usdhc2_vmmc: regulator-vsd-3v3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_reg_usdhc2>;
	compatible = "regulator-fixed";
	regulator-name = "VSD_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	buck2_reg: regulator-buck2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_buck2>;
	compatible = "regulator-gpio";
	regulator-name = "vdd_arm";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1000000>;
	gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
	states = <1000000 0x0
	900000 0x1>;
	regulator-boot-on;
	regulator-always-on;
	};

	ir-receiver {
	compatible = "gpio-ir-receiver";
	gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ir>;
	};

	wm8524: audio-codec {
	#sound-dai-cells = <0>;
	compatible = "wlf,wm8524";
	wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
	};

	sound-wm8524 {
	compatible = "simple-audio-card";
	simple-audio-card,name = "wm8524-audio";
	simple-audio-card,format = "i2s";
	simple-audio-card,frame-master = <&cpudai>;
	simple-audio-card,bitclock-master = <&cpudai>;
	simple-audio-card,widgets =
	"Line", "Left Line Out Jack",
	"Line", "Right Line Out Jack";
	simple-audio-card,routing =
	"Left Line Out Jack", "LINEVOUTL",
	"Right Line Out Jack", "LINEVOUTR";

	cpudai: simple-audio-card,cpu {
	sound-dai = <&sai2>;
	};

	link_codec: simple-audio-card,codec {
	sound-dai = <&wm8524>;
	clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
	};
	};
	};

	&A53_0 {
	cpu-supply = <&buck2_reg>;
	};

	&A53_1 {
	cpu-supply = <&buck2_reg>;
	};

	&A53_2 {
	cpu-supply = <&buck2_reg>;
	};

	&A53_3 {
	cpu-supply = <&buck2_reg>;
	};

	&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
	compatible = "operating-points-v2";

	opp-25M {
	opp-hz = /bits/ 64 <25000000>;
	};

	opp-100M {
	opp-hz = /bits/ 64 <100000000>;
	};

	/*
	* On imx8mq B0 PLL can't be bypassed so low bus is 166M
	*/
	opp-166M {
	opp-hz = /bits/ 64 <166935483>;
	};

	opp-800M {
	opp-hz = /bits/ 64 <800000000>;
	};
	};
	};

	&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	+ phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
	+ phy-reset-duration = <10>;
	fsl,magic-packet;
	status = "okay";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy0: ethernet-phy@0 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <0>;
	};
	};
	};

	&gpio5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wifi_reset>;

	wl-reg-on {
	gpio-hog;
	gpios = <29 GPIO_ACTIVE_HIGH>;
	output-high;
	};
	};

	&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic@8 {
	compatible = "fsl,pfuze100";
	reg = <0x8>;

	regulators {
	sw1a_reg: sw1ab {
	regulator-min-microvolt = <825000>;
	regulator-max-microvolt = <1100000>;
	};

	sw1c_reg: sw1c {
	regulator-min-microvolt = <825000>;
	regulator-max-microvolt = <1100000>;
	};

	sw2_reg: sw2 {
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;
	};

	sw3a_reg: sw3ab {
	regulator-min-microvolt = <825000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;
	};

	sw4_reg: sw4 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	swbst_reg: swbst {
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5150000>;
	};

	snvs_reg: vsnvs {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;
	};

	vref_reg: vrefddr {
	regulator-always-on;
	};

	vgen1_reg: vgen1 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1550000>;
	};

	vgen2_reg: vgen2 {
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <975000>;
	regulator-always-on;
	};

	vgen3_reg: vgen3 {
	regulator-min-microvolt = <1675000>;
	regulator-max-microvolt = <1975000>;
	regulator-always-on;
	};

	vgen4_reg: vgen4 {
	regulator-min-microvolt = <1625000>;
	regulator-max-microvolt = <1875000>;
	regulator-always-on;
	};

	vgen5_reg: vgen5 {
	regulator-min-microvolt = <3075000>;
	regulator-max-microvolt = <3625000>;
	regulator-always-on;
	};

	vgen6_reg: vgen6 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	};
	};
	};
	};

	&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
	<&clk IMX8MQ_CLK_PCIE1_AUX>,
	<&clk IMX8MQ_CLK_PCIE1_PHY>,
	<&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	status = "okay";
	};

	&pgc_gpu {
	power-supply = <&sw1a_reg>;
	};

	&qspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi>;
	status = "okay";

	n25q256a: flash@0 {
	reg = <0>;
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "micron,n25q256a", "jedec,spi-nor";
	spi-max-frequency = <29000000>;
	};
	};

	&sai2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <0>, <24576000>;
	status = "okay";
	};

	&snvs_pwrkey {
	status = "okay";
	};

	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
	};

	&usb3_phy1 {
	status = "okay";
	};

	&usb_dwc3_1 {
	dr_mode = "host";
	status = "okay";
	};

	&usdhc1 {
	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	vqmmc-supply = <&sw4_reg>;
	bus-width = <8>;
	non-removable;
	no-sd;
	no-sdio;
	status = "okay";
	};

	&usdhc2 {
	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
	};

	&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
	};

	&iomuxc {
	pinctrl_buck2: vddarmgrp {
	fsl,pins = <
	MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
	>;

	};

	pinctrl_fec1: fec1grp {
	fsl,pins = <
	MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
	MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
	MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
	MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
	MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
	MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
	MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
	MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
	MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
	MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
	MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
	MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
	MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
	MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
	MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
	MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
	>;
	};

	pinctrl_ir: irgrp {
	fsl,pins = <
	MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f
	>;
	};

	pinctrl_pcie0: pcie0grp {
	fsl,pins = <
	MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
	MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
	>;
	};

	pinctrl_qspi: qspigrp {
	fsl,pins = <
	MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
	MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
	MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
	MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
	MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
	MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82

	>;
	};

	pinctrl_reg_usdhc2: regusdhc2grpgpio {
	fsl,pins = <
	MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
	>;
	};

	pinctrl_sai2: sai2grp {
	fsl,pins = <
	MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
	MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
	MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
	MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
	MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
	MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
	>;
	};

	pinctrl_usdhc1: usdhc1grp {
	fsl,pins = <
	MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
	MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
	MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
	MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
	MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
	MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
	MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
	MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
	MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
	MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
	MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
	MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
	>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100grp {
	fsl,pins = <
	MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
	MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
	MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
	MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
	MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
	MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
	MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
	MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
	MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
	MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
	MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
	MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
	>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200grp {
	fsl,pins = <
	MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
	MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
	MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
	MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
	MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
	MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
	MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
	MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
	MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
	MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
	MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
	MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
	>;
	};

	pinctrl_usdhc2: usdhc2grp {
	fsl,pins = <
	MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
	MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
	MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
	MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
	MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
	MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
	MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
	>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100grp {
	fsl,pins = <
	MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
	MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
	MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
	MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
	MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
	MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
	MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
	>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200grp {
	fsl,pins = <
	MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
	MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
	MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
	MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
	MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
	MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
	MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
	>;
	};

	pinctrl_wdog: wdog1grp {
	fsl,pins = <
	MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
	>;
	};

	pinctrl_wifi_reset: wifiresetgrp {
	fsl,pins = <
	MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/freescale/imx8mq-librem5-devkit.dts b/sys/gnu/dts/arm64/freescale/imx8mq-librem5-devkit.dts
	index 764a4cb4e125..10eca94194be 100644
	--- a/sys/gnu/dts/arm64/freescale/imx8mq-librem5-devkit.dts
	+++ b/sys/gnu/dts/arm64/freescale/imx8mq-librem5-devkit.dts
	@@ -1,824 +1,966 @@
	// SPDX-License-Identifier: GPL-2.0+
	/*
	* Copyright 2018-2019 Purism SPC
	*/

	/dts-v1/;

	#include "dt-bindings/input/input.h"
	#include "dt-bindings/pwm/pwm.h"
	#include "dt-bindings/usb/pd.h"
	#include "imx8mq.dtsi"

	/ {
	model = "Purism Librem 5 devkit";
	compatible = "purism,librem5-devkit", "fsl,imx8mq";

	backlight_dsi: backlight-dsi {
	compatible = "pwm-backlight";
	/* 200 Hz for the PAM2841 */
	pwms = <&pwm1 0 5000000>;
	brightness-levels = <0 100>;
	num-interpolated-steps = <100>;
	/* Default brightness level (index into the array defined by */
	/* the "brightness-levels" property) */
	default-brightness-level = <0>;
	power-supply = <&reg_22v4_p>;
	};

	chosen {
	stdout-path = &uart1;
	};

	gpio-keys {
	compatible = "gpio-keys";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_keys>;

	btn1 {
	label = "VOL_UP";
	gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
	wakeup-source;
	linux,code = <KEY_VOLUMEUP>;
	};

	btn2 {
	label = "VOL_DOWN";
	gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
	wakeup-source;
	linux,code = <KEY_VOLUMEDOWN>;
	};

	hp-det {
	label = "HP_DET";
	gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
	wakeup-source;
	linux,code = <KEY_HP>;
	};
	+
	+ wwan-wake {
	+ label = "WWAN_WAKE";
	+ gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
	+ interrupt-parent = <&gpio3>;
	+ interrupts = <8 GPIO_ACTIVE_LOW>;
	+ wakeup-source;
	+ linux,code = <KEY_PHONE>;
	+ };
	};

	leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_leds>;

	led1 {
	label = "LED 1";
	gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
	default-state = "off";
	};
	};

	pmic_osc: clock-pmic {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "pmic_osc";
	};

	reg_1v8_p: regulator-1v8-p {
	compatible = "regulator-fixed";
	regulator-name = "1v8_p";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&reg_pwr_en>;
	};

	reg_2v8_p: regulator-2v8-p {
	compatible = "regulator-fixed";
	regulator-name = "2v8_p";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	vin-supply = <&reg_pwr_en>;
	};

	reg_3v3_p: regulator-3v3-p {
	compatible = "regulator-fixed";
	regulator-name = "3v3_p";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&reg_pwr_en>;

	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	reg_5v_p: regulator-5v-p {
	compatible = "regulator-fixed";
	regulator-name = "5v_p";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&reg_pwr_en>;

	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	reg_22v4_p: regulator-22v4-p {
	compatible = "regulator-fixed";
	regulator-name = "22v4_P";
	regulator-min-microvolt = <22400000>;
	regulator-max-microvolt = <22400000>;
	vin-supply = <&reg_pwr_en>;
	};

	reg_pwr_en: regulator-pwr-en {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwr_en>;
	regulator-name = "PWR_EN";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	regulator-always-on;
	};

	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2_pwr>;
	regulator-name = "VSD_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	regulator-always-on;
	};

	+ wwan_codec: sound-wwan-codec {
	+ compatible = "option,gtm601";
	+ #sound-dai-cells = <0>;
	+ };
	+
	+ sound {
	+ compatible = "simple-audio-card";
	+ simple-audio-card,name = "sgtl5000";
	+ simple-audio-card,format = "i2s";
	+ simple-audio-card,widgets =
	+ "Microphone", "Microphone Jack",
	+ "Headphone", "Headphone Jack",
	+ "Speaker", "Speaker Ext",
	+ "Line", "Line In Jack";
	+ simple-audio-card,routing =
	+ "MIC_IN", "Microphone Jack",
	+ "Microphone Jack", "Mic Bias",
	+ "LINE_IN", "Line In Jack",
	+ "Headphone Jack", "HP_OUT",
	+ "Speaker Ext", "LINE_OUT";
	+
	+ simple-audio-card,cpu {
	+ sound-dai = <&sai2>;
	+ };
	+
	+ simple-audio-card,codec {
	+ sound-dai = <&sgtl5000>;
	+ clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
	+ frame-master;
	+ bitclock-master;
	+ };
	+ };
	+
	+ sound-wwan {
	+ compatible = "simple-audio-card";
	+ simple-audio-card,name = "SIMCom SIM7100";
	+ simple-audio-card,format = "dsp_a";
	+
	+ simple-audio-card,cpu {
	+ sound-dai = <&sai6>;
	+ };
	+
	+ telephony_link_master: simple-audio-card,codec {
	+ sound-dai = <&wwan_codec>;
	+ frame-master;
	+ bitclock-master;
	+ };
	+ };
	+
	vibrator {
	compatible = "gpio-vibrator";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_haptic>;
	enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
	vcc-supply = <&reg_3v3_p>;
	};

	wifi_pwr_en: regulator-wifi-en {
	compatible = "regulator-fixed";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wifi_pwr_en>;
	regulator-name = "WIFI_EN";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	regulator-always-on;
	};
	};

	+&A53_0 {
	+ cpu-supply = <&buck2_reg>;
	+};
	+
	+&A53_1 {
	+ cpu-supply = <&buck2_reg>;
	+};
	+
	+&A53_2 {
	+ cpu-supply = <&buck2_reg>;
	+};
	+
	+&A53_3 {
	+ cpu-supply = <&buck2_reg>;
	+};
	+
	&clk {
	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
	assigned-clock-rates = <786432000>, <722534400>;
	};

	&dphy {
	status = "okay";
	};

	&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	phy-supply = <&reg_3v3_p>;
	status = "okay";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy0: ethernet-phy@1 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <1>;
	};
	};
	};

	&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic: pmic@4b {
	compatible = "rohm,bd71837";
	reg = <0x4b>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pmic>;
	clocks = <&pmic_osc>;
	clock-names = "osc";
	clock-output-names = "pmic_clk";
	interrupt-parent = <&gpio1>;
	interrupts = <3 GPIO_ACTIVE_LOW>;
	interrupt-names = "irq";
	rohm,reset-snvs-powered;

	regulators {
	buck1_reg: BUCK1 {
	regulator-name = "buck1";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1300000>;
	regulator-boot-on;
	regulator-ramp-delay = <1250>;
	rohm,dvs-run-voltage = <900000>;
	rohm,dvs-idle-voltage = <850000>;
	rohm,dvs-suspend-voltage = <800000>;
	};

	buck2_reg: BUCK2 {
	regulator-name = "buck2";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1300000>;
	regulator-boot-on;
	regulator-ramp-delay = <1250>;
	rohm,dvs-run-voltage = <1000000>;
	rohm,dvs-idle-voltage = <900000>;
	};

	buck3_reg: BUCK3 {
	regulator-name = "buck3";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1300000>;
	regulator-boot-on;
	rohm,dvs-run-voltage = <1000000>;
	};

	buck4_reg: BUCK4 {
	regulator-name = "buck4";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1300000>;
	rohm,dvs-run-voltage = <1000000>;
	};

	buck5_reg: BUCK5 {
	regulator-name = "buck5";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1350000>;
	regulator-boot-on;
	};

	buck6_reg: BUCK6 {
	regulator-name = "buck6";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	};

	buck7_reg: BUCK7 {
	regulator-name = "buck7";
	regulator-min-microvolt = <1605000>;
	regulator-max-microvolt = <1995000>;
	regulator-boot-on;
	};

	buck8_reg: BUCK8 {
	regulator-name = "buck8";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1400000>;
	regulator-boot-on;
	};

	ldo1_reg: LDO1 {
	regulator-name = "ldo1";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	/* leave on for snvs power button */
	regulator-always-on;
	};

	ldo2_reg: LDO2 {
	regulator-name = "ldo2";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <900000>;
	regulator-boot-on;
	/* leave on for snvs power button */
	regulator-always-on;
	};

	ldo3_reg: LDO3 {
	regulator-name = "ldo3";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	};

	ldo4_reg: LDO4 {
	regulator-name = "ldo4";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	};

	ldo5_reg: LDO5 {
	regulator-name = "ldo5";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	};

	ldo6_reg: LDO6 {
	regulator-name = "ldo6";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	};

	ldo7_reg: LDO7 {
	regulator-name = "ldo7";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	};
	};
	};

	typec_ptn5100: usb_typec@52 {
	compatible = "nxp,ptn5110";
	reg = <0x52>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_typec>;
	interrupt-parent = <&gpio3>;
	interrupts = <1 IRQ_TYPE_LEVEL_LOW>;

	connector {
	compatible = "usb-c-connector";
	label = "USB-C";
	data-role = "dual";
	power-role = "dual";
	try-power-role = "sink";
	source-pdos = <PDO_FIXED(5000, 2000,
	PDO_FIXED_USB_COMM \|
	PDO_FIXED_DUAL_ROLE \|
	PDO_FIXED_DATA_SWAP )>;
	- sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM \|
	+ sink-pdos = <PDO_FIXED(5000, 3500, PDO_FIXED_USB_COMM \|
	PDO_FIXED_DUAL_ROLE \|
	PDO_FIXED_DATA_SWAP )
	- PDO_VAR(5000, 3000, 3000)>;
	+ PDO_VAR(5000, 5000, 3500)>;
	op-sink-microwatt = <10000000>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	usb_con_hs: endpoint {
	remote-endpoint = <&typec_hs>;
	};
	};

	port@1 {
	reg = <1>;

	usb_con_ss: endpoint {
	remote-endpoint = <&typec_ss>;
	};
	};
	};
	};
	};

	rtc@68 {
	compatible = "microcrystal,rv4162";
	reg = <0x68>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_rtc>;
	interrupt-parent = <&gpio4>;
	interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
	};

	charger@6b { /* bq25896 */
	compatible = "ti,bq25890";
	reg = <0x6b>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_charger>;
	interrupt-parent = <&gpio3>;
	interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
	ti,battery-regulation-voltage = <4192000>; /* 4.192V */
	ti,charge-current = <1600000>; /* 1.6A */
	ti,termination-current = <66000>; /* 66mA */
	ti,precharge-current = <130000>; /* 130mA */
	ti,minimum-sys-voltage = <3000000>; /* 3V */
	ti,boost-voltage = <5000000>; /* 5V */
	ti,boost-max-current = <50000>; /* 50mA */
	};
	};

	&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	magnetometer@1e {
	compatible = "st,lsm9ds1-magn";
	reg = <0x1e>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_imu>;
	interrupt-parent = <&gpio3>;
	interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
	vdd-supply = <&reg_3v3_p>;
	vddio-supply = <&reg_3v3_p>;
	};

	+ sgtl5000: audio-codec@a {
	+ compatible = "fsl,sgtl5000";
	+ clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
	+ assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
	+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
	+ assigned-clock-rates = <24576000>;
	+ #sound-dai-cells = <0>;
	+ reg = <0x0a>;
	+ VDDD-supply = <&reg_1v8_p>;
	+ VDDIO-supply = <&reg_3v3_p>;
	+ VDDA-supply = <&reg_3v3_p>;
	+ };
	+
	touchscreen@5d {
	compatible = "goodix,gt5688";
	reg = <0x5d>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ts>;
	interrupt-parent = <&gpio3>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
	irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
	touchscreen-size-x = <720>;
	touchscreen-size-y = <1440>;
	AVDD28-supply = <&reg_2v8_p>;
	VDDIO-supply = <&reg_1v8_p>;
	};

	+ proximity-sensor@60 {
	+ compatible = "vishay,vcnl4040";
	+ reg = <0x60>;
	+ pinctrl-0 = <&pinctrl_prox>;
	+ };
	+
	accel-gyro@6a {
	compatible = "st,lsm9ds1-imu";
	reg = <0x6a>;
	vdd-supply = <&reg_3v3_p>;
	vddio-supply = <&reg_3v3_p>;
	+ mount-matrix = "1", "0", "0",
	+ "0", "1", "0",
	+ "0", "0", "-1";
	};
	};

	&iomuxc {
	pinctrl_bl: blgrp {
	fsl,pins = <
	MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */
	>;
	};

	pinctrl_bt: btgrp {
	fsl,pins = <
	MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */
	MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */
	>;
	};

	pinctrl_charger: chargergrp {
	fsl,pins = <
	MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80 /* CHRG_nINT */
	>;
	};

	pinctrl_fec1: fec1grp {
	fsl,pins = <
	MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
	MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
	MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
	MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
	MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
	MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
	MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
	MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
	MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
	MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
	MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
	MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
	MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
	MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
	MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
	MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f
	>;
	};

	pinctrl_ts: tsgrp {
	fsl,pins = <
	MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16 /* TOUCH INT */
	MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */
	>;
	};

	pinctrl_gpio_leds: gpioledgrp {
	fsl,pins = <
	MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16
	>;
	};

	pinctrl_gpio_keys: gpiokeygrp {
	fsl,pins = <
	MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
	MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16
	MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x180 /* HP_DET */
	+ MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */
	>;
	};

	pinctrl_haptic: hapticgrp {
	fsl,pins = <
	MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0xc6 /* nHAPTIC */
	>;
	};

	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f
	MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f
	>;
	};

	pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f
	MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f
	>;
	};

	pinctrl_imu: imugrp {
	fsl,pins = <
	MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8 /* IMU_INT */
	>;
	};

	pinctrl_pmic: pmicgrp {
	fsl,pins = <
	MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */
	>;
	};

	+ pinctrl_prox: proxgrp {
	+ fsl,pins = <
	+ MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80 /* prox intr */
	+ >;
	+ };
	+
	pinctrl_pwr_en: pwrengrp {
	fsl,pins = <
	MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06
	>;
	};

	pinctrl_rtc: rtcgrp {
	fsl,pins = <
	MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80 /* RTC intr */
	>;
	};

	+ pinctrl_sai2: sai2grp {
	+ fsl,pins = <
	+ MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
	+ MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
	+ MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
	+ MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
	+ MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
	+ >;
	+ };
	+
	+ pinctrl_sai6: sai6grp {
	+ fsl,pins = <
	+ MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6
	+ MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6
	+ MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6
	+ MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6
	+ >;
	+ };
	+
	pinctrl_typec: typecgrp {
	fsl,pins = <
	MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16
	MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
	MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
	>;
	};

	pinctrl_uart2: uart2grp {
	fsl,pins = <
	MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
	MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
	MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
	MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
	>;
	};

	pinctrl_uart3: uart3grp {
	fsl,pins = <
	MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
	MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
	>;
	};

	pinctrl_uart4: uart4grp {
	fsl,pins = <
	MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49
	MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49
	MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49
	MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49
	MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49
	>;
	};

	pinctrl_usdhc1: usdhc1grp {
	fsl,pins = <
	MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
	MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
	MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
	MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
	MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
	MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
	MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
	MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
	MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
	MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
	MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
	MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
	>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
	fsl,pins = <
	MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
	MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
	MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
	MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
	MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
	MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
	MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
	MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
	MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
	MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
	MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
	MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
	>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
	fsl,pins = <
	MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
	MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
	MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
	MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
	MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
	MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
	MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
	MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
	MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
	MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
	MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
	MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
	>;
	};

	pinctrl_usdhc2_pwr: usdhc2grppwr {
	fsl,pins = <
	MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
	>;
	};

	pinctrl_usdhc2_gpio: usdhc2grpgpio {
	fsl,pins = <
	MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */
	>;
	};

	pinctrl_usdhc2: usdhc2grp {
	fsl,pins = <
	MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
	MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
	MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
	MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
	MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
	MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
	>;
	};

	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
	fsl,pins = <
	MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
	MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
	MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
	MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
	MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
	MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
	>;
	};

	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
	fsl,pins = <
	MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
	MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf
	MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf
	MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf
	MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf
	MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf
	>;
	};

	pinctrl_wdog: wdoggrp {
	fsl,pins = <
	MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
	>;
	};

	pinctrl_wifi_pwr_en: wifipwrengrp {
	fsl,pins = <
	MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06
	>;
	};

	pinctrl_wwan: wwangrp {
	fsl,pins = <
	MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */
	MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */
	MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */
	>;
	};
	};

	&pgc_gpu {
	power-supply = <&buck3_reg>;
	};

	&pgc_vpu {
	power-supply = <&buck4_reg>;
	};

	&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_bl>;
	status = "okay";
	};

	&snvs_pwrkey {
	status = "okay";
	};

	+&sai2 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_sai2>;
	+ assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
	+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
	+ assigned-clock-rates = <24576000>;
	+ status = "okay";
	+};
	+
	+&sai6 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_sai6>;
	+ assigned-clocks = <&clk IMX8MQ_CLK_SAI6>;
	+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
	+ assigned-clock-rates = <24576000>;
	+ fsl,sai-synchronous-rx;
	+ status = "okay";
	+};
	+
	&uart1 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
	};

	&uart3 { /* GNSS */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
	};

	&uart4 { /* BT */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
	uart-has-rtscts;
	status = "okay";
	};

	&usb3_phy0 {
	+ vbus-supply = <&reg_5v_p>;
	status = "okay";
	};

	&usb3_phy1 {
	vbus-supply = <&reg_5v_p>;
	status = "okay";
	};

	&usb_dwc3_0 {
	#address-cells = <1>;
	#size-cells = <0>;
	dr_mode = "otg";
	status = "okay";

	port@0 {
	reg = <0>;

	typec_hs: endpoint {
	remote-endpoint = <&usb_con_hs>;
	};
	};

	port@1 {
	reg = <1>;

	typec_ss: endpoint {
	remote-endpoint = <&usb_con_ss>;
	};
	};
	};

	&usb_dwc3_1 {
	dr_mode = "host";
	status = "okay";
	};

	&usdhc1 {
	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
	};

	&usdhc2 {
	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	power-supply = <&wifi_pwr_en>;
	- non-removable;
	+ broken-cd;
	disable-wp;
	cap-sdio-irq;
	keep-power-in-suspend;
	wakeup-source;
	status = "okay";
	};

	&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/freescale/imx8mq-phanbell.dts b/sys/gnu/dts/arm64/freescale/imx8mq-phanbell.dts
	index 3f2a489a4ad8..77ab568fae67 100644
	--- a/sys/gnu/dts/arm64/freescale/imx8mq-phanbell.dts
	+++ b/sys/gnu/dts/arm64/freescale/imx8mq-phanbell.dts
	@@ -1,376 +1,480 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	/*
	* Copyright 2017-2019 NXP
	*/

	/dts-v1/;

	#include "imx8mq.dtsi"

	/ {
	model = "Google i.MX8MQ Phanbell";
	compatible = "google,imx8mq-phanbell", "fsl,imx8mq";

	chosen {
	stdout-path = &uart1;
	};

	memory@40000000 {
	device_type = "memory";
	reg = <0x00000000 0x40000000 0 0x40000000>;
	};

	pmic_osc: clock-pmic {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "pmic_osc";
	};

	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
	compatible = "regulator-fixed";
	regulator-name = "VSD_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};
	+
	+ fan: gpio-fan {
	+ compatible = "gpio-fan";
	+ gpio-fan,speed-map = <0 0 8600 1>;
	+ gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
	+ #cooling-cells = <2>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_gpio_fan>;
	+ status = "okay";
	+ };
	};

	&A53_0 {
	cpu-supply = <&buck2>;
	};

	&A53_1 {
	cpu-supply = <&buck2>;
	};

	&A53_2 {
	cpu-supply = <&buck2>;
	};

	&A53_3 {
	cpu-supply = <&buck2>;
	};

	+&cpu_thermal {
	+ trips {
	+ cpu_alert0: trip0 {
	+ temperature = <75000>;
	+ hysteresis = <2000>;
	+ type = "passive";
	+ };
	+
	+ cpu_alert1: trip1 {
	+ temperature = <80000>;
	+ hysteresis = <2000>;
	+ type = "passive";
	+ };
	+
	+ cpu_crit0: trip3 {
	+ temperature = <90000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	+
	+ fan_toggle0: trip4 {
	+ temperature = <65000>;
	+ hysteresis = <10000>;
	+ type = "active";
	+ };
	+ };
	+
	+ cooling-maps {
	+ map0 {
	+ trip = <&cpu_alert0>;
	+ cooling-device =
	+ <&A53_0 0 1>; /* Exclude highest OPP */
	+ };
	+
	+ map1 {
	+ trip = <&cpu_alert1>;
	+ cooling-device =
	+ <&A53_0 0 2>; /* Exclude two highest OPPs */
	+ };
	+
	+ map4 {
	+ trip = <&fan_toggle0>;
	+ cooling-device = <&fan 0 1>;
	+ };
	+ };
	+};
	+
	&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic: pmic@4b {
	compatible = "rohm,bd71837";
	reg = <0x4b>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pmic>;
	#clock-cells = <0>;
	clocks = <&pmic_osc>;
	clock-output-names = "pmic_clk";
	interrupt-parent = <&gpio1>;
	interrupts = <3 GPIO_ACTIVE_LOW>;

	regulators {
	buck1: BUCK1 {
	regulator-name = "buck1";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1300000>;
	regulator-boot-on;
	regulator-always-on;
	regulator-ramp-delay = <1250>;
	rohm,dvs-run-voltage = <900000>;
	rohm,dvs-idle-voltage = <900000>;
	rohm,dvs-suspend-voltage = <800000>;
	};

	buck2: BUCK2 {
	regulator-name = "buck2";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1000000>;
	regulator-boot-on;
	regulator-always-on;
	rohm,dvs-run-voltage = <1000000>;
	rohm,dvs-idle-voltage = <900000>;
	};

	buck3: BUCK3 {
	regulator-name = "buck3";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1300000>;
	regulator-boot-on;
	rohm,dvs-run-voltage = <900000>;
	};

	buck4: BUCK4 {
	regulator-name = "buck4";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1300000>;
	regulator-boot-on;
	regulator-always-on;
	rohm,dvs-run-voltage = <900000>;
	};

	buck5: BUCK5 {
	regulator-name = "buck5";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1350000>;
	regulator-boot-on;
	regulator-always-on;
	};

	buck6: BUCK6 {
	regulator-name = "buck6";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	buck7: BUCK7 {
	regulator-name = "buck7";
	regulator-min-microvolt = <1605000>;
	regulator-max-microvolt = <1995000>;
	regulator-boot-on;
	regulator-always-on;
	};

	buck8: BUCK8 {
	regulator-name = "buck8";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1400000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo1: LDO1 {
	regulator-name = "ldo1";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo2: LDO2 {
	regulator-name = "ldo2";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <900000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo3: LDO3 {
	regulator-name = "ldo3";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo4: LDO4 {
	regulator-name = "ldo4";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo5: LDO5 {
	regulator-name = "ldo5";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo6: LDO6 {
	regulator-name = "ldo6";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo7: LDO7 {
	regulator-name = "ldo7";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};
	};
	};

	+&fec1 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pinctrl_fec1>;
	+ phy-mode = "rgmii-id";
	+ phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
	+ phy-reset-duration = <10>;
	+ phy-reset-post-delay = <50>;
	+ phy-handle = <&ethphy0>;
	+ fsl,magic-packet;
	+ status = "okay";
	+
	+ mdio {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ ethphy0: ethernet-phy@0 {
	+ compatible = "ethernet-phy-ieee802.3-c22";
	+ reg = <0>;
	+ };
	+ };
	+};
	+
	&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
	};

	&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
	};

	&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	bus-width = <4>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
	};

	&usb3_phy0 {
	status = "okay";
	};

	&usb_dwc3_0 {
	dr_mode = "otg";
	status = "okay";
	};

	&usb3_phy1 {
	status = "okay";
	};

	&usb_dwc3_1 {
	dr_mode = "host";
	status = "okay";
	};

	&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
	};

	&iomuxc {
	+ pinctrl_fec1: fec1grp {
	+ fsl,pins = <
	+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
	+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
	+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
	+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
	+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
	+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
	+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
	+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
	+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
	+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
	+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
	+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
	+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
	+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
	+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
	+ >;
	+ };
	+
	+ pinctrl_gpio_fan: gpiofangrp {
	+ fsl,pins = <
	+ MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16
	+ >;
	+ };
	+
	pinctrl_i2c1: i2c1grp {
	fsl,pins = <
	MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
	MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
	>;
	};

	pinctrl_pmic: pmicirq {
	fsl,pins = <
	MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
	>;
	};

	pinctrl_uart1: uart1grp {
	fsl,pins = <
	MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
	MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
	>;
	};

	pinctrl_usdhc1: usdhc1grp {
	fsl,pins = <
	MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
	MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
	MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
	MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
	MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
	MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
	MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
	MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
	MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
	MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
	MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
	MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
	>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
	fsl,pins = <
	MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
	MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
	MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
	MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
	MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
	MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
	MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
	MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
	MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
	MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
	MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
	MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
	>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
	fsl,pins = <
	MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
	MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
	MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
	MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
	MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
	MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
	MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
	MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
	MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
	MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
	MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
	MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
	>;
	};

	pinctrl_usdhc2_gpio: usdhc2grpgpio {
	fsl,pins = <
	MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
	MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
	>;
	};

	pinctrl_usdhc2: usdhc2grp {
	fsl,pins = <
	MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
	MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
	MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
	MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
	MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
	MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
	MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
	>;
	};

	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
	fsl,pins = <
	MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
	MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
	MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
	MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
	MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
	MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
	MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
	>;
	};

	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
	fsl,pins = <
	MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
	MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
	MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
	MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
	MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
	MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
	MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
	>;
	};

	pinctrl_wdog: wdoggrp {
	fsl,pins = <
	MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
	>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/freescale/imx8mq.dtsi b/sys/gnu/dts/arm64/freescale/imx8mq.dtsi
	index 6a1e83922c71..bab88369be1b 100644
	--- a/sys/gnu/dts/arm64/freescale/imx8mq.dtsi
	+++ b/sys/gnu/dts/arm64/freescale/imx8mq.dtsi
	@@ -1,1222 +1,1228 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright 2017 NXP
	* Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
	*/

	#include <dt-bindings/clock/imx8mq-clock.h>
	#include <dt-bindings/power/imx8mq-power.h>
	#include <dt-bindings/reset/imx8mq-reset.h>
	#include <dt-bindings/gpio/gpio.h>
	#include "dt-bindings/input/input.h"
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/thermal/thermal.h>
	#include "imx8mq-pinfunc.h"

	/ {
	interrupt-parent = <&gpc>;

	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	gpio0 = &gpio1;
	gpio1 = &gpio2;
	gpio2 = &gpio3;
	gpio3 = &gpio4;
	gpio4 = &gpio5;
	i2c0 = &i2c1;
	i2c1 = &i2c2;
	i2c2 = &i2c3;
	i2c3 = &i2c4;
	serial0 = &uart1;
	serial1 = &uart2;
	serial2 = &uart3;
	serial3 = &uart4;
	spi0 = &ecspi1;
	spi1 = &ecspi2;
	spi2 = &ecspi3;
	};

	ckil: clock-ckil {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "ckil";
	};

	osc_25m: clock-osc-25m {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <25000000>;
	clock-output-names = "osc_25m";
	};

	osc_27m: clock-osc-27m {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <27000000>;
	clock-output-names = "osc_27m";
	};

	clk_ext1: clock-ext1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <133000000>;
	clock-output-names = "clk_ext1";
	};

	clk_ext2: clock-ext2 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <133000000>;
	clock-output-names = "clk_ext2";
	};

	clk_ext3: clock-ext3 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <133000000>;
	clock-output-names = "clk_ext3";
	};

	clk_ext4: clock-ext4 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency= <133000000>;
	clock-output-names = "clk_ext4";
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	A53_0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0>;
	clock-latency = <61036>; /* two CLK32 periods */
	clocks = <&clk IMX8MQ_CLK_ARM>;
	enable-method = "psci";
	next-level-cache = <&A53_L2>;
	operating-points-v2 = <&a53_opp_table>;
	#cooling-cells = <2>;
	nvmem-cells = <&cpu_speed_grade>;
	nvmem-cell-names = "speed_grade";
	};

	A53_1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x1>;
	clock-latency = <61036>; /* two CLK32 periods */
	clocks = <&clk IMX8MQ_CLK_ARM>;
	enable-method = "psci";
	next-level-cache = <&A53_L2>;
	operating-points-v2 = <&a53_opp_table>;
	#cooling-cells = <2>;
	};

	A53_2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x2>;
	clock-latency = <61036>; /* two CLK32 periods */
	clocks = <&clk IMX8MQ_CLK_ARM>;
	enable-method = "psci";
	next-level-cache = <&A53_L2>;
	operating-points-v2 = <&a53_opp_table>;
	#cooling-cells = <2>;
	};

	A53_3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x3>;
	clock-latency = <61036>; /* two CLK32 periods */
	clocks = <&clk IMX8MQ_CLK_ARM>;
	enable-method = "psci";
	next-level-cache = <&A53_L2>;
	operating-points-v2 = <&a53_opp_table>;
	#cooling-cells = <2>;
	};

	A53_L2: l2-cache0 {
	compatible = "cache";
	};
	};

	a53_opp_table: opp-table {
	compatible = "operating-points-v2";
	opp-shared;

	opp-800000000 {
	opp-hz = /bits/ 64 <800000000>;
	opp-microvolt = <900000>;
	/* Industrial only */
	opp-supported-hw = <0xf>, <0x4>;
	clock-latency-ns = <150000>;
	opp-suspend;
	};

	opp-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	opp-microvolt = <900000>;
	/* Consumer only */
	opp-supported-hw = <0xe>, <0x3>;
	clock-latency-ns = <150000>;
	opp-suspend;
	};

	opp-1300000000 {
	opp-hz = /bits/ 64 <1300000000>;
	opp-microvolt = <1000000>;
	opp-supported-hw = <0xc>, <0x4>;
	clock-latency-ns = <150000>;
	opp-suspend;
	};

	opp-1500000000 {
	opp-hz = /bits/ 64 <1500000000>;
	opp-microvolt = <1000000>;
	opp-supported-hw = <0x8>, <0x3>;
	clock-latency-ns = <150000>;
	opp-suspend;
	};
	};

	pmu {
	compatible = "arm,cortex-a53-pmu";
	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-parent = <&gic>;
	interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	thermal-zones {
	- cpu-thermal {
	+ cpu_thermal: cpu-thermal {
	polling-delay-passive = <250>;
	polling-delay = <2000>;
	thermal-sensors = <&tmu 0>;

	trips {
	cpu_alert: cpu-alert {
	temperature = <80000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu-crit {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu_alert>;
	cooling-device =
	<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	gpu-thermal {
	polling-delay-passive = <250>;
	polling-delay = <2000>;
	thermal-sensors = <&tmu 1>;

	trips {
	gpu_alert: gpu-alert {
	temperature = <80000>;
	hysteresis = <2000>;
	type = "passive";
	};

	gpu-crit {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&gpu_alert>;
	cooling-device =
	<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	vpu-thermal {
	polling-delay-passive = <250>;
	polling-delay = <2000>;
	thermal-sensors = <&tmu 2>;

	trips {
	vpu-crit {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
	interrupt-parent = <&gic>;
	arm,no-tick-in-suspend;
	};

	soc@0 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x0 0x3e000000>;
	dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;

	bus@30000000 { /* AIPS1 */
	- compatible = "simple-bus";
	+ compatible = "fsl,aips-bus", "simple-bus";
	+ reg = <0x30000000 0x400000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x30000000 0x30000000 0x400000>;

	sai1: sai@30010000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx8mq-sai";
	reg = <0x30010000 0x10000>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,
	<&clk IMX8MQ_CLK_SAI1_ROOT>,
	<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	sai6: sai@30030000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx8mq-sai";
	reg = <0x30030000 0x10000>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_SAI6_IPG>,
	<&clk IMX8MQ_CLK_SAI6_ROOT>,
	<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	sai5: sai@30040000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx8mq-sai";
	reg = <0x30040000 0x10000>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_SAI5_IPG>,
	<&clk IMX8MQ_CLK_SAI5_ROOT>,
	<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	sai4: sai@30050000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx8mq-sai";
	reg = <0x30050000 0x10000>;
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_SAI4_IPG>,
	<&clk IMX8MQ_CLK_SAI4_ROOT>,
	<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	gpio1: gpio@30200000 {
	compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
	reg = <0x30200000 0x10000>;
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 10 30>;
	};

	gpio2: gpio@30210000 {
	compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
	reg = <0x30210000 0x10000>;
	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 40 21>;
	};

	gpio3: gpio@30220000 {
	compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
	reg = <0x30220000 0x10000>;
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 61 26>;
	};

	gpio4: gpio@30230000 {
	compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
	reg = <0x30230000 0x10000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 87 32>;
	};

	gpio5: gpio@30240000 {
	compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
	reg = <0x30240000 0x10000>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&iomuxc 0 119 30>;
	};

	tmu: tmu@30260000 {
	compatible = "fsl,imx8mq-tmu";
	reg = <0x30260000 0x10000>;
	interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
	little-endian;
	fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
	fsl,tmu-calibration = <0x00000000 0x00000023
	0x00000001 0x00000029
	0x00000002 0x0000002f
	0x00000003 0x00000035
	0x00000004 0x0000003d
	0x00000005 0x00000043
	0x00000006 0x0000004b
	0x00000007 0x00000051
	0x00000008 0x00000057
	0x00000009 0x0000005f
	0x0000000a 0x00000067
	0x0000000b 0x0000006f

	0x00010000 0x0000001b
	0x00010001 0x00000023
	0x00010002 0x0000002b
	0x00010003 0x00000033
	0x00010004 0x0000003b
	0x00010005 0x00000043
	0x00010006 0x0000004b
	0x00010007 0x00000055
	0x00010008 0x0000005d
	0x00010009 0x00000067
	0x0001000a 0x00000070

	0x00020000 0x00000017
	0x00020001 0x00000023
	0x00020002 0x0000002d
	0x00020003 0x00000037
	0x00020004 0x00000041
	0x00020005 0x0000004b
	0x00020006 0x00000057
	0x00020007 0x00000063
	0x00020008 0x0000006f

	0x00030000 0x00000015
	0x00030001 0x00000021
	0x00030002 0x0000002d
	0x00030003 0x00000039
	0x00030004 0x00000045
	0x00030005 0x00000053
	0x00030006 0x0000005f
	0x00030007 0x00000071>;
	#thermal-sensor-cells = <1>;
	};

	wdog1: watchdog@30280000 {
	compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
	reg = <0x30280000 0x10000>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
	status = "disabled";
	};

	wdog2: watchdog@30290000 {
	compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
	reg = <0x30290000 0x10000>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
	status = "disabled";
	};

	wdog3: watchdog@302a0000 {
	compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
	reg = <0x302a0000 0x10000>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
	status = "disabled";
	};

	sdma2: sdma@302c0000 {
	compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
	reg = <0x302c0000 0x10000>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
	<&clk IMX8MQ_CLK_SDMA2_ROOT>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
	};

	lcdif: lcd-controller@30320000 {
	compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
	reg = <0x30320000 0x10000>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
	clock-names = "pix";
	assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
	<&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
	<&clk IMX8MQ_CLK_LCDIF_PIXEL>,
	<&clk IMX8MQ_VIDEO_PLL1>;
	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
	<&clk IMX8MQ_VIDEO_PLL1>,
	<&clk IMX8MQ_VIDEO_PLL1_OUT>;
	assigned-clock-rates = <0>, <0>, <0>, <594000000>;
	status = "disabled";
	};

	- iomuxc: iomuxc@30330000 {
	+ iomuxc: pinctrl@30330000 {
	compatible = "fsl,imx8mq-iomuxc";
	reg = <0x30330000 0x10000>;
	};

	iomuxc_gpr: syscon@30340000 {
	compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
	"syscon", "simple-mfd";
	reg = <0x30340000 0x10000>;

	mux: mux-controller {
	compatible = "mmio-mux";
	#mux-control-cells = <1>;
	mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
	};
	};

	ocotp: ocotp-ctrl@30350000 {
	compatible = "fsl,imx8mq-ocotp", "syscon";
	reg = <0x30350000 0x10000>;
	clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpu_speed_grade: speed-grade@10 {
	reg = <0x10 4>;
	};
	};

	anatop: syscon@30360000 {
	compatible = "fsl,imx8mq-anatop", "syscon";
	reg = <0x30360000 0x10000>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	};

	snvs: snvs@30370000 {
	compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
	reg = <0x30370000 0x10000>;

	snvs_rtc: snvs-rtc-lp{
	compatible = "fsl,sec-v4.0-mon-rtc-lp";
	regmap =<&snvs>;
	offset = <0x34>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
	clock-names = "snvs-rtc";
	};

	snvs_pwrkey: snvs-powerkey {
	compatible = "fsl,sec-v4.0-pwrkey";
	regmap = <&snvs>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
	+ clock-names = "snvs-pwrkey";
	linux,keycode = <KEY_POWER>;
	wakeup-source;
	status = "disabled";
	};
	};

	clk: clock-controller@30380000 {
	compatible = "fsl,imx8mq-ccm";
	reg = <0x30380000 0x10000>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	#clock-cells = <1>;
	clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
	<&clk_ext1>, <&clk_ext2>,
	<&clk_ext3>, <&clk_ext4>;
	clock-names = "ckil", "osc_25m", "osc_27m",
	"clk_ext1", "clk_ext2",
	"clk_ext3", "clk_ext4";
	assigned-clocks = <&clk IMX8MQ_CLK_NOC>;
	assigned-clock-rates = <800000000>;
	};

	src: reset-controller@30390000 {
	compatible = "fsl,imx8mq-src", "syscon";
	reg = <0x30390000 0x10000>;
	#reset-cells = <1>;
	};

	gpc: gpc@303a0000 {
	compatible = "fsl,imx8mq-gpc";
	reg = <0x303a0000 0x10000>;
	interrupt-parent = <&gic>;
	interrupt-controller;
	#interrupt-cells = <3>;

	pgc {
	#address-cells = <1>;
	#size-cells = <0>;

	pgc_mipi: power-domain@0 {
	#power-domain-cells = <0>;
	reg = <IMX8M_POWER_DOMAIN_MIPI>;
	};

	/*
	* As per comment in ATF source code:
	*
	* PCIE1 and PCIE2 share the
	* same reset signal, if we
	* power down PCIE2, PCIE1
	* will be held in reset too.
	*
	* So instead of creating two
	* separate power domains for
	* PCIE1 and PCIE2 we create a
	* link between both and use
	* it as a shared PCIE power
	* domain.
	*/
	pgc_pcie: power-domain@1 {
	#power-domain-cells = <0>;
	reg = <IMX8M_POWER_DOMAIN_PCIE1>;
	power-domains = <&pgc_pcie2>;
	};

	pgc_otg1: power-domain@2 {
	#power-domain-cells = <0>;
	reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
	};

	pgc_otg2: power-domain@3 {
	#power-domain-cells = <0>;
	reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
	};

	pgc_ddr1: power-domain@4 {
	#power-domain-cells = <0>;
	reg = <IMX8M_POWER_DOMAIN_DDR1>;
	};

	pgc_gpu: power-domain@5 {
	#power-domain-cells = <0>;
	reg = <IMX8M_POWER_DOMAIN_GPU>;
	clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
	<&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
	<&clk IMX8MQ_CLK_GPU_AXI>,
	<&clk IMX8MQ_CLK_GPU_AHB>;
	};

	pgc_vpu: power-domain@6 {
	#power-domain-cells = <0>;
	reg = <IMX8M_POWER_DOMAIN_VPU>;
	};

	pgc_disp: power-domain@7 {
	#power-domain-cells = <0>;
	reg = <IMX8M_POWER_DOMAIN_DISP>;
	};

	pgc_mipi_csi1: power-domain@8 {
	#power-domain-cells = <0>;
	reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
	};

	pgc_mipi_csi2: power-domain@9 {
	#power-domain-cells = <0>;
	reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
	};

	pgc_pcie2: power-domain@a {
	#power-domain-cells = <0>;
	reg = <IMX8M_POWER_DOMAIN_PCIE2>;
	};
	};
	};
	};

	bus@30400000 { /* AIPS2 */
	- compatible = "simple-bus";
	+ compatible = "fsl,aips-bus", "simple-bus";
	+ reg = <0x30400000 0x400000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x30400000 0x30400000 0x400000>;

	pwm1: pwm@30660000 {
	compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
	reg = <0x30660000 0x10000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
	<&clk IMX8MQ_CLK_PWM1_ROOT>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm2: pwm@30670000 {
	compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
	reg = <0x30670000 0x10000>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
	<&clk IMX8MQ_CLK_PWM2_ROOT>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm3: pwm@30680000 {
	compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
	reg = <0x30680000 0x10000>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
	<&clk IMX8MQ_CLK_PWM3_ROOT>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm4: pwm@30690000 {
	compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
	reg = <0x30690000 0x10000>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
	<&clk IMX8MQ_CLK_PWM4_ROOT>;
	clock-names = "ipg", "per";
	#pwm-cells = <2>;
	status = "disabled";
	};

	system_counter: timer@306a0000 {
	compatible = "nxp,sysctr-timer";
	reg = <0x306a0000 0x20000>;
	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc_25m>;
	clock-names = "per";
	};
	};

	bus@30800000 { /* AIPS3 */
	- compatible = "simple-bus";
	+ compatible = "fsl,aips-bus", "simple-bus";
	+ reg = <0x30800000 0x400000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x30800000 0x30800000 0x400000>,
	<0x08000000 0x08000000 0x10000000>;

	ecspi1: spi@30820000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
	reg = <0x30820000 0x10000>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
	<&clk IMX8MQ_CLK_ECSPI1_ROOT>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ecspi2: spi@30830000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
	reg = <0x30830000 0x10000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
	<&clk IMX8MQ_CLK_ECSPI2_ROOT>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	ecspi3: spi@30840000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
	reg = <0x30840000 0x10000>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
	<&clk IMX8MQ_CLK_ECSPI3_ROOT>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart1: serial@30860000 {
	compatible = "fsl,imx8mq-uart",
	"fsl,imx6q-uart";
	reg = <0x30860000 0x10000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
	<&clk IMX8MQ_CLK_UART1_ROOT>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart3: serial@30880000 {
	compatible = "fsl,imx8mq-uart",
	"fsl,imx6q-uart";
	reg = <0x30880000 0x10000>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
	<&clk IMX8MQ_CLK_UART3_ROOT>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	uart2: serial@30890000 {
	compatible = "fsl,imx8mq-uart",
	"fsl,imx6q-uart";
	reg = <0x30890000 0x10000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
	<&clk IMX8MQ_CLK_UART2_ROOT>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	sai2: sai@308b0000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx8mq-sai";
	reg = <0x308b0000 0x10000>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
	<&clk IMX8MQ_CLK_SAI2_ROOT>,
	<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	sai3: sai@308c0000 {
	#sound-dai-cells = <0>;
	compatible = "fsl,imx8mq-sai";
	reg = <0x308c0000 0x10000>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_SAI3_IPG>,
	<&clk IMX8MQ_CLK_SAI3_ROOT>,
	<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	crypto: crypto@30900000 {
	compatible = "fsl,sec-v4.0";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x30900000 0x40000>;
	ranges = <0 0x30900000 0x40000>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_AHB>,
	<&clk IMX8MQ_CLK_IPG_ROOT>;
	clock-names = "aclk", "ipg";

	sec_jr0: jr@1000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x1000 0x1000>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	};

	sec_jr1: jr@2000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x2000 0x1000>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	};

	sec_jr2: jr@3000 {
	compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x3000 0x1000>;
	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	dphy: dphy@30a00300 {
	compatible = "fsl,imx8mq-mipi-dphy";
	reg = <0x30a00300 0x100>;
	clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
	clock-names = "phy_ref";
	assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
	assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
	assigned-clock-rates = <24000000>;
	#phy-cells = <0>;
	power-domains = <&pgc_mipi>;
	status = "disabled";
	};

	i2c1: i2c@30a20000 {
	compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
	reg = <0x30a20000 0x10000>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c2: i2c@30a30000 {
	compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
	reg = <0x30a30000 0x10000>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c3: i2c@30a40000 {
	compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
	reg = <0x30a40000 0x10000>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c4: i2c@30a50000 {
	compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
	reg = <0x30a50000 0x10000>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart4: serial@30a60000 {
	compatible = "fsl,imx8mq-uart",
	"fsl,imx6q-uart";
	reg = <0x30a60000 0x10000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
	<&clk IMX8MQ_CLK_UART4_ROOT>;
	clock-names = "ipg", "per";
	status = "disabled";
	};

	usdhc1: mmc@30b40000 {
	compatible = "fsl,imx8mq-usdhc",
	"fsl,imx7d-usdhc";
	reg = <0x30b40000 0x10000>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
	<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
	<&clk IMX8MQ_CLK_USDHC1_ROOT>;
	clock-names = "ipg", "ahb", "per";
	fsl,tuning-start-tap = <20>;
	fsl,tuning-step = <2>;
	bus-width = <4>;
	status = "disabled";
	};

	usdhc2: mmc@30b50000 {
	compatible = "fsl,imx8mq-usdhc",
	"fsl,imx7d-usdhc";
	reg = <0x30b50000 0x10000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
	<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
	<&clk IMX8MQ_CLK_USDHC2_ROOT>;
	clock-names = "ipg", "ahb", "per";
	fsl,tuning-start-tap = <20>;
	fsl,tuning-step = <2>;
	bus-width = <4>;
	status = "disabled";
	};

	qspi0: spi@30bb0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
	reg = <0x30bb0000 0x10000>,
	<0x08000000 0x10000000>;
	reg-names = "QuadSPI", "QuadSPI-memory";
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
	<&clk IMX8MQ_CLK_QSPI_ROOT>;
	clock-names = "qspi_en", "qspi";
	status = "disabled";
	};

	sdma1: sdma@30bd0000 {
	compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
	reg = <0x30bd0000 0x10000>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
	<&clk IMX8MQ_CLK_AHB>;
	clock-names = "ipg", "ahb";
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
	};

	fec1: ethernet@30be0000 {
	compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
	reg = <0x30be0000 0x10000>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
	<&clk IMX8MQ_CLK_ENET1_ROOT>,
	<&clk IMX8MQ_CLK_ENET_TIMER>,
	<&clk IMX8MQ_CLK_ENET_REF>,
	<&clk IMX8MQ_CLK_ENET_PHY_REF>;
	clock-names = "ipg", "ahb", "ptp",
	"enet_clk_ref", "enet_out";
	fsl,num-tx-queues = <3>;
	fsl,num-rx-queues = <3>;
	status = "disabled";
	};
	};

	bus@32c00000 { /* AIPS4 */
	- compatible = "simple-bus";
	+ compatible = "fsl,aips-bus", "simple-bus";
	+ reg = <0x32c00000 0x400000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x32c00000 0x32c00000 0x400000>;

	irqsteer: interrupt-controller@32e2d000 {
	compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
	reg = <0x32e2d000 0x1000>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
	clock-names = "ipg";
	fsl,channel = <0>;
	fsl,num-irqs = <64>;
	interrupt-controller;
	#interrupt-cells = <1>;
	};
	};

	gpu: gpu@38000000 {
	compatible = "vivante,gc";
	reg = <0x38000000 0x40000>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
	<&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
	<&clk IMX8MQ_CLK_GPU_AXI>,
	<&clk IMX8MQ_CLK_GPU_AHB>;
	clock-names = "core", "shader", "bus", "reg";
	#cooling-cells = <2>;
	assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
	<&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
	<&clk IMX8MQ_CLK_GPU_AXI>,
	<&clk IMX8MQ_CLK_GPU_AHB>,
	<&clk IMX8MQ_GPU_PLL_BYPASS>;
	assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
	<&clk IMX8MQ_GPU_PLL_OUT>,
	<&clk IMX8MQ_GPU_PLL_OUT>,
	<&clk IMX8MQ_GPU_PLL_OUT>,
	<&clk IMX8MQ_GPU_PLL>;
	assigned-clock-rates = <800000000>, <800000000>,
	<800000000>, <800000000>, <0>;
	power-domains = <&pgc_gpu>;
	};

	usb_dwc3_0: usb@38100000 {
	compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
	reg = <0x38100000 0x10000>;
	clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
	<&clk IMX8MQ_CLK_USB_CORE_REF>,
	<&clk IMX8MQ_CLK_32K>;
	clock-names = "bus_early", "ref", "suspend";
	assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
	<&clk IMX8MQ_CLK_USB_CORE_REF>;
	assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
	<&clk IMX8MQ_SYS1_PLL_100M>;
	assigned-clock-rates = <500000000>, <100000000>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	phys = <&usb3_phy0>, <&usb3_phy0>;
	phy-names = "usb2-phy", "usb3-phy";
	power-domains = <&pgc_otg1>;
	usb3-resume-missing-cas;
	status = "disabled";
	};

	usb3_phy0: usb-phy@381f0040 {
	compatible = "fsl,imx8mq-usb-phy";
	reg = <0x381f0040 0x40>;
	clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
	clock-names = "phy";
	assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
	assigned-clock-rates = <100000000>;
	#phy-cells = <0>;
	status = "disabled";
	};

	usb_dwc3_1: usb@38200000 {
	compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
	reg = <0x38200000 0x10000>;
	clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
	<&clk IMX8MQ_CLK_USB_CORE_REF>,
	<&clk IMX8MQ_CLK_32K>;
	clock-names = "bus_early", "ref", "suspend";
	assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
	<&clk IMX8MQ_CLK_USB_CORE_REF>;
	assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
	<&clk IMX8MQ_SYS1_PLL_100M>;
	assigned-clock-rates = <500000000>, <100000000>;
	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	phys = <&usb3_phy1>, <&usb3_phy1>;
	phy-names = "usb2-phy", "usb3-phy";
	power-domains = <&pgc_otg2>;
	usb3-resume-missing-cas;
	status = "disabled";
	};

	usb3_phy1: usb-phy@382f0040 {
	compatible = "fsl,imx8mq-usb-phy";
	reg = <0x382f0040 0x40>;
	clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
	clock-names = "phy";
	assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
	assigned-clock-rates = <100000000>;
	#phy-cells = <0>;
	status = "disabled";
	};

	pcie0: pcie@33800000 {
	compatible = "fsl,imx8mq-pcie";
	reg = <0x33800000 0x400000>,
	<0x1ff00000 0x80000>;
	reg-names = "dbi", "config";
	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	bus-range = <0x00 0xff>;
	ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
	0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
	num-lanes = <1>;
	num-viewport = <4>;
	interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
	fsl,max-link-speed = <2>;
	power-domains = <&pgc_pcie>;
	resets = <&src IMX8MQ_RESET_PCIEPHY>,
	<&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
	<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
	reset-names = "pciephy", "apps", "turnoff";
	status = "disabled";
	};

	pcie1: pcie@33c00000 {
	compatible = "fsl,imx8mq-pcie";
	reg = <0x33c00000 0x400000>,
	<0x27f00000 0x80000>;
	reg-names = "dbi", "config";
	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
	0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
	num-lanes = <1>;
	num-viewport = <4>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	fsl,max-link-speed = <2>;
	power-domains = <&pgc_pcie>;
	resets = <&src IMX8MQ_RESET_PCIEPHY2>,
	<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
	<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
	reset-names = "pciephy", "apps", "turnoff";
	status = "disabled";
	};

	gic: interrupt-controller@38800000 {
	compatible = "arm,gic-v3";
	reg = <0x38800000 0x10000>, /* GIC Dist */
	<0x38880000 0xc0000>, /* GICR */
	<0x31000000 0x2000>, /* GICC */
	<0x31010000 0x2000>, /* GICV */
	<0x31020000 0x2000>; /* GICH */
	#interrupt-cells = <3>;
	interrupt-controller;
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-parent = <&gic>;
	};

	ddrc: memory-controller@3d400000 {
	compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
	reg = <0x3d400000 0x400000>;
	clock-names = "core", "pll", "alt", "apb";
	clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
	<&clk IMX8MQ_DRAM_PLL_OUT>,
	<&clk IMX8MQ_CLK_DRAM_ALT>,
	<&clk IMX8MQ_CLK_DRAM_APB>;
	};

	ddr-pmu@3d800000 {
	compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
	reg = <0x3d800000 0x400000>;
	interrupt-parent = <&gic>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/freescale/imx8qxp.dtsi b/sys/gnu/dts/arm64/freescale/imx8qxp.dtsi
	index fb5f752b15fe..e8ffb7590656 100644
	--- a/sys/gnu/dts/arm64/freescale/imx8qxp.dtsi
	+++ b/sys/gnu/dts/arm64/freescale/imx8qxp.dtsi
	@@ -1,589 +1,628 @@
	// SPDX-License-Identifier: GPL-2.0+
	/*
	* Copyright (C) 2016 Freescale Semiconductor, Inc.
	* Copyright 2017-2018 NXP
	* Dong Aisheng <aisheng.dong@nxp.com>
	*/

	#include <dt-bindings/clock/imx8-clock.h>
	#include <dt-bindings/firmware/imx/rsrc.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/pinctrl/pads-imx8qxp.h>
	+#include <dt-bindings/thermal/thermal.h>

	/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	gpio0 = &lsio_gpio0;
	gpio1 = &lsio_gpio1;
	gpio2 = &lsio_gpio2;
	gpio3 = &lsio_gpio3;
	gpio4 = &lsio_gpio4;
	gpio5 = &lsio_gpio5;
	gpio6 = &lsio_gpio6;
	gpio7 = &lsio_gpio7;
	mmc0 = &usdhc1;
	mmc1 = &usdhc2;
	mmc2 = &usdhc3;
	mu1 = &lsio_mu1;
	serial0 = &adma_lpuart0;
	serial1 = &adma_lpuart1;
	serial2 = &adma_lpuart2;
	serial3 = &adma_lpuart3;
	};

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	/* We have 1 clusters with 4 Cortex-A35 cores */
	A35_0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a35";
	reg = <0x0 0x0>;
	enable-method = "psci";
	next-level-cache = <&A35_L2>;
	clocks = <&clk IMX_A35_CLK>;
	operating-points-v2 = <&a35_opp_table>;
	#cooling-cells = <2>;
	};

	A35_1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a35";
	reg = <0x0 0x1>;
	enable-method = "psci";
	next-level-cache = <&A35_L2>;
	clocks = <&clk IMX_A35_CLK>;
	operating-points-v2 = <&a35_opp_table>;
	#cooling-cells = <2>;
	};

	A35_2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a35";
	reg = <0x0 0x2>;
	enable-method = "psci";
	next-level-cache = <&A35_L2>;
	clocks = <&clk IMX_A35_CLK>;
	operating-points-v2 = <&a35_opp_table>;
	#cooling-cells = <2>;
	};

	A35_3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a35";
	reg = <0x0 0x3>;
	enable-method = "psci";
	next-level-cache = <&A35_L2>;
	clocks = <&clk IMX_A35_CLK>;
	operating-points-v2 = <&a35_opp_table>;
	#cooling-cells = <2>;
	};

	A35_L2: l2-cache0 {
	compatible = "cache";
	};
	};

	a35_opp_table: opp-table {
	compatible = "operating-points-v2";
	opp-shared;

	opp-900000000 {
	opp-hz = /bits/ 64 <900000000>;
	opp-microvolt = <1000000>;
	clock-latency-ns = <150000>;
	};

	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	opp-microvolt = <1100000>;
	clock-latency-ns = <150000>;
	opp-suspend;
	};
	};

	gic: interrupt-controller@51a00000 {
	compatible = "arm,gic-v3";
	reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
	<0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
	#interrupt-cells = <3>;
	interrupt-controller;
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	dsp_reserved: dsp@92400000 {
	reg = <0 0x92400000 0 0x2000000>;
	no-map;
	};
	};

	pmu {
	compatible = "arm,armv8-pmuv3";
	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	scu {
	compatible = "fsl,imx-scu";
	mbox-names = "tx0", "tx1", "tx2", "tx3",
	"rx0", "rx1", "rx2", "rx3",
	"gip3";
	mboxes = <&lsio_mu1 0 0
	&lsio_mu1 0 1
	&lsio_mu1 0 2
	&lsio_mu1 0 3
	&lsio_mu1 1 0
	&lsio_mu1 1 1
	&lsio_mu1 1 2
	&lsio_mu1 1 3
	&lsio_mu1 3 3>;

	clk: clock-controller {
	compatible = "fsl,imx8qxp-clk";
	#clock-cells = <1>;
	clocks = <&xtal32k &xtal24m>;
	clock-names = "xtal_32KHz", "xtal_24Mhz";
	};

	iomuxc: pinctrl {
	compatible = "fsl,imx8qxp-iomuxc";
	};

	ocotp: imx8qx-ocotp {
	compatible = "fsl,imx8qxp-scu-ocotp";
	#address-cells = <1>;
	#size-cells = <1>;
	};

	pd: imx8qx-pd {
	compatible = "fsl,imx8qxp-scu-pd";
	#power-domain-cells = <1>;
	};

	scu_key: scu-key {
	compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
	linux,keycodes = <KEY_POWER>;
	status = "disabled";
	};

	rtc: rtc {
	compatible = "fsl,imx8qxp-sc-rtc";
	};

	watchdog {
	compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
	timeout-sec = <60>;
	};
	+
	+ tsens: thermal-sensor {
	+ compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
	+ #thermal-sensor-cells = <1>;
	+ };
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
	};

	xtal32k: clock-xtal32k {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "xtal_32KHz";
	};

	xtal24m: clock-xtal24m {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "xtal_24MHz";
	};

	adma_subsys: bus@59000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x59000000 0x0 0x59000000 0x2000000>;

	adma_lpcg: clock-controller@59000000 {
	compatible = "fsl,imx8qxp-lpcg-adma";
	reg = <0x59000000 0x2000000>;
	#clock-cells = <1>;
	};

	adma_dsp: dsp@596e8000 {
	compatible = "fsl,imx8qxp-dsp";
	reg = <0x596e8000 0x88000>;
	clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
	<&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
	<&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
	clock-names = "ipg", "ocram", "core";
	power-domains = <&pd IMX_SC_R_MU_13A>,
	<&pd IMX_SC_R_MU_13B>,
	<&pd IMX_SC_R_DSP>,
	<&pd IMX_SC_R_DSP_RAM>;
	mbox-names = "txdb0", "txdb1",
	"rxdb0", "rxdb1";
	mboxes = <&lsio_mu13 2 0>,
	<&lsio_mu13 2 1>,
	<&lsio_mu13 3 0>,
	<&lsio_mu13 3 1>;
	memory-region = <&dsp_reserved>;
	status = "disabled";
	};

	adma_lpuart0: serial@5a060000 {
	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
	reg = <0x5a060000 0x1000>;
	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>,
	<&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
	clock-names = "ipg", "baud";
	power-domains = <&pd IMX_SC_R_UART_0>;
	status = "disabled";
	};

	adma_lpuart1: serial@5a070000 {
	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
	reg = <0x5a070000 0x1000>;
	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>,
	<&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
	clock-names = "ipg", "baud";
	power-domains = <&pd IMX_SC_R_UART_1>;
	status = "disabled";
	};

	adma_lpuart2: serial@5a080000 {
	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
	reg = <0x5a080000 0x1000>;
	interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>,
	<&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
	clock-names = "ipg", "baud";
	power-domains = <&pd IMX_SC_R_UART_2>;
	status = "disabled";
	};

	adma_lpuart3: serial@5a090000 {
	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
	reg = <0x5a090000 0x1000>;
	interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>,
	<&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
	clock-names = "ipg", "baud";
	power-domains = <&pd IMX_SC_R_UART_3>;
	status = "disabled";
	};

	adma_i2c0: i2c@5a800000 {
	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
	reg = <0x5a800000 0x4000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
	clock-names = "per";
	assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
	assigned-clock-rates = <24000000>;
	power-domains = <&pd IMX_SC_R_I2C_0>;
	status = "disabled";
	};

	adma_i2c1: i2c@5a810000 {
	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
	reg = <0x5a810000 0x4000>;
	interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
	clock-names = "per";
	assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
	assigned-clock-rates = <24000000>;
	power-domains = <&pd IMX_SC_R_I2C_1>;
	status = "disabled";
	};

	adma_i2c2: i2c@5a820000 {
	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
	reg = <0x5a820000 0x4000>;
	interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
	clock-names = "per";
	assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
	assigned-clock-rates = <24000000>;
	power-domains = <&pd IMX_SC_R_I2C_2>;
	status = "disabled";
	};

	adma_i2c3: i2c@5a830000 {
	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
	reg = <0x5a830000 0x4000>;
	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
	clock-names = "per";
	assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
	assigned-clock-rates = <24000000>;
	power-domains = <&pd IMX_SC_R_I2C_3>;
	status = "disabled";
	};
	};

	conn_subsys: bus@5b000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;

	conn_lpcg: clock-controller@5b200000 {
	compatible = "fsl,imx8qxp-lpcg-conn";
	reg = <0x5b200000 0xb0000>;
	#clock-cells = <1>;
	};

	usdhc1: mmc@5b010000 {
	compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
	interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x5b010000 0x10000>;
	clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
	<&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
	<&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
	clock-names = "ipg", "per", "ahb";
	power-domains = <&pd IMX_SC_R_SDHC_0>;
	status = "disabled";
	};

	usdhc2: mmc@5b020000 {
	compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
	interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x5b020000 0x10000>;
	clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
	<&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
	<&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
	clock-names = "ipg", "per", "ahb";
	power-domains = <&pd IMX_SC_R_SDHC_1>;
	fsl,tuning-start-tap = <20>;
	fsl,tuning-step= <2>;
	status = "disabled";
	};

	usdhc3: mmc@5b030000 {
	compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
	interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x5b030000 0x10000>;
	clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
	<&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
	<&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
	clock-names = "ipg", "per", "ahb";
	power-domains = <&pd IMX_SC_R_SDHC_2>;
	status = "disabled";
	};

	fec1: ethernet@5b040000 {
	compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
	reg = <0x5b040000 0x10000>;
	interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
	<&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
	<&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
	<&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
	clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
	fsl,num-tx-queues=<3>;
	fsl,num-rx-queues=<3>;
	power-domains = <&pd IMX_SC_R_ENET_0>;
	status = "disabled";
	};

	fec2: ethernet@5b050000 {
	compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
	reg = <0x5b050000 0x10000>;
	interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
	<&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
	<&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
	<&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
	clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
	fsl,num-tx-queues=<3>;
	fsl,num-rx-queues=<3>;
	power-domains = <&pd IMX_SC_R_ENET_1>;
	status = "disabled";
	};
	};

	ddr_subsyss: bus@5c000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;

	ddr-pmu@5c020000 {
	compatible = "fsl,imx8-ddr-pmu";
	reg = <0x5c020000 0x10000>;
	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	lsio_subsys: bus@5d000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;

	lsio_gpio0: gpio@5d080000 {
	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
	reg = <0x5d080000 0x10000>;
	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	power-domains = <&pd IMX_SC_R_GPIO_0>;
	};

	lsio_gpio1: gpio@5d090000 {
	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
	reg = <0x5d090000 0x10000>;
	interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	power-domains = <&pd IMX_SC_R_GPIO_1>;
	};

	lsio_gpio2: gpio@5d0a0000 {
	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
	reg = <0x5d0a0000 0x10000>;
	interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	power-domains = <&pd IMX_SC_R_GPIO_2>;
	};

	lsio_gpio3: gpio@5d0b0000 {
	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
	reg = <0x5d0b0000 0x10000>;
	interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	power-domains = <&pd IMX_SC_R_GPIO_3>;
	};

	lsio_gpio4: gpio@5d0c0000 {
	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
	reg = <0x5d0c0000 0x10000>;
	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	power-domains = <&pd IMX_SC_R_GPIO_4>;
	};

	lsio_gpio5: gpio@5d0d0000 {
	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
	reg = <0x5d0d0000 0x10000>;
	interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	power-domains = <&pd IMX_SC_R_GPIO_5>;
	};

	lsio_gpio6: gpio@5d0e0000 {
	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
	reg = <0x5d0e0000 0x10000>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	power-domains = <&pd IMX_SC_R_GPIO_6>;
	};

	lsio_gpio7: gpio@5d0f0000 {
	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
	reg = <0x5d0f0000 0x10000>;
	interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	power-domains = <&pd IMX_SC_R_GPIO_7>;
	};

	lsio_mu0: mailbox@5d1b0000 {
	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
	reg = <0x5d1b0000 0x10000>;
	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	#mbox-cells = <2>;
	status = "disabled";
	};

	lsio_mu1: mailbox@5d1c0000 {
	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
	reg = <0x5d1c0000 0x10000>;
	interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
	#mbox-cells = <2>;
	};

	lsio_mu2: mailbox@5d1d0000 {
	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
	reg = <0x5d1d0000 0x10000>;
	interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
	#mbox-cells = <2>;
	status = "disabled";
	};

	lsio_mu3: mailbox@5d1e0000 {
	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
	reg = <0x5d1e0000 0x10000>;
	interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
	#mbox-cells = <2>;
	status = "disabled";
	};

	lsio_mu4: mailbox@5d1f0000 {
	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
	reg = <0x5d1f0000 0x10000>;
	interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
	#mbox-cells = <2>;
	status = "disabled";
	};

	lsio_mu13: mailbox@5d280000 {
	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
	reg = <0x5d280000 0x10000>;
	interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
	#mbox-cells = <2>;
	power-domains = <&pd IMX_SC_R_MU_13A>;
	};

	lsio_lpcg: clock-controller@5d400000 {
	compatible = "fsl,imx8qxp-lpcg-lsio";
	reg = <0x5d400000 0x400000>;
	#clock-cells = <1>;
	};
	};
	+
	+ thermal_zones: thermal-zones {
	+ cpu-thermal0 {
	+ polling-delay-passive = <250>;
	+ polling-delay = <2000>;
	+ thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
	+
	+ trips {
	+ cpu_alert0: trip0 {
	+ temperature = <107000>;
	+ hysteresis = <2000>;
	+ type = "passive";
	+ };
	+
	+ cpu_crit0: trip1 {
	+ temperature = <127000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	+ };
	+
	+ cooling-maps {
	+ map0 {
	+ trip = <&cpu_alert0>;
	+ cooling-device =
	+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	+ };
	+ };
	+ };
	+ };
	};
	diff --git a/sys/gnu/dts/arm64/freescale/s32v234.dtsi b/sys/gnu/dts/arm64/freescale/s32v234.dtsi
	index e746b9c48f7a..ba0b5305d481 100644
	--- a/sys/gnu/dts/arm64/freescale/s32v234.dtsi
	+++ b/sys/gnu/dts/arm64/freescale/s32v234.dtsi
	@@ -1,139 +1,139 @@
	// SPDX-License-Identifier: GPL-2.0-or-later
	/*
	* Copyright 2015-2016 Freescale Semiconductor, Inc.
	* Copyright 2016-2018 NXP
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>

	/memreserve/ 0x80000000 0x00010000;

	/ {
	compatible = "fsl,s32v234";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	serial0 = &uart0;
	serial1 = &uart1;
	};

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x0>;
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x80000000>;
	next-level-cache = <&cluster0_l2_cache>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x1>;
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x80000000>;
	next-level-cache = <&cluster0_l2_cache>;
	};

	cpu2: cpu@100 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x100>;
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x80000000>;
	next-level-cache = <&cluster1_l2_cache>;
	};

	cpu3: cpu@101 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x101>;
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x80000000>;
	next-level-cache = <&cluster1_l2_cache>;
	};

	cluster0_l2_cache: l2-cache0 {
	compatible = "cache";
	};

	cluster1_l2_cache: l2-cache1 {
	compatible = "cache";
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \|
	IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \|
	IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \|
	IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \|
	IRQ_TYPE_LEVEL_LOW)>;
	/* clock-frequency might be modified by u-boot, depending on the
	* chip version.
	*/
	clock-frequency = <10000000>;
	};

	gic: interrupt-controller@7d001000 {
	compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0 0x7d001000 0 0x1000>,
	<0 0x7d002000 0 0x2000>,
	<0 0x7d004000 0 0x2000>,
	<0 0x7d006000 0 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \|
	IRQ_TYPE_LEVEL_HIGH)>;
	};

	soc {
	#address-cells = <2>;
	#size-cells = <2>;
	compatible = "simple-bus";
	interrupt-parent = <&gic>;
	ranges;

	- aips0: aips-bus@40000000 {
	+ aips0: bus@40000000 {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;
	reg = <0x0 0x40000000 0x0 0x7d000>;
	ranges;

	uart0: serial@40053000 {
	compatible = "fsl,s32v234-linflexuart";
	reg = <0x0 0x40053000 0x0 0x1000>;
	interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
	status = "disabled";
	};
	};

	- aips1: aips-bus@40080000 {
	+ aips1: bus@40080000 {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;
	reg = <0x0 0x40080000 0x0 0x70000>;
	ranges;

	uart1: serial@400bc000 {
	compatible = "fsl,s32v234-linflexuart";
	reg = <0x0 0x400bc000 0x0 0x1000>;
	interrupts = <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
	status = "disabled";
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/intel/socfpga_agilex_socdk.dts b/sys/gnu/dts/arm64/intel/socfpga_agilex_socdk.dts
	index e794a12ba7c5..51d948323bfd 100644
	--- a/sys/gnu/dts/arm64/intel/socfpga_agilex_socdk.dts
	+++ b/sys/gnu/dts/arm64/intel/socfpga_agilex_socdk.dts
	@@ -1,133 +1,133 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Copyright (C) 2019, Intel Corporation
	*/
	#include "socfpga_agilex.dtsi"

	/ {
	model = "SoCFPGA Agilex SoCDK";

	aliases {
	serial0 = &uart0;
	ethernet0 = &gmac0;
	ethernet1 = &gmac1;
	ethernet2 = &gmac2;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	leds {
	compatible = "gpio-leds";
	hps0 {
	label = "hps_led0";
	gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
	};

	hps1 {
	label = "hps_led1";
	gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
	};

	hps2 {
	label = "hps_led2";
	gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
	};
	};

	memory {
	device_type = "memory";
	/* We expect the bootloader to fill in the reg */
	reg = <0 0 0 0>;
	};
	};

	&gpio1 {
	status = "okay";
	};

	&gmac0 {
	status = "okay";
	phy-mode = "rgmii";
	phy-handle = <&phy0>;

	max-frame-size = <9000>;

	mdio0 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,dwmac-mdio";
	phy0: ethernet-phy@0 {
	reg = <4>;

	txd0-skew-ps = <0>; /* -420ps */
	txd1-skew-ps = <0>; /* -420ps */
	txd2-skew-ps = <0>; /* -420ps */
	txd3-skew-ps = <0>; /* -420ps */
	rxd0-skew-ps = <420>; /* 0ps */
	rxd1-skew-ps = <420>; /* 0ps */
	rxd2-skew-ps = <420>; /* 0ps */
	rxd3-skew-ps = <420>; /* 0ps */
	txen-skew-ps = <0>; /* -420ps */
	txc-skew-ps = <900>; /* 0ps */
	rxdv-skew-ps = <420>; /* 0ps */
	rxc-skew-ps = <1680>; /* 780ps */
	};
	};
	};

	&mmc {
	status = "okay";
	cap-sd-highspeed;
	broken-cd;
	bus-width = <4>;
	};

	&uart0 {
	status = "okay";
	};

	&usb0 {
	status = "okay";
	disable-over-current;
	};

	&watchdog0 {
	status = "okay";
	};

	&qspi {
	flash@0 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "mt25qu02g";
	reg = <0>;
	spi-max-frequency = <100000000>;

	m25p,fast-read;
	cdns,page-size = <256>;
	cdns,block-size = <16>;
	cdns,read-delay = <1>;
	cdns,tshsl-ns = <50>;
	cdns,tsd2d-ns = <50>;
	cdns,tchsh-ns = <4>;
	cdns,tslch-ns = <4>;

	partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	qspi_boot: partition@0 {
	label = "Boot and fpga data";
	- reg = <0x0 0x034B0000>;
	+ reg = <0x0 0x03FE0000>;
	};

	- qspi_rootfs: partition@34B0000 {
	+ qspi_rootfs: partition@3FE0000 {
	label = "Root Filesystem - JFFS2";
	- reg = <0x034B0000 0x0EB50000>;
	+ reg = <0x03FE0000 0x0C020000>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-emmc.dts b/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-emmc.dts
	index bd9ed9dc9c3e..ec72a11ed80f 100644
	--- a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-emmc.dts
	+++ b/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-emmc.dts
	@@ -1,42 +1,44 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Device Tree file for Globalscale Marvell ESPRESSOBin Board with eMMC
	* Copyright (C) 2018 Marvell
	*
	* Romain Perier <romain.perier@free-electrons.com>
	* Konstantin Porotchkin <kostap@marvell.com>
	*
	*/
	/*
	* Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
	*/

	+/dts-v1/;
	+
	#include "armada-3720-espressobin.dtsi"

	/ {
	model = "Globalscale Marvell ESPRESSOBin Board (eMMC)";
	compatible = "globalscale,espressobin-emmc", "globalscale,espressobin",
	"marvell,armada3720", "marvell,armada3710";
	};

	/* U11 */
	&sdhci0 {
	non-removable;
	bus-width = <8>;
	mmc-ddr-1_8v;
	mmc-hs400-1_8v;
	marvell,xenon-emmc;
	marvell,xenon-tun-count = <9>;
	marvell,pad-type = "fixed-1-8v";

	pinctrl-names = "default";
	pinctrl-0 = <&mmc_pins>;
	status = "okay";

	#address-cells = <1>;
	#size-cells = <0>;
	mmccard: mmccard@0 {
	compatible = "mmc-card";
	reg = <0>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-v7-emmc.dts b/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-v7-emmc.dts
	index 6e876a6d9532..03733fd92732 100644
	--- a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-v7-emmc.dts
	+++ b/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-v7-emmc.dts
	@@ -1,59 +1,61 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Device Tree file for Globalscale Marvell ESPRESSOBin Board V7 with eMMC
	* Copyright (C) 2018 Marvell
	*
	* Romain Perier <romain.perier@free-electrons.com>
	* Konstantin Porotchkin <kostap@marvell.com>
	*
	*/
	/*
	* Schematic available at http://wiki.espressobin.net/tiki-download_file.php?fileId=200
	*/

	+/dts-v1/;
	+
	#include "armada-3720-espressobin.dtsi"

	/ {
	model = "Globalscale Marvell ESPRESSOBin Board V7 (eMMC)";
	compatible = "globalscale,espressobin-v7-emmc", "globalscale,espressobin-v7",
	"globalscale,espressobin", "marvell,armada3720",
	"marvell,armada3710";
	};

	&switch0 {
	ports {
	port@1 {
	reg = <1>;
	label = "lan1";
	phy-handle = <&switch0phy0>;
	};

	port@3 {
	reg = <3>;
	label = "wan";
	phy-handle = <&switch0phy2>;
	};
	};
	};

	/* U11 */
	&sdhci0 {
	non-removable;
	bus-width = <8>;
	mmc-ddr-1_8v;
	mmc-hs400-1_8v;
	marvell,xenon-emmc;
	marvell,xenon-tun-count = <9>;
	marvell,pad-type = "fixed-1-8v";

	pinctrl-names = "default";
	pinctrl-0 = <&mmc_pins>;
	status = "okay";

	#address-cells = <1>;
	#size-cells = <0>;
	mmccard: mmccard@0 {
	compatible = "mmc-card";
	reg = <0>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-v7.dts b/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-v7.dts
	index 0f8405d085fd..8570c5f47d7d 100644
	--- a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-v7.dts
	+++ b/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-v7.dts
	@@ -1,36 +1,38 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Device Tree file for Globalscale Marvell ESPRESSOBin Board V7
	* Copyright (C) 2018 Marvell
	*
	* Romain Perier <romain.perier@free-electrons.com>
	* Konstantin Porotchkin <kostap@marvell.com>
	*
	*/
	/*
	* Schematic available at http://wiki.espressobin.net/tiki-download_file.php?fileId=200
	*/

	+/dts-v1/;
	+
	#include "armada-3720-espressobin.dtsi"

	/ {
	model = "Globalscale Marvell ESPRESSOBin Board V7";
	compatible = "globalscale,espressobin-v7", "globalscale,espressobin",
	"marvell,armada3720", "marvell,armada3710";
	};

	&switch0 {
	ports {
	port@1 {
	reg = <1>;
	label = "lan1";
	phy-handle = <&switch0phy0>;
	};

	port@3 {
	reg = <3>;
	label = "wan";
	phy-handle = <&switch0phy2>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin.dtsi b/sys/gnu/dts/arm64/marvell/armada-3720-espressobin.dtsi
	index 53b8ac55a7f3..42e992f9c8a5 100644
	--- a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin.dtsi
	+++ b/sys/gnu/dts/arm64/marvell/armada-3720-espressobin.dtsi
	@@ -1,177 +1,181 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Device Tree file for Globalscale Marvell ESPRESSOBin Board
	* Copyright (C) 2016 Marvell
	*
	* Romain Perier <romain.perier@free-electrons.com>
	*
	*/

	-/dts-v1/;
	-
	#include <dt-bindings/gpio/gpio.h>
	#include "armada-372x.dtsi"

	/ {
	+ aliases {
	+ ethernet0 = &eth0;
	+ serial0 = &uart0;
	+ serial1 = &uart1;
	+ };
	+
	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@0 {
	device_type = "memory";
	reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
	};

	vcc_sd_reg1: regulator {
	compatible = "regulator-gpio";
	regulator-name = "vcc_sd1";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;

	gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
	gpios-states = <0>;
	states = <1800000 0x1
	3300000 0x0>;
	enable-active-high;
	};
	};

	/* J9 */
	&pcie0 {
	status = "okay";
	phys = <&comphy1 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
	};

	/* J6 */
	&sata {
	status = "okay";
	phys = <&comphy2 0>;
	phy-names = "sata-phy";
	};

	/* J1 */
	&sdhci1 {
	wp-inverted;
	bus-width = <4>;
	cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
	marvell,pad-type = "sd";
	vqmmc-supply = <&vcc_sd_reg1>;

	pinctrl-names = "default";
	pinctrl-0 = <&sdio_pins>;
	status = "okay";
	};

	&spi0 {
	status = "okay";

	flash@0 {
	reg = <0>;
	compatible = "jedec,spi-nor";
	spi-max-frequency = <104000000>;
	m25p,fast-read;
	};
	};

	/* Exported on the micro USB connector J5 through an FTDI */
	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
	status = "okay";
	};

	/*
	* Connector J17 and J18 expose a number of different features. Some pins are
	* multiplexed. This is the case for instance for the following features:
	* - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
	* how to enable it. Beware that the signals are 1.8V TTL.
	* - I2C
	* - SPI
	* - MMC
	*/

	/* J7 */
	&usb3 {
	status = "okay";
	};

	/* J8 */
	&usb2 {
	status = "okay";
	};

	&mdio {
	switch0: switch0@1 {
	compatible = "marvell,mv88e6085";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	dsa,member = <0 0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	label = "cpu";
	ethernet = <&eth0>;
	phy-mode = "rgmii-id";
	fixed-link {
	speed = <1000>;
	full-duplex;
	};
	};

	port@1 {
	reg = <1>;
	label = "wan";
	phy-handle = <&switch0phy0>;
	};

	port@2 {
	reg = <2>;
	label = "lan0";
	phy-handle = <&switch0phy1>;
	};

	port@3 {
	reg = <3>;
	label = "lan1";
	phy-handle = <&switch0phy2>;
	};

	};

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	switch0phy0: switch0phy0@11 {
	reg = <0x11>;
	};
	switch0phy1: switch0phy1@12 {
	reg = <0x12>;
	};
	switch0phy2: switch0phy2@13 {
	reg = <0x13>;
	};
	};
	};
	};

	&eth0 {
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
	phy-mode = "rgmii-id";
	status = "okay";

	fixed-link {
	speed = <1000>;
	full-duplex;
	};
	};
	diff --git a/sys/gnu/dts/arm64/marvell/armada-8040-clearfog-gt-8k.dts b/sys/gnu/dts/arm64/marvell/armada-8040-clearfog-gt-8k.dts
	index a211a046b2f2..b90d78a5724b 100644
	--- a/sys/gnu/dts/arm64/marvell/armada-8040-clearfog-gt-8k.dts
	+++ b/sys/gnu/dts/arm64/marvell/armada-8040-clearfog-gt-8k.dts
	@@ -1,485 +1,486 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (C) 2018 SolidRun ltd.
	* Based on Marvell MACCHIATOBin board
	*
	* Device Tree file for SolidRun's ClearFog GT 8K
	*/

	#include "armada-8040.dtsi"

	#include <dt-bindings/input/input.h>
	#include <dt-bindings/gpio/gpio.h>

	/ {
	model = "SolidRun ClearFog GT 8K";
	compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
	"marvell,armada-ap806-quad", "marvell,armada-ap806";

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@00000000 {
	device_type = "memory";
	reg = <0x0 0x0 0x0 0x80000000>;
	};

	aliases {
	ethernet0 = &cp1_eth1;
	ethernet1 = &cp0_eth0;
	ethernet2 = &cp1_eth2;
	};

	v_3_3: regulator-3-3v {
	compatible = "regulator-fixed";
	regulator-name = "v_3_3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	status = "okay";
	};

	v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
	compatible = "regulator-fixed";
	gpio = <&cp0_gpio2 15 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_xhci_vbus_pins>;
	regulator-name = "v_5v0_usb3_hst_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	status = "okay";
	};

	sfp_cp0_eth0: sfp-cp0-eth0 {
	compatible = "sff,sfp";
	i2c-bus = <&cp0_i2c1>;
	mod-def0-gpio = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>;
	tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_sfp_present_pins &cp1_sfp_tx_disable_pins>;
	maximum-power-milliwatt = <2000>;
	};

	leds {
	compatible = "gpio-leds";
	pinctrl-0 = <&cp0_led0_pins
	&cp0_led1_pins>;
	pinctrl-names = "default";
	/* No designated function for these LEDs at the moment */
	led0 {
	label = "clearfog-gt-8k:green:led0";
	gpios = <&cp0_gpio2 8 GPIO_ACTIVE_LOW>;
	default-state = "on";
	};
	led1 {
	label = "clearfog-gt-8k:green:led1";
	gpios = <&cp0_gpio2 9 GPIO_ACTIVE_LOW>;
	default-state = "on";
	};
	};

	keys {
	compatible = "gpio-keys";
	pinctrl-0 = <&cp0_gpio_reset_pins &cp1_wps_button_pins>;
	pinctrl-names = "default";

	button_0 {
	/* The rear button */
	label = "Rear Button";
	gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>;
	linux,can-disable;
	linux,code = <BTN_0>;
	};

	button_1 {
	/* The wps button */
	label = "WPS Button";
	gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>;
	linux,can-disable;
	linux,code = <KEY_WPS_BUTTON>;
	};
	};
	};

	&uart0 {
	status = "okay";
	pinctrl-0 = <&uart0_pins>;
	pinctrl-names = "default";
	};

	&ap_sdhci0 {
	bus-width = <8>;
	no-1-8-v;
	no-sd;
	no-sdio;
	non-removable;
	status = "okay";
	vqmmc-supply = <&v_3_3>;
	};

	&cp0_i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c0_pins>;
	status = "okay";
	};

	&cp0_i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c1_pins>;
	status = "okay";
	};

	&cp0_pinctrl {
	/*
	* MPP Bus:
	* [0-31] = 0xff: Keep default CP0_shared_pins:
	* [11] CLKOUT_MPP_11 (out)
	* [23] LINK_RD_IN_CP2CP (in)
	* [25] CLKOUT_MPP_25 (out)
	* [29] AVS_FB_IN_CP2CP (in)
	* [32, 33, 34] pci0/1/2 reset
	* [35-38] CP0 I2C1 and I2C0
	* [39] GPIO reset button
	* [40,41] LED0 and LED1
	* [43] 1512 phy reset
	* [47] USB VBUS EN (active low)
	* [48] FAN PWM
	* [49] SFP+ present signal
	* [50] TPM interrupt
	* [51] WLAN0 disable
	* [52] WLAN1 disable
	* [53] LTE disable
	* [54] NFC reset
	* [55] Micro SD card detect
	* [56-61] Micro SD
	*/

	cp0_pci0_reset_pins: pci0-reset-pins {
	marvell,pins = "mpp32";
	marvell,function = "gpio";
	};

	cp0_pci1_reset_pins: pci1-reset-pins {
	marvell,pins = "mpp33";
	marvell,function = "gpio";
	};

	cp0_pci2_reset_pins: pci2-reset-pins {
	marvell,pins = "mpp34";
	marvell,function = "gpio";
	};

	cp0_i2c1_pins: i2c1-pins {
	marvell,pins = "mpp35", "mpp36";
	marvell,function = "i2c1";
	};

	cp0_i2c0_pins: i2c0-pins {
	marvell,pins = "mpp37", "mpp38";
	marvell,function = "i2c0";
	};

	cp0_gpio_reset_pins: gpio-reset-pins {
	marvell,pins = "mpp39";
	marvell,function = "gpio";
	};

	cp0_led0_pins: led0-pins {
	marvell,pins = "mpp40";
	marvell,function = "gpio";
	};

	cp0_led1_pins: led1-pins {
	marvell,pins = "mpp41";
	marvell,function = "gpio";
	};

	cp0_copper_eth_phy_reset: copper-eth-phy-reset {
	marvell,pins = "mpp43";
	marvell,function = "gpio";
	};

	cp0_xhci_vbus_pins: xhci0-vbus-pins {
	marvell,pins = "mpp47";
	marvell,function = "gpio";
	};

	cp0_fan_pwm_pins: fan-pwm-pins {
	marvell,pins = "mpp48";
	marvell,function = "gpio";
	};

	cp0_sfp_present_pins: sfp-present-pins {
	marvell,pins = "mpp49";
	marvell,function = "gpio";
	};

	cp0_tpm_irq_pins: tpm-irq-pins {
	marvell,pins = "mpp50";
	marvell,function = "gpio";
	};

	cp0_wlan_disable_pins: wlan-disable-pins {
	marvell,pins = "mpp51";
	marvell,function = "gpio";
	};

	cp0_sdhci_pins: sdhci-pins {
	marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
	"mpp60", "mpp61";
	marvell,function = "sdio";
	};
	};

	&cp0_pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_pci0_reset_pins &cp0_wlan_disable_pins>;
	reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
	phys = <&cp0_comphy0 0>;
	phy-names = "cp0-pcie0-x1-phy";
	status = "okay";
	};

	&cp0_gpio2 {
	sata_reset {
	gpio-hog;
	gpios = <1 GPIO_ACTIVE_HIGH>;
	output-high;
	};

	lte_reset {
	gpio-hog;
	gpios = <2 GPIO_ACTIVE_LOW>;
	output-low;
	};

	wlan_disable {
	gpio-hog;
	gpios = <19 GPIO_ACTIVE_LOW>;
	output-low;
	};

	lte_disable {
	gpio-hog;
	gpios = <21 GPIO_ACTIVE_LOW>;
	output-low;
	};
	};

	&cp0_ethernet {
	status = "okay";
	};

	/* SFP */
	&cp0_eth0 {
	status = "okay";
	phy-mode = "10gbase-kr";
	managed = "in-band-status";
	phys = <&cp0_comphy2 0>;
	sfp = <&sfp_cp0_eth0>;
	};

	&cp0_sdhci0 {
	broken-cd;
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_sdhci_pins>;
	status = "okay";
	vqmmc-supply = <&v_3_3>;
	};

	&cp0_usb3_1 {
	status = "okay";
	};

	&cp1_pinctrl {
	/*
	* MPP Bus:
	* [0-5] TDM
	* [6] VHV Enable
	* [7] CP1 SPI0 CSn1 (FXS)
	* [8] CP1 SPI0 CSn0 (TPM)
	* [9.11]CP1 SPI0 MOSI/MISO/CLK
	* [13] CP1 SPI1 MISO (TDM and SPI ROM shared)
	* [14] CP1 SPI1 CS0n (64Mb SPI ROM)
	* [15] CP1 SPI1 MOSI (TDM and SPI ROM shared)
	* [16] CP1 SPI1 CLK (TDM and SPI ROM shared)
	* [24] Topaz switch reset
	* [26] Buzzer
	* [27] CP1 SMI MDIO
	* [28] CP1 SMI MDC
	* [29] CP0 10G SFP TX Disable
	* [30] WPS button
	* [31] Front panel button
	*/

	cp1_spi1_pins: spi1-pins {
	marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
	marvell,function = "spi1";
	};

	cp1_switch_reset_pins: switch-reset-pins {
	marvell,pins = "mpp24";
	marvell,function = "gpio";
	};

	cp1_ge_mdio_pins: ge-mdio-pins {
	marvell,pins = "mpp27", "mpp28";
	marvell,function = "ge";
	};

	cp1_sfp_tx_disable_pins: sfp-tx-disable-pins {
	marvell,pins = "mpp29";
	marvell,function = "gpio";
	};

	cp1_wps_button_pins: wps-button-pins {
	marvell,pins = "mpp30";
	marvell,function = "gpio";
	};
	};

	&cp1_sata0 {
	pinctrl-0 = <&cp0_pci1_reset_pins>;
	status = "okay";

	sata-port@1 {
	phys = <&cp1_comphy0 1>;
	phy-names = "cp1-sata0-1-phy";
	};
	};

	&cp1_mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_ge_mdio_pins>;
	status = "okay";

	ge_phy: ethernet-phy@0 {
	/* LED0 - GB link
	* LED1 - on: link, blink: activity
	*/
	marvell,reg-init = <3 16 0 0x1017>;
	reg = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_copper_eth_phy_reset>;
	reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
	reset-assert-us = <10000>;
	+ reset-deassert-us = <10000>;
	};

	switch0: switch0@4 {
	compatible = "marvell,mv88e6085";
	reg = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_switch_reset_pins>;
	reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	reg = <1>;
	label = "lan2";
	phy-handle = <&switch0phy0>;
	};

	port@2 {
	reg = <2>;
	label = "lan1";
	phy-handle = <&switch0phy1>;
	};

	port@3 {
	reg = <3>;
	label = "lan4";
	phy-handle = <&switch0phy2>;
	};

	port@4 {
	reg = <4>;
	label = "lan3";
	phy-handle = <&switch0phy3>;
	};

	port@5 {
	reg = <5>;
	label = "cpu";
	ethernet = <&cp1_eth2>;
	phy-mode = "2500base-x";
	managed = "in-band-status";
	};
	};

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	switch0phy0: switch0phy0@11 {
	reg = <0x11>;
	};

	switch0phy1: switch0phy1@12 {
	reg = <0x12>;
	};

	switch0phy2: switch0phy2@13 {
	reg = <0x13>;
	};

	switch0phy3: switch0phy3@14 {
	reg = <0x14>;
	};
	};
	};
	};

	&cp1_ethernet {
	status = "okay";
	};

	/* 1G copper */
	&cp1_eth1 {
	status = "okay";
	phy-mode = "sgmii";
	phy = <&ge_phy>;
	phys = <&cp1_comphy3 1>;
	};

	/* Switch uplink */
	&cp1_eth2 {
	status = "okay";
	phy-mode = "2500base-x";
	phys = <&cp1_comphy5 2>;
	fixed-link {
	speed = <2500>;
	full-duplex;
	};
	};

	&cp1_spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_spi1_pins>;
	status = "okay";

	spi-flash@0 {
	compatible = "st,w25q32";
	spi-max-frequency = <50000000>;
	reg = <0>;
	};
	};

	&cp1_comphy2 {
	cp1_usbh0_con: connector {
	compatible = "usb-a-connector";
	phy-supply = <&v_5v0_usb3_hst_vbus>;
	};
	};

	&cp1_usb3_0 {
	phys = <&cp1_comphy2 0>;
	phy-names = "cp1-usb3h0-comphy";
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/marvell/armada-8040-mcbin.dtsi b/sys/gnu/dts/arm64/marvell/armada-8040-mcbin.dtsi
	index 572e2610e0a3..cbcb210cb6d8 100644
	--- a/sys/gnu/dts/arm64/marvell/armada-8040-mcbin.dtsi
	+++ b/sys/gnu/dts/arm64/marvell/armada-8040-mcbin.dtsi
	@@ -1,369 +1,372 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (C) 2016 Marvell Technology Group Ltd.
	*
	* Device Tree file for MACCHIATOBin Armada 8040 community board platform
	*/

	#include "armada-8040.dtsi"

	#include <dt-bindings/gpio/gpio.h>

	/ {
	model = "Marvell 8040 MACCHIATOBin";
	compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
	"marvell,armada-ap806-quad", "marvell,armada-ap806";

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory@0 {
	device_type = "memory";
	reg = <0x0 0x0 0x0 0x80000000>;
	};

	aliases {
	ethernet0 = &cp0_eth0;
	ethernet1 = &cp1_eth0;
	ethernet2 = &cp1_eth1;
	ethernet3 = &cp1_eth2;
	};

	/* Regulator labels correspond with schematics */
	v_3_3: regulator-3-3v {
	compatible = "regulator-fixed";
	regulator-name = "v_3_3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	status = "okay";
	};

	v_vddo_h: regulator-1-8v {
	compatible = "regulator-fixed";
	regulator-name = "v_vddo_h";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	status = "okay";
	};

	v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_xhci_vbus_pins>;
	regulator-name = "v_5v0_usb3_hst_vbus";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	status = "okay";
	};

	sfp_eth0: sfp-eth0 {
	/* CON15,16 - CPM lane 4 */
	compatible = "sff,sfp";
	i2c-bus = <&sfpp0_i2c>;
	los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
	mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
	tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
	tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_sfpp0_pins>;
	+ maximum-power-milliwatt = <2000>;
	};

	sfp_eth1: sfp-eth1 {
	/* CON17,18 - CPS lane 4 */
	compatible = "sff,sfp";
	i2c-bus = <&sfpp1_i2c>;
	los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
	mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
	tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
	tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
	+ maximum-power-milliwatt = <2000>;
	};

	sfp_eth3: sfp-eth3 {
	/* CON13,14 - CPS lane 5 */
	compatible = "sff,sfp";
	i2c-bus = <&sfp_1g_i2c>;
	los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
	mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
	tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
	tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
	+ maximum-power-milliwatt = <2000>;
	};
	};

	&uart0 {
	status = "okay";
	pinctrl-0 = <&uart0_pins>;
	pinctrl-names = "default";
	};

	&ap_sdhci0 {
	bus-width = <8>;
	/*
	* Not stable in HS modes - phy needs "more calibration", so add
	* the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
	*/
	marvell,xenon-phy-slow-mode;
	no-1-8-v;
	no-sd;
	no-sdio;
	non-removable;
	status = "okay";
	vqmmc-supply = <&v_vddo_h>;
	};

	&cp0_i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c0_pins>;
	status = "okay";
	};

	&cp0_i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c1_pins>;
	status = "okay";

	i2c-switch@70 {
	compatible = "nxp,pca9548";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x70>;

	sfpp0_i2c: i2c@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;
	};
	sfpp1_i2c: i2c@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;
	};
	sfp_1g_i2c: i2c@2 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <2>;
	};
	};
	};

	/* J25 UART header */
	&cp0_uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_uart1_pins>;
	status = "okay";
	};

	&cp0_mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_ge_mdio_pins>;
	status = "okay";

	ge_phy: ethernet-phy@0 {
	reg = <0>;
	};
	};

	&cp0_pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_pcie_pins>;
	num-lanes = <4>;
	num-viewport = <8>;
	reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
	ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
	phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
	<&cp0_comphy2 0>, <&cp0_comphy3 0>;
	phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
	"cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy";
	status = "okay";
	};

	&cp0_pinctrl {
	cp0_ge_mdio_pins: ge-mdio-pins {
	marvell,pins = "mpp32", "mpp34";
	marvell,function = "ge";
	};
	cp0_i2c1_pins: i2c1-pins {
	marvell,pins = "mpp35", "mpp36";
	marvell,function = "i2c1";
	};
	cp0_i2c0_pins: i2c0-pins {
	marvell,pins = "mpp37", "mpp38";
	marvell,function = "i2c0";
	};
	cp0_uart1_pins: uart1-pins {
	marvell,pins = "mpp40", "mpp41";
	marvell,function = "uart1";
	};
	cp0_xhci_vbus_pins: xhci0-vbus-pins {
	marvell,pins = "mpp47";
	marvell,function = "gpio";
	};
	cp0_sfp_1g_pins: sfp-1g-pins {
	marvell,pins = "mpp51", "mpp53", "mpp54";
	marvell,function = "gpio";
	};
	cp0_pcie_pins: pcie-pins {
	marvell,pins = "mpp52";
	marvell,function = "gpio";
	};
	cp0_sdhci_pins: sdhci-pins {
	marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
	"mpp60", "mpp61";
	marvell,function = "sdio";
	};
	cp0_sfpp1_pins: sfpp1-pins {
	marvell,pins = "mpp62";
	marvell,function = "gpio";
	};
	};

	&cp0_ethernet {
	status = "okay";
	};

	&cp0_eth0 {
	/* Generic PHY, providing serdes lanes */
	phys = <&cp0_comphy4 0>;
	};

	&cp0_sata0 {
	status = "okay";

	/* CPM Lane 5 - U29 */
	sata-port@1 {
	phys = <&cp0_comphy5 1>;
	phy-names = "cp0-sata0-1-phy";
	};
	};

	&cp0_sdhci0 {
	/* U6 */
	broken-cd;
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_sdhci_pins>;
	status = "okay";
	vqmmc-supply = <&v_3_3>;
	};

	&cp0_usb3_0 {
	/* J38? - USB2.0 only */
	status = "okay";
	};

	&cp0_usb3_1 {
	/* J38? - USB2.0 only */
	status = "okay";
	};

	&cp1_ethernet {
	status = "okay";
	};

	&cp1_eth0 {
	/* Generic PHY, providing serdes lanes */
	phys = <&cp1_comphy4 0>;
	};

	&cp1_eth1 {
	/* CPS Lane 0 - J5 (Gigabit RJ45) */
	status = "okay";
	/* Network PHY */
	phy = <&ge_phy>;
	phy-mode = "sgmii";
	/* Generic PHY, providing serdes lanes */
	phys = <&cp1_comphy0 1>;
	};

	&cp1_eth2 {
	/* CPS Lane 5 */
	status = "okay";
	/* Network PHY */
	phy-mode = "2500base-x";
	managed = "in-band-status";
	/* Generic PHY, providing serdes lanes */
	phys = <&cp1_comphy5 2>;
	sfp = <&sfp_eth3>;
	};

	&cp1_pinctrl {
	cp1_sfpp1_pins: sfpp1-pins {
	marvell,pins = "mpp8", "mpp10", "mpp11";
	marvell,function = "gpio";
	};
	cp1_spi1_pins: spi1-pins {
	marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
	marvell,function = "spi1";
	};
	cp1_uart0_pins: uart0-pins {
	marvell,pins = "mpp6", "mpp7";
	marvell,function = "uart0";
	};
	cp1_sfp_1g_pins: sfp-1g-pins {
	marvell,pins = "mpp24";
	marvell,function = "gpio";
	};
	cp1_sfpp0_pins: sfpp0-pins {
	marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
	marvell,function = "gpio";
	};
	};

	/* J27 UART header */
	&cp1_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_uart0_pins>;
	status = "okay";
	};

	&cp1_sata0 {
	status = "okay";

	/* CPS Lane 1 - U32 */
	sata-port@0 {
	phys = <&cp1_comphy1 0>;
	phy-names = "cp1-sata0-0-phy";
	};

	/* CPS Lane 3 - U31 */
	sata-port@1 {
	phys = <&cp1_comphy3 1>;
	phy-names = "cp1-sata0-1-phy";
	};
	};

	&cp1_spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_spi1_pins>;
	status = "okay";

	spi-flash@0 {
	compatible = "st,w25q32";
	spi-max-frequency = <50000000>;
	reg = <0>;
	};
	};

	&cp1_comphy2 {
	cp1_usbh0_con: connector {
	compatible = "usb-a-connector";
	phy-supply = <&v_5v0_usb3_hst_vbus>;
	};
	};

	&cp1_usb3_0 {
	/* CPS Lane 2 - CON7 */
	phys = <&cp1_comphy2 0>;
	phy-names = "cp1-usb3h0-comphy";
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/marvell/armada-ap806-dual.dtsi b/sys/gnu/dts/arm64/marvell/armada-ap806-dual.dtsi
	index 09849558a776..fcab5173fe67 100644
	--- a/sys/gnu/dts/arm64/marvell/armada-ap806-dual.dtsi
	+++ b/sys/gnu/dts/arm64/marvell/armada-ap806-dual.dtsi
	@@ -1,56 +1,61 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (C) 2016 Marvell Technology Group Ltd.
	*
	* Device Tree file for Marvell Armada AP806.
	*/

	#include "armada-ap806.dtsi"

	/ {
	model = "Marvell Armada AP806 Dual";
	compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	reg = <0x000>;
	enable-method = "psci";
	#cooling-cells = <2>;
	clocks = <&cpu_clk 0>;
	i-cache-size = <0xc000>;
	i-cache-line-size = <64>;
	i-cache-sets = <256>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&l2>;
	};
	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	reg = <0x001>;
	enable-method = "psci";
	#cooling-cells = <2>;
	clocks = <&cpu_clk 0>;
	i-cache-size = <0xc000>;
	i-cache-line-size = <64>;
	i-cache-sets = <256>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&l2>;
	};

	l2: l2-cache {
	compatible = "cache";
	cache-size = <0x80000>;
	cache-line-size = <64>;
	cache-sets = <512>;
	};
	};
	+
	+ thermal-zones {
	+ /delete-node/ ap-thermal-cpu2;
	+ /delete-node/ ap-thermal-cpu3;
	+ };
	};
	diff --git a/sys/gnu/dts/arm64/marvell/armada-ap807-quad.dtsi b/sys/gnu/dts/arm64/marvell/armada-ap807-quad.dtsi
	index 840466e143b4..68782f161f12 100644
	--- a/sys/gnu/dts/arm64/marvell/armada-ap807-quad.dtsi
	+++ b/sys/gnu/dts/arm64/marvell/armada-ap807-quad.dtsi
	@@ -1,93 +1,93 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Device Tree file for Marvell Armada AP807 Quad
	*
	* Copyright (C) 2019 Marvell Technology Group Ltd.
	*/

	#include "armada-ap807.dtsi"

	/ {
	model = "Marvell Armada AP807 Quad";
	compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	- compatible = "arm,cortex-a72", "arm,armv8";
	+ compatible = "arm,cortex-a72";
	reg = <0x000>;
	enable-method = "psci";
	#cooling-cells = <2>;
	clocks = <&cpu_clk 0>;
	i-cache-size = <0xc000>;
	i-cache-line-size = <64>;
	i-cache-sets = <256>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&l2_0>;
	};
	cpu1: cpu@1 {
	device_type = "cpu";
	- compatible = "arm,cortex-a72", "arm,armv8";
	+ compatible = "arm,cortex-a72";
	reg = <0x001>;
	enable-method = "psci";
	#cooling-cells = <2>;
	clocks = <&cpu_clk 0>;
	i-cache-size = <0xc000>;
	i-cache-line-size = <64>;
	i-cache-sets = <256>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&l2_0>;
	};
	cpu2: cpu@100 {
	device_type = "cpu";
	- compatible = "arm,cortex-a72", "arm,armv8";
	+ compatible = "arm,cortex-a72";
	reg = <0x100>;
	enable-method = "psci";
	#cooling-cells = <2>;
	clocks = <&cpu_clk 1>;
	i-cache-size = <0xc000>;
	i-cache-line-size = <64>;
	i-cache-sets = <256>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&l2_1>;
	};
	cpu3: cpu@101 {
	device_type = "cpu";
	- compatible = "arm,cortex-a72", "arm,armv8";
	+ compatible = "arm,cortex-a72";
	reg = <0x101>;
	enable-method = "psci";
	#cooling-cells = <2>;
	clocks = <&cpu_clk 1>;
	i-cache-size = <0xc000>;
	i-cache-line-size = <64>;
	i-cache-sets = <256>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&l2_1>;
	};

	l2_0: l2-cache0 {
	compatible = "cache";
	cache-size = <0x80000>;
	cache-line-size = <64>;
	cache-sets = <512>;
	};

	l2_1: l2-cache1 {
	compatible = "cache";
	cache-size = <0x80000>;
	cache-line-size = <64>;
	cache-sets = <512>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/mediatek/mt2712e.dtsi b/sys/gnu/dts/arm64/mediatek/mt2712e.dtsi
	index 43307bad3f0d..2cd8b33886e5 100644
	--- a/sys/gnu/dts/arm64/mediatek/mt2712e.dtsi
	+++ b/sys/gnu/dts/arm64/mediatek/mt2712e.dtsi
	@@ -1,1003 +1,1009 @@
	/*
	* Copyright (c) 2017 MediaTek Inc.
	* Author: YT Shen <yt.shen@mediatek.com>
	*
	* SPDX-License-Identifier: (GPL-2.0 OR MIT)
	*/

	#include <dt-bindings/clock/mt2712-clk.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/memory/mt2712-larb-port.h>
	#include <dt-bindings/phy/phy.h>
	#include <dt-bindings/power/mt2712-power.h>
	#include "mt2712-pinfunc.h"

	/ {
	compatible = "mediatek,mt2712";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	cluster0_opp: opp_table0 {
	compatible = "operating-points-v2";
	opp-shared;
	opp00 {
	opp-hz = /bits/ 64 <598000000>;
	opp-microvolt = <1000000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <702000000>;
	opp-microvolt = <1000000>;
	};
	opp02 {
	opp-hz = /bits/ 64 <793000000>;
	opp-microvolt = <1000000>;
	};
	};

	cluster1_opp: opp_table1 {
	compatible = "operating-points-v2";
	opp-shared;
	opp00 {
	opp-hz = /bits/ 64 <598000000>;
	opp-microvolt = <1000000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <702000000>;
	opp-microvolt = <1000000>;
	};
	opp02 {
	opp-hz = /bits/ 64 <793000000>;
	opp-microvolt = <1000000>;
	};
	opp03 {
	opp-hz = /bits/ 64 <897000000>;
	opp-microvolt = <1000000>;
	};
	opp04 {
	opp-hz = /bits/ 64 <1001000000>;
	opp-microvolt = <1000000>;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu-map {
	cluster0 {
	core0 {
	cpu = <&cpu0>;
	};
	core1 {
	cpu = <&cpu1>;
	};
	};

	cluster1 {
	core0 {
	cpu = <&cpu2>;
	};
	};
	};

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a35";
	reg = <0x000>;
	clocks = <&mcucfg CLK_MCU_MP0_SEL>,
	<&topckgen CLK_TOP_F_MP0_PLL1>;
	clock-names = "cpu", "intermediate";
	proc-supply = <&cpus_fixed_vproc0>;
	operating-points-v2 = <&cluster0_opp>;
	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a35";
	reg = <0x001>;
	enable-method = "psci";
	clocks = <&mcucfg CLK_MCU_MP0_SEL>,
	<&topckgen CLK_TOP_F_MP0_PLL1>;
	clock-names = "cpu", "intermediate";
	proc-supply = <&cpus_fixed_vproc0>;
	operating-points-v2 = <&cluster0_opp>;
	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
	};

	cpu2: cpu@200 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	reg = <0x200>;
	enable-method = "psci";
	clocks = <&mcucfg CLK_MCU_MP2_SEL>,
	<&topckgen CLK_TOP_F_BIG_PLL1>;
	clock-names = "cpu", "intermediate";
	proc-supply = <&cpus_fixed_vproc1>;
	operating-points-v2 = <&cluster1_opp>;
	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
	};

	idle-states {
	entry-method = "psci";

	CPU_SLEEP_0: cpu-sleep-0 {
	compatible = "arm,idle-state";
	local-timer-stop;
	entry-latency-us = <100>;
	exit-latency-us = <80>;
	min-residency-us = <2000>;
	arm,psci-suspend-param = <0x0010000>;
	};

	CLUSTER_SLEEP_0: cluster-sleep-0 {
	compatible = "arm,idle-state";
	local-timer-stop;
	entry-latency-us = <350>;
	exit-latency-us = <80>;
	min-residency-us = <3000>;
	arm,psci-suspend-param = <0x1010000>;
	};
	};
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	baud_clk: dummy26m {
	compatible = "fixed-clock";
	clock-frequency = <26000000>;
	#clock-cells = <0>;
	};

	sys_clk: dummyclk {
	compatible = "fixed-clock";
	clock-frequency = <26000000>;
	#clock-cells = <0>;
	};

	clk26m: oscillator@0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <26000000>;
	clock-output-names = "clk26m";
	};

	clk32k: oscillator@1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "clk32k";
	};

	clkfpc: oscillator@2 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <50000000>;
	clock-output-names = "clkfpc";
	};

	clkaud_ext_i_0: oscillator@3 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <6500000>;
	clock-output-names = "clkaud_ext_i_0";
	};

	clkaud_ext_i_1: oscillator@4 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <196608000>;
	clock-output-names = "clkaud_ext_i_1";
	};

	clkaud_ext_i_2: oscillator@5 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <180633600>;
	clock-output-names = "clkaud_ext_i_2";
	};

	clki2si0_mck_i: oscillator@6 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <30000000>;
	clock-output-names = "clki2si0_mck_i";
	};

	clki2si1_mck_i: oscillator@7 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <30000000>;
	clock-output-names = "clki2si1_mck_i";
	};

	clki2si2_mck_i: oscillator@8 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <30000000>;
	clock-output-names = "clki2si2_mck_i";
	};

	clktdmin_mclk_i: oscillator@9 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <30000000>;
	clock-output-names = "clktdmin_mclk_i";
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupt-parent = <&gic>;
	interrupts = <GIC_PPI 13
	(GIC_CPU_MASK_RAW(0x13) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14
	(GIC_CPU_MASK_RAW(0x13) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11
	(GIC_CPU_MASK_RAW(0x13) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10
	(GIC_CPU_MASK_RAW(0x13) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	topckgen: syscon@10000000 {
	compatible = "mediatek,mt2712-topckgen", "syscon";
	reg = <0 0x10000000 0 0x1000>;
	#clock-cells = <1>;
	};

	infracfg: syscon@10001000 {
	compatible = "mediatek,mt2712-infracfg", "syscon";
	reg = <0 0x10001000 0 0x1000>;
	#clock-cells = <1>;
	};

	pericfg: syscon@10003000 {
	compatible = "mediatek,mt2712-pericfg", "syscon";
	reg = <0 0x10003000 0 0x1000>;
	#clock-cells = <1>;
	};

	syscfg_pctl_a: syscfg_pctl_a@10005000 {
	compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
	reg = <0 0x10005000 0 0x1000>;
	};

	pio: pinctrl@10005000 {
	compatible = "mediatek,mt2712-pinctrl";
	reg = <0 0x1000b000 0 0x1000>;
	mediatek,pctl-regmap = <&syscfg_pctl_a>;
	pins-are-numbered;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	};

	- scpsys: scpsys@10006000 {
	+ scpsys: power-controller@10006000 {
	compatible = "mediatek,mt2712-scpsys", "syscon";
	#power-domain-cells = <1>;
	reg = <0 0x10006000 0 0x1000>;
	clocks = <&topckgen CLK_TOP_MM_SEL>,
	<&topckgen CLK_TOP_MFG_SEL>,
	<&topckgen CLK_TOP_VENC_SEL>,
	<&topckgen CLK_TOP_JPGDEC_SEL>,
	<&topckgen CLK_TOP_A1SYS_HP_SEL>,
	<&topckgen CLK_TOP_VDEC_SEL>;
	clock-names = "mm", "mfg", "venc",
	"jpgdec", "audio", "vdec";
	infracfg = <&infracfg>;
	};

	uart5: serial@1000f000 {
	compatible = "mediatek,mt2712-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x1000f000 0 0x400>;
	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&baud_clk>, <&sys_clk>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	+ rtc: rtc@10011000 {
	+ compatible = "mediatek,mt2712-rtc";
	+ reg = <0 0x10011000 0 0x1000>;
	+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>;
	+ };
	+
	spis1: spi@10013000 {
	compatible = "mediatek,mt2712-spi-slave";
	reg = <0 0x10013000 0 0x100>;
	interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_AO_SPI1>;
	clock-names = "spi";
	assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
	status = "disabled";
	};

	iommu0: iommu@10205000 {
	compatible = "mediatek,mt2712-m4u";
	reg = <0 0x10205000 0 0x1000>;
	interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_M4U>;
	clock-names = "bclk";
	mediatek,larbs = <&larb0 &larb1 &larb2
	&larb3 &larb6>;
	#iommu-cells = <1>;
	};

	apmixedsys: syscon@10209000 {
	compatible = "mediatek,mt2712-apmixedsys", "syscon";
	reg = <0 0x10209000 0 0x1000>;
	#clock-cells = <1>;
	};

	iommu1: iommu@1020a000 {
	compatible = "mediatek,mt2712-m4u";
	reg = <0 0x1020a000 0 0x1000>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_M4U>;
	clock-names = "bclk";
	mediatek,larbs = <&larb4 &larb5 &larb7>;
	#iommu-cells = <1>;
	};

	mcucfg: syscon@10220000 {
	compatible = "mediatek,mt2712-mcucfg", "syscon";
	reg = <0 0x10220000 0 0x1000>;
	#clock-cells = <1>;
	};

	sysirq: interrupt-controller@10220a80 {
	compatible = "mediatek,mt2712-sysirq",
	"mediatek,mt6577-sysirq";
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	reg = <0 0x10220a80 0 0x40>;
	};

	gic: interrupt-controller@10510000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	interrupt-controller;
	reg = <0 0x10510000 0 0x10000>,
	<0 0x10520000 0 0x20000>,
	<0 0x10540000 0 0x20000>,
	<0 0x10560000 0 0x20000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_RAW(0x13) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	auxadc: adc@11001000 {
	compatible = "mediatek,mt2712-auxadc";
	reg = <0 0x11001000 0 0x1000>;
	clocks = <&pericfg CLK_PERI_AUXADC>;
	clock-names = "main";
	#io-channel-cells = <1>;
	status = "disabled";
	};

	uart0: serial@11002000 {
	compatible = "mediatek,mt2712-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11002000 0 0x400>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&baud_clk>, <&sys_clk>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart1: serial@11003000 {
	compatible = "mediatek,mt2712-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11003000 0 0x400>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&baud_clk>, <&sys_clk>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart2: serial@11004000 {
	compatible = "mediatek,mt2712-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11004000 0 0x400>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&baud_clk>, <&sys_clk>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart3: serial@11005000 {
	compatible = "mediatek,mt2712-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11005000 0 0x400>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&baud_clk>, <&sys_clk>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	pwm: pwm@11006000 {
	compatible = "mediatek,mt2712-pwm";
	reg = <0 0x11006000 0 0x1000>;
	#pwm-cells = <2>;
	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_PWM_SEL>,
	<&pericfg CLK_PERI_PWM>,
	<&pericfg CLK_PERI_PWM0>,
	<&pericfg CLK_PERI_PWM1>,
	<&pericfg CLK_PERI_PWM2>,
	<&pericfg CLK_PERI_PWM3>,
	<&pericfg CLK_PERI_PWM4>,
	<&pericfg CLK_PERI_PWM5>,
	<&pericfg CLK_PERI_PWM6>,
	<&pericfg CLK_PERI_PWM7>;
	clock-names = "top",
	"main",
	"pwm1",
	"pwm2",
	"pwm3",
	"pwm4",
	"pwm5",
	"pwm6",
	"pwm7",
	"pwm8";
	status = "disabled";
	};

	i2c0: i2c@11007000 {
	compatible = "mediatek,mt2712-i2c";
	reg = <0 0x11007000 0 0x90>,
	<0 0x11000180 0 0x80>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <4>;
	clocks = <&pericfg CLK_PERI_I2C0>,
	<&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main",
	"dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c1: i2c@11008000 {
	compatible = "mediatek,mt2712-i2c";
	reg = <0 0x11008000 0 0x90>,
	<0 0x11000200 0 0x80>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <4>;
	clocks = <&pericfg CLK_PERI_I2C1>,
	<&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main",
	"dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c2: i2c@11009000 {
	compatible = "mediatek,mt2712-i2c";
	reg = <0 0x11009000 0 0x90>,
	<0 0x11000280 0 0x80>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <4>;
	clocks = <&pericfg CLK_PERI_I2C2>,
	<&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main",
	"dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi0: spi@1100a000 {
	compatible = "mediatek,mt2712-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x1100a000 0 0x100>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
	<&topckgen CLK_TOP_SPI_SEL>,
	<&pericfg CLK_PERI_SPI0>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	nandc: nfi@1100e000 {
	compatible = "mediatek,mt2712-nfc";
	reg = <0 0x1100e000 0 0x1000>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>;
	clock-names = "nfi_clk", "pad_clk";
	ecc-engine = <&bch>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	bch: ecc@1100f000 {
	compatible = "mediatek,mt2712-ecc";
	reg = <0 0x1100f000 0 0x1000>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>;
	clock-names = "nfiecc_clk";
	status = "disabled";
	};

	i2c3: i2c@11010000 {
	compatible = "mediatek,mt2712-i2c";
	reg = <0 0x11010000 0 0x90>,
	<0 0x11000300 0 0x80>;
	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <4>;
	clocks = <&pericfg CLK_PERI_I2C3>,
	<&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main",
	"dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c4: i2c@11011000 {
	compatible = "mediatek,mt2712-i2c";
	reg = <0 0x11011000 0 0x90>,
	<0 0x11000380 0 0x80>;
	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <4>;
	clocks = <&pericfg CLK_PERI_I2C4>,
	<&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main",
	"dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c5: i2c@11013000 {
	compatible = "mediatek,mt2712-i2c";
	reg = <0 0x11013000 0 0x90>,
	<0 0x11000100 0 0x80>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <4>;
	clocks = <&pericfg CLK_PERI_I2C5>,
	<&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main",
	"dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi2: spi@11015000 {
	compatible = "mediatek,mt2712-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x11015000 0 0x100>;
	interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
	<&topckgen CLK_TOP_SPI_SEL>,
	<&pericfg CLK_PERI_SPI2>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	spi3: spi@11016000 {
	compatible = "mediatek,mt2712-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x11016000 0 0x100>;
	interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
	<&topckgen CLK_TOP_SPI_SEL>,
	<&pericfg CLK_PERI_SPI3>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	spi4: spi@10012000 {
	compatible = "mediatek,mt2712-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x10012000 0 0x100>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
	<&topckgen CLK_TOP_SPI_SEL>,
	<&infracfg CLK_INFRA_AO_SPI0>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	spi5: spi@11018000 {
	compatible = "mediatek,mt2712-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x11018000 0 0x100>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
	<&topckgen CLK_TOP_SPI_SEL>,
	<&pericfg CLK_PERI_SPI5>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	uart4: serial@11019000 {
	compatible = "mediatek,mt2712-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11019000 0 0x400>;
	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&baud_clk>, <&sys_clk>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	mmc0: mmc@11230000 {
	compatible = "mediatek,mt2712-mmc";
	reg = <0 0x11230000 0 0x1000>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_MSDC30_0>,
	<&pericfg CLK_PERI_MSDC50_0_HCLK_EN>,
	<&pericfg CLK_PERI_MSDC30_0_QTR_EN>,
	<&pericfg CLK_PERI_MSDC50_0_EN>;
	clock-names = "source", "hclk", "bus_clk", "source_cg";
	status = "disabled";
	};

	mmc1: mmc@11240000 {
	compatible = "mediatek,mt2712-mmc";
	reg = <0 0x11240000 0 0x1000>;
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_MSDC30_1>,
	<&topckgen CLK_TOP_AXI_SEL>,
	<&pericfg CLK_PERI_MSDC30_1_EN>;
	clock-names = "source", "hclk", "source_cg";
	status = "disabled";
	};

	mmc2: mmc@11250000 {
	compatible = "mediatek,mt2712-mmc";
	reg = <0 0x11250000 0 0x1000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_MSDC30_2>,
	<&topckgen CLK_TOP_AXI_SEL>,
	<&pericfg CLK_PERI_MSDC30_2_EN>;
	clock-names = "source", "hclk", "source_cg";
	status = "disabled";
	};

	ssusb: usb@11271000 {
	compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
	reg = <0 0x11271000 0 0x3000>,
	<0 0x11280700 0 0x0100>;
	reg-names = "mac", "ippc";
	interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
	phys = <&u2port0 PHY_TYPE_USB2>,
	<&u2port1 PHY_TYPE_USB2>;
	power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
	clocks = <&topckgen CLK_TOP_USB30_SEL>;
	clock-names = "sys_ck";
	mediatek,syscon-wakeup = <&pericfg 0x510 2>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "disabled";

	usb_host0: xhci@11270000 {
	compatible = "mediatek,mt2712-xhci",
	"mediatek,mtk-xhci";
	reg = <0 0x11270000 0 0x1000>;
	reg-names = "mac";
	interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
	clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
	clock-names = "sys_ck", "ref_ck";
	status = "disabled";
	};
	};

	u3phy0: usb-phy@11290000 {
	compatible = "mediatek,mt2712-u3phy";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "okay";

	u2port0: usb-phy@11290000 {
	reg = <0 0x11290000 0 0x700>;
	clocks = <&clk26m>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};

	u2port1: usb-phy@11298000 {
	reg = <0 0x11298000 0 0x700>;
	clocks = <&clk26m>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};

	u3port0: usb-phy@11298700 {
	reg = <0 0x11298700 0 0x900>;
	clocks = <&clk26m>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};
	};

	ssusb1: usb@112c1000 {
	compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
	reg = <0 0x112c1000 0 0x3000>,
	<0 0x112d0700 0 0x0100>;
	reg-names = "mac", "ippc";
	interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_LOW>;
	phys = <&u2port2 PHY_TYPE_USB2>,
	<&u2port3 PHY_TYPE_USB2>,
	<&u3port1 PHY_TYPE_USB3>;
	power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
	clocks = <&topckgen CLK_TOP_USB30_SEL>;
	clock-names = "sys_ck";
	mediatek,syscon-wakeup = <&pericfg 0x514 2>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "disabled";

	usb_host1: xhci@112c0000 {
	compatible = "mediatek,mt2712-xhci",
	"mediatek,mtk-xhci";
	reg = <0 0x112c0000 0 0x1000>;
	reg-names = "mac";
	interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
	clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
	clock-names = "sys_ck", "ref_ck";
	status = "disabled";
	};
	};

	u3phy1: usb-phy@112e0000 {
	compatible = "mediatek,mt2712-u3phy";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "okay";

	u2port2: usb-phy@112e0000 {
	reg = <0 0x112e0000 0 0x700>;
	clocks = <&clk26m>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};

	u2port3: usb-phy@112e8000 {
	reg = <0 0x112e8000 0 0x700>;
	clocks = <&clk26m>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};

	u3port1: usb-phy@112e8700 {
	reg = <0 0x112e8700 0 0x900>;
	clocks = <&clk26m>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};
	};

	pcie: pcie@11700000 {
	compatible = "mediatek,mt2712-pcie";
	device_type = "pci";
	reg = <0 0x11700000 0 0x1000>,
	<0 0x112ff000 0 0x1000>;
	reg-names = "port0", "port1";
	#address-cells = <3>;
	#size-cells = <2>;
	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
	<&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
	<&pericfg CLK_PERI_PCIE0>,
	<&pericfg CLK_PERI_PCIE1>;
	clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
	phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
	phy-names = "pcie-phy0", "pcie-phy1";
	bus-range = <0x00 0xff>;
	ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;

	pcie0: pcie@0,0 {
	device_type = "pci";
	status = "disabled";
	reg = <0x0000 0 0 0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0 0 0 1 &pcie_intc0 0>,
	<0 0 0 2 &pcie_intc0 1>,
	<0 0 0 3 &pcie_intc0 2>,
	<0 0 0 4 &pcie_intc0 3>;
	pcie_intc0: interrupt-controller {
	interrupt-controller;
	#address-cells = <0>;
	#interrupt-cells = <1>;
	};
	};

	pcie1: pcie@1,0 {
	device_type = "pci";
	status = "disabled";
	reg = <0x0800 0 0 0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0 0 0 1 &pcie_intc1 0>,
	<0 0 0 2 &pcie_intc1 1>,
	<0 0 0 3 &pcie_intc1 2>,
	<0 0 0 4 &pcie_intc1 3>;
	pcie_intc1: interrupt-controller {
	interrupt-controller;
	#address-cells = <0>;
	#interrupt-cells = <1>;
	};
	};
	};

	mfgcfg: syscon@13000000 {
	compatible = "mediatek,mt2712-mfgcfg", "syscon";
	reg = <0 0x13000000 0 0x1000>;
	#clock-cells = <1>;
	};

	mmsys: syscon@14000000 {
	compatible = "mediatek,mt2712-mmsys", "syscon";
	reg = <0 0x14000000 0 0x1000>;
	#clock-cells = <1>;
	};

	larb0: larb@14021000 {
	compatible = "mediatek,mt2712-smi-larb";
	reg = <0 0x14021000 0 0x1000>;
	mediatek,smi = <&smi_common0>;
	mediatek,larb-id = <0>;
	power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_SMI_LARB0>,
	<&mmsys CLK_MM_SMI_LARB0>;
	clock-names = "apb", "smi";
	};

	smi_common0: smi@14022000 {
	compatible = "mediatek,mt2712-smi-common";
	reg = <0 0x14022000 0 0x1000>;
	power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_SMI_COMMON>,
	<&mmsys CLK_MM_SMI_COMMON>;
	clock-names = "apb", "smi";
	};

	larb4: larb@14027000 {
	compatible = "mediatek,mt2712-smi-larb";
	reg = <0 0x14027000 0 0x1000>;
	mediatek,smi = <&smi_common1>;
	mediatek,larb-id = <4>;
	power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_SMI_LARB4>,
	<&mmsys CLK_MM_SMI_LARB4>;
	clock-names = "apb", "smi";
	};

	larb5: larb@14030000 {
	compatible = "mediatek,mt2712-smi-larb";
	reg = <0 0x14030000 0 0x1000>;
	mediatek,smi = <&smi_common1>;
	mediatek,larb-id = <5>;
	power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_SMI_LARB5>,
	<&mmsys CLK_MM_SMI_LARB5>;
	clock-names = "apb", "smi";
	};

	smi_common1: smi@14031000 {
	compatible = "mediatek,mt2712-smi-common";
	reg = <0 0x14031000 0 0x1000>;
	power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_SMI_COMMON1>,
	<&mmsys CLK_MM_SMI_COMMON1>;
	clock-names = "apb", "smi";
	};

	larb7: larb@14032000 {
	compatible = "mediatek,mt2712-smi-larb";
	reg = <0 0x14032000 0 0x1000>;
	mediatek,smi = <&smi_common1>;
	mediatek,larb-id = <7>;
	power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_SMI_LARB7>,
	<&mmsys CLK_MM_SMI_LARB7>;
	clock-names = "apb", "smi";
	};

	imgsys: syscon@15000000 {
	compatible = "mediatek,mt2712-imgsys", "syscon";
	reg = <0 0x15000000 0 0x1000>;
	#clock-cells = <1>;
	};

	larb2: larb@15001000 {
	compatible = "mediatek,mt2712-smi-larb";
	reg = <0 0x15001000 0 0x1000>;
	mediatek,smi = <&smi_common0>;
	mediatek,larb-id = <2>;
	power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>;
	clocks = <&imgsys CLK_IMG_SMI_LARB2>,
	<&imgsys CLK_IMG_SMI_LARB2>;
	clock-names = "apb", "smi";
	};

	bdpsys: syscon@15010000 {
	compatible = "mediatek,mt2712-bdpsys", "syscon";
	reg = <0 0x15010000 0 0x1000>;
	#clock-cells = <1>;
	};

	vdecsys: syscon@16000000 {
	compatible = "mediatek,mt2712-vdecsys", "syscon";
	reg = <0 0x16000000 0 0x1000>;
	#clock-cells = <1>;
	};

	larb1: larb@16010000 {
	compatible = "mediatek,mt2712-smi-larb";
	reg = <0 0x16010000 0 0x1000>;
	mediatek,smi = <&smi_common0>;
	mediatek,larb-id = <1>;
	power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>;
	clocks = <&vdecsys CLK_VDEC_CKEN>,
	<&vdecsys CLK_VDEC_LARB1_CKEN>;
	clock-names = "apb", "smi";
	};

	vencsys: syscon@18000000 {
	compatible = "mediatek,mt2712-vencsys", "syscon";
	reg = <0 0x18000000 0 0x1000>;
	#clock-cells = <1>;
	};

	larb3: larb@18001000 {
	compatible = "mediatek,mt2712-smi-larb";
	reg = <0 0x18001000 0 0x1000>;
	mediatek,smi = <&smi_common0>;
	mediatek,larb-id = <3>;
	power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
	clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>,
	<&vencsys CLK_VENC_VENC>;
	clock-names = "apb", "smi";
	};

	larb6: larb@18002000 {
	compatible = "mediatek,mt2712-smi-larb";
	reg = <0 0x18002000 0 0x1000>;
	mediatek,smi = <&smi_common0>;
	mediatek,larb-id = <6>;
	power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
	clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>,
	<&vencsys CLK_VENC_VENC>;
	clock-names = "apb", "smi";
	};

	jpgdecsys: syscon@19000000 {
	compatible = "mediatek,mt2712-jpgdecsys", "syscon";
	reg = <0 0x19000000 0 0x1000>;
	#clock-cells = <1>;
	};
	};

	diff --git a/sys/gnu/dts/arm64/mediatek/mt6797.dtsi b/sys/gnu/dts/arm64/mediatek/mt6797.dtsi
	index 2b2a69c7567f..136ef9527a0d 100644
	--- a/sys/gnu/dts/arm64/mediatek/mt6797.dtsi
	+++ b/sys/gnu/dts/arm64/mediatek/mt6797.dtsi
	@@ -1,270 +1,270 @@
	/*
	* Copyright (c) 2017 MediaTek Inc.
	* Author: Mars.C <mars.cheng@mediatek.com>
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License version 2 as
	* published by the Free Software Foundation.
	*
	* This program is distributed in the hope that it will be useful,
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*/

	#include <dt-bindings/clock/mt6797-clk.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/pinctrl/mt6797-pinfunc.h>

	/ {
	compatible = "mediatek,mt6797";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	enable-method = "psci";
	reg = <0x000>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	enable-method = "psci";
	reg = <0x001>;
	};

	cpu2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	enable-method = "psci";
	reg = <0x002>;
	};

	cpu3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	enable-method = "psci";
	reg = <0x003>;
	};

	cpu4: cpu@100 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	enable-method = "psci";
	reg = <0x100>;
	};

	cpu5: cpu@101 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	enable-method = "psci";
	reg = <0x101>;
	};

	cpu6: cpu@102 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	enable-method = "psci";
	reg = <0x102>;
	};

	cpu7: cpu@103 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	enable-method = "psci";
	reg = <0x103>;
	};

	cpu8: cpu@200 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x200>;
	};

	cpu9: cpu@201 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	enable-method = "psci";
	reg = <0x201>;
	};
	};

	clk26m: oscillator@0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <26000000>;
	clock-output-names = "clk26m";
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupt-parent = <&gic>;
	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	topckgen: topckgen@10000000 {
	compatible = "mediatek,mt6797-topckgen";
	reg = <0 0x10000000 0 0x1000>;
	#clock-cells = <1>;
	};

	infrasys: infracfg_ao@10001000 {
	compatible = "mediatek,mt6797-infracfg", "syscon";
	reg = <0 0x10001000 0 0x1000>;
	#clock-cells = <1>;
	};

	pio: pinctrl@10005000 {
	compatible = "mediatek,mt6797-pinctrl";
	reg = <0 0x10005000 0 0x1000>,
	<0 0x10002000 0 0x400>,
	<0 0x10002400 0 0x400>,
	<0 0x10002800 0 0x400>,
	<0 0x10002C00 0 0x400>;
	reg-names = "gpio", "iocfgl", "iocfgb",
	"iocfgr", "iocfgt";
	gpio-controller;
	#gpio-cells = <2>;

	uart0_pins_a: uart0 {
	pins0 {
	pinmux = <MT6797_GPIO234__FUNC_UTXD0>,
	<MT6797_GPIO235__FUNC_URXD0>;
	};
	};

	uart1_pins_a: uart1 {
	pins1 {
	pinmux = <MT6797_GPIO232__FUNC_URXD1>,
	<MT6797_GPIO233__FUNC_UTXD1>;
	};
	};
	};

	- scpsys: scpsys@10006000 {
	+ scpsys: power-controller@10006000 {
	compatible = "mediatek,mt6797-scpsys";
	#power-domain-cells = <1>;
	reg = <0 0x10006000 0 0x1000>;
	clocks = <&topckgen CLK_TOP_MUX_MFG>,
	<&topckgen CLK_TOP_MUX_MM>,
	<&topckgen CLK_TOP_MUX_VDEC>;
	clock-names = "mfg", "mm", "vdec";
	infracfg = <&infrasys>;
	};

	watchdog: watchdog@10007000 {
	compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt";
	reg = <0 0x10007000 0 0x100>;
	};

	apmixedsys: apmixed@1000c000 {
	compatible = "mediatek,mt6797-apmixedsys";
	reg = <0 0x1000c000 0 0x1000>;
	#clock-cells = <1>;
	};

	sysirq: intpol-controller@10200620 {
	compatible = "mediatek,mt6797-sysirq",
	"mediatek,mt6577-sysirq";
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	reg = <0 0x10220620 0 0x20>,
	<0 0x10220690 0 0x10>;
	};

	uart0: serial@11002000 {
	compatible = "mediatek,mt6797-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11002000 0 0x400>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infrasys CLK_INFRA_UART0>,
	<&infrasys CLK_INFRA_AP_DMA>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart1: serial@11003000 {
	compatible = "mediatek,mt6797-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11003000 0 0x400>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infrasys CLK_INFRA_UART1>,
	<&infrasys CLK_INFRA_AP_DMA>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart2: serial@11004000 {
	compatible = "mediatek,mt6797-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11004000 0 0x400>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infrasys CLK_INFRA_UART2>,
	<&infrasys CLK_INFRA_AP_DMA>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart3: serial@11005000 {
	compatible = "mediatek,mt6797-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11005000 0 0x400>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infrasys CLK_INFRA_UART3>,
	<&infrasys CLK_INFRA_AP_DMA>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	mmsys: mmsys_config@14000000 {
	compatible = "mediatek,mt6797-mmsys", "syscon";
	reg = <0 0x14000000 0 0x1000>;
	#clock-cells = <1>;
	};

	imgsys: imgsys_config@15000000 {
	compatible = "mediatek,mt6797-imgsys", "syscon";
	reg = <0 0x15000000 0 0x1000>;
	#clock-cells = <1>;
	};

	vdecsys: vdec_gcon@16000000 {
	compatible = "mediatek,mt6797-vdecsys", "syscon";
	reg = <0 0x16000000 0 0x10000>;
	#clock-cells = <1>;
	};

	vencsys: venc_gcon@17000000 {
	compatible = "mediatek,mt6797-vencsys", "syscon";
	reg = <0 0x17000000 0 0x1000>;
	#clock-cells = <1>;
	};

	gic: interrupt-controller@19000000 {
	compatible = "arm,gic-v3";
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	reg = <0 0x19000000 0 0x10000>, /* GICD */
	<0 0x19200000 0 0x200000>, /* GICR */
	<0 0x10240000 0 0x2000>; /* GICC */
	};
	};
	diff --git a/sys/gnu/dts/arm64/mediatek/mt7622.dtsi b/sys/gnu/dts/arm64/mediatek/mt7622.dtsi
	index dac51e98204c..339dc9f88f43 100644
	--- a/sys/gnu/dts/arm64/mediatek/mt7622.dtsi
	+++ b/sys/gnu/dts/arm64/mediatek/mt7622.dtsi
	@@ -1,935 +1,935 @@
	/*
	* Copyright (c) 2017 MediaTek Inc.
	* Author: Ming Huang <ming.huang@mediatek.com>
	* Sean Wang <sean.wang@mediatek.com>
	*
	* SPDX-License-Identifier: (GPL-2.0 OR MIT)
	*/

	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/mt7622-clk.h>
	#include <dt-bindings/phy/phy.h>
	#include <dt-bindings/power/mt7622-power.h>
	#include <dt-bindings/reset/mt7622-reset.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	compatible = "mediatek,mt7622";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpu_opp_table: opp-table {
	compatible = "operating-points-v2";
	opp-shared;
	opp-300000000 {
	opp-hz = /bits/ 64 <30000000>;
	opp-microvolt = <950000>;
	};

	opp-437500000 {
	opp-hz = /bits/ 64 <437500000>;
	opp-microvolt = <1000000>;
	};

	opp-600000000 {
	opp-hz = /bits/ 64 <600000000>;
	opp-microvolt = <1050000>;
	};

	opp-812500000 {
	opp-hz = /bits/ 64 <812500000>;
	opp-microvolt = <1100000>;
	};

	opp-1025000000 {
	opp-hz = /bits/ 64 <1025000000>;
	opp-microvolt = <1150000>;
	};

	opp-1137500000 {
	opp-hz = /bits/ 64 <1137500000>;
	opp-microvolt = <1200000>;
	};

	opp-1262500000 {
	opp-hz = /bits/ 64 <1262500000>;
	opp-microvolt = <1250000>;
	};

	opp-1350000000 {
	opp-hz = /bits/ 64 <1350000000>;
	opp-microvolt = <1310000>;
	};
	};

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x0>;
	clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
	<&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
	clock-names = "cpu", "intermediate";
	operating-points-v2 = <&cpu_opp_table>;
	#cooling-cells = <2>;
	enable-method = "psci";
	clock-frequency = <1300000000>;
	cci-control-port = <&cci_control2>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x1>;
	clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
	<&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
	clock-names = "cpu", "intermediate";
	operating-points-v2 = <&cpu_opp_table>;
	#cooling-cells = <2>;
	enable-method = "psci";
	clock-frequency = <1300000000>;
	cci-control-port = <&cci_control2>;
	};
	};

	pwrap_clk: dummy40m {
	compatible = "fixed-clock";
	clock-frequency = <40000000>;
	#clock-cells = <0>;
	};

	clk25m: oscillator {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <25000000>;
	clock-output-names = "clkxtal";
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	pmu {
	compatible = "arm,cortex-a53-pmu";
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
	interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
	secmon_reserved: secmon@43000000 {
	reg = <0 0x43000000 0 0x30000>;
	no-map;
	};
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	polling-delay-passive = <1000>;
	polling-delay = <1000>;

	thermal-sensors = <&thermal 0>;

	trips {
	cpu_passive: cpu-passive {
	temperature = <47000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu_active: cpu-active {
	temperature = <67000>;
	hysteresis = <2000>;
	type = "active";
	};

	cpu_hot: cpu-hot {
	temperature = <87000>;
	hysteresis = <2000>;
	type = "hot";
	};

	cpu-crit {
	temperature = <107000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu_passive>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};

	map1 {
	trip = <&cpu_active>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};

	map2 {
	trip = <&cpu_hot>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupt-parent = <&gic>;
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_LEVEL_HIGH)>;
	};

	infracfg: infracfg@10000000 {
	compatible = "mediatek,mt7622-infracfg",
	"syscon";
	reg = <0 0x10000000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pwrap: pwrap@10001000 {
	compatible = "mediatek,mt7622-pwrap";
	reg = <0 0x10001000 0 0x250>;
	reg-names = "pwrap";
	clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
	clock-names = "spi", "wrap";
	resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
	reset-names = "pwrap";
	interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	pericfg: pericfg@10002000 {
	compatible = "mediatek,mt7622-pericfg",
	"syscon";
	reg = <0 0x10002000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	- scpsys: scpsys@10006000 {
	+ scpsys: power-controller@10006000 {
	compatible = "mediatek,mt7622-scpsys",
	"syscon";
	#power-domain-cells = <1>;
	reg = <0 0x10006000 0 0x1000>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
	infracfg = <&infracfg>;
	clocks = <&topckgen CLK_TOP_HIF_SEL>;
	clock-names = "hif_sel";
	};

	cir: cir@10009000 {
	compatible = "mediatek,mt7622-cir";
	reg = <0 0x10009000 0 0x1000>;
	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_IRRX_PD>,
	<&topckgen CLK_TOP_AXI_SEL>;
	clock-names = "clk", "bus";
	status = "disabled";
	};

	sysirq: interrupt-controller@10200620 {
	compatible = "mediatek,mt7622-sysirq",
	"mediatek,mt6577-sysirq";
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	reg = <0 0x10200620 0 0x20>;
	};

	efuse: efuse@10206000 {
	compatible = "mediatek,mt7622-efuse",
	"mediatek,efuse";
	reg = <0 0x10206000 0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;

	thermal_calibration: calib@198 {
	reg = <0x198 0xc>;
	};
	};

	apmixedsys: apmixedsys@10209000 {
	compatible = "mediatek,mt7622-apmixedsys",
	"syscon";
	reg = <0 0x10209000 0 0x1000>;
	#clock-cells = <1>;
	};

	topckgen: topckgen@10210000 {
	compatible = "mediatek,mt7622-topckgen",
	"syscon";
	reg = <0 0x10210000 0 0x1000>;
	#clock-cells = <1>;
	};

	rng: rng@1020f000 {
	compatible = "mediatek,mt7622-rng",
	"mediatek,mt7623-rng";
	reg = <0 0x1020f000 0 0x1000>;
	clocks = <&infracfg CLK_INFRA_TRNG>;
	clock-names = "rng";
	};

	pio: pinctrl@10211000 {
	compatible = "mediatek,mt7622-pinctrl";
	reg = <0 0x10211000 0 0x1000>,
	<0 0x10005000 0 0x1000>;
	reg-names = "base", "eint";
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pio 0 0 103>;
	interrupt-controller;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-parent = <&gic>;
	#interrupt-cells = <2>;
	};

	watchdog: watchdog@10212000 {
	compatible = "mediatek,mt7622-wdt",
	"mediatek,mt6589-wdt";
	reg = <0 0x10212000 0 0x800>;
	};

	rtc: rtc@10212800 {
	compatible = "mediatek,mt7622-rtc",
	"mediatek,soc-rtc";
	reg = <0 0x10212800 0 0x200>;
	interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_RTC>;
	clock-names = "rtc";
	};

	gic: interrupt-controller@10300000 {
	compatible = "arm,gic-400";
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	reg = <0 0x10310000 0 0x1000>,
	<0 0x10320000 0 0x1000>,
	<0 0x10340000 0 0x2000>,
	<0 0x10360000 0 0x2000>;
	};

	cci: cci@10390000 {
	compatible = "arm,cci-400";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0 0x10390000 0 0x1000>;
	ranges = <0 0 0x10390000 0x10000>;

	cci_control0: slave-if@1000 {
	compatible = "arm,cci-400-ctrl-if";
	interface-type = "ace-lite";
	reg = <0x1000 0x1000>;
	};

	cci_control1: slave-if@4000 {
	compatible = "arm,cci-400-ctrl-if";
	interface-type = "ace";
	reg = <0x4000 0x1000>;
	};

	cci_control2: slave-if@5000 {
	compatible = "arm,cci-400-ctrl-if";
	interface-type = "ace";
	reg = <0x5000 0x1000>;
	};

	pmu@9000 {
	compatible = "arm,cci-400-pmu,r1";
	reg = <0x9000 0x5000>;
	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	auxadc: adc@11001000 {
	compatible = "mediatek,mt7622-auxadc";
	reg = <0 0x11001000 0 0x1000>;
	clocks = <&pericfg CLK_PERI_AUXADC_PD>;
	clock-names = "main";
	#io-channel-cells = <1>;
	};

	uart0: serial@11002000 {
	compatible = "mediatek,mt7622-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11002000 0 0x400>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_UART_SEL>,
	<&pericfg CLK_PERI_UART0_PD>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart1: serial@11003000 {
	compatible = "mediatek,mt7622-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11003000 0 0x400>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_UART_SEL>,
	<&pericfg CLK_PERI_UART1_PD>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart2: serial@11004000 {
	compatible = "mediatek,mt7622-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11004000 0 0x400>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_UART_SEL>,
	<&pericfg CLK_PERI_UART2_PD>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart3: serial@11005000 {
	compatible = "mediatek,mt7622-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11005000 0 0x400>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_UART_SEL>,
	<&pericfg CLK_PERI_UART3_PD>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	pwm: pwm@11006000 {
	compatible = "mediatek,mt7622-pwm";
	reg = <0 0x11006000 0 0x1000>;
	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_PWM_SEL>,
	<&pericfg CLK_PERI_PWM_PD>,
	<&pericfg CLK_PERI_PWM1_PD>,
	<&pericfg CLK_PERI_PWM2_PD>,
	<&pericfg CLK_PERI_PWM3_PD>,
	<&pericfg CLK_PERI_PWM4_PD>,
	<&pericfg CLK_PERI_PWM5_PD>,
	<&pericfg CLK_PERI_PWM6_PD>;
	clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
	"pwm5", "pwm6";
	status = "disabled";
	};

	i2c0: i2c@11007000 {
	compatible = "mediatek,mt7622-i2c";
	reg = <0 0x11007000 0 0x90>,
	<0 0x11000100 0 0x80>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C0_PD>,
	<&pericfg CLK_PERI_AP_DMA_PD>;
	clock-names = "main", "dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c1: i2c@11008000 {
	compatible = "mediatek,mt7622-i2c";
	reg = <0 0x11008000 0 0x90>,
	<0 0x11000180 0 0x80>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C1_PD>,
	<&pericfg CLK_PERI_AP_DMA_PD>;
	clock-names = "main", "dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c2: i2c@11009000 {
	compatible = "mediatek,mt7622-i2c";
	reg = <0 0x11009000 0 0x90>,
	<0 0x11000200 0 0x80>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C2_PD>,
	<&pericfg CLK_PERI_AP_DMA_PD>;
	clock-names = "main", "dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi0: spi@1100a000 {
	compatible = "mediatek,mt7622-spi";
	reg = <0 0x1100a000 0 0x100>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	<&topckgen CLK_TOP_SPI0_SEL>,
	<&pericfg CLK_PERI_SPI0_PD>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	thermal: thermal@1100b000 {
	#thermal-sensor-cells = <1>;
	compatible = "mediatek,mt7622-thermal";
	reg = <0 0x1100b000 0 0x1000>;
	interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_THERM_PD>,
	<&pericfg CLK_PERI_AUXADC_PD>;
	clock-names = "therm", "auxadc";
	resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
	reset-names = "therm";
	mediatek,auxadc = <&auxadc>;
	mediatek,apmixedsys = <&apmixedsys>;
	nvmem-cells = <&thermal_calibration>;
	nvmem-cell-names = "calibration-data";
	};

	btif: serial@1100c000 {
	compatible = "mediatek,mt7622-btif",
	"mediatek,mtk-btif";
	reg = <0 0x1100c000 0 0x1000>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_BTIF_PD>;
	clock-names = "main";
	reg-shift = <2>;
	reg-io-width = <4>;
	status = "disabled";

	bluetooth {
	compatible = "mediatek,mt7622-bluetooth";
	power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
	clocks = <&clk25m>;
	clock-names = "ref";
	};
	};

	nandc: nfi@1100d000 {
	compatible = "mediatek,mt7622-nfc";
	reg = <0 0x1100D000 0 0x1000>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_NFI_PD>,
	<&pericfg CLK_PERI_SNFI_PD>;
	clock-names = "nfi_clk", "pad_clk";
	ecc-engine = <&bch>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	bch: ecc@1100e000 {
	compatible = "mediatek,mt7622-ecc";
	reg = <0 0x1100e000 0 0x1000>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_NFIECC_PD>;
	clock-names = "nfiecc_clk";
	status = "disabled";
	};

	nor_flash: spi@11014000 {
	compatible = "mediatek,mt7622-nor",
	"mediatek,mt8173-nor";
	reg = <0 0x11014000 0 0xe0>;
	clocks = <&pericfg CLK_PERI_FLASH_PD>,
	<&topckgen CLK_TOP_FLASH_SEL>;
	clock-names = "spi", "sf";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi1: spi@11016000 {
	compatible = "mediatek,mt7622-spi";
	reg = <0 0x11016000 0 0x100>;
	interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	<&topckgen CLK_TOP_SPI1_SEL>,
	<&pericfg CLK_PERI_SPI1_PD>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart4: serial@11019000 {
	compatible = "mediatek,mt7622-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11019000 0 0x400>;
	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_UART_SEL>,
	<&pericfg CLK_PERI_UART4_PD>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	audsys: clock-controller@11220000 {
	compatible = "mediatek,mt7622-audsys", "syscon";
	reg = <0 0x11220000 0 0x2000>;
	#clock-cells = <1>;

	afe: audio-controller {
	compatible = "mediatek,mt7622-audio";
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
	interrupt-names = "afe", "asys";

	clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
	<&topckgen CLK_TOP_AUD1_SEL>,
	<&topckgen CLK_TOP_AUD2_SEL>,
	<&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
	<&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
	<&topckgen CLK_TOP_I2S0_MCK_SEL>,
	<&topckgen CLK_TOP_I2S1_MCK_SEL>,
	<&topckgen CLK_TOP_I2S2_MCK_SEL>,
	<&topckgen CLK_TOP_I2S3_MCK_SEL>,
	<&topckgen CLK_TOP_I2S0_MCK_DIV>,
	<&topckgen CLK_TOP_I2S1_MCK_DIV>,
	<&topckgen CLK_TOP_I2S2_MCK_DIV>,
	<&topckgen CLK_TOP_I2S3_MCK_DIV>,
	<&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
	<&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
	<&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
	<&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
	<&audsys CLK_AUDIO_I2SO1>,
	<&audsys CLK_AUDIO_I2SO2>,
	<&audsys CLK_AUDIO_I2SO3>,
	<&audsys CLK_AUDIO_I2SO4>,
	<&audsys CLK_AUDIO_I2SIN1>,
	<&audsys CLK_AUDIO_I2SIN2>,
	<&audsys CLK_AUDIO_I2SIN3>,
	<&audsys CLK_AUDIO_I2SIN4>,
	<&audsys CLK_AUDIO_ASRCO1>,
	<&audsys CLK_AUDIO_ASRCO2>,
	<&audsys CLK_AUDIO_ASRCO3>,
	<&audsys CLK_AUDIO_ASRCO4>,
	<&audsys CLK_AUDIO_AFE>,
	<&audsys CLK_AUDIO_AFE_CONN>,
	<&audsys CLK_AUDIO_A1SYS>,
	<&audsys CLK_AUDIO_A2SYS>;

	clock-names = "infra_sys_audio_clk",
	"top_audio_mux1_sel",
	"top_audio_mux2_sel",
	"top_audio_a1sys_hp",
	"top_audio_a2sys_hp",
	"i2s0_src_sel",
	"i2s1_src_sel",
	"i2s2_src_sel",
	"i2s3_src_sel",
	"i2s0_src_div",
	"i2s1_src_div",
	"i2s2_src_div",
	"i2s3_src_div",
	"i2s0_mclk_en",
	"i2s1_mclk_en",
	"i2s2_mclk_en",
	"i2s3_mclk_en",
	"i2so0_hop_ck",
	"i2so1_hop_ck",
	"i2so2_hop_ck",
	"i2so3_hop_ck",
	"i2si0_hop_ck",
	"i2si1_hop_ck",
	"i2si2_hop_ck",
	"i2si3_hop_ck",
	"asrc0_out_ck",
	"asrc1_out_ck",
	"asrc2_out_ck",
	"asrc3_out_ck",
	"audio_afe_pd",
	"audio_afe_conn_pd",
	"audio_a1sys_pd",
	"audio_a2sys_pd";

	assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
	<&topckgen CLK_TOP_A2SYS_HP_SEL>,
	<&topckgen CLK_TOP_A1SYS_HP_DIV>,
	<&topckgen CLK_TOP_A2SYS_HP_DIV>;
	assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
	<&topckgen CLK_TOP_AUD2PLL>;
	assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
	};
	};

	mmc0: mmc@11230000 {
	compatible = "mediatek,mt7622-mmc";
	reg = <0 0x11230000 0 0x1000>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
	<&topckgen CLK_TOP_MSDC50_0_SEL>;
	clock-names = "source", "hclk";
	status = "disabled";
	};

	mmc1: mmc@11240000 {
	compatible = "mediatek,mt7622-mmc";
	reg = <0 0x11240000 0 0x1000>;
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
	<&topckgen CLK_TOP_AXI_SEL>;
	clock-names = "source", "hclk";
	status = "disabled";
	};

	ssusbsys: ssusbsys@1a000000 {
	compatible = "mediatek,mt7622-ssusbsys",
	"syscon";
	reg = <0 0x1a000000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	ssusb: usb@1a0c0000 {
	compatible = "mediatek,mt7622-xhci",
	"mediatek,mtk-xhci";
	reg = <0 0x1a0c0000 0 0x01000>,
	<0 0x1a0c4700 0 0x0100>;
	reg-names = "mac", "ippc";
	interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
	clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
	<&ssusbsys CLK_SSUSB_REF_EN>,
	<&ssusbsys CLK_SSUSB_MCU_EN>,
	<&ssusbsys CLK_SSUSB_DMA_EN>;
	clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
	phys = <&u2port0 PHY_TYPE_USB2>,
	<&u3port0 PHY_TYPE_USB3>,
	<&u2port1 PHY_TYPE_USB2>;

	status = "disabled";
	};

	u3phy: usb-phy@1a0c4000 {
	compatible = "mediatek,mt7622-u3phy",
	"mediatek,generic-tphy-v1";
	reg = <0 0x1a0c4000 0 0x700>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "disabled";

	u2port0: usb-phy@1a0c4800 {
	reg = <0 0x1a0c4800 0 0x0100>;
	#phy-cells = <1>;
	clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
	clock-names = "ref";
	};

	u3port0: usb-phy@1a0c4900 {
	reg = <0 0x1a0c4900 0 0x0700>;
	#phy-cells = <1>;
	clocks = <&clk25m>;
	clock-names = "ref";
	};

	u2port1: usb-phy@1a0c5000 {
	reg = <0 0x1a0c5000 0 0x0100>;
	#phy-cells = <1>;
	clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
	clock-names = "ref";
	};
	};

	pciesys: pciesys@1a100800 {
	compatible = "mediatek,mt7622-pciesys",
	"syscon";
	reg = <0 0x1a100800 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pcie: pcie@1a140000 {
	compatible = "mediatek,mt7622-pcie";
	device_type = "pci";
	reg = <0 0x1a140000 0 0x1000>,
	<0 0x1a143000 0 0x1000>,
	<0 0x1a145000 0 0x1000>;
	reg-names = "subsys", "port0", "port1";
	#address-cells = <3>;
	#size-cells = <2>;
	interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
	<&pciesys CLK_PCIE_P1_MAC_EN>,
	<&pciesys CLK_PCIE_P0_AHB_EN>,
	<&pciesys CLK_PCIE_P0_AHB_EN>,
	<&pciesys CLK_PCIE_P0_AUX_EN>,
	<&pciesys CLK_PCIE_P1_AUX_EN>,
	<&pciesys CLK_PCIE_P0_AXI_EN>,
	<&pciesys CLK_PCIE_P1_AXI_EN>,
	<&pciesys CLK_PCIE_P0_OBFF_EN>,
	<&pciesys CLK_PCIE_P1_OBFF_EN>,
	<&pciesys CLK_PCIE_P0_PIPE_EN>,
	<&pciesys CLK_PCIE_P1_PIPE_EN>;
	clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
	"aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
	"obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
	power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
	bus-range = <0x00 0xff>;
	ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
	status = "disabled";

	pcie0: pcie@0,0 {
	reg = <0x0000 0 0 0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges;
	status = "disabled";

	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0 0 0 1 &pcie_intc0 0>,
	<0 0 0 2 &pcie_intc0 1>,
	<0 0 0 3 &pcie_intc0 2>,
	<0 0 0 4 &pcie_intc0 3>;
	pcie_intc0: interrupt-controller {
	interrupt-controller;
	#address-cells = <0>;
	#interrupt-cells = <1>;
	};
	};

	pcie1: pcie@1,0 {
	reg = <0x0800 0 0 0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges;
	status = "disabled";

	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0 0 0 1 &pcie_intc1 0>,
	<0 0 0 2 &pcie_intc1 1>,
	<0 0 0 3 &pcie_intc1 2>,
	<0 0 0 4 &pcie_intc1 3>;
	pcie_intc1: interrupt-controller {
	interrupt-controller;
	#address-cells = <0>;
	#interrupt-cells = <1>;
	};
	};
	};

	sata: sata@1a200000 {
	compatible = "mediatek,mt7622-ahci",
	"mediatek,mtk-ahci";
	reg = <0 0x1a200000 0 0x1100>;
	interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hostc";
	clocks = <&pciesys CLK_SATA_AHB_EN>,
	<&pciesys CLK_SATA_AXI_EN>,
	<&pciesys CLK_SATA_ASIC_EN>,
	<&pciesys CLK_SATA_RBC_EN>,
	<&pciesys CLK_SATA_PM_EN>;
	clock-names = "ahb", "axi", "asic", "rbc", "pm";
	phys = <&sata_port PHY_TYPE_SATA>;
	phy-names = "sata-phy";
	ports-implemented = <0x1>;
	power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
	resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
	<&pciesys MT7622_SATA_PHY_SW_RST>,
	<&pciesys MT7622_SATA_PHY_REG_RST>;
	reset-names = "axi", "sw", "reg";
	mediatek,phy-mode = <&pciesys>;
	status = "disabled";
	};

	sata_phy: sata-phy@1a243000 {
	compatible = "mediatek,generic-tphy-v1";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "disabled";

	sata_port: sata-phy@1a243000 {
	reg = <0 0x1a243000 0 0x0100>;
	clocks = <&topckgen CLK_TOP_ETH_500M>;
	clock-names = "ref";
	#phy-cells = <1>;
	};
	};

	ethsys: syscon@1b000000 {
	compatible = "mediatek,mt7622-ethsys",
	"syscon";
	reg = <0 0x1b000000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	hsdma: dma-controller@1b007000 {
	compatible = "mediatek,mt7622-hsdma";
	reg = <0 0x1b007000 0 0x1000>;
	interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&ethsys CLK_ETH_HSDMA_EN>;
	clock-names = "hsdma";
	power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
	#dma-cells = <1>;
	};

	eth: ethernet@1b100000 {
	compatible = "mediatek,mt7622-eth",
	"mediatek,mt2701-eth",
	"syscon";
	reg = <0 0x1b100000 0 0x20000>;
	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_ETH_SEL>,
	<&ethsys CLK_ETH_ESW_EN>,
	<&ethsys CLK_ETH_GP0_EN>,
	<&ethsys CLK_ETH_GP1_EN>,
	<&ethsys CLK_ETH_GP2_EN>,
	<&sgmiisys CLK_SGMII_TX250M_EN>,
	<&sgmiisys CLK_SGMII_RX250M_EN>,
	<&sgmiisys CLK_SGMII_CDR_REF>,
	<&sgmiisys CLK_SGMII_CDR_FB>,
	<&topckgen CLK_TOP_SGMIIPLL>,
	<&apmixedsys CLK_APMIXED_ETH2PLL>;
	clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
	"sgmii_tx250m", "sgmii_rx250m",
	"sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
	"eth2pll";
	power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
	mediatek,ethsys = <&ethsys>;
	mediatek,sgmiisys = <&sgmiisys>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	sgmiisys: sgmiisys@1b128000 {
	compatible = "mediatek,mt7622-sgmiisys",
	"syscon";
	reg = <0 0x1b128000 0 0x3000>;
	#clock-cells = <1>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/mediatek/mt8173.dtsi b/sys/gnu/dts/arm64/mediatek/mt8173.dtsi
	index 8b4e806d5119..d819e44d94a8 100644
	--- a/sys/gnu/dts/arm64/mediatek/mt8173.dtsi
	+++ b/sys/gnu/dts/arm64/mediatek/mt8173.dtsi
	@@ -1,1439 +1,1440 @@
	/*
	* Copyright (c) 2014 MediaTek Inc.
	* Author: Eddie Huang <eddie.huang@mediatek.com>
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License version 2 as
	* published by the Free Software Foundation.
	*
	* This program is distributed in the hope that it will be useful,
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*/

	#include <dt-bindings/clock/mt8173-clk.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/memory/mt8173-larb-port.h>
	#include <dt-bindings/phy/phy.h>
	#include <dt-bindings/power/mt8173-power.h>
	#include <dt-bindings/reset/mt8173-resets.h>
	#include <dt-bindings/gce/mt8173-gce.h>
	#include "mt8173-pinfunc.h"

	/ {
	compatible = "mediatek,mt8173";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	ovl0 = &ovl0;
	ovl1 = &ovl1;
	rdma0 = &rdma0;
	rdma1 = &rdma1;
	rdma2 = &rdma2;
	wdma0 = &wdma0;
	wdma1 = &wdma1;
	color0 = &color0;
	color1 = &color1;
	split0 = &split0;
	split1 = &split1;
	dpi0 = &dpi0;
	dsi0 = &dsi0;
	dsi1 = &dsi1;
	mdp_rdma0 = &mdp_rdma0;
	mdp_rdma1 = &mdp_rdma1;
	mdp_rsz0 = &mdp_rsz0;
	mdp_rsz1 = &mdp_rsz1;
	mdp_rsz2 = &mdp_rsz2;
	mdp_wdma0 = &mdp_wdma0;
	mdp_wrot0 = &mdp_wrot0;
	mdp_wrot1 = &mdp_wrot1;
	};

	cluster0_opp: opp_table0 {
	compatible = "operating-points-v2";
	opp-shared;
	opp-507000000 {
	opp-hz = /bits/ 64 <507000000>;
	opp-microvolt = <859000>;
	};
	opp-702000000 {
	opp-hz = /bits/ 64 <702000000>;
	opp-microvolt = <908000>;
	};
	opp-1001000000 {
	opp-hz = /bits/ 64 <1001000000>;
	opp-microvolt = <983000>;
	};
	opp-1105000000 {
	opp-hz = /bits/ 64 <1105000000>;
	opp-microvolt = <1009000>;
	};
	opp-1209000000 {
	opp-hz = /bits/ 64 <1209000000>;
	opp-microvolt = <1034000>;
	};
	opp-1300000000 {
	opp-hz = /bits/ 64 <1300000000>;
	opp-microvolt = <1057000>;
	};
	opp-1508000000 {
	opp-hz = /bits/ 64 <1508000000>;
	opp-microvolt = <1109000>;
	};
	opp-1703000000 {
	opp-hz = /bits/ 64 <1703000000>;
	opp-microvolt = <1125000>;
	};
	};

	cluster1_opp: opp_table1 {
	compatible = "operating-points-v2";
	opp-shared;
	opp-507000000 {
	opp-hz = /bits/ 64 <507000000>;
	opp-microvolt = <828000>;
	};
	opp-702000000 {
	opp-hz = /bits/ 64 <702000000>;
	opp-microvolt = <867000>;
	};
	opp-1001000000 {
	opp-hz = /bits/ 64 <1001000000>;
	opp-microvolt = <927000>;
	};
	opp-1209000000 {
	opp-hz = /bits/ 64 <1209000000>;
	opp-microvolt = <968000>;
	};
	opp-1404000000 {
	opp-hz = /bits/ 64 <1404000000>;
	opp-microvolt = <1007000>;
	};
	opp-1612000000 {
	opp-hz = /bits/ 64 <1612000000>;
	opp-microvolt = <1049000>;
	};
	opp-1807000000 {
	opp-hz = /bits/ 64 <1807000000>;
	opp-microvolt = <1089000>;
	};
	opp-2106000000 {
	opp-hz = /bits/ 64 <2106000000>;
	opp-microvolt = <1125000>;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu-map {
	cluster0 {
	core0 {
	cpu = <&cpu0>;
	};
	core1 {
	cpu = <&cpu1>;
	};
	};

	cluster1 {
	core0 {
	cpu = <&cpu2>;
	};
	core1 {
	cpu = <&cpu3>;
	};
	};
	};

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x000>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	#cooling-cells = <2>;
	dynamic-power-coefficient = <263>;
	clocks = <&infracfg CLK_INFRA_CA53SEL>,
	<&apmixedsys CLK_APMIXED_MAINPLL>;
	clock-names = "cpu", "intermediate";
	operating-points-v2 = <&cluster0_opp>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x001>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	#cooling-cells = <2>;
	dynamic-power-coefficient = <263>;
	clocks = <&infracfg CLK_INFRA_CA53SEL>,
	<&apmixedsys CLK_APMIXED_MAINPLL>;
	clock-names = "cpu", "intermediate";
	operating-points-v2 = <&cluster0_opp>;
	};

	cpu2: cpu@100 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	reg = <0x100>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	#cooling-cells = <2>;
	dynamic-power-coefficient = <530>;
	clocks = <&infracfg CLK_INFRA_CA72SEL>,
	<&apmixedsys CLK_APMIXED_MAINPLL>;
	clock-names = "cpu", "intermediate";
	operating-points-v2 = <&cluster1_opp>;
	};

	cpu3: cpu@101 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	reg = <0x101>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	#cooling-cells = <2>;
	dynamic-power-coefficient = <530>;
	clocks = <&infracfg CLK_INFRA_CA72SEL>,
	<&apmixedsys CLK_APMIXED_MAINPLL>;
	clock-names = "cpu", "intermediate";
	operating-points-v2 = <&cluster1_opp>;
	};

	idle-states {
	entry-method = "psci";

	CPU_SLEEP_0: cpu-sleep-0 {
	compatible = "arm,idle-state";
	local-timer-stop;
	entry-latency-us = <639>;
	exit-latency-us = <680>;
	min-residency-us = <1088>;
	arm,psci-suspend-param = <0x0010000>;
	};
	};
	};

	pmu_a53 {
	compatible = "arm,cortex-a53-pmu";
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
	interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	pmu_a72 {
	compatible = "arm,cortex-a72-pmu";
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
	interrupt-affinity = <&cpu2>, <&cpu3>;
	};

	psci {
	compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
	method = "smc";
	cpu_suspend = <0x84000001>;
	cpu_off = <0x84000002>;
	cpu_on = <0x84000003>;
	};

	clk26m: oscillator@0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <26000000>;
	clock-output-names = "clk26m";
	};

	clk32k: oscillator@1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32000>;
	clock-output-names = "clk32k";
	};

	cpum_ck: oscillator@2 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	clock-output-names = "cpum_ck";
	};

	thermal-zones {
	cpu_thermal: cpu_thermal {
	polling-delay-passive = <1000>; /* milliseconds */
	polling-delay = <1000>; /* milliseconds */

	thermal-sensors = <&thermal>;
	sustainable-power = <1500>; /* milliwatts */

	trips {
	threshold: trip-point@0 {
	temperature = <68000>;
	hysteresis = <2000>;
	type = "passive";
	};

	target: trip-point@1 {
	temperature = <85000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu_crit: cpu_crit@0 {
	temperature = <115000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map@0 {
	trip = <&target>;
	cooling-device = <&cpu0 0 0>,
	<&cpu1 0 0>;
	contribution = <3072>;
	};
	map@1 {
	trip = <&target>;
	cooling-device = <&cpu2 0 0>,
	<&cpu3 0 0>;
	contribution = <1024>;
	};
	};
	};
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	vpu_dma_reserved: vpu_dma_mem_region {
	compatible = "shared-dma-pool";
	reg = <0 0xb7000000 0 0x500000>;
	alignment = <0x1000>;
	no-map;
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupt-parent = <&gic>;
	interrupts = <GIC_PPI 13
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	+ arm,no-tick-in-suspend;
	};

	soc {
	#address-cells = <2>;
	#size-cells = <2>;
	compatible = "simple-bus";
	ranges;

	topckgen: clock-controller@10000000 {
	compatible = "mediatek,mt8173-topckgen";
	reg = <0 0x10000000 0 0x1000>;
	#clock-cells = <1>;
	};

	infracfg: power-controller@10001000 {
	compatible = "mediatek,mt8173-infracfg", "syscon";
	reg = <0 0x10001000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pericfg: power-controller@10003000 {
	compatible = "mediatek,mt8173-pericfg", "syscon";
	reg = <0 0x10003000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	syscfg_pctl_a: syscfg_pctl_a@10005000 {
	compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
	reg = <0 0x10005000 0 0x1000>;
	};

	pio: pinctrl@10005000 {
	compatible = "mediatek,mt8173-pinctrl";
	reg = <0 0x1000b000 0 0x1000>;
	mediatek,pctl-regmap = <&syscfg_pctl_a>;
	pins-are-numbered;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;

	hdmi_pin: xxx {

	/hdmi htplg pin/
	pins1 {
	pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
	input-enable;
	bias-pull-down;
	};
	};

	i2c0_pins_a: i2c0 {
	pins1 {
	pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
	<MT8173_PIN_46_SCL0__FUNC_SCL0>;
	bias-disable;
	};
	};

	i2c1_pins_a: i2c1 {
	pins1 {
	pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
	<MT8173_PIN_126_SCL1__FUNC_SCL1>;
	bias-disable;
	};
	};

	i2c2_pins_a: i2c2 {
	pins1 {
	pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
	<MT8173_PIN_44_SCL2__FUNC_SCL2>;
	bias-disable;
	};
	};

	i2c3_pins_a: i2c3 {
	pins1 {
	pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
	<MT8173_PIN_107_SCL3__FUNC_SCL3>;
	bias-disable;
	};
	};

	i2c4_pins_a: i2c4 {
	pins1 {
	pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
	<MT8173_PIN_134_SCL4__FUNC_SCL4>;
	bias-disable;
	};
	};

	i2c6_pins_a: i2c6 {
	pins1 {
	pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
	<MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
	bias-disable;
	};
	};
	};

	- scpsys: scpsys@10006000 {
	+ scpsys: power-controller@10006000 {
	compatible = "mediatek,mt8173-scpsys";
	#power-domain-cells = <1>;
	reg = <0 0x10006000 0 0x1000>;
	clocks = <&clk26m>,
	<&topckgen CLK_TOP_MM_SEL>,
	<&topckgen CLK_TOP_VENC_SEL>,
	<&topckgen CLK_TOP_VENC_LT_SEL>;
	clock-names = "mfg", "mm", "venc", "venc_lt";
	infracfg = <&infracfg>;
	};

	watchdog: watchdog@10007000 {
	compatible = "mediatek,mt8173-wdt",
	"mediatek,mt6589-wdt";
	reg = <0 0x10007000 0 0x100>;
	};

	timer: timer@10008000 {
	compatible = "mediatek,mt8173-timer",
	"mediatek,mt6577-timer";
	reg = <0 0x10008000 0 0x1000>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_CLK_13M>,
	<&topckgen CLK_TOP_RTC_SEL>;
	};

	pwrap: pwrap@1000d000 {
	compatible = "mediatek,mt8173-pwrap";
	reg = <0 0x1000d000 0 0x1000>;
	reg-names = "pwrap";
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
	reset-names = "pwrap";
	clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
	clock-names = "spi", "wrap";
	};

	cec: cec@10013000 {
	compatible = "mediatek,mt8173-cec";
	reg = <0 0x10013000 0 0xbc>;
	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_CEC>;
	status = "disabled";
	};

	vpu: vpu@10020000 {
	compatible = "mediatek,mt8173-vpu";
	reg = <0 0x10020000 0 0x30000>,
	<0 0x10050000 0 0x100>;
	reg-names = "tcm", "cfg_reg";
	interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&topckgen CLK_TOP_SCP_SEL>;
	clock-names = "main";
	memory-region = <&vpu_dma_reserved>;
	};

	sysirq: intpol-controller@10200620 {
	compatible = "mediatek,mt8173-sysirq",
	"mediatek,mt6577-sysirq";
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	reg = <0 0x10200620 0 0x20>;
	};

	iommu: iommu@10205000 {
	compatible = "mediatek,mt8173-m4u";
	reg = <0 0x10205000 0 0x1000>;
	interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_M4U>;
	clock-names = "bclk";
	mediatek,larbs = <&larb0 &larb1 &larb2
	&larb3 &larb4 &larb5>;
	#iommu-cells = <1>;
	};

	efuse: efuse@10206000 {
	compatible = "mediatek,mt8173-efuse";
	reg = <0 0x10206000 0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	thermal_calibration: calib@528 {
	reg = <0x528 0xc>;
	};
	};

	apmixedsys: clock-controller@10209000 {
	compatible = "mediatek,mt8173-apmixedsys";
	reg = <0 0x10209000 0 0x1000>;
	#clock-cells = <1>;
	};

	hdmi_phy: hdmi-phy@10209100 {
	compatible = "mediatek,mt8173-hdmi-phy";
	reg = <0 0x10209100 0 0x24>;
	clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
	clock-names = "pll_ref";
	clock-output-names = "hdmitx_dig_cts";
	mediatek,ibias = <0xa>;
	mediatek,ibias_up = <0x1c>;
	#clock-cells = <0>;
	#phy-cells = <0>;
	status = "disabled";
	};

	gce: mailbox@10212000 {
	compatible = "mediatek,mt8173-gce";
	reg = <0 0x10212000 0 0x1000>;
	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_GCE>;
	clock-names = "gce";
	#mbox-cells = <3>;
	};

	mipi_tx0: mipi-dphy@10215000 {
	compatible = "mediatek,mt8173-mipi-tx";
	reg = <0 0x10215000 0 0x1000>;
	clocks = <&clk26m>;
	clock-output-names = "mipi_tx0_pll";
	#clock-cells = <0>;
	#phy-cells = <0>;
	status = "disabled";
	};

	mipi_tx1: mipi-dphy@10216000 {
	compatible = "mediatek,mt8173-mipi-tx";
	reg = <0 0x10216000 0 0x1000>;
	clocks = <&clk26m>;
	clock-output-names = "mipi_tx1_pll";
	#clock-cells = <0>;
	#phy-cells = <0>;
	status = "disabled";
	};

	gic: interrupt-controller@10220000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	interrupt-controller;
	reg = <0 0x10221000 0 0x1000>,
	<0 0x10222000 0 0x2000>,
	<0 0x10224000 0 0x2000>,
	<0 0x10226000 0 0x2000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	auxadc: auxadc@11001000 {
	compatible = "mediatek,mt8173-auxadc";
	reg = <0 0x11001000 0 0x1000>;
	clocks = <&pericfg CLK_PERI_AUXADC>;
	clock-names = "main";
	#io-channel-cells = <1>;
	};

	uart0: serial@11002000 {
	compatible = "mediatek,mt8173-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11002000 0 0x400>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart1: serial@11003000 {
	compatible = "mediatek,mt8173-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11003000 0 0x400>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart2: serial@11004000 {
	compatible = "mediatek,mt8173-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11004000 0 0x400>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart3: serial@11005000 {
	compatible = "mediatek,mt8173-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11005000 0 0x400>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	i2c0: i2c@11007000 {
	compatible = "mediatek,mt8173-i2c";
	reg = <0 0x11007000 0 0x70>,
	<0 0x11000100 0 0x80>;
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C0>,
	<&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main", "dma";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins_a>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c1: i2c@11008000 {
	compatible = "mediatek,mt8173-i2c";
	reg = <0 0x11008000 0 0x70>,
	<0 0x11000180 0 0x80>;
	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C1>,
	<&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main", "dma";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins_a>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c2: i2c@11009000 {
	compatible = "mediatek,mt8173-i2c";
	reg = <0 0x11009000 0 0x70>,
	<0 0x11000200 0 0x80>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C2>,
	<&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main", "dma";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins_a>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi: spi@1100a000 {
	compatible = "mediatek,mt8173-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x1100a000 0 0x1000>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	<&topckgen CLK_TOP_SPI_SEL>,
	<&pericfg CLK_PERI_SPI0>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	thermal: thermal@1100b000 {
	#thermal-sensor-cells = <0>;
	compatible = "mediatek,mt8173-thermal";
	reg = <0 0x1100b000 0 0x1000>;
	interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
	clock-names = "therm", "auxadc";
	resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
	mediatek,auxadc = <&auxadc>;
	mediatek,apmixedsys = <&apmixedsys>;
	nvmem-cells = <&thermal_calibration>;
	nvmem-cell-names = "calibration-data";
	};

	nor_flash: spi@1100d000 {
	compatible = "mediatek,mt8173-nor";
	reg = <0 0x1100d000 0 0xe0>;
	clocks = <&pericfg CLK_PERI_SPI>,
	<&topckgen CLK_TOP_SPINFI_IFR_SEL>;
	clock-names = "spi", "sf";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c3: i2c@11010000 {
	compatible = "mediatek,mt8173-i2c";
	reg = <0 0x11010000 0 0x70>,
	<0 0x11000280 0 0x80>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C3>,
	<&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main", "dma";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins_a>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c4: i2c@11011000 {
	compatible = "mediatek,mt8173-i2c";
	reg = <0 0x11011000 0 0x70>,
	<0 0x11000300 0 0x80>;
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C4>,
	<&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main", "dma";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins_a>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	hdmiddc0: i2c@11012000 {
	compatible = "mediatek,mt8173-hdmi-ddc";
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
	reg = <0 0x11012000 0 0x1C>;
	clocks = <&pericfg CLK_PERI_I2C5>;
	clock-names = "ddc-i2c";
	};

	i2c6: i2c@11013000 {
	compatible = "mediatek,mt8173-i2c";
	reg = <0 0x11013000 0 0x70>,
	<0 0x11000080 0 0x80>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C6>,
	<&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main", "dma";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c6_pins_a>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	afe: audio-controller@11220000 {
	compatible = "mediatek,mt8173-afe-pcm";
	reg = <0 0x11220000 0 0x1000>;
	interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
	clocks = <&infracfg CLK_INFRA_AUDIO>,
	<&topckgen CLK_TOP_AUDIO_SEL>,
	<&topckgen CLK_TOP_AUD_INTBUS_SEL>,
	<&topckgen CLK_TOP_APLL1_DIV0>,
	<&topckgen CLK_TOP_APLL2_DIV0>,
	<&topckgen CLK_TOP_I2S0_M_SEL>,
	<&topckgen CLK_TOP_I2S1_M_SEL>,
	<&topckgen CLK_TOP_I2S2_M_SEL>,
	<&topckgen CLK_TOP_I2S3_M_SEL>,
	<&topckgen CLK_TOP_I2S3_B_SEL>;
	clock-names = "infra_sys_audio_clk",
	"top_pdn_audio",
	"top_pdn_aud_intbus",
	"bck0",
	"bck1",
	"i2s0_m",
	"i2s1_m",
	"i2s2_m",
	"i2s3_m",
	"i2s3_b";
	assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
	<&topckgen CLK_TOP_AUD_2_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
	<&topckgen CLK_TOP_APLL2>;
	};

	mmc0: mmc@11230000 {
	compatible = "mediatek,mt8173-mmc";
	reg = <0 0x11230000 0 0x1000>;
	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_MSDC30_0>,
	<&topckgen CLK_TOP_MSDC50_0_H_SEL>;
	clock-names = "source", "hclk";
	status = "disabled";
	};

	mmc1: mmc@11240000 {
	compatible = "mediatek,mt8173-mmc";
	reg = <0 0x11240000 0 0x1000>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_MSDC30_1>,
	<&topckgen CLK_TOP_AXI_SEL>;
	clock-names = "source", "hclk";
	status = "disabled";
	};

	mmc2: mmc@11250000 {
	compatible = "mediatek,mt8173-mmc";
	reg = <0 0x11250000 0 0x1000>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_MSDC30_2>,
	<&topckgen CLK_TOP_AXI_SEL>;
	clock-names = "source", "hclk";
	status = "disabled";
	};

	mmc3: mmc@11260000 {
	compatible = "mediatek,mt8173-mmc";
	reg = <0 0x11260000 0 0x1000>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_MSDC30_3>,
	<&topckgen CLK_TOP_MSDC50_2_H_SEL>;
	clock-names = "source", "hclk";
	status = "disabled";
	};

	ssusb: usb@11271000 {
	compatible = "mediatek,mt8173-mtu3";
	reg = <0 0x11271000 0 0x3000>,
	<0 0x11280700 0 0x0100>;
	reg-names = "mac", "ippc";
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
	phys = <&u2port0 PHY_TYPE_USB2>,
	<&u3port0 PHY_TYPE_USB3>,
	<&u2port1 PHY_TYPE_USB2>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
	clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
	clock-names = "sys_ck", "ref_ck";
	mediatek,syscon-wakeup = <&pericfg 0x400 1>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "disabled";

	usb_host: xhci@11270000 {
	compatible = "mediatek,mt8173-xhci";
	reg = <0 0x11270000 0 0x1000>;
	reg-names = "mac";
	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
	clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
	clock-names = "sys_ck", "ref_ck";
	status = "disabled";
	};
	};

	u3phy: usb-phy@11290000 {
	compatible = "mediatek,mt8173-u3phy";
	reg = <0 0x11290000 0 0x800>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "okay";

	u2port0: usb-phy@11290800 {
	reg = <0 0x11290800 0 0x100>;
	clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};

	u3port0: usb-phy@11290900 {
	reg = <0 0x11290900 0 0x700>;
	clocks = <&clk26m>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};

	u2port1: usb-phy@11291000 {
	reg = <0 0x11291000 0 0x100>;
	clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};
	};

	mmsys: clock-controller@14000000 {
	compatible = "mediatek,mt8173-mmsys", "syscon";
	reg = <0 0x14000000 0 0x1000>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
	assigned-clock-rates = <400000000>;
	#clock-cells = <1>;
	};

	mdp_rdma0: rdma@14001000 {
	compatible = "mediatek,mt8173-mdp-rdma",
	"mediatek,mt8173-mdp";
	reg = <0 0x14001000 0 0x1000>;
	clocks = <&mmsys CLK_MM_MDP_RDMA0>,
	<&mmsys CLK_MM_MUTEX_32K>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	iommus = <&iommu M4U_PORT_MDP_RDMA0>;
	mediatek,larb = <&larb0>;
	mediatek,vpu = <&vpu>;
	};

	mdp_rdma1: rdma@14002000 {
	compatible = "mediatek,mt8173-mdp-rdma";
	reg = <0 0x14002000 0 0x1000>;
	clocks = <&mmsys CLK_MM_MDP_RDMA1>,
	<&mmsys CLK_MM_MUTEX_32K>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	iommus = <&iommu M4U_PORT_MDP_RDMA1>;
	mediatek,larb = <&larb4>;
	};

	mdp_rsz0: rsz@14003000 {
	compatible = "mediatek,mt8173-mdp-rsz";
	reg = <0 0x14003000 0 0x1000>;
	clocks = <&mmsys CLK_MM_MDP_RSZ0>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	};

	mdp_rsz1: rsz@14004000 {
	compatible = "mediatek,mt8173-mdp-rsz";
	reg = <0 0x14004000 0 0x1000>;
	clocks = <&mmsys CLK_MM_MDP_RSZ1>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	};

	mdp_rsz2: rsz@14005000 {
	compatible = "mediatek,mt8173-mdp-rsz";
	reg = <0 0x14005000 0 0x1000>;
	clocks = <&mmsys CLK_MM_MDP_RSZ2>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	};

	mdp_wdma0: wdma@14006000 {
	compatible = "mediatek,mt8173-mdp-wdma";
	reg = <0 0x14006000 0 0x1000>;
	clocks = <&mmsys CLK_MM_MDP_WDMA>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	iommus = <&iommu M4U_PORT_MDP_WDMA>;
	mediatek,larb = <&larb0>;
	};

	mdp_wrot0: wrot@14007000 {
	compatible = "mediatek,mt8173-mdp-wrot";
	reg = <0 0x14007000 0 0x1000>;
	clocks = <&mmsys CLK_MM_MDP_WROT0>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	iommus = <&iommu M4U_PORT_MDP_WROT0>;
	mediatek,larb = <&larb0>;
	};

	mdp_wrot1: wrot@14008000 {
	compatible = "mediatek,mt8173-mdp-wrot";
	reg = <0 0x14008000 0 0x1000>;
	clocks = <&mmsys CLK_MM_MDP_WROT1>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	iommus = <&iommu M4U_PORT_MDP_WROT1>;
	mediatek,larb = <&larb4>;
	};

	ovl0: ovl@1400c000 {
	compatible = "mediatek,mt8173-disp-ovl";
	reg = <0 0x1400c000 0 0x1000>;
	interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_OVL0>;
	iommus = <&iommu M4U_PORT_DISP_OVL0>;
	mediatek,larb = <&larb0>;
	};

	ovl1: ovl@1400d000 {
	compatible = "mediatek,mt8173-disp-ovl";
	reg = <0 0x1400d000 0 0x1000>;
	interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_OVL1>;
	iommus = <&iommu M4U_PORT_DISP_OVL1>;
	mediatek,larb = <&larb4>;
	};

	rdma0: rdma@1400e000 {
	compatible = "mediatek,mt8173-disp-rdma";
	reg = <0 0x1400e000 0 0x1000>;
	interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_RDMA0>;
	iommus = <&iommu M4U_PORT_DISP_RDMA0>;
	mediatek,larb = <&larb0>;
	};

	rdma1: rdma@1400f000 {
	compatible = "mediatek,mt8173-disp-rdma";
	reg = <0 0x1400f000 0 0x1000>;
	interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_RDMA1>;
	iommus = <&iommu M4U_PORT_DISP_RDMA1>;
	mediatek,larb = <&larb4>;
	};

	rdma2: rdma@14010000 {
	compatible = "mediatek,mt8173-disp-rdma";
	reg = <0 0x14010000 0 0x1000>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_RDMA2>;
	iommus = <&iommu M4U_PORT_DISP_RDMA2>;
	mediatek,larb = <&larb4>;
	};

	wdma0: wdma@14011000 {
	compatible = "mediatek,mt8173-disp-wdma";
	reg = <0 0x14011000 0 0x1000>;
	interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_WDMA0>;
	iommus = <&iommu M4U_PORT_DISP_WDMA0>;
	mediatek,larb = <&larb0>;
	};

	wdma1: wdma@14012000 {
	compatible = "mediatek,mt8173-disp-wdma";
	reg = <0 0x14012000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_WDMA1>;
	iommus = <&iommu M4U_PORT_DISP_WDMA1>;
	mediatek,larb = <&larb4>;
	};

	color0: color@14013000 {
	compatible = "mediatek,mt8173-disp-color";
	reg = <0 0x14013000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_COLOR0>;
	};

	color1: color@14014000 {
	compatible = "mediatek,mt8173-disp-color";
	reg = <0 0x14014000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_COLOR1>;
	};

	aal@14015000 {
	compatible = "mediatek,mt8173-disp-aal";
	reg = <0 0x14015000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_AAL>;
	};

	gamma@14016000 {
	compatible = "mediatek,mt8173-disp-gamma";
	reg = <0 0x14016000 0 0x1000>;
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_GAMMA>;
	};

	merge@14017000 {
	compatible = "mediatek,mt8173-disp-merge";
	reg = <0 0x14017000 0 0x1000>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_MERGE>;
	};

	split0: split@14018000 {
	compatible = "mediatek,mt8173-disp-split";
	reg = <0 0x14018000 0 0x1000>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
	};

	split1: split@14019000 {
	compatible = "mediatek,mt8173-disp-split";
	reg = <0 0x14019000 0 0x1000>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
	};

	ufoe@1401a000 {
	compatible = "mediatek,mt8173-disp-ufoe";
	reg = <0 0x1401a000 0 0x1000>;
	interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_UFOE>;
	};

	dsi0: dsi@1401b000 {
	compatible = "mediatek,mt8173-dsi";
	reg = <0 0x1401b000 0 0x1000>;
	interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
	<&mmsys CLK_MM_DSI0_DIGITAL>,
	<&mipi_tx0>;
	clock-names = "engine", "digital", "hs";
	phys = <&mipi_tx0>;
	phy-names = "dphy";
	status = "disabled";
	};

	dsi1: dsi@1401c000 {
	compatible = "mediatek,mt8173-dsi";
	reg = <0 0x1401c000 0 0x1000>;
	interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
	<&mmsys CLK_MM_DSI1_DIGITAL>,
	<&mipi_tx1>;
	clock-names = "engine", "digital", "hs";
	phy = <&mipi_tx1>;
	phy-names = "dphy";
	status = "disabled";
	};

	dpi0: dpi@1401d000 {
	compatible = "mediatek,mt8173-dpi";
	reg = <0 0x1401d000 0 0x1000>;
	interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DPI_PIXEL>,
	<&mmsys CLK_MM_DPI_ENGINE>,
	<&apmixedsys CLK_APMIXED_TVDPLL>;
	clock-names = "pixel", "engine", "pll";
	status = "disabled";

	port {
	dpi0_out: endpoint {
	remote-endpoint = <&hdmi0_in>;
	};
	};
	};

	pwm0: pwm@1401e000 {
	compatible = "mediatek,mt8173-disp-pwm",
	"mediatek,mt6595-disp-pwm";
	reg = <0 0x1401e000 0 0x1000>;
	#pwm-cells = <2>;
	clocks = <&mmsys CLK_MM_DISP_PWM026M>,
	<&mmsys CLK_MM_DISP_PWM0MM>;
	clock-names = "main", "mm";
	status = "disabled";
	};

	pwm1: pwm@1401f000 {
	compatible = "mediatek,mt8173-disp-pwm",
	"mediatek,mt6595-disp-pwm";
	reg = <0 0x1401f000 0 0x1000>;
	#pwm-cells = <2>;
	clocks = <&mmsys CLK_MM_DISP_PWM126M>,
	<&mmsys CLK_MM_DISP_PWM1MM>;
	clock-names = "main", "mm";
	status = "disabled";
	};

	mutex: mutex@14020000 {
	compatible = "mediatek,mt8173-disp-mutex";
	reg = <0 0x14020000 0 0x1000>;
	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_MUTEX_32K>;
	};

	larb0: larb@14021000 {
	compatible = "mediatek,mt8173-smi-larb";
	reg = <0 0x14021000 0 0x1000>;
	mediatek,smi = <&smi_common>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_SMI_LARB0>,
	<&mmsys CLK_MM_SMI_LARB0>;
	clock-names = "apb", "smi";
	};

	smi_common: smi@14022000 {
	compatible = "mediatek,mt8173-smi-common";
	reg = <0 0x14022000 0 0x1000>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_SMI_COMMON>,
	<&mmsys CLK_MM_SMI_COMMON>;
	clock-names = "apb", "smi";
	};

	od@14023000 {
	compatible = "mediatek,mt8173-disp-od";
	reg = <0 0x14023000 0 0x1000>;
	clocks = <&mmsys CLK_MM_DISP_OD>;
	};

	hdmi0: hdmi@14025000 {
	compatible = "mediatek,mt8173-hdmi";
	reg = <0 0x14025000 0 0x400>;
	interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
	<&mmsys CLK_MM_HDMI_PLLCK>,
	<&mmsys CLK_MM_HDMI_AUDIO>,
	<&mmsys CLK_MM_HDMI_SPDIF>;
	clock-names = "pixel", "pll", "bclk", "spdif";
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_pin>;
	phys = <&hdmi_phy>;
	phy-names = "hdmi";
	mediatek,syscon-hdmi = <&mmsys 0x900>;
	assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
	assigned-clock-parents = <&hdmi_phy>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	hdmi0_in: endpoint {
	remote-endpoint = <&dpi0_out>;
	};
	};
	};
	};

	larb4: larb@14027000 {
	compatible = "mediatek,mt8173-smi-larb";
	reg = <0 0x14027000 0 0x1000>;
	mediatek,smi = <&smi_common>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_SMI_LARB4>,
	<&mmsys CLK_MM_SMI_LARB4>;
	clock-names = "apb", "smi";
	};

	imgsys: clock-controller@15000000 {
	compatible = "mediatek,mt8173-imgsys", "syscon";
	reg = <0 0x15000000 0 0x1000>;
	#clock-cells = <1>;
	};

	larb2: larb@15001000 {
	compatible = "mediatek,mt8173-smi-larb";
	reg = <0 0x15001000 0 0x1000>;
	mediatek,smi = <&smi_common>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
	clocks = <&imgsys CLK_IMG_LARB2_SMI>,
	<&imgsys CLK_IMG_LARB2_SMI>;
	clock-names = "apb", "smi";
	};

	vdecsys: clock-controller@16000000 {
	compatible = "mediatek,mt8173-vdecsys", "syscon";
	reg = <0 0x16000000 0 0x1000>;
	#clock-cells = <1>;
	};

	vcodec_dec: vcodec@16000000 {
	compatible = "mediatek,mt8173-vcodec-dec";
	reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
	<0 0x16020000 0 0x1000>, /* VDEC_MISC */
	<0 0x16021000 0 0x800>, /* VDEC_LD */
	<0 0x16021800 0 0x800>, /* VDEC_TOP */
	<0 0x16022000 0 0x1000>, /* VDEC_CM */
	<0 0x16023000 0 0x1000>, /* VDEC_AD */
	<0 0x16024000 0 0x1000>, /* VDEC_AV */
	<0 0x16025000 0 0x1000>, /* VDEC_PP */
	<0 0x16026800 0 0x800>, /* VDEC_HWD */
	<0 0x16027000 0 0x800>, /* VDEC_HWQ */
	<0 0x16027800 0 0x800>, /* VDEC_HWB */
	<0 0x16028400 0 0x400>; /* VDEC_HWG */
	interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
	mediatek,larb = <&larb1>;
	iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
	<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
	<&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
	<&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
	<&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
	<&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
	<&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
	<&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
	mediatek,vpu = <&vpu>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
	clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
	<&topckgen CLK_TOP_UNIVPLL_D2>,
	<&topckgen CLK_TOP_CCI400_SEL>,
	<&topckgen CLK_TOP_VDEC_SEL>,
	<&topckgen CLK_TOP_VCODECPLL>,
	<&apmixedsys CLK_APMIXED_VENCPLL>,
	<&topckgen CLK_TOP_VENC_LT_SEL>,
	<&topckgen CLK_TOP_VCODECPLL_370P5>;
	clock-names = "vcodecpll",
	"univpll_d2",
	"clk_cci400_sel",
	"vdec_sel",
	"vdecpll",
	"vencpll",
	"venc_lt_sel",
	"vdec_bus_clk_src";
	assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
	<&topckgen CLK_TOP_CCI400_SEL>,
	<&topckgen CLK_TOP_VDEC_SEL>,
	<&apmixedsys CLK_APMIXED_VCODECPLL>,
	<&apmixedsys CLK_APMIXED_VENCPLL>;
	assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
	<&topckgen CLK_TOP_UNIVPLL_D2>,
	<&topckgen CLK_TOP_VCODECPLL>;
	assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
	};

	larb1: larb@16010000 {
	compatible = "mediatek,mt8173-smi-larb";
	reg = <0 0x16010000 0 0x1000>;
	mediatek,smi = <&smi_common>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
	clocks = <&vdecsys CLK_VDEC_CKEN>,
	<&vdecsys CLK_VDEC_LARB_CKEN>;
	clock-names = "apb", "smi";
	};

	vencsys: clock-controller@18000000 {
	compatible = "mediatek,mt8173-vencsys", "syscon";
	reg = <0 0x18000000 0 0x1000>;
	#clock-cells = <1>;
	};

	larb3: larb@18001000 {
	compatible = "mediatek,mt8173-smi-larb";
	reg = <0 0x18001000 0 0x1000>;
	mediatek,smi = <&smi_common>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
	clocks = <&vencsys CLK_VENC_CKE1>,
	<&vencsys CLK_VENC_CKE0>;
	clock-names = "apb", "smi";
	};

	vcodec_enc: vcodec@18002000 {
	compatible = "mediatek,mt8173-vcodec-enc";
	reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
	<0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
	interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
	mediatek,larb = <&larb3>,
	<&larb5>;
	iommus = <&iommu M4U_PORT_VENC_RCPU>,
	<&iommu M4U_PORT_VENC_REC>,
	<&iommu M4U_PORT_VENC_BSDMA>,
	<&iommu M4U_PORT_VENC_SV_COMV>,
	<&iommu M4U_PORT_VENC_RD_COMV>,
	<&iommu M4U_PORT_VENC_CUR_LUMA>,
	<&iommu M4U_PORT_VENC_CUR_CHROMA>,
	<&iommu M4U_PORT_VENC_REF_LUMA>,
	<&iommu M4U_PORT_VENC_REF_CHROMA>,
	<&iommu M4U_PORT_VENC_NBM_RDMA>,
	<&iommu M4U_PORT_VENC_NBM_WDMA>,
	<&iommu M4U_PORT_VENC_RCPU_SET2>,
	<&iommu M4U_PORT_VENC_REC_FRM_SET2>,
	<&iommu M4U_PORT_VENC_BSDMA_SET2>,
	<&iommu M4U_PORT_VENC_SV_COMA_SET2>,
	<&iommu M4U_PORT_VENC_RD_COMA_SET2>,
	<&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
	<&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
	<&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
	<&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
	mediatek,vpu = <&vpu>;
	clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
	<&topckgen CLK_TOP_VENC_SEL>,
	<&topckgen CLK_TOP_UNIVPLL1_D2>,
	<&topckgen CLK_TOP_VENC_LT_SEL>;
	clock-names = "venc_sel_src",
	"venc_sel",
	"venc_lt_sel_src",
	"venc_lt_sel";
	assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
	<&topckgen CLK_TOP_VENC_LT_SEL>;
	- assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
	- <&topckgen CLK_TOP_UNIVPLL1_D2>;
	+ assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>,
	+ <&topckgen CLK_TOP_VCODECPLL_370P5>;
	};

	jpegdec: jpegdec@18004000 {
	compatible = "mediatek,mt8173-jpgdec";
	reg = <0 0x18004000 0 0x1000>;
	interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&vencsys CLK_VENC_CKE0>,
	<&vencsys CLK_VENC_CKE3>;
	clock-names = "jpgdec-smi",
	"jpgdec";
	power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
	mediatek,larb = <&larb3>;
	iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,
	<&iommu M4U_PORT_JPGDEC_BSDMA>;
	};

	vencltsys: clock-controller@19000000 {
	compatible = "mediatek,mt8173-vencltsys", "syscon";
	reg = <0 0x19000000 0 0x1000>;
	#clock-cells = <1>;
	};

	larb5: larb@19001000 {
	compatible = "mediatek,mt8173-smi-larb";
	reg = <0 0x19001000 0 0x1000>;
	mediatek,smi = <&smi_common>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
	clocks = <&vencltsys CLK_VENCLT_CKE1>,
	<&vencltsys CLK_VENCLT_CKE0>;
	clock-names = "apb", "smi";
	};
	};
	};

	diff --git a/sys/gnu/dts/arm64/mediatek/mt8183.dtsi b/sys/gnu/dts/arm64/mediatek/mt8183.dtsi
	index 124f9d3e09f5..97863adb7bc0 100644
	--- a/sys/gnu/dts/arm64/mediatek/mt8183.dtsi
	+++ b/sys/gnu/dts/arm64/mediatek/mt8183.dtsi
	@@ -1,656 +1,709 @@
	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	/*
	* Copyright (c) 2018 MediaTek Inc.
	* Author: Ben Ho <ben.ho@mediatek.com>
	* Erin Lo <erin.lo@mediatek.com>
	*/

	#include <dt-bindings/clock/mt8183-clk.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/reset-controller/mt8183-resets.h>
	#include "mt8183-pinfunc.h"

	/ {
	compatible = "mediatek,mt8183";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	i2c6 = &i2c6;
	i2c7 = &i2c7;
	i2c8 = &i2c8;
	i2c9 = &i2c9;
	i2c10 = &i2c10;
	i2c11 = &i2c11;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu-map {
	cluster0 {
	core0 {
	cpu = <&cpu0>;
	};
	core1 {
	cpu = <&cpu1>;
	};
	core2 {
	cpu = <&cpu2>;
	};
	core3 {
	cpu = <&cpu3>;
	};
	};

	cluster1 {
	core0 {
	cpu = <&cpu4>;
	};
	core1 {
	cpu = <&cpu5>;
	};
	core2 {
	cpu = <&cpu6>;
	};
	core3 {
	cpu = <&cpu7>;
	};
	};
	};

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x000>;
	enable-method = "psci";
	capacity-dmips-mhz = <741>;
	+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	+ dynamic-power-coefficient = <84>;
	+ #cooling-cells = <2>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x001>;
	enable-method = "psci";
	capacity-dmips-mhz = <741>;
	+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	+ dynamic-power-coefficient = <84>;
	+ #cooling-cells = <2>;
	};

	cpu2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x002>;
	enable-method = "psci";
	capacity-dmips-mhz = <741>;
	+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	+ dynamic-power-coefficient = <84>;
	+ #cooling-cells = <2>;
	};

	cpu3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x003>;
	enable-method = "psci";
	capacity-dmips-mhz = <741>;
	+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	+ dynamic-power-coefficient = <84>;
	+ #cooling-cells = <2>;
	};

	cpu4: cpu@100 {
	device_type = "cpu";
	compatible = "arm,cortex-a73";
	reg = <0x100>;
	enable-method = "psci";
	capacity-dmips-mhz = <1024>;
	+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	+ dynamic-power-coefficient = <211>;
	+ #cooling-cells = <2>;
	};

	cpu5: cpu@101 {
	device_type = "cpu";
	compatible = "arm,cortex-a73";
	reg = <0x101>;
	enable-method = "psci";
	capacity-dmips-mhz = <1024>;
	+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	+ dynamic-power-coefficient = <211>;
	+ #cooling-cells = <2>;
	};

	cpu6: cpu@102 {
	device_type = "cpu";
	compatible = "arm,cortex-a73";
	reg = <0x102>;
	enable-method = "psci";
	capacity-dmips-mhz = <1024>;
	+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	+ dynamic-power-coefficient = <211>;
	+ #cooling-cells = <2>;
	};

	cpu7: cpu@103 {
	device_type = "cpu";
	compatible = "arm,cortex-a73";
	reg = <0x103>;
	enable-method = "psci";
	capacity-dmips-mhz = <1024>;
	+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	+ dynamic-power-coefficient = <211>;
	+ #cooling-cells = <2>;
	+ };
	+
	+ idle-states {
	+ entry-method = "psci";
	+
	+ CPU_SLEEP: cpu-sleep {
	+ compatible = "arm,idle-state";
	+ local-timer-stop;
	+ arm,psci-suspend-param = <0x00010001>;
	+ entry-latency-us = <200>;
	+ exit-latency-us = <200>;
	+ min-residency-us = <800>;
	+ };
	+
	+ CLUSTER_SLEEP: cluster-sleep {
	+ compatible = "arm,idle-state";
	+ local-timer-stop;
	+ arm,psci-suspend-param = <0x01010001>;
	+ entry-latency-us = <250>;
	+ exit-latency-us = <400>;
	+ min-residency-us = <1300>;
	+ };
	};
	};

	pmu-a53 {
	compatible = "arm,cortex-a53-pmu";
	interrupt-parent = <&gic>;
	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
	};

	pmu-a73 {
	compatible = "arm,cortex-a73-pmu";
	interrupt-parent = <&gic>;
	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	clk26m: oscillator {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <26000000>;
	clock-output-names = "clk26m";
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupt-parent = <&gic>;
	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
	};

	soc {
	#address-cells = <2>;
	#size-cells = <2>;
	compatible = "simple-bus";
	ranges;

	soc_data: soc_data@8000000 {
	compatible = "mediatek,mt8183-efuse",
	"mediatek,efuse";
	reg = <0 0x08000000 0 0x0010>;
	#address-cells = <1>;
	#size-cells = <1>;
	status = "disabled";
	};

	gic: interrupt-controller@c000000 {
	compatible = "arm,gic-v3";
	#interrupt-cells = <4>;
	interrupt-parent = <&gic>;
	interrupt-controller;
	reg = <0 0x0c000000 0 0x40000>, /* GICD */
	<0 0x0c100000 0 0x200000>, /* GICR */
	<0 0x0c400000 0 0x2000>, /* GICC */
	<0 0x0c410000 0 0x1000>, /* GICH */
	<0 0x0c420000 0 0x2000>; /* GICV */

	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
	ppi-partitions {
	ppi_cluster0: interrupt-partition-0 {
	affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
	};
	ppi_cluster1: interrupt-partition-1 {
	affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
	};
	};
	};

	mcucfg: syscon@c530000 {
	compatible = "mediatek,mt8183-mcucfg", "syscon";
	reg = <0 0x0c530000 0 0x1000>;
	#clock-cells = <1>;
	};

	sysirq: interrupt-controller@c530a80 {
	compatible = "mediatek,mt8183-sysirq",
	"mediatek,mt6577-sysirq";
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	reg = <0 0x0c530a80 0 0x50>;
	};

	topckgen: syscon@10000000 {
	compatible = "mediatek,mt8183-topckgen", "syscon";
	reg = <0 0x10000000 0 0x1000>;
	#clock-cells = <1>;
	};

	infracfg: syscon@10001000 {
	compatible = "mediatek,mt8183-infracfg", "syscon";
	reg = <0 0x10001000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pio: pinctrl@10005000 {
	compatible = "mediatek,mt8183-pinctrl";
	reg = <0 0x10005000 0 0x1000>,
	<0 0x11f20000 0 0x1000>,
	<0 0x11e80000 0 0x1000>,
	<0 0x11e70000 0 0x1000>,
	<0 0x11e90000 0 0x1000>,
	<0 0x11d30000 0 0x1000>,
	<0 0x11d20000 0 0x1000>,
	<0 0x11c50000 0 0x1000>,
	<0 0x11f30000 0 0x1000>,
	<0 0x1000b000 0 0x1000>;
	reg-names = "iocfg0", "iocfg1", "iocfg2",
	"iocfg3", "iocfg4", "iocfg5",
	"iocfg6", "iocfg7", "iocfg8",
	"eint";
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pio 0 0 192>;
	interrupt-controller;
	interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <2>;
	};

	+ watchdog: watchdog@10007000 {
	+ compatible = "mediatek,mt8183-wdt",
	+ "mediatek,mt6589-wdt";
	+ reg = <0 0x10007000 0 0x100>;
	+ #reset-cells = <1>;
	+ };
	+
	apmixedsys: syscon@1000c000 {
	compatible = "mediatek,mt8183-apmixedsys", "syscon";
	reg = <0 0x1000c000 0 0x1000>;
	#clock-cells = <1>;
	};

	pwrap: pwrap@1000d000 {
	compatible = "mediatek,mt8183-pwrap";
	reg = <0 0x1000d000 0 0x1000>;
	reg-names = "pwrap";
	interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
	<&infracfg CLK_INFRA_PMIC_AP>;
	clock-names = "spi", "wrap";
	};

	systimer: timer@10017000 {
	compatible = "mediatek,mt8183-timer",
	"mediatek,mt6765-timer";
	reg = <0 0x10017000 0 0x1000>;
	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&topckgen CLK_TOP_CLK13M>;
	clock-names = "clk13m";
	};

	gce: mailbox@10238000 {
	compatible = "mediatek,mt8183-gce";
	reg = <0 0x10238000 0 0x4000>;
	interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
	#mbox-cells = <3>;
	clocks = <&infracfg CLK_INFRA_GCE>;
	clock-names = "gce";
	};

	auxadc: auxadc@11001000 {
	compatible = "mediatek,mt8183-auxadc",
	"mediatek,mt8173-auxadc";
	reg = <0 0x11001000 0 0x1000>;
	clocks = <&infracfg CLK_INFRA_AUXADC>;
	clock-names = "main";
	#io-channel-cells = <1>;
	status = "disabled";
	};

	uart0: serial@11002000 {
	compatible = "mediatek,mt8183-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11002000 0 0x1000>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart1: serial@11003000 {
	compatible = "mediatek,mt8183-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11003000 0 0x1000>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart2: serial@11004000 {
	compatible = "mediatek,mt8183-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11004000 0 0x1000>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	i2c6: i2c@11005000 {
	compatible = "mediatek,mt8183-i2c";
	reg = <0 0x11005000 0 0x1000>,
	<0 0x11000600 0 0x80>;
	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_I2C6>,
	<&infracfg CLK_INFRA_AP_DMA>;
	clock-names = "main", "dma";
	clock-div = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c0: i2c@11007000 {
	compatible = "mediatek,mt8183-i2c";
	reg = <0 0x11007000 0 0x1000>,
	<0 0x11000080 0 0x80>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_I2C0>,
	<&infracfg CLK_INFRA_AP_DMA>;
	clock-names = "main", "dma";
	clock-div = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c4: i2c@11008000 {
	compatible = "mediatek,mt8183-i2c";
	reg = <0 0x11008000 0 0x1000>,
	<0 0x11000100 0 0x80>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_I2C1>,
	<&infracfg CLK_INFRA_AP_DMA>,
	<&infracfg CLK_INFRA_I2C1_ARBITER>;
	clock-names = "main", "dma","arb";
	clock-div = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c2: i2c@11009000 {
	compatible = "mediatek,mt8183-i2c";
	reg = <0 0x11009000 0 0x1000>,
	<0 0x11000280 0 0x80>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_I2C2>,
	<&infracfg CLK_INFRA_AP_DMA>,
	<&infracfg CLK_INFRA_I2C2_ARBITER>;
	clock-names = "main", "dma", "arb";
	clock-div = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi0: spi@1100a000 {
	compatible = "mediatek,mt8183-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x1100a000 0 0x1000>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
	<&topckgen CLK_TOP_MUX_SPI>,
	<&infracfg CLK_INFRA_SPI0>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	i2c3: i2c@1100f000 {
	compatible = "mediatek,mt8183-i2c";
	reg = <0 0x1100f000 0 0x1000>,
	<0 0x11000400 0 0x80>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_I2C3>,
	<&infracfg CLK_INFRA_AP_DMA>;
	clock-names = "main", "dma";
	clock-div = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi1: spi@11010000 {
	compatible = "mediatek,mt8183-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x11010000 0 0x1000>;
	interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
	<&topckgen CLK_TOP_MUX_SPI>,
	<&infracfg CLK_INFRA_SPI1>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	i2c1: i2c@11011000 {
	compatible = "mediatek,mt8183-i2c";
	reg = <0 0x11011000 0 0x1000>,
	<0 0x11000480 0 0x80>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_I2C4>,
	<&infracfg CLK_INFRA_AP_DMA>;
	clock-names = "main", "dma";
	clock-div = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi2: spi@11012000 {
	compatible = "mediatek,mt8183-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x11012000 0 0x1000>;
	interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
	<&topckgen CLK_TOP_MUX_SPI>,
	<&infracfg CLK_INFRA_SPI2>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	spi3: spi@11013000 {
	compatible = "mediatek,mt8183-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x11013000 0 0x1000>;
	interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
	<&topckgen CLK_TOP_MUX_SPI>,
	<&infracfg CLK_INFRA_SPI3>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	i2c9: i2c@11014000 {
	compatible = "mediatek,mt8183-i2c";
	reg = <0 0x11014000 0 0x1000>,
	<0 0x11000180 0 0x80>;
	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
	<&infracfg CLK_INFRA_AP_DMA>,
	<&infracfg CLK_INFRA_I2C1_ARBITER>;
	clock-names = "main", "dma", "arb";
	clock-div = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c10: i2c@11015000 {
	compatible = "mediatek,mt8183-i2c";
	reg = <0 0x11015000 0 0x1000>,
	<0 0x11000300 0 0x80>;
	interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
	<&infracfg CLK_INFRA_AP_DMA>,
	<&infracfg CLK_INFRA_I2C2_ARBITER>;
	clock-names = "main", "dma", "arb";
	clock-div = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c5: i2c@11016000 {
	compatible = "mediatek,mt8183-i2c";
	reg = <0 0x11016000 0 0x1000>,
	<0 0x11000500 0 0x80>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_I2C5>,
	<&infracfg CLK_INFRA_AP_DMA>,
	<&infracfg CLK_INFRA_I2C5_ARBITER>;
	clock-names = "main", "dma", "arb";
	clock-div = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c11: i2c@11017000 {
	compatible = "mediatek,mt8183-i2c";
	reg = <0 0x11017000 0 0x1000>,
	<0 0x11000580 0 0x80>;
	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
	<&infracfg CLK_INFRA_AP_DMA>,
	<&infracfg CLK_INFRA_I2C5_ARBITER>;
	clock-names = "main", "dma", "arb";
	clock-div = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi4: spi@11018000 {
	compatible = "mediatek,mt8183-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x11018000 0 0x1000>;
	interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
	<&topckgen CLK_TOP_MUX_SPI>,
	<&infracfg CLK_INFRA_SPI4>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	spi5: spi@11019000 {
	compatible = "mediatek,mt8183-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x11019000 0 0x1000>;
	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
	<&topckgen CLK_TOP_MUX_SPI>,
	<&infracfg CLK_INFRA_SPI5>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	i2c7: i2c@1101a000 {
	compatible = "mediatek,mt8183-i2c";
	reg = <0 0x1101a000 0 0x1000>,
	<0 0x11000680 0 0x80>;
	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_I2C7>,
	<&infracfg CLK_INFRA_AP_DMA>;
	clock-names = "main", "dma";
	clock-div = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c8: i2c@1101b000 {
	compatible = "mediatek,mt8183-i2c";
	reg = <0 0x1101b000 0 0x1000>,
	<0 0x11000700 0 0x80>;
	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_I2C8>,
	<&infracfg CLK_INFRA_AP_DMA>;
	clock-names = "main", "dma";
	clock-div = <1>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	audiosys: syscon@11220000 {
	compatible = "mediatek,mt8183-audiosys", "syscon";
	reg = <0 0x11220000 0 0x1000>;
	#clock-cells = <1>;
	};

	efuse: efuse@11f10000 {
	compatible = "mediatek,mt8183-efuse",
	"mediatek,efuse";
	reg = <0 0x11f10000 0 0x1000>;
	};

	mfgcfg: syscon@13000000 {
	compatible = "mediatek,mt8183-mfgcfg", "syscon";
	reg = <0 0x13000000 0 0x1000>;
	#clock-cells = <1>;
	};

	mmsys: syscon@14000000 {
	compatible = "mediatek,mt8183-mmsys", "syscon";
	reg = <0 0x14000000 0 0x1000>;
	#clock-cells = <1>;
	};

	imgsys: syscon@15020000 {
	compatible = "mediatek,mt8183-imgsys", "syscon";
	reg = <0 0x15020000 0 0x1000>;
	#clock-cells = <1>;
	};

	vdecsys: syscon@16000000 {
	compatible = "mediatek,mt8183-vdecsys", "syscon";
	reg = <0 0x16000000 0 0x1000>;
	#clock-cells = <1>;
	};

	vencsys: syscon@17000000 {
	compatible = "mediatek,mt8183-vencsys", "syscon";
	reg = <0 0x17000000 0 0x1000>;
	#clock-cells = <1>;
	};

	ipu_conn: syscon@19000000 {
	compatible = "mediatek,mt8183-ipu_conn", "syscon";
	reg = <0 0x19000000 0 0x1000>;
	#clock-cells = <1>;
	};

	ipu_adl: syscon@19010000 {
	compatible = "mediatek,mt8183-ipu_adl", "syscon";
	reg = <0 0x19010000 0 0x1000>;
	#clock-cells = <1>;
	};

	ipu_core0: syscon@19180000 {
	compatible = "mediatek,mt8183-ipu_core0", "syscon";
	reg = <0 0x19180000 0 0x1000>;
	#clock-cells = <1>;
	};

	ipu_core1: syscon@19280000 {
	compatible = "mediatek,mt8183-ipu_core1", "syscon";
	reg = <0 0x19280000 0 0x1000>;
	#clock-cells = <1>;
	};

	camsys: syscon@1a000000 {
	compatible = "mediatek,mt8183-camsys", "syscon";
	reg = <0 0x1a000000 0 0x1000>;
	#clock-cells = <1>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/mediatek/mt8516-pinfunc.h b/sys/gnu/dts/arm64/mediatek/mt8516-pinfunc.h
	new file mode 100644
	index 000000000000..73339bb48f0d
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/mediatek/mt8516-pinfunc.h
	@@ -0,0 +1,663 @@
	+/* SPDX-License-Identifier: GPL-2.0 */
	+/*
	+ * Copyright (C) 2019 MediaTek Inc.
	+ */
	+#ifndef __DTS_MT8516_PINFUNC_H
	+#define __DTS_MT8516_PINFUNC_H
	+
	+#include <dt-bindings/pinctrl/mt65xx.h>
	+
	+#define MT8516_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) \| 0)
	+#define MT8516_PIN_0_EINT0__FUNC_PWM_B (MTK_PIN_NO(0) \| 1)
	+#define MT8516_PIN_0_EINT0__FUNC_I2S2_BCK (MTK_PIN_NO(0) \| 3)
	+#define MT8516_PIN_0_EINT0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) \| 4)
	+#define MT8516_PIN_0_EINT0__FUNC_SQICS (MTK_PIN_NO(0) \| 6)
	+#define MT8516_PIN_0_EINT0__FUNC_DBG_MON_A_6 (MTK_PIN_NO(0) \| 7)
	+
	+#define MT8516_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) \| 0)
	+#define MT8516_PIN_1_EINT1__FUNC_PWM_C (MTK_PIN_NO(1) \| 1)
	+#define MT8516_PIN_1_EINT1__FUNC_I2S2_DI (MTK_PIN_NO(1) \| 3)
	+#define MT8516_PIN_1_EINT1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) \| 4)
	+#define MT8516_PIN_1_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(1) \| 5)
	+#define MT8516_PIN_1_EINT1__FUNC_SQISO (MTK_PIN_NO(1) \| 6)
	+#define MT8516_PIN_1_EINT1__FUNC_DBG_MON_A_7 (MTK_PIN_NO(1) \| 7)
	+
	+#define MT8516_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) \| 0)
	+#define MT8516_PIN_2_EINT2__FUNC_CLKM0 (MTK_PIN_NO(2) \| 1)
	+#define MT8516_PIN_2_EINT2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) \| 3)
	+#define MT8516_PIN_2_EINT2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) \| 4)
	+#define MT8516_PIN_2_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(2) \| 5)
	+#define MT8516_PIN_2_EINT2__FUNC_SQISI (MTK_PIN_NO(2) \| 6)
	+#define MT8516_PIN_2_EINT2__FUNC_DBG_MON_A_8 (MTK_PIN_NO(2) \| 7)
	+
	+#define MT8516_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) \| 0)
	+#define MT8516_PIN_3_EINT3__FUNC_CLKM1 (MTK_PIN_NO(3) \| 1)
	+#define MT8516_PIN_3_EINT3__FUNC_SPI_MI (MTK_PIN_NO(3) \| 3)
	+#define MT8516_PIN_3_EINT3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) \| 4)
	+#define MT8516_PIN_3_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(3) \| 5)
	+#define MT8516_PIN_3_EINT3__FUNC_SQIWP (MTK_PIN_NO(3) \| 6)
	+#define MT8516_PIN_3_EINT3__FUNC_DBG_MON_A_9 (MTK_PIN_NO(3) \| 7)
	+
	+#define MT8516_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) \| 0)
	+#define MT8516_PIN_4_EINT4__FUNC_CLKM2 (MTK_PIN_NO(4) \| 1)
	+#define MT8516_PIN_4_EINT4__FUNC_SPI_MO (MTK_PIN_NO(4) \| 3)
	+#define MT8516_PIN_4_EINT4__FUNC_EXT_TXC (MTK_PIN_NO(4) \| 4)
	+#define MT8516_PIN_4_EINT4__FUNC_CONN_MCU_TCK (MTK_PIN_NO(4) \| 5)
	+#define MT8516_PIN_4_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(4) \| 6)
	+#define MT8516_PIN_4_EINT4__FUNC_DBG_MON_A_10 (MTK_PIN_NO(4) \| 7)
	+
	+#define MT8516_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) \| 0)
	+#define MT8516_PIN_5_EINT5__FUNC_UCTS2 (MTK_PIN_NO(5) \| 1)
	+#define MT8516_PIN_5_EINT5__FUNC_SPI_CSB (MTK_PIN_NO(5) \| 3)
	+#define MT8516_PIN_5_EINT5__FUNC_EXT_RXER (MTK_PIN_NO(5) \| 4)
	+#define MT8516_PIN_5_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(5) \| 5)
	+#define MT8516_PIN_5_EINT5__FUNC_CONN_TEST_CK (MTK_PIN_NO(5) \| 6)
	+#define MT8516_PIN_5_EINT5__FUNC_DBG_MON_A_11 (MTK_PIN_NO(5) \| 7)
	+
	+#define MT8516_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) \| 0)
	+#define MT8516_PIN_6_EINT6__FUNC_URTS2 (MTK_PIN_NO(6) \| 1)
	+#define MT8516_PIN_6_EINT6__FUNC_SPI_CLK (MTK_PIN_NO(6) \| 3)
	+#define MT8516_PIN_6_EINT6__FUNC_EXT_RXC (MTK_PIN_NO(6) \| 4)
	+#define MT8516_PIN_6_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(6) \| 5)
	+#define MT8516_PIN_6_EINT6__FUNC_DBG_MON_A_12 (MTK_PIN_NO(6) \| 7)
	+
	+#define MT8516_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) \| 0)
	+#define MT8516_PIN_7_EINT7__FUNC_SQIRST (MTK_PIN_NO(7) \| 1)
	+#define MT8516_PIN_7_EINT7__FUNC_SDA1_0 (MTK_PIN_NO(7) \| 3)
	+#define MT8516_PIN_7_EINT7__FUNC_EXT_RXDV (MTK_PIN_NO(7) \| 4)
	+#define MT8516_PIN_7_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(7) \| 5)
	+#define MT8516_PIN_7_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(7) \| 6)
	+#define MT8516_PIN_7_EINT7__FUNC_DBG_MON_A_13 (MTK_PIN_NO(7) \| 7)
	+
	+#define MT8516_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) \| 0)
	+#define MT8516_PIN_8_EINT8__FUNC_SQICK (MTK_PIN_NO(8) \| 1)
	+#define MT8516_PIN_8_EINT8__FUNC_CLKM3 (MTK_PIN_NO(8) \| 2)
	+#define MT8516_PIN_8_EINT8__FUNC_SCL1_0 (MTK_PIN_NO(8) \| 3)
	+#define MT8516_PIN_8_EINT8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) \| 4)
	+#define MT8516_PIN_8_EINT8__FUNC_ANT_SEL0 (MTK_PIN_NO(8) \| 5)
	+#define MT8516_PIN_8_EINT8__FUNC_DBG_MON_A_14 (MTK_PIN_NO(8) \| 7)
	+
	+#define MT8516_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) \| 0)
	+#define MT8516_PIN_9_EINT9__FUNC_CLKM4 (MTK_PIN_NO(9) \| 1)
	+#define MT8516_PIN_9_EINT9__FUNC_SDA2_0 (MTK_PIN_NO(9) \| 2)
	+#define MT8516_PIN_9_EINT9__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) \| 3)
	+#define MT8516_PIN_9_EINT9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) \| 4)
	+#define MT8516_PIN_9_EINT9__FUNC_ANT_SEL1 (MTK_PIN_NO(9) \| 5)
	+#define MT8516_PIN_9_EINT9__FUNC_DBG_MON_A_15 (MTK_PIN_NO(9) \| 7)
	+
	+#define MT8516_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) \| 0)
	+#define MT8516_PIN_10_EINT10__FUNC_CLKM5 (MTK_PIN_NO(10) \| 1)
	+#define MT8516_PIN_10_EINT10__FUNC_SCL2_0 (MTK_PIN_NO(10) \| 2)
	+#define MT8516_PIN_10_EINT10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) \| 3)
	+#define MT8516_PIN_10_EINT10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) \| 4)
	+#define MT8516_PIN_10_EINT10__FUNC_ANT_SEL2 (MTK_PIN_NO(10) \| 5)
	+#define MT8516_PIN_10_EINT10__FUNC_DBG_MON_A_16 (MTK_PIN_NO(10) \| 7)
	+
	+#define MT8516_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) \| 0)
	+#define MT8516_PIN_11_EINT11__FUNC_CLKM4 (MTK_PIN_NO(11) \| 1)
	+#define MT8516_PIN_11_EINT11__FUNC_PWM_C (MTK_PIN_NO(11) \| 2)
	+#define MT8516_PIN_11_EINT11__FUNC_CONN_TEST_CK (MTK_PIN_NO(11) \| 3)
	+#define MT8516_PIN_11_EINT11__FUNC_ANT_SEL3 (MTK_PIN_NO(11) \| 4)
	+#define MT8516_PIN_11_EINT11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) \| 6)
	+#define MT8516_PIN_11_EINT11__FUNC_DBG_MON_A_17 (MTK_PIN_NO(11) \| 7)
	+
	+#define MT8516_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) \| 0)
	+#define MT8516_PIN_12_EINT12__FUNC_CLKM5 (MTK_PIN_NO(12) \| 1)
	+#define MT8516_PIN_12_EINT12__FUNC_PWM_A (MTK_PIN_NO(12) \| 2)
	+#define MT8516_PIN_12_EINT12__FUNC_SPDIF_OUT (MTK_PIN_NO(12) \| 3)
	+#define MT8516_PIN_12_EINT12__FUNC_ANT_SEL4 (MTK_PIN_NO(12) \| 4)
	+#define MT8516_PIN_12_EINT12__FUNC_EXT_TXEN (MTK_PIN_NO(12) \| 6)
	+#define MT8516_PIN_12_EINT12__FUNC_DBG_MON_A_18 (MTK_PIN_NO(12) \| 7)
	+
	+#define MT8516_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) \| 0)
	+#define MT8516_PIN_13_EINT13__FUNC_TSF_IN (MTK_PIN_NO(13) \| 3)
	+#define MT8516_PIN_13_EINT13__FUNC_ANT_SEL5 (MTK_PIN_NO(13) \| 4)
	+#define MT8516_PIN_13_EINT13__FUNC_SPDIF_IN (MTK_PIN_NO(13) \| 6)
	+#define MT8516_PIN_13_EINT13__FUNC_DBG_MON_A_19 (MTK_PIN_NO(13) \| 7)
	+
	+#define MT8516_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) \| 0)
	+#define MT8516_PIN_14_EINT14__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(14) \| 2)
	+#define MT8516_PIN_14_EINT14__FUNC_TDM_RX_MCK (MTK_PIN_NO(14) \| 3)
	+#define MT8516_PIN_14_EINT14__FUNC_ANT_SEL1 (MTK_PIN_NO(14) \| 4)
	+#define MT8516_PIN_14_EINT14__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(14) \| 5)
	+#define MT8516_PIN_14_EINT14__FUNC_NCLE (MTK_PIN_NO(14) \| 6)
	+#define MT8516_PIN_14_EINT14__FUNC_DBG_MON_B_8 (MTK_PIN_NO(14) \| 7)
	+
	+#define MT8516_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) \| 0)
	+#define MT8516_PIN_15_EINT15__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(15) \| 2)
	+#define MT8516_PIN_15_EINT15__FUNC_TDM_RX_BCK (MTK_PIN_NO(15) \| 3)
	+#define MT8516_PIN_15_EINT15__FUNC_ANT_SEL2 (MTK_PIN_NO(15) \| 4)
	+#define MT8516_PIN_15_EINT15__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(15) \| 5)
	+#define MT8516_PIN_15_EINT15__FUNC_NCEB1 (MTK_PIN_NO(15) \| 6)
	+#define MT8516_PIN_15_EINT15__FUNC_DBG_MON_B_9 (MTK_PIN_NO(15) \| 7)
	+
	+#define MT8516_PIN_16_EINT16__FUNC_GPIO16 (MTK_PIN_NO(16) \| 0)
	+#define MT8516_PIN_16_EINT16__FUNC_I2S_8CH_BCK (MTK_PIN_NO(16) \| 2)
	+#define MT8516_PIN_16_EINT16__FUNC_TDM_RX_LRCK (MTK_PIN_NO(16) \| 3)
	+#define MT8516_PIN_16_EINT16__FUNC_ANT_SEL3 (MTK_PIN_NO(16) \| 4)
	+#define MT8516_PIN_16_EINT16__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(16) \| 5)
	+#define MT8516_PIN_16_EINT16__FUNC_NCEB0 (MTK_PIN_NO(16) \| 6)
	+#define MT8516_PIN_16_EINT16__FUNC_DBG_MON_B_10 (MTK_PIN_NO(16) \| 7)
	+
	+#define MT8516_PIN_17_EINT17__FUNC_GPIO17 (MTK_PIN_NO(17) \| 0)
	+#define MT8516_PIN_17_EINT17__FUNC_I2S_8CH_MCK (MTK_PIN_NO(17) \| 2)
	+#define MT8516_PIN_17_EINT17__FUNC_TDM_RX_DI (MTK_PIN_NO(17) \| 3)
	+#define MT8516_PIN_17_EINT17__FUNC_IDDIG (MTK_PIN_NO(17) \| 4)
	+#define MT8516_PIN_17_EINT17__FUNC_ANT_SEL4 (MTK_PIN_NO(17) \| 5)
	+#define MT8516_PIN_17_EINT17__FUNC_NREB (MTK_PIN_NO(17) \| 6)
	+#define MT8516_PIN_17_EINT17__FUNC_DBG_MON_B_11 (MTK_PIN_NO(17) \| 7)
	+
	+#define MT8516_PIN_18_EINT18__FUNC_GPIO18 (MTK_PIN_NO(18) \| 0)
	+#define MT8516_PIN_18_EINT18__FUNC_USB_DRVVBUS (MTK_PIN_NO(18) \| 2)
	+#define MT8516_PIN_18_EINT18__FUNC_I2S3_LRCK (MTK_PIN_NO(18) \| 3)
	+#define MT8516_PIN_18_EINT18__FUNC_CLKM1 (MTK_PIN_NO(18) \| 4)
	+#define MT8516_PIN_18_EINT18__FUNC_ANT_SEL3 (MTK_PIN_NO(18) \| 5)
	+#define MT8516_PIN_18_EINT18__FUNC_I2S2_BCK (MTK_PIN_NO(18) \| 6)
	+#define MT8516_PIN_18_EINT18__FUNC_DBG_MON_A_20 (MTK_PIN_NO(18) \| 7)
	+
	+#define MT8516_PIN_19_EINT19__FUNC_GPIO19 (MTK_PIN_NO(19) \| 0)
	+#define MT8516_PIN_19_EINT19__FUNC_UCTS1 (MTK_PIN_NO(19) \| 1)
	+#define MT8516_PIN_19_EINT19__FUNC_IDDIG (MTK_PIN_NO(19) \| 2)
	+#define MT8516_PIN_19_EINT19__FUNC_I2S3_BCK (MTK_PIN_NO(19) \| 3)
	+#define MT8516_PIN_19_EINT19__FUNC_CLKM2 (MTK_PIN_NO(19) \| 4)
	+#define MT8516_PIN_19_EINT19__FUNC_ANT_SEL4 (MTK_PIN_NO(19) \| 5)
	+#define MT8516_PIN_19_EINT19__FUNC_I2S2_DI (MTK_PIN_NO(19) \| 6)
	+#define MT8516_PIN_19_EINT19__FUNC_DBG_MON_A_21 (MTK_PIN_NO(19) \| 7)
	+
	+#define MT8516_PIN_20_EINT20__FUNC_GPIO20 (MTK_PIN_NO(20) \| 0)
	+#define MT8516_PIN_20_EINT20__FUNC_URTS1 (MTK_PIN_NO(20) \| 1)
	+#define MT8516_PIN_20_EINT20__FUNC_I2S3_DO (MTK_PIN_NO(20) \| 3)
	+#define MT8516_PIN_20_EINT20__FUNC_CLKM3 (MTK_PIN_NO(20) \| 4)
	+#define MT8516_PIN_20_EINT20__FUNC_ANT_SEL5 (MTK_PIN_NO(20) \| 5)
	+#define MT8516_PIN_20_EINT20__FUNC_I2S2_LRCK (MTK_PIN_NO(20) \| 6)
	+#define MT8516_PIN_20_EINT20__FUNC_DBG_MON_A_22 (MTK_PIN_NO(20) \| 7)
	+
	+#define MT8516_PIN_21_EINT21__FUNC_GPIO21 (MTK_PIN_NO(21) \| 0)
	+#define MT8516_PIN_21_EINT21__FUNC_NRNB (MTK_PIN_NO(21) \| 1)
	+#define MT8516_PIN_21_EINT21__FUNC_ANT_SEL0 (MTK_PIN_NO(21) \| 2)
	+#define MT8516_PIN_21_EINT21__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(21) \| 3)
	+#define MT8516_PIN_21_EINT21__FUNC_DBG_MON_B_31 (MTK_PIN_NO(21) \| 7)
	+
	+#define MT8516_PIN_22_EINT22__FUNC_GPIO22 (MTK_PIN_NO(22) \| 0)
	+#define MT8516_PIN_22_EINT22__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(22) \| 2)
	+#define MT8516_PIN_22_EINT22__FUNC_TSF_IN (MTK_PIN_NO(22) \| 3)
	+#define MT8516_PIN_22_EINT22__FUNC_USB_DRVVBUS (MTK_PIN_NO(22) \| 4)
	+#define MT8516_PIN_22_EINT22__FUNC_SPDIF_OUT (MTK_PIN_NO(22) \| 5)
	+#define MT8516_PIN_22_EINT22__FUNC_NRE_C (MTK_PIN_NO(22) \| 6)
	+#define MT8516_PIN_22_EINT22__FUNC_DBG_MON_B_12 (MTK_PIN_NO(22) \| 7)
	+
	+#define MT8516_PIN_23_EINT23__FUNC_GPIO23 (MTK_PIN_NO(23) \| 0)
	+#define MT8516_PIN_23_EINT23__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(23) \| 2)
	+#define MT8516_PIN_23_EINT23__FUNC_CLKM0 (MTK_PIN_NO(23) \| 3)
	+#define MT8516_PIN_23_EINT23__FUNC_IR (MTK_PIN_NO(23) \| 4)
	+#define MT8516_PIN_23_EINT23__FUNC_SPDIF_IN (MTK_PIN_NO(23) \| 5)
	+#define MT8516_PIN_23_EINT23__FUNC_NDQS_C (MTK_PIN_NO(23) \| 6)
	+#define MT8516_PIN_23_EINT23__FUNC_DBG_MON_B_13 (MTK_PIN_NO(23) \| 7)
	+
	+#define MT8516_PIN_24_EINT24__FUNC_GPIO24 (MTK_PIN_NO(24) \| 0)
	+#define MT8516_PIN_24_EINT24__FUNC_ANT_SEL1 (MTK_PIN_NO(24) \| 3)
	+#define MT8516_PIN_24_EINT24__FUNC_UCTS2 (MTK_PIN_NO(24) \| 4)
	+#define MT8516_PIN_24_EINT24__FUNC_PWM_A (MTK_PIN_NO(24) \| 5)
	+#define MT8516_PIN_24_EINT24__FUNC_I2S0_MCK (MTK_PIN_NO(24) \| 6)
	+#define MT8516_PIN_24_EINT24__FUNC_DBG_MON_A_0 (MTK_PIN_NO(24) \| 7)
	+
	+#define MT8516_PIN_25_EINT25__FUNC_GPIO25 (MTK_PIN_NO(25) \| 0)
	+#define MT8516_PIN_25_EINT25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) \| 3)
	+#define MT8516_PIN_25_EINT25__FUNC_URTS2 (MTK_PIN_NO(25) \| 4)
	+#define MT8516_PIN_25_EINT25__FUNC_PWM_B (MTK_PIN_NO(25) \| 5)
	+#define MT8516_PIN_25_EINT25__FUNC_I2S_8CH_MCK (MTK_PIN_NO(25) \| 6)
	+#define MT8516_PIN_25_EINT25__FUNC_DBG_MON_A_1 (MTK_PIN_NO(25) \| 7)
	+
	+#define MT8516_PIN_26_PWRAP_SPI0_MI__FUNC_GPIO26 (MTK_PIN_NO(26) \| 0)
	+#define MT8516_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(26) \| 1)
	+#define MT8516_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(26) \| 2)
	+
	+#define MT8516_PIN_27_PWRAP_SPI0_MO__FUNC_GPIO27 (MTK_PIN_NO(27) \| 0)
	+#define MT8516_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(27) \| 1)
	+#define MT8516_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(27) \| 2)
	+
	+#define MT8516_PIN_28_PWRAP_INT__FUNC_GPIO28 (MTK_PIN_NO(28) \| 0)
	+#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S0_MCK (MTK_PIN_NO(28) \| 1)
	+#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S_8CH_MCK (MTK_PIN_NO(28) \| 4)
	+#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S2_MCK (MTK_PIN_NO(28) \| 5)
	+#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S3_MCK (MTK_PIN_NO(28) \| 6)
	+
	+#define MT8516_PIN_29_PWRAP_SPI0_CK__FUNC_GPIO29 (MTK_PIN_NO(29) \| 0)
	+#define MT8516_PIN_29_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(29) \| 1)
	+
	+#define MT8516_PIN_30_PWRAP_SPI0_CSN__FUNC_GPIO30 (MTK_PIN_NO(30) \| 0)
	+#define MT8516_PIN_30_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(30) \| 1)
	+
	+#define MT8516_PIN_31_RTC32K_CK__FUNC_GPIO31 (MTK_PIN_NO(31) \| 0)
	+#define MT8516_PIN_31_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(31) \| 1)
	+
	+#define MT8516_PIN_32_WATCHDOG__FUNC_GPIO32 (MTK_PIN_NO(32) \| 0)
	+#define MT8516_PIN_32_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(32) \| 1)
	+
	+#define MT8516_PIN_33_SRCLKENA__FUNC_GPIO33 (MTK_PIN_NO(33) \| 0)
	+#define MT8516_PIN_33_SRCLKENA__FUNC_SRCLKENA0 (MTK_PIN_NO(33) \| 1)
	+
	+#define MT8516_PIN_34_URXD2__FUNC_GPIO34 (MTK_PIN_NO(34) \| 0)
	+#define MT8516_PIN_34_URXD2__FUNC_URXD2 (MTK_PIN_NO(34) \| 1)
	+#define MT8516_PIN_34_URXD2__FUNC_UTXD2 (MTK_PIN_NO(34) \| 3)
	+#define MT8516_PIN_34_URXD2__FUNC_DBG_SCL (MTK_PIN_NO(34) \| 4)
	+#define MT8516_PIN_34_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(34) \| 6)
	+#define MT8516_PIN_34_URXD2__FUNC_DBG_MON_B_0 (MTK_PIN_NO(34) \| 7)
	+
	+#define MT8516_PIN_35_UTXD2__FUNC_GPIO35 (MTK_PIN_NO(35) \| 0)
	+#define MT8516_PIN_35_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(35) \| 1)
	+#define MT8516_PIN_35_UTXD2__FUNC_URXD2 (MTK_PIN_NO(35) \| 3)
	+#define MT8516_PIN_35_UTXD2__FUNC_DBG_SDA (MTK_PIN_NO(35) \| 4)
	+#define MT8516_PIN_35_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(35) \| 6)
	+#define MT8516_PIN_35_UTXD2__FUNC_DBG_MON_B_1 (MTK_PIN_NO(35) \| 7)
	+
	+#define MT8516_PIN_36_MRG_CLK__FUNC_GPIO36 (MTK_PIN_NO(36) \| 0)
	+#define MT8516_PIN_36_MRG_CLK__FUNC_MRG_CLK (MTK_PIN_NO(36) \| 1)
	+#define MT8516_PIN_36_MRG_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(36) \| 3)
	+#define MT8516_PIN_36_MRG_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(36) \| 4)
	+#define MT8516_PIN_36_MRG_CLK__FUNC_PCM0_CLK (MTK_PIN_NO(36) \| 5)
	+#define MT8516_PIN_36_MRG_CLK__FUNC_IR (MTK_PIN_NO(36) \| 6)
	+#define MT8516_PIN_36_MRG_CLK__FUNC_DBG_MON_A_2 (MTK_PIN_NO(36) \| 7)
	+
	+#define MT8516_PIN_37_MRG_SYNC__FUNC_GPIO37 (MTK_PIN_NO(37) \| 0)
	+#define MT8516_PIN_37_MRG_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(37) \| 1)
	+#define MT8516_PIN_37_MRG_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(37) \| 3)
	+#define MT8516_PIN_37_MRG_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(37) \| 4)
	+#define MT8516_PIN_37_MRG_SYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(37) \| 5)
	+#define MT8516_PIN_37_MRG_SYNC__FUNC_EXT_COL (MTK_PIN_NO(37) \| 6)
	+#define MT8516_PIN_37_MRG_SYNC__FUNC_DBG_MON_A_3 (MTK_PIN_NO(37) \| 7)
	+
	+#define MT8516_PIN_38_MRG_DI__FUNC_GPIO38 (MTK_PIN_NO(38) \| 0)
	+#define MT8516_PIN_38_MRG_DI__FUNC_MRG_DI (MTK_PIN_NO(38) \| 1)
	+#define MT8516_PIN_38_MRG_DI__FUNC_I2S0_DI (MTK_PIN_NO(38) \| 3)
	+#define MT8516_PIN_38_MRG_DI__FUNC_I2S3_DO (MTK_PIN_NO(38) \| 4)
	+#define MT8516_PIN_38_MRG_DI__FUNC_PCM0_DI (MTK_PIN_NO(38) \| 5)
	+#define MT8516_PIN_38_MRG_DI__FUNC_EXT_MDIO (MTK_PIN_NO(38) \| 6)
	+#define MT8516_PIN_38_MRG_DI__FUNC_DBG_MON_A_4 (MTK_PIN_NO(38) \| 7)
	+
	+#define MT8516_PIN_39_MRG_DO__FUNC_GPIO39 (MTK_PIN_NO(39) \| 0)
	+#define MT8516_PIN_39_MRG_DO__FUNC_MRG_DO (MTK_PIN_NO(39) \| 1)
	+#define MT8516_PIN_39_MRG_DO__FUNC_I2S0_MCK (MTK_PIN_NO(39) \| 3)
	+#define MT8516_PIN_39_MRG_DO__FUNC_I2S3_MCK (MTK_PIN_NO(39) \| 4)
	+#define MT8516_PIN_39_MRG_DO__FUNC_PCM0_DO (MTK_PIN_NO(39) \| 5)
	+#define MT8516_PIN_39_MRG_DO__FUNC_EXT_MDC (MTK_PIN_NO(39) \| 6)
	+#define MT8516_PIN_39_MRG_DO__FUNC_DBG_MON_A_5 (MTK_PIN_NO(39) \| 7)
	+
	+#define MT8516_PIN_40_KPROW0__FUNC_GPIO40 (MTK_PIN_NO(40) \| 0)
	+#define MT8516_PIN_40_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(40) \| 1)
	+#define MT8516_PIN_40_KPROW0__FUNC_DBG_MON_B_4 (MTK_PIN_NO(40) \| 7)
	+
	+#define MT8516_PIN_41_KPROW1__FUNC_GPIO41 (MTK_PIN_NO(41) \| 0)
	+#define MT8516_PIN_41_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(41) \| 1)
	+#define MT8516_PIN_41_KPROW1__FUNC_IDDIG (MTK_PIN_NO(41) \| 2)
	+#define MT8516_PIN_41_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) \| 3)
	+#define MT8516_PIN_41_KPROW1__FUNC_DBG_MON_B_5 (MTK_PIN_NO(41) \| 7)
	+
	+#define MT8516_PIN_42_KPCOL0__FUNC_GPIO42 (MTK_PIN_NO(42) \| 0)
	+#define MT8516_PIN_42_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(42) \| 1)
	+#define MT8516_PIN_42_KPCOL0__FUNC_DBG_MON_B_6 (MTK_PIN_NO(42) \| 7)
	+
	+#define MT8516_PIN_43_KPCOL1__FUNC_GPIO43 (MTK_PIN_NO(43) \| 0)
	+#define MT8516_PIN_43_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(43) \| 1)
	+#define MT8516_PIN_43_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(43) \| 2)
	+#define MT8516_PIN_43_KPCOL1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(43) \| 3)
	+#define MT8516_PIN_43_KPCOL1__FUNC_TSF_IN (MTK_PIN_NO(43) \| 4)
	+#define MT8516_PIN_43_KPCOL1__FUNC_DBG_MON_B_7 (MTK_PIN_NO(43) \| 7)
	+
	+#define MT8516_PIN_44_JTMS__FUNC_GPIO44 (MTK_PIN_NO(44) \| 0)
	+#define MT8516_PIN_44_JTMS__FUNC_JTMS (MTK_PIN_NO(44) \| 1)
	+#define MT8516_PIN_44_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(44) \| 2)
	+#define MT8516_PIN_44_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(44) \| 3)
	+#define MT8516_PIN_44_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(44) \| 5)
	+#define MT8516_PIN_44_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(44) \| 6)
	+
	+#define MT8516_PIN_45_JTCK__FUNC_GPIO45 (MTK_PIN_NO(45) \| 0)
	+#define MT8516_PIN_45_JTCK__FUNC_JTCK (MTK_PIN_NO(45) \| 1)
	+#define MT8516_PIN_45_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(45) \| 2)
	+#define MT8516_PIN_45_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(45) \| 3)
	+
	+#define MT8516_PIN_46_JTDI__FUNC_GPIO46 (MTK_PIN_NO(46) \| 0)
	+#define MT8516_PIN_46_JTDI__FUNC_JTDI (MTK_PIN_NO(46) \| 1)
	+#define MT8516_PIN_46_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(46) \| 2)
	+
	+#define MT8516_PIN_47_JTDO__FUNC_GPIO47 (MTK_PIN_NO(47) \| 0)
	+#define MT8516_PIN_47_JTDO__FUNC_JTDO (MTK_PIN_NO(47) \| 1)
	+#define MT8516_PIN_47_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(47) \| 2)
	+
	+#define MT8516_PIN_48_SPI_CS__FUNC_GPIO48 (MTK_PIN_NO(48) \| 0)
	+#define MT8516_PIN_48_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(48) \| 1)
	+#define MT8516_PIN_48_SPI_CS__FUNC_I2S0_DI (MTK_PIN_NO(48) \| 3)
	+#define MT8516_PIN_48_SPI_CS__FUNC_I2S2_BCK (MTK_PIN_NO(48) \| 4)
	+#define MT8516_PIN_48_SPI_CS__FUNC_DBG_MON_A_23 (MTK_PIN_NO(48) \| 7)
	+
	+#define MT8516_PIN_49_SPI_CK__FUNC_GPIO49 (MTK_PIN_NO(49) \| 0)
	+#define MT8516_PIN_49_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(49) \| 1)
	+#define MT8516_PIN_49_SPI_CK__FUNC_I2S0_LRCK (MTK_PIN_NO(49) \| 3)
	+#define MT8516_PIN_49_SPI_CK__FUNC_I2S2_DI (MTK_PIN_NO(49) \| 4)
	+#define MT8516_PIN_49_SPI_CK__FUNC_DBG_MON_A_24 (MTK_PIN_NO(49) \| 7)
	+
	+#define MT8516_PIN_50_SPI_MI__FUNC_GPIO50 (MTK_PIN_NO(50) \| 0)
	+#define MT8516_PIN_50_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(50) \| 1)
	+#define MT8516_PIN_50_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(50) \| 2)
	+#define MT8516_PIN_50_SPI_MI__FUNC_I2S0_BCK (MTK_PIN_NO(50) \| 3)
	+#define MT8516_PIN_50_SPI_MI__FUNC_I2S2_LRCK (MTK_PIN_NO(50) \| 4)
	+#define MT8516_PIN_50_SPI_MI__FUNC_DBG_MON_A_25 (MTK_PIN_NO(50) \| 7)
	+
	+#define MT8516_PIN_51_SPI_MO__FUNC_GPIO51 (MTK_PIN_NO(51) \| 0)
	+#define MT8516_PIN_51_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(51) \| 1)
	+#define MT8516_PIN_51_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(51) \| 2)
	+#define MT8516_PIN_51_SPI_MO__FUNC_I2S0_MCK (MTK_PIN_NO(51) \| 3)
	+#define MT8516_PIN_51_SPI_MO__FUNC_I2S2_MCK (MTK_PIN_NO(51) \| 4)
	+#define MT8516_PIN_51_SPI_MO__FUNC_DBG_MON_A_26 (MTK_PIN_NO(51) \| 7)
	+
	+#define MT8516_PIN_52_SDA1__FUNC_GPIO52 (MTK_PIN_NO(52) \| 0)
	+#define MT8516_PIN_52_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(52) \| 1)
	+
	+#define MT8516_PIN_53_SCL1__FUNC_GPIO53 (MTK_PIN_NO(53) \| 0)
	+#define MT8516_PIN_53_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(53) \| 1)
	+
	+#define MT8516_PIN_54_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) \| 0)
	+#define MT8516_PIN_54_GPIO54__FUNC_PWM_B (MTK_PIN_NO(54) \| 2)
	+#define MT8516_PIN_54_GPIO54__FUNC_DBG_MON_B_2 (MTK_PIN_NO(54) \| 7)
	+
	+#define MT8516_PIN_55_I2S_DATA_IN__FUNC_GPIO55 (MTK_PIN_NO(55) \| 0)
	+#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(55) \| 1)
	+#define MT8516_PIN_55_I2S_DATA_IN__FUNC_UCTS0 (MTK_PIN_NO(55) \| 2)
	+#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(55) \| 3)
	+#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(55) \| 4)
	+#define MT8516_PIN_55_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(55) \| 5)
	+#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S2_BCK (MTK_PIN_NO(55) \| 6)
	+#define MT8516_PIN_55_I2S_DATA_IN__FUNC_DBG_MON_A_28 (MTK_PIN_NO(55) \| 7)
	+
	+#define MT8516_PIN_56_I2S_LRCK__FUNC_GPIO56 (MTK_PIN_NO(56) \| 0)
	+#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(56) \| 1)
	+#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(56) \| 3)
	+#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(56) \| 4)
	+#define MT8516_PIN_56_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(56) \| 5)
	+#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S2_DI (MTK_PIN_NO(56) \| 6)
	+#define MT8516_PIN_56_I2S_LRCK__FUNC_DBG_MON_A_29 (MTK_PIN_NO(56) \| 7)
	+
	+#define MT8516_PIN_57_I2S_BCK__FUNC_GPIO57 (MTK_PIN_NO(57) \| 0)
	+#define MT8516_PIN_57_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(57) \| 1)
	+#define MT8516_PIN_57_I2S_BCK__FUNC_URTS0 (MTK_PIN_NO(57) \| 2)
	+#define MT8516_PIN_57_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(57) \| 3)
	+#define MT8516_PIN_57_I2S_BCK__FUNC_I2S_8CH_BCK (MTK_PIN_NO(57) \| 4)
	+#define MT8516_PIN_57_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(57) \| 5)
	+#define MT8516_PIN_57_I2S_BCK__FUNC_I2S2_LRCK (MTK_PIN_NO(57) \| 6)
	+#define MT8516_PIN_57_I2S_BCK__FUNC_DBG_MON_A_30 (MTK_PIN_NO(57) \| 7)
	+
	+#define MT8516_PIN_58_SDA0__FUNC_GPIO58 (MTK_PIN_NO(58) \| 0)
	+#define MT8516_PIN_58_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(58) \| 1)
	+
	+#define MT8516_PIN_59_SCL0__FUNC_GPIO59 (MTK_PIN_NO(59) \| 0)
	+#define MT8516_PIN_59_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(59) \| 1)
	+
	+#define MT8516_PIN_60_SDA2__FUNC_GPIO60 (MTK_PIN_NO(60) \| 0)
	+#define MT8516_PIN_60_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(60) \| 1)
	+#define MT8516_PIN_60_SDA2__FUNC_PWM_B (MTK_PIN_NO(60) \| 2)
	+
	+#define MT8516_PIN_61_SCL2__FUNC_GPIO61 (MTK_PIN_NO(61) \| 0)
	+#define MT8516_PIN_61_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(61) \| 1)
	+#define MT8516_PIN_61_SCL2__FUNC_PWM_C (MTK_PIN_NO(61) \| 2)
	+
	+#define MT8516_PIN_62_URXD0__FUNC_GPIO62 (MTK_PIN_NO(62) \| 0)
	+#define MT8516_PIN_62_URXD0__FUNC_URXD0 (MTK_PIN_NO(62) \| 1)
	+#define MT8516_PIN_62_URXD0__FUNC_UTXD0 (MTK_PIN_NO(62) \| 2)
	+
	+#define MT8516_PIN_63_UTXD0__FUNC_GPIO63 (MTK_PIN_NO(63) \| 0)
	+#define MT8516_PIN_63_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(63) \| 1)
	+#define MT8516_PIN_63_UTXD0__FUNC_URXD0 (MTK_PIN_NO(63) \| 2)
	+
	+#define MT8516_PIN_64_URXD1__FUNC_GPIO64 (MTK_PIN_NO(64) \| 0)
	+#define MT8516_PIN_64_URXD1__FUNC_URXD1 (MTK_PIN_NO(64) \| 1)
	+#define MT8516_PIN_64_URXD1__FUNC_UTXD1 (MTK_PIN_NO(64) \| 2)
	+#define MT8516_PIN_64_URXD1__FUNC_DBG_MON_A_27 (MTK_PIN_NO(64) \| 7)
	+
	+#define MT8516_PIN_65_UTXD1__FUNC_GPIO65 (MTK_PIN_NO(65) \| 0)
	+#define MT8516_PIN_65_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(65) \| 1)
	+#define MT8516_PIN_65_UTXD1__FUNC_URXD1 (MTK_PIN_NO(65) \| 2)
	+#define MT8516_PIN_65_UTXD1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(65) \| 7)
	+
	+#define MT8516_PIN_68_MSDC2_CMD__FUNC_GPIO68 (MTK_PIN_NO(68) \| 0)
	+#define MT8516_PIN_68_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(68) \| 1)
	+#define MT8516_PIN_68_MSDC2_CMD__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(68) \| 2)
	+#define MT8516_PIN_68_MSDC2_CMD__FUNC_SDA1_0 (MTK_PIN_NO(68) \| 3)
	+#define MT8516_PIN_68_MSDC2_CMD__FUNC_USB_SDA (MTK_PIN_NO(68) \| 5)
	+#define MT8516_PIN_68_MSDC2_CMD__FUNC_I2S3_BCK (MTK_PIN_NO(68) \| 6)
	+#define MT8516_PIN_68_MSDC2_CMD__FUNC_DBG_MON_B_15 (MTK_PIN_NO(68) \| 7)
	+
	+#define MT8516_PIN_69_MSDC2_CLK__FUNC_GPIO69 (MTK_PIN_NO(69) \| 0)
	+#define MT8516_PIN_69_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(69) \| 1)
	+#define MT8516_PIN_69_MSDC2_CLK__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(69) \| 2)
	+#define MT8516_PIN_69_MSDC2_CLK__FUNC_SCL1_0 (MTK_PIN_NO(69) \| 3)
	+#define MT8516_PIN_69_MSDC2_CLK__FUNC_USB_SCL (MTK_PIN_NO(69) \| 5)
	+#define MT8516_PIN_69_MSDC2_CLK__FUNC_I2S3_LRCK (MTK_PIN_NO(69) \| 6)
	+#define MT8516_PIN_69_MSDC2_CLK__FUNC_DBG_MON_B_16 (MTK_PIN_NO(69) \| 7)
	+
	+#define MT8516_PIN_70_MSDC2_DAT0__FUNC_GPIO70 (MTK_PIN_NO(70) \| 0)
	+#define MT8516_PIN_70_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(70) \| 1)
	+#define MT8516_PIN_70_MSDC2_DAT0__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(70) \| 2)
	+#define MT8516_PIN_70_MSDC2_DAT0__FUNC_UTXD0 (MTK_PIN_NO(70) \| 5)
	+#define MT8516_PIN_70_MSDC2_DAT0__FUNC_I2S3_DO (MTK_PIN_NO(70) \| 6)
	+#define MT8516_PIN_70_MSDC2_DAT0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(70) \| 7)
	+
	+#define MT8516_PIN_71_MSDC2_DAT1__FUNC_GPIO71 (MTK_PIN_NO(71) \| 0)
	+#define MT8516_PIN_71_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(71) \| 1)
	+#define MT8516_PIN_71_MSDC2_DAT1__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(71) \| 2)
	+#define MT8516_PIN_71_MSDC2_DAT1__FUNC_PWM_A (MTK_PIN_NO(71) \| 3)
	+#define MT8516_PIN_71_MSDC2_DAT1__FUNC_I2S3_MCK (MTK_PIN_NO(71) \| 4)
	+#define MT8516_PIN_71_MSDC2_DAT1__FUNC_URXD0 (MTK_PIN_NO(71) \| 5)
	+#define MT8516_PIN_71_MSDC2_DAT1__FUNC_PWM_B (MTK_PIN_NO(71) \| 6)
	+#define MT8516_PIN_71_MSDC2_DAT1__FUNC_DBG_MON_B_18 (MTK_PIN_NO(71) \| 7)
	+
	+#define MT8516_PIN_72_MSDC2_DAT2__FUNC_GPIO72 (MTK_PIN_NO(72) \| 0)
	+#define MT8516_PIN_72_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(72) \| 1)
	+#define MT8516_PIN_72_MSDC2_DAT2__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(72) \| 2)
	+#define MT8516_PIN_72_MSDC2_DAT2__FUNC_SDA2_0 (MTK_PIN_NO(72) \| 3)
	+#define MT8516_PIN_72_MSDC2_DAT2__FUNC_UTXD1 (MTK_PIN_NO(72) \| 5)
	+#define MT8516_PIN_72_MSDC2_DAT2__FUNC_PWM_C (MTK_PIN_NO(72) \| 6)
	+#define MT8516_PIN_72_MSDC2_DAT2__FUNC_DBG_MON_B_19 (MTK_PIN_NO(72) \| 7)
	+
	+#define MT8516_PIN_73_MSDC2_DAT3__FUNC_GPIO73 (MTK_PIN_NO(73) \| 0)
	+#define MT8516_PIN_73_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(73) \| 1)
	+#define MT8516_PIN_73_MSDC2_DAT3__FUNC_I2S_8CH_BCK (MTK_PIN_NO(73) \| 2)
	+#define MT8516_PIN_73_MSDC2_DAT3__FUNC_SCL2_0 (MTK_PIN_NO(73) \| 3)
	+#define MT8516_PIN_73_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(73) \| 4)
	+#define MT8516_PIN_73_MSDC2_DAT3__FUNC_URXD1 (MTK_PIN_NO(73) \| 5)
	+#define MT8516_PIN_73_MSDC2_DAT3__FUNC_PWM_A (MTK_PIN_NO(73) \| 6)
	+#define MT8516_PIN_73_MSDC2_DAT3__FUNC_DBG_MON_B_20 (MTK_PIN_NO(73) \| 7)
	+
	+#define MT8516_PIN_74_TDN3__FUNC_GPI74 (MTK_PIN_NO(74) \| 0)
	+#define MT8516_PIN_74_TDN3__FUNC_TDN3 (MTK_PIN_NO(74) \| 1)
	+
	+#define MT8516_PIN_75_TDP3__FUNC_GPI75 (MTK_PIN_NO(75) \| 0)
	+#define MT8516_PIN_75_TDP3__FUNC_TDP3 (MTK_PIN_NO(75) \| 1)
	+
	+#define MT8516_PIN_76_TDN2__FUNC_GPI76 (MTK_PIN_NO(76) \| 0)
	+#define MT8516_PIN_76_TDN2__FUNC_TDN2 (MTK_PIN_NO(76) \| 1)
	+
	+#define MT8516_PIN_77_TDP2__FUNC_GPI77 (MTK_PIN_NO(77) \| 0)
	+#define MT8516_PIN_77_TDP2__FUNC_TDP2 (MTK_PIN_NO(77) \| 1)
	+
	+#define MT8516_PIN_78_TCN__FUNC_GPI78 (MTK_PIN_NO(78) \| 0)
	+#define MT8516_PIN_78_TCN__FUNC_TCN (MTK_PIN_NO(78) \| 1)
	+
	+#define MT8516_PIN_79_TCP__FUNC_GPI79 (MTK_PIN_NO(79) \| 0)
	+#define MT8516_PIN_79_TCP__FUNC_TCP (MTK_PIN_NO(79) \| 1)
	+
	+#define MT8516_PIN_80_TDN1__FUNC_GPI80 (MTK_PIN_NO(80) \| 0)
	+#define MT8516_PIN_80_TDN1__FUNC_TDN1 (MTK_PIN_NO(80) \| 1)
	+
	+#define MT8516_PIN_81_TDP1__FUNC_GPI81 (MTK_PIN_NO(81) \| 0)
	+#define MT8516_PIN_81_TDP1__FUNC_TDP1 (MTK_PIN_NO(81) \| 1)
	+
	+#define MT8516_PIN_82_TDN0__FUNC_GPI82 (MTK_PIN_NO(82) \| 0)
	+#define MT8516_PIN_82_TDN0__FUNC_TDN0 (MTK_PIN_NO(82) \| 1)
	+
	+#define MT8516_PIN_83_TDP0__FUNC_GPI83 (MTK_PIN_NO(83) \| 0)
	+#define MT8516_PIN_83_TDP0__FUNC_TDP0 (MTK_PIN_NO(83) \| 1)
	+
	+#define MT8516_PIN_84_RDN0__FUNC_GPI84 (MTK_PIN_NO(84) \| 0)
	+#define MT8516_PIN_84_RDN0__FUNC_RDN0 (MTK_PIN_NO(84) \| 1)
	+
	+#define MT8516_PIN_85_RDP0__FUNC_GPI85 (MTK_PIN_NO(85) \| 0)
	+#define MT8516_PIN_85_RDP0__FUNC_RDP0 (MTK_PIN_NO(85) \| 1)
	+
	+#define MT8516_PIN_86_RDN1__FUNC_GPI86 (MTK_PIN_NO(86) \| 0)
	+#define MT8516_PIN_86_RDN1__FUNC_RDN1 (MTK_PIN_NO(86) \| 1)
	+
	+#define MT8516_PIN_87_RDP1__FUNC_GPI87 (MTK_PIN_NO(87) \| 0)
	+#define MT8516_PIN_87_RDP1__FUNC_RDP1 (MTK_PIN_NO(87) \| 1)
	+
	+#define MT8516_PIN_88_RCN__FUNC_GPI88 (MTK_PIN_NO(88) \| 0)
	+#define MT8516_PIN_88_RCN__FUNC_RCN (MTK_PIN_NO(88) \| 1)
	+
	+#define MT8516_PIN_89_RCP__FUNC_GPI89 (MTK_PIN_NO(89) \| 0)
	+#define MT8516_PIN_89_RCP__FUNC_RCP (MTK_PIN_NO(89) \| 1)
	+
	+#define MT8516_PIN_90_RDN2__FUNC_GPI90 (MTK_PIN_NO(90) \| 0)
	+#define MT8516_PIN_90_RDN2__FUNC_RDN2 (MTK_PIN_NO(90) \| 1)
	+#define MT8516_PIN_90_RDN2__FUNC_CMDAT8 (MTK_PIN_NO(90) \| 2)
	+
	+#define MT8516_PIN_91_RDP2__FUNC_GPI91 (MTK_PIN_NO(91) \| 0)
	+#define MT8516_PIN_91_RDP2__FUNC_RDP2 (MTK_PIN_NO(91) \| 1)
	+#define MT8516_PIN_91_RDP2__FUNC_CMDAT9 (MTK_PIN_NO(91) \| 2)
	+
	+#define MT8516_PIN_92_RDN3__FUNC_GPI92 (MTK_PIN_NO(92) \| 0)
	+#define MT8516_PIN_92_RDN3__FUNC_RDN3 (MTK_PIN_NO(92) \| 1)
	+#define MT8516_PIN_92_RDN3__FUNC_CMDAT4 (MTK_PIN_NO(92) \| 2)
	+
	+#define MT8516_PIN_93_RDP3__FUNC_GPI93 (MTK_PIN_NO(93) \| 0)
	+#define MT8516_PIN_93_RDP3__FUNC_RDP3 (MTK_PIN_NO(93) \| 1)
	+#define MT8516_PIN_93_RDP3__FUNC_CMDAT5 (MTK_PIN_NO(93) \| 2)
	+
	+#define MT8516_PIN_94_RCN_A__FUNC_GPI94 (MTK_PIN_NO(94) \| 0)
	+#define MT8516_PIN_94_RCN_A__FUNC_RCN_A (MTK_PIN_NO(94) \| 1)
	+#define MT8516_PIN_94_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(94) \| 2)
	+
	+#define MT8516_PIN_95_RCP_A__FUNC_GPI95 (MTK_PIN_NO(95) \| 0)
	+#define MT8516_PIN_95_RCP_A__FUNC_RCP_A (MTK_PIN_NO(95) \| 1)
	+#define MT8516_PIN_95_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(95) \| 2)
	+
	+#define MT8516_PIN_96_RDN1_A__FUNC_GPI96 (MTK_PIN_NO(96) \| 0)
	+#define MT8516_PIN_96_RDN1_A__FUNC_RDN1_A (MTK_PIN_NO(96) \| 1)
	+#define MT8516_PIN_96_RDN1_A__FUNC_CMDAT2 (MTK_PIN_NO(96) \| 2)
	+#define MT8516_PIN_96_RDN1_A__FUNC_CMCSD2 (MTK_PIN_NO(96) \| 3)
	+
	+#define MT8516_PIN_97_RDP1_A__FUNC_GPI97 (MTK_PIN_NO(97) \| 0)
	+#define MT8516_PIN_97_RDP1_A__FUNC_RDP1_A (MTK_PIN_NO(97) \| 1)
	+#define MT8516_PIN_97_RDP1_A__FUNC_CMDAT3 (MTK_PIN_NO(97) \| 2)
	+#define MT8516_PIN_97_RDP1_A__FUNC_CMCSD3 (MTK_PIN_NO(97) \| 3)
	+
	+#define MT8516_PIN_98_RDN0_A__FUNC_GPI98 (MTK_PIN_NO(98) \| 0)
	+#define MT8516_PIN_98_RDN0_A__FUNC_RDN0_A (MTK_PIN_NO(98) \| 1)
	+#define MT8516_PIN_98_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(98) \| 2)
	+
	+#define MT8516_PIN_99_RDP0_A__FUNC_GPI99 (MTK_PIN_NO(99) \| 0)
	+#define MT8516_PIN_99_RDP0_A__FUNC_RDP0_A (MTK_PIN_NO(99) \| 1)
	+#define MT8516_PIN_99_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(99) \| 2)
	+
	+#define MT8516_PIN_100_CMDAT0__FUNC_GPIO100 (MTK_PIN_NO(100) \| 0)
	+#define MT8516_PIN_100_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(100) \| 1)
	+#define MT8516_PIN_100_CMDAT0__FUNC_CMCSD0 (MTK_PIN_NO(100) \| 2)
	+#define MT8516_PIN_100_CMDAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(100) \| 3)
	+#define MT8516_PIN_100_CMDAT0__FUNC_TDM_RX_MCK (MTK_PIN_NO(100) \| 5)
	+#define MT8516_PIN_100_CMDAT0__FUNC_DBG_MON_B_21 (MTK_PIN_NO(100) \| 7)
	+
	+#define MT8516_PIN_101_CMDAT1__FUNC_GPIO101 (MTK_PIN_NO(101) \| 0)
	+#define MT8516_PIN_101_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(101) \| 1)
	+#define MT8516_PIN_101_CMDAT1__FUNC_CMCSD1 (MTK_PIN_NO(101) \| 2)
	+#define MT8516_PIN_101_CMDAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(101) \| 3)
	+#define MT8516_PIN_101_CMDAT1__FUNC_CMFLASH (MTK_PIN_NO(101) \| 4)
	+#define MT8516_PIN_101_CMDAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(101) \| 5)
	+#define MT8516_PIN_101_CMDAT1__FUNC_DBG_MON_B_22 (MTK_PIN_NO(101) \| 7)
	+
	+#define MT8516_PIN_102_CMMCLK__FUNC_GPIO102 (MTK_PIN_NO(102) \| 0)
	+#define MT8516_PIN_102_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(102) \| 1)
	+#define MT8516_PIN_102_CMMCLK__FUNC_ANT_SEL4 (MTK_PIN_NO(102) \| 3)
	+#define MT8516_PIN_102_CMMCLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(102) \| 5)
	+#define MT8516_PIN_102_CMMCLK__FUNC_DBG_MON_B_23 (MTK_PIN_NO(102) \| 7)
	+
	+#define MT8516_PIN_103_CMPCLK__FUNC_GPIO103 (MTK_PIN_NO(103) \| 0)
	+#define MT8516_PIN_103_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(103) \| 1)
	+#define MT8516_PIN_103_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(103) \| 2)
	+#define MT8516_PIN_103_CMPCLK__FUNC_ANT_SEL5 (MTK_PIN_NO(103) \| 3)
	+#define MT8516_PIN_103_CMPCLK__FUNC_TDM_RX_DI (MTK_PIN_NO(103) \| 5)
	+#define MT8516_PIN_103_CMPCLK__FUNC_DBG_MON_B_24 (MTK_PIN_NO(103) \| 7)
	+
	+#define MT8516_PIN_104_MSDC1_CMD__FUNC_GPIO104 (MTK_PIN_NO(104) \| 0)
	+#define MT8516_PIN_104_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(104) \| 1)
	+#define MT8516_PIN_104_MSDC1_CMD__FUNC_SQICS (MTK_PIN_NO(104) \| 4)
	+#define MT8516_PIN_104_MSDC1_CMD__FUNC_DBG_MON_B_25 (MTK_PIN_NO(104) \| 7)
	+
	+#define MT8516_PIN_105_MSDC1_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) \| 0)
	+#define MT8516_PIN_105_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(105) \| 1)
	+#define MT8516_PIN_105_MSDC1_CLK__FUNC_SQISO (MTK_PIN_NO(105) \| 4)
	+#define MT8516_PIN_105_MSDC1_CLK__FUNC_DBG_MON_B_26 (MTK_PIN_NO(105) \| 7)
	+
	+#define MT8516_PIN_106_MSDC1_DAT0__FUNC_GPIO106 (MTK_PIN_NO(106) \| 0)
	+#define MT8516_PIN_106_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(106) \| 1)
	+#define MT8516_PIN_106_MSDC1_DAT0__FUNC_SQISI (MTK_PIN_NO(106) \| 4)
	+#define MT8516_PIN_106_MSDC1_DAT0__FUNC_DBG_MON_B_27 (MTK_PIN_NO(106) \| 7)
	+
	+#define MT8516_PIN_107_MSDC1_DAT1__FUNC_GPIO107 (MTK_PIN_NO(107) \| 0)
	+#define MT8516_PIN_107_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(107) \| 1)
	+#define MT8516_PIN_107_MSDC1_DAT1__FUNC_SQIWP (MTK_PIN_NO(107) \| 4)
	+#define MT8516_PIN_107_MSDC1_DAT1__FUNC_DBG_MON_B_28 (MTK_PIN_NO(107) \| 7)
	+
	+#define MT8516_PIN_108_MSDC1_DAT2__FUNC_GPIO108 (MTK_PIN_NO(108) \| 0)
	+#define MT8516_PIN_108_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(108) \| 1)
	+#define MT8516_PIN_108_MSDC1_DAT2__FUNC_SQIRST (MTK_PIN_NO(108) \| 4)
	+#define MT8516_PIN_108_MSDC1_DAT2__FUNC_DBG_MON_B_29 (MTK_PIN_NO(108) \| 7)
	+
	+#define MT8516_PIN_109_MSDC1_DAT3__FUNC_GPIO109 (MTK_PIN_NO(109) \| 0)
	+#define MT8516_PIN_109_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(109) \| 1)
	+#define MT8516_PIN_109_MSDC1_DAT3__FUNC_SQICK (MTK_PIN_NO(109) \| 4)
	+#define MT8516_PIN_109_MSDC1_DAT3__FUNC_DBG_MON_B_30 (MTK_PIN_NO(109) \| 7)
	+
	+#define MT8516_PIN_110_MSDC0_DAT7__FUNC_GPIO110 (MTK_PIN_NO(110) \| 0)
	+#define MT8516_PIN_110_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(110) \| 1)
	+#define MT8516_PIN_110_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(110) \| 4)
	+
	+#define MT8516_PIN_111_MSDC0_DAT6__FUNC_GPIO111 (MTK_PIN_NO(111) \| 0)
	+#define MT8516_PIN_111_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(111) \| 1)
	+#define MT8516_PIN_111_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(111) \| 4)
	+
	+#define MT8516_PIN_112_MSDC0_DAT5__FUNC_GPIO112 (MTK_PIN_NO(112) \| 0)
	+#define MT8516_PIN_112_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(112) \| 1)
	+#define MT8516_PIN_112_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(112) \| 4)
	+
	+#define MT8516_PIN_113_MSDC0_DAT4__FUNC_GPIO113 (MTK_PIN_NO(113) \| 0)
	+#define MT8516_PIN_113_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(113) \| 1)
	+#define MT8516_PIN_113_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(113) \| 4)
	+
	+#define MT8516_PIN_114_MSDC0_RSTB__FUNC_GPIO114 (MTK_PIN_NO(114) \| 0)
	+#define MT8516_PIN_114_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(114) \| 1)
	+#define MT8516_PIN_114_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(114) \| 4)
	+
	+#define MT8516_PIN_115_MSDC0_CMD__FUNC_GPIO115 (MTK_PIN_NO(115) \| 0)
	+#define MT8516_PIN_115_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(115) \| 1)
	+#define MT8516_PIN_115_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(115) \| 4)
	+
	+#define MT8516_PIN_116_MSDC0_CLK__FUNC_GPIO116 (MTK_PIN_NO(116) \| 0)
	+#define MT8516_PIN_116_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(116) \| 1)
	+#define MT8516_PIN_116_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(116) \| 4)
	+
	+#define MT8516_PIN_117_MSDC0_DAT3__FUNC_GPIO117 (MTK_PIN_NO(117) \| 0)
	+#define MT8516_PIN_117_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) \| 1)
	+#define MT8516_PIN_117_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(117) \| 4)
	+
	+#define MT8516_PIN_118_MSDC0_DAT2__FUNC_GPIO118 (MTK_PIN_NO(118) \| 0)
	+#define MT8516_PIN_118_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(118) \| 1)
	+#define MT8516_PIN_118_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(118) \| 4)
	+
	+#define MT8516_PIN_119_MSDC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) \| 0)
	+#define MT8516_PIN_119_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(119) \| 1)
	+#define MT8516_PIN_119_MSDC0_DAT1__FUNC_NLD8 (MTK_PIN_NO(119) \| 4)
	+
	+#define MT8516_PIN_120_MSDC0_DAT0__FUNC_GPIO120 (MTK_PIN_NO(120) \| 0)
	+#define MT8516_PIN_120_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(120) \| 1)
	+#define MT8516_PIN_120_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(120) \| 4)
	+#define MT8516_PIN_120_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(120) \| 5)
	+
	+#endif /* __DTS_MT8516_PINFUNC_H */
	diff --git a/sys/gnu/dts/arm64/mediatek/mt8516-pumpkin.dts b/sys/gnu/dts/arm64/mediatek/mt8516-pumpkin.dts
	new file mode 100644
	index 000000000000..cce642c53812
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/mediatek/mt8516-pumpkin.dts
	@@ -0,0 +1,20 @@
	+// SPDX-License-Identifier: GPL-2.0
	+/*
	+ * Copyright (c) 2019 BayLibre, SAS.
	+ * Author: Fabien Parent <fparent@baylibre.com>
	+ */
	+
	+/dts-v1/;
	+
	+#include "mt8516.dtsi"
	+#include "pumpkin-common.dtsi"
	+
	+/ {
	+ model = "Pumpkin MT8516";
	+ compatible = "mediatek,mt8516";
	+
	+ memory@40000000 {
	+ device_type = "memory";
	+ reg = <0 0x40000000 0 0x40000000>;
	+ };
	+};
	diff --git a/sys/gnu/dts/arm64/mediatek/mt8516.dtsi b/sys/gnu/dts/arm64/mediatek/mt8516.dtsi
	new file mode 100644
	index 000000000000..2f8adf042195
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/mediatek/mt8516.dtsi
	@@ -0,0 +1,457 @@
	+// SPDX-License-Identifier: GPL-2.0
	+/*
	+ * Copyright (c) 2019 MediaTek Inc.
	+ * Copyright (c) 2019 BayLibre, SAS.
	+ * Author: Fabien Parent <fparent@baylibre.com>
	+ */
	+
	+#include <dt-bindings/clock/mt8516-clk.h>
	+#include <dt-bindings/interrupt-controller/arm-gic.h>
	+#include <dt-bindings/interrupt-controller/irq.h>
	+#include <dt-bindings/phy/phy.h>
	+
	+#include "mt8516-pinfunc.h"
	+
	+/ {
	+ compatible = "mediatek,mt8516";
	+ interrupt-parent = <&sysirq>;
	+ #address-cells = <2>;
	+ #size-cells = <2>;
	+
	+ cluster0_opp: opp-table-0 {
	+ compatible = "operating-points-v2";
	+ opp-shared;
	+ opp-598000000 {
	+ opp-hz = /bits/ 64 <598000000>;
	+ opp-microvolt = <1150000>;
	+ };
	+ opp-747500000 {
	+ opp-hz = /bits/ 64 <747500000>;
	+ opp-microvolt = <1150000>;
	+ };
	+ opp-1040000000 {
	+ opp-hz = /bits/ 64 <1040000000>;
	+ opp-microvolt = <1200000>;
	+ };
	+ opp-1196000000 {
	+ opp-hz = /bits/ 64 <1196000000>;
	+ opp-microvolt = <1250000>;
	+ };
	+ opp-1300000000 {
	+ opp-hz = /bits/ 64 <1300000000>;
	+ opp-microvolt = <1300000>;
	+ };
	+ };
	+
	+ cpus {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ cpu0: cpu@0 {
	+ device_type = "cpu";
	+ compatible = "arm,cortex-a35";
	+ reg = <0x0>;
	+ enable-method = "psci";
	+ cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
	+ <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
	+ clocks = <&infracfg CLK_IFR_MUX1_SEL>,
	+ <&topckgen CLK_TOP_MAINPLL_D2>;
	+ clock-names = "cpu", "intermediate";
	+ operating-points-v2 = <&cluster0_opp>;
	+ };
	+
	+ cpu1: cpu@1 {
	+ device_type = "cpu";
	+ compatible = "arm,cortex-a35";
	+ reg = <0x1>;
	+ enable-method = "psci";
	+ cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
	+ <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
	+ clocks = <&infracfg CLK_IFR_MUX1_SEL>,
	+ <&topckgen CLK_TOP_MAINPLL_D2>;
	+ clock-names = "cpu", "intermediate";
	+ operating-points-v2 = <&cluster0_opp>;
	+ };
	+
	+ cpu2: cpu@2 {
	+ device_type = "cpu";
	+ compatible = "arm,cortex-a35";
	+ reg = <0x2>;
	+ enable-method = "psci";
	+ cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
	+ <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
	+ clocks = <&infracfg CLK_IFR_MUX1_SEL>,
	+ <&topckgen CLK_TOP_MAINPLL_D2>;
	+ clock-names = "cpu", "intermediate";
	+ operating-points-v2 = <&cluster0_opp>;
	+ };
	+
	+ cpu3: cpu@3 {
	+ device_type = "cpu";
	+ compatible = "arm,cortex-a35";
	+ reg = <0x3>;
	+ enable-method = "psci";
	+ cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
	+ <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
	+ clocks = <&infracfg CLK_IFR_MUX1_SEL>,
	+ <&topckgen CLK_TOP_MAINPLL_D2>;
	+ clock-names = "cpu", "intermediate", "armpll";
	+ operating-points-v2 = <&cluster0_opp>;
	+ };
	+
	+ idle-states {
	+ entry-method = "psci";
	+
	+ CPU_SLEEP_0_0: cpu-sleep-0-0 {
	+ compatible = "arm,idle-state";
	+ entry-latency-us = <600>;
	+ exit-latency-us = <600>;
	+ min-residency-us = <1200>;
	+ arm,psci-suspend-param = <0x0010000>;
	+ };
	+
	+ CLUSTER_SLEEP_0: cluster-sleep-0 {
	+ compatible = "arm,idle-state";
	+ entry-latency-us = <800>;
	+ exit-latency-us = <1000>;
	+ min-residency-us = <2000>;
	+ arm,psci-suspend-param = <0x2010000>;
	+ };
	+ };
	+ };
	+
	+ psci {
	+ compatible = "arm,psci-1.0";
	+ method = "smc";
	+ };
	+
	+ clk26m: clk26m {
	+ compatible = "fixed-clock";
	+ #clock-cells = <0>;
	+ clock-frequency = <26000000>;
	+ clock-output-names = "clk26m";
	+ };
	+
	+ clk32k: clk32k {
	+ compatible = "fixed-clock";
	+ #clock-cells = <0>;
	+ clock-frequency = <32000>;
	+ clock-output-names = "clk32k";
	+ };
	+
	+ reserved-memory {
	+ #address-cells = <2>;
	+ #size-cells = <2>;
	+ ranges;
	+
	+ /* 128 KiB reserved for ARM Trusted Firmware (BL31) */
	+ bl31_secmon_reserved: secmon@43000000 {
	+ no-map;
	+ reg = <0 0x43000000 0 0x20000>;
	+ };
	+ };
	+
	+ timer {
	+ compatible = "arm,armv8-timer";
	+ interrupt-parent = <&gic>;
	+ interrupts = <GIC_PPI 13
	+ (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	+ <GIC_PPI 14
	+ (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	+ <GIC_PPI 11
	+ (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	+ <GIC_PPI 10
	+ (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	+ };
	+
	+ pmu {
	+ compatible = "arm,armv8-pmuv3";
	+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
	+ <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
	+ <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,
	+ <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
	+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	+ };
	+
	+ soc {
	+ #address-cells = <2>;
	+ #size-cells = <2>;
	+ compatible = "simple-bus";
	+ ranges;
	+
	+ topckgen: topckgen@10000000 {
	+ compatible = "mediatek,mt8516-topckgen", "syscon";
	+ reg = <0 0x10000000 0 0x1000>;
	+ #clock-cells = <1>;
	+ };
	+
	+ infracfg: infracfg@10001000 {
	+ compatible = "mediatek,mt8516-infracfg", "syscon";
	+ reg = <0 0x10001000 0 0x1000>;
	+ #clock-cells = <1>;
	+ };
	+
	+ apmixedsys: apmixedsys@10018000 {
	+ compatible = "mediatek,mt8516-apmixedsys", "syscon";
	+ reg = <0 0x10018000 0 0x710>;
	+ #clock-cells = <1>;
	+ };
	+
	+ toprgu: toprgu@10007000 {
	+ compatible = "mediatek,mt8516-wdt",
	+ "mediatek,mt6589-wdt";
	+ reg = <0 0x10007000 0 0x1000>;
	+ interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>;
	+ #reset-cells = <1>;
	+ };
	+
	+ timer: timer@10008000 {
	+ compatible = "mediatek,mt8516-timer",
	+ "mediatek,mt6577-timer";
	+ reg = <0 0x10008000 0 0x1000>;
	+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
	+ clocks = <&topckgen CLK_TOP_CLK26M_D2>,
	+ <&topckgen CLK_TOP_APXGPT>;
	+ clock-names = "clk13m", "bus";
	+ };
	+
	+ syscfg_pctl: syscfg-pctl@10005000 {
	+ compatible = "syscon";
	+ reg = <0 0x10005000 0 0x1000>;
	+ };
	+
	+ pio: pinctrl@1000b000 {
	+ compatible = "mediatek,mt8516-pinctrl";
	+ reg = <0 0x1000b000 0 0x1000>;
	+ mediatek,pctl-regmap = <&syscfg_pctl>;
	+ pins-are-numbered;
	+ gpio-controller;
	+ #gpio-cells = <2>;
	+ interrupt-controller;
	+ #interrupt-cells = <2>;
	+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
	+ };
	+
	+ pwrap: pwrap@1000f000 {
	+ compatible = "mediatek,mt8516-pwrap";
	+ reg = <0 0x1000f000 0 0x1000>;
	+ reg-names = "pwrap";
	+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
	+ clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
	+ <&topckgen CLK_TOP_PMICWRAP_AP>;
	+ clock-names = "spi", "wrap";
	+ };
	+
	+ sysirq: interrupt-controller@10200620 {
	+ compatible = "mediatek,mt8516-sysirq",
	+ "mediatek,mt6577-sysirq";
	+ interrupt-controller;
	+ #interrupt-cells = <3>;
	+ interrupt-parent = <&gic>;
	+ reg = <0 0x10200620 0 0x20>;
	+ };
	+
	+ gic: interrupt-controller@10310000 {
	+ compatible = "arm,gic-400";
	+ #interrupt-cells = <3>;
	+ interrupt-parent = <&gic>;
	+ interrupt-controller;
	+ reg = <0 0x10310000 0 0x1000>,
	+ <0 0x10320000 0 0x1000>,
	+ <0 0x10340000 0 0x2000>,
	+ <0 0x10360000 0 0x2000>;
	+ interrupts = <GIC_PPI 9
	+ (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	+ };
	+
	+ uart0: serial@11005000 {
	+ compatible = "mediatek,mt8516-uart",
	+ "mediatek,mt6577-uart";
	+ reg = <0 0x11005000 0 0x1000>;
	+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
	+ clocks = <&topckgen CLK_TOP_UART0_SEL>,
	+ <&topckgen CLK_TOP_UART0>;
	+ clock-names = "baud", "bus";
	+ status = "disabled";
	+ };
	+
	+ uart1: serial@11006000 {
	+ compatible = "mediatek,mt8516-uart",
	+ "mediatek,mt6577-uart";
	+ reg = <0 0x11006000 0 0x1000>;
	+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
	+ clocks = <&topckgen CLK_TOP_UART1_SEL>,
	+ <&topckgen CLK_TOP_UART1>;
	+ clock-names = "baud", "bus";
	+ status = "disabled";
	+ };
	+
	+ uart2: serial@11007000 {
	+ compatible = "mediatek,mt8516-uart",
	+ "mediatek,mt6577-uart";
	+ reg = <0 0x11007000 0 0x1000>;
	+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
	+ clocks = <&topckgen CLK_TOP_UART2_SEL>,
	+ <&topckgen CLK_TOP_UART2>;
	+ clock-names = "baud", "bus";
	+ status = "disabled";
	+ };
	+
	+ i2c0: i2c@11009000 {
	+ compatible = "mediatek,mt8516-i2c",
	+ "mediatek,mt2712-i2c";
	+ reg = <0 0x11009000 0 0x90>,
	+ <0 0x11000180 0 0x80>;
	+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
	+ clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
	+ <&infracfg CLK_IFR_I2C0_SEL>,
	+ <&topckgen CLK_TOP_I2C0>,
	+ <&topckgen CLK_TOP_APDMA>;
	+ clock-names = "main-source",
	+ "main-sel",
	+ "main",
	+ "dma";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ status = "disabled";
	+ };
	+
	+ i2c1: i2c@1100a000 {
	+ compatible = "mediatek,mt8516-i2c",
	+ "mediatek,mt2712-i2c";
	+ reg = <0 0x1100a000 0 0x90>,
	+ <0 0x11000200 0 0x80>;
	+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
	+ clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
	+ <&infracfg CLK_IFR_I2C1_SEL>,
	+ <&topckgen CLK_TOP_I2C1>,
	+ <&topckgen CLK_TOP_APDMA>;
	+ clock-names = "main-source",
	+ "main-sel",
	+ "main",
	+ "dma";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ status = "disabled";
	+ };
	+
	+ i2c2: i2c@1100b000 {
	+ compatible = "mediatek,mt8516-i2c",
	+ "mediatek,mt2712-i2c";
	+ reg = <0 0x1100b000 0 0x90>,
	+ <0 0x11000280 0 0x80>;
	+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
	+ clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
	+ <&infracfg CLK_IFR_I2C2_SEL>,
	+ <&topckgen CLK_TOP_I2C2>,
	+ <&topckgen CLK_TOP_APDMA>;
	+ clock-names = "main-source",
	+ "main-sel",
	+ "main",
	+ "dma";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ status = "disabled";
	+ };
	+
	+ spi: spi@1100c000 {
	+ compatible = "mediatek,mt8516-spi",
	+ "mediatek,mt2712-spi";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ reg = <0 0x1100c000 0 0x1000>;
	+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
	+ clocks = <&topckgen CLK_TOP_UNIVPLL_D12>,
	+ <&topckgen CLK_TOP_SPI_SEL>,
	+ <&topckgen CLK_TOP_SPI>;
	+ clock-names = "parent-clk", "sel-clk", "spi-clk";
	+ status = "disabled";
	+ };
	+
	+ mmc0: mmc@11120000 {
	+ compatible = "mediatek,mt8516-mmc";
	+ reg = <0 0x11120000 0 0x1000>;
	+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
	+ clocks = <&topckgen CLK_TOP_MSDC0>,
	+ <&topckgen CLK_TOP_AHB_INFRA_SEL>,
	+ <&topckgen CLK_TOP_MSDC0_INFRA>;
	+ clock-names = "source", "hclk", "source_cg";
	+ status = "disabled";
	+ };
	+
	+ mmc1: mmc@11130000 {
	+ compatible = "mediatek,mt8516-mmc";
	+ reg = <0 0x11130000 0 0x1000>;
	+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
	+ clocks = <&topckgen CLK_TOP_MSDC1>,
	+ <&topckgen CLK_TOP_AHB_INFRA_SEL>,
	+ <&topckgen CLK_TOP_MSDC1_INFRA>;
	+ clock-names = "source", "hclk", "source_cg";
	+ status = "disabled";
	+ };
	+
	+ mmc2: mmc@11170000 {
	+ compatible = "mediatek,mt8516-mmc";
	+ reg = <0 0x11170000 0 0x1000>;
	+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>;
	+ clocks = <&topckgen CLK_TOP_MSDC2>,
	+ <&topckgen CLK_TOP_RG_MSDC2>,
	+ <&topckgen CLK_TOP_MSDC2_INFRA>;
	+ clock-names = "source", "hclk", "source_cg";
	+ status = "disabled";
	+ };
	+
	+ rng: rng@1020c000 {
	+ compatible = "mediatek,mt8516-rng",
	+ "mediatek,mt7623-rng";
	+ reg = <0 0x1020c000 0 0x100>;
	+ clocks = <&topckgen CLK_TOP_TRNG>;
	+ clock-names = "rng";
	+ };
	+
	+ pwm: pwm@11008000 {
	+ compatible = "mediatek,mt8516-pwm";
	+ reg = <0 0x11008000 0 0x1000>;
	+ #pwm-cells = <2>;
	+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
	+ clocks = <&topckgen CLK_TOP_PWM>,
	+ <&topckgen CLK_TOP_PWM_B>,
	+ <&topckgen CLK_TOP_PWM1_FB>,
	+ <&topckgen CLK_TOP_PWM2_FB>,
	+ <&topckgen CLK_TOP_PWM3_FB>,
	+ <&topckgen CLK_TOP_PWM4_FB>,
	+ <&topckgen CLK_TOP_PWM5_FB>;
	+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
	+ "pwm4", "pwm5";
	+ };
	+
	+ usb0: usb@11100000 {
	+ compatible = "mediatek,mtk-musb";
	+ reg = <0 0x11100000 0 0x1000>;
	+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
	+ interrupt-names = "mc";
	+ phys = <&usb0_port PHY_TYPE_USB2>;
	+ clocks = <&topckgen CLK_TOP_USB>,
	+ <&topckgen CLK_TOP_USBIF>,
	+ <&topckgen CLK_TOP_USB_1P>;
	+ clock-names = "main","mcu","univpll";
	+ status = "disabled";
	+ };
	+
	+ usb0_phy: usb@11110000 {
	+ compatible = "mediatek,generic-tphy-v1";
	+ reg = <0 0x11110000 0 0x800>;
	+ #address-cells = <2>;
	+ #size-cells = <2>;
	+ ranges;
	+ status = "disabled";
	+
	+ usb0_port: usb-phy@11110800 {
	+ reg = <0 0x11110800 0 0x100>;
	+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
	+ clock-names = "ref";
	+ #phy-cells = <1>;
	+ };
	+ };
	+ };
	+};
	diff --git a/sys/gnu/dts/arm64/mediatek/pumpkin-common.dtsi b/sys/gnu/dts/arm64/mediatek/pumpkin-common.dtsi
	new file mode 100644
	index 000000000000..a31093d7142b
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/mediatek/pumpkin-common.dtsi
	@@ -0,0 +1,221 @@
	+// SPDX-License-Identifier: GPL-2.0
	+/*
	+ * Copyright (c) 2019 BayLibre, SAS.
	+ * Author: Fabien Parent <fparent@baylibre.com>
	+ */
	+
	+#include <dt-bindings/gpio/gpio.h>
	+
	+/ {
	+ aliases {
	+ serial0 = &uart0;
	+ };
	+
	+ chosen {
	+ stdout-path = "serial0:921600n8";
	+ };
	+
	+ firmware {
	+ optee: optee@4fd00000 {
	+ compatible = "linaro,optee-tz";
	+ method = "smc";
	+ };
	+ };
	+
	+ gpio-keys {
	+ compatible = "gpio-keys";
	+ input-name = "gpio-keys";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&gpio_keys_default>;
	+
	+ volume-up {
	+ gpios = <&pio 42 GPIO_ACTIVE_LOW>;
	+ label = "volume_up";
	+ linux,code = <115>;
	+ wakeup-source;
	+ debounce-interval = <15>;
	+ };
	+
	+ volume-down {
	+ gpios = <&pio 43 GPIO_ACTIVE_LOW>;
	+ label = "volume_down";
	+ linux,code = <114>;
	+ wakeup-source;
	+ debounce-interval = <15>;
	+ };
	+ };
	+};
	+
	+&i2c0 {
	+ clock-div = <2>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&i2c0_pins_a>;
	+ status = "okay";
	+
	+ tca6416: gpio@20 {
	+ compatible = "ti,tca6416";
	+ reg = <0x20>;
	+ rst-gpio = <&pio 65 GPIO_ACTIVE_HIGH>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&tca6416_pins>;
	+
	+ gpio-controller;
	+ #gpio-cells = <2>;
	+
	+ eint20_mux_sel0 {
	+ gpio-hog;
	+ gpios = <0 0>;
	+ input;
	+ line-name = "eint20_mux_sel0";
	+ };
	+
	+ expcon_mux_sel1 {
	+ gpio-hog;
	+ gpios = <1 0>;
	+ input;
	+ line-name = "expcon_mux_sel1";
	+ };
	+
	+ mrg_di_mux_sel2 {
	+ gpio-hog;
	+ gpios = <2 0>;
	+ input;
	+ line-name = "mrg_di_mux_sel2";
	+ };
	+
	+ sd_sdio_mux_sel3 {
	+ gpio-hog;
	+ gpios = <3 0>;
	+ input;
	+ line-name = "sd_sdio_mux_sel3";
	+ };
	+
	+ sd_sdio_mux_ctrl7 {
	+ gpio-hog;
	+ gpios = <7 0>;
	+ output-low;
	+ line-name = "sd_sdio_mux_ctrl7";
	+ };
	+
	+ hw_id0 {
	+ gpio-hog;
	+ gpios = <8 0>;
	+ input;
	+ line-name = "hw_id0";
	+ };
	+
	+ hw_id1 {
	+ gpio-hog;
	+ gpios = <9 0>;
	+ input;
	+ line-name = "hw_id1";
	+ };
	+
	+ hw_id2 {
	+ gpio-hog;
	+ gpios = <10 0>;
	+ input;
	+ line-name = "hw_id2";
	+ };
	+
	+ fg_int_n {
	+ gpio-hog;
	+ gpios = <11 0>;
	+ input;
	+ line-name = "fg_int_n";
	+ };
	+
	+ usba_pwr_en {
	+ gpio-hog;
	+ gpios = <12 0>;
	+ output-high;
	+ line-name = "usba_pwr_en";
	+ };
	+
	+ wifi_3v3_pg {
	+ gpio-hog;
	+ gpios = <13 0>;
	+ input;
	+ line-name = "wifi_3v3_pg";
	+ };
	+
	+ cam_rst {
	+ gpio-hog;
	+ gpios = <14 0>;
	+ output-low;
	+ line-name = "cam_rst";
	+ };
	+
	+ cam_pwdn {
	+ gpio-hog;
	+ gpios = <15 0>;
	+ output-low;
	+ line-name = "cam_pwdn";
	+ };
	+ };
	+};
	+
	+&i2c2 {
	+ clock-div = <2>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&i2c2_pins_a>;
	+ status = "okay";
	+};
	+
	+&uart0 {
	+ status = "okay";
	+};
	+
	+&usb0 {
	+ status = "okay";
	+ dr_mode = "peripheral";
	+
	+ usb_con: connector {
	+ compatible = "usb-c-connector";
	+ label = "USB-C";
	+ };
	+};
	+
	+&usb0_phy {
	+ status = "okay";
	+};
	+
	+&pio {
	+ gpio_keys_default: gpiodefault {
	+ pins_cmd_dat {
	+ pinmux = <MT8516_PIN_42_KPCOL0__FUNC_GPIO42>,
	+ <MT8516_PIN_43_KPCOL1__FUNC_GPIO43>;
	+ bias-pull-up;
	+ input-enable;
	+ };
	+ };
	+
	+ i2c0_pins_a: i2c0@0 {
	+ pins1 {
	+ pinmux = <MT8516_PIN_58_SDA0__FUNC_SDA0_0>,
	+ <MT8516_PIN_59_SCL0__FUNC_SCL0_0>;
	+ bias-disable;
	+ };
	+ };
	+
	+ i2c2_pins_a: i2c2@0 {
	+ pins1 {
	+ pinmux = <MT8516_PIN_60_SDA2__FUNC_SDA2_0>,
	+ <MT8516_PIN_61_SCL2__FUNC_SCL2_0>;
	+ bias-disable;
	+ };
	+ };
	+
	+ tca6416_pins: pinmux_tca6416_pins {
	+ gpio_mux_rst_n_pin {
	+ pinmux = <MT8516_PIN_65_UTXD1__FUNC_GPIO65>;
	+ output-high;
	+ };
	+
	+ gpio_mux_int_n_pin {
	+ pinmux = <MT8516_PIN_64_URXD1__FUNC_GPIO64>;
	+ input-enable;
	+ bias-pull-up;
	+ };
	+ };
	+};
	diff --git a/sys/gnu/dts/arm64/nvidia/tegra132.dtsi b/sys/gnu/dts/arm64/nvidia/tegra132.dtsi
	index 6238e6e274b4..11a1bb428595 100644
	--- a/sys/gnu/dts/arm64/nvidia/tegra132.dtsi
	+++ b/sys/gnu/dts/arm64/nvidia/tegra132.dtsi
	@@ -1,1110 +1,1112 @@
	// SPDX-License-Identifier: GPL-2.0
	#include <dt-bindings/clock/tegra124-car.h>
	#include <dt-bindings/gpio/tegra-gpio.h>
	#include <dt-bindings/memory/tegra124-mc.h>
	#include <dt-bindings/pinctrl/pinctrl-tegra.h>
	#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/thermal/tegra124-soctherm.h>
	+#include <dt-bindings/soc/tegra-pmc.h>

	/ {
	compatible = "nvidia,tegra132", "nvidia,tegra124";
	interrupt-parent = <&lic>;
	#address-cells = <2>;
	#size-cells = <2>;

	pcie@1003000 {
	compatible = "nvidia,tegra124-pcie";
	device_type = "pci";
	reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
	0x0 0x01003800 0x0 0x00000800 /* AFI registers */
	0x0 0x02000000 0x0 0x10000000>; /* configuration space */
	reg-names = "pads", "afi", "cs";
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
	<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
	interrupt-names = "intr", "msi";

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

	bus-range = <0x00 0xff>;
	#address-cells = <3>;
	#size-cells = <2>;

	ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
	0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
	0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
	0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
	0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */

	clocks = <&tegra_car TEGRA124_CLK_PCIE>,
	<&tegra_car TEGRA124_CLK_AFI>,
	<&tegra_car TEGRA124_CLK_PLL_E>,
	<&tegra_car TEGRA124_CLK_CML0>;
	clock-names = "pex", "afi", "pll_e", "cml";
	resets = <&tegra_car 70>,
	<&tegra_car 72>,
	<&tegra_car 74>;
	reset-names = "pex", "afi", "pcie_x";
	status = "disabled";

	phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
	phy-names = "pcie";

	pci@1,0 {
	device_type = "pci";
	assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
	reg = <0x000800 0 0 0 0>;
	bus-range = <0x00 0xff>;
	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	ranges;

	nvidia,num-lanes = <2>;
	};

	pci@2,0 {
	device_type = "pci";
	assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
	reg = <0x001000 0 0 0 0>;
	bus-range = <0x00 0xff>;
	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	ranges;

	nvidia,num-lanes = <1>;
	};
	};

	host1x@50000000 {
	compatible = "nvidia,tegra124-host1x", "simple-bus";
	reg = <0x0 0x50000000 0x0 0x00034000>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
	clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
	clock-names = "host1x";
	resets = <&tegra_car 28>;
	reset-names = "host1x";

	#address-cells = <2>;
	#size-cells = <2>;

	ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;

	dc@54200000 {
	compatible = "nvidia,tegra124-dc";
	reg = <0x0 0x54200000 0x0 0x00040000>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_DISP1>,
	<&tegra_car TEGRA124_CLK_PLL_P>;
	clock-names = "dc", "parent";
	resets = <&tegra_car 27>;
	reset-names = "dc";

	iommus = <&mc TEGRA_SWGROUP_DC>;

	nvidia,head = <0>;
	};

	dc@54240000 {
	compatible = "nvidia,tegra124-dc";
	reg = <0x0 0x54240000 0x0 0x00040000>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_DISP2>,
	<&tegra_car TEGRA124_CLK_PLL_P>;
	clock-names = "dc", "parent";
	resets = <&tegra_car 26>;
	reset-names = "dc";

	iommus = <&mc TEGRA_SWGROUP_DCB>;

	nvidia,head = <1>;
	};

	hdmi@54280000 {
	compatible = "nvidia,tegra124-hdmi";
	reg = <0x0 0x54280000 0x0 0x00040000>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_HDMI>,
	<&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
	clock-names = "hdmi", "parent";
	resets = <&tegra_car 51>;
	reset-names = "hdmi";
	status = "disabled";
	};

	sor@54540000 {
	compatible = "nvidia,tegra124-sor";
	reg = <0x0 0x54540000 0x0 0x00040000>;
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_SOR0>,
	<&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
	<&tegra_car TEGRA124_CLK_PLL_DP>,
	<&tegra_car TEGRA124_CLK_CLK_M>;
	clock-names = "sor", "parent", "dp", "safe";
	resets = <&tegra_car 182>;
	reset-names = "sor";
	status = "disabled";
	};

	dpaux: dpaux@545c0000 {
	compatible = "nvidia,tegra124-dpaux";
	reg = <0x0 0x545c0000 0x0 0x00040000>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
	<&tegra_car TEGRA124_CLK_PLL_DP>;
	clock-names = "dpaux", "parent";
	resets = <&tegra_car 181>;
	reset-names = "dpaux";
	status = "disabled";
	};
	};

	gic: interrupt-controller@50041000 {
	compatible = "arm,cortex-a15-gic";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x0 0x50041000 0x0 0x1000>,
	<0x0 0x50042000 0x0 0x2000>,
	<0x0 0x50044000 0x0 0x2000>,
	<0x0 0x50046000 0x0 0x2000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	interrupt-parent = <&gic>;
	};

	gpu@57000000 {
	compatible = "nvidia,gk20a";
	reg = <0x0 0x57000000 0x0 0x01000000>,
	<0x0 0x58000000 0x0 0x01000000>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "stall", "nonstall";
	clocks = <&tegra_car TEGRA124_CLK_GPU>,
	<&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
	clock-names = "gpu", "pwr";
	resets = <&tegra_car 184>;
	reset-names = "gpu";
	status = "disabled";
	};

	lic: interrupt-controller@60004000 {
	compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
	reg = <0x0 0x60004000 0x0 0x100>,
	<0x0 0x60004100 0x0 0x100>,
	<0x0 0x60004200 0x0 0x100>,
	<0x0 0x60004300 0x0 0x100>,
	<0x0 0x60004400 0x0 0x100>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	};

	timer@60005000 {
	compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
	reg = <0x0 0x60005000 0x0 0x400>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_TIMER>;
	clock-names = "timer";
	};

	tegra_car: clock@60006000 {
	compatible = "nvidia,tegra132-car";
	reg = <0x0 0x60006000 0x0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	nvidia,external-memory-controller = <&emc>;
	};

	flow-controller@60007000 {
	compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl";
	reg = <0x0 0x60007000 0x0 0x1000>;
	};

	actmon@6000c800 {
	compatible = "nvidia,tegra124-actmon";
	reg = <0x0 0x6000c800 0x0 0x400>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
	<&tegra_car TEGRA124_CLK_EMC>;
	clock-names = "actmon", "emc";
	resets = <&tegra_car 119>;
	reset-names = "actmon";
	};

	gpio: gpio@6000d000 {
	compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
	reg = <0x0 0x6000d000 0x0 0x1000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	#interrupt-cells = <2>;
	interrupt-controller;
	};

	apbdma: dma@60020000 {
	compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
	reg = <0x0 0x60020000 0x0 0x1400>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
	clock-names = "dma";
	resets = <&tegra_car 34>;
	reset-names = "dma";
	#dma-cells = <1>;
	};

	apbmisc@70000800 {
	compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
	reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
	<0x0 0x7000e864 0x0 0x04>; /* Strapping options */
	};

	pinmux: pinmux@70000868 {
	compatible = "nvidia,tegra124-pinmux";
	reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
	<0x0 0x70003000 0x0 0x434>, /* Mux registers */
	<0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
	};

	/*
	* There are two serial driver i.e. 8250 based simple serial
	* driver and APB DMA based serial driver for higher baudrate
	* and performance. To enable the 8250 based driver, the compatible
	* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
	* the APB DMA based serial driver, the compatible is
	* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
	*/
	uarta: serial@70006000 {
	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x70006000 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_UARTA>;
	clock-names = "serial";
	resets = <&tegra_car 6>;
	reset-names = "serial";
	dmas = <&apbdma 8>, <&apbdma 8>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartb: serial@70006040 {
	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x70006040 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_UARTB>;
	clock-names = "serial";
	resets = <&tegra_car 7>;
	reset-names = "serial";
	dmas = <&apbdma 9>, <&apbdma 9>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartc: serial@70006200 {
	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x70006200 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_UARTC>;
	clock-names = "serial";
	resets = <&tegra_car 55>;
	reset-names = "serial";
	dmas = <&apbdma 10>, <&apbdma 10>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartd: serial@70006300 {
	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x70006300 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_UARTD>;
	clock-names = "serial";
	resets = <&tegra_car 65>;
	reset-names = "serial";
	dmas = <&apbdma 19>, <&apbdma 19>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	pwm: pwm@7000a000 {
	compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
	reg = <0x0 0x7000a000 0x0 0x100>;
	#pwm-cells = <2>;
	clocks = <&tegra_car TEGRA124_CLK_PWM>;
	clock-names = "pwm";
	resets = <&tegra_car 17>;
	reset-names = "pwm";
	status = "disabled";
	};

	i2c@7000c000 {
	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
	reg = <0x0 0x7000c000 0x0 0x100>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_I2C1>;
	clock-names = "div-clk";
	resets = <&tegra_car 12>;
	reset-names = "i2c";
	dmas = <&apbdma 21>, <&apbdma 21>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000c400 {
	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
	reg = <0x0 0x7000c400 0x0 0x100>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_I2C2>;
	clock-names = "div-clk";
	resets = <&tegra_car 54>;
	reset-names = "i2c";
	dmas = <&apbdma 22>, <&apbdma 22>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000c500 {
	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
	reg = <0x0 0x7000c500 0x0 0x100>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_I2C3>;
	clock-names = "div-clk";
	resets = <&tegra_car 67>;
	reset-names = "i2c";
	dmas = <&apbdma 23>, <&apbdma 23>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000c700 {
	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
	reg = <0x0 0x7000c700 0x0 0x100>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_I2C4>;
	clock-names = "div-clk";
	resets = <&tegra_car 103>;
	reset-names = "i2c";
	dmas = <&apbdma 26>, <&apbdma 26>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000d000 {
	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
	reg = <0x0 0x7000d000 0x0 0x100>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_I2C5>;
	clock-names = "div-clk";
	resets = <&tegra_car 47>;
	reset-names = "i2c";
	dmas = <&apbdma 24>, <&apbdma 24>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000d100 {
	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
	reg = <0x0 0x7000d100 0x0 0x100>;
	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_I2C6>;
	clock-names = "div-clk";
	resets = <&tegra_car 166>;
	reset-names = "i2c";
	dmas = <&apbdma 30>, <&apbdma 30>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000d400 {
	compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
	reg = <0x0 0x7000d400 0x0 0x200>;
	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_SBC1>;
	clock-names = "spi";
	resets = <&tegra_car 41>;
	reset-names = "spi";
	dmas = <&apbdma 15>, <&apbdma 15>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000d600 {
	compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
	reg = <0x0 0x7000d600 0x0 0x200>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_SBC2>;
	clock-names = "spi";
	resets = <&tegra_car 44>;
	reset-names = "spi";
	dmas = <&apbdma 16>, <&apbdma 16>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000d800 {
	compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
	reg = <0x0 0x7000d800 0x0 0x200>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_SBC3>;
	clock-names = "spi";
	resets = <&tegra_car 46>;
	reset-names = "spi";
	dmas = <&apbdma 17>, <&apbdma 17>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000da00 {
	compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
	reg = <0x0 0x7000da00 0x0 0x200>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_SBC4>;
	clock-names = "spi";
	resets = <&tegra_car 68>;
	reset-names = "spi";
	dmas = <&apbdma 18>, <&apbdma 18>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000dc00 {
	compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
	reg = <0x0 0x7000dc00 0x0 0x200>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_SBC5>;
	clock-names = "spi";
	resets = <&tegra_car 104>;
	reset-names = "spi";
	dmas = <&apbdma 27>, <&apbdma 27>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000de00 {
	compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
	reg = <0x0 0x7000de00 0x0 0x200>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA124_CLK_SBC6>;
	clock-names = "spi";
	resets = <&tegra_car 105>;
	reset-names = "spi";
	dmas = <&apbdma 28>, <&apbdma 28>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	rtc@7000e000 {
	compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
	reg = <0x0 0x7000e000 0x0 0x100>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_RTC>;
	clock-names = "rtc";
	};

	- pmc@7000e400 {
	+ tegra_pmc: pmc@7000e400 {
	compatible = "nvidia,tegra124-pmc";
	reg = <0x0 0x7000e400 0x0 0x400>;
	clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
	clock-names = "pclk", "clk32k_in";
	+ #clock-cells = <1>;
	};

	fuse@7000f800 {
	compatible = "nvidia,tegra124-efuse";
	reg = <0x0 0x7000f800 0x0 0x400>;
	clocks = <&tegra_car TEGRA124_CLK_FUSE>;
	clock-names = "fuse";
	resets = <&tegra_car 39>;
	reset-names = "fuse";
	};

	mc: memory-controller@70019000 {
	compatible = "nvidia,tegra132-mc";
	reg = <0x0 0x70019000 0x0 0x1000>;
	clocks = <&tegra_car TEGRA124_CLK_MC>;
	clock-names = "mc";

	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;

	#iommu-cells = <1>;
	};

	emc: external-memory-controller@7001b000 {
	compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc";
	reg = <0x0 0x7001b000 0x0 0x1000>;
	clocks = <&tegra_car TEGRA124_CLK_EMC>;
	clock-names = "emc";

	nvidia,memory-controller = <&mc>;
	};

	sata@70020000 {
	compatible = "nvidia,tegra124-ahci";
	reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
	<0x0 0x70020000 0x0 0x7000>; /* SATA */
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_SATA>,
	<&tegra_car TEGRA124_CLK_SATA_OOB>,
	<&tegra_car TEGRA124_CLK_CML1>,
	<&tegra_car TEGRA124_CLK_PLL_E>;
	clock-names = "sata", "sata-oob", "cml1", "pll_e";
	resets = <&tegra_car 124>,
	<&tegra_car 123>,
	<&tegra_car 129>;
	reset-names = "sata", "sata-oob", "sata-cold";
	phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
	phy-names = "sata-phy";
	status = "disabled";
	};

	hda@70030000 {
	compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda",
	"nvidia,tegra30-hda";
	reg = <0x0 0x70030000 0x0 0x10000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_HDA>,
	<&tegra_car TEGRA124_CLK_HDA2HDMI>,
	<&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
	clock-names = "hda", "hda2hdmi", "hda2codec_2x";
	resets = <&tegra_car 125>, /* hda */
	<&tegra_car 128>, /* hda2hdmi */
	<&tegra_car 111>; /* hda2codec_2x */
	reset-names = "hda", "hda2hdmi", "hda2codec_2x";
	status = "disabled";
	};

	padctl: padctl@7009f000 {
	compatible = "nvidia,tegra132-xusb-padctl",
	"nvidia,tegra124-xusb-padctl";
	reg = <0x0 0x7009f000 0x0 0x1000>;
	resets = <&tegra_car 142>;
	reset-names = "padctl";

	#phy-cells = <1>;

	phys {
	pcie-0 {
	status = "disabled";
	};

	sata-0 {
	status = "disabled";
	};

	usb3-0 {
	status = "disabled";
	};

	usb3-1 {
	status = "disabled";
	};

	utmi-0 {
	status = "disabled";
	};

	utmi-1 {
	status = "disabled";
	};

	utmi-2 {
	status = "disabled";
	};
	};
	};

	sdhci@700b0000 {
	compatible = "nvidia,tegra124-sdhci";
	reg = <0x0 0x700b0000 0x0 0x200>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
	clock-names = "sdhci";
	resets = <&tegra_car 14>;
	reset-names = "sdhci";
	status = "disabled";
	};

	sdhci@700b0200 {
	compatible = "nvidia,tegra124-sdhci";
	reg = <0x0 0x700b0200 0x0 0x200>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
	clock-names = "sdhci";
	resets = <&tegra_car 9>;
	reset-names = "sdhci";
	status = "disabled";
	};

	sdhci@700b0400 {
	compatible = "nvidia,tegra124-sdhci";
	reg = <0x0 0x700b0400 0x0 0x200>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
	clock-names = "sdhci";
	resets = <&tegra_car 69>;
	reset-names = "sdhci";
	status = "disabled";
	};

	sdhci@700b0600 {
	compatible = "nvidia,tegra124-sdhci";
	reg = <0x0 0x700b0600 0x0 0x200>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
	clock-names = "sdhci";
	resets = <&tegra_car 15>;
	reset-names = "sdhci";
	status = "disabled";
	};

	soctherm: thermal-sensor@700e2000 {
	compatible = "nvidia,tegra132-soctherm";
	reg = <0x0 0x700e2000 0x0 0x600 /* 0: SOC_THERM reg_base */
	0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
	reg-names = "soctherm-reg", "ccroc-reg";
	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
	<&tegra_car TEGRA124_CLK_SOC_THERM>;
	clock-names = "tsensor", "soctherm";
	resets = <&tegra_car 78>;
	reset-names = "soctherm";
	#thermal-sensor-cells = <1>;

	throttle-cfgs {
	throttle_heavy: heavy {
	nvidia,priority = <100>;
	nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;

	#cooling-cells = <2>;
	};
	};
	};

	thermal-zones {
	cpu {
	polling-delay-passive = <1000>;
	polling-delay = <0>;

	thermal-sensors =
	<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;

	trips {
	cpu_shutdown_trip {
	temperature = <105000>;
	hysteresis = <1000>;
	type = "critical";
	};

	cpu_throttle_trip: throttle-trip {
	temperature = <102000>;
	hysteresis = <1000>;
	type = "hot";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu_throttle_trip>;
	cooling-device = <&throttle_heavy 1 1>;
	};
	};
	};
	mem {
	polling-delay-passive = <0>;
	polling-delay = <0>;

	thermal-sensors =
	<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;

	trips {
	mem_shutdown_trip {
	temperature = <101000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	/*
	* There are currently no cooling maps,
	* because there are no cooling devices.
	*/
	};
	};
	gpu {
	polling-delay-passive = <1000>;
	polling-delay = <0>;

	thermal-sensors =
	<&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;

	trips {
	gpu_shutdown_trip {
	temperature = <101000>;
	hysteresis = <1000>;
	type = "critical";
	};

	gpu_throttle_trip: throttle-trip {
	temperature = <99000>;
	hysteresis = <1000>;
	type = "hot";
	};
	};

	cooling-maps {
	map0 {
	trip = <&gpu_throttle_trip>;
	cooling-device = <&throttle_heavy 1 1>;
	};
	};
	};
	pllx {
	polling-delay-passive = <0>;
	polling-delay = <0>;

	thermal-sensors =
	<&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;

	trips {
	pllx_shutdown_trip {
	temperature = <105000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	/*
	* There are currently no cooling maps,
	* because there are no cooling devices.
	*/
	};
	};
	};

	ahub@70300000 {
	compatible = "nvidia,tegra124-ahub";
	reg = <0x0 0x70300000 0x0 0x200>,
	<0x0 0x70300800 0x0 0x800>,
	<0x0 0x70300200 0x0 0x600>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
	<&tegra_car TEGRA124_CLK_APBIF>;
	clock-names = "d_audio", "apbif";
	resets = <&tegra_car 106>, /* d_audio */
	<&tegra_car 107>, /* apbif */
	<&tegra_car 30>, /* i2s0 */
	<&tegra_car 11>, /* i2s1 */
	<&tegra_car 18>, /* i2s2 */
	<&tegra_car 101>, /* i2s3 */
	<&tegra_car 102>, /* i2s4 */
	<&tegra_car 108>, /* dam0 */
	<&tegra_car 109>, /* dam1 */
	<&tegra_car 110>, /* dam2 */
	<&tegra_car 10>, /* spdif */
	<&tegra_car 153>, /* amx */
	<&tegra_car 185>, /* amx1 */
	<&tegra_car 154>, /* adx */
	<&tegra_car 180>, /* adx1 */
	<&tegra_car 186>, /* afc0 */
	<&tegra_car 187>, /* afc1 */
	<&tegra_car 188>, /* afc2 */
	<&tegra_car 189>, /* afc3 */
	<&tegra_car 190>, /* afc4 */
	<&tegra_car 191>; /* afc5 */
	reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
	"i2s3", "i2s4", "dam0", "dam1", "dam2",
	"spdif", "amx", "amx1", "adx", "adx1",
	"afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
	dmas = <&apbdma 1>, <&apbdma 1>,
	<&apbdma 2>, <&apbdma 2>,
	<&apbdma 3>, <&apbdma 3>,
	<&apbdma 4>, <&apbdma 4>,
	<&apbdma 6>, <&apbdma 6>,
	<&apbdma 7>, <&apbdma 7>,
	<&apbdma 12>, <&apbdma 12>,
	<&apbdma 13>, <&apbdma 13>,
	<&apbdma 14>, <&apbdma 14>,
	<&apbdma 29>, <&apbdma 29>;
	dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
	"rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
	"rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
	"rx9", "tx9";
	ranges;
	#address-cells = <2>;
	#size-cells = <2>;

	tegra_i2s0: i2s@70301000 {
	compatible = "nvidia,tegra124-i2s";
	reg = <0x0 0x70301000 0x0 0x100>;
	nvidia,ahub-cif-ids = <4 4>;
	clocks = <&tegra_car TEGRA124_CLK_I2S0>;
	clock-names = "i2s";
	resets = <&tegra_car 30>;
	reset-names = "i2s";
	status = "disabled";
	};

	tegra_i2s1: i2s@70301100 {
	compatible = "nvidia,tegra124-i2s";
	reg = <0x0 0x70301100 0x0 0x100>;
	nvidia,ahub-cif-ids = <5 5>;
	clocks = <&tegra_car TEGRA124_CLK_I2S1>;
	clock-names = "i2s";
	resets = <&tegra_car 11>;
	reset-names = "i2s";
	status = "disabled";
	};

	tegra_i2s2: i2s@70301200 {
	compatible = "nvidia,tegra124-i2s";
	reg = <0x0 0x70301200 0x0 0x100>;
	nvidia,ahub-cif-ids = <6 6>;
	clocks = <&tegra_car TEGRA124_CLK_I2S2>;
	clock-names = "i2s";
	resets = <&tegra_car 18>;
	reset-names = "i2s";
	status = "disabled";
	};

	tegra_i2s3: i2s@70301300 {
	compatible = "nvidia,tegra124-i2s";
	reg = <0x0 0x70301300 0x0 0x100>;
	nvidia,ahub-cif-ids = <7 7>;
	clocks = <&tegra_car TEGRA124_CLK_I2S3>;
	clock-names = "i2s";
	resets = <&tegra_car 101>;
	reset-names = "i2s";
	status = "disabled";
	};

	tegra_i2s4: i2s@70301400 {
	compatible = "nvidia,tegra124-i2s";
	reg = <0x0 0x70301400 0x0 0x100>;
	nvidia,ahub-cif-ids = <8 8>;
	clocks = <&tegra_car TEGRA124_CLK_I2S4>;
	clock-names = "i2s";
	resets = <&tegra_car 102>;
	reset-names = "i2s";
	status = "disabled";
	};
	};

	usb@7d000000 {
	compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
	reg = <0x0 0x7d000000 0x0 0x4000>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA124_CLK_USBD>;
	clock-names = "usb";
	resets = <&tegra_car 22>;
	reset-names = "usb";
	nvidia,phy = <&phy1>;
	status = "disabled";
	};

	phy1: usb-phy@7d000000 {
	compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
	reg = <0x0 0x7d000000 0x0 0x4000>,
	<0x0 0x7d000000 0x0 0x4000>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA124_CLK_USBD>,
	<&tegra_car TEGRA124_CLK_PLL_U>,
	<&tegra_car TEGRA124_CLK_USBD>;
	clock-names = "reg", "pll_u", "utmi-pads";
	resets = <&tegra_car 22>, <&tegra_car 22>;
	reset-names = "usb", "utmi-pads";
	nvidia,hssync-start-delay = <0>;
	nvidia,idle-wait-delay = <17>;
	nvidia,elastic-limit = <16>;
	nvidia,term-range-adj = <6>;
	nvidia,xcvr-setup = <9>;
	nvidia,xcvr-lsfslew = <0>;
	nvidia,xcvr-lsrslew = <3>;
	nvidia,hssquelch-level = <2>;
	nvidia,hsdiscon-level = <5>;
	nvidia,xcvr-hsslew = <12>;
	nvidia,has-utmi-pad-registers;
	status = "disabled";
	};

	usb@7d004000 {
	compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
	reg = <0x0 0x7d004000 0x0 0x4000>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA124_CLK_USB2>;
	clock-names = "usb";
	resets = <&tegra_car 58>;
	reset-names = "usb";
	nvidia,phy = <&phy2>;
	status = "disabled";
	};

	phy2: usb-phy@7d004000 {
	compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
	reg = <0x0 0x7d004000 0x0 0x4000>,
	<0x0 0x7d000000 0x0 0x4000>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA124_CLK_USB2>,
	<&tegra_car TEGRA124_CLK_PLL_U>,
	<&tegra_car TEGRA124_CLK_USBD>;
	clock-names = "reg", "pll_u", "utmi-pads";
	resets = <&tegra_car 58>, <&tegra_car 22>;
	reset-names = "usb", "utmi-pads";
	nvidia,hssync-start-delay = <0>;
	nvidia,idle-wait-delay = <17>;
	nvidia,elastic-limit = <16>;
	nvidia,term-range-adj = <6>;
	nvidia,xcvr-setup = <9>;
	nvidia,xcvr-lsfslew = <0>;
	nvidia,xcvr-lsrslew = <3>;
	nvidia,hssquelch-level = <2>;
	nvidia,hsdiscon-level = <5>;
	nvidia,xcvr-hsslew = <12>;
	status = "disabled";
	};

	usb@7d008000 {
	compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
	reg = <0x0 0x7d008000 0x0 0x4000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA124_CLK_USB3>;
	clock-names = "usb";
	resets = <&tegra_car 59>;
	reset-names = "usb";
	nvidia,phy = <&phy3>;
	status = "disabled";
	};

	phy3: usb-phy@7d008000 {
	compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
	reg = <0x0 0x7d008000 0x0 0x4000>,
	<0x0 0x7d000000 0x0 0x4000>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA124_CLK_USB3>,
	<&tegra_car TEGRA124_CLK_PLL_U>,
	<&tegra_car TEGRA124_CLK_USBD>;
	clock-names = "reg", "pll_u", "utmi-pads";
	resets = <&tegra_car 59>, <&tegra_car 22>;
	reset-names = "usb", "utmi-pads";
	nvidia,hssync-start-delay = <0>;
	nvidia,idle-wait-delay = <17>;
	nvidia,elastic-limit = <16>;
	nvidia,term-range-adj = <6>;
	nvidia,xcvr-setup = <9>;
	nvidia,xcvr-lsfslew = <0>;
	nvidia,xcvr-lsrslew = <3>;
	nvidia,hssquelch-level = <2>;
	nvidia,hsdiscon-level = <5>;
	nvidia,xcvr-hsslew = <12>;
	status = "disabled";
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "nvidia,denver";
	reg = <0>;
	};

	cpu@1 {
	device_type = "cpu";
	compatible = "nvidia,denver";
	reg = <1>;
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 13
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	interrupt-parent = <&gic>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/nvidia/tegra186-p2771-0000.dts b/sys/gnu/dts/arm64/nvidia/tegra186-p2771-0000.dts
	index f1de4ff6230a..1af7f9ffb7b6 100644
	--- a/sys/gnu/dts/arm64/nvidia/tegra186-p2771-0000.dts
	+++ b/sys/gnu/dts/arm64/nvidia/tegra186-p2771-0000.dts
	@@ -1,374 +1,394 @@
	// SPDX-License-Identifier: GPL-2.0
	/dts-v1/;

	#include <dt-bindings/input/linux-event-codes.h>
	#include <dt-bindings/input/gpio-keys.h>

	#include "tegra186-p3310.dtsi"

	/ {
	model = "NVIDIA Jetson TX2 Developer Kit";
	compatible = "nvidia,p2771-0000", "nvidia,tegra186";

	aconnect {
	status = "okay";

	dma-controller@2930000 {
	status = "okay";
	};

	interrupt-controller@2a40000 {
	status = "okay";
	};
	};

	i2c@3160000 {
	power-monitor@42 {
	compatible = "ti,ina3221";
	reg = <0x42>;
	#address-cells = <1>;
	#size-cells = <0>;

	channel@0 {
	reg = <0x0>;
	label = "VDD_MUX";
	shunt-resistor-micro-ohms = <20000>;
	};

	channel@1 {
	reg = <0x1>;
	label = "VDD_5V0_IO_SYS";
	shunt-resistor-micro-ohms = <5000>;
	};

	channel@2 {
	reg = <0x2>;
	label = "VDD_3V3_SYS";
	shunt-resistor-micro-ohms = <10000>;
	};
	};

	power-monitor@43 {
	compatible = "ti,ina3221";
	reg = <0x43>;
	#address-cells = <1>;
	#size-cells = <0>;

	channel@0 {
	reg = <0x0>;
	label = "VDD_3V3_IO_SLP";
	shunt-resistor-micro-ohms = <10000>;
	};

	channel@1 {
	reg = <0x1>;
	label = "VDD_1V8_IO";
	shunt-resistor-micro-ohms = <10000>;
	};

	channel@2 {
	reg = <0x2>;
	label = "VDD_M2_IN";
	shunt-resistor-micro-ohms = <10000>;
	};
	};

	exp1: gpio@74 {
	compatible = "ti,tca9539";
	reg = <0x74>;

	interrupt-parent = <&gpio>;
	interrupts = <TEGRA186_MAIN_GPIO(Y, 0)
	GPIO_ACTIVE_LOW>;

	#gpio-cells = <2>;
	gpio-controller;

	vcc-supply = <&vdd_3v3_sys>;
	};

	exp2: gpio@77 {
	compatible = "ti,tca9539";
	reg = <0x77>;

	interrupt-parent = <&gpio>;
	interrupts = <TEGRA186_MAIN_GPIO(Y, 6)
	GPIO_ACTIVE_LOW>;

	#gpio-cells = <2>;
	gpio-controller;

	vcc-supply = <&vdd_1v8>;
	};
	};

	/* SDMMC1 (SD/MMC) */
	sdhci@3400000 {
	status = "okay";

	vmmc-supply = <&vdd_sd>;
	};

	hda@3510000 {
	nvidia,model = "jetson-tx2-hda";
	status = "okay";
	};

	padctl@3520000 {
	status = "okay";

	avdd-pll-erefeut-supply = <&vdd_1v8_pll>;
	avdd-usb-supply = <&vdd_3v3_sys>;
	dvdd-pex-supply = <&vdd_pex>;
	dvdd-pex-pll-supply = <&vdd_pex>;
	hvdd-pex-supply = <&vdd_1v8>;
	hvdd-pex-pll-supply = <&vdd_1v8>;
	vclamp-usb-supply = <&vdd_1v8>;
	vddio-hsic-supply = <&gnd>;

	pads {
	usb2 {
	status = "okay";

	lanes {
	- usb2-0 {
	+ micro_b: usb2-0 {
	nvidia,function = "xusb";
	status = "okay";
	};

	usb2-1 {
	nvidia,function = "xusb";
	status = "okay";
	};

	usb2-2 {
	nvidia,function = "xusb";
	status = "okay";
	};
	};
	};

	usb3 {
	status = "okay";

	lanes {
	usb3-0 {
	nvidia,function = "xusb";
	status = "okay";
	};

	usb3-1 {
	nvidia,function = "xusb";
	status = "okay";
	};

	usb3-2 {
	nvidia,function = "xusb";
	status = "okay";
	};
	};
	};
	};

	ports {
	usb2-0 {
	status = "okay";
	mode = "otg";
	-
	vbus-supply = <&vdd_usb0>;
	+
	+ usb-role-switch;
	+ connector {
	+ compatible = "usb-b-connector",
	+ "gpio-usb-b-connector";
	+ label = "micro-USB";
	+ type = "micro";
	+ vbus-gpio = <&gpio
	+ TEGRA186_MAIN_GPIO(X, 7)
	+ GPIO_ACTIVE_LOW>;
	+ id-gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
	+ };
	+
	};

	usb2-1 {
	status = "okay";
	mode = "host";

	vbus-supply = <&vdd_usb1>;
	};

	usb3-0 {
	nvidia,usb2-companion = <1>;
	status = "okay";
	};
	};
	};

	usb@3530000 {
	status = "okay";

	phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>,
	<&{/padctl@3520000/pads/usb2/lanes/usb2-1}>,
	<&{/padctl@3520000/pads/usb3/lanes/usb3-0}>;
	phy-names = "usb2-0", "usb2-1", "usb3-0";
	};

	+ usb@3550000 {
	+ status = "okay";
	+
	+ phys = <&micro_b>;
	+ phy-names = "usb2-0";
	+ };
	+
	i2c@c250000 {
	/* carrier board ID EEPROM */
	eeprom@57 {
	compatible = "atmel,24c02";
	reg = <0x57>;

	+ vcc-supply = <&vdd_1v8>;
	address-bits = <8>;
	page-size = <8>;
	size = <256>;
	read-only;
	};
	};

	pcie@10003000 {
	status = "okay";

	dvdd-pex-supply = <&vdd_pex>;
	hvdd-pex-pll-supply = <&vdd_1v8>;
	hvdd-pex-supply = <&vdd_1v8>;
	vddio-pexctl-aud-supply = <&vdd_1v8>;

	pci@1,0 {
	nvidia,num-lanes = <4>;
	status = "okay";
	};

	pci@2,0 {
	nvidia,num-lanes = <0>;
	status = "disabled";
	};

	pci@3,0 {
	nvidia,num-lanes = <1>;
	status = "disabled";
	};
	};

	host1x@13e00000 {
	status = "okay";

	dpaux@15040000 {
	status = "okay";
	};

	display-hub@15200000 {
	status = "okay";
	};

	dsi@15300000 {
	status = "disabled";
	};

	/* DP on E3320 */
	sor@15540000 {
	status = "okay";

	avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
	- vdd-hdmi-dp-pll = <&vdd_1v8_ap>;
	+ vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;

	nvidia,dpaux = <&dpaux>;
	};

	sor@15580000 {
	status = "okay";

	avdd-io-supply = <&vdd_hdmi_1v05>;
	vdd-pll-supply = <&vdd_1v8_ap>;
	hdmi-supply = <&vdd_hdmi>;

	nvidia,ddc-i2c-bus = <&ddc>;
	nvidia,hpd-gpio = <&gpio TEGRA186_MAIN_GPIO(P, 1)
	GPIO_ACTIVE_LOW>;
	};

	dpaux@155c0000 {
	status = "okay";
	};
	};

	gpio-keys {
	compatible = "gpio-keys";

	power {
	label = "Power";
	gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0)
	GPIO_ACTIVE_LOW>;
	linux,input-type = <EV_KEY>;
	linux,code = <KEY_POWER>;
	debounce-interval = <10>;
	wakeup-event-action = <EV_ACT_ASSERTED>;
	wakeup-source;
	};

	volume-up {
	label = "Volume Up";
	gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1)
	GPIO_ACTIVE_LOW>;
	linux,input-type = <EV_KEY>;
	linux,code = <KEY_VOLUMEUP>;
	debounce-interval = <10>;
	};

	volume-down {
	label = "Volume Down";
	gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2)
	GPIO_ACTIVE_LOW>;
	linux,input-type = <EV_KEY>;
	linux,code = <KEY_VOLUMEDOWN>;
	debounce-interval = <10>;
	};
	};

	regulators {
	vdd_sd: regulator@100 {
	compatible = "regulator-fixed";
	reg = <100>;

	regulator-name = "SD_CARD_SW_PWR";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6)
	GPIO_ACTIVE_HIGH>;
	enable-active-high;

	vin-supply = <&vdd_3v3_sys>;
	};

	vdd_hdmi: regulator@101 {
	compatible = "regulator-fixed";
	reg = <101>;

	regulator-name = "VDD_HDMI_5V0";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;

	gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
	enable-active-high;

	vin-supply = <&vdd_5v0_sys>;
	};

	vdd_usb0: regulator@102 {
	compatible = "regulator-fixed";
	reg = <102>;

	regulator-name = "VDD_USB0";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;

	gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
	enable-active-high;

	vin-supply = <&vdd_5v0_sys>;
	};

	vdd_usb1: regulator@103 {
	compatible = "regulator-fixed";
	reg = <103>;

	regulator-name = "VDD_USB1";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;

	gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>;
	enable-active-high;

	vin-supply = <&vdd_5v0_sys>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/nvidia/tegra186-p3310.dtsi b/sys/gnu/dts/arm64/nvidia/tegra186-p3310.dtsi
	index 947744d0f04c..da96de04d003 100644
	--- a/sys/gnu/dts/arm64/nvidia/tegra186-p3310.dtsi
	+++ b/sys/gnu/dts/arm64/nvidia/tegra186-p3310.dtsi
	@@ -1,432 +1,433 @@
	// SPDX-License-Identifier: GPL-2.0
	#include "tegra186.dtsi"

	#include <dt-bindings/mfd/max77620.h>

	/ {
	model = "NVIDIA Jetson TX2";
	compatible = "nvidia,p3310", "nvidia,tegra186";

	aliases {
	ethernet0 = "/ethernet@2490000";
	sdhci0 = "/sdhci@3460000";
	sdhci1 = "/sdhci@3400000";
	serial0 = &uarta;
	i2c0 = "/bpmp/i2c";
	i2c1 = "/i2c@3160000";
	i2c2 = "/i2c@c240000";
	i2c3 = "/i2c@3180000";
	i2c4 = "/i2c@3190000";
	i2c5 = "/i2c@31c0000";
	i2c6 = "/i2c@c250000";
	i2c7 = "/i2c@31e0000";
	};

	chosen {
	bootargs = "earlycon console=ttyS0,115200n8";
	stdout-path = "serial0:115200n8";
	};

	memory {
	device_type = "memory";
	reg = <0x0 0x80000000 0x2 0x00000000>;
	};

	ethernet@2490000 {
	status = "okay";

	phy-reset-gpios = <&gpio TEGRA186_MAIN_GPIO(M, 4)
	GPIO_ACTIVE_LOW>;
	phy-handle = <&phy>;
	phy-mode = "rgmii";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	phy: phy@0 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <0x0>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA186_MAIN_GPIO(M, 5)
	IRQ_TYPE_LEVEL_LOW>;
	};
	};
	};

	memory-controller@2c00000 {
	status = "okay";
	};

	serial@3100000 {
	status = "okay";
	};

	i2c@3160000 {
	status = "okay";

	power-monitor@40 {
	compatible = "ti,ina3221";
	reg = <0x40>;
	#address-cells = <1>;
	#size-cells = <0>;

	channel@0 {
	reg = <0x0>;
	label = "VDD_SYS_GPU";
	shunt-resistor-micro-ohms = <10000>;
	};

	channel@1 {
	reg = <0x1>;
	label = "VDD_SYS_SOC";
	shunt-resistor-micro-ohms = <10000>;
	};

	channel@2 {
	reg = <0x2>;
	label = "VDD_3V8_WIFI";
	shunt-resistor-micro-ohms = <10000>;
	};
	};

	power-monitor@41 {
	compatible = "ti,ina3221";
	reg = <0x41>;
	#address-cells = <1>;
	#size-cells = <0>;

	channel@0 {
	reg = <0x0>;
	label = "VDD_IN";
	shunt-resistor-micro-ohms = <5000>;
	};

	channel@1 {
	reg = <0x1>;
	label = "VDD_SYS_CPU";
	shunt-resistor-micro-ohms = <10000>;
	};

	channel@2 {
	reg = <0x2>;
	label = "VDD_5V0_DDR";
	shunt-resistor-micro-ohms = <10000>;
	};
	};
	};

	i2c@3180000 {
	status = "okay";
	};

	ddc: i2c@3190000 {
	status = "okay";
	};

	i2c@31c0000 {
	status = "okay";
	};

	i2c@31e0000 {
	status = "okay";
	};

	/* SDMMC1 (SD/MMC) */
	sdhci@3400000 {
	cd-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>;

	vqmmc-supply = <&vddio_sdmmc1>;
	};

	/* SDMMC3 (SDIO) */
	sdhci@3440000 {
	status = "okay";
	};

	/* SDMMC4 (eMMC) */
	sdhci@3460000 {
	status = "okay";
	bus-width = <8>;
	non-removable;

	vqmmc-supply = <&vdd_1v8_ap>;
	vmmc-supply = <&vdd_3v3_sys>;
	};

	hsp@3c00000 {
	status = "okay";
	};

	i2c@c240000 {
	status = "okay";
	};

	i2c@c250000 {
	status = "okay";

	/* module ID EEPROM */
	eeprom@50 {
	compatible = "atmel,24c02";
	reg = <0x50>;

	+ vcc-supply = <&vdd_1v8>;
	address-bits = <8>;
	page-size = <8>;
	size = <256>;
	read-only;
	};
	};

	rtc@c2a0000 {
	status = "okay";
	};

	pmc@c360000 {
	nvidia,invert-interrupt;
	};

	cpus {
	cpu@0 {
	enable-method = "psci";
	};

	cpu@1 {
	enable-method = "psci";
	};

	cpu@2 {
	enable-method = "psci";
	};

	cpu@3 {
	enable-method = "psci";
	};

	cpu@4 {
	enable-method = "psci";
	};

	cpu@5 {
	enable-method = "psci";
	};
	};

	bpmp {
	i2c {
	status = "okay";

	pmic: pmic@3c {
	compatible = "maxim,max77620";
	reg = <0x3c>;

	interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <2>;
	interrupt-controller;

	#gpio-cells = <2>;
	gpio-controller;

	pinctrl-names = "default";
	pinctrl-0 = <&max77620_default>;

	max77620_default: pinmux {
	gpio0 {
	pins = "gpio0";
	function = "gpio";
	};

	gpio1 {
	pins = "gpio1";
	function = "fps-out";
	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
	};

	gpio2 {
	pins = "gpio2";
	function = "fps-out";
	maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
	};

	gpio3 {
	pins = "gpio3";
	function = "fps-out";
	maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
	};

	gpio4 {
	pins = "gpio4";
	function = "32k-out1";
	drive-push-pull = <1>;
	};

	gpio5 {
	pins = "gpio5";
	function = "gpio";
	drive-push-pull = <0>;
	};

	gpio6 {
	pins = "gpio6";
	function = "gpio";
	drive-push-pull = <1>;
	};

	gpio7 {
	pins = "gpio7";
	function = "gpio";
	drive-push-pull = <0>;
	};
	};

	fps {
	fps0 {
	maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
	maxim,shutdown-fps-time-period-us = <640>;
	};

	fps1 {
	maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
	maxim,shutdown-fps-time-period-us = <640>;
	};

	fps2 {
	maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
	maxim,shutdown-fps-time-period-us = <640>;
	};
	};

	regulators {
	in-sd0-supply = <&vdd_5v0_sys>;
	in-sd1-supply = <&vdd_5v0_sys>;
	in-sd2-supply = <&vdd_5v0_sys>;
	in-sd3-supply = <&vdd_5v0_sys>;

	in-ldo0-1-supply = <&vdd_5v0_sys>;
	in-ldo2-supply = <&vdd_5v0_sys>;
	in-ldo3-5-supply = <&vdd_5v0_sys>;
	in-ldo4-6-supply = <&vdd_1v8>;
	in-ldo7-8-supply = <&avdd_dsi_csi>;

	sd0 {
	regulator-name = "VDD_DDR_1V1_PMIC";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;
	regulator-boot-on;
	};

	avdd_dsi_csi: sd1 {
	regulator-name = "AVDD_DSI_CSI_1V2";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	vdd_1v8: sd2 {
	regulator-name = "VDD_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	vdd_3v3_sys: sd3 {
	regulator-name = "VDD_3V3_SYS";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	vdd_1v8_pll: ldo0 {
	regulator-name = "VDD_1V8_AP_PLL";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	ldo2 {
	regulator-name = "VDDIO_3V3_AOHV";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vddio_sdmmc1: ldo3 {
	regulator-name = "VDDIO_SDMMC1_AP";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	};

	ldo4 {
	regulator-name = "VDD_RTC";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	};

	vddio_sdmmc3: ldo5 {
	regulator-name = "VDDIO_SDMMC3_AP";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};

	vdd_hdmi_1v05: ldo7 {
	regulator-name = "VDD_HDMI_1V05";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	};

	vdd_pex: ldo8 {
	regulator-name = "VDD_PEX_1V05";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	};
	};
	};
	};
	};

	psci {
	compatible = "arm,psci-1.0";
	status = "okay";
	method = "smc";
	};

	regulators {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	gnd: regulator@0 {
	compatible = "regulator-fixed";
	reg = <0>;

	regulator-name = "GND";
	regulator-min-microvolt = <0>;
	regulator-max-microvolt = <0>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_5v0_sys: regulator@1 {
	compatible = "regulator-fixed";
	reg = <1>;

	regulator-name = "VDD_5V0_SYS";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_1v8_ap: regulator@2 {
	compatible = "regulator-fixed";
	reg = <2>;

	regulator-name = "VDD_1V8_AP";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
	enable-active-high;

	vin-supply = <&vdd_1v8>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/nvidia/tegra186.dtsi b/sys/gnu/dts/arm64/nvidia/tegra186.dtsi
	index c905527c26ef..58100fb9cd8b 100644
	--- a/sys/gnu/dts/arm64/nvidia/tegra186.dtsi
	+++ b/sys/gnu/dts/arm64/nvidia/tegra186.dtsi
	@@ -1,1454 +1,1473 @@
	// SPDX-License-Identifier: GPL-2.0
	#include <dt-bindings/clock/tegra186-clock.h>
	#include <dt-bindings/gpio/tegra186-gpio.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/mailbox/tegra186-hsp.h>
	#include <dt-bindings/memory/tegra186-mc.h>
	#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
	#include <dt-bindings/power/tegra186-powergate.h>
	#include <dt-bindings/reset/tegra186-reset.h>
	#include <dt-bindings/thermal/tegra186-bpmp-thermal.h>

	/ {
	compatible = "nvidia,tegra186";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	misc@100000 {
	compatible = "nvidia,tegra186-misc";
	reg = <0x0 0x00100000 0x0 0xf000>,
	<0x0 0x0010f000 0x0 0x1000>;
	};

	gpio: gpio@2200000 {
	compatible = "nvidia,tegra186-gpio";
	reg-names = "security", "gpio";
	reg = <0x0 0x2200000 0x0 0x10000>,
	<0x0 0x2210000 0x0 0x10000>;
	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <2>;
	interrupt-controller;
	#gpio-cells = <2>;
	gpio-controller;
	};

	ethernet@2490000 {
	compatible = "nvidia,tegra186-eqos",
	"snps,dwc-qos-ethernet-4.10";
	reg = <0x0 0x02490000 0x0 0x10000>;
	interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
	<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
	<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
	<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
	<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
	<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
	<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
	<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
	<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
	<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
	clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
	<&bpmp TEGRA186_CLK_EQOS_AXI>,
	<&bpmp TEGRA186_CLK_EQOS_RX>,
	<&bpmp TEGRA186_CLK_EQOS_TX>,
	<&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
	clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
	resets = <&bpmp TEGRA186_RESET_EQOS>;
	reset-names = "eqos";
	iommus = <&smmu TEGRA186_SID_EQOS>;
	status = "disabled";

	snps,write-requests = <1>;
	snps,read-requests = <3>;
	snps,burst-map = <0x7>;
	snps,txpbl = <32>;
	snps,rxpbl = <8>;
	};

	aconnect {
	compatible = "nvidia,tegra186-aconnect",
	"nvidia,tegra210-aconnect";
	clocks = <&bpmp TEGRA186_CLK_APE>,
	<&bpmp TEGRA186_CLK_APB2APE>;
	clock-names = "ape", "apb2ape";
	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x02900000 0x0 0x02900000 0x200000>;
	status = "disabled";

	dma-controller@2930000 {
	compatible = "nvidia,tegra186-adma";
	reg = <0x02930000 0x20000>;
	interrupt-parent = <&agic>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	clocks = <&bpmp TEGRA186_CLK_AHUB>;
	clock-names = "d_audio";
	status = "disabled";
	};

	agic: interrupt-controller@2a40000 {
	compatible = "nvidia,tegra186-agic",
	"nvidia,tegra210-agic";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x02a41000 0x1000>,
	<0x02a42000 0x2000>;
	interrupts = <GIC_SPI 145
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&bpmp TEGRA186_CLK_APE>;
	clock-names = "clk";
	status = "disabled";
	};
	};

	memory-controller@2c00000 {
	compatible = "nvidia,tegra186-mc";
	reg = <0x0 0x02c00000 0x0 0xb0000>;
	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";

	#address-cells = <2>;
	#size-cells = <2>;

	ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;

	/*
	* Memory clients have access to all 40 bits that the memory
	* controller can address.
	*/
	dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;

	emc: external-memory-controller@2c60000 {
	compatible = "nvidia,tegra186-emc";
	reg = <0x0 0x02c60000 0x0 0x50000>;
	interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_EMC>;
	clock-names = "emc";

	nvidia,bpmp = <&bpmp>;
	};
	};

	uarta: serial@3100000 {
	compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x03100000 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_UARTA>;
	clock-names = "serial";
	resets = <&bpmp TEGRA186_RESET_UARTA>;
	reset-names = "serial";
	status = "disabled";
	};

	uartb: serial@3110000 {
	compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x03110000 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_UARTB>;
	clock-names = "serial";
	resets = <&bpmp TEGRA186_RESET_UARTB>;
	reset-names = "serial";
	status = "disabled";
	};

	uartd: serial@3130000 {
	compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x03130000 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_UARTD>;
	clock-names = "serial";
	resets = <&bpmp TEGRA186_RESET_UARTD>;
	reset-names = "serial";
	status = "disabled";
	};

	uarte: serial@3140000 {
	compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x03140000 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_UARTE>;
	clock-names = "serial";
	resets = <&bpmp TEGRA186_RESET_UARTE>;
	reset-names = "serial";
	status = "disabled";
	};

	uartf: serial@3150000 {
	compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x03150000 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_UARTF>;
	clock-names = "serial";
	resets = <&bpmp TEGRA186_RESET_UARTF>;
	reset-names = "serial";
	status = "disabled";
	};

	gen1_i2c: i2c@3160000 {
	compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
	reg = <0x0 0x03160000 0x0 0x10000>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&bpmp TEGRA186_CLK_I2C1>;
	clock-names = "div-clk";
	resets = <&bpmp TEGRA186_RESET_I2C1>;
	reset-names = "i2c";
	status = "disabled";
	};

	cam_i2c: i2c@3180000 {
	compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
	reg = <0x0 0x03180000 0x0 0x10000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&bpmp TEGRA186_CLK_I2C3>;
	clock-names = "div-clk";
	resets = <&bpmp TEGRA186_RESET_I2C3>;
	reset-names = "i2c";
	status = "disabled";
	};

	/* shares pads with dpaux1 */
	dp_aux_ch1_i2c: i2c@3190000 {
	compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
	reg = <0x0 0x03190000 0x0 0x10000>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&bpmp TEGRA186_CLK_I2C4>;
	clock-names = "div-clk";
	resets = <&bpmp TEGRA186_RESET_I2C4>;
	reset-names = "i2c";
	pinctrl-names = "default", "idle";
	pinctrl-0 = <&state_dpaux1_i2c>;
	pinctrl-1 = <&state_dpaux1_off>;
	status = "disabled";
	};

	/* controlled by BPMP, should not be enabled */
	pwr_i2c: i2c@31a0000 {
	compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
	reg = <0x0 0x031a0000 0x0 0x10000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&bpmp TEGRA186_CLK_I2C5>;
	clock-names = "div-clk";
	resets = <&bpmp TEGRA186_RESET_I2C5>;
	reset-names = "i2c";
	status = "disabled";
	};

	/* shares pads with dpaux0 */
	dp_aux_ch0_i2c: i2c@31b0000 {
	compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
	reg = <0x0 0x031b0000 0x0 0x10000>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&bpmp TEGRA186_CLK_I2C6>;
	clock-names = "div-clk";
	resets = <&bpmp TEGRA186_RESET_I2C6>;
	reset-names = "i2c";
	pinctrl-names = "default", "idle";
	pinctrl-0 = <&state_dpaux_i2c>;
	pinctrl-1 = <&state_dpaux_off>;
	status = "disabled";
	};

	gen7_i2c: i2c@31c0000 {
	compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
	reg = <0x0 0x031c0000 0x0 0x10000>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&bpmp TEGRA186_CLK_I2C7>;
	clock-names = "div-clk";
	resets = <&bpmp TEGRA186_RESET_I2C7>;
	reset-names = "i2c";
	status = "disabled";
	};

	gen9_i2c: i2c@31e0000 {
	compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
	reg = <0x0 0x031e0000 0x0 0x10000>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&bpmp TEGRA186_CLK_I2C9>;
	clock-names = "div-clk";
	resets = <&bpmp TEGRA186_RESET_I2C9>;
	reset-names = "i2c";
	status = "disabled";
	};

	sdmmc1: sdhci@3400000 {
	compatible = "nvidia,tegra186-sdhci";
	reg = <0x0 0x03400000 0x0 0x10000>;
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
	clock-names = "sdhci";
	resets = <&bpmp TEGRA186_RESET_SDMMC1>;
	reset-names = "sdhci";
	iommus = <&smmu TEGRA186_SID_SDMMC1>;
	pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
	pinctrl-0 = <&sdmmc1_3v3>;
	pinctrl-1 = <&sdmmc1_1v8>;
	nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
	nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
	nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
	nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
	nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
	nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
	nvidia,default-tap = <0x5>;
	nvidia,default-trim = <0xb>;
	assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
	<&bpmp TEGRA186_CLK_PLLP_OUT0>;
	assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
	status = "disabled";
	};

	sdmmc2: sdhci@3420000 {
	compatible = "nvidia,tegra186-sdhci";
	reg = <0x0 0x03420000 0x0 0x10000>;
	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
	clock-names = "sdhci";
	resets = <&bpmp TEGRA186_RESET_SDMMC2>;
	reset-names = "sdhci";
	iommus = <&smmu TEGRA186_SID_SDMMC2>;
	pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
	pinctrl-0 = <&sdmmc2_3v3>;
	pinctrl-1 = <&sdmmc2_1v8>;
	nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
	nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
	nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
	nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
	nvidia,default-tap = <0x5>;
	nvidia,default-trim = <0xb>;
	status = "disabled";
	};

	sdmmc3: sdhci@3440000 {
	compatible = "nvidia,tegra186-sdhci";
	reg = <0x0 0x03440000 0x0 0x10000>;
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
	clock-names = "sdhci";
	resets = <&bpmp TEGRA186_RESET_SDMMC3>;
	reset-names = "sdhci";
	iommus = <&smmu TEGRA186_SID_SDMMC3>;
	pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
	pinctrl-0 = <&sdmmc3_3v3>;
	pinctrl-1 = <&sdmmc3_1v8>;
	nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
	nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
	nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
	nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
	nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
	nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
	nvidia,default-tap = <0x5>;
	nvidia,default-trim = <0xb>;
	status = "disabled";
	};

	sdmmc4: sdhci@3460000 {
	compatible = "nvidia,tegra186-sdhci";
	reg = <0x0 0x03460000 0x0 0x10000>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
	clock-names = "sdhci";
	assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
	<&bpmp TEGRA186_CLK_PLLC4_VCO>;
	assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
	resets = <&bpmp TEGRA186_RESET_SDMMC4>;
	reset-names = "sdhci";
	iommus = <&smmu TEGRA186_SID_SDMMC4>;
	nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
	nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
	nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
	nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
	nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
	nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
	nvidia,default-tap = <0x9>;
	nvidia,default-trim = <0x5>;
	nvidia,dqs-trim = <63>;
	mmc-hs400-1_8v;
	supports-cqe;
	status = "disabled";
	};

	hda@3510000 {
	compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
	reg = <0x0 0x03510000 0x0 0x10000>;
	interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_HDA>,
	<&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
	<&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
	clock-names = "hda", "hda2hdmi", "hda2codec_2x";
	resets = <&bpmp TEGRA186_RESET_HDA>,
	<&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
	<&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
	reset-names = "hda", "hda2hdmi", "hda2codec_2x";
	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
	iommus = <&smmu TEGRA186_SID_HDA>;
	status = "disabled";
	};

	padctl: padctl@3520000 {
	compatible = "nvidia,tegra186-xusb-padctl";
	reg = <0x0 0x03520000 0x0 0x1000>,
	<0x0 0x03540000 0x0 0x1000>;
	reg-names = "padctl", "ao";

	resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
	reset-names = "padctl";

	status = "disabled";

	pads {
	usb2 {
	clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
	clock-names = "trk";
	status = "disabled";

	lanes {
	usb2-0 {
	status = "disabled";
	#phy-cells = <0>;
	};

	usb2-1 {
	status = "disabled";
	#phy-cells = <0>;
	};

	usb2-2 {
	status = "disabled";
	#phy-cells = <0>;
	};
	};
	};

	hsic {
	clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
	clock-names = "trk";
	status = "disabled";

	lanes {
	hsic-0 {
	status = "disabled";
	#phy-cells = <0>;
	};
	};
	};

	usb3 {
	status = "disabled";

	lanes {
	usb3-0 {
	status = "disabled";
	#phy-cells = <0>;
	};

	usb3-1 {
	status = "disabled";
	#phy-cells = <0>;
	};

	usb3-2 {
	status = "disabled";
	#phy-cells = <0>;
	};
	};
	};
	};

	ports {
	usb2-0 {
	status = "disabled";
	};

	usb2-1 {
	status = "disabled";
	};

	usb2-2 {
	status = "disabled";
	};

	hsic-0 {
	status = "disabled";
	};

	usb3-0 {
	status = "disabled";
	};

	usb3-1 {
	status = "disabled";
	};

	usb3-2 {
	status = "disabled";
	};
	};
	};

	usb@3530000 {
	compatible = "nvidia,tegra186-xusb";
	reg = <0x0 0x03530000 0x0 0x8000>,
	<0x0 0x03538000 0x0 0x1000>;
	reg-names = "hcd", "fpci";
	interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
	<&bpmp TEGRA186_CLK_XUSB_FALCON>,
	<&bpmp TEGRA186_CLK_XUSB_SS>,
	<&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
	<&bpmp TEGRA186_CLK_CLK_M>,
	<&bpmp TEGRA186_CLK_XUSB_FS>,
	<&bpmp TEGRA186_CLK_PLLU>,
	<&bpmp TEGRA186_CLK_CLK_M>,
	<&bpmp TEGRA186_CLK_PLLE>;
	clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
	"xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
	"pll_u_480m", "clk_m", "pll_e";
	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
	<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
	power-domain-names = "xusb_host", "xusb_ss";
	iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";

	nvidia,xusb-padctl = <&padctl>;
	};

	+ usb@3550000 {
	+ compatible = "nvidia,tegra186-xudc";
	+ reg = <0x0 0x03550000 0x0 0x8000>,
	+ <0x0 0x03558000 0x0 0x1000>;
	+ reg-names = "base", "fpci";
	+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
	+ <&bpmp TEGRA186_CLK_XUSB_SS>,
	+ <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
	+ <&bpmp TEGRA186_CLK_XUSB_FS>;
	+ clock-names = "dev", "ss", "ss_src", "fs_src";
	+ iommus = <&smmu TEGRA186_SID_XUSB_DEV>;
	+ power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
	+ <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
	+ power-domain-names = "dev", "ss";
	+ nvidia,xusb-padctl = <&padctl>;
	+ status = "disabled";
	+ };
	+
	fuse@3820000 {
	compatible = "nvidia,tegra186-efuse";
	reg = <0x0 0x03820000 0x0 0x10000>;
	clocks = <&bpmp TEGRA186_CLK_FUSE>;
	clock-names = "fuse";
	};

	gic: interrupt-controller@3881000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x0 0x03881000 0x0 0x1000>,
	<0x0 0x03882000 0x0 0x2000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	interrupt-parent = <&gic>;
	};

	cec@3960000 {
	compatible = "nvidia,tegra186-cec";
	reg = <0x0 0x03960000 0x0 0x10000>;
	interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_CEC>;
	clock-names = "cec";
	status = "disabled";
	};

	hsp_top0: hsp@3c00000 {
	compatible = "nvidia,tegra186-hsp";
	reg = <0x0 0x03c00000 0x0 0xa0000>;
	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "doorbell";
	#mbox-cells = <2>;
	status = "disabled";
	};

	gen2_i2c: i2c@c240000 {
	compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
	reg = <0x0 0x0c240000 0x0 0x10000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&bpmp TEGRA186_CLK_I2C2>;
	clock-names = "div-clk";
	resets = <&bpmp TEGRA186_RESET_I2C2>;
	reset-names = "i2c";
	status = "disabled";
	};

	gen8_i2c: i2c@c250000 {
	compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
	reg = <0x0 0x0c250000 0x0 0x10000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&bpmp TEGRA186_CLK_I2C8>;
	clock-names = "div-clk";
	resets = <&bpmp TEGRA186_RESET_I2C8>;
	reset-names = "i2c";
	status = "disabled";
	};

	uartc: serial@c280000 {
	compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x0c280000 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_UARTC>;
	clock-names = "serial";
	resets = <&bpmp TEGRA186_RESET_UARTC>;
	reset-names = "serial";
	status = "disabled";
	};

	uartg: serial@c290000 {
	compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x0c290000 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_UARTG>;
	clock-names = "serial";
	resets = <&bpmp TEGRA186_RESET_UARTG>;
	reset-names = "serial";
	status = "disabled";
	};

	rtc: rtc@c2a0000 {
	compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
	reg = <0 0x0c2a0000 0 0x10000>;
	interrupt-parent = <&pmc>;
	interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
	clock-names = "rtc";
	status = "disabled";
	};

	gpio_aon: gpio@c2f0000 {
	compatible = "nvidia,tegra186-gpio-aon";
	reg-names = "security", "gpio";
	reg = <0x0 0xc2f0000 0x0 0x1000>,
	<0x0 0xc2f1000 0x0 0x1000>;
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	pmc: pmc@c360000 {
	compatible = "nvidia,tegra186-pmc";
	reg = <0 0x0c360000 0 0x10000>,
	<0 0x0c370000 0 0x10000>,
	<0 0x0c380000 0 0x10000>,
	<0 0x0c390000 0 0x10000>;
	reg-names = "pmc", "wake", "aotag", "scratch";

	#interrupt-cells = <2>;
	interrupt-controller;

	sdmmc1_3v3: sdmmc1-3v3 {
	pins = "sdmmc1-hv";
	power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
	};

	sdmmc1_1v8: sdmmc1-1v8 {
	pins = "sdmmc1-hv";
	power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
	};

	sdmmc2_3v3: sdmmc2-3v3 {
	pins = "sdmmc2-hv";
	power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
	};

	sdmmc2_1v8: sdmmc2-1v8 {
	pins = "sdmmc2-hv";
	power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
	};

	sdmmc3_3v3: sdmmc3-3v3 {
	pins = "sdmmc3-hv";
	power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
	};

	sdmmc3_1v8: sdmmc3-1v8 {
	pins = "sdmmc3-hv";
	power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
	};
	};

	ccplex@e000000 {
	compatible = "nvidia,tegra186-ccplex-cluster";
	reg = <0x0 0x0e000000 0x0 0x3fffff>;

	nvidia,bpmp = <&bpmp>;
	};

	pcie@10003000 {
	compatible = "nvidia,tegra186-pcie";
	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
	device_type = "pci";
	reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
	0x0 0x10003800 0x0 0x00000800 /* AFI registers */
	0x0 0x40000000 0x0 0x10000000>; /* configuration space */
	reg-names = "pads", "afi", "cs";

	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
	interrupt-names = "intr", "msi";

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;

	bus-range = <0x00 0xff>;
	#address-cells = <3>;
	#size-cells = <2>;

	ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
	0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
	0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
	0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
	0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
	0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */

	clocks = <&bpmp TEGRA186_CLK_AFI>,
	<&bpmp TEGRA186_CLK_PCIE>,
	<&bpmp TEGRA186_CLK_PLLE>;
	clock-names = "afi", "pex", "pll_e";

	resets = <&bpmp TEGRA186_RESET_AFI>,
	<&bpmp TEGRA186_RESET_PCIE>,
	<&bpmp TEGRA186_RESET_PCIEXCLK>;
	reset-names = "afi", "pex", "pcie_x";

	iommus = <&smmu TEGRA186_SID_AFI>;
	iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
	iommu-map-mask = <0x0>;

	status = "disabled";

	pci@1,0 {
	device_type = "pci";
	assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
	reg = <0x000800 0 0 0 0>;
	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	ranges;

	nvidia,num-lanes = <2>;
	};

	pci@2,0 {
	device_type = "pci";
	assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
	reg = <0x001000 0 0 0 0>;
	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	ranges;

	nvidia,num-lanes = <1>;
	};

	pci@3,0 {
	device_type = "pci";
	assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
	reg = <0x001800 0 0 0 0>;
	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	ranges;

	nvidia,num-lanes = <1>;
	};
	};

	smmu: iommu@12000000 {
	compatible = "arm,mmu-500";
	reg = <0 0x12000000 0 0x800000>;
	interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
	stream-match-mask = <0x7f80>;
	#global-interrupts = <1>;
	#iommu-cells = <1>;
	};

	host1x@13e00000 {
	compatible = "nvidia,tegra186-host1x", "simple-bus";
	reg = <0x0 0x13e00000 0x0 0x10000>,
	<0x0 0x13e10000 0x0 0x10000>;
	reg-names = "hypervisor", "vm";
	interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_HOST1X>;
	clock-names = "host1x";
	resets = <&bpmp TEGRA186_RESET_HOST1X>;
	reset-names = "host1x";

	#address-cells = <1>;
	#size-cells = <1>;

	ranges = <0x15000000 0x0 0x15000000 0x01000000>;
	iommus = <&smmu TEGRA186_SID_HOST1X>;

	dpaux1: dpaux@15040000 {
	compatible = "nvidia,tegra186-dpaux";
	reg = <0x15040000 0x10000>;
	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
	<&bpmp TEGRA186_CLK_PLLDP>;
	clock-names = "dpaux", "parent";
	resets = <&bpmp TEGRA186_RESET_DPAUX1>;
	reset-names = "dpaux";
	status = "disabled";

	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

	state_dpaux1_aux: pinmux-aux {
	groups = "dpaux-io";
	function = "aux";
	};

	state_dpaux1_i2c: pinmux-i2c {
	groups = "dpaux-io";
	function = "i2c";
	};

	state_dpaux1_off: pinmux-off {
	groups = "dpaux-io";
	function = "off";
	};

	i2c-bus {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	display-hub@15200000 {
	compatible = "nvidia,tegra186-display", "simple-bus";
	reg = <0x15200000 0x00040000>;
	resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
	<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
	<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
	<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
	<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
	<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
	<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
	reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
	"wgrp3", "wgrp4", "wgrp5";
	clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
	<&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
	<&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
	clock-names = "disp", "dsc", "hub";
	status = "disabled";

	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

	#address-cells = <1>;
	#size-cells = <1>;

	ranges = <0x15200000 0x15200000 0x40000>;

	display@15200000 {
	compatible = "nvidia,tegra186-dc";
	reg = <0x15200000 0x10000>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
	clock-names = "dc";
	resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
	reset-names = "dc";

	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
	iommus = <&smmu TEGRA186_SID_NVDISPLAY>;

	nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
	nvidia,head = <0>;
	};

	display@15210000 {
	compatible = "nvidia,tegra186-dc";
	reg = <0x15210000 0x10000>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
	clock-names = "dc";
	resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
	reset-names = "dc";

	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
	iommus = <&smmu TEGRA186_SID_NVDISPLAY>;

	nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
	nvidia,head = <1>;
	};

	display@15220000 {
	compatible = "nvidia,tegra186-dc";
	reg = <0x15220000 0x10000>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
	clock-names = "dc";
	resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
	reset-names = "dc";

	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
	iommus = <&smmu TEGRA186_SID_NVDISPLAY>;

	nvidia,outputs = <&sor0 &sor1>;
	nvidia,head = <2>;
	};
	};

	dsia: dsi@15300000 {
	compatible = "nvidia,tegra186-dsi";
	reg = <0x15300000 0x10000>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_DSI>,
	<&bpmp TEGRA186_CLK_DSIA_LP>,
	<&bpmp TEGRA186_CLK_PLLD>;
	clock-names = "dsi", "lp", "parent";
	resets = <&bpmp TEGRA186_RESET_DSI>;
	reset-names = "dsi";
	status = "disabled";

	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
	};

	vic@15340000 {
	compatible = "nvidia,tegra186-vic";
	reg = <0x15340000 0x40000>;
	interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_VIC>;
	clock-names = "vic";
	resets = <&bpmp TEGRA186_RESET_VIC>;
	reset-names = "vic";

	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
	iommus = <&smmu TEGRA186_SID_VIC>;
	};

	dsib: dsi@15400000 {
	compatible = "nvidia,tegra186-dsi";
	reg = <0x15400000 0x10000>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_DSIB>,
	<&bpmp TEGRA186_CLK_DSIB_LP>,
	<&bpmp TEGRA186_CLK_PLLD>;
	clock-names = "dsi", "lp", "parent";
	resets = <&bpmp TEGRA186_RESET_DSIB>;
	reset-names = "dsi";
	status = "disabled";

	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
	};

	sor0: sor@15540000 {
	compatible = "nvidia,tegra186-sor";
	reg = <0x15540000 0x10000>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_SOR0>,
	<&bpmp TEGRA186_CLK_SOR0_OUT>,
	<&bpmp TEGRA186_CLK_PLLD2>,
	<&bpmp TEGRA186_CLK_PLLDP>,
	<&bpmp TEGRA186_CLK_SOR_SAFE>,
	<&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
	clock-names = "sor", "out", "parent", "dp", "safe",
	"pad";
	resets = <&bpmp TEGRA186_RESET_SOR0>;
	reset-names = "sor";
	pinctrl-0 = <&state_dpaux_aux>;
	pinctrl-1 = <&state_dpaux_i2c>;
	pinctrl-2 = <&state_dpaux_off>;
	pinctrl-names = "aux", "i2c", "off";
	status = "disabled";

	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
	nvidia,interface = <0>;
	};

	sor1: sor@15580000 {
	compatible = "nvidia,tegra186-sor";
	reg = <0x15580000 0x10000>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_SOR1>,
	<&bpmp TEGRA186_CLK_SOR1_OUT>,
	<&bpmp TEGRA186_CLK_PLLD3>,
	<&bpmp TEGRA186_CLK_PLLDP>,
	<&bpmp TEGRA186_CLK_SOR_SAFE>,
	<&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
	clock-names = "sor", "out", "parent", "dp", "safe",
	"pad";
	resets = <&bpmp TEGRA186_RESET_SOR1>;
	reset-names = "sor";
	pinctrl-0 = <&state_dpaux1_aux>;
	pinctrl-1 = <&state_dpaux1_i2c>;
	pinctrl-2 = <&state_dpaux1_off>;
	pinctrl-names = "aux", "i2c", "off";
	status = "disabled";

	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
	nvidia,interface = <1>;
	};

	dpaux: dpaux@155c0000 {
	compatible = "nvidia,tegra186-dpaux";
	reg = <0x155c0000 0x10000>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_DPAUX>,
	<&bpmp TEGRA186_CLK_PLLDP>;
	clock-names = "dpaux", "parent";
	resets = <&bpmp TEGRA186_RESET_DPAUX>;
	reset-names = "dpaux";
	status = "disabled";

	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

	state_dpaux_aux: pinmux-aux {
	groups = "dpaux-io";
	function = "aux";
	};

	state_dpaux_i2c: pinmux-i2c {
	groups = "dpaux-io";
	function = "i2c";
	};

	state_dpaux_off: pinmux-off {
	groups = "dpaux-io";
	function = "off";
	};

	i2c-bus {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	padctl@15880000 {
	compatible = "nvidia,tegra186-dsi-padctl";
	reg = <0x15880000 0x10000>;
	resets = <&bpmp TEGRA186_RESET_DSI>;
	reset-names = "dsi";
	status = "disabled";
	};

	dsic: dsi@15900000 {
	compatible = "nvidia,tegra186-dsi";
	reg = <0x15900000 0x10000>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_DSIC>,
	<&bpmp TEGRA186_CLK_DSIC_LP>,
	<&bpmp TEGRA186_CLK_PLLD>;
	clock-names = "dsi", "lp", "parent";
	resets = <&bpmp TEGRA186_RESET_DSIC>;
	reset-names = "dsi";
	status = "disabled";

	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
	};

	dsid: dsi@15940000 {
	compatible = "nvidia,tegra186-dsi";
	reg = <0x15940000 0x10000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA186_CLK_DSID>,
	<&bpmp TEGRA186_CLK_DSID_LP>,
	<&bpmp TEGRA186_CLK_PLLD>;
	clock-names = "dsi", "lp", "parent";
	resets = <&bpmp TEGRA186_RESET_DSID>;
	reset-names = "dsi";
	status = "disabled";

	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
	};
	};

	gpu@17000000 {
	compatible = "nvidia,gp10b";
	reg = <0x0 0x17000000 0x0 0x1000000>,
	<0x0 0x18000000 0x0 0x1000000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
	GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "stall", "nonstall";

	clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
	<&bpmp TEGRA186_CLK_GPU>;
	clock-names = "gpu", "pwr";
	resets = <&bpmp TEGRA186_RESET_GPU>;
	reset-names = "gpu";
	status = "disabled";

	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
	};

	sysram@30000000 {
	compatible = "nvidia,tegra186-sysram", "mmio-sram";
	reg = <0x0 0x30000000 0x0 0x50000>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;

	cpu_bpmp_tx: shmem@4e000 {
	compatible = "nvidia,tegra186-bpmp-shmem";
	reg = <0x0 0x4e000 0x0 0x1000>;
	label = "cpu-bpmp-tx";
	pool;
	};

	cpu_bpmp_rx: shmem@4f000 {
	compatible = "nvidia,tegra186-bpmp-shmem";
	reg = <0x0 0x4f000 0x0 0x1000>;
	label = "cpu-bpmp-rx";
	pool;
	};
	};

	bpmp: bpmp {
	compatible = "nvidia,tegra186-bpmp";
	iommus = <&smmu TEGRA186_SID_BPMP>;
	mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
	TEGRA_HSP_DB_MASTER_BPMP>;
	shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;

	bpmp_i2c: i2c {
	compatible = "nvidia,tegra186-bpmp-i2c";
	nvidia,bpmp-bus-id = <5>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	bpmp_thermal: thermal {
	compatible = "nvidia,tegra186-bpmp-thermal";
	#thermal-sensor-cells = <1>;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	compatible = "nvidia,tegra186-denver";
	device_type = "cpu";
	i-cache-size = <0x20000>;
	i-cache-line-size = <64>;
	i-cache-sets = <512>;
	d-cache-size = <0x10000>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&L2_DENVER>;
	reg = <0x000>;
	};

	cpu@1 {
	compatible = "nvidia,tegra186-denver";
	device_type = "cpu";
	i-cache-size = <0x20000>;
	i-cache-line-size = <64>;
	i-cache-sets = <512>;
	d-cache-size = <0x10000>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&L2_DENVER>;
	reg = <0x001>;
	};

	cpu@2 {
	compatible = "arm,cortex-a57";
	device_type = "cpu";
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <256>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&L2_A57>;
	reg = <0x100>;
	};

	cpu@3 {
	compatible = "arm,cortex-a57";
	device_type = "cpu";
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <256>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&L2_A57>;
	reg = <0x101>;
	};

	cpu@4 {
	compatible = "arm,cortex-a57";
	device_type = "cpu";
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <256>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&L2_A57>;
	reg = <0x102>;
	};

	cpu@5 {
	compatible = "arm,cortex-a57";
	device_type = "cpu";
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <256>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&L2_A57>;
	reg = <0x103>;
	};

	L2_DENVER: l2-cache0 {
	compatible = "cache";
	cache-unified;
	cache-level = <2>;
	cache-size = <0x200000>;
	cache-line-size = <64>;
	cache-sets = <2048>;
	};

	L2_A57: l2-cache1 {
	compatible = "cache";
	cache-unified;
	cache-level = <2>;
	cache-size = <0x200000>;
	cache-line-size = <64>;
	cache-sets = <2048>;
	};
	};

	thermal-zones {
	a57 {
	polling-delay = <0>;
	polling-delay-passive = <1000>;

	thermal-sensors =
	<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;

	trips {
	critical {
	temperature = <101000>;
	hysteresis = <0>;
	type = "critical";
	};
	};

	cooling-maps {
	};
	};

	denver {
	polling-delay = <0>;
	polling-delay-passive = <1000>;

	thermal-sensors =
	<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;

	trips {
	critical {
	temperature = <101000>;
	hysteresis = <0>;
	type = "critical";
	};
	};

	cooling-maps {
	};
	};

	gpu {
	polling-delay = <0>;
	polling-delay-passive = <1000>;

	thermal-sensors =
	<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;

	trips {
	critical {
	temperature = <101000>;
	hysteresis = <0>;
	type = "critical";
	};
	};

	cooling-maps {
	};
	};

	pll {
	polling-delay = <0>;
	polling-delay-passive = <1000>;

	thermal-sensors =
	<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;

	trips {
	critical {
	temperature = <101000>;
	hysteresis = <0>;
	type = "critical";
	};
	};

	cooling-maps {
	};
	};

	always_on {
	polling-delay = <0>;
	polling-delay-passive = <1000>;

	thermal-sensors =
	<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;

	trips {
	critical {
	temperature = <101000>;
	hysteresis = <0>;
	type = "critical";
	};
	};

	cooling-maps {
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	interrupt-parent = <&gic>;
	always-on;
	};
	};
	diff --git a/sys/gnu/dts/arm64/nvidia/tegra194-p2888.dtsi b/sys/gnu/dts/arm64/nvidia/tegra194-p2888.dtsi
	index bdd33ff4e324..623f7d7d216b 100644
	--- a/sys/gnu/dts/arm64/nvidia/tegra194-p2888.dtsi
	+++ b/sys/gnu/dts/arm64/nvidia/tegra194-p2888.dtsi
	@@ -1,321 +1,355 @@
	// SPDX-License-Identifier: GPL-2.0
	#include "tegra194.dtsi"

	#include <dt-bindings/mfd/max77620.h>

	/ {
	model = "NVIDIA Jetson AGX Xavier";
	compatible = "nvidia,p2888", "nvidia,tegra194";

	aliases {
	ethernet0 = "/cbb@0/ethernet@2490000";
	sdhci0 = "/cbb@0/sdhci@3460000";
	sdhci1 = "/cbb@0/sdhci@3400000";
	serial0 = &tcu;
	i2c0 = "/bpmp/i2c";
	i2c1 = "/cbb@0/i2c@3160000";
	i2c2 = "/cbb@0/i2c@c240000";
	i2c3 = "/cbb@0/i2c@3180000";
	i2c4 = "/cbb@0/i2c@3190000";
	i2c5 = "/cbb@0/i2c@31c0000";
	i2c6 = "/cbb@0/i2c@c250000";
	i2c7 = "/cbb@0/i2c@31e0000";
	};

	chosen {
	bootargs = "console=ttyS0,115200n8";
	stdout-path = "serial0:115200n8";
	};

	cbb@0 {
	ethernet@2490000 {
	status = "okay";

	phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>;
	phy-handle = <&phy>;
	phy-mode = "rgmii";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	phy: phy@0 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <0x0>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA194_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
	};
	};
	};

	memory-controller@2c00000 {
	status = "okay";
	};

	serial@3110000 {
	status = "okay";
	};

	/* SDMMC1 (SD/MMC) */
	sdhci@3400000 {
	cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>;
	};

	/* SDMMC4 (eMMC) */
	sdhci@3460000 {
	status = "okay";
	bus-width = <8>;
	non-removable;

	vqmmc-supply = <&vdd_1v8ls>;
	vmmc-supply = <&vdd_emmc_3v3>;
	};

	+ padctl@3520000 {
	+ avdd-usb-supply = <&vdd_usb_3v3>;
	+ vclamp-usb-supply = <&vdd_1v8ao>;
	+
	+ ports {
	+ usb2-1 {
	+ vbus-supply = <&vdd_5v0_sys>;
	+ };
	+
	+ usb2-3 {
	+ vbus-supply = <&vdd_5v_sata>;
	+ };
	+
	+ usb3-0 {
	+ vbus-supply = <&vdd_5v0_sys>;
	+ };
	+
	+ usb3-3 {
	+ vbus-supply = <&vdd_5v0_sys>;
	+ };
	+ };
	+ };
	+
	rtc@c2a0000 {
	status = "okay";
	};

	pmc@c360000 {
	nvidia,invert-interrupt;
	};
	};

	bpmp {
	i2c {
	status = "okay";

	pmic: pmic@3c {
	compatible = "maxim,max20024";
	reg = <0x3c>;

	interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <2>;
	interrupt-controller;

	#gpio-cells = <2>;
	gpio-controller;

	pinctrl-names = "default";
	pinctrl-0 = <&max20024_default>;

	max20024_default: pinmux {
	gpio0 {
	pins = "gpio0";
	function = "gpio";
	};

	gpio1 {
	pins = "gpio1";
	function = "fps-out";
	maxim,active-fps-source = <MAX77620_FPS_SRC_DEF>;
	};

	gpio2 {
	pins = "gpio2";
	function = "fps-out";
	maxim,active-fps-source = <MAX77620_FPS_SRC_DEF>;
	};

	gpio3 {
	pins = "gpio3";
	function = "fps-out";
	maxim,active-fps-source = <MAX77620_FPS_SRC_DEF>;
	};

	gpio4 {
	pins = "gpio4";
	function = "32k-out1";
	drive-push-pull = <1>;
	};

	gpio6 {
	pins = "gpio6";
	function = "gpio";
	drive-push-pull = <1>;
	};

	gpio7 {
	pins = "gpio7";
	function = "gpio";
	drive-push-pull = <0>;
	};
	};

	fps {
	fps0 {
	maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
	maxim,shutdown-fps-time-period-us = <640>;
	};

	fps1 {
	maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
	maxim,shutdown-fps-time-period-us = <640>;
	maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>;
	};

	fps2 {
	maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
	maxim,shutdown-fps-time-period-us = <640>;
	};
	};

	regulators {
	in-sd0-supply = <&vdd_5v0_sys>;
	in-sd1-supply = <&vdd_5v0_sys>;
	in-sd2-supply = <&vdd_5v0_sys>;
	in-sd3-supply = <&vdd_5v0_sys>;
	in-sd4-supply = <&vdd_5v0_sys>;

	in-ldo0-1-supply = <&vdd_5v0_sys>;
	in-ldo2-supply = <&vdd_5v0_sys>;
	in-ldo3-5-supply = <&vdd_5v0_sys>;
	in-ldo4-6-supply = <&vdd_5v0_sys>;
	in-ldo7-8-supply = <&vdd_1v8ls>;

	vdd_1v0: sd0 {
	regulator-name = "VDDIO_SYS_1V0";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_1v8hs: sd1 {
	regulator-name = "VDDIO_SYS_1V8HS";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_1v8ls: sd2 {
	regulator-name = "VDDIO_SYS_1V8LS";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_1v8ao: sd3 {
	regulator-name = "VDDIO_AO_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	sd4 {
	regulator-name = "VDD_DDR_1V1";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldo0 {
	regulator-name = "VDD_RTC";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldo2 {
	regulator-name = "VDDIO_AO_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_emmc_3v3: ldo3 {
	regulator-name = "VDD_EMMC_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	- ldo5 {
	+ vdd_usb_3v3: ldo5 {
	regulator-name = "VDD_USB_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	ldo6 {
	regulator-name = "VDD_SDIO_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	ldo7 {
	regulator-name = "AVDD_CSI_1V2";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};
	};
	};

	temperature-sensor@4c {
	compatible = "ti,tmp451";
	reg = <0x4c>;

	interrupt-parent = <&gpio>;
	interrupts = <TEGRA194_MAIN_GPIO(H, 2)
	IRQ_TYPE_LEVEL_LOW>;
	vcc-supply = <&vdd_1v8ls>;

	#thermal-sensor-cells = <1>;
	};
	};
	};

	regulators {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	vdd_5v0_sys: regulator@0 {
	compatible = "regulator-fixed";
	reg = <0>;

	regulator-name = "VIN_SYS_5V0";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_hdmi: regulator@1 {
	compatible = "regulator-fixed";
	reg = <1>;

	regulator-name = "VDD_5V0_HDMI_CON";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio TEGRA194_MAIN_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vdd_3v3_pcie: regulator@2 {
	compatible = "regulator-fixed";
	reg = <2>;

	regulator-name = "PEX_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
	regulator-boot-on;
	enable-active-high;
	};

	vdd_12v_pcie: regulator@3 {
	compatible = "regulator-fixed";
	reg = <3>;

	regulator-name = "VDD_12V";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_HIGH>;
	regulator-boot-on;
	};
	+
	+ vdd_5v_sata: regulator@4 {
	+ compatible = "regulator-fixed";
	+ reg = <4>;
	+
	+ regulator-name = "VDD_5V_SATA";
	+ regulator-min-microvolt = <5000000>;
	+ regulator-max-microvolt = <5000000>;
	+ gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1) GPIO_ACTIVE_HIGH>;
	+ enable-active-high;
	+ };
	};
	};
	diff --git a/sys/gnu/dts/arm64/nvidia/tegra194-p2972-0000.dts b/sys/gnu/dts/arm64/nvidia/tegra194-p2972-0000.dts
	index 985e7d84f161..e15d1eac05f5 100644
	--- a/sys/gnu/dts/arm64/nvidia/tegra194-p2972-0000.dts
	+++ b/sys/gnu/dts/arm64/nvidia/tegra194-p2972-0000.dts
	@@ -1,254 +1,335 @@
	// SPDX-License-Identifier: GPL-2.0
	/dts-v1/;

	#include <dt-bindings/input/linux-event-codes.h>
	#include <dt-bindings/input/gpio-keys.h>

	#include "tegra194-p2888.dtsi"

	/ {
	model = "NVIDIA Jetson AGX Xavier Developer Kit";
	compatible = "nvidia,p2972-0000", "nvidia,tegra194";

	cbb@0 {
	aconnect@2900000 {
	status = "okay";

	dma-controller@2930000 {
	status = "okay";
	};

	interrupt-controller@2a40000 {
	status = "okay";
	};
	};

	ddc: i2c@31c0000 {
	status = "okay";
	};

	/* SDMMC1 (SD/MMC) */
	sdhci@3400000 {
	status = "okay";
	};

	hda@3510000 {
	nvidia,model = "jetson-xavier-hda";
	status = "okay";
	};

	+ padctl@3520000 {
	+ status = "okay";
	+
	+ pads {
	+ usb2 {
	+ lanes {
	+ usb2-1 {
	+ status = "okay";
	+ };
	+
	+ usb2-3 {
	+ status = "okay";
	+ };
	+ };
	+ };
	+
	+ usb3 {
	+ lanes {
	+ usb3-0 {
	+ status = "okay";
	+ };
	+
	+ usb3-3 {
	+ status = "okay";
	+ };
	+ };
	+ };
	+ };
	+
	+ ports {
	+ usb2-1 {
	+ mode = "host";
	+ status = "okay";
	+ };
	+
	+ usb2-3 {
	+ mode = "host";
	+ status = "okay";
	+ };
	+
	+ usb3-0 {
	+ nvidia,usb2-companion = <1>;
	+ status = "okay";
	+ };
	+
	+ usb3-3 {
	+ nvidia,usb2-companion = <3>;
	+ maximum-speed = "super-speed";
	+ status = "okay";
	+ };
	+ };
	+ };
	+
	+ usb@3610000 {
	+ status = "okay";
	+
	+ phys = <&{/cbb@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
	+ <&{/cbb@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
	+ <&{/cbb@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
	+ <&{/cbb@0/padctl@3520000/pads/usb3/lanes/usb3-3}>;
	+ phy-names = "usb2-1", "usb2-3", "usb3-0", "usb3-3";
	+ };
	+
	pwm@c340000 {
	status = "okay";
	};

	host1x@13e00000 {
	display-hub@15200000 {
	status = "okay";
	};

	dpaux@155c0000 {
	status = "okay";
	};

	dpaux@155d0000 {
	status = "okay";
	};

	dpaux@155e0000 {
	status = "okay";
	};

	/* DP0 */
	sor@15b00000 {
	status = "okay";

	avdd-io-hdmi-dp-supply = <&vdd_1v0>;
	vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>;

	nvidia,dpaux = <&dpaux0>;
	};

	/* DP1 */
	sor@15b40000 {
	status = "okay";

	avdd-io-hdmi-dp-supply = <&vdd_1v0>;
	vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>;

	nvidia,dpaux = <&dpaux1>;
	};

	/* HDMI */
	sor@15b80000 {
	status = "okay";

	avdd-io-supply = <&vdd_1v0>;
	vdd-pll-supply = <&vdd_1v8hs>;
	hdmi-supply = <&vdd_hdmi>;

	nvidia,ddc-i2c-bus = <&ddc>;
	nvidia,hpd-gpio = <&gpio TEGRA194_MAIN_GPIO(M, 2)
	GPIO_ACTIVE_LOW>;
	};
	};
	};

	pcie@14100000 {
	status = "okay";

	vddio-pex-ctl-supply = <&vdd_1v8ao>;

	phys = <&p2u_hsio_0>;
	phy-names = "p2u-0";
	};

	pcie@14140000 {
	status = "okay";

	vddio-pex-ctl-supply = <&vdd_1v8ao>;

	phys = <&p2u_hsio_7>;
	phy-names = "p2u-0";
	};

	pcie@14180000 {
	status = "okay";

	vddio-pex-ctl-supply = <&vdd_1v8ao>;

	phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
	<&p2u_hsio_5>;
	phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
	};

	pcie@141a0000 {
	status = "okay";

	vddio-pex-ctl-supply = <&vdd_1v8ao>;
	vpcie3v3-supply = <&vdd_3v3_pcie>;
	vpcie12v-supply = <&vdd_12v_pcie>;

	phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
	<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
	<&p2u_nvhs_6>, <&p2u_nvhs_7>;

	phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
	"p2u-5", "p2u-6", "p2u-7";
	};

	+ pcie_ep@141a0000 {
	+ status = "disabled";
	+
	+ vddio-pex-ctl-supply = <&vdd_1v8ao>;
	+
	+ reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
	+
	+ nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
	+ GPIO_ACTIVE_HIGH>;
	+
	+ phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
	+ <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
	+ <&p2u_nvhs_6>, <&p2u_nvhs_7>;
	+
	+ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
	+ "p2u-5", "p2u-6", "p2u-7";
	+ };
	+
	fan: fan {
	compatible = "pwm-fan";
	pwms = <&pwm4 0 45334>;

	cooling-levels = <0 64 128 255>;
	#cooling-cells = <2>;
	};

	gpio-keys {
	compatible = "gpio-keys";

	force-recovery {
	label = "Force Recovery";
	gpios = <&gpio TEGRA194_MAIN_GPIO(G, 0)
	GPIO_ACTIVE_LOW>;
	linux,input-type = <EV_KEY>;
	linux,code = <KEY_SLEEP>;
	debounce-interval = <10>;
	};

	power {
	label = "Power";
	gpios = <&gpio_aon TEGRA194_AON_GPIO(EE, 4)
	GPIO_ACTIVE_LOW>;
	linux,input-type = <EV_KEY>;
	linux,code = <KEY_POWER>;
	debounce-interval = <10>;
	wakeup-event-action = <EV_ACT_ASSERTED>;
	wakeup-source;
	};
	};

	thermal-zones {
	cpu {
	polling-delay = <0>;
	polling-delay-passive = <500>;
	status = "okay";

	trips {
	cpu_trip_critical: critical {
	temperature = <96500>;
	hysteresis = <0>;
	type = "critical";
	};

	cpu_trip_hot: hot {
	temperature = <70000>;
	hysteresis = <2000>;
	type = "hot";
	};

	cpu_trip_active: active {
	temperature = <50000>;
	hysteresis = <2000>;
	type = "active";
	};

	cpu_trip_passive: passive {
	temperature = <30000>;
	hysteresis = <2000>;
	type = "passive";
	};
	};

	cooling-maps {
	cpu-critical {
	cooling-device = <&fan 3 3>;
	trip = <&cpu_trip_critical>;
	};

	cpu-hot {
	cooling-device = <&fan 2 2>;
	trip = <&cpu_trip_hot>;
	};

	cpu-active {
	cooling-device = <&fan 1 1>;
	trip = <&cpu_trip_active>;
	};

	cpu-passive {
	cooling-device = <&fan 0 0>;
	trip = <&cpu_trip_passive>;
	};
	};
	};

	gpu {
	polling-delay = <0>;
	polling-delay-passive = <500>;
	status = "okay";

	trips {
	gpu_alert0: critical {
	temperature = <99000>;
	hysteresis = <0>;
	type = "critical";
	};
	};
	};

	aux {
	polling-delay = <0>;
	polling-delay-passive = <500>;
	status = "okay";

	trips {
	aux_alert0: critical {
	temperature = <90000>;
	hysteresis = <0>;
	type = "critical";
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/nvidia/tegra194.dtsi b/sys/gnu/dts/arm64/nvidia/tegra194.dtsi
	index ccac43be12ac..f4ede86e32b4 100644
	--- a/sys/gnu/dts/arm64/nvidia/tegra194.dtsi
	+++ b/sys/gnu/dts/arm64/nvidia/tegra194.dtsi
	@@ -1,1785 +1,2023 @@
	// SPDX-License-Identifier: GPL-2.0
	#include <dt-bindings/clock/tegra194-clock.h>
	#include <dt-bindings/gpio/tegra194-gpio.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/mailbox/tegra186-hsp.h>
	#include <dt-bindings/pinctrl/pinctrl-tegra.h>
	#include <dt-bindings/power/tegra194-powergate.h>
	#include <dt-bindings/reset/tegra194-reset.h>
	#include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
	#include <dt-bindings/memory/tegra194-mc.h>

	/ {
	compatible = "nvidia,tegra194";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	/* control backbone */
	cbb@0 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x0 0x40000000>;

	misc@100000 {
	compatible = "nvidia,tegra194-misc";
	reg = <0x00100000 0xf000>,
	<0x0010f000 0x1000>;
	};

	gpio: gpio@2200000 {
	compatible = "nvidia,tegra194-gpio";
	reg-names = "security", "gpio";
	reg = <0x2200000 0x10000>,
	<0x2210000 0x10000>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <2>;
	interrupt-controller;
	#gpio-cells = <2>;
	gpio-controller;
	};

	ethernet@2490000 {
	compatible = "nvidia,tegra194-eqos",
	"nvidia,tegra186-eqos",
	"snps,dwc-qos-ethernet-4.10";
	reg = <0x02490000 0x10000>;
	interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
	<&bpmp TEGRA194_CLK_EQOS_AXI>,
	<&bpmp TEGRA194_CLK_EQOS_RX>,
	<&bpmp TEGRA194_CLK_EQOS_TX>,
	<&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
	clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
	resets = <&bpmp TEGRA194_RESET_EQOS>;
	reset-names = "eqos";
	status = "disabled";

	snps,write-requests = <1>;
	snps,read-requests = <3>;
	snps,burst-map = <0x7>;
	snps,txpbl = <16>;
	snps,rxpbl = <8>;
	};

	aconnect@2900000 {
	compatible = "nvidia,tegra194-aconnect",
	"nvidia,tegra210-aconnect";
	clocks = <&bpmp TEGRA194_CLK_APE>,
	<&bpmp TEGRA194_CLK_APB2APE>;
	clock-names = "ape", "apb2ape";
	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x02900000 0x02900000 0x200000>;
	status = "disabled";

	dma-controller@2930000 {
	compatible = "nvidia,tegra194-adma",
	"nvidia,tegra186-adma";
	reg = <0x02930000 0x20000>;
	interrupt-parent = <&agic>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	clocks = <&bpmp TEGRA194_CLK_AHUB>;
	clock-names = "d_audio";
	status = "disabled";
	};

	agic: interrupt-controller@2a40000 {
	compatible = "nvidia,tegra194-agic",
	"nvidia,tegra210-agic";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x02a41000 0x1000>,
	<0x02a42000 0x2000>;
	interrupts = <GIC_SPI 145
	(GIC_CPU_MASK_SIMPLE(4) \|
	IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&bpmp TEGRA194_CLK_APE>;
	clock-names = "clk";
	status = "disabled";
	};
	};

	pinmux: pinmux@2430000 {
	compatible = "nvidia,tegra194-pinmux";
	reg = <0x2430000 0x17000
	0xc300000 0x4000>;

	status = "okay";

	pex_rst_c5_out_state: pex_rst_c5_out {
	pex_rst {
	nvidia,pins = "pex_l5_rst_n_pgg1";
	nvidia,schmitt = <TEGRA_PIN_DISABLE>;
	nvidia,lpdr = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	};
	};

	clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
	clkreq {
	nvidia,pins = "pex_l5_clkreq_n_pgg0";
	nvidia,schmitt = <TEGRA_PIN_DISABLE>;
	nvidia,lpdr = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	};
	};
	};

	mc: memory-controller@2c00000 {
	compatible = "nvidia,tegra194-mc";
	reg = <0x02c00000 0x100000>,
	<0x02b80000 0x040000>,
	<0x01700000 0x100000>;
	status = "disabled";

	#address-cells = <2>;
	#size-cells = <2>;

	ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
	<0x02b80000 0x0 0x02b80000 0x0 0x040000>,
	<0x02c00000 0x0 0x02c00000 0x0 0x100000>;

	/*
	* Bit 39 of addresses passing through the memory
	* controller selects the XBAR format used when memory
	* is accessed. This is used to transparently access
	* memory in the XBAR format used by the discrete GPU
	* (bit 39 set) or Tegra (bit 39 clear).
	*
	* As a consequence, the operating system must ensure
	* that bit 39 is never used implicitly, for example
	* via an I/O virtual address mapping of an IOMMU. If
	* devices require access to the XBAR switch, their
	* drivers must set this bit explicitly.
	*
	* Limit the DMA range for memory clients to [38:0].
	*/
	dma-ranges = <0x0 0x0 0x0 0x80 0x0>;

	emc: external-memory-controller@2c60000 {
	compatible = "nvidia,tegra194-emc";
	reg = <0x0 0x02c60000 0x0 0x90000>,
	<0x0 0x01780000 0x0 0x80000>;
	clocks = <&bpmp TEGRA194_CLK_EMC>;
	clock-names = "emc";

	nvidia,bpmp = <&bpmp>;
	};
	};

	uarta: serial@3100000 {
	compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
	reg = <0x03100000 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_UARTA>;
	clock-names = "serial";
	resets = <&bpmp TEGRA194_RESET_UARTA>;
	reset-names = "serial";
	status = "disabled";
	};

	uartb: serial@3110000 {
	compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
	reg = <0x03110000 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_UARTB>;
	clock-names = "serial";
	resets = <&bpmp TEGRA194_RESET_UARTB>;
	reset-names = "serial";
	status = "disabled";
	};

	uartd: serial@3130000 {
	compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
	reg = <0x03130000 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_UARTD>;
	clock-names = "serial";
	resets = <&bpmp TEGRA194_RESET_UARTD>;
	reset-names = "serial";
	status = "disabled";
	};

	uarte: serial@3140000 {
	compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
	reg = <0x03140000 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_UARTE>;
	clock-names = "serial";
	resets = <&bpmp TEGRA194_RESET_UARTE>;
	reset-names = "serial";
	status = "disabled";
	};

	uartf: serial@3150000 {
	compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
	reg = <0x03150000 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_UARTF>;
	clock-names = "serial";
	resets = <&bpmp TEGRA194_RESET_UARTF>;
	reset-names = "serial";
	status = "disabled";
	};

	gen1_i2c: i2c@3160000 {
	compatible = "nvidia,tegra194-i2c";
	reg = <0x03160000 0x10000>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&bpmp TEGRA194_CLK_I2C1>;
	clock-names = "div-clk";
	resets = <&bpmp TEGRA194_RESET_I2C1>;
	reset-names = "i2c";
	status = "disabled";
	};

	uarth: serial@3170000 {
	compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
	reg = <0x03170000 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_UARTH>;
	clock-names = "serial";
	resets = <&bpmp TEGRA194_RESET_UARTH>;
	reset-names = "serial";
	status = "disabled";
	};

	cam_i2c: i2c@3180000 {
	compatible = "nvidia,tegra194-i2c";
	reg = <0x03180000 0x10000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&bpmp TEGRA194_CLK_I2C3>;
	clock-names = "div-clk";
	resets = <&bpmp TEGRA194_RESET_I2C3>;
	reset-names = "i2c";
	status = "disabled";
	};

	/* shares pads with dpaux1 */
	dp_aux_ch1_i2c: i2c@3190000 {
	compatible = "nvidia,tegra194-i2c";
	reg = <0x03190000 0x10000>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&bpmp TEGRA194_CLK_I2C4>;
	clock-names = "div-clk";
	resets = <&bpmp TEGRA194_RESET_I2C4>;
	reset-names = "i2c";
	status = "disabled";
	};

	/* shares pads with dpaux0 */
	dp_aux_ch0_i2c: i2c@31b0000 {
	compatible = "nvidia,tegra194-i2c";
	reg = <0x031b0000 0x10000>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&bpmp TEGRA194_CLK_I2C6>;
	clock-names = "div-clk";
	resets = <&bpmp TEGRA194_RESET_I2C6>;
	reset-names = "i2c";
	status = "disabled";
	};

	gen7_i2c: i2c@31c0000 {
	compatible = "nvidia,tegra194-i2c";
	reg = <0x031c0000 0x10000>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&bpmp TEGRA194_CLK_I2C7>;
	clock-names = "div-clk";
	resets = <&bpmp TEGRA194_RESET_I2C7>;
	reset-names = "i2c";
	status = "disabled";
	};

	gen9_i2c: i2c@31e0000 {
	compatible = "nvidia,tegra194-i2c";
	reg = <0x031e0000 0x10000>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&bpmp TEGRA194_CLK_I2C9>;
	clock-names = "div-clk";
	resets = <&bpmp TEGRA194_RESET_I2C9>;
	reset-names = "i2c";
	status = "disabled";
	};

	pwm1: pwm@3280000 {
	compatible = "nvidia,tegra194-pwm",
	"nvidia,tegra186-pwm";
	reg = <0x3280000 0x10000>;
	clocks = <&bpmp TEGRA194_CLK_PWM1>;
	clock-names = "pwm";
	resets = <&bpmp TEGRA194_RESET_PWM1>;
	reset-names = "pwm";
	status = "disabled";
	#pwm-cells = <2>;
	};

	pwm2: pwm@3290000 {
	compatible = "nvidia,tegra194-pwm",
	"nvidia,tegra186-pwm";
	reg = <0x3290000 0x10000>;
	clocks = <&bpmp TEGRA194_CLK_PWM2>;
	clock-names = "pwm";
	resets = <&bpmp TEGRA194_RESET_PWM2>;
	reset-names = "pwm";
	status = "disabled";
	#pwm-cells = <2>;
	};

	pwm3: pwm@32a0000 {
	compatible = "nvidia,tegra194-pwm",
	"nvidia,tegra186-pwm";
	reg = <0x32a0000 0x10000>;
	clocks = <&bpmp TEGRA194_CLK_PWM3>;
	clock-names = "pwm";
	resets = <&bpmp TEGRA194_RESET_PWM3>;
	reset-names = "pwm";
	status = "disabled";
	#pwm-cells = <2>;
	};

	pwm5: pwm@32c0000 {
	compatible = "nvidia,tegra194-pwm",
	"nvidia,tegra186-pwm";
	reg = <0x32c0000 0x10000>;
	clocks = <&bpmp TEGRA194_CLK_PWM5>;
	clock-names = "pwm";
	resets = <&bpmp TEGRA194_RESET_PWM5>;
	reset-names = "pwm";
	status = "disabled";
	#pwm-cells = <2>;
	};

	pwm6: pwm@32d0000 {
	compatible = "nvidia,tegra194-pwm",
	"nvidia,tegra186-pwm";
	reg = <0x32d0000 0x10000>;
	clocks = <&bpmp TEGRA194_CLK_PWM6>;
	clock-names = "pwm";
	resets = <&bpmp TEGRA194_RESET_PWM6>;
	reset-names = "pwm";
	status = "disabled";
	#pwm-cells = <2>;
	};

	pwm7: pwm@32e0000 {
	compatible = "nvidia,tegra194-pwm",
	"nvidia,tegra186-pwm";
	reg = <0x32e0000 0x10000>;
	clocks = <&bpmp TEGRA194_CLK_PWM7>;
	clock-names = "pwm";
	resets = <&bpmp TEGRA194_RESET_PWM7>;
	reset-names = "pwm";
	status = "disabled";
	#pwm-cells = <2>;
	};

	pwm8: pwm@32f0000 {
	compatible = "nvidia,tegra194-pwm",
	"nvidia,tegra186-pwm";
	reg = <0x32f0000 0x10000>;
	clocks = <&bpmp TEGRA194_CLK_PWM8>;
	clock-names = "pwm";
	resets = <&bpmp TEGRA194_RESET_PWM8>;
	reset-names = "pwm";
	status = "disabled";
	#pwm-cells = <2>;
	};

	sdmmc1: sdhci@3400000 {
	compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
	reg = <0x03400000 0x10000>;
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
	clock-names = "sdhci";
	resets = <&bpmp TEGRA194_RESET_SDMMC1>;
	reset-names = "sdhci";
	nvidia,pad-autocal-pull-up-offset-3v3-timeout =
	<0x07>;
	nvidia,pad-autocal-pull-down-offset-3v3-timeout =
	<0x07>;
	nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
	nvidia,pad-autocal-pull-down-offset-1v8-timeout =
	<0x07>;
	nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
	nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
	nvidia,default-tap = <0x9>;
	nvidia,default-trim = <0x5>;
	status = "disabled";
	};

	sdmmc3: sdhci@3440000 {
	compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
	reg = <0x03440000 0x10000>;
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
	clock-names = "sdhci";
	resets = <&bpmp TEGRA194_RESET_SDMMC3>;
	reset-names = "sdhci";
	nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
	nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
	nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
	nvidia,pad-autocal-pull-down-offset-3v3-timeout =
	<0x07>;
	nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
	nvidia,pad-autocal-pull-down-offset-1v8-timeout =
	<0x07>;
	nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
	nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
	nvidia,default-tap = <0x9>;
	nvidia,default-trim = <0x5>;
	status = "disabled";
	};

	sdmmc4: sdhci@3460000 {
	compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
	reg = <0x03460000 0x10000>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
	clock-names = "sdhci";
	assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
	<&bpmp TEGRA194_CLK_PLLC4>;
	assigned-clock-parents =
	<&bpmp TEGRA194_CLK_PLLC4>;
	resets = <&bpmp TEGRA194_RESET_SDMMC4>;
	reset-names = "sdhci";
	nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
	nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
	nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
	nvidia,pad-autocal-pull-down-offset-1v8-timeout =
	<0x0a>;
	nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
	nvidia,pad-autocal-pull-down-offset-3v3-timeout =
	<0x0a>;
	nvidia,default-tap = <0x8>;
	nvidia,default-trim = <0x14>;
	nvidia,dqs-trim = <40>;
	supports-cqe;
	status = "disabled";
	};

	hda@3510000 {
	compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
	reg = <0x3510000 0x10000>;
	interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_HDA>,
	<&bpmp TEGRA194_CLK_HDA2CODEC_2X>,
	<&bpmp TEGRA194_CLK_HDA2HDMICODEC>;
	clock-names = "hda", "hda2codec_2x", "hda2hdmi";
	resets = <&bpmp TEGRA194_RESET_HDA>,
	<&bpmp TEGRA194_RESET_HDA2CODEC_2X>,
	<&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
	reset-names = "hda", "hda2codec_2x", "hda2hdmi";
	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
	status = "disabled";
	};

	+ xusb_padctl: padctl@3520000 {
	+ compatible = "nvidia,tegra194-xusb-padctl";
	+ reg = <0x03520000 0x1000>,
	+ <0x03540000 0x1000>;
	+ reg-names = "padctl", "ao";
	+
	+ resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
	+ reset-names = "padctl";
	+
	+ status = "disabled";
	+
	+ pads {
	+ usb2 {
	+ clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
	+ clock-names = "trk";
	+
	+ lanes {
	+ usb2-0 {
	+ nvidia,function = "xusb";
	+ status = "disabled";
	+ #phy-cells = <0>;
	+ };
	+
	+ usb2-1 {
	+ nvidia,function = "xusb";
	+ status = "disabled";
	+ #phy-cells = <0>;
	+ };
	+
	+ usb2-2 {
	+ nvidia,function = "xusb";
	+ status = "disabled";
	+ #phy-cells = <0>;
	+ };
	+
	+ usb2-3 {
	+ nvidia,function = "xusb";
	+ status = "disabled";
	+ #phy-cells = <0>;
	+ };
	+ };
	+ };
	+
	+ usb3 {
	+ lanes {
	+ usb3-0 {
	+ nvidia,function = "xusb";
	+ status = "disabled";
	+ #phy-cells = <0>;
	+ };
	+
	+ usb3-1 {
	+ nvidia,function = "xusb";
	+ status = "disabled";
	+ #phy-cells = <0>;
	+ };
	+
	+ usb3-2 {
	+ nvidia,function = "xusb";
	+ status = "disabled";
	+ #phy-cells = <0>;
	+ };
	+
	+ usb3-3 {
	+ nvidia,function = "xusb";
	+ status = "disabled";
	+ #phy-cells = <0>;
	+ };
	+ };
	+ };
	+ };
	+
	+ ports {
	+ usb2-0 {
	+ status = "disabled";
	+ };
	+
	+ usb2-1 {
	+ status = "disabled";
	+ };
	+
	+ usb2-2 {
	+ status = "disabled";
	+ };
	+
	+ usb2-3 {
	+ status = "disabled";
	+ };
	+
	+ usb3-0 {
	+ status = "disabled";
	+ };
	+
	+ usb3-1 {
	+ status = "disabled";
	+ };
	+
	+ usb3-2 {
	+ status = "disabled";
	+ };
	+
	+ usb3-3 {
	+ status = "disabled";
	+ };
	+ };
	+ };
	+
	+ usb@3610000 {
	+ compatible = "nvidia,tegra194-xusb";
	+ reg = <0x03610000 0x40000>,
	+ <0x03600000 0x10000>;
	+ reg-names = "hcd", "fpci";
	+
	+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	+
	+ clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
	+ <&bpmp TEGRA194_CLK_XUSB_FALCON>,
	+ <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
	+ <&bpmp TEGRA194_CLK_XUSB_SS>,
	+ <&bpmp TEGRA194_CLK_CLK_M>,
	+ <&bpmp TEGRA194_CLK_XUSB_FS>,
	+ <&bpmp TEGRA194_CLK_UTMIPLL>,
	+ <&bpmp TEGRA194_CLK_CLK_M>,
	+ <&bpmp TEGRA194_CLK_PLLE>;
	+ clock-names = "xusb_host", "xusb_falcon_src",
	+ "xusb_ss", "xusb_ss_src", "xusb_hs_src",
	+ "xusb_fs_src", "pll_u_480m", "clk_m",
	+ "pll_e";
	+
	+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
	+ <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
	+ power-domain-names = "xusb_host", "xusb_ss";
	+
	+ nvidia,xusb-padctl = <&xusb_padctl>;
	+ status = "disabled";
	+ };
	+
	fuse@3820000 {
	compatible = "nvidia,tegra194-efuse";
	reg = <0x03820000 0x10000>;
	clocks = <&bpmp TEGRA194_CLK_FUSE>;
	clock-names = "fuse";
	};

	gic: interrupt-controller@3881000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x03881000 0x1000>,
	<0x03882000 0x2000>,
	<0x03884000 0x2000>,
	<0x03886000 0x2000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	interrupt-parent = <&gic>;
	};

	cec@3960000 {
	compatible = "nvidia,tegra194-cec";
	reg = <0x03960000 0x10000>;
	interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_CEC>;
	clock-names = "cec";
	status = "disabled";
	};

	hsp_top0: hsp@3c00000 {
	compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
	reg = <0x03c00000 0xa0000>;
	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "doorbell", "shared0", "shared1", "shared2",
	"shared3", "shared4", "shared5", "shared6",
	"shared7";
	#mbox-cells = <2>;
	};

	p2u_hsio_0: phy@3e10000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03e10000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_hsio_1: phy@3e20000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03e20000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_hsio_2: phy@3e30000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03e30000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_hsio_3: phy@3e40000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03e40000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_hsio_4: phy@3e50000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03e50000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_hsio_5: phy@3e60000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03e60000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_hsio_6: phy@3e70000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03e70000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_hsio_7: phy@3e80000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03e80000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_hsio_8: phy@3e90000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03e90000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_hsio_9: phy@3ea0000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03ea0000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_nvhs_0: phy@3eb0000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03eb0000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_nvhs_1: phy@3ec0000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03ec0000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_nvhs_2: phy@3ed0000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03ed0000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_nvhs_3: phy@3ee0000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03ee0000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_nvhs_4: phy@3ef0000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03ef0000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_nvhs_5: phy@3f00000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03f00000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_nvhs_6: phy@3f10000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03f10000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_nvhs_7: phy@3f20000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03f20000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_hsio_10: phy@3f30000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03f30000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	p2u_hsio_11: phy@3f40000 {
	compatible = "nvidia,tegra194-p2u";
	reg = <0x03f40000 0x10000>;
	reg-names = "ctl";

	#phy-cells = <0>;
	};

	hsp_aon: hsp@c150000 {
	compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
	reg = <0x0c150000 0xa0000>;
	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	/*
	* Shared interrupt 0 is routed only to AON/SPE, so
	* we only have 4 shared interrupts for the CCPLEX.
	*/
	interrupt-names = "shared1", "shared2", "shared3", "shared4";
	#mbox-cells = <2>;
	};

	gen2_i2c: i2c@c240000 {
	compatible = "nvidia,tegra194-i2c";
	reg = <0x0c240000 0x10000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&bpmp TEGRA194_CLK_I2C2>;
	clock-names = "div-clk";
	resets = <&bpmp TEGRA194_RESET_I2C2>;
	reset-names = "i2c";
	status = "disabled";
	};

	gen8_i2c: i2c@c250000 {
	compatible = "nvidia,tegra194-i2c";
	reg = <0x0c250000 0x10000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&bpmp TEGRA194_CLK_I2C8>;
	clock-names = "div-clk";
	resets = <&bpmp TEGRA194_RESET_I2C8>;
	reset-names = "i2c";
	status = "disabled";
	};

	uartc: serial@c280000 {
	compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
	reg = <0x0c280000 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_UARTC>;
	clock-names = "serial";
	resets = <&bpmp TEGRA194_RESET_UARTC>;
	reset-names = "serial";
	status = "disabled";
	};

	uartg: serial@c290000 {
	compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
	reg = <0x0c290000 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_UARTG>;
	clock-names = "serial";
	resets = <&bpmp TEGRA194_RESET_UARTG>;
	reset-names = "serial";
	status = "disabled";
	};

	rtc: rtc@c2a0000 {
	compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
	reg = <0x0c2a0000 0x10000>;
	interrupt-parent = <&pmc>;
	interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
	clock-names = "rtc";
	status = "disabled";
	};

	gpio_aon: gpio@c2f0000 {
	compatible = "nvidia,tegra194-gpio-aon";
	reg-names = "security", "gpio";
	reg = <0xc2f0000 0x1000>,
	<0xc2f1000 0x1000>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	pwm4: pwm@c340000 {
	compatible = "nvidia,tegra194-pwm",
	"nvidia,tegra186-pwm";
	reg = <0xc340000 0x10000>;
	clocks = <&bpmp TEGRA194_CLK_PWM4>;
	clock-names = "pwm";
	resets = <&bpmp TEGRA194_RESET_PWM4>;
	reset-names = "pwm";
	status = "disabled";
	#pwm-cells = <2>;
	};

	pmc: pmc@c360000 {
	compatible = "nvidia,tegra194-pmc";
	reg = <0x0c360000 0x10000>,
	<0x0c370000 0x10000>,
	<0x0c380000 0x10000>,
	<0x0c390000 0x10000>,
	<0x0c3a0000 0x10000>;
	reg-names = "pmc", "wake", "aotag", "scratch", "misc";

	#interrupt-cells = <2>;
	interrupt-controller;
	};

	host1x@13e00000 {
	compatible = "nvidia,tegra194-host1x", "simple-bus";
	reg = <0x13e00000 0x10000>,
	<0x13e10000 0x10000>;
	reg-names = "hypervisor", "vm";
	interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_HOST1X>;
	clock-names = "host1x";
	resets = <&bpmp TEGRA194_RESET_HOST1X>;
	reset-names = "host1x";

	#address-cells = <1>;
	#size-cells = <1>;

	ranges = <0x15000000 0x15000000 0x01000000>;

	display-hub@15200000 {
	compatible = "nvidia,tegra194-display", "simple-bus";
	reg = <0x15200000 0x00040000>;
	resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
	<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
	<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
	<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
	<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
	<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
	<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
	reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
	"wgrp3", "wgrp4", "wgrp5";
	clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
	<&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
	clock-names = "disp", "hub";
	status = "disabled";

	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;

	#address-cells = <1>;
	#size-cells = <1>;

	ranges = <0x15200000 0x15200000 0x40000>;

	display@15200000 {
	compatible = "nvidia,tegra194-dc";
	reg = <0x15200000 0x10000>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
	clock-names = "dc";
	resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
	reset-names = "dc";

	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;

	nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
	nvidia,head = <0>;
	};

	display@15210000 {
	compatible = "nvidia,tegra194-dc";
	reg = <0x15210000 0x10000>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
	clock-names = "dc";
	resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
	reset-names = "dc";

	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;

	nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
	nvidia,head = <1>;
	};

	display@15220000 {
	compatible = "nvidia,tegra194-dc";
	reg = <0x15220000 0x10000>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
	clock-names = "dc";
	resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
	reset-names = "dc";

	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;

	nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
	nvidia,head = <2>;
	};

	display@15230000 {
	compatible = "nvidia,tegra194-dc";
	reg = <0x15230000 0x10000>;
	interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
	clock-names = "dc";
	resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
	reset-names = "dc";

	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;

	nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
	nvidia,head = <3>;
	};
	};

	vic@15340000 {
	compatible = "nvidia,tegra194-vic";
	reg = <0x15340000 0x00040000>;
	interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_VIC>;
	clock-names = "vic";
	resets = <&bpmp TEGRA194_RESET_VIC>;
	reset-names = "vic";

	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
	};

	dpaux0: dpaux@155c0000 {
	compatible = "nvidia,tegra194-dpaux";
	reg = <0x155c0000 0x10000>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_DPAUX>,
	<&bpmp TEGRA194_CLK_PLLDP>;
	clock-names = "dpaux", "parent";
	resets = <&bpmp TEGRA194_RESET_DPAUX>;
	reset-names = "dpaux";
	status = "disabled";

	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;

	state_dpaux0_aux: pinmux-aux {
	groups = "dpaux-io";
	function = "aux";
	};

	state_dpaux0_i2c: pinmux-i2c {
	groups = "dpaux-io";
	function = "i2c";
	};

	state_dpaux0_off: pinmux-off {
	groups = "dpaux-io";
	function = "off";
	};

	i2c-bus {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	dpaux1: dpaux@155d0000 {
	compatible = "nvidia,tegra194-dpaux";
	reg = <0x155d0000 0x10000>;
	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
	<&bpmp TEGRA194_CLK_PLLDP>;
	clock-names = "dpaux", "parent";
	resets = <&bpmp TEGRA194_RESET_DPAUX1>;
	reset-names = "dpaux";
	status = "disabled";

	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;

	state_dpaux1_aux: pinmux-aux {
	groups = "dpaux-io";
	function = "aux";
	};

	state_dpaux1_i2c: pinmux-i2c {
	groups = "dpaux-io";
	function = "i2c";
	};

	state_dpaux1_off: pinmux-off {
	groups = "dpaux-io";
	function = "off";
	};

	i2c-bus {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	dpaux2: dpaux@155e0000 {
	compatible = "nvidia,tegra194-dpaux";
	reg = <0x155e0000 0x10000>;
	interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
	<&bpmp TEGRA194_CLK_PLLDP>;
	clock-names = "dpaux", "parent";
	resets = <&bpmp TEGRA194_RESET_DPAUX2>;
	reset-names = "dpaux";
	status = "disabled";

	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;

	state_dpaux2_aux: pinmux-aux {
	groups = "dpaux-io";
	function = "aux";
	};

	state_dpaux2_i2c: pinmux-i2c {
	groups = "dpaux-io";
	function = "i2c";
	};

	state_dpaux2_off: pinmux-off {
	groups = "dpaux-io";
	function = "off";
	};

	i2c-bus {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	dpaux3: dpaux@155f0000 {
	compatible = "nvidia,tegra194-dpaux";
	reg = <0x155f0000 0x10000>;
	interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
	<&bpmp TEGRA194_CLK_PLLDP>;
	clock-names = "dpaux", "parent";
	resets = <&bpmp TEGRA194_RESET_DPAUX3>;
	reset-names = "dpaux";
	status = "disabled";

	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;

	state_dpaux3_aux: pinmux-aux {
	groups = "dpaux-io";
	function = "aux";
	};

	state_dpaux3_i2c: pinmux-i2c {
	groups = "dpaux-io";
	function = "i2c";
	};

	state_dpaux3_off: pinmux-off {
	groups = "dpaux-io";
	function = "off";
	};

	i2c-bus {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	sor0: sor@15b00000 {
	compatible = "nvidia,tegra194-sor";
	reg = <0x15b00000 0x40000>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
	<&bpmp TEGRA194_CLK_SOR0_OUT>,
	<&bpmp TEGRA194_CLK_PLLD>,
	<&bpmp TEGRA194_CLK_PLLDP>,
	<&bpmp TEGRA194_CLK_SOR_SAFE>,
	<&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
	clock-names = "sor", "out", "parent", "dp", "safe",
	"pad";
	resets = <&bpmp TEGRA194_RESET_SOR0>;
	reset-names = "sor";
	pinctrl-0 = <&state_dpaux0_aux>;
	pinctrl-1 = <&state_dpaux0_i2c>;
	pinctrl-2 = <&state_dpaux0_off>;
	pinctrl-names = "aux", "i2c", "off";
	status = "disabled";

	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
	nvidia,interface = <0>;
	};

	sor1: sor@15b40000 {
	compatible = "nvidia,tegra194-sor";
	reg = <0x15b40000 0x40000>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
	<&bpmp TEGRA194_CLK_SOR1_OUT>,
	<&bpmp TEGRA194_CLK_PLLD2>,
	<&bpmp TEGRA194_CLK_PLLDP>,
	<&bpmp TEGRA194_CLK_SOR_SAFE>,
	<&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
	clock-names = "sor", "out", "parent", "dp", "safe",
	"pad";
	resets = <&bpmp TEGRA194_RESET_SOR1>;
	reset-names = "sor";
	pinctrl-0 = <&state_dpaux1_aux>;
	pinctrl-1 = <&state_dpaux1_i2c>;
	pinctrl-2 = <&state_dpaux1_off>;
	pinctrl-names = "aux", "i2c", "off";
	status = "disabled";

	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
	nvidia,interface = <1>;
	};

	sor2: sor@15b80000 {
	compatible = "nvidia,tegra194-sor";
	reg = <0x15b80000 0x40000>;
	interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
	<&bpmp TEGRA194_CLK_SOR2_OUT>,
	<&bpmp TEGRA194_CLK_PLLD3>,
	<&bpmp TEGRA194_CLK_PLLDP>,
	<&bpmp TEGRA194_CLK_SOR_SAFE>,
	<&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
	clock-names = "sor", "out", "parent", "dp", "safe",
	"pad";
	resets = <&bpmp TEGRA194_RESET_SOR2>;
	reset-names = "sor";
	pinctrl-0 = <&state_dpaux2_aux>;
	pinctrl-1 = <&state_dpaux2_i2c>;
	pinctrl-2 = <&state_dpaux2_off>;
	pinctrl-names = "aux", "i2c", "off";
	status = "disabled";

	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
	nvidia,interface = <2>;
	};

	sor3: sor@15bc0000 {
	compatible = "nvidia,tegra194-sor";
	reg = <0x15bc0000 0x40000>;
	interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
	<&bpmp TEGRA194_CLK_SOR3_OUT>,
	<&bpmp TEGRA194_CLK_PLLD4>,
	<&bpmp TEGRA194_CLK_PLLDP>,
	<&bpmp TEGRA194_CLK_SOR_SAFE>,
	<&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
	clock-names = "sor", "out", "parent", "dp", "safe",
	"pad";
	resets = <&bpmp TEGRA194_RESET_SOR3>;
	reset-names = "sor";
	pinctrl-0 = <&state_dpaux3_aux>;
	pinctrl-1 = <&state_dpaux3_i2c>;
	pinctrl-2 = <&state_dpaux3_off>;
	pinctrl-names = "aux", "i2c", "off";
	status = "disabled";

	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
	nvidia,interface = <3>;
	};
	};
	};

	pcie@14100000 {
	- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
	+ compatible = "nvidia,tegra194-pcie";
	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
	reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */
	0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */
	0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
	0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
	reg-names = "appl", "config", "atu_dma", "dbi";

	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	num-lanes = <1>;
	num-viewport = <8>;
	linux,pci-domain = <1>;

	clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
	clock-names = "core";

	resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
	<&bpmp TEGRA194_RESET_PEX0_CORE_1>;
	reset-names = "apb", "core";

	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
	interrupt-names = "intr", "msi";

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;

	nvidia,bpmp = <&bpmp 1>;

	nvidia,aspm-cmrt-us = <60>;
	nvidia,aspm-pwr-on-t-us = <20>;
	nvidia,aspm-l0s-entrance-latency-us = <3>;

	bus-range = <0x0 0xff>;
	ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */
	0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */
	0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
	};

	pcie@14120000 {
	- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
	+ compatible = "nvidia,tegra194-pcie";
	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
	reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */
	0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */
	0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
	0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
	reg-names = "appl", "config", "atu_dma", "dbi";

	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	num-lanes = <1>;
	num-viewport = <8>;
	linux,pci-domain = <2>;

	clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
	clock-names = "core";

	resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
	<&bpmp TEGRA194_RESET_PEX0_CORE_2>;
	reset-names = "apb", "core";

	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
	interrupt-names = "intr", "msi";

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;

	nvidia,bpmp = <&bpmp 2>;

	nvidia,aspm-cmrt-us = <60>;
	nvidia,aspm-pwr-on-t-us = <20>;
	nvidia,aspm-l0s-entrance-latency-us = <3>;

	bus-range = <0x0 0xff>;
	ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */
	0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */
	0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
	};

	pcie@14140000 {
	- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
	+ compatible = "nvidia,tegra194-pcie";
	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
	reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */
	0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */
	0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
	0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
	reg-names = "appl", "config", "atu_dma", "dbi";

	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	num-lanes = <1>;
	num-viewport = <8>;
	linux,pci-domain = <3>;

	clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
	clock-names = "core";

	resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
	<&bpmp TEGRA194_RESET_PEX0_CORE_3>;
	reset-names = "apb", "core";

	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
	interrupt-names = "intr", "msi";

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

	nvidia,bpmp = <&bpmp 3>;

	nvidia,aspm-cmrt-us = <60>;
	nvidia,aspm-pwr-on-t-us = <20>;
	nvidia,aspm-l0s-entrance-latency-us = <3>;

	bus-range = <0x0 0xff>;
	ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */
	0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */
	0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
	};

	pcie@14160000 {
	- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
	+ compatible = "nvidia,tegra194-pcie";
	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
	reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
	0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */
	0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
	0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
	reg-names = "appl", "config", "atu_dma", "dbi";

	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	num-lanes = <4>;
	num-viewport = <8>;
	linux,pci-domain = <4>;

	clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
	clock-names = "core";

	resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
	<&bpmp TEGRA194_RESET_PEX0_CORE_4>;
	reset-names = "apb", "core";

	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
	interrupt-names = "intr", "msi";

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

	nvidia,bpmp = <&bpmp 4>;

	nvidia,aspm-cmrt-us = <60>;
	nvidia,aspm-pwr-on-t-us = <20>;
	nvidia,aspm-l0s-entrance-latency-us = <3>;

	bus-range = <0x0 0xff>;
	ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */
	0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
	0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
	};

	pcie@14180000 {
	- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
	+ compatible = "nvidia,tegra194-pcie";
	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
	reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
	0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
	0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
	0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
	reg-names = "appl", "config", "atu_dma", "dbi";

	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	num-lanes = <8>;
	num-viewport = <8>;
	linux,pci-domain = <0>;

	clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
	clock-names = "core";

	resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
	<&bpmp TEGRA194_RESET_PEX0_CORE_0>;
	reset-names = "apb", "core";

	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
	interrupt-names = "intr", "msi";

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;

	nvidia,bpmp = <&bpmp 0>;

	nvidia,aspm-cmrt-us = <60>;
	nvidia,aspm-pwr-on-t-us = <20>;
	nvidia,aspm-l0s-entrance-latency-us = <3>;

	bus-range = <0x0 0xff>;
	ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
	0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
	0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
	};

	pcie@141a0000 {
	- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
	+ compatible = "nvidia,tegra194-pcie";
	power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
	reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
	0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */
	0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
	0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
	reg-names = "appl", "config", "atu_dma", "dbi";

	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	num-lanes = <8>;
	num-viewport = <8>;
	linux,pci-domain = <5>;

	pinctrl-names = "default";
	pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;

	clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
	<&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
	clock-names = "core", "core_m";

	resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
	<&bpmp TEGRA194_RESET_PEX1_CORE_5>;
	reset-names = "apb", "core";

	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
	interrupt-names = "intr", "msi";

	nvidia,bpmp = <&bpmp 5>;

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;

	nvidia,aspm-cmrt-us = <60>;
	nvidia,aspm-pwr-on-t-us = <20>;
	nvidia,aspm-l0s-entrance-latency-us = <3>;

	bus-range = <0x0 0xff>;
	ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */
	0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
	0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
	};

	+ pcie_ep@14160000 {
	+ compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
	+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
	+ reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
	+ 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
	+ 0x00 0x36080000 0x0 0x00040000 /* DBI reg space (256K) */
	+ 0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
	+ reg-names = "appl", "atu_dma", "dbi", "addr_space";
	+
	+ status = "disabled";
	+
	+ num-lanes = <4>;
	+ num-ib-windows = <2>;
	+ num-ob-windows = <8>;
	+
	+ clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
	+ clock-names = "core";
	+
	+ resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
	+ <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
	+ reset-names = "apb", "core";
	+
	+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
	+ interrupt-names = "intr";
	+
	+ nvidia,bpmp = <&bpmp 4>;
	+
	+ nvidia,aspm-cmrt-us = <60>;
	+ nvidia,aspm-pwr-on-t-us = <20>;
	+ nvidia,aspm-l0s-entrance-latency-us = <3>;
	+ };
	+
	+ pcie_ep@14180000 {
	+ compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
	+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
	+ reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
	+ 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
	+ 0x00 0x38080000 0x0 0x00040000 /* DBI reg space (256K) */
	+ 0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
	+ reg-names = "appl", "atu_dma", "dbi", "addr_space";
	+
	+ status = "disabled";
	+
	+ num-lanes = <8>;
	+ num-ib-windows = <2>;
	+ num-ob-windows = <8>;
	+
	+ clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
	+ clock-names = "core";
	+
	+ resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
	+ <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
	+ reset-names = "apb", "core";
	+
	+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
	+ interrupt-names = "intr";
	+
	+ nvidia,bpmp = <&bpmp 0>;
	+
	+ nvidia,aspm-cmrt-us = <60>;
	+ nvidia,aspm-pwr-on-t-us = <20>;
	+ nvidia,aspm-l0s-entrance-latency-us = <3>;
	+ };
	+
	+ pcie_ep@141a0000 {
	+ compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
	+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
	+ reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
	+ 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
	+ 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
	+ 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
	+ reg-names = "appl", "atu_dma", "dbi", "addr_space";
	+
	+ status = "disabled";
	+
	+ num-lanes = <8>;
	+ num-ib-windows = <2>;
	+ num-ob-windows = <8>;
	+
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&clkreq_c5_bi_dir_state>;
	+
	+ clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
	+ clock-names = "core";
	+
	+ resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
	+ <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
	+ reset-names = "apb", "core";
	+
	+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
	+ interrupt-names = "intr";
	+
	+ nvidia,bpmp = <&bpmp 5>;
	+
	+ nvidia,aspm-cmrt-us = <60>;
	+ nvidia,aspm-pwr-on-t-us = <20>;
	+ nvidia,aspm-l0s-entrance-latency-us = <3>;
	+ };
	+
	sysram@40000000 {
	compatible = "nvidia,tegra194-sysram", "mmio-sram";
	reg = <0x0 0x40000000 0x0 0x50000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x40000000 0x50000>;

	cpu_bpmp_tx: shmem@4e000 {
	compatible = "nvidia,tegra194-bpmp-shmem";
	reg = <0x4e000 0x1000>;
	label = "cpu-bpmp-tx";
	pool;
	};

	cpu_bpmp_rx: shmem@4f000 {
	compatible = "nvidia,tegra194-bpmp-shmem";
	reg = <0x4f000 0x1000>;
	label = "cpu-bpmp-rx";
	pool;
	};
	};

	bpmp: bpmp {
	compatible = "nvidia,tegra186-bpmp";
	mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
	TEGRA_HSP_DB_MASTER_BPMP>;
	shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;

	bpmp_i2c: i2c {
	compatible = "nvidia,tegra186-bpmp-i2c";
	nvidia,bpmp-bus-id = <5>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	bpmp_thermal: thermal {
	compatible = "nvidia,tegra186-bpmp-thermal";
	#thermal-sensor-cells = <1>;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0_0: cpu@0 {
	compatible = "nvidia,tegra194-carmel";
	device_type = "cpu";
	reg = <0x000>;
	enable-method = "psci";
	i-cache-size = <131072>;
	i-cache-line-size = <64>;
	i-cache-sets = <512>;
	d-cache-size = <65536>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&l2c_0>;
	};

	cpu0_1: cpu@1 {
	compatible = "nvidia,tegra194-carmel";
	device_type = "cpu";
	reg = <0x001>;
	enable-method = "psci";
	i-cache-size = <131072>;
	i-cache-line-size = <64>;
	i-cache-sets = <512>;
	d-cache-size = <65536>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&l2c_0>;
	};

	cpu1_0: cpu@100 {
	compatible = "nvidia,tegra194-carmel";
	device_type = "cpu";
	reg = <0x100>;
	enable-method = "psci";
	i-cache-size = <131072>;
	i-cache-line-size = <64>;
	i-cache-sets = <512>;
	d-cache-size = <65536>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&l2c_1>;
	};

	cpu1_1: cpu@101 {
	compatible = "nvidia,tegra194-carmel";
	device_type = "cpu";
	reg = <0x101>;
	enable-method = "psci";
	i-cache-size = <131072>;
	i-cache-line-size = <64>;
	i-cache-sets = <512>;
	d-cache-size = <65536>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&l2c_1>;
	};

	cpu2_0: cpu@200 {
	compatible = "nvidia,tegra194-carmel";
	device_type = "cpu";
	reg = <0x200>;
	enable-method = "psci";
	i-cache-size = <131072>;
	i-cache-line-size = <64>;
	i-cache-sets = <512>;
	d-cache-size = <65536>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&l2c_2>;
	};

	cpu2_1: cpu@201 {
	compatible = "nvidia,tegra194-carmel";
	device_type = "cpu";
	reg = <0x201>;
	enable-method = "psci";
	i-cache-size = <131072>;
	i-cache-line-size = <64>;
	i-cache-sets = <512>;
	d-cache-size = <65536>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&l2c_2>;
	};

	cpu3_0: cpu@300 {
	compatible = "nvidia,tegra194-carmel";
	device_type = "cpu";
	reg = <0x300>;
	enable-method = "psci";
	i-cache-size = <131072>;
	i-cache-line-size = <64>;
	i-cache-sets = <512>;
	d-cache-size = <65536>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&l2c_3>;
	};

	cpu3_1: cpu@301 {
	compatible = "nvidia,tegra194-carmel";
	device_type = "cpu";
	reg = <0x301>;
	enable-method = "psci";
	i-cache-size = <131072>;
	i-cache-line-size = <64>;
	i-cache-sets = <512>;
	d-cache-size = <65536>;
	d-cache-line-size = <64>;
	d-cache-sets = <256>;
	next-level-cache = <&l2c_3>;
	};

	cpu-map {
	cluster0 {
	core0 {
	cpu = <&cpu0_0>;
	};

	core1 {
	cpu = <&cpu0_1>;
	};
	};

	cluster1 {
	core0 {
	cpu = <&cpu1_0>;
	};

	core1 {
	cpu = <&cpu1_1>;
	};
	};

	cluster2 {
	core0 {
	cpu = <&cpu2_0>;
	};

	core1 {
	cpu = <&cpu2_1>;
	};
	};

	cluster3 {
	core0 {
	cpu = <&cpu3_0>;
	};

	core1 {
	cpu = <&cpu3_1>;
	};
	};
	};

	l2c_0: l2-cache0 {
	cache-size = <2097152>;
	cache-line-size = <64>;
	cache-sets = <2048>;
	next-level-cache = <&l3c>;
	};

	l2c_1: l2-cache1 {
	cache-size = <2097152>;
	cache-line-size = <64>;
	cache-sets = <2048>;
	next-level-cache = <&l3c>;
	};

	l2c_2: l2-cache2 {
	cache-size = <2097152>;
	cache-line-size = <64>;
	cache-sets = <2048>;
	next-level-cache = <&l3c>;
	};

	l2c_3: l2-cache3 {
	cache-size = <2097152>;
	cache-line-size = <64>;
	cache-sets = <2048>;
	next-level-cache = <&l3c>;
	};

	l3c: l3-cache {
	cache-size = <4194304>;
	cache-line-size = <64>;
	cache-sets = <4096>;
	};
	};

	psci {
	compatible = "arm,psci-1.0";
	status = "okay";
	method = "smc";
	};

	tcu: tcu {
	compatible = "nvidia,tegra194-tcu";
	mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
	<&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
	mbox-names = "rx", "tx";
	};

	thermal-zones {
	cpu {
	thermal-sensors = <&{/bpmp/thermal}
	TEGRA194_BPMP_THERMAL_ZONE_CPU>;
	status = "disabled";
	};

	gpu {
	thermal-sensors = <&{/bpmp/thermal}
	TEGRA194_BPMP_THERMAL_ZONE_GPU>;
	status = "disabled";
	};

	aux {
	thermal-sensors = <&{/bpmp/thermal}
	TEGRA194_BPMP_THERMAL_ZONE_AUX>;
	status = "disabled";
	};

	pllx {
	thermal-sensors = <&{/bpmp/thermal}
	TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
	status = "disabled";
	};

	ao {
	thermal-sensors = <&{/bpmp/thermal}
	TEGRA194_BPMP_THERMAL_ZONE_AO>;
	status = "disabled";
	};

	tj {
	thermal-sensors = <&{/bpmp/thermal}
	TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
	status = "disabled";
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	interrupt-parent = <&gic>;
	always-on;
	};
	};
	diff --git a/sys/gnu/dts/arm64/nvidia/tegra210-p2180.dtsi b/sys/gnu/dts/arm64/nvidia/tegra210-p2180.dtsi
	index cb58f79deb48..f87d2437d11c 100644
	--- a/sys/gnu/dts/arm64/nvidia/tegra210-p2180.dtsi
	+++ b/sys/gnu/dts/arm64/nvidia/tegra210-p2180.dtsi
	@@ -1,355 +1,358 @@
	// SPDX-License-Identifier: GPL-2.0
	#include <dt-bindings/mfd/max77620.h>

	#include "tegra210.dtsi"

	/ {
	model = "NVIDIA Jetson TX1";
	compatible = "nvidia,p2180", "nvidia,tegra210";

	aliases {
	rtc0 = "/i2c@7000d000/pmic@3c";
	rtc1 = "/rtc@7000e000";
	serial0 = &uarta;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory {
	device_type = "memory";
	reg = <0x0 0x80000000 0x1 0x0>;
	};

	gpu@57000000 {
	vdd-supply = <&vdd_gpu>;
	};

	/* debug port */
	serial@70006000 {
	status = "okay";
	};

	i2c@7000d000 {
	status = "okay";
	clock-frequency = <400000>;

	pmic: pmic@3c {
	compatible = "maxim,max77620";
	reg = <0x3c>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;

	#interrupt-cells = <2>;
	interrupt-controller;

	#gpio-cells = <2>;
	gpio-controller;

	pinctrl-names = "default";
	pinctrl-0 = <&max77620_default>;

	max77620_default: pinmux {
	gpio0 {
	pins = "gpio0";
	function = "gpio";
	};

	gpio1 {
	pins = "gpio1";
	function = "fps-out";
	drive-push-pull = <1>;
	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
	maxim,active-fps-power-up-slot = <7>;
	maxim,active-fps-power-down-slot = <0>;
	};

	gpio2_3 {
	pins = "gpio2", "gpio3";
	function = "fps-out";
	drive-open-drain = <1>;
	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
	};

	gpio4 {
	pins = "gpio4";
	function = "32k-out1";
	};

	gpio5_6_7 {
	pins = "gpio5", "gpio6", "gpio7";
	function = "gpio";
	drive-push-pull = <1>;
	};
	};

	fps {
	fps0 {
	maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
	maxim,suspend-fps-time-period-us = <1280>;
	};

	fps1 {
	maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
	maxim,suspend-fps-time-period-us = <1280>;
	};

	fps2 {
	maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
	};
	};

	regulators {
	in-ldo0-1-supply = <&vdd_pre>;
	in-ldo7-8-supply = <&vdd_pre>;
	in-sd3-supply = <&vdd_5v0_sys>;

	vdd_soc: sd0 {
	regulator-name = "VDD_SOC";
	regulator-min-microvolt = <600000>;
	regulator-max-microvolt = <1400000>;
	regulator-always-on;
	regulator-boot-on;

	regulator-enable-ramp-delay = <146>;
	regulator-ramp-delay = <27500>;

	maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
	};

	vdd_ddr: sd1 {
	regulator-name = "VDD_DDR_1V1_PMIC";
	regulator-always-on;
	regulator-boot-on;

	regulator-enable-ramp-delay = <130>;
	regulator-ramp-delay = <27500>;

	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
	};

	vdd_pre: sd2 {
	regulator-name = "VDD_PRE_REG_1V35";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;

	regulator-enable-ramp-delay = <176>;
	regulator-ramp-delay = <27500>;

	maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
	};

	vdd_1v8: sd3 {
	regulator-name = "VDD_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;

	regulator-enable-ramp-delay = <242>;
	regulator-ramp-delay = <27500>;

	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
	};

	vdd_sys_1v2: ldo0 {
	regulator-name = "AVDD_SYS_1V2";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-always-on;
	regulator-boot-on;

	regulator-enable-ramp-delay = <26>;
	regulator-ramp-delay = <100000>;

	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
	};

	vdd_pex_1v05: ldo1 {
	regulator-name = "VDD_PEX_1V05";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;

	regulator-enable-ramp-delay = <22>;
	regulator-ramp-delay = <100000>;

	maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
	};

	vddio_sdmmc: ldo2 {
	regulator-name = "VDDIO_SDMMC";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;

	regulator-enable-ramp-delay = <62>;
	regulator-ramp-delay = <100000>;

	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
	};

	vdd_cam_hv: ldo3 {
	regulator-name = "VDD_CAM_HV";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;

	regulator-enable-ramp-delay = <50>;
	regulator-ramp-delay = <100000>;

	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
	};

	vdd_rtc: ldo4 {
	regulator-name = "VDD_RTC";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <850000>;
	regulator-always-on;
	regulator-boot-on;

	regulator-enable-ramp-delay = <22>;
	regulator-ramp-delay = <100000>;

	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
	};

	vdd_ts_hv: ldo5 {
	regulator-name = "VDD_TS_HV";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	regulator-enable-ramp-delay = <62>;
	regulator-ramp-delay = <100000>;

	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
	};

	vdd_ts: ldo6 {
	regulator-name = "VDD_TS_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	regulator-enable-ramp-delay = <36>;
	regulator-ramp-delay = <100000>;

	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
	maxim,active-fps-power-up-slot = <7>;
	maxim,active-fps-power-down-slot = <0>;
	};

	avdd_1v05_pll: ldo7 {
	regulator-name = "AVDD_1V05_PLL";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	regulator-always-on;
	regulator-boot-on;

	regulator-enable-ramp-delay = <24>;
	regulator-ramp-delay = <100000>;

	maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
	};

	avdd_1v05: ldo8 {
	regulator-name = "AVDD_SATA_HDMI_DP_1V05";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;

	regulator-enable-ramp-delay = <22>;
	regulator-ramp-delay = <100000>;

	maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
	};
	};
	};
	};

	i2c@7000c500 {
	+ status = "okay";
	+
	/* module ID EEPROM */
	eeprom@50 {
	compatible = "atmel,24c02";
	reg = <0x50>;

	+ vcc-supply = <&vdd_1v8>;
	address-bits = <8>;
	page-size = <8>;
	size = <256>;
	read-only;
	};
	};

	pmc@7000e400 {
	nvidia,invert-interrupt;
	nvidia,suspend-mode = <0>;
	nvidia,cpu-pwr-good-time = <0>;
	nvidia,cpu-pwr-off-time = <0>;
	nvidia,core-pwr-good-time = <4587 3876>;
	nvidia,core-pwr-off-time = <39065>;
	nvidia,core-power-req-active-high;
	nvidia,sys-clock-req-active-high;
	};

	/* eMMC */
	sdhci@700b0600 {
	status = "okay";
	bus-width = <8>;
	non-removable;
	vqmmc-supply = <&vdd_1v8>;
	};

	clocks {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	clk32k_in: clock@0 {
	compatible = "fixed-clock";
	reg = <0>;
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	};

	cpus {
	cpu@0 {
	enable-method = "psci";
	};

	cpu@1 {
	enable-method = "psci";
	};

	cpu@2 {
	enable-method = "psci";
	};

	cpu@3 {
	enable-method = "psci";
	};

	idle-states {
	cpu-sleep {
	status = "okay";
	};
	};
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	regulators {
	vdd_gpu: regulator@100 {
	compatible = "pwm-regulator";
	reg = <100>;
	pwms = <&pwm 1 4880>;
	regulator-name = "VDD_GPU";
	regulator-min-microvolt = <710000>;
	regulator-max-microvolt = <1320000>;
	enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
	regulator-ramp-delay = <80>;
	regulator-enable-ramp-delay = <2000>;
	regulator-settling-time-us = <160>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/nvidia/tegra210-p2371-2180.dts b/sys/gnu/dts/arm64/nvidia/tegra210-p2371-2180.dts
	index a3cafe39ba4c..ea0e1efa6973 100644
	--- a/sys/gnu/dts/arm64/nvidia/tegra210-p2371-2180.dts
	+++ b/sys/gnu/dts/arm64/nvidia/tegra210-p2371-2180.dts
	@@ -1,127 +1,129 @@
	// SPDX-License-Identifier: GPL-2.0
	/dts-v1/;

	#include "tegra210-p2180.dtsi"
	#include "tegra210-p2597.dtsi"

	/ {
	model = "NVIDIA Jetson TX1 Developer Kit";
	compatible = "nvidia,p2371-2180", "nvidia,tegra210";

	pcie@1003000 {
	status = "okay";

	avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
	hvddio-pex-supply = <&vdd_1v8>;
	dvddio-pex-supply = <&vdd_pex_1v05>;
	dvdd-pex-pll-supply = <&vdd_pex_1v05>;
	hvdd-pex-pll-e-supply = <&vdd_1v8>;
	vddio-pex-ctl-supply = <&vdd_1v8>;

	pci@1,0 {
	phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
	phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
	status = "okay";
	};

	pci@2,0 {
	phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
	phy-names = "pcie-0";
	status = "okay";
	};
	};

	host1x@50000000 {
	dsi@54300000 {
	status = "okay";

	avdd-dsi-csi-supply = <&vdd_dsi_csi>;

	panel@0 {
	compatible = "auo,b080uan01";
	reg = <0>;

	enable-gpios = <&gpio TEGRA_GPIO(V, 2)
	GPIO_ACTIVE_HIGH>;
	power-supply = <&vdd_5v0_io>;
	backlight = <&backlight>;
	};
	};
	};

	i2c@7000c400 {
	backlight: backlight@2c {
	compatible = "ti,lp8557";
	reg = <0x2c>;
	+ power-supply = <&vdd_3v3_sys>;

	dev-ctrl = /bits/ 8 <0x80>;
	init-brt = /bits/ 8 <0xff>;

	pwm-period = <29334>;

	pwms = <&pwm 0 29334>;
	pwm-names = "lp8557";

	/* 3 LED string */
	rom_14h {
	rom-addr = /bits/ 8 <0x14>;
	rom-val = /bits/ 8 <0x87>;
	};

	/* boost frequency 1 MHz */
	rom_13h {
	rom-addr = /bits/ 8 <0x13>;
	rom-val = /bits/ 8 <0x01>;
	};
	};
	};

	i2c@7000c500 {
	/* carrier board ID EEPROM */
	eeprom@57 {
	compatible = "atmel,24c02";
	reg = <0x57>;

	+ vcc-supply = <&vdd_1v8>;
	address-bits = <8>;
	page-size = <8>;
	size = <256>;
	read-only;
	};
	};

	clock@70110000 {
	status = "okay";

	nvidia,cf = <6>;
	nvidia,ci = <0>;
	nvidia,cg = <2>;
	nvidia,droop-ctrl = <0x00000f00>;
	nvidia,force-mode = <1>;
	nvidia,sample-rate = <25000>;

	nvidia,pwm-min-microvolts = <708000>;
	nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
	nvidia,pwm-to-pmic;
	nvidia,pwm-tristate-microvolts = <1000000>;
	nvidia,pwm-voltage-step-microvolts = <19200>;

	pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
	pinctrl-0 = <&dvfs_pwm_active_state>;
	pinctrl-1 = <&dvfs_pwm_inactive_state>;
	};

	aconnect@702c0000 {
	status = "okay";

	dma@702e2000 {
	status = "okay";
	};

	agic@702f9000 {
	status = "okay";
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/nvidia/tegra210-p2597.dtsi b/sys/gnu/dts/arm64/nvidia/tegra210-p2597.dtsi
	index b0095072bc28..313a4c29d37a 100644
	--- a/sys/gnu/dts/arm64/nvidia/tegra210-p2597.dtsi
	+++ b/sys/gnu/dts/arm64/nvidia/tegra210-p2597.dtsi
	@@ -1,1644 +1,1685 @@
	// SPDX-License-Identifier: GPL-2.0
	#include <dt-bindings/input/input.h>

	/ {
	model = "NVIDIA Tegra210 P2597 I/O board";
	compatible = "nvidia,p2597", "nvidia,tegra210";

	+ aliases {
	+ ethernet = "/usb@70090000/ethernet@1";
	+ };
	+
	host1x@50000000 {
	dpaux@54040000 {
	status = "okay";
	};

	sor@54580000 {
	status = "okay";

	avdd-io-supply = <&avdd_1v05>;
	vdd-pll-supply = <&vdd_1v8>;
	hdmi-supply = <&vdd_hdmi>;

	nvidia,ddc-i2c-bus = <&hdmi_ddc>;
	nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
	GPIO_ACTIVE_LOW>;
	};
	};

	pinmux: pinmux@700008d4 {
	pinctrl-names = "boot";
	pinctrl-0 = <&state_boot>;

	state_boot: pinmux {
	pex_l0_rst_n_pa0 {
	nvidia,pins = "pex_l0_rst_n_pa0";
	nvidia,function = "pe0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_ENABLE>;
	};
	pex_l0_clkreq_n_pa1 {
	nvidia,pins = "pex_l0_clkreq_n_pa1";
	nvidia,function = "pe0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_ENABLE>;
	};
	pex_wake_n_pa2 {
	nvidia,pins = "pex_wake_n_pa2";
	nvidia,function = "pe";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_ENABLE>;
	};
	pex_l1_rst_n_pa3 {
	nvidia,pins = "pex_l1_rst_n_pa3";
	nvidia,function = "pe1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_ENABLE>;
	};
	pex_l1_clkreq_n_pa4 {
	nvidia,pins = "pex_l1_clkreq_n_pa4";
	nvidia,function = "pe1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_ENABLE>;
	};
	sata_led_active_pa5 {
	nvidia,pins = "sata_led_active_pa5";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pa6 {
	nvidia,pins = "pa6";
	nvidia,function = "sata";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap1_fs_pb0 {
	nvidia,pins = "dap1_fs_pb0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap1_din_pb1 {
	nvidia,pins = "dap1_din_pb1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap1_dout_pb2 {
	nvidia,pins = "dap1_dout_pb2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap1_sclk_pb3 {
	nvidia,pins = "dap1_sclk_pb3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi2_mosi_pb4 {
	nvidia,pins = "spi2_mosi_pb4";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi2_miso_pb5 {
	nvidia,pins = "spi2_miso_pb5";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi2_sck_pb6 {
	nvidia,pins = "spi2_sck_pb6";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi2_cs0_pb7 {
	nvidia,pins = "spi2_cs0_pb7";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi1_mosi_pc0 {
	nvidia,pins = "spi1_mosi_pc0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi1_miso_pc1 {
	nvidia,pins = "spi1_miso_pc1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi1_sck_pc2 {
	nvidia,pins = "spi1_sck_pc2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi1_cs0_pc3 {
	nvidia,pins = "spi1_cs0_pc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi1_cs1_pc4 {
	nvidia,pins = "spi1_cs1_pc4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi4_sck_pc5 {
	nvidia,pins = "spi4_sck_pc5";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi4_cs0_pc6 {
	nvidia,pins = "spi4_cs0_pc6";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi4_mosi_pc7 {
	nvidia,pins = "spi4_mosi_pc7";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi4_miso_pd0 {
	nvidia,pins = "spi4_miso_pd0";
	nvidia,function = "spi4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart3_tx_pd1 {
	nvidia,pins = "uart3_tx_pd1";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart3_rx_pd2 {
	nvidia,pins = "uart3_rx_pd2";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart3_rts_pd3 {
	nvidia,pins = "uart3_rts_pd3";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart3_cts_pd4 {
	nvidia,pins = "uart3_cts_pd4";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dmic1_clk_pe0 {
	nvidia,pins = "dmic1_clk_pe0";
	nvidia,function = "i2s3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dmic1_dat_pe1 {
	nvidia,pins = "dmic1_dat_pe1";
	nvidia,function = "i2s3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dmic2_clk_pe2 {
	nvidia,pins = "dmic2_clk_pe2";
	nvidia,function = "i2s3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dmic2_dat_pe3 {
	nvidia,pins = "dmic2_dat_pe3";
	nvidia,function = "i2s3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dmic3_clk_pe4 {
	nvidia,pins = "dmic3_clk_pe4";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dmic3_dat_pe5 {
	nvidia,pins = "dmic3_dat_pe5";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pe6 {
	nvidia,pins = "pe6";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pe7 {
	nvidia,pins = "pe7";
	nvidia,function = "pwm3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	gen3_i2c_scl_pf0 {
	nvidia,pins = "gen3_i2c_scl_pf0";
	nvidia,function = "i2c3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	gen3_i2c_sda_pf1 {
	nvidia,pins = "gen3_i2c_sda_pf1";
	nvidia,function = "i2c3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	uart2_tx_pg0 {
	nvidia,pins = "uart2_tx_pg0";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart2_rx_pg1 {
	nvidia,pins = "uart2_rx_pg1";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart2_rts_pg2 {
	nvidia,pins = "uart2_rts_pg2";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart2_cts_pg3 {
	nvidia,pins = "uart2_cts_pg3";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	wifi_en_ph0 {
	nvidia,pins = "wifi_en_ph0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	wifi_rst_ph1 {
	nvidia,pins = "wifi_rst_ph1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	wifi_wake_ap_ph2 {
	nvidia,pins = "wifi_wake_ap_ph2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	ap_wake_bt_ph3 {
	nvidia,pins = "ap_wake_bt_ph3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	bt_rst_ph4 {
	nvidia,pins = "bt_rst_ph4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	bt_wake_ap_ph5 {
	nvidia,pins = "bt_wake_ap_ph5";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	ph6 {
	nvidia,pins = "ph6";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	ap_wake_nfc_ph7 {
	nvidia,pins = "ap_wake_nfc_ph7";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	nfc_en_pi0 {
	nvidia,pins = "nfc_en_pi0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	nfc_int_pi1 {
	nvidia,pins = "nfc_int_pi1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	gps_en_pi2 {
	nvidia,pins = "gps_en_pi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	gps_rst_pi3 {
	nvidia,pins = "gps_rst_pi3";
	nvidia,function = "rsvd0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart4_tx_pi4 {
	nvidia,pins = "uart4_tx_pi4";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart4_rx_pi5 {
	nvidia,pins = "uart4_rx_pi5";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart4_rts_pi6 {
	nvidia,pins = "uart4_rts_pi6";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart4_cts_pi7 {
	nvidia,pins = "uart4_cts_pi7";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	gen1_i2c_sda_pj0 {
	nvidia,pins = "gen1_i2c_sda_pj0";
	nvidia,function = "i2c1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	gen1_i2c_scl_pj1 {
	nvidia,pins = "gen1_i2c_scl_pj1";
	nvidia,function = "i2c1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	gen2_i2c_scl_pj2 {
	nvidia,pins = "gen2_i2c_scl_pj2";
	nvidia,function = "i2c2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_ENABLE>;
	};
	gen2_i2c_sda_pj3 {
	nvidia,pins = "gen2_i2c_sda_pj3";
	nvidia,function = "i2c2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_ENABLE>;
	};
	dap4_fs_pj4 {
	nvidia,pins = "dap4_fs_pj4";
	nvidia,function = "i2s4b";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap4_din_pj5 {
	nvidia,pins = "dap4_din_pj5";
	nvidia,function = "i2s4b";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap4_dout_pj6 {
	nvidia,pins = "dap4_dout_pj6";
	nvidia,function = "i2s4b";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap4_sclk_pj7 {
	nvidia,pins = "dap4_sclk_pj7";
	nvidia,function = "i2s4b";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pk0 {
	nvidia,pins = "pk0";
	nvidia,function = "i2s5b";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pk1 {
	nvidia,pins = "pk1";
	nvidia,function = "i2s5b";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pk2 {
	nvidia,pins = "pk2";
	nvidia,function = "i2s5b";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pk3 {
	nvidia,pins = "pk3";
	nvidia,function = "i2s5b";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pk4 {
	nvidia,pins = "pk4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pk5 {
	nvidia,pins = "pk5";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pk6 {
	nvidia,pins = "pk6";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pk7 {
	nvidia,pins = "pk7";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pl0 {
	nvidia,pins = "pl0";
	nvidia,function = "rsvd0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pl1 {
	nvidia,pins = "pl1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_clk_pm0 {
	nvidia,pins = "sdmmc1_clk_pm0";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_cmd_pm1 {
	nvidia,pins = "sdmmc1_cmd_pm1";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_dat3_pm2 {
	nvidia,pins = "sdmmc1_dat3_pm2";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_dat2_pm3 {
	nvidia,pins = "sdmmc1_dat2_pm3";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_dat1_pm4 {
	nvidia,pins = "sdmmc1_dat1_pm4";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_dat0_pm5 {
	nvidia,pins = "sdmmc1_dat0_pm5";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_clk_pp0 {
	nvidia,pins = "sdmmc3_clk_pp0";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_cmd_pp1 {
	nvidia,pins = "sdmmc3_cmd_pp1";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_dat3_pp2 {
	nvidia,pins = "sdmmc3_dat3_pp2";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_dat2_pp3 {
	nvidia,pins = "sdmmc3_dat2_pp3";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_dat1_pp4 {
	nvidia,pins = "sdmmc3_dat1_pp4";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_dat0_pp5 {
	nvidia,pins = "sdmmc3_dat0_pp5";
	nvidia,function = "sdmmc3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cam1_mclk_ps0 {
	nvidia,pins = "cam1_mclk_ps0";
	nvidia,function = "extperiph3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cam2_mclk_ps1 {
	nvidia,pins = "cam2_mclk_ps1";
	nvidia,function = "extperiph3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cam_i2c_scl_ps2 {
	nvidia,pins = "cam_i2c_scl_ps2";
	nvidia,function = "i2cvi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	cam_i2c_sda_ps3 {
	nvidia,pins = "cam_i2c_sda_ps3";
	nvidia,function = "i2cvi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	cam_rst_ps4 {
	nvidia,pins = "cam_rst_ps4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cam_af_en_ps5 {
	nvidia,pins = "cam_af_en_ps5";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cam_flash_en_ps6 {
	nvidia,pins = "cam_flash_en_ps6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cam1_pwdn_ps7 {
	nvidia,pins = "cam1_pwdn_ps7";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cam2_pwdn_pt0 {
	nvidia,pins = "cam2_pwdn_pt0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cam1_strobe_pt1 {
	nvidia,pins = "cam1_strobe_pt1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart1_tx_pu0 {
	nvidia,pins = "uart1_tx_pu0";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart1_rx_pu1 {
	nvidia,pins = "uart1_rx_pu1";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart1_rts_pu2 {
	nvidia,pins = "uart1_rts_pu2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart1_cts_pu3 {
	nvidia,pins = "uart1_cts_pu3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	lcd_bl_pwm_pv0 {
	nvidia,pins = "lcd_bl_pwm_pv0";
	nvidia,function = "pwm0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	lcd_bl_en_pv1 {
	nvidia,pins = "lcd_bl_en_pv1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	lcd_rst_pv2 {
	nvidia,pins = "lcd_rst_pv2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	lcd_gpio1_pv3 {
	nvidia,pins = "lcd_gpio1_pv3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	lcd_gpio2_pv4 {
	nvidia,pins = "lcd_gpio2_pv4";
	nvidia,function = "pwm1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	ap_ready_pv5 {
	nvidia,pins = "ap_ready_pv5";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	touch_rst_pv6 {
	nvidia,pins = "touch_rst_pv6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	touch_clk_pv7 {
	nvidia,pins = "touch_clk_pv7";
	nvidia,function = "touch";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	modem_wake_ap_px0 {
	nvidia,pins = "modem_wake_ap_px0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	touch_int_px1 {
	nvidia,pins = "touch_int_px1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	motion_int_px2 {
	nvidia,pins = "motion_int_px2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	als_prox_int_px3 {
	nvidia,pins = "als_prox_int_px3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	temp_alert_px4 {
	nvidia,pins = "temp_alert_px4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	button_power_on_px5 {
	nvidia,pins = "button_power_on_px5";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	button_vol_up_px6 {
	nvidia,pins = "button_vol_up_px6";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	button_vol_down_px7 {
	nvidia,pins = "button_vol_down_px7";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	button_slide_sw_py0 {
	nvidia,pins = "button_slide_sw_py0";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	button_home_py1 {
	nvidia,pins = "button_home_py1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	lcd_te_py2 {
	nvidia,pins = "lcd_te_py2";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pwr_i2c_scl_py3 {
	nvidia,pins = "pwr_i2c_scl_py3";
	nvidia,function = "i2cpmu";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	pwr_i2c_sda_py4 {
	nvidia,pins = "pwr_i2c_sda_py4";
	nvidia,function = "i2cpmu";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	clk_32k_out_py5 {
	nvidia,pins = "clk_32k_out_py5";
	nvidia,function = "soc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pz0 {
	nvidia,pins = "pz0";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pz1 {
	nvidia,pins = "pz1";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pz2 {
	nvidia,pins = "pz2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pz3 {
	nvidia,pins = "pz3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pz4 {
	nvidia,pins = "pz4";
	nvidia,function = "sdmmc1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pz5 {
	nvidia,pins = "pz5";
	nvidia,function = "soc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap2_fs_paa0 {
	nvidia,pins = "dap2_fs_paa0";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap2_sclk_paa1 {
	nvidia,pins = "dap2_sclk_paa1";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap2_din_paa2 {
	nvidia,pins = "dap2_din_paa2";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap2_dout_paa3 {
	nvidia,pins = "dap2_dout_paa3";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	aud_mclk_pbb0 {
	nvidia,pins = "aud_mclk_pbb0";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dvfs_pwm_pbb1 {
	nvidia,pins = "dvfs_pwm_pbb1";
	nvidia,function = "cldvfs";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dvfs_clk_pbb2 {
	nvidia,pins = "dvfs_clk_pbb2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	gpio_x1_aud_pbb3 {
	nvidia,pins = "gpio_x1_aud_pbb3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	gpio_x3_aud_pbb4 {
	nvidia,pins = "gpio_x3_aud_pbb4";
	nvidia,function = "rsvd0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	hdmi_cec_pcc0 {
	nvidia,pins = "hdmi_cec_pcc0";
	nvidia,function = "cec";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_ENABLE>;
	};
	hdmi_int_dp_hpd_pcc1 {
	nvidia,pins = "hdmi_int_dp_hpd_pcc1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	spdif_out_pcc2 {
	nvidia,pins = "spdif_out_pcc2";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spdif_in_pcc3 {
	nvidia,pins = "spdif_in_pcc3";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	usb_vbus_en0_pcc4 {
	nvidia,pins = "usb_vbus_en0_pcc4";
	nvidia,function = "usb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_ENABLE>;
	};
	usb_vbus_en1_pcc5 {
	nvidia,pins = "usb_vbus_en1_pcc5";
	nvidia,function = "usb";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_ENABLE>;
	};
	dp_hpd0_pcc6 {
	nvidia,pins = "dp_hpd0_pcc6";
	nvidia,function = "dp";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pcc7 {
	nvidia,pins = "pcc7";
	nvidia,function = "rsvd0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	spi2_cs1_pdd0 {
	nvidia,pins = "spi2_cs1_pdd0";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	qspi_sck_pee0 {
	nvidia,pins = "qspi_sck_pee0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	qspi_cs_n_pee1 {
	nvidia,pins = "qspi_cs_n_pee1";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	qspi_io0_pee2 {
	nvidia,pins = "qspi_io0_pee2";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	qspi_io1_pee3 {
	nvidia,pins = "qspi_io1_pee3";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	qspi_io2_pee4 {
	nvidia,pins = "qspi_io2_pee4";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	qspi_io3_pee5 {
	nvidia,pins = "qspi_io3_pee5";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	core_pwr_req {
	nvidia,pins = "core_pwr_req";
	nvidia,function = "core";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cpu_pwr_req {
	nvidia,pins = "cpu_pwr_req";
	nvidia,function = "cpu";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pwr_int_n {
	nvidia,pins = "pwr_int_n";
	nvidia,function = "pmi";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	clk_32k_in {
	nvidia,pins = "clk_32k_in";
	nvidia,function = "clk";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	jtag_rtck {
	nvidia,pins = "jtag_rtck";
	nvidia,function = "jtag";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	clk_req {
	nvidia,pins = "clk_req";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	shutdown {
	nvidia,pins = "shutdown";
	nvidia,function = "shutdown";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	};

	dvfs_pwm_active_state: dvfs_pwm_active {
	dvfs_pwm_pbb1 {
	nvidia,pins = "dvfs_pwm_pbb1";
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	};
	};

	dvfs_pwm_inactive_state: dvfs_pwm_inactive {
	dvfs_pwm_pbb1 {
	nvidia,pins = "dvfs_pwm_pbb1";
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	};
	};
	};

	pwm@7000a000 {
	status = "okay";
	};

	i2c@7000c400 {
	status = "okay";
	clock-frequency = <100000>;

	exp1: gpio@74 {
	compatible = "ti,tca9539";
	reg = <0x74>;

	#gpio-cells = <2>;
	gpio-controller;
	};
	};

	/* HDMI DDC */
	hdmi_ddc: i2c@7000c700 {
	status = "okay";
	clock-frequency = <100000>;
	};

	sata@70020000 {
	status = "okay";
	phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
	};

	hda@70030000 {
	nvidia,model = "jetson-tx1-hda";
	status = "okay";
	};

	usb@70090000 {
	phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
	<&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
	<&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
	<&{/padctl@7009f000/pads/usb2/lanes/usb2-3}>,
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>,
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>;
	phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0",
	"usb3-1";
	-
	dvddio-pex-supply = <&vdd_pex_1v05>;
	hvddio-pex-supply = <&vdd_1v8>;
	avdd-usb-supply = <&vdd_3v3_sys>;
	/* XXX what are these? */
	avdd-pll-utmip-supply = <&vdd_1v8>;
	avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
	dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>;
	hvdd-usb-ss-pll-e-supply = <&vdd_1v8>;

	status = "okay";
	+
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ ethernet@1 {
	+ reg = <1>;
	+ };
	};

	padctl@7009f000 {
	status = "okay";

	avdd-pll-utmip-supply = <&vdd_1v8>;
	avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
	dvdd-pex-pll-supply = <&vdd_pex_1v05>;
	hvdd-pex-pll-e-supply = <&vdd_1v8>;

	pads {
	usb2 {
	status = "okay";

	lanes {
	- usb2-0 {
	+ micro_b: usb2-0 {
	nvidia,function = "xusb";
	status = "okay";
	};

	usb2-1 {
	nvidia,function = "xusb";
	status = "okay";
	};

	usb2-2 {
	nvidia,function = "xusb";
	status = "okay";
	};

	usb2-3 {
	nvidia,function = "xusb";
	status = "okay";
	};
	};
	};

	pcie {
	status = "okay";

	lanes {
	pcie-0 {
	nvidia,function = "pcie-x1";
	status = "okay";
	};

	pcie-1 {
	nvidia,function = "pcie-x4";
	status = "okay";
	};

	pcie-2 {
	nvidia,function = "pcie-x4";
	status = "okay";
	};

	pcie-3 {
	nvidia,function = "pcie-x4";
	status = "okay";
	};

	pcie-4 {
	nvidia,function = "pcie-x4";
	status = "okay";
	};

	pcie-5 {
	nvidia,function = "usb3-ss";
	status = "okay";
	};

	pcie-6 {
	nvidia,function = "usb3-ss";
	status = "okay";
	};
	};
	};

	sata {
	status = "okay";

	lanes {
	sata-0 {
	nvidia,function = "sata";
	status = "okay";
	};
	};
	};
	};

	ports {
	usb2-0 {
	status = "okay";
	+ vbus-supply = <&vdd_usb_vbus_otg>;
	mode = "otg";
	+
	+ usb-role-switch;
	+ connector {
	+ compatible = "usb-b-connector",
	+ "gpio-usb-b-connector";
	+ label = "micro-USB";
	+ type = "micro";
	+ vbus-gpio = <&gpio TEGRA_GPIO(Z, 0)
	+ GPIO_ACTIVE_LOW>;
	+ id-gpio = <&pmic 0 0>;
	+ };
	};

	usb2-1 {
	status = "okay";
	vbus-supply = <&vdd_5v0_rtl>;
	mode = "host";
	};

	usb2-2 {
	status = "okay";
	vbus-supply = <&vdd_usb_vbus>;
	mode = "host";
	};

	usb2-3 {
	status = "okay";
	mode = "host";
	};

	usb3-0 {
	nvidia,usb2-companion = <1>;
	status = "okay";
	};

	usb3-1 {
	nvidia,usb2-companion = <2>;
	status = "okay";
	};
	};
	};

	/* MMC/SD */
	sdhci@700b0000 {
	status = "okay";
	bus-width = <4>;

	cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;

	vqmmc-supply = <&vddio_sdmmc>;
	vmmc-supply = <&vdd_3v3_sd>;
	};

	+ usb@700d0000 {
	+ status = "okay";
	+ phys = <&micro_b>;
	+ phy-names = "usb2-0";
	+ avddio-usb-supply = <&vdd_3v3_sys>;
	+ hvdd-usb-supply = <&vdd_1v8>;
	+ };
	+
	regulators {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	vdd_sys_mux: regulator@0 {
	compatible = "regulator-fixed";
	reg = <0>;
	regulator-name = "VDD_SYS_MUX";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_5v0_sys: regulator@1 {
	compatible = "regulator-fixed";
	reg = <1>;
	regulator-name = "VDD_5V0_SYS";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_sys_mux>;
	};

	vdd_3v3_sys: regulator@2 {
	compatible = "regulator-fixed";
	reg = <2>;
	regulator-name = "VDD_3V3_SYS";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_sys_mux>;

	regulator-enable-ramp-delay = <160>;
	regulator-disable-ramp-delay = <10000>;
	};

	vdd_5v0_io: regulator@3 {
	compatible = "regulator-fixed";
	reg = <3>;
	regulator-name = "VDD_5V0_IO_SYS";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_3v3_sd: regulator@4 {
	compatible = "regulator-fixed";
	reg = <4>;
	regulator-name = "VDD_3V3_SD";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_3v3_sys>;

	regulator-enable-ramp-delay = <472>;
	regulator-disable-ramp-delay = <4880>;
	};

	vdd_dsi_csi: regulator@5 {
	compatible = "regulator-fixed";
	reg = <5>;
	regulator-name = "AVDD_DSI_CSI_1V2";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	vin-supply = <&vdd_sys_1v2>;
	};

	vdd_3v3_dis: regulator@6 {
	compatible = "regulator-fixed";
	reg = <6>;
	regulator-name = "VDD_DIS_3V3_LCD";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_3v3_sys>;
	};

	vdd_1v8_dis: regulator@7 {
	compatible = "regulator-fixed";
	reg = <7>;
	regulator-name = "VDD_LCD_1V8_DIS";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_1v8>;
	};

	vdd_5v0_rtl: regulator@8 {
	compatible = "regulator-fixed";
	reg = <8>;
	regulator-name = "RTL_5V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_5v0_sys>;
	};

	vdd_usb_vbus: regulator@9 {
	compatible = "regulator-fixed";
	reg = <9>;
	regulator-name = "USB_VBUS_EN1";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_5v0_sys>;
	};

	+ vdd_usb_vbus_otg: regulator@11 {
	+ compatible = "regulator-fixed";
	+ reg = <9>;
	+ regulator-name = "USB_VBUS_EN0";
	+ regulator-min-microvolt = <5000000>;
	+ regulator-max-microvolt = <5000000>;
	+ gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
	+ enable-active-high;
	+ vin-supply = <&vdd_5v0_sys>;
	+ };
	+
	vdd_hdmi: regulator@10 {
	compatible = "regulator-fixed";
	reg = <10>;
	regulator-name = "VDD_HDMI_5V0";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	gpio = <&exp1 12 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	vin-supply = <&vdd_5v0_sys>;
	};
	};

	gpio-keys {
	compatible = "gpio-keys";
	label = "gpio-keys";

	power {
	label = "Power";
	gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
	linux,code = <KEY_POWER>;
	wakeup-source;
	};

	volume_down {
	label = "Volume Down";
	gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_LOW>;
	linux,code = <KEY_VOLUMEDOWN>;
	};

	volume_up {
	label = "Volume Up";
	gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
	linux,code = <KEY_VOLUMEUP>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/nvidia/tegra210-p3450-0000.dts b/sys/gnu/dts/arm64/nvidia/tegra210-p3450-0000.dts
	index 9101d3a39cd2..21ed1756b889 100644
	--- a/sys/gnu/dts/arm64/nvidia/tegra210-p3450-0000.dts
	+++ b/sys/gnu/dts/arm64/nvidia/tegra210-p3450-0000.dts
	@@ -1,792 +1,812 @@
	// SPDX-License-Identifier: GPL-2.0
	/dts-v1/;

	#include <dt-bindings/input/gpio-keys.h>
	#include <dt-bindings/input/linux-event-codes.h>
	#include <dt-bindings/mfd/max77620.h>

	#include "tegra210.dtsi"

	/ {
	model = "NVIDIA Jetson Nano Developer Kit";
	compatible = "nvidia,p3450-0000", "nvidia,tegra210";

	aliases {
	ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
	rtc0 = "/i2c@7000d000/pmic@3c";
	rtc1 = "/rtc@7000e000";
	serial0 = &uarta;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	memory {
	device_type = "memory";
	reg = <0x0 0x80000000 0x1 0x0>;
	};

	pcie@1003000 {
	status = "okay";

	avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
	hvddio-pex-supply = <&vdd_1v8>;
	dvddio-pex-supply = <&vdd_pex_1v05>;
	dvdd-pex-pll-supply = <&vdd_pex_1v05>;
	hvdd-pex-pll-e-supply = <&vdd_1v8>;
	vddio-pex-ctl-supply = <&vdd_1v8>;

	pci@1,0 {
	phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>,
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
	phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
	nvidia,num-lanes = <4>;
	status = "okay";
	};

	pci@2,0 {
	phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
	phy-names = "pcie-0";
	status = "okay";

	ethernet@0,0 {
	reg = <0x000000 0 0 0 0>;
	local-mac-address = [ 00 00 00 00 00 00 ];
	};
	};
	};

	host1x@50000000 {
	dpaux@54040000 {
	status = "okay";
	};

	sor@54540000 {
	status = "okay";

	avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>;
	vdd-hdmi-dp-pll-supply = <&vdd_1v8>;

	nvidia,xbar-cfg = <2 1 0 3 4>;
	nvidia,dpaux = <&dpaux>;
	};

	sor@54580000 {
	status = "okay";

	avdd-io-supply = <&avdd_1v05>;
	vdd-pll-supply = <&vdd_1v8>;
	hdmi-supply = <&vdd_hdmi>;

	nvidia,ddc-i2c-bus = <&hdmi_ddc>;
	nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
	GPIO_ACTIVE_LOW>;
	nvidia,xbar-cfg = <0 1 2 3 4>;
	};

	dpaux@545c0000 {
	status = "okay";
	};
	};

	gpu@57000000 {
	vdd-supply = <&vdd_gpu>;
	status = "okay";
	};

	/* debug port */
	serial@70006000 {
	status = "okay";
	};

	pwm@7000a000 {
	status = "okay";
	};

	i2c@7000c500 {
	status = "okay";
	clock-frequency = <100000>;

	eeprom@50 {
	compatible = "atmel,24c02";
	reg = <0x50>;

	+ vcc-supply = <&vdd_1v8>;
	address-bits = <8>;
	page-size = <8>;
	size = <256>;
	read-only;
	};

	eeprom@57 {
	compatible = "atmel,24c02";
	reg = <0x57>;

	+ vcc-supply = <&vdd_1v8>;
	address-bits = <8>;
	page-size = <8>;
	size = <256>;
	read-only;
	};
	};

	hdmi_ddc: i2c@7000c700 {
	status = "okay";
	clock-frequency = <100000>;
	};

	i2c@7000d000 {
	status = "okay";
	clock-frequency = <400000>;

	pmic: pmic@3c {
	compatible = "maxim,max77620";
	reg = <0x3c>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;

	#interrupt-cells = <2>;
	interrupt-controller;

	#gpio-cells = <2>;
	gpio-controller;

	pinctrl-names = "default";
	pinctrl-0 = <&max77620_default>;

	max77620_default: pinmux {
	gpio0 {
	pins = "gpio0";
	function = "gpio";
	};

	gpio1 {
	pins = "gpio1";
	function = "fps-out";
	drive-push-pull = <1>;
	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
	maxim,active-fps-power-up-slot = <0>;
	maxim,active-fps-power-down-slot = <7>;
	};

	gpio2 {
	pins = "gpio2";
	function = "fps-out";
	drive-open-drain = <1>;
	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
	maxim,active-fps-power-up-slot = <0>;
	maxim,active-fps-power-down-slot = <7>;
	};

	gpio3 {
	pins = "gpio3";
	function = "fps-out";
	drive-open-drain = <1>;
	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
	maxim,active-fps-power-up-slot = <4>;
	maxim,active-fps-power-down-slot = <3>;
	};

	gpio4 {
	pins = "gpio4";
	function = "32k-out1";
	};

	gpio5_6_7 {
	pins = "gpio5", "gpio6", "gpio7";
	function = "gpio";
	drive-push-pull = <1>;
	};
	};

	fps {
	fps0 {
	maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
	maxim,suspend-fps-time-period-us = <5120>;
	};

	fps1 {
	maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
	maxim,suspend-fps-time-period-us = <5120>;
	};

	fps2 {
	maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
	};
	};

	regulators {
	in-ldo0-1-supply = <&vdd_pre>;
	in-ldo2-supply = <&vdd_3v3_sys>;
	in-ldo3-5-supply = <&vdd_1v8>;
	in-ldo4-6-supply = <&vdd_5v0_sys>;
	in-ldo7-8-supply = <&vdd_pre>;
	in-sd0-supply = <&vdd_5v0_sys>;
	in-sd1-supply = <&vdd_5v0_sys>;
	in-sd2-supply = <&vdd_5v0_sys>;
	in-sd3-supply = <&vdd_5v0_sys>;

	vdd_soc: sd0 {
	regulator-name = "VDD_SOC";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1170000>;
	regulator-enable-ramp-delay = <146>;
	regulator-disable-ramp-delay = <4080>;
	regulator-ramp-delay = <27500>;
	regulator-ramp-delay-scale = <300>;
	regulator-always-on;
	regulator-boot-on;

	maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
	maxim,active-fps-power-up-slot = <1>;
	maxim,active-fps-power-down-slot = <6>;
	};

	vdd_ddr: sd1 {
	regulator-name = "VDD_DDR_1V1_PMIC";
	regulator-min-microvolt = <1150000>;
	regulator-max-microvolt = <1150000>;
	regulator-enable-ramp-delay = <176>;
	regulator-disable-ramp-delay = <145800>;
	regulator-ramp-delay = <27500>;
	regulator-ramp-delay-scale = <300>;
	regulator-always-on;
	regulator-boot-on;

	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
	maxim,active-fps-power-up-slot = <5>;
	maxim,active-fps-power-down-slot = <2>;
	};

	vdd_pre: sd2 {
	regulator-name = "VDD_PRE_REG_1V35";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-enable-ramp-delay = <176>;
	regulator-disable-ramp-delay = <32000>;
	regulator-ramp-delay = <27500>;
	regulator-ramp-delay-scale = <350>;
	regulator-always-on;
	regulator-boot-on;

	maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
	maxim,active-fps-power-up-slot = <2>;
	maxim,active-fps-power-down-slot = <5>;
	};

	vdd_1v8: sd3 {
	regulator-name = "VDD_1V8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-enable-ramp-delay = <242>;
	regulator-disable-ramp-delay = <118000>;
	regulator-ramp-delay = <27500>;
	regulator-ramp-delay-scale = <360>;
	regulator-always-on;
	regulator-boot-on;

	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
	maxim,active-fps-power-up-slot = <3>;
	maxim,active-fps-power-down-slot = <4>;
	};

	vdd_sys_1v2: ldo0 {
	regulator-name = "AVDD_SYS_1V2";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-enable-ramp-delay = <26>;
	regulator-disable-ramp-delay = <626>;
	regulator-ramp-delay = <100000>;
	regulator-ramp-delay-scale = <200>;
	regulator-always-on;
	regulator-boot-on;

	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
	maxim,active-fps-power-up-slot = <0>;
	maxim,active-fps-power-down-slot = <7>;
	};

	vdd_pex_1v05: ldo1 {
	regulator-name = "VDD_PEX_1V05";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	regulator-enable-ramp-delay = <22>;
	regulator-disable-ramp-delay = <650>;
	regulator-ramp-delay = <100000>;
	regulator-ramp-delay-scale = <200>;

	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
	maxim,active-fps-power-up-slot = <0>;
	maxim,active-fps-power-down-slot = <7>;
	};

	vddio_sdmmc: ldo2 {
	regulator-name = "VDDIO_SDMMC";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-enable-ramp-delay = <62>;
	regulator-disable-ramp-delay = <650>;
	regulator-ramp-delay = <100000>;
	regulator-ramp-delay-scale = <200>;

	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
	maxim,active-fps-power-up-slot = <0>;
	maxim,active-fps-power-down-slot = <7>;
	};

	ldo3 {
	status = "disabled";
	};

	vdd_rtc: ldo4 {
	regulator-name = "VDD_RTC";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1100000>;
	regulator-enable-ramp-delay = <22>;
	regulator-disable-ramp-delay = <610>;
	regulator-ramp-delay = <100000>;
	regulator-ramp-delay-scale = <200>;
	regulator-disable-active-discharge;
	regulator-always-on;
	regulator-boot-on;

	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
	maxim,active-fps-power-up-slot = <1>;
	maxim,active-fps-power-down-slot = <6>;
	};

	ldo5 {
	status = "disabled";
	};

	ldo6 {
	status = "disabled";
	};

	avdd_1v05_pll: ldo7 {
	regulator-name = "AVDD_1V05_PLL";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	regulator-enable-ramp-delay = <24>;
	regulator-disable-ramp-delay = <2768>;
	regulator-ramp-delay = <100000>;
	regulator-ramp-delay-scale = <200>;

	maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
	maxim,active-fps-power-up-slot = <3>;
	maxim,active-fps-power-down-slot = <4>;
	};

	avdd_1v05: ldo8 {
	regulator-name = "AVDD_SATA_HDMI_DP_1V05";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	regulator-enable-ramp-delay = <22>;
	regulator-disable-ramp-delay = <1160>;
	regulator-ramp-delay = <100000>;
	regulator-ramp-delay-scale = <200>;

	maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
	maxim,active-fps-power-up-slot = <6>;
	maxim,active-fps-power-down-slot = <1>;
	};
	};
	};
	};

	pmc@7000e400 {
	nvidia,invert-interrupt;
	nvidia,suspend-mode = <0>;
	nvidia,cpu-pwr-good-time = <0>;
	nvidia,cpu-pwr-off-time = <0>;
	nvidia,core-pwr-good-time = <4587 3876>;
	nvidia,core-pwr-off-time = <39065>;
	nvidia,core-power-req-active-high;
	nvidia,sys-clock-req-active-high;
	};

	hda@70030000 {
	nvidia,model = "jetson-nano-hda";

	status = "okay";
	};

	usb@70090000 {
	phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
	<&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
	<&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
	phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";

	avdd-usb-supply = <&vdd_3v3_sys>;
	dvddio-pex-supply = <&vdd_pex_1v05>;
	hvddio-pex-supply = <&vdd_1v8>;
	/* these really belong to the XUSB pad controller */
	avdd-pll-utmip-supply = <&vdd_1v8>;
	avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
	dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>;
	hvdd-usb-ss-pll-e-supply = <&vdd_1v8>;

	status = "okay";
	};

	padctl@7009f000 {
	status = "okay";

	avdd-pll-utmip-supply = <&vdd_1v8>;
	avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
	dvdd-pex-pll-supply = <&vdd_pex_1v05>;
	hvdd-pex-pll-e-supply = <&vdd_1v8>;

	pads {
	usb2 {
	status = "okay";

	lanes {
	- usb2-0 {
	+ micro_b: usb2-0 {
	nvidia,function = "xusb";
	status = "okay";
	};

	usb2-1 {
	nvidia,function = "xusb";
	status = "okay";
	};

	usb2-2 {
	nvidia,function = "xusb";
	status = "okay";
	};
	};
	};

	pcie {
	status = "okay";

	lanes {
	pcie-0 {
	nvidia,function = "pcie-x1";
	status = "okay";
	};

	pcie-1 {
	nvidia,function = "pcie-x4";
	status = "okay";
	};

	pcie-2 {
	nvidia,function = "pcie-x4";
	status = "okay";
	};

	pcie-3 {
	nvidia,function = "pcie-x4";
	status = "okay";
	};

	pcie-4 {
	nvidia,function = "pcie-x4";
	status = "okay";
	};

	pcie-5 {
	nvidia,function = "usb3-ss";
	status = "okay";
	};

	pcie-6 {
	nvidia,function = "usb3-ss";
	status = "okay";
	};
	};
	};
	};

	ports {
	usb2-0 {
	status = "okay";
	- mode = "otg";
	+ mode = "peripheral";
	+
	+ usb-role-switch;
	+ connector {
	+ compatible = "usb-b-connector",
	+ "gpio-usb-b-connector";
	+ label = "micro-USB";
	+ type = "micro";
	+ vbus-gpio = <&gpio TEGRA_GPIO(CC, 4)
	+ GPIO_ACTIVE_LOW>;
	+ };
	};

	usb2-1 {
	status = "okay";
	mode = "host";
	};

	usb2-2 {
	status = "okay";
	mode = "host";
	};

	usb3-0 {
	status = "okay";
	nvidia,usb2-companion = <1>;
	vbus-supply = <&vdd_hub_3v3>;
	};
	};
	};

	sdhci@700b0000 {
	status = "okay";
	bus-width = <4>;

	cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;

	vqmmc-supply = <&vddio_sdmmc>;
	vmmc-supply = <&vdd_3v3_sd>;
	};

	+ usb@700d0000 {
	+ status = "okay";
	+ phys = <&micro_b>;
	+ phy-names = "usb2-0";
	+ avddio-usb-supply = <&vdd_3v3_sys>;
	+ hvdd-usb-supply = <&vdd_1v8>;
	+ };
	+
	sdhci@700b0400 {
	status = "okay";
	bus-width = <4>;

	vqmmc-supply = <&vdd_1v8>;
	vmmc-supply = <&vdd_3v3_sys>;

	non-removable;
	cap-sdio-irq;
	keep-power-in-suspend;
	wakeup-source;
	};

	clocks {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	clk32k_in: clock@0 {
	compatible = "fixed-clock";
	reg = <0>;
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	};

	cpus {
	cpu@0 {
	enable-method = "psci";
	};

	cpu@1 {
	enable-method = "psci";
	};

	cpu@2 {
	enable-method = "psci";
	};

	cpu@3 {
	enable-method = "psci";
	};

	idle-states {
	cpu-sleep {
	status = "okay";
	};
	};
	};

	fan: fan {
	compatible = "pwm-fan";
	pwms = <&pwm 3 45334>;

	cooling-levels = <0 64 128 255>;
	#cooling-cells = <2>;
	};

	thermal-zones {
	cpu {
	trips {
	cpu_trip_critical: critical {
	temperature = <96500>;
	hysteresis = <0>;
	type = "critical";
	};

	cpu_trip_hot: hot {
	temperature = <70000>;
	hysteresis = <2000>;
	type = "hot";
	};

	cpu_trip_active: active {
	temperature = <50000>;
	hysteresis = <2000>;
	type = "active";
	};

	cpu_trip_passive: passive {
	temperature = <30000>;
	hysteresis = <2000>;
	type = "passive";
	};
	};

	cooling-maps {
	cpu-critical {
	cooling-device = <&fan 3 3>;
	trip = <&cpu_trip_critical>;
	};

	cpu-hot {
	cooling-device = <&fan 2 2>;
	trip = <&cpu_trip_hot>;
	};

	cpu-active {
	cooling-device = <&fan 1 1>;
	trip = <&cpu_trip_active>;
	};

	cpu-passive {
	cooling-device = <&fan 0 0>;
	trip = <&cpu_trip_passive>;
	};
	};
	};
	};

	gpio-keys {
	compatible = "gpio-keys";

	power {
	label = "Power";
	gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
	linux,input-type = <EV_KEY>;
	linux,code = <KEY_POWER>;
	debounce-interval = <30>;
	wakeup-event-action = <EV_ACT_ASSERTED>;
	wakeup-source;
	};

	force-recovery {
	label = "Force Recovery";
	gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
	linux,input-type = <EV_KEY>;
	linux,code = <BTN_1>;
	debounce-interval = <30>;
	};
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	regulators {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	vdd_5v0_sys: regulator@0 {
	compatible = "regulator-fixed";
	reg = <0>;

	regulator-name = "VDD_5V0_SYS";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_3v3_sys: regulator@1 {
	compatible = "regulator-fixed";
	reg = <1>;
	regulator-name = "VDD_3V3_SYS";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-enable-ramp-delay = <240>;
	regulator-disable-ramp-delay = <11340>;
	regulator-always-on;
	regulator-boot-on;

	gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
	enable-active-high;

	vin-supply = <&vdd_5v0_sys>;
	};

	vdd_3v3_sd: regulator@2 {
	compatible = "regulator-fixed";
	reg = <2>;

	regulator-name = "VDD_3V3_SD";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
	enable-active-high;

	vin-supply = <&vdd_3v3_sys>;
	};

	vdd_hdmi: regulator@3 {
	compatible = "regulator-fixed";
	reg = <3>;

	regulator-name = "VDD_HDMI_5V0";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;

	vin-supply = <&vdd_5v0_sys>;
	};

	vdd_hub_3v3: regulator@4 {
	compatible = "regulator-fixed";
	reg = <4>;

	regulator-name = "VDD_HUB_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
	enable-active-high;

	vin-supply = <&vdd_5v0_sys>;
	};

	vdd_cpu: regulator@5 {
	compatible = "regulator-fixed";
	reg = <5>;

	regulator-name = "VDD_CPU";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;

	gpio = <&pmic 5 GPIO_ACTIVE_HIGH>;
	enable-active-high;

	vin-supply = <&vdd_5v0_sys>;
	};

	vdd_gpu: regulator@6 {
	compatible = "pwm-regulator";
	reg = <6>;
	pwms = <&pwm 1 4880>;
	regulator-name = "VDD_GPU";
	regulator-min-microvolt = <710000>;
	regulator-max-microvolt = <1320000>;
	regulator-ramp-delay = <80>;
	regulator-enable-ramp-delay = <2000>;
	regulator-settling-time-us = <160>;
	enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
	vin-supply = <&vdd_5v0_sys>;
	};

	avdd_io_edp_1v05: regulator@7 {
	compatible = "regulator-fixed";
	reg = <7>;

	regulator-name = "AVDD_IO_EDP_1V05";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;

	gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
	enable-active-high;

	vin-supply = <&avdd_1v05_pll>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/nvidia/tegra210-smaug.dts b/sys/gnu/dts/arm64/nvidia/tegra210-smaug.dts
	index 72c7a04ac1df..2faab6390552 100644
	--- a/sys/gnu/dts/arm64/nvidia/tegra210-smaug.dts
	+++ b/sys/gnu/dts/arm64/nvidia/tegra210-smaug.dts
	@@ -1,1902 +1,1902 @@
	// SPDX-License-Identifier: GPL-2.0
	/dts-v1/;

	#include <dt-bindings/input/input.h>
	#include <dt-bindings/mfd/max77620.h>
	#include <dt-bindings/pinctrl/pinctrl-tegra.h>

	#include "tegra210.dtsi"

	/ {
	model = "Google Pixel C";
	compatible = "google,smaug-rev8", "google,smaug-rev7",
	"google,smaug-rev6", "google,smaug-rev5",
	"google,smaug-rev4", "google,smaug-rev3",
	"google,smaug-rev2", "google,smaug-rev1",
	"google,smaug", "nvidia,tegra210";

	aliases {
	serial0 = &uarta;
	};

	chosen {
	bootargs = "earlycon";
	stdout-path = "serial0:115200n8";
	};

	memory {
	device_type = "memory";
	reg = <0x0 0x80000000 0x0 0xc0000000>;
	};

	host1x@50000000 {
	dpaux: dpaux@545c0000 {
	status = "okay";
	};
	};

	pinmux: pinmux@700008d4 {
	pinctrl-names = "boot";
	pinctrl-0 = <&state_boot>;

	state_boot: pinmux {
	pex_l0_rst_n_pa0 {
	nvidia,pins = "pex_l0_rst_n_pa0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	pex_l0_clkreq_n_pa1 {
	nvidia,pins = "pex_l0_clkreq_n_pa1";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	pex_wake_n_pa2 {
	nvidia,pins = "pex_wake_n_pa2";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	pex_l1_rst_n_pa3 {
	nvidia,pins = "pex_l1_rst_n_pa3";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	pex_l1_clkreq_n_pa4 {
	nvidia,pins = "pex_l1_clkreq_n_pa4";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	sata_led_active_pa5 {
	nvidia,pins = "sata_led_active_pa5";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pa6 {
	nvidia,pins = "pa6";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap1_fs_pb0 {
	nvidia,pins = "dap1_fs_pb0";
	nvidia,function = "i2s1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap1_din_pb1 {
	nvidia,pins = "dap1_din_pb1";
	nvidia,function = "i2s1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap1_dout_pb2 {
	nvidia,pins = "dap1_dout_pb2";
	nvidia,function = "i2s1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap1_sclk_pb3 {
	nvidia,pins = "dap1_sclk_pb3";
	nvidia,function = "i2s1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi2_mosi_pb4 {
	nvidia,pins = "spi2_mosi_pb4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi2_miso_pb5 {
	nvidia,pins = "spi2_miso_pb5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi2_sck_pb6 {
	nvidia,pins = "spi2_sck_pb6";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi2_cs0_pb7 {
	nvidia,pins = "spi2_cs0_pb7";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi1_mosi_pc0 {
	nvidia,pins = "spi1_mosi_pc0";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi1_miso_pc1 {
	nvidia,pins = "spi1_miso_pc1";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi1_sck_pc2 {
	nvidia,pins = "spi1_sck_pc2";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi1_cs0_pc3 {
	nvidia,pins = "spi1_cs0_pc3";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi1_cs1_pc4 {
	nvidia,pins = "spi1_cs1_pc4";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi4_sck_pc5 {
	nvidia,pins = "spi4_sck_pc5";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi4_cs0_pc6 {
	nvidia,pins = "spi4_cs0_pc6";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi4_mosi_pc7 {
	nvidia,pins = "spi4_mosi_pc7";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spi4_miso_pd0 {
	nvidia,pins = "spi4_miso_pd0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart3_tx_pd1 {
	nvidia,pins = "uart3_tx_pd1";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart3_rx_pd2 {
	nvidia,pins = "uart3_rx_pd2";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart3_rts_pd3 {
	nvidia,pins = "uart3_rts_pd3";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart3_cts_pd4 {
	nvidia,pins = "uart3_cts_pd4";
	nvidia,function = "uartc";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dmic1_clk_pe0 {
	nvidia,pins = "dmic1_clk_pe0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dmic1_dat_pe1 {
	nvidia,pins = "dmic1_dat_pe1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dmic2_clk_pe2 {
	nvidia,pins = "dmic2_clk_pe2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dmic2_dat_pe3 {
	nvidia,pins = "dmic2_dat_pe3";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dmic3_clk_pe4 {
	nvidia,pins = "dmic3_clk_pe4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dmic3_dat_pe5 {
	nvidia,pins = "dmic3_dat_pe5";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pe6 {
	nvidia,pins = "pe6";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pe7 {
	nvidia,pins = "pe7";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	gen3_i2c_scl_pf0 {
	nvidia,pins = "gen3_i2c_scl_pf0";
	nvidia,function = "i2c3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	gen3_i2c_sda_pf1 {
	nvidia,pins = "gen3_i2c_sda_pf1";
	nvidia,function = "i2c3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	uart2_tx_pg0 {
	nvidia,pins = "uart2_tx_pg0";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart2_rx_pg1 {
	nvidia,pins = "uart2_rx_pg1";
	nvidia,function = "uartb";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart2_rts_pg2 {
	nvidia,pins = "uart2_rts_pg2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart2_cts_pg3 {
	nvidia,pins = "uart2_cts_pg3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	wifi_en_ph0 {
	nvidia,pins = "wifi_en_ph0";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	wifi_rst_ph1 {
	nvidia,pins = "wifi_rst_ph1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	wifi_wake_ap_ph2 {
	nvidia,pins = "wifi_wake_ap_ph2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	ap_wake_bt_ph3 {
	nvidia,pins = "ap_wake_bt_ph3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	bt_rst_ph4 {
	nvidia,pins = "bt_rst_ph4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	bt_wake_ap_ph5 {
	nvidia,pins = "bt_wake_ap_ph5";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	ph6 {
	nvidia,pins = "ph6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	ap_wake_nfc_ph7 {
	nvidia,pins = "ap_wake_nfc_ph7";
	nvidia,function = "rsvd0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	nfc_en_pi0 {
	nvidia,pins = "nfc_en_pi0";
	nvidia,function = "rsvd0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	nfc_int_pi1 {
	nvidia,pins = "nfc_int_pi1";
	nvidia,function = "rsvd0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	gps_en_pi2 {
	nvidia,pins = "gps_en_pi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	gps_rst_pi3 {
	nvidia,pins = "gps_rst_pi3";
	nvidia,function = "rsvd0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart4_tx_pi4 {
	nvidia,pins = "uart4_tx_pi4";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart4_rx_pi5 {
	nvidia,pins = "uart4_rx_pi5";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart4_rts_pi6 {
	nvidia,pins = "uart4_rts_pi6";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart4_cts_pi7 {
	nvidia,pins = "uart4_cts_pi7";
	nvidia,function = "uartd";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	gen1_i2c_sda_pj0 {
	nvidia,pins = "gen1_i2c_sda_pj0";
	nvidia,function = "i2c1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	gen1_i2c_scl_pj1 {
	nvidia,pins = "gen1_i2c_scl_pj1";
	nvidia,function = "i2c1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	gen2_i2c_scl_pj2 {
	nvidia,pins = "gen2_i2c_scl_pj2";
	nvidia,function = "i2c2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_ENABLE>;
	};
	gen2_i2c_sda_pj3 {
	nvidia,pins = "gen2_i2c_sda_pj3";
	nvidia,function = "i2c2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_ENABLE>;
	};
	dap4_fs_pj4 {
	nvidia,pins = "dap4_fs_pj4";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap4_din_pj5 {
	nvidia,pins = "dap4_din_pj5";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap4_dout_pj6 {
	nvidia,pins = "dap4_dout_pj6";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap4_sclk_pj7 {
	nvidia,pins = "dap4_sclk_pj7";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pk0 {
	nvidia,pins = "pk0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pk1 {
	nvidia,pins = "pk1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pk2 {
	nvidia,pins = "pk2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pk3 {
	nvidia,pins = "pk3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pk4 {
	nvidia,pins = "pk4";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pk5 {
	nvidia,pins = "pk5";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pk6 {
	nvidia,pins = "pk6";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pk7 {
	nvidia,pins = "pk7";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pl0 {
	nvidia,pins = "pl0";
	nvidia,function = "rsvd0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pl1 {
	nvidia,pins = "pl1";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_clk_pm0 {
	nvidia,pins = "sdmmc1_clk_pm0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_cmd_pm1 {
	nvidia,pins = "sdmmc1_cmd_pm1";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_dat3_pm2 {
	nvidia,pins = "sdmmc1_dat3_pm2";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_dat2_pm3 {
	nvidia,pins = "sdmmc1_dat2_pm3";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_dat1_pm4 {
	nvidia,pins = "sdmmc1_dat1_pm4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc1_dat0_pm5 {
	nvidia,pins = "sdmmc1_dat0_pm5";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_clk_pp0 {
	nvidia,pins = "sdmmc3_clk_pp0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_cmd_pp1 {
	nvidia,pins = "sdmmc3_cmd_pp1";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_dat3_pp2 {
	nvidia,pins = "sdmmc3_dat3_pp2";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_dat2_pp3 {
	nvidia,pins = "sdmmc3_dat2_pp3";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_dat1_pp4 {
	nvidia,pins = "sdmmc3_dat1_pp4";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	sdmmc3_dat0_pp5 {
	nvidia,pins = "sdmmc3_dat0_pp5";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cam1_mclk_ps0 {
	nvidia,pins = "cam1_mclk_ps0";
	nvidia,function = "extperiph3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cam2_mclk_ps1 {
	nvidia,pins = "cam2_mclk_ps1";
	nvidia,function = "extperiph3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cam_i2c_scl_ps2 {
	nvidia,pins = "cam_i2c_scl_ps2";
	nvidia,function = "i2cvi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	cam_i2c_sda_ps3 {
	nvidia,pins = "cam_i2c_sda_ps3";
	nvidia,function = "i2cvi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	cam_rst_ps4 {
	nvidia,pins = "cam_rst_ps4";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cam_af_en_ps5 {
	nvidia,pins = "cam_af_en_ps5";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cam_flash_en_ps6 {
	nvidia,pins = "cam_flash_en_ps6";
	nvidia,function = "rsvd2";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cam1_pwdn_ps7 {
	nvidia,pins = "cam1_pwdn_ps7";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cam2_pwdn_pt0 {
	nvidia,pins = "cam2_pwdn_pt0";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cam1_strobe_pt1 {
	nvidia,pins = "cam1_strobe_pt1";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart1_tx_pu0 {
	nvidia,pins = "uart1_tx_pu0";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart1_rx_pu1 {
	nvidia,pins = "uart1_rx_pu1";
	nvidia,function = "uarta";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart1_rts_pu2 {
	nvidia,pins = "uart1_rts_pu2";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	uart1_cts_pu3 {
	nvidia,pins = "uart1_cts_pu3";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	lcd_bl_pwm_pv0 {
	nvidia,pins = "lcd_bl_pwm_pv0";
	nvidia,function = "rsvd3";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	lcd_bl_en_pv1 {
	nvidia,pins = "lcd_bl_en_pv1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	lcd_rst_pv2 {
	nvidia,pins = "lcd_rst_pv2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	lcd_gpio1_pv3 {
	nvidia,pins = "lcd_gpio1_pv3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	lcd_gpio2_pv4 {
	nvidia,pins = "lcd_gpio2_pv4";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	ap_ready_pv5 {
	nvidia,pins = "ap_ready_pv5";
	nvidia,function = "rsvd0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	touch_rst_pv6 {
	nvidia,pins = "touch_rst_pv6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	touch_clk_pv7 {
	nvidia,pins = "touch_clk_pv7";
	nvidia,function = "touch";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	modem_wake_ap_px0 {
	nvidia,pins = "modem_wake_ap_px0";
	nvidia,function = "rsvd0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	touch_int_px1 {
	nvidia,pins = "touch_int_px1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	motion_int_px2 {
	nvidia,pins = "motion_int_px2";
	nvidia,function = "rsvd0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	als_prox_int_px3 {
	nvidia,pins = "als_prox_int_px3";
	nvidia,function = "rsvd0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	temp_alert_px4 {
	nvidia,pins = "temp_alert_px4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	button_power_on_px5 {
	nvidia,pins = "button_power_on_px5";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	button_vol_up_px6 {
	nvidia,pins = "button_vol_up_px6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	button_vol_down_px7 {
	nvidia,pins = "button_vol_down_px7";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	button_slide_sw_py0 {
	nvidia,pins = "button_slide_sw_py0";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	button_home_py1 {
	nvidia,pins = "button_home_py1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	lcd_te_py2 {
	nvidia,pins = "lcd_te_py2";
	nvidia,function = "displaya";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pwr_i2c_scl_py3 {
	nvidia,pins = "pwr_i2c_scl_py3";
	nvidia,function = "i2cpmu";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	pwr_i2c_sda_py4 {
	nvidia,pins = "pwr_i2c_sda_py4";
	nvidia,function = "i2cpmu";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	clk_32k_out_py5 {
	nvidia,pins = "clk_32k_out_py5";
	nvidia,function = "soc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pz0 {
	nvidia,pins = "pz0";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pz1 {
	nvidia,pins = "pz1";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pz2 {
	nvidia,pins = "pz2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pz3 {
	nvidia,pins = "pz3";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pz4 {
	nvidia,pins = "pz4";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pz5 {
	nvidia,pins = "pz5";
	nvidia,function = "soc";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap2_fs_paa0 {
	nvidia,pins = "dap2_fs_paa0";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap2_sclk_paa1 {
	nvidia,pins = "dap2_sclk_paa1";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap2_din_paa2 {
	nvidia,pins = "dap2_din_paa2";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dap2_dout_paa3 {
	nvidia,pins = "dap2_dout_paa3";
	nvidia,function = "i2s2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	aud_mclk_pbb0 {
	nvidia,pins = "aud_mclk_pbb0";
	nvidia,function = "aud";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dvfs_pwm_pbb1 {
	nvidia,pins = "dvfs_pwm_pbb1";
	nvidia,function = "rsvd0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	dvfs_clk_pbb2 {
	nvidia,pins = "dvfs_clk_pbb2";
	nvidia,function = "rsvd0";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	gpio_x1_aud_pbb3 {
	nvidia,pins = "gpio_x1_aud_pbb3";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	gpio_x3_aud_pbb4 {
	nvidia,pins = "gpio_x3_aud_pbb4";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	hdmi_cec_pcc0 {
	nvidia,pins = "hdmi_cec_pcc0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	hdmi_int_dp_hpd_pcc1 {
	nvidia,pins = "hdmi_int_dp_hpd_pcc1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	spdif_out_pcc2 {
	nvidia,pins = "spdif_out_pcc2";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	spdif_in_pcc3 {
	nvidia,pins = "spdif_in_pcc3";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	usb_vbus_en0_pcc4 {
	nvidia,pins = "usb_vbus_en0_pcc4";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	usb_vbus_en1_pcc5 {
	nvidia,pins = "usb_vbus_en1_pcc5";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	dp_hpd0_pcc6 {
	nvidia,pins = "dp_hpd0_pcc6";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pcc7 {
	nvidia,pins = "pcc7";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	nvidia,io-hv = <TEGRA_PIN_DISABLE>;
	};
	spi2_cs1_pdd0 {
	nvidia,pins = "spi2_cs1_pdd0";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	qspi_sck_pee0 {
	nvidia,pins = "qspi_sck_pee0";
	nvidia,function = "qspi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	qspi_cs_n_pee1 {
	nvidia,pins = "qspi_cs_n_pee1";
	nvidia,function = "qspi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	qspi_io0_pee2 {
	nvidia,pins = "qspi_io0_pee2";
	nvidia,function = "qspi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	qspi_io1_pee3 {
	nvidia,pins = "qspi_io1_pee3";
	nvidia,function = "qspi";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	qspi_io2_pee4 {
	nvidia,pins = "qspi_io2_pee4";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	qspi_io3_pee5 {
	nvidia,pins = "qspi_io3_pee5";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	core_pwr_req {
	nvidia,pins = "core_pwr_req";
	nvidia,function = "core";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	cpu_pwr_req {
	nvidia,pins = "cpu_pwr_req";
	nvidia,function = "cpu";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	pwr_int_n {
	nvidia,pins = "pwr_int_n";
	nvidia,function = "pmi";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	clk_32k_in {
	nvidia,pins = "clk_32k_in";
	nvidia,function = "clk";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	jtag_rtck {
	nvidia,pins = "jtag_rtck";
	nvidia,function = "jtag";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	clk_req {
	nvidia,pins = "clk_req";
	nvidia,function = "rsvd1";
	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	shutdown {
	nvidia,pins = "shutdown";
	nvidia,function = "shutdown";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,open-drain = <TEGRA_PIN_DISABLE>;
	};
	};
	};

	serial@70006000 {
	status = "okay";
	};

	i2c@7000c400 {
	status = "okay";
	clock-frequency = <1000000>;

	ec@1e {
	compatible = "google,cros-ec-i2c";
	reg = <0x1e>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(Z, 1) IRQ_TYPE_LEVEL_LOW>;
	wakeup-source;

	ec_i2c_0: i2c-tunnel {
	compatible = "google,cros-ec-i2c-tunnel";
	#address-cells = <1>;
	#size-cells = <0>;

	google,remote-bus = <0>;

	battery: bq27742@55 {
	compatible = "ti,bq27742";
	reg = <0x55>;
	battery-name = "battery";
	};
	};
	};
	};

	i2c@7000d000 {
	status = "okay";
	clock-frequency = <1000000>;

	max77621_cpu: max77621@1b {
	compatible = "maxim,max77621";
	reg = <0x1b>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(Y, 1) IRQ_TYPE_LEVEL_LOW>;
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1231250>;
	regulator-name = "PPVAR_CPU";
	regulator-ramp-delay = <12500>;
	maxim,dvs-default-state = <1>;
	maxim,enable-active-discharge;
	maxim,enable-bias-control;
	maxim,enable-etr;
	maxim,enable-gpio = <&max77620 5 0>;
	maxim,externally-enable;
	};

	max77620: max77620@3c {
	compatible = "maxim,max77620";
	reg = <0x3c>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;

	#interrupt-cells = <2>;
	interrupt-controller;

	gpio-controller;
	#gpio-cells = <2>;

	pinctrl-names = "default";
	pinctrl-0 = <&max77620_default>;

	max77620_default: pinmux@0 {
	pin_gpio {
	pins = "gpio0", "gpio1", "gpio2", "gpio7";
	function = "gpio";
	};

	/*
	* GPIO3 is used to en_pp3300, and it is part of power
	* sequence, So it must be sequenced up (automatically
	* set by OTP) and down properly.
	*/
	pin_gpio3 {
	pins = "gpio3";
	function = "fps-out";
	drive-open-drain = <1>;
	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
	maxim,active-fps-power-up-slot = <4>;
	maxim,active-fps-power-down-slot = <2>;
	};

	pin_gpio5_6 {
	pins = "gpio5", "gpio6";
	function = "gpio";
	drive-push-pull = <1>;
	};

	pin_32k {
	pins = "gpio4";
	function = "32k-out1";
	};
	};

	fps {
	fps0 {
	maxim,shutdown-fps-time-period-us = <5120>;
	maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
	};

	fps1 {
	maxim,shutdown-fps-time-period-us = <5120>;
	maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
	maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>;
	};

	fps2 {
	maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
	};
	};

	regulators {
	in-ldo0-1-supply = <&pp1350>;
	in-ldo2-supply = <&pp3300>;
	in-ldo3-5-supply = <&pp3300>;
	in-ldo7-8-supply = <&pp1350>;

	ppvar_soc: sd0 {
	regulator-name = "PPVAR_SOC";
	regulator-min-microvolt = <825000>;
	regulator-max-microvolt = <1125000>;
	regulator-always-on;
	regulator-boot-on;
	maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
	maxim,active-fps-power-up-slot = <1>;
	maxim,active-fps-power-down-slot = <7>;
	};

	pp1100_sd1: sd1 {
	regulator-name = "PP1100";
	regulator-min-microvolt = <1125000>;
	regulator-max-microvolt = <1125000>;
	regulator-always-on;
	regulator-boot-on;
	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
	maxim,active-fps-power-up-slot = <5>;
	maxim,active-fps-power-down-slot = <1>;
	};

	pp1350: sd2 {
	regulator-name = "PP1350";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
	maxim,active-fps-power-up-slot = <2>;
	maxim,active-fps-power-down-slot = <5>;
	};

	pp1800: sd3 {
	regulator-name = "PP1800";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
	maxim,active-fps-power-up-slot = <3>;
	maxim,active-fps-power-down-slot = <3>;
	};

	pp1200_avdd: ldo0 {
	regulator-name = "PP1200_AVDD";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-enable-ramp-delay = <26>;
	regulator-ramp-delay = <100000>;
	regulator-boot-on;
	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
	maxim,active-fps-power-up-slot = <0>;
	maxim,active-fps-power-down-slot = <7>;
	};

	pp1200_rcam: ldo1 {
	regulator-name = "PP1200_RCAM";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-enable-ramp-delay = <22>;
	regulator-ramp-delay = <100000>;
	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
	maxim,active-fps-power-up-slot = <0>;
	maxim,active-fps-power-down-slot = <7>;
	};

	pp_ldo2: ldo2 {
	regulator-name = "PP_LDO2";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-enable-ramp-delay = <62>;
	regulator-ramp-delay = <11000>;
	regulator-always-on;
	regulator-boot-on;
	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
	maxim,active-fps-power-up-slot = <0>;
	maxim,active-fps-power-down-slot = <7>;
	};

	pp2800l_rcam: ldo3 {
	regulator-name = "PP2800L_RCAM";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-enable-ramp-delay = <50>;
	regulator-ramp-delay = <100000>;
	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
	maxim,active-fps-power-up-slot = <0>;
	maxim,active-fps-power-down-slot = <7>;
	};

	pp100_soc_rtc: ldo4 {
	regulator-name = "PP1100_SOC_RTC";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <850000>;
	regulator-enable-ramp-delay = <22>;
	regulator-ramp-delay = <100000>;
	regulator-always-on; /* Check this */
	regulator-boot-on;
	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
	maxim,active-fps-power-up-slot = <1>;
	maxim,active-fps-power-down-slot = <7>;
	};

	pp2800l_fcam: ldo5 {
	regulator-name = "PP2800L_FCAM";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	regulator-enable-ramp-delay = <62>;
	regulator-ramp-delay = <100000>;
	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
	maxim,active-fps-power-up-slot = <0>;
	maxim,active-fps-power-down-slot = <7>;
	};

	ldo6 {
	/* Unused. */
	regulator-name = "PP_LDO6";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-enable-ramp-delay = <36>;
	regulator-ramp-delay = <100000>;
	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
	maxim,active-fps-power-up-slot = <0>;
	maxim,active-fps-power-down-slot = <7>;
	};

	pp1050_avdd: ldo7 {
	regulator-name = "PP1050_AVDD";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	regulator-enable-ramp-delay = <24>;
	regulator-ramp-delay = <100000>;
	regulator-always-on;
	regulator-boot-on;
	maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
	maxim,active-fps-power-up-slot = <3>;
	maxim,active-fps-power-down-slot = <4>;
	};

	avddio_1v05: ldo8 {
	regulator-name = "AVDDIO_1V05";
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;
	regulator-enable-ramp-delay = <22>;
	regulator-ramp-delay = <100000>;
	regulator-boot-on;
	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
	maxim,active-fps-power-up-slot = <0>;
	maxim,active-fps-power-down-slot = <7>;
	};
	};
	};
	};

	i2c@7000d100 {
	status = "okay";
	clock-frequency = <400000>;

	nau8825@1a {
	compatible = "nuvoton,nau8825";
	reg = <0x1a>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(E, 6) IRQ_TYPE_LEVEL_LOW>;
	- clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>;
	+ clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_2>;
	clock-names = "mclk";

	nuvoton,jkdet-enable;
	nuvoton,jkdet-polarity = <GPIO_ACTIVE_LOW>;
	nuvoton,vref-impedance = <2>;
	nuvoton,micbias-voltage = <6>;
	nuvoton,sar-threshold-num = <4>;
	nuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>;
	nuvoton,sar-hysteresis = <1>;
	nuvoton,sar-voltage = <0>;
	nuvoton,sar-compare-time = <0>;
	nuvoton,sar-sampling-time = <0>;
	nuvoton,short-key-debounce = <2>;
	nuvoton,jack-insert-debounce = <7>;
	nuvoton,jack-eject-debounce = <7>;
	status = "okay";
	};

	audio-codec@2d {
	compatible = "realtek,rt5677";
	reg = <0x2d>;
	interrupt-parent = <&gpio>;
	interrupts = <TEGRA_GPIO(X, 0) IRQ_TYPE_LEVEL_HIGH>;
	realtek,reset-gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_LOW>;
	gpio-controller;
	#gpio-cells = <2>;
	status = "okay";
	};
	};

	pmc@7000e400 {
	nvidia,invert-interrupt;
	nvidia,suspend-mode = <0>;
	nvidia,cpu-pwr-good-time = <0>;
	nvidia,cpu-pwr-off-time = <0>;
	nvidia,core-pwr-good-time = <12000 6000>;
	nvidia,core-pwr-off-time = <39053>;
	nvidia,core-power-req-active-high;
	nvidia,sys-clock-req-active-high;
	status = "okay";
	};

	usb@70090000 {
	phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
	<&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
	phy-names = "usb2-0", "usb3-0";

	dvddio-pex-supply = <&avddio_1v05>;
	hvddio-pex-supply = <&pp1800>;
	avdd-usb-supply = <&pp3300>;
	avdd-pll-utmip-supply = <&pp1800>;
	avdd-pll-uerefe-supply = <&pp1050_avdd>;
	dvdd-pex-pll-supply = <&avddio_1v05>;
	hvdd-pex-pll-e-supply = <&pp1800>;

	status = "okay";
	};

	padctl@7009f000 {
	status = "okay";

	avdd-pll-utmip-supply = <&pp1800>;
	avdd-pll-uerefe-supply = <&pp1050_avdd>;
	dvdd-pex-pll-supply = <&avddio_1v05>;
	hvdd-pex-pll-e-supply = <&pp1800>;

	pads {
	usb2 {
	status = "okay";

	lanes {
	usb2-0 {
	nvidia,function = "xusb";
	status = "okay";
	};
	};
	};

	pcie {
	status = "okay";

	lanes {
	pcie-6 {
	nvidia,function = "usb3-ss";
	status = "okay";
	};
	};
	};
	};

	ports {
	usb2-0 {
	status = "okay";
	vbus-supply = <&usbc_vbus>;
	mode = "otg";
	};

	usb3-0 {
	nvidia,usb2-companion = <0>;
	status = "okay";
	};
	};
	};

	sdhci@700b0600 {
	bus-width = <8>;
	non-removable;
	status = "okay";
	};

	clock@70110000 {
	status = "okay";
	nvidia,cf = <6>;
	nvidia,ci = <0>;
	nvidia,cg = <2>;
	nvidia,droop-ctrl = <0x00000f00>;
	nvidia,force-mode = <1>;
	nvidia,i2c-fs-rate = <400000>;
	nvidia,sample-rate = <12500>;
	vdd-cpu-supply = <&max77621_cpu>;
	};

	aconnect@702c0000 {
	status = "okay";

	dma@702e2000 {
	status = "okay";
	};

	agic@702f9000 {
	status = "okay";
	};
	};

	clocks {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <0>;

	clk32k_in: clock@0 {
	compatible = "fixed-clock";
	reg = <0>;
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	};

	cpus {
	cpu@0 {
	enable-method = "psci";
	};

	cpu@1 {
	enable-method = "psci";
	};

	cpu@2 {
	enable-method = "psci";
	};

	cpu@3 {
	enable-method = "psci";
	};

	idle-states {
	cpu-sleep {
	arm,psci-suspend-param = <0x00010007>;
	status = "okay";
	};
	};
	};

	gpio-keys {
	compatible = "gpio-keys";

	power {
	label = "Power";
	gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
	linux,code = <KEY_POWER>;
	debounce-interval = <30>;
	wakeup-source;
	};

	lid {
	label = "Lid";
	gpios = <&gpio TEGRA_GPIO(B, 4) GPIO_ACTIVE_LOW>;
	linux,input-type = <EV_SW>;
	linux,code = <SW_LID>;
	wakeup-source;
	};

	tablet_mode {
	label = "Tablet Mode";
	gpios = <&gpio TEGRA_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
	linux,input-type = <EV_SW>;
	linux,code = <SW_TABLET_MODE>;
	wakeup-source;
	};

	volume_down {
	label = "Volume Down";
	gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
	linux,code = <KEY_VOLUMEDOWN>;
	};

	volume_up {
	label = "Volume Up";
	gpios = <&gpio TEGRA_GPIO(M, 4) GPIO_ACTIVE_LOW>;
	linux,code = <KEY_VOLUMEUP>;
	};
	};

	max98357a {
	compatible = "maxim,max98357a";
	status = "okay";
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	regulators {
	compatible = "simple-bus";
	device_type = "fixed-regulators";
	#address-cells = <1>;
	#size-cells = <0>;

	ppvar_sys: regulator@0 {
	compatible = "regulator-fixed";
	reg = <0>;
	regulator-name = "PPVAR_SYS";
	regulator-min-microvolt = <4400000>;
	regulator-max-microvolt = <4400000>;
	regulator-always-on;
	};

	pplcd_vdd: regulator@1 {
	compatible = "regulator-fixed";
	reg = <1>;
	regulator-name = "PPLCD_VDD";
	regulator-min-microvolt = <4400000>;
	regulator-max-microvolt = <4400000>;
	gpio = <&gpio TEGRA_GPIO(V, 4) 0>;
	enable-active-high;
	regulator-boot-on;
	};

	pp3000_always: regulator@2 {
	compatible = "regulator-fixed";
	reg = <2>;
	regulator-name = "PP3000_ALWAYS";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;
	};

	pp3300: regulator@3 {
	compatible = "regulator-fixed";
	reg = <3>;
	regulator-name = "PP3300";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	enable-active-high;
	};

	pp5000: regulator@4 {
	compatible = "regulator-fixed";
	reg = <4>;
	regulator-name = "PP5000";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	};

	pp1800_lcdio: regulator@5 {
	compatible = "regulator-fixed";
	reg = <5>;
	regulator-name = "PP1800_LCDIO";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	gpio = <&gpio TEGRA_GPIO(V, 3) 0>;
	enable-active-high;
	regulator-boot-on;
	};

	pp1800_cam: regulator@6 {
	compatible = "regulator-fixed";
	reg= <6>;
	regulator-name = "PP1800_CAM";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	gpio = <&gpio TEGRA_GPIO(K, 3) 0>;
	enable-active-high;
	};

	usbc_vbus: regulator@7 {
	compatible = "regulator-fixed";
	reg = <7>;
	regulator-name = "USBC_VBUS";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/nvidia/tegra210.dtsi b/sys/gnu/dts/arm64/nvidia/tegra210.dtsi
	index 48c63256ba7f..64c46ce3849d 100644
	--- a/sys/gnu/dts/arm64/nvidia/tegra210.dtsi
	+++ b/sys/gnu/dts/arm64/nvidia/tegra210.dtsi
	@@ -1,1599 +1,1620 @@
	// SPDX-License-Identifier: GPL-2.0
	#include <dt-bindings/clock/tegra210-car.h>
	#include <dt-bindings/gpio/tegra-gpio.h>
	#include <dt-bindings/memory/tegra210-mc.h>
	#include <dt-bindings/pinctrl/pinctrl-tegra.h>
	#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
	#include <dt-bindings/reset/tegra210-car.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/thermal/tegra124-soctherm.h>
	+#include <dt-bindings/soc/tegra-pmc.h>

	/ {
	compatible = "nvidia,tegra210";
	interrupt-parent = <&lic>;
	#address-cells = <2>;
	#size-cells = <2>;

	pcie@1003000 {
	compatible = "nvidia,tegra210-pcie";
	device_type = "pci";
	reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
	0x0 0x01003800 0x0 0x00000800 /* AFI registers */
	0x0 0x02000000 0x0 0x10000000>; /* configuration space */
	reg-names = "pads", "afi", "cs";
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
	<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
	interrupt-names = "intr", "msi";

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

	bus-range = <0x00 0xff>;
	#address-cells = <3>;
	#size-cells = <2>;

	ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
	0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
	0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
	0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
	0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */

	clocks = <&tegra_car TEGRA210_CLK_PCIE>,
	<&tegra_car TEGRA210_CLK_AFI>,
	<&tegra_car TEGRA210_CLK_PLL_E>,
	<&tegra_car TEGRA210_CLK_CML0>;
	clock-names = "pex", "afi", "pll_e", "cml";
	resets = <&tegra_car 70>,
	<&tegra_car 72>,
	<&tegra_car 74>;
	reset-names = "pex", "afi", "pcie_x";

	pinctrl-names = "default", "idle";
	pinctrl-0 = <&pex_dpd_disable>;
	pinctrl-1 = <&pex_dpd_enable>;

	status = "disabled";

	pci@1,0 {
	device_type = "pci";
	assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
	reg = <0x000800 0 0 0 0>;
	bus-range = <0x00 0xff>;
	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	ranges;

	nvidia,num-lanes = <4>;
	};

	pci@2,0 {
	device_type = "pci";
	assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
	reg = <0x001000 0 0 0 0>;
	bus-range = <0x00 0xff>;
	status = "disabled";

	#address-cells = <3>;
	#size-cells = <2>;
	ranges;

	nvidia,num-lanes = <1>;
	};
	};

	host1x@50000000 {
	compatible = "nvidia,tegra210-host1x", "simple-bus";
	reg = <0x0 0x50000000 0x0 0x00034000>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
	clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
	clock-names = "host1x";
	resets = <&tegra_car 28>;
	reset-names = "host1x";

	#address-cells = <2>;
	#size-cells = <2>;

	ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;

	iommus = <&mc TEGRA_SWGROUP_HC>;

	dpaux1: dpaux@54040000 {
	compatible = "nvidia,tegra210-dpaux";
	reg = <0x0 0x54040000 0x0 0x00040000>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
	<&tegra_car TEGRA210_CLK_PLL_DP>;
	clock-names = "dpaux", "parent";
	resets = <&tegra_car 207>;
	reset-names = "dpaux";
	power-domains = <&pd_sor>;
	status = "disabled";

	state_dpaux1_aux: pinmux-aux {
	groups = "dpaux-io";
	function = "aux";
	};

	state_dpaux1_i2c: pinmux-i2c {
	groups = "dpaux-io";
	function = "i2c";
	};

	state_dpaux1_off: pinmux-off {
	groups = "dpaux-io";
	function = "off";
	};

	i2c-bus {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	vi@54080000 {
	compatible = "nvidia,tegra210-vi";
	reg = <0x0 0x54080000 0x0 0x00040000>;
	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	tsec@54100000 {
	compatible = "nvidia,tegra210-tsec";
	reg = <0x0 0x54100000 0x0 0x00040000>;
	};

	dc@54200000 {
	compatible = "nvidia,tegra210-dc";
	reg = <0x0 0x54200000 0x0 0x00040000>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_DISP1>,
	<&tegra_car TEGRA210_CLK_PLL_P>;
	clock-names = "dc", "parent";
	resets = <&tegra_car 27>;
	reset-names = "dc";

	iommus = <&mc TEGRA_SWGROUP_DC>;

	nvidia,head = <0>;
	};

	dc@54240000 {
	compatible = "nvidia,tegra210-dc";
	reg = <0x0 0x54240000 0x0 0x00040000>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_DISP2>,
	<&tegra_car TEGRA210_CLK_PLL_P>;
	clock-names = "dc", "parent";
	resets = <&tegra_car 26>;
	reset-names = "dc";

	iommus = <&mc TEGRA_SWGROUP_DCB>;

	nvidia,head = <1>;
	};

	dsi@54300000 {
	compatible = "nvidia,tegra210-dsi";
	reg = <0x0 0x54300000 0x0 0x00040000>;
	clocks = <&tegra_car TEGRA210_CLK_DSIA>,
	<&tegra_car TEGRA210_CLK_DSIALP>,
	<&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
	clock-names = "dsi", "lp", "parent";
	resets = <&tegra_car 48>;
	reset-names = "dsi";
	power-domains = <&pd_sor>;
	nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */

	status = "disabled";

	#address-cells = <1>;
	#size-cells = <0>;
	};

	vic@54340000 {
	compatible = "nvidia,tegra210-vic";
	reg = <0x0 0x54340000 0x0 0x00040000>;
	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_VIC03>;
	clock-names = "vic";
	resets = <&tegra_car 178>;
	reset-names = "vic";

	iommus = <&mc TEGRA_SWGROUP_VIC>;
	power-domains = <&pd_vic>;
	};

	nvjpg@54380000 {
	compatible = "nvidia,tegra210-nvjpg";
	reg = <0x0 0x54380000 0x0 0x00040000>;
	status = "disabled";
	};

	dsi@54400000 {
	compatible = "nvidia,tegra210-dsi";
	reg = <0x0 0x54400000 0x0 0x00040000>;
	clocks = <&tegra_car TEGRA210_CLK_DSIB>,
	<&tegra_car TEGRA210_CLK_DSIBLP>,
	<&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
	clock-names = "dsi", "lp", "parent";
	resets = <&tegra_car 82>;
	reset-names = "dsi";
	power-domains = <&pd_sor>;
	nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */

	status = "disabled";

	#address-cells = <1>;
	#size-cells = <0>;
	};

	nvdec@54480000 {
	compatible = "nvidia,tegra210-nvdec";
	reg = <0x0 0x54480000 0x0 0x00040000>;
	status = "disabled";
	};

	nvenc@544c0000 {
	compatible = "nvidia,tegra210-nvenc";
	reg = <0x0 0x544c0000 0x0 0x00040000>;
	status = "disabled";
	};

	tsec@54500000 {
	compatible = "nvidia,tegra210-tsec";
	reg = <0x0 0x54500000 0x0 0x00040000>;
	status = "disabled";
	};

	sor@54540000 {
	compatible = "nvidia,tegra210-sor";
	reg = <0x0 0x54540000 0x0 0x00040000>;
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_SOR0>,
	<&tegra_car TEGRA210_CLK_SOR0_OUT>,
	<&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
	<&tegra_car TEGRA210_CLK_PLL_DP>,
	<&tegra_car TEGRA210_CLK_SOR_SAFE>;
	clock-names = "sor", "out", "parent", "dp", "safe";
	resets = <&tegra_car 182>;
	reset-names = "sor";
	pinctrl-0 = <&state_dpaux_aux>;
	pinctrl-1 = <&state_dpaux_i2c>;
	pinctrl-2 = <&state_dpaux_off>;
	pinctrl-names = "aux", "i2c", "off";
	power-domains = <&pd_sor>;
	status = "disabled";
	};

	sor@54580000 {
	compatible = "nvidia,tegra210-sor1";
	reg = <0x0 0x54580000 0x0 0x00040000>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_SOR1>,
	<&tegra_car TEGRA210_CLK_SOR1_OUT>,
	<&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
	<&tegra_car TEGRA210_CLK_PLL_DP>,
	<&tegra_car TEGRA210_CLK_SOR_SAFE>;
	clock-names = "sor", "out", "parent", "dp", "safe";
	resets = <&tegra_car 183>;
	reset-names = "sor";
	pinctrl-0 = <&state_dpaux1_aux>;
	pinctrl-1 = <&state_dpaux1_i2c>;
	pinctrl-2 = <&state_dpaux1_off>;
	pinctrl-names = "aux", "i2c", "off";
	power-domains = <&pd_sor>;
	status = "disabled";
	};

	dpaux: dpaux@545c0000 {
	compatible = "nvidia,tegra124-dpaux";
	reg = <0x0 0x545c0000 0x0 0x00040000>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
	<&tegra_car TEGRA210_CLK_PLL_DP>;
	clock-names = "dpaux", "parent";
	resets = <&tegra_car 181>;
	reset-names = "dpaux";
	power-domains = <&pd_sor>;
	status = "disabled";

	state_dpaux_aux: pinmux-aux {
	groups = "dpaux-io";
	function = "aux";
	};

	state_dpaux_i2c: pinmux-i2c {
	groups = "dpaux-io";
	function = "i2c";
	};

	state_dpaux_off: pinmux-off {
	groups = "dpaux-io";
	function = "off";
	};

	i2c-bus {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	isp@54600000 {
	compatible = "nvidia,tegra210-isp";
	reg = <0x0 0x54600000 0x0 0x00040000>;
	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	isp@54680000 {
	compatible = "nvidia,tegra210-isp";
	reg = <0x0 0x54680000 0x0 0x00040000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c@546c0000 {
	compatible = "nvidia,tegra210-i2c-vi";
	reg = <0x0 0x546c0000 0x0 0x00040000>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	gic: interrupt-controller@50041000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x0 0x50041000 0x0 0x1000>,
	<0x0 0x50042000 0x0 0x2000>,
	<0x0 0x50044000 0x0 0x2000>,
	<0x0 0x50046000 0x0 0x2000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	interrupt-parent = <&gic>;
	};

	gpu@57000000 {
	compatible = "nvidia,gm20b";
	reg = <0x0 0x57000000 0x0 0x01000000>,
	<0x0 0x58000000 0x0 0x01000000>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "stall", "nonstall";
	clocks = <&tegra_car TEGRA210_CLK_GPU>,
	<&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
	<&tegra_car TEGRA210_CLK_PLL_G_REF>;
	clock-names = "gpu", "pwr", "ref";
	resets = <&tegra_car 184>;
	reset-names = "gpu";

	iommus = <&mc TEGRA_SWGROUP_GPU>;

	status = "disabled";
	};

	lic: interrupt-controller@60004000 {
	compatible = "nvidia,tegra210-ictlr";
	reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
	<0x0 0x60004100 0x0 0x40>, /* secondary controller */
	<0x0 0x60004200 0x0 0x40>, /* tertiary controller */
	<0x0 0x60004300 0x0 0x40>, /* quaternary controller */
	<0x0 0x60004400 0x0 0x40>, /* quinary controller */
	<0x0 0x60004500 0x0 0x40>; /* senary controller */
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	};

	timer@60005000 {
	compatible = "nvidia,tegra210-timer";
	reg = <0x0 0x60005000 0x0 0x400>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_TIMER>;
	clock-names = "timer";
	};

	tegra_car: clock@60006000 {
	compatible = "nvidia,tegra210-car";
	reg = <0x0 0x60006000 0x0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	flow-controller@60007000 {
	compatible = "nvidia,tegra210-flowctrl";
	reg = <0x0 0x60007000 0x0 0x1000>;
	};

	gpio: gpio@6000d000 {
	compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
	reg = <0x0 0x6000d000 0x0 0x1000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	#interrupt-cells = <2>;
	interrupt-controller;
	};

	apbdma: dma@60020000 {
	compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
	reg = <0x0 0x60020000 0x0 0x1400>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
	clock-names = "dma";
	resets = <&tegra_car 34>;
	reset-names = "dma";
	#dma-cells = <1>;
	};

	apbmisc@70000800 {
	compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
	reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
	<0x0 0x70000008 0x0 0x04>; /* Strapping options */
	};

	pinmux: pinmux@700008d4 {
	compatible = "nvidia,tegra210-pinmux";
	reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
	<0x0 0x70003000 0x0 0x294>; /* Mux registers */
	sdmmc1_3v3_drv: sdmmc1-3v3-drv {
	sdmmc1 {
	nvidia,pins = "drive_sdmmc1";
	nvidia,pull-down-strength = <0x8>;
	nvidia,pull-up-strength = <0x8>;
	};
	};
	sdmmc1_1v8_drv: sdmmc1-1v8-drv {
	sdmmc1 {
	nvidia,pins = "drive_sdmmc1";
	nvidia,pull-down-strength = <0x4>;
	nvidia,pull-up-strength = <0x3>;
	};
	};
	sdmmc2_1v8_drv: sdmmc2-1v8-drv {
	sdmmc2 {
	nvidia,pins = "drive_sdmmc2";
	nvidia,pull-down-strength = <0x10>;
	nvidia,pull-up-strength = <0x10>;
	};
	};
	sdmmc3_3v3_drv: sdmmc3-3v3-drv {
	sdmmc3 {
	nvidia,pins = "drive_sdmmc3";
	nvidia,pull-down-strength = <0x8>;
	nvidia,pull-up-strength = <0x8>;
	};
	};
	sdmmc3_1v8_drv: sdmmc3-1v8-drv {
	sdmmc3 {
	nvidia,pins = "drive_sdmmc3";
	nvidia,pull-down-strength = <0x4>;
	nvidia,pull-up-strength = <0x3>;
	};
	};
	sdmmc4_1v8_drv: sdmmc4-1v8-drv {
	sdmmc4 {
	nvidia,pins = "drive_sdmmc4";
	nvidia,pull-down-strength = <0x10>;
	nvidia,pull-up-strength = <0x10>;
	};
	};
	};

	/*
	* There are two serial driver i.e. 8250 based simple serial
	* driver and APB DMA based serial driver for higher baudrate
	* and performance. To enable the 8250 based driver, the compatible
	* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
	* the APB DMA based serial driver, the compatible is
	* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
	*/
	uarta: serial@70006000 {
	compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x70006000 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_UARTA>;
	clock-names = "serial";
	resets = <&tegra_car 6>;
	reset-names = "serial";
	dmas = <&apbdma 8>, <&apbdma 8>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartb: serial@70006040 {
	compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x70006040 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_UARTB>;
	clock-names = "serial";
	resets = <&tegra_car 7>;
	reset-names = "serial";
	dmas = <&apbdma 9>, <&apbdma 9>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartc: serial@70006200 {
	compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x70006200 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_UARTC>;
	clock-names = "serial";
	resets = <&tegra_car 55>;
	reset-names = "serial";
	dmas = <&apbdma 10>, <&apbdma 10>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	uartd: serial@70006300 {
	compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
	reg = <0x0 0x70006300 0x0 0x40>;
	reg-shift = <2>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_UARTD>;
	clock-names = "serial";
	resets = <&tegra_car 65>;
	reset-names = "serial";
	dmas = <&apbdma 19>, <&apbdma 19>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	pwm: pwm@7000a000 {
	compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
	reg = <0x0 0x7000a000 0x0 0x100>;
	#pwm-cells = <2>;
	clocks = <&tegra_car TEGRA210_CLK_PWM>;
	clock-names = "pwm";
	resets = <&tegra_car 17>;
	reset-names = "pwm";
	status = "disabled";
	};

	i2c@7000c000 {
	compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
	reg = <0x0 0x7000c000 0x0 0x100>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA210_CLK_I2C1>;
	clock-names = "div-clk";
	resets = <&tegra_car 12>;
	reset-names = "i2c";
	dmas = <&apbdma 21>, <&apbdma 21>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000c400 {
	compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
	reg = <0x0 0x7000c400 0x0 0x100>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA210_CLK_I2C2>;
	clock-names = "div-clk";
	resets = <&tegra_car 54>;
	reset-names = "i2c";
	dmas = <&apbdma 22>, <&apbdma 22>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000c500 {
	compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
	reg = <0x0 0x7000c500 0x0 0x100>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA210_CLK_I2C3>;
	clock-names = "div-clk";
	resets = <&tegra_car 67>;
	reset-names = "i2c";
	dmas = <&apbdma 23>, <&apbdma 23>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000c700 {
	compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
	reg = <0x0 0x7000c700 0x0 0x100>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA210_CLK_I2C4>;
	clock-names = "div-clk";
	resets = <&tegra_car 103>;
	reset-names = "i2c";
	dmas = <&apbdma 26>, <&apbdma 26>;
	dma-names = "rx", "tx";
	pinctrl-0 = <&state_dpaux1_i2c>;
	pinctrl-1 = <&state_dpaux1_off>;
	pinctrl-names = "default", "idle";
	status = "disabled";
	};

	i2c@7000d000 {
	compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
	reg = <0x0 0x7000d000 0x0 0x100>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA210_CLK_I2C5>;
	clock-names = "div-clk";
	resets = <&tegra_car 47>;
	reset-names = "i2c";
	dmas = <&apbdma 24>, <&apbdma 24>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	i2c@7000d100 {
	compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
	reg = <0x0 0x7000d100 0x0 0x100>;
	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA210_CLK_I2C6>;
	clock-names = "div-clk";
	resets = <&tegra_car 166>;
	reset-names = "i2c";
	dmas = <&apbdma 30>, <&apbdma 30>;
	dma-names = "rx", "tx";
	pinctrl-0 = <&state_dpaux_i2c>;
	pinctrl-1 = <&state_dpaux_off>;
	pinctrl-names = "default", "idle";
	status = "disabled";
	};

	spi@7000d400 {
	compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
	reg = <0x0 0x7000d400 0x0 0x200>;
	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA210_CLK_SBC1>;
	clock-names = "spi";
	resets = <&tegra_car 41>;
	reset-names = "spi";
	dmas = <&apbdma 15>, <&apbdma 15>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000d600 {
	compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
	reg = <0x0 0x7000d600 0x0 0x200>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA210_CLK_SBC2>;
	clock-names = "spi";
	resets = <&tegra_car 44>;
	reset-names = "spi";
	dmas = <&apbdma 16>, <&apbdma 16>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000d800 {
	compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
	reg = <0x0 0x7000d800 0x0 0x200>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA210_CLK_SBC3>;
	clock-names = "spi";
	resets = <&tegra_car 46>;
	reset-names = "spi";
	dmas = <&apbdma 17>, <&apbdma 17>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	spi@7000da00 {
	compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
	reg = <0x0 0x7000da00 0x0 0x200>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA210_CLK_SBC4>;
	clock-names = "spi";
	resets = <&tegra_car 68>;
	reset-names = "spi";
	dmas = <&apbdma 18>, <&apbdma 18>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	rtc@7000e000 {
	compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
	reg = <0x0 0x7000e000 0x0 0x100>;
	interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
	- interrupt-parent = <&pmc>;
	+ interrupt-parent = <&tegra_pmc>;
	clocks = <&tegra_car TEGRA210_CLK_RTC>;
	clock-names = "rtc";
	};

	- pmc: pmc@7000e400 {
	+ tegra_pmc: pmc@7000e400 {
	compatible = "nvidia,tegra210-pmc";
	reg = <0x0 0x7000e400 0x0 0x400>;
	clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
	clock-names = "pclk", "clk32k_in";
	+ #clock-cells = <1>;
	#interrupt-cells = <2>;
	interrupt-controller;

	powergates {
	pd_audio: aud {
	clocks = <&tegra_car TEGRA210_CLK_APE>,
	<&tegra_car TEGRA210_CLK_APB2APE>;
	resets = <&tegra_car 198>;
	#power-domain-cells = <0>;
	};

	pd_sor: sor {
	clocks = <&tegra_car TEGRA210_CLK_SOR0>,
	<&tegra_car TEGRA210_CLK_SOR1>,
	<&tegra_car TEGRA210_CLK_CSI>,
	<&tegra_car TEGRA210_CLK_DSIA>,
	<&tegra_car TEGRA210_CLK_DSIB>,
	<&tegra_car TEGRA210_CLK_DPAUX>,
	<&tegra_car TEGRA210_CLK_DPAUX1>,
	<&tegra_car TEGRA210_CLK_MIPI_CAL>;
	resets = <&tegra_car TEGRA210_CLK_SOR0>,
	<&tegra_car TEGRA210_CLK_SOR1>,
	<&tegra_car TEGRA210_CLK_CSI>,
	<&tegra_car TEGRA210_CLK_DSIA>,
	<&tegra_car TEGRA210_CLK_DSIB>,
	<&tegra_car TEGRA210_CLK_DPAUX>,
	<&tegra_car TEGRA210_CLK_DPAUX1>,
	<&tegra_car TEGRA210_CLK_MIPI_CAL>;
	#power-domain-cells = <0>;
	};

	pd_xusbss: xusba {
	clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
	resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
	#power-domain-cells = <0>;
	};

	pd_xusbdev: xusbb {
	clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
	resets = <&tegra_car 95>;
	#power-domain-cells = <0>;
	};

	pd_xusbhost: xusbc {
	clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
	resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
	#power-domain-cells = <0>;
	};

	pd_vic: vic {
	clocks = <&tegra_car TEGRA210_CLK_VIC03>;
	clock-names = "vic";
	resets = <&tegra_car 178>;
	reset-names = "vic";
	#power-domain-cells = <0>;
	};
	};

	sdmmc1_3v3: sdmmc1-3v3 {
	pins = "sdmmc1";
	power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
	};

	sdmmc1_1v8: sdmmc1-1v8 {
	pins = "sdmmc1";
	power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
	};

	sdmmc3_3v3: sdmmc3-3v3 {
	pins = "sdmmc3";
	power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
	};

	sdmmc3_1v8: sdmmc3-1v8 {
	pins = "sdmmc3";
	power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
	};

	pex_dpd_disable: pex_en {
	pex-dpd-disable {
	pins = "pex-bias", "pex-clk1", "pex-clk2";
	low-power-disable;
	};
	};

	pex_dpd_enable: pex_dis {
	pex-dpd-enable {
	pins = "pex-bias", "pex-clk1", "pex-clk2";
	low-power-enable;
	};
	};
	};

	fuse@7000f800 {
	compatible = "nvidia,tegra210-efuse";
	reg = <0x0 0x7000f800 0x0 0x400>;
	clocks = <&tegra_car TEGRA210_CLK_FUSE>;
	clock-names = "fuse";
	resets = <&tegra_car 39>;
	reset-names = "fuse";
	};

	mc: memory-controller@70019000 {
	compatible = "nvidia,tegra210-mc";
	reg = <0x0 0x70019000 0x0 0x1000>;
	clocks = <&tegra_car TEGRA210_CLK_MC>;
	clock-names = "mc";

	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;

	#iommu-cells = <1>;
	};

	sata@70020000 {
	compatible = "nvidia,tegra210-ahci";
	reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
	<0x0 0x70020000 0x0 0x7000>, /* SATA */
	<0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_SATA>,
	<&tegra_car TEGRA210_CLK_SATA_OOB>;
	clock-names = "sata", "sata-oob";
	resets = <&tegra_car 124>,
	<&tegra_car 123>,
	<&tegra_car 129>;
	reset-names = "sata", "sata-oob", "sata-cold";
	status = "disabled";
	};

	hda@70030000 {
	compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
	reg = <0x0 0x70030000 0x0 0x10000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_HDA>,
	<&tegra_car TEGRA210_CLK_HDA2HDMI>,
	<&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
	clock-names = "hda", "hda2hdmi", "hda2codec_2x";
	resets = <&tegra_car 125>, /* hda */
	<&tegra_car 128>, /* hda2hdmi */
	<&tegra_car 111>; /* hda2codec_2x */
	reset-names = "hda", "hda2hdmi", "hda2codec_2x";
	status = "disabled";
	};

	usb@70090000 {
	compatible = "nvidia,tegra210-xusb";
	reg = <0x0 0x70090000 0x0 0x8000>,
	<0x0 0x70098000 0x0 0x1000>,
	<0x0 0x70099000 0x0 0x1000>;
	reg-names = "hcd", "fpci", "ipfs";

	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
	<&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
	<&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
	<&tegra_car TEGRA210_CLK_XUSB_SS>,
	<&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
	<&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
	<&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
	<&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
	<&tegra_car TEGRA210_CLK_PLL_U_480M>,
	<&tegra_car TEGRA210_CLK_CLK_M>,
	<&tegra_car TEGRA210_CLK_PLL_E>;
	clock-names = "xusb_host", "xusb_host_src",
	"xusb_falcon_src", "xusb_ss",
	"xusb_ss_div2", "xusb_ss_src",
	"xusb_hs_src", "xusb_fs_src",
	"pll_u_480m", "clk_m", "pll_e";
	resets = <&tegra_car 89>, <&tegra_car 156>,
	<&tegra_car 143>;
	reset-names = "xusb_host", "xusb_ss", "xusb_src";
	power-domains = <&pd_xusbhost>, <&pd_xusbss>;
	power-domain-names = "xusb_host", "xusb_ss";

	nvidia,xusb-padctl = <&padctl>;

	status = "disabled";
	};

	padctl: padctl@7009f000 {
	compatible = "nvidia,tegra210-xusb-padctl";
	reg = <0x0 0x7009f000 0x0 0x1000>;
	resets = <&tegra_car 142>;
	reset-names = "padctl";

	status = "disabled";

	pads {
	usb2 {
	clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
	clock-names = "trk";
	status = "disabled";

	lanes {
	usb2-0 {
	status = "disabled";
	#phy-cells = <0>;
	};

	usb2-1 {
	status = "disabled";
	#phy-cells = <0>;
	};

	usb2-2 {
	status = "disabled";
	#phy-cells = <0>;
	};

	usb2-3 {
	status = "disabled";
	#phy-cells = <0>;
	};
	};
	};

	hsic {
	clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
	clock-names = "trk";
	status = "disabled";

	lanes {
	hsic-0 {
	status = "disabled";
	#phy-cells = <0>;
	};

	hsic-1 {
	status = "disabled";
	#phy-cells = <0>;
	};
	};
	};

	pcie {
	clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
	clock-names = "pll";
	resets = <&tegra_car 205>;
	reset-names = "phy";
	status = "disabled";

	lanes {
	pcie-0 {
	status = "disabled";
	#phy-cells = <0>;
	};

	pcie-1 {
	status = "disabled";
	#phy-cells = <0>;
	};

	pcie-2 {
	status = "disabled";
	#phy-cells = <0>;
	};

	pcie-3 {
	status = "disabled";
	#phy-cells = <0>;
	};

	pcie-4 {
	status = "disabled";
	#phy-cells = <0>;
	};

	pcie-5 {
	status = "disabled";
	#phy-cells = <0>;
	};

	pcie-6 {
	status = "disabled";
	#phy-cells = <0>;
	};
	};
	};

	sata {
	clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
	clock-names = "pll";
	resets = <&tegra_car 204>;
	reset-names = "phy";
	status = "disabled";

	lanes {
	sata-0 {
	status = "disabled";
	#phy-cells = <0>;
	};
	};
	};
	};

	ports {
	usb2-0 {
	status = "disabled";
	};

	usb2-1 {
	status = "disabled";
	};

	usb2-2 {
	status = "disabled";
	};

	usb2-3 {
	status = "disabled";
	};

	hsic-0 {
	status = "disabled";
	};

	usb3-0 {
	status = "disabled";
	};

	usb3-1 {
	status = "disabled";
	};

	usb3-2 {
	status = "disabled";
	};

	usb3-3 {
	status = "disabled";
	};
	};
	};

	sdhci@700b0000 {
	compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
	reg = <0x0 0x700b0000 0x0 0x200>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
	clock-names = "sdhci";
	resets = <&tegra_car 14>;
	reset-names = "sdhci";
	pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
	"sdmmc-3v3-drv", "sdmmc-1v8-drv";
	pinctrl-0 = <&sdmmc1_3v3>;
	pinctrl-1 = <&sdmmc1_1v8>;
	pinctrl-2 = <&sdmmc1_3v3_drv>;
	pinctrl-3 = <&sdmmc1_1v8_drv>;
	nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
	nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
	nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
	nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
	nvidia,default-tap = <0x2>;
	nvidia,default-trim = <0x4>;
	assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
	<&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
	<&tegra_car TEGRA210_CLK_PLL_C4>;
	assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
	assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
	status = "disabled";
	};

	sdhci@700b0200 {
	compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
	reg = <0x0 0x700b0200 0x0 0x200>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
	clock-names = "sdhci";
	resets = <&tegra_car 9>;
	reset-names = "sdhci";
	pinctrl-names = "sdmmc-1v8-drv";
	pinctrl-0 = <&sdmmc2_1v8_drv>;
	nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
	nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
	nvidia,default-tap = <0x8>;
	nvidia,default-trim = <0x0>;
	status = "disabled";
	};

	sdhci@700b0400 {
	compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
	reg = <0x0 0x700b0400 0x0 0x200>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
	clock-names = "sdhci";
	resets = <&tegra_car 69>;
	reset-names = "sdhci";
	pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
	"sdmmc-3v3-drv", "sdmmc-1v8-drv";
	pinctrl-0 = <&sdmmc3_3v3>;
	pinctrl-1 = <&sdmmc3_1v8>;
	pinctrl-2 = <&sdmmc3_3v3_drv>;
	pinctrl-3 = <&sdmmc3_1v8_drv>;
	nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
	nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
	nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
	nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
	nvidia,default-tap = <0x3>;
	nvidia,default-trim = <0x3>;
	status = "disabled";
	};

	sdhci@700b0600 {
	compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
	reg = <0x0 0x700b0600 0x0 0x200>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
	clock-names = "sdhci";
	resets = <&tegra_car 15>;
	reset-names = "sdhci";
	pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
	pinctrl-0 = <&sdmmc4_1v8_drv>;
	pinctrl-1 = <&sdmmc4_1v8_drv>;
	nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
	nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
	nvidia,default-tap = <0x8>;
	nvidia,default-trim = <0x0>;
	assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
	<&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
	assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
	nvidia,dqs-trim = <40>;
	mmc-hs400-1_8v;
	status = "disabled";
	};

	+ usb@700d0000 {
	+ compatible = "nvidia,tegra210-xudc";
	+ reg = <0x0 0x700d0000 0x0 0x8000>,
	+ <0x0 0x700d8000 0x0 0x1000>,
	+ <0x0 0x700d9000 0x0 0x1000>;
	+ reg-names = "base", "fpci", "ipfs";
	+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>,
	+ <&tegra_car TEGRA210_CLK_XUSB_SS>,
	+ <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>,
	+ <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
	+ <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>;
	+ clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src";
	+ power-domains = <&pd_xusbdev>, <&pd_xusbss>;
	+ power-domain-names = "dev", "ss";
	+ nvidia,xusb-padctl = <&padctl>;
	+ status = "disabled";
	+ };
	+
	mipi: mipi@700e3000 {
	compatible = "nvidia,tegra210-mipi";
	reg = <0x0 0x700e3000 0x0 0x100>;
	clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
	clock-names = "mipi-cal";
	power-domains = <&pd_sor>;
	#nvidia,mipi-calibrate-cells = <1>;
	};

	dfll: clock@70110000 {
	compatible = "nvidia,tegra210-dfll";
	reg = <0 0x70110000 0 0x100>, /* DFLL control */
	<0 0x70110000 0 0x100>, /* I2C output control */
	<0 0x70110100 0 0x100>, /* Integrated I2C controller */
	<0 0x70110200 0 0x100>; /* Look-up table RAM */
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
	<&tegra_car TEGRA210_CLK_DFLL_REF>,
	<&tegra_car TEGRA210_CLK_I2C5>;
	clock-names = "soc", "ref", "i2c";
	resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
	reset-names = "dvco";
	#clock-cells = <0>;
	clock-output-names = "dfllCPU_out";
	status = "disabled";
	};

	aconnect@702c0000 {
	compatible = "nvidia,tegra210-aconnect";
	clocks = <&tegra_car TEGRA210_CLK_APE>,
	<&tegra_car TEGRA210_CLK_APB2APE>;
	clock-names = "ape", "apb2ape";
	power-domains = <&pd_audio>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
	status = "disabled";

	adma: dma@702e2000 {
	compatible = "nvidia,tegra210-adma";
	reg = <0x702e2000 0x2000>;
	interrupt-parent = <&agic>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
	clock-names = "d_audio";
	status = "disabled";
	};

	agic: agic@702f9000 {
	compatible = "nvidia,tegra210-agic";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x702f9000 0x1000>,
	<0x702fa000 0x2000>;
	interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&tegra_car TEGRA210_CLK_APE>;
	clock-names = "clk";
	status = "disabled";
	};
	};

	spi@70410000 {
	compatible = "nvidia,tegra210-qspi";
	reg = <0x0 0x70410000 0x0 0x1000>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car TEGRA210_CLK_QSPI>;
	clock-names = "qspi";
	resets = <&tegra_car 211>;
	reset-names = "qspi";
	dmas = <&apbdma 5>, <&apbdma 5>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	usb@7d000000 {
	compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
	reg = <0x0 0x7d000000 0x0 0x4000>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA210_CLK_USBD>;
	clock-names = "usb";
	resets = <&tegra_car 22>;
	reset-names = "usb";
	nvidia,phy = <&phy1>;
	status = "disabled";
	};

	phy1: usb-phy@7d000000 {
	compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
	reg = <0x0 0x7d000000 0x0 0x4000>,
	<0x0 0x7d000000 0x0 0x4000>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA210_CLK_USBD>,
	<&tegra_car TEGRA210_CLK_PLL_U>,
	<&tegra_car TEGRA210_CLK_USBD>;
	clock-names = "reg", "pll_u", "utmi-pads";
	resets = <&tegra_car 22>, <&tegra_car 22>;
	reset-names = "usb", "utmi-pads";
	nvidia,hssync-start-delay = <0>;
	nvidia,idle-wait-delay = <17>;
	nvidia,elastic-limit = <16>;
	nvidia,term-range-adj = <6>;
	nvidia,xcvr-setup = <9>;
	nvidia,xcvr-lsfslew = <0>;
	nvidia,xcvr-lsrslew = <3>;
	nvidia,hssquelch-level = <2>;
	nvidia,hsdiscon-level = <5>;
	nvidia,xcvr-hsslew = <12>;
	nvidia,has-utmi-pad-registers;
	status = "disabled";
	};

	usb@7d004000 {
	compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
	reg = <0x0 0x7d004000 0x0 0x4000>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA210_CLK_USB2>;
	clock-names = "usb";
	resets = <&tegra_car 58>;
	reset-names = "usb";
	nvidia,phy = <&phy2>;
	status = "disabled";
	};

	phy2: usb-phy@7d004000 {
	compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
	reg = <0x0 0x7d004000 0x0 0x4000>,
	<0x0 0x7d000000 0x0 0x4000>;
	phy_type = "utmi";
	clocks = <&tegra_car TEGRA210_CLK_USB2>,
	<&tegra_car TEGRA210_CLK_PLL_U>,
	<&tegra_car TEGRA210_CLK_USBD>;
	clock-names = "reg", "pll_u", "utmi-pads";
	resets = <&tegra_car 58>, <&tegra_car 22>;
	reset-names = "usb", "utmi-pads";
	nvidia,hssync-start-delay = <0>;
	nvidia,idle-wait-delay = <17>;
	nvidia,elastic-limit = <16>;
	nvidia,term-range-adj = <6>;
	nvidia,xcvr-setup = <9>;
	nvidia,xcvr-lsfslew = <0>;
	nvidia,xcvr-lsrslew = <3>;
	nvidia,hssquelch-level = <2>;
	nvidia,hsdiscon-level = <5>;
	nvidia,xcvr-hsslew = <12>;
	status = "disabled";
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a57";
	reg = <0>;
	clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
	<&tegra_car TEGRA210_CLK_PLL_X>,
	<&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
	<&dfll>;
	clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
	clock-latency = <300000>;
	cpu-idle-states = <&CPU_SLEEP>;
	next-level-cache = <&L2>;
	};

	cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a57";
	reg = <1>;
	cpu-idle-states = <&CPU_SLEEP>;
	next-level-cache = <&L2>;
	};

	cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a57";
	reg = <2>;
	cpu-idle-states = <&CPU_SLEEP>;
	next-level-cache = <&L2>;
	};

	cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a57";
	reg = <3>;
	cpu-idle-states = <&CPU_SLEEP>;
	next-level-cache = <&L2>;
	};

	idle-states {
	entry-method = "psci";

	CPU_SLEEP: cpu-sleep {
	compatible = "arm,idle-state";
	arm,psci-suspend-param = <0x40000007>;
	entry-latency-us = <100>;
	exit-latency-us = <30>;
	min-residency-us = <1000>;
	wakeup-latency-us = <130>;
	idle-state-name = "cpu-sleep";
	status = "disabled";
	};
	};

	L2: l2-cache {
	compatible = "cache";
	};
	};

	pmu {
	compatible = "arm,armv8-pmuv3";
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
	&{/cpus/cpu@2} &{/cpus/cpu@3}>;
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	interrupt-parent = <&gic>;
	arm,no-tick-in-suspend;
	};

	soctherm: thermal-sensor@700e2000 {
	compatible = "nvidia,tegra210-soctherm";
	reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
	0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
	reg-names = "soctherm-reg", "car-reg";
	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "thermal", "edp";
	clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
	<&tegra_car TEGRA210_CLK_SOC_THERM>;
	clock-names = "tsensor", "soctherm";
	resets = <&tegra_car 78>;
	reset-names = "soctherm";
	#thermal-sensor-cells = <1>;

	throttle-cfgs {
	throttle_heavy: heavy {
	nvidia,priority = <100>;
	nvidia,cpu-throt-percent = <85>;

	#cooling-cells = <2>;
	};
	};
	};

	thermal-zones {
	cpu {
	polling-delay-passive = <1000>;
	polling-delay = <0>;

	thermal-sensors =
	<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;

	trips {
	cpu-shutdown-trip {
	temperature = <102500>;
	hysteresis = <0>;
	type = "critical";
	};

	cpu_throttle_trip: throttle-trip {
	temperature = <98500>;
	hysteresis = <1000>;
	type = "hot";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu_throttle_trip>;
	cooling-device = <&throttle_heavy 1 1>;
	};
	};
	};

	mem {
	polling-delay-passive = <0>;
	polling-delay = <0>;

	thermal-sensors =
	<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;

	trips {
	mem-shutdown-trip {
	temperature = <103000>;
	hysteresis = <0>;
	type = "critical";
	};
	};

	cooling-maps {
	/*
	* There are currently no cooling maps,
	* because there are no cooling devices.
	*/
	};
	};

	gpu {
	polling-delay-passive = <1000>;
	polling-delay = <0>;

	thermal-sensors =
	<&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;

	trips {
	gpu-shutdown-trip {
	temperature = <103000>;
	hysteresis = <0>;
	type = "critical";
	};

	gpu_throttle_trip: throttle-trip {
	temperature = <100000>;
	hysteresis = <1000>;
	type = "hot";
	};
	};

	cooling-maps {
	map0 {
	trip = <&gpu_throttle_trip>;
	cooling-device = <&throttle_heavy 1 1>;
	};
	};
	};

	pllx {
	polling-delay-passive = <0>;
	polling-delay = <0>;

	thermal-sensors =
	<&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;

	trips {
	pllx-shutdown-trip {
	temperature = <103000>;
	hysteresis = <0>;
	type = "critical";
	};
	};

	cooling-maps {
	/*
	* There are currently no cooling maps,
	* because there are no cooling devices.
	*/
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/qcom/apq8016-sbc.dtsi b/sys/gnu/dts/arm64/qcom/apq8016-sbc.dtsi
	index 037e26b3f8d5..06aab44d798c 100644
	--- a/sys/gnu/dts/arm64/qcom/apq8016-sbc.dtsi
	+++ b/sys/gnu/dts/arm64/qcom/apq8016-sbc.dtsi
	@@ -1,683 +1,682 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (c) 2015, The Linux Foundation. All rights reserved.
	*/

	#include "msm8916.dtsi"
	#include "pm8916.dtsi"
	#include "apq8016-sbc-soc-pins.dtsi"
	#include "apq8016-sbc-pmic-pins.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/sound/apq8016-lpass.h>

	/*
	* GPIO name legend: proper name = the GPIO line is used as GPIO
	* NC = not connected (pin out but not routed from the chip to
	* anything the board)
	* "[PER]" = pin is muxed for [peripheral] (not GPIO)
	* LSEC = Low Speed External Connector
	* HSEC = High Speed External Connector
	*
	* Line names are taken from the schematic "DragonBoard410c"
	* dated monday, august 31, 2015. Page 5 in particular.
	*
	* For the lines routed to the external connectors the
	* lines are named after the 96Boards CE Specification 1.0,
	* Appendix "Expansion Connector Signal Description".
	*
	* When the 96Board naming of a line and the schematic name of
	* the same line are in conflict, the 96Board specification
	* takes precedence, which means that the external UART on the
	* LSEC is named UART0 while the schematic and SoC names this
	* UART3. This is only for the informational lines i.e. "[FOO]",
	* the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
	* ones actually used for GPIO.
	*/

	/ {
	aliases {
	serial0 = &blsp1_uart2;
	serial1 = &blsp1_uart1;
	usid0 = &pm8916_0;
	i2c0 = &blsp_i2c2;
	i2c1 = &blsp_i2c6;
	i2c3 = &blsp_i2c4;
	spi0 = &blsp_spi5;
	spi1 = &blsp_spi3;
	};

	chosen {
	stdout-path = "serial0";
	};

	reserved-memory {
	ramoops@bff00000{
	compatible = "ramoops";
	reg = <0x0 0xbff00000 0x0 0x100000>;

	record-size = <0x20000>;
	console-size = <0x20000>;
	ftrace-size = <0x20000>;
	};
	};

	soc {
	pinctrl@1000000 {
	gpio-line-names =
	"[UART0_TX]", /* GPIO_0, LSEC pin 5 */
	"[UART0_RX]", /* GPIO_1, LSEC pin 7 */
	"[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */
	"[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */
	"[UART1_TX]", /* GPIO_4, LSEC pin 11 */
	"[UART1_RX]", /* GPIO_5, LSEC pin 13 */
	"[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */
	"[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */
	"[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */
	"[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */
	"[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */
	"[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */
	"GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */
	"GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */
	"[I2C3_SDA]", /* HSEC pin 38 */
	"[I2C3_SCL]", /* HSEC pin 36 */
	"[SPI0_MOSI]", /* LSEC pin 14 */
	"[SPI0_MISO]", /* LSEC pin 10 */
	"[SPI0_CS_N]", /* LSEC pin 12 */
	"[SPI0_CLK]", /* LSEC pin 8 */
	"HDMI_HPD_N", /* GPIO 20 */
	"USR_LED_1_CTRL",
	"[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */
	"[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */
	"GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */
	"GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */
	"[CSI0_MCLK]", /* HSEC pin 15 */
	"[CSI1_MCLK]", /* HSEC pin 17 */
	"GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */
	"[I2C2_SDA]", /* HSEC pin 34 */
	"[I2C2_SCL]", /* HSEC pin 32 */
	"DSI2HDMI_INT_N",
	"DSI_SW_SEL_APQ",
	"GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */
	"GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */
	"GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */
	"GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */
	"FORCED_USB_BOOT",
	"SD_CARD_DET_N",
	"[WCSS_BT_SSBI]",
	"[WCSS_WLAN_DATA_2]", /* GPIO 40 */
	"[WCSS_WLAN_DATA_1]",
	"[WCSS_WLAN_DATA_0]",
	"[WCSS_WLAN_SET]",
	"[WCSS_WLAN_CLK]",
	"[WCSS_FM_SSBI]",
	"[WCSS_FM_SDI]",
	"[WCSS_BT_DAT_CTL]",
	"[WCSS_BT_DAT_STB]",
	"NC",
	"NC", /* GPIO 50 */
	"NC",
	"NC",
	"NC",
	"NC",
	"NC",
	"NC",
	"NC",
	"NC",
	"NC",
	"NC", /* GPIO 60 */
	"NC",
	"NC",
	"[CDC_PDM0_CLK]",
	"[CDC_PDM0_SYNC]",
	"[CDC_PDM0_TX0]",
	"[CDC_PDM0_RX0]",
	"[CDC_PDM0_RX1]",
	"[CDC_PDM0_RX2]",
	"GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */
	"NC", /* GPIO 70 */
	"NC",
	"NC",
	"NC",
	"NC", /* GPIO 74 */
	"NC",
	"NC",
	"NC",
	"NC",
	"NC",
	"BOOT_CONFIG_0", /* GPIO 80 */
	"BOOT_CONFIG_1",
	"BOOT_CONFIG_2",
	"BOOT_CONFIG_3",
	"NC",
	"NC",
	"BOOT_CONFIG_5",
	"NC",
	"NC",
	"NC",
	"NC", /* GPIO 90 */
	"NC",
	"NC",
	"NC",
	"NC",
	"NC",
	"NC",
	"NC",
	"NC",
	"NC",
	"NC", /* GPIO 100 */
	"NC",
	"NC",
	"NC",
	"SSBI_GPS",
	"NC",
	"NC",
	"KEY_VOLP_N",
	"NC",
	"NC",
	"[LS_EXP_MI2S_WS]", /* GPIO 110 */
	"NC",
	"NC",
	"[LS_EXP_MI2S_SCK]",
	"[LS_EXP_MI2S_DATA0]",
	"GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */
	"NC",
	"[DSI2HDMI_MI2S_WS]",
	"[DSI2HDMI_MI2S_SCK]",
	"[DSI2HDMI_MI2S_DATA0]",
	"USR_LED_2_CTRL", /* GPIO 120 */
	"SB_HS_ID";
	};

	dma@7884000 {
	status = "okay";
	};

	serial@78af000 {
	label = "LS-UART0";
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&blsp1_uart1_default>;
	pinctrl-1 = <&blsp1_uart1_sleep>;
	};

	serial@78b0000 {
	label = "LS-UART1";
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&blsp1_uart2_default>;
	pinctrl-1 = <&blsp1_uart2_sleep>;
	};

	i2c@78b6000 {
	/* On Low speed expansion */
	label = "LS-I2C0";
	status = "okay";
	};

	i2c@78b8000 {
	/* On High speed expansion */
	label = "HS-I2C2";
	status = "okay";

	adv_bridge: bridge@39 {
	status = "okay";

	compatible = "adi,adv7533";
	reg = <0x39>;

	interrupt-parent = <&msmgpio>;
	interrupts = <31 2>;

	adi,dsi-lanes = <4>;
	clocks = <&rpmcc RPM_SMD_BB_CLK2>;
	clock-names = "cec";

	pd-gpios = <&msmgpio 32 0>;

	avdd-supply = <&pm8916_l6>;
	v1p2-supply = <&pm8916_l6>;
	v3p3-supply = <&pm8916_l17>;

	pinctrl-names = "default","sleep";
	pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>;
	pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>;
	#sound-dai-cells = <1>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7533_in: endpoint {
	remote-endpoint = <&dsi0_out>;
	};
	};

	port@1 {
	reg = <1>;
	adv7533_out: endpoint {
	remote-endpoint = <&hdmi_con>;
	};
	};
	};
	};
	};

	i2c@78ba000 {
	/* On Low speed expansion */
	label = "LS-I2C1";
	status = "okay";
	};

	spi@78b7000 {
	/* On High speed expansion */
	label = "HS-SPI1";
	status = "okay";
	};

	spi@78b9000 {
	/* On Low speed expansion */
	label = "LS-SPI0";
	status = "okay";
	};

	leds {
	pinctrl-names = "default";
	pinctrl-0 = <&msmgpio_leds>,
	<&pm8916_gpios_leds>,
	<&pm8916_mpps_leds>;

	compatible = "gpio-leds";

	led@1 {
	label = "apq8016-sbc:green:user1";
	gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	default-state = "off";
	};

	led@2 {
	label = "apq8016-sbc:green:user2";
	gpios = <&msmgpio 120 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "mmc0";
	default-state = "off";
	};

	led@3 {
	label = "apq8016-sbc:green:user3";
	gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "mmc1";
	default-state = "off";
	};

	led@4 {
	label = "apq8016-sbc:green:user4";
	gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "none";
	panic-indicator;
	default-state = "off";
	};

	led@5 {
	label = "apq8016-sbc:yellow:wlan";
	gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "phy0tx";
	default-state = "off";
	};

	led@6 {
	label = "apq8016-sbc:blue:bt";
	gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "bluetooth-power";
	default-state = "off";
	};
	};

	sdhci@7824000 {
	vmmc-supply = <&pm8916_l8>;
	vqmmc-supply = <&pm8916_l5>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
	status = "okay";
	};

	sdhci@7864000 {
	vmmc-supply = <&pm8916_l11>;
	vqmmc-supply = <&pm8916_l12>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;

	cd-gpios = <&msmgpio 38 0x1>;
	status = "okay";
	};

	usb@78d9000 {
	extcon = <&usb_id>, <&usb_id>;
	status = "okay";
	adp-disable;
	hnp-disable;
	srp-disable;
	dr_mode = "otg";
	pinctrl-names = "default", "device";
	pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>;
	pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>;
	ulpi {
	phy {
	v1p8-supply = <&pm8916_l7>;
	v3p3-supply = <&pm8916_l13>;
	extcon = <&usb_id>;
	};
	};
	};

	lpass@7708000 {
	status = "okay";
	};

	mdss@1a00000 {
	status = "okay";

	mdp@1a01000 {
	status = "okay";
	};

	dsi@1a98000 {
	status = "okay";

	vdda-supply = <&pm8916_l2>;
	vddio-supply = <&pm8916_l6>;

	ports {
	port@1 {
	endpoint {
	remote-endpoint = <&adv7533_in>;
	data-lanes = <0 1 2 3>;
	};
	};
	};
	};

	dsi-phy@1a98300 {
	status = "okay";

	vddio-supply = <&pm8916_l6>;
	};
	};

	lpass_codec: codec{
	status = "okay";
	};

	/*
	Internal Codec
	playback - Primary MI2S
	capture - Ter MI2S

	External Primary:
	playback - secondary MI2S
	capture - Quat MI2S

	External Secondary:
	playback - Quat MI2S
	capture - Quat MI2S

	*/

	sound: sound {
	compatible = "qcom,apq8016-sbc-sndcard";
	reg = <0x07702000 0x4>, <0x07702004 0x4>;
	reg-names = "mic-iomux", "spkr-iomux";

	status = "okay";
	pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>;
	pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>;
	pinctrl-names = "default", "sleep";
	qcom,model = "DB410c";
	qcom,audio-routing =
	"AMIC2", "MIC BIAS Internal2",
	"AMIC3", "MIC BIAS External1";
	external-dai-link@0 {
	link-name = "ADV7533";
	cpu { /* QUAT */
	sound-dai = <&lpass MI2S_QUATERNARY>;
	};
	codec {
	sound-dai = <&adv_bridge 0>;
	};
	};

	internal-codec-playback-dai-link@0 { /* I2S - Internal codec */
	link-name = "WCD";
	cpu { /* PRIMARY */
	sound-dai = <&lpass MI2S_PRIMARY>;
	};
	codec {
	sound-dai = <&lpass_codec 0>, <&wcd_codec 0>;
	};
	};

	internal-codec-capture-dai-link@0 { /* I2S - Internal codec */
	link-name = "WCD-Capture";
	cpu { /* PRIMARY */
	sound-dai = <&lpass MI2S_TERTIARY>;
	};
	codec {
	sound-dai = <&lpass_codec 1>, <&wcd_codec 1>;
	};
	};
	};

	spmi@200f000 {
	pm8916@0 {
	gpios@c000 {
	gpio-line-names =
	"USR_LED_3_CTRL",
	"USR_LED_4_CTRL",
	"USB_HUB_RESET_N_PM",
	"USB_SW_SEL_PM";
	};
	mpps@a000 {
	gpio-line-names =
	"VDD_PX_BIAS",
	"WLAN_LED_CTRL",
	"BT_LED_CTRL",
	"GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */
	};
	};
	};

	wcnss@a21b000 {
	status = "okay";
	};
	};

	usb2513 {
	compatible = "smsc,usb3503";
	reset-gpios = <&pm8916_gpios 3 GPIO_ACTIVE_LOW>;
	initial-mode = <1>;
	};

	usb_id: usb-id {
	compatible = "linux,extcon-usb-gpio";
	id-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&usb_id_default>;
	};

	hdmi-out {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con: endpoint {
	remote-endpoint = <&adv7533_out>;
	};
	};
	};

	gpio_keys {
	compatible = "gpio-keys";
	#address-cells = <1>;
	#size-cells = <0>;
	autorepeat;

	pinctrl-names = "default";
	pinctrl-0 = <&msm_key_volp_n_default>;

	button@0 {
	label = "Volume Up";
	linux,code = <KEY_VOLUMEUP>;
	gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>;
	};
	};
	};

	&spmi_bus {
	pm8916_0: pm8916@0 {
	pon@800 {
	resin {
	compatible = "qcom,pm8941-resin";
	interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
	debounce = <15625>;
	bias-pull-up;
	linux,code = <KEY_VOLUMEDOWN>;
	};
	};
	};
	};

	&wcd_codec {
	status = "okay";
	clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
	clock-names = "mclk";
	qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
	qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
	};

	&smd_rpm_regulators {
	vdd_l1_l2_l3-supply = <&pm8916_s3>;
	- vdd_l5-supply = <&pm8916_s3>;
	vdd_l4_l5_l6-supply = <&pm8916_s4>;
	vdd_l7-supply = <&pm8916_s4>;

	s1 {
	regulator-min-microvolt = <375000>;
	regulator-max-microvolt = <1562000>;
	};

	s3 {
	regulator-min-microvolt = <375000>;
	regulator-max-microvolt = <1562000>;
	};

	s4 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	regulator-always-on;
	regulator-boot-on;
	};

	l1 {
	regulator-min-microvolt = <375000>;
	regulator-max-microvolt = <1525000>;
	};

	l2 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	l3 {
	regulator-min-microvolt = <375000>;
	regulator-max-microvolt = <1525000>;
	};

	l4 {
	regulator-min-microvolt = <1750000>;
	regulator-max-microvolt = <3337000>;
	};

	l5 {
	regulator-min-microvolt = <1750000>;
	regulator-max-microvolt = <3337000>;
	};

	l6 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	l7 {
	regulator-min-microvolt = <1750000>;
	regulator-max-microvolt = <3337000>;
	};

	l8 {
	regulator-min-microvolt = <1750000>;
	regulator-max-microvolt = <3337000>;
	};

	l9 {
	regulator-min-microvolt = <1750000>;
	regulator-max-microvolt = <3337000>;
	};

	l10 {
	regulator-min-microvolt = <1750000>;
	regulator-max-microvolt = <3337000>;
	};

	l11 {
	regulator-min-microvolt = <1750000>;
	regulator-max-microvolt = <3337000>;
	regulator-allow-set-load;
	regulator-system-load = <200000>;
	};

	l12 {
	regulator-min-microvolt = <1750000>;
	regulator-max-microvolt = <3337000>;
	};

	l13 {
	regulator-min-microvolt = <1750000>;
	regulator-max-microvolt = <3337000>;
	};

	l14 {
	regulator-min-microvolt = <1750000>;
	regulator-max-microvolt = <3337000>;
	};

	/**
	* 1.8v required on LS expansion
	* for mezzanine boards
	*/
	l15 {
	regulator-min-microvolt = <1750000>;
	regulator-max-microvolt = <3337000>;
	regulator-always-on;
	};

	l16 {
	regulator-min-microvolt = <1750000>;
	regulator-max-microvolt = <3337000>;
	};

	l17 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	l18 {
	regulator-min-microvolt = <1750000>;
	regulator-max-microvolt = <3337000>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/qcom/apq8096-db820c.dtsi b/sys/gnu/dts/arm64/qcom/apq8096-db820c.dtsi
	index fff6115f2670..c4abbccf2bed 100644
	--- a/sys/gnu/dts/arm64/qcom/apq8096-db820c.dtsi
	+++ b/sys/gnu/dts/arm64/qcom/apq8096-db820c.dtsi
	@@ -1,1062 +1,1073 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
	*/

	#include "msm8996.dtsi"
	#include "pm8994.dtsi"
	#include "pmi8994.dtsi"
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
	#include <dt-bindings/sound/qcom,q6afe.h>
	#include <dt-bindings/sound/qcom,q6asm.h>

	/*
	* GPIO name legend: proper name = the GPIO line is used as GPIO
	* NC = not connected (pin out but not routed from the chip to
	* anything the board)
	* "[PER]" = pin is muxed for [peripheral] (not GPIO)
	* LSEC = Low Speed External Connector
	* P HSEC = Primary High Speed External Connector
	* S HSEC = Secondary High Speed External Connector
	* J14 = Camera Connector
	* TP = Test Points
	*
	* Line names are taken from the schematic "DragonBoard 820c",
	* drawing no: LM25-P2751-1
	*
	* For the lines routed to the external connectors the
	* lines are named after the 96Boards CE Specification 1.0,
	* Appendix "Expansion Connector Signal Description".
	*
	* When the 96Board naming of a line and the schematic name of
	* the same line are in conflict, the 96Board specification
	* takes precedence, which means that the external UART on the
	* LSEC is named UART0 while the schematic and SoC names this
	* UART3. This is only for the informational lines i.e. "[FOO]",
	* the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
	* ones actually used for GPIO.
	*/

	/ {
	aliases {
	serial0 = &blsp2_uart1;
	serial1 = &blsp2_uart2;
	serial2 = &blsp1_uart1;
	i2c0 = &blsp1_i2c2;
	i2c1 = &blsp2_i2c1;
	i2c2 = &blsp2_i2c0;
	spi0 = &blsp1_spi0;
	spi1 = &blsp2_spi5;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	clocks {
	compatible = "simple-bus";
	divclk4: divclk4 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	clock-output-names = "divclk4";

	pinctrl-names = "default";
	pinctrl-0 = <&divclk4_pin_a>;
	};

	div1_mclk: divclk1 {
	compatible = "gpio-gate-clock";
	pinctrl-0 = <&audio_mclk>;
	pinctrl-names = "default";
	clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
	#clock-cells = <0>;
	enable-gpios = <&pm8994_gpios 15 0>;
	};
	};

	gpio_keys {
	compatible = "gpio-keys";
	#address-cells = <1>;
	#size-cells = <0>;
	autorepeat;

	pinctrl-names = "default";
	pinctrl-0 = <&volume_up_gpio>;

	button@0 {
	label = "Volume Up";
	linux,code = <KEY_VOLUMEUP>;
	gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>;
	};
	};

	usb2_id: usb2-id {
	compatible = "linux,extcon-usb-gpio";
	id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&usb2_vbus_det_gpio>;
	};

	usb3_id: usb3-id {
	compatible = "linux,extcon-usb-gpio";
	id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&usb3_vbus_det_gpio>;
	};

	vph_pwr: vph-pwr-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vph_pwr";
	regulator-always-on;
	regulator-boot-on;

	regulator-min-microvolt = <3700000>;
	regulator-max-microvolt = <3700000>;
	};

	vreg_s8a_l3a_input: vreg-s8a-l3a-input {
	compatible = "regulator-fixed";
	regulator-name = "vreg_s8a_l3a_input";
	regulator-always-on;
	regulator-boot-on;

	regulator-min-microvolt = <0>;
	regulator-max-microvolt = <0>;
	};

	wlan_en: wlan-en-1-8v {
	pinctrl-names = "default";
	pinctrl-0 = <&wlan_en_gpios>;
	compatible = "regulator-fixed";
	regulator-name = "wlan-en-regulator";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	gpio = <&pm8994_gpios 8 0>;

	/* WLAN card specific delay */
	startup-delay-us = <70000>;
	enable-active-high;
	};
	};

	&blsp1_i2c2 {
	/* On Low speed expansion */
	label = "LS-I2C0";
	status = "okay";
	};

	&blsp1_spi0 {
	/* On Low speed expansion */
	label = "LS-SPI0";
	status = "okay";
	};

	&blsp1_uart1 {
	label = "BT-UART";
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&blsp1_uart1_default>;
	pinctrl-1 = <&blsp1_uart1_sleep>;

	bluetooth {
	compatible = "qcom,qca6174-bt";

	/* bt_disable_n gpio */
	enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;

	clocks = <&divclk4>;
	};
	};

	&blsp2_i2c0 {
	/* On High speed expansion */
	label = "HS-I2C2";
	status = "okay";
	};

	&blsp2_i2c1 {
	/* On Low speed expansion */
	label = "LS-I2C1";
	status = "okay";
	};

	&blsp2_spi5 {
	/* On High speed expansion */
	label = "HS-SPI1";
	status = "okay";
	};

	&blsp2_uart1 {
	label = "LS-UART1";
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&blsp2_uart1_2pins_default>;
	pinctrl-1 = <&blsp2_uart1_2pins_sleep>;
	};

	&blsp2_uart2 {
	label = "LS-UART0";
	status = "disabled";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&blsp2_uart2_4pins_default>;
	pinctrl-1 = <&blsp2_uart2_4pins_sleep>;
	};

	&camss {
	vdda-supply = <&vreg_l2a_1p25>;
	};

	&hdmi {
	status = "okay";

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
	pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;

	core-vdda-supply = <&vreg_l12a_1p8>;
	core-vcc-supply = <&vreg_s4a_1p8>;
	};

	&hdmi_phy {
	status = "okay";

	vddio-supply = <&vreg_l12a_1p8>;
	vcca-supply = <&vreg_l28a_0p925>;
	#phy-cells = <0>;
	};

	&hsusb_phy1 {
	status = "okay";

	vdda-pll-supply = <&vreg_l12a_1p8>;
	vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
	};

	&hsusb_phy2 {
	status = "okay";

	vdda-pll-supply = <&vreg_l12a_1p8>;
	vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
	};

	&mdp {
	status = "okay";
	};

	&mdss {
	status = "okay";
	};

	&msmgpio {
	gpio-line-names =
	"[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */
	"[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */
	"[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */
	"[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */
	"[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */
	"[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */
	"[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */
	"[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */
	"GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */
	"TP93", /* GPIO_9 */
	"GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */
	"[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */
	"NC", /* GPIO_12 */
	"[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */
	"[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */
	"[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */
	"TP99", /* GPIO_16 */
	"[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */
	"[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */
	"[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */
	"[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */
	"FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */
	"FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */
	"GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */
	"GPIO-D", /* GPIO_24, LSEC pin 26 */
	"GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */
	"GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */
	"BLSP6_I2C_SDA", /* GPIO_27 */
	"BLSP6_I2C_SCL", /* GPIO_28 */
	"GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */
	"GPIO30", /* GPIO_30, S HSEC pin 4 */
	"HDMI_CEC", /* GPIO_31 */
	"HDMI_DDC_CLOCK", /* GPIO_32 */
	"HDMI_DDC_DATA", /* GPIO_33 */
	"HDMI_HOT_PLUG_DETECT", /* GPIO_34 */
	"PCIE0_RST_N", /* GPIO_35 */
	"PCIE0_CLKREQ_N", /* GPIO_36 */
	"PCIE0_WAKE", /* GPIO_37 */
	"SD_CARD_DET_N", /* GPIO_38 */
	"TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */
	"W_DISABLE_N", /* GPIO_40 */
	"[BLSP9_UART_TX]", /* GPIO_41 */
	"[BLSP9_UART_RX]", /* GPIO_42 */
	"[BLSP2_UART_CTS_N]", /* GPIO_43 */
	"[BLSP2_UART_RFR_N]", /* GPIO_44 */
	"[BLSP3_UART_TX]", /* GPIO_45 */
	"[BLSP3_UART_RX]", /* GPIO_46 */
	"[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */
	"[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */
	"[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */
	"[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */
	"[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */
	"[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */
	"[CODEC_INT1_N]", /* GPIO_53 */
	"[CODEC_INT2_N]", /* GPIO_54 */
	"[BLSP7_I2C_SDA]", /* GPIO_55 */
	"[BLSP7_I2C_SCL]", /* GPIO_56 */
	"MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */
	"[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */
	"[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */
	"[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */
	"[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */
	"GPIO-E", /* GPIO_62, LSEC pin 27 */
	"TP87", /* GPIO_63 */
	"[CODEC_RST_N]", /* GPIO_64 */
	"[PCM1_CLK]", /* GPIO_65 */
	"[PCM1_SYNC]", /* GPIO_66 */
	"[PCM1_DIN]", /* GPIO_67 */
	"[PCM1_DOUT]", /* GPIO_68 */
	"AUDIO_REF_CLK", /* GPIO_69 */
	"SLIMBUS_CLK", /* GPIO_70 */
	"SLIMBUS_DATA0", /* GPIO_71 */
	"SLIMBUS_DATA1", /* GPIO_72 */
	"NC", /* GPIO_73 */
	"NC", /* GPIO_74 */
	"NC", /* GPIO_75 */
	"NC", /* GPIO_76 */
	"TP94", /* GPIO_77 */
	"NC", /* GPIO_78 */
	"TP95", /* GPIO_79 */
	"GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */
	"TP88", /* GPIO_81 */
	"TP89", /* GPIO_82 */
	"TP90", /* GPIO_83 */
	"TP91", /* GPIO_84 */
	"[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */
	"[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */
	"[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */
	"[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */
	"TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */
	"TSIF1_EN", /* GPIO_90, S HSEC pin 46 */
	"TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */
	"NC", /* GPIO_92 */
	"TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */
	"TSIF2_EN", /* GPIO_94, S HSEC pin 56 */
	"TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */
	"TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */
	"NC", /* GPIO_97 */
	"CAM1_STANDBY_N", /* GPIO_98 */
	"NC", /* GPIO_99 */
	"NC", /* GPIO_100 */
	"[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */
	"BOOT_CONFIG1", /* GPIO_102 */
	"USB_HUB_RESET", /* GPIO_103 */
	"CAM1_RST_N", /* GPIO_104 */
	"NC", /* GPIO_105 */
	"NC", /* GPIO_106 */
	"NC", /* GPIO_107 */
	"NC", /* GPIO_108 */
	"NC", /* GPIO_109 */
	"NC", /* GPIO_110 */
	"NC", /* GPIO_111 */
	"NC", /* GPIO_112 */
	"PMI8994_BUA", /* GPIO_113 */
	"PCIE2_RST_N", /* GPIO_114 */
	"PCIE2_CLKREQ_N", /* GPIO_115 */
	"PCIE2_WAKE", /* GPIO_116 */
	"SSC_IRQ_0", /* GPIO_117 */
	"SSC_IRQ_1", /* GPIO_118 */
	"SSC_IRQ_2", /* GPIO_119 */
	"NC", /* GPIO_120 */
	"GPIO121", /* GPIO_121, S HSEC pin 2 */
	"NC", /* GPIO_122 */
	"SSC_IRQ_6", /* GPIO_123 */
	"SSC_IRQ_7", /* GPIO_124 */
	"GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */
	"BOOT_CONFIG5", /* GPIO_126 */
	"NC", /* GPIO_127 */
	"NC", /* GPIO_128 */
	"BOOT_CONFIG7", /* GPIO_129 */
	"PCIE1_RST_N", /* GPIO_130 */
	"PCIE1_CLKREQ_N", /* GPIO_131 */
	"PCIE1_WAKE", /* GPIO_132 */
	"GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */
	"NC", /* GPIO_134 */
	"NC", /* GPIO_135 */
	"BOOT_CONFIG8", /* GPIO_136 */
	"NC", /* GPIO_137 */
	"NC", /* GPIO_138 */
	"GPS_SSBI2", /* GPIO_139 */
	"GPS_SSBI1", /* GPIO_140 */
	"NC", /* GPIO_141 */
	"NC", /* GPIO_142 */
	"NC", /* GPIO_143 */
	"BOOT_CONFIG6", /* GPIO_144 */
	"NC", /* GPIO_145 */
	"NC", /* GPIO_146 */
	"NC", /* GPIO_147 */
	"NC", /* GPIO_148 */
	"NC"; /* GPIO_149 */

	sdc2_cd_on: sdc2_cd_on {
	mux {
	pins = "gpio38";
	function = "gpio";
	};

	config {
	pins = "gpio38";
	bias-pull-up; /* pull up */
	drive-strength = <16>; /* 16 MA */
	};
	};

	sdc2_cd_off: sdc2_cd_off {
	mux {
	pins = "gpio38";
	function = "gpio";
	};

	config {
	pins = "gpio38";
	bias-pull-up; /* pull up */
	drive-strength = <2>; /* 2 MA */
	};
	};

	blsp1_uart1_default: blsp1_uart1_default {
	mux {
	pins = "gpio41", "gpio42", "gpio43", "gpio44";
	function = "blsp_uart2";
	};

	config {
	pins = "gpio41", "gpio42", "gpio43", "gpio44";
	drive-strength = <16>;
	bias-disable;
	};
	};

	blsp1_uart1_sleep: blsp1_uart1_sleep {
	mux {
	pins = "gpio41", "gpio42", "gpio43", "gpio44";
	function = "gpio";
	};

	config {
	pins = "gpio41", "gpio42", "gpio43", "gpio44";
	drive-strength = <2>;
	bias-disable;
	};
	};

	hdmi_hpd_active: hdmi_hpd_active {
	mux {
	pins = "gpio34";
	function = "hdmi_hot";
	};

	config {
	pins = "gpio34";
	bias-pull-down;
	drive-strength = <16>;
	};
	};

	hdmi_hpd_suspend: hdmi_hpd_suspend {
	mux {
	pins = "gpio34";
	function = "hdmi_hot";
	};

	config {
	pins = "gpio34";
	bias-pull-down;
	drive-strength = <2>;
	};
	};

	hdmi_ddc_active: hdmi_ddc_active {
	mux {
	pins = "gpio32", "gpio33";
	function = "hdmi_ddc";
	};

	config {
	pins = "gpio32", "gpio33";
	drive-strength = <2>;
	bias-pull-up;
	};
	};

	hdmi_ddc_suspend: hdmi_ddc_suspend {
	mux {
	pins = "gpio32", "gpio33";
	function = "hdmi_ddc";
	};

	config {
	pins = "gpio32", "gpio33";
	drive-strength = <2>;
	bias-pull-down;
	};
	};
	};

	&pcie0 {
	status = "okay";
	perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
	vddpe-3v3-supply = <&wlan_en>;
	vdda-supply = <&vreg_l28a_0p925>;
	};

	&pcie1 {
	status = "okay";
	perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
	vdda-supply = <&vreg_l28a_0p925>;
	};

	&pcie2 {
	status = "okay";
	perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
	vdda-supply = <&vreg_l28a_0p925>;
	};

	&pcie_phy {
	status = "okay";

	vdda-phy-supply = <&vreg_l28a_0p925>;
	vdda-pll-supply = <&vreg_l12a_1p8>;
	};

	&pm8994_gpios {
	gpio-line-names =
	"NC",
	"KEY_VOLP_N",
	"NC",
	"BL1_PWM",
	"GPIO-F", /* BL0_PWM, LSEC pin 28 */
	"BL1_EN",
	"NC",
	"WLAN_EN",
	"NC",
	"NC",
	"NC",
	"NC",
	"NC",
	"NC",
	"DIVCLK1",
	"DIVCLK2",
	"DIVCLK3",
	"DIVCLK4",
	"BT_EN",
	"PMIC_SLB",
	"PMIC_BUA",
	"USB_VBUS_DET";

	pinctrl-names = "default";
	pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>;

	ls_exp_gpio_f: pm8994_gpio5 {
	pinconf {
	pins = "gpio5";
	output-low;
	power-source = <2>; // PM8994_GPIO_S4, 1.8V
	};
	};

	bt_en_gpios: bt_en_gpios {
	pinconf {
	pins = "gpio19";
	function = PMIC_GPIO_FUNC_NORMAL;
	output-low;
	power-source = <PM8994_GPIO_S4>; // 1.8V
	qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
	bias-pull-down;
	};
	};

	wlan_en_gpios: wlan_en_gpios {
	pinconf {
	pins = "gpio8";
	function = PMIC_GPIO_FUNC_NORMAL;
	output-low;
	power-source = <PM8994_GPIO_S4>; // 1.8V
	qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
	bias-pull-down;
	};
	};

	audio_mclk: clk_div1 {
	pinconf {
	pins = "gpio15";
	function = "func1";
	power-source = <PM8994_GPIO_S4>; // 1.8V
	};
	};

	volume_up_gpio: pm8996_gpio2 {
	pinconf {
	pins = "gpio2";
	function = "normal";
	input-enable;
	drive-push-pull;
	bias-pull-up;
	qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
	power-source = <PM8994_GPIO_S4>; // 1.8V
	};
	};

	divclk4_pin_a: divclk4 {
	pinconf {
	pins = "gpio18";
	function = PMIC_GPIO_FUNC_FUNC2;

	bias-disable;
	power-source = <PM8994_GPIO_S4>;
	};
	};

	usb3_vbus_det_gpio: pm8996_gpio22 {
	pinconf {
	pins = "gpio22";
	function = PMIC_GPIO_FUNC_NORMAL;
	input-enable;
	bias-pull-down;
	qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
	power-source = <PM8994_GPIO_S4>; // 1.8V
	};
	};
	};

	&pm8994_mpps {
	gpio-line-names =
	"VDDPX_BIAS",
	"WIFI_LED",
	"NC",
	"BT_LED",
	"PM_MPP05",
	"PM_MPP06",
	"PM_MPP07",
	"NC";
	};

	&pm8994_spmi_regulators {
	qcom,saw-reg = <&saw3>;
	s9 {
	qcom,saw-slave;
	};
	s10 {
	qcom,saw-slave;
	};
	s11 {
	qcom,saw-leader;
	regulator-always-on;
	- regulator-min-microvolt = <1230000>;
	- regulator-max-microvolt = <1230000>;
	+ regulator-min-microvolt = <980000>;
	+ regulator-max-microvolt = <980000>;
	};
	};

	&pmi8994_gpios {
	gpio-line-names =
	"NC",
	"SPKR_AMP_EN1",
	"SPKR_AMP_EN2",
	"TP61",
	"NC",
	"USB2_VBUS_DET",
	"NC",
	"NC",
	"NC",
	"NC";

	usb2_vbus_det_gpio: pmi8996_gpio6 {
	pinconf {
	pins = "gpio6";
	function = PMIC_GPIO_FUNC_NORMAL;
	input-enable;
	bias-pull-down;
	qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
	power-source = <PM8994_GPIO_S4>; // 1.8V
	};
	};
	};

	&rpm_requests {
	pm8994-regulators {
	compatible = "qcom,rpm-pm8994-regulators";

	vdd_s1-supply = <&vph_pwr>;
	vdd_s2-supply = <&vph_pwr>;
	vdd_s3-supply = <&vph_pwr>;
	vdd_s4-supply = <&vph_pwr>;
	vdd_s5-supply = <&vph_pwr>;
	vdd_s6-supply = <&vph_pwr>;
	vdd_s7-supply = <&vph_pwr>;
	vdd_s8-supply = <&vph_pwr>;
	vdd_s9-supply = <&vph_pwr>;
	vdd_s10-supply = <&vph_pwr>;
	vdd_s11-supply = <&vph_pwr>;
	vdd_s12-supply = <&vph_pwr>;
	vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>;
	vdd_l3_l11-supply = <&vreg_s8a_l3a_input>;
	vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>;
	vdd_l5_l7-supply = <&vreg_s5a_2p15>;
	vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>;
	vdd_l8_l16_l30-supply = <&vph_pwr>;
	vdd_l14_l15-supply = <&vreg_s5a_2p15>;
	vdd_l25-supply = <&vreg_s3a_1p3>;
	vdd_lvs1_2-supply = <&vreg_s4a_1p8>;

	vreg_s3a_1p3: s3 {
	regulator-name = "vreg_s3a_1p3";
	regulator-min-microvolt = <1300000>;
	regulator-max-microvolt = <1300000>;
	};

	/**
	* 1.8v required on LS expansion
	* for mezzanine boards
	*/
	vreg_s4a_1p8: s4 {
	regulator-name = "vreg_s4a_1p8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};
	vreg_s5a_2p15: s5 {
	regulator-name = "vreg_s5a_2p15";
	regulator-min-microvolt = <2150000>;
	regulator-max-microvolt = <2150000>;
	};
	vreg_s7a_1p0: s7 {
	regulator-name = "vreg_s7a_1p0";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <800000>;
	};

	vreg_l1a_1p0: l1 {
	regulator-name = "vreg_l1a_1p0";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	};
	vreg_l2a_1p25: l2 {
	regulator-name = "vreg_l2a_1p25";
	regulator-min-microvolt = <1250000>;
	regulator-max-microvolt = <1250000>;
	};
	vreg_l3a_0p875: l3 {
	regulator-name = "vreg_l3a_0p875";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <850000>;
	};
	vreg_l4a_1p225: l4 {
	regulator-name = "vreg_l4a_1p225";
	regulator-min-microvolt = <1225000>;
	regulator-max-microvolt = <1225000>;
	};
	vreg_l6a_1p2: l6 {
	regulator-name = "vreg_l6a_1p2";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};
	vreg_l8a_1p8: l8 {
	regulator-name = "vreg_l8a_1p8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	vreg_l9a_1p8: l9 {
	regulator-name = "vreg_l9a_1p8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	vreg_l10a_1p8: l10 {
	regulator-name = "vreg_l10a_1p8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	vreg_l11a_1p15: l11 {
	regulator-name = "vreg_l11a_1p15";
	regulator-min-microvolt = <1150000>;
	regulator-max-microvolt = <1150000>;
	};
	vreg_l12a_1p8: l12 {
	regulator-name = "vreg_l12a_1p8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	vreg_l13a_2p95: l13 {
	regulator-name = "vreg_l13a_2p95";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2950000>;
	};
	vreg_l14a_1p8: l14 {
	regulator-name = "vreg_l14a_1p8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	vreg_l15a_1p8: l15 {
	regulator-name = "vreg_l15a_1p8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	vreg_l16a_2p7: l16 {
	regulator-name = "vreg_l16a_2p7";
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <2700000>;
	};
	vreg_l17a_2p8: l17 {
	regulator-name = "vreg_l17a_2p8";
	regulator-min-microvolt = <2500000>;
	regulator-max-microvolt = <2500000>;
	};
	vreg_l18a_2p85: l18 {
	regulator-name = "vreg_l18a_2p85";
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <2900000>;
	};
	vreg_l19a_2p8: l19 {
	regulator-name = "vreg_l19a_2p8";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	};
	vreg_l20a_2p95: l20 {
	regulator-name = "vreg_l20a_2p95";
	regulator-min-microvolt = <2950000>;
	regulator-max-microvolt = <2950000>;
	regulator-allow-set-load;
	};
	vreg_l21a_2p95: l21 {
	regulator-name = "vreg_l21a_2p95";
	regulator-min-microvolt = <2950000>;
	regulator-max-microvolt = <2950000>;
	regulator-allow-set-load;
	regulator-system-load = <200000>;
	};
	vreg_l22a_3p0: l22 {
	regulator-name = "vreg_l22a_3p0";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};
	vreg_l23a_2p8: l23 {
	regulator-name = "vreg_l23a_2p8";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};
	vreg_l24a_3p075: l24 {
	regulator-name = "vreg_l24a_3p075";
	regulator-min-microvolt = <3075000>;
	regulator-max-microvolt = <3075000>;
	};
	vreg_l25a_1p2: l25 {
	regulator-name = "vreg_l25a_1p2";
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-allow-set-load;
	};
	vreg_l26a_0p8: l27 {
	regulator-name = "vreg_l26a_0p8";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	};
	vreg_l28a_0p925: l28 {
	regulator-name = "vreg_l28a_0p925";
	regulator-min-microvolt = <925000>;
	regulator-max-microvolt = <925000>;
	regulator-allow-set-load;
	};
	vreg_l29a_2p8: l29 {
	regulator-name = "vreg_l29a_2p8";
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
	};
	vreg_l30a_1p8: l30 {
	regulator-name = "vreg_l30a_1p8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	vreg_l32a_1p8: l32 {
	regulator-name = "vreg_l32a_1p8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	vreg_lvs1a_1p8: lvs1 {
	regulator-name = "vreg_lvs1a_1p8";
	};

	vreg_lvs2a_1p8: lvs2 {
	regulator-name = "vreg_lvs2a_1p8";
	};
	};
	};

	&sdhc2 {
	/* External SD card */
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
	cd-gpios = <&msmgpio 38 0x1>;
	vmmc-supply = <&vreg_l21a_2p95>;
	vqmmc-supply = <&vreg_l13a_2p95>;
	status = "okay";
	};

	+&q6asmdai {
	+ dai@0 {
	+ reg = <0>;
	+ };
	+
	+ dai@1 {
	+ reg = <1>;
	+ };
	+
	+ dai@2 {
	+ reg = <2>;
	+ };
	+};
	+
	&sound {
	compatible = "qcom,apq8096-sndcard";
	model = "DB820c";
	- audio-routing = "RX_BIAS", "MCLK";
	+ audio-routing = "RX_BIAS", "MCLK",
	+ "MM_DL1", "MultiMedia1 Playback",
	+ "MM_DL2", "MultiMedia2 Playback",
	+ "MultiMedia3 Capture", "MM_UL3";

	mm1-dai-link {
	link-name = "MultiMedia1";
	cpu {
	sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
	};
	};

	mm2-dai-link {
	link-name = "MultiMedia2";
	cpu {
	sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
	};
	};

	mm3-dai-link {
	link-name = "MultiMedia3";
	cpu {
	sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
	};
	};

	hdmi-dai-link {
	link-name = "HDMI";
	cpu {
	sound-dai = <&q6afedai HDMI_RX>;
	};

	platform {
	sound-dai = <&q6routing>;
	};

	codec {
	sound-dai = <&hdmi 0>;
	};
	};

	slim-dai-link {
	link-name = "SLIM Playback";
	cpu {
	sound-dai = <&q6afedai SLIMBUS_6_RX>;
	};

	platform {
	sound-dai = <&q6routing>;
	};

	codec {
	sound-dai = <&wcd9335 6>;
	};
	};

	slimcap-dai-link {
	link-name = "SLIM Capture";
	cpu {
	sound-dai = <&q6afedai SLIMBUS_0_TX>;
	};

	platform {
	sound-dai = <&q6routing>;
	};

	codec {
	sound-dai = <&wcd9335 1>;
	};
	};
	};

	&spmi_bus {
	pmic@0 {
	pon@800 {
	resin {
	compatible = "qcom,pm8941-resin";
	interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
	debounce = <15625>;
	bias-pull-up;
	linux,code = <KEY_VOLUMEDOWN>;
	};
	};
	};
	};

	&ufsphy {
	status = "okay";

	vdda-phy-supply = <&vreg_l28a_0p925>;
	vdda-pll-supply = <&vreg_l12a_1p8>;
	-
	- vdda-phy-max-microamp = <18380>;
	- vdda-pll-max-microamp = <9440>;
	-
	vddp-ref-clk-supply = <&vreg_l25a_1p2>;
	- vddp-ref-clk-max-microamp = <100>;
	- vddp-ref-clk-always-on;
	};

	&ufshc {
	status = "okay";

	vcc-supply = <&vreg_l20a_2p95>;
	vccq-supply = <&vreg_l25a_1p2>;
	vccq2-supply = <&vreg_s4a_1p8>;

	vcc-max-microamp = <600000>;
	vccq-max-microamp = <450000>;
	vccq2-max-microamp = <450000>;
	};

	&usb2 {
	status = "okay";
	extcon = <&usb2_id>;

	dwc3@7600000 {
	extcon = <&usb2_id>;
	dr_mode = "otg";
	maximum-speed = "high-speed";
	};
	};

	&usb3 {
	status = "okay";
	extcon = <&usb3_id>;

	dwc3@6a00000 {
	extcon = <&usb3_id>;
	dr_mode = "otg";
	};
	};

	&usb3phy {
	status = "okay";

	vdda-phy-supply = <&vreg_l28a_0p925>;
	vdda-pll-supply = <&vreg_l12a_1p8>;

	};

	&wcd9335 {
	clock-names = "mclk", "slimbus";
	clocks = <&div1_mclk>,
	<&rpmcc RPM_SMD_BB_CLK1>;

	vdd-buck-supply = <&vreg_s4a_1p8>;
	vdd-buck-sido-supply = <&vreg_s4a_1p8>;
	vdd-tx-supply = <&vreg_s4a_1p8>;
	vdd-rx-supply = <&vreg_s4a_1p8>;
	vdd-io-supply = <&vreg_s4a_1p8>;
	};
	diff --git a/sys/gnu/dts/arm64/qcom/ipq6018-cp01-c1.dts b/sys/gnu/dts/arm64/qcom/ipq6018-cp01-c1.dts
	new file mode 100644
	index 000000000000..b31117a93995
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/qcom/ipq6018-cp01-c1.dts
	@@ -0,0 +1,64 @@
	+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
	+/*
	+ * IPQ6018 CP01 board device tree source
	+ *
	+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
	+ */
	+
	+/dts-v1/;
	+
	+#include "ipq6018.dtsi"
	+
	+/ {
	+ model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
	+ compatible = "qcom,ipq6018-cp01", "qcom,ipq6018";
	+
	+ aliases {
	+ serial0 = &blsp1_uart3;
	+ };
	+
	+ chosen {
	+ stdout-path = "serial0:115200n8";
	+ bootargs-append = " swiotlb=1";
	+ };
	+};
	+
	+&blsp1_uart3 {
	+ pinctrl-0 = <&serial_3_pins>;
	+ pinctrl-names = "default";
	+ status = "ok";
	+};
	+
	+&i2c_1 {
	+ pinctrl-0 = <&i2c_1_pins>;
	+ pinctrl-names = "default";
	+ status = "ok";
	+};
	+
	+&spi_0 {
	+ cs-select = <0>;
	+ status = "ok";
	+
	+ m25p80@0 {
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ reg = <0>;
	+ compatible = "n25q128a11";
	+ spi-max-frequency = <50000000>;
	+ };
	+};
	+
	+&tlmm {
	+ i2c_1_pins: i2c-1-pins {
	+ pins = "gpio42", "gpio43";
	+ function = "blsp2_i2c";
	+ drive-strength = <8>;
	+ };
	+
	+ spi_0_pins: spi-0-pins {
	+ pins = "gpio38", "gpio39", "gpio40", "gpio41";
	+ function = "blsp0_spi";
	+ drive-strength = <8>;
	+ bias-pull-down;
	+ };
	+};
	diff --git a/sys/gnu/dts/arm64/qcom/ipq6018.dtsi b/sys/gnu/dts/arm64/qcom/ipq6018.dtsi
	new file mode 100644
	index 000000000000..1aa8d8579463
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/qcom/ipq6018.dtsi
	@@ -0,0 +1,443 @@
	+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
	+/*
	+ * IPQ6018 SoC device tree source
	+ *
	+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
	+ */
	+
	+#include <dt-bindings/interrupt-controller/arm-gic.h>
	+#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
	+#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
	+
	+/ {
	+ #address-cells = <2>;
	+ #size-cells = <2>;
	+ interrupt-parent = <&intc>;
	+
	+ clocks {
	+ sleep_clk: sleep-clk {
	+ compatible = "fixed-clock";
	+ clock-frequency = <32000>;
	+ #clock-cells = <0>;
	+ };
	+
	+ xo: xo {
	+ compatible = "fixed-clock";
	+ clock-frequency = <24000000>;
	+ #clock-cells = <0>;
	+ };
	+ };
	+
	+ cpus: cpus {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ CPU0: cpu@0 {
	+ device_type = "cpu";
	+ compatible = "arm,cortex-a53";
	+ reg = <0x0>;
	+ enable-method = "psci";
	+ next-level-cache = <&L2_0>;
	+ };
	+
	+ CPU1: cpu@1 {
	+ device_type = "cpu";
	+ compatible = "arm,cortex-a53";
	+ enable-method = "psci";
	+ reg = <0x1>;
	+ next-level-cache = <&L2_0>;
	+ };
	+
	+ CPU2: cpu@2 {
	+ device_type = "cpu";
	+ compatible = "arm,cortex-a53";
	+ enable-method = "psci";
	+ reg = <0x2>;
	+ next-level-cache = <&L2_0>;
	+ };
	+
	+ CPU3: cpu@3 {
	+ device_type = "cpu";
	+ compatible = "arm,cortex-a53";
	+ enable-method = "psci";
	+ reg = <0x3>;
	+ next-level-cache = <&L2_0>;
	+ };
	+
	+ L2_0: l2-cache {
	+ compatible = "cache";
	+ cache-level = <0x2>;
	+ };
	+ };
	+
	+ firmware {
	+ scm {
	+ compatible = "qcom,scm";
	+ };
	+ };
	+
	+ tcsr_mutex: hwlock {
	+ compatible = "qcom,tcsr-mutex";
	+ syscon = <&tcsr_mutex_regs 0 0x80>;
	+ #hwlock-cells = <1>;
	+ };
	+
	+ pmuv8: pmu {
	+ compatible = "arm,cortex-a53-pmu";
	+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) \|
	+ IRQ_TYPE_LEVEL_HIGH)>;
	+ };
	+
	+ psci: psci {
	+ compatible = "arm,psci-1.0";
	+ method = "smc";
	+ };
	+
	+ reserved-memory {
	+ #address-cells = <2>;
	+ #size-cells = <2>;
	+ ranges;
	+
	+ tz: tz@48500000 {
	+ reg = <0x0 0x48500000 0x0 0x00200000>;
	+ no-map;
	+ };
	+
	+ smem_region: memory@4aa00000 {
	+ reg = <0x0 0x4aa00000 0x0 0x00100000>;
	+ no-map;
	+ };
	+
	+ q6_region: memory@4ab00000 {
	+ reg = <0x0 0x4ab00000 0x0 0x02800000>;
	+ no-map;
	+ };
	+ };
	+
	+ smem {
	+ compatible = "qcom,smem";
	+ memory-region = <&smem_region>;
	+ hwlocks = <&tcsr_mutex 0>;
	+ };
	+
	+ soc: soc {
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0 0 0 0xffffffff>;
	+ dma-ranges;
	+ compatible = "simple-bus";
	+
	+ prng: qrng@e1000 {
	+ compatible = "qcom,prng-ee";
	+ reg = <0xe3000 0x1000>;
	+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
	+ clock-names = "core";
	+ };
	+
	+ cryptobam: dma@704000 {
	+ compatible = "qcom,bam-v1.7.0";
	+ reg = <0x00704000 0x20000>;
	+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
	+ clock-names = "bam_clk";
	+ #dma-cells = <1>;
	+ qcom,ee = <1>;
	+ qcom,controlled-remotely = <1>;
	+ qcom,config-pipe-trust-reg = <0>;
	+ };
	+
	+ crypto: crypto@73a000 {
	+ compatible = "qcom,crypto-v5.1";
	+ reg = <0x0073a000 0x6000>;
	+ clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
	+ <&gcc GCC_CRYPTO_AXI_CLK>,
	+ <&gcc GCC_CRYPTO_CLK>;
	+ clock-names = "iface", "bus", "core";
	+ dmas = <&cryptobam 2>, <&cryptobam 3>;
	+ dma-names = "rx", "tx";
	+ };
	+
	+ tlmm: pinctrl@1000000 {
	+ compatible = "qcom,ipq6018-pinctrl";
	+ reg = <0x01000000 0x300000>;
	+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	+ gpio-controller;
	+ #gpio-cells = <2>;
	+ gpio-ranges = <&tlmm 0 80>;
	+ interrupt-controller;
	+ #interrupt-cells = <2>;
	+
	+ serial_3_pins: serial3-pinmux {
	+ pins = "gpio44", "gpio45";
	+ function = "blsp2_uart";
	+ drive-strength = <8>;
	+ bias-pull-down;
	+ };
	+ };
	+
	+ gcc: gcc@1800000 {
	+ compatible = "qcom,gcc-ipq6018";
	+ reg = <0x01800000 0x80000>;
	+ clocks = <&xo>, <&sleep_clk>;
	+ clock-names = "xo", "sleep_clk";
	+ #clock-cells = <1>;
	+ #reset-cells = <1>;
	+ };
	+
	+ tcsr_mutex_regs: syscon@1905000 {
	+ compatible = "syscon";
	+ reg = <0x01905000 0x8000>;
	+ };
	+
	+ tcsr_q6: syscon@1945000 {
	+ compatible = "syscon";
	+ reg = <0x01945000 0xe000>;
	+ };
	+
	+ blsp_dma: dma@7884000 {
	+ compatible = "qcom,bam-v1.7.0";
	+ reg = <0x07884000 0x2b000>;
	+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
	+ clock-names = "bam_clk";
	+ #dma-cells = <1>;
	+ qcom,ee = <0>;
	+ };
	+
	+ blsp1_uart3: serial@78b1000 {
	+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	+ reg = <0x078b1000 0x200>;
	+ interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
	+ <&gcc GCC_BLSP1_AHB_CLK>;
	+ clock-names = "core", "iface";
	+ status = "disabled";
	+ };
	+
	+ spi_0: spi@78b5000 {
	+ compatible = "qcom,spi-qup-v2.2.1";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ reg = <0x078b5000 0x600>;
	+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	+ spi-max-frequency = <50000000>;
	+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
	+ <&gcc GCC_BLSP1_AHB_CLK>;
	+ clock-names = "core", "iface";
	+ dmas = <&blsp_dma 12>, <&blsp_dma 13>;
	+ dma-names = "tx", "rx";
	+ status = "disabled";
	+ };
	+
	+ spi_1: spi@78b6000 {
	+ compatible = "qcom,spi-qup-v2.2.1";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ reg = <0x078b6000 0x600>;
	+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	+ spi-max-frequency = <50000000>;
	+ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
	+ <&gcc GCC_BLSP1_AHB_CLK>;
	+ clock-names = "core", "iface";
	+ dmas = <&blsp_dma 14>, <&blsp_dma 15>;
	+ dma-names = "tx", "rx";
	+ status = "disabled";
	+ };
	+
	+ i2c_0: i2c@78b6000 {
	+ compatible = "qcom,i2c-qup-v2.2.1";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ reg = <0x078b6000 0x600>;
	+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
	+ clock-names = "iface", "core";
	+ clock-frequency = <400000>;
	+ dmas = <&blsp_dma 15>, <&blsp_dma 14>;
	+ dma-names = "rx", "tx";
	+ status = "disabled";
	+ };
	+
	+ i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */
	+ compatible = "qcom,i2c-qup-v2.2.1";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ reg = <0x078b7000 0x600>;
	+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	+ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
	+ clock-names = "iface", "core";
	+ clock-frequency = <400000>;
	+ dmas = <&blsp_dma 17>, <&blsp_dma 16>;
	+ dma-names = "rx", "tx";
	+ status = "disabled";
	+ };
	+
	+ intc: interrupt-controller@b000000 {
	+ compatible = "qcom,msm-qgic2";
	+ interrupt-controller;
	+ #interrupt-cells = <0x3>;
	+ reg = <0x0b000000 0x1000>, /GICD/
	+ <0x0b002000 0x1000>, /GICC/
	+ <0x0b001000 0x1000>, /GICH/
	+ <0x0b004000 0x1000>; /GICV/
	+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	+ };
	+
	+ watchdog@b017000 {
	+ compatible = "qcom,kpss-wdt";
	+ interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
	+ reg = <0x0b017000 0x40>;
	+ clocks = <&sleep_clk>;
	+ timeout-sec = <10>;
	+ };
	+
	+ apcs_glb: mailbox@b111000 {
	+ compatible = "qcom,ipq8074-apcs-apps-global";
	+ reg = <0x0b111000 0xc>;
	+
	+ #mbox-cells = <1>;
	+ };
	+
	+ timer {
	+ compatible = "arm,armv8-timer";
	+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	+ };
	+
	+ timer@b120000 {
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges;
	+ compatible = "arm,armv7-timer-mem";
	+ reg = <0x0b120000 0x1000>;
	+ clock-frequency = <19200000>;
	+
	+ frame@b120000 {
	+ frame-number = <0>;
	+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0b121000 0x1000>,
	+ <0x0b122000 0x1000>;
	+ };
	+
	+ frame@b123000 {
	+ frame-number = <1>;
	+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0xb123000 0x1000>;
	+ status = "disabled";
	+ };
	+
	+ frame@b124000 {
	+ frame-number = <2>;
	+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0b124000 0x1000>;
	+ status = "disabled";
	+ };
	+
	+ frame@b125000 {
	+ frame-number = <3>;
	+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0b125000 0x1000>;
	+ status = "disabled";
	+ };
	+
	+ frame@b126000 {
	+ frame-number = <4>;
	+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0b126000 0x1000>;
	+ status = "disabled";
	+ };
	+
	+ frame@b127000 {
	+ frame-number = <5>;
	+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0b127000 0x1000>;
	+ status = "disabled";
	+ };
	+
	+ frame@b128000 {
	+ frame-number = <6>;
	+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0b128000 0x1000>;
	+ status = "disabled";
	+ };
	+ };
	+
	+ q6v5_wcss: remoteproc@cd00000 {
	+ compatible = "qcom,ipq8074-wcss-pil";
	+ reg = <0x0cd00000 0x4040>,
	+ <0x004ab000 0x20>;
	+ reg-names = "qdsp6",
	+ "rmb";
	+ interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
	+ <&wcss_smp2p_in 0 0>,
	+ <&wcss_smp2p_in 1 0>,
	+ <&wcss_smp2p_in 2 0>,
	+ <&wcss_smp2p_in 3 0>;
	+ interrupt-names = "wdog",
	+ "fatal",
	+ "ready",
	+ "handover",
	+ "stop-ack";
	+
	+ resets = <&gcc GCC_WCSSAON_RESET>,
	+ <&gcc GCC_WCSS_BCR>,
	+ <&gcc GCC_WCSS_Q6_BCR>;
	+
	+ reset-names = "wcss_aon_reset",
	+ "wcss_reset",
	+ "wcss_q6_reset";
	+
	+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
	+ clock-names = "prng";
	+
	+ qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
	+
	+ qcom,smem-states = <&wcss_smp2p_out 0>,
	+ <&wcss_smp2p_out 1>;
	+ qcom,smem-state-names = "shutdown",
	+ "stop";
	+
	+ memory-region = <&q6_region>;
	+
	+ glink-edge {
	+ interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
	+ qcom,remote-pid = <1>;
	+ mboxes = <&apcs_glb 8>;
	+
	+ qrtr_requests {
	+ qcom,glink-channels = "IPCRTR";
	+ };
	+ };
	+ };
	+
	+ };
	+
	+ wcss: wcss-smp2p {
	+ compatible = "qcom,smp2p";
	+ qcom,smem = <435>, <428>;
	+
	+ interrupt-parent = <&intc>;
	+ interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;
	+
	+ mboxes = <&apcs_glb 9>;
	+
	+ qcom,local-pid = <0>;
	+ qcom,remote-pid = <1>;
	+
	+ wcss_smp2p_out: master-kernel {
	+ qcom,entry-name = "master-kernel";
	+ #qcom,smem-state-cells = <1>;
	+ };
	+
	+ wcss_smp2p_in: slave-kernel {
	+ qcom,entry-name = "slave-kernel";
	+ interrupt-controller;
	+ #interrupt-cells = <2>;
	+ };
	+ };
	+};
	diff --git a/sys/gnu/dts/arm64/qcom/ipq8074.dtsi b/sys/gnu/dts/arm64/qcom/ipq8074.dtsi
	index 67ee5f560104..2b31823d3ccd 100644
	--- a/sys/gnu/dts/arm64/qcom/ipq8074.dtsi
	+++ b/sys/gnu/dts/arm64/qcom/ipq8074.dtsi
	@@ -1,495 +1,496 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (c) 2017, The Linux Foundation. All rights reserved.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/qcom,gcc-ipq8074.h>

	/ {
	model = "Qualcomm Technologies, Inc. IPQ8074";
	compatible = "qcom,ipq8074";

	soc: soc {
	#address-cells = <0x1>;
	#size-cells = <0x1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	tlmm: pinctrl@1000000 {
	compatible = "qcom,ipq8074-pinctrl";
	reg = <0x1000000 0x300000>;
	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	+ gpio-ranges = <&tlmm 0 0 70>;
	#gpio-cells = <0x2>;
	interrupt-controller;
	#interrupt-cells = <0x2>;

	serial_4_pins: serial4-pinmux {
	pins = "gpio23", "gpio24";
	function = "blsp4_uart1";
	drive-strength = <8>;
	bias-disable;
	};

	i2c_0_pins: i2c-0-pinmux {
	pins = "gpio42", "gpio43";
	function = "blsp1_i2c";
	drive-strength = <8>;
	bias-disable;
	};

	spi_0_pins: spi-0-pins {
	pins = "gpio38", "gpio39", "gpio40", "gpio41";
	function = "blsp0_spi";
	drive-strength = <8>;
	bias-disable;
	};

	hsuart_pins: hsuart-pins {
	pins = "gpio46", "gpio47", "gpio48", "gpio49";
	function = "blsp2_uart";
	drive-strength = <8>;
	bias-disable;
	};

	qpic_pins: qpic-pins {
	pins = "gpio1", "gpio3", "gpio4",
	"gpio5", "gpio6", "gpio7",
	"gpio8", "gpio10", "gpio11",
	"gpio12", "gpio13", "gpio14",
	"gpio15", "gpio16", "gpio17";
	function = "qpic";
	drive-strength = <8>;
	bias-disable;
	};
	};

	intc: interrupt-controller@b000000 {
	compatible = "qcom,msm-qgic2";
	interrupt-controller;
	#interrupt-cells = <0x3>;
	reg = <0xb000000 0x1000>, <0xb002000 0x1000>;
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	timer@b120000 {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "arm,armv7-timer-mem";
	reg = <0xb120000 0x1000>;
	clock-frequency = <19200000>;

	frame@b120000 {
	frame-number = <0>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb121000 0x1000>,
	<0xb122000 0x1000>;
	};

	frame@b123000 {
	frame-number = <1>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb123000 0x1000>;
	status = "disabled";
	};

	frame@b124000 {
	frame-number = <2>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb124000 0x1000>;
	status = "disabled";
	};

	frame@b125000 {
	frame-number = <3>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb125000 0x1000>;
	status = "disabled";
	};

	frame@b126000 {
	frame-number = <4>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb126000 0x1000>;
	status = "disabled";
	};

	frame@b127000 {
	frame-number = <5>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb127000 0x1000>;
	status = "disabled";
	};

	frame@b128000 {
	frame-number = <6>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb128000 0x1000>;
	status = "disabled";
	};
	};

	gcc: gcc@1800000 {
	compatible = "qcom,gcc-ipq8074";
	reg = <0x1800000 0x80000>;
	#clock-cells = <0x1>;
	#reset-cells = <0x1>;
	};

	blsp1_uart5: serial@78b3000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x78b3000 0x200>;
	interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	pinctrl-0 = <&serial_4_pins>;
	pinctrl-names = "default";
	status = "disabled";
	};

	blsp_dma: dma@7884000 {
	compatible = "qcom,bam-v1.7.0";
	reg = <0x7884000 0x2b000>;
	interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	};

	blsp1_uart1: serial@78af000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x78af000 0x200>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	blsp1_uart3: serial@78b1000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x78b1000 0x200>;
	interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp_dma 4>,
	<&blsp_dma 5>;
	dma-names = "tx", "rx";
	pinctrl-0 = <&hsuart_pins>;
	pinctrl-names = "default";
	status = "disabled";
	};

	blsp1_spi1: spi@78b5000 {
	compatible = "qcom,spi-qup-v2.2.1";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x78b5000 0x600>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	spi-max-frequency = <50000000>;
	clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp_dma 12>, <&blsp_dma 13>;
	dma-names = "tx", "rx";
	pinctrl-0 = <&spi_0_pins>;
	pinctrl-names = "default";
	status = "disabled";
	};

	blsp1_i2c2: i2c@78b6000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x78b6000 0x600>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	clock-frequency = <400000>;
	dmas = <&blsp_dma 15>, <&blsp_dma 14>;
	dma-names = "rx", "tx";
	pinctrl-0 = <&i2c_0_pins>;
	pinctrl-names = "default";
	status = "disabled";
	};

	blsp1_i2c3: i2c@78b7000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x78b7000 0x600>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	clock-frequency = <100000>;
	dmas = <&blsp_dma 17>, <&blsp_dma 16>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	qpic_bam: dma@7984000 {
	compatible = "qcom,bam-v1.7.0";
	reg = <0x7984000 0x1a000>;
	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_QPIC_AHB_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	status = "disabled";
	};

	qpic_nand: nand@79b0000 {
	compatible = "qcom,ipq8074-nand";
	reg = <0x79b0000 0x10000>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&gcc GCC_QPIC_CLK>,
	<&gcc GCC_QPIC_AHB_CLK>;
	clock-names = "core", "aon";

	dmas = <&qpic_bam 0>,
	<&qpic_bam 1>,
	<&qpic_bam 2>;
	dma-names = "tx", "rx", "cmd";
	pinctrl-0 = <&qpic_pins>;
	pinctrl-names = "default";
	status = "disabled";
	};

	pcie_phy0: phy@86000 {
	compatible = "qcom,ipq8074-qmp-pcie-phy";
	reg = <0x86000 0x1000>;
	#phy-cells = <0>;
	clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
	clock-names = "pipe_clk";
	clock-output-names = "pcie20_phy0_pipe_clk";

	resets = <&gcc GCC_PCIE0_PHY_BCR>,
	<&gcc GCC_PCIE0PHY_PHY_BCR>;
	reset-names = "phy",
	"common";
	status = "disabled";
	};

	pcie0: pci@20000000 {
	compatible = "qcom,pcie-ipq8074";
	reg = <0x20000000 0xf1d
	0x20000f20 0xa8
	0x80000 0x2000
	0x20100000 0x1000>;
	reg-names = "dbi", "elbi", "parf", "config";
	device_type = "pci";
	linux,pci-domain = <0>;
	bus-range = <0x00 0xff>;
	num-lanes = <1>;
	#address-cells = <3>;
	#size-cells = <2>;

	phys = <&pcie_phy0>;
	phy-names = "pciephy";

	ranges = <0x81000000 0 0x20200000 0x20200000
	0 0x100000 /* downstream I/O */
	0x82000000 0 0x20300000 0x20300000
	0 0xd00000>; /* non-prefetchable memory */

	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &intc 0 75
	IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	<0 0 0 2 &intc 0 78
	IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	<0 0 0 3 &intc 0 79
	IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	<0 0 0 4 &intc 0 83
	IRQ_TYPE_LEVEL_HIGH>; /* int_d */

	clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
	<&gcc GCC_PCIE0_AXI_M_CLK>,
	<&gcc GCC_PCIE0_AXI_S_CLK>,
	<&gcc GCC_PCIE0_AHB_CLK>,
	<&gcc GCC_PCIE0_AUX_CLK>;

	clock-names = "iface",
	"axi_m",
	"axi_s",
	"ahb",
	"aux";
	resets = <&gcc GCC_PCIE0_PIPE_ARES>,
	<&gcc GCC_PCIE0_SLEEP_ARES>,
	<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
	<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
	<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
	<&gcc GCC_PCIE0_AHB_ARES>,
	<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
	reset-names = "pipe",
	"sleep",
	"sticky",
	"axi_m",
	"axi_s",
	"ahb",
	"axi_m_sticky";
	status = "disabled";
	};

	pcie_phy1: phy@8e000 {
	compatible = "qcom,ipq8074-qmp-pcie-phy";
	reg = <0x8e000 0x1000>;
	#phy-cells = <0>;
	clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
	clock-names = "pipe_clk";
	clock-output-names = "pcie20_phy1_pipe_clk";

	resets = <&gcc GCC_PCIE1_PHY_BCR>,
	<&gcc GCC_PCIE1PHY_PHY_BCR>;
	reset-names = "phy",
	"common";
	status = "disabled";
	};

	pcie1: pci@10000000 {
	compatible = "qcom,pcie-ipq8074";
	reg = <0x10000000 0xf1d
	0x10000f20 0xa8
	0x88000 0x2000
	0x10100000 0x1000>;
	reg-names = "dbi", "elbi", "parf", "config";
	device_type = "pci";
	linux,pci-domain = <1>;
	bus-range = <0x00 0xff>;
	num-lanes = <1>;
	#address-cells = <3>;
	#size-cells = <2>;

	phys = <&pcie_phy1>;
	phy-names = "pciephy";

	ranges = <0x81000000 0 0x10200000 0x10200000
	0 0x100000 /* downstream I/O */
	0x82000000 0 0x10300000 0x10300000
	0 0xd00000>; /* non-prefetchable memory */

	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &intc 0 142
	IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	<0 0 0 2 &intc 0 143
	IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	<0 0 0 3 &intc 0 144
	IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	<0 0 0 4 &intc 0 145
	IRQ_TYPE_LEVEL_HIGH>; /* int_d */

	clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
	<&gcc GCC_PCIE1_AXI_M_CLK>,
	<&gcc GCC_PCIE1_AXI_S_CLK>,
	<&gcc GCC_PCIE1_AHB_CLK>,
	<&gcc GCC_PCIE1_AUX_CLK>;
	clock-names = "iface",
	"axi_m",
	"axi_s",
	"ahb",
	"aux";
	resets = <&gcc GCC_PCIE1_PIPE_ARES>,
	<&gcc GCC_PCIE1_SLEEP_ARES>,
	<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
	<&gcc GCC_PCIE1_AXI_MASTER_ARES>,
	<&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
	<&gcc GCC_PCIE1_AHB_ARES>,
	<&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
	reset-names = "pipe",
	"sleep",
	"sticky",
	"axi_m",
	"axi_s",
	"ahb",
	"axi_m_sticky";
	status = "disabled";
	};
	};

	cpus {
	#address-cells = <0x1>;
	#size-cells = <0x0>;

	CPU0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0>;
	next-level-cache = <&L2_0>;
	enable-method = "psci";
	};

	CPU1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	enable-method = "psci";
	reg = <0x1>;
	next-level-cache = <&L2_0>;
	};

	CPU2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	enable-method = "psci";
	reg = <0x2>;
	next-level-cache = <&L2_0>;
	};

	CPU3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	enable-method = "psci";
	reg = <0x3>;
	next-level-cache = <&L2_0>;
	};

	L2_0: l2-cache {
	compatible = "cache";
	cache-level = <0x2>;
	};
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	pmu {
	compatible = "arm,armv8-pmuv3";
	interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	clocks {
	sleep_clk: sleep_clk {
	compatible = "fixed-clock";
	clock-frequency = <32000>;
	#clock-cells = <0>;
	};

	xo: xo {
	compatible = "fixed-clock";
	clock-frequency = <19200000>;
	#clock-cells = <0>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/qcom/msm8916-samsung-a2015-common.dtsi b/sys/gnu/dts/arm64/qcom/msm8916-samsung-a2015-common.dtsi
	index bd1eb3eeca53..43c5e0f882f1 100644
	--- a/sys/gnu/dts/arm64/qcom/msm8916-samsung-a2015-common.dtsi
	+++ b/sys/gnu/dts/arm64/qcom/msm8916-samsung-a2015-common.dtsi
	@@ -1,316 +1,324 @@
	// SPDX-License-Identifier: GPL-2.0-only

	#include "msm8916.dtsi"
	#include "pm8916.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/interrupt-controller/irq.h>

	/ {
	aliases {
	serial0 = &blsp1_uart2;
	};

	chosen {
	stdout-path = "serial0";
	};

	+ reserved-memory {
	+ /* Additional memory used by Samsung firmware modifications */
	+ tz-apps@85500000 {
	+ reg = <0x0 0x85500000 0x0 0xb00000>;
	+ no-map;
	+ };
	+ };
	+
	soc {
	sdhci@7824000 {
	status = "okay";

	vmmc-supply = <&pm8916_l8>;
	vqmmc-supply = <&pm8916_l5>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
	};

	sdhci@7864000 {
	status = "okay";

	vmmc-supply = <&pm8916_l11>;
	vqmmc-supply = <&pm8916_l12>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;

	cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>;
	};

	serial@78b0000 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&blsp1_uart2_default>;
	pinctrl-1 = <&blsp1_uart2_sleep>;
	};

	usb@78d9000 {
	status = "okay";
	extcon = <&muic>, <&muic>;

	hnp-disable;
	srp-disable;
	adp-disable;

	ulpi {
	phy {
	extcon = <&muic>;
	v1p8-supply = <&pm8916_l7>;
	v3p3-supply = <&pm8916_l13>;
	};
	};
	};

	wcnss@a21b000 {
	status = "okay";
	};

	/*
	* Attempting to enable these devices causes a "synchronous
	* external abort". Suspected cause is that the debug power
	* domain is not enabled by default on this device.
	* Disable these devices for now to avoid the crash.
	*
	* See: https://lore.kernel.org/linux-arm-msm/20190618202623.GA53651@gerhold.net/
	*/
	tpiu@820000 { status = "disabled"; };
	funnel@821000 { status = "disabled"; };
	replicator@824000 { status = "disabled"; };
	etf@825000 { status = "disabled"; };
	etr@826000 { status = "disabled"; };
	funnel@841000 { status = "disabled"; };
	debug@850000 { status = "disabled"; };
	debug@852000 { status = "disabled"; };
	debug@854000 { status = "disabled"; };
	debug@856000 { status = "disabled"; };
	etm@85c000 { status = "disabled"; };
	etm@85d000 { status = "disabled"; };
	etm@85e000 { status = "disabled"; };
	etm@85f000 { status = "disabled"; };
	};

	gpio-keys {
	compatible = "gpio-keys";

	pinctrl-names = "default";
	pinctrl-0 = <&gpio_keys_default>;

	label = "GPIO Buttons";

	volume-up {
	label = "Volume Up";
	gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_VOLUMEUP>;
	};

	home {
	label = "Home";
	gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_HOMEPAGE>;
	};
	};

	gpio-hall-sensor {
	compatible = "gpio-keys";

	pinctrl-names = "default";
	pinctrl-0 = <&gpio_hall_sensor_default>;

	label = "GPIO Hall Effect Sensor";

	hall-sensor {
	label = "Hall Effect Sensor";
	gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>;
	linux,input-type = <EV_SW>;
	linux,code = <SW_LID>;
	linux,can-disable;
	};
	};

	i2c-muic {
	compatible = "i2c-gpio";
	sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH\|GPIO_OPEN_DRAIN)>;
	scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH\|GPIO_OPEN_DRAIN)>;

	#address-cells = <1>;
	#size-cells = <0>;

	muic: sm5502@25 {
	compatible = "siliconmitus,sm5502-muic";

	reg = <0x25>;
	interrupt-parent = <&msmgpio>;
	interrupts = <12 IRQ_TYPE_EDGE_FALLING>;

	pinctrl-names = "default";
	pinctrl-0 = <&muic_int_default>;
	};
	};
	};

	&msmgpio {
	gpio_keys_default: gpio_keys_default {
	pinmux {
	function = "gpio";
	pins = "gpio107", "gpio109";
	};
	pinconf {
	pins = "gpio107", "gpio109";
	drive-strength = <2>;
	bias-pull-up;
	};
	};

	gpio_hall_sensor_default: gpio_hall_sensor_default {
	pinmux {
	function = "gpio";
	pins = "gpio52";
	};
	pinconf {
	pins = "gpio52";
	drive-strength = <2>;
	bias-disable;
	};
	};

	muic_int_default: muic_int_default {
	pinmux {
	function = "gpio";
	pins = "gpio12";
	};
	pinconf {
	pins = "gpio12";
	drive-strength = <2>;
	bias-disable;
	};
	};
	};

	&smd_rpm_regulators {
	vdd_l1_l2_l3-supply = <&pm8916_s3>;
	vdd_l4_l5_l6-supply = <&pm8916_s4>;
	vdd_l7-supply = <&pm8916_s4>;

	s1 {
	regulator-min-microvolt = <500000>;
	regulator-max-microvolt = <1300000>;
	};

	s3 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1300000>;
	};

	s4 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2100000>;
	};

	l1 {
	regulator-min-microvolt = <1225000>;
	regulator-max-microvolt = <1225000>;
	};

	l2 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};

	l3 {
	regulator-min-microvolt = <500000>;
	regulator-max-microvolt = <1287500>;
	};

	l4 {
	regulator-min-microvolt = <2050000>;
	regulator-max-microvolt = <2050000>;
	};

	l5 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	l6 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	l7 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	l8 {
	regulator-min-microvolt = <2850000>;
	regulator-max-microvolt = <2900000>;
	};

	l9 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	l10 {
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <2800000>;
	};

	l11 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2950000>;
	regulator-allow-set-load;
	regulator-system-load = <200000>;
	};

	l12 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2950000>;
	};

	l13 {
	regulator-min-microvolt = <3075000>;
	regulator-max-microvolt = <3075000>;
	};

	l14 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	};

	l15 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	};

	l16 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	};

	l17 {
	regulator-min-microvolt = <2850000>;
	regulator-max-microvolt = <2850000>;
	};

	l18 {
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <2700000>;
	};
	};

	&spmi_bus {
	pm8916@0 {
	pon@800 {
	volume-down {
	compatible = "qcom,pm8941-resin";
	interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
	bias-pull-up;
	linux,code = <KEY_VOLUMEDOWN>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/qcom/msm8916.dtsi b/sys/gnu/dts/arm64/qcom/msm8916.dtsi
	index 9f31064f2374..a88a15f2352b 100644
	--- a/sys/gnu/dts/arm64/qcom/msm8916.dtsi
	+++ b/sys/gnu/dts/arm64/qcom/msm8916.dtsi
	@@ -1,1717 +1,1736 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/qcom,gcc-msm8916.h>
	#include <dt-bindings/reset/qcom,gcc-msm8916.h>
	#include <dt-bindings/clock/qcom,rpmcc.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
	sdhc2 = &sdhc_2; /* SDC2 SD card slot */
	};

	chosen { };

	memory {
	device_type = "memory";
	/* We expect the bootloader to fill in the reg */
	reg = <0 0 0 0>;
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	tz-apps@86000000 {
	reg = <0x0 0x86000000 0x0 0x300000>;
	no-map;
	};

	smem_mem: smem_region@86300000 {
	reg = <0x0 0x86300000 0x0 0x100000>;
	no-map;
	};

	hypervisor@86400000 {
	reg = <0x0 0x86400000 0x0 0x100000>;
	no-map;
	};

	tz@86500000 {
	reg = <0x0 0x86500000 0x0 0x180000>;
	no-map;
	};

	reserved@8668000 {
	reg = <0x0 0x86680000 0x0 0x80000>;
	no-map;
	};

	rmtfs@86700000 {
	compatible = "qcom,rmtfs-mem";
	reg = <0x0 0x86700000 0x0 0xe0000>;
	no-map;

	qcom,client-id = <1>;
	};

	rfsa@867e00000 {
	reg = <0x0 0x867e0000 0x0 0x20000>;
	no-map;
	};

	mpss_mem: mpss@86800000 {
	reg = <0x0 0x86800000 0x0 0x2b00000>;
	no-map;
	};

	wcnss_mem: wcnss@89300000 {
	reg = <0x0 0x89300000 0x0 0x600000>;
	no-map;
	};

	venus_mem: venus@89900000 {
	reg = <0x0 0x89900000 0x0 0x600000>;
	no-map;
	};

	mba_mem: mba@8ea00000 {
	no-map;
	reg = <0 0x8ea00000 0 0x100000>;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	CPU0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0>;
	next-level-cache = <&L2_0>;
	enable-method = "psci";
	clocks = <&apcs>;
	operating-points-v2 = <&cpu_opp_table>;
	#cooling-cells = <2>;
	power-domains = <&CPU_PD0>;
	power-domain-names = "psci";
	};

	CPU1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x1>;
	next-level-cache = <&L2_0>;
	enable-method = "psci";
	clocks = <&apcs>;
	operating-points-v2 = <&cpu_opp_table>;
	#cooling-cells = <2>;
	power-domains = <&CPU_PD1>;
	power-domain-names = "psci";
	};

	CPU2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x2>;
	next-level-cache = <&L2_0>;
	enable-method = "psci";
	clocks = <&apcs>;
	operating-points-v2 = <&cpu_opp_table>;
	#cooling-cells = <2>;
	power-domains = <&CPU_PD2>;
	power-domain-names = "psci";
	};

	CPU3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x3>;
	next-level-cache = <&L2_0>;
	enable-method = "psci";
	clocks = <&apcs>;
	operating-points-v2 = <&cpu_opp_table>;
	#cooling-cells = <2>;
	power-domains = <&CPU_PD3>;
	power-domain-names = "psci";
	};

	L2_0: l2-cache {
	compatible = "cache";
	cache-level = <2>;
	};

	idle-states {
	entry-method = "psci";

	CPU_SLEEP_0: cpu-sleep-0 {
	compatible = "arm,idle-state";
	idle-state-name = "standalone-power-collapse";
	arm,psci-suspend-param = <0x40000002>;
	entry-latency-us = <130>;
	exit-latency-us = <150>;
	min-residency-us = <2000>;
	local-timer-stop;
	};

	CLUSTER_RET: cluster-retention {
	compatible = "domain-idle-state";
	arm,psci-suspend-param = <0x41000012>;
	entry-latency-us = <500>;
	exit-latency-us = <500>;
	min-residency-us = <2000>;
	};

	CLUSTER_PWRDN: cluster-gdhs {
	compatible = "domain-idle-state";
	arm,psci-suspend-param = <0x41000032>;
	entry-latency-us = <2000>;
	exit-latency-us = <2000>;
	min-residency-us = <6000>;
	};
	};
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";

	CPU_PD0: cpu-pd0 {
	#power-domain-cells = <0>;
	power-domains = <&CLUSTER_PD>;
	domain-idle-states = <&CPU_SLEEP_0>;
	};

	CPU_PD1: cpu-pd1 {
	#power-domain-cells = <0>;
	power-domains = <&CLUSTER_PD>;
	domain-idle-states = <&CPU_SLEEP_0>;
	};

	CPU_PD2: cpu-pd2 {
	#power-domain-cells = <0>;
	power-domains = <&CLUSTER_PD>;
	domain-idle-states = <&CPU_SLEEP_0>;
	};

	CPU_PD3: cpu-pd3 {
	#power-domain-cells = <0>;
	power-domains = <&CLUSTER_PD>;
	domain-idle-states = <&CPU_SLEEP_0>;
	};

	CLUSTER_PD: cluster-pd {
	#power-domain-cells = <0>;
	domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
	};
	};

	pmu {
	compatible = "arm,cortex-a53-pmu";
	interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)\| IRQ_TYPE_LEVEL_HIGH)>;
	};

	thermal-zones {
	cpu0_1-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 5>;

	trips {
	cpu0_1_alert0: trip-point@0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu0_1_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu0_1_alert0>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu2_3-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 4>;

	trips {
	cpu2_3_alert0: trip-point@0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu2_3_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu2_3_alert0>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	gpu-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 2>;

	trips {
	gpu_alert0: trip-point@0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	gpu_crit: gpu_crit {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	camera-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 1>;

	trips {
	cam_alert0: trip-point@0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	modem-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 0>;

	trips {
	modem_alert0: trip-point@0 {
	temperature = <85000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	};

	cpu_opp_table: cpu_opp_table {
	compatible = "operating-points-v2";
	opp-shared;

	opp-200000000 {
	opp-hz = /bits/ 64 <200000000>;
	};
	opp-400000000 {
	opp-hz = /bits/ 64 <400000000>;
	};
	opp-800000000 {
	opp-hz = /bits/ 64 <800000000>;
	};
	opp-998400000 {
	opp-hz = /bits/ 64 <998400000>;
	};
	};

	gpu_opp_table: opp_table {
	compatible = "operating-points-v2";

	opp-400000000 {
	opp-hz = /bits/ 64 <400000000>;
	};
	opp-19200000 {
	opp-hz = /bits/ 64 <19200000>;
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	clocks {
	xo_board: xo_board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <19200000>;
	};

	sleep_clk: sleep_clk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	};

	smem {
	compatible = "qcom,smem";

	memory-region = <&smem_mem>;
	qcom,rpm-msg-ram = <&rpm_msg_ram>;

	hwlocks = <&tcsr_mutex 3>;
	};

	firmware {
	scm: scm {
	compatible = "qcom,scm";
	clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
	clock-names = "core", "bus", "iface";
	#reset-cells = <1>;

	qcom,dload-mode = <&tcsr 0x6100>;
	};
	};

	soc: soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	restart@4ab000 {
	compatible = "qcom,pshold";
	reg = <0x4ab000 0x4>;
	};

	msmgpio: pinctrl@1000000 {
	compatible = "qcom,msm8916-pinctrl";
	reg = <0x1000000 0x300000>;
	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	+ gpio-ranges = <&msmgpio 0 0 122>;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gcc: clock-controller@1800000 {
	compatible = "qcom,gcc-msm8916";
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;
	reg = <0x1800000 0x80000>;
	};

	tcsr_mutex_regs: syscon@1905000 {
	compatible = "syscon";
	reg = <0x1905000 0x20000>;
	};

	tcsr: syscon@1937000 {
	compatible = "qcom,tcsr-msm8916", "syscon";
	reg = <0x1937000 0x30000>;
	};

	tcsr_mutex: hwlock {
	compatible = "qcom,tcsr-mutex";
	syscon = <&tcsr_mutex_regs 0 0x1000>;
	#hwlock-cells = <1>;
	};

	rpm_msg_ram: memory@60000 {
	compatible = "qcom,rpm-msg-ram";
	reg = <0x60000 0x8000>;
	};

	blsp1_uart1: serial@78af000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x78af000 0x200>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp_dma 1>, <&blsp_dma 0>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	a53pll: clock@b016000 {
	compatible = "qcom,msm8916-a53pll";
	reg = <0xb016000 0x40>;
	#clock-cells = <0>;
	};

	apcs: mailbox@b011000 {
	compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
	reg = <0xb011000 0x1000>;
	#mbox-cells = <1>;
	clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
	clock-names = "pll", "aux";
	#clock-cells = <0>;
	};

	blsp1_uart2: serial@78b0000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x78b0000 0x200>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp_dma 3>, <&blsp_dma 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	blsp_dma: dma@7884000 {
	compatible = "qcom,bam-v1.7.0";
	reg = <0x07884000 0x23000>;
	interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	status = "disabled";
	};

	blsp_spi1: spi@78b5000 {
	compatible = "qcom,spi-qup-v2.2.1";
	reg = <0x078b5000 0x500>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp_dma 5>, <&blsp_dma 4>;
	dma-names = "rx", "tx";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&spi1_default>;
	pinctrl-1 = <&spi1_sleep>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp_spi2: spi@78b6000 {
	compatible = "qcom,spi-qup-v2.2.1";
	reg = <0x078b6000 0x500>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp_dma 7>, <&blsp_dma 6>;
	dma-names = "rx", "tx";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&spi2_default>;
	pinctrl-1 = <&spi2_sleep>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp_spi3: spi@78b7000 {
	compatible = "qcom,spi-qup-v2.2.1";
	reg = <0x078b7000 0x500>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp_dma 9>, <&blsp_dma 8>;
	dma-names = "rx", "tx";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&spi3_default>;
	pinctrl-1 = <&spi3_sleep>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp_spi4: spi@78b8000 {
	compatible = "qcom,spi-qup-v2.2.1";
	reg = <0x078b8000 0x500>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp_dma 11>, <&blsp_dma 10>;
	dma-names = "rx", "tx";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&spi4_default>;
	pinctrl-1 = <&spi4_sleep>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp_spi5: spi@78b9000 {
	compatible = "qcom,spi-qup-v2.2.1";
	reg = <0x078b9000 0x500>;
	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp_dma 13>, <&blsp_dma 12>;
	dma-names = "rx", "tx";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&spi5_default>;
	pinctrl-1 = <&spi5_sleep>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp_spi6: spi@78ba000 {
	compatible = "qcom,spi-qup-v2.2.1";
	reg = <0x078ba000 0x500>;
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp_dma 15>, <&blsp_dma 14>;
	dma-names = "rx", "tx";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&spi6_default>;
	pinctrl-1 = <&spi6_sleep>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp_i2c2: i2c@78b6000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x078b6000 0x500>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c2_default>;
	pinctrl-1 = <&i2c2_sleep>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp_i2c4: i2c@78b8000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x078b8000 0x500>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c4_default>;
	pinctrl-1 = <&i2c4_sleep>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp_i2c6: i2c@78ba000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x078ba000 0x500>;
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c6_default>;
	pinctrl-1 = <&i2c6_sleep>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	lpass: lpass@7708000 {
	status = "disabled";
	compatible = "qcom,lpass-cpu-apq8016";
	clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
	<&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
	<&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
	<&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
	<&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
	<&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
	<&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;

	clock-names = "ahbix-clk",
	"pcnoc-mport-clk",
	"pcnoc-sway-clk",
	"mi2s-bit-clk0",
	"mi2s-bit-clk1",
	"mi2s-bit-clk2",
	"mi2s-bit-clk3";
	#sound-dai-cells = <1>;

	interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "lpass-irq-lpaif";
	reg = <0x07708000 0x10000>;
	reg-names = "lpass-lpaif";
	};

	lpass_codec: codec{
	compatible = "qcom,msm8916-wcd-digital-codec";
	reg = <0x0771c000 0x400>;
	clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
	<&gcc GCC_CODEC_DIGCODEC_CLK>;
	clock-names = "ahbix-clk", "mclk";
	#sound-dai-cells = <1>;
	};

	sdhc_1: sdhci@7824000 {
	compatible = "qcom,sdhci-msm-v4";
	reg = <0x07824900 0x11c>, <0x07824000 0x800>;
	reg-names = "hc_mem", "core_mem";

	interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hc_irq", "pwr_irq";
	clocks = <&gcc GCC_SDCC1_APPS_CLK>,
	<&gcc GCC_SDCC1_AHB_CLK>,
	<&xo_board>;
	clock-names = "core", "iface", "xo";
	mmc-ddr-1_8v;
	bus-width = <8>;
	non-removable;
	status = "disabled";
	};

	sdhc_2: sdhci@7864000 {
	compatible = "qcom,sdhci-msm-v4";
	reg = <0x07864900 0x11c>, <0x07864000 0x800>;
	reg-names = "hc_mem", "core_mem";

	interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hc_irq", "pwr_irq";
	clocks = <&gcc GCC_SDCC2_APPS_CLK>,
	<&gcc GCC_SDCC2_AHB_CLK>,
	<&xo_board>;
	clock-names = "core", "iface", "xo";
	bus-width = <4>;
	status = "disabled";
	};

	otg: usb@78d9000 {
	compatible = "qcom,ci-hdrc";
	reg = <0x78d9000 0x200>,
	<0x78d9200 0x200>;
	interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_USB_HS_AHB_CLK>,
	<&gcc GCC_USB_HS_SYSTEM_CLK>;
	clock-names = "iface", "core";
	assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
	assigned-clock-rates = <80000000>;
	resets = <&gcc GCC_USB_HS_BCR>;
	reset-names = "core";
	phy_type = "ulpi";
	dr_mode = "otg";
	ahb-burst-config = <0>;
	phy-names = "usb-phy";
	phys = <&usb_hs_phy>;
	status = "disabled";
	#reset-cells = <1>;

	ulpi {
	usb_hs_phy: phy {
	compatible = "qcom,usb-hs-phy-msm8916",
	"qcom,usb-hs-phy";
	#phy-cells = <0>;
	clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
	clock-names = "ref", "sleep";
	resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
	reset-names = "phy", "por";
	qcom,init-seq = /bits/ 8 <0x0 0x44
	0x1 0x6b 0x2 0x24 0x3 0x13>;
	};
	};
	};

	intc: interrupt-controller@b000000 {
	compatible = "qcom,msm-qgic2";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
	};

	timer@b020000 {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "arm,armv7-timer-mem";
	reg = <0xb020000 0x1000>;
	clock-frequency = <19200000>;

	frame@b021000 {
	frame-number = <0>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb021000 0x1000>,
	<0xb022000 0x1000>;
	};

	frame@b023000 {
	frame-number = <1>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb023000 0x1000>;
	status = "disabled";
	};

	frame@b024000 {
	frame-number = <2>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb024000 0x1000>;
	status = "disabled";
	};

	frame@b025000 {
	frame-number = <3>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb025000 0x1000>;
	status = "disabled";
	};

	frame@b026000 {
	frame-number = <4>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb026000 0x1000>;
	status = "disabled";
	};

	frame@b027000 {
	frame-number = <5>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb027000 0x1000>;
	status = "disabled";
	};

	frame@b028000 {
	frame-number = <6>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb028000 0x1000>;
	status = "disabled";
	};
	};

	spmi_bus: spmi@200f000 {
	compatible = "qcom,spmi-pmic-arb";
	reg = <0x200f000 0x001000>,
	<0x2400000 0x400000>,
	<0x2c00000 0x400000>,
	<0x3800000 0x200000>,
	<0x200a000 0x002100>;
	reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
	interrupt-names = "periph_irq";
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	qcom,ee = <0>;
	qcom,channel = <0>;
	#address-cells = <2>;
	#size-cells = <0>;
	interrupt-controller;
	#interrupt-cells = <4>;
	};

	rng@22000 {
	compatible = "qcom,prng";
	reg = <0x00022000 0x200>;
	clocks = <&gcc GCC_PRNG_AHB_CLK>;
	clock-names = "core";
	};

	qfprom: qfprom@5c000 {
	compatible = "qcom,qfprom";
	reg = <0x5c000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	tsens_caldata: caldata@d0 {
	reg = <0xd0 0x8>;
	};
	tsens_calsel: calsel@ec {
	reg = <0xec 0x4>;
	};
	};

	tsens: thermal-sensor@4a9000 {
	- compatible = "qcom,msm8916-tsens";
	+ compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
	reg = <0x4a9000 0x1000>, /* TM */
	<0x4a8000 0x1000>; /* SROT */
	nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
	nvmem-cell-names = "calib", "calib_sel";
	#qcom,sensors = <5>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "uplow";
	#thermal-sensor-cells = <1>;
	};

	apps_iommu: iommu@1ef0000 {
	#address-cells = <1>;
	#size-cells = <1>;
	#iommu-cells = <1>;
	compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
	ranges = <0 0x1e20000 0x40000>;
	reg = <0x1ef0000 0x3000>;
	clocks = <&gcc GCC_SMMU_CFG_CLK>,
	<&gcc GCC_APSS_TCU_CLK>;
	clock-names = "iface", "bus";
	qcom,iommu-secure-id = <17>;

	// vfe:
	iommu-ctx@3000 {
	compatible = "qcom,msm-iommu-v1-sec";
	reg = <0x3000 0x1000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	};

	// mdp_0:
	iommu-ctx@4000 {
	compatible = "qcom,msm-iommu-v1-ns";
	reg = <0x4000 0x1000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	};

	// venus_ns:
	iommu-ctx@5000 {
	compatible = "qcom,msm-iommu-v1-sec";
	reg = <0x5000 0x1000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	gpu_iommu: iommu@1f08000 {
	#address-cells = <1>;
	#size-cells = <1>;
	#iommu-cells = <1>;
	compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
	ranges = <0 0x1f08000 0x10000>;
	clocks = <&gcc GCC_SMMU_CFG_CLK>,
	<&gcc GCC_GFX_TCU_CLK>;
	clock-names = "iface", "bus";
	qcom,iommu-secure-id = <18>;

	// gfx3d_user:
	iommu-ctx@1000 {
	compatible = "qcom,msm-iommu-v1-ns";
	reg = <0x1000 0x1000>;
	interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
	};

	// gfx3d_priv:
	iommu-ctx@2000 {
	compatible = "qcom,msm-iommu-v1-ns";
	reg = <0x2000 0x1000>;
	interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	gpu@1c00000 {
	compatible = "qcom,adreno-306.0", "qcom,adreno";
	reg = <0x01c00000 0x20000>;
	reg-names = "kgsl_3d0_reg_memory";
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "kgsl_3d0_irq";
	clock-names =
	"core",
	"iface",
	"mem",
	"mem_iface",
	"alt_mem_iface",
	"gfx3d";
	clocks =
	<&gcc GCC_OXILI_GFX3D_CLK>,
	<&gcc GCC_OXILI_AHB_CLK>,
	<&gcc GCC_OXILI_GMEM_CLK>,
	<&gcc GCC_BIMC_GFX_CLK>,
	<&gcc GCC_BIMC_GPU_CLK>,
	<&gcc GFX3D_CLK_SRC>;
	power-domains = <&gcc OXILI_GDSC>;
	operating-points-v2 = <&gpu_opp_table>;
	iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
	};

	mdss: mdss@1a00000 {
	compatible = "qcom,mdss";
	reg = <0x1a00000 0x1000>,
	<0x1ac8000 0x3000>;
	reg-names = "mdss_phys", "vbif_phys";

	power-domains = <&gcc MDSS_GDSC>;

	clocks = <&gcc GCC_MDSS_AHB_CLK>,
	<&gcc GCC_MDSS_AXI_CLK>,
	<&gcc GCC_MDSS_VSYNC_CLK>;
	clock-names = "iface",
	"bus",
	"vsync";

	interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;

	interrupt-controller;
	#interrupt-cells = <1>;

	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	mdp: mdp@1a01000 {
	compatible = "qcom,mdp5";
	reg = <0x1a01000 0x89000>;
	reg-names = "mdp_phys";

	interrupt-parent = <&mdss>;
	interrupts = <0 0>;

	clocks = <&gcc GCC_MDSS_AHB_CLK>,
	<&gcc GCC_MDSS_AXI_CLK>,
	<&gcc GCC_MDSS_MDP_CLK>,
	<&gcc GCC_MDSS_VSYNC_CLK>;
	clock-names = "iface",
	"bus",
	"core",
	"vsync";

	iommus = <&apps_iommu 4>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	mdp5_intf1_out: endpoint {
	remote-endpoint = <&dsi0_in>;
	};
	};
	};
	};

	dsi0: dsi@1a98000 {
	compatible = "qcom,mdss-dsi-ctrl";
	reg = <0x1a98000 0x25c>;
	reg-names = "dsi_ctrl";

	interrupt-parent = <&mdss>;
	interrupts = <4 0>;

	assigned-clocks = <&gcc BYTE0_CLK_SRC>,
	<&gcc PCLK0_CLK_SRC>;
	assigned-clock-parents = <&dsi_phy0 0>,
	<&dsi_phy0 1>;

	clocks = <&gcc GCC_MDSS_MDP_CLK>,
	<&gcc GCC_MDSS_AHB_CLK>,
	<&gcc GCC_MDSS_AXI_CLK>,
	<&gcc GCC_MDSS_BYTE0_CLK>,
	<&gcc GCC_MDSS_PCLK0_CLK>,
	<&gcc GCC_MDSS_ESC0_CLK>;
	clock-names = "mdp_core",
	"iface",
	"bus",
	"byte",
	"pixel",
	"core";
	phys = <&dsi_phy0>;
	phy-names = "dsi-phy";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	dsi0_in: endpoint {
	remote-endpoint = <&mdp5_intf1_out>;
	};
	};

	port@1 {
	reg = <1>;
	dsi0_out: endpoint {
	};
	};
	};
	};

	dsi_phy0: dsi-phy@1a98300 {
	compatible = "qcom,dsi-phy-28nm-lp";
	reg = <0x1a98300 0xd4>,
	<0x1a98500 0x280>,
	<0x1a98780 0x30>;
	reg-names = "dsi_pll",
	"dsi_phy",
	"dsi_phy_regulator";

	#clock-cells = <1>;
	#phy-cells = <0>;

	clocks = <&gcc GCC_MDSS_AHB_CLK>,
	<&xo_board>;
	clock-names = "iface", "ref";
	};
	};


	hexagon@4080000 {
	compatible = "qcom,q6v5-pil";
	reg = <0x04080000 0x100>,
	<0x04020000 0x040>;

	reg-names = "qdsp6", "rmb";

	interrupts-extended = <&intc 0 24 1>,
	<&hexagon_smp2p_in 0 0>,
	<&hexagon_smp2p_in 1 0>,
	<&hexagon_smp2p_in 2 0>,
	<&hexagon_smp2p_in 3 0>;
	interrupt-names = "wdog", "fatal", "ready",
	"handover", "stop-ack";

	clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
	<&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
	<&gcc GCC_BOOT_ROM_AHB_CLK>,
	<&xo_board>;
	clock-names = "iface", "bus", "mem", "xo";

	qcom,smem-states = <&hexagon_smp2p_out 0>;
	qcom,smem-state-names = "stop";

	resets = <&scm 0>;
	reset-names = "mss_restart";

	cx-supply = <&pm8916_s1>;
	mx-supply = <&pm8916_l3>;
	pll-supply = <&pm8916_l7>;

	qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;

	status = "disabled";

	mba {
	memory-region = <&mba_mem>;
	};

	mpss {
	memory-region = <&mpss_mem>;
	};

	smd-edge {
	interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;

	qcom,smd-edge = <0>;
	qcom,ipc = <&apcs 8 12>;
	qcom,remote-pid = <1>;

	label = "hexagon";
	+
	+ fastrpc {
	+ compatible = "qcom,fastrpc";
	+ qcom,smd-channels = "fastrpcsmd-apps-dsp";
	+ label = "adsp";
	+
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ cb@1{
	+ compatible = "qcom,fastrpc-compute-cb";
	+ reg = <1>;
	+ };
	+ };
	};
	};

	pronto: wcnss@a21b000 {
	compatible = "qcom,pronto-v2-pil", "qcom,pronto";
	reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
	reg-names = "ccu", "dxe", "pmu";

	memory-region = <&wcnss_mem>;

	interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
	<&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	<&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	<&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	<&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";

	vddmx-supply = <&pm8916_l3>;
	vddpx-supply = <&pm8916_l7>;

	qcom,state = <&wcnss_smp2p_out 0>;
	qcom,state-names = "stop";

	pinctrl-names = "default";
	pinctrl-0 = <&wcnss_pin_a>;

	status = "disabled";

	iris {
	compatible = "qcom,wcn3620";

	clocks = <&rpmcc RPM_SMD_RF_CLK2>;
	clock-names = "xo";

	vddxo-supply = <&pm8916_l7>;
	vddrfa-supply = <&pm8916_s3>;
	vddpa-supply = <&pm8916_l9>;
	vdddig-supply = <&pm8916_l5>;
	};

	smd-edge {
	interrupts = <0 142 1>;

	qcom,ipc = <&apcs 8 17>;
	qcom,smd-edge = <6>;
	qcom,remote-pid = <4>;

	label = "pronto";

	wcnss {
	compatible = "qcom,wcnss";
	qcom,smd-channels = "WCNSS_CTRL";

	qcom,mmio = <&pronto>;

	bt {
	compatible = "qcom,wcnss-bt";
	};

	wifi {
	compatible = "qcom,wcnss-wlan";

	interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
	<0 146 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "tx", "rx";

	qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
	qcom,smem-state-names = "tx-enable", "tx-rings-empty";
	};
	};
	};
	};

	tpiu@820000 {
	compatible = "arm,coresight-tpiu", "arm,primecell";
	reg = <0x820000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	port {
	tpiu_in: endpoint {
	remote-endpoint = <&replicator_out1>;
	};
	};
	};
	};

	funnel@821000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0x821000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	/*
	* Not described input ports:
	* 0 - connected to Resource and Power Manger CPU ETM
	* 1 - not-connected
	* 2 - connected to Modem CPU ETM
	* 3 - not-connected
	* 5 - not-connected
	* 6 - connected trought funnel to Wireless CPU ETM
	* 7 - connected to STM component
	*/

	port@4 {
	reg = <4>;
	funnel0_in4: endpoint {
	remote-endpoint = <&funnel1_out>;
	};
	};
	};

	out-ports {
	port {
	funnel0_out: endpoint {
	remote-endpoint = <&etf_in>;
	};
	};
	};
	};

	replicator@824000 {
	compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
	reg = <0x824000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	out-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	replicator_out0: endpoint {
	remote-endpoint = <&etr_in>;
	};
	};
	port@1 {
	reg = <1>;
	replicator_out1: endpoint {
	remote-endpoint = <&tpiu_in>;
	};
	};
	};

	in-ports {
	port {
	replicator_in: endpoint {
	remote-endpoint = <&etf_out>;
	};
	};
	};
	};

	etf@825000 {
	compatible = "arm,coresight-tmc", "arm,primecell";
	reg = <0x825000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	port {
	etf_in: endpoint {
	remote-endpoint = <&funnel0_out>;
	};
	};
	};

	out-ports {
	port {
	etf_out: endpoint {
	remote-endpoint = <&replicator_in>;
	};
	};
	};
	};

	etr@826000 {
	compatible = "arm,coresight-tmc", "arm,primecell";
	reg = <0x826000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	port {
	etr_in: endpoint {
	remote-endpoint = <&replicator_out0>;
	};
	};
	};
	};

	funnel@841000 { /* APSS funnel only 4 inputs are used */
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0x841000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	funnel1_in0: endpoint {
	remote-endpoint = <&etm0_out>;
	};
	};
	port@1 {
	reg = <1>;
	funnel1_in1: endpoint {
	remote-endpoint = <&etm1_out>;
	};
	};
	port@2 {
	reg = <2>;
	funnel1_in2: endpoint {
	remote-endpoint = <&etm2_out>;
	};
	};
	port@3 {
	reg = <3>;
	funnel1_in3: endpoint {
	remote-endpoint = <&etm3_out>;
	};
	};
	};

	out-ports {
	port {
	funnel1_out: endpoint {
	remote-endpoint = <&funnel0_in4>;
	};
	};
	};
	};

	debug@850000 {
	compatible = "arm,coresight-cpu-debug","arm,primecell";
	reg = <0x850000 0x1000>;
	clocks = <&rpmcc RPM_QDSS_CLK>;
	clock-names = "apb_pclk";
	cpu = <&CPU0>;
	};

	debug@852000 {
	compatible = "arm,coresight-cpu-debug","arm,primecell";
	reg = <0x852000 0x1000>;
	clocks = <&rpmcc RPM_QDSS_CLK>;
	clock-names = "apb_pclk";
	cpu = <&CPU1>;
	};

	debug@854000 {
	compatible = "arm,coresight-cpu-debug","arm,primecell";
	reg = <0x854000 0x1000>;
	clocks = <&rpmcc RPM_QDSS_CLK>;
	clock-names = "apb_pclk";
	cpu = <&CPU2>;
	};

	debug@856000 {
	compatible = "arm,coresight-cpu-debug","arm,primecell";
	reg = <0x856000 0x1000>;
	clocks = <&rpmcc RPM_QDSS_CLK>;
	clock-names = "apb_pclk";
	cpu = <&CPU3>;
	};

	etm@85c000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0x85c000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";
	+ arm,coresight-loses-context-with-cpu;

	cpu = <&CPU0>;

	out-ports {
	port {
	etm0_out: endpoint {
	remote-endpoint = <&funnel1_in0>;
	};
	};
	};
	};

	etm@85d000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0x85d000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";
	+ arm,coresight-loses-context-with-cpu;

	cpu = <&CPU1>;

	out-ports {
	port {
	etm1_out: endpoint {
	remote-endpoint = <&funnel1_in1>;
	};
	};
	};
	};

	etm@85e000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0x85e000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";
	+ arm,coresight-loses-context-with-cpu;

	cpu = <&CPU2>;

	out-ports {
	port {
	etm2_out: endpoint {
	remote-endpoint = <&funnel1_in2>;
	};
	};
	};
	};

	etm@85f000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0x85f000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";
	+ arm,coresight-loses-context-with-cpu;

	cpu = <&CPU3>;

	out-ports {
	port {
	etm3_out: endpoint {
	remote-endpoint = <&funnel1_in3>;
	};
	};
	};
	};

	venus: video-codec@1d00000 {
	compatible = "qcom,msm8916-venus";
	reg = <0x01d00000 0xff000>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&gcc VENUS_GDSC>;
	clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
	<&gcc GCC_VENUS0_AHB_CLK>,
	<&gcc GCC_VENUS0_AXI_CLK>;
	clock-names = "core", "iface", "bus";
	iommus = <&apps_iommu 5>;
	memory-region = <&venus_mem>;
	status = "okay";

	video-decoder {
	compatible = "venus-decoder";
	};

	video-encoder {
	compatible = "venus-encoder";
	};
	};

	camss: camss@1b00000 {
	compatible = "qcom,msm8916-camss";
	reg = <0x1b0ac00 0x200>,
	<0x1b00030 0x4>,
	<0x1b0b000 0x200>,
	<0x1b00038 0x4>,
	<0x1b08000 0x100>,
	<0x1b08400 0x100>,
	<0x1b0a000 0x500>,
	<0x1b00020 0x10>,
	<0x1b10000 0x1000>;
	reg-names = "csiphy0",
	"csiphy0_clk_mux",
	"csiphy1",
	"csiphy1_clk_mux",
	"csid0",
	"csid1",
	"ispif",
	"csi_clk_mux",
	"vfe0";
	interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "csiphy0",
	"csiphy1",
	"csid0",
	"csid1",
	"ispif",
	"vfe0";
	power-domains = <&gcc VFE_GDSC>;
	clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
	<&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
	<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
	<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
	<&gcc GCC_CAMSS_CSI0_AHB_CLK>,
	<&gcc GCC_CAMSS_CSI0_CLK>,
	<&gcc GCC_CAMSS_CSI0PHY_CLK>,
	<&gcc GCC_CAMSS_CSI0PIX_CLK>,
	<&gcc GCC_CAMSS_CSI0RDI_CLK>,
	<&gcc GCC_CAMSS_CSI1_AHB_CLK>,
	<&gcc GCC_CAMSS_CSI1_CLK>,
	<&gcc GCC_CAMSS_CSI1PHY_CLK>,
	<&gcc GCC_CAMSS_CSI1PIX_CLK>,
	<&gcc GCC_CAMSS_CSI1RDI_CLK>,
	<&gcc GCC_CAMSS_AHB_CLK>,
	<&gcc GCC_CAMSS_VFE0_CLK>,
	<&gcc GCC_CAMSS_CSI_VFE0_CLK>,
	<&gcc GCC_CAMSS_VFE_AHB_CLK>,
	<&gcc GCC_CAMSS_VFE_AXI_CLK>;
	clock-names = "top_ahb",
	"ispif_ahb",
	"csiphy0_timer",
	"csiphy1_timer",
	"csi0_ahb",
	"csi0",
	"csi0_phy",
	"csi0_pix",
	"csi0_rdi",
	"csi1_ahb",
	"csi1",
	"csi1_phy",
	"csi1_pix",
	"csi1_rdi",
	"ahb",
	"vfe0",
	"csi_vfe0",
	"vfe_ahb",
	"vfe_axi";
	vdda-supply = <&pm8916_l2>;
	iommus = <&apps_iommu 3>;
	status = "disabled";
	ports {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};
	};

	smd {
	compatible = "qcom,smd";

	rpm {
	interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
	qcom,ipc = <&apcs 8 0>;
	qcom,smd-edge = <15>;

	rpm_requests {
	compatible = "qcom,rpm-msm8916";
	qcom,smd-channels = "rpm_requests";

	rpmcc: qcom,rpmcc {
	compatible = "qcom,rpmcc-msm8916";
	#clock-cells = <1>;
	};

	smd_rpm_regulators: pm8916-regulators {
	compatible = "qcom,rpm-pm8916-regulators";

	pm8916_s1: s1 {};
	pm8916_s3: s3 {};
	pm8916_s4: s4 {};

	pm8916_l1: l1 {};
	pm8916_l2: l2 {};
	pm8916_l3: l3 {};
	pm8916_l4: l4 {};
	pm8916_l5: l5 {};
	pm8916_l6: l6 {};
	pm8916_l7: l7 {};
	pm8916_l8: l8 {};
	pm8916_l9: l9 {};
	pm8916_l10: l10 {};
	pm8916_l11: l11 {};
	pm8916_l12: l12 {};
	pm8916_l13: l13 {};
	pm8916_l14: l14 {};
	pm8916_l15: l15 {};
	pm8916_l16: l16 {};
	pm8916_l17: l17 {};
	pm8916_l18: l18 {};
	};
	};
	};
	};

	hexagon-smp2p {
	compatible = "qcom,smp2p";
	qcom,smem = <435>, <428>;

	interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;

	qcom,ipc = <&apcs 8 14>;

	qcom,local-pid = <0>;
	qcom,remote-pid = <1>;

	hexagon_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";

	#qcom,smem-state-cells = <1>;
	};

	hexagon_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";

	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	wcnss-smp2p {
	compatible = "qcom,smp2p";
	qcom,smem = <451>, <431>;

	interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;

	qcom,ipc = <&apcs 8 18>;

	qcom,local-pid = <0>;
	qcom,remote-pid = <4>;

	wcnss_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";

	#qcom,smem-state-cells = <1>;
	};

	wcnss_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";

	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	smsm {
	compatible = "qcom,smsm";

	#address-cells = <1>;
	#size-cells = <0>;

	qcom,ipc-1 = <&apcs 8 13>;
	qcom,ipc-3 = <&apcs 8 19>;

	apps_smsm: apps@0 {
	reg = <0>;

	#qcom,smem-state-cells = <1>;
	};

	hexagon_smsm: hexagon@1 {
	reg = <1>;
	interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	wcnss_smsm: wcnss@6 {
	reg = <6>;
	interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};
	};

	#include "msm8916-pins.dtsi"
	diff --git a/sys/gnu/dts/arm64/qcom/msm8992.dtsi b/sys/gnu/dts/arm64/qcom/msm8992.dtsi
	index 8be60c08a9ab..2021795c99ad 100644
	--- a/sys/gnu/dts/arm64/qcom/msm8992.dtsi
	+++ b/sys/gnu/dts/arm64/qcom/msm8992.dtsi
	@@ -1,314 +1,315 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/qcom,gcc-msm8994.h>

	/ {
	model = "Qualcomm Technologies, Inc. MSM 8992";
	compatible = "qcom,msm8992";
	// msm-id needed by bootloader for selecting correct blob
	qcom,msm-id = <251 0>, <252 0>;
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;
	cpu-map {
	cluster0 {
	core0 {
	cpu = <&CPU0>;
	};
	};
	};

	CPU0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x0>;
	next-level-cache = <&L2_0>;
	L2_0: l2-cache {
	compatible = "cache";
	cache-level = <2>;
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	xo_board: xo_board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <19200000>;
	};

	sleep_clk: sleep_clk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};

	vreg_vph_pwr: vreg-vph-pwr {
	compatible = "regulator-fixed";
	status = "okay";
	regulator-name = "vph-pwr";

	regulator-min-microvolt = <3600000>;
	regulator-max-microvolt = <3600000>;

	regulator-always-on;
	};

	sfpb_mutex: hwmutex {
	compatible = "qcom,sfpb-mutex";
	syscon = <&sfpb_mutex_regs 0x0 0x100>;
	#hwlock-cells = <1>;
	};

	smem {
	compatible = "qcom,smem";
	memory-region = <&smem_region>;
	qcom,rpm-msg-ram = <&rpm_msg_ram>;
	hwlocks = <&sfpb_mutex 3>;
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	intc: interrupt-controller@f9000000 {
	compatible = "qcom,msm-qgic2";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0xf9000000 0x1000>,
	<0xf9002000 0x1000>;
	};

	apcs: syscon@f900d000 {
	compatible = "syscon";
	reg = <0xf900d000 0x2000>;
	};

	timer@f9020000 {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "arm,armv7-timer-mem";
	reg = <0xf9020000 0x1000>;

	frame@f9021000 {
	frame-number = <0>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9021000 0x1000>,
	<0xf9022000 0x1000>;
	};

	frame@f9023000 {
	frame-number = <1>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9023000 0x1000>;
	status = "disabled";
	};

	frame@f9024000 {
	frame-number = <2>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9024000 0x1000>;
	status = "disabled";
	};

	frame@f9025000 {
	frame-number = <3>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9025000 0x1000>;
	status = "disabled";
	};

	frame@f9026000 {
	frame-number = <4>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9026000 0x1000>;
	status = "disabled";
	};

	frame@f9027000 {
	frame-number = <5>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9027000 0x1000>;
	status = "disabled";
	};

	frame@f9028000 {
	frame-number = <6>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9028000 0x1000>;
	status = "disabled";
	};
	};

	restart@fc4ab000 {
	compatible = "qcom,pshold";
	reg = <0xfc4ab000 0x4>;
	};

	msmgpio: pinctrl@fd510000 {
	compatible = "qcom,msm8994-pinctrl";
	reg = <0xfd510000 0x4000>;
	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	+ gpio-ranges = <&msmgpio 0 0 146>;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	blsp1_uart2: serial@f991e000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0xf991e000 0x1000>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
	status = "disabled";
	clock-names = "core", "iface";
	clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
	<&clock_gcc GCC_BLSP1_AHB_CLK>;
	};

	clock_gcc: clock-controller@fc400000 {
	compatible = "qcom,gcc-msm8994";
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;
	reg = <0xfc400000 0x2000>;
	};

	sdhci1: mmc@f9824900 {
	compatible = "qcom,sdhci-msm-v4";
	reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
	reg-names = "hc_mem", "core_mem";

	interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>,
	<GIC_SPI 138 IRQ_TYPE_NONE>;
	interrupt-names = "hc_irq", "pwr_irq";

	clocks = <&clock_gcc GCC_SDCC1_APPS_CLK>,
	<&clock_gcc GCC_SDCC1_AHB_CLK>;
	clock-names = "core", "iface";

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
	&sdc1_rclk_on>;
	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
	&sdc1_rclk_off>;

	regulator-always-on;
	bus-width = <8>;
	mmc-hs400-1_8v;
	status = "okay";
	};

	rpm_msg_ram: memory@fc428000 {
	compatible = "qcom,rpm-msg-ram";
	reg = <0xfc428000 0x4000>;
	};

	sfpb_mutex_regs: syscon@fd484000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "syscon";
	reg = <0xfd484000 0x400>;
	};
	};

	memory {
	device_type = "memory";
	reg = <0 0 0 0>; // bootloader will update
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	smem_region: smem@6a00000 {
	reg = <0x0 0x6a00000 0x0 0x200000>;
	no-map;
	};
	};

	smd_rpm: smd {
	compatible = "qcom,smd";
	rpm {
	interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
	qcom,ipc = <&apcs 8 0>;
	qcom,smd-edge = <15>;
	qcom,local-pid = <0>;
	qcom,remote-pid = <6>;

	rpm-requests {
	compatible = "qcom,rpm-msm8994";
	qcom,smd-channels = "rpm_requests";

	pm8994-regulators {
	compatible = "qcom,rpm-pm8994-regulators";

	pm8994_s1: s1 {};
	pm8994_s2: s2 {};
	pm8994_s3: s3 {};
	pm8994_s4: s4 {};
	pm8994_s5: s5 {};
	pm8994_s6: s6 {};
	pm8994_s7: s7 {};

	pm8994_l1: l1 {};
	pm8994_l2: l2 {};
	pm8994_l3: l3 {};
	pm8994_l4: l4 {};
	pm8994_l6: l6 {};
	pm8994_l8: l8 {};
	pm8994_l9: l9 {};
	pm8994_l10: l10 {};
	pm8994_l11: l11 {};
	pm8994_l12: l12 {};
	pm8994_l13: l13 {};
	pm8994_l14: l14 {};
	pm8994_l15: l15 {};
	pm8994_l16: l16 {};
	pm8994_l17: l17 {};
	pm8994_l18: l18 {};
	pm8994_l19: l19 {};
	pm8994_l20: l20 {};
	pm8994_l21: l21 {};
	pm8994_l22: l22 {};
	pm8994_l23: l23 {};
	pm8994_l24: l24 {};
	pm8994_l25: l25 {};
	pm8994_l26: l26 {};
	pm8994_l27: l27 {};
	pm8994_l28: l28 {};
	pm8994_l29: l29 {};
	pm8994_l30: l30 {};
	pm8994_l31: l31 {};
	pm8994_l32: l32 {};

	pm8994_lvs1: lvs1 {};
	pm8994_lvs2: lvs2 {};
	};
	};
	};
	};
	};

	#include "msm8992-pins.dtsi"
	diff --git a/sys/gnu/dts/arm64/qcom/msm8994.dtsi b/sys/gnu/dts/arm64/qcom/msm8994.dtsi
	index 3932757f78b7..b1c2d7d6a0f2 100644
	--- a/sys/gnu/dts/arm64/qcom/msm8994.dtsi
	+++ b/sys/gnu/dts/arm64/qcom/msm8994.dtsi
	@@ -1,208 +1,209 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/qcom,gcc-msm8994.h>

	/ {
	model = "Qualcomm Technologies, Inc. MSM 8994";
	compatible = "qcom,msm8994";
	// msm-id and pmic-id are required by bootloader for
	// proper selection of dt blob
	qcom,msm-id = <207 0x20000>;
	qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	cpu-map {
	cluster0 {
	core0 {
	cpu = <&CPU0>;
	};
	};
	};

	CPU0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0>;
	next-level-cache = <&L2_0>;
	L2_0: l2-cache {
	compatible = "cache";
	cache-level = <2>;
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <1 2 0xff08>,
	<1 3 0xff08>,
	<1 4 0xff08>,
	<1 1 0xff08>;
	};

	soc: soc {

	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	intc: interrupt-controller@f9000000 {
	compatible = "qcom,msm-qgic2";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0xf9000000 0x1000>,
	<0xf9002000 0x1000>;
	};

	timer@f9020000 {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "arm,armv7-timer-mem";
	reg = <0xf9020000 0x1000>;

	frame@f9021000 {
	frame-number = <0>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9021000 0x1000>,
	<0xf9022000 0x1000>;
	};

	frame@f9023000 {
	frame-number = <1>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9023000 0x1000>;
	status = "disabled";
	};

	frame@f9024000 {
	frame-number = <2>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9024000 0x1000>;
	status = "disabled";
	};

	frame@f9025000 {
	frame-number = <3>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9025000 0x1000>;
	status = "disabled";
	};

	frame@f9026000 {
	frame-number = <4>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9026000 0x1000>;
	status = "disabled";
	};

	frame@f9027000 {
	frame-number = <5>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9027000 0x1000>;
	status = "disabled";
	};

	frame@f9028000 {
	frame-number = <6>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xf9028000 0x1000>;
	status = "disabled";
	};
	};

	restart@fc4ab000 {
	compatible = "qcom,pshold";
	reg = <0xfc4ab000 0x4>;
	};

	msmgpio: pinctrl@fd510000 {
	compatible = "qcom,msm8994-pinctrl";
	reg = <0xfd510000 0x4000>;
	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	+ gpio-ranges = <&msmgpio 0 0 146>;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	blsp1_uart2: serial@f991e000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0xf991e000 0x1000>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	clock-names = "core", "iface";
	clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
	<&clock_gcc GCC_BLSP1_AHB_CLK>;
	};

	tcsr_mutex_regs: syscon@fd484000 {
	compatible = "syscon";
	reg = <0xfd484000 0x2000>;
	};

	clock_gcc: clock-controller@fc400000 {
	compatible = "qcom,gcc-msm8994";
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;
	reg = <0xfc400000 0x2000>;
	};
	};

	memory {
	device_type = "memory";
	// We expect the bootloader to fill in the reg
	reg = <0 0 0 0>;
	};

	xo_board: xo_board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <19200000>;
	};

	sleep_clk: sleep_clk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	smem_mem: smem_region@6a00000 {
	reg = <0x0 0x6a00000 0x0 0x200000>;
	no-map;
	};
	};

	tcsr_mutex: hwlock {
	compatible = "qcom,tcsr-mutex";
	syscon = <&tcsr_mutex_regs 0 0x80>;
	#hwlock-cells = <1>;
	};

	qcom,smem@6a00000 {
	compatible = "qcom,smem";
	memory-region = <&smem_mem>;
	hwlocks = <&tcsr_mutex 3>;
	};
	};


	#include "msm8994-pins.dtsi"
	diff --git a/sys/gnu/dts/arm64/qcom/msm8996.dtsi b/sys/gnu/dts/arm64/qcom/msm8996.dtsi
	index 7ae082ea14ea..98634d5c4440 100644
	--- a/sys/gnu/dts/arm64/qcom/msm8996.dtsi
	+++ b/sys/gnu/dts/arm64/qcom/msm8996.dtsi
	@@ -1,2404 +1,2419 @@
	// SPDX-License-Identifier: GPL-2.0-only
	/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/qcom,gcc-msm8996.h>
	#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
	#include <dt-bindings/clock/qcom,rpmcc.h>
	#include <dt-bindings/soc/qcom,apr.h>

	/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	clocks {
	xo_board: xo_board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <19200000>;
	clock-output-names = "xo_board";
	};

	sleep_clk: sleep_clk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32764>;
	clock-output-names = "sleep_clk";
	};
	};

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	CPU0: cpu@0 {
	device_type = "cpu";
	compatible = "qcom,kryo";
	reg = <0x0 0x0>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	capacity-dmips-mhz = <1024>;
	next-level-cache = <&L2_0>;
	L2_0: l2-cache {
	compatible = "cache";
	cache-level = <2>;
	};
	};

	CPU1: cpu@1 {
	device_type = "cpu";
	compatible = "qcom,kryo";
	reg = <0x0 0x1>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	capacity-dmips-mhz = <1024>;
	next-level-cache = <&L2_0>;
	};

	CPU2: cpu@100 {
	device_type = "cpu";
	compatible = "qcom,kryo";
	reg = <0x0 0x100>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	capacity-dmips-mhz = <1024>;
	next-level-cache = <&L2_1>;
	L2_1: l2-cache {
	compatible = "cache";
	cache-level = <2>;
	};
	};

	CPU3: cpu@101 {
	device_type = "cpu";
	compatible = "qcom,kryo";
	reg = <0x0 0x101>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	capacity-dmips-mhz = <1024>;
	next-level-cache = <&L2_1>;
	};

	cpu-map {
	cluster0 {
	core0 {
	cpu = <&CPU0>;
	};

	core1 {
	cpu = <&CPU1>;
	};
	};

	cluster1 {
	core0 {
	cpu = <&CPU2>;
	};

	core1 {
	cpu = <&CPU3>;
	};
	};
	};

	idle-states {
	entry-method = "psci";

	CPU_SLEEP_0: cpu-sleep-0 {
	compatible = "arm,idle-state";
	idle-state-name = "standalone-power-collapse";
	arm,psci-suspend-param = <0x00000004>;
	entry-latency-us = <130>;
	exit-latency-us = <80>;
	min-residency-us = <300>;
	};
	};
	};

	firmware {
	scm {
	compatible = "qcom,scm-msm8996";
	qcom,dload-mode = <&tcsr 0x13000>;
	};
	};

	tcsr_mutex: hwlock {
	compatible = "qcom,tcsr-mutex";
	syscon = <&tcsr_mutex_regs 0 0x1000>;
	#hwlock-cells = <1>;
	};

	memory {
	device_type = "memory";
	/* We expect the bootloader to fill in the reg */
	reg = <0 0 0 0>;
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	mba_region: mba@91500000 {
	reg = <0x0 0x91500000 0x0 0x200000>;
	no-map;
	};

	slpi_region: slpi@90b00000 {
	reg = <0x0 0x90b00000 0x0 0xa00000>;
	no-map;
	};

	venus_region: venus@90400000 {
	reg = <0x0 0x90400000 0x0 0x700000>;
	no-map;
	};

	adsp_region: adsp@8ea00000 {
	reg = <0x0 0x8ea00000 0x0 0x1a00000>;
	no-map;
	};

	mpss_region: mpss@88800000 {
	reg = <0x0 0x88800000 0x0 0x6200000>;
	no-map;
	};

	smem_mem: smem-mem@86000000 {
	reg = <0x0 0x86000000 0x0 0x200000>;
	no-map;
	};

	memory@85800000 {
	reg = <0x0 0x85800000 0x0 0x800000>;
	no-map;
	};

	memory@86200000 {
	reg = <0x0 0x86200000 0x0 0x2600000>;
	no-map;
	};

	rmtfs@86700000 {
	compatible = "qcom,rmtfs-mem";

	size = <0x0 0x200000>;
	alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
	no-map;

	qcom,client-id = <1>;
	qcom,vmid = <15>;
	};

	zap_shader_region: gpu@8f200000 {
	compatible = "shared-dma-pool";
	reg = <0x0 0x90b00000 0x0 0xa00000>;
	no-map;
	};
	};

	rpm-glink {
	compatible = "qcom,glink-rpm";

	interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;

	qcom,rpm-msg-ram = <&rpm_msg_ram>;

	mboxes = <&apcs_glb 0>;

	rpm_requests: rpm-requests {
	compatible = "qcom,rpm-msm8996";
	qcom,glink-channels = "rpm_requests";

	rpmcc: qcom,rpmcc {
	compatible = "qcom,rpmcc-msm8996";
	#clock-cells = <1>;
	};

	rpmpd: power-controller {
	compatible = "qcom,msm8996-rpmpd";
	#power-domain-cells = <1>;
	operating-points-v2 = <&rpmpd_opp_table>;

	rpmpd_opp_table: opp-table {
	compatible = "operating-points-v2";

	rpmpd_opp1: opp1 {
	opp-level = <1>;
	};

	rpmpd_opp2: opp2 {
	opp-level = <2>;
	};

	rpmpd_opp3: opp3 {
	opp-level = <3>;
	};

	rpmpd_opp4: opp4 {
	opp-level = <4>;
	};

	rpmpd_opp5: opp5 {
	opp-level = <5>;
	};

	rpmpd_opp6: opp6 {
	opp-level = <6>;
	};
	};
	};
	};
	};

	smem {
	compatible = "qcom,smem";
	memory-region = <&smem_mem>;
	hwlocks = <&tcsr_mutex 3>;
	};

	smp2p-adsp {
	compatible = "qcom,smp2p";
	qcom,smem = <443>, <429>;

	interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;

	mboxes = <&apcs_glb 10>;

	qcom,local-pid = <0>;
	qcom,remote-pid = <2>;

	smp2p_adsp_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};

	smp2p_adsp_in: slave-kernel {
	qcom,entry-name = "slave-kernel";

	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	smp2p-modem {
	compatible = "qcom,smp2p";
	qcom,smem = <435>, <428>;

	interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;

	mboxes = <&apcs_glb 14>;

	qcom,local-pid = <0>;
	qcom,remote-pid = <1>;

	modem_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};

	modem_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";

	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	smp2p-slpi {
	compatible = "qcom,smp2p";
	qcom,smem = <481>, <430>;

	interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;

	mboxes = <&apcs_glb 26>;

	qcom,local-pid = <0>;
	qcom,remote-pid = <3>;

	smp2p_slpi_in: slave-kernel {
	qcom,entry-name = "slave-kernel";
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	smp2p_slpi_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};
	};

	soc: soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	pcie_phy: phy@34000 {
	compatible = "qcom,msm8996-qmp-pcie-phy";
	reg = <0x00034000 0x488>;
	#clock-cells = <1>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
	<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
	<&gcc GCC_PCIE_CLKREF_CLK>;
	clock-names = "aux", "cfg_ahb", "ref";

	resets = <&gcc GCC_PCIE_PHY_BCR>,
	<&gcc GCC_PCIE_PHY_COM_BCR>,
	<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
	reset-names = "phy", "common", "cfg";
	status = "disabled";

	pciephy_0: lane@35000 {
	reg = <0x00035000 0x130>,
	<0x00035200 0x200>,
	<0x00035400 0x1dc>;
	#phy-cells = <0>;

	clock-output-names = "pcie_0_pipe_clk_src";
	clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
	clock-names = "pipe0";
	resets = <&gcc GCC_PCIE_0_PHY_BCR>;
	reset-names = "lane0";
	};

	pciephy_1: lane@36000 {
	reg = <0x00036000 0x130>,
	<0x00036200 0x200>,
	<0x00036400 0x1dc>;
	#phy-cells = <0>;

	clock-output-names = "pcie_1_pipe_clk_src";
	clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
	clock-names = "pipe1";
	resets = <&gcc GCC_PCIE_1_PHY_BCR>;
	reset-names = "lane1";
	};

	pciephy_2: lane@37000 {
	reg = <0x00037000 0x130>,
	<0x00037200 0x200>,
	<0x00037400 0x1dc>;
	#phy-cells = <0>;

	clock-output-names = "pcie_2_pipe_clk_src";
	clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
	clock-names = "pipe2";
	resets = <&gcc GCC_PCIE_2_PHY_BCR>;
	reset-names = "lane2";
	};
	};

	rpm_msg_ram: memory@68000 {
	compatible = "qcom,rpm-msg-ram";
	reg = <0x00068000 0x6000>;
	};

	qfprom@74000 {
	compatible = "qcom,qfprom";
	reg = <0x00074000 0x8ff>;
	#address-cells = <1>;
	#size-cells = <1>;

	qusb2p_hstx_trim: hstx_trim@24e {
	reg = <0x24e 0x2>;
	bits = <5 4>;
	};

	qusb2s_hstx_trim: hstx_trim@24f {
	reg = <0x24f 0x1>;
	bits = <1 4>;
	};

	gpu_speed_bin: gpu_speed_bin@133 {
	reg = <0x133 0x1>;
	bits = <5 3>;
	};
	};

	rng: rng@83000 {
	compatible = "qcom,prng-ee";
	reg = <0x00083000 0x1000>;
	clocks = <&gcc GCC_PRNG_AHB_CLK>;
	clock-names = "core";
	};

	gcc: clock-controller@300000 {
	compatible = "qcom,gcc-msm8996";
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;
	reg = <0x00300000 0x90000>;
	+
	+ clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
	+ clock-names = "cxo2";
	};

	tsens0: thermal-sensor@4a9000 {
	- compatible = "qcom,msm8996-tsens";
	+ compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
	reg = <0x004a9000 0x1000>, /* TM */
	<0x004a8000 0x1000>; /* SROT */
	#qcom,sensors = <13>;
	interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "uplow", "critical";
	#thermal-sensor-cells = <1>;
	};

	tsens1: thermal-sensor@4ad000 {
	- compatible = "qcom,msm8996-tsens";
	+ compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
	reg = <0x004ad000 0x1000>, /* TM */
	<0x004ac000 0x1000>; /* SROT */
	#qcom,sensors = <8>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "uplow", "critical";
	#thermal-sensor-cells = <1>;
	};

	tcsr_mutex_regs: syscon@740000 {
	compatible = "syscon";
	reg = <0x00740000 0x20000>;
	};

	tcsr: syscon@7a0000 {
	compatible = "qcom,tcsr-msm8996", "syscon";
	reg = <0x007a0000 0x18000>;
	};

	mmcc: clock-controller@8c0000 {
	compatible = "qcom,mmcc-msm8996";
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;
	reg = <0x008c0000 0x40000>;
	assigned-clocks = <&mmcc MMPLL9_PLL>,
	<&mmcc MMPLL1_PLL>,
	<&mmcc MMPLL3_PLL>,
	<&mmcc MMPLL4_PLL>,
	<&mmcc MMPLL5_PLL>;
	assigned-clock-rates = <624000000>,
	<810000000>,
	<980000000>,
	<960000000>,
	<825000000>;
	};

	mdss: mdss@900000 {
	compatible = "qcom,mdss";

	reg = <0x00900000 0x1000>,
	<0x009b0000 0x1040>,
	<0x009b8000 0x1040>;
	reg-names = "mdss_phys",
	"vbif_phys",
	"vbif_nrt_phys";

	power-domains = <&mmcc MDSS_GDSC>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

	interrupt-controller;
	#interrupt-cells = <1>;

	clocks = <&mmcc MDSS_AHB_CLK>;
	clock-names = "iface";

	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	mdp: mdp@901000 {
	compatible = "qcom,mdp5";
	reg = <0x00901000 0x90000>;
	reg-names = "mdp_phys";

	interrupt-parent = <&mdss>;
	interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&mmcc MDSS_AHB_CLK>,
	<&mmcc MDSS_AXI_CLK>,
	<&mmcc MDSS_MDP_CLK>,
	<&mmcc SMMU_MDP_AXI_CLK>,
	<&mmcc MDSS_VSYNC_CLK>;
	clock-names = "iface",
	"bus",
	"core",
	"iommu",
	"vsync";

	iommus = <&mdp_smmu 0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	mdp5_intf3_out: endpoint {
	remote-endpoint = <&hdmi_in>;
	};
	};
	};
	};

	hdmi: hdmi-tx@9a0000 {
	compatible = "qcom,hdmi-tx-8996";
	reg = <0x009a0000 0x50c>,
	<0x00070000 0x6158>,
	<0x009e0000 0xfff>;
	reg-names = "core_physical",
	"qfprom_physical",
	"hdcp_physical";

	interrupt-parent = <&mdss>;
	interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&mmcc MDSS_MDP_CLK>,
	<&mmcc MDSS_AHB_CLK>,
	<&mmcc MDSS_HDMI_CLK>,
	<&mmcc MDSS_HDMI_AHB_CLK>,
	<&mmcc MDSS_EXTPCLK_CLK>;
	clock-names =
	"mdp_core",
	"iface",
	"core",
	"alt_iface",
	"extp";

	phys = <&hdmi_phy>;
	phy-names = "hdmi_phy";
	#sound-dai-cells = <1>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	hdmi_in: endpoint {
	remote-endpoint = <&mdp5_intf3_out>;
	};
	};
	};
	};

	hdmi_phy: hdmi-phy@9a0600 {
	#phy-cells = <0>;
	compatible = "qcom,hdmi-phy-8996";
	reg = <0x009a0600 0x1c4>,
	<0x009a0a00 0x124>,
	<0x009a0c00 0x124>,
	<0x009a0e00 0x124>,
	<0x009a1000 0x124>,
	<0x009a1200 0x0c8>;
	reg-names = "hdmi_pll",
	"hdmi_tx_l0",
	"hdmi_tx_l1",
	"hdmi_tx_l2",
	"hdmi_tx_l3",
	"hdmi_phy";

	clocks = <&mmcc MDSS_AHB_CLK>,
	<&gcc GCC_HDMI_CLKREF_CLK>;
	clock-names = "iface",
	"ref";
	};
	};
	gpu@b00000 {
	compatible = "qcom,adreno-530.2", "qcom,adreno";
	#stream-id-cells = <16>;

	reg = <0x00b00000 0x3f000>;
	reg-names = "kgsl_3d0_reg_memory";

	interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&mmcc GPU_GX_GFX3D_CLK>,
	<&mmcc GPU_AHB_CLK>,
	<&mmcc GPU_GX_RBBMTIMER_CLK>,
	<&gcc GCC_BIMC_GFX_CLK>,
	<&gcc GCC_MMSS_BIMC_GFX_CLK>;

	clock-names = "core",
	"iface",
	"rbbmtimer",
	"mem",
	"mem_iface";

	power-domains = <&mmcc GPU_GDSC>;
	iommus = <&adreno_smmu 0>;

	nvmem-cells = <&gpu_speed_bin>;
	nvmem-cell-names = "speed_bin";

	qcom,gpu-quirk-two-pass-use-wfi;
	qcom,gpu-quirk-fault-detect-mask;

	operating-points-v2 = <&gpu_opp_table>;

	gpu_opp_table: opp-table {
	compatible ="operating-points-v2";

	/*
	* 624Mhz and 560Mhz are only available on speed
	* bin (1 << 0). All the rest are available on
	* all bins of the hardware
	*/
	opp-624000000 {
	opp-hz = /bits/ 64 <624000000>;
	opp-supported-hw = <0x01>;
	};
	opp-560000000 {
	opp-hz = /bits/ 64 <560000000>;
	opp-supported-hw = <0x01>;
	};
	opp-510000000 {
	opp-hz = /bits/ 64 <510000000>;
	opp-supported-hw = <0xFF>;
	};
	opp-401800000 {
	opp-hz = /bits/ 64 <401800000>;
	opp-supported-hw = <0xFF>;
	};
	opp-315000000 {
	opp-hz = /bits/ 64 <315000000>;
	opp-supported-hw = <0xFF>;
	};
	opp-214000000 {
	opp-hz = /bits/ 64 <214000000>;
	opp-supported-hw = <0xFF>;
	};
	opp-133000000 {
	opp-hz = /bits/ 64 <133000000>;
	opp-supported-hw = <0xFF>;
	};
	};

	zap-shader {
	memory-region = <&zap_shader_region>;
	};
	};

	msmgpio: pinctrl@1010000 {
	compatible = "qcom,msm8996-pinctrl";
	reg = <0x01010000 0x300000>;
	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	+ gpio-ranges = <&msmgpio 0 0 150>;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	spmi_bus: qcom,spmi@400f000 {
	compatible = "qcom,spmi-pmic-arb";
	reg = <0x0400f000 0x1000>,
	<0x04400000 0x800000>,
	<0x04c00000 0x800000>,
	<0x05800000 0x200000>,
	<0x0400a000 0x002100>;
	reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
	interrupt-names = "periph_irq";
	interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
	qcom,ee = <0>;
	qcom,channel = <0>;
	#address-cells = <2>;
	#size-cells = <0>;
	interrupt-controller;
	#interrupt-cells = <4>;
	};

	agnoc@0 {
	power-domains = <&gcc AGGRE0_NOC_GDSC>;
	compatible = "simple-pm-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	pcie0: pcie@600000 {
	compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
	status = "disabled";
	power-domains = <&gcc PCIE0_GDSC>;
	bus-range = <0x00 0xff>;
	num-lanes = <1>;

	reg = <0x00600000 0x2000>,
	<0x0c000000 0xf1d>,
	<0x0c000f20 0xa8>,
	<0x0c100000 0x100000>;
	reg-names = "parf", "dbi", "elbi","config";

	phys = <&pciephy_0>;
	phy-names = "pciephy";

	#address-cells = <3>;
	#size-cells = <2>;
	ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
	<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;

	interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
	pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;

	linux,pci-domain = <0>;

	clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
	<&gcc GCC_PCIE_0_AUX_CLK>,
	<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
	<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
	<&gcc GCC_PCIE_0_SLV_AXI_CLK>;

	clock-names = "pipe",
	"aux",
	"cfg",
	"bus_master",
	"bus_slave";

	};

	pcie1: pcie@608000 {
	compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
	power-domains = <&gcc PCIE1_GDSC>;
	bus-range = <0x00 0xff>;
	num-lanes = <1>;

	status = "disabled";

	reg = <0x00608000 0x2000>,
	<0x0d000000 0xf1d>,
	<0x0d000f20 0xa8>,
	<0x0d100000 0x100000>;

	reg-names = "parf", "dbi", "elbi","config";

	phys = <&pciephy_1>;
	phy-names = "pciephy";

	#address-cells = <3>;
	#size-cells = <2>;
	ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
	<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;

	interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
	pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;

	linux,pci-domain = <1>;

	clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
	<&gcc GCC_PCIE_1_AUX_CLK>,
	<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
	<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
	<&gcc GCC_PCIE_1_SLV_AXI_CLK>;

	clock-names = "pipe",
	"aux",
	"cfg",
	"bus_master",
	"bus_slave";
	};

	pcie2: pcie@610000 {
	compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
	power-domains = <&gcc PCIE2_GDSC>;
	bus-range = <0x00 0xff>;
	num-lanes = <1>;
	status = "disabled";
	reg = <0x00610000 0x2000>,
	<0x0e000000 0xf1d>,
	<0x0e000f20 0xa8>,
	<0x0e100000 0x100000>;

	reg-names = "parf", "dbi", "elbi","config";

	phys = <&pciephy_2>;
	phy-names = "pciephy";

	#address-cells = <3>;
	#size-cells = <2>;
	ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
	<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;

	device_type = "pci";

	interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
	pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;

	linux,pci-domain = <2>;
	clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
	<&gcc GCC_PCIE_2_AUX_CLK>,
	<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
	<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
	<&gcc GCC_PCIE_2_SLV_AXI_CLK>;

	clock-names = "pipe",
	"aux",
	"cfg",
	"bus_master",
	"bus_slave";
	};
	};

	ufshc: ufshc@624000 {
	compatible = "qcom,ufshc";
	reg = <0x00624000 0x2500>;
	interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

	- phys = <&ufsphy>;
	+ phys = <&ufsphy_lane>;
	phy-names = "ufsphy";

	power-domains = <&gcc UFS_GDSC>;

	clock-names =
	"core_clk_src",
	"core_clk",
	"bus_clk",
	"bus_aggr_clk",
	"iface_clk",
	"core_clk_unipro_src",
	"core_clk_unipro",
	"core_clk_ice",
	"ref_clk",
	"tx_lane0_sync_clk",
	"rx_lane0_sync_clk";
	clocks =
	<&gcc UFS_AXI_CLK_SRC>,
	<&gcc GCC_UFS_AXI_CLK>,
	<&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
	<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
	<&gcc GCC_UFS_AHB_CLK>,
	<&gcc UFS_ICE_CORE_CLK_SRC>,
	<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
	<&gcc GCC_UFS_ICE_CORE_CLK>,
	<&rpmcc RPM_SMD_LN_BB_CLK>,
	<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
	<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
	freq-table-hz =
	<100000000 200000000>,
	<0 0>,
	<0 0>,
	<0 0>,
	<0 0>,
	<150000000 300000000>,
	<0 0>,
	<0 0>,
	<0 0>,
	<0 0>,
	<0 0>;

	lanes-per-direction = <1>;
	#reset-cells = <1>;
	status = "disabled";

	ufs_variant {
	compatible = "qcom,ufs_variant";
	};
	};

	ufsphy: phy@627000 {
	- compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
	- reg = <0x00627000 0xda8>;
	- reg-names = "phy_mem";
	- #phy-cells = <0>;
	+ compatible = "qcom,msm8996-qmp-ufs-phy";
	+ reg = <0x00627000 0x1c4>;
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges;
	+
	+ clocks = <&gcc GCC_UFS_CLKREF_CLK>;
	+ clock-names = "ref";

	- clock-names = "ref_clk_src", "ref_clk";
	- clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
	- <&gcc GCC_UFS_CLKREF_CLK>;
	resets = <&ufshc 0>;
	+ reset-names = "ufsphy";
	status = "disabled";
	+
	+ ufsphy_lane: lanes@627400 {
	+ reg = <0x627400 0x12c>,
	+ <0x627600 0x200>,
	+ <0x627c00 0x1b4>;
	+ #phy-cells = <0>;
	+ };
	};

	camss: camss@a00000 {
	compatible = "qcom,msm8996-camss";
	reg = <0x00a34000 0x1000>,
	<0x00a00030 0x4>,
	<0x00a35000 0x1000>,
	<0x00a00038 0x4>,
	<0x00a36000 0x1000>,
	<0x00a00040 0x4>,
	<0x00a30000 0x100>,
	<0x00a30400 0x100>,
	<0x00a30800 0x100>,
	<0x00a30c00 0x100>,
	<0x00a31000 0x500>,
	<0x00a00020 0x10>,
	<0x00a10000 0x1000>,
	<0x00a14000 0x1000>;
	reg-names = "csiphy0",
	"csiphy0_clk_mux",
	"csiphy1",
	"csiphy1_clk_mux",
	"csiphy2",
	"csiphy2_clk_mux",
	"csid0",
	"csid1",
	"csid2",
	"csid3",
	"ispif",
	"csi_clk_mux",
	"vfe0",
	"vfe1";
	interrupts = <GIC_SPI 78 0>,
	<GIC_SPI 79 0>,
	<GIC_SPI 80 0>,
	<GIC_SPI 296 0>,
	<GIC_SPI 297 0>,
	<GIC_SPI 298 0>,
	<GIC_SPI 299 0>,
	<GIC_SPI 309 0>,
	<GIC_SPI 314 0>,
	<GIC_SPI 315 0>;
	interrupt-names = "csiphy0",
	"csiphy1",
	"csiphy2",
	"csid0",
	"csid1",
	"csid2",
	"csid3",
	"ispif",
	"vfe0",
	"vfe1";
	power-domains = <&mmcc VFE0_GDSC>;
	clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
	<&mmcc CAMSS_ISPIF_AHB_CLK>,
	<&mmcc CAMSS_CSI0PHYTIMER_CLK>,
	<&mmcc CAMSS_CSI1PHYTIMER_CLK>,
	<&mmcc CAMSS_CSI2PHYTIMER_CLK>,
	<&mmcc CAMSS_CSI0_AHB_CLK>,
	<&mmcc CAMSS_CSI0_CLK>,
	<&mmcc CAMSS_CSI0PHY_CLK>,
	<&mmcc CAMSS_CSI0PIX_CLK>,
	<&mmcc CAMSS_CSI0RDI_CLK>,
	<&mmcc CAMSS_CSI1_AHB_CLK>,
	<&mmcc CAMSS_CSI1_CLK>,
	<&mmcc CAMSS_CSI1PHY_CLK>,
	<&mmcc CAMSS_CSI1PIX_CLK>,
	<&mmcc CAMSS_CSI1RDI_CLK>,
	<&mmcc CAMSS_CSI2_AHB_CLK>,
	<&mmcc CAMSS_CSI2_CLK>,
	<&mmcc CAMSS_CSI2PHY_CLK>,
	<&mmcc CAMSS_CSI2PIX_CLK>,
	<&mmcc CAMSS_CSI2RDI_CLK>,
	<&mmcc CAMSS_CSI3_AHB_CLK>,
	<&mmcc CAMSS_CSI3_CLK>,
	<&mmcc CAMSS_CSI3PHY_CLK>,
	<&mmcc CAMSS_CSI3PIX_CLK>,
	<&mmcc CAMSS_CSI3RDI_CLK>,
	<&mmcc CAMSS_AHB_CLK>,
	<&mmcc CAMSS_VFE0_CLK>,
	<&mmcc CAMSS_CSI_VFE0_CLK>,
	<&mmcc CAMSS_VFE0_AHB_CLK>,
	<&mmcc CAMSS_VFE0_STREAM_CLK>,
	<&mmcc CAMSS_VFE1_CLK>,
	<&mmcc CAMSS_CSI_VFE1_CLK>,
	<&mmcc CAMSS_VFE1_AHB_CLK>,
	<&mmcc CAMSS_VFE1_STREAM_CLK>,
	<&mmcc CAMSS_VFE_AHB_CLK>,
	<&mmcc CAMSS_VFE_AXI_CLK>;
	clock-names = "top_ahb",
	"ispif_ahb",
	"csiphy0_timer",
	"csiphy1_timer",
	"csiphy2_timer",
	"csi0_ahb",
	"csi0",
	"csi0_phy",
	"csi0_pix",
	"csi0_rdi",
	"csi1_ahb",
	"csi1",
	"csi1_phy",
	"csi1_pix",
	"csi1_rdi",
	"csi2_ahb",
	"csi2",
	"csi2_phy",
	"csi2_pix",
	"csi2_rdi",
	"csi3_ahb",
	"csi3",
	"csi3_phy",
	"csi3_pix",
	"csi3_rdi",
	"ahb",
	"vfe0",
	"csi_vfe0",
	"vfe0_ahb",
	"vfe0_stream",
	"vfe1",
	"csi_vfe1",
	"vfe1_ahb",
	"vfe1_stream",
	"vfe_ahb",
	"vfe_axi";
	iommus = <&vfe_smmu 0>,
	<&vfe_smmu 1>,
	<&vfe_smmu 2>,
	<&vfe_smmu 3>;
	status = "disabled";
	ports {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	adreno_smmu: iommu@b40000 {
	compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
	reg = <0x00b40000 0x10000>;

	#global-interrupts = <1>;
	interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;

	clocks = <&mmcc GPU_AHB_CLK>,
	<&gcc GCC_MMSS_BIMC_GFX_CLK>;
	clock-names = "iface", "bus";

	power-domains = <&mmcc GPU_GDSC>;
	};

	video-codec@c00000 {
	compatible = "qcom,msm8996-venus";
	reg = <0x00c00000 0xff000>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&mmcc VENUS_GDSC>;
	clocks = <&mmcc VIDEO_CORE_CLK>,
	<&mmcc VIDEO_AHB_CLK>,
	<&mmcc VIDEO_AXI_CLK>,
	<&mmcc VIDEO_MAXI_CLK>;
	clock-names = "core", "iface", "bus", "mbus";
	iommus = <&venus_smmu 0x00>,
	<&venus_smmu 0x01>,
	<&venus_smmu 0x0a>,
	<&venus_smmu 0x07>,
	<&venus_smmu 0x0e>,
	<&venus_smmu 0x0f>,
	<&venus_smmu 0x08>,
	<&venus_smmu 0x09>,
	<&venus_smmu 0x0b>,
	<&venus_smmu 0x0c>,
	<&venus_smmu 0x0d>,
	<&venus_smmu 0x10>,
	<&venus_smmu 0x11>,
	<&venus_smmu 0x21>,
	<&venus_smmu 0x28>,
	<&venus_smmu 0x29>,
	<&venus_smmu 0x2b>,
	<&venus_smmu 0x2c>,
	<&venus_smmu 0x2d>,
	<&venus_smmu 0x31>;
	memory-region = <&venus_region>;
	status = "okay";

	video-decoder {
	compatible = "venus-decoder";
	clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
	clock-names = "core";
	power-domains = <&mmcc VENUS_CORE0_GDSC>;
	};

	video-encoder {
	compatible = "venus-encoder";
	clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
	clock-names = "core";
	power-domains = <&mmcc VENUS_CORE1_GDSC>;
	};
	};

	mdp_smmu: iommu@d00000 {
	compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
	reg = <0x00d00000 0x10000>;

	#global-interrupts = <1>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
	#iommu-cells = <1>;
	clocks = <&mmcc SMMU_MDP_AHB_CLK>,
	<&mmcc SMMU_MDP_AXI_CLK>;
	clock-names = "iface", "bus";

	power-domains = <&mmcc MDSS_GDSC>;
	};

	venus_smmu: iommu@d40000 {
	compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
	reg = <0x00d40000 0x20000>;
	#global-interrupts = <1>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
	clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
	<&mmcc SMMU_VIDEO_AXI_CLK>;
	clock-names = "iface", "bus";
	#iommu-cells = <1>;
	status = "okay";
	};

	vfe_smmu: iommu@da0000 {
	compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
	reg = <0x00da0000 0x10000>;

	#global-interrupts = <1>;
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
	clocks = <&mmcc SMMU_VFE_AHB_CLK>,
	<&mmcc SMMU_VFE_AXI_CLK>;
	clock-names = "iface",
	"bus";
	#iommu-cells = <1>;
	};

	lpass_q6_smmu: iommu@1600000 {
	compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
	reg = <0x01600000 0x20000>;
	#iommu-cells = <1>;
	power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;

	#global-interrupts = <1>;
	interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
	<&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
	clock-names = "iface", "bus";
	};

	stm@3002000 {
	compatible = "arm,coresight-stm", "arm,primecell";
	reg = <0x3002000 0x1000>,
	<0x8280000 0x180000>;
	reg-names = "stm-base", "stm-stimulus-base";

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	out-ports {
	port {
	stm_out: endpoint {
	remote-endpoint =
	<&funnel0_in>;
	};
	};
	};
	};

	tpiu@3020000 {
	compatible = "arm,coresight-tpiu", "arm,primecell";
	reg = <0x3020000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	port {
	tpiu_in: endpoint {
	remote-endpoint =
	<&replicator_out1>;
	};
	};
	};
	};

	funnel@3021000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0x3021000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@7 {
	reg = <7>;
	funnel0_in: endpoint {
	remote-endpoint =
	<&stm_out>;
	};
	};
	};

	out-ports {
	port {
	funnel0_out: endpoint {
	remote-endpoint =
	<&merge_funnel_in0>;
	};
	};
	};
	};

	funnel@3022000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0x3022000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@6 {
	reg = <6>;
	funnel1_in: endpoint {
	remote-endpoint =
	<&apss_merge_funnel_out>;
	};
	};
	};

	out-ports {
	port {
	funnel1_out: endpoint {
	remote-endpoint =
	<&merge_funnel_in1>;
	};
	};
	};
	};

	funnel@3023000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0x3023000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";


	out-ports {
	port {
	funnel2_out: endpoint {
	remote-endpoint =
	<&merge_funnel_in2>;
	};
	};
	};
	};

	funnel@3025000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0x3025000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	merge_funnel_in0: endpoint {
	remote-endpoint =
	<&funnel0_out>;
	};
	};

	port@1 {
	reg = <1>;
	merge_funnel_in1: endpoint {
	remote-endpoint =
	<&funnel1_out>;
	};
	};

	port@2 {
	reg = <2>;
	merge_funnel_in2: endpoint {
	remote-endpoint =
	<&funnel2_out>;
	};
	};
	};

	out-ports {
	port {
	merge_funnel_out: endpoint {
	remote-endpoint =
	<&etf_in>;
	};
	};
	};
	};

	replicator@3026000 {
	compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
	reg = <0x3026000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	port {
	replicator_in: endpoint {
	remote-endpoint =
	<&etf_out>;
	};
	};
	};

	out-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	replicator_out0: endpoint {
	remote-endpoint =
	<&etr_in>;
	};
	};

	port@1 {
	reg = <1>;
	replicator_out1: endpoint {
	remote-endpoint =
	<&tpiu_in>;
	};
	};
	};
	};

	etf@3027000 {
	compatible = "arm,coresight-tmc", "arm,primecell";
	reg = <0x3027000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	port {
	etf_in: endpoint {
	remote-endpoint =
	<&merge_funnel_out>;
	};
	};
	};

	out-ports {
	port {
	etf_out: endpoint {
	remote-endpoint =
	<&replicator_in>;
	};
	};
	};
	};

	etr@3028000 {
	compatible = "arm,coresight-tmc", "arm,primecell";
	reg = <0x3028000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";
	arm,scatter-gather;

	in-ports {
	port {
	etr_in: endpoint {
	remote-endpoint =
	<&replicator_out0>;
	};
	};
	};
	};

	debug@3810000 {
	compatible = "arm,coresight-cpu-debug", "arm,primecell";
	reg = <0x3810000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>;
	clock-names = "apb_pclk";

	cpu = <&CPU0>;
	};

	etm@3840000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0x3840000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	cpu = <&CPU0>;

	out-ports {
	port {
	etm0_out: endpoint {
	remote-endpoint =
	<&apss_funnel0_in0>;
	};
	};
	};
	};

	debug@3910000 {
	compatible = "arm,coresight-cpu-debug", "arm,primecell";
	reg = <0x3910000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>;
	clock-names = "apb_pclk";

	cpu = <&CPU1>;
	};

	etm@3940000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0x3940000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	cpu = <&CPU1>;

	out-ports {
	port {
	etm1_out: endpoint {
	remote-endpoint =
	<&apss_funnel0_in1>;
	};
	};
	};
	};

	funnel@39b0000 { /* APSS Funnel 0 */
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0x39b0000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	apss_funnel0_in0: endpoint {
	remote-endpoint = <&etm0_out>;
	};
	};

	port@1 {
	reg = <1>;
	apss_funnel0_in1: endpoint {
	remote-endpoint = <&etm1_out>;
	};
	};
	};

	out-ports {
	port {
	apss_funnel0_out: endpoint {
	remote-endpoint =
	<&apss_merge_funnel_in0>;
	};
	};
	};
	};

	debug@3a10000 {
	compatible = "arm,coresight-cpu-debug", "arm,primecell";
	reg = <0x3a10000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>;
	clock-names = "apb_pclk";

	cpu = <&CPU2>;
	};

	etm@3a40000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0x3a40000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	cpu = <&CPU2>;

	out-ports {
	port {
	etm2_out: endpoint {
	remote-endpoint =
	<&apss_funnel1_in0>;
	};
	};
	};
	};

	debug@3b10000 {
	compatible = "arm,coresight-cpu-debug", "arm,primecell";
	reg = <0x3b10000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>;
	clock-names = "apb_pclk";

	cpu = <&CPU3>;
	};

	etm@3b40000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0x3b40000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	cpu = <&CPU3>;

	out-ports {
	port {
	etm3_out: endpoint {
	remote-endpoint =
	<&apss_funnel1_in1>;
	};
	};
	};
	};

	funnel@3bb0000 { /* APSS Funnel 1 */
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0x3bb0000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	apss_funnel1_in0: endpoint {
	remote-endpoint = <&etm2_out>;
	};
	};

	port@1 {
	reg = <1>;
	apss_funnel1_in1: endpoint {
	remote-endpoint = <&etm3_out>;
	};
	};
	};

	out-ports {
	port {
	apss_funnel1_out: endpoint {
	remote-endpoint =
	<&apss_merge_funnel_in1>;
	};
	};
	};
	};

	funnel@3bc0000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0x3bc0000 0x1000>;

	clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	apss_merge_funnel_in0: endpoint {
	remote-endpoint =
	<&apss_funnel0_out>;
	};
	};

	port@1 {
	reg = <1>;
	apss_merge_funnel_in1: endpoint {
	remote-endpoint =
	<&apss_funnel1_out>;
	};
	};
	};

	out-ports {
	port {
	apss_merge_funnel_out: endpoint {
	remote-endpoint =
	<&funnel1_in>;
	};
	};
	};
	};
	kryocc: clock-controller@6400000 {
	compatible = "qcom,apcc-msm8996";
	reg = <0x06400000 0x90000>;
	#clock-cells = <1>;
	};

	usb3: usb@6af8800 {
	compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
	reg = <0x06af8800 0x400>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
	<&gcc GCC_USB30_MASTER_CLK>,
	<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
	<&gcc GCC_USB30_MOCK_UTMI_CLK>,
	<&gcc GCC_USB30_SLEEP_CLK>,
	<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;

	assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
	<&gcc GCC_USB30_MASTER_CLK>;
	assigned-clock-rates = <19200000>, <120000000>;

	power-domains = <&gcc USB30_GDSC>;
	status = "disabled";

	dwc3@6a00000 {
	compatible = "snps,dwc3";
	reg = <0x06a00000 0xcc00>;
	interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
	phys = <&hsusb_phy1>, <&ssusb_phy_0>;
	phy-names = "usb2-phy", "usb3-phy";
	snps,dis_u2_susphy_quirk;
	snps,dis_enblslpm_quirk;
	};
	};

	usb3phy: phy@7410000 {
	compatible = "qcom,msm8996-qmp-usb3-phy";
	reg = <0x07410000 0x1c4>;
	#clock-cells = <1>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
	<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	<&gcc GCC_USB3_CLKREF_CLK>;
	clock-names = "aux", "cfg_ahb", "ref";

	resets = <&gcc GCC_USB3_PHY_BCR>,
	<&gcc GCC_USB3PHY_PHY_BCR>;
	reset-names = "phy", "common";
	status = "disabled";

	ssusb_phy_0: lane@7410200 {
	reg = <0x07410200 0x200>,
	<0x07410400 0x130>,
	<0x07410600 0x1a8>;
	#phy-cells = <0>;

	clock-output-names = "usb3_phy_pipe_clk_src";
	clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
	clock-names = "pipe0";
	};
	};

	hsusb_phy1: phy@7411000 {
	compatible = "qcom,msm8996-qusb2-phy";
	reg = <0x07411000 0x180>;
	#phy-cells = <0>;

	clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	<&gcc GCC_RX1_USB2_CLKREF_CLK>;
	clock-names = "cfg_ahb", "ref";

	resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
	nvmem-cells = <&qusb2p_hstx_trim>;
	status = "disabled";
	};

	hsusb_phy2: phy@7412000 {
	compatible = "qcom,msm8996-qusb2-phy";
	reg = <0x07412000 0x180>;
	#phy-cells = <0>;

	clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	<&gcc GCC_RX2_USB2_CLKREF_CLK>;
	clock-names = "cfg_ahb", "ref";

	resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
	nvmem-cells = <&qusb2s_hstx_trim>;
	status = "disabled";
	};

	sdhc2: sdhci@74a4900 {
	status = "disabled";
	compatible = "qcom,sdhci-msm-v4";
	reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
	reg-names = "hc_mem", "core_mem";

	interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
	<0 221 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hc_irq", "pwr_irq";

	clock-names = "iface", "core", "xo";
	clocks = <&gcc GCC_SDCC2_AHB_CLK>,
	<&gcc GCC_SDCC2_APPS_CLK>,
	<&xo_board>;
	bus-width = <4>;
	};

	blsp1_uart1: serial@7570000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x07570000 0x1000>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	blsp1_spi0: spi@7575000 {
	compatible = "qcom,spi-qup-v2.2.1";
	reg = <0x07575000 0x600>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&blsp1_spi0_default>;
	pinctrl-1 = <&blsp1_spi0_sleep>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp1_i2c2: i2c@7577000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x07577000 0x1000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&blsp1_i2c2_default>;
	pinctrl-1 = <&blsp1_i2c2_sleep>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp2_uart1: serial@75b0000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x075b0000 0x1000>;
	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
	<&gcc GCC_BLSP2_AHB_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	blsp2_uart2: serial@75b1000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x075b1000 0x1000>;
	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
	<&gcc GCC_BLSP2_AHB_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	blsp2_i2c0: i2c@75b5000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x075b5000 0x1000>;
	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP2_AHB_CLK>,
	<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&blsp2_i2c0_default>;
	pinctrl-1 = <&blsp2_i2c0_sleep>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp2_i2c1: i2c@75b6000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x075b6000 0x1000>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP2_AHB_CLK>,
	<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&blsp2_i2c1_default>;
	pinctrl-1 = <&blsp2_i2c1_sleep>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp2_spi5: spi@75ba000{
	compatible = "qcom,spi-qup-v2.2.1";
	reg = <0x075ba000 0x600>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
	<&gcc GCC_BLSP2_AHB_CLK>;
	clock-names = "core", "iface";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&blsp2_spi5_default>;
	pinctrl-1 = <&blsp2_spi5_sleep>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	usb2: usb@76f8800 {
	compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
	reg = <0x076f8800 0x400>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
	<&gcc GCC_USB20_MASTER_CLK>,
	<&gcc GCC_USB20_MOCK_UTMI_CLK>,
	<&gcc GCC_USB20_SLEEP_CLK>,
	<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;

	assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
	<&gcc GCC_USB20_MASTER_CLK>;
	assigned-clock-rates = <19200000>, <60000000>;

	power-domains = <&gcc USB30_GDSC>;
	status = "disabled";

	dwc3@7600000 {
	compatible = "snps,dwc3";
	reg = <0x07600000 0xcc00>;
	interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
	phys = <&hsusb_phy2>;
	phy-names = "usb2-phy";
	snps,dis_u2_susphy_quirk;
	snps,dis_enblslpm_quirk;
	};
	};

	slimbam: dma@9184000 {
	compatible = "qcom,bam-v1.7.0";
	qcom,controlled-remotely;
	reg = <0x09184000 0x32000>;
	num-channels = <31>;
	interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	qcom,ee = <1>;
	qcom,num-ees = <2>;
	};

	slim_msm: slim@91c0000 {
	compatible = "qcom,slim-ngd-v1.5.0";
	reg = <0x091c0000 0x2C000>;
	reg-names = "ctrl";
	interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&slimbam 3>, <&slimbam 4>,
	<&slimbam 5>, <&slimbam 6>;
	dma-names = "rx", "tx", "tx2", "rx2";
	#address-cells = <1>;
	#size-cells = <0>;
	ngd@1 {
	reg = <1>;
	#address-cells = <1>;
	#size-cells = <1>;

	tasha_ifd: tas-ifd {
	compatible = "slim217,1a0";
	reg = <0 0>;
	};

	wcd9335: codec@1{
	pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
	pinctrl-names = "default";

	compatible = "slim217,1a0";
	reg = <1 0>;

	interrupt-parent = <&msmgpio>;
	interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
	<53 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "intr1", "intr2";
	interrupt-controller;
	#interrupt-cells = <1>;
	reset-gpios = <&msmgpio 64 0>;

	slim-ifc-dev = <&tasha_ifd>;

	#sound-dai-cells = <1>;
	};
	};
	};

	adsp_pil: remoteproc@9300000 {
	compatible = "qcom,msm8996-adsp-pil";
	reg = <0x09300000 0x80000>;

	interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
	<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
	<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
	<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
	<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "wdog", "fatal", "ready",
	"handover", "stop-ack";

	clocks = <&xo_board>;
	clock-names = "xo";

	memory-region = <&adsp_region>;

	qcom,smem-states = <&smp2p_adsp_out 0>;
	qcom,smem-state-names = "stop";

	smd-edge {
	interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;

	label = "lpass";
	mboxes = <&apcs_glb 8>;
	qcom,smd-edge = <1>;
	qcom,remote-pid = <2>;
	#address-cells = <1>;
	#size-cells = <0>;
	apr {
	power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
	compatible = "qcom,apr-v2";
	qcom,smd-channels = "apr_audio_svc";
	qcom,apr-domain = <APR_DOMAIN_ADSP>;
	#address-cells = <1>;
	#size-cells = <0>;

	q6core {
	reg = <APR_SVC_ADSP_CORE>;
	compatible = "qcom,q6core";
	};

	q6afe: q6afe {
	compatible = "qcom,q6afe";
	reg = <APR_SVC_AFE>;
	q6afedai: dais {
	compatible = "qcom,q6afe-dais";
	#address-cells = <1>;
	#size-cells = <0>;
	#sound-dai-cells = <1>;
	hdmi@1 {
	reg = <1>;
	};
	};
	};

	q6asm: q6asm {
	compatible = "qcom,q6asm";
	reg = <APR_SVC_ASM>;
	q6asmdai: dais {
	compatible = "qcom,q6asm-dais";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	#sound-dai-cells = <1>;
	iommus = <&lpass_q6_smmu 1>;
	};
	};

	q6adm: q6adm {
	compatible = "qcom,q6adm";
	reg = <APR_SVC_ADM>;
	q6routing: routing {
	compatible = "qcom,q6adm-routing";
	#sound-dai-cells = <0>;
	};
	};
	};

	};
	};

	apcs_glb: mailbox@9820000 {
	compatible = "qcom,msm8996-apcs-hmss-global";
	reg = <0x09820000 0x1000>;

	#mbox-cells = <1>;
	};

	timer@9840000 {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "arm,armv7-timer-mem";
	reg = <0x09840000 0x1000>;
	clock-frequency = <19200000>;

	frame@9850000 {
	frame-number = <0>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x09850000 0x1000>,
	<0x09860000 0x1000>;
	};

	frame@9870000 {
	frame-number = <1>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x09870000 0x1000>;
	status = "disabled";
	};

	frame@9880000 {
	frame-number = <2>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x09880000 0x1000>;
	status = "disabled";
	};

	frame@9890000 {
	frame-number = <3>;
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x09890000 0x1000>;
	status = "disabled";
	};

	frame@98a0000 {
	frame-number = <4>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x098a0000 0x1000>;
	status = "disabled";
	};

	frame@98b0000 {
	frame-number = <5>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x098b0000 0x1000>;
	status = "disabled";
	};

	frame@98c0000 {
	frame-number = <6>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x098c0000 0x1000>;
	status = "disabled";
	};
	};

	saw3: syscon@9a10000 {
	compatible = "syscon";
	reg = <0x09a10000 0x1000>;
	};

	intc: interrupt-controller@9bc0000 {
	compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
	#interrupt-cells = <3>;
	interrupt-controller;
	#redistributor-regions = <1>;
	redistributor-stride = <0x0 0x40000>;
	reg = <0x09bc0000 0x10000>,
	<0x09c00000 0x100000>;
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	sound: sound {
	};

	thermal-zones {
	cpu0-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 3>;

	trips {
	cpu0_alert0: trip-point@0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu0_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu1-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 5>;

	trips {
	cpu1_alert0: trip-point@0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu1_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu2-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 8>;

	trips {
	cpu2_alert0: trip-point@0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu2_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu3-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 10>;

	trips {
	cpu3_alert0: trip-point@0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu3_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	gpu-thermal-top {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 6>;

	trips {
	gpu1_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	gpu-thermal-bottom {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 7>;

	trips {
	gpu2_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	m4m-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 1>;

	trips {
	m4m_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	l3-or-venus-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 2>;

	trips {
	l3_or_venus_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	cluster0-l2-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 7>;

	trips {
	cluster0_l2_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	cluster1-l2-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 12>;

	trips {
	cluster1_l2_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	camera-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 1>;

	trips {
	camera_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	q6-dsp-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 2>;

	trips {
	q6_dsp_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	mem-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 3>;

	trips {
	mem_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	modemtx-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 4>;

	trips {
	modemtx_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};
	};
	#include "msm8996-pins.dtsi"
	diff --git a/sys/gnu/dts/arm64/qcom/msm8998-mtp.dtsi b/sys/gnu/dts/arm64/qcom/msm8998-mtp.dtsi
	index 0e0b9bc12945..8a14b2bf7bca 100644
	--- a/sys/gnu/dts/arm64/qcom/msm8998-mtp.dtsi
	+++ b/sys/gnu/dts/arm64/qcom/msm8998-mtp.dtsi
	@@ -1,407 +1,411 @@
	// SPDX-License-Identifier: GPL-2.0
	/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */

	#include "msm8998.dtsi"
	#include "pm8998.dtsi"
	#include "pmi8998.dtsi"
	#include "pm8005.dtsi"

	/ {
	aliases {
	serial0 = &blsp2_uart1;
	serial1 = &blsp1_uart3;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	vph_pwr: vph-pwr-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vph_pwr";
	regulator-always-on;
	regulator-boot-on;
	};
	};

	&blsp1_uart3 {
	status = "okay";

	bluetooth {
	compatible = "qcom,wcn3990-bt";

	vddio-supply = <&vreg_s4a_1p8>;
	vddxo-supply = <&vreg_l7a_1p8>;
	vddrf-supply = <&vreg_l17a_1p3>;
	vddch0-supply = <&vreg_l25a_3p3>;
	max-speed = <3200000>;
	};
	};

	&blsp2_uart1 {
	status = "okay";
	};

	&etf {
	status = "okay";
	};

	&etm1 {
	status = "okay";
	};

	&etm2 {
	status = "okay";
	};

	&etm3 {
	status = "okay";
	};

	&etm4 {
	status = "okay";
	};

	&etm5 {
	status = "okay";
	};

	&etm6 {
	status = "okay";
	};

	&etm7 {
	status = "okay";
	};

	&etm8 {
	status = "okay";
	};

	&etr {
	status = "okay";
	};

	&funnel1 {
	status = "okay";
	};

	&funnel2 {
	status = "okay";
	};

	&funnel3 {
	status = "okay";
	};

	&funnel4 {
	- status = "okay";
	+ // FIXME: Figure out why clock late_initcall crashes the board with
	+ // this enabled.
	+ // status = "okay";
	};

	&funnel5 {
	- status = "okay";
	+ // FIXME: Figure out why clock late_initcall crashes the board with
	+ // this enabled.
	+ // status = "okay";
	};

	&pm8005_lsid1 {
	pm8005-regulators {
	compatible = "qcom,pm8005-regulators";

	vdd_s1-supply = <&vph_pwr>;

	pm8005_s1: s1 { /* VDD_GFX supply */
	regulator-min-microvolt = <524000>;
	regulator-max-microvolt = <1100000>;
	regulator-enable-ramp-delay = <500>;

	/* hack until we rig up the gpu consumer */
	regulator-always-on;
	};
	};
	};

	&qusb2phy {
	status = "okay";

	vdda-pll-supply = <&vreg_l12a_1p8>;
	vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
	};

	&replicator1 {
	status = "okay";
	};

	&rpm_requests {
	pm8998-regulators {
	compatible = "qcom,rpm-pm8998-regulators";

	vdd_s1-supply = <&vph_pwr>;
	vdd_s2-supply = <&vph_pwr>;
	vdd_s3-supply = <&vph_pwr>;
	vdd_s4-supply = <&vph_pwr>;
	vdd_s5-supply = <&vph_pwr>;
	vdd_s6-supply = <&vph_pwr>;
	vdd_s7-supply = <&vph_pwr>;
	vdd_s8-supply = <&vph_pwr>;
	vdd_s9-supply = <&vph_pwr>;
	vdd_s10-supply = <&vph_pwr>;
	vdd_s11-supply = <&vph_pwr>;
	vdd_s12-supply = <&vph_pwr>;
	vdd_s13-supply = <&vph_pwr>;
	vdd_l1_l27-supply = <&vreg_s7a_1p025>;
	vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>;
	vdd_l3_l11-supply = <&vreg_s7a_1p025>;
	vdd_l4_l5-supply = <&vreg_s7a_1p025>;
	vdd_l6-supply = <&vreg_s5a_2p04>;
	vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>;
	vdd_l9-supply = <&vreg_bob>;
	vdd_l10_l23_l25-supply = <&vreg_bob>;
	vdd_l13_l19_l21-supply = <&vreg_bob>;
	vdd_l16_l28-supply = <&vreg_bob>;
	vdd_l18_l22-supply = <&vreg_bob>;
	vdd_l20_l24-supply = <&vreg_bob>;
	vdd_l26-supply = <&vreg_s3a_1p35>;
	vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>;

	vreg_s3a_1p35: s3 {
	regulator-min-microvolt = <1352000>;
	regulator-max-microvolt = <1352000>;
	};
	vreg_s4a_1p8: s4 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-allow-set-load;
	};
	vreg_s5a_2p04: s5 {
	regulator-min-microvolt = <1904000>;
	regulator-max-microvolt = <2040000>;
	};
	vreg_s7a_1p025: s7 {
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1028000>;
	};
	vreg_l1a_0p875: l1 {
	regulator-min-microvolt = <880000>;
	regulator-max-microvolt = <880000>;
	};
	vreg_l2a_1p2: l2 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};
	vreg_l3a_1p0: l3 {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	};
	vreg_l5a_0p8: l5 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <800000>;
	};
	vreg_l6a_1p8: l6 {
	regulator-min-microvolt = <1808000>;
	regulator-max-microvolt = <1808000>;
	};
	vreg_l7a_1p8: l7 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	vreg_l8a_1p2: l8 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	};
	vreg_l9a_1p8: l9 {
	regulator-min-microvolt = <1808000>;
	regulator-max-microvolt = <2960000>;
	};
	vreg_l10a_1p8: l10 {
	regulator-min-microvolt = <1808000>;
	regulator-max-microvolt = <2960000>;
	};
	vreg_l11a_1p0: l11 {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	};
	vreg_l12a_1p8: l12 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	vreg_l13a_2p95: l13 {
	regulator-min-microvolt = <1808000>;
	regulator-max-microvolt = <2960000>;
	};
	vreg_l14a_1p88: l14 {
	regulator-min-microvolt = <1880000>;
	regulator-max-microvolt = <1880000>;
	};
	vreg_15a_1p8: l15 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	vreg_l16a_2p7: l16 {
	regulator-min-microvolt = <2704000>;
	regulator-max-microvolt = <2704000>;
	};
	vreg_l17a_1p3: l17 {
	regulator-min-microvolt = <1304000>;
	regulator-max-microvolt = <1304000>;
	};
	vreg_l18a_2p7: l18 {
	regulator-min-microvolt = <2704000>;
	regulator-max-microvolt = <2704000>;
	};
	vreg_l19a_3p0: l19 {
	regulator-min-microvolt = <3008000>;
	regulator-max-microvolt = <3008000>;
	};
	vreg_l20a_2p95: l20 {
	regulator-min-microvolt = <2960000>;
	regulator-max-microvolt = <2960000>;
	regulator-allow-set-load;
	};
	vreg_l21a_2p95: l21 {
	regulator-min-microvolt = <2960000>;
	regulator-max-microvolt = <2960000>;
	regulator-allow-set-load;
	regulator-system-load = <800000>;
	};
	vreg_l22a_2p85: l22 {
	regulator-min-microvolt = <2864000>;
	regulator-max-microvolt = <2864000>;
	};
	vreg_l23a_3p3: l23 {
	regulator-min-microvolt = <3312000>;
	regulator-max-microvolt = <3312000>;
	};
	vreg_l24a_3p075: l24 {
	regulator-min-microvolt = <3088000>;
	regulator-max-microvolt = <3088000>;
	};
	vreg_l25a_3p3: l25 {
	regulator-min-microvolt = <3104000>;
	regulator-max-microvolt = <3312000>;
	};
	vreg_l26a_1p2: l26 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-allow-set-load;
	};
	vreg_l28_3p0: l28 {
	regulator-min-microvolt = <3008000>;
	regulator-max-microvolt = <3008000>;
	};

	vreg_lvs1a_1p8: lvs1 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	vreg_lvs2a_1p8: lvs2 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	};

	pmi8998-regulators {
	compatible = "qcom,rpm-pmi8998-regulators";

	vdd_bob-supply = <&vph_pwr>;

	vreg_bob: bob {
	regulator-min-microvolt = <3312000>;
	regulator-max-microvolt = <3600000>;
	};
	};
	};

	&remoteproc_adsp {
	status = "okay";
	};

	&remoteproc_slpi {
	status = "okay";
	};

	&tlmm {
	gpio-reserved-ranges = <0 4>, <81 4>;
	};

	&sdhc2 {
	status = "okay";
	cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>;

	vmmc-supply = <&vreg_l21a_2p95>;
	vqmmc-supply = <&vreg_l13a_2p95>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
	};

	&stm {
	status = "okay";
	};

	&ufshc {
	vcc-supply = <&vreg_l20a_2p95>;
	vccq-supply = <&vreg_l26a_1p2>;
	vccq2-supply = <&vreg_s4a_1p8>;
	vcc-max-microamp = <750000>;
	vccq-max-microamp = <560000>;
	vccq2-max-microamp = <750000>;
	};

	&ufsphy {
	vdda-phy-supply = <&vreg_l1a_0p875>;
	vdda-pll-supply = <&vreg_l2a_1p2>;
	vddp-ref-clk-supply = <&vreg_l26a_1p2>;
	vdda-phy-max-microamp = <51400>;
	vdda-pll-max-microamp = <14600>;
	vddp-ref-clk-max-microamp = <100>;
	vddp-ref-clk-always-on;
	};

	&usb3 {
	status = "okay";
	};

	&usb3_dwc3 {
	dr_mode = "host"; /* Force to host until we have Type-C hooked up */
	};

	&usb3phy {
	status = "okay";

	vdda-phy-supply = <&vreg_l1a_0p875>;
	vdda-pll-supply = <&vreg_l2a_1p2>;
	};

	&wifi {
	status = "okay";

	vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
	vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
	vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
	vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
	};

	/* PINCTRL - board-specific pinctrl */
	&blsp1_uart3_on {
	rx {
	/delete-property/ bias-disable;
	/*
	* Configure a pull-up on 45 (RX). This is needed to
	* avoid garbage data when the TX pin of the Bluetooth
	* module is in tri-state (module powered off or not
	* driving the signal yet).
	*/
	bias-pull-up;
	};

	cts {
	/delete-property/ bias-disable;
	/*
	* Configure a pull-down on 47 (CTS) to match the pull
	* of the Bluetooth module.
	*/
	bias-pull-down;
	};
	};
	diff --git a/sys/gnu/dts/arm64/qcom/msm8998.dtsi b/sys/gnu/dts/arm64/qcom/msm8998.dtsi
	index 91f7f2d07597..c07fee6fd7eb 100644
	--- a/sys/gnu/dts/arm64/qcom/msm8998.dtsi
	+++ b/sys/gnu/dts/arm64/qcom/msm8998.dtsi
	@@ -1,2114 +1,2114 @@
	// SPDX-License-Identifier: GPL-2.0
	/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/qcom,gcc-msm8998.h>
	#include <dt-bindings/clock/qcom,gpucc-msm8998.h>
	#include <dt-bindings/clock/qcom,rpmcc.h>
	#include <dt-bindings/power/qcom-rpmpd.h>
	#include <dt-bindings/gpio/gpio.h>

	/ {
	interrupt-parent = <&intc>;

	qcom,msm-id = <292 0x0>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	memory {
	device_type = "memory";
	/* We expect the bootloader to fill in the reg */
	reg = <0 0 0 0>;
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	hyp_mem: memory@85800000 {
	reg = <0x0 0x85800000 0x0 0x600000>;
	no-map;
	};

	xbl_mem: memory@85e00000 {
	reg = <0x0 0x85e00000 0x0 0x100000>;
	no-map;
	};

	smem_mem: smem-mem@86000000 {
	reg = <0x0 0x86000000 0x0 0x200000>;
	no-map;
	};

	tz_mem: memory@86200000 {
	reg = <0x0 0x86200000 0x0 0x2d00000>;
	no-map;
	};

	rmtfs_mem: memory@88f00000 {
	compatible = "qcom,rmtfs-mem";
	reg = <0x0 0x88f00000 0x0 0x200000>;
	no-map;

	qcom,client-id = <1>;
	qcom,vmid = <15>;
	};

	spss_mem: memory@8ab00000 {
	reg = <0x0 0x8ab00000 0x0 0x700000>;
	no-map;
	};

	adsp_mem: memory@8b200000 {
	reg = <0x0 0x8b200000 0x0 0x1a00000>;
	no-map;
	};

	mpss_mem: memory@8cc00000 {
	reg = <0x0 0x8cc00000 0x0 0x7000000>;
	no-map;
	};

	venus_mem: memory@93c00000 {
	reg = <0x0 0x93c00000 0x0 0x500000>;
	no-map;
	};

	mba_mem: memory@94100000 {
	reg = <0x0 0x94100000 0x0 0x200000>;
	no-map;
	};

	slpi_mem: memory@94300000 {
	reg = <0x0 0x94300000 0x0 0xf00000>;
	no-map;
	};

	ipa_fw_mem: memory@95200000 {
	reg = <0x0 0x95200000 0x0 0x10000>;
	no-map;
	};

	ipa_gsi_mem: memory@95210000 {
	reg = <0x0 0x95210000 0x0 0x5000>;
	no-map;
	};

	gpu_mem: memory@95600000 {
	reg = <0x0 0x95600000 0x0 0x100000>;
	no-map;
	};

	wlan_msa_mem: memory@95700000 {
	reg = <0x0 0x95700000 0x0 0x100000>;
	no-map;
	};
	};

	clocks {
	xo: xo-board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <19200000>;
	clock-output-names = "xo_board";
	};

	sleep_clk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32764>;
	};
	};

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	CPU0: cpu@0 {
	device_type = "cpu";
	- compatible = "arm,armv8";
	+ compatible = "qcom,kryo280";
	reg = <0x0 0x0>;
	enable-method = "psci";
	cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
	next-level-cache = <&L2_0>;
	L2_0: l2-cache {
	compatible = "arm,arch-cache";
	cache-level = <2>;
	};
	L1_I_0: l1-icache {
	compatible = "arm,arch-cache";
	};
	L1_D_0: l1-dcache {
	compatible = "arm,arch-cache";
	};
	};

	CPU1: cpu@1 {
	device_type = "cpu";
	- compatible = "arm,armv8";
	+ compatible = "qcom,kryo280";
	reg = <0x0 0x1>;
	enable-method = "psci";
	cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
	next-level-cache = <&L2_0>;
	L1_I_1: l1-icache {
	compatible = "arm,arch-cache";
	};
	L1_D_1: l1-dcache {
	compatible = "arm,arch-cache";
	};
	};

	CPU2: cpu@2 {
	device_type = "cpu";
	- compatible = "arm,armv8";
	+ compatible = "qcom,kryo280";
	reg = <0x0 0x2>;
	enable-method = "psci";
	cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
	next-level-cache = <&L2_0>;
	L1_I_2: l1-icache {
	compatible = "arm,arch-cache";
	};
	L1_D_2: l1-dcache {
	compatible = "arm,arch-cache";
	};
	};

	CPU3: cpu@3 {
	device_type = "cpu";
	- compatible = "arm,armv8";
	+ compatible = "qcom,kryo280";
	reg = <0x0 0x3>;
	enable-method = "psci";
	cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
	next-level-cache = <&L2_0>;
	L1_I_3: l1-icache {
	compatible = "arm,arch-cache";
	};
	L1_D_3: l1-dcache {
	compatible = "arm,arch-cache";
	};
	};

	CPU4: cpu@100 {
	device_type = "cpu";
	- compatible = "arm,armv8";
	+ compatible = "qcom,kryo280";
	reg = <0x0 0x100>;
	enable-method = "psci";
	cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
	next-level-cache = <&L2_1>;
	L2_1: l2-cache {
	compatible = "arm,arch-cache";
	cache-level = <2>;
	};
	L1_I_100: l1-icache {
	compatible = "arm,arch-cache";
	};
	L1_D_100: l1-dcache {
	compatible = "arm,arch-cache";
	};
	};

	CPU5: cpu@101 {
	device_type = "cpu";
	- compatible = "arm,armv8";
	+ compatible = "qcom,kryo280";
	reg = <0x0 0x101>;
	enable-method = "psci";
	cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
	next-level-cache = <&L2_1>;
	L1_I_101: l1-icache {
	compatible = "arm,arch-cache";
	};
	L1_D_101: l1-dcache {
	compatible = "arm,arch-cache";
	};
	};

	CPU6: cpu@102 {
	device_type = "cpu";
	- compatible = "arm,armv8";
	+ compatible = "qcom,kryo280";
	reg = <0x0 0x102>;
	enable-method = "psci";
	cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
	next-level-cache = <&L2_1>;
	L1_I_102: l1-icache {
	compatible = "arm,arch-cache";
	};
	L1_D_102: l1-dcache {
	compatible = "arm,arch-cache";
	};
	};

	CPU7: cpu@103 {
	device_type = "cpu";
	- compatible = "arm,armv8";
	+ compatible = "qcom,kryo280";
	reg = <0x0 0x103>;
	enable-method = "psci";
	cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
	next-level-cache = <&L2_1>;
	L1_I_103: l1-icache {
	compatible = "arm,arch-cache";
	};
	L1_D_103: l1-dcache {
	compatible = "arm,arch-cache";
	};
	};

	cpu-map {
	cluster0 {
	core0 {
	cpu = <&CPU0>;
	};

	core1 {
	cpu = <&CPU1>;
	};

	core2 {
	cpu = <&CPU2>;
	};

	core3 {
	cpu = <&CPU3>;
	};
	};

	cluster1 {
	core0 {
	cpu = <&CPU4>;
	};

	core1 {
	cpu = <&CPU5>;
	};

	core2 {
	cpu = <&CPU6>;
	};

	core3 {
	cpu = <&CPU7>;
	};
	};
	};

	idle-states {
	entry-method = "psci";

	LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
	compatible = "arm,idle-state";
	idle-state-name = "little-retention";
	arm,psci-suspend-param = <0x00000002>;
	entry-latency-us = <81>;
	exit-latency-us = <86>;
	min-residency-us = <200>;
	};

	LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
	compatible = "arm,idle-state";
	idle-state-name = "little-power-collapse";
	arm,psci-suspend-param = <0x40000003>;
	entry-latency-us = <273>;
	exit-latency-us = <612>;
	min-residency-us = <1000>;
	local-timer-stop;
	};

	BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
	compatible = "arm,idle-state";
	idle-state-name = "big-retention";
	arm,psci-suspend-param = <0x00000002>;
	entry-latency-us = <79>;
	exit-latency-us = <82>;
	min-residency-us = <200>;
	};

	BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
	compatible = "arm,idle-state";
	idle-state-name = "big-power-collapse";
	arm,psci-suspend-param = <0x40000003>;
	entry-latency-us = <336>;
	exit-latency-us = <525>;
	min-residency-us = <1000>;
	local-timer-stop;
	};
	};
	};

	firmware {
	scm {
	compatible = "qcom,scm-msm8998", "qcom,scm";
	};
	};

	tcsr_mutex: hwlock {
	compatible = "qcom,tcsr-mutex";
	syscon = <&tcsr_mutex_regs 0 0x1000>;
	#hwlock-cells = <1>;
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	rpm-glink {
	compatible = "qcom,glink-rpm";

	interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
	qcom,rpm-msg-ram = <&rpm_msg_ram>;
	mboxes = <&apcs_glb 0>;

	rpm_requests: rpm-requests {
	compatible = "qcom,rpm-msm8998";
	qcom,glink-channels = "rpm_requests";

	rpmcc: clock-controller {
	compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
	#clock-cells = <1>;
	};

	rpmpd: power-controller {
	compatible = "qcom,msm8998-rpmpd";
	#power-domain-cells = <1>;
	operating-points-v2 = <&rpmpd_opp_table>;

	rpmpd_opp_table: opp-table {
	compatible = "operating-points-v2";

	rpmpd_opp_ret: opp1 {
	opp-level = <16>;
	};

	rpmpd_opp_ret_plus: opp2 {
	opp-level = <32>;
	};

	rpmpd_opp_min_svs: opp3 {
	opp-level = <48>;
	};

	rpmpd_opp_low_svs: opp4 {
	opp-level = <64>;
	};

	rpmpd_opp_svs: opp5 {
	opp-level = <128>;
	};

	rpmpd_opp_svs_plus: opp6 {
	opp-level = <192>;
	};

	rpmpd_opp_nom: opp7 {
	opp-level = <256>;
	};

	rpmpd_opp_nom_plus: opp8 {
	opp-level = <320>;
	};

	rpmpd_opp_turbo: opp9 {
	opp-level = <384>;
	};

	rpmpd_opp_turbo_plus: opp10 {
	opp-level = <512>;
	};
	};
	};
	};
	};

	smem {
	compatible = "qcom,smem";
	memory-region = <&smem_mem>;
	hwlocks = <&tcsr_mutex 3>;
	};

	smp2p-lpass {
	compatible = "qcom,smp2p";
	qcom,smem = <443>, <429>;

	interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;

	mboxes = <&apcs_glb 10>;

	qcom,local-pid = <0>;
	qcom,remote-pid = <2>;

	adsp_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};

	adsp_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";

	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	smp2p-mpss {
	compatible = "qcom,smp2p";
	qcom,smem = <435>, <428>;
	interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
	mboxes = <&apcs_glb 14>;
	qcom,local-pid = <0>;
	qcom,remote-pid = <1>;

	modem_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};

	modem_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	smp2p-slpi {
	compatible = "qcom,smp2p";
	qcom,smem = <481>, <430>;
	interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
	mboxes = <&apcs_glb 26>;
	qcom,local-pid = <0>;
	qcom,remote-pid = <3>;

	slpi_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};

	slpi_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	thermal-zones {
	cpu0-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 1>;

	trips {
	cpu0_alert0: trip-point@0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu0_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu1-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 2>;

	trips {
	cpu1_alert0: trip-point@0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu1_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu2-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 3>;

	trips {
	cpu2_alert0: trip-point@0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu2_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu3-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 4>;

	trips {
	cpu3_alert0: trip-point@0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu3_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu4-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 7>;

	trips {
	cpu4_alert0: trip-point@0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu4_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu5-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 8>;

	trips {
	cpu5_alert0: trip-point@0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu5_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu6-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 9>;

	trips {
	cpu6_alert0: trip-point@0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu6_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpu7-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 10>;

	trips {
	cpu7_alert0: trip-point@0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu7_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	gpu-thermal-bottom {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 12>;

	trips {
	gpu1_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	gpu-thermal-top {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 13>;

	trips {
	gpu2_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	clust0-mhm-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 5>;

	trips {
	cluster0_mhm_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	clust1-mhm-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 6>;

	trips {
	cluster1_mhm_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	cluster1-l2-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 11>;

	trips {
	cluster1_l2_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	modem-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 1>;

	trips {
	modem_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	mem-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 2>;

	trips {
	mem_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	wlan-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 3>;

	trips {
	wlan_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	q6-dsp-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 4>;

	trips {
	q6_dsp_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	camera-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 5>;

	trips {
	camera_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	multimedia-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 6>;

	trips {
	multimedia_alert0: trip-point@0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
	};

	soc: soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	gcc: clock-controller@100000 {
	compatible = "qcom,gcc-msm8998";
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;
	reg = <0x00100000 0xb0000>;
	};

	rpm_msg_ram: memory@778000 {
	compatible = "qcom,rpm-msg-ram";
	reg = <0x00778000 0x7000>;
	};

	qfprom: qfprom@780000 {
	compatible = "qcom,qfprom";
	reg = <0x00780000 0x621c>;
	#address-cells = <1>;
	#size-cells = <1>;

	qusb2_hstx_trim: hstx-trim@423a {
	reg = <0x423a 0x1>;
	bits = <0 4>;
	};
	};

	tsens0: thermal@10ab000 {
	compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
	reg = <0x010ab000 0x1000>, /* TM */
	<0x010aa000 0x1000>; /* SROT */
	#qcom,sensors = <14>;
	interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "uplow", "critical";
	#thermal-sensor-cells = <1>;
	};

	tsens1: thermal@10ae000 {
	compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
	reg = <0x010ae000 0x1000>, /* TM */
	<0x010ad000 0x1000>; /* SROT */
	#qcom,sensors = <8>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "uplow", "critical";
	#thermal-sensor-cells = <1>;
	};

	anoc1_smmu: iommu@1680000 {
	compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
	reg = <0x01680000 0x10000>;
	#iommu-cells = <1>;

	#global-interrupts = <0>;
	interrupts =
	<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
	};

	anoc2_smmu: iommu@16c0000 {
	compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
	reg = <0x016c0000 0x40000>;
	#iommu-cells = <1>;

	#global-interrupts = <0>;
	interrupts =
	<GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
	};

	pcie0: pci@1c00000 {
	compatible = "qcom,pcie-msm8996";
	reg = <0x01c00000 0x2000>,
	<0x1b000000 0xf1d>,
	<0x1b000f20 0xa8>,
	<0x1b100000 0x100000>;
	reg-names = "parf", "dbi", "elbi", "config";
	device_type = "pci";
	linux,pci-domain = <0>;
	bus-range = <0x00 0xff>;
	#address-cells = <3>;
	#size-cells = <2>;
	num-lanes = <1>;
	phys = <&pciephy>;
	phy-names = "pciephy";

	ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
	<0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;

	#interrupt-cells = <1>;
	interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>,
	<0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
	<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
	<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
	<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
	<&gcc GCC_PCIE_0_AUX_CLK>;
	clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";

	power-domains = <&gcc PCIE_0_GDSC>;
	iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
	perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
	};

	phy@1c06000 {
	compatible = "qcom,msm8998-qmp-pcie-phy";
	reg = <0x01c06000 0x18c>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
	<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
	<&gcc GCC_PCIE_CLKREF_CLK>;
	clock-names = "aux", "cfg_ahb", "ref";

	resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
	reset-names = "phy", "common";

	vdda-phy-supply = <&vreg_l1a_0p875>;
	vdda-pll-supply = <&vreg_l2a_1p2>;

	pciephy: lane@1c06800 {
	reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
	#phy-cells = <0>;

	clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
	clock-names = "pipe0";
	clock-output-names = "pcie_0_pipe_clk_src";
	#clock-cells = <0>;
	};
	};

	ufshc: ufshc@1da4000 {
	compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
	reg = <0x01da4000 0x2500>;
	interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
	phys = <&ufsphy_lanes>;
	phy-names = "ufsphy";
	lanes-per-direction = <2>;
	power-domains = <&gcc UFS_GDSC>;
	#reset-cells = <1>;

	clock-names =
	"core_clk",
	"bus_aggr_clk",
	"iface_clk",
	"core_clk_unipro",
	"ref_clk",
	"tx_lane0_sync_clk",
	"rx_lane0_sync_clk",
	"rx_lane1_sync_clk";
	clocks =
	<&gcc GCC_UFS_AXI_CLK>,
	<&gcc GCC_AGGRE1_UFS_AXI_CLK>,
	<&gcc GCC_UFS_AHB_CLK>,
	<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
	<&rpmcc RPM_SMD_LN_BB_CLK1>,
	<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
	<&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
	<&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
	freq-table-hz =
	<50000000 200000000>,
	<0 0>,
	<0 0>,
	<37500000 150000000>,
	<0 0>,
	<0 0>,
	<0 0>,
	<0 0>;

	resets = <&gcc GCC_UFS_BCR>;
	reset-names = "rst";
	};

	ufsphy: phy@1da7000 {
	compatible = "qcom,msm8998-qmp-ufs-phy";
	reg = <0x01da7000 0x18c>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	clock-names =
	"ref",
	"ref_aux";
	clocks =
	<&gcc GCC_UFS_CLKREF_CLK>,
	<&gcc GCC_UFS_PHY_AUX_CLK>;

	reset-names = "ufsphy";
	resets = <&ufshc 0>;

	ufsphy_lanes: lanes@1da7400 {
	reg = <0x01da7400 0x128>,
	<0x01da7600 0x1fc>,
	<0x01da7c00 0x1dc>,
	<0x01da7800 0x128>,
	<0x01da7a00 0x1fc>;
	#phy-cells = <0>;
	};
	};

	tcsr_mutex_regs: syscon@1f40000 {
	compatible = "syscon";
	reg = <0x01f40000 0x40000>;
	};

	tlmm: pinctrl@3400000 {
	compatible = "qcom,msm8998-pinctrl";
	reg = <0x03400000 0xc00000>;
	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <0x2>;
	interrupt-controller;
	#interrupt-cells = <0x2>;
	};

	remoteproc_mss: remoteproc@4080000 {
	compatible = "qcom,msm8998-mss-pil";
	reg = <0x04080000 0x100>, <0x04180000 0x20>;
	reg-names = "qdsp6", "rmb";

	interrupts-extended =
	<&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
	<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
	<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "wdog", "fatal", "ready",
	"handover", "stop-ack",
	"shutdown-ack";

	clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
	<&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
	<&gcc GCC_BOOT_ROM_AHB_CLK>,
	<&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
	<&gcc GCC_MSS_SNOC_AXI_CLK>,
	<&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
	<&rpmcc RPM_SMD_QDSS_CLK>,
	<&rpmcc RPM_SMD_XO_CLK_SRC>;
	clock-names = "iface", "bus", "mem", "gpll0_mss",
	"snoc_axi", "mnoc_axi", "qdss", "xo";

	qcom,smem-states = <&modem_smp2p_out 0>;
	qcom,smem-state-names = "stop";

	resets = <&gcc GCC_MSS_RESTART>;
	reset-names = "mss_restart";

	qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;

	power-domains = <&rpmpd MSM8998_VDDCX>,
	<&rpmpd MSM8998_VDDMX>;
	power-domain-names = "cx", "mx";

	mba {
	memory-region = <&mba_mem>;
	};

	mpss {
	memory-region = <&mpss_mem>;
	};

	glink-edge {
	interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
	label = "modem";
	qcom,remote-pid = <1>;
	mboxes = <&apcs_glb 15>;
	};
	};

	gpucc: clock-controller@5065000 {
	compatible = "qcom,msm8998-gpucc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;
	reg = <0x05065000 0x9000>;

	clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
	<&gcc GPLL0_OUT_MAIN>;
	clock-names = "xo",
	"gpll0";
	};

	remoteproc_slpi: remoteproc@5800000 {
	compatible = "qcom,msm8998-slpi-pas";
	reg = <0x05800000 0x4040>;

	interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
	<&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	<&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	<&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	<&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "wdog", "fatal", "ready",
	"handover", "stop-ack";

	px-supply = <&vreg_lvs2a_1p8>;

	clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
	<&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
	clock-names = "xo", "aggre2";

	memory-region = <&slpi_mem>;

	qcom,smem-states = <&slpi_smp2p_out 0>;
	qcom,smem-state-names = "stop";

	power-domains = <&rpmpd MSM8998_SSCCX>;
	power-domain-names = "ssc_cx";

	status = "disabled";

	glink-edge {
	interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
	label = "dsps";
	qcom,remote-pid = <3>;
	mboxes = <&apcs_glb 27>;
	};
	};

	stm: stm@6002000 {
	compatible = "arm,coresight-stm", "arm,primecell";
	reg = <0x06002000 0x1000>,
	<0x16280000 0x180000>;
	reg-names = "stm-base", "stm-data-base";
	status = "disabled";

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	out-ports {
	port {
	stm_out: endpoint {
	remote-endpoint = <&funnel0_in7>;
	};
	};
	};
	};

	funnel1: funnel@6041000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0x06041000 0x1000>;
	status = "disabled";

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	out-ports {
	port {
	funnel0_out: endpoint {
	remote-endpoint =
	<&merge_funnel_in0>;
	};
	};
	};

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@7 {
	reg = <7>;
	funnel0_in7: endpoint {
	remote-endpoint = <&stm_out>;
	};
	};
	};
	};

	funnel2: funnel@6042000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0x06042000 0x1000>;
	status = "disabled";

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	out-ports {
	port {
	funnel1_out: endpoint {
	remote-endpoint =
	<&merge_funnel_in1>;
	};
	};
	};

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@6 {
	reg = <6>;
	funnel1_in6: endpoint {
	remote-endpoint =
	<&apss_merge_funnel_out>;
	};
	};
	};
	};

	funnel3: funnel@6045000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0x06045000 0x1000>;
	status = "disabled";

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	out-ports {
	port {
	merge_funnel_out: endpoint {
	remote-endpoint =
	<&etf_in>;
	};
	};
	};

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	merge_funnel_in0: endpoint {
	remote-endpoint =
	<&funnel0_out>;
	};
	};

	port@1 {
	reg = <1>;
	merge_funnel_in1: endpoint {
	remote-endpoint =
	<&funnel1_out>;
	};
	};
	};
	};

	replicator1: replicator@6046000 {
	compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
	reg = <0x06046000 0x1000>;
	status = "disabled";

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	out-ports {
	port {
	replicator_out: endpoint {
	remote-endpoint = <&etr_in>;
	};
	};
	};

	in-ports {
	port {
	replicator_in: endpoint {
	remote-endpoint = <&etf_out>;
	};
	};
	};
	};

	etf: etf@6047000 {
	compatible = "arm,coresight-tmc", "arm,primecell";
	reg = <0x06047000 0x1000>;
	status = "disabled";

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	out-ports {
	port {
	etf_out: endpoint {
	remote-endpoint =
	<&replicator_in>;
	};
	};
	};

	in-ports {
	port {
	etf_in: endpoint {
	remote-endpoint =
	<&merge_funnel_out>;
	};
	};
	};
	};

	etr: etr@6048000 {
	compatible = "arm,coresight-tmc", "arm,primecell";
	reg = <0x06048000 0x1000>;
	status = "disabled";

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";
	arm,scatter-gather;

	in-ports {
	port {
	etr_in: endpoint {
	remote-endpoint =
	<&replicator_out>;
	};
	};
	};
	};

	etm1: etm@7840000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0x07840000 0x1000>;
	status = "disabled";

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	cpu = <&CPU0>;

	out-ports {
	port {
	etm0_out: endpoint {
	remote-endpoint =
	<&apss_funnel_in0>;
	};
	};
	};
	};

	etm2: etm@7940000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0x07940000 0x1000>;
	status = "disabled";

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	cpu = <&CPU1>;

	out-ports {
	port {
	etm1_out: endpoint {
	remote-endpoint =
	<&apss_funnel_in1>;
	};
	};
	};
	};

	etm3: etm@7a40000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0x07a40000 0x1000>;
	status = "disabled";

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	cpu = <&CPU2>;

	out-ports {
	port {
	etm2_out: endpoint {
	remote-endpoint =
	<&apss_funnel_in2>;
	};
	};
	};
	};

	etm4: etm@7b40000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0x07b40000 0x1000>;
	status = "disabled";

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	cpu = <&CPU3>;

	out-ports {
	port {
	etm3_out: endpoint {
	remote-endpoint =
	<&apss_funnel_in3>;
	};
	};
	};
	};

	funnel4: funnel@7b60000 { /* APSS Funnel */
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0x07b60000 0x1000>;
	status = "disabled";

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	out-ports {
	port {
	apss_funnel_out: endpoint {
	remote-endpoint =
	<&apss_merge_funnel_in>;
	};
	};
	};

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	apss_funnel_in0: endpoint {
	remote-endpoint =
	<&etm0_out>;
	};
	};

	port@1 {
	reg = <1>;
	apss_funnel_in1: endpoint {
	remote-endpoint =
	<&etm1_out>;
	};
	};

	port@2 {
	reg = <2>;
	apss_funnel_in2: endpoint {
	remote-endpoint =
	<&etm2_out>;
	};
	};

	port@3 {
	reg = <3>;
	apss_funnel_in3: endpoint {
	remote-endpoint =
	<&etm3_out>;
	};
	};

	port@4 {
	reg = <4>;
	apss_funnel_in4: endpoint {
	remote-endpoint =
	<&etm4_out>;
	};
	};

	port@5 {
	reg = <5>;
	apss_funnel_in5: endpoint {
	remote-endpoint =
	<&etm5_out>;
	};
	};

	port@6 {
	reg = <6>;
	apss_funnel_in6: endpoint {
	remote-endpoint =
	<&etm6_out>;
	};
	};

	port@7 {
	reg = <7>;
	apss_funnel_in7: endpoint {
	remote-endpoint =
	<&etm7_out>;
	};
	};
	};
	};

	funnel5: funnel@7b70000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0x07b70000 0x1000>;
	status = "disabled";

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	out-ports {
	port {
	apss_merge_funnel_out: endpoint {
	remote-endpoint =
	<&funnel1_in6>;
	};
	};
	};

	in-ports {
	port {
	apss_merge_funnel_in: endpoint {
	remote-endpoint =
	<&apss_funnel_out>;
	};
	};
	};
	};

	etm5: etm@7c40000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0x07c40000 0x1000>;
	status = "disabled";

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	cpu = <&CPU4>;

	port{
	etm4_out: endpoint {
	remote-endpoint = <&apss_funnel_in4>;
	};
	};
	};

	etm6: etm@7d40000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0x07d40000 0x1000>;
	status = "disabled";

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	cpu = <&CPU5>;

	port{
	etm5_out: endpoint {
	remote-endpoint = <&apss_funnel_in5>;
	};
	};
	};

	etm7: etm@7e40000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0x07e40000 0x1000>;
	status = "disabled";

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	cpu = <&CPU6>;

	port{
	etm6_out: endpoint {
	remote-endpoint = <&apss_funnel_in6>;
	};
	};
	};

	etm8: etm@7f40000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0x07f40000 0x1000>;
	status = "disabled";

	clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
	clock-names = "apb_pclk", "atclk";

	cpu = <&CPU7>;

	port{
	etm7_out: endpoint {
	remote-endpoint = <&apss_funnel_in7>;
	};
	};
	};

	spmi_bus: spmi@800f000 {
	compatible = "qcom,spmi-pmic-arb";
	reg = <0x0800f000 0x1000>,
	<0x08400000 0x1000000>,
	<0x09400000 0x1000000>,
	<0x0a400000 0x220000>,
	<0x0800a000 0x3000>;
	reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
	interrupt-names = "periph_irq";
	interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
	qcom,ee = <0>;
	qcom,channel = <0>;
	#address-cells = <2>;
	#size-cells = <0>;
	interrupt-controller;
	#interrupt-cells = <4>;
	cell-index = <0>;
	};

	usb3: usb@a8f8800 {
	compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
	reg = <0x0a8f8800 0x400>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
	<&gcc GCC_USB30_MASTER_CLK>,
	<&gcc GCC_AGGRE1_USB3_AXI_CLK>,
	<&gcc GCC_USB30_MOCK_UTMI_CLK>,
	<&gcc GCC_USB30_SLEEP_CLK>;
	clock-names = "cfg_noc", "core", "iface", "mock_utmi",
	"sleep";

	assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
	<&gcc GCC_USB30_MASTER_CLK>;
	assigned-clock-rates = <19200000>, <120000000>;

	interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hs_phy_irq", "ss_phy_irq";

	power-domains = <&gcc USB_30_GDSC>;

	resets = <&gcc GCC_USB_30_BCR>;

	usb3_dwc3: dwc3@a800000 {
	compatible = "snps,dwc3";
	reg = <0x0a800000 0xcd00>;
	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
	snps,dis_u2_susphy_quirk;
	snps,dis_enblslpm_quirk;
	phys = <&qusb2phy>, <&usb1_ssphy>;
	phy-names = "usb2-phy", "usb3-phy";
	snps,has-lpm-erratum;
	snps,hird-threshold = /bits/ 8 <0x10>;
	};
	};

	usb3phy: phy@c010000 {
	compatible = "qcom,msm8998-qmp-usb3-phy";
	reg = <0x0c010000 0x18c>;
	status = "disabled";
	#clock-cells = <1>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
	<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	<&gcc GCC_USB3_CLKREF_CLK>;
	clock-names = "aux", "cfg_ahb", "ref";

	resets = <&gcc GCC_USB3_PHY_BCR>,
	<&gcc GCC_USB3PHY_PHY_BCR>;
	reset-names = "phy", "common";

	usb1_ssphy: lane@c010200 {
	reg = <0xc010200 0x128>,
	<0xc010400 0x200>,
	<0xc010c00 0x20c>,
	<0xc010600 0x128>,
	<0xc010800 0x200>;
	#phy-cells = <0>;
	clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
	clock-names = "pipe0";
	clock-output-names = "usb3_phy_pipe_clk_src";
	};
	};

	qusb2phy: phy@c012000 {
	compatible = "qcom,msm8998-qusb2-phy";
	reg = <0x0c012000 0x2a8>;
	status = "disabled";
	#phy-cells = <0>;

	clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	<&gcc GCC_RX1_USB2_CLKREF_CLK>;
	clock-names = "cfg_ahb", "ref";

	resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

	nvmem-cells = <&qusb2_hstx_trim>;
	};

	sdhc2: sdhci@c0a4900 {
	compatible = "qcom,sdhci-msm-v4";
	reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
	reg-names = "hc_mem", "core_mem";

	interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hc_irq", "pwr_irq";

	clock-names = "iface", "core", "xo";
	clocks = <&gcc GCC_SDCC2_AHB_CLK>,
	<&gcc GCC_SDCC2_APPS_CLK>,
	<&xo>;
	bus-width = <4>;
	status = "disabled";
	};

	blsp1_dma: dma@c144000 {
	compatible = "qcom,bam-v1.7.0";
	reg = <0x0c144000 0x25000>;
	interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	qcom,controlled-remotely;
	num-channels = <18>;
	qcom,num-ees = <4>;
	};

	blsp1_uart3: serial@c171000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x0c171000 0x1000>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp1_uart3_on>;
	status = "disabled";
	};

	blsp1_i2c1: i2c@c175000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x0c175000 0x600>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	clock-frequency = <400000>;

	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	blsp1_i2c2: i2c@c176000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x0c176000 0x600>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	clock-frequency = <400000>;

	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	blsp1_i2c3: i2c@c177000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x0c177000 0x600>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	clock-frequency = <400000>;

	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	blsp1_i2c4: i2c@c178000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x0c178000 0x600>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	clock-frequency = <400000>;

	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	blsp1_i2c5: i2c@c179000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x0c179000 0x600>;
	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	clock-frequency = <400000>;

	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	blsp1_i2c6: i2c@c17a000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x0c17a000 0x600>;
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	clock-frequency = <400000>;

	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	blsp2_uart1: serial@c1b0000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x0c1b0000 0x1000>;
	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
	<&gcc GCC_BLSP2_AHB_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	blsp2_i2c0: i2c@c1b5000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x0c1b5000 0x600>;
	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
	<&gcc GCC_BLSP2_AHB_CLK>;
	clock-names = "core", "iface";
	clock-frequency = <400000>;

	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	blsp2_i2c1: i2c@c1b6000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x0c1b6000 0x600>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
	<&gcc GCC_BLSP2_AHB_CLK>;
	clock-names = "core", "iface";
	clock-frequency = <400000>;

	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	blsp2_i2c2: i2c@c1b7000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x0c1b7000 0x600>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
	<&gcc GCC_BLSP2_AHB_CLK>;
	clock-names = "core", "iface";
	clock-frequency = <400000>;

	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	blsp2_i2c3: i2c@c1b8000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x0c1b8000 0x600>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
	<&gcc GCC_BLSP2_AHB_CLK>;
	clock-names = "core", "iface";
	clock-frequency = <400000>;

	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	blsp2_i2c4: i2c@c1b9000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x0c1b9000 0x600>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
	<&gcc GCC_BLSP2_AHB_CLK>;
	clock-names = "core", "iface";
	clock-frequency = <400000>;

	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	blsp2_i2c5: i2c@c1ba000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x0c1ba000 0x600>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
	<&gcc GCC_BLSP2_AHB_CLK>;
	clock-names = "core", "iface";
	clock-frequency = <400000>;

	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	remoteproc_adsp: remoteproc@17300000 {
	compatible = "qcom,msm8998-adsp-pas";
	reg = <0x17300000 0x4040>;

	interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
	<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "wdog", "fatal", "ready",
	"handover", "stop-ack";

	clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
	clock-names = "xo";

	memory-region = <&adsp_mem>;

	qcom,smem-states = <&adsp_smp2p_out 0>;
	qcom,smem-state-names = "stop";

	power-domains = <&rpmpd MSM8998_VDDCX>;
	power-domain-names = "cx";

	status = "disabled";

	glink-edge {
	interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
	label = "lpass";
	qcom,remote-pid = <2>;
	mboxes = <&apcs_glb 9>;
	};
	};

	apcs_glb: mailbox@17911000 {
	compatible = "qcom,msm8998-apcs-hmss-global";
	reg = <0x17911000 0x1000>;

	#mbox-cells = <1>;
	};

	timer@17920000 {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "arm,armv7-timer-mem";
	reg = <0x17920000 0x1000>;

	frame@17921000 {
	frame-number = <0>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x17921000 0x1000>,
	<0x17922000 0x1000>;
	};

	frame@17923000 {
	frame-number = <1>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x17923000 0x1000>;
	status = "disabled";
	};

	frame@17924000 {
	frame-number = <2>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x17924000 0x1000>;
	status = "disabled";
	};

	frame@17925000 {
	frame-number = <3>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x17925000 0x1000>;
	status = "disabled";
	};

	frame@17926000 {
	frame-number = <4>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x17926000 0x1000>;
	status = "disabled";
	};

	frame@17927000 {
	frame-number = <5>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x17927000 0x1000>;
	status = "disabled";
	};

	frame@17928000 {
	frame-number = <6>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x17928000 0x1000>;
	status = "disabled";
	};
	};

	intc: interrupt-controller@17a00000 {
	compatible = "arm,gic-v3";
	reg = <0x17a00000 0x10000>, /* GICD */
	<0x17b00000 0x100000>; /* GICR * 8 */
	#interrupt-cells = <3>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	interrupt-controller;
	#redistributor-regions = <1>;
	redistributor-stride = <0x0 0x20000>;
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	wifi: wifi@18800000 {
	compatible = "qcom,wcn3990-wifi";
	status = "disabled";
	reg = <0x18800000 0x800000>;
	reg-names = "membase";
	memory-region = <&wlan_msa_mem>;
	clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
	clock-names = "cxo_ref_clk_pin";
	interrupts =
	<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
	iommus = <&anoc2_smmu 0x1900>,
	<&anoc2_smmu 0x1901>;
	qcom,snoc-host-cap-8bit-quirk;
	};
	};
	};

	#include "msm8998-pins.dtsi"
	diff --git a/sys/gnu/dts/arm64/qcom/pm6150.dtsi b/sys/gnu/dts/arm64/qcom/pm6150.dtsi
	index 23534639f455..57af0b4a384d 100644
	--- a/sys/gnu/dts/arm64/qcom/pm6150.dtsi
	+++ b/sys/gnu/dts/arm64/qcom/pm6150.dtsi
	@@ -1,72 +1,72 @@
	// SPDX-License-Identifier: BSD-3-Clause
	// Copyright (c) 2019, The Linux Foundation. All rights reserved.

	#include <dt-bindings/iio/qcom,spmi-vadc.h>
	#include <dt-bindings/input/linux-event-codes.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/spmi/spmi.h>
	#include <dt-bindings/thermal/thermal.h>

	&spmi_bus {
	pm6150_lsid0: pmic@0 {
	compatible = "qcom,pm6150", "qcom,spmi-pmic";
	reg = <0x0 SPMI_USID>;
	#address-cells = <1>;
	#size-cells = <0>;

	pm6150_pon: pon@800 {
	compatible = "qcom,pm8998-pon";
	reg = <0x800>;
	mode-bootloader = <0x2>;
	mode-recovery = <0x1>;

	- pwrkey {
	+ pm6150_pwrkey: pwrkey {
	compatible = "qcom,pm8941-pwrkey";
	interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
	debounce = <15625>;
	bias-pull-up;
	linux,code = <KEY_POWER>;
	};
	};

	pm6150_temp: temp-alarm@2400 {
	compatible = "qcom,spmi-temp-alarm";
	reg = <0x2400>;
	interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
	io-channels = <&pm6150_adc ADC5_DIE_TEMP>;
	io-channel-names = "thermal";
	#thermal-sensor-cells = <0>;
	};

	pm6150_adc: adc@3100 {
	compatible = "qcom,spmi-adc5";
	reg = <0x3100>;
	interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
	#address-cells = <1>;
	#size-cells = <0>;
	#io-channel-cells = <1>;

	adc-chan@6 {
	reg = <ADC5_DIE_TEMP>;
	label = "die_temp";
	};
	};

	pm6150_gpio: gpios@c000 {
	compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio";
	reg = <0xc000>;
	gpio-controller;
	gpio-ranges = <&pm6150_gpio 0 0 10>;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	pm6150_lsid1: pmic@1 {
	compatible = "qcom,pm6150", "qcom,spmi-pmic";
	reg = <0x1 SPMI_USID>;
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/qcom/pm8998.dtsi b/sys/gnu/dts/arm64/qcom/pm8998.dtsi
	index dc2ce23cde05..67283d60e2ac 100644
	--- a/sys/gnu/dts/arm64/qcom/pm8998.dtsi
	+++ b/sys/gnu/dts/arm64/qcom/pm8998.dtsi
	@@ -1,112 +1,112 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/* Copyright 2018 Google LLC. */

	#include <dt-bindings/iio/qcom,spmi-vadc.h>
	#include <dt-bindings/input/linux-event-codes.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/spmi/spmi.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	thermal-zones {
	pm8998 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&pm8998_temp>;

	trips {
	pm8998_alert0: pm8998-alert0 {
	temperature = <105000>;
	hysteresis = <2000>;
	type = "passive";
	};
	pm8998_crit: pm8998-crit {
	temperature = <125000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};
	};
	};

	&spmi_bus {
	pm8998_lsid0: pmic@0 {
	compatible = "qcom,pm8998", "qcom,spmi-pmic";
	reg = <0x0 SPMI_USID>;
	#address-cells = <1>;
	#size-cells = <0>;

	pm8998_pon: pon@800 {
	compatible = "qcom,pm8998-pon";

	reg = <0x800>;
	mode-bootloader = <0x2>;
	mode-recovery = <0x1>;

	- pwrkey {
	+ pm8998_pwrkey: pwrkey {
	compatible = "qcom,pm8941-pwrkey";
	interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
	debounce = <15625>;
	bias-pull-up;
	linux,code = <KEY_POWER>;
	};
	};

	pm8998_temp: temp-alarm@2400 {
	compatible = "qcom,spmi-temp-alarm";
	reg = <0x2400>;
	interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
	io-channels = <&pm8998_adc ADC5_DIE_TEMP>;
	io-channel-names = "thermal";
	#thermal-sensor-cells = <0>;
	};

	pm8998_coincell: coincell@2800 {
	compatible = "qcom,pm8941-coincell";
	reg = <0x2800>;

	status = "disabled";
	};

	pm8998_adc: adc@3100 {
	compatible = "qcom,spmi-adc-rev2";
	reg = <0x3100>;
	interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
	#address-cells = <1>;
	#size-cells = <0>;
	#io-channel-cells = <1>;

	adc-chan@6 {
	reg = <ADC5_DIE_TEMP>;
	label = "die_temp";
	};
	};

	rtc@6000 {
	compatible = "qcom,pm8941-rtc";
	reg = <0x6000>, <0x6100>;
	reg-names = "rtc", "alarm";
	interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
	};

	pm8998_gpio: gpios@c000 {
	compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio";
	reg = <0xc000>;
	gpio-controller;
	gpio-ranges = <&pm8998_gpio 0 0 26>;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	};

	pm8998_lsid1: pmic@1 {
	compatible = "qcom,pm8998", "qcom,spmi-pmic";
	reg = <0x1 SPMI_USID>;
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/qcom/qcs404-evb.dtsi b/sys/gnu/dts/arm64/qcom/qcs404-evb.dtsi
	index 522d3ef72df5..afe69e8f3114 100644
	--- a/sys/gnu/dts/arm64/qcom/qcs404-evb.dtsi
	+++ b/sys/gnu/dts/arm64/qcom/qcs404-evb.dtsi
	@@ -1,311 +1,312 @@
	// SPDX-License-Identifier: GPL-2.0
	// Copyright (c) 2018, Linaro Limited

	#include <dt-bindings/gpio/gpio.h>
	#include "qcs404.dtsi"
	#include "pms405.dtsi"

	/ {
	aliases {
	serial0 = &blsp1_uart2;
	serial1 = &blsp1_uart3;
	};

	chosen {
	stdout-path = "serial0";
	};

	vph_pwr: vph-pwr-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vph_pwr";
	regulator-always-on;
	regulator-boot-on;
	};

	vdd_ch0_3p3:
	vdd_esmps3_3p3: vdd-esmps3-3p3-regulator {
	compatible = "regulator-fixed";
	regulator-name = "eSMPS3_3P3";

	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};
	};

	&blsp1_uart3 {
	status = "okay";

	bluetooth {
	compatible = "qcom,wcn3990-bt";
	vddio-supply = <&vreg_l6_1p8>;
	vddxo-supply = <&vreg_l5_1p8>;
	vddrf-supply = <&vreg_l1_1p3>;
	vddch0-supply = <&vdd_ch0_3p3>;

	local-bd-address = [ 02 00 00 00 5a ad ];

	max-speed = <3200000>;
	};
	};

	&blsp1_dma {
	qcom,controlled-remotely;
	};

	&blsp2_dma {
	qcom,controlled-remotely;
	};

	&gcc {
	protected-clocks = <GCC_BIMC_CDSP_CLK>,
	<GCC_CDSP_CFG_AHB_CLK>,
	<GCC_CDSP_BIMC_CLK_SRC>,
	<GCC_CDSP_TBU_CLK>,
	<141>, /* GCC_WCSS_Q6_AHB_CLK */
	<142>; /* GCC_WCSS_Q6_AXIM_CLK */
	};

	&pms405_spmi_regulators {
	vdd_s3-supply = <&vph_pwr>;

	pms405_s3: s3 {
	regulator-always-on;
	regulator-boot-on;
	regulator-name = "vdd_apc";
	regulator-initial-mode = <1>;
	regulator-min-microvolt = <1048000>;
	regulator-max-microvolt = <1384000>;
	};
	};

	&pcie {
	status = "ok";

	perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>;

	pinctrl-names = "default";
	pinctrl-0 = <&perst_state>;
	};

	&pcie_phy {
	status = "ok";

	vdda-vp-supply = <&vreg_l3_1p05>;
	vdda-vph-supply = <&vreg_l5_1p8>;
	};

	&remoteproc_adsp {
	status = "ok";
	};

	&remoteproc_cdsp {
	status = "ok";
	};

	&remoteproc_wcss {
	status = "ok";
	};

	&rpm_requests {
	pms405-regulators {
	compatible = "qcom,rpm-pms405-regulators";

	vdd_s1-supply = <&vph_pwr>;
	vdd_s2-supply = <&vph_pwr>;
	vdd_s3-supply = <&vph_pwr>;
	vdd_s4-supply = <&vph_pwr>;
	vdd_s5-supply = <&vph_pwr>;
	vdd_l1_l2-supply = <&vreg_s5_1p35>;
	vdd_l3_l8-supply = <&vreg_s5_1p35>;
	vdd_l4-supply = <&vreg_s5_1p35>;
	vdd_l5_l6-supply = <&vreg_s4_1p8>;
	vdd_l7-supply = <&vph_pwr>;
	vdd_l9-supply = <&vreg_s5_1p35>;
	vdd_l10_l11_l12_l13-supply = <&vph_pwr>;

	vreg_s4_1p8: s4 {
	regulator-min-microvolt = <1728000>;
	regulator-max-microvolt = <1920000>;
	};

	vreg_s5_1p35: s5 {
	regulator-min-microvolt = <1352000>;
	regulator-max-microvolt = <1352000>;
	};

	vreg_l1_1p3: l1 {
	regulator-min-microvolt = <1240000>;
	regulator-max-microvolt = <1352000>;
	};

	vreg_l2_1p275: l2 {
	regulator-min-microvolt = <1048000>;
	regulator-max-microvolt = <1280000>;
	};

	vreg_l3_1p05: l3 {
	regulator-min-microvolt = <1048000>;
	regulator-max-microvolt = <1160000>;
	};

	vreg_l4_1p2: l4 {
	regulator-min-microvolt = <1144000>;
	regulator-max-microvolt = <1256000>;
	};

	vreg_l5_1p8: l5 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	vreg_l6_1p8: l6 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	vreg_l7_1p8: l7 {
	regulator-min-microvolt = <1616000>;
	regulator-max-microvolt = <3000000>;
	};

	vreg_l8_1p2: l8 {
	regulator-min-microvolt = <1136000>;
	regulator-max-microvolt = <1352000>;
	};

	vreg_l10_3p3: l10 {
	regulator-min-microvolt = <2936000>;
	regulator-max-microvolt = <3088000>;
	};

	vreg_l11_sdc2: l11 {
	regulator-min-microvolt = <2696000>;
	regulator-max-microvolt = <3304000>;
	};

	vreg_l12_3p3: l12 {
	regulator-min-microvolt = <2968000>;
	regulator-max-microvolt = <3300000>;
	};

	vreg_l13_3p3: l13 {
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3300000>;
	};
	};
	};

	&sdcc1 {
	status = "ok";

	+ supports-cqe;
	mmc-ddr-1_8v;
	mmc-hs400-1_8v;
	bus-width = <8>;
	non-removable;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sdc1_on>;
	pinctrl-1 = <&sdc1_off>;
	};

	&tlmm {
	perst_state: perst {
	pins = "gpio43";
	function = "gpio";

	drive-strength = <2>;
	bias-disable;
	output-low;
	};

	sdc1_on: sdc1-on {
	clk {
	pins = "sdc1_clk";
	bias-disable;
	drive-strength = <16>;
	};

	cmd {
	pins = "sdc1_cmd";
	bias-pull-up;
	drive-strength = <10>;
	};

	data {
	pins = "sdc1_data";
	bias-pull-up;
	drive-strength = <10>;
	};

	rclk {
	pins = "sdc1_rclk";
	bias-pull-down;
	};
	};

	sdc1_off: sdc1-off {
	clk {
	pins = "sdc1_clk";
	bias-disable;
	drive-strength = <2>;
	};

	cmd {
	pins = "sdc1_cmd";
	bias-pull-up;
	drive-strength = <2>;
	};

	data {
	pins = "sdc1_data";
	bias-pull-up;
	drive-strength = <2>;
	};

	rclk {
	pins = "sdc1_rclk";
	bias-pull-down;
	};
	};
	};

	&wifi {
	status = "okay";
	vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>;
	vdd-1.8-xo-supply = <&vreg_l5_1p8>;
	vdd-1.3-rfa-supply = <&vreg_l1_1p3>;
	};

	/* PINCTRL - additions to nodes defined in qcs404.dtsi */

	&blsp1_uart2_default {
	rx {
	drive-strength = <2>;
	bias-disable;
	};

	tx {
	drive-strength = <2>;
	bias-disable;
	};
	};

	&blsp1_uart3_default {
	cts {
	pins = "gpio84";
	bias-disable;
	};

	rts-tx {
	pins = "gpio85", "gpio82";
	drive-strength = <2>;
	bias-disable;
	};

	rx {
	pins = "gpio83";
	bias-pull-up;
	};
	};
	diff --git a/sys/gnu/dts/arm64/qcom/qcs404.dtsi b/sys/gnu/dts/arm64/qcom/qcs404.dtsi
	index 4ee1e3d5f123..f149a538c1cc 100644
	--- a/sys/gnu/dts/arm64/qcom/qcs404.dtsi
	+++ b/sys/gnu/dts/arm64/qcom/qcs404.dtsi
	@@ -1,1527 +1,1527 @@
	// SPDX-License-Identifier: GPL-2.0
	// Copyright (c) 2018, Linaro Limited

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/qcom,gcc-qcs404.h>
	#include <dt-bindings/clock/qcom,turingcc-qcs404.h>
	#include <dt-bindings/clock/qcom,rpmcc.h>
	#include <dt-bindings/power/qcom-rpmpd.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	clocks {
	xo_board: xo-board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <19200000>;
	};

	sleep_clk: sleep-clk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	CPU0: cpu@100 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x100>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	next-level-cache = <&L2_0>;
	#cooling-cells = <2>;
	clocks = <&apcs_glb>;
	operating-points-v2 = <&cpu_opp_table>;
	power-domains = <&cpr>;
	power-domain-names = "cpr";
	};

	CPU1: cpu@101 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x101>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	next-level-cache = <&L2_0>;
	#cooling-cells = <2>;
	clocks = <&apcs_glb>;
	operating-points-v2 = <&cpu_opp_table>;
	power-domains = <&cpr>;
	power-domain-names = "cpr";
	};

	CPU2: cpu@102 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x102>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	next-level-cache = <&L2_0>;
	#cooling-cells = <2>;
	clocks = <&apcs_glb>;
	operating-points-v2 = <&cpu_opp_table>;
	power-domains = <&cpr>;
	power-domain-names = "cpr";
	};

	CPU3: cpu@103 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x103>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	next-level-cache = <&L2_0>;
	#cooling-cells = <2>;
	clocks = <&apcs_glb>;
	operating-points-v2 = <&cpu_opp_table>;
	power-domains = <&cpr>;
	power-domain-names = "cpr";
	};

	L2_0: l2-cache {
	compatible = "cache";
	cache-level = <2>;
	};

	idle-states {
	entry-method = "psci";

	CPU_SLEEP_0: cpu-sleep-0 {
	compatible = "arm,idle-state";
	idle-state-name = "standalone-power-collapse";
	arm,psci-suspend-param = <0x40000003>;
	entry-latency-us = <125>;
	exit-latency-us = <180>;
	min-residency-us = <595>;
	local-timer-stop;
	};
	};
	};

	cpu_opp_table: cpu-opp-table {
	compatible = "operating-points-v2-kryo-cpu";
	opp-shared;

	opp-1094400000 {
	opp-hz = /bits/ 64 <1094400000>;
	required-opps = <&cpr_opp1>;
	};
	opp-1248000000 {
	opp-hz = /bits/ 64 <1248000000>;
	required-opps = <&cpr_opp2>;
	};
	opp-1401600000 {
	opp-hz = /bits/ 64 <1401600000>;
	required-opps = <&cpr_opp3>;
	};
	};

	cpr_opp_table: cpr-opp-table {
	compatible = "operating-points-v2-qcom-level";

	cpr_opp1: opp1 {
	opp-level = <1>;
	qcom,opp-fuse-level = <1>;
	};
	cpr_opp2: opp2 {
	opp-level = <2>;
	qcom,opp-fuse-level = <2>;
	};
	cpr_opp3: opp3 {
	opp-level = <3>;
	qcom,opp-fuse-level = <3>;
	};
	};

	firmware {
	scm: scm {
	compatible = "qcom,scm-qcs404", "qcom,scm";
	#reset-cells = <1>;
	};
	};

	memory@80000000 {
	device_type = "memory";
	/* We expect the bootloader to fill in the size */
	reg = <0 0x80000000 0 0>;
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	tz_apps_mem: memory@85900000 {
	reg = <0 0x85900000 0 0x500000>;
	no-map;
	};

	xbl_mem: memory@85e00000 {
	reg = <0 0x85e00000 0 0x100000>;
	no-map;
	};

	smem_region: memory@85f00000 {
	reg = <0 0x85f00000 0 0x200000>;
	no-map;
	};

	tz_mem: memory@86100000 {
	reg = <0 0x86100000 0 0x300000>;
	no-map;
	};

	wlan_fw_mem: memory@86400000 {
	reg = <0 0x86400000 0 0x1100000>;
	no-map;
	};

	adsp_fw_mem: memory@87500000 {
	reg = <0 0x87500000 0 0x1a00000>;
	no-map;
	};

	cdsp_fw_mem: memory@88f00000 {
	reg = <0 0x88f00000 0 0x600000>;
	no-map;
	};

	wlan_msa_mem: memory@89500000 {
	reg = <0 0x89500000 0 0x100000>;
	no-map;
	};

	uefi_mem: memory@9f800000 {
	reg = <0 0x9f800000 0 0x800000>;
	no-map;
	};
	};

	rpm-glink {
	compatible = "qcom,glink-rpm";

	interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
	qcom,rpm-msg-ram = <&rpm_msg_ram>;
	mboxes = <&apcs_glb 0>;

	rpm_requests: glink-channel {
	compatible = "qcom,rpm-qcs404";
	qcom,glink-channels = "rpm_requests";

	rpmcc: clock-controller {
	compatible = "qcom,rpmcc-qcs404";
	#clock-cells = <1>;
	};

	rpmpd: power-controller {
	compatible = "qcom,qcs404-rpmpd";
	#power-domain-cells = <1>;
	operating-points-v2 = <&rpmpd_opp_table>;

	rpmpd_opp_table: opp-table {
	compatible = "operating-points-v2";

	rpmpd_opp_ret: opp1 {
	opp-level = <16>;
	};

	rpmpd_opp_ret_plus: opp2 {
	opp-level = <32>;
	};

	rpmpd_opp_min_svs: opp3 {
	opp-level = <48>;
	};

	rpmpd_opp_low_svs: opp4 {
	opp-level = <64>;
	};

	rpmpd_opp_svs: opp5 {
	opp-level = <128>;
	};

	rpmpd_opp_svs_plus: opp6 {
	opp-level = <192>;
	};

	rpmpd_opp_nom: opp7 {
	opp-level = <256>;
	};

	rpmpd_opp_nom_plus: opp8 {
	opp-level = <320>;
	};

	rpmpd_opp_turbo: opp9 {
	opp-level = <384>;
	};

	rpmpd_opp_turbo_no_cpr: opp10 {
	opp-level = <416>;
	};

	rpmpd_opp_turbo_plus: opp11 {
	opp-level = <512>;
	};
	};
	};
	};
	};

	smem {
	compatible = "qcom,smem";

	memory-region = <&smem_region>;
	qcom,rpm-msg-ram = <&rpm_msg_ram>;

	hwlocks = <&tcsr_mutex 3>;
	};

	tcsr_mutex: hwlock {
	compatible = "qcom,tcsr-mutex";
	syscon = <&tcsr_mutex_regs 0 0x1000>;
	#hwlock-cells = <1>;
	};

	soc: soc@0 {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	turingcc: clock-controller@800000 {
	compatible = "qcom,qcs404-turingcc";
	reg = <0x00800000 0x30000>;
	clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;

	#clock-cells = <1>;
	#reset-cells = <1>;

	status = "disabled";
	};

	rpm_msg_ram: memory@60000 {
	compatible = "qcom,rpm-msg-ram";
	reg = <0x00060000 0x6000>;
	};

	qfprom: qfprom@a4000 {
	compatible = "qcom,qfprom";
	reg = <0x000a4000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	tsens_caldata: caldata@d0 {
	reg = <0x1f8 0x14>;
	};
	cpr_efuse_speedbin: speedbin@13c {
	reg = <0x13c 0x4>;
	bits = <2 3>;
	};
	cpr_efuse_quot_offset1: qoffset1@231 {
	reg = <0x231 0x4>;
	bits = <4 7>;
	};
	cpr_efuse_quot_offset2: qoffset2@232 {
	reg = <0x232 0x4>;
	bits = <3 7>;
	};
	cpr_efuse_quot_offset3: qoffset3@233 {
	reg = <0x233 0x4>;
	bits = <2 7>;
	};
	cpr_efuse_init_voltage1: ivoltage1@229 {
	reg = <0x229 0x4>;
	bits = <4 6>;
	};
	cpr_efuse_init_voltage2: ivoltage2@22a {
	reg = <0x22a 0x4>;
	bits = <2 6>;
	};
	cpr_efuse_init_voltage3: ivoltage3@22b {
	reg = <0x22b 0x4>;
	bits = <0 6>;
	};
	cpr_efuse_quot1: quot1@22b {
	reg = <0x22b 0x4>;
	bits = <6 12>;
	};
	cpr_efuse_quot2: quot2@22d {
	reg = <0x22d 0x4>;
	bits = <2 12>;
	};
	cpr_efuse_quot3: quot3@230 {
	reg = <0x230 0x4>;
	bits = <0 12>;
	};
	cpr_efuse_ring1: ring1@228 {
	reg = <0x228 0x4>;
	bits = <0 3>;
	};
	cpr_efuse_ring2: ring2@228 {
	reg = <0x228 0x4>;
	bits = <4 3>;
	};
	cpr_efuse_ring3: ring3@229 {
	reg = <0x229 0x4>;
	bits = <0 3>;
	};
	cpr_efuse_revision: revision@218 {
	reg = <0x218 0x4>;
	bits = <3 3>;
	};
	};

	rng: rng@e3000 {
	compatible = "qcom,prng-ee";
	reg = <0x000e3000 0x1000>;
	clocks = <&gcc GCC_PRNG_AHB_CLK>;
	clock-names = "core";
	};

	bimc: interconnect@400000 {
	reg = <0x00400000 0x80000>;
	compatible = "qcom,qcs404-bimc";
	#interconnect-cells = <1>;
	clock-names = "bus", "bus_a";
	clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
	<&rpmcc RPM_SMD_BIMC_A_CLK>;
	};

	tsens: thermal-sensor@4a9000 {
	compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
	reg = <0x004a9000 0x1000>, /* TM */
	<0x004a8000 0x1000>; /* SROT */
	nvmem-cells = <&tsens_caldata>;
	nvmem-cell-names = "calib";
	#qcom,sensors = <10>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "uplow";
	#thermal-sensor-cells = <1>;
	};

	pcnoc: interconnect@500000 {
	reg = <0x00500000 0x15080>;
	compatible = "qcom,qcs404-pcnoc";
	#interconnect-cells = <1>;
	clock-names = "bus", "bus_a";
	clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
	<&rpmcc RPM_SMD_PNOC_A_CLK>;
	};

	snoc: interconnect@580000 {
	reg = <0x00580000 0x23080>;
	compatible = "qcom,qcs404-snoc";
	#interconnect-cells = <1>;
	clock-names = "bus", "bus_a";
	clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
	<&rpmcc RPM_SMD_SNOC_A_CLK>;
	};

	remoteproc_cdsp: remoteproc@b00000 {
	compatible = "qcom,qcs404-cdsp-pas";
	reg = <0x00b00000 0x4040>;

	interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
	<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	<&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "wdog", "fatal", "ready",
	"handover", "stop-ack";

	clocks = <&xo_board>,
	<&gcc GCC_CDSP_CFG_AHB_CLK>,
	<&gcc GCC_CDSP_TBU_CLK>,
	<&gcc GCC_BIMC_CDSP_CLK>,
	<&turingcc TURING_WRAPPER_AON_CLK>,
	<&turingcc TURING_Q6SS_AHBS_AON_CLK>,
	<&turingcc TURING_Q6SS_AHBM_AON_CLK>,
	<&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
	clock-names = "xo",
	"sway",
	"tbu",
	"bimc",
	"ahb_aon",
	"q6ss_slave",
	"q6ss_master",
	"q6_axim";

	resets = <&gcc GCC_CDSP_RESTART>;
	reset-names = "restart";

	qcom,halt-regs = <&tcsr 0x19004>;

	memory-region = <&cdsp_fw_mem>;

	qcom,smem-states = <&cdsp_smp2p_out 0>;
	qcom,smem-state-names = "stop";

	status = "disabled";

	glink-edge {
	interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;

	qcom,remote-pid = <5>;
	mboxes = <&apcs_glb 12>;

	label = "cdsp";
	};
	};

	tlmm: pinctrl@1000000 {
	compatible = "qcom,qcs404-pinctrl";
	reg = <0x01000000 0x200000>,
	<0x01300000 0x200000>,
	<0x07b00000 0x200000>;
	reg-names = "south", "north", "east";
	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	gpio-ranges = <&tlmm 0 0 120>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;

	blsp1_i2c0_default: blsp1-i2c0-default {
	pins = "gpio32", "gpio33";
	function = "blsp_i2c0";
	};

	blsp1_i2c1_default: blsp1-i2c1-default {
	pins = "gpio24", "gpio25";
	function = "blsp_i2c1";
	};

	blsp1_i2c2_default: blsp1-i2c2-default {
	sda {
	pins = "gpio19";
	function = "blsp_i2c_sda_a2";
	};

	scl {
	pins = "gpio20";
	function = "blsp_i2c_scl_a2";
	};
	};

	blsp1_i2c3_default: blsp1-i2c3-default {
	pins = "gpio84", "gpio85";
	function = "blsp_i2c3";
	};

	blsp1_i2c4_default: blsp1-i2c4-default {
	pins = "gpio117", "gpio118";
	function = "blsp_i2c4";
	};

	blsp1_uart0_default: blsp1-uart0-default {
	pins = "gpio30", "gpio31", "gpio32", "gpio33";
	function = "blsp_uart0";
	};

	blsp1_uart1_default: blsp1-uart1-default {
	pins = "gpio22", "gpio23";
	function = "blsp_uart1";
	};

	blsp1_uart2_default: blsp1-uart2-default {
	rx {
	pins = "gpio18";
	function = "blsp_uart_rx_a2";
	};

	tx {
	pins = "gpio17";
	function = "blsp_uart_tx_a2";
	};
	};

	blsp1_uart3_default: blsp1-uart3-default {
	pins = "gpio82", "gpio83", "gpio84", "gpio85";
	function = "blsp_uart3";
	};

	blsp2_i2c0_default: blsp2-i2c0-default {
	pins = "gpio28", "gpio29";
	function = "blsp_i2c5";
	};

	blsp1_spi0_default: blsp1-spi0-default {
	pins = "gpio30", "gpio31", "gpio32", "gpio33";
	function = "blsp_spi0";
	};

	blsp1_spi1_default: blsp1-spi1-default {
	pins = "gpio22", "gpio23", "gpio24", "gpio25";
	function = "blsp_spi1";
	};

	blsp1_spi2_default: blsp1-spi2-default {
	pins = "gpio17", "gpio18", "gpio19", "gpio20";
	function = "blsp_spi2";
	};

	blsp1_spi3_default: blsp1-spi3-default {
	pins = "gpio82", "gpio83", "gpio84", "gpio85";
	function = "blsp_spi3";
	};

	blsp1_spi4_default: blsp1-spi4-default {
	pins = "gpio37", "gpio38", "gpio117", "gpio118";
	function = "blsp_spi4";
	};

	blsp2_spi0_default: blsp2-spi0-default {
	pins = "gpio26", "gpio27", "gpio28", "gpio29";
	function = "blsp_spi5";
	};

	blsp2_uart0_default: blsp2-uart0-default {
	pins = "gpio26", "gpio27", "gpio28", "gpio29";
	function = "blsp_uart5";
	};
	};

	gcc: clock-controller@1800000 {
	compatible = "qcom,gcc-qcs404";
	reg = <0x01800000 0x80000>;
	#clock-cells = <1>;
	#reset-cells = <1>;

	assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
	assigned-clock-rates = <19200000>;
	};

	tcsr_mutex_regs: syscon@1905000 {
	compatible = "syscon";
	reg = <0x01905000 0x20000>;
	};

	tcsr: syscon@1937000 {
	compatible = "syscon";
	reg = <0x01937000 0x25000>;
	};

	spmi_bus: spmi@200f000 {
	compatible = "qcom,spmi-pmic-arb";
	reg = <0x0200f000 0x001000>,
	<0x02400000 0x800000>,
	<0x02c00000 0x800000>,
	<0x03800000 0x200000>,
	<0x0200a000 0x002100>;
	reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
	interrupt-names = "periph_irq";
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	qcom,ee = <0>;
	qcom,channel = <0>;
	#address-cells = <2>;
	#size-cells = <0>;
	interrupt-controller;
	#interrupt-cells = <4>;
	};

	remoteproc_wcss: remoteproc@7400000 {
	compatible = "qcom,qcs404-wcss-pas";
	reg = <0x07400000 0x4040>;

	interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
	<&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	<&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	<&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	<&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "wdog", "fatal", "ready",
	"handover", "stop-ack";

	clocks = <&xo_board>;
	clock-names = "xo";

	memory-region = <&wlan_fw_mem>;

	qcom,smem-states = <&wcss_smp2p_out 0>;
	qcom,smem-state-names = "stop";

	status = "disabled";

	glink-edge {
	interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;

	qcom,remote-pid = <1>;
	mboxes = <&apcs_glb 16>;

	label = "wcss";
	};
	};

	pcie_phy: phy@7786000 {
	compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
	reg = <0x07786000 0xb8>;

	clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
	resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
	<&gcc 21>;
	reset-names = "phy", "pipe";

	clock-output-names = "pcie_0_pipe_clk";
	#phy-cells = <0>;

	status = "disabled";
	};

	sdcc1: sdcc@7804000 {
	- compatible = "qcom,sdhci-msm-v5";
	+ compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
	reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
	- reg-names = "hc_mem", "cmdq_mem";
	+ reg-names = "hc", "cqhci";

	interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hc_irq", "pwr_irq";

	clocks = <&gcc GCC_SDCC1_APPS_CLK>,
	<&gcc GCC_SDCC1_AHB_CLK>,
	<&xo_board>;
	clock-names = "core", "iface", "xo";

	status = "disabled";
	};

	blsp1_dma: dma@7884000 {
	compatible = "qcom,bam-v1.7.0";
	reg = <0x07884000 0x25000>;
	interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	status = "okay";
	};

	blsp1_uart0: serial@78af000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x078af000 0x200>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp1_dma 1>, <&blsp1_dma 0>;
	dma-names = "rx", "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp1_uart0_default>;
	status = "disabled";
	};

	blsp1_uart1: serial@78b0000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x078b0000 0x200>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp1_dma 3>, <&blsp1_dma 2>;
	dma-names = "rx", "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp1_uart1_default>;
	status = "disabled";
	};

	blsp1_uart2: serial@78b1000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x078b1000 0x200>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp1_dma 5>, <&blsp1_dma 4>;
	dma-names = "rx", "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp1_uart2_default>;
	status = "okay";
	};

	ethernet: ethernet@7a80000 {
	compatible = "qcom,qcs404-ethqos";
	reg = <0x07a80000 0x10000>,
	<0x07a96000 0x100>;
	reg-names = "stmmaceth", "rgmii";
	clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
	clocks = <&gcc GCC_ETH_AXI_CLK>,
	<&gcc GCC_ETH_SLAVE_AHB_CLK>,
	<&gcc GCC_ETH_PTP_CLK>,
	<&gcc GCC_ETH_RGMII_CLK>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq", "eth_lpi";

	snps,tso;
	rx-fifo-depth = <4096>;
	tx-fifo-depth = <4096>;

	status = "disabled";
	};

	wifi: wifi@a000000 {
	compatible = "qcom,wcn3990-wifi";
	reg = <0xa000000 0x800000>;
	reg-names = "membase";
	memory-region = <&wlan_msa_mem>;
	interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	blsp1_uart3: serial@78b2000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x078b2000 0x200>;
	interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp1_dma 7>, <&blsp1_dma 6>;
	dma-names = "rx", "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp1_uart3_default>;
	status = "disabled";
	};

	blsp1_i2c0: i2c@78b5000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x078b5000 0x600>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp1_i2c0_default>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp1_spi0: spi@78b5000 {
	compatible = "qcom,spi-qup-v2.2.1";
	reg = <0x078b5000 0x600>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp1_spi0_default>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp1_i2c1: i2c@78b6000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x078b6000 0x600>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp1_i2c1_default>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp1_spi1: spi@78b6000 {
	compatible = "qcom,spi-qup-v2.2.1";
	reg = <0x078b6000 0x600>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp1_spi1_default>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp1_i2c2: i2c@78b7000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x078b7000 0x600>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp1_i2c2_default>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp1_spi2: spi@78b7000 {
	compatible = "qcom,spi-qup-v2.2.1";
	reg = <0x078b7000 0x600>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp1_spi2_default>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp1_i2c3: i2c@78b8000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x078b8000 0x600>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp1_i2c3_default>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp1_spi3: spi@78b8000 {
	compatible = "qcom,spi-qup-v2.2.1";
	reg = <0x078b8000 0x600>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp1_spi3_default>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp1_i2c4: i2c@78b9000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x078b9000 0x600>;
	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp1_i2c4_default>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp1_spi4: spi@78b9000 {
	compatible = "qcom,spi-qup-v2.2.1";
	reg = <0x078b9000 0x600>;
	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp1_spi4_default>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp2_dma: dma@7ac4000 {
	compatible = "qcom,bam-v1.7.0";
	reg = <0x07ac4000 0x17000>;
	interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP2_AHB_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	status = "disabled";
	};

	blsp2_uart0: serial@7aef000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x07aef000 0x200>;
	interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp2_dma 1>, <&blsp2_dma 0>;
	dma-names = "rx", "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp2_uart0_default>;
	status = "disabled";
	};

	blsp2_i2c0: i2c@7af5000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	reg = <0x07af5000 0x600>;
	interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP2_AHB_CLK>,
	<&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp2_i2c0_default>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	blsp2_spi0: spi@7af5000 {
	compatible = "qcom,spi-qup-v2.2.1";
	reg = <0x07af5000 0x600>;
	interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP2_AHB_CLK>,
	<&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>;
	clock-names = "iface", "core";
	pinctrl-names = "default";
	pinctrl-0 = <&blsp2_spi0_default>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	intc: interrupt-controller@b000000 {
	compatible = "qcom,msm-qgic2";
	interrupt-controller;
	#interrupt-cells = <3>;
	reg = <0x0b000000 0x1000>,
	<0x0b002000 0x1000>;
	};

	apcs_glb: mailbox@b011000 {
	compatible = "qcom,qcs404-apcs-apps-global", "syscon";
	reg = <0x0b011000 0x1000>;
	#mbox-cells = <1>;
	clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
	clock-names = "pll", "aux";
	#clock-cells = <0>;
	};

	apcs_hfpll: clock-controller@b016000 {
	compatible = "qcom,hfpll";
	reg = <0x0b016000 0x30>;
	#clock-cells = <0>;
	clock-output-names = "apcs_hfpll";
	clocks = <&xo_board>;
	clock-names = "xo";
	};

	watchdog@b017000 {
	compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
	reg = <0x0b017000 0x1000>;
	clocks = <&sleep_clk>;
	};

	cpr: power-controller@b018000 {
	compatible = "qcom,qcs404-cpr", "qcom,cpr";
	reg = <0x0b018000 0x1000>;
	interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
	clocks = <&xo_board>;
	clock-names = "ref";
	vdd-apc-supply = <&pms405_s3>;
	#power-domain-cells = <0>;
	operating-points-v2 = <&cpr_opp_table>;
	acc-syscon = <&tcsr>;

	nvmem-cells = <&cpr_efuse_quot_offset1>,
	<&cpr_efuse_quot_offset2>,
	<&cpr_efuse_quot_offset3>,
	<&cpr_efuse_init_voltage1>,
	<&cpr_efuse_init_voltage2>,
	<&cpr_efuse_init_voltage3>,
	<&cpr_efuse_quot1>,
	<&cpr_efuse_quot2>,
	<&cpr_efuse_quot3>,
	<&cpr_efuse_ring1>,
	<&cpr_efuse_ring2>,
	<&cpr_efuse_ring3>,
	<&cpr_efuse_revision>;
	nvmem-cell-names = "cpr_quotient_offset1",
	"cpr_quotient_offset2",
	"cpr_quotient_offset3",
	"cpr_init_voltage1",
	"cpr_init_voltage2",
	"cpr_init_voltage3",
	"cpr_quotient1",
	"cpr_quotient2",
	"cpr_quotient3",
	"cpr_ring_osc1",
	"cpr_ring_osc2",
	"cpr_ring_osc3",
	"cpr_fuse_revision";
	};

	timer@b120000 {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "arm,armv7-timer-mem";
	reg = <0x0b120000 0x1000>;
	clock-frequency = <19200000>;

	frame@b121000 {
	frame-number = <0>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x0b121000 0x1000>,
	<0x0b122000 0x1000>;
	};

	frame@b123000 {
	frame-number = <1>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x0b123000 0x1000>;
	status = "disabled";
	};

	frame@b124000 {
	frame-number = <2>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x0b124000 0x1000>;
	status = "disabled";
	};

	frame@b125000 {
	frame-number = <3>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x0b125000 0x1000>;
	status = "disabled";
	};

	frame@b126000 {
	frame-number = <4>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x0b126000 0x1000>;
	status = "disabled";
	};

	frame@b127000 {
	frame-number = <5>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb127000 0x1000>;
	status = "disabled";
	};

	frame@b128000 {
	frame-number = <6>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x0b128000 0x1000>;
	status = "disabled";
	};
	};

	remoteproc_adsp: remoteproc@c700000 {
	compatible = "qcom,qcs404-adsp-pas";
	reg = <0x0c700000 0x4040>;

	interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
	<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "wdog", "fatal", "ready",
	"handover", "stop-ack";

	clocks = <&xo_board>;
	clock-names = "xo";

	memory-region = <&adsp_fw_mem>;

	qcom,smem-states = <&adsp_smp2p_out 0>;
	qcom,smem-state-names = "stop";

	status = "disabled";

	glink-edge {
	interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;

	qcom,remote-pid = <2>;
	mboxes = <&apcs_glb 8>;

	label = "adsp";
	};
	};

	pcie: pci@10000000 {
	compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
	reg = <0x10000000 0xf1d>,
	<0x10000f20 0xa8>,
	<0x07780000 0x2000>,
	<0x10001000 0x2000>;
	reg-names = "dbi", "elbi", "parf", "config";
	device_type = "pci";
	linux,pci-domain = <0>;
	bus-range = <0x00 0xff>;
	num-lanes = <1>;
	#address-cells = <3>;
	#size-cells = <2>;

	ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */
	<0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */

	interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	<0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	<0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	<0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
	clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
	<&gcc GCC_PCIE_0_AUX_CLK>,
	<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
	<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
	clock-names = "iface", "aux", "master_bus", "slave_bus";

	resets = <&gcc 18>,
	<&gcc 17>,
	<&gcc 15>,
	<&gcc 19>,
	<&gcc GCC_PCIE_0_BCR>,
	<&gcc 16>;
	reset-names = "axi_m",
	"axi_s",
	"axi_m_sticky",
	"pipe_sticky",
	"pwr",
	"ahb";

	phys = <&pcie_phy>;
	phy-names = "pciephy";

	status = "disabled";
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 2 0xff08>,
	<GIC_PPI 3 0xff08>,
	<GIC_PPI 4 0xff08>,
	<GIC_PPI 1 0xff08>;
	};

	smp2p-adsp {
	compatible = "qcom,smp2p";
	qcom,smem = <443>, <429>;
	interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
	mboxes = <&apcs_glb 10>;
	qcom,local-pid = <0>;
	qcom,remote-pid = <2>;

	adsp_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};

	adsp_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	smp2p-cdsp {
	compatible = "qcom,smp2p";
	qcom,smem = <94>, <432>;
	interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
	mboxes = <&apcs_glb 14>;
	qcom,local-pid = <0>;
	qcom,remote-pid = <5>;

	cdsp_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};

	cdsp_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	smp2p-wcss {
	compatible = "qcom,smp2p";
	qcom,smem = <435>, <428>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
	mboxes = <&apcs_glb 18>;
	qcom,local-pid = <0>;
	qcom,remote-pid = <1>;

	wcss_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};

	wcss_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	thermal-zones {
	aoss-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 0>;

	trips {
	aoss_alert0: trip-point0 {
	temperature = <105000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	q6-hvx-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 1>;

	trips {
	q6_hvx_alert0: trip-point0 {
	temperature = <105000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	lpass-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 2>;

	trips {
	lpass_alert0: trip-point0 {
	temperature = <105000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	wlan-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 3>;

	trips {
	wlan_alert0: trip-point0 {
	temperature = <105000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	cluster-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 4>;

	trips {
	cluster_alert0: trip-point0 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "hot";
	};
	cluster_alert1: trip-point1 {
	temperature = <105000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cluster_crit: cluster_crit {
	temperature = <120000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	cooling-maps {
	map0 {
	trip = <&cluster_alert1>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu0-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 5>;

	trips {
	cpu0_alert0: trip-point0 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "hot";
	};
	cpu0_alert1: trip-point1 {
	temperature = <105000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu0_crit: cpu_crit {
	temperature = <120000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	cooling-maps {
	map0 {
	trip = <&cpu0_alert1>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu1-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 6>;

	trips {
	cpu1_alert0: trip-point0 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "hot";
	};
	cpu1_alert1: trip-point1 {
	temperature = <105000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu1_crit: cpu_crit {
	temperature = <120000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	cooling-maps {
	map0 {
	trip = <&cpu1_alert1>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu2-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 7>;

	trips {
	cpu2_alert0: trip-point0 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "hot";
	};
	cpu2_alert1: trip-point1 {
	temperature = <105000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu2_crit: cpu_crit {
	temperature = <120000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	cooling-maps {
	map0 {
	trip = <&cpu2_alert1>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu3-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 8>;

	trips {
	cpu3_alert0: trip-point0 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "hot";
	};
	cpu3_alert1: trip-point1 {
	temperature = <105000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu3_crit: cpu_crit {
	temperature = <120000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	cooling-maps {
	map0 {
	trip = <&cpu3_alert1>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	gpu-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens 9>;

	trips {
	gpu_alert0: trip-point0 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/qcom/sc7180-idp.dts b/sys/gnu/dts/arm64/qcom/sc7180-idp.dts
	index 388f50ad4fde..043c9b9b5024 100644
	--- a/sys/gnu/dts/arm64/qcom/sc7180-idp.dts
	+++ b/sys/gnu/dts/arm64/qcom/sc7180-idp.dts
	@@ -1,430 +1,470 @@
	// SPDX-License-Identifier: BSD-3-Clause
	/*
	* SC7180 IDP board device tree source
	*
	* Copyright (c) 2019, The Linux Foundation. All rights reserved.
	*/

	/dts-v1/;

	+#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
	#include "sc7180.dtsi"
	#include "pm6150.dtsi"
	#include "pm6150l.dtsi"

	/ {
	model = "Qualcomm Technologies, Inc. SC7180 IDP";
	compatible = "qcom,sc7180-idp", "qcom,sc7180";

	aliases {
	+ bluetooth0 = &bluetooth;
	hsuart0 = &uart3;
	serial0 = &uart8;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};
	};

	&apps_rsc {
	pm6150-rpmh-regulators {
	compatible = "qcom,pm6150-rpmh-regulators";
	qcom,pmic-id = "a";

	vreg_s1a_1p1: smps1 {
	regulator-min-microvolt = <1128000>;
	regulator-max-microvolt = <1128000>;
	};

	vreg_s4a_1p0: smps4 {
	regulator-min-microvolt = <824000>;
	regulator-max-microvolt = <1120000>;
	};

	vreg_s5a_2p0: smps5 {
	regulator-min-microvolt = <1744000>;
	regulator-max-microvolt = <2040000>;
	};

	vreg_l1a_1p2: ldo1 {
	regulator-min-microvolt = <1178000>;
	regulator-max-microvolt = <1256000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l2a_1p0: ldo2 {
	regulator-min-microvolt = <944000>;
	regulator-max-microvolt = <1056000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l3a_1p0: ldo3 {
	regulator-min-microvolt = <968000>;
	regulator-max-microvolt = <1064000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l4a_0p8: ldo4 {
	regulator-min-microvolt = <824000>;
	regulator-max-microvolt = <928000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l5a_2p7: ldo5 {
	regulator-min-microvolt = <2496000>;
	regulator-max-microvolt = <3000000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l6a_0p6: ldo6 {
	regulator-min-microvolt = <568000>;
	regulator-max-microvolt = <648000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l9a_0p6: ldo9 {
	regulator-min-microvolt = <488000>;
	regulator-max-microvolt = <800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l10a_1p8: ldo10 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1832000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l11a_1p8: ldo11 {
	regulator-min-microvolt = <1696000>;
	regulator-max-microvolt = <1904000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l12a_1p8: ldo12 {
	- regulator-min-microvolt = <1696000>;
	- regulator-max-microvolt = <1952000>;
	- regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l13a_1p8: ldo13 {
	regulator-min-microvolt = <1696000>;
	regulator-max-microvolt = <1904000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l14a_1p8: ldo14 {
	regulator-min-microvolt = <1728000>;
	regulator-max-microvolt = <1832000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l15a_1p8: ldo15 {
	regulator-min-microvolt = <1696000>;
	regulator-max-microvolt = <1904000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l16a_2p7: ldo16 {
	regulator-min-microvolt = <2496000>;
	regulator-max-microvolt = <3304000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l17a_3p0: ldo17 {
	regulator-min-microvolt = <2920000>;
	regulator-max-microvolt = <3232000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l18a_2p8: ldo18 {
	regulator-min-microvolt = <2496000>;
	regulator-max-microvolt = <3304000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l19a_2p9: ldo19 {
	- regulator-min-microvolt = <2696000>;
	- regulator-max-microvolt = <3304000>;
	- regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	+ regulator-min-microvolt = <2960000>;
	+ regulator-max-microvolt = <2960000>;
	+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};
	};

	pm6150l-rpmh-regulators {
	compatible = "qcom,pm6150l-rpmh-regulators";
	qcom,pmic-id = "c";

	vreg_s8c_1p3: smps8 {
	regulator-min-microvolt = <1120000>;
	regulator-max-microvolt = <1408000>;
	};

	vreg_l1c_1p8: ldo1 {
	regulator-min-microvolt = <1616000>;
	regulator-max-microvolt = <1984000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l2c_1p3: ldo2 {
	regulator-min-microvolt = <1168000>;
	regulator-max-microvolt = <1304000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l3c_1p2: ldo3 {
	regulator-min-microvolt = <1144000>;
	regulator-max-microvolt = <1304000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l4c_1p8: ldo4 {
	regulator-min-microvolt = <1648000>;
	regulator-max-microvolt = <3304000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l5c_1p8: ldo5 {
	regulator-min-microvolt = <1648000>;
	regulator-max-microvolt = <3304000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l6c_2p9: ldo6 {
	- regulator-min-microvolt = <2696000>;
	- regulator-max-microvolt = <3304000>;
	- regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <2950000>;
	+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l7c_3p0: ldo7 {
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3312000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l8c_1p8: ldo8 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1904000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l9c_2p9: ldo9 {
	- regulator-min-microvolt = <2952000>;
	- regulator-max-microvolt = <3304000>;
	- regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	+ regulator-min-microvolt = <2960000>;
	+ regulator-max-microvolt = <2960000>;
	+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l10c_3p3: ldo10 {
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3400000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_l11c_3p3: ldo11 {
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3400000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
	};

	vreg_bob: bob {
	regulator-min-microvolt = <3008000>;
	regulator-max-microvolt = <3960000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
	};
	};
	};

	&qspi {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>;

	flash@0 {
	compatible = "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <25000000>;
	spi-tx-bus-width = <2>;
	spi-rx-bus-width = <2>;
	};
	};

	&qupv3_id_0 {
	status = "okay";
	};

	&qupv3_id_1 {
	status = "okay";
	};

	+&sdhc_1 {
	+ status = "okay";
	+
	+ pinctrl-names = "default", "sleep";
	+ pinctrl-0 = <&sdc1_on>;
	+ pinctrl-1 = <&sdc1_off>;
	+ vmmc-supply = <&vreg_l19a_2p9>;
	+ vqmmc-supply = <&vreg_l12a_1p8>;
	+};
	+
	+&sdhc_2 {
	+ status = "okay";
	+
	+ pinctrl-names = "default","sleep";
	+ pinctrl-0 = <&sdc2_on>;
	+ pinctrl-1 = <&sdc2_off>;
	+ vmmc-supply = <&vreg_l9c_2p9>;
	+ vqmmc-supply = <&vreg_l6c_2p9>;
	+
	+ cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>;
	+};
	+
	&uart3 {
	status = "okay";
	+
	+ bluetooth: wcn3990-bt {
	+ compatible = "qcom,wcn3990-bt";
	+ vddio-supply = <&vreg_l10a_1p8>;
	+ vddxo-supply = <&vreg_l1c_1p8>;
	+ vddrf-supply = <&vreg_l2c_1p3>;
	+ vddch0-supply = <&vreg_l10c_3p3>;
	+ max-speed = <3200000>;
	+ clocks = <&rpmhcc RPMH_RF_CLK2>;
	+ };
	};

	&uart8 {
	status = "okay";
	};

	&usb_1 {
	status = "okay";
	};

	&usb_1_dwc3 {
	dr_mode = "host";
	};

	&usb_1_hsphy {
	status = "okay";
	vdd-supply = <&vreg_l4a_0p8>;
	vdda-pll-supply = <&vreg_l11a_1p8>;
	vdda-phy-dpdm-supply = <&vreg_l17a_3p0>;
	qcom,imp-res-offset-value = <8>;
	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
	qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
	qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
	};

	&usb_1_qmpphy {
	status = "okay";
	vdda-phy-supply = <&vreg_l3c_1p2>;
	vdda-pll-supply = <&vreg_l4a_0p8>;
	};

	+&venus {
	+ video-firmware {
	+ iommus = <&apps_smmu 0x0c42 0x0>;
	+ };
	+};
	+
	/* PINCTRL - additions to nodes defined in sc7180.dtsi */

	&qspi_clk {
	pinconf {
	pins = "gpio63";
	bias-disable;
	};
	};

	&qspi_cs0 {
	pinconf {
	pins = "gpio68";
	bias-disable;
	};
	};

	&qspi_data01 {
	pinconf {
	pins = "gpio64", "gpio65";

	/* High-Z when no transfers; nice to park the lines */
	bias-pull-up;
	};
	};

	&qup_i2c2_default {
	pinconf {
	pins = "gpio15", "gpio16";
	drive-strength = <2>;

	/* Has external pullup */
	bias-disable;
	};
	};

	&qup_i2c4_default {
	pinconf {
	pins = "gpio115", "gpio116";
	drive-strength = <2>;

	/* Has external pullup */
	bias-disable;
	};
	};

	&qup_i2c7_default {
	pinconf {
	pins = "gpio6", "gpio7";
	drive-strength = <2>;

	/* Has external pullup */
	bias-disable;
	};
	};

	&qup_i2c9_default {
	pinconf {
	pins = "gpio46", "gpio47";
	drive-strength = <2>;

	/* Has external pullup */
	bias-disable;
	};
	};

	&qup_uart3_default {
	pinconf-cts {
	/*
	* Configure a pull-down on 38 (CTS) to match the pull of
	* the Bluetooth module.
	*/
	pins = "gpio38";
	bias-pull-down;
	output-high;
	};

	pinconf-rts {
	/* We'll drive 39 (RTS), so no pull */
	pins = "gpio39";
	drive-strength = <2>;
	bias-disable;
	};

	pinconf-tx {
	/* We'll drive 40 (TX), so no pull */
	pins = "gpio40";
	drive-strength = <2>;
	bias-disable;
	output-high;
	};

	pinconf-rx {
	/*
	* Configure a pull-up on 41 (RX). This is needed to avoid
	* garbage data when the TX pin of the Bluetooth module is
	* in tri-state (module powered off or not driving the
	* signal yet).
	*/
	pins = "gpio41";
	bias-pull-up;
	};
	};

	&qup_uart8_default {
	pinconf-tx {
	pins = "gpio44";
	drive-strength = <2>;
	bias-disable;
	};

	pinconf-rx {
	pins = "gpio45";
	drive-strength = <2>;
	bias-pull-up;
	};
	};

	&qup_spi0_default {
	pinconf {
	pins = "gpio34", "gpio35", "gpio36", "gpio37";
	drive-strength = <2>;
	bias-disable;
	};
	};

	&qup_spi6_default {
	pinconf {
	pins = "gpio59", "gpio60", "gpio61", "gpio62";
	drive-strength = <2>;
	bias-disable;
	};
	};

	&qup_spi10_default {
	pinconf {
	pins = "gpio86", "gpio87", "gpio88", "gpio89";
	drive-strength = <2>;
	bias-disable;
	};
	};

	diff --git a/sys/gnu/dts/arm64/qcom/sc7180.dtsi b/sys/gnu/dts/arm64/qcom/sc7180.dtsi
	index 8011c5fe2a31..998f101ad623 100644
	--- a/sys/gnu/dts/arm64/qcom/sc7180.dtsi
	+++ b/sys/gnu/dts/arm64/qcom/sc7180.dtsi
	@@ -1,2187 +1,2782 @@
	// SPDX-License-Identifier: BSD-3-Clause
	/*
	* SC7180 SoC device tree source
	*
	* Copyright (c) 2019, The Linux Foundation. All rights reserved.
	*/

	+#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
	#include <dt-bindings/clock/qcom,gcc-sc7180.h>
	+#include <dt-bindings/clock/qcom,gpucc-sc7180.h>
	#include <dt-bindings/clock/qcom,rpmh.h>
	+#include <dt-bindings/clock/qcom,videocc-sc7180.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/phy/phy-qcom-qusb2.h>
	#include <dt-bindings/power/qcom-aoss-qmp.h>
	#include <dt-bindings/power/qcom-rpmpd.h>
	#include <dt-bindings/reset/qcom,sdm845-aoss.h>
	#include <dt-bindings/reset/qcom,sdm845-pdc.h>
	#include <dt-bindings/soc/qcom,rpmh-rsc.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	i2c6 = &i2c6;
	i2c7 = &i2c7;
	i2c8 = &i2c8;
	i2c9 = &i2c9;
	i2c10 = &i2c10;
	i2c11 = &i2c11;
	spi0 = &spi0;
	spi1 = &spi1;
	spi3 = &spi3;
	spi5 = &spi5;
	spi6 = &spi6;
	spi8 = &spi8;
	spi10 = &spi10;
	spi11 = &spi11;
	};

	clocks {
	xo_board: xo-board {
	compatible = "fixed-clock";
	clock-frequency = <38400000>;
	#clock-cells = <0>;
	};

	sleep_clk: sleep-clk {
	compatible = "fixed-clock";
	clock-frequency = <32764>;
	#clock-cells = <0>;
	};
	};

	reserved_memory: reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	aop_cmd_db_mem: memory@80820000 {
	reg = <0x0 0x80820000 0x0 0x20000>;
	compatible = "qcom,cmd-db";
	};

	smem_mem: memory@80900000 {
	reg = <0x0 0x80900000 0x0 0x200000>;
	no-map;
	};
	+
	+ venus_mem: memory@8f600000 {
	+ reg = <0 0x8f600000 0 0x500000>;
	+ no-map;
	+ };
	};

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	CPU0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x0>;
	enable-method = "psci";
	+ capacity-dmips-mhz = <1024>;
	+ dynamic-power-coefficient = <100>;
	next-level-cache = <&L2_0>;
	#cooling-cells = <2>;
	qcom,freq-domain = <&cpufreq_hw 0>;
	L2_0: l2-cache {
	compatible = "cache";
	next-level-cache = <&L3_0>;
	L3_0: l3-cache {
	compatible = "cache";
	};
	};
	};

	CPU1: cpu@100 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x100>;
	enable-method = "psci";
	+ capacity-dmips-mhz = <1024>;
	+ dynamic-power-coefficient = <100>;
	next-level-cache = <&L2_100>;
	#cooling-cells = <2>;
	qcom,freq-domain = <&cpufreq_hw 0>;
	L2_100: l2-cache {
	compatible = "cache";
	next-level-cache = <&L3_0>;
	};
	};

	CPU2: cpu@200 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x200>;
	enable-method = "psci";
	+ capacity-dmips-mhz = <1024>;
	+ dynamic-power-coefficient = <100>;
	next-level-cache = <&L2_200>;
	#cooling-cells = <2>;
	qcom,freq-domain = <&cpufreq_hw 0>;
	L2_200: l2-cache {
	compatible = "cache";
	next-level-cache = <&L3_0>;
	};
	};

	CPU3: cpu@300 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x300>;
	enable-method = "psci";
	+ capacity-dmips-mhz = <1024>;
	+ dynamic-power-coefficient = <100>;
	next-level-cache = <&L2_300>;
	#cooling-cells = <2>;
	qcom,freq-domain = <&cpufreq_hw 0>;
	L2_300: l2-cache {
	compatible = "cache";
	next-level-cache = <&L3_0>;
	};
	};

	CPU4: cpu@400 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x400>;
	enable-method = "psci";
	+ capacity-dmips-mhz = <1024>;
	+ dynamic-power-coefficient = <100>;
	next-level-cache = <&L2_400>;
	#cooling-cells = <2>;
	qcom,freq-domain = <&cpufreq_hw 0>;
	L2_400: l2-cache {
	compatible = "cache";
	next-level-cache = <&L3_0>;
	};
	};

	CPU5: cpu@500 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x500>;
	enable-method = "psci";
	+ capacity-dmips-mhz = <1024>;
	+ dynamic-power-coefficient = <100>;
	next-level-cache = <&L2_500>;
	#cooling-cells = <2>;
	qcom,freq-domain = <&cpufreq_hw 0>;
	L2_500: l2-cache {
	compatible = "cache";
	next-level-cache = <&L3_0>;
	};
	};

	CPU6: cpu@600 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x600>;
	enable-method = "psci";
	+ capacity-dmips-mhz = <1740>;
	+ dynamic-power-coefficient = <405>;
	next-level-cache = <&L2_600>;
	#cooling-cells = <2>;
	qcom,freq-domain = <&cpufreq_hw 1>;
	L2_600: l2-cache {
	compatible = "cache";
	next-level-cache = <&L3_0>;
	};
	};

	CPU7: cpu@700 {
	device_type = "cpu";
	compatible = "arm,armv8";
	reg = <0x0 0x700>;
	enable-method = "psci";
	+ capacity-dmips-mhz = <1740>;
	+ dynamic-power-coefficient = <405>;
	next-level-cache = <&L2_700>;
	#cooling-cells = <2>;
	qcom,freq-domain = <&cpufreq_hw 1>;
	L2_700: l2-cache {
	compatible = "cache";
	next-level-cache = <&L3_0>;
	};
	};
	+
	+ cpu-map {
	+ cluster0 {
	+ core0 {
	+ cpu = <&CPU0>;
	+ };
	+
	+ core1 {
	+ cpu = <&CPU1>;
	+ };
	+
	+ core2 {
	+ cpu = <&CPU2>;
	+ };
	+
	+ core3 {
	+ cpu = <&CPU3>;
	+ };
	+
	+ core4 {
	+ cpu = <&CPU4>;
	+ };
	+
	+ core5 {
	+ cpu = <&CPU5>;
	+ };
	+
	+ core6 {
	+ cpu = <&CPU6>;
	+ };
	+
	+ core7 {
	+ cpu = <&CPU7>;
	+ };
	+ };
	+ };
	};

	memory@80000000 {
	device_type = "memory";
	/* We expect the bootloader to fill in the size */
	reg = <0 0x80000000 0 0>;
	};

	pmu {
	compatible = "arm,armv8-pmuv3";
	interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
	};

	firmware {
	scm {
	compatible = "qcom,scm-sc7180", "qcom,scm";
	};
	};

	tcsr_mutex: hwlock {
	compatible = "qcom,tcsr-mutex";
	syscon = <&tcsr_mutex_regs 0 0x1000>;
	#hwlock-cells = <1>;
	};

	smem {
	compatible = "qcom,smem";
	memory-region = <&smem_mem>;
	hwlocks = <&tcsr_mutex 3>;
	};

	smp2p-cdsp {
	compatible = "qcom,smp2p";
	qcom,smem = <94>, <432>;

	interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;

	mboxes = <&apss_shared 6>;

	qcom,local-pid = <0>;
	qcom,remote-pid = <5>;

	cdsp_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};

	cdsp_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";

	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	smp2p-lpass {
	compatible = "qcom,smp2p";
	qcom,smem = <443>, <429>;

	interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;

	mboxes = <&apss_shared 10>;

	qcom,local-pid = <0>;
	qcom,remote-pid = <2>;

	adsp_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};

	adsp_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";

	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	smp2p-mpss {
	compatible = "qcom,smp2p";
	qcom,smem = <435>, <428>;
	interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
	mboxes = <&apss_shared 14>;
	qcom,local-pid = <0>;
	qcom,remote-pid = <1>;

	modem_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};

	modem_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	- soc: soc {
	+ soc: soc@0 {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0 0 0 0 0x10 0>;
	dma-ranges = <0 0 0 0 0x10 0>;
	compatible = "simple-bus";

	gcc: clock-controller@100000 {
	compatible = "qcom,gcc-sc7180";
	reg = <0 0x00100000 0 0x1f0000>;
	clocks = <&rpmhcc RPMH_CXO_CLK>,
	- <&rpmhcc RPMH_CXO_CLK_A>;
	- clock-names = "bi_tcxo", "bi_tcxo_ao";
	+ <&rpmhcc RPMH_CXO_CLK_A>,
	+ <&sleep_clk>;
	+ clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;
	};

	qfprom@784000 {
	compatible = "qcom,qfprom";
	reg = <0 0x00784000 0 0x8ff>;
	#address-cells = <1>;
	#size-cells = <1>;

	qusb2p_hstx_trim: hstx-trim-primary@25b {
	reg = <0x25b 0x1>;
	bits = <1 3>;
	};
	};

	+ sdhc_1: sdhci@7c4000 {
	+ compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
	+ reg = <0 0x7c4000 0 0x1000>,
	+ <0 0x07c5000 0 0x1000>;
	+ reg-names = "hc", "cqhci";
	+
	+ iommus = <&apps_smmu 0x60 0x0>;
	+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
	+ interrupt-names = "hc_irq", "pwr_irq";
	+
	+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
	+ <&gcc GCC_SDCC1_AHB_CLK>;
	+ clock-names = "core", "iface";
	+
	+ bus-width = <8>;
	+ non-removable;
	+ supports-cqe;
	+
	+ mmc-ddr-1_8v;
	+ mmc-hs200-1_8v;
	+ mmc-hs400-1_8v;
	+ mmc-hs400-enhanced-strobe;
	+
	+ status = "disabled";
	+ };
	+
	qupv3_id_0: geniqup@8c0000 {
	compatible = "qcom,geni-se-qup";
	reg = <0 0x008c0000 0 0x6000>;
	clock-names = "m-ahb", "s-ahb";
	clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
	<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	+ iommus = <&apps_smmu 0x43 0x0>;
	status = "disabled";

	i2c0: i2c@880000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00880000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c0_default>;
	interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi0: spi@880000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00880000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi0_default>;
	interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart0: serial@880000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00880000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart0_default>;
	interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c1: i2c@884000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00884000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c1_default>;
	interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi1: spi@884000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00884000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi1_default>;
	interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart1: serial@884000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00884000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart1_default>;
	interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c2: i2c@888000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00888000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c2_default>;
	interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart2: serial@888000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00888000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart2_default>;
	interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c3: i2c@88c000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x0088c000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c3_default>;
	interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi3: spi@88c000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x0088c000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi3_default>;
	interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart3: serial@88c000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x0088c000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart3_default>;
	interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c4: i2c@890000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00890000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c4_default>;
	interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart4: serial@890000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00890000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart4_default>;
	interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c5: i2c@894000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00894000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c5_default>;
	interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi5: spi@894000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00894000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi5_default>;
	interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart5: serial@894000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00894000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart5_default>;
	interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	qupv3_id_1: geniqup@ac0000 {
	compatible = "qcom,geni-se-qup";
	reg = <0 0x00ac0000 0 0x6000>;
	clock-names = "m-ahb", "s-ahb";
	clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
	<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	+ iommus = <&apps_smmu 0x4c3 0x0>;
	status = "disabled";

	i2c6: i2c@a80000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00a80000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c6_default>;
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi6: spi@a80000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00a80000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi6_default>;
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart6: serial@a80000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00a80000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart6_default>;
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c7: i2c@a84000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00a84000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c7_default>;
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart7: serial@a84000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00a84000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart7_default>;
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c8: i2c@a88000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00a88000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c8_default>;
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi8: spi@a88000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00a88000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi8_default>;
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart8: serial@a88000 {
	compatible = "qcom,geni-debug-uart";
	reg = <0 0x00a88000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart8_default>;
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c9: i2c@a8c000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00a8c000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c9_default>;
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart9: serial@a8c000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00a8c000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart9_default>;
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c10: i2c@a90000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00a90000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c10_default>;
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi10: spi@a90000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00a90000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi10_default>;
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart10: serial@a90000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00a90000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart10_default>;
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c11: i2c@a94000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00a94000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c11_default>;
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi11: spi@a94000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00a94000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi11_default>;
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart11: serial@a94000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00a94000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart11_default>;
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	+ config_noc: interconnect@1500000 {
	+ compatible = "qcom,sc7180-config-noc";
	+ reg = <0 0x01500000 0 0x28000>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	+ system_noc: interconnect@1620000 {
	+ compatible = "qcom,sc7180-system-noc";
	+ reg = <0 0x01620000 0 0x17080>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	+ mc_virt: interconnect@1638000 {
	+ compatible = "qcom,sc7180-mc-virt";
	+ reg = <0 0x01638000 0 0x1000>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	+ qup_virt: interconnect@1650000 {
	+ compatible = "qcom,sc7180-qup-virt";
	+ reg = <0 0x01650000 0 0x1000>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	+ aggre1_noc: interconnect@16e0000 {
	+ compatible = "qcom,sc7180-aggre1-noc";
	+ reg = <0 0x016e0000 0 0x15080>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	+ aggre2_noc: interconnect@1705000 {
	+ compatible = "qcom,sc7180-aggre2-noc";
	+ reg = <0 0x01705000 0 0x9000>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	+ compute_noc: interconnect@170e000 {
	+ compatible = "qcom,sc7180-compute-noc";
	+ reg = <0 0x0170e000 0 0x6000>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	+ mmss_noc: interconnect@1740000 {
	+ compatible = "qcom,sc7180-mmss-noc";
	+ reg = <0 0x01740000 0 0x1c100>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	+ ipa_virt: interconnect@1e00000 {
	+ compatible = "qcom,sc7180-ipa-virt";
	+ reg = <0 0x01e00000 0 0x1000>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	tcsr_mutex_regs: syscon@1f40000 {
	compatible = "syscon";
	reg = <0 0x01f40000 0 0x40000>;
	};

	tlmm: pinctrl@3500000 {
	compatible = "qcom,sc7180-pinctrl";
	reg = <0 0x03500000 0 0x300000>,
	<0 0x03900000 0 0x300000>,
	<0 0x03d00000 0 0x300000>;
	reg-names = "west", "north", "south";
	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&tlmm 0 0 120>;
	wakeup-parent = <&pdc>;

	qspi_clk: qspi-clk {
	pinmux {
	pins = "gpio63";
	function = "qspi_clk";
	};
	};

	qspi_cs0: qspi-cs0 {
	pinmux {
	pins = "gpio68";
	function = "qspi_cs";
	};
	};

	qspi_cs1: qspi-cs1 {
	pinmux {
	pins = "gpio72";
	function = "qspi_cs";
	};
	};

	qspi_data01: qspi-data01 {
	pinmux-data {
	pins = "gpio64", "gpio65";
	function = "qspi_data";
	};
	};

	qspi_data12: qspi-data12 {
	pinmux-data {
	pins = "gpio66", "gpio67";
	function = "qspi_data";
	};
	};

	qup_i2c0_default: qup-i2c0-default {
	pinmux {
	pins = "gpio34", "gpio35";
	function = "qup00";
	};
	};

	qup_i2c1_default: qup-i2c1-default {
	pinmux {
	pins = "gpio0", "gpio1";
	function = "qup01";
	};
	};

	qup_i2c2_default: qup-i2c2-default {
	pinmux {
	pins = "gpio15", "gpio16";
	function = "qup02_i2c";
	};
	};

	qup_i2c3_default: qup-i2c3-default {
	pinmux {
	pins = "gpio38", "gpio39";
	function = "qup03";
	};
	};

	qup_i2c4_default: qup-i2c4-default {
	pinmux {
	pins = "gpio115", "gpio116";
	function = "qup04_i2c";
	};
	};

	qup_i2c5_default: qup-i2c5-default {
	pinmux {
	pins = "gpio25", "gpio26";
	function = "qup05";
	};
	};

	qup_i2c6_default: qup-i2c6-default {
	pinmux {
	pins = "gpio59", "gpio60";
	function = "qup10";
	};
	};

	qup_i2c7_default: qup-i2c7-default {
	pinmux {
	pins = "gpio6", "gpio7";
	function = "qup11_i2c";
	};
	};

	qup_i2c8_default: qup-i2c8-default {
	pinmux {
	pins = "gpio42", "gpio43";
	function = "qup12";
	};
	};

	qup_i2c9_default: qup-i2c9-default {
	pinmux {
	pins = "gpio46", "gpio47";
	function = "qup13_i2c";
	};
	};

	qup_i2c10_default: qup-i2c10-default {
	pinmux {
	pins = "gpio86", "gpio87";
	function = "qup14";
	};
	};

	qup_i2c11_default: qup-i2c11-default {
	pinmux {
	pins = "gpio53", "gpio54";
	function = "qup15";
	};
	};

	qup_spi0_default: qup-spi0-default {
	pinmux {
	pins = "gpio34", "gpio35",
	"gpio36", "gpio37";
	function = "qup00";
	};
	};

	qup_spi1_default: qup-spi1-default {
	pinmux {
	pins = "gpio0", "gpio1",
	"gpio2", "gpio3";
	function = "qup01";
	};
	};

	qup_spi3_default: qup-spi3-default {
	pinmux {
	pins = "gpio38", "gpio39",
	"gpio40", "gpio41";
	function = "qup03";
	};
	};

	qup_spi5_default: qup-spi5-default {
	pinmux {
	pins = "gpio25", "gpio26",
	"gpio27", "gpio28";
	function = "qup05";
	};
	};

	qup_spi6_default: qup-spi6-default {
	pinmux {
	pins = "gpio59", "gpio60",
	"gpio61", "gpio62";
	function = "qup10";
	};
	};

	qup_spi8_default: qup-spi8-default {
	pinmux {
	pins = "gpio42", "gpio43",
	"gpio44", "gpio45";
	function = "qup12";
	};
	};

	qup_spi10_default: qup-spi10-default {
	pinmux {
	pins = "gpio86", "gpio87",
	"gpio88", "gpio89";
	function = "qup14";
	};
	};

	qup_spi11_default: qup-spi11-default {
	pinmux {
	pins = "gpio53", "gpio54",
	"gpio55", "gpio56";
	function = "qup15";
	};
	};

	qup_uart0_default: qup-uart0-default {
	pinmux {
	pins = "gpio34", "gpio35",
	"gpio36", "gpio37";
	function = "qup00";
	};
	};

	qup_uart1_default: qup-uart1-default {
	pinmux {
	pins = "gpio0", "gpio1",
	"gpio2", "gpio3";
	function = "qup01";
	};
	};

	qup_uart2_default: qup-uart2-default {
	pinmux {
	pins = "gpio15", "gpio16";
	function = "qup02_uart";
	};
	};

	qup_uart3_default: qup-uart3-default {
	pinmux {
	pins = "gpio38", "gpio39",
	"gpio40", "gpio41";
	function = "qup03";
	};
	};

	qup_uart4_default: qup-uart4-default {
	pinmux {
	pins = "gpio115", "gpio116";
	function = "qup04_uart";
	};
	};

	qup_uart5_default: qup-uart5-default {
	pinmux {
	pins = "gpio25", "gpio26",
	"gpio27", "gpio28";
	function = "qup05";
	};
	};

	qup_uart6_default: qup-uart6-default {
	pinmux {
	pins = "gpio59", "gpio60",
	"gpio61", "gpio62";
	function = "qup10";
	};
	};

	qup_uart7_default: qup-uart7-default {
	pinmux {
	pins = "gpio6", "gpio7";
	function = "qup11_uart";
	};
	};

	qup_uart8_default: qup-uart8-default {
	pinmux {
	pins = "gpio44", "gpio45";
	function = "qup12";
	};
	};

	qup_uart9_default: qup-uart9-default {
	pinmux {
	pins = "gpio46", "gpio47";
	function = "qup13_uart";
	};
	};

	qup_uart10_default: qup-uart10-default {
	pinmux {
	pins = "gpio86", "gpio87",
	"gpio88", "gpio89";
	function = "qup14";
	};
	};

	qup_uart11_default: qup-uart11-default {
	pinmux {
	pins = "gpio53", "gpio54",
	"gpio55", "gpio56";
	function = "qup15";
	};
	};
	+
	+ sdc1_on: sdc1-on {
	+ pinconf-clk {
	+ pins = "sdc1_clk";
	+ bias-disable;
	+ drive-strength = <16>;
	+ };
	+
	+ pinconf-cmd {
	+ pins = "sdc1_cmd";
	+ bias-pull-up;
	+ drive-strength = <10>;
	+ };
	+
	+ pinconf-data {
	+ pins = "sdc1_data";
	+ bias-pull-up;
	+ drive-strength = <10>;
	+ };
	+
	+ pinconf-rclk {
	+ pins = "sdc1_rclk";
	+ bias-pull-down;
	+ };
	+ };
	+
	+ sdc1_off: sdc1-off {
	+ pinconf-clk {
	+ pins = "sdc1_clk";
	+ bias-disable;
	+ drive-strength = <2>;
	+ };
	+
	+ pinconf-cmd {
	+ pins = "sdc1_cmd";
	+ bias-pull-up;
	+ drive-strength = <2>;
	+ };
	+
	+ pinconf-data {
	+ pins = "sdc1_data";
	+ bias-pull-up;
	+ drive-strength = <2>;
	+ };
	+
	+ pinconf-rclk {
	+ pins = "sdc1_rclk";
	+ bias-pull-down;
	+ };
	+ };
	+
	+ sdc2_on: sdc2-on {
	+ pinconf-clk {
	+ pins = "sdc2_clk";
	+ bias-disable;
	+ drive-strength = <16>;
	+ };
	+
	+ pinconf-cmd {
	+ pins = "sdc2_cmd";
	+ bias-pull-up;
	+ drive-strength = <10>;
	+ };
	+
	+ pinconf-data {
	+ pins = "sdc2_data";
	+ bias-pull-up;
	+ drive-strength = <10>;
	+ };
	+
	+ pinconf-sd-cd {
	+ pins = "gpio69";
	+ bias-pull-up;
	+ drive-strength = <2>;
	+ };
	+ };
	+
	+ sdc2_off: sdc2-off {
	+ pinconf-clk {
	+ pins = "sdc2_clk";
	+ bias-disable;
	+ drive-strength = <2>;
	+ };
	+
	+ pinconf-cmd {
	+ pins = "sdc2_cmd";
	+ bias-pull-up;
	+ drive-strength = <2>;
	+ };
	+
	+ pinconf-data {
	+ pins = "sdc2_data";
	+ bias-pull-up;
	+ drive-strength = <2>;
	+ };
	+
	+ pinconf-sd-cd {
	+ pins = "gpio69";
	+ bias-disable;
	+ drive-strength = <2>;
	+ };
	+ };
	+ };
	+
	+ sdhc_2: sdhci@8804000 {
	+ compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
	+ reg = <0 0x08804000 0 0x1000>;
	+
	+ iommus = <&apps_smmu 0x80 0>;
	+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
	+ interrupt-names = "hc_irq", "pwr_irq";
	+
	+ clocks = <&gcc GCC_SDCC2_APPS_CLK>,
	+ <&gcc GCC_SDCC2_AHB_CLK>;
	+ clock-names = "core", "iface";
	+
	+ bus-width = <4>;
	+
	+ status = "disabled";
	+ };
	+
	+ gpucc: clock-controller@5090000 {
	+ compatible = "qcom,sc7180-gpucc";
	+ reg = <0 0x05090000 0 0x9000>;
	+ clocks = <&rpmhcc RPMH_CXO_CLK>,
	+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
	+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
	+ clock-names = "bi_tcxo",
	+ "gcc_gpu_gpll0_clk_src",
	+ "gcc_gpu_gpll0_div_clk_src";
	+ #clock-cells = <1>;
	+ #reset-cells = <1>;
	+ #power-domain-cells = <1>;
	};

	qspi: spi@88dc000 {
	compatible = "qcom,qspi-v1";
	reg = <0 0x088dc000 0 0x600>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
	<&gcc GCC_QSPI_CORE_CLK>;
	clock-names = "iface", "core";
	status = "disabled";
	};

	usb_1_hsphy: phy@88e3000 {
	compatible = "qcom,sc7180-qusb2-phy";
	reg = <0 0x088e3000 0 0x400>;
	status = "disabled";
	#phy-cells = <0>;
	clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	<&rpmhcc RPMH_CXO_CLK>;
	clock-names = "cfg_ahb", "ref";
	resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

	nvmem-cells = <&qusb2p_hstx_trim>;
	};

	usb_1_qmpphy: phy-wrapper@88e9000 {
	compatible = "qcom,sc7180-qmp-usb3-phy";
	reg = <0 0x088e9000 0 0x18c>,
	<0 0x088e8000 0 0x38>;
	reg-names = "reg-base", "dp_com";
	status = "disabled";
	#clock-cells = <1>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
	<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
	<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
	clock-names = "aux", "cfg_ahb", "ref", "com_aux";

	- resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
	- <&gcc GCC_USB3_PHY_PRIM_BCR>;
	+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
	+ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
	reset-names = "phy", "common";

	usb_1_ssphy: phy@88e9200 {
	reg = <0 0x088e9200 0 0x128>,
	<0 0x088e9400 0 0x200>,
	<0 0x088e9c00 0 0x218>,
	<0 0x088e9600 0 0x128>,
	<0 0x088e9800 0 0x200>,
	<0 0x088e9a00 0 0x18>;
	#clock-cells = <0>;
	#phy-cells = <0>;
	clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
	clock-names = "pipe0";
	clock-output-names = "usb3_phy_pipe_clk_src";
	};
	};

	+ dc_noc: interconnect@9160000 {
	+ compatible = "qcom,sc7180-dc-noc";
	+ reg = <0 0x09160000 0 0x03200>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	system-cache-controller@9200000 {
	compatible = "qcom,sc7180-llcc";
	reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
	reg-names = "llcc_base", "llcc_broadcast_base";
	interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
	};

	+ gem_noc: interconnect@9680000 {
	+ compatible = "qcom,sc7180-gem-noc";
	+ reg = <0 0x09680000 0 0x3e200>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	+ npu_noc: interconnect@9990000 {
	+ compatible = "qcom,sc7180-npu-noc";
	+ reg = <0 0x09990000 0 0x1600>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	usb_1: usb@a6f8800 {
	compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
	reg = <0 0x0a6f8800 0 0x400>;
	status = "disabled";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	dma-ranges;

	clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
	<&gcc GCC_USB30_PRIM_MASTER_CLK>,
	<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
	<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
	<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
	clock-names = "cfg_noc", "core", "iface", "mock_utmi",
	"sleep";

	assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
	<&gcc GCC_USB30_PRIM_MASTER_CLK>;
	assigned-clock-rates = <19200000>, <150000000>;

	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hs_phy_irq", "ss_phy_irq",
	"dm_hs_phy_irq", "dp_hs_phy_irq";

	power-domains = <&gcc USB30_PRIM_GDSC>;

	resets = <&gcc GCC_USB30_PRIM_BCR>;

	usb_1_dwc3: dwc3@a600000 {
	compatible = "snps,dwc3";
	reg = <0 0x0a600000 0 0xe000>;
	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
	iommus = <&apps_smmu 0x540 0>;
	snps,dis_u2_susphy_quirk;
	snps,dis_enblslpm_quirk;
	phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
	phy-names = "usb2-phy", "usb3-phy";
	};
	};

	+ venus: video-codec@aa00000 {
	+ compatible = "qcom,sc7180-venus";
	+ reg = <0 0x0aa00000 0 0xff000>;
	+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	+ power-domains = <&videocc VENUS_GDSC>,
	+ <&videocc VCODEC0_GDSC>;
	+ power-domain-names = "venus", "vcodec0";
	+ clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
	+ <&videocc VIDEO_CC_VENUS_AHB_CLK>,
	+ <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
	+ <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
	+ <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
	+ clock-names = "core", "iface", "bus",
	+ "vcodec0_core", "vcodec0_bus";
	+ iommus = <&apps_smmu 0x0c00 0x60>;
	+ memory-region = <&venus_mem>;
	+
	+ video-decoder {
	+ compatible = "venus-decoder";
	+ };
	+
	+ video-encoder {
	+ compatible = "venus-encoder";
	+ };
	+ };
	+
	+ videocc: clock-controller@ab00000 {
	+ compatible = "qcom,sc7180-videocc";
	+ reg = <0 0x0ab00000 0 0x10000>;
	+ clocks = <&rpmhcc RPMH_CXO_CLK>;
	+ clock-names = "bi_tcxo";
	+ #clock-cells = <1>;
	+ #reset-cells = <1>;
	+ #power-domain-cells = <1>;
	+ };
	+
	+ camnoc_virt: interconnect@ac00000 {
	+ compatible = "qcom,sc7180-camnoc-virt";
	+ reg = <0 0x0ac00000 0 0x1000>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	+ mdss: mdss@ae00000 {
	+ compatible = "qcom,sc7180-mdss";
	+ reg = <0 0x0ae00000 0 0x1000>;
	+ reg-names = "mdss";
	+
	+ power-domains = <&dispcc MDSS_GDSC>;
	+
	+ clocks = <&gcc GCC_DISP_AHB_CLK>,
	+ <&gcc GCC_DISP_HF_AXI_CLK>,
	+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
	+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
	+ clock-names = "iface", "bus", "ahb", "core";
	+
	+ assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
	+ assigned-clock-rates = <300000000>;
	+
	+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	+ interrupt-controller;
	+ #interrupt-cells = <1>;
	+
	+ iommus = <&apps_smmu 0x800 0x2>;
	+
	+ #address-cells = <2>;
	+ #size-cells = <2>;
	+ ranges;
	+
	+ status = "disabled";
	+
	+ mdp: mdp@ae01000 {
	+ compatible = "qcom,sc7180-dpu";
	+ reg = <0 0x0ae01000 0 0x8f000>,
	+ <0 0x0aeb0000 0 0x2008>;
	+ reg-names = "mdp", "vbif";
	+
	+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
	+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
	+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
	+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
	+ clock-names = "iface", "rot", "lut", "core",
	+ "vsync";
	+ assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
	+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
	+ assigned-clock-rates = <300000000>,
	+ <19200000>;
	+
	+ interrupt-parent = <&mdss>;
	+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
	+
	+ status = "disabled";
	+
	+ ports {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ port@0 {
	+ reg = <0>;
	+ dpu_intf1_out: endpoint {
	+ remote-endpoint = <&dsi0_in>;
	+ };
	+ };
	+ };
	+ };
	+
	+ dsi0: dsi@ae94000 {
	+ compatible = "qcom,mdss-dsi-ctrl";
	+ reg = <0 0x0ae94000 0 0x400>;
	+ reg-names = "dsi_ctrl";
	+
	+ interrupt-parent = <&mdss>;
	+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
	+
	+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
	+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
	+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
	+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
	+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
	+ <&gcc GCC_DISP_HF_AXI_CLK>;
	+ clock-names = "byte",
	+ "byte_intf",
	+ "pixel",
	+ "core",
	+ "iface",
	+ "bus";
	+
	+ phys = <&dsi_phy>;
	+ phy-names = "dsi";
	+
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ status = "disabled";
	+
	+ ports {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ port@0 {
	+ reg = <0>;
	+ dsi0_in: endpoint {
	+ remote-endpoint = <&dpu_intf1_out>;
	+ };
	+ };
	+
	+ port@1 {
	+ reg = <1>;
	+ dsi0_out: endpoint {
	+ };
	+ };
	+ };
	+ };
	+
	+ dsi_phy: dsi-phy@ae94400 {
	+ compatible = "qcom,dsi-phy-10nm";
	+ reg = <0 0x0ae94400 0 0x200>,
	+ <0 0x0ae94600 0 0x280>,
	+ <0 0x0ae94a00 0 0x1e0>;
	+ reg-names = "dsi_phy",
	+ "dsi_phy_lane",
	+ "dsi_pll";
	+
	+ #clock-cells = <1>;
	+ #phy-cells = <0>;
	+
	+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	+ <&rpmhcc RPMH_CXO_CLK>;
	+ clock-names = "iface", "ref";
	+
	+ status = "disabled";
	+ };
	+ };
	+
	+ dispcc: clock-controller@af00000 {
	+ compatible = "qcom,sc7180-dispcc";
	+ reg = <0 0x0af00000 0 0x200000>;
	+ clocks = <&rpmhcc RPMH_CXO_CLK>,
	+ <&gcc GCC_DISP_GPLL0_CLK_SRC>,
	+ <&dsi_phy 0>,
	+ <&dsi_phy 1>,
	+ <0>,
	+ <0>;
	+ clock-names = "bi_tcxo",
	+ "gcc_disp_gpll0_clk_src",
	+ "dsi0_phy_pll_out_byteclk",
	+ "dsi0_phy_pll_out_dsiclk",
	+ "dp_phy_pll_link_clk",
	+ "dp_phy_pll_vco_div_clk";
	+ #clock-cells = <1>;
	+ #reset-cells = <1>;
	+ #power-domain-cells = <1>;
	+ };
	+
	pdc: interrupt-controller@b220000 {
	compatible = "qcom,sc7180-pdc", "qcom,pdc";
	reg = <0 0x0b220000 0 0x30000>;
	qcom,pdc-ranges = <0 480 15>, <17 497 98>,
	<119 634 4>, <124 639 1>;
	#interrupt-cells = <2>;
	interrupt-parent = <&intc>;
	interrupt-controller;
	};

	pdc_reset: reset-controller@b2e0000 {
	compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
	reg = <0 0x0b2e0000 0 0x20000>;
	#reset-cells = <1>;
	};

	tsens0: thermal-sensor@c263000 {
	compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
	reg = <0 0x0c263000 0 0x1ff>, /* TM */
	<0 0x0c222000 0 0x1ff>; /* SROT */
	#qcom,sensors = <15>;
	interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "uplow","critical";
	#thermal-sensor-cells = <1>;
	};

	tsens1: thermal-sensor@c265000 {
	compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
	reg = <0 0x0c265000 0 0x1ff>, /* TM */
	<0 0x0c223000 0 0x1ff>; /* SROT */
	#qcom,sensors = <10>;
	interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "uplow","critical";
	#thermal-sensor-cells = <1>;
	};

	aoss_reset: reset-controller@c2a0000 {
	compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
	reg = <0 0x0c2a0000 0 0x31000>;
	#reset-cells = <1>;
	};

	aoss_qmp: qmp@c300000 {
	compatible = "qcom,sc7180-aoss-qmp";
	reg = <0 0x0c300000 0 0x100000>;
	interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
	mboxes = <&apss_shared 0>;

	#clock-cells = <0>;
	#power-domain-cells = <1>;
	};

	spmi_bus: spmi@c440000 {
	compatible = "qcom,spmi-pmic-arb";
	reg = <0 0x0c440000 0 0x1100>,
	<0 0x0c600000 0 0x2000000>,
	<0 0x0e600000 0 0x100000>,
	<0 0x0e700000 0 0xa0000>,
	<0 0x0c40a000 0 0x26000>;
	reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
	interrupt-names = "periph_irq";
	interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
	qcom,ee = <0>;
	qcom,channel = <0>;
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-controller;
	#interrupt-cells = <4>;
	cell-index = <0>;
	};

	apps_smmu: iommu@15000000 {
	compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
	reg = <0 0x15000000 0 0x100000>;
	#iommu-cells = <2>;
	#global-interrupts = <1>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
	};

	intc: interrupt-controller@17a00000 {
	compatible = "arm,gic-v3";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0 0x17a00000 0 0x10000>, /* GICD */
	<0 0x17a60000 0 0x100000>; /* GICR * 8 */
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

	msi-controller@17a40000 {
	compatible = "arm,gic-v3-its";
	msi-controller;
	#msi-cells = <1>;
	reg = <0 0x17a40000 0 0x20000>;
	status = "disabled";
	};
	};

	apss_shared: mailbox@17c00000 {
	compatible = "qcom,sc7180-apss-shared";
	reg = <0 0x17c00000 0 0x10000>;
	#mbox-cells = <1>;
	};

	watchdog@17c10000 {
	compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
	reg = <0 0x17c10000 0 0x1000>;
	clocks = <&sleep_clk>;
	};

	timer@17c20000{
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	compatible = "arm,armv7-timer-mem";
	reg = <0 0x17c20000 0 0x1000>;

	frame@17c21000 {
	frame-number = <0>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0 0x17c21000 0 0x1000>,
	<0 0x17c22000 0 0x1000>;
	};

	frame@17c23000 {
	frame-number = <1>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0 0x17c23000 0 0x1000>;
	status = "disabled";
	};

	frame@17c25000 {
	frame-number = <2>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0 0x17c25000 0 0x1000>;
	status = "disabled";
	};

	frame@17c27000 {
	frame-number = <3>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0 0x17c27000 0 0x1000>;
	status = "disabled";
	};

	frame@17c29000 {
	frame-number = <4>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0 0x17c29000 0 0x1000>;
	status = "disabled";
	};

	frame@17c2b000 {
	frame-number = <5>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0 0x17c2b000 0 0x1000>;
	status = "disabled";
	};

	frame@17c2d000 {
	frame-number = <6>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0 0x17c2d000 0 0x1000>;
	status = "disabled";
	};
	};

	apps_rsc: rsc@18200000 {
	compatible = "qcom,rpmh-rsc";
	reg = <0 0x18200000 0 0x10000>,
	<0 0x18210000 0 0x10000>,
	<0 0x18220000 0 0x10000>;
	reg-names = "drv-0", "drv-1", "drv-2";
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	qcom,tcs-offset = <0xd00>;
	qcom,drv-id = <2>;
	qcom,tcs-config = <ACTIVE_TCS 2>,
	<SLEEP_TCS 3>,
	<WAKE_TCS 3>,
	<CONTROL_TCS 1>;

	rpmhcc: clock-controller {
	compatible = "qcom,sc7180-rpmh-clk";
	clocks = <&xo_board>;
	clock-names = "xo";
	#clock-cells = <1>;
	};

	rpmhpd: power-controller {
	compatible = "qcom,sc7180-rpmhpd";
	#power-domain-cells = <1>;
	operating-points-v2 = <&rpmhpd_opp_table>;

	rpmhpd_opp_table: opp-table {
	compatible = "operating-points-v2";

	rpmhpd_opp_ret: opp1 {
	opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
	};

	rpmhpd_opp_min_svs: opp2 {
	opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
	};

	rpmhpd_opp_low_svs: opp3 {
	opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
	};

	rpmhpd_opp_svs: opp4 {
	opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
	};

	rpmhpd_opp_svs_l1: opp5 {
	opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
	};

	rpmhpd_opp_svs_l2: opp6 {
	opp-level = <224>;
	};

	rpmhpd_opp_nom: opp7 {
	opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
	};

	rpmhpd_opp_nom_l1: opp8 {
	opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
	};

	rpmhpd_opp_nom_l2: opp9 {
	opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
	};

	rpmhpd_opp_turbo: opp10 {
	opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
	};

	rpmhpd_opp_turbo_l1: opp11 {
	opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
	};
	};
	};
	+
	+ apps_bcm_voter: bcm_voter {
	+ compatible = "qcom,bcm-voter";
	+ };
	+ };
	+
	+ osm_l3: interconnect@18321000 {
	+ compatible = "qcom,sc7180-osm-l3";
	+ reg = <0 0x18321000 0 0x1400>;
	+
	+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
	+ clock-names = "xo", "alternate";
	+
	+ #interconnect-cells = <1>;
	};

	cpufreq_hw: cpufreq@18323000 {
	compatible = "qcom,cpufreq-hw";
	reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
	reg-names = "freq-domain0", "freq-domain1";

	clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
	clock-names = "xo", "alternate";

	#freq-domain-cells = <1>;
	};
	};

	thermal-zones {
	cpu0-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 1>;

	trips {
	cpu0_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu0_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu0_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu0_alert0>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu0_alert1>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu1-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 2>;

	trips {
	cpu1_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu1_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu1_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu1_alert0>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu1_alert1>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu2-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 3>;

	trips {
	cpu2_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu2_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu2_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu2_alert0>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu2_alert1>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu3-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 4>;

	trips {
	cpu3_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu3_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu3_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu3_alert0>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu3_alert1>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu4-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 5>;

	trips {
	cpu4_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu4_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu4_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu4_alert0>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu4_alert1>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu5-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 6>;

	trips {
	cpu5_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu5_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu5_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu5_alert0>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu5_alert1>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu6-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 9>;

	trips {
	cpu6_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu6_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu6_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu6_alert0>;
	cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu6_alert1>;
	cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu7-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 10>;

	trips {
	cpu7_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu7_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu7_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu7_alert0>;
	cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu7_alert1>;
	cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu8-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 11>;

	trips {
	cpu8_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu8_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu8_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu8_alert0>;
	cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu8_alert1>;
	cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu9-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 12>;

	trips {
	cpu9_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu9_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu9_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu9_alert0>;
	cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu9_alert1>;
	cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	aoss0-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 0>;

	trips {
	aoss0_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	+
	+ aoss0_crit: aoss0_crit {
	+ temperature = <110000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	};
	};

	cpuss0-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 7>;

	trips {
	cpuss0_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	cpuss0_crit: cluster0_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cpuss1-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 8>;

	trips {
	cpuss1_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	cpuss1_crit: cluster0_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	gpuss0-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 13>;

	trips {
	gpuss0_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	+
	+ gpuss0_crit: gpuss0_crit {
	+ temperature = <110000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	};
	};

	gpuss1-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 14>;

	trips {
	gpuss1_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	+
	+ gpuss1_crit: gpuss1_crit {
	+ temperature = <110000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	};
	};

	aoss1-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 0>;

	trips {
	aoss1_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	+
	+ aoss1_crit: aoss1_crit {
	+ temperature = <110000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	};
	};

	cwlan-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 1>;

	trips {
	cwlan_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	+
	+ cwlan_crit: cwlan_crit {
	+ temperature = <110000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	};
	};

	audio-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 2>;

	trips {
	audio_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	+
	+ audio_crit: audio_crit {
	+ temperature = <110000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	};
	};

	ddr-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 3>;

	trips {
	ddr_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	+
	+ ddr_crit: ddr_crit {
	+ temperature = <110000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	};
	};

	q6-hvx-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 4>;

	trips {
	q6_hvx_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	+
	+ q6_hvx_crit: q6_hvx_crit {
	+ temperature = <110000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	};
	};

	camera-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 5>;

	trips {
	camera_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	+
	+ camera_crit: camera_crit {
	+ temperature = <110000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	};
	};

	mdm-core-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 6>;

	trips {
	mdm_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	+
	+ mdm_crit: mdm_crit {
	+ temperature = <110000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	};
	};

	mdm-dsp-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 7>;

	trips {
	mdm_dsp_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	+
	+ mdm_dsp_crit: mdm_dsp_crit {
	+ temperature = <110000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	};
	};

	npu-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 8>;

	trips {
	npu_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	+
	+ npu_crit: npu_crit {
	+ temperature = <110000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	};
	};

	video-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 9>;

	trips {
	video_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	+
	+ video_crit: video_crit {
	+ temperature = <110000>;
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/qcom/sdm845-cheza.dtsi b/sys/gnu/dts/arm64/qcom/sdm845-cheza.dtsi
	index 7b53b3c7ffe6..9070be43a309 100644
	--- a/sys/gnu/dts/arm64/qcom/sdm845-cheza.dtsi
	+++ b/sys/gnu/dts/arm64/qcom/sdm845-cheza.dtsi
	@@ -1,1294 +1,1309 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Google Cheza device tree source (common between revisions)
	*
	* Copyright 2018 Google LLC.
	*/

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
	#include "sdm845.dtsi"

	/* PMICs depend on spmi_bus label and so must come after SoC */
	#include "pm8005.dtsi"
	#include "pm8998.dtsi"

	/ {
	aliases {
	bluetooth0 = &bluetooth;
	hsuart0 = &uart6;
	serial0 = &uart9;
	wifi0 = &wifi;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	backlight: backlight {
	compatible = "pwm-backlight";
	pwms = <&cros_ec_pwm 0>;
	enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
	power-supply = <&ppvar_sys>;
	pinctrl-names = "default";
	pinctrl-0 = <&ap_edp_bklten>;
	};

	/* FIXED REGULATORS - parents above children */

	/* This is the top level supply and variable voltage */
	ppvar_sys: ppvar-sys-regulator {
	compatible = "regulator-fixed";
	regulator-name = "ppvar_sys";
	regulator-always-on;
	regulator-boot-on;
	};

	/* This divides ppvar_sys by 2, so voltage is variable */
	src_vph_pwr: src-vph-pwr-regulator {
	compatible = "regulator-fixed";
	regulator-name = "src_vph_pwr";

	/* EC turns on with switchcap_on_l; always on for AP */
	regulator-always-on;
	regulator-boot-on;

	vin-supply = <&ppvar_sys>;
	};

	pp5000_a: pp5000-a-regulator {
	compatible = "regulator-fixed";
	regulator-name = "pp5000_a";

	/* EC turns on with en_pp5000_a; always on for AP */
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;

	vin-supply = <&ppvar_sys>;
	};

	src_vreg_bob: src-vreg-bob-regulator {
	compatible = "regulator-fixed";
	regulator-name = "src_vreg_bob";

	/* EC turns on with vbob_en; always on for AP */
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <3600000>;
	regulator-max-microvolt = <3600000>;

	vin-supply = <&ppvar_sys>;
	};

	pp3300_dx_edp: pp3300-dx-edp-regulator {
	compatible = "regulator-fixed";
	regulator-name = "pp3300_dx_edp";

	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	pinctrl-names = "default";
	pinctrl-0 = <&en_pp3300_dx_edp>;
	};

	/*
	* Apparently RPMh does not provide support for PM8998 S4 because it
	* is always-on; model it as a fixed regulator.
	*/
	src_pp1800_s4a: pm8998-smps4 {
	compatible = "regulator-fixed";
	regulator-name = "src_pp1800_s4a";

	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	regulator-always-on;
	regulator-boot-on;

	vin-supply = <&src_vph_pwr>;
	};

	/* BOARD-SPECIFIC TOP LEVEL NODES */

	gpio-keys {
	compatible = "gpio-keys";
	pinctrl-names = "default";
	pinctrl-0 = <&pen_eject_odl>;

	pen-insert {
	label = "Pen Insert";
	/* Insert = low, eject = high */
	gpios = <&tlmm 119 GPIO_ACTIVE_LOW>;
	linux,code = <SW_PEN_INSERTED>;
	linux,input-type = <EV_SW>;
	wakeup-source;
	};
	};

	panel: panel {
	compatible ="innolux,p120zdg-bf1";
	power-supply = <&pp3300_dx_edp>;
	backlight = <&backlight>;
	no-hpd;

	ports {
	panel_in: port {
	panel_in_edp: endpoint {
	remote-endpoint = <&sn65dsi86_out>;
	};
	};
	};
	};
	};

	/*
	* Reserved memory changes
	*
	* Putting this all together (out of order with the rest of the file) to keep
	* all modifications to the memory map (from sdm845.dtsi) in one place.
	*/

	/*
	* Our mpss_region is 8MB bigger than the default one and that conflicts
	* with venus_mem and cdsp_mem.
	*
	* For venus_mem we'll delete and re-create at a different address.
	*
	* cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but
	* that also means we need to delete cdsp_pas.
	*/
	/delete-node/ &venus_mem;
	/delete-node/ &cdsp_mem;
	/delete-node/ &cdsp_pas;
	/delete-node/ &gpu_mem;

	/* Increase the size from 120 MB to 128 MB */
	&mpss_region {
	reg = <0 0x8e000000 0 0x8000000>;
	};

	/* Increase the size from 2MB to 8MB */
	&rmtfs_mem {
	reg = <0 0x88f00000 0 0x800000>;
	};

	/ {
	reserved-memory {
	venus_mem: memory@96000000 {
	reg = <0 0x96000000 0 0x500000>;
	no-map;
	};
	};
	};

	&qspi {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>;

	flash@0 {
	compatible = "jedec,spi-nor";
	reg = <0>;

	/*
	* In theory chip supports up to 104 MHz and controller up
	* to 80 MHz, but above 25 MHz wasn't reliable so we'll use
	* that for now. b:117440651
	*/
	spi-max-frequency = <25000000>;
	spi-tx-bus-width = <2>;
	spi-rx-bus-width = <2>;
	};
	};


	&apps_rsc {
	pm8998-rpmh-regulators {
	compatible = "qcom,pm8998-rpmh-regulators";
	qcom,pmic-id = "a";

	vdd-s1-supply = <&src_vph_pwr>;
	vdd-s2-supply = <&src_vph_pwr>;
	vdd-s3-supply = <&src_vph_pwr>;
	vdd-s4-supply = <&src_vph_pwr>;
	vdd-s5-supply = <&src_vph_pwr>;
	vdd-s6-supply = <&src_vph_pwr>;
	vdd-s7-supply = <&src_vph_pwr>;
	vdd-s8-supply = <&src_vph_pwr>;
	vdd-s9-supply = <&src_vph_pwr>;
	vdd-s10-supply = <&src_vph_pwr>;
	vdd-s11-supply = <&src_vph_pwr>;
	vdd-s12-supply = <&src_vph_pwr>;
	vdd-s13-supply = <&src_vph_pwr>;
	vdd-l1-l27-supply = <&src_pp1025_s7a>;
	vdd-l2-l8-l17-supply = <&src_pp1350_s3a>;
	vdd-l3-l11-supply = <&src_pp1025_s7a>;
	vdd-l4-l5-supply = <&src_pp1025_s7a>;
	vdd-l6-supply = <&src_vph_pwr>;
	vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>;
	vdd-l9-supply = <&src_pp2040_s5a>;
	vdd-l10-l23-l25-supply = <&src_vreg_bob>;
	vdd-l13-l19-l21-supply = <&src_vreg_bob>;
	vdd-l16-l28-supply = <&src_vreg_bob>;
	vdd-l18-l22-supply = <&src_vreg_bob>;
	vdd-l20-l24-supply = <&src_vreg_bob>;
	vdd-l26-supply = <&src_pp1350_s3a>;
	vin-lvs-1-2-supply = <&src_pp1800_s4a>;

	src_pp1125_s2a: smps2 {
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	};

	src_pp1350_s3a: smps3 {
	regulator-min-microvolt = <1352000>;
	regulator-max-microvolt = <1352000>;
	};

	src_pp2040_s5a: smps5 {
	regulator-min-microvolt = <1904000>;
	regulator-max-microvolt = <2040000>;
	};

	src_pp1025_s7a: smps7 {
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1028000>;
	};

	vdd_qusb_hs0:
	vdda_hp_pcie_core:
	vdda_mipi_csi0_0p9:
	vdda_mipi_csi1_0p9:
	vdda_mipi_csi2_0p9:
	vdda_mipi_dsi0_pll:
	vdda_mipi_dsi1_pll:
	vdda_qlink_lv:
	vdda_qlink_lv_ck:
	vdda_qrefs_0p875:
	vdda_pcie_core:
	vdda_pll_cc_ebi01:
	vdda_pll_cc_ebi23:
	vdda_sp_sensor:
	vdda_ufs1_core:
	vdda_ufs2_core:
	vdda_usb1_ss_core:
	vdda_usb2_ss_core:
	src_pp875_l1a: ldo1 {
	regulator-min-microvolt = <880000>;
	regulator-max-microvolt = <880000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vddpx_10:
	src_pp1200_l2a: ldo2 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;

	/* TODO: why??? */
	regulator-always-on;
	};

	pp1000_l3a_sdr845: ldo3 {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vdd_wcss_cx:
	vdd_wcss_mx:
	vdda_wcss_pll:
	src_pp800_l5a: ldo5 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vddpx_13:
	src_pp1800_l6a: ldo6 {
	regulator-min-microvolt = <1856000>;
	regulator-max-microvolt = <1856000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	pp1800_l7a_wcn3990: ldo7 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	src_pp1200_l8a: ldo8 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1248000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	pp1800_dx_pen:
	src_pp1800_l9a: ldo9 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	src_pp1800_l10a: ldo10 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	pp1000_l11a_sdr845: ldo11 {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1048000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vdd_qfprom:
	vdd_qfprom_sp:
	vdda_apc1_cs_1p8:
	vdda_gfx_cs_1p8:
	vdda_qrefs_1p8:
	vdda_qusb_hs0_1p8:
	vddpx_11:
	src_pp1800_l12a: ldo12 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vddpx_2:
	src_pp2950_l13a: ldo13 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2960000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	src_pp1800_l14a: ldo14 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	src_pp1800_l15a: ldo15 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	pp2700_l16a: ldo16 {
	regulator-min-microvolt = <2704000>;
	regulator-max-microvolt = <2704000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	src_pp1300_l17a: ldo17 {
	regulator-min-microvolt = <1304000>;
	regulator-max-microvolt = <1304000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	pp2700_l18a: ldo18 {
	regulator-min-microvolt = <2704000>;
	regulator-max-microvolt = <2960000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	/*
	* NOTE: this rail should have been called
	* src_pp3300_l19a in the schematic
	*/
	src_pp3000_l19a: ldo19 {
	regulator-min-microvolt = <3304000>;
	regulator-max-microvolt = <3304000>;

	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	src_pp2950_l20a: ldo20 {
	regulator-min-microvolt = <2704000>;
	regulator-max-microvolt = <2960000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	src_pp2950_l21a: ldo21 {
	regulator-min-microvolt = <2704000>;
	regulator-max-microvolt = <2960000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	pp3300_hub:
	src_pp3300_l22a: ldo22 {
	regulator-min-microvolt = <3304000>;
	regulator-max-microvolt = <3304000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	/*
	* HACK: Should add a usb hub node and driver
	* to turn this on and off at suspend/resume time
	*/
	regulator-boot-on;
	regulator-always-on;
	};

	pp3300_l23a_ch1_wcn3990: ldo23 {
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3312000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vdda_qusb_hs0_3p1:
	src_pp3075_l24a: ldo24 {
	regulator-min-microvolt = <3088000>;
	regulator-max-microvolt = <3088000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	pp3300_l25a_ch0_wcn3990: ldo25 {
	regulator-min-microvolt = <3304000>;
	regulator-max-microvolt = <3304000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	pp1200_hub:
	vdda_hp_pcie_1p2:
	vdda_hv_ebi0:
	vdda_hv_ebi1:
	vdda_hv_ebi2:
	vdda_hv_ebi3:
	vdda_mipi_csi_1p25:
	vdda_mipi_dsi0_1p2:
	vdda_mipi_dsi1_1p2:
	vdda_pcie_1p2:
	vdda_ufs1_1p2:
	vdda_ufs2_1p2:
	vdda_usb1_ss_1p2:
	vdda_usb2_ss_1p2:
	src_pp1200_l26a: ldo26 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	pp3300_dx_pen:
	src_pp3300_l28a: ldo28 {
	regulator-min-microvolt = <3304000>;
	regulator-max-microvolt = <3304000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	src_pp1800_lvs1: lvs1 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	src_pp1800_lvs2: lvs2 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	};

	pm8005-rpmh-regulators {
	compatible = "qcom,pm8005-rpmh-regulators";
	qcom,pmic-id = "c";

	vdd-s1-supply = <&src_vph_pwr>;
	vdd-s2-supply = <&src_vph_pwr>;
	vdd-s3-supply = <&src_vph_pwr>;
	vdd-s4-supply = <&src_vph_pwr>;

	src_pp600_s3c: smps3 {
	regulator-min-microvolt = <600000>;
	regulator-max-microvolt = <600000>;
	};
	};
	};

	&dsi0 {
	status = "okay";
	vdda-supply = <&vdda_mipi_dsi0_1p2>;

	ports {
	port@1 {
	endpoint {
	remote-endpoint = <&sn65dsi86_in>;
	data-lanes = <0 1 2 3>;
	};
	};
	};
	};

	&dsi0_phy {
	status = "okay";
	vdds-supply = <&vdda_mipi_dsi0_pll>;
	};

	edp_brij_i2c: &i2c3 {
	status = "okay";
	clock-frequency = <400000>;

	sn65dsi86_bridge: bridge@2d {
	compatible = "ti,sn65dsi86";
	reg = <0x2d>;
	pinctrl-names = "default";
	pinctrl-0 = <&edp_brij_en &edp_brij_irq>;

	interrupt-parent = <&tlmm>;
	interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;

	enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;

	vpll-supply = <&src_pp1800_s4a>;
	vccio-supply = <&src_pp1800_s4a>;
	vcca-supply = <&src_pp1200_l2a>;
	vcc-supply = <&src_pp1200_l2a>;

	clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
	clock-names = "refclk";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	sn65dsi86_in: endpoint {
	remote-endpoint = <&dsi0_out>;
	};
	};

	port@1 {
	reg = <1>;
	sn65dsi86_out: endpoint {
	remote-endpoint = <&panel_in_edp>;
	};
	};
	};
	};
	};

	ap_pen_1v8: &i2c11 {
	status = "okay";
	clock-frequency = <400000>;

	digitizer@9 {
	compatible = "wacom,w9013", "hid-over-i2c";
	reg = <0x9>;
	pinctrl-names = "default";
	pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>;

	vdd-supply = <&pp3300_dx_pen>;
	vddl-supply = <&pp1800_dx_pen>;
	post-power-on-delay-ms = <100>;

	interrupt-parent = <&tlmm>;
	interrupts = <24 IRQ_TYPE_LEVEL_LOW>;

	hid-descr-addr = <0x1>;
	};
	};

	amp_i2c: &i2c12 {
	status = "okay";
	clock-frequency = <400000>;
	};

	ap_ts_i2c: &i2c14 {
	status = "okay";
	clock-frequency = <400000>;

	touchscreen@10 {
	compatible = "elan,ekth3500";
	reg = <0x10>;
	pinctrl-names = "default";
	pinctrl-0 = <&ts_int_l &ts_reset_l>;

	interrupt-parent = <&tlmm>;
	interrupts = <125 IRQ_TYPE_LEVEL_LOW>;

	vcc33-supply = <&src_pp3300_l28a>;

	reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>;
	};
	};

	+&ipa {
	+ status = "okay";
	+ modem-init;
	+};
	+
	&lpasscc {
	status = "okay";
	};

	&mdss {
	status = "okay";
	};

	&mdss_mdp {
	status = "okay";
	};

	+&pm8998_pwrkey {
	+ status = "disabled";
	+};
	+
	&qupv3_id_0 {
	status = "okay";
	};

	&qupv3_id_1 {
	status = "okay";
	};

	&sdhc_2 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>;

	vmmc-supply = <&src_pp2950_l21a>;
	vqmmc-supply = <&vddpx_2>;

	cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
	};

	&spi0 {
	status = "okay";
	};

	&spi5 {
	status = "okay";

	tpm@0 {
	compatible = "google,cr50";
	reg = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&h1_ap_int_odl>;
	spi-max-frequency = <800000>;
	interrupt-parent = <&tlmm>;
	interrupts = <129 IRQ_TYPE_EDGE_RISING>;
	};
	};

	&spi10 {
	status = "okay";

	cros_ec: ec@0 {
	compatible = "google,cros-ec-spi";
	reg = <0>;
	interrupt-parent = <&tlmm>;
	interrupts = <122 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&ec_ap_int_l>;
	spi-max-frequency = <3000000>;

	cros_ec_pwm: ec-pwm {
	compatible = "google,cros-ec-pwm";
	#pwm-cells = <1>;
	};

	i2c_tunnel: i2c-tunnel {
	compatible = "google,cros-ec-i2c-tunnel";
	google,remote-bus = <0>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	pdupdate {
	compatible = "google,cros-ec-pd-update";
	};
	};
	};

	#include <arm/cros-ec-keyboard.dtsi>
	#include <arm/cros-ec-sbs.dtsi>

	&uart6 {
	status = "okay";

	bluetooth: wcn3990-bt {
	compatible = "qcom,wcn3990-bt";
	vddio-supply = <&src_pp1800_s4a>;
	vddxo-supply = <&pp1800_l7a_wcn3990>;
	vddrf-supply = <&src_pp1300_l17a>;
	vddch0-supply = <&pp3300_l25a_ch0_wcn3990>;
	max-speed = <3200000>;
	};
	};

	&uart9 {
	status = "okay";
	};

	&ufs_mem_hc {
	status = "okay";

	reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;

	vcc-supply = <&src_pp2950_l20a>;
	vcc-max-microamp = <600000>;
	};

	&ufs_mem_phy {
	status = "okay";

	vdda-phy-supply = <&vdda_ufs1_core>;
	vdda-pll-supply = <&vdda_ufs1_1p2>;
	};

	&usb_1 {
	status = "okay";

	/* We'll use this as USB 2.0 only */
	qcom,select-utmi-as-pipe-clk;
	};

	&usb_1_dwc3 {
	/*
	* The hardware design intends this port to be hooked up in peripheral
	* mode, so we'll hardcode it here. Some details:
	* - SDM845 expects only a single Type C connector so it has only one
	* native Type C port but cheza has two Type C connectors.
	* - The only source of DP is the single native Type C port.
	* - On cheza we want to be able to hook DP up to _either_ of the
	* two Type C connectors and want to be able to achieve 4 lanes of DP.
	* - When you configure a Type C port for 4 lanes of DP you lose USB3.
	* - In order to make everything work, the native Type C port is always
	* configured as 4-lanes DP so it's always available.
	* - The extra USB3 port on SDM845 goes to a USB 3 hub which is then
	* sent to the two Type C connectors.
	* - The extra USB2 lines from the native Type C port are always
	* setup as "peripheral" so that we can mux them over to one connector
	* or the other if someone needs the connector configured as a gadget
	* (but they only get USB2 speeds).
	*
	* All the hardware muxes would allow us to hook things up in different
	* ways to some potential benefit for static configurations (you could
	* achieve extra USB2 bandwidth by using two different ports for the
	* two connectors or possibly even get USB3 peripheral mode), but in
	* each case you end up forcing to disconnect/reconnect an in-use
	* USB session in some cases depending on what you hotplug into the
	* other connector. Thus hardcoding this as peripheral makes sense.
	*/
	dr_mode = "peripheral";

	/*
	* We always need the high speed pins as 4-lanes DP in case someone
	* hotplugs a DP peripheral. Thus limit this port to a max of high
	* speed.
	*/
	maximum-speed = "high-speed";

	/*
	* We don't need the usb3-phy since we run in highspeed mode always, so
	* re-define these properties removing the superspeed USB PHY reference.
	*/
	phys = <&usb_1_hsphy>;
	phy-names = "usb2-phy";
	};

	&usb_1_hsphy {
	status = "okay";

	vdd-supply = <&vdda_usb1_ss_core>;
	vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
	vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;

	qcom,imp-res-offset-value = <8>;
	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
	qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
	qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
	};

	&usb_2 {
	status = "okay";
	};

	&usb_2_dwc3 {
	/* We have this hooked up to a hub and we always use in host mode */
	dr_mode = "host";
	};

	&usb_2_hsphy {
	status = "okay";

	vdd-supply = <&vdda_usb2_ss_core>;
	vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
	vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;

	qcom,imp-res-offset-value = <8>;
	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
	};

	&usb_2_qmpphy {
	status = "okay";

	vdda-phy-supply = <&vdda_usb2_ss_1p2>;
	vdda-pll-supply = <&vdda_usb2_ss_core>;
	};

	&wifi {
	status = "okay";

	vdd-0.8-cx-mx-supply = <&src_pp800_l5a >;
	vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>;
	vdd-1.3-rfa-supply = <&src_pp1300_l17a>;
	vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>;
	};

	/* PINCTRL - additions to nodes defined in sdm845.dtsi */

	&qspi_cs0 {
	pinconf {
	pins = "gpio90";
	bias-disable;
	};
	};

	&qspi_clk {
	pinconf {
	pins = "gpio95";
	bias-disable;
	};
	};

	&qspi_data01 {
	pinconf {
	pins = "gpio91", "gpio92";

	/* High-Z when no transfers; nice to park the lines */
	bias-pull-up;
	};
	};

	&qup_i2c3_default {
	pinconf {
	pins = "gpio41", "gpio42";
	drive-strength = <2>;

	/* Has external pullup */
	bias-disable;
	};
	};

	&qup_i2c11_default {
	pinconf {
	pins = "gpio31", "gpio32";
	drive-strength = <2>;

	/* Has external pullup */
	bias-disable;
	};
	};

	&qup_i2c12_default {
	pinconf {
	pins = "gpio49", "gpio50";
	drive-strength = <2>;

	/* Has external pullup */
	bias-disable;
	};
	};

	&qup_i2c14_default {
	pinconf {
	pins = "gpio33", "gpio34";
	drive-strength = <2>;

	/* Has external pullup */
	bias-disable;
	};
	};

	&qup_spi0_default {
	pinconf {
	pins = "gpio0", "gpio1", "gpio2", "gpio3";
	drive-strength = <2>;
	bias-disable;
	};
	};

	&qup_spi5_default {
	pinconf {
	pins = "gpio85", "gpio86", "gpio87", "gpio88";
	drive-strength = <2>;
	bias-disable;
	};
	};

	&qup_spi10_default {
	pinconf {
	pins = "gpio53", "gpio54", "gpio55", "gpio56";
	drive-strength = <2>;
	bias-disable;
	};
	};

	&qup_uart6_default {
	/* Change pinmux to all 4 pins since CTS and RTS are connected */
	pinmux {
	pins = "gpio45", "gpio46",
	"gpio47", "gpio48";
	};

	pinconf-cts {
	/*
	* Configure a pull-down on 45 (CTS) to match the pull of
	* the Bluetooth module.
	*/
	pins = "gpio45";
	bias-pull-down;
	};

	pinconf-rts-tx {
	/* We'll drive 46 (RTS) and 47 (TX), so no pull */
	pins = "gpio46", "gpio47";
	drive-strength = <2>;
	bias-disable;
	};

	pinconf-rx {
	/*
	* Configure a pull-up on 48 (RX). This is needed to avoid
	* garbage data when the TX pin of the Bluetooth module is
	* in tri-state (module powered off or not driving the
	* signal yet).
	*/
	pins = "gpio48";
	bias-pull-up;
	};
	};

	&qup_uart9_default {
	pinconf-tx {
	pins = "gpio4";
	drive-strength = <2>;
	bias-disable;
	};

	pinconf-rx {
	pins = "gpio5";
	drive-strength = <2>;
	bias-pull-up;
	};
	};

	/* PINCTRL - board-specific pinctrl */
	&pm8005_gpio {
	gpio-line-names = "",
	"",
	"SLB",
	"";
	};

	&pm8998_adc {
	adc-chan@4d {
	reg = <ADC5_AMUX_THM1_100K_PU>;
	label = "sdm_temp";
	};

	adc-chan@4e {
	reg = <ADC5_AMUX_THM2_100K_PU>;
	label = "quiet_temp";
	};

	adc-chan@4f {
	reg = <ADC5_AMUX_THM3_100K_PU>;
	label = "lte_temp_1";
	};

	adc-chan@50 {
	reg = <ADC5_AMUX_THM4_100K_PU>;
	label = "lte_temp_2";
	};

	adc-chan@51 {
	reg = <ADC5_AMUX_THM5_100K_PU>;
	label = "charger_temp";
	};
	};

	&pm8998_gpio {
	gpio-line-names = "",
	"",
	"SW_CTRL",
	"",
	"",
	"",
	"",
	"",
	"",
	"",
	"",
	"",
	"",
	"",
	"",
	"",
	"",
	"",
	"",
	"",
	"",
	"CFG_OPT1",
	"WCSS_PWR_REQ",
	"",
	"CFG_OPT2",
	"SLB";
	};

	&tlmm {
	/*
	* pinctrl settings for pins that have no real owners.
	*/
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&bios_flash_wp_r_l>,
	<&ap_suspend_l_deassert>;

	pinctrl-1 = <&bios_flash_wp_r_l>,
	<&ap_suspend_l_assert>;

	/*
	* Hogs prevent usermode from changing the value. A GPIO can be both
	* here and in the pinctrl section.
	*/
	ap-suspend-l-hog {
	gpio-hog;
	gpios = <126 GPIO_ACTIVE_LOW>;
	output-low;
	};

	ap_edp_bklten: ap-edp-bklten {
	pinmux {
	pins = "gpio37";
	function = "gpio";
	};

	pinconf {
	pins = "gpio37";
	drive-strength = <2>;
	bias-disable;
	};
	};

	bios_flash_wp_r_l: bios-flash-wp-r-l {
	pinmux {
	pins = "gpio128";
	function = "gpio";
	input-enable;
	};

	pinconf {
	pins = "gpio128";
	bias-disable;
	};
	};

	ec_ap_int_l: ec-ap-int-l {
	pinmux {
	pins = "gpio122";
	function = "gpio";
	input-enable;
	};

	pinconf {
	pins = "gpio122";
	bias-pull-up;
	};
	};

	edp_brij_en: edp-brij-en {
	pinmux {
	pins = "gpio102";
	function = "gpio";
	};

	pinconf {
	pins = "gpio102";
	drive-strength = <2>;
	bias-disable;
	};
	};

	edp_brij_irq: edp-brij-irq {
	pinmux {
	pins = "gpio10";
	function = "gpio";
	};

	pinconf {
	pins = "gpio10";
	drive-strength = <2>;
	bias-pull-down;
	};
	};

	en_pp3300_dx_edp: en-pp3300-dx-edp {
	pinmux {
	pins = "gpio43";
	function = "gpio";
	};

	pinconf {
	pins = "gpio43";
	drive-strength = <2>;
	bias-disable;
	};
	};

	h1_ap_int_odl: h1-ap-int-odl {
	pinmux {
	pins = "gpio129";
	function = "gpio";
	input-enable;
	};

	pinconf {
	pins = "gpio129";
	bias-pull-up;
	};
	};

	pen_eject_odl: pen-eject-odl {
	pinmux {
	pins = "gpio119";
	function = "gpio";
	bias-pull-up;
	};
	};

	pen_irq_l: pen-irq-l {
	pinmux {
	pins = "gpio24";
	function = "gpio";
	};

	pinconf {
	pins = "gpio24";

	/* Has external pullup */
	bias-disable;
	};
	};

	pen_pdct_l: pen-pdct-l {
	pinmux {
	pins = "gpio63";
	function = "gpio";
	};

	pinconf {
	pins = "gpio63";

	/* Has external pullup */
	bias-disable;
	};
	};

	pen_rst_l: pen-rst-l {
	pinmux {
	pins = "gpio23";
	function = "gpio";
	};

	pinconf {
	pins = "gpio23";
	bias-disable;
	drive-strength = <2>;

	/*
	* The pen driver doesn't currently support
	* driving this reset line. By specifying
	* output-high here we're relying on the fact
	* that this pin has a default pulldown at boot
	* (which makes sure the pen was in reset if it
	* was powered) and then we set it high here to
	* take it out of reset. Better would be if the
	* pen driver could control this and we could
	* remove "output-high" here.
	*/
	output-high;
	};
	};

	sdc2_clk: sdc2-clk {
	pinconf {
	pins = "sdc2_clk";
	bias-disable;

	/*
	* It seems that mmc_test reports errors if drive
	* strength is not 16.
	*/
	drive-strength = <16>;
	};
	};

	sdc2_cmd: sdc2-cmd {
	pinconf {
	pins = "sdc2_cmd";
	bias-pull-up;
	drive-strength = <16>;
	};
	};

	sdc2_data: sdc2-data {
	pinconf {
	pins = "sdc2_data";
	bias-pull-up;
	drive-strength = <16>;
	};
	};

	sd_cd_odl: sd-cd-odl {
	pinmux {
	pins = "gpio44";
	function = "gpio";
	};

	pinconf {
	pins = "gpio44";
	bias-pull-up;
	};
	};

	ts_int_l: ts-int-l {
	pinmux {
	pins = "gpio125";
	function = "gpio";
	};

	pinconf {
	pins = "gpio125";
	bias-pull-up;
	};
	};

	ts_reset_l: ts-reset-l {
	pinmux {
	pins = "gpio118";
	function = "gpio";
	};

	pinconf {
	pins = "gpio118";
	bias-disable;
	drive-strength = <2>;
	};
	};

	ap_suspend_l_assert: ap_suspend_l_assert {
	config {
	pins = "gpio126";
	function = "gpio";
	bias-no-pull;
	drive-strength = <2>;
	output-low;
	};
	};

	ap_suspend_l_deassert: ap_suspend_l_deassert {
	config {
	pins = "gpio126";
	function = "gpio";
	bias-no-pull;
	drive-strength = <2>;
	output-high;
	};
	};
	};
	+
	+&venus {
	+ video-firmware {
	+ iommus = <&apps_smmu 0x10b2 0x0>;
	+ };
	+};
	diff --git a/sys/gnu/dts/arm64/qcom/sdm845-db845c.dts b/sys/gnu/dts/arm64/qcom/sdm845-db845c.dts
	index eb77aaa6a819..21fd6f8d5799 100644
	--- a/sys/gnu/dts/arm64/qcom/sdm845-db845c.dts
	+++ b/sys/gnu/dts/arm64/qcom/sdm845-db845c.dts
	@@ -1,585 +1,865 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Copyright (c) 2019, Linaro Ltd.
	*/

	/dts-v1/;

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
	#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
	+#include <dt-bindings/sound/qcom,q6afe.h>
	+#include <dt-bindings/sound/qcom,q6asm.h>
	#include "sdm845.dtsi"
	#include "pm8998.dtsi"
	#include "pmi8998.dtsi"

	/ {
	model = "Thundercomm Dragonboard 845c";
	compatible = "thundercomm,db845c", "qcom,sdm845";

	aliases {
	serial0 = &uart9;
	hsuart0 = &uart6;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	dc12v: dc12v-regulator {
	compatible = "regulator-fixed";
	regulator-name = "DC12V";
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	regulator-always-on;
	};

	gpio_keys {
	compatible = "gpio-keys";
	autorepeat;

	pinctrl-names = "default";
	pinctrl-0 = <&vol_up_pin_a>;

	vol-up {
	label = "Volume Up";
	linux,code = <KEY_VOLUMEUP>;
	gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>;
	};
	};

	leds {
	compatible = "gpio-leds";

	user4 {
	label = "green:user4";
	gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "panic-indicator";
	default-state = "off";
	};

	wlan {
	label = "yellow:wlan";
	gpios = <&pm8998_gpio 9 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "phy0tx";
	default-state = "off";
	};

	bt {
	label = "blue:bt";
	gpios = <&pm8998_gpio 5 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "bluetooth-power";
	default-state = "off";
	};
	};

	lt9611_1v8: lt9611-vdd18-regulator {
	compatible = "regulator-fixed";
	regulator-name = "LT9611_1V8";

	vin-supply = <&vdc_5v>;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	lt9611_3v3: lt9611-3v3 {
	compatible = "regulator-fixed";
	regulator-name = "LT9611_3V3";

	vin-supply = <&vdc_3v3>;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	// TODO: make it possible to drive same GPIO from two clients
	// gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>;
	// enable-active-high;
	};

	pcie0_1p05v: pcie-0-1p05v-regulator {
	compatible = "regulator-fixed";
	regulator-name = "PCIE0_1.05V";

	vin-supply = <&vbat>;
	regulator-min-microvolt = <1050000>;
	regulator-max-microvolt = <1050000>;

	// TODO: make it possible to drive same GPIO from two clients
	// gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>;
	// enable-active-high;
	};

	pcie0_3p3v_dual: vldo-3v3-regulator {
	compatible = "regulator-fixed";
	regulator-name = "VLDO_3V3";

	vin-supply = <&vbat>;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>;
	enable-active-high;

	pinctrl-names = "default";
	pinctrl-0 = <&pcie0_pwren_state>;
	};

	v5p0_hdmiout: v5p0-hdmiout-regulator {
	compatible = "regulator-fixed";
	regulator-name = "V5P0_HDMIOUT";

	vin-supply = <&vdc_5v>;
	regulator-min-microvolt = <500000>;
	regulator-max-microvolt = <500000>;

	// TODO: make it possible to drive same GPIO from two clients
	// gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>;
	// enable-active-high;
	};

	vbat: vbat-regulator {
	compatible = "regulator-fixed";
	regulator-name = "VBAT";

	vin-supply = <&dc12v>;
	regulator-min-microvolt = <4200000>;
	regulator-max-microvolt = <4200000>;
	regulator-always-on;
	};

	vbat_som: vbat-som-regulator {
	compatible = "regulator-fixed";
	regulator-name = "VBAT_SOM";

	vin-supply = <&dc12v>;
	regulator-min-microvolt = <4200000>;
	regulator-max-microvolt = <4200000>;
	regulator-always-on;
	};

	vdc_3v3: vdc-3v3-regulator {
	compatible = "regulator-fixed";
	regulator-name = "VDC_3V3";
	vin-supply = <&dc12v>;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	vdc_5v: vdc-5v-regulator {
	compatible = "regulator-fixed";
	regulator-name = "VDC_5V";

	vin-supply = <&dc12v>;
	regulator-min-microvolt = <500000>;
	regulator-max-microvolt = <500000>;
	regulator-always-on;
	};

	vreg_s4a_1p8: vreg-s4a-1p8 {
	compatible = "regulator-fixed";
	regulator-name = "vreg_s4a_1p8";

	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	vph_pwr: vph-pwr-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vph_pwr";

	vin-supply = <&vbat_som>;
	};
	};

	&adsp_pas {
	status = "okay";

	firmware-name = "qcom/sdm845/adsp.mdt";
	};

	&apps_rsc {
	pm8998-rpmh-regulators {
	compatible = "qcom,pm8998-rpmh-regulators";
	qcom,pmic-id = "a";
	vdd-s1-supply = <&vph_pwr>;
	vdd-s2-supply = <&vph_pwr>;
	vdd-s3-supply = <&vph_pwr>;
	vdd-s4-supply = <&vph_pwr>;
	vdd-s5-supply = <&vph_pwr>;
	vdd-s6-supply = <&vph_pwr>;
	vdd-s7-supply = <&vph_pwr>;
	vdd-s8-supply = <&vph_pwr>;
	vdd-s9-supply = <&vph_pwr>;
	vdd-s10-supply = <&vph_pwr>;
	vdd-s11-supply = <&vph_pwr>;
	vdd-s12-supply = <&vph_pwr>;
	vdd-s13-supply = <&vph_pwr>;
	vdd-l1-l27-supply = <&vreg_s7a_1p025>;
	vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
	vdd-l3-l11-supply = <&vreg_s7a_1p025>;
	vdd-l4-l5-supply = <&vreg_s7a_1p025>;
	vdd-l6-supply = <&vph_pwr>;
	vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
	vdd-l9-supply = <&vreg_bob>;
	vdd-l10-l23-l25-supply = <&vreg_bob>;
	vdd-l13-l19-l21-supply = <&vreg_bob>;
	vdd-l16-l28-supply = <&vreg_bob>;
	vdd-l18-l22-supply = <&vreg_bob>;
	vdd-l20-l24-supply = <&vreg_bob>;
	vdd-l26-supply = <&vreg_s3a_1p35>;
	vin-lvs-1-2-supply = <&vreg_s4a_1p8>;

	vreg_s3a_1p35: smps3 {
	regulator-min-microvolt = <1352000>;
	regulator-max-microvolt = <1352000>;
	};

	vreg_s5a_2p04: smps5 {
	regulator-min-microvolt = <1904000>;
	regulator-max-microvolt = <2040000>;
	};

	vreg_s7a_1p025: smps7 {
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1028000>;
	};

	vreg_l1a_0p875: ldo1 {
	regulator-min-microvolt = <880000>;
	regulator-max-microvolt = <880000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l5a_0p8: ldo5 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l12a_1p8: ldo12 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l7a_1p8: ldo7 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l13a_2p95: ldo13 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2960000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l17a_1p3: ldo17 {
	regulator-min-microvolt = <1304000>;
	regulator-max-microvolt = <1304000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l20a_2p95: ldo20 {
	regulator-min-microvolt = <2960000>;
	regulator-max-microvolt = <2968000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l21a_2p95: ldo21 {
	regulator-min-microvolt = <2960000>;
	regulator-max-microvolt = <2968000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l24a_3p075: ldo24 {
	regulator-min-microvolt = <3088000>;
	regulator-max-microvolt = <3088000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l25a_3p3: ldo25 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3312000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l26a_1p2: ldo26 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_lvs1a_1p8: lvs1 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	vreg_lvs2a_1p8: lvs2 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};
	};

	pmi8998-rpmh-regulators {
	compatible = "qcom,pmi8998-rpmh-regulators";
	qcom,pmic-id = "b";

	vdd-bob-supply = <&vph_pwr>;

	vreg_bob: bob {
	regulator-min-microvolt = <3312000>;
	regulator-max-microvolt = <3600000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
	regulator-allow-bypass;
	};
	};
	};

	&cdsp_pas {
	status = "okay";
	firmware-name = "qcom/sdm845/cdsp.mdt";
	};

	&gcc {
	protected-clocks = <GCC_QSPI_CORE_CLK>,
	<GCC_QSPI_CORE_CLK_SRC>,
	<GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
	};

	&gpu {
	zap-shader {
	memory-region = <&gpu_mem>;
	firmware-name = "qcom/sdm845/a630_zap.mbn";
	};
	};

	+&i2c11 {
	+ /* On Low speed expansion */
	+ label = "LS-I2C1";
	+ status = "okay";
	+};
	+
	+&i2c14 {
	+ /* On Low speed expansion */
	+ label = "LS-I2C0";
	+ status = "okay";
	+};
	+
	&mss_pil {
	status = "okay";
	firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
	};

	+&pcie0 {
	+ status = "okay";
	+ perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;
	+ enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>;
	+
	+ vddpe-3v3-supply = <&pcie0_3p3v_dual>;
	+
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pcie0_default_state>;
	+};
	+
	+&pcie0_phy {
	+ status = "okay";
	+
	+ vdda-phy-supply = <&vreg_l1a_0p875>;
	+ vdda-pll-supply = <&vreg_l26a_1p2>;
	+};
	+
	+&pcie1 {
	+ status = "okay";
	+ perst-gpio = <&tlmm 102 GPIO_ACTIVE_LOW>;
	+
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pcie1_default_state>;
	+};
	+
	+&pcie1_phy {
	+ status = "okay";
	+
	+ vdda-phy-supply = <&vreg_l1a_0p875>;
	+ vdda-pll-supply = <&vreg_l26a_1p2>;
	+};
	+
	&pm8998_gpio {
	vol_up_pin_a: vol-up-active {
	pins = "gpio6";
	function = "normal";
	input-enable;
	bias-pull-up;
	qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
	};
	};

	&pm8998_pon {
	resin {
	compatible = "qcom,pm8941-resin";
	interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
	debounce = <15625>;
	bias-pull-up;
	linux,code = <KEY_VOLUMEDOWN>;
	};
	};

	+/* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */
	+&q6afedai {
	+ qi2s@22 {
	+ reg = <22>;
	+ qcom,sd-lines = <0 1 2 3>;
	+ };
	+};
	+
	+&q6asmdai {
	+ dai@0 {
	+ reg = <0>;
	+ };
	+
	+ dai@1 {
	+ reg = <1>;
	+ };
	+
	+ dai@2 {
	+ reg = <2>;
	+ };
	+
	+ dai@3 {
	+ reg = <3>;
	+ direction = <2>;
	+ is-compress-dai;
	+ };
	+};
	+
	&qupv3_id_0 {
	status = "okay";
	};

	&qupv3_id_1 {
	status = "okay";
	};

	&sdhc_2 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;

	vmmc-supply = <&vreg_l21a_2p95>;
	vqmmc-supply = <&vreg_l13a_2p95>;

	bus-width = <4>;
	cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
	};

	+&sound {
	+ compatible = "qcom,db845c-sndcard";
	+ pinctrl-0 = <&quat_mi2s_active
	+ &quat_mi2s_sd0_active
	+ &quat_mi2s_sd1_active
	+ &quat_mi2s_sd2_active
	+ &quat_mi2s_sd3_active>;
	+ pinctrl-names = "default";
	+ model = "DB845c";
	+ audio-routing =
	+ "RX_BIAS", "MCLK",
	+ "AMIC1", "MIC BIAS1",
	+ "AMIC2", "MIC BIAS2",
	+ "DMIC0", "MIC BIAS1",
	+ "DMIC1", "MIC BIAS1",
	+ "DMIC2", "MIC BIAS3",
	+ "DMIC3", "MIC BIAS3",
	+ "SpkrLeft IN", "SPK1 OUT",
	+ "SpkrRight IN", "SPK2 OUT",
	+ "MM_DL1", "MultiMedia1 Playback",
	+ "MM_DL2", "MultiMedia2 Playback",
	+ "MM_DL4", "MultiMedia4 Playback",
	+ "MultiMedia3 Capture", "MM_UL3";
	+
	+ mm1-dai-link {
	+ link-name = "MultiMedia1";
	+ cpu {
	+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
	+ };
	+ };
	+
	+ mm2-dai-link {
	+ link-name = "MultiMedia2";
	+ cpu {
	+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
	+ };
	+ };
	+
	+ mm3-dai-link {
	+ link-name = "MultiMedia3";
	+ cpu {
	+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
	+ };
	+ };
	+
	+ mm4-dai-link {
	+ link-name = "MultiMedia4";
	+ cpu {
	+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA4>;
	+ };
	+ };
	+
	+ slim-dai-link {
	+ link-name = "SLIM Playback";
	+ cpu {
	+ sound-dai = <&q6afedai SLIMBUS_0_RX>;
	+ };
	+
	+ platform {
	+ sound-dai = <&q6routing>;
	+ };
	+
	+ codec {
	+ sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>;
	+ };
	+ };
	+
	+ slimcap-dai-link {
	+ link-name = "SLIM Capture";
	+ cpu {
	+ sound-dai = <&q6afedai SLIMBUS_0_TX>;
	+ };
	+
	+ platform {
	+ sound-dai = <&q6routing>;
	+ };
	+
	+ codec {
	+ sound-dai = <&wcd9340 1>;
	+ };
	+ };
	+};
	+
	+&spi2 {
	+ /* On Low speed expansion */
	+ label = "LS-SPI0";
	+ status = "okay";
	+};
	+
	&tlmm {
	+ pcie0_default_state: pcie0-default {
	+ clkreq {
	+ pins = "gpio36";
	+ function = "pci_e0";
	+ bias-pull-up;
	+ };
	+
	+ reset-n {
	+ pins = "gpio35";
	+ function = "gpio";
	+
	+ drive-strength = <2>;
	+ output-low;
	+ bias-pull-down;
	+ };
	+
	+ wake-n {
	+ pins = "gpio37";
	+ function = "gpio";
	+
	+ drive-strength = <2>;
	+ bias-pull-up;
	+ };
	+ };
	+
	pcie0_pwren_state: pcie0-pwren {
	pins = "gpio90";
	function = "gpio";

	drive-strength = <2>;
	bias-disable;
	};

	+ pcie1_default_state: pcie1-default {
	+ perst-n {
	+ pins = "gpio102";
	+ function = "gpio";
	+
	+ drive-strength = <16>;
	+ bias-disable;
	+ };
	+
	+ clkreq {
	+ pins = "gpio103";
	+ function = "pci_e1";
	+ bias-pull-up;
	+ };
	+
	+ wake-n {
	+ pins = "gpio11";
	+ function = "gpio";
	+
	+ drive-strength = <2>;
	+ bias-pull-up;
	+ };
	+
	+ reset-n {
	+ pins = "gpio75";
	+ function = "gpio";
	+
	+ drive-strength = <16>;
	+ bias-pull-up;
	+ output-high;
	+ };
	+ };
	+
	sdc2_default_state: sdc2-default {
	clk {
	pins = "sdc2_clk";
	bias-disable;

	/*
	* It seems that mmc_test reports errors if drive
	* strength is not 16 on clk, cmd, and data pins.
	*/
	drive-strength = <16>;
	};

	cmd {
	pins = "sdc2_cmd";
	bias-pull-up;
	drive-strength = <10>;
	};

	data {
	pins = "sdc2_data";
	bias-pull-up;
	drive-strength = <10>;
	};
	};

	sdc2_card_det_n: sd-card-det-n {
	pins = "gpio126";
	function = "gpio";
	bias-pull-up;
	};
	+
	+ wcd_intr_default: wcd_intr_default {
	+ pins = <54>;
	+ function = "gpio";
	+
	+ input-enable;
	+ bias-pull-down;
	+ drive-strength = <2>;
	+ };
	+};
	+
	+&uart3 {
	+ label = "LS-UART0";
	+ status = "disabled";
	};

	&uart6 {
	status = "okay";

	bluetooth {
	compatible = "qcom,wcn3990-bt";

	vddio-supply = <&vreg_s4a_1p8>;
	vddxo-supply = <&vreg_l7a_1p8>;
	vddrf-supply = <&vreg_l17a_1p3>;
	vddch0-supply = <&vreg_l25a_3p3>;
	max-speed = <3200000>;
	};
	};

	&uart9 {
	+ label = "LS-UART1";
	status = "okay";
	};

	&usb_1 {
	status = "okay";
	};

	&usb_1_dwc3 {
	dr_mode = "peripheral";
	};

	&usb_1_hsphy {
	status = "okay";

	vdd-supply = <&vreg_l1a_0p875>;
	vdda-pll-supply = <&vreg_l12a_1p8>;
	vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;

	qcom,imp-res-offset-value = <8>;
	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
	qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
	qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
	};

	&usb_1_qmpphy {
	status = "okay";

	vdda-phy-supply = <&vreg_l26a_1p2>;
	vdda-pll-supply = <&vreg_l1a_0p875>;
	};

	&usb_2 {
	status = "okay";
	};

	&usb_2_dwc3 {
	dr_mode = "host";
	};

	&usb_2_hsphy {
	status = "okay";

	vdd-supply = <&vreg_l1a_0p875>;
	vdda-pll-supply = <&vreg_l12a_1p8>;
	vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;

	qcom,imp-res-offset-value = <8>;
	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
	};

	&usb_2_qmpphy {
	status = "okay";

	vdda-phy-supply = <&vreg_l26a_1p2>;
	vdda-pll-supply = <&vreg_l1a_0p875>;
	};

	&ufs_mem_hc {
	status = "okay";

	reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;

	vcc-supply = <&vreg_l20a_2p95>;
	vcc-max-microamp = <800000>;
	};

	&ufs_mem_phy {
	status = "okay";

	vdda-phy-supply = <&vreg_l1a_0p875>;
	vdda-pll-supply = <&vreg_l26a_1p2>;
	};

	+&wcd9340{
	+ pinctrl-0 = <&wcd_intr_default>;
	+ pinctrl-names = "default";
	+ clock-names = "extclk";
	+ clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
	+ reset-gpios = <&tlmm 64 0>;
	+ vdd-buck-supply = <&vreg_s4a_1p8>;
	+ vdd-buck-sido-supply = <&vreg_s4a_1p8>;
	+ vdd-tx-supply = <&vreg_s4a_1p8>;
	+ vdd-rx-supply = <&vreg_s4a_1p8>;
	+ vdd-io-supply = <&vreg_s4a_1p8>;
	+
	+ swm: swm@c85 {
	+ left_spkr: wsa8810-left{
	+ compatible = "sdw10217201000";
	+ reg = <0 1>;
	+ powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>;
	+ #thermal-sensor-cells = <0>;
	+ sound-name-prefix = "SpkrLeft";
	+ #sound-dai-cells = <0>;
	+ };
	+
	+ right_spkr: wsa8810-right{
	+ compatible = "sdw10217201000";
	+ powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>;
	+ reg = <0 2>;
	+ #thermal-sensor-cells = <0>;
	+ sound-name-prefix = "SpkrRight";
	+ #sound-dai-cells = <0>;
	+ };
	+ };
	+};
	+
	&wifi {
	status = "okay";

	vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
	vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
	vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
	vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;

	qcom,snoc-host-cap-8bit-quirk;
	};

	/* PINCTRL - additions to nodes defined in sdm845.dtsi */
	+&qup_spi2_default {
	+ drive-strength = <16>;
	+};
	+
	+&qup_uart3_default{
	+ pinmux {
	+ pins = "gpio41", "gpio42", "gpio43", "gpio44";
	+ function = "qup3";
	+ };
	+};

	&qup_uart6_default {
	pinmux {
	pins = "gpio45", "gpio46", "gpio47", "gpio48";
	function = "qup6";
	};

	cts {
	pins = "gpio45";
	bias-disable;
	};

	rts-tx {
	pins = "gpio46", "gpio47";
	drive-strength = <2>;
	bias-disable;
	};

	rx {
	pins = "gpio48";
	bias-pull-up;
	};
	};

	&qup_uart9_default {
	pinconf-tx {
	pins = "gpio4";
	drive-strength = <2>;
	bias-disable;
	};

	pinconf-rx {
	pins = "gpio5";
	drive-strength = <2>;
	bias-pull-up;
	};
	};
	diff --git a/sys/gnu/dts/arm64/qcom/sdm845-mtp.dts b/sys/gnu/dts/arm64/qcom/sdm845-mtp.dts
	index 09ad37b0dd71..023e8b04c7f6 100644
	--- a/sys/gnu/dts/arm64/qcom/sdm845-mtp.dts
	+++ b/sys/gnu/dts/arm64/qcom/sdm845-mtp.dts
	@@ -1,547 +1,636 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* SDM845 MTP board device tree source
	*
	* Copyright (c) 2018, The Linux Foundation. All rights reserved.
	*/

	/dts-v1/;

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
	#include "sdm845.dtsi"

	/ {
	model = "Qualcomm Technologies, Inc. SDM845 MTP";
	compatible = "qcom,sdm845-mtp";

	aliases {
	serial0 = &uart9;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	vph_pwr: vph-pwr-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vph_pwr";
	regulator-min-microvolt = <3700000>;
	regulator-max-microvolt = <3700000>;
	};

	/*
	* Apparently RPMh does not provide support for PM8998 S4 because it
	* is always-on; model it as a fixed regulator.
	*/
	vreg_s4a_1p8: pm8998-smps4 {
	compatible = "regulator-fixed";
	regulator-name = "vreg_s4a_1p8";

	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	regulator-always-on;
	regulator-boot-on;

	vin-supply = <&vph_pwr>;
	};
	};

	&adsp_pas {
	status = "okay";
	+ firmware-name = "qcom/sdm845/adsp.mdt";
	};

	&apps_rsc {
	pm8998-rpmh-regulators {
	compatible = "qcom,pm8998-rpmh-regulators";
	qcom,pmic-id = "a";

	vdd-s1-supply = <&vph_pwr>;
	vdd-s2-supply = <&vph_pwr>;
	vdd-s3-supply = <&vph_pwr>;
	vdd-s4-supply = <&vph_pwr>;
	vdd-s5-supply = <&vph_pwr>;
	vdd-s6-supply = <&vph_pwr>;
	vdd-s7-supply = <&vph_pwr>;
	vdd-s8-supply = <&vph_pwr>;
	vdd-s9-supply = <&vph_pwr>;
	vdd-s10-supply = <&vph_pwr>;
	vdd-s11-supply = <&vph_pwr>;
	vdd-s12-supply = <&vph_pwr>;
	vdd-s13-supply = <&vph_pwr>;
	vdd-l1-l27-supply = <&vreg_s7a_1p025>;
	vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
	vdd-l3-l11-supply = <&vreg_s7a_1p025>;
	vdd-l4-l5-supply = <&vreg_s7a_1p025>;
	vdd-l6-supply = <&vph_pwr>;
	vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
	vdd-l9-supply = <&vreg_bob>;
	vdd-l10-l23-l25-supply = <&vreg_bob>;
	vdd-l13-l19-l21-supply = <&vreg_bob>;
	vdd-l16-l28-supply = <&vreg_bob>;
	vdd-l18-l22-supply = <&vreg_bob>;
	vdd-l20-l24-supply = <&vreg_bob>;
	vdd-l26-supply = <&vreg_s3a_1p35>;
	vin-lvs-1-2-supply = <&vreg_s4a_1p8>;

	vreg_s2a_1p125: smps2 {
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	};

	vreg_s3a_1p35: smps3 {
	regulator-min-microvolt = <1352000>;
	regulator-max-microvolt = <1352000>;
	};

	vreg_s5a_2p04: smps5 {
	regulator-min-microvolt = <1904000>;
	regulator-max-microvolt = <2040000>;
	};

	vreg_s7a_1p025: smps7 {
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <1028000>;
	};

	vdd_qusb_hs0:
	vdda_hp_pcie_core:
	vdda_mipi_csi0_0p9:
	vdda_mipi_csi1_0p9:
	vdda_mipi_csi2_0p9:
	vdda_mipi_dsi0_pll:
	vdda_mipi_dsi1_pll:
	vdda_qlink_lv:
	vdda_qlink_lv_ck:
	vdda_qrefs_0p875:
	vdda_pcie_core:
	vdda_pll_cc_ebi01:
	vdda_pll_cc_ebi23:
	vdda_sp_sensor:
	vdda_ufs1_core:
	vdda_ufs2_core:
	vdda_usb1_ss_core:
	vdda_usb2_ss_core:
	vreg_l1a_0p875: ldo1 {
	regulator-min-microvolt = <880000>;
	regulator-max-microvolt = <880000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vddpx_10:
	vreg_l2a_1p2: ldo2 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	regulator-always-on;
	};

	vreg_l3a_1p0: ldo3 {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vdd_wcss_cx:
	vdd_wcss_mx:
	vdda_wcss_pll:
	vreg_l5a_0p8: ldo5 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vddpx_13:
	vreg_l6a_1p8: ldo6 {
	regulator-min-microvolt = <1856000>;
	regulator-max-microvolt = <1856000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l7a_1p8: ldo7 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l8a_1p2: ldo8 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1248000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l9a_1p8: ldo9 {
	regulator-min-microvolt = <1704000>;
	regulator-max-microvolt = <2928000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l10a_1p8: ldo10 {
	regulator-min-microvolt = <1704000>;
	regulator-max-microvolt = <2928000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l11a_1p0: ldo11 {
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1048000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vdd_qfprom:
	vdd_qfprom_sp:
	vdda_apc1_cs_1p8:
	vdda_gfx_cs_1p8:
	vdda_qrefs_1p8:
	vdda_qusb_hs0_1p8:
	vddpx_11:
	vreg_l12a_1p8: ldo12 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vddpx_2:
	vreg_l13a_2p95: ldo13 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <2960000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l14a_1p88: ldo14 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l15a_1p8: ldo15 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l16a_2p7: ldo16 {
	regulator-min-microvolt = <2704000>;
	regulator-max-microvolt = <2704000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l17a_1p3: ldo17 {
	regulator-min-microvolt = <1304000>;
	regulator-max-microvolt = <1304000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l18a_2p7: ldo18 {
	regulator-min-microvolt = <2704000>;
	regulator-max-microvolt = <2960000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l19a_3p0: ldo19 {
	regulator-min-microvolt = <2856000>;
	regulator-max-microvolt = <3104000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l20a_2p95: ldo20 {
	regulator-min-microvolt = <2704000>;
	regulator-max-microvolt = <2960000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l21a_2p95: ldo21 {
	regulator-min-microvolt = <2704000>;
	regulator-max-microvolt = <2960000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l22a_2p85: ldo22 {
	regulator-min-microvolt = <2864000>;
	regulator-max-microvolt = <3312000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l23a_3p3: ldo23 {
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3312000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vdda_qusb_hs0_3p1:
	vreg_l24a_3p075: ldo24 {
	regulator-min-microvolt = <3088000>;
	regulator-max-microvolt = <3088000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l25a_3p3: ldo25 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3312000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vdda_hp_pcie_1p2:
	vdda_hv_ebi0:
	vdda_hv_ebi1:
	vdda_hv_ebi2:
	vdda_hv_ebi3:
	vdda_mipi_csi_1p25:
	vdda_mipi_dsi0_1p2:
	vdda_mipi_dsi1_1p2:
	vdda_pcie_1p2:
	vdda_ufs1_1p2:
	vdda_ufs2_1p2:
	vdda_usb1_ss_1p2:
	vdda_usb2_ss_1p2:
	vreg_l26a_1p2: ldo26 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l28a_3p0: ldo28 {
	regulator-min-microvolt = <2856000>;
	regulator-max-microvolt = <3008000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_lvs1a_1p8: lvs1 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};

	vreg_lvs2a_1p8: lvs2 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	};
	};

	pmi8998-rpmh-regulators {
	compatible = "qcom,pmi8998-rpmh-regulators";
	qcom,pmic-id = "b";

	vdd-bob-supply = <&vph_pwr>;

	vreg_bob: bob {
	regulator-min-microvolt = <3312000>;
	regulator-max-microvolt = <3600000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
	regulator-allow-bypass;
	};
	};

	pm8005-rpmh-regulators {
	compatible = "qcom,pm8005-rpmh-regulators";
	qcom,pmic-id = "c";

	vdd-s1-supply = <&vph_pwr>;
	vdd-s2-supply = <&vph_pwr>;
	vdd-s3-supply = <&vph_pwr>;
	vdd-s4-supply = <&vph_pwr>;

	vreg_s3c_0p6: smps3 {
	regulator-min-microvolt = <600000>;
	regulator-max-microvolt = <600000>;
	};
	};
	};

	&cdsp_pas {
	status = "okay";
	+ firmware-name = "qcom/sdm845/cdsp.mdt";
	+};
	+
	+&dsi0 {
	+ status = "okay";
	+ vdda-supply = <&vdda_mipi_dsi0_1p2>;
	+
	+ qcom,dual-dsi-mode;
	+ qcom,master-dsi;
	+
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ ports {
	+ port@1 {
	+ endpoint {
	+ remote-endpoint = <&truly_in_0>;
	+ data-lanes = <0 1 2 3>;
	+ };
	+ };
	+ };
	+
	+ panel@0 {
	+ compatible = "truly,nt35597-2K-display";
	+ reg = <0>;
	+ vdda-supply = <&vreg_l14a_1p88>;
	+
	+ reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
	+ mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
	+
	+ ports {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ port@0 {
	+ reg = <0>;
	+ truly_in_0: endpoint {
	+ remote-endpoint = <&dsi0_out>;
	+ };
	+ };
	+
	+ port@1 {
	+ reg = <1>;
	+ truly_in_1: endpoint {
	+ remote-endpoint = <&dsi1_out>;
	+ };
	+ };
	+ };
	+ };
	+};
	+
	+&dsi0_phy {
	+ status = "okay";
	+ vdds-supply = <&vdda_mipi_dsi0_pll>;
	+};
	+
	+&dsi1 {
	+ status = "okay";
	+ vdda-supply = <&vdda_mipi_dsi1_1p2>;
	+
	+ qcom,dual-dsi-mode;
	+
	+ ports {
	+ port@1 {
	+ endpoint {
	+ remote-endpoint = <&truly_in_1>;
	+ data-lanes = <0 1 2 3>;
	+ };
	+ };
	+ };
	+};
	+
	+&dsi1_phy {
	+ status = "okay";
	+ vdds-supply = <&vdda_mipi_dsi1_pll>;
	};

	&gcc {
	protected-clocks = <GCC_QSPI_CORE_CLK>,
	<GCC_QSPI_CORE_CLK_SRC>,
	<GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
	<GCC_LPASS_Q6_AXI_CLK>,
	<GCC_LPASS_SWAY_CLK>;
	};

	&gpu {
	zap-shader {
	memory-region = <&gpu_mem>;
	firmware-name = "qcom/sdm845/a630_zap.mbn";
	};
	};

	&i2c10 {
	status = "okay";
	clock-frequency = <400000>;
	};

	+&mdss {
	+ status = "okay";
	+};
	+
	+&mdss_mdp {
	+ status = "okay";
	+};
	+
	+&mss_pil {
	+ status = "okay";
	+ firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
	+};
	+
	&qupv3_id_1 {
	status = "okay";
	};

	&sdhc_2 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_card_det_n>;

	vmmc-supply = <&vreg_l21a_2p95>;
	vqmmc-supply = <&vddpx_2>;

	cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
	};

	&uart9 {
	status = "okay";
	};

	&ufs_mem_hc {
	status = "okay";

	reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;

	vcc-supply = <&vreg_l20a_2p95>;
	vcc-max-microamp = <600000>;
	};

	&ufs_mem_phy {
	status = "okay";

	vdda-phy-supply = <&vdda_ufs1_core>;
	vdda-pll-supply = <&vdda_ufs1_1p2>;
	};

	&usb_1 {
	status = "okay";
	};

	&usb_1_dwc3 {
	/* Until we have Type C hooked up we'll force this as peripheral. */
	dr_mode = "peripheral";
	};

	&usb_1_hsphy {
	status = "okay";

	vdd-supply = <&vdda_usb1_ss_core>;
	vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
	vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;

	qcom,imp-res-offset-value = <8>;
	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
	qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
	qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
	};

	&usb_1_qmpphy {
	status = "okay";

	vdda-phy-supply = <&vdda_usb1_ss_1p2>;
	vdda-pll-supply = <&vdda_usb1_ss_core>;
	};

	&usb_2 {
	status = "okay";
	};

	&usb_2_dwc3 {
	/*
	* Though the USB block on SDM845 can support host, there's no vbus
	* signal for this port on MTP. Thus (unless you have a non-compliant
	* hub that works without vbus) the only sensible thing is to force
	* peripheral mode.
	*/
	dr_mode = "peripheral";
	};

	&usb_2_hsphy {
	status = "okay";

	vdd-supply = <&vdda_usb2_ss_core>;
	vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
	vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;

	qcom,imp-res-offset-value = <8>;
	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
	};

	&usb_2_qmpphy {
	status = "okay";

	vdda-phy-supply = <&vdda_usb2_ss_1p2>;
	vdda-pll-supply = <&vdda_usb2_ss_core>;
	};

	&wifi {
	status = "okay";
	vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
	vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
	vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
	vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
	};

	/* PINCTRL - additions to nodes defined in sdm845.dtsi */

	&qup_i2c10_default {
	pinconf {
	pins = "gpio55", "gpio56";
	drive-strength = <2>;
	bias-disable;
	};
	};

	&qup_uart9_default {
	pinconf-tx {
	pins = "gpio4";
	drive-strength = <2>;
	bias-disable;
	};

	pinconf-rx {
	pins = "gpio5";
	drive-strength = <2>;
	bias-pull-up;
	};
	};

	&tlmm {
	gpio-reserved-ranges = <0 4>, <81 4>;

	sdc2_clk: sdc2-clk {
	pinconf {
	pins = "sdc2_clk";
	bias-disable;

	/*
	* It seems that mmc_test reports errors if drive
	* strength is not 16 on clk, cmd, and data pins.
	*/
	drive-strength = <16>;
	};
	};

	sdc2_cmd: sdc2-cmd {
	pinconf {
	pins = "sdc2_cmd";
	bias-pull-up;
	drive-strength = <16>;
	};
	};

	sdc2_data: sdc2-data {
	pinconf {
	pins = "sdc2_data";
	bias-pull-up;
	drive-strength = <16>;
	};
	};

	sd_card_det_n: sd-card-det-n {
	pinmux {
	pins = "gpio126";
	function = "gpio";
	};

	pinconf {
	pins = "gpio126";
	bias-pull-up;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/qcom/sdm845.dtsi b/sys/gnu/dts/arm64/qcom/sdm845.dtsi
	index d42302b8889b..8f926b5234d4 100644
	--- a/sys/gnu/dts/arm64/qcom/sdm845.dtsi
	+++ b/sys/gnu/dts/arm64/qcom/sdm845.dtsi
	@@ -1,3865 +1,4497 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* SDM845 SoC device tree source
	*
	* Copyright (c) 2018, The Linux Foundation. All rights reserved.
	*/

	#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
	#include <dt-bindings/clock/qcom,gcc-sdm845.h>
	#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
	#include <dt-bindings/clock/qcom,lpass-sdm845.h>
	#include <dt-bindings/clock/qcom,rpmh.h>
	#include <dt-bindings/clock/qcom,videocc-sdm845.h>
	#include <dt-bindings/interconnect/qcom,sdm845.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/phy/phy-qcom-qusb2.h>
	#include <dt-bindings/power/qcom-rpmpd.h>
	#include <dt-bindings/reset/qcom,sdm845-aoss.h>
	#include <dt-bindings/reset/qcom,sdm845-pdc.h>
	+#include <dt-bindings/soc/qcom,apr.h>
	#include <dt-bindings/soc/qcom,rpmh-rsc.h>
	#include <dt-bindings/clock/qcom,gcc-sdm845.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	i2c6 = &i2c6;
	i2c7 = &i2c7;
	i2c8 = &i2c8;
	i2c9 = &i2c9;
	i2c10 = &i2c10;
	i2c11 = &i2c11;
	i2c12 = &i2c12;
	i2c13 = &i2c13;
	i2c14 = &i2c14;
	i2c15 = &i2c15;
	spi0 = &spi0;
	spi1 = &spi1;
	spi2 = &spi2;
	spi3 = &spi3;
	spi4 = &spi4;
	spi5 = &spi5;
	spi6 = &spi6;
	spi7 = &spi7;
	spi8 = &spi8;
	spi9 = &spi9;
	spi10 = &spi10;
	spi11 = &spi11;
	spi12 = &spi12;
	spi13 = &spi13;
	spi14 = &spi14;
	spi15 = &spi15;
	};

	chosen { };

	memory@80000000 {
	device_type = "memory";
	/* We expect the bootloader to fill in the size */
	reg = <0 0x80000000 0 0>;
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	hyp_mem: memory@85700000 {
	reg = <0 0x85700000 0 0x600000>;
	no-map;
	};

	xbl_mem: memory@85e00000 {
	reg = <0 0x85e00000 0 0x100000>;
	no-map;
	};

	aop_mem: memory@85fc0000 {
	reg = <0 0x85fc0000 0 0x20000>;
	no-map;
	};

	aop_cmd_db_mem: memory@85fe0000 {
	compatible = "qcom,cmd-db";
	reg = <0x0 0x85fe0000 0 0x20000>;
	no-map;
	};

	smem_mem: memory@86000000 {
	reg = <0x0 0x86000000 0 0x200000>;
	no-map;
	};

	tz_mem: memory@86200000 {
	reg = <0 0x86200000 0 0x2d00000>;
	no-map;
	};

	rmtfs_mem: memory@88f00000 {
	compatible = "qcom,rmtfs-mem";
	reg = <0 0x88f00000 0 0x200000>;
	no-map;

	qcom,client-id = <1>;
	qcom,vmid = <15>;
	};

	qseecom_mem: memory@8ab00000 {
	reg = <0 0x8ab00000 0 0x1400000>;
	no-map;
	};

	camera_mem: memory@8bf00000 {
	reg = <0 0x8bf00000 0 0x500000>;
	no-map;
	};

	ipa_fw_mem: memory@8c400000 {
	reg = <0 0x8c400000 0 0x10000>;
	no-map;
	};

	ipa_gsi_mem: memory@8c410000 {
	reg = <0 0x8c410000 0 0x5000>;
	no-map;
	};

	gpu_mem: memory@8c415000 {
	reg = <0 0x8c415000 0 0x2000>;
	no-map;
	};

	adsp_mem: memory@8c500000 {
	reg = <0 0x8c500000 0 0x1a00000>;
	no-map;
	};

	wlan_msa_mem: memory@8df00000 {
	reg = <0 0x8df00000 0 0x100000>;
	no-map;
	};

	mpss_region: memory@8e000000 {
	reg = <0 0x8e000000 0 0x7800000>;
	no-map;
	};

	venus_mem: memory@95800000 {
	reg = <0 0x95800000 0 0x500000>;
	no-map;
	};

	cdsp_mem: memory@95d00000 {
	reg = <0 0x95d00000 0 0x800000>;
	no-map;
	};

	mba_region: memory@96500000 {
	reg = <0 0x96500000 0 0x200000>;
	no-map;
	};

	slpi_mem: memory@96700000 {
	reg = <0 0x96700000 0 0x1400000>;
	no-map;
	};

	spss_mem: memory@97b00000 {
	reg = <0 0x97b00000 0 0x100000>;
	no-map;
	};
	};

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	CPU0: cpu@0 {
	device_type = "cpu";
	compatible = "qcom,kryo385";
	reg = <0x0 0x0>;
	enable-method = "psci";
	cpu-idle-states = <&LITTLE_CPU_SLEEP_0
	&LITTLE_CPU_SLEEP_1
	&CLUSTER_SLEEP_0>;
	capacity-dmips-mhz = <607>;
	dynamic-power-coefficient = <100>;
	qcom,freq-domain = <&cpufreq_hw 0>;
	#cooling-cells = <2>;
	next-level-cache = <&L2_0>;
	L2_0: l2-cache {
	compatible = "cache";
	next-level-cache = <&L3_0>;
	L3_0: l3-cache {
	compatible = "cache";
	};
	};
	};

	CPU1: cpu@100 {
	device_type = "cpu";
	compatible = "qcom,kryo385";
	reg = <0x0 0x100>;
	enable-method = "psci";
	cpu-idle-states = <&LITTLE_CPU_SLEEP_0
	&LITTLE_CPU_SLEEP_1
	&CLUSTER_SLEEP_0>;
	capacity-dmips-mhz = <607>;
	dynamic-power-coefficient = <100>;
	qcom,freq-domain = <&cpufreq_hw 0>;
	#cooling-cells = <2>;
	next-level-cache = <&L2_100>;
	L2_100: l2-cache {
	compatible = "cache";
	next-level-cache = <&L3_0>;
	};
	};

	CPU2: cpu@200 {
	device_type = "cpu";
	compatible = "qcom,kryo385";
	reg = <0x0 0x200>;
	enable-method = "psci";
	cpu-idle-states = <&LITTLE_CPU_SLEEP_0
	&LITTLE_CPU_SLEEP_1
	&CLUSTER_SLEEP_0>;
	capacity-dmips-mhz = <607>;
	dynamic-power-coefficient = <100>;
	qcom,freq-domain = <&cpufreq_hw 0>;
	#cooling-cells = <2>;
	next-level-cache = <&L2_200>;
	L2_200: l2-cache {
	compatible = "cache";
	next-level-cache = <&L3_0>;
	};
	};

	CPU3: cpu@300 {
	device_type = "cpu";
	compatible = "qcom,kryo385";
	reg = <0x0 0x300>;
	enable-method = "psci";
	cpu-idle-states = <&LITTLE_CPU_SLEEP_0
	&LITTLE_CPU_SLEEP_1
	&CLUSTER_SLEEP_0>;
	capacity-dmips-mhz = <607>;
	dynamic-power-coefficient = <100>;
	qcom,freq-domain = <&cpufreq_hw 0>;
	#cooling-cells = <2>;
	next-level-cache = <&L2_300>;
	L2_300: l2-cache {
	compatible = "cache";
	next-level-cache = <&L3_0>;
	};
	};

	CPU4: cpu@400 {
	device_type = "cpu";
	compatible = "qcom,kryo385";
	reg = <0x0 0x400>;
	enable-method = "psci";
	capacity-dmips-mhz = <1024>;
	cpu-idle-states = <&BIG_CPU_SLEEP_0
	&BIG_CPU_SLEEP_1
	&CLUSTER_SLEEP_0>;
	dynamic-power-coefficient = <396>;
	qcom,freq-domain = <&cpufreq_hw 1>;
	#cooling-cells = <2>;
	next-level-cache = <&L2_400>;
	L2_400: l2-cache {
	compatible = "cache";
	next-level-cache = <&L3_0>;
	};
	};

	CPU5: cpu@500 {
	device_type = "cpu";
	compatible = "qcom,kryo385";
	reg = <0x0 0x500>;
	enable-method = "psci";
	capacity-dmips-mhz = <1024>;
	cpu-idle-states = <&BIG_CPU_SLEEP_0
	&BIG_CPU_SLEEP_1
	&CLUSTER_SLEEP_0>;
	dynamic-power-coefficient = <396>;
	qcom,freq-domain = <&cpufreq_hw 1>;
	#cooling-cells = <2>;
	next-level-cache = <&L2_500>;
	L2_500: l2-cache {
	compatible = "cache";
	next-level-cache = <&L3_0>;
	};
	};

	CPU6: cpu@600 {
	device_type = "cpu";
	compatible = "qcom,kryo385";
	reg = <0x0 0x600>;
	enable-method = "psci";
	capacity-dmips-mhz = <1024>;
	cpu-idle-states = <&BIG_CPU_SLEEP_0
	&BIG_CPU_SLEEP_1
	&CLUSTER_SLEEP_0>;
	dynamic-power-coefficient = <396>;
	qcom,freq-domain = <&cpufreq_hw 1>;
	#cooling-cells = <2>;
	next-level-cache = <&L2_600>;
	L2_600: l2-cache {
	compatible = "cache";
	next-level-cache = <&L3_0>;
	};
	};

	CPU7: cpu@700 {
	device_type = "cpu";
	compatible = "qcom,kryo385";
	reg = <0x0 0x700>;
	enable-method = "psci";
	capacity-dmips-mhz = <1024>;
	cpu-idle-states = <&BIG_CPU_SLEEP_0
	&BIG_CPU_SLEEP_1
	&CLUSTER_SLEEP_0>;
	dynamic-power-coefficient = <396>;
	qcom,freq-domain = <&cpufreq_hw 1>;
	#cooling-cells = <2>;
	next-level-cache = <&L2_700>;
	L2_700: l2-cache {
	compatible = "cache";
	next-level-cache = <&L3_0>;
	};
	};

	cpu-map {
	cluster0 {
	core0 {
	cpu = <&CPU0>;
	};

	core1 {
	cpu = <&CPU1>;
	};

	core2 {
	cpu = <&CPU2>;
	};

	core3 {
	cpu = <&CPU3>;
	};

	core4 {
	cpu = <&CPU4>;
	};

	core5 {
	cpu = <&CPU5>;
	};

	core6 {
	cpu = <&CPU6>;
	};

	core7 {
	cpu = <&CPU7>;
	};
	};
	};

	idle-states {
	entry-method = "psci";

	LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
	compatible = "arm,idle-state";
	idle-state-name = "little-power-down";
	arm,psci-suspend-param = <0x40000003>;
	entry-latency-us = <350>;
	exit-latency-us = <461>;
	min-residency-us = <1890>;
	local-timer-stop;
	};

	LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
	compatible = "arm,idle-state";
	idle-state-name = "little-rail-power-down";
	arm,psci-suspend-param = <0x40000004>;
	entry-latency-us = <360>;
	exit-latency-us = <531>;
	min-residency-us = <3934>;
	local-timer-stop;
	};

	BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
	compatible = "arm,idle-state";
	idle-state-name = "big-power-down";
	arm,psci-suspend-param = <0x40000003>;
	entry-latency-us = <264>;
	exit-latency-us = <621>;
	min-residency-us = <952>;
	local-timer-stop;
	};

	BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
	compatible = "arm,idle-state";
	idle-state-name = "big-rail-power-down";
	arm,psci-suspend-param = <0x40000004>;
	entry-latency-us = <702>;
	exit-latency-us = <1061>;
	min-residency-us = <4488>;
	local-timer-stop;
	};

	CLUSTER_SLEEP_0: cluster-sleep-0 {
	compatible = "arm,idle-state";
	idle-state-name = "cluster-power-down";
	arm,psci-suspend-param = <0x400000F4>;
	entry-latency-us = <3263>;
	exit-latency-us = <6562>;
	min-residency-us = <9987>;
	local-timer-stop;
	};
	};
	};

	pmu {
	compatible = "arm,armv8-pmuv3";
	interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
	};

	clocks {
	xo_board: xo-board {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <38400000>;
	clock-output-names = "xo_board";
	};

	sleep_clk: sleep-clk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32764>;
	};
	};

	firmware {
	scm {
	compatible = "qcom,scm-sdm845", "qcom,scm";
	};
	};

	adsp_pas: remoteproc-adsp {
	compatible = "qcom,sdm845-adsp-pas";

	interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
	<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "wdog", "fatal", "ready",
	"handover", "stop-ack";

	clocks = <&rpmhcc RPMH_CXO_CLK>;
	clock-names = "xo";

	memory-region = <&adsp_mem>;

	qcom,smem-states = <&adsp_smp2p_out 0>;
	qcom,smem-state-names = "stop";

	status = "disabled";

	glink-edge {
	interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
	label = "lpass";
	qcom,remote-pid = <2>;
	mboxes = <&apss_shared 8>;
	+
	+ apr {
	+ compatible = "qcom,apr-v2";
	+ qcom,glink-channels = "apr_audio_svc";
	+ qcom,apr-domain = <APR_DOMAIN_ADSP>;
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ qcom,intents = <512 20>;
	+
	+ apr-service@3 {
	+ reg = <APR_SVC_ADSP_CORE>;
	+ compatible = "qcom,q6core";
	+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
	+ };
	+
	+ q6afe: apr-service@4 {
	+ compatible = "qcom,q6afe";
	+ reg = <APR_SVC_AFE>;
	+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
	+ q6afedai: dais {
	+ compatible = "qcom,q6afe-dais";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ #sound-dai-cells = <1>;
	+ };
	+ };
	+
	+ q6asm: apr-service@7 {
	+ compatible = "qcom,q6asm";
	+ reg = <APR_SVC_ASM>;
	+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
	+ q6asmdai: dais {
	+ compatible = "qcom,q6asm-dais";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ #sound-dai-cells = <1>;
	+ iommus = <&apps_smmu 0x1821 0x0>;
	+ };
	+ };
	+
	+ q6adm: apr-service@8 {
	+ compatible = "qcom,q6adm";
	+ reg = <APR_SVC_ADM>;
	+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
	+ q6routing: routing {
	+ compatible = "qcom,q6adm-routing";
	+ #sound-dai-cells = <0>;
	+ };
	+ };
	+ };
	+
	fastrpc {
	compatible = "qcom,fastrpc";
	qcom,glink-channels = "fastrpcglink-apps-dsp";
	label = "adsp";
	#address-cells = <1>;
	#size-cells = <0>;

	compute-cb@3 {
	compatible = "qcom,fastrpc-compute-cb";
	reg = <3>;
	iommus = <&apps_smmu 0x1823 0x0>;
	};

	compute-cb@4 {
	compatible = "qcom,fastrpc-compute-cb";
	reg = <4>;
	iommus = <&apps_smmu 0x1824 0x0>;
	};
	};
	};
	};

	cdsp_pas: remoteproc-cdsp {
	compatible = "qcom,sdm845-cdsp-pas";

	interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
	<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	<&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "wdog", "fatal", "ready",
	"handover", "stop-ack";

	clocks = <&rpmhcc RPMH_CXO_CLK>;
	clock-names = "xo";

	memory-region = <&cdsp_mem>;

	qcom,smem-states = <&cdsp_smp2p_out 0>;
	qcom,smem-state-names = "stop";

	status = "disabled";

	glink-edge {
	interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
	label = "turing";
	qcom,remote-pid = <5>;
	mboxes = <&apss_shared 4>;
	fastrpc {
	compatible = "qcom,fastrpc";
	qcom,glink-channels = "fastrpcglink-apps-dsp";
	label = "cdsp";
	#address-cells = <1>;
	#size-cells = <0>;

	compute-cb@1 {
	compatible = "qcom,fastrpc-compute-cb";
	reg = <1>;
	iommus = <&apps_smmu 0x1401 0x30>;
	};

	compute-cb@2 {
	compatible = "qcom,fastrpc-compute-cb";
	reg = <2>;
	iommus = <&apps_smmu 0x1402 0x30>;
	};

	compute-cb@3 {
	compatible = "qcom,fastrpc-compute-cb";
	reg = <3>;
	iommus = <&apps_smmu 0x1403 0x30>;
	};

	compute-cb@4 {
	compatible = "qcom,fastrpc-compute-cb";
	reg = <4>;
	iommus = <&apps_smmu 0x1404 0x30>;
	};

	compute-cb@5 {
	compatible = "qcom,fastrpc-compute-cb";
	reg = <5>;
	iommus = <&apps_smmu 0x1405 0x30>;
	};

	compute-cb@6 {
	compatible = "qcom,fastrpc-compute-cb";
	reg = <6>;
	iommus = <&apps_smmu 0x1406 0x30>;
	};

	compute-cb@7 {
	compatible = "qcom,fastrpc-compute-cb";
	reg = <7>;
	iommus = <&apps_smmu 0x1407 0x30>;
	};

	compute-cb@8 {
	compatible = "qcom,fastrpc-compute-cb";
	reg = <8>;
	iommus = <&apps_smmu 0x1408 0x30>;
	};
	};
	};
	};

	tcsr_mutex: hwlock {
	compatible = "qcom,tcsr-mutex";
	syscon = <&tcsr_mutex_regs 0 0x1000>;
	#hwlock-cells = <1>;
	};

	smem {
	compatible = "qcom,smem";
	memory-region = <&smem_mem>;
	hwlocks = <&tcsr_mutex 3>;
	};

	smp2p-cdsp {
	compatible = "qcom,smp2p";
	qcom,smem = <94>, <432>;

	interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;

	mboxes = <&apss_shared 6>;

	qcom,local-pid = <0>;
	qcom,remote-pid = <5>;

	cdsp_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};

	cdsp_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";

	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	smp2p-lpass {
	compatible = "qcom,smp2p";
	qcom,smem = <443>, <429>;

	interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;

	mboxes = <&apss_shared 10>;

	qcom,local-pid = <0>;
	qcom,remote-pid = <2>;

	adsp_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};

	adsp_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";

	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	smp2p-mpss {
	compatible = "qcom,smp2p";
	qcom,smem = <435>, <428>;
	interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
	mboxes = <&apss_shared 14>;
	qcom,local-pid = <0>;
	qcom,remote-pid = <1>;

	modem_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};

	modem_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	+
	+ ipa_smp2p_out: ipa-ap-to-modem {
	+ qcom,entry-name = "ipa";
	+ #qcom,smem-state-cells = <1>;
	+ };
	+
	+ ipa_smp2p_in: ipa-modem-to-ap {
	+ qcom,entry-name = "ipa";
	+ interrupt-controller;
	+ #interrupt-cells = <2>;
	+ };
	};

	smp2p-slpi {
	compatible = "qcom,smp2p";
	qcom,smem = <481>, <430>;
	interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
	mboxes = <&apss_shared 26>;
	qcom,local-pid = <0>;
	qcom,remote-pid = <3>;

	slpi_smp2p_out: master-kernel {
	qcom,entry-name = "master-kernel";
	#qcom,smem-state-cells = <1>;
	};

	slpi_smp2p_in: slave-kernel {
	qcom,entry-name = "slave-kernel";
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	soc: soc@0 {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0 0 0 0 0x10 0>;
	dma-ranges = <0 0 0 0 0x10 0>;
	compatible = "simple-bus";

	gcc: clock-controller@100000 {
	compatible = "qcom,gcc-sdm845";
	reg = <0 0x00100000 0 0x1f0000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;
	};

	qfprom@784000 {
	compatible = "qcom,qfprom";
	reg = <0 0x00784000 0 0x8ff>;
	#address-cells = <1>;
	#size-cells = <1>;

	qusb2p_hstx_trim: hstx-trim-primary@1eb {
	reg = <0x1eb 0x1>;
	bits = <1 4>;
	};

	qusb2s_hstx_trim: hstx-trim-secondary@1eb {
	reg = <0x1eb 0x2>;
	bits = <6 4>;
	};
	};

	rng: rng@793000 {
	compatible = "qcom,prng-ee";
	reg = <0 0x00793000 0 0x1000>;
	clocks = <&gcc GCC_PRNG_AHB_CLK>;
	clock-names = "core";
	};

	qupv3_id_0: geniqup@8c0000 {
	compatible = "qcom,geni-se-qup";
	reg = <0 0x008c0000 0 0x6000>;
	clock-names = "m-ahb", "s-ahb";
	clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
	<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "disabled";

	i2c0: i2c@880000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00880000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c0_default>;
	interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi0: spi@880000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00880000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi0_default>;
	interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart0: serial@880000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00880000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart0_default>;
	interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c1: i2c@884000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00884000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c1_default>;
	interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi1: spi@884000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00884000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi1_default>;
	interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart1: serial@884000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00884000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart1_default>;
	interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c2: i2c@888000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00888000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c2_default>;
	interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi2: spi@888000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00888000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi2_default>;
	interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart2: serial@888000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00888000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart2_default>;
	interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c3: i2c@88c000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x0088c000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c3_default>;
	interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi3: spi@88c000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x0088c000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi3_default>;
	interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart3: serial@88c000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x0088c000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart3_default>;
	interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c4: i2c@890000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00890000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c4_default>;
	interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi4: spi@890000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00890000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi4_default>;
	interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart4: serial@890000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00890000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart4_default>;
	interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c5: i2c@894000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00894000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c5_default>;
	interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi5: spi@894000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00894000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi5_default>;
	interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart5: serial@894000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00894000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart5_default>;
	interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c6: i2c@898000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00898000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c6_default>;
	interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi6: spi@898000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00898000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi6_default>;
	interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart6: serial@898000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00898000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart6_default>;
	interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c7: i2c@89c000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x0089c000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c7_default>;
	interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi7: spi@89c000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x0089c000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi7_default>;
	interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart7: serial@89c000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x0089c000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart7_default>;
	interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	qupv3_id_1: geniqup@ac0000 {
	compatible = "qcom,geni-se-qup";
	reg = <0 0x00ac0000 0 0x6000>;
	clock-names = "m-ahb", "s-ahb";
	clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
	<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "disabled";

	i2c8: i2c@a80000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00a80000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c8_default>;
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi8: spi@a80000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00a80000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi8_default>;
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart8: serial@a80000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00a80000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart8_default>;
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c9: i2c@a84000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00a84000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c9_default>;
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi9: spi@a84000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00a84000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi9_default>;
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart9: serial@a84000 {
	compatible = "qcom,geni-debug-uart";
	reg = <0 0x00a84000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart9_default>;
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c10: i2c@a88000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00a88000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c10_default>;
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi10: spi@a88000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00a88000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi10_default>;
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart10: serial@a88000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00a88000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart10_default>;
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c11: i2c@a8c000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00a8c000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c11_default>;
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi11: spi@a8c000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00a8c000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi11_default>;
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart11: serial@a8c000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00a8c000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart11_default>;
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c12: i2c@a90000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00a90000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c12_default>;
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi12: spi@a90000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00a90000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi12_default>;
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart12: serial@a90000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00a90000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart12_default>;
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c13: i2c@a94000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00a94000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c13_default>;
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi13: spi@a94000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00a94000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi13_default>;
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart13: serial@a94000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00a94000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart13_default>;
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c14: i2c@a98000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00a98000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c14_default>;
	interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi14: spi@a98000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00a98000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi14_default>;
	interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart14: serial@a98000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00a98000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart14_default>;
	interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	i2c15: i2c@a9c000 {
	compatible = "qcom,geni-i2c";
	reg = <0 0x00a9c000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_i2c15_default>;
	interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi15: spi@a9c000 {
	compatible = "qcom,geni-spi";
	reg = <0 0x00a9c000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_spi15_default>;
	interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart15: serial@a9c000 {
	compatible = "qcom,geni-uart";
	reg = <0 0x00a9c000 0 0x4000>;
	clock-names = "se";
	clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
	pinctrl-names = "default";
	pinctrl-0 = <&qup_uart15_default>;
	interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};

	system-cache-controller@1100000 {
	compatible = "qcom,sdm845-llcc";
	reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
	reg-names = "llcc_base", "llcc_broadcast_base";
	interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
	};

	+ pcie0: pci@1c00000 {
	+ compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
	+ reg = <0 0x01c00000 0 0x2000>,
	+ <0 0x60000000 0 0xf1d>,
	+ <0 0x60000f20 0 0xa8>,
	+ <0 0x60100000 0 0x100000>;
	+ reg-names = "parf", "dbi", "elbi", "config";
	+ device_type = "pci";
	+ linux,pci-domain = <0>;
	+ bus-range = <0x00 0xff>;
	+ num-lanes = <1>;
	+
	+ #address-cells = <3>;
	+ #size-cells = <2>;
	+
	+ ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
	+ <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
	+
	+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
	+ interrupt-names = "msi";
	+ #interrupt-cells = <1>;
	+ interrupt-map-mask = <0 0 0 0x7>;
	+ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	+ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	+ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	+ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
	+
	+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
	+ <&gcc GCC_PCIE_0_AUX_CLK>,
	+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
	+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
	+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
	+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
	+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
	+ clock-names = "pipe",
	+ "aux",
	+ "cfg",
	+ "bus_master",
	+ "bus_slave",
	+ "slave_q2a",
	+ "tbu";
	+
	+ iommus = <&apps_smmu 0x1c10 0xf>;
	+ iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
	+ <0x100 &apps_smmu 0x1c11 0x1>,
	+ <0x200 &apps_smmu 0x1c12 0x1>,
	+ <0x300 &apps_smmu 0x1c13 0x1>,
	+ <0x400 &apps_smmu 0x1c14 0x1>,
	+ <0x500 &apps_smmu 0x1c15 0x1>,
	+ <0x600 &apps_smmu 0x1c16 0x1>,
	+ <0x700 &apps_smmu 0x1c17 0x1>,
	+ <0x800 &apps_smmu 0x1c18 0x1>,
	+ <0x900 &apps_smmu 0x1c19 0x1>,
	+ <0xa00 &apps_smmu 0x1c1a 0x1>,
	+ <0xb00 &apps_smmu 0x1c1b 0x1>,
	+ <0xc00 &apps_smmu 0x1c1c 0x1>,
	+ <0xd00 &apps_smmu 0x1c1d 0x1>,
	+ <0xe00 &apps_smmu 0x1c1e 0x1>,
	+ <0xf00 &apps_smmu 0x1c1f 0x1>;
	+
	+ resets = <&gcc GCC_PCIE_0_BCR>;
	+ reset-names = "pci";
	+
	+ power-domains = <&gcc PCIE_0_GDSC>;
	+
	+ phys = <&pcie0_lane>;
	+ phy-names = "pciephy";
	+
	+ status = "disabled";
	+ };
	+
	+ pcie0_phy: phy@1c06000 {
	+ compatible = "qcom,sdm845-qmp-pcie-phy";
	+ reg = <0 0x01c06000 0 0x18c>;
	+ #address-cells = <2>;
	+ #size-cells = <2>;
	+ ranges;
	+ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
	+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
	+ <&gcc GCC_PCIE_0_CLKREF_CLK>,
	+ <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
	+ clock-names = "aux", "cfg_ahb", "ref", "refgen";
	+
	+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
	+ reset-names = "phy";
	+
	+ assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
	+ assigned-clock-rates = <100000000>;
	+
	+ status = "disabled";
	+
	+ pcie0_lane: lanes@1c06200 {
	+ reg = <0 0x01c06200 0 0x128>,
	+ <0 0x01c06400 0 0x1fc>,
	+ <0 0x01c06800 0 0x218>,
	+ <0 0x01c06600 0 0x70>;
	+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
	+ clock-names = "pipe0";
	+
	+ #phy-cells = <0>;
	+ clock-output-names = "pcie_0_pipe_clk";
	+ };
	+ };
	+
	+ pcie1: pci@1c08000 {
	+ compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
	+ reg = <0 0x01c08000 0 0x2000>,
	+ <0 0x40000000 0 0xf1d>,
	+ <0 0x40000f20 0 0xa8>,
	+ <0 0x40100000 0 0x100000>;
	+ reg-names = "parf", "dbi", "elbi", "config";
	+ device_type = "pci";
	+ linux,pci-domain = <1>;
	+ bus-range = <0x00 0xff>;
	+ num-lanes = <1>;
	+
	+ #address-cells = <3>;
	+ #size-cells = <2>;
	+
	+ ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
	+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
	+
	+ interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
	+ interrupt-names = "msi";
	+ #interrupt-cells = <1>;
	+ interrupt-map-mask = <0 0 0 0x7>;
	+ interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	+ <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	+ <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	+ <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
	+
	+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
	+ <&gcc GCC_PCIE_1_AUX_CLK>,
	+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
	+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
	+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
	+ <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
	+ <&gcc GCC_PCIE_1_CLKREF_CLK>,
	+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
	+ clock-names = "pipe",
	+ "aux",
	+ "cfg",
	+ "bus_master",
	+ "bus_slave",
	+ "slave_q2a",
	+ "ref",
	+ "tbu";
	+
	+ assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
	+ assigned-clock-rates = <19200000>;
	+
	+ iommus = <&apps_smmu 0x1c00 0xf>;
	+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
	+ <0x100 &apps_smmu 0x1c01 0x1>,
	+ <0x200 &apps_smmu 0x1c02 0x1>,
	+ <0x300 &apps_smmu 0x1c03 0x1>,
	+ <0x400 &apps_smmu 0x1c04 0x1>,
	+ <0x500 &apps_smmu 0x1c05 0x1>,
	+ <0x600 &apps_smmu 0x1c06 0x1>,
	+ <0x700 &apps_smmu 0x1c07 0x1>,
	+ <0x800 &apps_smmu 0x1c08 0x1>,
	+ <0x900 &apps_smmu 0x1c09 0x1>,
	+ <0xa00 &apps_smmu 0x1c0a 0x1>,
	+ <0xb00 &apps_smmu 0x1c0b 0x1>,
	+ <0xc00 &apps_smmu 0x1c0c 0x1>,
	+ <0xd00 &apps_smmu 0x1c0d 0x1>,
	+ <0xe00 &apps_smmu 0x1c0e 0x1>,
	+ <0xf00 &apps_smmu 0x1c0f 0x1>;
	+
	+ resets = <&gcc GCC_PCIE_1_BCR>;
	+ reset-names = "pci";
	+
	+ power-domains = <&gcc PCIE_1_GDSC>;
	+
	+ phys = <&pcie1_lane>;
	+ phy-names = "pciephy";
	+
	+ status = "disabled";
	+ };
	+
	+ pcie1_phy: phy@1c0a000 {
	+ compatible = "qcom,sdm845-qhp-pcie-phy";
	+ reg = <0 0x01c0a000 0 0x800>;
	+ #address-cells = <2>;
	+ #size-cells = <2>;
	+ ranges;
	+ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
	+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
	+ <&gcc GCC_PCIE_1_CLKREF_CLK>,
	+ <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
	+ clock-names = "aux", "cfg_ahb", "ref", "refgen";
	+
	+ resets = <&gcc GCC_PCIE_1_PHY_BCR>;
	+ reset-names = "phy";
	+
	+ assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
	+ assigned-clock-rates = <100000000>;
	+
	+ status = "disabled";
	+
	+ pcie1_lane: lanes@1c06200 {
	+ reg = <0 0x01c0a800 0 0x800>,
	+ <0 0x01c0a800 0 0x800>,
	+ <0 0x01c0b800 0 0x400>;
	+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
	+ clock-names = "pipe0";
	+
	+ #phy-cells = <0>;
	+ clock-output-names = "pcie_1_pipe_clk";
	+ };
	+ };
	+
	+ mem_noc: interconnect@1380000 {
	+ compatible = "qcom,sdm845-mem-noc";
	+ reg = <0 0x01380000 0 0x27200>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	+ dc_noc: interconnect@14e0000 {
	+ compatible = "qcom,sdm845-dc-noc";
	+ reg = <0 0x014e0000 0 0x400>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	+ config_noc: interconnect@1500000 {
	+ compatible = "qcom,sdm845-config-noc";
	+ reg = <0 0x01500000 0 0x5080>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	+ system_noc: interconnect@1620000 {
	+ compatible = "qcom,sdm845-system-noc";
	+ reg = <0 0x01620000 0 0x18080>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	+ aggre1_noc: interconnect@16e0000 {
	+ compatible = "qcom,sdm845-aggre1-noc";
	+ reg = <0 0x016e0000 0 0x15080>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	+ aggre2_noc: interconnect@1700000 {
	+ compatible = "qcom,sdm845-aggre2-noc";
	+ reg = <0 0x01700000 0 0x1f300>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	+ mmss_noc: interconnect@1740000 {
	+ compatible = "qcom,sdm845-mmss-noc";
	+ reg = <0 0x01740000 0 0x1c100>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	ufs_mem_hc: ufshc@1d84000 {
	compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
	"jedec,ufs-2.0";
	reg = <0 0x01d84000 0 0x2500>;
	interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
	phys = <&ufs_mem_phy_lanes>;
	phy-names = "ufsphy";
	lanes-per-direction = <2>;
	power-domains = <&gcc UFS_PHY_GDSC>;
	#reset-cells = <1>;
	resets = <&gcc GCC_UFS_PHY_BCR>;
	reset-names = "rst";

	iommus = <&apps_smmu 0x100 0xf>;

	clock-names =
	"core_clk",
	"bus_aggr_clk",
	"iface_clk",
	"core_clk_unipro",
	"ref_clk",
	"tx_lane0_sync_clk",
	"rx_lane0_sync_clk",
	"rx_lane1_sync_clk";
	clocks =
	<&gcc GCC_UFS_PHY_AXI_CLK>,
	<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
	<&gcc GCC_UFS_PHY_AHB_CLK>,
	<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
	<&rpmhcc RPMH_CXO_CLK>,
	<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
	<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
	<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
	freq-table-hz =
	<50000000 200000000>,
	<0 0>,
	<0 0>,
	<37500000 150000000>,
	<0 0>,
	<0 0>,
	<0 0>,
	<0 0>;

	status = "disabled";
	};

	ufs_mem_phy: phy@1d87000 {
	compatible = "qcom,sdm845-qmp-ufs-phy";
	reg = <0 0x01d87000 0 0x18c>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	clock-names = "ref",
	"ref_aux";
	clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
	<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;

	resets = <&ufs_mem_hc 0>;
	reset-names = "ufsphy";
	status = "disabled";

	ufs_mem_phy_lanes: lanes@1d87400 {
	reg = <0 0x01d87400 0 0x108>,
	<0 0x01d87600 0 0x1e0>,
	<0 0x01d87c00 0 0x1dc>,
	<0 0x01d87800 0 0x108>,
	<0 0x01d87a00 0 0x1e0>;
	#phy-cells = <0>;
	};
	};

	+ ipa: ipa@1e40000 {
	+ compatible = "qcom,sdm845-ipa";
	+ reg = <0 0x1e40000 0 0x7000>,
	+ <0 0x1e47000 0 0x2000>,
	+ <0 0x1e04000 0 0x2c000>;
	+ reg-names = "ipa-reg",
	+ "ipa-shared",
	+ "gsi";
	+
	+ interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>,
	+ <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
	+ <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	+ <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
	+ interrupt-names = "ipa",
	+ "gsi",
	+ "ipa-clock-query",
	+ "ipa-setup-ready";
	+
	+ clocks = <&rpmhcc RPMH_IPA_CLK>;
	+ clock-names = "core";
	+
	+ interconnects = <&aggre2_noc MASTER_IPA &mem_noc SLAVE_EBI1>,
	+ <&aggre2_noc MASTER_IPA &system_noc SLAVE_IMEM>,
	+ <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
	+ interconnect-names = "memory",
	+ "imem",
	+ "config";
	+
	+ qcom,smem-states = <&ipa_smp2p_out 0>,
	+ <&ipa_smp2p_out 1>;
	+ qcom,smem-state-names = "ipa-clock-enabled-valid",
	+ "ipa-clock-enabled";
	+
	+ modem-remoteproc = <&mss_pil>;
	+
	+ status = "disabled";
	+ };
	+
	tcsr_mutex_regs: syscon@1f40000 {
	compatible = "syscon";
	reg = <0 0x01f40000 0 0x40000>;
	};

	tlmm: pinctrl@3400000 {
	compatible = "qcom,sdm845-pinctrl";
	reg = <0 0x03400000 0 0xc00000>;
	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&tlmm 0 0 150>;
	wakeup-parent = <&pdc_intc>;

	qspi_clk: qspi-clk {
	pinmux {
	pins = "gpio95";
	function = "qspi_clk";
	};
	};

	qspi_cs0: qspi-cs0 {
	pinmux {
	pins = "gpio90";
	function = "qspi_cs";
	};
	};

	qspi_cs1: qspi-cs1 {
	pinmux {
	pins = "gpio89";
	function = "qspi_cs";
	};
	};

	qspi_data01: qspi-data01 {
	pinmux-data {
	pins = "gpio91", "gpio92";
	function = "qspi_data";
	};
	};

	qspi_data12: qspi-data12 {
	pinmux-data {
	pins = "gpio93", "gpio94";
	function = "qspi_data";
	};
	};

	qup_i2c0_default: qup-i2c0-default {
	pinmux {
	pins = "gpio0", "gpio1";
	function = "qup0";
	};
	};

	qup_i2c1_default: qup-i2c1-default {
	pinmux {
	pins = "gpio17", "gpio18";
	function = "qup1";
	};
	};

	qup_i2c2_default: qup-i2c2-default {
	pinmux {
	pins = "gpio27", "gpio28";
	function = "qup2";
	};
	};

	qup_i2c3_default: qup-i2c3-default {
	pinmux {
	pins = "gpio41", "gpio42";
	function = "qup3";
	};
	};

	qup_i2c4_default: qup-i2c4-default {
	pinmux {
	pins = "gpio89", "gpio90";
	function = "qup4";
	};
	};

	qup_i2c5_default: qup-i2c5-default {
	pinmux {
	pins = "gpio85", "gpio86";
	function = "qup5";
	};
	};

	qup_i2c6_default: qup-i2c6-default {
	pinmux {
	pins = "gpio45", "gpio46";
	function = "qup6";
	};
	};

	qup_i2c7_default: qup-i2c7-default {
	pinmux {
	pins = "gpio93", "gpio94";
	function = "qup7";
	};
	};

	qup_i2c8_default: qup-i2c8-default {
	pinmux {
	pins = "gpio65", "gpio66";
	function = "qup8";
	};
	};

	qup_i2c9_default: qup-i2c9-default {
	pinmux {
	pins = "gpio6", "gpio7";
	function = "qup9";
	};
	};

	qup_i2c10_default: qup-i2c10-default {
	pinmux {
	pins = "gpio55", "gpio56";
	function = "qup10";
	};
	};

	qup_i2c11_default: qup-i2c11-default {
	pinmux {
	pins = "gpio31", "gpio32";
	function = "qup11";
	};
	};

	qup_i2c12_default: qup-i2c12-default {
	pinmux {
	pins = "gpio49", "gpio50";
	function = "qup12";
	};
	};

	qup_i2c13_default: qup-i2c13-default {
	pinmux {
	pins = "gpio105", "gpio106";
	function = "qup13";
	};
	};

	qup_i2c14_default: qup-i2c14-default {
	pinmux {
	pins = "gpio33", "gpio34";
	function = "qup14";
	};
	};

	qup_i2c15_default: qup-i2c15-default {
	pinmux {
	pins = "gpio81", "gpio82";
	function = "qup15";
	};
	};

	qup_spi0_default: qup-spi0-default {
	pinmux {
	pins = "gpio0", "gpio1",
	"gpio2", "gpio3";
	function = "qup0";
	};
	};

	qup_spi1_default: qup-spi1-default {
	pinmux {
	pins = "gpio17", "gpio18",
	"gpio19", "gpio20";
	function = "qup1";
	};
	};

	qup_spi2_default: qup-spi2-default {
	pinmux {
	pins = "gpio27", "gpio28",
	"gpio29", "gpio30";
	function = "qup2";
	};
	};

	qup_spi3_default: qup-spi3-default {
	pinmux {
	pins = "gpio41", "gpio42",
	"gpio43", "gpio44";
	function = "qup3";
	};
	};

	qup_spi4_default: qup-spi4-default {
	pinmux {
	pins = "gpio89", "gpio90",
	"gpio91", "gpio92";
	function = "qup4";
	};
	};

	qup_spi5_default: qup-spi5-default {
	pinmux {
	pins = "gpio85", "gpio86",
	"gpio87", "gpio88";
	function = "qup5";
	};
	};

	qup_spi6_default: qup-spi6-default {
	pinmux {
	pins = "gpio45", "gpio46",
	"gpio47", "gpio48";
	function = "qup6";
	};
	};

	qup_spi7_default: qup-spi7-default {
	pinmux {
	pins = "gpio93", "gpio94",
	"gpio95", "gpio96";
	function = "qup7";
	};
	};

	qup_spi8_default: qup-spi8-default {
	pinmux {
	pins = "gpio65", "gpio66",
	"gpio67", "gpio68";
	function = "qup8";
	};
	};

	qup_spi9_default: qup-spi9-default {
	pinmux {
	pins = "gpio6", "gpio7",
	"gpio4", "gpio5";
	function = "qup9";
	};
	};

	qup_spi10_default: qup-spi10-default {
	pinmux {
	pins = "gpio55", "gpio56",
	"gpio53", "gpio54";
	function = "qup10";
	};
	};

	qup_spi11_default: qup-spi11-default {
	pinmux {
	pins = "gpio31", "gpio32",
	"gpio33", "gpio34";
	function = "qup11";
	};
	};

	qup_spi12_default: qup-spi12-default {
	pinmux {
	pins = "gpio49", "gpio50",
	"gpio51", "gpio52";
	function = "qup12";
	};
	};

	qup_spi13_default: qup-spi13-default {
	pinmux {
	pins = "gpio105", "gpio106",
	"gpio107", "gpio108";
	function = "qup13";
	};
	};

	qup_spi14_default: qup-spi14-default {
	pinmux {
	pins = "gpio33", "gpio34",
	"gpio31", "gpio32";
	function = "qup14";
	};
	};

	qup_spi15_default: qup-spi15-default {
	pinmux {
	pins = "gpio81", "gpio82",
	"gpio83", "gpio84";
	function = "qup15";
	};
	};

	qup_uart0_default: qup-uart0-default {
	pinmux {
	pins = "gpio2", "gpio3";
	function = "qup0";
	};
	};

	qup_uart1_default: qup-uart1-default {
	pinmux {
	pins = "gpio19", "gpio20";
	function = "qup1";
	};
	};

	qup_uart2_default: qup-uart2-default {
	pinmux {
	pins = "gpio29", "gpio30";
	function = "qup2";
	};
	};

	qup_uart3_default: qup-uart3-default {
	pinmux {
	pins = "gpio43", "gpio44";
	function = "qup3";
	};
	};

	qup_uart4_default: qup-uart4-default {
	pinmux {
	pins = "gpio91", "gpio92";
	function = "qup4";
	};
	};

	qup_uart5_default: qup-uart5-default {
	pinmux {
	pins = "gpio87", "gpio88";
	function = "qup5";
	};
	};

	qup_uart6_default: qup-uart6-default {
	pinmux {
	pins = "gpio47", "gpio48";
	function = "qup6";
	};
	};

	qup_uart7_default: qup-uart7-default {
	pinmux {
	pins = "gpio95", "gpio96";
	function = "qup7";
	};
	};

	qup_uart8_default: qup-uart8-default {
	pinmux {
	pins = "gpio67", "gpio68";
	function = "qup8";
	};
	};

	qup_uart9_default: qup-uart9-default {
	pinmux {
	pins = "gpio4", "gpio5";
	function = "qup9";
	};
	};

	qup_uart10_default: qup-uart10-default {
	pinmux {
	pins = "gpio53", "gpio54";
	function = "qup10";
	};
	};

	qup_uart11_default: qup-uart11-default {
	pinmux {
	pins = "gpio33", "gpio34";
	function = "qup11";
	};
	};

	qup_uart12_default: qup-uart12-default {
	pinmux {
	pins = "gpio51", "gpio52";
	function = "qup12";
	};
	};

	qup_uart13_default: qup-uart13-default {
	pinmux {
	pins = "gpio107", "gpio108";
	function = "qup13";
	};
	};

	qup_uart14_default: qup-uart14-default {
	pinmux {
	pins = "gpio31", "gpio32";
	function = "qup14";
	};
	};

	qup_uart15_default: qup-uart15-default {
	pinmux {
	pins = "gpio83", "gpio84";
	function = "qup15";
	};
	};
	+
	+ quat_mi2s_sleep: quat_mi2s_sleep {
	+ mux {
	+ pins = "gpio58", "gpio59";
	+ function = "gpio";
	+ };
	+
	+ config {
	+ pins = "gpio58", "gpio59";
	+ drive-strength = <2>;
	+ bias-pull-down;
	+ input-enable;
	+ };
	+ };
	+
	+ quat_mi2s_active: quat_mi2s_active {
	+ mux {
	+ pins = "gpio58", "gpio59";
	+ function = "qua_mi2s";
	+ };
	+
	+ config {
	+ pins = "gpio58", "gpio59";
	+ drive-strength = <8>;
	+ bias-disable;
	+ output-high;
	+ };
	+ };
	+
	+ quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
	+ mux {
	+ pins = "gpio60";
	+ function = "gpio";
	+ };
	+
	+ config {
	+ pins = "gpio60";
	+ drive-strength = <2>;
	+ bias-pull-down;
	+ input-enable;
	+ };
	+ };
	+
	+ quat_mi2s_sd0_active: quat_mi2s_sd0_active {
	+ mux {
	+ pins = "gpio60";
	+ function = "qua_mi2s";
	+ };
	+
	+ config {
	+ pins = "gpio60";
	+ drive-strength = <8>;
	+ bias-disable;
	+ };
	+ };
	+
	+ quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
	+ mux {
	+ pins = "gpio61";
	+ function = "gpio";
	+ };
	+
	+ config {
	+ pins = "gpio61";
	+ drive-strength = <2>;
	+ bias-pull-down;
	+ input-enable;
	+ };
	+ };
	+
	+ quat_mi2s_sd1_active: quat_mi2s_sd1_active {
	+ mux {
	+ pins = "gpio61";
	+ function = "qua_mi2s";
	+ };
	+
	+ config {
	+ pins = "gpio61";
	+ drive-strength = <8>;
	+ bias-disable;
	+ };
	+ };
	+
	+ quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
	+ mux {
	+ pins = "gpio62";
	+ function = "gpio";
	+ };
	+
	+ config {
	+ pins = "gpio62";
	+ drive-strength = <2>;
	+ bias-pull-down;
	+ input-enable;
	+ };
	+ };
	+
	+ quat_mi2s_sd2_active: quat_mi2s_sd2_active {
	+ mux {
	+ pins = "gpio62";
	+ function = "qua_mi2s";
	+ };
	+
	+ config {
	+ pins = "gpio62";
	+ drive-strength = <8>;
	+ bias-disable;
	+ };
	+ };
	+
	+ quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
	+ mux {
	+ pins = "gpio63";
	+ function = "gpio";
	+ };
	+
	+ config {
	+ pins = "gpio63";
	+ drive-strength = <2>;
	+ bias-pull-down;
	+ input-enable;
	+ };
	+ };
	+
	+ quat_mi2s_sd3_active: quat_mi2s_sd3_active {
	+ mux {
	+ pins = "gpio63";
	+ function = "qua_mi2s";
	+ };
	+
	+ config {
	+ pins = "gpio63";
	+ drive-strength = <8>;
	+ bias-disable;
	+ };
	+ };
	};

	mss_pil: remoteproc@4080000 {
	compatible = "qcom,sdm845-mss-pil";
	reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
	reg-names = "qdsp6", "rmb";

	interrupts-extended =
	<&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
	<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
	<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "wdog", "fatal", "ready",
	"handover", "stop-ack",
	"shutdown-ack";

	clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
	<&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
	<&gcc GCC_BOOT_ROM_AHB_CLK>,
	<&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
	<&gcc GCC_MSS_SNOC_AXI_CLK>,
	<&gcc GCC_MSS_MFAB_AXIS_CLK>,
	<&gcc GCC_PRNG_AHB_CLK>,
	<&rpmhcc RPMH_CXO_CLK>;
	clock-names = "iface", "bus", "mem", "gpll0_mss",
	"snoc_axi", "mnoc_axi", "prng", "xo";

	qcom,smem-states = <&modem_smp2p_out 0>;
	qcom,smem-state-names = "stop";

	resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
	<&pdc_reset PDC_MODEM_SYNC_RESET>;
	reset-names = "mss_restart", "pdc_reset";

	qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;

	power-domains = <&aoss_qmp 2>,
	<&rpmhpd SDM845_CX>,
	<&rpmhpd SDM845_MX>,
	<&rpmhpd SDM845_MSS>;
	power-domain-names = "load_state", "cx", "mx", "mss";

	mba {
	memory-region = <&mba_region>;
	};

	mpss {
	memory-region = <&mpss_region>;
	};

	glink-edge {
	interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
	label = "modem";
	qcom,remote-pid = <1>;
	mboxes = <&apss_shared 12>;
	};
	};

	gpucc: clock-controller@5090000 {
	compatible = "qcom,sdm845-gpucc";
	reg = <0 0x05090000 0 0x9000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;
	- clocks = <&rpmhcc RPMH_CXO_CLK>;
	- clock-names = "xo";
	+ clocks = <&rpmhcc RPMH_CXO_CLK>,
	+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
	+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
	+ clock-names = "bi_tcxo",
	+ "gcc_gpu_gpll0_clk_src",
	+ "gcc_gpu_gpll0_div_clk_src";
	};

	stm@6002000 {
	compatible = "arm,coresight-stm", "arm,primecell";
	reg = <0 0x06002000 0 0x1000>,
	<0 0x16280000 0 0x180000>;
	reg-names = "stm-base", "stm-stimulus-base";

	clocks = <&aoss_qmp>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	stm_out: endpoint {
	remote-endpoint =
	<&funnel0_in7>;
	};
	};
	};
	};

	funnel@6041000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0 0x06041000 0 0x1000>;

	clocks = <&aoss_qmp>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	funnel0_out: endpoint {
	remote-endpoint =
	<&merge_funnel_in0>;
	};
	};
	};

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@7 {
	reg = <7>;
	funnel0_in7: endpoint {
	remote-endpoint = <&stm_out>;
	};
	};
	};
	};

	funnel@6043000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0 0x06043000 0 0x1000>;

	clocks = <&aoss_qmp>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	funnel2_out: endpoint {
	remote-endpoint =
	<&merge_funnel_in2>;
	};
	};
	};

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@5 {
	reg = <5>;
	funnel2_in5: endpoint {
	remote-endpoint =
	<&apss_merge_funnel_out>;
	};
	};
	};
	};

	funnel@6045000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0 0x06045000 0 0x1000>;

	clocks = <&aoss_qmp>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	merge_funnel_out: endpoint {
	remote-endpoint = <&etf_in>;
	};
	};
	};

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	merge_funnel_in0: endpoint {
	remote-endpoint =
	<&funnel0_out>;
	};
	};

	port@2 {
	reg = <2>;
	merge_funnel_in2: endpoint {
	remote-endpoint =
	<&funnel2_out>;
	};
	};
	};
	};

	replicator@6046000 {
	compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
	reg = <0 0x06046000 0 0x1000>;

	clocks = <&aoss_qmp>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	replicator_out: endpoint {
	remote-endpoint = <&etr_in>;
	};
	};
	};

	in-ports {
	port {
	replicator_in: endpoint {
	remote-endpoint = <&etf_out>;
	};
	};
	};
	};

	etf@6047000 {
	compatible = "arm,coresight-tmc", "arm,primecell";
	reg = <0 0x06047000 0 0x1000>;

	clocks = <&aoss_qmp>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	etf_out: endpoint {
	remote-endpoint =
	<&replicator_in>;
	};
	};
	};

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	reg = <1>;
	etf_in: endpoint {
	remote-endpoint =
	<&merge_funnel_out>;
	};
	};
	};
	};

	etr@6048000 {
	compatible = "arm,coresight-tmc", "arm,primecell";
	reg = <0 0x06048000 0 0x1000>;

	clocks = <&aoss_qmp>;
	clock-names = "apb_pclk";
	arm,scatter-gather;

	in-ports {
	port {
	etr_in: endpoint {
	remote-endpoint =
	<&replicator_out>;
	};
	};
	};
	};

	etm@7040000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0 0x07040000 0 0x1000>;

	cpu = <&CPU0>;

	clocks = <&aoss_qmp>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	etm0_out: endpoint {
	remote-endpoint =
	<&apss_funnel_in0>;
	};
	};
	};
	};

	etm@7140000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0 0x07140000 0 0x1000>;

	cpu = <&CPU1>;

	clocks = <&aoss_qmp>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	etm1_out: endpoint {
	remote-endpoint =
	<&apss_funnel_in1>;
	};
	};
	};
	};

	etm@7240000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0 0x07240000 0 0x1000>;

	cpu = <&CPU2>;

	clocks = <&aoss_qmp>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	etm2_out: endpoint {
	remote-endpoint =
	<&apss_funnel_in2>;
	};
	};
	};
	};

	etm@7340000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0 0x07340000 0 0x1000>;

	cpu = <&CPU3>;

	clocks = <&aoss_qmp>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	etm3_out: endpoint {
	remote-endpoint =
	<&apss_funnel_in3>;
	};
	};
	};
	};

	etm@7440000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0 0x07440000 0 0x1000>;

	cpu = <&CPU4>;

	clocks = <&aoss_qmp>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	etm4_out: endpoint {
	remote-endpoint =
	<&apss_funnel_in4>;
	};
	};
	};
	};

	etm@7540000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0 0x07540000 0 0x1000>;

	cpu = <&CPU5>;

	clocks = <&aoss_qmp>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	etm5_out: endpoint {
	remote-endpoint =
	<&apss_funnel_in5>;
	};
	};
	};
	};

	etm@7640000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0 0x07640000 0 0x1000>;

	cpu = <&CPU6>;

	clocks = <&aoss_qmp>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	etm6_out: endpoint {
	remote-endpoint =
	<&apss_funnel_in6>;
	};
	};
	};
	};

	etm@7740000 {
	compatible = "arm,coresight-etm4x", "arm,primecell";
	reg = <0 0x07740000 0 0x1000>;

	cpu = <&CPU7>;

	clocks = <&aoss_qmp>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	etm7_out: endpoint {
	remote-endpoint =
	<&apss_funnel_in7>;
	};
	};
	};
	};

	funnel@7800000 { /* APSS Funnel */
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0 0x07800000 0 0x1000>;

	clocks = <&aoss_qmp>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	apss_funnel_out: endpoint {
	remote-endpoint =
	<&apss_merge_funnel_in>;
	};
	};
	};

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	apss_funnel_in0: endpoint {
	remote-endpoint =
	<&etm0_out>;
	};
	};

	port@1 {
	reg = <1>;
	apss_funnel_in1: endpoint {
	remote-endpoint =
	<&etm1_out>;
	};
	};

	port@2 {
	reg = <2>;
	apss_funnel_in2: endpoint {
	remote-endpoint =
	<&etm2_out>;
	};
	};

	port@3 {
	reg = <3>;
	apss_funnel_in3: endpoint {
	remote-endpoint =
	<&etm3_out>;
	};
	};

	port@4 {
	reg = <4>;
	apss_funnel_in4: endpoint {
	remote-endpoint =
	<&etm4_out>;
	};
	};

	port@5 {
	reg = <5>;
	apss_funnel_in5: endpoint {
	remote-endpoint =
	<&etm5_out>;
	};
	};

	port@6 {
	reg = <6>;
	apss_funnel_in6: endpoint {
	remote-endpoint =
	<&etm6_out>;
	};
	};

	port@7 {
	reg = <7>;
	apss_funnel_in7: endpoint {
	remote-endpoint =
	<&etm7_out>;
	};
	};
	};
	};

	funnel@7810000 {
	compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	reg = <0 0x07810000 0 0x1000>;

	clocks = <&aoss_qmp>;
	clock-names = "apb_pclk";

	out-ports {
	port {
	apss_merge_funnel_out: endpoint {
	remote-endpoint =
	<&funnel2_in5>;
	};
	};
	};

	in-ports {
	port {
	apss_merge_funnel_in: endpoint {
	remote-endpoint =
	<&apss_funnel_out>;
	};
	};
	};
	};

	sdhc_2: sdhci@8804000 {
	compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
	reg = <0 0x08804000 0 0x1000>;

	interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hc_irq", "pwr_irq";

	clocks = <&gcc GCC_SDCC2_AHB_CLK>,
	<&gcc GCC_SDCC2_APPS_CLK>;
	clock-names = "iface", "core";
	iommus = <&apps_smmu 0xa0 0xf>;

	status = "disabled";
	};

	qspi: spi@88df000 {
	compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
	reg = <0 0x088df000 0 0x600>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
	<&gcc GCC_QSPI_CORE_CLK>;
	clock-names = "iface", "core";
	status = "disabled";
	};

	+ slim: slim@171c0000 {
	+ compatible = "qcom,slim-ngd-v2.1.0";
	+ reg = <0 0x171c0000 0 0x2c000>;
	+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
	+
	+ qcom,apps-ch-pipes = <0x780000>;
	+ qcom,ea-pc = <0x270>;
	+ status = "okay";
	+ dmas = <&slimbam 3>, <&slimbam 4>,
	+ <&slimbam 5>, <&slimbam 6>;
	+ dma-names = "rx", "tx", "tx2", "rx2";
	+
	+ iommus = <&apps_smmu 0x1806 0x0>;
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ ngd@1 {
	+ reg = <1>;
	+ #address-cells = <2>;
	+ #size-cells = <0>;
	+
	+ wcd9340_ifd: ifd@0{
	+ compatible = "slim217,250";
	+ reg = <0 0>;
	+ };
	+
	+ wcd9340: codec@1{
	+ compatible = "slim217,250";
	+ reg = <1 0>;
	+ slim-ifc-dev = <&wcd9340_ifd>;
	+
	+ #sound-dai-cells = <1>;
	+
	+ interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
	+ interrupt-controller;
	+ #interrupt-cells = <1>;
	+
	+ #clock-cells = <0>;
	+ clock-frequency = <9600000>;
	+ clock-output-names = "mclk";
	+ qcom,micbias1-millivolt = <1800>;
	+ qcom,micbias2-millivolt = <1800>;
	+ qcom,micbias3-millivolt = <1800>;
	+ qcom,micbias4-millivolt = <1800>;
	+
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+
	+ wcdgpio: gpio-controller@42 {
	+ compatible = "qcom,wcd9340-gpio";
	+ gpio-controller;
	+ #gpio-cells = <2>;
	+ reg = <0x42 0x2>;
	+ };
	+
	+ swm: swm@c85 {
	+ compatible = "qcom,soundwire-v1.3.0";
	+ reg = <0xc85 0x40>;
	+ interrupts-extended = <&wcd9340 20>;
	+
	+ qcom,dout-ports = <6>;
	+ qcom,din-ports = <2>;
	+ qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
	+ qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
	+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
	+
	+ #sound-dai-cells = <1>;
	+ clocks = <&wcd9340>;
	+ clock-names = "iface";
	+ #address-cells = <2>;
	+ #size-cells = <0>;
	+
	+
	+ };
	+ };
	+ };
	+ };
	+
	+ sound: sound {
	+ };
	+
	usb_1_hsphy: phy@88e2000 {
	compatible = "qcom,sdm845-qusb2-phy";
	reg = <0 0x088e2000 0 0x400>;
	status = "disabled";
	#phy-cells = <0>;

	clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	<&rpmhcc RPMH_CXO_CLK>;
	clock-names = "cfg_ahb", "ref";

	resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

	nvmem-cells = <&qusb2p_hstx_trim>;
	};

	usb_2_hsphy: phy@88e3000 {
	compatible = "qcom,sdm845-qusb2-phy";
	reg = <0 0x088e3000 0 0x400>;
	status = "disabled";
	#phy-cells = <0>;

	clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	<&rpmhcc RPMH_CXO_CLK>;
	clock-names = "cfg_ahb", "ref";

	resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;

	nvmem-cells = <&qusb2s_hstx_trim>;
	};

	usb_1_qmpphy: phy@88e9000 {
	compatible = "qcom,sdm845-qmp-usb3-phy";
	reg = <0 0x088e9000 0 0x18c>,
	<0 0x088e8000 0 0x10>;
	reg-names = "reg-base", "dp_com";
	status = "disabled";
	#clock-cells = <1>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
	<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
	<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
	clock-names = "aux", "cfg_ahb", "ref", "com_aux";

	resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
	<&gcc GCC_USB3_PHY_PRIM_BCR>;
	reset-names = "phy", "common";

	usb_1_ssphy: lanes@88e9200 {
	reg = <0 0x088e9200 0 0x128>,
	<0 0x088e9400 0 0x200>,
	<0 0x088e9c00 0 0x218>,
	<0 0x088e9600 0 0x128>,
	<0 0x088e9800 0 0x200>,
	<0 0x088e9a00 0 0x100>;
	#phy-cells = <0>;
	clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
	clock-names = "pipe0";
	clock-output-names = "usb3_phy_pipe_clk_src";
	};
	};

	usb_2_qmpphy: phy@88eb000 {
	compatible = "qcom,sdm845-qmp-usb3-uni-phy";
	reg = <0 0x088eb000 0 0x18c>;
	status = "disabled";
	#clock-cells = <1>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
	<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	<&gcc GCC_USB3_SEC_CLKREF_CLK>,
	<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
	clock-names = "aux", "cfg_ahb", "ref", "com_aux";

	resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
	<&gcc GCC_USB3_PHY_SEC_BCR>;
	reset-names = "phy", "common";

	usb_2_ssphy: lane@88eb200 {
	reg = <0 0x088eb200 0 0x128>,
	<0 0x088eb400 0 0x1fc>,
	<0 0x088eb800 0 0x218>,
	<0 0x088eb600 0 0x70>;
	#phy-cells = <0>;
	clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
	clock-names = "pipe0";
	clock-output-names = "usb3_uni_phy_pipe_clk_src";
	};
	};

	usb_1: usb@a6f8800 {
	compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
	reg = <0 0x0a6f8800 0 0x400>;
	status = "disabled";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	dma-ranges;

	clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
	<&gcc GCC_USB30_PRIM_MASTER_CLK>,
	<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
	<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
	<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
	clock-names = "cfg_noc", "core", "iface", "mock_utmi",
	"sleep";

	assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
	<&gcc GCC_USB30_PRIM_MASTER_CLK>;
	assigned-clock-rates = <19200000>, <150000000>;

	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hs_phy_irq", "ss_phy_irq",
	"dm_hs_phy_irq", "dp_hs_phy_irq";

	power-domains = <&gcc USB30_PRIM_GDSC>;

	resets = <&gcc GCC_USB30_PRIM_BCR>;

	usb_1_dwc3: dwc3@a600000 {
	compatible = "snps,dwc3";
	reg = <0 0x0a600000 0 0xcd00>;
	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
	iommus = <&apps_smmu 0x740 0>;
	snps,dis_u2_susphy_quirk;
	snps,dis_enblslpm_quirk;
	phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
	phy-names = "usb2-phy", "usb3-phy";
	};
	};

	usb_2: usb@a8f8800 {
	compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
	reg = <0 0x0a8f8800 0 0x400>;
	status = "disabled";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	dma-ranges;

	clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
	<&gcc GCC_USB30_SEC_MASTER_CLK>,
	<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
	<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
	<&gcc GCC_USB30_SEC_SLEEP_CLK>;
	clock-names = "cfg_noc", "core", "iface", "mock_utmi",
	"sleep";

	assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
	<&gcc GCC_USB30_SEC_MASTER_CLK>;
	assigned-clock-rates = <19200000>, <150000000>;

	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hs_phy_irq", "ss_phy_irq",
	"dm_hs_phy_irq", "dp_hs_phy_irq";

	power-domains = <&gcc USB30_SEC_GDSC>;

	resets = <&gcc GCC_USB30_SEC_BCR>;

	usb_2_dwc3: dwc3@a800000 {
	compatible = "snps,dwc3";
	reg = <0 0x0a800000 0 0xcd00>;
	interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	iommus = <&apps_smmu 0x760 0>;
	snps,dis_u2_susphy_quirk;
	snps,dis_enblslpm_quirk;
	phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
	phy-names = "usb2-phy", "usb3-phy";
	};
	};

	- video-codec@aa00000 {
	- compatible = "qcom,sdm845-venus";
	+ venus: video-codec@aa00000 {
	+ compatible = "qcom,sdm845-venus-v2";
	reg = <0 0x0aa00000 0 0xff000>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	- power-domains = <&videocc VENUS_GDSC>;
	+ power-domains = <&videocc VENUS_GDSC>,
	+ <&videocc VCODEC0_GDSC>,
	+ <&videocc VCODEC1_GDSC>;
	+ power-domain-names = "venus", "vcodec0", "vcodec1";
	clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
	<&videocc VIDEO_CC_VENUS_AHB_CLK>,
	- <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;
	- clock-names = "core", "iface", "bus";
	+ <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
	+ <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
	+ <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
	+ <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
	+ <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
	+ clock-names = "core", "iface", "bus",
	+ "vcodec0_core", "vcodec0_bus",
	+ "vcodec1_core", "vcodec1_bus";
	iommus = <&apps_smmu 0x10a0 0x8>,
	<&apps_smmu 0x10b0 0x0>;
	memory-region = <&venus_mem>;

	video-core0 {
	compatible = "venus-decoder";
	- clocks = <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
	- <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
	- clock-names = "core", "bus";
	- power-domains = <&videocc VCODEC0_GDSC>;
	};

	video-core1 {
	compatible = "venus-encoder";
	- clocks = <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
	- <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
	- clock-names = "core", "bus";
	- power-domains = <&videocc VCODEC1_GDSC>;
	};
	};

	videocc: clock-controller@ab00000 {
	compatible = "qcom,sdm845-videocc";
	reg = <0 0x0ab00000 0 0x10000>;
	+ clocks = <&rpmhcc RPMH_CXO_CLK>;
	+ clock-names = "bi_tcxo";
	#clock-cells = <1>;
	#power-domain-cells = <1>;
	#reset-cells = <1>;
	};

	mdss: mdss@ae00000 {
	compatible = "qcom,sdm845-mdss";
	reg = <0 0x0ae00000 0 0x1000>;
	reg-names = "mdss";

	power-domains = <&dispcc MDSS_GDSC>;

	clocks = <&gcc GCC_DISP_AHB_CLK>,
	<&gcc GCC_DISP_AXI_CLK>,
	<&dispcc DISP_CC_MDSS_MDP_CLK>;
	clock-names = "iface", "bus", "core";

	assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
	assigned-clock-rates = <300000000>;

	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <1>;

	iommus = <&apps_smmu 0x880 0x8>,
	<&apps_smmu 0xc80 0x8>;

	status = "disabled";

	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	mdss_mdp: mdp@ae01000 {
	compatible = "qcom,sdm845-dpu";
	reg = <0 0x0ae01000 0 0x8f000>,
	<0 0x0aeb0000 0 0x2008>;
	reg-names = "mdp", "vbif";

	clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	<&dispcc DISP_CC_MDSS_AXI_CLK>,
	<&dispcc DISP_CC_MDSS_MDP_CLK>,
	<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
	clock-names = "iface", "bus", "core", "vsync";

	assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
	<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
	assigned-clock-rates = <300000000>,
	<19200000>;

	interrupt-parent = <&mdss>;
	interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;

	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	dpu_intf1_out: endpoint {
	remote-endpoint = <&dsi0_in>;
	};
	};

	port@1 {
	reg = <1>;
	dpu_intf2_out: endpoint {
	remote-endpoint = <&dsi1_in>;
	};
	};
	};
	};

	dsi0: dsi@ae94000 {
	compatible = "qcom,mdss-dsi-ctrl";
	reg = <0 0x0ae94000 0 0x400>;
	reg-names = "dsi_ctrl";

	interrupt-parent = <&mdss>;
	interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
	<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
	<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
	<&dispcc DISP_CC_MDSS_ESC0_CLK>,
	<&dispcc DISP_CC_MDSS_AHB_CLK>,
	<&dispcc DISP_CC_MDSS_AXI_CLK>;
	clock-names = "byte",
	"byte_intf",
	"pixel",
	"core",
	"iface",
	"bus";

	phys = <&dsi0_phy>;
	phy-names = "dsi";

	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	dsi0_in: endpoint {
	remote-endpoint = <&dpu_intf1_out>;
	};
	};

	port@1 {
	reg = <1>;
	dsi0_out: endpoint {
	};
	};
	};
	};

	dsi0_phy: dsi-phy@ae94400 {
	compatible = "qcom,dsi-phy-10nm";
	reg = <0 0x0ae94400 0 0x200>,
	<0 0x0ae94600 0 0x280>,
	<0 0x0ae94a00 0 0x1e0>;
	reg-names = "dsi_phy",
	"dsi_phy_lane",
	"dsi_pll";

	#clock-cells = <1>;
	#phy-cells = <0>;

	clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	<&rpmhcc RPMH_CXO_CLK>;
	clock-names = "iface", "ref";

	status = "disabled";
	};

	dsi1: dsi@ae96000 {
	compatible = "qcom,mdss-dsi-ctrl";
	reg = <0 0x0ae96000 0 0x400>;
	reg-names = "dsi_ctrl";

	interrupt-parent = <&mdss>;
	interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
	<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
	<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
	<&dispcc DISP_CC_MDSS_ESC1_CLK>,
	<&dispcc DISP_CC_MDSS_AHB_CLK>,
	<&dispcc DISP_CC_MDSS_AXI_CLK>;
	clock-names = "byte",
	"byte_intf",
	"pixel",
	"core",
	"iface",
	"bus";

	phys = <&dsi1_phy>;
	phy-names = "dsi";

	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	dsi1_in: endpoint {
	remote-endpoint = <&dpu_intf2_out>;
	};
	};

	port@1 {
	reg = <1>;
	dsi1_out: endpoint {
	};
	};
	};
	};

	dsi1_phy: dsi-phy@ae96400 {
	compatible = "qcom,dsi-phy-10nm";
	reg = <0 0x0ae96400 0 0x200>,
	<0 0x0ae96600 0 0x280>,
	<0 0x0ae96a00 0 0x10e>;
	reg-names = "dsi_phy",
	"dsi_phy_lane",
	"dsi_pll";

	#clock-cells = <1>;
	#phy-cells = <0>;

	clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	<&rpmhcc RPMH_CXO_CLK>;
	clock-names = "iface", "ref";

	status = "disabled";
	};
	};

	gpu: gpu@5000000 {
	compatible = "qcom,adreno-630.2", "qcom,adreno";
	#stream-id-cells = <16>;

	reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
	reg-names = "kgsl_3d0_reg_memory", "cx_mem";

	/*
	* Look ma, no clocks! The GPU clocks and power are
	* controlled entirely by the GMU
	*/

	interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

	iommus = <&adreno_smmu 0>;

	operating-points-v2 = <&gpu_opp_table>;

	qcom,gmu = <&gmu>;

	gpu_opp_table: opp-table {
	compatible = "operating-points-v2";

	opp-710000000 {
	opp-hz = /bits/ 64 <710000000>;
	opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
	};

	opp-675000000 {
	opp-hz = /bits/ 64 <675000000>;
	opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
	};

	opp-596000000 {
	opp-hz = /bits/ 64 <596000000>;
	opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
	};

	opp-520000000 {
	opp-hz = /bits/ 64 <520000000>;
	opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
	};

	opp-414000000 {
	opp-hz = /bits/ 64 <414000000>;
	opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
	};

	opp-342000000 {
	opp-hz = /bits/ 64 <342000000>;
	opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
	};

	opp-257000000 {
	opp-hz = /bits/ 64 <257000000>;
	opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
	};
	};
	};

	adreno_smmu: iommu@5040000 {
	compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
	reg = <0 0x5040000 0 0x10000>;
	#iommu-cells = <1>;
	#global-interrupts = <2>;
	interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
	<GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
	clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
	<&gcc GCC_GPU_CFG_AHB_CLK>;
	clock-names = "bus", "iface";

	power-domains = <&gpucc GPU_CX_GDSC>;
	};

	gmu: gmu@506a000 {
	compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";

	reg = <0 0x506a000 0 0x30000>,
	<0 0xb280000 0 0x10000>,
	<0 0xb480000 0 0x10000>;
	reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";

	interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hfi", "gmu";

	clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
	<&gpucc GPU_CC_CXO_CLK>,
	<&gcc GCC_DDRSS_GPU_AXI_CLK>,
	<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
	clock-names = "gmu", "cxo", "axi", "memnoc";

	power-domains = <&gpucc GPU_CX_GDSC>,
	<&gpucc GPU_GX_GDSC>;
	power-domain-names = "cx", "gx";

	iommus = <&adreno_smmu 5>;

	operating-points-v2 = <&gmu_opp_table>;

	gmu_opp_table: opp-table {
	compatible = "operating-points-v2";

	opp-400000000 {
	opp-hz = /bits/ 64 <400000000>;
	opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
	};

	opp-200000000 {
	opp-hz = /bits/ 64 <200000000>;
	opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
	};
	};
	};

	dispcc: clock-controller@af00000 {
	compatible = "qcom,sdm845-dispcc";
	reg = <0 0x0af00000 0 0x10000>;
	+ clocks = <&rpmhcc RPMH_CXO_CLK>,
	+ <&gcc GCC_DISP_GPLL0_CLK_SRC>,
	+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
	+ <&dsi0_phy 0>,
	+ <&dsi0_phy 1>,
	+ <&dsi1_phy 0>,
	+ <&dsi1_phy 1>,
	+ <0>,
	+ <0>;
	+ clock-names = "bi_tcxo",
	+ "gcc_disp_gpll0_clk_src",
	+ "gcc_disp_gpll0_div_clk_src",
	+ "dsi0_phy_pll_out_byteclk",
	+ "dsi0_phy_pll_out_dsiclk",
	+ "dsi1_phy_pll_out_byteclk",
	+ "dsi1_phy_pll_out_dsiclk",
	+ "dp_link_clk_divsel_ten",
	+ "dp_vco_divided_clk_src_mux";
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;
	};

	pdc_intc: interrupt-controller@b220000 {
	compatible = "qcom,sdm845-pdc", "qcom,pdc";
	reg = <0 0x0b220000 0 0x30000>;
	qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
	#interrupt-cells = <2>;
	interrupt-parent = <&intc>;
	interrupt-controller;
	};

	pdc_reset: reset-controller@b2e0000 {
	compatible = "qcom,sdm845-pdc-global";
	reg = <0 0x0b2e0000 0 0x20000>;
	#reset-cells = <1>;
	};

	tsens0: thermal-sensor@c263000 {
	compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
	reg = <0 0x0c263000 0 0x1ff>, /* TM */
	<0 0x0c222000 0 0x1ff>; /* SROT */
	#qcom,sensors = <13>;
	interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "uplow", "critical";
	#thermal-sensor-cells = <1>;
	};

	tsens1: thermal-sensor@c265000 {
	compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
	reg = <0 0x0c265000 0 0x1ff>, /* TM */
	<0 0x0c223000 0 0x1ff>; /* SROT */
	#qcom,sensors = <8>;
	interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "uplow", "critical";
	#thermal-sensor-cells = <1>;
	};

	aoss_reset: reset-controller@c2a0000 {
	compatible = "qcom,sdm845-aoss-cc";
	reg = <0 0x0c2a0000 0 0x31000>;
	#reset-cells = <1>;
	};

	aoss_qmp: qmp@c300000 {
	compatible = "qcom,sdm845-aoss-qmp";
	reg = <0 0x0c300000 0 0x100000>;
	interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
	mboxes = <&apss_shared 0>;

	#clock-cells = <0>;
	#power-domain-cells = <1>;

	cx_cdev: cx {
	#cooling-cells = <2>;
	};

	ebi_cdev: ebi {
	#cooling-cells = <2>;
	};
	};

	spmi_bus: spmi@c440000 {
	compatible = "qcom,spmi-pmic-arb";
	reg = <0 0x0c440000 0 0x1100>,
	<0 0x0c600000 0 0x2000000>,
	<0 0x0e600000 0 0x100000>,
	<0 0x0e700000 0 0xa0000>,
	<0 0x0c40a000 0 0x26000>;
	reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
	interrupt-names = "periph_irq";
	interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
	qcom,ee = <0>;
	qcom,channel = <0>;
	#address-cells = <2>;
	#size-cells = <0>;
	interrupt-controller;
	#interrupt-cells = <4>;
	cell-index = <0>;
	};

	apps_smmu: iommu@15000000 {
	compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
	reg = <0 0x15000000 0 0x80000>;
	#iommu-cells = <2>;
	#global-interrupts = <1>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
	};

	lpasscc: clock-controller@17014000 {
	compatible = "qcom,sdm845-lpasscc";
	reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
	reg-names = "cc", "qdsp6ss";
	#clock-cells = <1>;
	status = "disabled";
	};

	+ gladiator_noc: interconnect@17900000 {
	+ compatible = "qcom,sdm845-gladiator-noc";
	+ reg = <0 0x17900000 0 0xd080>;
	+ #interconnect-cells = <1>;
	+ qcom,bcm-voters = <&apps_bcm_voter>;
	+ };
	+
	watchdog@17980000 {
	compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
	reg = <0 0x17980000 0 0x1000>;
	clocks = <&sleep_clk>;
	};

	apss_shared: mailbox@17990000 {
	compatible = "qcom,sdm845-apss-shared";
	reg = <0 0x17990000 0 0x1000>;
	#mbox-cells = <1>;
	};

	apps_rsc: rsc@179c0000 {
	label = "apps_rsc";
	compatible = "qcom,rpmh-rsc";
	reg = <0 0x179c0000 0 0x10000>,
	<0 0x179d0000 0 0x10000>,
	<0 0x179e0000 0 0x10000>;
	reg-names = "drv-0", "drv-1", "drv-2";
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	qcom,tcs-offset = <0xd00>;
	qcom,drv-id = <2>;
	qcom,tcs-config = <ACTIVE_TCS 2>,
	<SLEEP_TCS 3>,
	<WAKE_TCS 3>,
	<CONTROL_TCS 1>;

	+ apps_bcm_voter: bcm-voter {
	+ compatible = "qcom,bcm-voter";
	+ };
	+
	rpmhcc: clock-controller {
	compatible = "qcom,sdm845-rpmh-clk";
	#clock-cells = <1>;
	clock-names = "xo";
	clocks = <&xo_board>;
	};

	rpmhpd: power-controller {
	compatible = "qcom,sdm845-rpmhpd";
	#power-domain-cells = <1>;
	operating-points-v2 = <&rpmhpd_opp_table>;

	rpmhpd_opp_table: opp-table {
	compatible = "operating-points-v2";

	rpmhpd_opp_ret: opp1 {
	opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
	};

	rpmhpd_opp_min_svs: opp2 {
	opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
	};

	rpmhpd_opp_low_svs: opp3 {
	opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
	};

	rpmhpd_opp_svs: opp4 {
	opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
	};

	rpmhpd_opp_svs_l1: opp5 {
	opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
	};

	rpmhpd_opp_nom: opp6 {
	opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
	};

	rpmhpd_opp_nom_l1: opp7 {
	opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
	};

	rpmhpd_opp_nom_l2: opp8 {
	opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
	};

	rpmhpd_opp_turbo: opp9 {
	opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
	};

	rpmhpd_opp_turbo_l1: opp10 {
	opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
	};
	};
	};
	-
	- rsc_hlos: interconnect {
	- compatible = "qcom,sdm845-rsc-hlos";
	- #interconnect-cells = <1>;
	- };
	};

	intc: interrupt-controller@17a00000 {
	compatible = "arm,gic-v3";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0 0x17a00000 0 0x10000>, /* GICD */
	<0 0x17a60000 0 0x100000>; /* GICR * 8 */
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

	msi-controller@17a40000 {
	compatible = "arm,gic-v3-its";
	msi-controller;
	#msi-cells = <1>;
	reg = <0 0x17a40000 0 0x20000>;
	status = "disabled";
	};
	};

	+ slimbam: dma@17184000 {
	+ compatible = "qcom,bam-v1.7.0";
	+ qcom,controlled-remotely;
	+ reg = <0 0x17184000 0 0x2a000>;
	+ num-channels = <31>;
	+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	+ #dma-cells = <1>;
	+ qcom,ee = <1>;
	+ qcom,num-ees = <2>;
	+ iommus = <&apps_smmu 0x1806 0x0>;
	+ };
	+
	timer@17c90000 {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	compatible = "arm,armv7-timer-mem";
	reg = <0 0x17c90000 0 0x1000>;

	frame@17ca0000 {
	frame-number = <0>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0 0x17ca0000 0 0x1000>,
	<0 0x17cb0000 0 0x1000>;
	};

	frame@17cc0000 {
	frame-number = <1>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0 0x17cc0000 0 0x1000>;
	status = "disabled";
	};

	frame@17cd0000 {
	frame-number = <2>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0 0x17cd0000 0 0x1000>;
	status = "disabled";
	};

	frame@17ce0000 {
	frame-number = <3>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0 0x17ce0000 0 0x1000>;
	status = "disabled";
	};

	frame@17cf0000 {
	frame-number = <4>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0 0x17cf0000 0 0x1000>;
	status = "disabled";
	};

	frame@17d00000 {
	frame-number = <5>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0 0x17d00000 0 0x1000>;
	status = "disabled";
	};

	frame@17d10000 {
	frame-number = <6>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0 0x17d10000 0 0x1000>;
	status = "disabled";
	};
	};

	+ osm_l3: interconnect@17d41000 {
	+ compatible = "qcom,sdm845-osm-l3";
	+ reg = <0 0x17d41000 0 0x1400>;
	+
	+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
	+ clock-names = "xo", "alternate";
	+
	+ #interconnect-cells = <1>;
	+ };
	+
	cpufreq_hw: cpufreq@17d43000 {
	compatible = "qcom,cpufreq-hw";
	reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
	reg-names = "freq-domain0", "freq-domain1";

	clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
	clock-names = "xo", "alternate";

	#freq-domain-cells = <1>;
	};

	wifi: wifi@18800000 {
	compatible = "qcom,wcn3990-wifi";
	status = "disabled";
	reg = <0 0x18800000 0 0x800000>;
	reg-names = "membase";
	memory-region = <&wlan_msa_mem>;
	clock-names = "cxo_ref_clk_pin";
	clocks = <&rpmhcc RPMH_RF_CLK2>;
	interrupts =
	<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
	iommus = <&apps_smmu 0x0040 0x1>;
	};
	};

	thermal-zones {
	cpu0-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 1>;

	trips {
	cpu0_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu0_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu0_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu0_alert0>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu0_alert1>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu1-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 2>;

	trips {
	cpu1_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu1_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu1_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu1_alert0>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu1_alert1>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu2-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 3>;

	trips {
	cpu2_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu2_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu2_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu2_alert0>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu2_alert1>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu3-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 4>;

	trips {
	cpu3_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu3_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu3_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu3_alert0>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu3_alert1>;
	cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu4-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 7>;

	trips {
	cpu4_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu4_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu4_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu4_alert0>;
	cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu4_alert1>;
	cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu5-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 8>;

	trips {
	cpu5_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu5_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu5_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu5_alert0>;
	cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu5_alert1>;
	cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu6-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 9>;

	trips {
	cpu6_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu6_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu6_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu6_alert0>;
	cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu6_alert1>;
	cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	cpu7-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 10>;

	trips {
	cpu7_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu7_alert1: trip-point1 {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu7_crit: cpu_crit {
	temperature = <110000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu7_alert0>;
	cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu7_alert1>;
	cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	aoss0-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 0>;

	trips {
	aoss0_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	cluster0-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 5>;

	trips {
	cluster0_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	cluster0_crit: cluster0_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	cluster1-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 6>;

	trips {
	cluster1_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	cluster1_crit: cluster1_crit {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};

	gpu-thermal-top {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 11>;

	trips {
	gpu1_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	gpu-thermal-bottom {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens0 12>;

	trips {
	gpu2_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	aoss1-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 0>;

	trips {
	aoss1_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	q6-modem-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 1>;

	trips {
	q6_modem_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	mem-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 2>;

	trips {
	mem_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	wlan-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 3>;

	trips {
	wlan_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	q6-hvx-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 4>;

	trips {
	q6_hvx_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	camera-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 5>;

	trips {
	camera_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	video-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 6>;

	trips {
	video_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};

	modem-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;

	thermal-sensors = <&tsens1 7>;

	trips {
	modem_alert0: trip-point0 {
	temperature = <90000>;
	hysteresis = <2000>;
	type = "hot";
	};
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/qcom/sdm850-lenovo-yoga-c630.dts b/sys/gnu/dts/arm64/qcom/sdm850-lenovo-yoga-c630.dts
	index b255be3a4a0a..51a670ad15b2 100644
	--- a/sys/gnu/dts/arm64/qcom/sdm850-lenovo-yoga-c630.dts
	+++ b/sys/gnu/dts/arm64/qcom/sdm850-lenovo-yoga-c630.dts
	@@ -1,467 +1,579 @@
	// SPDX-License-Identifier: BSD-3-Clause
	/*
	* Lenovo Yoga C630
	*
	* Copyright (c) 2019, Linaro Ltd.
	*/

	/dts-v1/;

	+#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
	+#include <dt-bindings/sound/qcom,q6afe.h>
	+#include <dt-bindings/sound/qcom,q6asm.h>
	#include "sdm845.dtsi"
	#include "pm8998.dtsi"

	/ {
	model = "Lenovo Yoga C630";
	compatible = "lenovo,yoga-c630", "qcom,sdm845";

	aliases {
	hsuart0 = &uart6;
	};
	};

	&adsp_pas {
	firmware-name = "qcom/LENOVO/81JL/qcadsp850.mbn";
	status = "okay";
	};

	&apps_rsc {
	pm8998-rpmh-regulators {
	compatible = "qcom,pm8998-rpmh-regulators";
	qcom,pmic-id = "a";

	vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
	vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;

	vreg_s2a_1p125: smps2 {
	};

	vreg_s3a_1p35: smps3 {
	regulator-min-microvolt = <1352000>;
	regulator-max-microvolt = <1352000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_s4a_1p8: smps4 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_s5a_2p04: smps5 {
	regulator-min-microvolt = <2040000>;
	regulator-max-microvolt = <2040000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_s7a_1p025: smps7 {
	};

	vdd_qusb_hs0:
	vdda_hp_pcie_core:
	vdda_mipi_csi0_0p9:
	vdda_mipi_csi1_0p9:
	vdda_mipi_csi2_0p9:
	vdda_mipi_dsi0_pll:
	vdda_mipi_dsi1_pll:
	vdda_qlink_lv:
	vdda_qlink_lv_ck:
	vdda_qrefs_0p875:
	vdda_pcie_core:
	vdda_pll_cc_ebi01:
	vdda_pll_cc_ebi23:
	vdda_sp_sensor:
	vdda_ufs1_core:
	vdda_ufs2_core:
	vdda_usb1_ss_core:
	vdda_usb2_ss_core:
	vreg_l1a_0p875: ldo1 {
	regulator-min-microvolt = <880000>;
	regulator-max-microvolt = <880000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vddpx_10:
	vreg_l2a_1p2: ldo2 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	regulator-always-on;
	};

	vreg_l3a_1p0: ldo3 {
	};

	vdd_wcss_cx:
	vdd_wcss_mx:
	vdda_wcss_pll:
	vreg_l5a_0p8: ldo5 {
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vddpx_13:
	vreg_l6a_1p8: ldo6 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l7a_1p8: ldo7 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l8a_1p2: ldo8 {
	};

	vreg_l9a_1p8: ldo9 {
	};

	vreg_l10a_1p8: ldo10 {
	};

	vreg_l11a_1p0: ldo11 {
	};

	vdd_qfprom:
	vdd_qfprom_sp:
	vdda_apc1_cs_1p8:
	vdda_gfx_cs_1p8:
	vdda_qrefs_1p8:
	vdda_qusb_hs0_1p8:
	vddpx_11:
	vreg_l12a_1p8: ldo12 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vddpx_2:
	vreg_l13a_2p95: ldo13 {
	};

	vreg_l14a_1p88: ldo14 {
	regulator-min-microvolt = <1880000>;
	regulator-max-microvolt = <1880000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	regulator-always-on;
	};

	vreg_l15a_1p8: ldo15 {
	};

	vreg_l16a_2p7: ldo16 {
	};

	vreg_l17a_1p3: ldo17 {
	regulator-min-microvolt = <1304000>;
	regulator-max-microvolt = <1304000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l18a_2p7: ldo18 {
	};

	vreg_l19a_3p0: ldo19 {
	regulator-min-microvolt = <3100000>;
	regulator-max-microvolt = <3108000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l20a_2p95: ldo20 {
	regulator-min-microvolt = <2960000>;
	regulator-max-microvolt = <2960000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l21a_2p95: ldo21 {
	};

	vreg_l22a_2p85: ldo22 {
	};

	vreg_l23a_3p3: ldo23 {
	};

	vdda_qusb_hs0_3p1:
	vreg_l24a_3p075: ldo24 {
	regulator-min-microvolt = <3075000>;
	regulator-max-microvolt = <3083000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l25a_3p3: ldo25 {
	regulator-min-microvolt = <3104000>;
	regulator-max-microvolt = <3112000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vdda_hp_pcie_1p2:
	vdda_hv_ebi0:
	vdda_hv_ebi1:
	vdda_hv_ebi2:
	vdda_hv_ebi3:
	vdda_mipi_csi_1p25:
	vdda_mipi_dsi0_1p2:
	vdda_mipi_dsi1_1p2:
	vdda_pcie_1p2:
	vdda_ufs1_1p2:
	vdda_ufs2_1p2:
	vdda_usb1_ss_1p2:
	vdda_usb2_ss_1p2:
	vreg_l26a_1p2: ldo26 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1208000>;
	regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
	};

	vreg_l28a_3p0: ldo28 {
	};

	vreg_lvs1a_1p8: lvs1 {
	};

	vreg_lvs2a_1p8: lvs2 {
	};
	};
	};

	&apps_smmu {
	/* TODO: Figure out how to survive booting with this enabled */
	status = "disabled";
	};

	&cdsp_pas {
	firmware-name = "qcom/LENOVO/81JL/qccdsp850.mbn";
	status = "okay";
	};

	&gcc {
	protected-clocks = <GCC_QSPI_CORE_CLK>,
	<GCC_QSPI_CORE_CLK_SRC>,
	<GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
	};

	&gpu {
	zap-shader {
	memory-region = <&gpu_mem>;
	firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn";
	};
	};

	&i2c1 {
	status = "okay";
	clock-frequency = <400000>;
	};

	&i2c3 {
	status = "okay";
	clock-frequency = <400000>;

	hid@15 {
	compatible = "hid-over-i2c";
	reg = <0x15>;
	hid-descr-addr = <0x1>;

	interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>;
	};

	hid@2c {
	compatible = "hid-over-i2c";
	reg = <0x2c>;
	hid-descr-addr = <0x20>;

	interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>;

	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_hid_active>;
	};
	};

	&i2c5 {
	status = "okay";
	clock-frequency = <400000>;

	hid@10 {
	compatible = "hid-over-i2c";
	reg = <0x10>;
	hid-descr-addr = <0x1>;

	interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>;

	pinctrl-names = "default";
	pinctrl-0 = <&i2c6_hid_active>;
	};
	};

	&i2c11 {
	status = "okay";
	clock-frequency = <400000>;

	hid@5c {
	compatible = "hid-over-i2c";
	reg = <0x5c>;
	hid-descr-addr = <0x1>;

	interrupts-extended = <&tlmm 92 IRQ_TYPE_LEVEL_LOW>;

	pinctrl-names = "default";
	pinctrl-0 = <&i2c12_hid_active>;
	};
	};

	&mss_pil {
	firmware-name = "qcom/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/LENOVO/81JL/qcdsp2850.mbn";
	};

	&qup_i2c12_default {
	drive-strength = <2>;
	bias-disable;
	};

	&qup_uart6_default {
	pinmux {
	pins = "gpio45", "gpio46", "gpio47", "gpio48";
	function = "qup6";
	};

	cts {
	pins = "gpio45";
	bias-pull-down;
	};

	rts-tx {
	pins = "gpio46", "gpio47";
	drive-strength = <2>;
	bias-disable;
	};

	rx {
	pins = "gpio48";
	bias-pull-up;
	};
	};

	&qupv3_id_0 {
	status = "okay";
	};

	&qupv3_id_1 {
	status = "okay";
	};

	+&q6asmdai {
	+ dai@0 {
	+ reg = <0>;
	+ };
	+
	+ dai@1 {
	+ reg = <1>;
	+ };
	+};
	+
	+&sound {
	+ compatible = "qcom,db845c-sndcard";
	+ model = "Lenovo-YOGA-C630-13Q50";
	+
	+ audio-routing =
	+ "RX_BIAS", "MCLK",
	+ "AMIC2", "MIC BIAS2",
	+ "SpkrLeft IN", "SPK1 OUT",
	+ "SpkrRight IN", "SPK2 OUT",
	+ "MM_DL1", "MultiMedia1 Playback",
	+ "MultiMedia2 Capture", "MM_UL2";
	+
	+ mm1-dai-link {
	+ link-name = "MultiMedia1";
	+ cpu {
	+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
	+ };
	+ };
	+
	+ mm2-dai-link {
	+ link-name = "MultiMedia2";
	+ cpu {
	+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
	+ };
	+ };
	+
	+ slim-dai-link {
	+ link-name = "SLIM Playback";
	+ cpu {
	+ sound-dai = <&q6afedai SLIMBUS_0_RX>;
	+ };
	+
	+ platform {
	+ sound-dai = <&q6routing>;
	+ };
	+
	+ codec {
	+ sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>;
	+ };
	+ };
	+
	+ slimcap-dai-link {
	+ link-name = "SLIM Capture";
	+ cpu {
	+ sound-dai = <&q6afedai SLIMBUS_0_TX>;
	+ };
	+
	+ platform {
	+ sound-dai = <&q6routing>;
	+ };
	+
	+ codec {
	+ sound-dai = <&wcd9340 1>;
	+ };
	+ };
	+};
	+
	&tlmm {
	gpio-reserved-ranges = <0 4>, <81 4>;

	i2c2_hid_active: i2c2-hid-active {
	pins = <37>;
	function = "gpio";

	input-enable;
	bias-pull-up;
	drive-strength = <2>;
	};

	i2c6_hid_active: i2c6-hid-active {
	pins = <125>;
	function = "gpio";

	input-enable;
	bias-pull-up;
	drive-strength = <2>;
	};

	i2c12_hid_active: i2c12-hid-active {
	pins = <92>;
	function = "gpio";

	input-enable;
	bias-pull-up;
	drive-strength = <2>;
	};
	+
	+ wcd_intr_default: wcd_intr_default {
	+ pins = <54>;
	+ function = "gpio";
	+
	+ input-enable;
	+ bias-pull-down;
	+ drive-strength = <2>;
	+ };
	};

	&uart6 {
	status = "okay";

	bluetooth {
	compatible = "qcom,wcn3990-bt";

	vddio-supply = <&vreg_s4a_1p8>;
	vddxo-supply = <&vreg_l7a_1p8>;
	vddrf-supply = <&vreg_l17a_1p3>;
	vddch0-supply = <&vreg_l25a_3p3>;
	max-speed = <3200000>;
	};
	};

	&ufs_mem_hc {
	status = "okay";

	vcc-supply = <&vreg_l20a_2p95>;
	vcc-max-microamp = <600000>;
	};

	&ufs_mem_phy {
	status = "okay";

	vdda-phy-supply = <&vdda_ufs1_core>;
	vdda-pll-supply = <&vdda_ufs1_1p2>;
	};

	&usb_1 {
	status = "okay";
	};

	&usb_1_dwc3 {
	dr_mode = "host";
	};

	&usb_1_hsphy {
	status = "okay";

	vdd-supply = <&vdda_usb1_ss_core>;
	vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
	vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;

	qcom,imp-res-offset-value = <8>;
	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
	qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
	qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
	};

	&usb_1_qmpphy {
	status = "okay";

	vdda-phy-supply = <&vdda_usb1_ss_1p2>;
	vdda-pll-supply = <&vdda_usb1_ss_core>;
	};

	&usb_2 {
	status = "okay";
	};

	&usb_2_dwc3 {
	dr_mode = "host";
	};

	&usb_2_hsphy {
	status = "okay";

	vdd-supply = <&vdda_usb2_ss_core>;
	vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
	vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;

	qcom,imp-res-offset-value = <8>;
	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
	};

	&usb_2_qmpphy {
	status = "okay";

	vdda-phy-supply = <&vdda_usb2_ss_1p2>;
	vdda-pll-supply = <&vdda_usb2_ss_core>;
	};
	+
	+&wcd9340{
	+ pinctrl-0 = <&wcd_intr_default>;
	+ pinctrl-names = "default";
	+ clock-names = "extclk";
	+ clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
	+ reset-gpios = <&tlmm 64 0>;
	+ vdd-buck-supply = <&vreg_s4a_1p8>;
	+ vdd-buck-sido-supply = <&vreg_s4a_1p8>;
	+ vdd-tx-supply = <&vreg_s4a_1p8>;
	+ vdd-rx-supply = <&vreg_s4a_1p8>;
	+ vdd-io-supply = <&vreg_s4a_1p8>;
	+
	+ swm: swm@c85 {
	+ left_spkr: wsa8810-left{
	+ compatible = "sdw10217211000";
	+ reg = <0 3>;
	+ powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>;
	+ #thermal-sensor-cells = <0>;
	+ sound-name-prefix = "SpkrLeft";
	+ #sound-dai-cells = <0>;
	+ };
	+
	+ right_spkr: wsa8810-right{
	+ compatible = "sdw10217211000";
	+ powerdown-gpios = <&wcdgpio 3 GPIO_ACTIVE_HIGH>;
	+ reg = <0 4>;
	+ #thermal-sensor-cells = <0>;
	+ sound-name-prefix = "SpkrRight";
	+ #sound-dai-cells = <0>;
	+ };
	+ };
	+};
	diff --git a/sys/gnu/dts/arm64/qcom/sm8250-mtp.dts b/sys/gnu/dts/arm64/qcom/sm8250-mtp.dts
	new file mode 100644
	index 000000000000..224d0f1ea6f9
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/qcom/sm8250-mtp.dts
	@@ -0,0 +1,29 @@
	+// SPDX-License-Identifier: BSD-3-Clause
	+/*
	+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
	+ */
	+
	+/dts-v1/;
	+
	+#include "sm8250.dtsi"
	+
	+/ {
	+ model = "Qualcomm Technologies, Inc. SM8250 MTP";
	+ compatible = "qcom,sm8250-mtp";
	+
	+ aliases {
	+ serial0 = &uart2;
	+ };
	+
	+ chosen {
	+ stdout-path = "serial0:115200n8";
	+ };
	+};
	+
	+&qupv3_id_1 {
	+ status = "okay";
	+};
	+
	+&uart2 {
	+ status = "okay";
	+};
	diff --git a/sys/gnu/dts/arm64/qcom/sm8250.dtsi b/sys/gnu/dts/arm64/qcom/sm8250.dtsi
	new file mode 100644
	index 000000000000..891d83b2afea
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/qcom/sm8250.dtsi
	@@ -0,0 +1,444 @@
	+// SPDX-License-Identifier: BSD-3-Clause
	+/*
	+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
	+ */
	+
	+#include <dt-bindings/interrupt-controller/arm-gic.h>
	+#include <dt-bindings/clock/qcom,rpmh.h>
	+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
	+
	+/ {
	+ interrupt-parent = <&intc>;
	+
	+ #address-cells = <2>;
	+ #size-cells = <2>;
	+
	+ chosen { };
	+
	+ clocks {
	+ xo_board: xo-board {
	+ compatible = "fixed-clock";
	+ #clock-cells = <0>;
	+ clock-frequency = <38400000>;
	+ clock-output-names = "xo_board";
	+ };
	+
	+ sleep_clk: sleep-clk {
	+ compatible = "fixed-clock";
	+ clock-frequency = <32000>;
	+ #clock-cells = <0>;
	+ };
	+ };
	+
	+ cpus {
	+ #address-cells = <2>;
	+ #size-cells = <0>;
	+
	+ CPU0: cpu@0 {
	+ device_type = "cpu";
	+ compatible = "qcom,kryo485";
	+ reg = <0x0 0x0>;
	+ enable-method = "psci";
	+ next-level-cache = <&L2_0>;
	+ L2_0: l2-cache {
	+ compatible = "cache";
	+ next-level-cache = <&L3_0>;
	+ L3_0: l3-cache {
	+ compatible = "cache";
	+ };
	+ };
	+ };
	+
	+ CPU1: cpu@100 {
	+ device_type = "cpu";
	+ compatible = "qcom,kryo485";
	+ reg = <0x0 0x100>;
	+ enable-method = "psci";
	+ next-level-cache = <&L2_100>;
	+ L2_100: l2-cache {
	+ compatible = "cache";
	+ next-level-cache = <&L3_0>;
	+ };
	+ };
	+
	+ CPU2: cpu@200 {
	+ device_type = "cpu";
	+ compatible = "qcom,kryo485";
	+ reg = <0x0 0x200>;
	+ enable-method = "psci";
	+ next-level-cache = <&L2_200>;
	+ L2_200: l2-cache {
	+ compatible = "cache";
	+ next-level-cache = <&L3_0>;
	+ };
	+ };
	+
	+ CPU3: cpu@300 {
	+ device_type = "cpu";
	+ compatible = "qcom,kryo485";
	+ reg = <0x0 0x300>;
	+ enable-method = "psci";
	+ next-level-cache = <&L2_300>;
	+ L2_300: l2-cache {
	+ compatible = "cache";
	+ next-level-cache = <&L3_0>;
	+ };
	+ };
	+
	+ CPU4: cpu@400 {
	+ device_type = "cpu";
	+ compatible = "qcom,kryo485";
	+ reg = <0x0 0x400>;
	+ enable-method = "psci";
	+ next-level-cache = <&L2_400>;
	+ L2_400: l2-cache {
	+ compatible = "cache";
	+ next-level-cache = <&L3_0>;
	+ };
	+ };
	+
	+ CPU5: cpu@500 {
	+ device_type = "cpu";
	+ compatible = "qcom,kryo485";
	+ reg = <0x0 0x500>;
	+ enable-method = "psci";
	+ next-level-cache = <&L2_500>;
	+ L2_500: l2-cache {
	+ compatible = "cache";
	+ next-level-cache = <&L3_0>;
	+ };
	+
	+ };
	+
	+ CPU6: cpu@600 {
	+ device_type = "cpu";
	+ compatible = "qcom,kryo485";
	+ reg = <0x0 0x600>;
	+ enable-method = "psci";
	+ next-level-cache = <&L2_600>;
	+ L2_600: l2-cache {
	+ compatible = "cache";
	+ next-level-cache = <&L3_0>;
	+ };
	+ };
	+
	+ CPU7: cpu@700 {
	+ device_type = "cpu";
	+ compatible = "qcom,kryo485";
	+ reg = <0x0 0x700>;
	+ enable-method = "psci";
	+ next-level-cache = <&L2_700>;
	+ L2_700: l2-cache {
	+ compatible = "cache";
	+ next-level-cache = <&L3_0>;
	+ };
	+ };
	+ };
	+
	+ firmware {
	+ scm: scm {
	+ compatible = "qcom,scm";
	+ #reset-cells = <1>;
	+ };
	+ };
	+
	+ tcsr_mutex: hwlock {
	+ compatible = "qcom,tcsr-mutex";
	+ syscon = <&tcsr_mutex_regs 0 0x1000>;
	+ #hwlock-cells = <1>;
	+ };
	+
	+ memory@80000000 {
	+ device_type = "memory";
	+ /* We expect the bootloader to fill in the size */
	+ reg = <0x0 0x80000000 0x0 0x0>;
	+ };
	+
	+ pmu {
	+ compatible = "arm,armv8-pmuv3";
	+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	+ };
	+
	+ psci {
	+ compatible = "arm,psci-1.0";
	+ method = "smc";
	+ };
	+
	+ reserved-memory {
	+ #address-cells = <2>;
	+ #size-cells = <2>;
	+ ranges;
	+
	+ hyp_mem: memory@80000000 {
	+ reg = <0x0 0x80000000 0x0 0x600000>;
	+ no-map;
	+ };
	+
	+ xbl_aop_mem: memory@80700000 {
	+ reg = <0x0 0x80700000 0x0 0x160000>;
	+ no-map;
	+ };
	+
	+ cmd_db: memory@80860000 {
	+ compatible = "qcom,cmd-db";
	+ reg = <0x0 0x80860000 0x0 0x20000>;
	+ no-map;
	+ };
	+
	+ smem_mem: memory@80900000 {
	+ reg = <0x0 0x80900000 0x0 0x200000>;
	+ no-map;
	+ };
	+
	+ removed_mem: memory@80b00000 {
	+ reg = <0x0 0x80b00000 0x0 0x5300000>;
	+ no-map;
	+ };
	+
	+ camera_mem: memory@86200000 {
	+ reg = <0x0 0x86200000 0x0 0x500000>;
	+ no-map;
	+ };
	+
	+ wlan_mem: memory@86700000 {
	+ reg = <0x0 0x86700000 0x0 0x100000>;
	+ no-map;
	+ };
	+
	+ ipa_fw_mem: memory@86800000 {
	+ reg = <0x0 0x86800000 0x0 0x10000>;
	+ no-map;
	+ };
	+
	+ ipa_gsi_mem: memory@86810000 {
	+ reg = <0x0 0x86810000 0x0 0xa000>;
	+ no-map;
	+ };
	+
	+ gpu_mem: memory@8681a000 {
	+ reg = <0x0 0x8681a000 0x0 0x2000>;
	+ no-map;
	+ };
	+
	+ npu_mem: memory@86900000 {
	+ reg = <0x0 0x86900000 0x0 0x500000>;
	+ no-map;
	+ };
	+
	+ video_mem: memory@86e00000 {
	+ reg = <0x0 0x86e00000 0x0 0x500000>;
	+ no-map;
	+ };
	+
	+ cvp_mem: memory@87300000 {
	+ reg = <0x0 0x87300000 0x0 0x500000>;
	+ no-map;
	+ };
	+
	+ cdsp_mem: memory@87800000 {
	+ reg = <0x0 0x87800000 0x0 0x1400000>;
	+ no-map;
	+ };
	+
	+ slpi_mem: memory@88c00000 {
	+ reg = <0x0 0x88c00000 0x0 0x1500000>;
	+ no-map;
	+ };
	+
	+ adsp_mem: memory@8a100000 {
	+ reg = <0x0 0x8a100000 0x0 0x1d00000>;
	+ no-map;
	+ };
	+
	+ spss_mem: memory@8be00000 {
	+ reg = <0x0 0x8be00000 0x0 0x100000>;
	+ no-map;
	+ };
	+
	+ cdsp_secure_heap: memory@8bf00000 {
	+ reg = <0x0 0x8bf00000 0x0 0x4600000>;
	+ no-map;
	+ };
	+ };
	+
	+ smem: qcom,smem {
	+ compatible = "qcom,smem";
	+ memory-region = <&smem_mem>;
	+ hwlocks = <&tcsr_mutex 3>;
	+ };
	+
	+ soc: soc@0 {
	+ #address-cells = <2>;
	+ #size-cells = <2>;
	+ ranges = <0 0 0 0 0x10 0>;
	+ dma-ranges = <0 0 0 0 0x10 0>;
	+ compatible = "simple-bus";
	+
	+ gcc: clock-controller@100000 {
	+ compatible = "qcom,gcc-sm8250";
	+ reg = <0x0 0x00100000 0x0 0x1f0000>;
	+ #clock-cells = <1>;
	+ #reset-cells = <1>;
	+ #power-domain-cells = <1>;
	+ clock-names = "bi_tcxo", "sleep_clk";
	+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
	+ };
	+
	+ qupv3_id_1: geniqup@ac0000 {
	+ compatible = "qcom,geni-se-qup";
	+ reg = <0x0 0x00ac0000 0x0 0x6000>;
	+ clock-names = "m-ahb", "s-ahb";
	+ clocks = <&gcc 133>, <&gcc 134>;
	+ #address-cells = <2>;
	+ #size-cells = <2>;
	+ ranges;
	+ status = "disabled";
	+
	+ uart2: serial@a90000 {
	+ compatible = "qcom,geni-debug-uart";
	+ reg = <0x0 0x00a90000 0x0 0x4000>;
	+ clock-names = "se";
	+ clocks = <&gcc 113>;
	+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	+ status = "disabled";
	+ };
	+ };
	+
	+ intc: interrupt-controller@17a00000 {
	+ compatible = "arm,gic-v3";
	+ #interrupt-cells = <3>;
	+ interrupt-controller;
	+ reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
	+ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
	+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	+ };
	+
	+ pdc: interrupt-controller@b220000 {
	+ compatible = "qcom,sm8250-pdc";
	+ reg = <0x0b220000 0x30000>, <0x17c000f0 0x60>;
	+ qcom,pdc-ranges = <0 480 94>, <94 609 31>,
	+ <125 63 1>, <126 716 12>;
	+ #interrupt-cells = <2>;
	+ interrupt-parent = <&intc>;
	+ interrupt-controller;
	+ };
	+
	+ spmi: qcom,spmi@c440000 {
	+ compatible = "qcom,spmi-pmic-arb";
	+ reg = <0x0 0x0c440000 0x0 0x0001100>,
	+ <0x0 0x0c600000 0x0 0x2000000>,
	+ <0x0 0x0e600000 0x0 0x0100000>,
	+ <0x0 0x0e700000 0x0 0x00a0000>,
	+ <0x0 0x0c40a000 0x0 0x0026000>;
	+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
	+ interrupt-names = "periph_irq";
	+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
	+ qcom,ee = <0>;
	+ qcom,channel = <0>;
	+ #address-cells = <2>;
	+ #size-cells = <0>;
	+ interrupt-controller;
	+ #interrupt-cells = <4>;
	+ };
	+
	+ apps_rsc: rsc@18200000 {
	+ label = "apps_rsc";
	+ compatible = "qcom,rpmh-rsc";
	+ reg = <0x0 0x18200000 0x0 0x10000>,
	+ <0x0 0x18210000 0x0 0x10000>,
	+ <0x0 0x18220000 0x0 0x10000>;
	+ reg-names = "drv-0", "drv-1", "drv-2";
	+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	+ qcom,tcs-offset = <0xd00>;
	+ qcom,drv-id = <2>;
	+ qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
	+ <WAKE_TCS 3>, <CONTROL_TCS 1>;
	+
	+ rpmhcc: clock-controller {
	+ compatible = "qcom,sm8250-rpmh-clk";
	+ #clock-cells = <1>;
	+ clock-names = "xo";
	+ clocks = <&xo_board>;
	+ };
	+ };
	+
	+ tcsr_mutex_regs: syscon@1f40000 {
	+ compatible = "syscon";
	+ reg = <0x0 0x01f40000 0x0 0x40000>;
	+ };
	+
	+ timer@17c20000 {
	+ #address-cells = <2>;
	+ #size-cells = <2>;
	+ ranges;
	+ compatible = "arm,armv7-timer-mem";
	+ reg = <0x0 0x17c20000 0x0 0x1000>;
	+ clock-frequency = <19200000>;
	+
	+ frame@17c21000 {
	+ frame-number = <0>;
	+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0 0x17c21000 0x0 0x1000>,
	+ <0x0 0x17c22000 0x0 0x1000>;
	+ };
	+
	+ frame@17c23000 {
	+ frame-number = <1>;
	+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0 0x17c23000 0x0 0x1000>;
	+ status = "disabled";
	+ };
	+
	+ frame@17c25000 {
	+ frame-number = <2>;
	+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0 0x17c25000 0x0 0x1000>;
	+ status = "disabled";
	+ };
	+
	+ frame@17c27000 {
	+ frame-number = <3>;
	+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0 0x17c27000 0x0 0x1000>;
	+ status = "disabled";
	+ };
	+
	+ frame@17c29000 {
	+ frame-number = <4>;
	+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0 0x17c29000 0x0 0x1000>;
	+ status = "disabled";
	+ };
	+
	+ frame@17c2b000 {
	+ frame-number = <5>;
	+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0 0x17c2b000 0x0 0x1000>;
	+ status = "disabled";
	+ };
	+
	+ frame@17c2d000 {
	+ frame-number = <6>;
	+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0 0x17c2d000 0x0 0x1000>;
	+ status = "disabled";
	+ };
	+ };
	+
	+ };
	+
	+ timer {
	+ compatible = "arm,armv8-timer";
	+ interrupts = <GIC_PPI 13
	+ (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	+ <GIC_PPI 14
	+ (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	+ <GIC_PPI 11
	+ (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	+ <GIC_PPI 12
	+ (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>;
	+ };
	+};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts b/sys/gnu/dts/arm64/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts
	new file mode 100644
	index 000000000000..2ab5edd84e9b
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts
	@@ -0,0 +1,52 @@
	+// SPDX-License-Identifier: GPL-2.0
	+/*
	+ * Device Tree Source for the HiHope RZ/G2M sub board connected to an
	+ * Advantech IDK-1110WR 10.1" LVDS panel
	+ *
	+ * Copyright (C) 2020 Renesas Electronics Corp.
	+ */
	+
	+#include "r8a774a1-hihope-rzg2m-ex.dts"
	+#include "rzg2-advantech-idk-1110wr-panel.dtsi"
	+
	+/ {
	+ backlight {
	+ compatible = "pwm-backlight";
	+ pwms = <&pwm0 0 50000>;
	+
	+ brightness-levels = <0 2 8 16 32 64 128 255>;
	+ default-brightness-level = <6>;
	+ };
	+
	+};
	+
	+&gpio1 {
	+ /*
	+ * When GP1_20 is LOW LVDS0 is connected to the LVDS connector
	+ * When GP1_20 is HIGH LVDS0 is connected to the LT8918L
	+ */
	+ lvds-connector-en-gpio {
	+ gpio-hog;
	+ gpios = <20 GPIO_ACTIVE_HIGH>;
	+ output-low;
	+ line-name = "lvds-connector-en-gpio";
	+ };
	+};
	+
	+&lvds0 {
	+ status = "okay";
	+};
	+
	+&pfc {
	+ pwm0_pins: pwm0 {
	+ groups = "pwm0";
	+ function = "pwm0";
	+ };
	+};
	+
	+&pwm0 {
	+ pinctrl-0 = <&pwm0_pins>;
	+ pinctrl-names = "default";
	+
	+ status = "okay";
	+};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a774a1.dtsi b/sys/gnu/dts/arm64/renesas/r8a774a1.dtsi
	index 8f950dabca54..79023433a740 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a774a1.dtsi
	+++ b/sys/gnu/dts/arm64/renesas/r8a774a1.dtsi
	@@ -1,2786 +1,2787 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the r8a774a1 SoC
	*
	* Copyright (C) 2018 Renesas Electronics Corp.
	*/

	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
	#include <dt-bindings/power/r8a774a1-sysc.h>

	/ {
	compatible = "renesas,r8a774a1";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	i2c6 = &i2c6;
	i2c7 = &i2c_dvfs;
	};

	/*
	* The external audio clocks are configured as 0 Hz fixed frequency
	* clocks by default.
	* Boards that provide audio clocks should override them.
	*/
	audio_clk_a: audio_clk_a {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_b: audio_clk_b {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_c: audio_clk_c {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	/* External CAN clock - to be overridden by boards that provide it */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	cluster0_opp: opp_table0 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-500000000 {
	opp-hz = /bits/ 64 <500000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1500000000 {
	opp-hz = /bits/ 64 <1500000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	};

	cluster1_opp: opp_table1 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-800000000 {
	opp-hz = /bits/ 64 <800000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu-map {
	cluster0 {
	core0 {
	cpu = <&a57_0>;
	};
	core1 {
	cpu = <&a57_1>;
	};
	};

	cluster1 {
	core0 {
	cpu = <&a53_0>;
	};
	core1 {
	cpu = <&a53_1>;
	};
	core2 {
	cpu = <&a53_2>;
	};
	core3 {
	cpu = <&a53_3>;
	};
	};
	};

	a57_0: cpu@0 {
	compatible = "arm,cortex-a57";
	reg = <0x0>;
	device_type = "cpu";
	power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
	next-level-cache = <&L2_CA57>;
	enable-method = "psci";
	dynamic-power-coefficient = <854>;
	clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
	operating-points-v2 = <&cluster0_opp>;
	capacity-dmips-mhz = <1024>;
	#cooling-cells = <2>;
	};

	a57_1: cpu@1 {
	compatible = "arm,cortex-a57";
	reg = <0x1>;
	device_type = "cpu";
	power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
	next-level-cache = <&L2_CA57>;
	enable-method = "psci";
	clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
	operating-points-v2 = <&cluster0_opp>;
	capacity-dmips-mhz = <1024>;
	#cooling-cells = <2>;
	};

	a53_0: cpu@100 {
	compatible = "arm,cortex-a53";
	reg = <0x100>;
	device_type = "cpu";
	power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	#cooling-cells = <2>;
	dynamic-power-coefficient = <277>;
	clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	capacity-dmips-mhz = <560>;
	};

	a53_1: cpu@101 {
	compatible = "arm,cortex-a53";
	reg = <0x101>;
	device_type = "cpu";
	power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	capacity-dmips-mhz = <560>;
	};

	a53_2: cpu@102 {
	compatible = "arm,cortex-a53";
	reg = <0x102>;
	device_type = "cpu";
	power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	capacity-dmips-mhz = <560>;
	};

	a53_3: cpu@103 {
	compatible = "arm,cortex-a53";
	reg = <0x103>;
	device_type = "cpu";
	power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	capacity-dmips-mhz = <560>;
	};

	L2_CA57: cache-controller-0 {
	compatible = "cache";
	power-domains = <&sysc R8A774A1_PD_CA57_SCU>;
	cache-unified;
	cache-level = <2>;
	};

	L2_CA53: cache-controller-1 {
	compatible = "cache";
	power-domains = <&sysc R8A774A1_PD_CA53_SCU>;
	cache-unified;
	cache-level = <2>;
	};
	};

	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	extalr_clk: extalr {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	/* External PCIe clock - can be overridden by the board */
	pcie_bus_clk: pcie_bus {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	pmu_a53 {
	compatible = "arm,cortex-a53-pmu";
	interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
	};

	pmu_a57 {
	compatible = "arm,cortex-a57-pmu";
	interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&a57_0>, <&a57_1>;
	};

	psci {
	compatible = "arm,psci-1.0", "arm,psci-0.2";
	method = "smc";
	};

	/* External SCIF clock - to be overridden by boards that provide it */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a774a1-wdt",
	"renesas,rcar-gen3-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a774a1",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 16>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a774a1",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 29>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a774a1",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 15>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a774a1",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 16>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a774a1",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 18>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a774a1",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	gpio6: gpio@e6055400 {
	compatible = "renesas,gpio-r8a774a1",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055400 0 0x50>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 192 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 906>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 906>;
	};

	gpio7: gpio@e6055800 {
	compatible = "renesas,gpio-r8a774a1",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055800 0 0x50>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 224 4>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 905>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 905>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a774a1";
	reg = <0 0xe6060000 0 0x50c>;
	};

	cmt0: timer@e60f0000 {
	compatible = "renesas,r8a774a1-cmt0",
	"renesas,rcar-gen3-cmt0";
	reg = <0 0xe60f0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 303>;
	clock-names = "fck";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 303>;
	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a774a1-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 302>;
	clock-names = "fck";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 302>;
	status = "disabled";
	};

	cmt2: timer@e6140000 {
	compatible = "renesas,r8a774a1-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6140000 0 0x1004>;
	interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 301>;
	clock-names = "fck";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 301>;
	status = "disabled";
	};

	cmt3: timer@e6148000 {
	compatible = "renesas,r8a774a1-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6148000 0 0x1004>;
	interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 300>;
	clock-names = "fck";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 300>;
	status = "disabled";
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a774a1-cpg-mssr";
	reg = <0 0xe6150000 0 0x0bb0>;
	clocks = <&extal_clk>, <&extalr_clk>;
	clock-names = "extal", "extalr";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a774a1-rst";
	reg = <0 0xe6160000 0 0x018c>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a774a1-sysc";
	reg = <0 0xe6180000 0 0x0400>;
	#power-domain-cells = <1>;
	};

	tsc: thermal@e6198000 {
	compatible = "renesas,r8a774a1-thermal";
	reg = <0 0xe6198000 0 0x100>,
	<0 0xe61a0000 0 0x100>,
	<0 0xe61a8000 0 0x100>;
	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 522>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 522>;
	#thermal-sensor-cells = <1>;
	};

	intc_ex: interrupt-controller@e61c0000 {
	compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	tmu0: timer@e61e0000 {
	compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
	reg = <0 0xe61e0000 0 0x30>;
	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 125>;
	clock-names = "fck";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 125>;
	status = "disabled";
	};

	tmu1: timer@e6fc0000 {
	compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
	reg = <0 0xe6fc0000 0 0x30>;
	interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 124>;
	clock-names = "fck";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 124>;
	status = "disabled";
	};

	tmu2: timer@e6fd0000 {
	compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
	reg = <0 0xe6fd0000 0 0x30>;
	interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 123>;
	clock-names = "fck";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 123>;
	status = "disabled";
	};

	tmu3: timer@e6fe0000 {
	compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
	reg = <0 0xe6fe0000 0 0x30>;
	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 122>;
	clock-names = "fck";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 122>;
	status = "disabled";
	};

	tmu4: timer@ffc00000 {
	compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
	reg = <0 0xffc00000 0 0x30>;
	interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 121>;
	clock-names = "fck";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 121>;
	status = "disabled";
	};

	i2c0: i2c@e6500000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774a1",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6500000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	dmas = <&dmac1 0x91>, <&dmac1 0x90>,
	<&dmac2 0x91>, <&dmac2 0x90>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c1: i2c@e6508000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774a1",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	dmas = <&dmac1 0x93>, <&dmac1 0x92>,
	<&dmac2 0x93>, <&dmac2 0x92>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c2: i2c@e6510000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774a1",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6510000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	dmas = <&dmac1 0x95>, <&dmac1 0x94>,
	<&dmac2 0x95>, <&dmac2 0x94>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c3: i2c@e66d0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774a1",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d0000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	dmas = <&dmac0 0x97>, <&dmac0 0x96>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c4: i2c@e66d8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774a1",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d8000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	dmas = <&dmac0 0x99>, <&dmac0 0x98>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c5: i2c@e66e0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774a1",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66e0000 0 0x40>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 919>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 919>;
	dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c6: i2c@e66e8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774a1",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66e8000 0 0x40>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 918>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 918>;
	dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c_dvfs: i2c@e60b0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a774a1",
	"renesas,rcar-gen3-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe60b0000 0 0x425>;
	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 926>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 926>;
	dmas = <&dmac0 0x11>, <&dmac0 0x10>;
	dma-names = "tx", "rx";
	status = "disabled";
	};

	hscif0: serial@e6540000 {
	compatible = "renesas,hscif-r8a774a1",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6540000 0 0x60>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 520>,
	<&cpg CPG_CORE R8A774A1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x31>, <&dmac1 0x30>,
	<&dmac2 0x31>, <&dmac2 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 520>;
	status = "disabled";
	};

	hscif1: serial@e6550000 {
	compatible = "renesas,hscif-r8a774a1",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6550000 0 0x60>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 519>,
	<&cpg CPG_CORE R8A774A1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x33>, <&dmac1 0x32>,
	<&dmac2 0x33>, <&dmac2 0x32>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 519>;
	status = "disabled";
	};

	hscif2: serial@e6560000 {
	compatible = "renesas,hscif-r8a774a1",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6560000 0 0x60>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 518>,
	<&cpg CPG_CORE R8A774A1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x35>, <&dmac1 0x34>,
	<&dmac2 0x35>, <&dmac2 0x34>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 518>;
	status = "disabled";
	};

	hscif3: serial@e66a0000 {
	compatible = "renesas,hscif-r8a774a1",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe66a0000 0 0x60>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 517>,
	<&cpg CPG_CORE R8A774A1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x37>, <&dmac0 0x36>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 517>;
	status = "disabled";
	};

	hscif4: serial@e66b0000 {
	compatible = "renesas,hscif-r8a774a1",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe66b0000 0 0x60>;
	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 516>,
	<&cpg CPG_CORE R8A774A1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x39>, <&dmac0 0x38>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 516>;
	status = "disabled";
	};

	hsusb: usb@e6590000 {
	compatible = "renesas,usbhs-r8a774a1",
	"renesas,rcar-gen3-usbhs";
	reg = <0 0xe6590000 0 0x200>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
	dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
	<&usb_dmac1 0>, <&usb_dmac1 1>;
	dma-names = "ch0", "ch1", "ch2", "ch3";
	renesas,buswait = <11>;
	phys = <&usb2_phy0 3>;
	phy-names = "usb";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 704>, <&cpg 703>;
	status = "disabled";
	};

	usb_dmac0: dma-controller@e65a0000 {
	compatible = "renesas,r8a774a1-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65a0000 0 0x100>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 330>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 330>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac1: dma-controller@e65b0000 {
	compatible = "renesas,r8a774a1-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65b0000 0 0x100>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 331>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 331>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb3_phy0: usb-phy@e65ee000 {
	compatible = "renesas,r8a774a1-usb3-phy",
	"renesas,rcar-gen3-usb3-phy";
	reg = <0 0xe65ee000 0 0x90>;
	clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
	<&usb_extal_clk>;
	clock-names = "usb3-if", "usb3s_clk", "usb_extal";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	#phy-cells = <0>;
	status = "disabled";
	};

	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a774a1",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x10000>;
	interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
	<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
	<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
	<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
	<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
	<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
	<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
	<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
	};

	dmac1: dma-controller@e7300000 {
	compatible = "renesas,dmac-r8a774a1",
	"renesas,rcar-dmac";
	reg = <0 0xe7300000 0 0x10000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
	<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
	<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
	<&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
	<&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
	<&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
	<&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
	<&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
	};

	dmac2: dma-controller@e7310000 {
	compatible = "renesas,dmac-r8a774a1",
	"renesas,rcar-dmac";
	reg = <0 0xe7310000 0 0x10000>;
	interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 217>;
	clock-names = "fck";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 217>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
	<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
	<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
	<&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
	<&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
	<&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
	<&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
	<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
	};

	ipmmu_ds0: mmu@e6740000 {
	compatible = "renesas,ipmmu-r8a774a1";
	reg = <0 0xe6740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 0>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_ds1: mmu@e7740000 {
	compatible = "renesas,ipmmu-r8a774a1";
	reg = <0 0xe7740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 1>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_hc: mmu@e6570000 {
	compatible = "renesas,ipmmu-r8a774a1";
	reg = <0 0xe6570000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 2>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_mm: mmu@e67b0000 {
	compatible = "renesas,ipmmu-r8a774a1";
	reg = <0 0xe67b0000 0 0x1000>;
	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_mp: mmu@ec670000 {
	compatible = "renesas,ipmmu-r8a774a1";
	reg = <0 0xec670000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 4>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_pv0: mmu@fd800000 {
	compatible = "renesas,ipmmu-r8a774a1";
	reg = <0 0xfd800000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 5>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_pv1: mmu@fd950000 {
	compatible = "renesas,ipmmu-r8a774a1";
	reg = <0 0xfd950000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 6>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vc0: mmu@fe6b0000 {
	compatible = "renesas,ipmmu-r8a774a1";
	reg = <0 0xfe6b0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 8>;
	power-domains = <&sysc R8A774A1_PD_A3VC>;
	#iommu-cells = <1>;
	};

	ipmmu_vi0: mmu@febd0000 {
	compatible = "renesas,ipmmu-r8a774a1";
	reg = <0 0xfebd0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 9>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a774a1",
	"renesas,etheravb-rcar-gen3";
	reg = <0 0xe6800000 0 0x800>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15",
	"ch16", "ch17", "ch18", "ch19",
	"ch20", "ch21", "ch22", "ch23",
	"ch24";
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	phy-mode = "rgmii";
	iommus = <&ipmmu_ds0 16>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	can0: can@e6c30000 {
	compatible = "renesas,can-r8a774a1",
	"renesas,rcar-gen3-can";
	reg = <0 0xe6c30000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 916>,
	<&cpg CPG_CORE R8A774A1_CLK_CANFD>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 916>;
	status = "disabled";
	};

	can1: can@e6c38000 {
	compatible = "renesas,can-r8a774a1",
	"renesas,rcar-gen3-can";
	reg = <0 0xe6c38000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 915>,
	<&cpg CPG_CORE R8A774A1_CLK_CANFD>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 915>;
	status = "disabled";
	};

	canfd: can@e66c0000 {
	compatible = "renesas,r8a774a1-canfd",
	"renesas,rcar-gen3-canfd";
	reg = <0 0xe66c0000 0 0x8000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 914>,
	<&cpg CPG_CORE R8A774A1_CLK_CANFD>,
	<&can_clk>;
	clock-names = "fck", "canfd", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 914>;
	status = "disabled";

	channel0 {
	status = "disabled";
	};

	channel1 {
	status = "disabled";
	};
	};

	pwm0: pwm@e6e30000 {
	compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
	reg = <0 0xe6e30000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm1: pwm@e6e31000 {
	compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
	reg = <0 0xe6e31000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm2: pwm@e6e32000 {
	compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
	reg = <0 0xe6e32000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm3: pwm@e6e33000 {
	compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
	reg = <0 0xe6e33000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm4: pwm@e6e34000 {
	compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
	reg = <0 0xe6e34000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm5: pwm@e6e35000 {
	compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
	reg = <0 0xe6e35000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm6: pwm@e6e36000 {
	compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
	reg = <0 0xe6e36000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a774a1",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e60000 0 0x40>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 207>,
	<&cpg CPG_CORE R8A774A1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x51>, <&dmac1 0x50>,
	<&dmac2 0x51>, <&dmac2 0x50>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 207>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a774a1",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e68000 0 0x40>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 206>,
	<&cpg CPG_CORE R8A774A1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x53>, <&dmac1 0x52>,
	<&dmac2 0x53>, <&dmac2 0x52>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 206>;
	status = "disabled";
	};

	scif2: serial@e6e88000 {
	compatible = "renesas,scif-r8a774a1",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e88000 0 0x40>;
	interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 310>,
	<&cpg CPG_CORE R8A774A1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x13>, <&dmac1 0x12>,
	<&dmac2 0x13>, <&dmac2 0x12>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 310>;
	status = "disabled";
	};

	scif3: serial@e6c50000 {
	compatible = "renesas,scif-r8a774a1",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6c50000 0 0x40>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 204>,
	<&cpg CPG_CORE R8A774A1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x57>, <&dmac0 0x56>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 204>;
	status = "disabled";
	};

	scif4: serial@e6c40000 {
	compatible = "renesas,scif-r8a774a1",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6c40000 0 0x40>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 203>,
	<&cpg CPG_CORE R8A774A1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x59>, <&dmac0 0x58>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 203>;
	status = "disabled";
	};

	scif5: serial@e6f30000 {
	compatible = "renesas,scif-r8a774a1",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6f30000 0 0x40>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 202>,
	<&cpg CPG_CORE R8A774A1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
	<&dmac2 0x5b>, <&dmac2 0x5a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 202>;
	status = "disabled";
	};

	msiof0: spi@e6e90000 {
	compatible = "renesas,msiof-r8a774a1",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6e90000 0 0x0064>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 211>;
	dmas = <&dmac1 0x41>, <&dmac1 0x40>,
	<&dmac2 0x41>, <&dmac2 0x40>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 211>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof1: spi@e6ea0000 {
	compatible = "renesas,msiof-r8a774a1",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6ea0000 0 0x0064>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 210>;
	dmas = <&dmac1 0x43>, <&dmac1 0x42>,
	<&dmac2 0x43>, <&dmac2 0x42>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 210>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof2: spi@e6c00000 {
	compatible = "renesas,msiof-r8a774a1",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c00000 0 0x0064>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 209>;
	dmas = <&dmac0 0x45>, <&dmac0 0x44>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 209>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof3: spi@e6c10000 {
	compatible = "renesas,msiof-r8a774a1",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c10000 0 0x0064>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 208>;
	dmas = <&dmac0 0x47>, <&dmac0 0x46>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 208>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	vin0: video@e6ef0000 {
	compatible = "renesas,vin-r8a774a1";
	reg = <0 0xe6ef0000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 811>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 811>;
	renesas,id = <0>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin0csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin0>;
	};
	vin0csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin0>;
	};
	};
	};
	};

	vin1: video@e6ef1000 {
	compatible = "renesas,vin-r8a774a1";
	reg = <0 0xe6ef1000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 810>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 810>;
	renesas,id = <1>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin1csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin1>;
	};
	vin1csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin1>;
	};
	};
	};
	};

	vin2: video@e6ef2000 {
	compatible = "renesas,vin-r8a774a1";
	reg = <0 0xe6ef2000 0 0x1000>;
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 809>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 809>;
	renesas,id = <2>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin2csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin2>;
	};
	vin2csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin2>;
	};
	};
	};
	};

	vin3: video@e6ef3000 {
	compatible = "renesas,vin-r8a774a1";
	reg = <0 0xe6ef3000 0 0x1000>;
	interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 808>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 808>;
	renesas,id = <3>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin3csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin3>;
	};
	vin3csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin3>;
	};
	};
	};
	};

	vin4: video@e6ef4000 {
	compatible = "renesas,vin-r8a774a1";
	reg = <0 0xe6ef4000 0 0x1000>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 807>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 807>;
	renesas,id = <4>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin4csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin4>;
	};
	vin4csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin4>;
	};
	};
	};
	};

	vin5: video@e6ef5000 {
	compatible = "renesas,vin-r8a774a1";
	reg = <0 0xe6ef5000 0 0x1000>;
	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 806>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 806>;
	renesas,id = <5>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin5csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin5>;
	};
	vin5csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin5>;
	};
	};
	};
	};

	vin6: video@e6ef6000 {
	compatible = "renesas,vin-r8a774a1";
	reg = <0 0xe6ef6000 0 0x1000>;
	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 805>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 805>;
	renesas,id = <6>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin6csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin6>;
	};
	vin6csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin6>;
	};
	};
	};
	};

	vin7: video@e6ef7000 {
	compatible = "renesas,vin-r8a774a1";
	reg = <0 0xe6ef7000 0 0x1000>;
	interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 804>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 804>;
	renesas,id = <7>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin7csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin7>;
	};
	vin7csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin7>;
	};
	};
	};
	};

	rcar_sound: sound@ec500000 {
	/*
	* #sound-dai-cells is required
	*
	* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
	* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
	*/
	/*
	* #clock-cells is required for audio_clkout0/1/2/3
	*
	* clkout : #clock-cells = <0>; <&rcar_sound>;
	* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
	*/
	compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
	reg = <0 0xec500000 0 0x1000>, /* SCU */
	<0 0xec5a0000 0 0x100>, /* ADG */
	<0 0xec540000 0 0x1000>, /* SSIU */
	<0 0xec541000 0 0x280>, /* SSI */
	<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
	reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

	clocks = <&cpg CPG_MOD 1005>,
	<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
	<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
	<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
	<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
	<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	<&audio_clk_a>, <&audio_clk_b>,
	<&audio_clk_c>,
	<&cpg CPG_CORE R8A774A1_CLK_S0D4>;
	clock-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0",
	"src.9", "src.8", "src.7", "src.6",
	"src.5", "src.4", "src.3", "src.2",
	"src.1", "src.0",
	"mix.1", "mix.0",
	"ctu.1", "ctu.0",
	"dvc.0", "dvc.1",
	"clk_a", "clk_b", "clk_c", "clk_i";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 1005>,
	<&cpg 1006>, <&cpg 1007>,
	<&cpg 1008>, <&cpg 1009>,
	<&cpg 1010>, <&cpg 1011>,
	<&cpg 1012>, <&cpg 1013>,
	<&cpg 1014>, <&cpg 1015>;
	reset-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0";
	status = "disabled";

	rcar_sound,ctu {
	ctu00: ctu-0 { };
	ctu01: ctu-1 { };
	ctu02: ctu-2 { };
	ctu03: ctu-3 { };
	ctu10: ctu-4 { };
	ctu11: ctu-5 { };
	ctu12: ctu-6 { };
	ctu13: ctu-7 { };
	};

	rcar_sound,dvc {
	dvc0: dvc-0 {
	dmas = <&audma1 0xbc>;
	dma-names = "tx";
	};
	dvc1: dvc-1 {
	dmas = <&audma1 0xbe>;
	dma-names = "tx";
	};
	};

	rcar_sound,mix {
	mix0: mix-0 { };
	mix1: mix-1 { };
	};

	rcar_sound,src {
	src0: src-0 {
	interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x85>, <&audma1 0x9a>;
	dma-names = "rx", "tx";
	};
	src1: src-1 {
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x87>, <&audma1 0x9c>;
	dma-names = "rx", "tx";
	};
	src2: src-2 {
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x89>, <&audma1 0x9e>;
	dma-names = "rx", "tx";
	};
	src3: src-3 {
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8b>, <&audma1 0xa0>;
	dma-names = "rx", "tx";
	};
	src4: src-4 {
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8d>, <&audma1 0xb0>;
	dma-names = "rx", "tx";
	};
	src5: src-5 {
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8f>, <&audma1 0xb2>;
	dma-names = "rx", "tx";
	};
	src6: src-6 {
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x91>, <&audma1 0xb4>;
	dma-names = "rx", "tx";
	};
	src7: src-7 {
	interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x93>, <&audma1 0xb6>;
	dma-names = "rx", "tx";
	};
	src8: src-8 {
	interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x95>, <&audma1 0xb8>;
	dma-names = "rx", "tx";
	};
	src9: src-9 {
	interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x97>, <&audma1 0xba>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssi {
	ssi0: ssi-0 {
	interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x01>, <&audma1 0x02>;
	dma-names = "rx", "tx";
	};
	ssi1: ssi-1 {
	interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x03>, <&audma1 0x04>;
	dma-names = "rx", "tx";
	};
	ssi2: ssi-2 {
	interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x05>, <&audma1 0x06>;
	dma-names = "rx", "tx";
	};
	ssi3: ssi-3 {
	interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x07>, <&audma1 0x08>;
	dma-names = "rx", "tx";
	};
	ssi4: ssi-4 {
	interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x09>, <&audma1 0x0a>;
	dma-names = "rx", "tx";
	};
	ssi5: ssi-5 {
	interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0b>, <&audma1 0x0c>;
	dma-names = "rx", "tx";
	};
	ssi6: ssi-6 {
	interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0d>, <&audma1 0x0e>;
	dma-names = "rx", "tx";
	};
	ssi7: ssi-7 {
	interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0f>, <&audma1 0x10>;
	dma-names = "rx", "tx";
	};
	ssi8: ssi-8 {
	interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x11>, <&audma1 0x12>;
	dma-names = "rx", "tx";
	};
	ssi9: ssi-9 {
	interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x13>, <&audma1 0x14>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssiu {
	ssiu00: ssiu-0 {
	dmas = <&audma0 0x15>, <&audma1 0x16>;
	dma-names = "rx", "tx";
	};
	ssiu01: ssiu-1 {
	dmas = <&audma0 0x35>, <&audma1 0x36>;
	dma-names = "rx", "tx";
	};
	ssiu02: ssiu-2 {
	dmas = <&audma0 0x37>, <&audma1 0x38>;
	dma-names = "rx", "tx";
	};
	ssiu03: ssiu-3 {
	dmas = <&audma0 0x47>, <&audma1 0x48>;
	dma-names = "rx", "tx";
	};
	ssiu04: ssiu-4 {
	dmas = <&audma0 0x3F>, <&audma1 0x40>;
	dma-names = "rx", "tx";
	};
	ssiu05: ssiu-5 {
	dmas = <&audma0 0x43>, <&audma1 0x44>;
	dma-names = "rx", "tx";
	};
	ssiu06: ssiu-6 {
	dmas = <&audma0 0x4F>, <&audma1 0x50>;
	dma-names = "rx", "tx";
	};
	ssiu07: ssiu-7 {
	dmas = <&audma0 0x53>, <&audma1 0x54>;
	dma-names = "rx", "tx";
	};
	ssiu10: ssiu-8 {
	dmas = <&audma0 0x49>, <&audma1 0x4a>;
	dma-names = "rx", "tx";
	};
	ssiu11: ssiu-9 {
	dmas = <&audma0 0x4B>, <&audma1 0x4C>;
	dma-names = "rx", "tx";
	};
	ssiu12: ssiu-10 {
	dmas = <&audma0 0x57>, <&audma1 0x58>;
	dma-names = "rx", "tx";
	};
	ssiu13: ssiu-11 {
	dmas = <&audma0 0x59>, <&audma1 0x5A>;
	dma-names = "rx", "tx";
	};
	ssiu14: ssiu-12 {
	dmas = <&audma0 0x5F>, <&audma1 0x60>;
	dma-names = "rx", "tx";
	};
	ssiu15: ssiu-13 {
	dmas = <&audma0 0xC3>, <&audma1 0xC4>;
	dma-names = "rx", "tx";
	};
	ssiu16: ssiu-14 {
	dmas = <&audma0 0xC7>, <&audma1 0xC8>;
	dma-names = "rx", "tx";
	};
	ssiu17: ssiu-15 {
	dmas = <&audma0 0xCB>, <&audma1 0xCC>;
	dma-names = "rx", "tx";
	};
	ssiu20: ssiu-16 {
	dmas = <&audma0 0x63>, <&audma1 0x64>;
	dma-names = "rx", "tx";
	};
	ssiu21: ssiu-17 {
	dmas = <&audma0 0x67>, <&audma1 0x68>;
	dma-names = "rx", "tx";
	};
	ssiu22: ssiu-18 {
	dmas = <&audma0 0x6B>, <&audma1 0x6C>;
	dma-names = "rx", "tx";
	};
	ssiu23: ssiu-19 {
	dmas = <&audma0 0x6D>, <&audma1 0x6E>;
	dma-names = "rx", "tx";
	};
	ssiu24: ssiu-20 {
	dmas = <&audma0 0xCF>, <&audma1 0xCE>;
	dma-names = "rx", "tx";
	};
	ssiu25: ssiu-21 {
	dmas = <&audma0 0xEB>, <&audma1 0xEC>;
	dma-names = "rx", "tx";
	};
	ssiu26: ssiu-22 {
	dmas = <&audma0 0xED>, <&audma1 0xEE>;
	dma-names = "rx", "tx";
	};
	ssiu27: ssiu-23 {
	dmas = <&audma0 0xEF>, <&audma1 0xF0>;
	dma-names = "rx", "tx";
	};
	ssiu30: ssiu-24 {
	dmas = <&audma0 0x6f>, <&audma1 0x70>;
	dma-names = "rx", "tx";
	};
	ssiu31: ssiu-25 {
	dmas = <&audma0 0x21>, <&audma1 0x22>;
	dma-names = "rx", "tx";
	};
	ssiu32: ssiu-26 {
	dmas = <&audma0 0x23>, <&audma1 0x24>;
	dma-names = "rx", "tx";
	};
	ssiu33: ssiu-27 {
	dmas = <&audma0 0x25>, <&audma1 0x26>;
	dma-names = "rx", "tx";
	};
	ssiu34: ssiu-28 {
	dmas = <&audma0 0x27>, <&audma1 0x28>;
	dma-names = "rx", "tx";
	};
	ssiu35: ssiu-29 {
	dmas = <&audma0 0x29>, <&audma1 0x2A>;
	dma-names = "rx", "tx";
	};
	ssiu36: ssiu-30 {
	dmas = <&audma0 0x2B>, <&audma1 0x2C>;
	dma-names = "rx", "tx";
	};
	ssiu37: ssiu-31 {
	dmas = <&audma0 0x2D>, <&audma1 0x2E>;
	dma-names = "rx", "tx";
	};
	ssiu40: ssiu-32 {
	dmas = <&audma0 0x71>, <&audma1 0x72>;
	dma-names = "rx", "tx";
	};
	ssiu41: ssiu-33 {
	dmas = <&audma0 0x17>, <&audma1 0x18>;
	dma-names = "rx", "tx";
	};
	ssiu42: ssiu-34 {
	dmas = <&audma0 0x19>, <&audma1 0x1A>;
	dma-names = "rx", "tx";
	};
	ssiu43: ssiu-35 {
	dmas = <&audma0 0x1B>, <&audma1 0x1C>;
	dma-names = "rx", "tx";
	};
	ssiu44: ssiu-36 {
	dmas = <&audma0 0x1D>, <&audma1 0x1E>;
	dma-names = "rx", "tx";
	};
	ssiu45: ssiu-37 {
	dmas = <&audma0 0x1F>, <&audma1 0x20>;
	dma-names = "rx", "tx";
	};
	ssiu46: ssiu-38 {
	dmas = <&audma0 0x31>, <&audma1 0x32>;
	dma-names = "rx", "tx";
	};
	ssiu47: ssiu-39 {
	dmas = <&audma0 0x33>, <&audma1 0x34>;
	dma-names = "rx", "tx";
	};
	ssiu50: ssiu-40 {
	dmas = <&audma0 0x73>, <&audma1 0x74>;
	dma-names = "rx", "tx";
	};
	ssiu60: ssiu-41 {
	dmas = <&audma0 0x75>, <&audma1 0x76>;
	dma-names = "rx", "tx";
	};
	ssiu70: ssiu-42 {
	dmas = <&audma0 0x79>, <&audma1 0x7a>;
	dma-names = "rx", "tx";
	};
	ssiu80: ssiu-43 {
	dmas = <&audma0 0x7b>, <&audma1 0x7c>;
	dma-names = "rx", "tx";
	};
	ssiu90: ssiu-44 {
	dmas = <&audma0 0x7d>, <&audma1 0x7e>;
	dma-names = "rx", "tx";
	};
	ssiu91: ssiu-45 {
	dmas = <&audma0 0x7F>, <&audma1 0x80>;
	dma-names = "rx", "tx";
	};
	ssiu92: ssiu-46 {
	dmas = <&audma0 0x81>, <&audma1 0x82>;
	dma-names = "rx", "tx";
	};
	ssiu93: ssiu-47 {
	dmas = <&audma0 0x83>, <&audma1 0x84>;
	dma-names = "rx", "tx";
	};
	ssiu94: ssiu-48 {
	dmas = <&audma0 0xA3>, <&audma1 0xA4>;
	dma-names = "rx", "tx";
	};
	ssiu95: ssiu-49 {
	dmas = <&audma0 0xA5>, <&audma1 0xA6>;
	dma-names = "rx", "tx";
	};
	ssiu96: ssiu-50 {
	dmas = <&audma0 0xA7>, <&audma1 0xA8>;
	dma-names = "rx", "tx";
	};
	ssiu97: ssiu-51 {
	dmas = <&audma0 0xA9>, <&audma1 0xAA>;
	dma-names = "rx", "tx";
	};
	};
	};

	audma0: dma-controller@ec700000 {
	compatible = "renesas,dmac-r8a774a1",
	"renesas,rcar-dmac";
	reg = <0 0xec700000 0 0x10000>;
	interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 502>;
	clock-names = "fck";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 502>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
	<&ipmmu_mp 2>, <&ipmmu_mp 3>,
	<&ipmmu_mp 4>, <&ipmmu_mp 5>,
	<&ipmmu_mp 6>, <&ipmmu_mp 7>,
	<&ipmmu_mp 8>, <&ipmmu_mp 9>,
	<&ipmmu_mp 10>, <&ipmmu_mp 11>,
	<&ipmmu_mp 12>, <&ipmmu_mp 13>,
	<&ipmmu_mp 14>, <&ipmmu_mp 15>;
	};

	audma1: dma-controller@ec720000 {
	compatible = "renesas,dmac-r8a774a1",
	"renesas,rcar-dmac";
	reg = <0 0xec720000 0 0x10000>;
	interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 501>;
	clock-names = "fck";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 501>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
	<&ipmmu_mp 18>, <&ipmmu_mp 19>,
	<&ipmmu_mp 20>, <&ipmmu_mp 21>,
	<&ipmmu_mp 22>, <&ipmmu_mp 23>,
	<&ipmmu_mp 24>, <&ipmmu_mp 25>,
	<&ipmmu_mp 26>, <&ipmmu_mp 27>,
	<&ipmmu_mp 28>, <&ipmmu_mp 29>,
	<&ipmmu_mp 30>, <&ipmmu_mp 31>;
	};

	xhci0: usb@ee000000 {
	compatible = "renesas,xhci-r8a774a1",
	"renesas,rcar-gen3-xhci";
	reg = <0 0xee000000 0 0xc00>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	status = "disabled";
	};

	usb3_peri0: usb@ee020000 {
	compatible = "renesas,r8a774a1-usb3-peri",
	"renesas,rcar-gen3-usb3-peri";
	reg = <0 0xee020000 0 0x400>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	status = "disabled";
	};

	ohci0: usb@ee080000 {
	compatible = "generic-ohci";
	reg = <0 0xee080000 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	phys = <&usb2_phy0 1>;
	phy-names = "usb";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	status = "disabled";
	};

	ohci1: usb@ee0a0000 {
	compatible = "generic-ohci";
	reg = <0 0xee0a0000 0 0x100>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 702>;
	phys = <&usb2_phy1 1>;
	phy-names = "usb";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 702>;
	status = "disabled";
	};

	ehci0: usb@ee080100 {
	compatible = "generic-ehci";
	reg = <0 0xee080100 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	phys = <&usb2_phy0 2>;
	phy-names = "usb";
	companion = <&ohci0>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	status = "disabled";
	};

	ehci1: usb@ee0a0100 {
	compatible = "generic-ehci";
	reg = <0 0xee0a0100 0 0x100>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 702>;
	phys = <&usb2_phy1 2>;
	phy-names = "usb";
	companion = <&ohci1>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 702>;
	status = "disabled";
	};

	usb2_phy0: usb-phy@ee080200 {
	compatible = "renesas,usb2-phy-r8a774a1",
	"renesas,rcar-gen3-usb2-phy";
	reg = <0 0xee080200 0 0x700>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	#phy-cells = <1>;
	status = "disabled";
	};

	usb2_phy1: usb-phy@ee0a0200 {
	compatible = "renesas,usb2-phy-r8a774a1",
	"renesas,rcar-gen3-usb2-phy";
	reg = <0 0xee0a0200 0 0x700>;
	clocks = <&cpg CPG_MOD 702>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 702>;
	#phy-cells = <1>;
	status = "disabled";
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a774a1",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee100000 0 0x2000>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	status = "disabled";
	};

	sdhi1: sd@ee120000 {
	compatible = "renesas,sdhi-r8a774a1",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee120000 0 0x2000>;
	interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 313>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 313>;
	status = "disabled";
	};

	sdhi2: sd@ee140000 {
	compatible = "renesas,sdhi-r8a774a1",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee140000 0 0x2000>;
	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 312>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 312>;
	status = "disabled";
	};

	sdhi3: sd@ee160000 {
	compatible = "renesas,sdhi-r8a774a1",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee160000 0 0x2000>;
	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 311>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 311>;
	status = "disabled";
	};

	gic: interrupt-controller@f1010000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x0 0xf1010000 0 0x1000>,
	<0x0 0xf1020000 0 0x20000>,
	<0x0 0xf1040000 0 0x20000>,
	<0x0 0xf1060000 0 0x20000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	pciec0: pcie@fe000000 {
	compatible = "renesas,pcie-r8a774a1",
	"renesas,pcie-rcar-gen3";
	reg = <0 0xfe000000 0 0x80000>;
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x00 0xff>;
	device_type = "pci";
	ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
	<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
	<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
	<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
	/* Map all possible DDR as inbound ranges */
	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
	clock-names = "pcie", "pcie_bus";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 319>;
	status = "disabled";
	};

	pciec1: pcie@ee800000 {
	compatible = "renesas,pcie-r8a774a1",
	"renesas,pcie-rcar-gen3";
	reg = <0 0xee800000 0 0x80000>;
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x00 0xff>;
	device_type = "pci";
	ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
	<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
	<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
	<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
	/* Map all possible DDR as inbound ranges */
	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
	clock-names = "pcie", "pcie_bus";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 318>;
	status = "disabled";
	};

	fdp1@fe940000 {
	compatible = "renesas,fdp1";
	reg = <0 0xfe940000 0 0x2400>;
	interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 119>;
	power-domains = <&sysc R8A774A1_PD_A3VC>;
	resets = <&cpg 119>;
	renesas,fcp = <&fcpf0>;
	};

	fcpf0: fcp@fe950000 {
	compatible = "renesas,fcpf";
	reg = <0 0xfe950000 0 0x200>;
	clocks = <&cpg CPG_MOD 615>;
	power-domains = <&sysc R8A774A1_PD_A3VC>;
	resets = <&cpg 615>;
	};

	fcpvb0: fcp@fe96f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe96f000 0 0x200>;
	clocks = <&cpg CPG_MOD 607>;
	power-domains = <&sysc R8A774A1_PD_A3VC>;
	resets = <&cpg 607>;
	};

	fcpvd0: fcp@fea27000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea27000 0 0x200>;
	clocks = <&cpg CPG_MOD 603>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 603>;
	iommus = <&ipmmu_vi0 8>;
	};

	fcpvd1: fcp@fea2f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea2f000 0 0x200>;
	clocks = <&cpg CPG_MOD 602>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 602>;
	iommus = <&ipmmu_vi0 9>;
	};

	fcpvd2: fcp@fea37000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea37000 0 0x200>;
	clocks = <&cpg CPG_MOD 601>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 601>;
	iommus = <&ipmmu_vi0 10>;
	};

	fcpvi0: fcp@fe9af000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe9af000 0 0x200>;
	clocks = <&cpg CPG_MOD 611>;
	power-domains = <&sysc R8A774A1_PD_A3VC>;
	resets = <&cpg 611>;
	iommus = <&ipmmu_vc0 19>;
	};

	vspb: vsp@fe960000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe960000 0 0x8000>;
	interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 626>;
	power-domains = <&sysc R8A774A1_PD_A3VC>;
	resets = <&cpg 626>;

	renesas,fcp = <&fcpvb0>;
	};

	vspd0: vsp@fea20000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea20000 0 0x5000>;
	interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 623>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 623>;

	renesas,fcp = <&fcpvd0>;
	};

	vspd1: vsp@fea28000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea28000 0 0x5000>;
	interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 622>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 622>;

	renesas,fcp = <&fcpvd1>;
	};

	vspd2: vsp@fea30000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea30000 0 0x5000>;
	interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 621>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 621>;

	renesas,fcp = <&fcpvd2>;
	};

	vspi0: vsp@fe9a0000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe9a0000 0 0x8000>;
	interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 631>;
	power-domains = <&sysc R8A774A1_PD_A3VC>;
	resets = <&cpg 631>;

	renesas,fcp = <&fcpvi0>;
	};

	csi20: csi2@fea80000 {
	compatible = "renesas,r8a774a1-csi2";
	reg = <0 0xfea80000 0 0x10000>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 714>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 714>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	csi20vin0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vin0csi20>;
	};
	csi20vin1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vin1csi20>;
	};
	csi20vin2: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&vin2csi20>;
	};
	csi20vin3: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&vin3csi20>;
	};
	csi20vin4: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&vin4csi20>;
	};
	csi20vin5: endpoint@5 {
	reg = <5>;
	remote-endpoint = <&vin5csi20>;
	};
	csi20vin6: endpoint@6 {
	reg = <6>;
	remote-endpoint = <&vin6csi20>;
	};
	csi20vin7: endpoint@7 {
	reg = <7>;
	remote-endpoint = <&vin7csi20>;
	};
	};
	};
	};

	csi40: csi2@feaa0000 {
	compatible = "renesas,r8a774a1-csi2";
	reg = <0 0xfeaa0000 0 0x10000>;
	interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	csi40vin0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vin0csi40>;
	};
	csi40vin1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vin1csi40>;
	};
	csi40vin2: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&vin2csi40>;
	};
	csi40vin3: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&vin3csi40>;
	};
	csi40vin4: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&vin4csi40>;
	};
	csi40vin5: endpoint@5 {
	reg = <5>;
	remote-endpoint = <&vin5csi40>;
	};
	csi40vin6: endpoint@6 {
	reg = <6>;
	remote-endpoint = <&vin6csi40>;
	};
	csi40vin7: endpoint@7 {
	reg = <7>;
	remote-endpoint = <&vin7csi40>;
	};
	};

	};
	};

	hdmi0: hdmi@fead0000 {
	compatible = "renesas,r8a774a1-hdmi",
	"renesas,rcar-gen3-hdmi";
	reg = <0 0xfead0000 0 0x10000>;
	interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 729>,
	<&cpg CPG_CORE R8A774A1_CLK_HDMI>;
	clock-names = "iahb", "isfr";
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 729>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;
	port@0 {
	reg = <0>;
	dw_hdmi0_in: endpoint {
	remote-endpoint = <&du_out_hdmi0>;
	};
	};
	port@1 {
	reg = <1>;
	};
	port@2 {
	/* HDMI sound */
	reg = <2>;
	};
	};
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a774a1";
	reg = <0 0xfeb00000 0 0x70000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&cpg CPG_MOD 724>,
	- <&cpg CPG_MOD 723>,
	+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
	<&cpg CPG_MOD 722>;
	clock-names = "du.0", "du.1", "du.2";
	+ resets = <&cpg 724>, <&cpg 722>;
	+ reset-names = "du.0", "du.2";
	status = "disabled";

	- vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
	+ renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb: endpoint {
	};
	};
	port@1 {
	reg = <1>;
	du_out_hdmi0: endpoint {
	remote-endpoint = <&dw_hdmi0_in>;
	};
	};
	port@2 {
	reg = <2>;
	du_out_lvds0: endpoint {
	remote-endpoint = <&lvds0_in>;
	};
	};
	};
	};

	lvds0: lvds@feb90000 {
	compatible = "renesas,r8a774a1-lvds";
	reg = <0 0xfeb90000 0 0x14>;
	clocks = <&cpg CPG_MOD 727>;
	power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
	resets = <&cpg 727>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds0_in: endpoint {
	remote-endpoint = <&du_out_lvds0>;
	};
	};
	port@1 {
	reg = <1>;
	lvds0_out: endpoint {
	};
	};
	};
	};

	prr: chipid@fff00044 {
	compatible = "renesas,prr";
	reg = <0 0xfff00044 0 4>;
	};
	};

	thermal-zones {
	sensor_thermal1: sensor-thermal1 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&tsc 0>;
	sustainable-power = <3874>;

	trips {
	sensor1_crit: sensor1-crit {
	temperature = <120000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};
	};

	sensor_thermal2: sensor-thermal2 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&tsc 1>;
	sustainable-power = <3874>;

	trips {
	sensor2_crit: sensor2-crit {
	temperature = <120000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};
	};

	sensor_thermal3: sensor-thermal3 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&tsc 2>;
	sustainable-power = <3874>;

	cooling-maps {
	map0 {
	trip = <&target>;
	cooling-device = <&a57_0 0 2>;
	contribution = <1024>;
	};
	map1 {
	trip = <&target>;
	cooling-device = <&a53_0 0 2>;
	contribution = <1024>;
	};
	};
	trips {
	target: trip-point1 {
	temperature = <100000>;
	hysteresis = <1000>;
	type = "passive";
	};

	sensor3_crit: sensor3-crit {
	temperature = <120000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clocks - can be overridden by the board */
	usb3s0_clk: usb3s0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	usb_extal_clk: usb_extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a774b1.dtsi b/sys/gnu/dts/arm64/renesas/r8a774b1.dtsi
	index c40ea300968e..3137f735974b 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a774b1.dtsi
	+++ b/sys/gnu/dts/arm64/renesas/r8a774b1.dtsi
	@@ -1,2627 +1,2628 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the r8a774b1 SoC
	*
	* Copyright (C) 2019 Renesas Electronics Corp.
	*/

	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
	#include <dt-bindings/power/r8a774b1-sysc.h>

	/ {
	compatible = "renesas,r8a774b1";
	#address-cells = <2>;
	#size-cells = <2>;

	/*
	* The external audio clocks are configured as 0 Hz fixed frequency
	* clocks by default.
	* Boards that provide audio clocks should override them.
	*/
	audio_clk_a: audio_clk_a {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_b: audio_clk_b {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_c: audio_clk_c {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	/* External CAN clock - to be overridden by boards that provide it */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	cluster0_opp: opp_table0 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-500000000 {
	opp-hz = /bits/ 64 <500000000>;
	opp-microvolt = <830000>;
	clock-latency-ns = <300000>;
	};
	opp-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	opp-microvolt = <830000>;
	clock-latency-ns = <300000>;
	};
	opp-1500000000 {
	opp-hz = /bits/ 64 <1500000000>;
	opp-microvolt = <830000>;
	clock-latency-ns = <300000>;
	opp-suspend;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	a57_0: cpu@0 {
	compatible = "arm,cortex-a57";
	reg = <0x0>;
	device_type = "cpu";
	power-domains = <&sysc R8A774B1_PD_CA57_CPU0>;
	next-level-cache = <&L2_CA57>;
	enable-method = "psci";
	#cooling-cells = <2>;
	dynamic-power-coefficient = <854>;
	clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
	operating-points-v2 = <&cluster0_opp>;
	};

	a57_1: cpu@1 {
	compatible = "arm,cortex-a57";
	reg = <0x1>;
	device_type = "cpu";
	power-domains = <&sysc R8A774B1_PD_CA57_CPU1>;
	next-level-cache = <&L2_CA57>;
	enable-method = "psci";
	clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
	operating-points-v2 = <&cluster0_opp>;
	};

	L2_CA57: cache-controller-0 {
	compatible = "cache";
	power-domains = <&sysc R8A774B1_PD_CA57_SCU>;
	cache-unified;
	cache-level = <2>;
	};
	};

	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	extalr_clk: extalr {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	/* External PCIe clock - can be overridden by the board */
	pcie_bus_clk: pcie_bus {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	pmu_a57 {
	compatible = "arm,cortex-a57-pmu";
	interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&a57_0>, <&a57_1>;
	};

	psci {
	compatible = "arm,psci-1.0", "arm,psci-0.2";
	method = "smc";
	};

	/* External SCIF clock - to be overridden by boards that provide it */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a774b1-wdt",
	"renesas,rcar-gen3-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a774b1",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 16>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a774b1",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 29>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a774b1",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 15>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a774b1",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 16>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a774b1",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 18>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a774b1",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	gpio6: gpio@e6055400 {
	compatible = "renesas,gpio-r8a774b1",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055400 0 0x50>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 192 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 906>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 906>;
	};

	gpio7: gpio@e6055800 {
	compatible = "renesas,gpio-r8a774b1",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055800 0 0x50>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 224 4>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 905>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 905>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a774b1";
	reg = <0 0xe6060000 0 0x50c>;
	};

	cmt0: timer@e60f0000 {
	compatible = "renesas,r8a774b1-cmt0",
	"renesas,rcar-gen3-cmt0";
	reg = <0 0xe60f0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 303>;
	clock-names = "fck";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 303>;
	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a774b1-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 302>;
	clock-names = "fck";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 302>;
	status = "disabled";
	};

	cmt2: timer@e6140000 {
	compatible = "renesas,r8a774b1-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6140000 0 0x1004>;
	interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 301>;
	clock-names = "fck";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 301>;
	status = "disabled";
	};

	cmt3: timer@e6148000 {
	compatible = "renesas,r8a774b1-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6148000 0 0x1004>;
	interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 300>;
	clock-names = "fck";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 300>;
	status = "disabled";
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a774b1-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>, <&extalr_clk>;
	clock-names = "extal", "extalr";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a774b1-rst";
	reg = <0 0xe6160000 0 0x0200>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a774b1-sysc";
	reg = <0 0xe6180000 0 0x0400>;
	#power-domain-cells = <1>;
	};

	tsc: thermal@e6198000 {
	compatible = "renesas,r8a774b1-thermal";
	reg = <0 0xe6198000 0 0x100>,
	<0 0xe61a0000 0 0x100>,
	<0 0xe61a8000 0 0x100>;
	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 522>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 522>;
	#thermal-sensor-cells = <1>;
	};

	intc_ex: interrupt-controller@e61c0000 {
	compatible = "renesas,intc-ex-r8a774b1", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	tmu0: timer@e61e0000 {
	compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
	reg = <0 0xe61e0000 0 0x30>;
	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 125>;
	clock-names = "fck";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 125>;
	status = "disabled";
	};

	tmu1: timer@e6fc0000 {
	compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
	reg = <0 0xe6fc0000 0 0x30>;
	interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 124>;
	clock-names = "fck";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 124>;
	status = "disabled";
	};

	tmu2: timer@e6fd0000 {
	compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
	reg = <0 0xe6fd0000 0 0x30>;
	interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 123>;
	clock-names = "fck";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 123>;
	status = "disabled";
	};

	tmu3: timer@e6fe0000 {
	compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
	reg = <0 0xe6fe0000 0 0x30>;
	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 122>;
	clock-names = "fck";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 122>;
	status = "disabled";
	};

	tmu4: timer@ffc00000 {
	compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
	reg = <0 0xffc00000 0 0x30>;
	interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 121>;
	clock-names = "fck";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 121>;
	status = "disabled";
	};

	i2c0: i2c@e6500000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774b1",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6500000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	dmas = <&dmac1 0x91>, <&dmac1 0x90>,
	<&dmac2 0x91>, <&dmac2 0x90>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c1: i2c@e6508000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774b1",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	dmas = <&dmac1 0x93>, <&dmac1 0x92>,
	<&dmac2 0x93>, <&dmac2 0x92>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c2: i2c@e6510000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774b1",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6510000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	dmas = <&dmac1 0x95>, <&dmac1 0x94>,
	<&dmac2 0x95>, <&dmac2 0x94>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c3: i2c@e66d0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774b1",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d0000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	dmas = <&dmac0 0x97>, <&dmac0 0x96>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c4: i2c@e66d8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774b1",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d8000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	dmas = <&dmac0 0x99>, <&dmac0 0x98>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c5: i2c@e66e0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774b1",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66e0000 0 0x40>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 919>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 919>;
	dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c6: i2c@e66e8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774b1",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66e8000 0 0x40>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 918>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 918>;
	dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c_dvfs: i2c@e60b0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a774b1",
	"renesas,rcar-gen3-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe60b0000 0 0x425>;
	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 926>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 926>;
	dmas = <&dmac0 0x11>, <&dmac0 0x10>;
	dma-names = "tx", "rx";
	status = "disabled";
	};

	hscif0: serial@e6540000 {
	compatible = "renesas,hscif-r8a774b1",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6540000 0 0x60>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 520>,
	<&cpg CPG_CORE R8A774B1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x31>, <&dmac1 0x30>,
	<&dmac2 0x31>, <&dmac2 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 520>;
	status = "disabled";
	};

	hscif1: serial@e6550000 {
	compatible = "renesas,hscif-r8a774b1",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6550000 0 0x60>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 519>,
	<&cpg CPG_CORE R8A774B1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x33>, <&dmac1 0x32>,
	<&dmac2 0x33>, <&dmac2 0x32>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 519>;
	status = "disabled";
	};

	hscif2: serial@e6560000 {
	compatible = "renesas,hscif-r8a774b1",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6560000 0 0x60>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 518>,
	<&cpg CPG_CORE R8A774B1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x35>, <&dmac1 0x34>,
	<&dmac2 0x35>, <&dmac2 0x34>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 518>;
	status = "disabled";
	};

	hscif3: serial@e66a0000 {
	compatible = "renesas,hscif-r8a774b1",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe66a0000 0 0x60>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 517>,
	<&cpg CPG_CORE R8A774B1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x37>, <&dmac0 0x36>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 517>;
	status = "disabled";
	};

	hscif4: serial@e66b0000 {
	compatible = "renesas,hscif-r8a774b1",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe66b0000 0 0x60>;
	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 516>,
	<&cpg CPG_CORE R8A774B1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x39>, <&dmac0 0x38>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 516>;
	status = "disabled";
	};

	hsusb: usb@e6590000 {
	compatible = "renesas,usbhs-r8a774b1",
	"renesas,rcar-gen3-usbhs";
	reg = <0 0xe6590000 0 0x200>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
	dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
	<&usb_dmac1 0>, <&usb_dmac1 1>;
	dma-names = "ch0", "ch1", "ch2", "ch3";
	renesas,buswait = <11>;
	phys = <&usb2_phy0 3>;
	phy-names = "usb";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 704>, <&cpg 703>;
	status = "disabled";
	};

	usb_dmac0: dma-controller@e65a0000 {
	compatible = "renesas,r8a774b1-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65a0000 0 0x100>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 330>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 330>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac1: dma-controller@e65b0000 {
	compatible = "renesas,r8a774b1-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65b0000 0 0x100>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 331>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 331>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb3_phy0: usb-phy@e65ee000 {
	compatible = "renesas,r8a774b1-usb3-phy",
	"renesas,rcar-gen3-usb3-phy";
	reg = <0 0xe65ee000 0 0x90>;
	clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
	<&usb_extal_clk>;
	clock-names = "usb3-if", "usb3s_clk", "usb_extal";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	#phy-cells = <0>;
	status = "disabled";
	};

	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a774b1",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x10000>;
	interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
	<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
	<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
	<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
	<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
	<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
	<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
	<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
	};

	dmac1: dma-controller@e7300000 {
	compatible = "renesas,dmac-r8a774b1",
	"renesas,rcar-dmac";
	reg = <0 0xe7300000 0 0x10000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
	<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
	<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
	<&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
	<&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
	<&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
	<&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
	<&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
	};

	dmac2: dma-controller@e7310000 {
	compatible = "renesas,dmac-r8a774b1",
	"renesas,rcar-dmac";
	reg = <0 0xe7310000 0 0x10000>;
	interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 217>;
	clock-names = "fck";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 217>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
	<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
	<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
	<&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
	<&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
	<&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
	<&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
	<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
	};

	ipmmu_ds0: mmu@e6740000 {
	compatible = "renesas,ipmmu-r8a774b1";
	reg = <0 0xe6740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 0>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_ds1: mmu@e7740000 {
	compatible = "renesas,ipmmu-r8a774b1";
	reg = <0 0xe7740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 1>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_hc: mmu@e6570000 {
	compatible = "renesas,ipmmu-r8a774b1";
	reg = <0 0xe6570000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 2>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_mm: mmu@e67b0000 {
	compatible = "renesas,ipmmu-r8a774b1";
	reg = <0 0xe67b0000 0 0x1000>;
	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_mp: mmu@ec670000 {
	compatible = "renesas,ipmmu-r8a774b1";
	reg = <0 0xec670000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 4>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_pv0: mmu@fd800000 {
	compatible = "renesas,ipmmu-r8a774b1";
	reg = <0 0xfd800000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 6>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vc0: mmu@fe6b0000 {
	compatible = "renesas,ipmmu-r8a774b1";
	reg = <0 0xfe6b0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 12>;
	power-domains = <&sysc R8A774B1_PD_A3VC>;
	#iommu-cells = <1>;
	};

	ipmmu_vi0: mmu@febd0000 {
	compatible = "renesas,ipmmu-r8a774b1";
	reg = <0 0xfebd0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 14>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vp0: mmu@fe990000 {
	compatible = "renesas,ipmmu-r8a774b1";
	reg = <0 0xfe990000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 16>;
	power-domains = <&sysc R8A774B1_PD_A3VP>;
	#iommu-cells = <1>;
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a774b1",
	"renesas,etheravb-rcar-gen3";
	reg = <0 0xe6800000 0 0x800>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15",
	"ch16", "ch17", "ch18", "ch19",
	"ch20", "ch21", "ch22", "ch23",
	"ch24";
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	phy-mode = "rgmii";
	iommus = <&ipmmu_ds0 16>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	can0: can@e6c30000 {
	compatible = "renesas,can-r8a774b1",
	"renesas,rcar-gen3-can";
	reg = <0 0xe6c30000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 916>,
	<&cpg CPG_CORE R8A774B1_CLK_CANFD>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 916>;
	status = "disabled";
	};

	can1: can@e6c38000 {
	compatible = "renesas,can-r8a774b1",
	"renesas,rcar-gen3-can";
	reg = <0 0xe6c38000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 915>,
	<&cpg CPG_CORE R8A774B1_CLK_CANFD>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 915>;
	status = "disabled";
	};

	canfd: can@e66c0000 {
	compatible = "renesas,r8a774b1-canfd",
	"renesas,rcar-gen3-canfd";
	reg = <0 0xe66c0000 0 0x8000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 914>,
	<&cpg CPG_CORE R8A774B1_CLK_CANFD>,
	<&can_clk>;
	clock-names = "fck", "canfd", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 914>;
	status = "disabled";

	channel0 {
	status = "disabled";
	};

	channel1 {
	status = "disabled";
	};
	};

	pwm0: pwm@e6e30000 {
	compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
	reg = <0 0xe6e30000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm1: pwm@e6e31000 {
	compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
	reg = <0 0xe6e31000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm2: pwm@e6e32000 {
	compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
	reg = <0 0xe6e32000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm3: pwm@e6e33000 {
	compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
	reg = <0 0xe6e33000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm4: pwm@e6e34000 {
	compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
	reg = <0 0xe6e34000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm5: pwm@e6e35000 {
	compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
	reg = <0 0xe6e35000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm6: pwm@e6e36000 {
	compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
	reg = <0 0xe6e36000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a774b1",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e60000 0 0x40>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 207>,
	<&cpg CPG_CORE R8A774B1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x51>, <&dmac1 0x50>,
	<&dmac2 0x51>, <&dmac2 0x50>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 207>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a774b1",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e68000 0 0x40>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 206>,
	<&cpg CPG_CORE R8A774B1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x53>, <&dmac1 0x52>,
	<&dmac2 0x53>, <&dmac2 0x52>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 206>;
	status = "disabled";
	};

	scif2: serial@e6e88000 {
	compatible = "renesas,scif-r8a774b1",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e88000 0 0x40>;
	interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 310>,
	<&cpg CPG_CORE R8A774B1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x13>, <&dmac1 0x12>,
	<&dmac2 0x13>, <&dmac2 0x12>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 310>;
	status = "disabled";
	};

	scif3: serial@e6c50000 {
	compatible = "renesas,scif-r8a774b1",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6c50000 0 0x40>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 204>,
	<&cpg CPG_CORE R8A774B1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x57>, <&dmac0 0x56>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 204>;
	status = "disabled";
	};

	scif4: serial@e6c40000 {
	compatible = "renesas,scif-r8a774b1",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6c40000 0 0x40>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 203>,
	<&cpg CPG_CORE R8A774B1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x59>, <&dmac0 0x58>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 203>;
	status = "disabled";
	};

	scif5: serial@e6f30000 {
	compatible = "renesas,scif-r8a774b1",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6f30000 0 0x40>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 202>,
	<&cpg CPG_CORE R8A774B1_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
	<&dmac2 0x5b>, <&dmac2 0x5a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 202>;
	status = "disabled";
	};

	msiof0: spi@e6e90000 {
	compatible = "renesas,msiof-r8a774b1",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6e90000 0 0x0064>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 211>;
	dmas = <&dmac1 0x41>, <&dmac1 0x40>,
	<&dmac2 0x41>, <&dmac2 0x40>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 211>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof1: spi@e6ea0000 {
	compatible = "renesas,msiof-r8a774b1",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6ea0000 0 0x0064>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 210>;
	dmas = <&dmac1 0x43>, <&dmac1 0x42>,
	<&dmac2 0x43>, <&dmac2 0x42>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 210>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof2: spi@e6c00000 {
	compatible = "renesas,msiof-r8a774b1",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c00000 0 0x0064>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 209>;
	dmas = <&dmac0 0x45>, <&dmac0 0x44>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 209>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof3: spi@e6c10000 {
	compatible = "renesas,msiof-r8a774b1",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c10000 0 0x0064>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 208>;
	dmas = <&dmac0 0x47>, <&dmac0 0x46>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 208>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	vin0: video@e6ef0000 {
	compatible = "renesas,vin-r8a774b1";
	reg = <0 0xe6ef0000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 811>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 811>;
	renesas,id = <0>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin0csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin0>;
	};
	vin0csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin0>;
	};
	};
	};
	};

	vin1: video@e6ef1000 {
	compatible = "renesas,vin-r8a774b1";
	reg = <0 0xe6ef1000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 810>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 810>;
	renesas,id = <1>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin1csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin1>;
	};
	vin1csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin1>;
	};
	};
	};
	};

	vin2: video@e6ef2000 {
	compatible = "renesas,vin-r8a774b1";
	reg = <0 0xe6ef2000 0 0x1000>;
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 809>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 809>;
	renesas,id = <2>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin2csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin2>;
	};
	vin2csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin2>;
	};
	};
	};
	};

	vin3: video@e6ef3000 {
	compatible = "renesas,vin-r8a774b1";
	reg = <0 0xe6ef3000 0 0x1000>;
	interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 808>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 808>;
	renesas,id = <3>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin3csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin3>;
	};
	vin3csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin3>;
	};
	};
	};
	};

	vin4: video@e6ef4000 {
	compatible = "renesas,vin-r8a774b1";
	reg = <0 0xe6ef4000 0 0x1000>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 807>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 807>;
	renesas,id = <4>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin4csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin4>;
	};
	vin4csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin4>;
	};
	};
	};
	};

	vin5: video@e6ef5000 {
	compatible = "renesas,vin-r8a774b1";
	reg = <0 0xe6ef5000 0 0x1000>;
	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 806>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 806>;
	renesas,id = <5>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin5csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin5>;
	};
	vin5csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin5>;
	};
	};
	};
	};

	vin6: video@e6ef6000 {
	compatible = "renesas,vin-r8a774b1";
	reg = <0 0xe6ef6000 0 0x1000>;
	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 805>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 805>;
	renesas,id = <6>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin6csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin6>;
	};
	vin6csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin6>;
	};
	};
	};
	};

	vin7: video@e6ef7000 {
	compatible = "renesas,vin-r8a774b1";
	reg = <0 0xe6ef7000 0 0x1000>;
	interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 804>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 804>;
	renesas,id = <7>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin7csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin7>;
	};
	vin7csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin7>;
	};
	};
	};
	};

	rcar_sound: sound@ec500000 {
	/*
	* #sound-dai-cells is required
	*
	* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
	* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
	*/
	/*
	* #clock-cells is required for audio_clkout0/1/2/3
	*
	* clkout : #clock-cells = <0>; <&rcar_sound>;
	* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
	*/
	compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3";
	reg = <0 0xec500000 0 0x1000>, /* SCU */
	<0 0xec5a0000 0 0x100>, /* ADG */
	<0 0xec540000 0 0x1000>, /* SSIU */
	<0 0xec541000 0 0x280>, /* SSI */
	<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
	reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

	clocks = <&cpg CPG_MOD 1005>,
	<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
	<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
	<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
	<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
	<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	<&audio_clk_a>, <&audio_clk_b>,
	<&audio_clk_c>,
	<&cpg CPG_CORE R8A774B1_CLK_S0D4>;
	clock-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0",
	"src.9", "src.8", "src.7", "src.6",
	"src.5", "src.4", "src.3", "src.2",
	"src.1", "src.0",
	"mix.1", "mix.0",
	"ctu.1", "ctu.0",
	"dvc.0", "dvc.1",
	"clk_a", "clk_b", "clk_c", "clk_i";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 1005>,
	<&cpg 1006>, <&cpg 1007>,
	<&cpg 1008>, <&cpg 1009>,
	<&cpg 1010>, <&cpg 1011>,
	<&cpg 1012>, <&cpg 1013>,
	<&cpg 1014>, <&cpg 1015>;
	reset-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0";
	status = "disabled";

	rcar_sound,ctu {
	ctu00: ctu-0 { };
	ctu01: ctu-1 { };
	ctu02: ctu-2 { };
	ctu03: ctu-3 { };
	ctu10: ctu-4 { };
	ctu11: ctu-5 { };
	ctu12: ctu-6 { };
	ctu13: ctu-7 { };
	};

	rcar_sound,dvc {
	dvc0: dvc-0 {
	dmas = <&audma1 0xbc>;
	dma-names = "tx";
	};
	dvc1: dvc-1 {
	dmas = <&audma1 0xbe>;
	dma-names = "tx";
	};
	};

	rcar_sound,mix {
	mix0: mix-0 { };
	mix1: mix-1 { };
	};

	rcar_sound,src {
	src0: src-0 {
	interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x85>, <&audma1 0x9a>;
	dma-names = "rx", "tx";
	};
	src1: src-1 {
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x87>, <&audma1 0x9c>;
	dma-names = "rx", "tx";
	};
	src2: src-2 {
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x89>, <&audma1 0x9e>;
	dma-names = "rx", "tx";
	};
	src3: src-3 {
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8b>, <&audma1 0xa0>;
	dma-names = "rx", "tx";
	};
	src4: src-4 {
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8d>, <&audma1 0xb0>;
	dma-names = "rx", "tx";
	};
	src5: src-5 {
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8f>, <&audma1 0xb2>;
	dma-names = "rx", "tx";
	};
	src6: src-6 {
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x91>, <&audma1 0xb4>;
	dma-names = "rx", "tx";
	};
	src7: src-7 {
	interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x93>, <&audma1 0xb6>;
	dma-names = "rx", "tx";
	};
	src8: src-8 {
	interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x95>, <&audma1 0xb8>;
	dma-names = "rx", "tx";
	};
	src9: src-9 {
	interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x97>, <&audma1 0xba>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssi {
	ssi0: ssi-0 {
	interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x01>, <&audma1 0x02>;
	dma-names = "rx", "tx";
	};
	ssi1: ssi-1 {
	interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x03>, <&audma1 0x04>;
	dma-names = "rx", "tx";
	};
	ssi2: ssi-2 {
	interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x05>, <&audma1 0x06>;
	dma-names = "rx", "tx";
	};
	ssi3: ssi-3 {
	interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x07>, <&audma1 0x08>;
	dma-names = "rx", "tx";
	};
	ssi4: ssi-4 {
	interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x09>, <&audma1 0x0a>;
	dma-names = "rx", "tx";
	};
	ssi5: ssi-5 {
	interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0b>, <&audma1 0x0c>;
	dma-names = "rx", "tx";
	};
	ssi6: ssi-6 {
	interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0d>, <&audma1 0x0e>;
	dma-names = "rx", "tx";
	};
	ssi7: ssi-7 {
	interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0f>, <&audma1 0x10>;
	dma-names = "rx", "tx";
	};
	ssi8: ssi-8 {
	interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x11>, <&audma1 0x12>;
	dma-names = "rx", "tx";
	};
	ssi9: ssi-9 {
	interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x13>, <&audma1 0x14>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssiu {
	ssiu00: ssiu-0 {
	dmas = <&audma0 0x15>, <&audma1 0x16>;
	dma-names = "rx", "tx";
	};
	ssiu01: ssiu-1 {
	dmas = <&audma0 0x35>, <&audma1 0x36>;
	dma-names = "rx", "tx";
	};
	ssiu02: ssiu-2 {
	dmas = <&audma0 0x37>, <&audma1 0x38>;
	dma-names = "rx", "tx";
	};
	ssiu03: ssiu-3 {
	dmas = <&audma0 0x47>, <&audma1 0x48>;
	dma-names = "rx", "tx";
	};
	ssiu04: ssiu-4 {
	dmas = <&audma0 0x3F>, <&audma1 0x40>;
	dma-names = "rx", "tx";
	};
	ssiu05: ssiu-5 {
	dmas = <&audma0 0x43>, <&audma1 0x44>;
	dma-names = "rx", "tx";
	};
	ssiu06: ssiu-6 {
	dmas = <&audma0 0x4F>, <&audma1 0x50>;
	dma-names = "rx", "tx";
	};
	ssiu07: ssiu-7 {
	dmas = <&audma0 0x53>, <&audma1 0x54>;
	dma-names = "rx", "tx";
	};
	ssiu10: ssiu-8 {
	dmas = <&audma0 0x49>, <&audma1 0x4a>;
	dma-names = "rx", "tx";
	};
	ssiu11: ssiu-9 {
	dmas = <&audma0 0x4B>, <&audma1 0x4C>;
	dma-names = "rx", "tx";
	};
	ssiu12: ssiu-10 {
	dmas = <&audma0 0x57>, <&audma1 0x58>;
	dma-names = "rx", "tx";
	};
	ssiu13: ssiu-11 {
	dmas = <&audma0 0x59>, <&audma1 0x5A>;
	dma-names = "rx", "tx";
	};
	ssiu14: ssiu-12 {
	dmas = <&audma0 0x5F>, <&audma1 0x60>;
	dma-names = "rx", "tx";
	};
	ssiu15: ssiu-13 {
	dmas = <&audma0 0xC3>, <&audma1 0xC4>;
	dma-names = "rx", "tx";
	};
	ssiu16: ssiu-14 {
	dmas = <&audma0 0xC7>, <&audma1 0xC8>;
	dma-names = "rx", "tx";
	};
	ssiu17: ssiu-15 {
	dmas = <&audma0 0xCB>, <&audma1 0xCC>;
	dma-names = "rx", "tx";
	};
	ssiu20: ssiu-16 {
	dmas = <&audma0 0x63>, <&audma1 0x64>;
	dma-names = "rx", "tx";
	};
	ssiu21: ssiu-17 {
	dmas = <&audma0 0x67>, <&audma1 0x68>;
	dma-names = "rx", "tx";
	};
	ssiu22: ssiu-18 {
	dmas = <&audma0 0x6B>, <&audma1 0x6C>;
	dma-names = "rx", "tx";
	};
	ssiu23: ssiu-19 {
	dmas = <&audma0 0x6D>, <&audma1 0x6E>;
	dma-names = "rx", "tx";
	};
	ssiu24: ssiu-20 {
	dmas = <&audma0 0xCF>, <&audma1 0xCE>;
	dma-names = "rx", "tx";
	};
	ssiu25: ssiu-21 {
	dmas = <&audma0 0xEB>, <&audma1 0xEC>;
	dma-names = "rx", "tx";
	};
	ssiu26: ssiu-22 {
	dmas = <&audma0 0xED>, <&audma1 0xEE>;
	dma-names = "rx", "tx";
	};
	ssiu27: ssiu-23 {
	dmas = <&audma0 0xEF>, <&audma1 0xF0>;
	dma-names = "rx", "tx";
	};
	ssiu30: ssiu-24 {
	dmas = <&audma0 0x6f>, <&audma1 0x70>;
	dma-names = "rx", "tx";
	};
	ssiu31: ssiu-25 {
	dmas = <&audma0 0x21>, <&audma1 0x22>;
	dma-names = "rx", "tx";
	};
	ssiu32: ssiu-26 {
	dmas = <&audma0 0x23>, <&audma1 0x24>;
	dma-names = "rx", "tx";
	};
	ssiu33: ssiu-27 {
	dmas = <&audma0 0x25>, <&audma1 0x26>;
	dma-names = "rx", "tx";
	};
	ssiu34: ssiu-28 {
	dmas = <&audma0 0x27>, <&audma1 0x28>;
	dma-names = "rx", "tx";
	};
	ssiu35: ssiu-29 {
	dmas = <&audma0 0x29>, <&audma1 0x2A>;
	dma-names = "rx", "tx";
	};
	ssiu36: ssiu-30 {
	dmas = <&audma0 0x2B>, <&audma1 0x2C>;
	dma-names = "rx", "tx";
	};
	ssiu37: ssiu-31 {
	dmas = <&audma0 0x2D>, <&audma1 0x2E>;
	dma-names = "rx", "tx";
	};
	ssiu40: ssiu-32 {
	dmas = <&audma0 0x71>, <&audma1 0x72>;
	dma-names = "rx", "tx";
	};
	ssiu41: ssiu-33 {
	dmas = <&audma0 0x17>, <&audma1 0x18>;
	dma-names = "rx", "tx";
	};
	ssiu42: ssiu-34 {
	dmas = <&audma0 0x19>, <&audma1 0x1A>;
	dma-names = "rx", "tx";
	};
	ssiu43: ssiu-35 {
	dmas = <&audma0 0x1B>, <&audma1 0x1C>;
	dma-names = "rx", "tx";
	};
	ssiu44: ssiu-36 {
	dmas = <&audma0 0x1D>, <&audma1 0x1E>;
	dma-names = "rx", "tx";
	};
	ssiu45: ssiu-37 {
	dmas = <&audma0 0x1F>, <&audma1 0x20>;
	dma-names = "rx", "tx";
	};
	ssiu46: ssiu-38 {
	dmas = <&audma0 0x31>, <&audma1 0x32>;
	dma-names = "rx", "tx";
	};
	ssiu47: ssiu-39 {
	dmas = <&audma0 0x33>, <&audma1 0x34>;
	dma-names = "rx", "tx";
	};
	ssiu50: ssiu-40 {
	dmas = <&audma0 0x73>, <&audma1 0x74>;
	dma-names = "rx", "tx";
	};
	ssiu60: ssiu-41 {
	dmas = <&audma0 0x75>, <&audma1 0x76>;
	dma-names = "rx", "tx";
	};
	ssiu70: ssiu-42 {
	dmas = <&audma0 0x79>, <&audma1 0x7a>;
	dma-names = "rx", "tx";
	};
	ssiu80: ssiu-43 {
	dmas = <&audma0 0x7b>, <&audma1 0x7c>;
	dma-names = "rx", "tx";
	};
	ssiu90: ssiu-44 {
	dmas = <&audma0 0x7d>, <&audma1 0x7e>;
	dma-names = "rx", "tx";
	};
	ssiu91: ssiu-45 {
	dmas = <&audma0 0x7F>, <&audma1 0x80>;
	dma-names = "rx", "tx";
	};
	ssiu92: ssiu-46 {
	dmas = <&audma0 0x81>, <&audma1 0x82>;
	dma-names = "rx", "tx";
	};
	ssiu93: ssiu-47 {
	dmas = <&audma0 0x83>, <&audma1 0x84>;
	dma-names = "rx", "tx";
	};
	ssiu94: ssiu-48 {
	dmas = <&audma0 0xA3>, <&audma1 0xA4>;
	dma-names = "rx", "tx";
	};
	ssiu95: ssiu-49 {
	dmas = <&audma0 0xA5>, <&audma1 0xA6>;
	dma-names = "rx", "tx";
	};
	ssiu96: ssiu-50 {
	dmas = <&audma0 0xA7>, <&audma1 0xA8>;
	dma-names = "rx", "tx";
	};
	ssiu97: ssiu-51 {
	dmas = <&audma0 0xA9>, <&audma1 0xAA>;
	dma-names = "rx", "tx";
	};
	};
	};

	audma0: dma-controller@ec700000 {
	compatible = "renesas,dmac-r8a774b1",
	"renesas,rcar-dmac";
	reg = <0 0xec700000 0 0x10000>;
	interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 502>;
	clock-names = "fck";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 502>;
	#dma-cells = <1>;
	dma-channels = <16>;
	};

	audma1: dma-controller@ec720000 {
	compatible = "renesas,dmac-r8a774b1",
	"renesas,rcar-dmac";
	reg = <0 0xec720000 0 0x10000>;
	interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 501>;
	clock-names = "fck";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 501>;
	#dma-cells = <1>;
	dma-channels = <16>;
	};

	xhci0: usb@ee000000 {
	compatible = "renesas,xhci-r8a774b1",
	"renesas,rcar-gen3-xhci";
	reg = <0 0xee000000 0 0xc00>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	status = "disabled";
	};

	usb3_peri0: usb@ee020000 {
	compatible = "renesas,r8a774b1-usb3-peri",
	"renesas,rcar-gen3-usb3-peri";
	reg = <0 0xee020000 0 0x400>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	status = "disabled";
	};

	ohci0: usb@ee080000 {
	compatible = "generic-ohci";
	reg = <0 0xee080000 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	phys = <&usb2_phy0 1>;
	phy-names = "usb";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	status = "disabled";
	};

	ohci1: usb@ee0a0000 {
	compatible = "generic-ohci";
	reg = <0 0xee0a0000 0 0x100>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 702>;
	phys = <&usb2_phy1 1>;
	phy-names = "usb";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 702>;
	status = "disabled";
	};

	ehci0: usb@ee080100 {
	compatible = "generic-ehci";
	reg = <0 0xee080100 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	phys = <&usb2_phy0 2>;
	phy-names = "usb";
	companion = <&ohci0>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	status = "disabled";
	};

	ehci1: usb@ee0a0100 {
	compatible = "generic-ehci";
	reg = <0 0xee0a0100 0 0x100>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 702>;
	phys = <&usb2_phy1 2>;
	phy-names = "usb";
	companion = <&ohci1>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 702>;
	status = "disabled";
	};

	usb2_phy0: usb-phy@ee080200 {
	compatible = "renesas,usb2-phy-r8a774b1",
	"renesas,rcar-gen3-usb2-phy";
	reg = <0 0xee080200 0 0x700>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	#phy-cells = <1>;
	status = "disabled";
	};

	usb2_phy1: usb-phy@ee0a0200 {
	compatible = "renesas,usb2-phy-r8a774b1",
	"renesas,rcar-gen3-usb2-phy";
	reg = <0 0xee0a0200 0 0x700>;
	clocks = <&cpg CPG_MOD 702>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 702>;
	#phy-cells = <1>;
	status = "disabled";
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a774b1",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee100000 0 0x2000>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	status = "disabled";
	};

	sdhi1: sd@ee120000 {
	compatible = "renesas,sdhi-r8a774b1",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee120000 0 0x2000>;
	interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 313>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 313>;
	status = "disabled";
	};

	sdhi2: sd@ee140000 {
	compatible = "renesas,sdhi-r8a774b1",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee140000 0 0x2000>;
	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 312>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 312>;
	status = "disabled";
	};

	sdhi3: sd@ee160000 {
	compatible = "renesas,sdhi-r8a774b1",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee160000 0 0x2000>;
	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 311>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 311>;
	status = "disabled";
	};

	sata: sata@ee300000 {
	compatible = "renesas,sata-r8a774b1",
	"renesas,rcar-gen3-sata";
	reg = <0 0xee300000 0 0x200000>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 815>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 815>;
	status = "disabled";
	};

	gic: interrupt-controller@f1010000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x0 0xf1010000 0 0x1000>,
	<0x0 0xf1020000 0 0x20000>,
	<0x0 0xf1040000 0 0x20000>,
	<0x0 0xf1060000 0 0x20000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	pciec0: pcie@fe000000 {
	compatible = "renesas,pcie-r8a774b1",
	"renesas,pcie-rcar-gen3";
	reg = <0 0xfe000000 0 0x80000>;
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x00 0xff>;
	device_type = "pci";
	ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
	<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
	<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
	<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
	/* Map all possible DDR as inbound ranges */
	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
	clock-names = "pcie", "pcie_bus";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 319>;
	status = "disabled";
	};

	pciec1: pcie@ee800000 {
	compatible = "renesas,pcie-r8a774b1",
	"renesas,pcie-rcar-gen3";
	reg = <0 0xee800000 0 0x80000>;
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x00 0xff>;
	device_type = "pci";
	ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
	<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
	<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
	<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
	/* Map all possible DDR as inbound ranges */
	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
	clock-names = "pcie", "pcie_bus";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 318>;
	status = "disabled";
	};

	fdp1@fe940000 {
	compatible = "renesas,fdp1";
	reg = <0 0xfe940000 0 0x2400>;
	interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 119>;
	power-domains = <&sysc R8A774B1_PD_A3VP>;
	resets = <&cpg 119>;
	renesas,fcp = <&fcpf0>;
	};

	fcpf0: fcp@fe950000 {
	compatible = "renesas,fcpf";
	reg = <0 0xfe950000 0 0x200>;
	clocks = <&cpg CPG_MOD 615>;
	power-domains = <&sysc R8A774B1_PD_A3VP>;
	resets = <&cpg 615>;
	};

	vspb: vsp@fe960000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe960000 0 0x8000>;
	interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 626>;
	power-domains = <&sysc R8A774B1_PD_A3VP>;
	resets = <&cpg 626>;

	renesas,fcp = <&fcpvb0>;
	};

	vspi0: vsp@fe9a0000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe9a0000 0 0x8000>;
	interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 631>;
	power-domains = <&sysc R8A774B1_PD_A3VP>;
	resets = <&cpg 631>;

	renesas,fcp = <&fcpvi0>;
	};

	vspd0: vsp@fea20000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea20000 0 0x5000>;
	interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 623>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 623>;

	renesas,fcp = <&fcpvd0>;
	};

	vspd1: vsp@fea28000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea28000 0 0x5000>;
	interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 622>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 622>;

	renesas,fcp = <&fcpvd1>;
	};

	fcpvb0: fcp@fe96f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe96f000 0 0x200>;
	clocks = <&cpg CPG_MOD 607>;
	power-domains = <&sysc R8A774B1_PD_A3VP>;
	resets = <&cpg 607>;
	};

	fcpvd0: fcp@fea27000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea27000 0 0x200>;
	clocks = <&cpg CPG_MOD 603>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 603>;
	};

	fcpvd1: fcp@fea2f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea2f000 0 0x200>;
	clocks = <&cpg CPG_MOD 602>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 602>;
	};

	fcpvi0: fcp@fe9af000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe9af000 0 0x200>;
	clocks = <&cpg CPG_MOD 611>;
	power-domains = <&sysc R8A774B1_PD_A3VP>;
	resets = <&cpg 611>;
	};

	csi20: csi2@fea80000 {
	compatible = "renesas,r8a774b1-csi2";
	reg = <0 0xfea80000 0 0x10000>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 714>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 714>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	csi20vin0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vin0csi20>;
	};
	csi20vin1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vin1csi20>;
	};
	csi20vin2: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&vin2csi20>;
	};
	csi20vin3: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&vin3csi20>;
	};
	csi20vin4: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&vin4csi20>;
	};
	csi20vin5: endpoint@5 {
	reg = <5>;
	remote-endpoint = <&vin5csi20>;
	};
	csi20vin6: endpoint@6 {
	reg = <6>;
	remote-endpoint = <&vin6csi20>;
	};
	csi20vin7: endpoint@7 {
	reg = <7>;
	remote-endpoint = <&vin7csi20>;
	};
	};
	};
	};

	csi40: csi2@feaa0000 {
	compatible = "renesas,r8a774b1-csi2";
	reg = <0 0xfeaa0000 0 0x10000>;
	interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	csi40vin0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vin0csi40>;
	};
	csi40vin1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vin1csi40>;
	};
	csi40vin2: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&vin2csi40>;
	};
	csi40vin3: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&vin3csi40>;
	};
	csi40vin4: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&vin4csi40>;
	};
	csi40vin5: endpoint@5 {
	reg = <5>;
	remote-endpoint = <&vin5csi40>;
	};
	csi40vin6: endpoint@6 {
	reg = <6>;
	remote-endpoint = <&vin6csi40>;
	};
	csi40vin7: endpoint@7 {
	reg = <7>;
	remote-endpoint = <&vin7csi40>;
	};
	};
	};
	};

	hdmi0: hdmi@fead0000 {
	compatible = "renesas,r8a774b1-hdmi",
	"renesas,rcar-gen3-hdmi";
	reg = <0 0xfead0000 0 0x10000>;
	interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 729>,
	<&cpg CPG_CORE R8A774B1_CLK_HDMI>;
	clock-names = "iahb", "isfr";
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 729>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	dw_hdmi0_in: endpoint {
	remote-endpoint = <&du_out_hdmi0>;
	};
	};
	port@1 {
	reg = <1>;
	};
	port@2 {
	/* HDMI sound */
	reg = <2>;
	};
	};
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a774b1";
	reg = <0 0xfeb00000 0 0x80000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&cpg CPG_MOD 724>,
	- <&cpg CPG_MOD 723>,
	+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
	<&cpg CPG_MOD 721>;
	clock-names = "du.0", "du.1", "du.3";
	+ resets = <&cpg 724>, <&cpg 722>;
	+ reset-names = "du.0", "du.3";
	status = "disabled";

	- vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
	+ renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb: endpoint {
	};
	};
	port@1 {
	reg = <1>;
	du_out_hdmi0: endpoint {
	remote-endpoint = <&dw_hdmi0_in>;
	};
	};
	port@2 {
	reg = <2>;
	du_out_lvds0: endpoint {
	remote-endpoint = <&lvds0_in>;
	};
	};
	};
	};

	lvds0: lvds@feb90000 {
	compatible = "renesas,r8a774b1-lvds";
	reg = <0 0xfeb90000 0 0x14>;
	clocks = <&cpg CPG_MOD 727>;
	power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
	resets = <&cpg 727>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds0_in: endpoint {
	remote-endpoint = <&du_out_lvds0>;
	};
	};
	port@1 {
	reg = <1>;
	lvds0_out: endpoint {
	};
	};
	};
	};

	prr: chipid@fff00044 {
	compatible = "renesas,prr";
	reg = <0 0xfff00044 0 4>;
	};
	};

	thermal-zones {
	sensor_thermal1: sensor-thermal1 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&tsc 0>;
	sustainable-power = <2439>;

	trips {
	sensor1_crit: sensor1-crit {
	temperature = <120000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};
	};

	sensor_thermal2: sensor-thermal2 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&tsc 1>;
	sustainable-power = <2439>;

	trips {
	sensor2_crit: sensor2-crit {
	temperature = <120000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};
	};

	sensor_thermal3: sensor-thermal3 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&tsc 2>;
	sustainable-power = <2439>;

	cooling-maps {
	map0 {
	trip = <&target>;
	cooling-device = <&a57_0 0 2>;
	contribution = <1024>;
	};
	};
	trips {
	target: trip-point1 {
	temperature = <100000>;
	hysteresis = <1000>;
	type = "passive";
	};

	sensor3_crit: sensor3-crit {
	temperature = <120000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clocks - can be overridden by the board */
	usb3s0_clk: usb3s0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	usb_extal_clk: usb_extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a774c0.dtsi b/sys/gnu/dts/arm64/renesas/r8a774c0.dtsi
	index a53cd5fcc401..22785cbddff5 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a774c0.dtsi
	+++ b/sys/gnu/dts/arm64/renesas/r8a774c0.dtsi
	@@ -1,1958 +1,1960 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the RZ/G2E (R8A774C0) SoC
	*
	* Copyright (C) 2018-2019 Renesas Electronics Corp.
	*/

	#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/power/r8a774c0-sysc.h>

	/ {
	compatible = "renesas,r8a774c0";
	#address-cells = <2>;
	#size-cells = <2>;

	/*
	* The external audio clocks are configured as 0 Hz fixed frequency
	* clocks by default.
	* Boards that provide audio clocks should override them.
	*/
	audio_clk_a: audio_clk_a {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_b: audio_clk_b {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_c: audio_clk_c {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	/* External CAN clock - to be overridden by boards that provide it */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	cluster1_opp: opp_table10 {
	compatible = "operating-points-v2";
	opp-shared;
	opp-800000000 {
	opp-hz = /bits/ 64 <800000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	opp-suspend;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	a53_0: cpu@0 {
	compatible = "arm,cortex-a53";
	reg = <0>;
	device_type = "cpu";
	#cooling-cells = <2>;
	power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	dynamic-power-coefficient = <277>;
	clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	};

	a53_1: cpu@1 {
	compatible = "arm,cortex-a53";
	reg = <1>;
	device_type = "cpu";
	power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	};

	L2_CA53: cache-controller-0 {
	compatible = "cache";
	power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
	cache-unified;
	cache-level = <2>;
	};
	};

	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	/* External PCIe clock - can be overridden by the board */
	pcie_bus_clk: pcie_bus {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	pmu_a53 {
	compatible = "arm,cortex-a53-pmu";
	interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&a53_0>, <&a53_1>;
	};

	psci {
	compatible = "arm,psci-1.0", "arm,psci-0.2";
	method = "smc";
	};

	/* External SCIF clock - to be overridden by boards that provide it */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	soc: soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a774c0-wdt",
	"renesas,rcar-gen3-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a774c0",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 18>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a774c0",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 23>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a774c0",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a774c0",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 16>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a774c0",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 11>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a774c0",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 20>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	gpio6: gpio@e6055400 {
	compatible = "renesas,gpio-r8a774c0",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055400 0 0x50>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 192 18>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 906>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 906>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a774c0";
	reg = <0 0xe6060000 0 0x508>;
	};

	cmt0: timer@e60f0000 {
	compatible = "renesas,r8a774c0-cmt0",
	"renesas,rcar-gen3-cmt0";
	reg = <0 0xe60f0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 303>;
	clock-names = "fck";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 303>;
	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a774c0-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 302>;
	clock-names = "fck";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 302>;
	status = "disabled";
	};

	cmt2: timer@e6140000 {
	compatible = "renesas,r8a774c0-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6140000 0 0x1004>;
	interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 301>;
	clock-names = "fck";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 301>;
	status = "disabled";
	};

	cmt3: timer@e6148000 {
	compatible = "renesas,r8a774c0-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6148000 0 0x1004>;
	interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 300>;
	clock-names = "fck";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 300>;
	status = "disabled";
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a774c0-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>;
	clock-names = "extal";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a774c0-rst";
	reg = <0 0xe6160000 0 0x0200>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a774c0-sysc";
	reg = <0 0xe6180000 0 0x0400>;
	#power-domain-cells = <1>;
	};

	thermal: thermal@e6190000 {
	compatible = "renesas,thermal-r8a774c0";
	reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 522>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 522>;
	#thermal-sensor-cells = <0>;
	};

	intc_ex: interrupt-controller@e61c0000 {
	compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	tmu0: timer@e61e0000 {
	compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
	reg = <0 0xe61e0000 0 0x30>;
	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 125>;
	clock-names = "fck";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 125>;
	status = "disabled";
	};

	tmu1: timer@e6fc0000 {
	compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
	reg = <0 0xe6fc0000 0 0x30>;
	interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 124>;
	clock-names = "fck";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 124>;
	status = "disabled";
	};

	tmu2: timer@e6fd0000 {
	compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
	reg = <0 0xe6fd0000 0 0x30>;
	interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 123>;
	clock-names = "fck";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 123>;
	status = "disabled";
	};

	tmu3: timer@e6fe0000 {
	compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
	reg = <0 0xe6fe0000 0 0x30>;
	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 122>;
	clock-names = "fck";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 122>;
	status = "disabled";
	};

	tmu4: timer@ffc00000 {
	compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
	reg = <0 0xffc00000 0 0x30>;
	interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 121>;
	clock-names = "fck";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 121>;
	status = "disabled";
	};

	i2c0: i2c@e6500000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774c0",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6500000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	dmas = <&dmac1 0x91>, <&dmac1 0x90>,
	<&dmac2 0x91>, <&dmac2 0x90>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c1: i2c@e6508000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774c0",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	dmas = <&dmac1 0x93>, <&dmac1 0x92>,
	<&dmac2 0x93>, <&dmac2 0x92>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c2: i2c@e6510000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774c0",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6510000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	dmas = <&dmac1 0x95>, <&dmac1 0x94>,
	<&dmac2 0x95>, <&dmac2 0x94>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c3: i2c@e66d0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774c0",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d0000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	dmas = <&dmac0 0x97>, <&dmac0 0x96>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c4: i2c@e66d8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774c0",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d8000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	dmas = <&dmac0 0x99>, <&dmac0 0x98>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c5: i2c@e66e0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774c0",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66e0000 0 0x40>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 919>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 919>;
	dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c6: i2c@e66e8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774c0",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66e8000 0 0x40>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 918>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 918>;
	dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c7: i2c@e6690000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a774c0",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6690000 0 0x40>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1003>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 1003>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c_dvfs: i2c@e60b0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a774c0";
	reg = <0 0xe60b0000 0 0x15>;
	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 926>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 926>;
	dmas = <&dmac0 0x11>, <&dmac0 0x10>;
	dma-names = "tx", "rx";
	status = "disabled";
	};

	hscif0: serial@e6540000 {
	compatible = "renesas,hscif-r8a774c0",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6540000 0 0x60>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 520>,
	<&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x31>, <&dmac1 0x30>,
	<&dmac2 0x31>, <&dmac2 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 520>;
	status = "disabled";
	};

	hscif1: serial@e6550000 {
	compatible = "renesas,hscif-r8a774c0",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6550000 0 0x60>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 519>,
	<&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x33>, <&dmac1 0x32>,
	<&dmac2 0x33>, <&dmac2 0x32>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 519>;
	status = "disabled";
	};

	hscif2: serial@e6560000 {
	compatible = "renesas,hscif-r8a774c0",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6560000 0 0x60>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 518>,
	<&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x35>, <&dmac1 0x34>,
	<&dmac2 0x35>, <&dmac2 0x34>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 518>;
	status = "disabled";
	};

	hscif3: serial@e66a0000 {
	compatible = "renesas,hscif-r8a774c0",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe66a0000 0 0x60>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 517>,
	<&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x37>, <&dmac0 0x36>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 517>;
	status = "disabled";
	};

	hscif4: serial@e66b0000 {
	compatible = "renesas,hscif-r8a774c0",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe66b0000 0 0x60>;
	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 516>,
	<&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x39>, <&dmac0 0x38>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 516>;
	status = "disabled";
	};

	hsusb: usb@e6590000 {
	compatible = "renesas,usbhs-r8a774c0",
	"renesas,rcar-gen3-usbhs";
	reg = <0 0xe6590000 0 0x200>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
	dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
	<&usb_dmac1 0>, <&usb_dmac1 1>;
	dma-names = "ch0", "ch1", "ch2", "ch3";
	renesas,buswait = <11>;
	phys = <&usb2_phy0 3>;
	phy-names = "usb";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 704>, <&cpg 703>;
	status = "disabled";
	};

	usb_dmac0: dma-controller@e65a0000 {
	compatible = "renesas,r8a774c0-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65a0000 0 0x100>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 330>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 330>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac1: dma-controller@e65b0000 {
	compatible = "renesas,r8a774c0-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65b0000 0 0x100>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 331>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 331>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a774c0",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x10000>;
	interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
	<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
	<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
	<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
	<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
	<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
	<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
	<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
	};

	dmac1: dma-controller@e7300000 {
	compatible = "renesas,dmac-r8a774c0",
	"renesas,rcar-dmac";
	reg = <0 0xe7300000 0 0x10000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
	<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
	<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
	<&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
	<&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
	<&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
	<&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
	<&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
	};

	dmac2: dma-controller@e7310000 {
	compatible = "renesas,dmac-r8a774c0",
	"renesas,rcar-dmac";
	reg = <0 0xe7310000 0 0x10000>;
	interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 217>;
	clock-names = "fck";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 217>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
	<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
	<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
	<&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
	<&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
	<&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
	<&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
	<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
	};

	ipmmu_ds0: mmu@e6740000 {
	compatible = "renesas,ipmmu-r8a774c0";
	reg = <0 0xe6740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 0>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_ds1: mmu@e7740000 {
	compatible = "renesas,ipmmu-r8a774c0";
	reg = <0 0xe7740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 1>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_hc: mmu@e6570000 {
	compatible = "renesas,ipmmu-r8a774c0";
	reg = <0 0xe6570000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 2>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_mm: mmu@e67b0000 {
	compatible = "renesas,ipmmu-r8a774c0";
	reg = <0 0xe67b0000 0 0x1000>;
	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_mp: mmu@ec670000 {
	compatible = "renesas,ipmmu-r8a774c0";
	reg = <0 0xec670000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 4>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_pv0: mmu@fd800000 {
	compatible = "renesas,ipmmu-r8a774c0";
	reg = <0 0xfd800000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 6>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vc0: mmu@fe6b0000 {
	compatible = "renesas,ipmmu-r8a774c0";
	reg = <0 0xfe6b0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 12>;
	power-domains = <&sysc R8A774C0_PD_A3VC>;
	#iommu-cells = <1>;
	};

	ipmmu_vi0: mmu@febd0000 {
	compatible = "renesas,ipmmu-r8a774c0";
	reg = <0 0xfebd0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 14>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vp0: mmu@fe990000 {
	compatible = "renesas,ipmmu-r8a774c0";
	reg = <0 0xfe990000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 16>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a774c0",
	"renesas,etheravb-rcar-gen3";
	reg = <0 0xe6800000 0 0x800>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15",
	"ch16", "ch17", "ch18", "ch19",
	"ch20", "ch21", "ch22", "ch23",
	"ch24";
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	phy-mode = "rgmii";
	iommus = <&ipmmu_ds0 16>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	can0: can@e6c30000 {
	compatible = "renesas,can-r8a774c0",
	"renesas,rcar-gen3-can";
	reg = <0 0xe6c30000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 916>,
	<&cpg CPG_CORE R8A774C0_CLK_CANFD>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 916>;
	status = "disabled";
	};

	can1: can@e6c38000 {
	compatible = "renesas,can-r8a774c0",
	"renesas,rcar-gen3-can";
	reg = <0 0xe6c38000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 915>,
	<&cpg CPG_CORE R8A774C0_CLK_CANFD>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 915>;
	status = "disabled";
	};

	canfd: can@e66c0000 {
	compatible = "renesas,r8a774c0-canfd",
	"renesas,rcar-gen3-canfd";
	reg = <0 0xe66c0000 0 0x8000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 914>,
	<&cpg CPG_CORE R8A774C0_CLK_CANFD>,
	<&can_clk>;
	clock-names = "fck", "canfd", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 914>;
	status = "disabled";

	channel0 {
	status = "disabled";
	};

	channel1 {
	status = "disabled";
	};
	};

	pwm0: pwm@e6e30000 {
	compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
	reg = <0 0xe6e30000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm1: pwm@e6e31000 {
	compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
	reg = <0 0xe6e31000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm2: pwm@e6e32000 {
	compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
	reg = <0 0xe6e32000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm3: pwm@e6e33000 {
	compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
	reg = <0 0xe6e33000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm4: pwm@e6e34000 {
	compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
	reg = <0 0xe6e34000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm5: pwm@e6e35000 {
	compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
	reg = <0 0xe6e35000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm6: pwm@e6e36000 {
	compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
	reg = <0 0xe6e36000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a774c0",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e60000 0 64>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 207>,
	<&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x51>, <&dmac1 0x50>,
	<&dmac2 0x51>, <&dmac2 0x50>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 207>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a774c0",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e68000 0 64>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 206>,
	<&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x53>, <&dmac1 0x52>,
	<&dmac2 0x53>, <&dmac2 0x52>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 206>;
	status = "disabled";
	};

	scif2: serial@e6e88000 {
	compatible = "renesas,scif-r8a774c0",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e88000 0 64>;
	interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 310>,
	<&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x13>, <&dmac1 0x12>,
	<&dmac2 0x13>, <&dmac2 0x12>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 310>;
	status = "disabled";
	};

	scif3: serial@e6c50000 {
	compatible = "renesas,scif-r8a774c0",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6c50000 0 64>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 204>,
	<&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x57>, <&dmac0 0x56>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 204>;
	status = "disabled";
	};

	scif4: serial@e6c40000 {
	compatible = "renesas,scif-r8a774c0",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6c40000 0 64>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 203>,
	<&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x59>, <&dmac0 0x58>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 203>;
	status = "disabled";
	};

	scif5: serial@e6f30000 {
	compatible = "renesas,scif-r8a774c0",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6f30000 0 64>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 202>,
	<&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 202>;
	status = "disabled";
	};

	msiof0: spi@e6e90000 {
	compatible = "renesas,msiof-r8a774c0",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6e90000 0 0x0064>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 211>;
	dmas = <&dmac1 0x41>, <&dmac1 0x40>,
	<&dmac2 0x41>, <&dmac2 0x40>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 211>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof1: spi@e6ea0000 {
	compatible = "renesas,msiof-r8a774c0",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6ea0000 0 0x0064>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 210>;
	dmas = <&dmac1 0x43>, <&dmac1 0x42>,
	<&dmac2 0x43>, <&dmac2 0x42>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 210>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof2: spi@e6c00000 {
	compatible = "renesas,msiof-r8a774c0",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c00000 0 0x0064>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 209>;
	dmas = <&dmac0 0x45>, <&dmac0 0x44>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 209>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof3: spi@e6c10000 {
	compatible = "renesas,msiof-r8a774c0",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c10000 0 0x0064>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 208>;
	dmas = <&dmac0 0x47>, <&dmac0 0x46>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 208>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	vin4: video@e6ef4000 {
	compatible = "renesas,vin-r8a774c0";
	reg = <0 0xe6ef4000 0 0x1000>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 807>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 807>;
	renesas,id = <4>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin4csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint= <&csi40vin4>;
	};
	};
	};
	};

	vin5: video@e6ef5000 {
	compatible = "renesas,vin-r8a774c0";
	reg = <0 0xe6ef5000 0 0x1000>;
	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 806>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 806>;
	renesas,id = <5>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin5csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint= <&csi40vin5>;
	};
	};
	};
	};

	rcar_sound: sound@ec500000 {
	/*
	* #sound-dai-cells is required
	*
	* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
	* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
	*/
	/*
	* #clock-cells is required for audio_clkout0/1/2/3
	*
	* clkout : #clock-cells = <0>; <&rcar_sound>;
	* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
	*/
	compatible = "renesas,rcar_sound-r8a774c0",
	"renesas,rcar_sound-gen3";
	reg = <0 0xec500000 0 0x1000>, /* SCU */
	<0 0xec5a0000 0 0x100>, /* ADG */
	<0 0xec540000 0 0x1000>, /* SSIU */
	<0 0xec541000 0 0x280>, /* SSI */
	<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
	reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

	clocks = <&cpg CPG_MOD 1005>,
	<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
	<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
	<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
	<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
	<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	<&audio_clk_a>, <&audio_clk_b>,
	<&audio_clk_c>,
	<&cpg CPG_CORE R8A774C0_CLK_ZA2>;
	clock-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0",
	"src.9", "src.8", "src.7", "src.6",
	"src.5", "src.4", "src.3", "src.2",
	"src.1", "src.0",
	"mix.1", "mix.0",
	"ctu.1", "ctu.0",
	"dvc.0", "dvc.1",
	"clk_a", "clk_b", "clk_c", "clk_i";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 1005>,
	<&cpg 1006>, <&cpg 1007>,
	<&cpg 1008>, <&cpg 1009>,
	<&cpg 1010>, <&cpg 1011>,
	<&cpg 1012>, <&cpg 1013>,
	<&cpg 1014>, <&cpg 1015>;
	reset-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0";
	status = "disabled";

	rcar_sound,ctu {
	ctu00: ctu-0 { };
	ctu01: ctu-1 { };
	ctu02: ctu-2 { };
	ctu03: ctu-3 { };
	ctu10: ctu-4 { };
	ctu11: ctu-5 { };
	ctu12: ctu-6 { };
	ctu13: ctu-7 { };
	};

	rcar_sound,dvc {
	dvc0: dvc-0 {
	dmas = <&audma0 0xbc>;
	dma-names = "tx";
	};
	dvc1: dvc-1 {
	dmas = <&audma0 0xbe>;
	dma-names = "tx";
	};
	};

	rcar_sound,mix {
	mix0: mix-0 { };
	mix1: mix-1 { };
	};

	rcar_sound,src {
	src0: src-0 {
	interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x85>, <&audma0 0x9a>;
	dma-names = "rx", "tx";
	};
	src1: src-1 {
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x87>, <&audma0 0x9c>;
	dma-names = "rx", "tx";
	};
	src2: src-2 {
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x89>, <&audma0 0x9e>;
	dma-names = "rx", "tx";
	};
	src3: src-3 {
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8b>, <&audma0 0xa0>;
	dma-names = "rx", "tx";
	};
	src4: src-4 {
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8d>, <&audma0 0xb0>;
	dma-names = "rx", "tx";
	};
	src5: src-5 {
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8f>, <&audma0 0xb2>;
	dma-names = "rx", "tx";
	};
	src6: src-6 {
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x91>, <&audma0 0xb4>;
	dma-names = "rx", "tx";
	};
	src7: src-7 {
	interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x93>, <&audma0 0xb6>;
	dma-names = "rx", "tx";
	};
	src8: src-8 {
	interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x95>, <&audma0 0xb8>;
	dma-names = "rx", "tx";
	};
	src9: src-9 {
	interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x97>, <&audma0 0xba>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssi {
	ssi0: ssi-0 {
	interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x01>, <&audma0 0x02>,
	<&audma0 0x15>, <&audma0 0x16>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi1: ssi-1 {
	interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x03>, <&audma0 0x04>,
	<&audma0 0x49>, <&audma0 0x4a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi2: ssi-2 {
	interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x05>, <&audma0 0x06>,
	<&audma0 0x63>, <&audma0 0x64>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi3: ssi-3 {
	interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x07>, <&audma0 0x08>,
	<&audma0 0x6f>, <&audma0 0x70>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi4: ssi-4 {
	interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x09>, <&audma0 0x0a>,
	<&audma0 0x71>, <&audma0 0x72>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi5: ssi-5 {
	interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0b>, <&audma0 0x0c>,
	<&audma0 0x73>, <&audma0 0x74>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi6: ssi-6 {
	interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0d>, <&audma0 0x0e>,
	<&audma0 0x75>, <&audma0 0x76>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi7: ssi-7 {
	interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0f>, <&audma0 0x10>,
	<&audma0 0x79>, <&audma0 0x7a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi8: ssi-8 {
	interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x11>, <&audma0 0x12>,
	<&audma0 0x7b>, <&audma0 0x7c>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi9: ssi-9 {
	interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x13>, <&audma0 0x14>,
	<&audma0 0x7d>, <&audma0 0x7e>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	};
	};

	audma0: dma-controller@ec700000 {
	compatible = "renesas,dmac-r8a774c0",
	"renesas,rcar-dmac";
	reg = <0 0xec700000 0 0x10000>;
	interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 502>;
	clock-names = "fck";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 502>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
	<&ipmmu_mp 2>, <&ipmmu_mp 3>,
	<&ipmmu_mp 4>, <&ipmmu_mp 5>,
	<&ipmmu_mp 6>, <&ipmmu_mp 7>,
	<&ipmmu_mp 8>, <&ipmmu_mp 9>,
	<&ipmmu_mp 10>, <&ipmmu_mp 11>,
	<&ipmmu_mp 12>, <&ipmmu_mp 13>,
	<&ipmmu_mp 14>, <&ipmmu_mp 15>;
	};

	xhci0: usb@ee000000 {
	compatible = "renesas,xhci-r8a774c0",
	"renesas,rcar-gen3-xhci";
	reg = <0 0xee000000 0 0xc00>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	status = "disabled";
	};

	usb3_peri0: usb@ee020000 {
	compatible = "renesas,r8a774c0-usb3-peri",
	"renesas,rcar-gen3-usb3-peri";
	reg = <0 0xee020000 0 0x400>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	status = "disabled";
	};

	ohci0: usb@ee080000 {
	compatible = "generic-ohci";
	reg = <0 0xee080000 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	phys = <&usb2_phy0 1>;
	phy-names = "usb";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	status = "disabled";
	};

	ehci0: usb@ee080100 {
	compatible = "generic-ehci";
	reg = <0 0xee080100 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	phys = <&usb2_phy0 2>;
	phy-names = "usb";
	companion = <&ohci0>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	status = "disabled";
	};

	usb2_phy0: usb-phy@ee080200 {
	compatible = "renesas,usb2-phy-r8a774c0",
	"renesas,rcar-gen3-usb2-phy";
	reg = <0 0xee080200 0 0x700>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	#phy-cells = <1>;
	status = "disabled";
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a774c0",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee100000 0 0x2000>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	status = "disabled";
	};

	sdhi1: sd@ee120000 {
	compatible = "renesas,sdhi-r8a774c0",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee120000 0 0x2000>;
	interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 313>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 313>;
	status = "disabled";
	};

	sdhi3: sd@ee160000 {
	compatible = "renesas,sdhi-r8a774c0",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee160000 0 0x2000>;
	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 311>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 311>;
	status = "disabled";
	};

	gic: interrupt-controller@f1010000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x0 0xf1010000 0 0x1000>,
	<0x0 0xf1020000 0 0x20000>,
	<0x0 0xf1040000 0 0x20000>,
	<0x0 0xf1060000 0 0x20000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	pciec0: pcie@fe000000 {
	compatible = "renesas,pcie-r8a774c0",
	"renesas,pcie-rcar-gen3";
	reg = <0 0xfe000000 0 0x80000>;
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x00 0xff>;
	device_type = "pci";
	ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
	<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
	<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
	<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
	/* Map all possible DDR as inbound ranges */
	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
	clock-names = "pcie", "pcie_bus";
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 319>;
	status = "disabled";
	};

	vspb0: vsp@fe960000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe960000 0 0x8000>;
	interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 626>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 626>;
	renesas,fcp = <&fcpvb0>;
	};

	vspd0: vsp@fea20000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea20000 0 0x7000>;
	interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 623>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 623>;
	renesas,fcp = <&fcpvd0>;
	};

	vspd1: vsp@fea28000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea28000 0 0x7000>;
	interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 622>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 622>;
	renesas,fcp = <&fcpvd1>;
	};

	vspi0: vsp@fe9a0000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe9a0000 0 0x8000>;
	interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 631>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 631>;
	renesas,fcp = <&fcpvi0>;
	};

	fcpvb0: fcp@fe96f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe96f000 0 0x200>;
	clocks = <&cpg CPG_MOD 607>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 607>;
	iommus = <&ipmmu_vp0 5>;
	};

	fcpvd0: fcp@fea27000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea27000 0 0x200>;
	clocks = <&cpg CPG_MOD 603>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 603>;
	iommus = <&ipmmu_vi0 8>;
	};

	fcpvd1: fcp@fea2f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea2f000 0 0x200>;
	clocks = <&cpg CPG_MOD 602>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 602>;
	iommus = <&ipmmu_vi0 9>;
	};

	fcpvi0: fcp@fe9af000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe9af000 0 0x200>;
	clocks = <&cpg CPG_MOD 611>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 611>;
	iommus = <&ipmmu_vp0 8>;
	};

	csi40: csi2@feaa0000 {
	compatible = "renesas,r8a774c0-csi2";
	reg = <0 0xfeaa0000 0 0x10000>;
	interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	csi40vin4: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vin4csi40>;
	};
	csi40vin5: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vin5csi40>;
	};
	};
	};
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a774c0";
	reg = <0 0xfeb00000 0 0x40000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&cpg CPG_MOD 724>,
	- <&cpg CPG_MOD 723>;
	+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
	clock-names = "du.0", "du.1";
	- vsps = <&vspd0 0>, <&vspd1 0>;
	+ resets = <&cpg 724>;
	+ reset-names = "du.0";
	+ renesas,vsps = <&vspd0 0>, <&vspd1 0>;
	+
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb: endpoint {
	};
	};

	port@1 {
	reg = <1>;
	du_out_lvds0: endpoint {
	remote-endpoint = <&lvds0_in>;
	};
	};

	port@2 {
	reg = <2>;
	du_out_lvds1: endpoint {
	remote-endpoint = <&lvds1_in>;
	};
	};
	};
	};

	lvds0: lvds-encoder@feb90000 {
	compatible = "renesas,r8a774c0-lvds";
	reg = <0 0xfeb90000 0 0x20>;
	clocks = <&cpg CPG_MOD 727>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 727>;
	status = "disabled";

	renesas,companion = <&lvds1>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds0_in: endpoint {
	remote-endpoint = <&du_out_lvds0>;
	};
	};

	port@1 {
	reg = <1>;
	lvds0_out: endpoint {
	};
	};
	};
	};

	lvds1: lvds-encoder@feb90100 {
	compatible = "renesas,r8a774c0-lvds";
	reg = <0 0xfeb90100 0 0x20>;
	clocks = <&cpg CPG_MOD 727>;
	power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
	resets = <&cpg 726>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds1_in: endpoint {
	remote-endpoint = <&du_out_lvds1>;
	};
	};

	port@1 {
	reg = <1>;
	lvds1_out: endpoint {
	};
	};
	};
	};

	prr: chipid@fff00044 {
	compatible = "renesas,prr";
	reg = <0 0xfff00044 0 4>;
	};
	};

	thermal-zones {
	cpu-thermal {
	polling-delay-passive = <250>;
	polling-delay = <0>;
	thermal-sensors = <&thermal 0>;
	sustainable-power = <717>;

	cooling-maps {
	map0 {
	trip = <&target>;
	cooling-device = <&a53_0 0 2>;
	contribution = <1024>;
	};
	};

	trips {
	sensor1_crit: sensor1-crit {
	temperature = <120000>;
	hysteresis = <2000>;
	type = "critical";
	};

	target: trip-point1 {
	temperature = <100000>;
	hysteresis = <2000>;
	type = "passive";
	};
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clocks - can be overridden by the board */
	usb3s0_clk: usb3s0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	usb_extal_clk: usb_extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a77950.dtsi b/sys/gnu/dts/arm64/renesas/r8a77950.dtsi
	index 15216495e1c8..3975eecd50c4 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a77950.dtsi
	+++ b/sys/gnu/dts/arm64/renesas/r8a77950.dtsi
	@@ -1,319 +1,319 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the R-Car H3 (R8A77950) SoC
	*
	* Copyright (C) 2015 Renesas Electronics Corp.
	*/

	#include "r8a77951.dtsi"

	&audma0 {
	iommus = <&ipmmu_mp1 0>, <&ipmmu_mp1 1>,
	<&ipmmu_mp1 2>, <&ipmmu_mp1 3>,
	<&ipmmu_mp1 4>, <&ipmmu_mp1 5>,
	<&ipmmu_mp1 6>, <&ipmmu_mp1 7>,
	<&ipmmu_mp1 8>, <&ipmmu_mp1 9>,
	<&ipmmu_mp1 10>, <&ipmmu_mp1 11>,
	<&ipmmu_mp1 12>, <&ipmmu_mp1 13>,
	<&ipmmu_mp1 14>, <&ipmmu_mp1 15>;
	};

	&audma1 {
	iommus = <&ipmmu_mp1 16>, <&ipmmu_mp1 17>,
	<&ipmmu_mp1 18>, <&ipmmu_mp1 19>,
	<&ipmmu_mp1 20>, <&ipmmu_mp1 21>,
	<&ipmmu_mp1 22>, <&ipmmu_mp1 23>,
	<&ipmmu_mp1 24>, <&ipmmu_mp1 25>,
	<&ipmmu_mp1 26>, <&ipmmu_mp1 27>,
	<&ipmmu_mp1 28>, <&ipmmu_mp1 29>,
	<&ipmmu_mp1 30>, <&ipmmu_mp1 31>;
	};

	&du {
	- vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>;
	+ renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>;
	};

	&fcpvb1 {
	iommus = <&ipmmu_vp0 7>;
	};

	&fcpf1 {
	iommus = <&ipmmu_vp0 1>;
	};

	&fcpvi1 {
	iommus = <&ipmmu_vp0 9>;
	};

	&fcpvd2 {
	iommus = <&ipmmu_vi0 10>;
	};

	&gpio1 {
	gpio-ranges = <&pfc 0 32 28>;
	};

	&ipmmu_vi0 {
	renesas,ipmmu-main = <&ipmmu_mm 11>;
	};

	&ipmmu_vp0 {
	renesas,ipmmu-main = <&ipmmu_mm 12>;
	};

	&ipmmu_vc0 {
	renesas,ipmmu-main = <&ipmmu_mm 9>;
	};

	&ipmmu_vc1 {
	renesas,ipmmu-main = <&ipmmu_mm 10>;
	};

	&ipmmu_rt {
	renesas,ipmmu-main = <&ipmmu_mm 7>;
	};

	&soc {
	/delete-node/ dma-controller@e6460000;
	/delete-node/ dma-controller@e6470000;

	ipmmu_mp1: mmu@ec680000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xec680000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 5>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_sy: mmu@e7730000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xe7730000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 8>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	/delete-node/ mmu@fd950000;
	/delete-node/ mmu@fd960000;
	/delete-node/ mmu@fd970000;
	/delete-node/ mmu@febe0000;
	/delete-node/ mmu@fe980000;

	xhci1: usb@ee040000 {
	compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
	reg = <0 0xee040000 0 0xc00>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 327>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 327>;
	status = "disabled";
	};

	/delete-node/ usb@e659c000;
	/delete-node/ usb@ee0e0000;
	/delete-node/ usb@ee0e0100;

	/delete-node/ usb-phy@ee0e0200;

	fdp1@fe948000 {
	compatible = "renesas,fdp1";
	reg = <0 0xfe948000 0 0x2400>;
	interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 117>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	resets = <&cpg 117>;
	renesas,fcp = <&fcpf2>;
	};

	fcpf2: fcp@fe952000 {
	compatible = "renesas,fcpf";
	reg = <0 0xfe952000 0 0x200>;
	clocks = <&cpg CPG_MOD 613>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	resets = <&cpg 613>;
	iommus = <&ipmmu_vp0 2>;
	};

	fcpvd3: fcp@fea3f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea3f000 0 0x200>;
	clocks = <&cpg CPG_MOD 600>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 600>;
	iommus = <&ipmmu_vi0 11>;
	};

	fcpvi2: fcp@fe9cf000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe9cf000 0 0x200>;
	clocks = <&cpg CPG_MOD 609>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	resets = <&cpg 609>;
	iommus = <&ipmmu_vp0 10>;
	};

	vspd3: vsp@fea38000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea38000 0 0x5000>;
	interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 620>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 620>;

	renesas,fcp = <&fcpvd3>;
	};

	vspi2: vsp@fe9c0000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe9c0000 0 0x8000>;
	interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 629>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	resets = <&cpg 629>;

	renesas,fcp = <&fcpvi2>;
	};

	csi21: csi2@fea90000 {
	compatible = "renesas,r8a7795-csi2";
	reg = <0 0xfea90000 0 0x10000>;
	interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 713>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 713>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	csi21vin0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vin0csi21>;
	};
	csi21vin1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vin1csi21>;
	};
	csi21vin2: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&vin2csi21>;
	};
	csi21vin3: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&vin3csi21>;
	};
	csi21vin4: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&vin4csi21>;
	};
	csi21vin5: endpoint@5 {
	reg = <5>;
	remote-endpoint = <&vin5csi21>;
	};
	csi21vin6: endpoint@6 {
	reg = <6>;
	remote-endpoint = <&vin6csi21>;
	};
	csi21vin7: endpoint@7 {
	reg = <7>;
	remote-endpoint = <&vin7csi21>;
	};
	};
	};
	};
	};

	&vin0 {
	ports {
	port@1 {
	vin0csi21: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&csi21vin0>;
	};
	};
	};
	};

	&vin1 {
	ports {
	port@1 {
	vin1csi21: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&csi21vin1>;
	};
	};
	};
	};

	&vin2 {
	ports {
	port@1 {
	vin2csi21: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&csi21vin2>;
	};
	};
	};
	};

	&vin3 {
	ports {
	port@1 {
	vin3csi21: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&csi21vin3>;
	};
	};
	};
	};

	&vin4 {
	ports {
	port@1 {
	vin4csi21: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&csi21vin4>;
	};
	};
	};
	};

	&vin5 {
	ports {
	port@1 {
	vin5csi21: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&csi21vin5>;
	};
	};
	};
	};

	&vin6 {
	ports {
	port@1 {
	vin6csi21: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&csi21vin6>;
	};
	};
	};
	};

	&vin7 {
	ports {
	port@1 {
	vin7csi21: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&csi21vin7>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a77951.dtsi b/sys/gnu/dts/arm64/renesas/r8a77951.dtsi
	index a8729eb744db..52229546454c 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a77951.dtsi
	+++ b/sys/gnu/dts/arm64/renesas/r8a77951.dtsi
	@@ -1,3339 +1,3340 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the R-Car H3 (R8A77951) SoC
	*
	* Copyright (C) 2015 Renesas Electronics Corp.
	*/

	#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/power/r8a7795-sysc.h>

	#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4

	/ {
	compatible = "renesas,r8a7795";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	i2c6 = &i2c6;
	i2c7 = &i2c_dvfs;
	};

	/*
	* The external audio clocks are configured as 0 Hz fixed frequency
	* clocks by default.
	* Boards that provide audio clocks should override them.
	*/
	audio_clk_a: audio_clk_a {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_b: audio_clk_b {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_c: audio_clk_c {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	/* External CAN clock - to be overridden by boards that provide it */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	cluster0_opp: opp_table0 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-500000000 {
	opp-hz = /bits/ 64 <500000000>;
	opp-microvolt = <830000>;
	clock-latency-ns = <300000>;
	};
	opp-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	opp-microvolt = <830000>;
	clock-latency-ns = <300000>;
	};
	opp-1500000000 {
	opp-hz = /bits/ 64 <1500000000>;
	opp-microvolt = <830000>;
	clock-latency-ns = <300000>;
	opp-suspend;
	};
	opp-1600000000 {
	opp-hz = /bits/ 64 <1600000000>;
	opp-microvolt = <900000>;
	clock-latency-ns = <300000>;
	turbo-mode;
	};
	opp-1700000000 {
	opp-hz = /bits/ 64 <1700000000>;
	opp-microvolt = <960000>;
	clock-latency-ns = <300000>;
	turbo-mode;
	};
	};

	cluster1_opp: opp_table1 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-800000000 {
	opp-hz = /bits/ 64 <800000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu-map {
	cluster0 {
	core0 {
	cpu = <&a57_0>;
	};
	core1 {
	cpu = <&a57_1>;
	};
	core2 {
	cpu = <&a57_2>;
	};
	core3 {
	cpu = <&a57_3>;
	};
	};

	cluster1 {
	core0 {
	cpu = <&a53_0>;
	};
	core1 {
	cpu = <&a53_1>;
	};
	core2 {
	cpu = <&a53_2>;
	};
	core3 {
	cpu = <&a53_3>;
	};
	};
	};

	a57_0: cpu@0 {
	compatible = "arm,cortex-a57";
	reg = <0x0>;
	device_type = "cpu";
	power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
	next-level-cache = <&L2_CA57>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	dynamic-power-coefficient = <854>;
	clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
	operating-points-v2 = <&cluster0_opp>;
	capacity-dmips-mhz = <1024>;
	#cooling-cells = <2>;
	};

	a57_1: cpu@1 {
	compatible = "arm,cortex-a57";
	reg = <0x1>;
	device_type = "cpu";
	power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
	next-level-cache = <&L2_CA57>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
	operating-points-v2 = <&cluster0_opp>;
	capacity-dmips-mhz = <1024>;
	#cooling-cells = <2>;
	};

	a57_2: cpu@2 {
	compatible = "arm,cortex-a57";
	reg = <0x2>;
	device_type = "cpu";
	power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
	next-level-cache = <&L2_CA57>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
	operating-points-v2 = <&cluster0_opp>;
	capacity-dmips-mhz = <1024>;
	#cooling-cells = <2>;
	};

	a57_3: cpu@3 {
	compatible = "arm,cortex-a57";
	reg = <0x3>;
	device_type = "cpu";
	power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
	next-level-cache = <&L2_CA57>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
	operating-points-v2 = <&cluster0_opp>;
	capacity-dmips-mhz = <1024>;
	#cooling-cells = <2>;
	};

	a53_0: cpu@100 {
	compatible = "arm,cortex-a53";
	reg = <0x100>;
	device_type = "cpu";
	power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_1>;
	#cooling-cells = <2>;
	dynamic-power-coefficient = <277>;
	clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	capacity-dmips-mhz = <535>;
	};

	a53_1: cpu@101 {
	compatible = "arm,cortex-a53";
	reg = <0x101>;
	device_type = "cpu";
	power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_1>;
	clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	capacity-dmips-mhz = <535>;
	};

	a53_2: cpu@102 {
	compatible = "arm,cortex-a53";
	reg = <0x102>;
	device_type = "cpu";
	power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_1>;
	clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	capacity-dmips-mhz = <535>;
	};

	a53_3: cpu@103 {
	compatible = "arm,cortex-a53";
	reg = <0x103>;
	device_type = "cpu";
	power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_1>;
	clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	capacity-dmips-mhz = <535>;
	};

	L2_CA57: cache-controller-0 {
	compatible = "cache";
	power-domains = <&sysc R8A7795_PD_CA57_SCU>;
	cache-unified;
	cache-level = <2>;
	};

	L2_CA53: cache-controller-1 {
	compatible = "cache";
	power-domains = <&sysc R8A7795_PD_CA53_SCU>;
	cache-unified;
	cache-level = <2>;
	};

	idle-states {
	entry-method = "psci";

	CPU_SLEEP_0: cpu-sleep-0 {
	compatible = "arm,idle-state";
	arm,psci-suspend-param = <0x0010000>;
	local-timer-stop;
	entry-latency-us = <400>;
	exit-latency-us = <500>;
	min-residency-us = <4000>;
	};

	CPU_SLEEP_1: cpu-sleep-1 {
	compatible = "arm,idle-state";
	arm,psci-suspend-param = <0x0010000>;
	local-timer-stop;
	entry-latency-us = <700>;
	exit-latency-us = <700>;
	min-residency-us = <5000>;
	};
	};
	};

	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	extalr_clk: extalr {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	/* External PCIe clock - can be overridden by the board */
	pcie_bus_clk: pcie_bus {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	pmu_a53 {
	compatible = "arm,cortex-a53-pmu";
	interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&a53_0>,
	<&a53_1>,
	<&a53_2>,
	<&a53_3>;
	};

	pmu_a57 {
	compatible = "arm,cortex-a57-pmu";
	interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&a57_0>,
	<&a57_1>,
	<&a57_2>,
	<&a57_3>;
	};

	psci {
	compatible = "arm,psci-1.0", "arm,psci-0.2";
	method = "smc";
	};

	/* External SCIF clock - to be overridden by boards that provide it */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	soc: soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;

	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a7795",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 16>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a7795",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 29>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a7795",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 15>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a7795",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 16>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a7795",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 18>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a7795",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	gpio6: gpio@e6055400 {
	compatible = "renesas,gpio-r8a7795",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055400 0 0x50>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 192 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 906>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 906>;
	};

	gpio7: gpio@e6055800 {
	compatible = "renesas,gpio-r8a7795",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055800 0 0x50>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 224 4>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 905>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 905>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a7795";
	reg = <0 0xe6060000 0 0x50c>;
	};

	cmt0: timer@e60f0000 {
	compatible = "renesas,r8a7795-cmt0",
	"renesas,rcar-gen3-cmt0";
	reg = <0 0xe60f0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 303>;
	clock-names = "fck";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 303>;
	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a7795-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 302>;
	clock-names = "fck";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 302>;
	status = "disabled";
	};

	cmt2: timer@e6140000 {
	compatible = "renesas,r8a7795-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6140000 0 0x1004>;
	interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 301>;
	clock-names = "fck";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 301>;
	status = "disabled";
	};

	cmt3: timer@e6148000 {
	compatible = "renesas,r8a7795-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6148000 0 0x1004>;
	interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 300>;
	clock-names = "fck";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 300>;
	status = "disabled";
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a7795-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>, <&extalr_clk>;
	clock-names = "extal", "extalr";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a7795-rst";
	reg = <0 0xe6160000 0 0x0200>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a7795-sysc";
	reg = <0 0xe6180000 0 0x0400>;
	#power-domain-cells = <1>;
	};

	tsc: thermal@e6198000 {
	compatible = "renesas,r8a7795-thermal";
	reg = <0 0xe6198000 0 0x100>,
	<0 0xe61a0000 0 0x100>,
	<0 0xe61a8000 0 0x100>;
	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 522>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 522>;
	#thermal-sensor-cells = <1>;
	};

	intc_ex: interrupt-controller@e61c0000 {
	compatible = "renesas,intc-ex-r8a7795", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	i2c0: i2c@e6500000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7795",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6500000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	dmas = <&dmac1 0x91>, <&dmac1 0x90>,
	<&dmac2 0x91>, <&dmac2 0x90>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c1: i2c@e6508000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7795",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	dmas = <&dmac1 0x93>, <&dmac1 0x92>,
	<&dmac2 0x93>, <&dmac2 0x92>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c2: i2c@e6510000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7795",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6510000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	dmas = <&dmac1 0x95>, <&dmac1 0x94>,
	<&dmac2 0x95>, <&dmac2 0x94>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c3: i2c@e66d0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7795",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d0000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	dmas = <&dmac0 0x97>, <&dmac0 0x96>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c4: i2c@e66d8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7795",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d8000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	dmas = <&dmac0 0x99>, <&dmac0 0x98>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c5: i2c@e66e0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7795",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66e0000 0 0x40>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 919>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 919>;
	dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c6: i2c@e66e8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7795",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66e8000 0 0x40>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 918>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 918>;
	dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c_dvfs: i2c@e60b0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7795",
	"renesas,rcar-gen3-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe60b0000 0 0x425>;
	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 926>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 926>;
	dmas = <&dmac0 0x11>, <&dmac0 0x10>;
	dma-names = "tx", "rx";
	status = "disabled";
	};

	hscif0: serial@e6540000 {
	compatible = "renesas,hscif-r8a7795",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6540000 0 96>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 520>,
	<&cpg CPG_CORE R8A7795_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x31>, <&dmac1 0x30>,
	<&dmac2 0x31>, <&dmac2 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 520>;
	status = "disabled";
	};

	hscif1: serial@e6550000 {
	compatible = "renesas,hscif-r8a7795",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6550000 0 96>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 519>,
	<&cpg CPG_CORE R8A7795_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x33>, <&dmac1 0x32>,
	<&dmac2 0x33>, <&dmac2 0x32>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 519>;
	status = "disabled";
	};

	hscif2: serial@e6560000 {
	compatible = "renesas,hscif-r8a7795",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6560000 0 96>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 518>,
	<&cpg CPG_CORE R8A7795_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x35>, <&dmac1 0x34>,
	<&dmac2 0x35>, <&dmac2 0x34>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 518>;
	status = "disabled";
	};

	hscif3: serial@e66a0000 {
	compatible = "renesas,hscif-r8a7795",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe66a0000 0 96>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 517>,
	<&cpg CPG_CORE R8A7795_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x37>, <&dmac0 0x36>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 517>;
	status = "disabled";
	};

	hscif4: serial@e66b0000 {
	compatible = "renesas,hscif-r8a7795",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe66b0000 0 96>;
	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 516>,
	<&cpg CPG_CORE R8A7795_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x39>, <&dmac0 0x38>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 516>;
	status = "disabled";
	};

	hsusb: usb@e6590000 {
	compatible = "renesas,usbhs-r8a7795",
	"renesas,rcar-gen3-usbhs";
	reg = <0 0xe6590000 0 0x200>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
	dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
	<&usb_dmac1 0>, <&usb_dmac1 1>;
	dma-names = "ch0", "ch1", "ch2", "ch3";
	renesas,buswait = <11>;
	phys = <&usb2_phy0 3>;
	phy-names = "usb";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 704>, <&cpg 703>;
	status = "disabled";
	};

	hsusb3: usb@e659c000 {
	compatible = "renesas,usbhs-r8a7795",
	"renesas,rcar-gen3-usbhs";
	reg = <0 0xe659c000 0 0x200>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 705>, <&cpg CPG_MOD 700>;
	dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
	<&usb_dmac3 0>, <&usb_dmac3 1>;
	dma-names = "ch0", "ch1", "ch2", "ch3";
	renesas,buswait = <11>;
	phys = <&usb2_phy3 3>;
	phy-names = "usb";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 705>, <&cpg 700>;
	status = "disabled";
	};

	usb_dmac0: dma-controller@e65a0000 {
	compatible = "renesas,r8a7795-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65a0000 0 0x100>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 330>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 330>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac1: dma-controller@e65b0000 {
	compatible = "renesas,r8a7795-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65b0000 0 0x100>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 331>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 331>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac2: dma-controller@e6460000 {
	compatible = "renesas,r8a7795-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe6460000 0 0x100>;
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 326>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 326>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac3: dma-controller@e6470000 {
	compatible = "renesas,r8a7795-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe6470000 0 0x100>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 329>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 329>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb3_phy0: usb-phy@e65ee000 {
	compatible = "renesas,r8a7795-usb3-phy",
	"renesas,rcar-gen3-usb3-phy";
	reg = <0 0xe65ee000 0 0x90>;
	clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
	<&usb_extal_clk>;
	clock-names = "usb3-if", "usb3s_clk", "usb_extal";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	#phy-cells = <0>;
	status = "disabled";
	};

	arm_cc630p: crypto@e6601000 {
	compatible = "arm,cryptocell-630p-ree";
	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x0 0xe6601000 0 0x1000>;
	clocks = <&cpg CPG_MOD 229>;
	resets = <&cpg 229>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	};

	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a7795",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x10000>;
	interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
	<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
	<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
	<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
	<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
	<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
	<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
	<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
	};

	dmac1: dma-controller@e7300000 {
	compatible = "renesas,dmac-r8a7795",
	"renesas,rcar-dmac";
	reg = <0 0xe7300000 0 0x10000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
	<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
	<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
	<&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
	<&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
	<&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
	<&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
	<&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
	};

	dmac2: dma-controller@e7310000 {
	compatible = "renesas,dmac-r8a7795",
	"renesas,rcar-dmac";
	reg = <0 0xe7310000 0 0x10000>;
	interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 217>;
	clock-names = "fck";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 217>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
	<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
	<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
	<&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
	<&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
	<&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
	<&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
	<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
	};

	ipmmu_ds0: mmu@e6740000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xe6740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 0>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_ds1: mmu@e7740000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xe7740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 1>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_hc: mmu@e6570000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xe6570000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 2>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_ir: mmu@ff8b0000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xff8b0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 3>;
	power-domains = <&sysc R8A7795_PD_A3IR>;
	#iommu-cells = <1>;
	};

	ipmmu_mm: mmu@e67b0000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xe67b0000 0 0x1000>;
	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_mp0: mmu@ec670000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xec670000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 4>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_pv0: mmu@fd800000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xfd800000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 6>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_pv1: mmu@fd950000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xfd950000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 7>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_pv2: mmu@fd960000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xfd960000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 8>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_pv3: mmu@fd970000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xfd970000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 9>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_rt: mmu@ffc80000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xffc80000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 10>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vc0: mmu@fe6b0000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xfe6b0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 12>;
	power-domains = <&sysc R8A7795_PD_A3VC>;
	#iommu-cells = <1>;
	};

	ipmmu_vc1: mmu@fe6f0000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xfe6f0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 13>;
	power-domains = <&sysc R8A7795_PD_A3VC>;
	#iommu-cells = <1>;
	};

	ipmmu_vi0: mmu@febd0000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xfebd0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 14>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vi1: mmu@febe0000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xfebe0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 15>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vp0: mmu@fe990000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xfe990000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 16>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	#iommu-cells = <1>;
	};

	ipmmu_vp1: mmu@fe980000 {
	compatible = "renesas,ipmmu-r8a7795";
	reg = <0 0xfe980000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 17>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	#iommu-cells = <1>;
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a7795",
	"renesas,etheravb-rcar-gen3";
	reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15",
	"ch16", "ch17", "ch18", "ch19",
	"ch20", "ch21", "ch22", "ch23",
	"ch24";
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	phy-mode = "rgmii";
	iommus = <&ipmmu_ds0 16>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	can0: can@e6c30000 {
	compatible = "renesas,can-r8a7795",
	"renesas,rcar-gen3-can";
	reg = <0 0xe6c30000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 916>,
	<&cpg CPG_CORE R8A7795_CLK_CANFD>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 916>;
	status = "disabled";
	};

	can1: can@e6c38000 {
	compatible = "renesas,can-r8a7795",
	"renesas,rcar-gen3-can";
	reg = <0 0xe6c38000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 915>,
	<&cpg CPG_CORE R8A7795_CLK_CANFD>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 915>;
	status = "disabled";
	};

	canfd: can@e66c0000 {
	compatible = "renesas,r8a7795-canfd",
	"renesas,rcar-gen3-canfd";
	reg = <0 0xe66c0000 0 0x8000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 914>,
	<&cpg CPG_CORE R8A7795_CLK_CANFD>,
	<&can_clk>;
	clock-names = "fck", "canfd", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 914>;
	status = "disabled";

	channel0 {
	status = "disabled";
	};

	channel1 {
	status = "disabled";
	};
	};

	pwm0: pwm@e6e30000 {
	compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
	reg = <0 0xe6e30000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm1: pwm@e6e31000 {
	compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
	reg = <0 0xe6e31000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm2: pwm@e6e32000 {
	compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
	reg = <0 0xe6e32000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm3: pwm@e6e33000 {
	compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
	reg = <0 0xe6e33000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm4: pwm@e6e34000 {
	compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
	reg = <0 0xe6e34000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm5: pwm@e6e35000 {
	compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
	reg = <0 0xe6e35000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm6: pwm@e6e36000 {
	compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
	reg = <0 0xe6e36000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a7795",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e60000 0 64>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 207>,
	<&cpg CPG_CORE R8A7795_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x51>, <&dmac1 0x50>,
	<&dmac2 0x51>, <&dmac2 0x50>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 207>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a7795",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e68000 0 64>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 206>,
	<&cpg CPG_CORE R8A7795_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x53>, <&dmac1 0x52>,
	<&dmac2 0x53>, <&dmac2 0x52>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 206>;
	status = "disabled";
	};

	scif2: serial@e6e88000 {
	compatible = "renesas,scif-r8a7795",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e88000 0 64>;
	interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 310>,
	<&cpg CPG_CORE R8A7795_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x13>, <&dmac1 0x12>,
	<&dmac2 0x13>, <&dmac2 0x12>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 310>;
	status = "disabled";
	};

	scif3: serial@e6c50000 {
	compatible = "renesas,scif-r8a7795",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6c50000 0 64>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 204>,
	<&cpg CPG_CORE R8A7795_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x57>, <&dmac0 0x56>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 204>;
	status = "disabled";
	};

	scif4: serial@e6c40000 {
	compatible = "renesas,scif-r8a7795",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6c40000 0 64>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 203>,
	<&cpg CPG_CORE R8A7795_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x59>, <&dmac0 0x58>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 203>;
	status = "disabled";
	};

	scif5: serial@e6f30000 {
	compatible = "renesas,scif-r8a7795",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6f30000 0 64>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 202>,
	<&cpg CPG_CORE R8A7795_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
	<&dmac2 0x5b>, <&dmac2 0x5a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 202>;
	status = "disabled";
	};

	tpu: pwm@e6e80000 {
	compatible = "renesas,tpu-r8a7795", "renesas,tpu";
	reg = <0 0xe6e80000 0 0x148>;
	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 304>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 304>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	msiof0: spi@e6e90000 {
	compatible = "renesas,msiof-r8a7795",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6e90000 0 0x0064>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 211>;
	dmas = <&dmac1 0x41>, <&dmac1 0x40>,
	<&dmac2 0x41>, <&dmac2 0x40>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 211>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof1: spi@e6ea0000 {
	compatible = "renesas,msiof-r8a7795",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6ea0000 0 0x0064>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 210>;
	dmas = <&dmac1 0x43>, <&dmac1 0x42>,
	<&dmac2 0x43>, <&dmac2 0x42>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 210>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof2: spi@e6c00000 {
	compatible = "renesas,msiof-r8a7795",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c00000 0 0x0064>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 209>;
	dmas = <&dmac0 0x45>, <&dmac0 0x44>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 209>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof3: spi@e6c10000 {
	compatible = "renesas,msiof-r8a7795",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c10000 0 0x0064>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 208>;
	dmas = <&dmac0 0x47>, <&dmac0 0x46>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 208>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	vin0: video@e6ef0000 {
	compatible = "renesas,vin-r8a7795";
	reg = <0 0xe6ef0000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 811>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 811>;
	renesas,id = <0>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin0csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin0>;
	};
	vin0csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin0>;
	};
	};
	};
	};

	vin1: video@e6ef1000 {
	compatible = "renesas,vin-r8a7795";
	reg = <0 0xe6ef1000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 810>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 810>;
	renesas,id = <1>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin1csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin1>;
	};
	vin1csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin1>;
	};
	};
	};
	};

	vin2: video@e6ef2000 {
	compatible = "renesas,vin-r8a7795";
	reg = <0 0xe6ef2000 0 0x1000>;
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 809>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 809>;
	renesas,id = <2>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin2csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin2>;
	};
	vin2csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin2>;
	};
	};
	};
	};

	vin3: video@e6ef3000 {
	compatible = "renesas,vin-r8a7795";
	reg = <0 0xe6ef3000 0 0x1000>;
	interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 808>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 808>;
	renesas,id = <3>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin3csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin3>;
	};
	vin3csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin3>;
	};
	};
	};
	};

	vin4: video@e6ef4000 {
	compatible = "renesas,vin-r8a7795";
	reg = <0 0xe6ef4000 0 0x1000>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 807>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 807>;
	renesas,id = <4>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin4csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin4>;
	};
	vin4csi41: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&csi41vin4>;
	};
	};
	};
	};

	vin5: video@e6ef5000 {
	compatible = "renesas,vin-r8a7795";
	reg = <0 0xe6ef5000 0 0x1000>;
	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 806>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 806>;
	renesas,id = <5>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin5csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin5>;
	};
	vin5csi41: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&csi41vin5>;
	};
	};
	};
	};

	vin6: video@e6ef6000 {
	compatible = "renesas,vin-r8a7795";
	reg = <0 0xe6ef6000 0 0x1000>;
	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 805>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 805>;
	renesas,id = <6>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin6csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin6>;
	};
	vin6csi41: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&csi41vin6>;
	};
	};
	};
	};

	vin7: video@e6ef7000 {
	compatible = "renesas,vin-r8a7795";
	reg = <0 0xe6ef7000 0 0x1000>;
	interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 804>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 804>;
	renesas,id = <7>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin7csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin7>;
	};
	vin7csi41: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&csi41vin7>;
	};
	};
	};
	};

	drif00: rif@e6f40000 {
	compatible = "renesas,r8a7795-drif",
	"renesas,rcar-gen3-drif";
	reg = <0 0xe6f40000 0 0x64>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 515>;
	clock-names = "fck";
	dmas = <&dmac1 0x20>, <&dmac2 0x20>;
	dma-names = "rx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 515>;
	renesas,bonding = <&drif01>;
	status = "disabled";
	};

	drif01: rif@e6f50000 {
	compatible = "renesas,r8a7795-drif",
	"renesas,rcar-gen3-drif";
	reg = <0 0xe6f50000 0 0x64>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 514>;
	clock-names = "fck";
	dmas = <&dmac1 0x22>, <&dmac2 0x22>;
	dma-names = "rx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 514>;
	renesas,bonding = <&drif00>;
	status = "disabled";
	};

	drif10: rif@e6f60000 {
	compatible = "renesas,r8a7795-drif",
	"renesas,rcar-gen3-drif";
	reg = <0 0xe6f60000 0 0x64>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 513>;
	clock-names = "fck";
	dmas = <&dmac1 0x24>, <&dmac2 0x24>;
	dma-names = "rx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 513>;
	renesas,bonding = <&drif11>;
	status = "disabled";
	};

	drif11: rif@e6f70000 {
	compatible = "renesas,r8a7795-drif",
	"renesas,rcar-gen3-drif";
	reg = <0 0xe6f70000 0 0x64>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 512>;
	clock-names = "fck";
	dmas = <&dmac1 0x26>, <&dmac2 0x26>;
	dma-names = "rx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 512>;
	renesas,bonding = <&drif10>;
	status = "disabled";
	};

	drif20: rif@e6f80000 {
	compatible = "renesas,r8a7795-drif",
	"renesas,rcar-gen3-drif";
	reg = <0 0xe6f80000 0 0x64>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 511>;
	clock-names = "fck";
	dmas = <&dmac1 0x28>, <&dmac2 0x28>;
	dma-names = "rx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 511>;
	renesas,bonding = <&drif21>;
	status = "disabled";
	};

	drif21: rif@e6f90000 {
	compatible = "renesas,r8a7795-drif",
	"renesas,rcar-gen3-drif";
	reg = <0 0xe6f90000 0 0x64>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 510>;
	clock-names = "fck";
	dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
	dma-names = "rx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 510>;
	renesas,bonding = <&drif20>;
	status = "disabled";
	};

	drif30: rif@e6fa0000 {
	compatible = "renesas,r8a7795-drif",
	"renesas,rcar-gen3-drif";
	reg = <0 0xe6fa0000 0 0x64>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 509>;
	clock-names = "fck";
	dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
	dma-names = "rx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 509>;
	renesas,bonding = <&drif31>;
	status = "disabled";
	};

	drif31: rif@e6fb0000 {
	compatible = "renesas,r8a7795-drif",
	"renesas,rcar-gen3-drif";
	reg = <0 0xe6fb0000 0 0x64>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 508>;
	clock-names = "fck";
	dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
	dma-names = "rx", "rx";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 508>;
	renesas,bonding = <&drif30>;
	status = "disabled";
	};

	rcar_sound: sound@ec500000 {
	/*
	* #sound-dai-cells is required
	*
	* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
	* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
	*/
	/*
	* #clock-cells is required for audio_clkout0/1/2/3
	*
	* clkout : #clock-cells = <0>; <&rcar_sound>;
	* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
	*/
	compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3";
	reg = <0 0xec500000 0 0x1000>, /* SCU */
	<0 0xec5a0000 0 0x100>, /* ADG */
	<0 0xec540000 0 0x1000>, /* SSIU */
	<0 0xec541000 0 0x280>, /* SSI */
	<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
	reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

	clocks = <&cpg CPG_MOD 1005>,
	<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
	<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
	<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
	<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
	<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	<&audio_clk_a>, <&audio_clk_b>,
	<&audio_clk_c>,
	<&cpg CPG_CORE R8A7795_CLK_S0D4>;
	clock-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0",
	"src.9", "src.8", "src.7", "src.6",
	"src.5", "src.4", "src.3", "src.2",
	"src.1", "src.0",
	"mix.1", "mix.0",
	"ctu.1", "ctu.0",
	"dvc.0", "dvc.1",
	"clk_a", "clk_b", "clk_c", "clk_i";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 1005>,
	<&cpg 1006>, <&cpg 1007>,
	<&cpg 1008>, <&cpg 1009>,
	<&cpg 1010>, <&cpg 1011>,
	<&cpg 1012>, <&cpg 1013>,
	<&cpg 1014>, <&cpg 1015>;
	reset-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0";
	status = "disabled";

	rcar_sound,dvc {
	dvc0: dvc-0 {
	dmas = <&audma1 0xbc>;
	dma-names = "tx";
	};
	dvc1: dvc-1 {
	dmas = <&audma1 0xbe>;
	dma-names = "tx";
	};
	};

	rcar_sound,mix {
	mix0: mix-0 { };
	mix1: mix-1 { };
	};

	rcar_sound,ctu {
	ctu00: ctu-0 { };
	ctu01: ctu-1 { };
	ctu02: ctu-2 { };
	ctu03: ctu-3 { };
	ctu10: ctu-4 { };
	ctu11: ctu-5 { };
	ctu12: ctu-6 { };
	ctu13: ctu-7 { };
	};

	rcar_sound,src {
	src0: src-0 {
	interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x85>, <&audma1 0x9a>;
	dma-names = "rx", "tx";
	};
	src1: src-1 {
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x87>, <&audma1 0x9c>;
	dma-names = "rx", "tx";
	};
	src2: src-2 {
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x89>, <&audma1 0x9e>;
	dma-names = "rx", "tx";
	};
	src3: src-3 {
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8b>, <&audma1 0xa0>;
	dma-names = "rx", "tx";
	};
	src4: src-4 {
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8d>, <&audma1 0xb0>;
	dma-names = "rx", "tx";
	};
	src5: src-5 {
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8f>, <&audma1 0xb2>;
	dma-names = "rx", "tx";
	};
	src6: src-6 {
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x91>, <&audma1 0xb4>;
	dma-names = "rx", "tx";
	};
	src7: src-7 {
	interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x93>, <&audma1 0xb6>;
	dma-names = "rx", "tx";
	};
	src8: src-8 {
	interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x95>, <&audma1 0xb8>;
	dma-names = "rx", "tx";
	};
	src9: src-9 {
	interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x97>, <&audma1 0xba>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssiu {
	ssiu00: ssiu-0 {
	dmas = <&audma0 0x15>, <&audma1 0x16>;
	dma-names = "rx", "tx";
	};
	ssiu01: ssiu-1 {
	dmas = <&audma0 0x35>, <&audma1 0x36>;
	dma-names = "rx", "tx";
	};
	ssiu02: ssiu-2 {
	dmas = <&audma0 0x37>, <&audma1 0x38>;
	dma-names = "rx", "tx";
	};
	ssiu03: ssiu-3 {
	dmas = <&audma0 0x47>, <&audma1 0x48>;
	dma-names = "rx", "tx";
	};
	ssiu04: ssiu-4 {
	dmas = <&audma0 0x3F>, <&audma1 0x40>;
	dma-names = "rx", "tx";
	};
	ssiu05: ssiu-5 {
	dmas = <&audma0 0x43>, <&audma1 0x44>;
	dma-names = "rx", "tx";
	};
	ssiu06: ssiu-6 {
	dmas = <&audma0 0x4F>, <&audma1 0x50>;
	dma-names = "rx", "tx";
	};
	ssiu07: ssiu-7 {
	dmas = <&audma0 0x53>, <&audma1 0x54>;
	dma-names = "rx", "tx";
	};
	ssiu10: ssiu-8 {
	dmas = <&audma0 0x49>, <&audma1 0x4a>;
	dma-names = "rx", "tx";
	};
	ssiu11: ssiu-9 {
	dmas = <&audma0 0x4B>, <&audma1 0x4C>;
	dma-names = "rx", "tx";
	};
	ssiu12: ssiu-10 {
	dmas = <&audma0 0x57>, <&audma1 0x58>;
	dma-names = "rx", "tx";
	};
	ssiu13: ssiu-11 {
	dmas = <&audma0 0x59>, <&audma1 0x5A>;
	dma-names = "rx", "tx";
	};
	ssiu14: ssiu-12 {
	dmas = <&audma0 0x5F>, <&audma1 0x60>;
	dma-names = "rx", "tx";
	};
	ssiu15: ssiu-13 {
	dmas = <&audma0 0xC3>, <&audma1 0xC4>;
	dma-names = "rx", "tx";
	};
	ssiu16: ssiu-14 {
	dmas = <&audma0 0xC7>, <&audma1 0xC8>;
	dma-names = "rx", "tx";
	};
	ssiu17: ssiu-15 {
	dmas = <&audma0 0xCB>, <&audma1 0xCC>;
	dma-names = "rx", "tx";
	};
	ssiu20: ssiu-16 {
	dmas = <&audma0 0x63>, <&audma1 0x64>;
	dma-names = "rx", "tx";
	};
	ssiu21: ssiu-17 {
	dmas = <&audma0 0x67>, <&audma1 0x68>;
	dma-names = "rx", "tx";
	};
	ssiu22: ssiu-18 {
	dmas = <&audma0 0x6B>, <&audma1 0x6C>;
	dma-names = "rx", "tx";
	};
	ssiu23: ssiu-19 {
	dmas = <&audma0 0x6D>, <&audma1 0x6E>;
	dma-names = "rx", "tx";
	};
	ssiu24: ssiu-20 {
	dmas = <&audma0 0xCF>, <&audma1 0xCE>;
	dma-names = "rx", "tx";
	};
	ssiu25: ssiu-21 {
	dmas = <&audma0 0xEB>, <&audma1 0xEC>;
	dma-names = "rx", "tx";
	};
	ssiu26: ssiu-22 {
	dmas = <&audma0 0xED>, <&audma1 0xEE>;
	dma-names = "rx", "tx";
	};
	ssiu27: ssiu-23 {
	dmas = <&audma0 0xEF>, <&audma1 0xF0>;
	dma-names = "rx", "tx";
	};
	ssiu30: ssiu-24 {
	dmas = <&audma0 0x6f>, <&audma1 0x70>;
	dma-names = "rx", "tx";
	};
	ssiu31: ssiu-25 {
	dmas = <&audma0 0x21>, <&audma1 0x22>;
	dma-names = "rx", "tx";
	};
	ssiu32: ssiu-26 {
	dmas = <&audma0 0x23>, <&audma1 0x24>;
	dma-names = "rx", "tx";
	};
	ssiu33: ssiu-27 {
	dmas = <&audma0 0x25>, <&audma1 0x26>;
	dma-names = "rx", "tx";
	};
	ssiu34: ssiu-28 {
	dmas = <&audma0 0x27>, <&audma1 0x28>;
	dma-names = "rx", "tx";
	};
	ssiu35: ssiu-29 {
	dmas = <&audma0 0x29>, <&audma1 0x2A>;
	dma-names = "rx", "tx";
	};
	ssiu36: ssiu-30 {
	dmas = <&audma0 0x2B>, <&audma1 0x2C>;
	dma-names = "rx", "tx";
	};
	ssiu37: ssiu-31 {
	dmas = <&audma0 0x2D>, <&audma1 0x2E>;
	dma-names = "rx", "tx";
	};
	ssiu40: ssiu-32 {
	dmas = <&audma0 0x71>, <&audma1 0x72>;
	dma-names = "rx", "tx";
	};
	ssiu41: ssiu-33 {
	dmas = <&audma0 0x17>, <&audma1 0x18>;
	dma-names = "rx", "tx";
	};
	ssiu42: ssiu-34 {
	dmas = <&audma0 0x19>, <&audma1 0x1A>;
	dma-names = "rx", "tx";
	};
	ssiu43: ssiu-35 {
	dmas = <&audma0 0x1B>, <&audma1 0x1C>;
	dma-names = "rx", "tx";
	};
	ssiu44: ssiu-36 {
	dmas = <&audma0 0x1D>, <&audma1 0x1E>;
	dma-names = "rx", "tx";
	};
	ssiu45: ssiu-37 {
	dmas = <&audma0 0x1F>, <&audma1 0x20>;
	dma-names = "rx", "tx";
	};
	ssiu46: ssiu-38 {
	dmas = <&audma0 0x31>, <&audma1 0x32>;
	dma-names = "rx", "tx";
	};
	ssiu47: ssiu-39 {
	dmas = <&audma0 0x33>, <&audma1 0x34>;
	dma-names = "rx", "tx";
	};
	ssiu50: ssiu-40 {
	dmas = <&audma0 0x73>, <&audma1 0x74>;
	dma-names = "rx", "tx";
	};
	ssiu60: ssiu-41 {
	dmas = <&audma0 0x75>, <&audma1 0x76>;
	dma-names = "rx", "tx";
	};
	ssiu70: ssiu-42 {
	dmas = <&audma0 0x79>, <&audma1 0x7a>;
	dma-names = "rx", "tx";
	};
	ssiu80: ssiu-43 {
	dmas = <&audma0 0x7b>, <&audma1 0x7c>;
	dma-names = "rx", "tx";
	};
	ssiu90: ssiu-44 {
	dmas = <&audma0 0x7d>, <&audma1 0x7e>;
	dma-names = "rx", "tx";
	};
	ssiu91: ssiu-45 {
	dmas = <&audma0 0x7F>, <&audma1 0x80>;
	dma-names = "rx", "tx";
	};
	ssiu92: ssiu-46 {
	dmas = <&audma0 0x81>, <&audma1 0x82>;
	dma-names = "rx", "tx";
	};
	ssiu93: ssiu-47 {
	dmas = <&audma0 0x83>, <&audma1 0x84>;
	dma-names = "rx", "tx";
	};
	ssiu94: ssiu-48 {
	dmas = <&audma0 0xA3>, <&audma1 0xA4>;
	dma-names = "rx", "tx";
	};
	ssiu95: ssiu-49 {
	dmas = <&audma0 0xA5>, <&audma1 0xA6>;
	dma-names = "rx", "tx";
	};
	ssiu96: ssiu-50 {
	dmas = <&audma0 0xA7>, <&audma1 0xA8>;
	dma-names = "rx", "tx";
	};
	ssiu97: ssiu-51 {
	dmas = <&audma0 0xA9>, <&audma1 0xAA>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssi {
	ssi0: ssi-0 {
	interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x01>, <&audma1 0x02>;
	dma-names = "rx", "tx";
	};
	ssi1: ssi-1 {
	interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x03>, <&audma1 0x04>;
	dma-names = "rx", "tx";
	};
	ssi2: ssi-2 {
	interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x05>, <&audma1 0x06>;
	dma-names = "rx", "tx";
	};
	ssi3: ssi-3 {
	interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x07>, <&audma1 0x08>;
	dma-names = "rx", "tx";
	};
	ssi4: ssi-4 {
	interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x09>, <&audma1 0x0a>;
	dma-names = "rx", "tx";
	};
	ssi5: ssi-5 {
	interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0b>, <&audma1 0x0c>;
	dma-names = "rx", "tx";
	};
	ssi6: ssi-6 {
	interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0d>, <&audma1 0x0e>;
	dma-names = "rx", "tx";
	};
	ssi7: ssi-7 {
	interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0f>, <&audma1 0x10>;
	dma-names = "rx", "tx";
	};
	ssi8: ssi-8 {
	interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x11>, <&audma1 0x12>;
	dma-names = "rx", "tx";
	};
	ssi9: ssi-9 {
	interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x13>, <&audma1 0x14>;
	dma-names = "rx", "tx";
	};
	};
	};

	audma0: dma-controller@ec700000 {
	compatible = "renesas,dmac-r8a7795",
	"renesas,rcar-dmac";
	reg = <0 0xec700000 0 0x10000>;
	interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 502>;
	clock-names = "fck";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 502>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
	<&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
	<&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
	<&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
	<&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
	<&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
	<&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
	<&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
	};

	audma1: dma-controller@ec720000 {
	compatible = "renesas,dmac-r8a7795",
	"renesas,rcar-dmac";
	reg = <0 0xec720000 0 0x10000>;
	interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 501>;
	clock-names = "fck";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 501>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
	<&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
	<&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
	<&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
	<&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
	<&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
	<&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
	<&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
	};

	xhci0: usb@ee000000 {
	compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
	reg = <0 0xee000000 0 0xc00>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	status = "disabled";
	};

	usb3_peri0: usb@ee020000 {
	compatible = "renesas,r8a7795-usb3-peri",
	"renesas,rcar-gen3-usb3-peri";
	reg = <0 0xee020000 0 0x400>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	status = "disabled";
	};

	ohci0: usb@ee080000 {
	compatible = "generic-ohci";
	reg = <0 0xee080000 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	phys = <&usb2_phy0 1>;
	phy-names = "usb";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	status = "disabled";
	};

	ohci1: usb@ee0a0000 {
	compatible = "generic-ohci";
	reg = <0 0xee0a0000 0 0x100>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 702>;
	phys = <&usb2_phy1 1>;
	phy-names = "usb";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 702>;
	status = "disabled";
	};

	ohci2: usb@ee0c0000 {
	compatible = "generic-ohci";
	reg = <0 0xee0c0000 0 0x100>;
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 701>;
	phys = <&usb2_phy2 1>;
	phy-names = "usb";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 701>;
	status = "disabled";
	};

	ohci3: usb@ee0e0000 {
	compatible = "generic-ohci";
	reg = <0 0xee0e0000 0 0x100>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
	phys = <&usb2_phy3 1>;
	phy-names = "usb";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 700>, <&cpg 705>;
	status = "disabled";
	};

	ehci0: usb@ee080100 {
	compatible = "generic-ehci";
	reg = <0 0xee080100 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	phys = <&usb2_phy0 2>;
	phy-names = "usb";
	companion = <&ohci0>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	status = "disabled";
	};

	ehci1: usb@ee0a0100 {
	compatible = "generic-ehci";
	reg = <0 0xee0a0100 0 0x100>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 702>;
	phys = <&usb2_phy1 2>;
	phy-names = "usb";
	companion = <&ohci1>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 702>;
	status = "disabled";
	};

	ehci2: usb@ee0c0100 {
	compatible = "generic-ehci";
	reg = <0 0xee0c0100 0 0x100>;
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 701>;
	phys = <&usb2_phy2 2>;
	phy-names = "usb";
	companion = <&ohci2>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 701>;
	status = "disabled";
	};

	ehci3: usb@ee0e0100 {
	compatible = "generic-ehci";
	reg = <0 0xee0e0100 0 0x100>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
	phys = <&usb2_phy3 2>;
	phy-names = "usb";
	companion = <&ohci3>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 700>, <&cpg 705>;
	status = "disabled";
	};

	usb2_phy0: usb-phy@ee080200 {
	compatible = "renesas,usb2-phy-r8a7795",
	"renesas,rcar-gen3-usb2-phy";
	reg = <0 0xee080200 0 0x700>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	#phy-cells = <1>;
	status = "disabled";
	};

	usb2_phy1: usb-phy@ee0a0200 {
	compatible = "renesas,usb2-phy-r8a7795",
	"renesas,rcar-gen3-usb2-phy";
	reg = <0 0xee0a0200 0 0x700>;
	clocks = <&cpg CPG_MOD 702>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 702>;
	#phy-cells = <1>;
	status = "disabled";
	};

	usb2_phy2: usb-phy@ee0c0200 {
	compatible = "renesas,usb2-phy-r8a7795",
	"renesas,rcar-gen3-usb2-phy";
	reg = <0 0xee0c0200 0 0x700>;
	clocks = <&cpg CPG_MOD 701>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 701>;
	#phy-cells = <1>;
	status = "disabled";
	};

	usb2_phy3: usb-phy@ee0e0200 {
	compatible = "renesas,usb2-phy-r8a7795",
	"renesas,rcar-gen3-usb2-phy";
	reg = <0 0xee0e0200 0 0x700>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 700>, <&cpg 705>;
	#phy-cells = <1>;
	status = "disabled";
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a7795",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee100000 0 0x2000>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	iommus = <&ipmmu_ds1 32>;
	status = "disabled";
	};

	sdhi1: sd@ee120000 {
	compatible = "renesas,sdhi-r8a7795",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee120000 0 0x2000>;
	interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 313>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 313>;
	iommus = <&ipmmu_ds1 33>;
	status = "disabled";
	};

	sdhi2: sd@ee140000 {
	compatible = "renesas,sdhi-r8a7795",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee140000 0 0x2000>;
	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 312>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 312>;
	iommus = <&ipmmu_ds1 34>;
	status = "disabled";
	};

	sdhi3: sd@ee160000 {
	compatible = "renesas,sdhi-r8a7795",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee160000 0 0x2000>;
	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 311>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 311>;
	iommus = <&ipmmu_ds1 35>;
	status = "disabled";
	};

	sata: sata@ee300000 {
	compatible = "renesas,sata-r8a7795",
	"renesas,rcar-gen3-sata";
	reg = <0 0xee300000 0 0x200000>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 815>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 815>;
	status = "disabled";
	iommus = <&ipmmu_hc 2>;
	};

	gic: interrupt-controller@f1010000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x0 0xf1010000 0 0x1000>,
	<0x0 0xf1020000 0 0x20000>,
	<0x0 0xf1040000 0 0x20000>,
	<0x0 0xf1060000 0 0x20000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	pciec0: pcie@fe000000 {
	compatible = "renesas,pcie-r8a7795",
	"renesas,pcie-rcar-gen3";
	reg = <0 0xfe000000 0 0x80000>;
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x00 0xff>;
	device_type = "pci";
	ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
	<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
	<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
	<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
	/* Map all possible DDR as inbound ranges */
	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
	clock-names = "pcie", "pcie_bus";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 319>;
	status = "disabled";
	};

	pciec1: pcie@ee800000 {
	compatible = "renesas,pcie-r8a7795",
	"renesas,pcie-rcar-gen3";
	reg = <0 0xee800000 0 0x80000>;
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x00 0xff>;
	device_type = "pci";
	ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
	<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
	<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
	<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
	/* Map all possible DDR as inbound ranges */
	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
	clock-names = "pcie", "pcie_bus";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 318>;
	status = "disabled";
	};

	imr-lx4@fe860000 {
	compatible = "renesas,r8a7795-imr-lx4",
	"renesas,imr-lx4";
	reg = <0 0xfe860000 0 0x2000>;
	interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 823>;
	power-domains = <&sysc R8A7795_PD_A3VC>;
	resets = <&cpg 823>;
	};

	imr-lx4@fe870000 {
	compatible = "renesas,r8a7795-imr-lx4",
	"renesas,imr-lx4";
	reg = <0 0xfe870000 0 0x2000>;
	interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 822>;
	power-domains = <&sysc R8A7795_PD_A3VC>;
	resets = <&cpg 822>;
	};

	imr-lx4@fe880000 {
	compatible = "renesas,r8a7795-imr-lx4",
	"renesas,imr-lx4";
	reg = <0 0xfe880000 0 0x2000>;
	interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 821>;
	power-domains = <&sysc R8A7795_PD_A3VC>;
	resets = <&cpg 821>;
	};

	imr-lx4@fe890000 {
	compatible = "renesas,r8a7795-imr-lx4",
	"renesas,imr-lx4";
	reg = <0 0xfe890000 0 0x2000>;
	interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 820>;
	power-domains = <&sysc R8A7795_PD_A3VC>;
	resets = <&cpg 820>;
	};

	vspbc: vsp@fe920000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe920000 0 0x8000>;
	interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 624>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	resets = <&cpg 624>;

	renesas,fcp = <&fcpvb1>;
	};

	vspbd: vsp@fe960000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe960000 0 0x8000>;
	interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 626>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	resets = <&cpg 626>;

	renesas,fcp = <&fcpvb0>;
	};

	vspd0: vsp@fea20000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea20000 0 0x5000>;
	interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 623>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 623>;

	renesas,fcp = <&fcpvd0>;
	};

	vspd1: vsp@fea28000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea28000 0 0x5000>;
	interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 622>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 622>;

	renesas,fcp = <&fcpvd1>;
	};

	vspd2: vsp@fea30000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea30000 0 0x5000>;
	interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 621>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 621>;

	renesas,fcp = <&fcpvd2>;
	};

	vspi0: vsp@fe9a0000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe9a0000 0 0x8000>;
	interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 631>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	resets = <&cpg 631>;

	renesas,fcp = <&fcpvi0>;
	};

	vspi1: vsp@fe9b0000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe9b0000 0 0x8000>;
	interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 630>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	resets = <&cpg 630>;

	renesas,fcp = <&fcpvi1>;
	};

	fdp1@fe940000 {
	compatible = "renesas,fdp1";
	reg = <0 0xfe940000 0 0x2400>;
	interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 119>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	resets = <&cpg 119>;
	renesas,fcp = <&fcpf0>;
	};

	fdp1@fe944000 {
	compatible = "renesas,fdp1";
	reg = <0 0xfe944000 0 0x2400>;
	interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 118>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	resets = <&cpg 118>;
	renesas,fcp = <&fcpf1>;
	};

	fcpf0: fcp@fe950000 {
	compatible = "renesas,fcpf";
	reg = <0 0xfe950000 0 0x200>;
	clocks = <&cpg CPG_MOD 615>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	resets = <&cpg 615>;
	iommus = <&ipmmu_vp0 0>;
	};

	fcpf1: fcp@fe951000 {
	compatible = "renesas,fcpf";
	reg = <0 0xfe951000 0 0x200>;
	clocks = <&cpg CPG_MOD 614>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	resets = <&cpg 614>;
	iommus = <&ipmmu_vp1 1>;
	};

	fcpvb0: fcp@fe96f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe96f000 0 0x200>;
	clocks = <&cpg CPG_MOD 607>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	resets = <&cpg 607>;
	iommus = <&ipmmu_vp0 5>;
	};

	fcpvb1: fcp@fe92f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe92f000 0 0x200>;
	clocks = <&cpg CPG_MOD 606>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	resets = <&cpg 606>;
	iommus = <&ipmmu_vp1 7>;
	};

	fcpvi0: fcp@fe9af000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe9af000 0 0x200>;
	clocks = <&cpg CPG_MOD 611>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	resets = <&cpg 611>;
	iommus = <&ipmmu_vp0 8>;
	};

	fcpvi1: fcp@fe9bf000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe9bf000 0 0x200>;
	clocks = <&cpg CPG_MOD 610>;
	power-domains = <&sysc R8A7795_PD_A3VP>;
	resets = <&cpg 610>;
	iommus = <&ipmmu_vp1 9>;
	};

	fcpvd0: fcp@fea27000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea27000 0 0x200>;
	clocks = <&cpg CPG_MOD 603>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 603>;
	iommus = <&ipmmu_vi0 8>;
	};

	fcpvd1: fcp@fea2f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea2f000 0 0x200>;
	clocks = <&cpg CPG_MOD 602>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 602>;
	iommus = <&ipmmu_vi0 9>;
	};

	fcpvd2: fcp@fea37000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea37000 0 0x200>;
	clocks = <&cpg CPG_MOD 601>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 601>;
	iommus = <&ipmmu_vi1 10>;
	};

	cmm0: cmm@fea40000 {
	compatible = "renesas,r8a7795-cmm",
	"renesas,rcar-gen3-cmm";
	reg = <0 0xfea40000 0 0x1000>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	clocks = <&cpg CPG_MOD 711>;
	resets = <&cpg 711>;
	};

	cmm1: cmm@fea50000 {
	compatible = "renesas,r8a7795-cmm",
	"renesas,rcar-gen3-cmm";
	reg = <0 0xfea50000 0 0x1000>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	clocks = <&cpg CPG_MOD 710>;
	resets = <&cpg 710>;
	};

	cmm2: cmm@fea60000 {
	compatible = "renesas,r8a7795-cmm",
	"renesas,rcar-gen3-cmm";
	reg = <0 0xfea60000 0 0x1000>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	clocks = <&cpg CPG_MOD 709>;
	resets = <&cpg 709>;
	};

	cmm3: cmm@fea70000 {
	compatible = "renesas,r8a7795-cmm",
	"renesas,rcar-gen3-cmm";
	reg = <0 0xfea70000 0 0x1000>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	clocks = <&cpg CPG_MOD 708>;
	resets = <&cpg 708>;
	};

	csi20: csi2@fea80000 {
	compatible = "renesas,r8a7795-csi2";
	reg = <0 0xfea80000 0 0x10000>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 714>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 714>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	csi20vin0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vin0csi20>;
	};
	csi20vin1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vin1csi20>;
	};
	csi20vin2: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&vin2csi20>;
	};
	csi20vin3: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&vin3csi20>;
	};
	csi20vin4: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&vin4csi20>;
	};
	csi20vin5: endpoint@5 {
	reg = <5>;
	remote-endpoint = <&vin5csi20>;
	};
	csi20vin6: endpoint@6 {
	reg = <6>;
	remote-endpoint = <&vin6csi20>;
	};
	csi20vin7: endpoint@7 {
	reg = <7>;
	remote-endpoint = <&vin7csi20>;
	};
	};
	};
	};

	csi40: csi2@feaa0000 {
	compatible = "renesas,r8a7795-csi2";
	reg = <0 0xfeaa0000 0 0x10000>;
	interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	csi40vin0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vin0csi40>;
	};
	csi40vin1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vin1csi40>;
	};
	csi40vin2: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&vin2csi40>;
	};
	csi40vin3: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&vin3csi40>;
	};
	};
	};
	};

	csi41: csi2@feab0000 {
	compatible = "renesas,r8a7795-csi2";
	reg = <0 0xfeab0000 0 0x10000>;
	interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 715>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 715>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	csi41vin4: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vin4csi41>;
	};
	csi41vin5: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vin5csi41>;
	};
	csi41vin6: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&vin6csi41>;
	};
	csi41vin7: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&vin7csi41>;
	};
	};
	};
	};

	hdmi0: hdmi@fead0000 {
	compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
	reg = <0 0xfead0000 0 0x10000>;
	interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>;
	clock-names = "iahb", "isfr";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 729>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;
	port@0 {
	reg = <0>;
	dw_hdmi0_in: endpoint {
	remote-endpoint = <&du_out_hdmi0>;
	};
	};
	port@1 {
	reg = <1>;
	};
	port@2 {
	/* HDMI sound */
	reg = <2>;
	};
	};
	};

	hdmi1: hdmi@feae0000 {
	compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
	reg = <0 0xfeae0000 0 0x10000>;
	interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>;
	clock-names = "iahb", "isfr";
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 728>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;
	port@0 {
	reg = <0>;
	dw_hdmi1_in: endpoint {
	remote-endpoint = <&du_out_hdmi1>;
	};
	};
	port@1 {
	reg = <1>;
	};
	port@2 {
	/* HDMI sound */
	reg = <2>;
	};
	};
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a7795";
	reg = <0 0xfeb00000 0 0x80000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&cpg CPG_MOD 724>,
	- <&cpg CPG_MOD 723>,
	- <&cpg CPG_MOD 722>,
	- <&cpg CPG_MOD 721>;
	+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
	+ <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>;
	clock-names = "du.0", "du.1", "du.2", "du.3";
	+ resets = <&cpg 724>, <&cpg 722>;
	+ reset-names = "du.0", "du.2";

	renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
	- vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
	+ renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>,
	+ <&vspd0 1>;

	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb: endpoint {
	};
	};
	port@1 {
	reg = <1>;
	du_out_hdmi0: endpoint {
	remote-endpoint = <&dw_hdmi0_in>;
	};
	};
	port@2 {
	reg = <2>;
	du_out_hdmi1: endpoint {
	remote-endpoint = <&dw_hdmi1_in>;
	};
	};
	port@3 {
	reg = <3>;
	du_out_lvds0: endpoint {
	remote-endpoint = <&lvds0_in>;
	};
	};
	};
	};

	lvds0: lvds@feb90000 {
	compatible = "renesas,r8a7795-lvds";
	reg = <0 0xfeb90000 0 0x14>;
	clocks = <&cpg CPG_MOD 727>;
	power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
	resets = <&cpg 727>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds0_in: endpoint {
	remote-endpoint = <&du_out_lvds0>;
	};
	};
	port@1 {
	reg = <1>;
	lvds0_out: endpoint {
	};
	};
	};
	};

	prr: chipid@fff00044 {
	compatible = "renesas,prr";
	reg = <0 0xfff00044 0 4>;
	};
	};

	thermal-zones {
	sensor_thermal1: sensor-thermal1 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&tsc 0>;
	sustainable-power = <6313>;

	trips {
	sensor1_crit: sensor1-crit {
	temperature = <120000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};
	};

	sensor_thermal2: sensor-thermal2 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&tsc 1>;
	sustainable-power = <6313>;

	trips {
	sensor2_crit: sensor2-crit {
	temperature = <120000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};
	};

	sensor_thermal3: sensor-thermal3 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&tsc 2>;

	trips {
	target: trip-point1 {
	temperature = <100000>;
	hysteresis = <1000>;
	type = "passive";
	};

	sensor3_crit: sensor3-crit {
	temperature = <120000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&target>;
	cooling-device = <&a57_0 2 4>;
	contribution = <1024>;
	};

	map1 {
	trip = <&target>;
	cooling-device = <&a53_0 0 2>;
	contribution = <1024>;
	};
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clocks - can be overridden by the board */
	usb3s0_clk: usb3s0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	usb_extal_clk: usb_extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a77960.dtsi b/sys/gnu/dts/arm64/renesas/r8a77960.dtsi
	index 60f156cfd2d6..31282367d3ac 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a77960.dtsi
	+++ b/sys/gnu/dts/arm64/renesas/r8a77960.dtsi
	@@ -1,2972 +1,2982 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the R-Car M3-W (R8A77960) SoC
	*
	* Copyright (C) 2016-2017 Renesas Electronics Corp.
	*/

	#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/power/r8a7796-sysc.h>

	#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4

	/ {
	compatible = "renesas,r8a7796";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	i2c6 = &i2c6;
	i2c7 = &i2c_dvfs;
	};

	/*
	* The external audio clocks are configured as 0 Hz fixed frequency
	* clocks by default.
	* Boards that provide audio clocks should override them.
	*/
	audio_clk_a: audio_clk_a {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_b: audio_clk_b {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_c: audio_clk_c {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	/* External CAN clock - to be overridden by boards that provide it */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	cluster0_opp: opp_table0 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-500000000 {
	opp-hz = /bits/ 64 <500000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1500000000 {
	opp-hz = /bits/ 64 <1500000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1600000000 {
	opp-hz = /bits/ 64 <1600000000>;
	opp-microvolt = <900000>;
	clock-latency-ns = <300000>;
	turbo-mode;
	};
	opp-1700000000 {
	opp-hz = /bits/ 64 <1700000000>;
	opp-microvolt = <900000>;
	clock-latency-ns = <300000>;
	turbo-mode;
	};
	opp-1800000000 {
	opp-hz = /bits/ 64 <1800000000>;
	opp-microvolt = <960000>;
	clock-latency-ns = <300000>;
	turbo-mode;
	};
	};

	cluster1_opp: opp_table1 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-800000000 {
	opp-hz = /bits/ 64 <800000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1300000000 {
	opp-hz = /bits/ 64 <1300000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	turbo-mode;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu-map {
	cluster0 {
	core0 {
	cpu = <&a57_0>;
	};
	core1 {
	cpu = <&a57_1>;
	};
	};

	cluster1 {
	core0 {
	cpu = <&a53_0>;
	};
	core1 {
	cpu = <&a53_1>;
	};
	core2 {
	cpu = <&a53_2>;
	};
	core3 {
	cpu = <&a53_3>;
	};
	};
	};

	a57_0: cpu@0 {
	compatible = "arm,cortex-a57";
	reg = <0x0>;
	device_type = "cpu";
	power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
	next-level-cache = <&L2_CA57>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	dynamic-power-coefficient = <854>;
	clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
	operating-points-v2 = <&cluster0_opp>;
	capacity-dmips-mhz = <1024>;
	#cooling-cells = <2>;
	};

	a57_1: cpu@1 {
	compatible = "arm,cortex-a57";
	reg = <0x1>;
	device_type = "cpu";
	power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
	next-level-cache = <&L2_CA57>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
	operating-points-v2 = <&cluster0_opp>;
	capacity-dmips-mhz = <1024>;
	#cooling-cells = <2>;
	};

	a53_0: cpu@100 {
	compatible = "arm,cortex-a53";
	reg = <0x100>;
	device_type = "cpu";
	power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_1>;
	#cooling-cells = <2>;
	dynamic-power-coefficient = <277>;
	clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	capacity-dmips-mhz = <535>;
	};

	a53_1: cpu@101 {
	compatible = "arm,cortex-a53";
	reg = <0x101>;
	device_type = "cpu";
	power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_1>;
	clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	capacity-dmips-mhz = <535>;
	};

	a53_2: cpu@102 {
	compatible = "arm,cortex-a53";
	reg = <0x102>;
	device_type = "cpu";
	power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_1>;
	clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	capacity-dmips-mhz = <535>;
	};

	a53_3: cpu@103 {
	compatible = "arm,cortex-a53";
	reg = <0x103>;
	device_type = "cpu";
	power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_1>;
	clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	capacity-dmips-mhz = <535>;
	};

	L2_CA57: cache-controller-0 {
	compatible = "cache";
	power-domains = <&sysc R8A7796_PD_CA57_SCU>;
	cache-unified;
	cache-level = <2>;
	};

	L2_CA53: cache-controller-1 {
	compatible = "cache";
	power-domains = <&sysc R8A7796_PD_CA53_SCU>;
	cache-unified;
	cache-level = <2>;
	};

	idle-states {
	entry-method = "psci";

	CPU_SLEEP_0: cpu-sleep-0 {
	compatible = "arm,idle-state";
	arm,psci-suspend-param = <0x0010000>;
	local-timer-stop;
	entry-latency-us = <400>;
	exit-latency-us = <500>;
	min-residency-us = <4000>;
	};

	CPU_SLEEP_1: cpu-sleep-1 {
	compatible = "arm,idle-state";
	arm,psci-suspend-param = <0x0010000>;
	local-timer-stop;
	entry-latency-us = <700>;
	exit-latency-us = <700>;
	min-residency-us = <5000>;
	};
	};
	};

	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	extalr_clk: extalr {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	/* External PCIe clock - can be overridden by the board */
	pcie_bus_clk: pcie_bus {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	pmu_a53 {
	compatible = "arm,cortex-a53-pmu";
	interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
	};

	pmu_a57 {
	compatible = "arm,cortex-a57-pmu";
	interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&a57_0>, <&a57_1>;
	};

	psci {
	compatible = "arm,psci-1.0", "arm,psci-0.2";
	method = "smc";
	};

	/* External SCIF clock - to be overridden by boards that provide it */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a7796-wdt",
	"renesas,rcar-gen3-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a7796",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 16>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a7796",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 29>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a7796",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 15>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a7796",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 16>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a7796",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 18>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a7796",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	gpio6: gpio@e6055400 {
	compatible = "renesas,gpio-r8a7796",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055400 0 0x50>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 192 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 906>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 906>;
	};

	gpio7: gpio@e6055800 {
	compatible = "renesas,gpio-r8a7796",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055800 0 0x50>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 224 4>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 905>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 905>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a7796";
	reg = <0 0xe6060000 0 0x50c>;
	};

	cmt0: timer@e60f0000 {
	compatible = "renesas,r8a7796-cmt0",
	"renesas,rcar-gen3-cmt0";
	reg = <0 0xe60f0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 303>;
	clock-names = "fck";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 303>;
	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a7796-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 302>;
	clock-names = "fck";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 302>;
	status = "disabled";
	};

	cmt2: timer@e6140000 {
	compatible = "renesas,r8a7796-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6140000 0 0x1004>;
	interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 301>;
	clock-names = "fck";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 301>;
	status = "disabled";
	};

	cmt3: timer@e6148000 {
	compatible = "renesas,r8a7796-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6148000 0 0x1004>;
	interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 300>;
	clock-names = "fck";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 300>;
	status = "disabled";
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a7796-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>, <&extalr_clk>;
	clock-names = "extal", "extalr";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a7796-rst";
	reg = <0 0xe6160000 0 0x0200>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a7796-sysc";
	reg = <0 0xe6180000 0 0x0400>;
	#power-domain-cells = <1>;
	};

	tsc: thermal@e6198000 {
	compatible = "renesas,r8a7796-thermal";
	reg = <0 0xe6198000 0 0x100>,
	<0 0xe61a0000 0 0x100>,
	<0 0xe61a8000 0 0x100>;
	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 522>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 522>;
	#thermal-sensor-cells = <1>;
	};

	intc_ex: interrupt-controller@e61c0000 {
	compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	i2c0: i2c@e6500000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7796",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6500000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	dmas = <&dmac1 0x91>, <&dmac1 0x90>,
	<&dmac2 0x91>, <&dmac2 0x90>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c1: i2c@e6508000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7796",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	dmas = <&dmac1 0x93>, <&dmac1 0x92>,
	<&dmac2 0x93>, <&dmac2 0x92>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c2: i2c@e6510000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7796",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6510000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	dmas = <&dmac1 0x95>, <&dmac1 0x94>,
	<&dmac2 0x95>, <&dmac2 0x94>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c3: i2c@e66d0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7796",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d0000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	dmas = <&dmac0 0x97>, <&dmac0 0x96>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c4: i2c@e66d8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7796",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d8000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	dmas = <&dmac0 0x99>, <&dmac0 0x98>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c5: i2c@e66e0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7796",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66e0000 0 0x40>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 919>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 919>;
	dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c6: i2c@e66e8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a7796",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66e8000 0 0x40>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 918>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 918>;
	dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c_dvfs: i2c@e60b0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a7796",
	"renesas,rcar-gen3-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe60b0000 0 0x425>;
	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 926>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 926>;
	dmas = <&dmac0 0x11>, <&dmac0 0x10>;
	dma-names = "tx", "rx";
	status = "disabled";
	};

	hscif0: serial@e6540000 {
	compatible = "renesas,hscif-r8a7796",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6540000 0 0x60>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 520>,
	<&cpg CPG_CORE R8A7796_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x31>, <&dmac1 0x30>,
	<&dmac2 0x31>, <&dmac2 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 520>;
	status = "disabled";
	};

	hscif1: serial@e6550000 {
	compatible = "renesas,hscif-r8a7796",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6550000 0 0x60>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 519>,
	<&cpg CPG_CORE R8A7796_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x33>, <&dmac1 0x32>,
	<&dmac2 0x33>, <&dmac2 0x32>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 519>;
	status = "disabled";
	};

	hscif2: serial@e6560000 {
	compatible = "renesas,hscif-r8a7796",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6560000 0 0x60>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 518>,
	<&cpg CPG_CORE R8A7796_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x35>, <&dmac1 0x34>,
	<&dmac2 0x35>, <&dmac2 0x34>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 518>;
	status = "disabled";
	};

	hscif3: serial@e66a0000 {
	compatible = "renesas,hscif-r8a7796",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe66a0000 0 0x60>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 517>,
	<&cpg CPG_CORE R8A7796_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x37>, <&dmac0 0x36>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 517>;
	status = "disabled";
	};

	hscif4: serial@e66b0000 {
	compatible = "renesas,hscif-r8a7796",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe66b0000 0 0x60>;
	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 516>,
	<&cpg CPG_CORE R8A7796_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x39>, <&dmac0 0x38>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 516>;
	status = "disabled";
	};

	hsusb: usb@e6590000 {
	compatible = "renesas,usbhs-r8a7796",
	"renesas,rcar-gen3-usbhs";
	reg = <0 0xe6590000 0 0x200>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
	dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
	<&usb_dmac1 0>, <&usb_dmac1 1>;
	dma-names = "ch0", "ch1", "ch2", "ch3";
	renesas,buswait = <11>;
	phys = <&usb2_phy0 3>;
	phy-names = "usb";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 704>, <&cpg 703>;
	status = "disabled";
	};

	usb_dmac0: dma-controller@e65a0000 {
	compatible = "renesas,r8a7796-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65a0000 0 0x100>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 330>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 330>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac1: dma-controller@e65b0000 {
	compatible = "renesas,r8a7796-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65b0000 0 0x100>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 331>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 331>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb3_phy0: usb-phy@e65ee000 {
	compatible = "renesas,r8a7796-usb3-phy",
	"renesas,rcar-gen3-usb3-phy";
	reg = <0 0xe65ee000 0 0x90>;
	clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
	<&usb_extal_clk>;
	clock-names = "usb3-if", "usb3s_clk", "usb_extal";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	#phy-cells = <0>;
	status = "disabled";
	};

	+ arm_cc630p: crypto@e6601000 {
	+ compatible = "arm,cryptocell-630p-ree";
	+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0 0xe6601000 0 0x1000>;
	+ clocks = <&cpg CPG_MOD 229>;
	+ resets = <&cpg 229>;
	+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	+ };
	+
	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a7796",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x10000>;
	interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
	<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
	<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
	<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
	<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
	<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
	<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
	<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
	};

	dmac1: dma-controller@e7300000 {
	compatible = "renesas,dmac-r8a7796",
	"renesas,rcar-dmac";
	reg = <0 0xe7300000 0 0x10000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
	<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
	<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
	<&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
	<&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
	<&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
	<&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
	<&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
	};

	dmac2: dma-controller@e7310000 {
	compatible = "renesas,dmac-r8a7796",
	"renesas,rcar-dmac";
	reg = <0 0xe7310000 0 0x10000>;
	interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 217>;
	clock-names = "fck";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 217>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
	<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
	<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
	<&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
	<&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
	<&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
	<&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
	<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
	};

	ipmmu_ds0: mmu@e6740000 {
	compatible = "renesas,ipmmu-r8a7796";
	reg = <0 0xe6740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 0>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_ds1: mmu@e7740000 {
	compatible = "renesas,ipmmu-r8a7796";
	reg = <0 0xe7740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 1>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_hc: mmu@e6570000 {
	compatible = "renesas,ipmmu-r8a7796";
	reg = <0 0xe6570000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 2>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_ir: mmu@ff8b0000 {
	compatible = "renesas,ipmmu-r8a7796";
	reg = <0 0xff8b0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 3>;
	power-domains = <&sysc R8A7796_PD_A3IR>;
	#iommu-cells = <1>;
	};

	ipmmu_mm: mmu@e67b0000 {
	compatible = "renesas,ipmmu-r8a7796";
	reg = <0 0xe67b0000 0 0x1000>;
	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_mp: mmu@ec670000 {
	compatible = "renesas,ipmmu-r8a7796";
	reg = <0 0xec670000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 4>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_pv0: mmu@fd800000 {
	compatible = "renesas,ipmmu-r8a7796";
	reg = <0 0xfd800000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 5>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_pv1: mmu@fd950000 {
	compatible = "renesas,ipmmu-r8a7796";
	reg = <0 0xfd950000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 6>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_rt: mmu@ffc80000 {
	compatible = "renesas,ipmmu-r8a7796";
	reg = <0 0xffc80000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 7>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vc0: mmu@fe6b0000 {
	compatible = "renesas,ipmmu-r8a7796";
	reg = <0 0xfe6b0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 8>;
	power-domains = <&sysc R8A7796_PD_A3VC>;
	#iommu-cells = <1>;
	};

	ipmmu_vi0: mmu@febd0000 {
	compatible = "renesas,ipmmu-r8a7796";
	reg = <0 0xfebd0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 9>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a7796",
	"renesas,etheravb-rcar-gen3";
	reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15",
	"ch16", "ch17", "ch18", "ch19",
	"ch20", "ch21", "ch22", "ch23",
	"ch24";
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	phy-mode = "rgmii";
	iommus = <&ipmmu_ds0 16>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	can0: can@e6c30000 {
	compatible = "renesas,can-r8a7796",
	"renesas,rcar-gen3-can";
	reg = <0 0xe6c30000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 916>,
	<&cpg CPG_CORE R8A7796_CLK_CANFD>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 916>;
	status = "disabled";
	};

	can1: can@e6c38000 {
	compatible = "renesas,can-r8a7796",
	"renesas,rcar-gen3-can";
	reg = <0 0xe6c38000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 915>,
	<&cpg CPG_CORE R8A7796_CLK_CANFD>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 915>;
	status = "disabled";
	};

	canfd: can@e66c0000 {
	compatible = "renesas,r8a7796-canfd",
	"renesas,rcar-gen3-canfd";
	reg = <0 0xe66c0000 0 0x8000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 914>,
	<&cpg CPG_CORE R8A7796_CLK_CANFD>,
	<&can_clk>;
	clock-names = "fck", "canfd", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 914>;
	status = "disabled";

	channel0 {
	status = "disabled";
	};

	channel1 {
	status = "disabled";
	};
	};

	pwm0: pwm@e6e30000 {
	compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
	reg = <0 0xe6e30000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm1: pwm@e6e31000 {
	compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
	reg = <0 0xe6e31000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm2: pwm@e6e32000 {
	compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
	reg = <0 0xe6e32000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm3: pwm@e6e33000 {
	compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
	reg = <0 0xe6e33000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm4: pwm@e6e34000 {
	compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
	reg = <0 0xe6e34000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm5: pwm@e6e35000 {
	compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
	reg = <0 0xe6e35000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm6: pwm@e6e36000 {
	compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
	reg = <0 0xe6e36000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a7796",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e60000 0 64>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 207>,
	<&cpg CPG_CORE R8A7796_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x51>, <&dmac1 0x50>,
	<&dmac2 0x51>, <&dmac2 0x50>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 207>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a7796",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e68000 0 64>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 206>,
	<&cpg CPG_CORE R8A7796_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x53>, <&dmac1 0x52>,
	<&dmac2 0x53>, <&dmac2 0x52>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 206>;
	status = "disabled";
	};

	scif2: serial@e6e88000 {
	compatible = "renesas,scif-r8a7796",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e88000 0 64>;
	interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 310>,
	<&cpg CPG_CORE R8A7796_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x13>, <&dmac1 0x12>,
	<&dmac2 0x13>, <&dmac2 0x12>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 310>;
	status = "disabled";
	};

	scif3: serial@e6c50000 {
	compatible = "renesas,scif-r8a7796",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6c50000 0 64>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 204>,
	<&cpg CPG_CORE R8A7796_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x57>, <&dmac0 0x56>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 204>;
	status = "disabled";
	};

	scif4: serial@e6c40000 {
	compatible = "renesas,scif-r8a7796",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6c40000 0 64>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 203>,
	<&cpg CPG_CORE R8A7796_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x59>, <&dmac0 0x58>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 203>;
	status = "disabled";
	};

	scif5: serial@e6f30000 {
	compatible = "renesas,scif-r8a7796",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6f30000 0 64>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 202>,
	<&cpg CPG_CORE R8A7796_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
	<&dmac2 0x5b>, <&dmac2 0x5a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 202>;
	status = "disabled";
	};

	tpu: pwm@e6e80000 {
	compatible = "renesas,tpu-r8a7796", "renesas,tpu";
	reg = <0 0xe6e80000 0 0x148>;
	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 304>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 304>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	msiof0: spi@e6e90000 {
	compatible = "renesas,msiof-r8a7796",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6e90000 0 0x0064>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 211>;
	dmas = <&dmac1 0x41>, <&dmac1 0x40>,
	<&dmac2 0x41>, <&dmac2 0x40>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 211>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof1: spi@e6ea0000 {
	compatible = "renesas,msiof-r8a7796",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6ea0000 0 0x0064>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 210>;
	dmas = <&dmac1 0x43>, <&dmac1 0x42>,
	<&dmac2 0x43>, <&dmac2 0x42>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 210>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof2: spi@e6c00000 {
	compatible = "renesas,msiof-r8a7796",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c00000 0 0x0064>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 209>;
	dmas = <&dmac0 0x45>, <&dmac0 0x44>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 209>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof3: spi@e6c10000 {
	compatible = "renesas,msiof-r8a7796",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c10000 0 0x0064>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 208>;
	dmas = <&dmac0 0x47>, <&dmac0 0x46>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 208>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	vin0: video@e6ef0000 {
	compatible = "renesas,vin-r8a7796";
	reg = <0 0xe6ef0000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 811>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 811>;
	renesas,id = <0>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin0csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin0>;
	};
	vin0csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin0>;
	};
	};
	};
	};

	vin1: video@e6ef1000 {
	compatible = "renesas,vin-r8a7796";
	reg = <0 0xe6ef1000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 810>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 810>;
	renesas,id = <1>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin1csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin1>;
	};
	vin1csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin1>;
	};
	};
	};
	};

	vin2: video@e6ef2000 {
	compatible = "renesas,vin-r8a7796";
	reg = <0 0xe6ef2000 0 0x1000>;
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 809>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 809>;
	renesas,id = <2>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin2csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin2>;
	};
	vin2csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin2>;
	};
	};
	};
	};

	vin3: video@e6ef3000 {
	compatible = "renesas,vin-r8a7796";
	reg = <0 0xe6ef3000 0 0x1000>;
	interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 808>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 808>;
	renesas,id = <3>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin3csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin3>;
	};
	vin3csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin3>;
	};
	};
	};
	};

	vin4: video@e6ef4000 {
	compatible = "renesas,vin-r8a7796";
	reg = <0 0xe6ef4000 0 0x1000>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 807>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 807>;
	renesas,id = <4>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin4csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin4>;
	};
	vin4csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin4>;
	};
	};
	};
	};

	vin5: video@e6ef5000 {
	compatible = "renesas,vin-r8a7796";
	reg = <0 0xe6ef5000 0 0x1000>;
	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 806>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 806>;
	renesas,id = <5>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin5csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin5>;
	};
	vin5csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin5>;
	};
	};
	};
	};

	vin6: video@e6ef6000 {
	compatible = "renesas,vin-r8a7796";
	reg = <0 0xe6ef6000 0 0x1000>;
	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 805>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 805>;
	renesas,id = <6>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin6csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin6>;
	};
	vin6csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin6>;
	};
	};
	};
	};

	vin7: video@e6ef7000 {
	compatible = "renesas,vin-r8a7796";
	reg = <0 0xe6ef7000 0 0x1000>;
	interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 804>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 804>;
	renesas,id = <7>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin7csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin7>;
	};
	vin7csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin7>;
	};
	};
	};
	};

	drif00: rif@e6f40000 {
	compatible = "renesas,r8a7796-drif",
	"renesas,rcar-gen3-drif";
	reg = <0 0xe6f40000 0 0x64>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 515>;
	clock-names = "fck";
	dmas = <&dmac1 0x20>, <&dmac2 0x20>;
	dma-names = "rx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 515>;
	renesas,bonding = <&drif01>;
	status = "disabled";
	};

	drif01: rif@e6f50000 {
	compatible = "renesas,r8a7796-drif",
	"renesas,rcar-gen3-drif";
	reg = <0 0xe6f50000 0 0x64>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 514>;
	clock-names = "fck";
	dmas = <&dmac1 0x22>, <&dmac2 0x22>;
	dma-names = "rx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 514>;
	renesas,bonding = <&drif00>;
	status = "disabled";
	};

	drif10: rif@e6f60000 {
	compatible = "renesas,r8a7796-drif",
	"renesas,rcar-gen3-drif";
	reg = <0 0xe6f60000 0 0x64>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 513>;
	clock-names = "fck";
	dmas = <&dmac1 0x24>, <&dmac2 0x24>;
	dma-names = "rx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 513>;
	renesas,bonding = <&drif11>;
	status = "disabled";
	};

	drif11: rif@e6f70000 {
	compatible = "renesas,r8a7796-drif",
	"renesas,rcar-gen3-drif";
	reg = <0 0xe6f70000 0 0x64>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 512>;
	clock-names = "fck";
	dmas = <&dmac1 0x26>, <&dmac2 0x26>;
	dma-names = "rx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 512>;
	renesas,bonding = <&drif10>;
	status = "disabled";
	};

	drif20: rif@e6f80000 {
	compatible = "renesas,r8a7796-drif",
	"renesas,rcar-gen3-drif";
	reg = <0 0xe6f80000 0 0x64>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 511>;
	clock-names = "fck";
	dmas = <&dmac1 0x28>, <&dmac2 0x28>;
	dma-names = "rx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 511>;
	renesas,bonding = <&drif21>;
	status = "disabled";
	};

	drif21: rif@e6f90000 {
	compatible = "renesas,r8a7796-drif",
	"renesas,rcar-gen3-drif";
	reg = <0 0xe6f90000 0 0x64>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 510>;
	clock-names = "fck";
	dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
	dma-names = "rx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 510>;
	renesas,bonding = <&drif20>;
	status = "disabled";
	};

	drif30: rif@e6fa0000 {
	compatible = "renesas,r8a7796-drif",
	"renesas,rcar-gen3-drif";
	reg = <0 0xe6fa0000 0 0x64>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 509>;
	clock-names = "fck";
	dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
	dma-names = "rx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 509>;
	renesas,bonding = <&drif31>;
	status = "disabled";
	};

	drif31: rif@e6fb0000 {
	compatible = "renesas,r8a7796-drif",
	"renesas,rcar-gen3-drif";
	reg = <0 0xe6fb0000 0 0x64>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 508>;
	clock-names = "fck";
	dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
	dma-names = "rx", "rx";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 508>;
	renesas,bonding = <&drif30>;
	status = "disabled";
	};

	rcar_sound: sound@ec500000 {
	/*
	* #sound-dai-cells is required
	*
	* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
	* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
	*/
	/*
	* #clock-cells is required for audio_clkout0/1/2/3
	*
	* clkout : #clock-cells = <0>; <&rcar_sound>;
	* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
	*/
	compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
	reg = <0 0xec500000 0 0x1000>, /* SCU */
	<0 0xec5a0000 0 0x100>, /* ADG */
	<0 0xec540000 0 0x1000>, /* SSIU */
	<0 0xec541000 0 0x280>, /* SSI */
	<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
	reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

	clocks = <&cpg CPG_MOD 1005>,
	<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
	<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
	<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
	<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
	<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	<&audio_clk_a>, <&audio_clk_b>,
	<&audio_clk_c>,
	<&cpg CPG_CORE R8A7796_CLK_S0D4>;
	clock-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0",
	"src.9", "src.8", "src.7", "src.6",
	"src.5", "src.4", "src.3", "src.2",
	"src.1", "src.0",
	"mix.1", "mix.0",
	"ctu.1", "ctu.0",
	"dvc.0", "dvc.1",
	"clk_a", "clk_b", "clk_c", "clk_i";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 1005>,
	<&cpg 1006>, <&cpg 1007>,
	<&cpg 1008>, <&cpg 1009>,
	<&cpg 1010>, <&cpg 1011>,
	<&cpg 1012>, <&cpg 1013>,
	<&cpg 1014>, <&cpg 1015>;
	reset-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0";
	status = "disabled";

	rcar_sound,ctu {
	ctu00: ctu-0 { };
	ctu01: ctu-1 { };
	ctu02: ctu-2 { };
	ctu03: ctu-3 { };
	ctu10: ctu-4 { };
	ctu11: ctu-5 { };
	ctu12: ctu-6 { };
	ctu13: ctu-7 { };
	};

	rcar_sound,dvc {
	dvc0: dvc-0 {
	dmas = <&audma1 0xbc>;
	dma-names = "tx";
	};
	dvc1: dvc-1 {
	dmas = <&audma1 0xbe>;
	dma-names = "tx";
	};
	};

	rcar_sound,mix {
	mix0: mix-0 { };
	mix1: mix-1 { };
	};

	rcar_sound,src {
	src0: src-0 {
	interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x85>, <&audma1 0x9a>;
	dma-names = "rx", "tx";
	};
	src1: src-1 {
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x87>, <&audma1 0x9c>;
	dma-names = "rx", "tx";
	};
	src2: src-2 {
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x89>, <&audma1 0x9e>;
	dma-names = "rx", "tx";
	};
	src3: src-3 {
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8b>, <&audma1 0xa0>;
	dma-names = "rx", "tx";
	};
	src4: src-4 {
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8d>, <&audma1 0xb0>;
	dma-names = "rx", "tx";
	};
	src5: src-5 {
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8f>, <&audma1 0xb2>;
	dma-names = "rx", "tx";
	};
	src6: src-6 {
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x91>, <&audma1 0xb4>;
	dma-names = "rx", "tx";
	};
	src7: src-7 {
	interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x93>, <&audma1 0xb6>;
	dma-names = "rx", "tx";
	};
	src8: src-8 {
	interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x95>, <&audma1 0xb8>;
	dma-names = "rx", "tx";
	};
	src9: src-9 {
	interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x97>, <&audma1 0xba>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssi {
	ssi0: ssi-0 {
	interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x01>, <&audma1 0x02>;
	dma-names = "rx", "tx";
	};
	ssi1: ssi-1 {
	interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x03>, <&audma1 0x04>;
	dma-names = "rx", "tx";
	};
	ssi2: ssi-2 {
	interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x05>, <&audma1 0x06>;
	dma-names = "rx", "tx";
	};
	ssi3: ssi-3 {
	interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x07>, <&audma1 0x08>;
	dma-names = "rx", "tx";
	};
	ssi4: ssi-4 {
	interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x09>, <&audma1 0x0a>;
	dma-names = "rx", "tx";
	};
	ssi5: ssi-5 {
	interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0b>, <&audma1 0x0c>;
	dma-names = "rx", "tx";
	};
	ssi6: ssi-6 {
	interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0d>, <&audma1 0x0e>;
	dma-names = "rx", "tx";
	};
	ssi7: ssi-7 {
	interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0f>, <&audma1 0x10>;
	dma-names = "rx", "tx";
	};
	ssi8: ssi-8 {
	interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x11>, <&audma1 0x12>;
	dma-names = "rx", "tx";
	};
	ssi9: ssi-9 {
	interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x13>, <&audma1 0x14>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssiu {
	ssiu00: ssiu-0 {
	dmas = <&audma0 0x15>, <&audma1 0x16>;
	dma-names = "rx", "tx";
	};
	ssiu01: ssiu-1 {
	dmas = <&audma0 0x35>, <&audma1 0x36>;
	dma-names = "rx", "tx";
	};
	ssiu02: ssiu-2 {
	dmas = <&audma0 0x37>, <&audma1 0x38>;
	dma-names = "rx", "tx";
	};
	ssiu03: ssiu-3 {
	dmas = <&audma0 0x47>, <&audma1 0x48>;
	dma-names = "rx", "tx";
	};
	ssiu04: ssiu-4 {
	dmas = <&audma0 0x3F>, <&audma1 0x40>;
	dma-names = "rx", "tx";
	};
	ssiu05: ssiu-5 {
	dmas = <&audma0 0x43>, <&audma1 0x44>;
	dma-names = "rx", "tx";
	};
	ssiu06: ssiu-6 {
	dmas = <&audma0 0x4F>, <&audma1 0x50>;
	dma-names = "rx", "tx";
	};
	ssiu07: ssiu-7 {
	dmas = <&audma0 0x53>, <&audma1 0x54>;
	dma-names = "rx", "tx";
	};
	ssiu10: ssiu-8 {
	dmas = <&audma0 0x49>, <&audma1 0x4a>;
	dma-names = "rx", "tx";
	};
	ssiu11: ssiu-9 {
	dmas = <&audma0 0x4B>, <&audma1 0x4C>;
	dma-names = "rx", "tx";
	};
	ssiu12: ssiu-10 {
	dmas = <&audma0 0x57>, <&audma1 0x58>;
	dma-names = "rx", "tx";
	};
	ssiu13: ssiu-11 {
	dmas = <&audma0 0x59>, <&audma1 0x5A>;
	dma-names = "rx", "tx";
	};
	ssiu14: ssiu-12 {
	dmas = <&audma0 0x5F>, <&audma1 0x60>;
	dma-names = "rx", "tx";
	};
	ssiu15: ssiu-13 {
	dmas = <&audma0 0xC3>, <&audma1 0xC4>;
	dma-names = "rx", "tx";
	};
	ssiu16: ssiu-14 {
	dmas = <&audma0 0xC7>, <&audma1 0xC8>;
	dma-names = "rx", "tx";
	};
	ssiu17: ssiu-15 {
	dmas = <&audma0 0xCB>, <&audma1 0xCC>;
	dma-names = "rx", "tx";
	};
	ssiu20: ssiu-16 {
	dmas = <&audma0 0x63>, <&audma1 0x64>;
	dma-names = "rx", "tx";
	};
	ssiu21: ssiu-17 {
	dmas = <&audma0 0x67>, <&audma1 0x68>;
	dma-names = "rx", "tx";
	};
	ssiu22: ssiu-18 {
	dmas = <&audma0 0x6B>, <&audma1 0x6C>;
	dma-names = "rx", "tx";
	};
	ssiu23: ssiu-19 {
	dmas = <&audma0 0x6D>, <&audma1 0x6E>;
	dma-names = "rx", "tx";
	};
	ssiu24: ssiu-20 {
	dmas = <&audma0 0xCF>, <&audma1 0xCE>;
	dma-names = "rx", "tx";
	};
	ssiu25: ssiu-21 {
	dmas = <&audma0 0xEB>, <&audma1 0xEC>;
	dma-names = "rx", "tx";
	};
	ssiu26: ssiu-22 {
	dmas = <&audma0 0xED>, <&audma1 0xEE>;
	dma-names = "rx", "tx";
	};
	ssiu27: ssiu-23 {
	dmas = <&audma0 0xEF>, <&audma1 0xF0>;
	dma-names = "rx", "tx";
	};
	ssiu30: ssiu-24 {
	dmas = <&audma0 0x6f>, <&audma1 0x70>;
	dma-names = "rx", "tx";
	};
	ssiu31: ssiu-25 {
	dmas = <&audma0 0x21>, <&audma1 0x22>;
	dma-names = "rx", "tx";
	};
	ssiu32: ssiu-26 {
	dmas = <&audma0 0x23>, <&audma1 0x24>;
	dma-names = "rx", "tx";
	};
	ssiu33: ssiu-27 {
	dmas = <&audma0 0x25>, <&audma1 0x26>;
	dma-names = "rx", "tx";
	};
	ssiu34: ssiu-28 {
	dmas = <&audma0 0x27>, <&audma1 0x28>;
	dma-names = "rx", "tx";
	};
	ssiu35: ssiu-29 {
	dmas = <&audma0 0x29>, <&audma1 0x2A>;
	dma-names = "rx", "tx";
	};
	ssiu36: ssiu-30 {
	dmas = <&audma0 0x2B>, <&audma1 0x2C>;
	dma-names = "rx", "tx";
	};
	ssiu37: ssiu-31 {
	dmas = <&audma0 0x2D>, <&audma1 0x2E>;
	dma-names = "rx", "tx";
	};
	ssiu40: ssiu-32 {
	dmas = <&audma0 0x71>, <&audma1 0x72>;
	dma-names = "rx", "tx";
	};
	ssiu41: ssiu-33 {
	dmas = <&audma0 0x17>, <&audma1 0x18>;
	dma-names = "rx", "tx";
	};
	ssiu42: ssiu-34 {
	dmas = <&audma0 0x19>, <&audma1 0x1A>;
	dma-names = "rx", "tx";
	};
	ssiu43: ssiu-35 {
	dmas = <&audma0 0x1B>, <&audma1 0x1C>;
	dma-names = "rx", "tx";
	};
	ssiu44: ssiu-36 {
	dmas = <&audma0 0x1D>, <&audma1 0x1E>;
	dma-names = "rx", "tx";
	};
	ssiu45: ssiu-37 {
	dmas = <&audma0 0x1F>, <&audma1 0x20>;
	dma-names = "rx", "tx";
	};
	ssiu46: ssiu-38 {
	dmas = <&audma0 0x31>, <&audma1 0x32>;
	dma-names = "rx", "tx";
	};
	ssiu47: ssiu-39 {
	dmas = <&audma0 0x33>, <&audma1 0x34>;
	dma-names = "rx", "tx";
	};
	ssiu50: ssiu-40 {
	dmas = <&audma0 0x73>, <&audma1 0x74>;
	dma-names = "rx", "tx";
	};
	ssiu60: ssiu-41 {
	dmas = <&audma0 0x75>, <&audma1 0x76>;
	dma-names = "rx", "tx";
	};
	ssiu70: ssiu-42 {
	dmas = <&audma0 0x79>, <&audma1 0x7a>;
	dma-names = "rx", "tx";
	};
	ssiu80: ssiu-43 {
	dmas = <&audma0 0x7b>, <&audma1 0x7c>;
	dma-names = "rx", "tx";
	};
	ssiu90: ssiu-44 {
	dmas = <&audma0 0x7d>, <&audma1 0x7e>;
	dma-names = "rx", "tx";
	};
	ssiu91: ssiu-45 {
	dmas = <&audma0 0x7F>, <&audma1 0x80>;
	dma-names = "rx", "tx";
	};
	ssiu92: ssiu-46 {
	dmas = <&audma0 0x81>, <&audma1 0x82>;
	dma-names = "rx", "tx";
	};
	ssiu93: ssiu-47 {
	dmas = <&audma0 0x83>, <&audma1 0x84>;
	dma-names = "rx", "tx";
	};
	ssiu94: ssiu-48 {
	dmas = <&audma0 0xA3>, <&audma1 0xA4>;
	dma-names = "rx", "tx";
	};
	ssiu95: ssiu-49 {
	dmas = <&audma0 0xA5>, <&audma1 0xA6>;
	dma-names = "rx", "tx";
	};
	ssiu96: ssiu-50 {
	dmas = <&audma0 0xA7>, <&audma1 0xA8>;
	dma-names = "rx", "tx";
	};
	ssiu97: ssiu-51 {
	dmas = <&audma0 0xA9>, <&audma1 0xAA>;
	dma-names = "rx", "tx";
	};
	};
	};

	audma0: dma-controller@ec700000 {
	compatible = "renesas,dmac-r8a7796",
	"renesas,rcar-dmac";
	reg = <0 0xec700000 0 0x10000>;
	interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 502>;
	clock-names = "fck";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 502>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
	<&ipmmu_mp 2>, <&ipmmu_mp 3>,
	<&ipmmu_mp 4>, <&ipmmu_mp 5>,
	<&ipmmu_mp 6>, <&ipmmu_mp 7>,
	<&ipmmu_mp 8>, <&ipmmu_mp 9>,
	<&ipmmu_mp 10>, <&ipmmu_mp 11>,
	<&ipmmu_mp 12>, <&ipmmu_mp 13>,
	<&ipmmu_mp 14>, <&ipmmu_mp 15>;
	};

	audma1: dma-controller@ec720000 {
	compatible = "renesas,dmac-r8a7796",
	"renesas,rcar-dmac";
	reg = <0 0xec720000 0 0x10000>;
	interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 501>;
	clock-names = "fck";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 501>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
	<&ipmmu_mp 18>, <&ipmmu_mp 19>,
	<&ipmmu_mp 20>, <&ipmmu_mp 21>,
	<&ipmmu_mp 22>, <&ipmmu_mp 23>,
	<&ipmmu_mp 24>, <&ipmmu_mp 25>,
	<&ipmmu_mp 26>, <&ipmmu_mp 27>,
	<&ipmmu_mp 28>, <&ipmmu_mp 29>,
	<&ipmmu_mp 30>, <&ipmmu_mp 31>;
	};

	xhci0: usb@ee000000 {
	compatible = "renesas,xhci-r8a7796",
	"renesas,rcar-gen3-xhci";
	reg = <0 0xee000000 0 0xc00>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	status = "disabled";
	};

	usb3_peri0: usb@ee020000 {
	compatible = "renesas,r8a7796-usb3-peri",
	"renesas,rcar-gen3-usb3-peri";
	reg = <0 0xee020000 0 0x400>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	status = "disabled";
	};

	ohci0: usb@ee080000 {
	compatible = "generic-ohci";
	reg = <0 0xee080000 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	phys = <&usb2_phy0 1>;
	phy-names = "usb";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	status = "disabled";
	};

	ohci1: usb@ee0a0000 {
	compatible = "generic-ohci";
	reg = <0 0xee0a0000 0 0x100>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 702>;
	phys = <&usb2_phy1 1>;
	phy-names = "usb";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 702>;
	status = "disabled";
	};

	ehci0: usb@ee080100 {
	compatible = "generic-ehci";
	reg = <0 0xee080100 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	phys = <&usb2_phy0 2>;
	phy-names = "usb";
	companion = <&ohci0>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	status = "disabled";
	};

	ehci1: usb@ee0a0100 {
	compatible = "generic-ehci";
	reg = <0 0xee0a0100 0 0x100>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 702>;
	phys = <&usb2_phy1 2>;
	phy-names = "usb";
	companion = <&ohci1>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 702>;
	status = "disabled";
	};

	usb2_phy0: usb-phy@ee080200 {
	compatible = "renesas,usb2-phy-r8a7796",
	"renesas,rcar-gen3-usb2-phy";
	reg = <0 0xee080200 0 0x700>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	#phy-cells = <1>;
	status = "disabled";
	};

	usb2_phy1: usb-phy@ee0a0200 {
	compatible = "renesas,usb2-phy-r8a7796",
	"renesas,rcar-gen3-usb2-phy";
	reg = <0 0xee0a0200 0 0x700>;
	clocks = <&cpg CPG_MOD 702>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 702>;
	#phy-cells = <1>;
	status = "disabled";
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a7796",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee100000 0 0x2000>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	iommus = <&ipmmu_ds1 32>;
	status = "disabled";
	};

	sdhi1: sd@ee120000 {
	compatible = "renesas,sdhi-r8a7796",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee120000 0 0x2000>;
	interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 313>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 313>;
	iommus = <&ipmmu_ds1 33>;
	status = "disabled";
	};

	sdhi2: sd@ee140000 {
	compatible = "renesas,sdhi-r8a7796",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee140000 0 0x2000>;
	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 312>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 312>;
	iommus = <&ipmmu_ds1 34>;
	status = "disabled";
	};

	sdhi3: sd@ee160000 {
	compatible = "renesas,sdhi-r8a7796",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee160000 0 0x2000>;
	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 311>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 311>;
	iommus = <&ipmmu_ds1 35>;
	status = "disabled";
	};

	gic: interrupt-controller@f1010000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x0 0xf1010000 0 0x1000>,
	<0x0 0xf1020000 0 0x20000>,
	<0x0 0xf1040000 0 0x20000>,
	<0x0 0xf1060000 0 0x20000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	pciec0: pcie@fe000000 {
	compatible = "renesas,pcie-r8a7796",
	"renesas,pcie-rcar-gen3";
	reg = <0 0xfe000000 0 0x80000>;
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x00 0xff>;
	device_type = "pci";
	ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
	<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
	<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
	<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
	/* Map all possible DDR as inbound ranges */
	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
	clock-names = "pcie", "pcie_bus";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 319>;
	status = "disabled";
	};

	pciec1: pcie@ee800000 {
	compatible = "renesas,pcie-r8a7796",
	"renesas,pcie-rcar-gen3";
	reg = <0 0xee800000 0 0x80000>;
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x00 0xff>;
	device_type = "pci";
	ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
	<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
	<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
	<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
	/* Map all possible DDR as inbound ranges */
	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
	clock-names = "pcie", "pcie_bus";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 318>;
	status = "disabled";
	};

	imr-lx4@fe860000 {
	compatible = "renesas,r8a7796-imr-lx4",
	"renesas,imr-lx4";
	reg = <0 0xfe860000 0 0x2000>;
	interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 823>;
	power-domains = <&sysc R8A7796_PD_A3VC>;
	resets = <&cpg 823>;
	};

	imr-lx4@fe870000 {
	compatible = "renesas,r8a7796-imr-lx4",
	"renesas,imr-lx4";
	reg = <0 0xfe870000 0 0x2000>;
	interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 822>;
	power-domains = <&sysc R8A7796_PD_A3VC>;
	resets = <&cpg 822>;
	};

	fdp1@fe940000 {
	compatible = "renesas,fdp1";
	reg = <0 0xfe940000 0 0x2400>;
	interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 119>;
	power-domains = <&sysc R8A7796_PD_A3VC>;
	resets = <&cpg 119>;
	renesas,fcp = <&fcpf0>;
	};

	fcpf0: fcp@fe950000 {
	compatible = "renesas,fcpf";
	reg = <0 0xfe950000 0 0x200>;
	clocks = <&cpg CPG_MOD 615>;
	power-domains = <&sysc R8A7796_PD_A3VC>;
	resets = <&cpg 615>;
	};

	fcpvb0: fcp@fe96f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe96f000 0 0x200>;
	clocks = <&cpg CPG_MOD 607>;
	power-domains = <&sysc R8A7796_PD_A3VC>;
	resets = <&cpg 607>;
	};

	fcpvi0: fcp@fe9af000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe9af000 0 0x200>;
	clocks = <&cpg CPG_MOD 611>;
	power-domains = <&sysc R8A7796_PD_A3VC>;
	resets = <&cpg 611>;
	iommus = <&ipmmu_vc0 19>;
	};

	fcpvd0: fcp@fea27000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea27000 0 0x200>;
	clocks = <&cpg CPG_MOD 603>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 603>;
	iommus = <&ipmmu_vi0 8>;
	};

	fcpvd1: fcp@fea2f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea2f000 0 0x200>;
	clocks = <&cpg CPG_MOD 602>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 602>;
	iommus = <&ipmmu_vi0 9>;
	};

	fcpvd2: fcp@fea37000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea37000 0 0x200>;
	clocks = <&cpg CPG_MOD 601>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 601>;
	iommus = <&ipmmu_vi0 10>;
	};

	vspb: vsp@fe960000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe960000 0 0x8000>;
	interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 626>;
	power-domains = <&sysc R8A7796_PD_A3VC>;
	resets = <&cpg 626>;

	renesas,fcp = <&fcpvb0>;
	};

	vspd0: vsp@fea20000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea20000 0 0x5000>;
	interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 623>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 623>;

	renesas,fcp = <&fcpvd0>;
	};

	vspd1: vsp@fea28000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea28000 0 0x5000>;
	interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 622>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 622>;

	renesas,fcp = <&fcpvd1>;
	};

	vspd2: vsp@fea30000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea30000 0 0x5000>;
	interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 621>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 621>;

	renesas,fcp = <&fcpvd2>;
	};

	vspi0: vsp@fe9a0000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe9a0000 0 0x8000>;
	interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 631>;
	power-domains = <&sysc R8A7796_PD_A3VC>;
	resets = <&cpg 631>;

	renesas,fcp = <&fcpvi0>;
	};

	cmm0: cmm@fea40000 {
	compatible = "renesas,r8a7796-cmm",
	"renesas,rcar-gen3-cmm";
	reg = <0 0xfea40000 0 0x1000>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	clocks = <&cpg CPG_MOD 711>;
	resets = <&cpg 711>;
	};

	cmm1: cmm@fea50000 {
	compatible = "renesas,r8a7796-cmm",
	"renesas,rcar-gen3-cmm";
	reg = <0 0xfea50000 0 0x1000>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	clocks = <&cpg CPG_MOD 710>;
	resets = <&cpg 710>;
	};

	cmm2: cmm@fea60000 {
	compatible = "renesas,r8a7796-cmm",
	"renesas,rcar-gen3-cmm";
	reg = <0 0xfea60000 0 0x1000>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	clocks = <&cpg CPG_MOD 709>;
	resets = <&cpg 709>;
	};

	csi20: csi2@fea80000 {
	compatible = "renesas,r8a7796-csi2";
	reg = <0 0xfea80000 0 0x10000>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 714>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 714>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	csi20vin0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vin0csi20>;
	};
	csi20vin1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vin1csi20>;
	};
	csi20vin2: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&vin2csi20>;
	};
	csi20vin3: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&vin3csi20>;
	};
	csi20vin4: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&vin4csi20>;
	};
	csi20vin5: endpoint@5 {
	reg = <5>;
	remote-endpoint = <&vin5csi20>;
	};
	csi20vin6: endpoint@6 {
	reg = <6>;
	remote-endpoint = <&vin6csi20>;
	};
	csi20vin7: endpoint@7 {
	reg = <7>;
	remote-endpoint = <&vin7csi20>;
	};
	};
	};
	};

	csi40: csi2@feaa0000 {
	compatible = "renesas,r8a7796-csi2";
	reg = <0 0xfeaa0000 0 0x10000>;
	interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	csi40vin0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vin0csi40>;
	};
	csi40vin1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vin1csi40>;
	};
	csi40vin2: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&vin2csi40>;
	};
	csi40vin3: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&vin3csi40>;
	};
	csi40vin4: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&vin4csi40>;
	};
	csi40vin5: endpoint@5 {
	reg = <5>;
	remote-endpoint = <&vin5csi40>;
	};
	csi40vin6: endpoint@6 {
	reg = <6>;
	remote-endpoint = <&vin6csi40>;
	};
	csi40vin7: endpoint@7 {
	reg = <7>;
	remote-endpoint = <&vin7csi40>;
	};
	};

	};
	};

	hdmi0: hdmi@fead0000 {
	compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
	reg = <0 0xfead0000 0 0x10000>;
	interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>;
	clock-names = "iahb", "isfr";
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 729>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;
	port@0 {
	reg = <0>;
	dw_hdmi0_in: endpoint {
	remote-endpoint = <&du_out_hdmi0>;
	};
	};
	port@1 {
	reg = <1>;
	};
	port@2 {
	/* HDMI sound */
	reg = <2>;
	};
	};
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a7796";
	reg = <0 0xfeb00000 0 0x70000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&cpg CPG_MOD 724>,
	- <&cpg CPG_MOD 723>,
	+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
	<&cpg CPG_MOD 722>;
	clock-names = "du.0", "du.1", "du.2";
	+ resets = <&cpg 724>, <&cpg 722>;
	+ reset-names = "du.0", "du.2";

	renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>;
	- vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
	+ renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;

	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb: endpoint {
	};
	};
	port@1 {
	reg = <1>;
	du_out_hdmi0: endpoint {
	remote-endpoint = <&dw_hdmi0_in>;
	};
	};
	port@2 {
	reg = <2>;
	du_out_lvds0: endpoint {
	remote-endpoint = <&lvds0_in>;
	};
	};
	};
	};

	lvds0: lvds@feb90000 {
	compatible = "renesas,r8a7796-lvds";
	reg = <0 0xfeb90000 0 0x14>;
	clocks = <&cpg CPG_MOD 727>;
	power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
	resets = <&cpg 727>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds0_in: endpoint {
	remote-endpoint = <&du_out_lvds0>;
	};
	};
	port@1 {
	reg = <1>;
	lvds0_out: endpoint {
	};
	};
	};
	};

	prr: chipid@fff00044 {
	compatible = "renesas,prr";
	reg = <0 0xfff00044 0 4>;
	};
	};

	thermal-zones {
	sensor_thermal1: sensor-thermal1 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&tsc 0>;
	sustainable-power = <3874>;

	trips {
	sensor1_crit: sensor1-crit {
	temperature = <120000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};
	};

	sensor_thermal2: sensor-thermal2 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&tsc 1>;
	sustainable-power = <3874>;

	trips {
	sensor2_crit: sensor2-crit {
	temperature = <120000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};
	};

	sensor_thermal3: sensor-thermal3 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&tsc 2>;
	sustainable-power = <3874>;

	cooling-maps {
	map0 {
	trip = <&target>;
	cooling-device = <&a57_0 2 4>;
	contribution = <1024>;
	};
	map1 {
	trip = <&target>;
	cooling-device = <&a53_0 0 2>;
	contribution = <1024>;
	};
	};
	trips {
	target: trip-point1 {
	temperature = <100000>;
	hysteresis = <1000>;
	type = "passive";
	};

	sensor3_crit: sensor3-crit {
	temperature = <120000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clocks - can be overridden by the board */
	usb3s0_clk: usb3s0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	usb_extal_clk: usb_extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a77961-salvator-xs.dts b/sys/gnu/dts/arm64/renesas/r8a77961-salvator-xs.dts
	index 4abd78ac1cd5..2ffc7e31dd58 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a77961-salvator-xs.dts
	+++ b/sys/gnu/dts/arm64/renesas/r8a77961-salvator-xs.dts
	@@ -1,31 +1,31 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the Salvator-X 2nd version board with R-Car M3-W+
	*
	* Copyright (C) 2018 Renesas Electronics Corp.
	*/

	/dts-v1/;
	#include "r8a77961.dtsi"
	#include "salvator-xs.dtsi"

	/ {
	model = "Renesas Salvator-X 2nd version board based on r8a77961";
	compatible = "renesas,salvator-xs", "renesas,r8a77961";

	memory@48000000 {
	device_type = "memory";
	/* first 128MB is reserved for secure area. */
	reg = <0x0 0x48000000 0x0 0x78000000>;
	};

	- memory@400000000 {
	+ memory@480000000 {
	device_type = "memory";
	reg = <0x4 0x80000000 0x0 0x80000000>;
	};

	memory@600000000 {
	device_type = "memory";
	reg = <0x6 0x00000000 0x1 0x00000000>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a77961-salvator-xs.dts b/sys/gnu/dts/arm64/renesas/r8a77961-ulcb.dts
	similarity index 57%
	copy from sys/gnu/dts/arm64/renesas/r8a77961-salvator-xs.dts
	copy to sys/gnu/dts/arm64/renesas/r8a77961-ulcb.dts
	index 4abd78ac1cd5..7c6e60f6f32d 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a77961-salvator-xs.dts
	+++ b/sys/gnu/dts/arm64/renesas/r8a77961-ulcb.dts
	@@ -1,31 +1,32 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	- * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-W+
	+ * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board with R-Car
	+ * M3-W+
	*
	- * Copyright (C) 2018 Renesas Electronics Corp.
	+ * Copyright (C) 2020 Renesas Electronics Corp.
	*/

	/dts-v1/;
	#include "r8a77961.dtsi"
	-#include "salvator-xs.dtsi"
	+#include "ulcb.dtsi"

	/ {
	- model = "Renesas Salvator-X 2nd version board based on r8a77961";
	- compatible = "renesas,salvator-xs", "renesas,r8a77961";
	+ model = "Renesas M3ULCB board based on r8a77961";
	+ compatible = "renesas,m3ulcb", "renesas,r8a77961";

	memory@48000000 {
	device_type = "memory";
	/* first 128MB is reserved for secure area. */
	reg = <0x0 0x48000000 0x0 0x78000000>;
	};

	- memory@400000000 {
	+ memory@480000000 {
	device_type = "memory";
	reg = <0x4 0x80000000 0x0 0x80000000>;
	};

	memory@600000000 {
	device_type = "memory";
	reg = <0x6 0x00000000 0x1 0x00000000>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a77961.dtsi b/sys/gnu/dts/arm64/renesas/r8a77961.dtsi
	index be3824bda632..0d96f2d3492b 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a77961.dtsi
	+++ b/sys/gnu/dts/arm64/renesas/r8a77961.dtsi
	@@ -1,1087 +1,1176 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
	*
	* Copyright (C) 2016-2017 Renesas Electronics Corp.
	*/

	#include <dt-bindings/clock/r8a77961-cpg-mssr.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/power/r8a77961-sysc.h>

	#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4

	/ {
	compatible = "renesas,r8a77961";
	#address-cells = <2>;
	#size-cells = <2>;

	/*
	* The external audio clocks are configured as 0 Hz fixed frequency
	* clocks by default.
	* Boards that provide audio clocks should override them.
	*/
	audio_clk_a: audio_clk_a {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_b: audio_clk_b {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_c: audio_clk_c {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	/* External CAN clock - to be overridden by boards that provide it */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	cluster0_opp: opp_table0 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-500000000 {
	opp-hz = /bits/ 64 <500000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1500000000 {
	opp-hz = /bits/ 64 <1500000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1600000000 {
	opp-hz = /bits/ 64 <1600000000>;
	opp-microvolt = <900000>;
	clock-latency-ns = <300000>;
	turbo-mode;
	};
	opp-1700000000 {
	opp-hz = /bits/ 64 <1700000000>;
	opp-microvolt = <900000>;
	clock-latency-ns = <300000>;
	turbo-mode;
	};
	opp-1800000000 {
	opp-hz = /bits/ 64 <1800000000>;
	opp-microvolt = <960000>;
	clock-latency-ns = <300000>;
	turbo-mode;
	};
	};

	cluster1_opp: opp_table1 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-800000000 {
	opp-hz = /bits/ 64 <800000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1300000000 {
	opp-hz = /bits/ 64 <1300000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	turbo-mode;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu-map {
	cluster0 {
	core0 {
	cpu = <&a57_0>;
	};
	core1 {
	cpu = <&a57_1>;
	};
	};

	cluster1 {
	core0 {
	cpu = <&a53_0>;
	};
	core1 {
	cpu = <&a53_1>;
	};
	core2 {
	cpu = <&a53_2>;
	};
	core3 {
	cpu = <&a53_3>;
	};
	};
	};

	a57_0: cpu@0 {
	compatible = "arm,cortex-a57";
	reg = <0x0>;
	device_type = "cpu";
	power-domains = <&sysc R8A77961_PD_CA57_CPU0>;
	next-level-cache = <&L2_CA57>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	dynamic-power-coefficient = <854>;
	clocks = <&cpg CPG_CORE R8A77961_CLK_Z>;
	operating-points-v2 = <&cluster0_opp>;
	capacity-dmips-mhz = <1024>;
	#cooling-cells = <2>;
	};

	a57_1: cpu@1 {
	compatible = "arm,cortex-a57";
	reg = <0x1>;
	device_type = "cpu";
	power-domains = <&sysc R8A77961_PD_CA57_CPU1>;
	next-level-cache = <&L2_CA57>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_0>;
	clocks = <&cpg CPG_CORE R8A77961_CLK_Z>;
	operating-points-v2 = <&cluster0_opp>;
	capacity-dmips-mhz = <1024>;
	#cooling-cells = <2>;
	};

	a53_0: cpu@100 {
	compatible = "arm,cortex-a53";
	reg = <0x100>;
	device_type = "cpu";
	power-domains = <&sysc R8A77961_PD_CA53_CPU0>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_1>;
	#cooling-cells = <2>;
	dynamic-power-coefficient = <277>;
	clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	capacity-dmips-mhz = <535>;
	};

	a53_1: cpu@101 {
	compatible = "arm,cortex-a53";
	reg = <0x101>;
	device_type = "cpu";
	power-domains = <&sysc R8A77961_PD_CA53_CPU1>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_1>;
	clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	capacity-dmips-mhz = <535>;
	};

	a53_2: cpu@102 {
	compatible = "arm,cortex-a53";
	reg = <0x102>;
	device_type = "cpu";
	power-domains = <&sysc R8A77961_PD_CA53_CPU2>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_1>;
	clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	capacity-dmips-mhz = <535>;
	};

	a53_3: cpu@103 {
	compatible = "arm,cortex-a53";
	reg = <0x103>;
	device_type = "cpu";
	power-domains = <&sysc R8A77961_PD_CA53_CPU3>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	cpu-idle-states = <&CPU_SLEEP_1>;
	clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	capacity-dmips-mhz = <535>;
	};

	L2_CA57: cache-controller-0 {
	compatible = "cache";
	power-domains = <&sysc R8A77961_PD_CA57_SCU>;
	cache-unified;
	cache-level = <2>;
	};

	L2_CA53: cache-controller-1 {
	compatible = "cache";
	power-domains = <&sysc R8A77961_PD_CA53_SCU>;
	cache-unified;
	cache-level = <2>;
	};

	idle-states {
	entry-method = "psci";

	CPU_SLEEP_0: cpu-sleep-0 {
	compatible = "arm,idle-state";
	arm,psci-suspend-param = <0x0010000>;
	local-timer-stop;
	entry-latency-us = <400>;
	exit-latency-us = <500>;
	min-residency-us = <4000>;
	};

	CPU_SLEEP_1: cpu-sleep-1 {
	compatible = "arm,idle-state";
	arm,psci-suspend-param = <0x0010000>;
	local-timer-stop;
	entry-latency-us = <700>;
	exit-latency-us = <700>;
	min-residency-us = <5000>;
	};
	};
	};

	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	extalr_clk: extalr {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	/* External PCIe clock - can be overridden by the board */
	pcie_bus_clk: pcie_bus {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	pmu_a53 {
	compatible = "arm,cortex-a53-pmu";
	interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
	};

	pmu_a57 {
	compatible = "arm,cortex-a57-pmu";
	interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&a57_0>, <&a57_1>;
	};

	psci {
	compatible = "arm,psci-1.0", "arm,psci-0.2";
	method = "smc";
	};

	/* External SCIF clock - to be overridden by boards that provide it */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a77961-wdt",
	"renesas,rcar-gen3-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a77961",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 16>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a77961",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 29>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a77961",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 15>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a77961",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 16>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a77961",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 18>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a77961",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	gpio6: gpio@e6055400 {
	compatible = "renesas,gpio-r8a77961",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055400 0 0x50>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 192 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 906>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 906>;
	};

	gpio7: gpio@e6055800 {
	compatible = "renesas,gpio-r8a77961",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055800 0 0x50>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 224 4>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 905>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 905>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a77961";
	reg = <0 0xe6060000 0 0x50c>;
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a77961-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>, <&extalr_clk>;
	clock-names = "extal", "extalr";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a77961-rst";
	reg = <0 0xe6160000 0 0x0200>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a77961-sysc";
	reg = <0 0xe6180000 0 0x0400>;
	#power-domain-cells = <1>;
	};

	+ tsc: thermal@e6198000 {
	+ compatible = "renesas,r8a77961-thermal";
	+ reg = <0 0xe6198000 0 0x100>,
	+ <0 0xe61a0000 0 0x100>,
	+ <0 0xe61a8000 0 0x100>;
	+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	+ clocks = <&cpg CPG_MOD 522>;
	+ power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	+ resets = <&cpg 522>;
	+ #thermal-sensor-cells = <1>;
	+ };
	+
	intc_ex: interrupt-controller@e61c0000 {
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	/* placeholder */
	};

	i2c0: i2c@e6500000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77961",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6500000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	dmas = <&dmac1 0x91>, <&dmac1 0x90>,
	<&dmac2 0x91>, <&dmac2 0x90>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c1: i2c@e6508000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77961",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	dmas = <&dmac1 0x93>, <&dmac1 0x92>,
	<&dmac2 0x93>, <&dmac2 0x92>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c2: i2c@e6510000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77961",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6510000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	dmas = <&dmac1 0x95>, <&dmac1 0x94>,
	<&dmac2 0x95>, <&dmac2 0x94>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c3: i2c@e66d0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77961",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d0000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	dmas = <&dmac0 0x97>, <&dmac0 0x96>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c4: i2c@e66d8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77961",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d8000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	dmas = <&dmac0 0x99>, <&dmac0 0x98>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c5: i2c@e66e0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77961",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66e0000 0 0x40>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 919>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 919>;
	dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c6: i2c@e66e8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77961",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66e8000 0 0x40>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 918>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 918>;
	dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c_dvfs: i2c@e60b0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a77961",
	"renesas,rcar-gen3-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe60b0000 0 0x425>;
	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 926>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 926>;
	dmas = <&dmac0 0x11>, <&dmac0 0x10>;
	dma-names = "tx", "rx";
	status = "disabled";
	};


	hscif1: serial@e6550000 {
	reg = <0 0xe6550000 0 0x60>;
	/* placeholder */
	};

	hsusb: usb@e6590000 {
	reg = <0 0xe6590000 0 0x200>;
	/* placeholder */
	};

	usb3_phy0: usb-phy@e65ee000 {
	reg = <0 0xe65ee000 0 0x90>;
	#phy-cells = <0>;
	/* placeholder */
	};

	+ arm_cc630p: crypto@e6601000 {
	+ compatible = "arm,cryptocell-630p-ree";
	+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0 0xe6601000 0 0x1000>;
	+ clocks = <&cpg CPG_MOD 229>;
	+ resets = <&cpg 229>;
	+ power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	+ };
	+
	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a77961",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x10000>;
	interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <16>;
	};

	dmac1: dma-controller@e7300000 {
	compatible = "renesas,dmac-r8a77961",
	"renesas,rcar-dmac";
	reg = <0 0xe7300000 0 0x10000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <16>;
	};

	dmac2: dma-controller@e7310000 {
	compatible = "renesas,dmac-r8a77961",
	"renesas,rcar-dmac";
	reg = <0 0xe7310000 0 0x10000>;
	interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 217>;
	clock-names = "fck";
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 217>;
	#dma-cells = <1>;
	dma-channels = <16>;
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a77961",
	"renesas,etheravb-rcar-gen3";
	reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15",
	"ch16", "ch17", "ch18", "ch19",
	"ch20", "ch21", "ch22", "ch23",
	"ch24";
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	phy-mode = "rgmii";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	pwm1: pwm@e6e31000 {
	reg = <0 0xe6e31000 0 8>;
	#pwm-cells = <2>;
	/* placeholder */
	};

	scif1: serial@e6e68000 {
	reg = <0 0xe6e68000 0 64>;
	/* placeholder */
	};

	scif2: serial@e6e88000 {
	compatible = "renesas,scif-r8a77961",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e88000 0 64>;
	interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 310>,
	<&cpg CPG_CORE R8A77961_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 310>;
	status = "disabled";
	};

	vin0: video@e6ef0000 {
	reg = <0 0xe6ef0000 0 0x1000>;
	/* placeholder */
	};

	vin1: video@e6ef1000 {
	reg = <0 0xe6ef1000 0 0x1000>;
	/* placeholder */
	};

	vin2: video@e6ef2000 {
	reg = <0 0xe6ef2000 0 0x1000>;
	/* placeholder */
	};

	vin3: video@e6ef3000 {
	reg = <0 0xe6ef3000 0 0x1000>;
	/* placeholder */
	};

	vin4: video@e6ef4000 {
	reg = <0 0xe6ef4000 0 0x1000>;
	/* placeholder */
	};

	vin5: video@e6ef5000 {
	reg = <0 0xe6ef5000 0 0x1000>;
	/* placeholder */
	};

	vin6: video@e6ef6000 {
	reg = <0 0xe6ef6000 0 0x1000>;
	/* placeholder */
	};

	vin7: video@e6ef7000 {
	reg = <0 0xe6ef7000 0 0x1000>;
	/* placeholder */
	};

	rcar_sound: sound@ec500000 {
	reg = <0 0xec500000 0 0x1000>, /* SCU */
	<0 0xec5a0000 0 0x100>, /* ADG */
	<0 0xec540000 0 0x1000>, /* SSIU */
	<0 0xec541000 0 0x280>, /* SSI */
	<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
	/* placeholder */
	rcar_sound,dvc {
	dvc0: dvc-0 { };
	dvc1: dvc-1 { };
	};

	rcar_sound,src {
	src0: src-0 { };
	src1: src-1 { };
	};

	rcar_sound,ssi {
	ssi0: ssi-0 { };
	ssi1: ssi-1 { };
	+ ssi2: ssi-2 { };
	};
	};

	xhci0: usb@ee000000 {
	reg = <0 0xee000000 0 0xc00>;
	/* placeholder */
	};

	usb3_peri0: usb@ee020000 {
	reg = <0 0xee020000 0 0x400>;
	/* placeholder */
	};

	ohci0: usb@ee080000 {
	reg = <0 0xee080000 0 0x100>;
	/* placeholder */
	};

	ohci1: usb@ee0a0000 {
	reg = <0 0xee0a0000 0 0x100>;
	/* placeholder */
	};

	ehci0: usb@ee080100 {
	reg = <0 0xee080100 0 0x100>;
	/* placeholder */
	};

	ehci1: usb@ee0a0100 {
	reg = <0 0xee0a0100 0 0x100>;
	/* placeholder */
	};

	usb2_phy0: usb-phy@ee080200 {
	reg = <0 0xee080200 0 0x700>;
	/* placeholder */
	};

	usb2_phy1: usb-phy@ee0a0200 {
	reg = <0 0xee0a0200 0 0x700>;
	/* placeholder */
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a77961",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee100000 0 0x2000>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	status = "disabled";
	};

	sdhi1: sd@ee120000 {
	compatible = "renesas,sdhi-r8a77961",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee120000 0 0x2000>;
	interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 313>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 313>;
	status = "disabled";
	};

	sdhi2: sd@ee140000 {
	compatible = "renesas,sdhi-r8a77961",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee140000 0 0x2000>;
	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 312>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 312>;
	status = "disabled";
	};

	sdhi3: sd@ee160000 {
	compatible = "renesas,sdhi-r8a77961",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee160000 0 0x2000>;
	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 311>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 311>;
	status = "disabled";
	};

	gic: interrupt-controller@f1010000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x0 0xf1010000 0 0x1000>,
	<0x0 0xf1020000 0 0x20000>,
	<0x0 0xf1040000 0 0x20000>,
	<0x0 0xf1060000 0 0x20000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	pciec0: pcie@fe000000 {
	reg = <0 0xfe000000 0 0x80000>;
	/* placeholder */
	};

	pciec1: pcie@ee800000 {
	reg = <0 0xee800000 0 0x80000>;
	/* placeholder */
	};

	csi20: csi2@fea80000 {
	reg = <0 0xfea80000 0 0x10000>;
	/* placeholder */

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;
	};
	};
	};

	csi40: csi2@feaa0000 {
	reg = <0 0xfeaa0000 0 0x10000>;
	/* placeholder */

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;
	};
	};
	};

	hdmi0: hdmi@fead0000 {
	reg = <0 0xfead0000 0 0x10000>;
	/* placeholder */

	ports {
	#address-cells = <1>;
	#size-cells = <0>;
	port@0 {
	reg = <0>;
	};
	port@1 {
	reg = <1>;
	};
	port@2 {
	/* HDMI sound */
	reg = <2>;
	};
	};
	};

	du: display@feb00000 {
	reg = <0 0xfeb00000 0 0x70000>;
	/* placeholder */

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb: endpoint {
	};
	};
	port@1 {
	reg = <1>;
	du_out_hdmi0: endpoint {
	};
	};
	port@2 {
	reg = <2>;
	du_out_lvds0: endpoint {
	};
	};
	};
	};

	prr: chipid@fff00044 {
	compatible = "renesas,prr";
	reg = <0 0xfff00044 0 4>;
	};
	};

	+ thermal-zones {
	+ sensor_thermal1: sensor-thermal1 {
	+ polling-delay-passive = <250>;
	+ polling-delay = <1000>;
	+ thermal-sensors = <&tsc 0>;
	+ sustainable-power = <3874>;
	+
	+ trips {
	+ sensor1_crit: sensor1-crit {
	+ temperature = <120000>;
	+ hysteresis = <1000>;
	+ type = "critical";
	+ };
	+ };
	+ };
	+
	+ sensor_thermal2: sensor-thermal2 {
	+ polling-delay-passive = <250>;
	+ polling-delay = <1000>;
	+ thermal-sensors = <&tsc 1>;
	+ sustainable-power = <3874>;
	+
	+ trips {
	+ sensor2_crit: sensor2-crit {
	+ temperature = <120000>;
	+ hysteresis = <1000>;
	+ type = "critical";
	+ };
	+ };
	+ };
	+
	+ sensor_thermal3: sensor-thermal3 {
	+ polling-delay-passive = <250>;
	+ polling-delay = <1000>;
	+ thermal-sensors = <&tsc 2>;
	+ sustainable-power = <3874>;
	+
	+ cooling-maps {
	+ map0 {
	+ trip = <&target>;
	+ cooling-device = <&a57_0 2 4>;
	+ contribution = <1024>;
	+ };
	+ map1 {
	+ trip = <&target>;
	+ cooling-device = <&a53_0 0 2>;
	+ contribution = <1024>;
	+ };
	+ };
	+ trips {
	+ target: trip-point1 {
	+ temperature = <100000>;
	+ hysteresis = <1000>;
	+ type = "passive";
	+ };
	+
	+ sensor3_crit: sensor3-crit {
	+ temperature = <120000>;
	+ hysteresis = <1000>;
	+ type = "critical";
	+ };
	+ };
	+ };
	+ };
	+
	timer {
	compatible = "arm,armv8-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clocks - can be overridden by the board */
	usb3s0_clk: usb3s0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	usb_extal_clk: usb_extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a77965.dtsi b/sys/gnu/dts/arm64/renesas/r8a77965.dtsi
	index c17d90bd160e..d82dd4e67b62 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a77965.dtsi
	+++ b/sys/gnu/dts/arm64/renesas/r8a77965.dtsi
	@@ -1,2645 +1,2670 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the R-Car M3-N (R8A77965) SoC
	*
	* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
	*
	* Based on r8a7796.dtsi
	* Copyright (C) 2016 Renesas Electronics Corp.
	*/

	#include <dt-bindings/clock/r8a77965-cpg-mssr.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/power/r8a77965-sysc.h>

	#define CPG_AUDIO_CLK_I R8A77965_CLK_S0D4

	/ {
	compatible = "renesas,r8a77965";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	i2c6 = &i2c6;
	i2c7 = &i2c_dvfs;
	};

	/*
	* The external audio clocks are configured as 0 Hz fixed frequency
	* clocks by default.
	* Boards that provide audio clocks should override them.
	*/
	audio_clk_a: audio_clk_a {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_b: audio_clk_b {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_c: audio_clk_c {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	/* External CAN clock - to be overridden by boards that provide it */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	cluster0_opp: opp_table0 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-500000000 {
	opp-hz = /bits/ 64 <500000000>;
	opp-microvolt = <830000>;
	clock-latency-ns = <300000>;
	};
	opp-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	opp-microvolt = <830000>;
	clock-latency-ns = <300000>;
	};
	opp-1500000000 {
	opp-hz = /bits/ 64 <1500000000>;
	opp-microvolt = <830000>;
	clock-latency-ns = <300000>;
	opp-suspend;
	};
	opp-1600000000 {
	opp-hz = /bits/ 64 <1600000000>;
	opp-microvolt = <900000>;
	clock-latency-ns = <300000>;
	turbo-mode;
	};
	opp-1700000000 {
	opp-hz = /bits/ 64 <1700000000>;
	opp-microvolt = <900000>;
	clock-latency-ns = <300000>;
	turbo-mode;
	};
	opp-1800000000 {
	opp-hz = /bits/ 64 <1800000000>;
	opp-microvolt = <960000>;
	clock-latency-ns = <300000>;
	turbo-mode;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	a57_0: cpu@0 {
	compatible = "arm,cortex-a57";
	reg = <0x0>;
	device_type = "cpu";
	power-domains = <&sysc R8A77965_PD_CA57_CPU0>;
	next-level-cache = <&L2_CA57>;
	enable-method = "psci";
	+ cpu-idle-states = <&CPU_SLEEP_0>;
	#cooling-cells = <2>;
	dynamic-power-coefficient = <854>;
	clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
	operating-points-v2 = <&cluster0_opp>;
	};

	a57_1: cpu@1 {
	compatible = "arm,cortex-a57";
	reg = <0x1>;
	device_type = "cpu";
	power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
	next-level-cache = <&L2_CA57>;
	enable-method = "psci";
	+ cpu-idle-states = <&CPU_SLEEP_0>;
	clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
	operating-points-v2 = <&cluster0_opp>;
	};

	L2_CA57: cache-controller-0 {
	compatible = "cache";
	power-domains = <&sysc R8A77965_PD_CA57_SCU>;
	cache-unified;
	cache-level = <2>;
	};
	+
	+ idle-states {
	+ entry-method = "psci";
	+
	+ CPU_SLEEP_0: cpu-sleep-0 {
	+ compatible = "arm,idle-state";
	+ arm,psci-suspend-param = <0x0010000>;
	+ local-timer-stop;
	+ entry-latency-us = <400>;
	+ exit-latency-us = <500>;
	+ min-residency-us = <4000>;
	+ };
	+ };
	};

	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	extalr_clk: extalr {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	/* External PCIe clock - can be overridden by the board */
	pcie_bus_clk: pcie_bus {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	pmu_a57 {
	compatible = "arm,cortex-a57-pmu";
	interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&a57_0>,
	<&a57_1>;
	};

	psci {
	compatible = "arm,psci-1.0", "arm,psci-0.2";
	method = "smc";
	};

	/* External SCIF clock - to be overridden by boards that provide it */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a77965-wdt",
	"renesas,rcar-gen3-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a77965",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 16>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a77965",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 29>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a77965",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 15>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a77965",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 16>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a77965",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 18>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a77965",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	gpio6: gpio@e6055400 {
	compatible = "renesas,gpio-r8a77965",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055400 0 0x50>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 192 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 906>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 906>;
	};

	gpio7: gpio@e6055800 {
	compatible = "renesas,gpio-r8a77965",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055800 0 0x50>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 224 4>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 905>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 905>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a77965";
	reg = <0 0xe6060000 0 0x50c>;
	};

	cmt0: timer@e60f0000 {
	compatible = "renesas,r8a77965-cmt0",
	"renesas,rcar-gen3-cmt0";
	reg = <0 0xe60f0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 303>;
	clock-names = "fck";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 303>;
	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a77965-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 302>;
	clock-names = "fck";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 302>;
	status = "disabled";
	};

	cmt2: timer@e6140000 {
	compatible = "renesas,r8a77965-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6140000 0 0x1004>;
	interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 301>;
	clock-names = "fck";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 301>;
	status = "disabled";
	};

	cmt3: timer@e6148000 {
	compatible = "renesas,r8a77965-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6148000 0 0x1004>;
	interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 300>;
	clock-names = "fck";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 300>;
	status = "disabled";
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a77965-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>, <&extalr_clk>;
	clock-names = "extal", "extalr";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a77965-rst";
	reg = <0 0xe6160000 0 0x0200>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a77965-sysc";
	reg = <0 0xe6180000 0 0x0400>;
	#power-domain-cells = <1>;
	};

	tsc: thermal@e6198000 {
	compatible = "renesas,r8a77965-thermal";
	reg = <0 0xe6198000 0 0x100>,
	<0 0xe61a0000 0 0x100>,
	<0 0xe61a8000 0 0x100>;
	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 522>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 522>;
	#thermal-sensor-cells = <1>;
	};

	intc_ex: interrupt-controller@e61c0000 {
	compatible = "renesas,intc-ex-r8a77965", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	i2c0: i2c@e6500000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77965",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6500000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	dmas = <&dmac1 0x91>, <&dmac1 0x90>,
	<&dmac2 0x91>, <&dmac2 0x90>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c1: i2c@e6508000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77965",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	dmas = <&dmac1 0x93>, <&dmac1 0x92>,
	<&dmac2 0x93>, <&dmac2 0x92>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c2: i2c@e6510000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77965",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6510000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	dmas = <&dmac1 0x95>, <&dmac1 0x94>,
	<&dmac2 0x95>, <&dmac2 0x94>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c3: i2c@e66d0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77965",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d0000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	dmas = <&dmac0 0x97>, <&dmac0 0x96>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c4: i2c@e66d8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77965",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d8000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	dmas = <&dmac0 0x99>, <&dmac0 0x98>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c5: i2c@e66e0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77965",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66e0000 0 0x40>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 919>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 919>;
	dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c6: i2c@e66e8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77965",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66e8000 0 0x40>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 918>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 918>;
	dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c_dvfs: i2c@e60b0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a77965",
	"renesas,rcar-gen3-iic",
	"renesas,rmobile-iic";
	reg = <0 0xe60b0000 0 0x425>;
	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 926>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 926>;
	dmas = <&dmac0 0x11>, <&dmac0 0x10>;
	dma-names = "tx", "rx";
	status = "disabled";
	};

	hscif0: serial@e6540000 {
	compatible = "renesas,hscif-r8a77965",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6540000 0 0x60>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 520>,
	<&cpg CPG_CORE R8A77965_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x31>, <&dmac1 0x30>,
	<&dmac2 0x31>, <&dmac2 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 520>;
	status = "disabled";
	};

	hscif1: serial@e6550000 {
	compatible = "renesas,hscif-r8a77965",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6550000 0 0x60>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 519>,
	<&cpg CPG_CORE R8A77965_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x33>, <&dmac1 0x32>,
	<&dmac2 0x33>, <&dmac2 0x32>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 519>;
	status = "disabled";
	};

	hscif2: serial@e6560000 {
	compatible = "renesas,hscif-r8a77965",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6560000 0 0x60>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 518>,
	<&cpg CPG_CORE R8A77965_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x35>, <&dmac1 0x34>,
	<&dmac2 0x35>, <&dmac2 0x34>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 518>;
	status = "disabled";
	};

	hscif3: serial@e66a0000 {
	compatible = "renesas,hscif-r8a77965",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe66a0000 0 0x60>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 517>,
	<&cpg CPG_CORE R8A77965_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x37>, <&dmac0 0x36>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 517>;
	status = "disabled";
	};

	hscif4: serial@e66b0000 {
	compatible = "renesas,hscif-r8a77965",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe66b0000 0 0x60>;
	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 516>,
	<&cpg CPG_CORE R8A77965_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x39>, <&dmac0 0x38>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 516>;
	status = "disabled";
	};

	hsusb: usb@e6590000 {
	compatible = "renesas,usbhs-r8a77965",
	"renesas,rcar-gen3-usbhs";
	reg = <0 0xe6590000 0 0x200>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
	dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
	<&usb_dmac1 0>, <&usb_dmac1 1>;
	dma-names = "ch0", "ch1", "ch2", "ch3";
	renesas,buswait = <11>;
	phys = <&usb2_phy0 3>;
	phy-names = "usb";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 704>, <&cpg 703>;
	status = "disabled";
	};

	usb_dmac0: dma-controller@e65a0000 {
	compatible = "renesas,r8a77965-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65a0000 0 0x100>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 330>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 330>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac1: dma-controller@e65b0000 {
	compatible = "renesas,r8a77965-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65b0000 0 0x100>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 331>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 331>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb3_phy0: usb-phy@e65ee000 {
	compatible = "renesas,r8a77965-usb3-phy",
	"renesas,rcar-gen3-usb3-phy";
	reg = <0 0xe65ee000 0 0x90>;
	clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
	<&usb_extal_clk>;
	clock-names = "usb3-if", "usb3s_clk", "usb_extal";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	#phy-cells = <0>;
	status = "disabled";
	};

	+ arm_cc630p: crypto@e6601000 {
	+ compatible = "arm,cryptocell-630p-ree";
	+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0 0xe6601000 0 0x1000>;
	+ clocks = <&cpg CPG_MOD 229>;
	+ resets = <&cpg 229>;
	+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	+ };
	+
	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a77965",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x10000>;
	interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
	<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
	<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
	<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
	<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
	<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
	<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
	<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
	};

	dmac1: dma-controller@e7300000 {
	compatible = "renesas,dmac-r8a77965",
	"renesas,rcar-dmac";
	reg = <0 0xe7300000 0 0x10000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
	<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
	<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
	<&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
	<&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
	<&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
	<&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
	<&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
	};

	dmac2: dma-controller@e7310000 {
	compatible = "renesas,dmac-r8a77965",
	"renesas,rcar-dmac";
	reg = <0 0xe7310000 0 0x10000>;
	interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 217>;
	clock-names = "fck";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 217>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
	<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
	<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
	<&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
	<&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
	<&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
	<&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
	<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
	};

	ipmmu_ds0: mmu@e6740000 {
	compatible = "renesas,ipmmu-r8a77965";
	reg = <0 0xe6740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 0>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_ds1: mmu@e7740000 {
	compatible = "renesas,ipmmu-r8a77965";
	reg = <0 0xe7740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 1>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_hc: mmu@e6570000 {
	compatible = "renesas,ipmmu-r8a77965";
	reg = <0 0xe6570000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 2>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_mm: mmu@e67b0000 {
	compatible = "renesas,ipmmu-r8a77965";
	reg = <0 0xe67b0000 0 0x1000>;
	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_mp: mmu@ec670000 {
	compatible = "renesas,ipmmu-r8a77965";
	reg = <0 0xec670000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 4>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_pv0: mmu@fd800000 {
	compatible = "renesas,ipmmu-r8a77965";
	reg = <0 0xfd800000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 6>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_rt: mmu@ffc80000 {
	compatible = "renesas,ipmmu-r8a77965";
	reg = <0 0xffc80000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 10>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vc0: mmu@fe6b0000 {
	compatible = "renesas,ipmmu-r8a77965";
	reg = <0 0xfe6b0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 12>;
	power-domains = <&sysc R8A77965_PD_A3VC>;
	#iommu-cells = <1>;
	};

	ipmmu_vi0: mmu@febd0000 {
	compatible = "renesas,ipmmu-r8a77965";
	reg = <0 0xfebd0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 14>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vp0: mmu@fe990000 {
	compatible = "renesas,ipmmu-r8a77965";
	reg = <0 0xfe990000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 16>;
	power-domains = <&sysc R8A77965_PD_A3VP>;
	#iommu-cells = <1>;
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a77965",
	"renesas,etheravb-rcar-gen3";
	reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15",
	"ch16", "ch17", "ch18", "ch19",
	"ch20", "ch21", "ch22", "ch23",
	"ch24";
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	phy-mode = "rgmii";
	iommus = <&ipmmu_ds0 16>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	can0: can@e6c30000 {
	compatible = "renesas,can-r8a77965",
	"renesas,rcar-gen3-can";
	reg = <0 0xe6c30000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 916>,
	<&cpg CPG_CORE R8A77965_CLK_CANFD>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 916>;
	status = "disabled";
	};

	can1: can@e6c38000 {
	compatible = "renesas,can-r8a77965",
	"renesas,rcar-gen3-can";
	reg = <0 0xe6c38000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 915>,
	<&cpg CPG_CORE R8A77965_CLK_CANFD>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 915>;
	status = "disabled";
	};

	canfd: can@e66c0000 {
	compatible = "renesas,r8a77965-canfd",
	"renesas,rcar-gen3-canfd";
	reg = <0 0xe66c0000 0 0x8000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 914>,
	<&cpg CPG_CORE R8A77965_CLK_CANFD>,
	<&can_clk>;
	clock-names = "fck", "canfd", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 914>;
	status = "disabled";

	channel0 {
	status = "disabled";
	};

	channel1 {
	status = "disabled";
	};
	};

	pwm0: pwm@e6e30000 {
	compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
	reg = <0 0xe6e30000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm1: pwm@e6e31000 {
	compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
	reg = <0 0xe6e31000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm2: pwm@e6e32000 {
	compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
	reg = <0 0xe6e32000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm3: pwm@e6e33000 {
	compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
	reg = <0 0xe6e33000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm4: pwm@e6e34000 {
	compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
	reg = <0 0xe6e34000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm5: pwm@e6e35000 {
	compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
	reg = <0 0xe6e35000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	status = "disabled";
	};

	pwm6: pwm@e6e36000 {
	compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
	reg = <0 0xe6e36000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	resets = <&cpg 523>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a77965",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e60000 0 64>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 207>,
	<&cpg CPG_CORE R8A77965_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x51>, <&dmac1 0x50>,
	<&dmac2 0x51>, <&dmac2 0x50>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 207>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a77965",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e68000 0 64>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 206>,
	<&cpg CPG_CORE R8A77965_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x53>, <&dmac1 0x52>,
	<&dmac2 0x53>, <&dmac2 0x52>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 206>;
	status = "disabled";
	};

	scif2: serial@e6e88000 {
	compatible = "renesas,scif-r8a77965",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e88000 0 64>;
	interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 310>,
	<&cpg CPG_CORE R8A77965_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x13>, <&dmac1 0x12>,
	<&dmac2 0x13>, <&dmac2 0x12>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 310>;
	status = "disabled";
	};

	scif3: serial@e6c50000 {
	compatible = "renesas,scif-r8a77965",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6c50000 0 64>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 204>,
	<&cpg CPG_CORE R8A77965_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x57>, <&dmac0 0x56>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 204>;
	status = "disabled";
	};

	scif4: serial@e6c40000 {
	compatible = "renesas,scif-r8a77965",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6c40000 0 64>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 203>,
	<&cpg CPG_CORE R8A77965_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x59>, <&dmac0 0x58>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 203>;
	status = "disabled";
	};

	scif5: serial@e6f30000 {
	compatible = "renesas,scif-r8a77965",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6f30000 0 64>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 202>,
	<&cpg CPG_CORE R8A77965_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
	<&dmac2 0x5b>, <&dmac2 0x5a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 202>;
	status = "disabled";
	};

	tpu: pwm@e6e80000 {
	compatible = "renesas,tpu-r8a77965", "renesas,tpu";
	reg = <0 0xe6e80000 0 0x148>;
	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 304>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 304>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	msiof0: spi@e6e90000 {
	compatible = "renesas,msiof-r8a77965",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6e90000 0 0x0064>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 211>;
	dmas = <&dmac1 0x41>, <&dmac1 0x40>,
	<&dmac2 0x41>, <&dmac2 0x40>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 211>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof1: spi@e6ea0000 {
	compatible = "renesas,msiof-r8a77965",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6ea0000 0 0x0064>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 210>;
	dmas = <&dmac1 0x43>, <&dmac1 0x42>,
	<&dmac2 0x43>, <&dmac2 0x42>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 210>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof2: spi@e6c00000 {
	compatible = "renesas,msiof-r8a77965",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c00000 0 0x0064>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 209>;
	dmas = <&dmac0 0x45>, <&dmac0 0x44>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 209>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof3: spi@e6c10000 {
	compatible = "renesas,msiof-r8a77965",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c10000 0 0x0064>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 208>;
	dmas = <&dmac0 0x47>, <&dmac0 0x46>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 208>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	vin0: video@e6ef0000 {
	compatible = "renesas,vin-r8a77965";
	reg = <0 0xe6ef0000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 811>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 811>;
	renesas,id = <0>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin0csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin0>;
	};
	vin0csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin0>;
	};
	};
	};
	};

	vin1: video@e6ef1000 {
	compatible = "renesas,vin-r8a77965";
	reg = <0 0xe6ef1000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 810>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 810>;
	renesas,id = <1>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin1csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin1>;
	};
	vin1csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin1>;
	};
	};
	};
	};

	vin2: video@e6ef2000 {
	compatible = "renesas,vin-r8a77965";
	reg = <0 0xe6ef2000 0 0x1000>;
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 809>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 809>;
	renesas,id = <2>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin2csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin2>;
	};
	vin2csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin2>;
	};
	};
	};
	};

	vin3: video@e6ef3000 {
	compatible = "renesas,vin-r8a77965";
	reg = <0 0xe6ef3000 0 0x1000>;
	interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 808>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 808>;
	renesas,id = <3>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin3csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin3>;
	};
	vin3csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin3>;
	};
	};
	};
	};

	vin4: video@e6ef4000 {
	compatible = "renesas,vin-r8a77965";
	reg = <0 0xe6ef4000 0 0x1000>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 807>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 807>;
	renesas,id = <4>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin4csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin4>;
	};
	vin4csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin4>;
	};
	};
	};
	};

	vin5: video@e6ef5000 {
	compatible = "renesas,vin-r8a77965";
	reg = <0 0xe6ef5000 0 0x1000>;
	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 806>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 806>;
	renesas,id = <5>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin5csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin5>;
	};
	vin5csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin5>;
	};
	};
	};
	};

	vin6: video@e6ef6000 {
	compatible = "renesas,vin-r8a77965";
	reg = <0 0xe6ef6000 0 0x1000>;
	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 805>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 805>;
	renesas,id = <6>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin6csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin6>;
	};
	vin6csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin6>;
	};
	};
	};
	};

	vin7: video@e6ef7000 {
	compatible = "renesas,vin-r8a77965";
	reg = <0 0xe6ef7000 0 0x1000>;
	interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 804>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 804>;
	renesas,id = <7>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin7csi20: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&csi20vin7>;
	};
	vin7csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin7>;
	};
	};
	};
	};

	rcar_sound: sound@ec500000 {
	/*
	* #sound-dai-cells is required
	*
	* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
	* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
	*/
	/*
	* #clock-cells is required for audio_clkout0/1/2/3
	*
	* clkout : #clock-cells = <0>; <&rcar_sound>;
	* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
	*/
	compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3";
	reg = <0 0xec500000 0 0x1000>, /* SCU */
	<0 0xec5a0000 0 0x100>, /* ADG */
	<0 0xec540000 0 0x1000>, /* SSIU */
	<0 0xec541000 0 0x280>, /* SSI */
	<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
	reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

	clocks = <&cpg CPG_MOD 1005>,
	<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
	<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
	<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
	<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
	<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	<&audio_clk_a>, <&audio_clk_b>,
	<&audio_clk_c>,
	<&cpg CPG_CORE R8A77965_CLK_S0D4>;
	clock-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0",
	"src.9", "src.8", "src.7", "src.6",
	"src.5", "src.4", "src.3", "src.2",
	"src.1", "src.0",
	"mix.1", "mix.0",
	"ctu.1", "ctu.0",
	"dvc.0", "dvc.1",
	"clk_a", "clk_b", "clk_c", "clk_i";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 1005>,
	<&cpg 1006>, <&cpg 1007>,
	<&cpg 1008>, <&cpg 1009>,
	<&cpg 1010>, <&cpg 1011>,
	<&cpg 1012>, <&cpg 1013>,
	<&cpg 1014>, <&cpg 1015>;
	reset-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0";
	status = "disabled";

	rcar_sound,dvc {
	dvc0: dvc-0 {
	dmas = <&audma1 0xbc>;
	dma-names = "tx";
	};
	dvc1: dvc-1 {
	dmas = <&audma1 0xbe>;
	dma-names = "tx";
	};
	};

	rcar_sound,mix {
	mix0: mix-0 { };
	mix1: mix-1 { };
	};

	rcar_sound,ctu {
	ctu00: ctu-0 { };
	ctu01: ctu-1 { };
	ctu02: ctu-2 { };
	ctu03: ctu-3 { };
	ctu10: ctu-4 { };
	ctu11: ctu-5 { };
	ctu12: ctu-6 { };
	ctu13: ctu-7 { };
	};

	rcar_sound,src {
	src0: src-0 {
	interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x85>, <&audma1 0x9a>;
	dma-names = "rx", "tx";
	};
	src1: src-1 {
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x87>, <&audma1 0x9c>;
	dma-names = "rx", "tx";
	};
	src2: src-2 {
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x89>, <&audma1 0x9e>;
	dma-names = "rx", "tx";
	};
	src3: src-3 {
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8b>, <&audma1 0xa0>;
	dma-names = "rx", "tx";
	};
	src4: src-4 {
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8d>, <&audma1 0xb0>;
	dma-names = "rx", "tx";
	};
	src5: src-5 {
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8f>, <&audma1 0xb2>;
	dma-names = "rx", "tx";
	};
	src6: src-6 {
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x91>, <&audma1 0xb4>;
	dma-names = "rx", "tx";
	};
	src7: src-7 {
	interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x93>, <&audma1 0xb6>;
	dma-names = "rx", "tx";
	};
	src8: src-8 {
	interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x95>, <&audma1 0xb8>;
	dma-names = "rx", "tx";
	};
	src9: src-9 {
	interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x97>, <&audma1 0xba>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssiu {
	ssiu00: ssiu-0 {
	dmas = <&audma0 0x15>, <&audma1 0x16>;
	dma-names = "rx", "tx";
	};
	ssiu01: ssiu-1 {
	dmas = <&audma0 0x35>, <&audma1 0x36>;
	dma-names = "rx", "tx";
	};
	ssiu02: ssiu-2 {
	dmas = <&audma0 0x37>, <&audma1 0x38>;
	dma-names = "rx", "tx";
	};
	ssiu03: ssiu-3 {
	dmas = <&audma0 0x47>, <&audma1 0x48>;
	dma-names = "rx", "tx";
	};
	ssiu04: ssiu-4 {
	dmas = <&audma0 0x3F>, <&audma1 0x40>;
	dma-names = "rx", "tx";
	};
	ssiu05: ssiu-5 {
	dmas = <&audma0 0x43>, <&audma1 0x44>;
	dma-names = "rx", "tx";
	};
	ssiu06: ssiu-6 {
	dmas = <&audma0 0x4F>, <&audma1 0x50>;
	dma-names = "rx", "tx";
	};
	ssiu07: ssiu-7 {
	dmas = <&audma0 0x53>, <&audma1 0x54>;
	dma-names = "rx", "tx";
	};
	ssiu10: ssiu-8 {
	dmas = <&audma0 0x49>, <&audma1 0x4a>;
	dma-names = "rx", "tx";
	};
	ssiu11: ssiu-9 {
	dmas = <&audma0 0x4B>, <&audma1 0x4C>;
	dma-names = "rx", "tx";
	};
	ssiu12: ssiu-10 {
	dmas = <&audma0 0x57>, <&audma1 0x58>;
	dma-names = "rx", "tx";
	};
	ssiu13: ssiu-11 {
	dmas = <&audma0 0x59>, <&audma1 0x5A>;
	dma-names = "rx", "tx";
	};
	ssiu14: ssiu-12 {
	dmas = <&audma0 0x5F>, <&audma1 0x60>;
	dma-names = "rx", "tx";
	};
	ssiu15: ssiu-13 {
	dmas = <&audma0 0xC3>, <&audma1 0xC4>;
	dma-names = "rx", "tx";
	};
	ssiu16: ssiu-14 {
	dmas = <&audma0 0xC7>, <&audma1 0xC8>;
	dma-names = "rx", "tx";
	};
	ssiu17: ssiu-15 {
	dmas = <&audma0 0xCB>, <&audma1 0xCC>;
	dma-names = "rx", "tx";
	};
	ssiu20: ssiu-16 {
	dmas = <&audma0 0x63>, <&audma1 0x64>;
	dma-names = "rx", "tx";
	};
	ssiu21: ssiu-17 {
	dmas = <&audma0 0x67>, <&audma1 0x68>;
	dma-names = "rx", "tx";
	};
	ssiu22: ssiu-18 {
	dmas = <&audma0 0x6B>, <&audma1 0x6C>;
	dma-names = "rx", "tx";
	};
	ssiu23: ssiu-19 {
	dmas = <&audma0 0x6D>, <&audma1 0x6E>;
	dma-names = "rx", "tx";
	};
	ssiu24: ssiu-20 {
	dmas = <&audma0 0xCF>, <&audma1 0xCE>;
	dma-names = "rx", "tx";
	};
	ssiu25: ssiu-21 {
	dmas = <&audma0 0xEB>, <&audma1 0xEC>;
	dma-names = "rx", "tx";
	};
	ssiu26: ssiu-22 {
	dmas = <&audma0 0xED>, <&audma1 0xEE>;
	dma-names = "rx", "tx";
	};
	ssiu27: ssiu-23 {
	dmas = <&audma0 0xEF>, <&audma1 0xF0>;
	dma-names = "rx", "tx";
	};
	ssiu30: ssiu-24 {
	dmas = <&audma0 0x6f>, <&audma1 0x70>;
	dma-names = "rx", "tx";
	};
	ssiu31: ssiu-25 {
	dmas = <&audma0 0x21>, <&audma1 0x22>;
	dma-names = "rx", "tx";
	};
	ssiu32: ssiu-26 {
	dmas = <&audma0 0x23>, <&audma1 0x24>;
	dma-names = "rx", "tx";
	};
	ssiu33: ssiu-27 {
	dmas = <&audma0 0x25>, <&audma1 0x26>;
	dma-names = "rx", "tx";
	};
	ssiu34: ssiu-28 {
	dmas = <&audma0 0x27>, <&audma1 0x28>;
	dma-names = "rx", "tx";
	};
	ssiu35: ssiu-29 {
	dmas = <&audma0 0x29>, <&audma1 0x2A>;
	dma-names = "rx", "tx";
	};
	ssiu36: ssiu-30 {
	dmas = <&audma0 0x2B>, <&audma1 0x2C>;
	dma-names = "rx", "tx";
	};
	ssiu37: ssiu-31 {
	dmas = <&audma0 0x2D>, <&audma1 0x2E>;
	dma-names = "rx", "tx";
	};
	ssiu40: ssiu-32 {
	dmas = <&audma0 0x71>, <&audma1 0x72>;
	dma-names = "rx", "tx";
	};
	ssiu41: ssiu-33 {
	dmas = <&audma0 0x17>, <&audma1 0x18>;
	dma-names = "rx", "tx";
	};
	ssiu42: ssiu-34 {
	dmas = <&audma0 0x19>, <&audma1 0x1A>;
	dma-names = "rx", "tx";
	};
	ssiu43: ssiu-35 {
	dmas = <&audma0 0x1B>, <&audma1 0x1C>;
	dma-names = "rx", "tx";
	};
	ssiu44: ssiu-36 {
	dmas = <&audma0 0x1D>, <&audma1 0x1E>;
	dma-names = "rx", "tx";
	};
	ssiu45: ssiu-37 {
	dmas = <&audma0 0x1F>, <&audma1 0x20>;
	dma-names = "rx", "tx";
	};
	ssiu46: ssiu-38 {
	dmas = <&audma0 0x31>, <&audma1 0x32>;
	dma-names = "rx", "tx";
	};
	ssiu47: ssiu-39 {
	dmas = <&audma0 0x33>, <&audma1 0x34>;
	dma-names = "rx", "tx";
	};
	ssiu50: ssiu-40 {
	dmas = <&audma0 0x73>, <&audma1 0x74>;
	dma-names = "rx", "tx";
	};
	ssiu60: ssiu-41 {
	dmas = <&audma0 0x75>, <&audma1 0x76>;
	dma-names = "rx", "tx";
	};
	ssiu70: ssiu-42 {
	dmas = <&audma0 0x79>, <&audma1 0x7a>;
	dma-names = "rx", "tx";
	};
	ssiu80: ssiu-43 {
	dmas = <&audma0 0x7b>, <&audma1 0x7c>;
	dma-names = "rx", "tx";
	};
	ssiu90: ssiu-44 {
	dmas = <&audma0 0x7d>, <&audma1 0x7e>;
	dma-names = "rx", "tx";
	};
	ssiu91: ssiu-45 {
	dmas = <&audma0 0x7F>, <&audma1 0x80>;
	dma-names = "rx", "tx";
	};
	ssiu92: ssiu-46 {
	dmas = <&audma0 0x81>, <&audma1 0x82>;
	dma-names = "rx", "tx";
	};
	ssiu93: ssiu-47 {
	dmas = <&audma0 0x83>, <&audma1 0x84>;
	dma-names = "rx", "tx";
	};
	ssiu94: ssiu-48 {
	dmas = <&audma0 0xA3>, <&audma1 0xA4>;
	dma-names = "rx", "tx";
	};
	ssiu95: ssiu-49 {
	dmas = <&audma0 0xA5>, <&audma1 0xA6>;
	dma-names = "rx", "tx";
	};
	ssiu96: ssiu-50 {
	dmas = <&audma0 0xA7>, <&audma1 0xA8>;
	dma-names = "rx", "tx";
	};
	ssiu97: ssiu-51 {
	dmas = <&audma0 0xA9>, <&audma1 0xAA>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssi {
	ssi0: ssi-0 {
	interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x01>, <&audma1 0x02>;
	dma-names = "rx", "tx";
	};
	ssi1: ssi-1 {
	interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x03>, <&audma1 0x04>;
	dma-names = "rx", "tx";
	};
	ssi2: ssi-2 {
	interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x05>, <&audma1 0x06>;
	dma-names = "rx", "tx";
	};
	ssi3: ssi-3 {
	interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x07>, <&audma1 0x08>;
	dma-names = "rx", "tx";
	};
	ssi4: ssi-4 {
	interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x09>, <&audma1 0x0a>;
	dma-names = "rx", "tx";
	};
	ssi5: ssi-5 {
	interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0b>, <&audma1 0x0c>;
	dma-names = "rx", "tx";
	};
	ssi6: ssi-6 {
	interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0d>, <&audma1 0x0e>;
	dma-names = "rx", "tx";
	};
	ssi7: ssi-7 {
	interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0f>, <&audma1 0x10>;
	dma-names = "rx", "tx";
	};
	ssi8: ssi-8 {
	interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x11>, <&audma1 0x12>;
	dma-names = "rx", "tx";
	};
	ssi9: ssi-9 {
	interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x13>, <&audma1 0x14>;
	dma-names = "rx", "tx";
	};
	};
	};

	audma0: dma-controller@ec700000 {
	compatible = "renesas,dmac-r8a77965",
	"renesas,rcar-dmac";
	reg = <0 0xec700000 0 0x10000>;
	interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 502>;
	clock-names = "fck";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 502>;
	#dma-cells = <1>;
	dma-channels = <16>;
	};

	audma1: dma-controller@ec720000 {
	compatible = "renesas,dmac-r8a77965",
	"renesas,rcar-dmac";
	reg = <0 0xec720000 0 0x10000>;
	interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 501>;
	clock-names = "fck";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 501>;
	#dma-cells = <1>;
	dma-channels = <16>;
	};

	xhci0: usb@ee000000 {
	compatible = "renesas,xhci-r8a77965",
	"renesas,rcar-gen3-xhci";
	reg = <0 0xee000000 0 0xc00>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	status = "disabled";
	};

	usb3_peri0: usb@ee020000 {
	compatible = "renesas,r8a77965-usb3-peri",
	"renesas,rcar-gen3-usb3-peri";
	reg = <0 0xee020000 0 0x400>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	status = "disabled";
	};

	ohci0: usb@ee080000 {
	compatible = "generic-ohci";
	reg = <0 0xee080000 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	phys = <&usb2_phy0 1>;
	phy-names = "usb";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	status = "disabled";
	};

	ohci1: usb@ee0a0000 {
	compatible = "generic-ohci";
	reg = <0 0xee0a0000 0 0x100>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 702>;
	phys = <&usb2_phy1 1>;
	phy-names = "usb";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 702>;
	status = "disabled";
	};

	ehci0: usb@ee080100 {
	compatible = "generic-ehci";
	reg = <0 0xee080100 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	phys = <&usb2_phy0 2>;
	phy-names = "usb";
	companion = <&ohci0>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	status = "disabled";
	};

	ehci1: usb@ee0a0100 {
	compatible = "generic-ehci";
	reg = <0 0xee0a0100 0 0x100>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 702>;
	phys = <&usb2_phy1 2>;
	phy-names = "usb";
	companion = <&ohci1>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 702>;
	status = "disabled";
	};

	usb2_phy0: usb-phy@ee080200 {
	compatible = "renesas,usb2-phy-r8a77965",
	"renesas,rcar-gen3-usb2-phy";
	reg = <0 0xee080200 0 0x700>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	#phy-cells = <1>;
	status = "disabled";
	};

	usb2_phy1: usb-phy@ee0a0200 {
	compatible = "renesas,usb2-phy-r8a77965",
	"renesas,rcar-gen3-usb2-phy";
	reg = <0 0xee0a0200 0 0x700>;
	clocks = <&cpg CPG_MOD 702>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 702>;
	#phy-cells = <1>;
	status = "disabled";
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a77965",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee100000 0 0x2000>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	iommus = <&ipmmu_ds1 32>;
	status = "disabled";
	};

	sdhi1: sd@ee120000 {
	compatible = "renesas,sdhi-r8a77965",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee120000 0 0x2000>;
	interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 313>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 313>;
	iommus = <&ipmmu_ds1 33>;
	status = "disabled";
	};

	sdhi2: sd@ee140000 {
	compatible = "renesas,sdhi-r8a77965",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee140000 0 0x2000>;
	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 312>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 312>;
	iommus = <&ipmmu_ds1 34>;
	status = "disabled";
	};

	sdhi3: sd@ee160000 {
	compatible = "renesas,sdhi-r8a77965",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee160000 0 0x2000>;
	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 311>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 311>;
	iommus = <&ipmmu_ds1 35>;
	status = "disabled";
	};

	sata: sata@ee300000 {
	compatible = "renesas,sata-r8a77965",
	"renesas,rcar-gen3-sata";
	reg = <0 0xee300000 0 0x200000>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 815>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 815>;
	status = "disabled";
	};

	gic: interrupt-controller@f1010000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x0 0xf1010000 0 0x1000>,
	<0x0 0xf1020000 0 0x20000>,
	<0x0 0xf1040000 0 0x20000>,
	<0x0 0xf1060000 0 0x20000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	pciec0: pcie@fe000000 {
	compatible = "renesas,pcie-r8a77965",
	"renesas,pcie-rcar-gen3";
	reg = <0 0xfe000000 0 0x80000>;
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x00 0xff>;
	device_type = "pci";
	ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
	<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
	<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
	<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
	/* Map all possible DDR as inbound ranges */
	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
	clock-names = "pcie", "pcie_bus";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 319>;
	status = "disabled";
	};

	pciec1: pcie@ee800000 {
	compatible = "renesas,pcie-r8a77965",
	"renesas,pcie-rcar-gen3";
	reg = <0 0xee800000 0 0x80000>;
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x00 0xff>;
	device_type = "pci";
	ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
	<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
	<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
	<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
	/* Map all possible DDR as inbound ranges */
	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
	clock-names = "pcie", "pcie_bus";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 318>;
	status = "disabled";
	};

	fdp1@fe940000 {
	compatible = "renesas,fdp1";
	reg = <0 0xfe940000 0 0x2400>;
	interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 119>;
	power-domains = <&sysc R8A77965_PD_A3VP>;
	resets = <&cpg 119>;
	renesas,fcp = <&fcpf0>;
	};

	fcpf0: fcp@fe950000 {
	compatible = "renesas,fcpf";
	reg = <0 0xfe950000 0 0x200>;
	clocks = <&cpg CPG_MOD 615>;
	power-domains = <&sysc R8A77965_PD_A3VP>;
	resets = <&cpg 615>;
	};

	vspb: vsp@fe960000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe960000 0 0x8000>;
	interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 626>;
	power-domains = <&sysc R8A77965_PD_A3VP>;
	resets = <&cpg 626>;

	renesas,fcp = <&fcpvb0>;
	};

	vspi0: vsp@fe9a0000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe9a0000 0 0x8000>;
	interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 631>;
	power-domains = <&sysc R8A77965_PD_A3VP>;
	resets = <&cpg 631>;

	renesas,fcp = <&fcpvi0>;
	};

	vspd0: vsp@fea20000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea20000 0 0x5000>;
	interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 623>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 623>;

	renesas,fcp = <&fcpvd0>;
	};

	vspd1: vsp@fea28000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea28000 0 0x5000>;
	interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 622>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 622>;

	renesas,fcp = <&fcpvd1>;
	};

	fcpvb0: fcp@fe96f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe96f000 0 0x200>;
	clocks = <&cpg CPG_MOD 607>;
	power-domains = <&sysc R8A77965_PD_A3VP>;
	resets = <&cpg 607>;
	};

	fcpvd0: fcp@fea27000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea27000 0 0x200>;
	clocks = <&cpg CPG_MOD 603>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 603>;
	};

	fcpvd1: fcp@fea2f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea2f000 0 0x200>;
	clocks = <&cpg CPG_MOD 602>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 602>;
	};

	fcpvi0: fcp@fe9af000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe9af000 0 0x200>;
	clocks = <&cpg CPG_MOD 611>;
	power-domains = <&sysc R8A77965_PD_A3VP>;
	resets = <&cpg 611>;
	};

	cmm0: cmm@fea40000 {
	compatible = "renesas,r8a77965-cmm",
	"renesas,rcar-gen3-cmm";
	reg = <0 0xfea40000 0 0x1000>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	clocks = <&cpg CPG_MOD 711>;
	resets = <&cpg 711>;
	};

	cmm1: cmm@fea50000 {
	compatible = "renesas,r8a77965-cmm",
	"renesas,rcar-gen3-cmm";
	reg = <0 0xfea50000 0 0x1000>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	clocks = <&cpg CPG_MOD 710>;
	resets = <&cpg 710>;
	};

	cmm3: cmm@fea70000 {
	compatible = "renesas,r8a77965-cmm",
	"renesas,rcar-gen3-cmm";
	reg = <0 0xfea70000 0 0x1000>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	clocks = <&cpg CPG_MOD 708>;
	resets = <&cpg 708>;
	};

	csi20: csi2@fea80000 {
	compatible = "renesas,r8a77965-csi2";
	reg = <0 0xfea80000 0 0x10000>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 714>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 714>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	csi20vin0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vin0csi20>;
	};
	csi20vin1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vin1csi20>;
	};
	csi20vin2: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&vin2csi20>;
	};
	csi20vin3: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&vin3csi20>;
	};
	csi20vin4: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&vin4csi20>;
	};
	csi20vin5: endpoint@5 {
	reg = <5>;
	remote-endpoint = <&vin5csi20>;
	};
	csi20vin6: endpoint@6 {
	reg = <6>;
	remote-endpoint = <&vin6csi20>;
	};
	csi20vin7: endpoint@7 {
	reg = <7>;
	remote-endpoint = <&vin7csi20>;
	};
	};
	};
	};

	csi40: csi2@feaa0000 {
	compatible = "renesas,r8a77965-csi2";
	reg = <0 0xfeaa0000 0 0x10000>;
	interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	csi40vin0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vin0csi40>;
	};
	csi40vin1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vin1csi40>;
	};
	csi40vin2: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&vin2csi40>;
	};
	csi40vin3: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&vin3csi40>;
	};
	csi40vin4: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&vin4csi40>;
	};
	csi40vin5: endpoint@5 {
	reg = <5>;
	remote-endpoint = <&vin5csi40>;
	};
	csi40vin6: endpoint@6 {
	reg = <6>;
	remote-endpoint = <&vin6csi40>;
	};
	csi40vin7: endpoint@7 {
	reg = <7>;
	remote-endpoint = <&vin7csi40>;
	};
	};
	};
	};

	hdmi0: hdmi@fead0000 {
	compatible = "renesas,r8a77965-hdmi",
	"renesas,rcar-gen3-hdmi";
	reg = <0 0xfead0000 0 0x10000>;
	interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 729>,
	<&cpg CPG_CORE R8A77965_CLK_HDMI>;
	clock-names = "iahb", "isfr";
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 729>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;
	port@0 {
	reg = <0>;
	dw_hdmi0_in: endpoint {
	remote-endpoint = <&du_out_hdmi0>;
	};
	};
	port@1 {
	reg = <1>;
	};
	};
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a77965";
	reg = <0 0xfeb00000 0 0x80000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&cpg CPG_MOD 724>,
	- <&cpg CPG_MOD 723>,
	+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
	<&cpg CPG_MOD 721>;
	clock-names = "du.0", "du.1", "du.3";
	+ resets = <&cpg 724>, <&cpg 722>;
	+ reset-names = "du.0", "du.3";

	renesas,cmms = <&cmm0>, <&cmm1>, <&cmm3>;
	- vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
	+ renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;

	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb: endpoint {
	};
	};
	port@1 {
	reg = <1>;
	du_out_hdmi0: endpoint {
	remote-endpoint = <&dw_hdmi0_in>;
	};
	};
	port@2 {
	reg = <2>;
	du_out_lvds0: endpoint {
	remote-endpoint = <&lvds0_in>;
	};
	};
	};
	};

	lvds0: lvds@feb90000 {
	compatible = "renesas,r8a77965-lvds";
	reg = <0 0xfeb90000 0 0x14>;
	clocks = <&cpg CPG_MOD 727>;
	power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
	resets = <&cpg 727>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds0_in: endpoint {
	remote-endpoint = <&du_out_lvds0>;
	};
	};
	port@1 {
	reg = <1>;
	lvds0_out: endpoint {
	};
	};
	};
	};

	prr: chipid@fff00044 {
	compatible = "renesas,prr";
	reg = <0 0xfff00044 0 4>;
	};
	};

	thermal-zones {
	sensor_thermal1: sensor-thermal1 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&tsc 0>;
	sustainable-power = <2439>;

	trips {
	sensor1_crit: sensor1-crit {
	temperature = <120000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};
	};

	sensor_thermal2: sensor-thermal2 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&tsc 1>;
	sustainable-power = <2439>;

	trips {
	sensor2_crit: sensor2-crit {
	temperature = <120000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};
	};

	sensor_thermal3: sensor-thermal3 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&tsc 2>;
	sustainable-power = <2439>;

	trips {
	target: trip-point1 {
	/* miliCelsius */
	temperature = <100000>;
	hysteresis = <1000>;
	type = "passive";
	};

	sensor3_crit: sensor3-crit {
	temperature = <120000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&target>;
	cooling-device = <&a57_0 2 4>;
	contribution = <1024>;
	};
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clocks - can be overridden by the board */
	usb3s0_clk: usb3s0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	usb_extal_clk: usb_extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a77970-eagle.dts b/sys/gnu/dts/arm64/renesas/r8a77970-eagle.dts
	index 2afb91ec9c8d..ac2156ab3e62 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a77970-eagle.dts
	+++ b/sys/gnu/dts/arm64/renesas/r8a77970-eagle.dts
	@@ -1,208 +1,206 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the Eagle board
	*
	* Copyright (C) 2016-2017 Renesas Electronics Corp.
	* Copyright (C) 2017 Cogent Embedded, Inc.
	*/

	/dts-v1/;
	#include "r8a77970.dtsi"

	/ {
	model = "Renesas Eagle board based on r8a77970";
	compatible = "renesas,eagle", "renesas,r8a77970";

	aliases {
	serial0 = &scif0;
	ethernet0 = &avb;
	};

	chosen {
	bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
	stdout-path = "serial0:115200n8";
	};

	d3p3: regulator-fixed {
	compatible = "regulator-fixed";
	regulator-name = "fixed-3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	hdmi-out {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con_out: endpoint {
	remote-endpoint = <&adv7511_out>;
	};
	};
	};

	lvds-decoder {
	compatible = "thine,thc63lvd1024";

	vcc-supply = <&d3p3>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	thc63lvd1024_in: endpoint {
	remote-endpoint = <&lvds0_out>;
	};
	};

	port@2 {
	reg = <2>;
	thc63lvd1024_out: endpoint {
	remote-endpoint = <&adv7511_in>;
	};
	};
	};
	};

	memory@48000000 {
	device_type = "memory";
	/* first 128MB is reserved for secure area. */
	reg = <0x0 0x48000000 0x0 0x38000000>;
	};
	};

	&avb {
	pinctrl-0 = <&avb_pins>;
	pinctrl-names = "default";

	renesas,no-ether-link;
	phy-handle = <&phy0>;
	phy-mode = "rgmii-id";
	status = "okay";

	phy0: ethernet-phy@0 {
	rxc-skew-ps = <1500>;
	reg = <0>;
	interrupt-parent = <&gpio1>;
	interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
	};
	};

	&canfd {
	pinctrl-0 = <&canfd0_pins>;
	pinctrl-names = "default";
	status = "okay";

	channel0 {
	status = "okay";
	};
	};

	&du {
	status = "okay";
	};

	&extal_clk {
	clock-frequency = <16666666>;
	};

	&extalr_clk {
	clock-frequency = <32768>;
	};

	&i2c0 {
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "default";

	status = "okay";
	clock-frequency = <400000>;

	io_expander: gpio@20 {
	compatible = "onnn,pca9654";
	reg = <0x20>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	hdmi@39 {
	compatible = "adi,adv7511w";
	reg = <0x39>;
	interrupt-parent = <&gpio1>;
	interrupts = <20 IRQ_TYPE_LEVEL_LOW>;

	adi,input-depth = <8>;
	adi,input-colorspace = "rgb";
	adi,input-clock = "1x";
	- adi,input-style = <1>;
	- adi,input-justification = "evenly";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7511_in: endpoint {
	remote-endpoint = <&thc63lvd1024_out>;
	};
	};

	port@1 {
	reg = <1>;
	adv7511_out: endpoint {
	remote-endpoint = <&hdmi_con_out>;
	};
	};
	};
	};
	};

	&lvds0 {
	status = "okay";

	ports {
	port@1 {
	lvds0_out: endpoint {
	remote-endpoint = <&thc63lvd1024_in>;
	};
	};
	};
	};

	&pfc {
	avb_pins: avb0 {
	groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
	function = "avb0";
	};

	canfd0_pins: canfd0 {
	groups = "canfd0_data_a";
	function = "canfd0";
	};

	i2c0_pins: i2c0 {
	groups = "i2c0";
	function = "i2c0";
	};

	scif0_pins: scif0 {
	groups = "scif0_data";
	function = "scif0";
	};
	};

	&rwdt {
	timeout-sec = <60>;
	status = "okay";
	};

	&scif0 {
	pinctrl-0 = <&scif0_pins>;
	pinctrl-names = "default";

	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a77970-v3msk.dts b/sys/gnu/dts/arm64/renesas/r8a77970-v3msk.dts
	index d7c7b9156e08..01c4ba0f7be1 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a77970-v3msk.dts
	+++ b/sys/gnu/dts/arm64/renesas/r8a77970-v3msk.dts
	@@ -1,228 +1,226 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the V3M Starter Kit board
	*
	* Copyright (C) 2017 Renesas Electronics Corp.
	* Copyright (C) 2017 Cogent Embedded, Inc.
	*/

	/dts-v1/;
	#include "r8a77970.dtsi"

	/ {
	model = "Renesas V3M Starter Kit board";
	compatible = "renesas,v3msk", "renesas,r8a77970";

	aliases {
	serial0 = &scif0;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	hdmi-out {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con: endpoint {
	remote-endpoint = <&adv7511_out>;
	};
	};
	};

	lvds-decoder {
	compatible = "thine,thc63lvd1024";
	vcc-supply = <&vcc_d3_3v>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	thc63lvd1024_in: endpoint {
	remote-endpoint = <&lvds0_out>;
	};
	};

	port@2 {
	reg = <2>;
	thc63lvd1024_out: endpoint {
	remote-endpoint = <&adv7511_in>;
	};
	};
	};
	};

	memory@48000000 {
	device_type = "memory";
	/* first 128MB is reserved for secure area. */
	reg = <0x0 0x48000000 0x0 0x38000000>;
	};

	osc5_clk: osc5-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <148500000>;
	};

	vcc_d1_8v: regulator-0 {
	compatible = "regulator-fixed";
	regulator-name = "VCC_D1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vcc_d3_3v: regulator-1 {
	compatible = "regulator-fixed";
	regulator-name = "VCC_D3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vcc_vddq_vin0: regulator-2 {
	compatible = "regulator-fixed";
	regulator-name = "VCC_VDDQ_VIN0";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};

	&avb {
	pinctrl-0 = <&avb_pins>;
	pinctrl-names = "default";

	renesas,no-ether-link;
	phy-handle = <&phy0>;
	phy-mode = "rgmii-id";
	status = "okay";

	phy0: ethernet-phy@0 {
	rxc-skew-ps = <1500>;
	reg = <0>;
	interrupt-parent = <&gpio1>;
	interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
	};
	};

	&du {
	clocks = <&cpg CPG_MOD 724>,
	<&osc5_clk>;
	clock-names = "du.0", "dclkin.0";
	status = "okay";
	};

	&extal_clk {
	clock-frequency = <16666666>;
	};

	&extalr_clk {
	clock-frequency = <32768>;
	};

	&i2c0 {
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "default";

	status = "okay";
	clock-frequency = <400000>;

	hdmi@39{
	compatible = "adi,adv7511w";
	#sound-dai-cells = <0>;
	reg = <0x39>;
	interrupt-parent = <&gpio1>;
	interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
	avdd-supply = <&vcc_d1_8v>;
	dvdd-supply = <&vcc_d1_8v>;
	pvdd-supply = <&vcc_d1_8v>;
	bgvdd-supply = <&vcc_d1_8v>;
	dvdd-3v-supply = <&vcc_d3_3v>;

	adi,input-depth = <8>;
	adi,input-colorspace = "rgb";
	adi,input-clock = "1x";
	- adi,input-style = <1>;
	- adi,input-justification = "evenly";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7511_in: endpoint {
	remote-endpoint = <&thc63lvd1024_out>;
	};
	};

	port@1 {
	reg = <1>;
	adv7511_out: endpoint {
	remote-endpoint = <&hdmi_con>;
	};
	};
	};
	};
	};

	&lvds0 {
	status = "okay";

	ports {
	port@1 {
	lvds0_out: endpoint {
	remote-endpoint = <&thc63lvd1024_in>;
	};
	};
	};
	};

	&mmc0 {
	pinctrl-0 = <&mmc_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&vcc_d3_3v>;
	vqmmc-supply = <&vcc_vddq_vin0>;
	bus-width = <8>;
	non-removable;
	status = "okay";
	};

	&pfc {
	avb_pins: avb0 {
	groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
	function = "avb0";
	};

	i2c0_pins: i2c0 {
	groups = "i2c0";
	function = "i2c0";
	};

	mmc_pins: mmc_3_3v {
	groups = "mmc_data8", "mmc_ctrl";
	function = "mmc";
	power-source = <3300>;
	};

	scif0_pins: scif0 {
	groups = "scif0_data";
	function = "scif0";
	};
	};

	&scif0 {
	pinctrl-0 = <&scif0_pins>;
	pinctrl-names = "default";

	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a77970.dtsi b/sys/gnu/dts/arm64/renesas/r8a77970.dtsi
	index 664a73a2cc69..a009c0ebc8b4 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a77970.dtsi
	+++ b/sys/gnu/dts/arm64/renesas/r8a77970.dtsi
	@@ -1,1205 +1,1207 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the R-Car V3M (R8A77970) SoC
	*
	* Copyright (C) 2016-2017 Renesas Electronics Corp.
	* Copyright (C) 2017 Cogent Embedded, Inc.
	*/

	#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/power/r8a77970-sysc.h>

	/ {
	compatible = "renesas,r8a77970";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	};

	/* External CAN clock - to be overridden by boards that provide it */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	a53_0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0>;
	clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
	power-domains = <&sysc R8A77970_PD_CA53_CPU0>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	};

	a53_1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <1>;
	clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
	power-domains = <&sysc R8A77970_PD_CA53_CPU1>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	};

	L2_CA53: cache-controller {
	compatible = "cache";
	power-domains = <&sysc R8A77970_PD_CA53_SCU>;
	cache-unified;
	cache-level = <2>;
	};
	};

	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	extalr_clk: extalr {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	pmu_a53 {
	compatible = "arm,cortex-a53-pmu";
	interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&a53_0>, <&a53_1>;
	};

	psci {
	compatible = "arm,psci-1.0", "arm,psci-0.2";
	method = "smc";
	};

	/* External SCIF clock - to be overridden by boards that provide it */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;

	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a77970-wdt",
	"renesas,rcar-gen3-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a77970",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 22>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a77970",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 28>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a77970",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 17>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a77970",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 17>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a77970",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 6>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a77970",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 15>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a77970";
	reg = <0 0xe6060000 0 0x504>;
	};

	cmt0: timer@e60f0000 {
	compatible = "renesas,r8a77970-cmt0",
	"renesas,rcar-gen3-cmt0";
	reg = <0 0xe60f0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 303>;
	clock-names = "fck";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 303>;
	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a77970-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 302>;
	clock-names = "fck";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 302>;
	status = "disabled";
	};

	cmt2: timer@e6140000 {
	compatible = "renesas,r8a77970-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6140000 0 0x1004>;
	interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 301>;
	clock-names = "fck";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 301>;
	status = "disabled";
	};

	cmt3: timer@e6148000 {
	compatible = "renesas,r8a77970-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6148000 0 0x1004>;
	interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 300>;
	clock-names = "fck";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 300>;
	status = "disabled";
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a77970-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>, <&extalr_clk>;
	clock-names = "extal", "extalr";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a77970-rst";
	reg = <0 0xe6160000 0 0x200>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a77970-sysc";
	reg = <0 0xe6180000 0 0x440>;
	#power-domain-cells = <1>;
	};

	thermal: thermal@e6190000 {
	compatible = "renesas,thermal-r8a77970";
	reg = <0 0xe6190000 0 0x10>,
	<0 0xe6190100 0 0x120>;
	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 522>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 522>;
	#thermal-sensor-cells = <0>;
	};

	intc_ex: interrupt-controller@e61c0000 {
	compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	tmu0: timer@e61e0000 {
	compatible = "renesas,tmu-r8a77970", "renesas,tmu";
	reg = <0 0xe61e0000 0 0x30>;
	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 125>;
	clock-names = "fck";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 125>;
	status = "disabled";
	};

	tmu1: timer@e6fc0000 {
	compatible = "renesas,tmu-r8a77970", "renesas,tmu";
	reg = <0 0xe6fc0000 0 0x30>;
	interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 124>;
	clock-names = "fck";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 124>;
	status = "disabled";
	};

	tmu2: timer@e6fd0000 {
	compatible = "renesas,tmu-r8a77970", "renesas,tmu";
	reg = <0 0xe6fd0000 0 0x30>;
	interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 123>;
	clock-names = "fck";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 123>;
	status = "disabled";
	};

	tmu3: timer@e6fe0000 {
	compatible = "renesas,tmu-r8a77970", "renesas,tmu";
	reg = <0 0xe6fe0000 0 0x30>;
	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 122>;
	clock-names = "fck";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 122>;
	status = "disabled";
	};

	tmu4: timer@ffc00000 {
	compatible = "renesas,tmu-r8a77970", "renesas,tmu";
	reg = <0 0xffc00000 0 0x30>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 121>;
	clock-names = "fck";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 121>;
	status = "disabled";
	};

	i2c0: i2c@e6500000 {
	compatible = "renesas,i2c-r8a77970",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6500000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	dmas = <&dmac1 0x91>, <&dmac1 0x90>,
	<&dmac2 0x91>, <&dmac2 0x90>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c1: i2c@e6508000 {
	compatible = "renesas,i2c-r8a77970",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	dmas = <&dmac1 0x93>, <&dmac1 0x92>,
	<&dmac2 0x93>, <&dmac2 0x92>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c2: i2c@e6510000 {
	compatible = "renesas,i2c-r8a77970",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6510000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	dmas = <&dmac1 0x95>, <&dmac1 0x94>,
	<&dmac2 0x95>, <&dmac2 0x94>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c3: i2c@e66d0000 {
	compatible = "renesas,i2c-r8a77970",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d0000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	dmas = <&dmac1 0x97>, <&dmac1 0x96>,
	<&dmac2 0x97>, <&dmac2 0x96>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c4: i2c@e66d8000 {
	compatible = "renesas,i2c-r8a77970",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d8000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	dmas = <&dmac1 0x99>, <&dmac1 0x98>,
	<&dmac2 0x99>, <&dmac2 0x98>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	hscif0: serial@e6540000 {
	compatible = "renesas,hscif-r8a77970",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6540000 0 96>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 520>,
	<&cpg CPG_CORE R8A77970_CLK_S2D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x31>, <&dmac1 0x30>,
	<&dmac2 0x31>, <&dmac2 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 520>;
	status = "disabled";
	};

	hscif1: serial@e6550000 {
	compatible = "renesas,hscif-r8a77970",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6550000 0 96>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 519>,
	<&cpg CPG_CORE R8A77970_CLK_S2D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x33>, <&dmac1 0x32>,
	<&dmac2 0x33>, <&dmac2 0x32>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 519>;
	status = "disabled";
	};

	hscif2: serial@e6560000 {
	compatible = "renesas,hscif-r8a77970",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6560000 0 96>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 518>,
	<&cpg CPG_CORE R8A77970_CLK_S2D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x35>, <&dmac1 0x34>,
	<&dmac2 0x35>, <&dmac2 0x34>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 518>;
	status = "disabled";
	};

	hscif3: serial@e66a0000 {
	compatible = "renesas,hscif-r8a77970",
	"renesas,rcar-gen3-hscif", "renesas,hscif";
	reg = <0 0xe66a0000 0 96>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 517>,
	<&cpg CPG_CORE R8A77970_CLK_S2D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x37>, <&dmac1 0x36>,
	<&dmac2 0x37>, <&dmac2 0x36>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 517>;
	status = "disabled";
	};

	canfd: can@e66c0000 {
	compatible = "renesas,r8a77970-canfd",
	"renesas,rcar-gen3-canfd";
	reg = <0 0xe66c0000 0 0x8000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 914>,
	<&cpg CPG_CORE R8A77970_CLK_CANFD>,
	<&can_clk>;
	clock-names = "fck", "canfd", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 914>;
	status = "disabled";

	channel0 {
	status = "disabled";
	};

	channel1 {
	status = "disabled";
	};
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a77970",
	"renesas,etheravb-rcar-gen3";
	reg = <0 0xe6800000 0 0x800>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15",
	"ch16", "ch17", "ch18", "ch19",
	"ch20", "ch21", "ch22", "ch23",
	"ch24";
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	phy-mode = "rgmii";
	iommus = <&ipmmu_rt 3>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	pwm0: pwm@e6e30000 {
	compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
	reg = <0 0xe6e30000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	status = "disabled";
	};

	pwm1: pwm@e6e31000 {
	compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
	reg = <0 0xe6e31000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	status = "disabled";
	};

	pwm2: pwm@e6e32000 {
	compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
	reg = <0 0xe6e32000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	status = "disabled";
	};

	pwm3: pwm@e6e33000 {
	compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
	reg = <0 0xe6e33000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	status = "disabled";
	};

	pwm4: pwm@e6e34000 {
	compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
	reg = <0 0xe6e34000 0 8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a77970",
	"renesas,rcar-gen3-scif",
	"renesas,scif";
	reg = <0 0xe6e60000 0 64>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 207>,
	<&cpg CPG_CORE R8A77970_CLK_S2D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x51>, <&dmac1 0x50>,
	<&dmac2 0x51>, <&dmac2 0x50>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 207>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a77970",
	"renesas,rcar-gen3-scif",
	"renesas,scif";
	reg = <0 0xe6e68000 0 64>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 206>,
	<&cpg CPG_CORE R8A77970_CLK_S2D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x53>, <&dmac1 0x52>,
	<&dmac2 0x53>, <&dmac2 0x52>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 206>;
	status = "disabled";
	};

	scif3: serial@e6c50000 {
	compatible = "renesas,scif-r8a77970",
	"renesas,rcar-gen3-scif",
	"renesas,scif";
	reg = <0 0xe6c50000 0 64>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 204>,
	<&cpg CPG_CORE R8A77970_CLK_S2D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x57>, <&dmac1 0x56>,
	<&dmac2 0x57>, <&dmac2 0x56>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 204>;
	status = "disabled";
	};

	scif4: serial@e6c40000 {
	compatible = "renesas,scif-r8a77970",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6c40000 0 64>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 203>,
	<&cpg CPG_CORE R8A77970_CLK_S2D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x59>, <&dmac1 0x58>,
	<&dmac2 0x59>, <&dmac2 0x58>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 203>;
	status = "disabled";
	};

	tpu: pwm@e6e80000 {
	compatible = "renesas,tpu-r8a77970", "renesas,tpu";
	reg = <0 0xe6e80000 0 0x148>;
	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 304>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 304>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	msiof0: spi@e6e90000 {
	compatible = "renesas,msiof-r8a77970",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6e90000 0 0x64>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 211>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 211>;
	dmas = <&dmac1 0x41>, <&dmac1 0x40>,
	<&dmac2 0x41>, <&dmac2 0x40>;
	dma-names = "tx", "rx", "tx", "rx";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof1: spi@e6ea0000 {
	compatible = "renesas,msiof-r8a77970",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6ea0000 0 0x0064>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 210>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 210>;
	dmas = <&dmac1 0x43>, <&dmac1 0x42>,
	<&dmac2 0x43>, <&dmac2 0x42>;
	dma-names = "tx", "rx", "tx", "rx";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof2: spi@e6c00000 {
	compatible = "renesas,msiof-r8a77970",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c00000 0 0x0064>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 209>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 209>;
	dmas = <&dmac1 0x45>, <&dmac1 0x44>,
	<&dmac2 0x45>, <&dmac2 0x44>;
	dma-names = "tx", "rx", "tx", "rx";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof3: spi@e6c10000 {
	compatible = "renesas,msiof-r8a77970",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c10000 0 0x0064>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 208>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 208>;
	dmas = <&dmac1 0x47>, <&dmac1 0x46>,
	<&dmac2 0x47>, <&dmac2 0x46>;
	dma-names = "tx", "rx", "tx", "rx";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	vin0: video@e6ef0000 {
	compatible = "renesas,vin-r8a77970";
	reg = <0 0xe6ef0000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 811>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 811>;
	renesas,id = <0>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin0csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin0>;
	};
	};
	};
	};

	vin1: video@e6ef1000 {
	compatible = "renesas,vin-r8a77970";
	reg = <0 0xe6ef1000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 810>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 810>;
	renesas,id = <1>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin1csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin1>;
	};
	};
	};
	};

	vin2: video@e6ef2000 {
	compatible = "renesas,vin-r8a77970";
	reg = <0 0xe6ef2000 0 0x1000>;
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 809>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 809>;
	renesas,id = <2>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin2csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin2>;
	};
	};
	};
	};

	vin3: video@e6ef3000 {
	compatible = "renesas,vin-r8a77970";
	reg = <0 0xe6ef3000 0 0x1000>;
	interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 808>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 808>;
	renesas,id = <3>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin3csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin3>;
	};
	};
	};
	};

	dmac1: dma-controller@e7300000 {
	compatible = "renesas,dmac-r8a77970",
	"renesas,rcar-dmac";
	reg = <0 0xe7300000 0 0x10000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <8>;
	iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
	<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
	<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
	<&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
	};

	dmac2: dma-controller@e7310000 {
	compatible = "renesas,dmac-r8a77970",
	"renesas,rcar-dmac";
	reg = <0 0xe7310000 0 0x10000>;
	interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7";
	clocks = <&cpg CPG_MOD 217>;
	clock-names = "fck";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 217>;
	#dma-cells = <1>;
	dma-channels = <8>;
	iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
	<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
	<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
	<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
	};

	ipmmu_ds1: mmu@e7740000 {
	compatible = "renesas,ipmmu-r8a77970";
	reg = <0 0xe7740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 0>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_ir: mmu@ff8b0000 {
	compatible = "renesas,ipmmu-r8a77970";
	reg = <0 0xff8b0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 3>;
	power-domains = <&sysc R8A77970_PD_A3IR>;
	#iommu-cells = <1>;
	};

	ipmmu_mm: mmu@e67b0000 {
	compatible = "renesas,ipmmu-r8a77970";
	reg = <0 0xe67b0000 0 0x1000>;
	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_rt: mmu@ffc80000 {
	compatible = "renesas,ipmmu-r8a77970";
	reg = <0 0xffc80000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 7>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vi0: mmu@febd0000 {
	compatible = "renesas,ipmmu-r8a77970";
	reg = <0 0xfebd0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 9>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	mmc0: mmc@ee140000 {
	compatible = "renesas,sdhi-r8a77970",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee140000 0 0x2000>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	max-frequency = <200000000>;
	iommus = <&ipmmu_ds1 32>;
	status = "disabled";
	};

	gic: interrupt-controller@f1010000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0 0xf1010000 0 0x1000>,
	<0 0xf1020000 0 0x20000>,
	<0 0xf1040000 0 0x20000>,
	<0 0xf1060000 0 0x20000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) \|
	IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	vspd0: vsp@fea20000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea20000 0 0x5000>;
	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 623>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 623>;
	renesas,fcp = <&fcpvd0>;
	};

	fcpvd0: fcp@fea27000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea27000 0 0x200>;
	clocks = <&cpg CPG_MOD 603>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 603>;
	};

	csi40: csi2@feaa0000 {
	compatible = "renesas,r8a77970-csi2";
	reg = <0 0xfeaa0000 0 0x10000>;
	interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	csi40vin0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vin0csi40>;
	};
	csi40vin1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vin1csi40>;
	};
	csi40vin2: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&vin2csi40>;
	};
	csi40vin3: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&vin3csi40>;
	};
	};
	};
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a77970";
	reg = <0 0xfeb00000 0 0x80000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 724>;
	clock-names = "du.0";
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 724>;
	- vsps = <&vspd0 0>;
	+ reset-names = "du.0";
	+ renesas,vsps = <&vspd0 0>;
	+
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb: endpoint {
	};
	};

	port@1 {
	reg = <1>;
	du_out_lvds0: endpoint {
	remote-endpoint = <&lvds0_in>;
	};
	};
	};
	};

	lvds0: lvds-encoder@feb90000 {
	compatible = "renesas,r8a77970-lvds";
	reg = <0 0xfeb90000 0 0x14>;
	clocks = <&cpg CPG_MOD 727>;
	power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
	resets = <&cpg 727>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds0_in: endpoint {
	remote-endpoint =
	<&du_out_lvds0>;
	};
	};
	port@1 {
	reg = <1>;
	lvds0_out: endpoint {
	};
	};
	};
	};

	prr: chipid@fff00044 {
	compatible = "renesas,prr";
	reg = <0 0xfff00044 0 4>;
	};
	};

	thermal-zones {
	cpu-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&thermal>;

	cooling-maps {
	};

	trips {
	cpu-crit {
	temperature = <120000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a77980-condor.dts b/sys/gnu/dts/arm64/renesas/r8a77980-condor.dts
	index 3dde028e22a6..ef8350a062af 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a77980-condor.dts
	+++ b/sys/gnu/dts/arm64/renesas/r8a77980-condor.dts
	@@ -1,292 +1,290 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the Condor board
	*
	* Copyright (C) 2018 Renesas Electronics Corp.
	* Copyright (C) 2018 Cogent Embedded, Inc.
	*/

	/dts-v1/;
	#include "r8a77980.dtsi"

	/ {
	model = "Renesas Condor board based on r8a77980";
	compatible = "renesas,condor", "renesas,r8a77980";

	aliases {
	serial0 = &scif0;
	ethernet0 = &gether;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	d1_8v: regulator-2 {
	compatible = "regulator-fixed";
	regulator-name = "D1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	d3_3v: regulator-0 {
	compatible = "regulator-fixed";
	regulator-name = "D3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	hdmi-out {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con: endpoint {
	remote-endpoint = <&adv7511_out>;
	};
	};
	};

	lvds-decoder {
	compatible = "thine,thc63lvd1024";
	vcc-supply = <&d3_3v>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	thc63lvd1024_in: endpoint {
	remote-endpoint = <&lvds0_out>;
	};
	};

	port@2 {
	reg = <2>;
	thc63lvd1024_out: endpoint {
	remote-endpoint = <&adv7511_in>;
	};
	};
	};
	};

	memory@48000000 {
	device_type = "memory";
	/* first 128MB is reserved for secure area. */
	reg = <0 0x48000000 0 0x78000000>;
	};

	vddq_vin01: regulator-1 {
	compatible = "regulator-fixed";
	regulator-name = "VDDQ_VIN01";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	x1_clk: x1-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <148500000>;
	};
	};

	&canfd {
	pinctrl-0 = <&canfd0_pins>;
	pinctrl-names = "default";
	status = "okay";

	channel0 {
	status = "okay";
	};
	};

	&du {
	clocks = <&cpg CPG_MOD 724>,
	<&x1_clk>;
	clock-names = "du.0", "dclkin.0";
	status = "okay";
	};

	&extal_clk {
	clock-frequency = <16666666>;
	};

	&extalr_clk {
	clock-frequency = <32768>;
	};

	&gether {
	pinctrl-0 = <&gether_pins>;
	pinctrl-names = "default";

	phy-mode = "rgmii-id";
	phy-handle = <&phy0>;
	renesas,no-ether-link;
	status = "okay";

	phy0: ethernet-phy@0 {
	rxc-skew-ps = <1500>;
	reg = <0>;
	interrupt-parent = <&gpio4>;
	interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
	};
	};

	&i2c0 {
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "default";

	status = "okay";
	clock-frequency = <400000>;

	io_expander0: gpio@20 {
	compatible = "onnn,pca9654";
	reg = <0x20>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	io_expander1: gpio@21 {
	compatible = "onnn,pca9654";
	reg = <0x21>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	hdmi@39 {
	compatible = "adi,adv7511w";
	reg = <0x39>;
	interrupt-parent = <&gpio1>;
	interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
	avdd-supply = <&d1_8v>;
	dvdd-supply = <&d1_8v>;
	pvdd-supply = <&d1_8v>;
	bgvdd-supply = <&d1_8v>;
	dvdd-3v-supply = <&d3_3v>;

	adi,input-depth = <8>;
	adi,input-colorspace = "rgb";
	adi,input-clock = "1x";
	- adi,input-style = <1>;
	- adi,input-justification = "evenly";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7511_in: endpoint {
	remote-endpoint = <&thc63lvd1024_out>;
	};
	};

	port@1 {
	reg = <1>;
	adv7511_out: endpoint {
	remote-endpoint = <&hdmi_con>;
	};
	};
	};
	};
	};

	&lvds0 {
	status = "okay";

	ports {
	port@1 {
	lvds0_out: endpoint {
	remote-endpoint = <&thc63lvd1024_in>;
	};
	};
	};
	};

	&mmc0 {
	pinctrl-0 = <&mmc_pins>;
	pinctrl-1 = <&mmc_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&d3_3v>;
	vqmmc-supply = <&vddq_vin01>;
	mmc-hs200-1_8v;
	bus-width = <8>;
	non-removable;
	status = "okay";
	};

	&pciec {
	status = "okay";
	};

	&pcie_bus_clk {
	clock-frequency = <100000000>;
	};

	&pcie_phy {
	status = "okay";
	};

	&pfc {
	canfd0_pins: canfd0 {
	groups = "canfd0_data_a";
	function = "canfd0";
	};

	gether_pins: gether {
	groups = "gether_mdio_a", "gether_rgmii",
	"gether_txcrefclk", "gether_txcrefclk_mega";
	function = "gether";
	};

	i2c0_pins: i2c0 {
	groups = "i2c0";
	function = "i2c0";
	};

	mmc_pins: mmc {
	groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
	function = "mmc";
	power-source = <3300>;
	};

	mmc_pins_uhs: mmc_uhs {
	groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
	function = "mmc";
	power-source = <1800>;
	};

	scif0_pins: scif0 {
	groups = "scif0_data";
	function = "scif0";
	};

	scif_clk_pins: scif_clk {
	groups = "scif_clk_b";
	function = "scif_clk";
	};
	};

	&rwdt {
	timeout-sec = <60>;
	status = "okay";
	};

	&scif0 {
	pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&scif_clk {
	clock-frequency = <14745600>;
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a77980-v3hsk.dts b/sys/gnu/dts/arm64/renesas/r8a77980-v3hsk.dts
	index adbfd8f07d06..6dff04693223 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a77980-v3hsk.dts
	+++ b/sys/gnu/dts/arm64/renesas/r8a77980-v3hsk.dts
	@@ -1,217 +1,215 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the V3H Starter Kit board
	*
	* Copyright (C) 2018 Renesas Electronics Corp.
	* Copyright (C) 2018 Cogent Embedded, Inc.
	*/

	/dts-v1/;
	#include "r8a77980.dtsi"

	/ {
	model = "Renesas V3H Starter Kit board";
	compatible = "renesas,v3hsk", "renesas,r8a77980";

	aliases {
	serial0 = &scif0;
	ethernet0 = &gether;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	hdmi-out {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con: endpoint {
	remote-endpoint = <&adv7511_out>;
	};
	};
	};

	lvds-decoder {
	compatible = "thine,thc63lvd1024";
	vcc-supply = <&vcc3v3_d5>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	thc63lvd1024_in: endpoint {
	remote-endpoint = <&lvds0_out>;
	};
	};

	port@2 {
	reg = <2>;
	thc63lvd1024_out: endpoint {
	remote-endpoint = <&adv7511_in>;
	};
	};
	};
	};

	memory@48000000 {
	device_type = "memory";
	/* first 128MB is reserved for secure area. */
	reg = <0 0x48000000 0 0x78000000>;
	};

	osc1_clk: osc1-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <148500000>;
	};

	vcc1v8_d4: regulator-0 {
	compatible = "regulator-fixed";
	regulator-name = "VCC1V8_D4";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vcc3v3_d5: regulator-1 {
	compatible = "regulator-fixed";
	regulator-name = "VCC3V3_D5";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};
	};

	&du {
	clocks = <&cpg CPG_MOD 724>,
	<&osc1_clk>;
	clock-names = "du.0", "dclkin.0";
	status = "okay";
	};

	&extal_clk {
	clock-frequency = <16666666>;
	};

	&extalr_clk {
	clock-frequency = <32768>;
	};

	&gether {
	pinctrl-0 = <&gether_pins>;
	pinctrl-names = "default";

	phy-mode = "rgmii";
	phy-handle = <&phy0>;
	renesas,no-ether-link;
	status = "okay";

	phy0: ethernet-phy@0 {
	reg = <0>;
	interrupt-parent = <&gpio4>;
	interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
	};
	};

	&i2c0 {
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "default";

	status = "okay";
	clock-frequency = <400000>;

	hdmi@39 {
	compatible = "adi,adv7511w";
	#sound-dai-cells = <0>;
	reg = <0x39>;
	interrupt-parent = <&gpio1>;
	interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
	avdd-supply = <&vcc1v8_d4>;
	dvdd-supply = <&vcc1v8_d4>;
	pvdd-supply = <&vcc1v8_d4>;
	bgvdd-supply = <&vcc1v8_d4>;
	dvdd-3v-supply = <&vcc3v3_d5>;

	adi,input-depth = <8>;
	adi,input-colorspace = "rgb";
	adi,input-clock = "1x";
	- adi,input-style = <1>;
	- adi,input-justification = "evenly";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7511_in: endpoint {
	remote-endpoint = <&thc63lvd1024_out>;
	};
	};

	port@1 {
	reg = <1>;
	adv7511_out: endpoint {
	remote-endpoint = <&hdmi_con>;
	};
	};
	};
	};
	};

	&lvds0 {
	status = "okay";

	ports {
	port@1 {
	lvds0_out: endpoint {
	remote-endpoint = <&thc63lvd1024_in>;
	};
	};
	};
	};

	&pfc {
	gether_pins: gether {
	groups = "gether_mdio_a", "gether_rgmii",
	"gether_txcrefclk", "gether_txcrefclk_mega";
	function = "gether";
	};

	i2c0_pins: i2c0 {
	groups = "i2c0";
	function = "i2c0";
	};

	scif0_pins: scif0 {
	groups = "scif0_data";
	function = "scif0";
	};

	scif_clk_pins: scif_clk {
	groups = "scif_clk_b";
	function = "scif_clk";
	};
	};

	&rwdt {
	timeout-sec = <60>;
	status = "okay";
	};

	&scif0 {
	pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&scif_clk {
	clock-frequency = <14745600>;
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a77980.dtsi b/sys/gnu/dts/arm64/renesas/r8a77980.dtsi
	index b340fb469999..d672b320bc14 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a77980.dtsi
	+++ b/sys/gnu/dts/arm64/renesas/r8a77980.dtsi
	@@ -1,1602 +1,1605 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the R-Car V3H (R8A77980) SoC
	*
	* Copyright (C) 2018 Renesas Electronics Corp.
	* Copyright (C) 2018 Cogent Embedded, Inc.
	*/

	#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/power/r8a77980-sysc.h>

	/ {
	compatible = "renesas,r8a77980";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	};

	/* External CAN clock - to be overridden by boards that provide it */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	a53_0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0>;
	clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
	power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	};

	a53_1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <1>;
	clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
	power-domains = <&sysc R8A77980_PD_CA53_CPU1>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	};

	a53_2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <2>;
	clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
	power-domains = <&sysc R8A77980_PD_CA53_CPU2>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	};

	a53_3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <3>;
	clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
	power-domains = <&sysc R8A77980_PD_CA53_CPU3>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	};

	L2_CA53: cache-controller {
	compatible = "cache";
	power-domains = <&sysc R8A77980_PD_CA53_SCU>;
	cache-unified;
	cache-level = <2>;
	};
	};

	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	extalr_clk: extalr {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	/* External PCIe clock - can be overridden by the board */
	pcie_bus_clk: pcie_bus {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	pmu_a53 {
	compatible = "arm,cortex-a53-pmu";
	interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
	};

	psci {
	compatible = "arm,psci-1.0", "arm,psci-0.2";
	method = "smc";
	};

	/* External SCIF clock - to be overridden by boards that provide it */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;

	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a77980-wdt",
	"renesas,rcar-gen3-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a77980",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 22>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a77980",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 28>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a77980",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 30>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a77980",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 17>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a77980",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 25>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a77980",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 15>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a77980";
	reg = <0 0xe6060000 0 0x50c>;
	};

	cmt0: timer@e60f0000 {
	compatible = "renesas,r8a77980-cmt0",
	"renesas,rcar-gen3-cmt0";
	reg = <0 0xe60f0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 303>;
	clock-names = "fck";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 303>;
	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a77980-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 302>;
	clock-names = "fck";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 302>;
	status = "disabled";
	};

	cmt2: timer@e6140000 {
	compatible = "renesas,r8a77980-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6140000 0 0x1004>;
	interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 301>;
	clock-names = "fck";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 301>;
	status = "disabled";
	};

	cmt3: timer@e6148000 {
	compatible = "renesas,r8a77980-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6148000 0 0x1004>;
	interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 300>;
	clock-names = "fck";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 300>;
	status = "disabled";
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a77980-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>, <&extalr_clk>;
	clock-names = "extal", "extalr";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a77980-rst";
	reg = <0 0xe6160000 0 0x200>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a77980-sysc";
	reg = <0 0xe6180000 0 0x440>;
	#power-domain-cells = <1>;
	};

	tsc: thermal@e6198000 {
	compatible = "renesas,r8a77980-thermal";
	reg = <0 0xe6198000 0 0x100>,
	<0 0xe61a0000 0 0x100>;
	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 522>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 522>;
	#thermal-sensor-cells = <1>;
	};

	intc_ex: interrupt-controller@e61c0000 {
	compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	tmu0: timer@e61e0000 {
	compatible = "renesas,tmu-r8a77980", "renesas,tmu";
	reg = <0 0xe61e0000 0 0x30>;
	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 125>;
	clock-names = "fck";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 125>;
	status = "disabled";
	};

	tmu1: timer@e6fc0000 {
	compatible = "renesas,tmu-r8a77980", "renesas,tmu";
	reg = <0 0xe6fc0000 0 0x30>;
	interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 124>;
	clock-names = "fck";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 124>;
	status = "disabled";
	};

	tmu2: timer@e6fd0000 {
	compatible = "renesas,tmu-r8a77980", "renesas,tmu";
	reg = <0 0xe6fd0000 0 0x30>;
	interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 123>;
	clock-names = "fck";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 123>;
	status = "disabled";
	};

	tmu3: timer@e6fe0000 {
	compatible = "renesas,tmu-r8a77980", "renesas,tmu";
	reg = <0 0xe6fe0000 0 0x30>;
	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 122>;
	clock-names = "fck";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 122>;
	status = "disabled";
	};

	tmu4: timer@ffc00000 {
	compatible = "renesas,tmu-r8a77980", "renesas,tmu";
	reg = <0 0xffc00000 0 0x30>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 121>;
	clock-names = "fck";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 121>;
	status = "disabled";
	};

	i2c0: i2c@e6500000 {
	compatible = "renesas,i2c-r8a77980",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6500000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	dmas = <&dmac1 0x91>, <&dmac1 0x90>,
	<&dmac2 0x91>, <&dmac2 0x90>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c1: i2c@e6508000 {
	compatible = "renesas,i2c-r8a77980",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	dmas = <&dmac1 0x93>, <&dmac1 0x92>,
	<&dmac2 0x93>, <&dmac2 0x92>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c2: i2c@e6510000 {
	compatible = "renesas,i2c-r8a77980",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6510000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	dmas = <&dmac1 0x95>, <&dmac1 0x94>,
	<&dmac2 0x95>, <&dmac2 0x94>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c3: i2c@e66d0000 {
	compatible = "renesas,i2c-r8a77980",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d0000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	i2c-scl-internal-delay-ns = <6>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c4: i2c@e66d8000 {
	compatible = "renesas,i2c-r8a77980",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d8000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	i2c-scl-internal-delay-ns = <6>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c5: i2c@e66e0000 {
	compatible = "renesas,i2c-r8a77980",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66e0000 0 0x40>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 919>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 919>;
	dmas = <&dmac1 0x9b>, <&dmac1 0x9a>,
	<&dmac2 0x9b>, <&dmac2 0x9a>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	hscif0: serial@e6540000 {
	compatible = "renesas,hscif-r8a77980",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6540000 0 0x60>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 520>,
	<&cpg CPG_CORE R8A77980_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x31>, <&dmac1 0x30>,
	<&dmac2 0x31>, <&dmac2 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 520>;
	status = "disabled";
	};

	hscif1: serial@e6550000 {
	compatible = "renesas,hscif-r8a77980",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6550000 0 0x60>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 519>,
	<&cpg CPG_CORE R8A77980_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x33>, <&dmac1 0x32>,
	<&dmac2 0x33>, <&dmac2 0x32>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 519>;
	status = "disabled";
	};

	hscif2: serial@e6560000 {
	compatible = "renesas,hscif-r8a77980",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6560000 0 0x60>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 518>,
	<&cpg CPG_CORE R8A77980_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x35>, <&dmac1 0x34>,
	<&dmac2 0x35>, <&dmac2 0x34>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 518>;
	status = "disabled";
	};

	hscif3: serial@e66a0000 {
	compatible = "renesas,hscif-r8a77980",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe66a0000 0 0x60>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 517>,
	<&cpg CPG_CORE R8A77980_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x37>, <&dmac1 0x36>,
	<&dmac2 0x37>, <&dmac2 0x36>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 517>;
	status = "disabled";
	};

	pcie_phy: pcie-phy@e65d0000 {
	compatible = "renesas,r8a77980-pcie-phy";
	reg = <0 0xe65d0000 0 0x8000>;
	#phy-cells = <0>;
	clocks = <&cpg CPG_MOD 319>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 319>;
	status = "disabled";
	};

	canfd: can@e66c0000 {
	compatible = "renesas,r8a77980-canfd",
	"renesas,rcar-gen3-canfd";
	reg = <0 0xe66c0000 0 0x8000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 914>,
	<&cpg CPG_CORE R8A77980_CLK_CANFD>,
	<&can_clk>;
	clock-names = "fck", "canfd", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 914>;
	status = "disabled";

	channel0 {
	status = "disabled";
	};

	channel1 {
	status = "disabled";
	};
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a77980",
	"renesas,etheravb-rcar-gen3";
	reg = <0 0xe6800000 0 0x800>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15",
	"ch16", "ch17", "ch18", "ch19",
	"ch20", "ch21", "ch22", "ch23",
	"ch24";
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	phy-mode = "rgmii";
	iommus = <&ipmmu_ds1 33>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	pwm0: pwm@e6e30000 {
	compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
	reg = <0 0xe6e30000 0 0x10>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	status = "disabled";
	};

	pwm1: pwm@e6e31000 {
	compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
	reg = <0 0xe6e31000 0 0x10>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	status = "disabled";
	};

	pwm2: pwm@e6e32000 {
	compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
	reg = <0 0xe6e32000 0 0x10>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	status = "disabled";
	};

	pwm3: pwm@e6e33000 {
	compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
	reg = <0 0xe6e33000 0 0x10>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	status = "disabled";
	};

	pwm4: pwm@e6e34000 {
	compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
	reg = <0 0xe6e34000 0 0x10>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a77980",
	"renesas,rcar-gen3-scif",
	"renesas,scif";
	reg = <0 0xe6e60000 0 0x40>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 207>,
	<&cpg CPG_CORE R8A77980_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x51>, <&dmac1 0x50>,
	<&dmac2 0x51>, <&dmac2 0x50>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 207>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a77980",
	"renesas,rcar-gen3-scif",
	"renesas,scif";
	reg = <0 0xe6e68000 0 0x40>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 206>,
	<&cpg CPG_CORE R8A77980_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x53>, <&dmac1 0x52>,
	<&dmac2 0x53>, <&dmac2 0x52>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 206>;
	status = "disabled";
	};

	scif3: serial@e6c50000 {
	compatible = "renesas,scif-r8a77980",
	"renesas,rcar-gen3-scif",
	"renesas,scif";
	reg = <0 0xe6c50000 0 0x40>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 204>,
	<&cpg CPG_CORE R8A77980_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x57>, <&dmac1 0x56>,
	<&dmac2 0x57>, <&dmac2 0x56>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 204>;
	status = "disabled";
	};

	scif4: serial@e6c40000 {
	compatible = "renesas,scif-r8a77980",
	"renesas,rcar-gen3-scif",
	"renesas,scif";
	reg = <0 0xe6c40000 0 0x40>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 203>,
	<&cpg CPG_CORE R8A77980_CLK_S3D1>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x59>, <&dmac1 0x58>,
	<&dmac2 0x59>, <&dmac2 0x58>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 203>;
	status = "disabled";
	};

	tpu: pwm@e6e80000 {
	compatible = "renesas,tpu-r8a77980", "renesas,tpu";
	reg = <0 0xe6e80000 0 0x148>;
	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 304>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 304>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	msiof0: spi@e6e90000 {
	compatible = "renesas,msiof-r8a77980",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6e90000 0 0x64>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 211>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 211>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof1: spi@e6ea0000 {
	compatible = "renesas,msiof-r8a77980",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6ea0000 0 0x0064>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 210>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 210>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof2: spi@e6c00000 {
	compatible = "renesas,msiof-r8a77980",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c00000 0 0x0064>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 209>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 209>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof3: spi@e6c10000 {
	compatible = "renesas,msiof-r8a77980",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c10000 0 0x0064>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 208>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 208>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	vin0: video@e6ef0000 {
	compatible = "renesas,vin-r8a77980";
	reg = <0 0xe6ef0000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 811>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 811>;
	renesas,id = <0>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin0csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin0>;
	};
	};
	};
	};

	vin1: video@e6ef1000 {
	compatible = "renesas,vin-r8a77980";
	reg = <0 0xe6ef1000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 810>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	status = "disabled";
	renesas,id = <1>;
	resets = <&cpg 810>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin1csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin1>;
	};
	};
	};
	};

	vin2: video@e6ef2000 {
	compatible = "renesas,vin-r8a77980";
	reg = <0 0xe6ef2000 0 0x1000>;
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 809>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 809>;
	renesas,id = <2>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin2csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin2>;
	};
	};
	};
	};

	vin3: video@e6ef3000 {
	compatible = "renesas,vin-r8a77980";
	reg = <0 0xe6ef3000 0 0x1000>;
	interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 808>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 808>;
	renesas,id = <3>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin3csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi40vin3>;
	};
	};
	};
	};

	vin4: video@e6ef4000 {
	compatible = "renesas,vin-r8a77980";
	reg = <0 0xe6ef4000 0 0x1000>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 807>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 807>;
	renesas,id = <4>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin4csi41: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi41vin4>;
	};
	};
	};
	};

	vin5: video@e6ef5000 {
	compatible = "renesas,vin-r8a77980";
	reg = <0 0xe6ef5000 0 0x1000>;
	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 806>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 806>;
	renesas,id = <5>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin5csi41: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi41vin5>;
	};
	};
	};
	};

	vin6: video@e6ef6000 {
	compatible = "renesas,vin-r8a77980";
	reg = <0 0xe6ef6000 0 0x1000>;
	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 805>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 805>;
	renesas,id = <6>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin6csi41: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi41vin6>;
	};
	};
	};
	};

	vin7: video@e6ef7000 {
	compatible = "renesas,vin-r8a77980";
	reg = <0 0xe6ef7000 0 0x1000>;
	interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 804>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 804>;
	renesas,id = <7>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin7csi41: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&csi41vin7>;
	};
	};
	};
	};

	vin8: video@e6ef8000 {
	compatible = "renesas,vin-r8a77980";
	reg = <0 0xe6ef8000 0 0x1000>;
	interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 628>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 628>;
	renesas,id = <8>;
	status = "disabled";
	};

	vin9: video@e6ef9000 {
	compatible = "renesas,vin-r8a77980";
	reg = <0 0xe6ef9000 0 0x1000>;
	interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 627>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 627>;
	renesas,id = <9>;
	status = "disabled";
	};

	vin10: video@e6efa000 {
	compatible = "renesas,vin-r8a77980";
	reg = <0 0xe6efa000 0 0x1000>;
	interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 625>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 625>;
	renesas,id = <10>;
	status = "disabled";
	};

	vin11: video@e6efb000 {
	compatible = "renesas,vin-r8a77980";
	reg = <0 0xe6efb000 0 0x1000>;
	interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 618>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 618>;
	renesas,id = <11>;
	status = "disabled";
	};

	vin12: video@e6efc000 {
	compatible = "renesas,vin-r8a77980";
	reg = <0 0xe6efc000 0 0x1000>;
	interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 612>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 612>;
	renesas,id = <12>;
	status = "disabled";
	};

	vin13: video@e6efd000 {
	compatible = "renesas,vin-r8a77980";
	reg = <0 0xe6efd000 0 0x1000>;
	interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 608>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 608>;
	renesas,id = <13>;
	status = "disabled";
	};

	vin14: video@e6efe000 {
	compatible = "renesas,vin-r8a77980";
	reg = <0 0xe6efe000 0 0x1000>;
	interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 605>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 605>;
	renesas,id = <14>;
	status = "disabled";
	};

	vin15: video@e6eff000 {
	compatible = "renesas,vin-r8a77980";
	reg = <0 0xe6eff000 0 0x1000>;
	interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 604>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 604>;
	renesas,id = <15>;
	status = "disabled";
	};

	dmac1: dma-controller@e7300000 {
	compatible = "renesas,dmac-r8a77980",
	"renesas,rcar-dmac";
	reg = <0 0xe7300000 0 0x10000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
	<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
	<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
	<&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
	<&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
	<&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
	<&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
	<&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
	};

	dmac2: dma-controller@e7310000 {
	compatible = "renesas,dmac-r8a77980",
	"renesas,rcar-dmac";
	reg = <0 0xe7310000 0 0x10000>;
	interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 217>;
	clock-names = "fck";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 217>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
	<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
	<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
	<&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
	<&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
	<&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
	<&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
	<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
	};

	gether: ethernet@e7400000 {
	compatible = "renesas,gether-r8a77980";
	reg = <0 0xe7400000 0 0x1000>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 813>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 813>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	ipmmu_ds1: mmu@e7740000 {
	compatible = "renesas,ipmmu-r8a77980";
	reg = <0 0xe7740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 0>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_ir: mmu@ff8b0000 {
	compatible = "renesas,ipmmu-r8a77980";
	reg = <0 0xff8b0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 3>;
	power-domains = <&sysc R8A77980_PD_A3IR>;
	#iommu-cells = <1>;
	};

	ipmmu_mm: mmu@e67b0000 {
	compatible = "renesas,ipmmu-r8a77980";
	reg = <0 0xe67b0000 0 0x1000>;
	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_rt: mmu@ffc80000 {
	compatible = "renesas,ipmmu-r8a77980";
	reg = <0 0xffc80000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 10>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vc0: mmu@fe990000 {
	compatible = "renesas,ipmmu-r8a77980";
	reg = <0 0xfe990000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 12>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vi0: mmu@febd0000 {
	compatible = "renesas,ipmmu-r8a77980";
	reg = <0 0xfebd0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 14>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vip0: mmu@e7b00000 {
	compatible = "renesas,ipmmu-r8a77980";
	reg = <0 0xe7b00000 0 0x1000>;
	+ renesas,ipmmu-main = <&ipmmu_mm 4>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vip1: mmu@e7960000 {
	compatible = "renesas,ipmmu-r8a77980";
	reg = <0 0xe7960000 0 0x1000>;
	+ renesas,ipmmu-main = <&ipmmu_mm 11>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	mmc0: mmc@ee140000 {
	compatible = "renesas,sdhi-r8a77980",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee140000 0 0x2000>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	max-frequency = <200000000>;
	iommus = <&ipmmu_ds1 32>;
	status = "disabled";
	};

	gic: interrupt-controller@f1010000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x0 0xf1010000 0 0x1000>,
	<0x0 0xf1020000 0 0x20000>,
	<0x0 0xf1040000 0 0x20000>,
	<0x0 0xf1060000 0 0x20000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \|
	IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	pciec: pcie@fe000000 {
	compatible = "renesas,pcie-r8a77980",
	"renesas,pcie-rcar-gen3";
	reg = <0 0xfe000000 0 0x80000>;
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x00 0xff>;
	device_type = "pci";
	ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000>,
	<0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>,
	<0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>,
	<0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>;
	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
	clock-names = "pcie", "pcie_bus";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 319>;
	phys = <&pcie_phy>;
	phy-names = "pcie";
	status = "disabled";
	};

	vspd0: vsp@fea20000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea20000 0 0x5000>;
	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 623>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 623>;
	renesas,fcp = <&fcpvd0>;
	};

	fcpvd0: fcp@fea27000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea27000 0 0x200>;
	clocks = <&cpg CPG_MOD 603>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 603>;
	};

	csi40: csi2@feaa0000 {
	compatible = "renesas,r8a77980-csi2";
	reg = <0 0xfeaa0000 0 0x10000>;
	interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	csi40vin0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vin0csi40>;
	};
	csi40vin1: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vin1csi40>;
	};
	csi40vin2: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&vin2csi40>;
	};
	csi40vin3: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&vin3csi40>;
	};
	};
	};
	};

	csi41: csi2@feab0000 {
	compatible = "renesas,r8a77980-csi2";
	reg = <0 0xfeab0000 0 0x10000>;
	interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 715>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 715>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	csi41vin4: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vin4csi41>;
	};
	csi41vin5: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vin5csi41>;
	};
	csi41vin6: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&vin6csi41>;
	};
	csi41vin7: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&vin7csi41>;
	};
	};
	};
	};

	du: display@feb00000 {
	- compatible = "renesas,du-r8a77980",
	- "renesas,du-r8a77970";
	+ compatible = "renesas,du-r8a77980";
	reg = <0 0xfeb00000 0 0x80000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 724>;
	clock-names = "du.0";
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 724>;
	- vsps = <&vspd0 0>;
	+ reset-names = "du.0";
	+ renesas,vsps = <&vspd0 0>;
	+
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb: endpoint {
	};
	};

	port@1 {
	reg = <1>;
	du_out_lvds0: endpoint {
	remote-endpoint = <&lvds0_in>;
	};
	};
	};
	};

	lvds0: lvds-encoder@feb90000 {
	compatible = "renesas,r8a77980-lvds";
	reg = <0 0xfeb90000 0 0x14>;
	clocks = <&cpg CPG_MOD 727>;
	power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
	resets = <&cpg 727>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds0_in: endpoint {
	remote-endpoint =
	<&du_out_lvds0>;
	};
	};

	port@1 {
	reg = <1>;
	lvds0_out: endpoint {
	};
	};
	};
	};

	prr: chipid@fff00044 {
	compatible = "renesas,prr";
	reg = <0 0xfff00044 0 4>;
	};
	};

	thermal-zones {
	thermal-sensor-1 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&tsc 0>;

	trips {
	sensor1-passive {
	temperature = <95000>;
	hysteresis = <1000>;
	type = "passive";
	};
	sensor1-critical {
	temperature = <120000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};
	};

	thermal-sensor-2 {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&tsc 1>;

	trips {
	sensor2-passive {
	temperature = <95000>;
	hysteresis = <1000>;
	type = "passive";
	};
	sensor2-critical {
	temperature = <120000>;
	hysteresis = <1000>;
	type = "critical";
	};
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \|
	IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \|
	IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \|
	IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \|
	IRQ_TYPE_LEVEL_LOW)>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a77990-ebisu.dts b/sys/gnu/dts/arm64/renesas/r8a77990-ebisu.dts
	index 4fd2b14fbb8b..dc24cec46ae1 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a77990-ebisu.dts
	+++ b/sys/gnu/dts/arm64/renesas/r8a77990-ebisu.dts
	@@ -1,753 +1,751 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the ebisu board
	*
	* Copyright (C) 2018 Renesas Electronics Corp.
	*/

	/dts-v1/;
	#include "r8a77990.dtsi"
	#include <dt-bindings/gpio/gpio.h>

	/ {
	model = "Renesas Ebisu board based on r8a77990";
	compatible = "renesas,ebisu", "renesas,r8a77990";

	aliases {
	serial0 = &scif2;
	ethernet0 = &avb;
	};

	chosen {
	bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
	stdout-path = "serial0:115200n8";
	};

	audio_clkout: audio-clkout {
	/*
	* This is same as <&rcar_sound 0>
	* but needed to avoid cs2000/rcar_sound probe dead-lock
	*/
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <11289600>;
	};

	backlight: backlight {
	compatible = "pwm-backlight";
	pwms = <&pwm3 0 50000>;

	brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
	default-brightness-level = <10>;

	power-supply = <&reg_12p0v>;
	};

	cvbs-in {
	compatible = "composite-video-connector";
	label = "CVBS IN";

	port {
	cvbs_con: endpoint {
	remote-endpoint = <&adv7482_ain7>;
	};
	};
	};

	hdmi-in {
	compatible = "hdmi-connector";
	label = "HDMI IN";
	type = "a";

	port {
	hdmi_in_con: endpoint {
	remote-endpoint = <&adv7482_hdmi>;
	};
	};
	};

	hdmi-out {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con_out: endpoint {
	remote-endpoint = <&adv7511_out>;
	};
	};
	};

	lvds-decoder {
	compatible = "thine,thc63lvd1024";
	vcc-supply = <&reg_3p3v>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	thc63lvd1024_in: endpoint {
	remote-endpoint = <&lvds0_out>;
	};
	};

	port@2 {
	reg = <2>;
	thc63lvd1024_out: endpoint {
	remote-endpoint = <&adv7511_in>;
	};
	};
	};
	};

	memory@48000000 {
	device_type = "memory";
	/* first 128MB is reserved for secure area. */
	reg = <0x0 0x48000000 0x0 0x38000000>;
	};

	reg_1p8v: regulator0 {
	compatible = "regulator-fixed";
	regulator-name = "fixed-1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_3p3v: regulator1 {
	compatible = "regulator-fixed";
	regulator-name = "fixed-3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_12p0v: regulator2 {
	compatible = "regulator-fixed";
	regulator-name = "D12.0V";
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	regulator-boot-on;
	regulator-always-on;
	};

	rsnd_ak4613: sound {
	compatible = "simple-audio-card";

	simple-audio-card,name = "rsnd-ak4613";
	simple-audio-card,format = "left_j";
	simple-audio-card,bitclock-master = <&sndcpu>;
	simple-audio-card,frame-master = <&sndcpu>;

	sndcodec: simple-audio-card,codec {
	sound-dai = <&ak4613>;
	};

	sndcpu: simple-audio-card,cpu {
	sound-dai = <&rcar_sound>;
	};
	};

	vbus0_usb2: regulator-vbus0-usb2 {
	compatible = "regulator-fixed";

	regulator-name = "USB20_VBUS_CN";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;

	gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vcc_sdhi0: regulator-vcc-sdhi0 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI0 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vccq_sdhi0: regulator-vccq-sdhi0 {
	compatible = "regulator-gpio";

	regulator-name = "SDHI0 VccQ";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
	gpios-states = <1>;
	states = <3300000 1>, <1800000 0>;
	};

	vcc_sdhi1: regulator-vcc-sdhi1 {
	compatible = "regulator-fixed";

	regulator-name = "SDHI1 Vcc";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	};

	vccq_sdhi1: regulator-vccq-sdhi1 {
	compatible = "regulator-gpio";

	regulator-name = "SDHI1 VccQ";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;

	gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
	gpios-states = <1>;
	states = <3300000 1>, <1800000 0>;
	};

	vga {
	compatible = "vga-connector";

	port {
	vga_in: endpoint {
	remote-endpoint = <&adv7123_out>;
	};
	};
	};

	vga-encoder {
	compatible = "adi,adv7123";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7123_in: endpoint {
	remote-endpoint = <&du_out_rgb>;
	};
	};
	port@1 {
	reg = <1>;
	adv7123_out: endpoint {
	remote-endpoint = <&vga_in>;
	};
	};
	};
	};

	x12_clk: x12 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24576000>;
	};

	x13_clk: x13 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <74250000>;
	};
	};

	&audio_clk_a {
	clock-frequency = <22579200>;
	};

	&avb {
	pinctrl-0 = <&avb_pins>;
	pinctrl-names = "default";
	phy-handle = <&phy0>;
	status = "okay";

	phy0: ethernet-phy@0 {
	rxc-skew-ps = <1500>;
	reg = <0>;
	interrupt-parent = <&gpio2>;
	interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
	reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
	/*
	* TX clock internal delay mode is required for reliable
	* 1Gbps communication using the KSZ9031RNX phy present on
	* the Ebisu board, however, TX clock internal delay mode
	* isn't supported on r8a77990. Thus, limit speed to
	* 100Mbps for reliable communication.
	*/
	max-speed = <100>;
	};
	};

	&canfd {
	pinctrl-0 = <&canfd0_pins>;
	pinctrl-names = "default";
	status = "okay";

	channel0 {
	status = "okay";
	};
	};

	&csi40 {
	status = "okay";

	ports {
	port@0 {
	reg = <0>;

	csi40_in: endpoint {
	clock-lanes = <0>;
	data-lanes = <1 2>;
	remote-endpoint = <&adv7482_txa>;
	};
	};
	};
	};

	&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";
	status = "okay";

	clocks = <&cpg CPG_MOD 724>,
	<&cpg CPG_MOD 723>,
	<&x13_clk>;
	clock-names = "du.0", "du.1", "dclkin.0";

	ports {
	port@0 {
	endpoint {
	remote-endpoint = <&adv7123_in>;
	};
	};
	};
	};

	&ehci0 {
	dr_mode = "otg";
	status = "okay";
	};

	&extal_clk {
	clock-frequency = <48000000>;
	};

	&hsusb {
	dr_mode = "otg";
	status = "okay";
	};

	&i2c0 {
	status = "okay";

	io_expander: gpio@20 {
	compatible = "onnn,pca9654";
	reg = <0x20>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-parent = <&gpio2>;
	interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
	};

	hdmi-encoder@39 {
	compatible = "adi,adv7511w";
	reg = <0x39>;
	interrupt-parent = <&gpio1>;
	interrupts = <1 IRQ_TYPE_LEVEL_LOW>;

	adi,input-depth = <8>;
	adi,input-colorspace = "rgb";
	adi,input-clock = "1x";
	- adi,input-style = <1>;
	- adi,input-justification = "evenly";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7511_in: endpoint {
	remote-endpoint = <&thc63lvd1024_out>;
	};
	};

	port@1 {
	reg = <1>;
	adv7511_out: endpoint {
	remote-endpoint = <&hdmi_con_out>;
	};
	};
	};
	};

	video-receiver@70 {
	compatible = "adi,adv7482";
	reg = <0x70>;

	#address-cells = <1>;
	#size-cells = <0>;

	interrupt-parent = <&gpio0>;
	interrupt-names = "intrq1", "intrq2";
	interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
	<17 IRQ_TYPE_LEVEL_LOW>;

	port@7 {
	reg = <7>;

	adv7482_ain7: endpoint {
	remote-endpoint = <&cvbs_con>;
	};
	};

	port@8 {
	reg = <8>;

	adv7482_hdmi: endpoint {
	remote-endpoint = <&hdmi_in_con>;
	};
	};

	port@a {
	reg = <10>;

	adv7482_txa: endpoint {
	clock-lanes = <0>;
	data-lanes = <1 2>;
	remote-endpoint = <&csi40_in>;
	};
	};
	};
	};

	&i2c3 {
	status = "okay";

	ak4613: codec@10 {
	compatible = "asahi-kasei,ak4613";
	#sound-dai-cells = <0>;
	reg = <0x10>;
	clocks = <&rcar_sound 3>;

	asahi-kasei,in1-single-end;
	asahi-kasei,in2-single-end;
	asahi-kasei,out1-single-end;
	asahi-kasei,out2-single-end;
	asahi-kasei,out3-single-end;
	asahi-kasei,out4-single-end;
	asahi-kasei,out5-single-end;
	asahi-kasei,out6-single-end;
	};

	cs2000: clk-multiplier@4f {
	#clock-cells = <0>;
	compatible = "cirrus,cs2000-cp";
	reg = <0x4f>;
	clocks = <&audio_clkout>, <&x12_clk>;
	clock-names = "clk_in", "ref_clk";

	assigned-clocks = <&cs2000>;
	assigned-clock-rates = <24576000>; /* 1/1 divide */
	};
	};

	&i2c_dvfs {
	status = "okay";

	clock-frequency = <400000>;

	pmic: pmic@30 {
	pinctrl-0 = <&irq0_pins>;
	pinctrl-names = "default";

	compatible = "rohm,bd9571mwv";
	reg = <0x30>;
	interrupt-parent = <&intc_ex>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;
	rohm,ddr-backup-power = <0x1>;
	rohm,rstbmode-level;
	};
	};

	&lvds0 {
	status = "okay";

	clocks = <&cpg CPG_MOD 727>,
	<&x13_clk>,
	<&extal_clk>;
	clock-names = "fck", "dclkin.0", "extal";

	ports {
	port@1 {
	lvds0_out: endpoint {
	remote-endpoint = <&thc63lvd1024_in>;
	};
	};
	};
	};

	&lvds1 {
	/*
	* Even though the LVDS1 output is not connected, the encoder must be
	* enabled to supply a pixel clock to the DU for the DPAD output when
	* LVDS0 is in use.
	*/
	status = "okay";

	clocks = <&cpg CPG_MOD 727>,
	<&x13_clk>,
	<&extal_clk>;
	clock-names = "fck", "dclkin.0", "extal";
	};

	&ohci0 {
	dr_mode = "otg";
	status = "okay";
	};

	&pcie_bus_clk {
	clock-frequency = <100000000>;
	};

	&pciec0 {
	status = "okay";
	};

	&pfc {
	avb_pins: avb {
	mux {
	groups = "avb_link", "avb_mii";
	function = "avb";
	};
	};

	canfd0_pins: canfd0 {
	groups = "canfd0_data";
	function = "canfd0";
	};

	du_pins: du {
	groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
	function = "du";
	};

	irq0_pins: irq0 {
	groups = "intc_ex_irq0";
	function = "intc_ex";
	};

	pwm3_pins: pwm3 {
	groups = "pwm3_b";
	function = "pwm3";
	};

	pwm5_pins: pwm5 {
	groups = "pwm5_a";
	function = "pwm5";
	};

	scif2_pins: scif2 {
	groups = "scif2_data_a";
	function = "scif2";
	};

	sdhi0_pins: sd0 {
	groups = "sdhi0_data4", "sdhi0_ctrl";
	function = "sdhi0";
	power-source = <3300>;
	};

	sdhi0_pins_uhs: sd0_uhs {
	groups = "sdhi0_data4", "sdhi0_ctrl";
	function = "sdhi0";
	power-source = <1800>;
	};

	sdhi1_pins: sd1 {
	groups = "sdhi1_data4", "sdhi1_ctrl";
	function = "sdhi1";
	power-source = <3300>;
	};

	sdhi1_pins_uhs: sd1_uhs {
	groups = "sdhi1_data4", "sdhi1_ctrl";
	function = "sdhi1";
	power-source = <1800>;
	};

	sdhi3_pins: sd3 {
	groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
	function = "sdhi3";
	power-source = <1800>;
	};

	sound_clk_pins: sound_clk {
	groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
	"audio_clkout_a", "audio_clkout1_a";
	function = "audio_clk";
	};

	sound_pins: sound {
	groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
	function = "ssi";
	};

	usb0_pins: usb {
	groups = "usb0_b", "usb0_id";
	function = "usb0";
	};

	usb30_pins: usb30 {
	groups = "usb30";
	function = "usb30";
	};
	};

	&pwm3 {
	pinctrl-0 = <&pwm3_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&pwm5 {
	pinctrl-0 = <&pwm5_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&rcar_sound {
	pinctrl-0 = <&sound_pins &sound_clk_pins>;
	pinctrl-names = "default";

	/* Single DAI */
	#sound-dai-cells = <0>;

	/* audio_clkout0/1/2/3 */
	#clock-cells = <1>;
	clock-frequency = <12288000 11289600>;

	status = "okay";

	/* update <audio_clk_b> to <cs2000> */
	clocks = <&cpg CPG_MOD 1005>,
	<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
	<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
	<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
	<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
	<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	<&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
	<&cpg CPG_CORE R8A77990_CLK_ZA2>;

	rcar_sound,dai {
	dai0 {
	playback = <&ssi0 &src0 &dvc0>;
	capture = <&ssi1 &src1 &dvc1>;
	};
	};

	};

	&rwdt {
	timeout-sec = <60>;
	status = "okay";
	};

	&scif2 {
	pinctrl-0 = <&scif2_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-1 = <&sdhi0_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi0>;
	vqmmc-supply = <&vccq_sdhi0>;
	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
	bus-width = <4>;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
	};

	&sdhi1 {
	pinctrl-0 = <&sdhi1_pins>;
	pinctrl-1 = <&sdhi1_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi1>;
	vqmmc-supply = <&vccq_sdhi1>;
	cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
	};

	&sdhi3 {
	/* used for on-board 8bit eMMC */
	pinctrl-0 = <&sdhi3_pins>;
	pinctrl-1 = <&sdhi3_pins>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_1p8v>;
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	bus-width = <8>;
	non-removable;
	status = "okay";
	};

	&ssi1 {
	shared-pin;
	};

	&usb2_phy0 {
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";

	vbus-supply = <&vbus0_usb2>;
	status = "okay";
	};

	&usb3_peri0 {
	companion = <&xhci0>;
	status = "okay";
	};

	&vin4 {
	status = "okay";
	};

	&vin5 {
	status = "okay";
	};

	&xhci0 {
	pinctrl-0 = <&usb30_pins>;
	pinctrl-names = "default";

	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a77990.dtsi b/sys/gnu/dts/arm64/renesas/r8a77990.dtsi
	index 32d91f210246..1543f18e834f 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a77990.dtsi
	+++ b/sys/gnu/dts/arm64/renesas/r8a77990.dtsi
	@@ -1,1924 +1,1947 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the R-Car E3 (R8A77990) SoC
	*
	* Copyright (C) 2018-2019 Renesas Electronics Corp.
	*/

	#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/power/r8a77990-sysc.h>

	/ {
	compatible = "renesas,r8a77990";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	i2c6 = &i2c6;
	i2c7 = &i2c7;
	};

	/*
	* The external audio clocks are configured as 0 Hz fixed frequency
	* clocks by default.
	* Boards that provide audio clocks should override them.
	*/
	audio_clk_a: audio_clk_a {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_b: audio_clk_b {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	audio_clk_c: audio_clk_c {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	/* External CAN clock - to be overridden by boards that provide it */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	cluster1_opp: opp_table10 {
	compatible = "operating-points-v2";
	opp-shared;
	opp-800000000 {
	opp-hz = /bits/ 64 <800000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	};
	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	opp-microvolt = <820000>;
	clock-latency-ns = <300000>;
	opp-suspend;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	a53_0: cpu@0 {
	compatible = "arm,cortex-a53";
	reg = <0>;
	device_type = "cpu";
	#cooling-cells = <2>;
	power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	+ cpu-idle-states = <&CPU_SLEEP_0>;
	dynamic-power-coefficient = <277>;
	clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	};

	a53_1: cpu@1 {
	compatible = "arm,cortex-a53";
	reg = <1>;
	device_type = "cpu";
	power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	+ cpu-idle-states = <&CPU_SLEEP_0>;
	clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
	operating-points-v2 = <&cluster1_opp>;
	};

	L2_CA53: cache-controller-0 {
	compatible = "cache";
	power-domains = <&sysc R8A77990_PD_CA53_SCU>;
	cache-unified;
	cache-level = <2>;
	};
	+
	+ idle-states {
	+ entry-method = "psci";
	+
	+ CPU_SLEEP_0: cpu-sleep-0 {
	+ compatible = "arm,idle-state";
	+ arm,psci-suspend-param = <0x0010000>;
	+ local-timer-stop;
	+ entry-latency-us = <700>;
	+ exit-latency-us = <700>;
	+ min-residency-us = <5000>;
	+ };
	+ };
	};

	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	/* External PCIe clock - can be overridden by the board */
	pcie_bus_clk: pcie_bus {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	pmu_a53 {
	compatible = "arm,cortex-a53-pmu";
	interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
	<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&a53_0>, <&a53_1>;
	};

	psci {
	compatible = "arm,psci-1.0", "arm,psci-0.2";
	method = "smc";
	};

	/* External SCIF clock - to be overridden by boards that provide it */
	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	soc: soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a77990-wdt",
	"renesas,rcar-gen3-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a77990",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 18>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a77990",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 23>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a77990",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 26>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a77990",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 16>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a77990",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 11>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a77990",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 20>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	gpio6: gpio@e6055400 {
	compatible = "renesas,gpio-r8a77990",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055400 0 0x50>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 192 18>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 906>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 906>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a77990";
	reg = <0 0xe6060000 0 0x508>;
	};

	i2c_dvfs: i2c@e60b0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,iic-r8a77990";
	reg = <0 0xe60b0000 0 0x15>;
	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 926>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 926>;
	dmas = <&dmac0 0x11>, <&dmac0 0x10>;
	dma-names = "tx", "rx";
	status = "disabled";
	};

	cmt0: timer@e60f0000 {
	compatible = "renesas,r8a77990-cmt0",
	"renesas,rcar-gen3-cmt0";
	reg = <0 0xe60f0000 0 0x1004>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 303>;
	clock-names = "fck";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 303>;
	status = "disabled";
	};

	cmt1: timer@e6130000 {
	compatible = "renesas,r8a77990-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6130000 0 0x1004>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 302>;
	clock-names = "fck";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 302>;
	status = "disabled";
	};

	cmt2: timer@e6140000 {
	compatible = "renesas,r8a77990-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6140000 0 0x1004>;
	interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 301>;
	clock-names = "fck";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 301>;
	status = "disabled";
	};

	cmt3: timer@e6148000 {
	compatible = "renesas,r8a77990-cmt1",
	"renesas,rcar-gen3-cmt1";
	reg = <0 0xe6148000 0 0x1004>;
	interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 300>;
	clock-names = "fck";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 300>;
	status = "disabled";
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a77990-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>;
	clock-names = "extal";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a77990-rst";
	reg = <0 0xe6160000 0 0x0200>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a77990-sysc";
	reg = <0 0xe6180000 0 0x0400>;
	#power-domain-cells = <1>;
	};

	thermal: thermal@e6190000 {
	compatible = "renesas,thermal-r8a77990";
	reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 522>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 522>;
	#thermal-sensor-cells = <0>;
	};

	intc_ex: interrupt-controller@e61c0000 {
	compatible = "renesas,intc-ex-r8a77990", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	i2c0: i2c@e6500000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77990",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6500000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	dmas = <&dmac1 0x91>, <&dmac1 0x90>,
	<&dmac2 0x91>, <&dmac2 0x90>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c1: i2c@e6508000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77990",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	dmas = <&dmac1 0x93>, <&dmac1 0x92>,
	<&dmac2 0x93>, <&dmac2 0x92>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c2: i2c@e6510000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77990",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6510000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	dmas = <&dmac1 0x95>, <&dmac1 0x94>,
	<&dmac2 0x95>, <&dmac2 0x94>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c3: i2c@e66d0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77990",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d0000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	dmas = <&dmac0 0x97>, <&dmac0 0x96>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <110>;
	status = "disabled";
	};

	i2c4: i2c@e66d8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77990",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d8000 0 0x40>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 927>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 927>;
	dmas = <&dmac0 0x99>, <&dmac0 0x98>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c5: i2c@e66e0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77990",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66e0000 0 0x40>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 919>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 919>;
	dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c6: i2c@e66e8000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77990",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66e8000 0 0x40>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 918>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 918>;
	dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c7: i2c@e6690000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77990",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6690000 0 0x40>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 1003>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 1003>;
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	hscif0: serial@e6540000 {
	compatible = "renesas,hscif-r8a77990",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6540000 0 0x60>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 520>,
	<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x31>, <&dmac1 0x30>,
	<&dmac2 0x31>, <&dmac2 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 520>;
	status = "disabled";
	};

	hscif1: serial@e6550000 {
	compatible = "renesas,hscif-r8a77990",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6550000 0 0x60>;
	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 519>,
	<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x33>, <&dmac1 0x32>,
	<&dmac2 0x33>, <&dmac2 0x32>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 519>;
	status = "disabled";
	};

	hscif2: serial@e6560000 {
	compatible = "renesas,hscif-r8a77990",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6560000 0 0x60>;
	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 518>,
	<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x35>, <&dmac1 0x34>,
	<&dmac2 0x35>, <&dmac2 0x34>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 518>;
	status = "disabled";
	};

	hscif3: serial@e66a0000 {
	compatible = "renesas,hscif-r8a77990",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe66a0000 0 0x60>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 517>,
	<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x37>, <&dmac0 0x36>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 517>;
	status = "disabled";
	};

	hscif4: serial@e66b0000 {
	compatible = "renesas,hscif-r8a77990",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe66b0000 0 0x60>;
	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 516>,
	<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x39>, <&dmac0 0x38>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 516>;
	status = "disabled";
	};

	hsusb: usb@e6590000 {
	compatible = "renesas,usbhs-r8a77990",
	"renesas,rcar-gen3-usbhs";
	reg = <0 0xe6590000 0 0x200>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
	dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
	<&usb_dmac1 0>, <&usb_dmac1 1>;
	dma-names = "ch0", "ch1", "ch2", "ch3";
	renesas,buswait = <11>;
	phys = <&usb2_phy0 3>;
	phy-names = "usb";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 704>, <&cpg 703>;
	status = "disabled";
	};

	usb_dmac0: dma-controller@e65a0000 {
	compatible = "renesas,r8a77990-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65a0000 0 0x100>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 330>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 330>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac1: dma-controller@e65b0000 {
	compatible = "renesas,r8a77990-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65b0000 0 0x100>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 331>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 331>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	+ arm_cc630p: crypto@e6601000 {
	+ compatible = "arm,cryptocell-630p-ree";
	+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0 0xe6601000 0 0x1000>;
	+ clocks = <&cpg CPG_MOD 229>;
	+ resets = <&cpg 229>;
	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	+ };
	+
	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a77990",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x10000>;
	interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
	<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
	<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
	<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
	<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
	<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
	<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
	<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
	};

	dmac1: dma-controller@e7300000 {
	compatible = "renesas,dmac-r8a77990",
	"renesas,rcar-dmac";
	reg = <0 0xe7300000 0 0x10000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
	<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
	<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
	<&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
	<&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
	<&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
	<&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
	<&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
	};

	dmac2: dma-controller@e7310000 {
	compatible = "renesas,dmac-r8a77990",
	"renesas,rcar-dmac";
	reg = <0 0xe7310000 0 0x10000>;
	interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 217>;
	clock-names = "fck";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 217>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
	<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
	<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
	<&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
	<&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
	<&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
	<&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
	<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
	};

	ipmmu_ds0: mmu@e6740000 {
	compatible = "renesas,ipmmu-r8a77990";
	reg = <0 0xe6740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 0>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_ds1: mmu@e7740000 {
	compatible = "renesas,ipmmu-r8a77990";
	reg = <0 0xe7740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 1>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_hc: mmu@e6570000 {
	compatible = "renesas,ipmmu-r8a77990";
	reg = <0 0xe6570000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 2>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_mm: mmu@e67b0000 {
	compatible = "renesas,ipmmu-r8a77990";
	reg = <0 0xe67b0000 0 0x1000>;
	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_mp: mmu@ec670000 {
	compatible = "renesas,ipmmu-r8a77990";
	reg = <0 0xec670000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 4>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_pv0: mmu@fd800000 {
	compatible = "renesas,ipmmu-r8a77990";
	reg = <0 0xfd800000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 6>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_rt: mmu@ffc80000 {
	compatible = "renesas,ipmmu-r8a77990";
	reg = <0 0xffc80000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 10>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vc0: mmu@fe6b0000 {
	compatible = "renesas,ipmmu-r8a77990";
	reg = <0 0xfe6b0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 12>;
	power-domains = <&sysc R8A77990_PD_A3VC>;
	#iommu-cells = <1>;
	};

	ipmmu_vi0: mmu@febd0000 {
	compatible = "renesas,ipmmu-r8a77990";
	reg = <0 0xfebd0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 14>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vp0: mmu@fe990000 {
	compatible = "renesas,ipmmu-r8a77990";
	reg = <0 0xfe990000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 16>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a77990",
	"renesas,etheravb-rcar-gen3";
	reg = <0 0xe6800000 0 0x800>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15",
	"ch16", "ch17", "ch18", "ch19",
	"ch20", "ch21", "ch22", "ch23",
	"ch24";
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	phy-mode = "rgmii";
	iommus = <&ipmmu_ds0 16>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	can0: can@e6c30000 {
	compatible = "renesas,can-r8a77990",
	"renesas,rcar-gen3-can";
	reg = <0 0xe6c30000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 916>,
	<&cpg CPG_CORE R8A77990_CLK_CANFD>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 916>;
	status = "disabled";
	};

	can1: can@e6c38000 {
	compatible = "renesas,can-r8a77990",
	"renesas,rcar-gen3-can";
	reg = <0 0xe6c38000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 915>,
	<&cpg CPG_CORE R8A77990_CLK_CANFD>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 915>;
	status = "disabled";
	};

	canfd: can@e66c0000 {
	compatible = "renesas,r8a77990-canfd",
	"renesas,rcar-gen3-canfd";
	reg = <0 0xe66c0000 0 0x8000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 914>,
	<&cpg CPG_CORE R8A77990_CLK_CANFD>,
	<&can_clk>;
	clock-names = "fck", "canfd", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 914>;
	status = "disabled";

	channel0 {
	status = "disabled";
	};

	channel1 {
	status = "disabled";
	};
	};

	pwm0: pwm@e6e30000 {
	compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
	reg = <0 0xe6e30000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm1: pwm@e6e31000 {
	compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
	reg = <0 0xe6e31000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm2: pwm@e6e32000 {
	compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
	reg = <0 0xe6e32000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm3: pwm@e6e33000 {
	compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
	reg = <0 0xe6e33000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm4: pwm@e6e34000 {
	compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
	reg = <0 0xe6e34000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm5: pwm@e6e35000 {
	compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
	reg = <0 0xe6e35000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	pwm6: pwm@e6e36000 {
	compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
	reg = <0 0xe6e36000 0 0x8>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	#pwm-cells = <2>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a77990",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e60000 0 64>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 207>,
	<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x51>, <&dmac1 0x50>,
	<&dmac2 0x51>, <&dmac2 0x50>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 207>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a77990",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e68000 0 64>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 206>,
	<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x53>, <&dmac1 0x52>,
	<&dmac2 0x53>, <&dmac2 0x52>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 206>;
	status = "disabled";
	};

	scif2: serial@e6e88000 {
	compatible = "renesas,scif-r8a77990",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e88000 0 64>;
	interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 310>,
	<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x13>, <&dmac1 0x12>,
	<&dmac2 0x13>, <&dmac2 0x12>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 310>;
	status = "disabled";
	};

	scif3: serial@e6c50000 {
	compatible = "renesas,scif-r8a77990",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6c50000 0 64>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 204>,
	<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x57>, <&dmac0 0x56>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 204>;
	status = "disabled";
	};

	scif4: serial@e6c40000 {
	compatible = "renesas,scif-r8a77990",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6c40000 0 64>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 203>,
	<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x59>, <&dmac0 0x58>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 203>;
	status = "disabled";
	};

	scif5: serial@e6f30000 {
	compatible = "renesas,scif-r8a77990",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6f30000 0 64>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 202>,
	<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 202>;
	status = "disabled";
	};

	msiof0: spi@e6e90000 {
	compatible = "renesas,msiof-r8a77990",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6e90000 0 0x0064>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 211>;
	dmas = <&dmac1 0x41>, <&dmac1 0x40>,
	<&dmac2 0x41>, <&dmac2 0x40>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 211>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof1: spi@e6ea0000 {
	compatible = "renesas,msiof-r8a77990",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6ea0000 0 0x0064>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 210>;
	dmas = <&dmac1 0x43>, <&dmac1 0x42>,
	<&dmac2 0x43>, <&dmac2 0x42>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 210>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof2: spi@e6c00000 {
	compatible = "renesas,msiof-r8a77990",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c00000 0 0x0064>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 209>;
	dmas = <&dmac0 0x45>, <&dmac0 0x44>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 209>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof3: spi@e6c10000 {
	compatible = "renesas,msiof-r8a77990",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c10000 0 0x0064>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 208>;
	dmas = <&dmac0 0x47>, <&dmac0 0x46>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 208>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	vin4: video@e6ef4000 {
	compatible = "renesas,vin-r8a77990";
	reg = <0 0xe6ef4000 0 0x1000>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 807>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 807>;
	renesas,id = <4>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin4csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint= <&csi40vin4>;
	};
	};
	};
	};

	vin5: video@e6ef5000 {
	compatible = "renesas,vin-r8a77990";
	reg = <0 0xe6ef5000 0 0x1000>;
	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 806>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 806>;
	renesas,id = <5>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	vin5csi40: endpoint@2 {
	reg = <2>;
	remote-endpoint= <&csi40vin5>;
	};
	};
	};
	};

	rcar_sound: sound@ec500000 {
	/*
	* #sound-dai-cells is required
	*
	* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
	* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
	*/
	/*
	* #clock-cells is required for audio_clkout0/1/2/3
	*
	* clkout : #clock-cells = <0>; <&rcar_sound>;
	* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
	*/
	compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3";
	reg = <0 0xec500000 0 0x1000>, /* SCU */
	<0 0xec5a0000 0 0x100>, /* ADG */
	<0 0xec540000 0 0x1000>, /* SSIU */
	<0 0xec541000 0 0x280>, /* SSI */
	<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
	reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

	clocks = <&cpg CPG_MOD 1005>,
	<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
	<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
	<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
	<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
	<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	<&audio_clk_a>, <&audio_clk_b>,
	<&audio_clk_c>,
	<&cpg CPG_CORE R8A77990_CLK_ZA2>;
	clock-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0",
	"src.9", "src.8", "src.7", "src.6",
	"src.5", "src.4", "src.3", "src.2",
	"src.1", "src.0",
	"mix.1", "mix.0",
	"ctu.1", "ctu.0",
	"dvc.0", "dvc.1",
	"clk_a", "clk_b", "clk_c", "clk_i";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 1005>,
	<&cpg 1006>, <&cpg 1007>,
	<&cpg 1008>, <&cpg 1009>,
	<&cpg 1010>, <&cpg 1011>,
	<&cpg 1012>, <&cpg 1013>,
	<&cpg 1014>, <&cpg 1015>;
	reset-names = "ssi-all",
	"ssi.9", "ssi.8", "ssi.7", "ssi.6",
	"ssi.5", "ssi.4", "ssi.3", "ssi.2",
	"ssi.1", "ssi.0";
	status = "disabled";

	rcar_sound,ctu {
	ctu00: ctu-0 { };
	ctu01: ctu-1 { };
	ctu02: ctu-2 { };
	ctu03: ctu-3 { };
	ctu10: ctu-4 { };
	ctu11: ctu-5 { };
	ctu12: ctu-6 { };
	ctu13: ctu-7 { };
	};

	rcar_sound,dvc {
	dvc0: dvc-0 {
	dmas = <&audma0 0xbc>;
	dma-names = "tx";
	};
	dvc1: dvc-1 {
	dmas = <&audma0 0xbe>;
	dma-names = "tx";
	};
	};

	rcar_sound,mix {
	mix0: mix-0 { };
	mix1: mix-1 { };
	};

	rcar_sound,src {
	src0: src-0 {
	interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x85>, <&audma0 0x9a>;
	dma-names = "rx", "tx";
	};
	src1: src-1 {
	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x87>, <&audma0 0x9c>;
	dma-names = "rx", "tx";
	};
	src2: src-2 {
	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x89>, <&audma0 0x9e>;
	dma-names = "rx", "tx";
	};
	src3: src-3 {
	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8b>, <&audma0 0xa0>;
	dma-names = "rx", "tx";
	};
	src4: src-4 {
	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8d>, <&audma0 0xb0>;
	dma-names = "rx", "tx";
	};
	src5: src-5 {
	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x8f>, <&audma0 0xb2>;
	dma-names = "rx", "tx";
	};
	src6: src-6 {
	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x91>, <&audma0 0xb4>;
	dma-names = "rx", "tx";
	};
	src7: src-7 {
	interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x93>, <&audma0 0xb6>;
	dma-names = "rx", "tx";
	};
	src8: src-8 {
	interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x95>, <&audma0 0xb8>;
	dma-names = "rx", "tx";
	};
	src9: src-9 {
	interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x97>, <&audma0 0xba>;
	dma-names = "rx", "tx";
	};
	};

	rcar_sound,ssi {
	ssi0: ssi-0 {
	interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x01>, <&audma0 0x02>,
	<&audma0 0x15>, <&audma0 0x16>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi1: ssi-1 {
	interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x03>, <&audma0 0x04>,
	<&audma0 0x49>, <&audma0 0x4a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi2: ssi-2 {
	interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x05>, <&audma0 0x06>,
	<&audma0 0x63>, <&audma0 0x64>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi3: ssi-3 {
	interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x07>, <&audma0 0x08>,
	<&audma0 0x6f>, <&audma0 0x70>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi4: ssi-4 {
	interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x09>, <&audma0 0x0a>,
	<&audma0 0x71>, <&audma0 0x72>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi5: ssi-5 {
	interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0b>, <&audma0 0x0c>,
	<&audma0 0x73>, <&audma0 0x74>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi6: ssi-6 {
	interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0d>, <&audma0 0x0e>,
	<&audma0 0x75>, <&audma0 0x76>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi7: ssi-7 {
	interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x0f>, <&audma0 0x10>,
	<&audma0 0x79>, <&audma0 0x7a>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi8: ssi-8 {
	interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x11>, <&audma0 0x12>,
	<&audma0 0x7b>, <&audma0 0x7c>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	ssi9: ssi-9 {
	interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
	dmas = <&audma0 0x13>, <&audma0 0x14>,
	<&audma0 0x7d>, <&audma0 0x7e>;
	dma-names = "rx", "tx", "rxu", "txu";
	};
	};
	};

	audma0: dma-controller@ec700000 {
	compatible = "renesas,dmac-r8a77990",
	"renesas,rcar-dmac";
	reg = <0 0xec700000 0 0x10000>;
	interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15";
	clocks = <&cpg CPG_MOD 502>;
	clock-names = "fck";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 502>;
	#dma-cells = <1>;
	dma-channels = <16>;
	iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
	<&ipmmu_mp 2>, <&ipmmu_mp 3>,
	<&ipmmu_mp 4>, <&ipmmu_mp 5>,
	<&ipmmu_mp 6>, <&ipmmu_mp 7>,
	<&ipmmu_mp 8>, <&ipmmu_mp 9>,
	<&ipmmu_mp 10>, <&ipmmu_mp 11>,
	<&ipmmu_mp 12>, <&ipmmu_mp 13>,
	<&ipmmu_mp 14>, <&ipmmu_mp 15>;
	};

	xhci0: usb@ee000000 {
	compatible = "renesas,xhci-r8a77990",
	"renesas,rcar-gen3-xhci";
	reg = <0 0xee000000 0 0xc00>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	status = "disabled";
	};

	usb3_peri0: usb@ee020000 {
	compatible = "renesas,r8a77990-usb3-peri",
	"renesas,rcar-gen3-usb3-peri";
	reg = <0 0xee020000 0 0x400>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 328>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 328>;
	status = "disabled";
	};

	ohci0: usb@ee080000 {
	compatible = "generic-ohci";
	reg = <0 0xee080000 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	phys = <&usb2_phy0 1>;
	phy-names = "usb";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	status = "disabled";
	};

	ehci0: usb@ee080100 {
	compatible = "generic-ehci";
	reg = <0 0xee080100 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	phys = <&usb2_phy0 2>;
	phy-names = "usb";
	companion = <&ohci0>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	status = "disabled";
	};

	usb2_phy0: usb-phy@ee080200 {
	compatible = "renesas,usb2-phy-r8a77990",
	"renesas,rcar-gen3-usb2-phy";
	reg = <0 0xee080200 0 0x700>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	#phy-cells = <1>;
	status = "disabled";
	};

	sdhi0: sd@ee100000 {
	compatible = "renesas,sdhi-r8a77990",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee100000 0 0x2000>;
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 314>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 314>;
	iommus = <&ipmmu_ds1 32>;
	status = "disabled";
	};

	sdhi1: sd@ee120000 {
	compatible = "renesas,sdhi-r8a77990",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee120000 0 0x2000>;
	interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 313>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 313>;
	iommus = <&ipmmu_ds1 33>;
	status = "disabled";
	};

	sdhi3: sd@ee160000 {
	compatible = "renesas,sdhi-r8a77990",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee160000 0 0x2000>;
	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 311>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 311>;
	iommus = <&ipmmu_ds1 35>;
	status = "disabled";
	};

	gic: interrupt-controller@f1010000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x0 0xf1010000 0 0x1000>,
	<0x0 0xf1020000 0 0x20000>,
	<0x0 0xf1040000 0 0x20000>,
	<0x0 0xf1060000 0 0x20000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	pciec0: pcie@fe000000 {
	compatible = "renesas,pcie-r8a77990",
	"renesas,pcie-rcar-gen3";
	reg = <0 0xfe000000 0 0x80000>;
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x00 0xff>;
	device_type = "pci";
	ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
	<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
	<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
	<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
	/* Map all possible DDR as inbound ranges */
	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
	clock-names = "pcie", "pcie_bus";
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 319>;
	status = "disabled";
	};

	vspb0: vsp@fe960000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe960000 0 0x8000>;
	interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 626>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 626>;
	renesas,fcp = <&fcpvb0>;
	};

	fcpvb0: fcp@fe96f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe96f000 0 0x200>;
	clocks = <&cpg CPG_MOD 607>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 607>;
	iommus = <&ipmmu_vp0 5>;
	};

	vspi0: vsp@fe9a0000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe9a0000 0 0x8000>;
	interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 631>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 631>;
	renesas,fcp = <&fcpvi0>;
	};

	fcpvi0: fcp@fe9af000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe9af000 0 0x200>;
	clocks = <&cpg CPG_MOD 611>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 611>;
	iommus = <&ipmmu_vp0 8>;
	};

	vspd0: vsp@fea20000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea20000 0 0x7000>;
	interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 623>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 623>;
	renesas,fcp = <&fcpvd0>;
	};

	fcpvd0: fcp@fea27000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea27000 0 0x200>;
	clocks = <&cpg CPG_MOD 603>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 603>;
	iommus = <&ipmmu_vi0 8>;
	};

	vspd1: vsp@fea28000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea28000 0 0x7000>;
	interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 622>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 622>;
	renesas,fcp = <&fcpvd1>;
	};

	fcpvd1: fcp@fea2f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea2f000 0 0x200>;
	clocks = <&cpg CPG_MOD 602>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 602>;
	iommus = <&ipmmu_vi0 9>;
	};

	cmm0: cmm@fea40000 {
	compatible = "renesas,r8a77990-cmm",
	"renesas,rcar-gen3-cmm";
	reg = <0 0xfea40000 0 0x1000>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	clocks = <&cpg CPG_MOD 711>;
	resets = <&cpg 711>;
	};

	cmm1: cmm@fea50000 {
	compatible = "renesas,r8a77990-cmm",
	"renesas,rcar-gen3-cmm";
	reg = <0 0xfea50000 0 0x1000>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	clocks = <&cpg CPG_MOD 710>;
	resets = <&cpg 710>;
	};

	csi40: csi2@feaa0000 {
	compatible = "renesas,r8a77990-csi2";
	reg = <0 0xfeaa0000 0 0x10000>;
	interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 716>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 716>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
	#address-cells = <1>;
	#size-cells = <0>;

	reg = <1>;

	csi40vin4: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vin4csi40>;
	};
	csi40vin5: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vin5csi40>;
	};
	};
	};
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a77990";
	reg = <0 0xfeb00000 0 0x40000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&cpg CPG_MOD 724>,
	- <&cpg CPG_MOD 723>;
	+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
	clock-names = "du.0", "du.1";
	resets = <&cpg 724>;
	reset-names = "du.0";

	renesas,cmms = <&cmm0>, <&cmm1>;
	- vsps = <&vspd0 0>, <&vspd1 0>;
	+ renesas,vsps = <&vspd0 0>, <&vspd1 0>;

	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb: endpoint {
	};
	};

	port@1 {
	reg = <1>;
	du_out_lvds0: endpoint {
	remote-endpoint = <&lvds0_in>;
	};
	};

	port@2 {
	reg = <2>;
	du_out_lvds1: endpoint {
	remote-endpoint = <&lvds1_in>;
	};
	};
	};
	};

	lvds0: lvds-encoder@feb90000 {
	compatible = "renesas,r8a77990-lvds";
	reg = <0 0xfeb90000 0 0x20>;
	clocks = <&cpg CPG_MOD 727>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 727>;
	status = "disabled";

	renesas,companion = <&lvds1>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds0_in: endpoint {
	remote-endpoint = <&du_out_lvds0>;
	};
	};

	port@1 {
	reg = <1>;
	lvds0_out: endpoint {
	};
	};
	};
	};

	lvds1: lvds-encoder@feb90100 {
	compatible = "renesas,r8a77990-lvds";
	reg = <0 0xfeb90100 0 0x20>;
	clocks = <&cpg CPG_MOD 727>;
	power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	resets = <&cpg 726>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds1_in: endpoint {
	remote-endpoint = <&du_out_lvds1>;
	};
	};

	port@1 {
	reg = <1>;
	lvds1_out: endpoint {
	};
	};
	};
	};

	prr: chipid@fff00044 {
	compatible = "renesas,prr";
	reg = <0 0xfff00044 0 4>;
	};
	};

	thermal-zones {
	cpu-thermal {
	polling-delay-passive = <250>;
	polling-delay = <0>;
	thermal-sensors = <&thermal 0>;
	sustainable-power = <717>;

	cooling-maps {
	map0 {
	trip = <&target>;
	cooling-device = <&a53_0 0 2>;
	contribution = <1024>;
	};
	};

	trips {
	sensor1_crit: sensor1-crit {
	temperature = <120000>;
	hysteresis = <2000>;
	type = "critical";
	};

	target: trip-point1 {
	temperature = <100000>;
	hysteresis = <2000>;
	type = "passive";
	};
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a77995-draak.dts b/sys/gnu/dts/arm64/renesas/r8a77995-draak.dts
	index 67634cb01d6b..79c73a99d2fe 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a77995-draak.dts
	+++ b/sys/gnu/dts/arm64/renesas/r8a77995-draak.dts
	@@ -1,528 +1,526 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the Draak board
	*
	* Copyright (C) 2016-2018 Renesas Electronics Corp.
	* Copyright (C) 2017 Glider bvba
	*/

	/dts-v1/;
	#include "r8a77995.dtsi"
	#include <dt-bindings/gpio/gpio.h>

	/ {
	model = "Renesas Draak board based on r8a77995";
	compatible = "renesas,draak", "renesas,r8a77995";

	aliases {
	serial0 = &scif2;
	ethernet0 = &avb;
	};

	backlight: backlight {
	compatible = "pwm-backlight";
	pwms = <&pwm1 0 50000>;

	brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
	default-brightness-level = <10>;

	power-supply = <&reg_12p0v>;
	enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
	};

	chosen {
	bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
	stdout-path = "serial0:115200n8";
	};

	composite-in {
	compatible = "composite-video-connector";

	port {
	composite_con_in: endpoint {
	remote-endpoint = <&adv7180_in>;
	};
	};
	};

	hdmi-in {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con_in: endpoint {
	remote-endpoint = <&adv7612_in>;
	};
	};
	};

	hdmi-out {
	compatible = "hdmi-connector";
	type = "a";

	port {
	hdmi_con_out: endpoint {
	remote-endpoint = <&adv7511_out>;
	};
	};
	};

	lvds-decoder {
	compatible = "thine,thc63lvd1024";
	vcc-supply = <&reg_3p3v>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	thc63lvd1024_in: endpoint {
	remote-endpoint = <&lvds0_out>;
	};
	};

	port@2 {
	reg = <2>;
	thc63lvd1024_out: endpoint {
	remote-endpoint = <&adv7511_in>;
	};
	};
	};
	};

	memory@48000000 {
	device_type = "memory";
	/* first 128MB is reserved for secure area. */
	reg = <0x0 0x48000000 0x0 0x18000000>;
	};

	reg_1p8v: regulator-1p8v {
	compatible = "regulator-fixed";
	regulator-name = "fixed-1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
	compatible = "regulator-fixed";
	regulator-name = "fixed-3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_12p0v: regulator-12p0v {
	compatible = "regulator-fixed";
	regulator-name = "D12.0V";
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vga {
	compatible = "vga-connector";

	port {
	vga_in: endpoint {
	remote-endpoint = <&adv7123_out>;
	};
	};
	};

	vga-encoder {
	compatible = "adi,adv7123";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7123_in: endpoint {
	remote-endpoint = <&du_out_rgb>;
	};
	};
	port@1 {
	reg = <1>;
	adv7123_out: endpoint {
	remote-endpoint = <&vga_in>;
	};
	};
	};
	};

	x12_clk: x12 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <74250000>;
	};
	};

	&avb {
	pinctrl-0 = <&avb0_pins>;
	pinctrl-names = "default";
	renesas,no-ether-link;
	phy-handle = <&phy0>;
	status = "okay";

	phy0: ethernet-phy@0 {
	rxc-skew-ps = <1500>;
	reg = <0>;
	interrupt-parent = <&gpio5>;
	interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
	/*
	* TX clock internal delay mode is required for reliable
	* 1Gbps communication using the KSZ9031RNX phy present on
	* the Draak board, however, TX clock internal delay mode
	* isn't supported on r8a77995. Thus, limit speed to
	* 100Mbps for reliable communication.
	*/
	max-speed = <100>;
	};
	};

	&can0 {
	pinctrl-0 = <&can0_pins>;
	pinctrl-names = "default";
	status = "okay";
	};

	&can1 {
	pinctrl-0 = <&can1_pins>;
	pinctrl-names = "default";
	status = "okay";
	};

	&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";
	status = "okay";

	clocks = <&cpg CPG_MOD 724>,
	<&cpg CPG_MOD 723>,
	<&x12_clk>;
	clock-names = "du.0", "du.1", "dclkin.0";

	ports {
	port@0 {
	endpoint {
	remote-endpoint = <&adv7123_in>;
	};
	};
	};
	};

	&ehci0 {
	dr_mode = "host";
	status = "okay";
	};

	&extal_clk {
	clock-frequency = <48000000>;
	};

	&hsusb {
	dr_mode = "host";
	status = "okay";
	};

	&i2c0 {
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "default";
	status = "okay";

	composite-in@20 {
	compatible = "adi,adv7180cp";
	reg = <0x20>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7180_in: endpoint {
	remote-endpoint = <&composite_con_in>;
	};
	};

	port@3 {
	reg = <3>;

	/*
	* The VIN4 video input path is shared between
	* CVBS and HDMI inputs through SW[49-53]
	* switches.
	*
	* CVBS is the default selection, link it to
	* VIN4 here.
	*/
	adv7180_out: endpoint {
	remote-endpoint = <&vin4_in>;
	};
	};
	};

	};

	hdmi-encoder@39 {
	compatible = "adi,adv7511w";
	- reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
	- reg-names = "main", "edid", "packet", "cec";
	+ reg = <0x39>, <0x3f>, <0x3c>, <0x38>;
	+ reg-names = "main", "edid", "cec", "packet";
	interrupt-parent = <&gpio1>;
	interrupts = <28 IRQ_TYPE_LEVEL_LOW>;

	/* Depends on LVDS */
	max-clock = <135000000>;
	min-vrefresh = <50>;

	adi,input-depth = <8>;
	adi,input-colorspace = "rgb";
	adi,input-clock = "1x";
	- adi,input-style = <1>;
	- adi,input-justification = "evenly";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	adv7511_in: endpoint {
	remote-endpoint = <&thc63lvd1024_out>;
	};
	};

	port@1 {
	reg = <1>;
	adv7511_out: endpoint {
	remote-endpoint = <&hdmi_con_out>;
	};
	};
	};
	};

	hdmi-decoder@4c {
	compatible = "adi,adv7612";
	reg = <0x4c>;
	default-input = <0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	adv7612_in: endpoint {
	remote-endpoint = <&hdmi_con_in>;
	};
	};

	port@2 {
	reg = <2>;

	/*
	* The VIN4 video input path is shared between
	* CVBS and HDMI inputs through SW[49-53]
	* switches.
	*
	* CVBS is the default selection, leave HDMI
	* not connected here.
	*/
	adv7612_out: endpoint {
	pclk-sample = <0>;
	hsync-active = <0>;
	vsync-active = <0>;
	};
	};
	};
	};

	eeprom@50 {
	compatible = "rohm,br24t01", "atmel,24c01";
	reg = <0x50>;
	pagesize = <8>;
	};
	};

	&i2c1 {
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-names = "default";
	status = "okay";
	};

	&lvds0 {
	status = "okay";

	clocks = <&cpg CPG_MOD 727>,
	<&x12_clk>,
	<&extal_clk>;
	clock-names = "fck", "dclkin.0", "extal";

	ports {
	port@1 {
	lvds0_out: endpoint {
	remote-endpoint = <&thc63lvd1024_in>;
	};
	};
	};
	};

	&lvds1 {
	/*
	* Even though the LVDS1 output is not connected, the encoder must be
	* enabled to supply a pixel clock to the DU for the DPAD output when
	* LVDS0 is in use.
	*/
	status = "okay";

	clocks = <&cpg CPG_MOD 727>,
	<&x12_clk>,
	<&extal_clk>;
	clock-names = "fck", "dclkin.0", "extal";
	};

	&ohci0 {
	dr_mode = "host";
	status = "okay";
	};

	&pfc {
	avb0_pins: avb {
	mux {
	groups = "avb0_link", "avb0_mdio", "avb0_mii";
	function = "avb0";
	};
	};

	can0_pins: can0 {
	groups = "can0_data_a";
	function = "can0";
	};

	can1_pins: can1 {
	groups = "can1_data_a";
	function = "can1";
	};

	du_pins: du {
	groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
	function = "du";
	};

	i2c0_pins: i2c0 {
	groups = "i2c0";
	function = "i2c0";
	};

	i2c1_pins: i2c1 {
	groups = "i2c1";
	function = "i2c1";
	};

	pwm0_pins: pwm0 {
	groups = "pwm0_c";
	function = "pwm0";
	};

	pwm1_pins: pwm1 {
	groups = "pwm1_c";
	function = "pwm1";
	};

	scif2_pins: scif2 {
	groups = "scif2_data";
	function = "scif2";
	};

	sdhi2_pins: sd2 {
	groups = "mmc_data8", "mmc_ctrl";
	function = "mmc";
	power-source = <1800>;
	};

	sdhi2_pins_uhs: sd2_uhs {
	groups = "mmc_data8", "mmc_ctrl";
	function = "mmc";
	power-source = <1800>;
	};

	usb0_pins: usb0 {
	groups = "usb0";
	function = "usb0";
	};

	vin4_pins_cvbs: vin4 {
	groups = "vin4_data8", "vin4_sync", "vin4_clk";
	function = "vin4";
	};
	};

	&pwm0 {
	pinctrl-0 = <&pwm0_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&pwm1 {
	pinctrl-0 = <&pwm1_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&rwdt {
	timeout-sec = <60>;
	status = "okay";
	};

	&scif2 {
	pinctrl-0 = <&scif2_pins>;
	pinctrl-names = "default";

	status = "okay";
	};

	&sdhi2 {
	/* used for on-board eMMC */
	pinctrl-0 = <&sdhi2_pins>;
	pinctrl-1 = <&sdhi2_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_1p8v>;
	bus-width = <8>;
	mmc-hs200-1_8v;
	non-removable;
	status = "okay";
	};

	&usb2_phy0 {
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";

	renesas,no-otg-pins;
	status = "okay";
	};

	&vin4 {
	pinctrl-0 = <&vin4_pins_cvbs>;
	pinctrl-names = "default";

	status = "okay";

	ports {
	port {
	vin4_in: endpoint {
	remote-endpoint = <&adv7180_out>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/renesas/r8a77995.dtsi b/sys/gnu/dts/arm64/renesas/r8a77995.dtsi
	index 9503007c34c0..e8d2290fe79d 100644
	--- a/sys/gnu/dts/arm64/renesas/r8a77995.dtsi
	+++ b/sys/gnu/dts/arm64/renesas/r8a77995.dtsi
	@@ -1,1145 +1,1153 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for the R-Car D3 (R8A77995) SoC
	*
	* Copyright (C) 2016 Renesas Electronics Corp.
	* Copyright (C) 2017 Glider bvba
	*/

	#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/power/r8a77995-sysc.h>

	/ {
	compatible = "renesas,r8a77995";
	#address-cells = <2>;
	#size-cells = <2>;

	/* External CAN clock - to be overridden by boards that provide it */
	can_clk: can {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	a53_0: cpu@0 {
	compatible = "arm,cortex-a53";
	reg = <0x0>;
	device_type = "cpu";
	power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
	next-level-cache = <&L2_CA53>;
	enable-method = "psci";
	};

	L2_CA53: cache-controller-1 {
	compatible = "cache";
	power-domains = <&sysc R8A77995_PD_CA53_SCU>;
	cache-unified;
	cache-level = <2>;
	};
	};

	extal_clk: extal {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board */
	clock-frequency = <0>;
	};

	pmu_a53 {
	compatible = "arm,cortex-a53-pmu";
	interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	};

	psci {
	compatible = "arm,psci-1.0", "arm,psci-0.2";
	method = "smc";
	};

	scif_clk: scif {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <0>;
	};

	soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	rwdt: watchdog@e6020000 {
	compatible = "renesas,r8a77995-wdt",
	"renesas,rcar-gen3-wdt";
	reg = <0 0xe6020000 0 0x0c>;
	clocks = <&cpg CPG_MOD 402>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 402>;
	status = "disabled";
	};

	gpio0: gpio@e6050000 {
	compatible = "renesas,gpio-r8a77995",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6050000 0 0x50>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 0 9>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 912>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 912>;
	};

	gpio1: gpio@e6051000 {
	compatible = "renesas,gpio-r8a77995",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6051000 0 0x50>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 32 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 911>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 911>;
	};

	gpio2: gpio@e6052000 {
	compatible = "renesas,gpio-r8a77995",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6052000 0 0x50>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 64 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 910>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 910>;
	};

	gpio3: gpio@e6053000 {
	compatible = "renesas,gpio-r8a77995",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6053000 0 0x50>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 96 10>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 909>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 909>;
	};

	gpio4: gpio@e6054000 {
	compatible = "renesas,gpio-r8a77995",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6054000 0 0x50>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 128 32>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 908>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 908>;
	};

	gpio5: gpio@e6055000 {
	compatible = "renesas,gpio-r8a77995",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055000 0 0x50>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 160 21>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 907>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 907>;
	};

	gpio6: gpio@e6055400 {
	compatible = "renesas,gpio-r8a77995",
	"renesas,rcar-gen3-gpio";
	reg = <0 0xe6055400 0 0x50>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	gpio-ranges = <&pfc 0 192 14>;
	#interrupt-cells = <2>;
	interrupt-controller;
	clocks = <&cpg CPG_MOD 906>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 906>;
	};

	pfc: pin-controller@e6060000 {
	compatible = "renesas,pfc-r8a77995";
	reg = <0 0xe6060000 0 0x508>;
	};

	cpg: clock-controller@e6150000 {
	compatible = "renesas,r8a77995-cpg-mssr";
	reg = <0 0xe6150000 0 0x1000>;
	clocks = <&extal_clk>;
	clock-names = "extal";
	#clock-cells = <2>;
	#power-domain-cells = <0>;
	#reset-cells = <1>;
	};

	rst: reset-controller@e6160000 {
	compatible = "renesas,r8a77995-rst";
	reg = <0 0xe6160000 0 0x0200>;
	};

	sysc: system-controller@e6180000 {
	compatible = "renesas,r8a77995-sysc";
	reg = <0 0xe6180000 0 0x0400>;
	#power-domain-cells = <1>;
	};

	thermal: thermal@e6190000 {
	compatible = "renesas,thermal-r8a77995";
	reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 522>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 522>;
	#thermal-sensor-cells = <0>;
	};

	intc_ex: interrupt-controller@e61c0000 {
	compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
	#interrupt-cells = <2>;
	interrupt-controller;
	reg = <0 0xe61c0000 0 0x200>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 407>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 407>;
	};

	i2c0: i2c@e6500000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77995",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6500000 0 0x40>;
	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 931>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 931>;
	dmas = <&dmac1 0x91>, <&dmac1 0x90>,
	<&dmac2 0x91>, <&dmac2 0x90>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c1: i2c@e6508000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77995",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6508000 0 0x40>;
	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 930>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 930>;
	dmas = <&dmac1 0x93>, <&dmac1 0x92>,
	<&dmac2 0x93>, <&dmac2 0x92>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c2: i2c@e6510000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77995",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe6510000 0 0x40>;
	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 929>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 929>;
	dmas = <&dmac1 0x95>, <&dmac1 0x94>,
	<&dmac2 0x95>, <&dmac2 0x94>;
	dma-names = "tx", "rx", "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	i2c3: i2c@e66d0000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "renesas,i2c-r8a77995",
	"renesas,rcar-gen3-i2c";
	reg = <0 0xe66d0000 0 0x40>;
	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 928>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 928>;
	dmas = <&dmac0 0x97>, <&dmac0 0x96>;
	dma-names = "tx", "rx";
	i2c-scl-internal-delay-ns = <6>;
	status = "disabled";
	};

	hscif0: serial@e6540000 {
	compatible = "renesas,hscif-r8a77995",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe6540000 0 0x60>;
	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 520>,
	<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x31>, <&dmac1 0x30>,
	<&dmac2 0x31>, <&dmac2 0x30>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 520>;
	status = "disabled";
	};

	hscif3: serial@e66a0000 {
	compatible = "renesas,hscif-r8a77995",
	"renesas,rcar-gen3-hscif",
	"renesas,hscif";
	reg = <0 0xe66a0000 0 0x60>;
	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 517>,
	<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x37>, <&dmac0 0x36>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 517>;
	status = "disabled";
	};

	hsusb: usb@e6590000 {
	compatible = "renesas,usbhs-r8a77995",
	"renesas,rcar-gen3-usbhs";
	reg = <0 0xe6590000 0 0x200>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
	dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
	<&usb_dmac1 0>, <&usb_dmac1 1>;
	dma-names = "ch0", "ch1", "ch2", "ch3";
	renesas,buswait = <11>;
	phys = <&usb2_phy0 3>;
	phy-names = "usb";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 704>, <&cpg 703>;
	status = "disabled";
	};

	usb_dmac0: dma-controller@e65a0000 {
	compatible = "renesas,r8a77995-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65a0000 0 0x100>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 330>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 330>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	usb_dmac1: dma-controller@e65b0000 {
	compatible = "renesas,r8a77995-usb-dmac",
	"renesas,usb-dmac";
	reg = <0 0xe65b0000 0 0x100>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1";
	clocks = <&cpg CPG_MOD 331>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 331>;
	#dma-cells = <1>;
	dma-channels = <2>;
	};

	+ arm_cc630p: crypto@e6601000 {
	+ compatible = "arm,cryptocell-630p-ree";
	+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	+ reg = <0x0 0xe6601000 0 0x1000>;
	+ clocks = <&cpg CPG_MOD 229>;
	+ resets = <&cpg 229>;
	+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	+ };
	+
	canfd: can@e66c0000 {
	compatible = "renesas,r8a77995-canfd",
	"renesas,rcar-gen3-canfd";
	reg = <0 0xe66c0000 0 0x8000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 914>,
	<&cpg CPG_CORE R8A77995_CLK_CANFD>,
	<&can_clk>;
	clock-names = "fck", "canfd", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 914>;
	status = "disabled";

	channel0 {
	status = "disabled";
	};

	channel1 {
	status = "disabled";
	};
	};

	dmac0: dma-controller@e6700000 {
	compatible = "renesas,dmac-r8a77995",
	"renesas,rcar-dmac";
	reg = <0 0xe6700000 0 0x10000>;
	interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7";
	clocks = <&cpg CPG_MOD 219>;
	clock-names = "fck";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 219>;
	#dma-cells = <1>;
	dma-channels = <8>;
	iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
	<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
	<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
	<&ipmmu_ds0 6>, <&ipmmu_ds0 7>;
	};

	dmac1: dma-controller@e7300000 {
	compatible = "renesas,dmac-r8a77995",
	"renesas,rcar-dmac";
	reg = <0 0xe7300000 0 0x10000>;
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7";
	clocks = <&cpg CPG_MOD 218>;
	clock-names = "fck";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 218>;
	#dma-cells = <1>;
	dma-channels = <8>;
	iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
	<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
	<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
	<&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
	};

	dmac2: dma-controller@e7310000 {
	compatible = "renesas,dmac-r8a77995",
	"renesas,rcar-dmac";
	reg = <0 0xe7310000 0 0x10000>;
	interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "error",
	"ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7";
	clocks = <&cpg CPG_MOD 217>;
	clock-names = "fck";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 217>;
	#dma-cells = <1>;
	dma-channels = <8>;
	iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
	<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
	<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
	<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
	};

	ipmmu_ds0: mmu@e6740000 {
	compatible = "renesas,ipmmu-r8a77995";
	reg = <0 0xe6740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 0>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_ds1: mmu@e7740000 {
	compatible = "renesas,ipmmu-r8a77995";
	reg = <0 0xe7740000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 1>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_hc: mmu@e6570000 {
	compatible = "renesas,ipmmu-r8a77995";
	reg = <0 0xe6570000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 2>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_mm: mmu@e67b0000 {
	compatible = "renesas,ipmmu-r8a77995";
	reg = <0 0xe67b0000 0 0x1000>;
	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_mp: mmu@ec670000 {
	compatible = "renesas,ipmmu-r8a77995";
	reg = <0 0xec670000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 4>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_pv0: mmu@fd800000 {
	compatible = "renesas,ipmmu-r8a77995";
	reg = <0 0xfd800000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 6>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_rt: mmu@ffc80000 {
	compatible = "renesas,ipmmu-r8a77995";
	reg = <0 0xffc80000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 10>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vc0: mmu@fe6b0000 {
	compatible = "renesas,ipmmu-r8a77995";
	reg = <0 0xfe6b0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 12>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vi0: mmu@febd0000 {
	compatible = "renesas,ipmmu-r8a77995";
	reg = <0 0xfebd0000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 14>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	ipmmu_vp0: mmu@fe990000 {
	compatible = "renesas,ipmmu-r8a77995";
	reg = <0 0xfe990000 0 0x1000>;
	renesas,ipmmu-main = <&ipmmu_mm 16>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	#iommu-cells = <1>;
	};

	avb: ethernet@e6800000 {
	compatible = "renesas,etheravb-r8a77995",
	"renesas,etheravb-rcar-gen3";
	reg = <0 0xe6800000 0 0x800>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "ch0", "ch1", "ch2", "ch3",
	"ch4", "ch5", "ch6", "ch7",
	"ch8", "ch9", "ch10", "ch11",
	"ch12", "ch13", "ch14", "ch15",
	"ch16", "ch17", "ch18", "ch19",
	"ch20", "ch21", "ch22", "ch23",
	"ch24";
	clocks = <&cpg CPG_MOD 812>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 812>;
	phy-mode = "rgmii";
	iommus = <&ipmmu_ds0 16>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	can0: can@e6c30000 {
	compatible = "renesas,can-r8a77995",
	"renesas,rcar-gen3-can";
	reg = <0 0xe6c30000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 916>,
	<&cpg CPG_CORE R8A77995_CLK_CANFD>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 916>;
	status = "disabled";
	};

	can1: can@e6c38000 {
	compatible = "renesas,can-r8a77995",
	"renesas,rcar-gen3-can";
	reg = <0 0xe6c38000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 915>,
	<&cpg CPG_CORE R8A77995_CLK_CANFD>,
	<&can_clk>;
	clock-names = "clkp1", "clkp2", "can_clk";
	assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
	assigned-clock-rates = <40000000>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 915>;
	status = "disabled";
	};

	pwm0: pwm@e6e30000 {
	compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
	reg = <0 0xe6e30000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	status = "disabled";
	};

	pwm1: pwm@e6e31000 {
	compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
	reg = <0 0xe6e31000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	status = "disabled";
	};

	pwm2: pwm@e6e32000 {
	compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
	reg = <0 0xe6e32000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	status = "disabled";
	};

	pwm3: pwm@e6e33000 {
	compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
	reg = <0 0xe6e33000 0 0x8>;
	#pwm-cells = <2>;
	clocks = <&cpg CPG_MOD 523>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 523>;
	status = "disabled";
	};

	scif0: serial@e6e60000 {
	compatible = "renesas,scif-r8a77995",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e60000 0 64>;
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 207>,
	<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x51>, <&dmac1 0x50>,
	<&dmac2 0x51>, <&dmac2 0x50>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 207>;
	status = "disabled";
	};

	scif1: serial@e6e68000 {
	compatible = "renesas,scif-r8a77995",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e68000 0 64>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 206>,
	<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x53>, <&dmac1 0x52>,
	<&dmac2 0x53>, <&dmac2 0x52>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 206>;
	status = "disabled";
	};

	scif2: serial@e6e88000 {
	compatible = "renesas,scif-r8a77995",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6e88000 0 64>;
	interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 310>,
	<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x13>, <&dmac1 0x12>,
	<&dmac2 0x13>, <&dmac2 0x12>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 310>;
	status = "disabled";
	};

	scif3: serial@e6c50000 {
	compatible = "renesas,scif-r8a77995",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6c50000 0 64>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 204>,
	<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x57>, <&dmac0 0x56>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 204>;
	status = "disabled";
	};

	scif4: serial@e6c40000 {
	compatible = "renesas,scif-r8a77995",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6c40000 0 64>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 203>,
	<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac0 0x59>, <&dmac0 0x58>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 203>;
	status = "disabled";
	};

	scif5: serial@e6f30000 {
	compatible = "renesas,scif-r8a77995",
	"renesas,rcar-gen3-scif", "renesas,scif";
	reg = <0 0xe6f30000 0 64>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 202>,
	<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
	<&scif_clk>;
	clock-names = "fck", "brg_int", "scif_clk";
	dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
	<&dmac2 0x5b>, <&dmac2 0x5a>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 202>;
	status = "disabled";
	};

	msiof0: spi@e6e90000 {
	compatible = "renesas,msiof-r8a77995",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6e90000 0 0x64>;
	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 211>;
	dmas = <&dmac1 0x41>, <&dmac1 0x40>,
	<&dmac2 0x41>, <&dmac2 0x40>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 211>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof1: spi@e6ea0000 {
	compatible = "renesas,msiof-r8a77995",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6ea0000 0 0x64>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 210>;
	dmas = <&dmac1 0x43>, <&dmac1 0x42>,
	<&dmac2 0x43>, <&dmac2 0x42>;
	dma-names = "tx", "rx", "tx", "rx";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 210>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof2: spi@e6c00000 {
	compatible = "renesas,msiof-r8a77995",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c00000 0 0x64>;
	interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 209>;
	dmas = <&dmac0 0x45>, <&dmac0 0x44>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 209>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	msiof3: spi@e6c10000 {
	compatible = "renesas,msiof-r8a77995",
	"renesas,rcar-gen3-msiof";
	reg = <0 0xe6c10000 0 0x64>;
	interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 208>;
	dmas = <&dmac0 0x47>, <&dmac0 0x46>;
	dma-names = "tx", "rx";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 208>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	vin4: video@e6ef4000 {
	compatible = "renesas,vin-r8a77995";
	reg = <0 0xe6ef4000 0 0x1000>;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 807>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 807>;
	renesas,id = <4>;
	status = "disabled";
	};

	ohci0: usb@ee080000 {
	compatible = "generic-ohci";
	reg = <0 0xee080000 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	phys = <&usb2_phy0 1>;
	phy-names = "usb";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	status = "disabled";
	};

	ehci0: usb@ee080100 {
	compatible = "generic-ehci";
	reg = <0 0xee080100 0 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	phys = <&usb2_phy0 2>;
	phy-names = "usb";
	companion = <&ohci0>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	status = "disabled";
	};

	usb2_phy0: usb-phy@ee080200 {
	compatible = "renesas,usb2-phy-r8a77995",
	"renesas,rcar-gen3-usb2-phy";
	reg = <0 0xee080200 0 0x700>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 703>, <&cpg 704>;
	#phy-cells = <1>;
	status = "disabled";
	};

	sdhi2: sd@ee140000 {
	compatible = "renesas,sdhi-r8a77995",
	"renesas,rcar-gen3-sdhi";
	reg = <0 0xee140000 0 0x2000>;
	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 312>;
	max-frequency = <200000000>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 312>;
	iommus = <&ipmmu_ds1 34>;
	status = "disabled";
	};

	gic: interrupt-controller@f1010000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x0 0xf1010000 0 0x1000>,
	<0x0 0xf1020000 0 0x20000>,
	<0x0 0xf1040000 0 0x20000>,
	<0x0 0xf1060000 0 0x20000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&cpg CPG_MOD 408>;
	clock-names = "clk";
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 408>;
	};

	vspbs: vsp@fe960000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfe960000 0 0x8000>;
	interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 627>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 627>;
	renesas,fcp = <&fcpvb0>;
	};

	vspd0: vsp@fea20000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea20000 0 0x5000>;
	interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 623>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 623>;
	renesas,fcp = <&fcpvd0>;
	};

	vspd1: vsp@fea28000 {
	compatible = "renesas,vsp2";
	reg = <0 0xfea28000 0 0x5000>;
	interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD 622>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 622>;
	renesas,fcp = <&fcpvd1>;
	};

	fcpvb0: fcp@fe96f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfe96f000 0 0x200>;
	clocks = <&cpg CPG_MOD 607>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 607>;
	iommus = <&ipmmu_vp0 5>;
	};

	fcpvd0: fcp@fea27000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea27000 0 0x200>;
	clocks = <&cpg CPG_MOD 603>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 603>;
	iommus = <&ipmmu_vi0 8>;
	};

	fcpvd1: fcp@fea2f000 {
	compatible = "renesas,fcpv";
	reg = <0 0xfea2f000 0 0x200>;
	clocks = <&cpg CPG_MOD 602>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 602>;
	iommus = <&ipmmu_vi0 9>;
	};

	cmm0: cmm@fea40000 {
	compatible = "renesas,r8a77995-cmm",
	"renesas,rcar-gen3-cmm";
	reg = <0 0xfea40000 0 0x1000>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	clocks = <&cpg CPG_MOD 711>;
	resets = <&cpg 711>;
	};

	cmm1: cmm@fea50000 {
	compatible = "renesas,r8a77995-cmm",
	"renesas,rcar-gen3-cmm";
	reg = <0 0xfea50000 0 0x1000>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	clocks = <&cpg CPG_MOD 710>;
	resets = <&cpg 710>;
	};

	du: display@feb00000 {
	compatible = "renesas,du-r8a77995";
	reg = <0 0xfeb00000 0 0x40000>;
	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
	- clocks = <&cpg CPG_MOD 724>,
	- <&cpg CPG_MOD 723>;
	+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
	clock-names = "du.0", "du.1";
	resets = <&cpg 724>;
	reset-names = "du.0";

	renesas,cmms = <&cmm0>, <&cmm1>;
	- vsps = <&vspd0 0>, <&vspd1 0>;
	+ renesas,vsps = <&vspd0 0>, <&vspd1 0>;

	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	du_out_rgb: endpoint {
	};
	};

	port@1 {
	reg = <1>;
	du_out_lvds0: endpoint {
	remote-endpoint = <&lvds0_in>;
	};
	};

	port@2 {
	reg = <2>;
	du_out_lvds1: endpoint {
	remote-endpoint = <&lvds1_in>;
	};
	};
	};
	};

	lvds0: lvds-encoder@feb90000 {
	compatible = "renesas,r8a77995-lvds";
	reg = <0 0xfeb90000 0 0x20>;
	clocks = <&cpg CPG_MOD 727>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 727>;
	status = "disabled";

	renesas,companion = <&lvds1>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds0_in: endpoint {
	remote-endpoint = <&du_out_lvds0>;
	};
	};

	port@1 {
	reg = <1>;
	lvds0_out: endpoint {
	};
	};
	};
	};

	lvds1: lvds-encoder@feb90100 {
	compatible = "renesas,r8a77995-lvds";
	reg = <0 0xfeb90100 0 0x20>;
	clocks = <&cpg CPG_MOD 727>;
	power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
	resets = <&cpg 726>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	lvds1_in: endpoint {
	remote-endpoint = <&du_out_lvds1>;
	};
	};

	port@1 {
	reg = <1>;
	lvds1_out: endpoint {
	};
	};
	};
	};

	prr: chipid@fff00044 {
	compatible = "renesas,prr";
	reg = <0 0xfff00044 0 4>;
	};
	};

	thermal-zones {
	cpu_thermal: cpu-thermal {
	polling-delay-passive = <250>;
	polling-delay = <1000>;
	thermal-sensors = <&thermal>;

	cooling-maps {
	};

	trips {
	cpu-crit {
	temperature = <120000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/rockchip/px30.dtsi b/sys/gnu/dts/arm64/rockchip/px30.dtsi
	index 75908c587511..adc9b8bf5eaa 100644
	--- a/sys/gnu/dts/arm64/rockchip/px30.dtsi
	+++ b/sys/gnu/dts/arm64/rockchip/px30.dtsi
	@@ -1,2237 +1,2235 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
	*/

	#include <dt-bindings/clock/px30-cru.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/pinctrl/rockchip.h>
	#include <dt-bindings/power/px30-power.h>
	#include <dt-bindings/soc/rockchip,boot-mode.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	compatible = "rockchip,px30";

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	ethernet0 = &gmac;
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	serial0 = &uart0;
	serial1 = &uart1;
	serial2 = &uart2;
	serial3 = &uart3;
	serial4 = &uart4;
	serial5 = &uart5;
	spi0 = &spi0;
	spi1 = &spi1;
	};

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a35";
	reg = <0x0 0x0>;
	enable-method = "psci";
	clocks = <&cru ARMCLK>;
	#cooling-cells = <2>;
	cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	dynamic-power-coefficient = <90>;
	operating-points-v2 = <&cpu0_opp_table>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a35";
	reg = <0x0 0x1>;
	enable-method = "psci";
	clocks = <&cru ARMCLK>;
	#cooling-cells = <2>;
	cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	dynamic-power-coefficient = <90>;
	operating-points-v2 = <&cpu0_opp_table>;
	};

	cpu2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a35";
	reg = <0x0 0x2>;
	enable-method = "psci";
	clocks = <&cru ARMCLK>;
	#cooling-cells = <2>;
	cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	dynamic-power-coefficient = <90>;
	operating-points-v2 = <&cpu0_opp_table>;
	};

	cpu3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a35";
	reg = <0x0 0x3>;
	enable-method = "psci";
	clocks = <&cru ARMCLK>;
	#cooling-cells = <2>;
	cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	dynamic-power-coefficient = <90>;
	operating-points-v2 = <&cpu0_opp_table>;
	};

	idle-states {
	entry-method = "psci";

	CPU_SLEEP: cpu-sleep {
	compatible = "arm,idle-state";
	local-timer-stop;
	arm,psci-suspend-param = <0x0010000>;
	entry-latency-us = <120>;
	exit-latency-us = <250>;
	min-residency-us = <900>;
	};

	CLUSTER_SLEEP: cluster-sleep {
	compatible = "arm,idle-state";
	local-timer-stop;
	arm,psci-suspend-param = <0x1010000>;
	entry-latency-us = <400>;
	exit-latency-us = <500>;
	min-residency-us = <2000>;
	};
	};
	};

	cpu0_opp_table: cpu0-opp-table {
	compatible = "operating-points-v2";
	opp-shared;

	opp-600000000 {
	opp-hz = /bits/ 64 <600000000>;
	opp-microvolt = <950000 950000 1350000>;
	clock-latency-ns = <40000>;
	opp-suspend;
	};
	opp-816000000 {
	opp-hz = /bits/ 64 <816000000>;
	opp-microvolt = <1050000 1050000 1350000>;
	clock-latency-ns = <40000>;
	};
	opp-1008000000 {
	opp-hz = /bits/ 64 <1008000000>;
	opp-microvolt = <1175000 1175000 1350000>;
	clock-latency-ns = <40000>;
	};
	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	opp-microvolt = <1300000 1300000 1350000>;
	clock-latency-ns = <40000>;
	};
	opp-1296000000 {
	opp-hz = /bits/ 64 <1296000000>;
	opp-microvolt = <1350000 1350000 1350000>;
	clock-latency-ns = <40000>;
	};
	};

	arm-pmu {
	- compatible = "arm,cortex-a53-pmu";
	+ compatible = "arm,cortex-a35-pmu";
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	display_subsystem: display-subsystem {
	compatible = "rockchip,display-subsystem";
	ports = <&vopb_out>, <&vopl_out>;
	status = "disabled";
	};

	gmac_clkin: external-gmac-clock {
	compatible = "fixed-clock";
	clock-frequency = <50000000>;
	clock-output-names = "gmac_clkin";
	#clock-cells = <0>;
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	thermal_zones: thermal-zones {
	soc_thermal: soc-thermal {
	polling-delay-passive = <20>;
	polling-delay = <1000>;
	sustainable-power = <750>;
	thermal-sensors = <&tsadc 0>;

	trips {
	threshold: trip-point-0 {
	temperature = <70000>;
	hysteresis = <2000>;
	type = "passive";
	};

	target: trip-point-1 {
	temperature = <85000>;
	hysteresis = <2000>;
	type = "passive";
	};

	soc_crit: soc-crit {
	temperature = <115000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&target>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	contribution = <4096>;
	};

	map1 {
	trip = <&target>;
	cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	contribution = <4096>;
	};
	};
	};

	gpu_thermal: gpu-thermal {
	polling-delay-passive = <100>; /* milliseconds */
	polling-delay = <1000>; /* milliseconds */
	thermal-sensors = <&tsadc 1>;
	};
	};

	xin24m: xin24m {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "xin24m";
	};

	pmu: power-management@ff000000 {
	compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
	reg = <0x0 0xff000000 0x0 0x1000>;

	power: power-controller {
	compatible = "rockchip,px30-power-controller";
	#power-domain-cells = <1>;
	#address-cells = <1>;
	#size-cells = <0>;

	/* These power domains are grouped by VD_LOGIC */
	pd_usb@PX30_PD_USB {
	reg = <PX30_PD_USB>;
	clocks = <&cru HCLK_HOST>,
	<&cru HCLK_OTG>,
	<&cru SCLK_OTG_ADP>;
	pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
	};
	pd_sdcard@PX30_PD_SDCARD {
	reg = <PX30_PD_SDCARD>;
	clocks = <&cru HCLK_SDMMC>,
	<&cru SCLK_SDMMC>;
	pm_qos = <&qos_sdmmc>;
	};
	pd_gmac@PX30_PD_GMAC {
	reg = <PX30_PD_GMAC>;
	clocks = <&cru ACLK_GMAC>,
	<&cru PCLK_GMAC>,
	<&cru SCLK_MAC_REF>,
	<&cru SCLK_GMAC_RX_TX>;
	pm_qos = <&qos_gmac>;
	};
	pd_mmc_nand@PX30_PD_MMC_NAND {
	reg = <PX30_PD_MMC_NAND>;
	clocks = <&cru HCLK_NANDC>,
	<&cru HCLK_EMMC>,
	<&cru HCLK_SDIO>,
	<&cru HCLK_SFC>,
	<&cru SCLK_EMMC>,
	<&cru SCLK_NANDC>,
	<&cru SCLK_SDIO>,
	<&cru SCLK_SFC>;
	pm_qos = <&qos_emmc>, <&qos_nand>,
	<&qos_sdio>, <&qos_sfc>;
	};
	pd_vpu@PX30_PD_VPU {
	reg = <PX30_PD_VPU>;
	clocks = <&cru ACLK_VPU>,
	<&cru HCLK_VPU>,
	<&cru SCLK_CORE_VPU>;
	pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
	};
	pd_vo@PX30_PD_VO {
	reg = <PX30_PD_VO>;
	clocks = <&cru ACLK_RGA>,
	<&cru ACLK_VOPB>,
	<&cru ACLK_VOPL>,
	<&cru DCLK_VOPB>,
	<&cru DCLK_VOPL>,
	<&cru HCLK_RGA>,
	<&cru HCLK_VOPB>,
	<&cru HCLK_VOPL>,
	<&cru PCLK_MIPI_DSI>,
	<&cru SCLK_RGA_CORE>,
	<&cru SCLK_VOPB_PWM>;
	pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
	<&qos_vop_m0>, <&qos_vop_m1>;
	};
	pd_vi@PX30_PD_VI {
	reg = <PX30_PD_VI>;
	clocks = <&cru ACLK_CIF>,
	<&cru ACLK_ISP>,
	<&cru HCLK_CIF>,
	<&cru HCLK_ISP>,
	<&cru SCLK_ISP>;
	pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
	<&qos_isp_wr>, <&qos_isp_m1>,
	<&qos_vip>;
	};
	pd_gpu@PX30_PD_GPU {
	reg = <PX30_PD_GPU>;
	clocks = <&cru SCLK_GPU>;
	pm_qos = <&qos_gpu>;
	};
	};
	};

	pmugrf: syscon@ff010000 {
	compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
	reg = <0x0 0xff010000 0x0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;

	pmu_io_domains: io-domains {
	compatible = "rockchip,px30-pmu-io-voltage-domain";
	status = "disabled";
	};

	reboot-mode {
	compatible = "syscon-reboot-mode";
	offset = <0x200>;
	mode-bootloader = <BOOT_BL_DOWNLOAD>;
	mode-fastboot = <BOOT_FASTBOOT>;
	mode-loader = <BOOT_BL_DOWNLOAD>;
	mode-normal = <BOOT_NORMAL>;
	mode-recovery = <BOOT_RECOVERY>;
	};
	};

	uart0: serial@ff030000 {
	compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff030000 0x0 0x100>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
	clock-names = "baudclk", "apb_pclk";
	dmas = <&dmac 0>, <&dmac 1>;
	dma-names = "tx", "rx";
	reg-shift = <2>;
	reg-io-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
	status = "disabled";
	};

	i2s1_2ch: i2s@ff070000 {
	compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
	reg = <0x0 0xff070000 0x0 0x1000>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
	clock-names = "i2s_clk", "i2s_hclk";
	dmas = <&dmac 18>, <&dmac 19>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
	&i2s1_2ch_sdi &i2s1_2ch_sdo>;
	#sound-dai-cells = <0>;
	status = "disabled";
	};

	i2s2_2ch: i2s@ff080000 {
	compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
	reg = <0x0 0xff080000 0x0 0x1000>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
	clock-names = "i2s_clk", "i2s_hclk";
	dmas = <&dmac 20>, <&dmac 21>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
	&i2s2_2ch_sdi &i2s2_2ch_sdo>;
	#sound-dai-cells = <0>;
	status = "disabled";
	};

	gic: interrupt-controller@ff131000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x0 0xff131000 0 0x1000>,
	<0x0 0xff132000 0 0x2000>,
	<0x0 0xff134000 0 0x2000>,
	<0x0 0xff136000 0 0x2000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	grf: syscon@ff140000 {
	compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
	reg = <0x0 0xff140000 0x0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;

	io_domains: io-domains {
	compatible = "rockchip,px30-io-voltage-domain";
	status = "disabled";
	};

	lvds: lvds {
	compatible = "rockchip,px30-lvds";
	- #address-cells = <1>;
	- #size-cells = <0>;
	phys = <&dsi_dphy>;
	phy-names = "dphy";
	rockchip,grf = <&grf>;
	rockchip,output = "lvds";
	status = "disabled";

	- port@0 {
	- reg = <0>;
	+ ports {
	#address-cells = <1>;
	#size-cells = <0>;

	- lvds_vopb_in: endpoint@0 {
	+ port@0 {
	reg = <0>;
	- remote-endpoint = <&vopb_out_lvds>;
	- };
	-
	- lvds_vopl_in: endpoint@1 {
	- reg = <1>;
	- remote-endpoint = <&vopl_out_lvds>;
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ lvds_vopb_in: endpoint@0 {
	+ reg = <0>;
	+ remote-endpoint = <&vopb_out_lvds>;
	+ };
	+
	+ lvds_vopl_in: endpoint@1 {
	+ reg = <1>;
	+ remote-endpoint = <&vopl_out_lvds>;
	+ };
	};
	};
	};
	};

	uart1: serial@ff158000 {
	compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff158000 0x0 0x100>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
	clock-names = "baudclk", "apb_pclk";
	dmas = <&dmac 2>, <&dmac 3>;
	dma-names = "tx", "rx";
	reg-shift = <2>;
	reg-io-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
	status = "disabled";
	};

	uart2: serial@ff160000 {
	compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff160000 0x0 0x100>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
	clock-names = "baudclk", "apb_pclk";
	dmas = <&dmac 4>, <&dmac 5>;
	dma-names = "tx", "rx";
	reg-shift = <2>;
	reg-io-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart2m0_xfer>;
	status = "disabled";
	};

	uart3: serial@ff168000 {
	compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff168000 0x0 0x100>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
	clock-names = "baudclk", "apb_pclk";
	dmas = <&dmac 6>, <&dmac 7>;
	dma-names = "tx", "rx";
	reg-shift = <2>;
	reg-io-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
	status = "disabled";
	};

	uart4: serial@ff170000 {
	compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff170000 0x0 0x100>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
	clock-names = "baudclk", "apb_pclk";
	dmas = <&dmac 8>, <&dmac 9>;
	dma-names = "tx", "rx";
	reg-shift = <2>;
	reg-io-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
	status = "disabled";
	};

	uart5: serial@ff178000 {
	compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff178000 0x0 0x100>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
	clock-names = "baudclk", "apb_pclk";
	dmas = <&dmac 10>, <&dmac 11>;
	dma-names = "tx", "rx";
	reg-shift = <2>;
	reg-io-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
	status = "disabled";
	};

	i2c0: i2c@ff180000 {
	compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
	reg = <0x0 0xff180000 0x0 0x1000>;
	clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
	clock-names = "i2c", "pclk";
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c1: i2c@ff190000 {
	compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
	reg = <0x0 0xff190000 0x0 0x1000>;
	clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
	clock-names = "i2c", "pclk";
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c2: i2c@ff1a0000 {
	compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
	reg = <0x0 0xff1a0000 0x0 0x1000>;
	clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
	clock-names = "i2c", "pclk";
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c3: i2c@ff1b0000 {
	compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
	reg = <0x0 0xff1b0000 0x0 0x1000>;
	clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
	clock-names = "i2c", "pclk";
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi0: spi@ff1d0000 {
	compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
	reg = <0x0 0xff1d0000 0x0 0x1000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
	clock-names = "spiclk", "apb_pclk";
	dmas = <&dmac 12>, <&dmac 13>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi1: spi@ff1d8000 {
	compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
	reg = <0x0 0xff1d8000 0x0 0x1000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
	clock-names = "spiclk", "apb_pclk";
	dmas = <&dmac 14>, <&dmac 15>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	wdt: watchdog@ff1e0000 {
	compatible = "snps,dw-wdt";
	reg = <0x0 0xff1e0000 0x0 0x100>;
	clocks = <&cru PCLK_WDT_NS>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	pwm0: pwm@ff200000 {
	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff200000 0x0 0x10>;
	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm1: pwm@ff200010 {
	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff200010 0x0 0x10>;
	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm2: pwm@ff200020 {
	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff200020 0x0 0x10>;
	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm3: pwm@ff200030 {
	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff200030 0x0 0x10>;
	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm4: pwm@ff208000 {
	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff208000 0x0 0x10>;
	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm4_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm5: pwm@ff208010 {
	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff208010 0x0 0x10>;
	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm5_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm6: pwm@ff208020 {
	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff208020 0x0 0x10>;
	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm6_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm7: pwm@ff208030 {
	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff208030 0x0 0x10>;
	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm7_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	rktimer: timer@ff210000 {
	compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
	reg = <0x0 0xff210000 0x0 0x1000>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
	clock-names = "pclk", "timer";
	};

	- amba {
	+ amba: bus {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	dmac: dmac@ff240000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x0 0xff240000 0x0 0x4000>;
	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru ACLK_DMAC>;
	clock-names = "apb_pclk";
	#dma-cells = <1>;
	};
	};

	tsadc: tsadc@ff280000 {
	compatible = "rockchip,px30-tsadc";
	reg = <0x0 0xff280000 0x0 0x100>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	assigned-clocks = <&cru SCLK_TSADC>;
	assigned-clock-rates = <50000>;
	clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
	clock-names = "tsadc", "apb_pclk";
	resets = <&cru SRST_TSADC>;
	reset-names = "tsadc-apb";
	rockchip,grf = <&grf>;
	rockchip,hw-tshut-temp = <120000>;
	pinctrl-names = "init", "default", "sleep";
	pinctrl-0 = <&tsadc_otp_gpio>;
	pinctrl-1 = <&tsadc_otp_out>;
	pinctrl-2 = <&tsadc_otp_gpio>;
	#thermal-sensor-cells = <1>;
	status = "disabled";
	};

	saradc: saradc@ff288000 {
	compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
	reg = <0x0 0xff288000 0x0 0x100>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	#io-channel-cells = <1>;
	clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
	clock-names = "saradc", "apb_pclk";
	resets = <&cru SRST_SARADC_P>;
	reset-names = "saradc-apb";
	status = "disabled";
	};

	otp: nvmem@ff290000 {
	compatible = "rockchip,px30-otp";
	reg = <0x0 0xff290000 0x0 0x4000>;
	clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
	<&cru PCLK_OTP_PHY>;
	clock-names = "otp", "apb_pclk", "phy";
	resets = <&cru SRST_OTP_PHY>;
	reset-names = "phy";
	#address-cells = <1>;
	#size-cells = <1>;

	/* Data cells */
	cpu_id: id@7 {
	reg = <0x07 0x10>;
	};
	cpu_leakage: cpu-leakage@17 {
	reg = <0x17 0x1>;
	};
	performance: performance@1e {
	reg = <0x1e 0x1>;
	bits = <4 3>;
	};
	};

	cru: clock-controller@ff2b0000 {
	compatible = "rockchip,px30-cru";
	reg = <0x0 0xff2b0000 0x0 0x1000>;
	clocks = <&xin24m>, <&pmucru PLL_GPLL>;
	clock-names = "xin24m", "gpll";
	rockchip,grf = <&grf>;
	#clock-cells = <1>;
	#reset-cells = <1>;

	assigned-clocks = <&cru PLL_NPLL>,
	<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
	<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
	<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;

	assigned-clock-rates = <1188000000>,
	<200000000>, <200000000>,
	<150000000>, <150000000>,
	<100000000>, <200000000>;
	};

	pmucru: clock-controller@ff2bc000 {
	compatible = "rockchip,px30-pmucru";
	reg = <0x0 0xff2bc000 0x0 0x1000>;
	clocks = <&xin24m>;
	clock-names = "xin24m";
	rockchip,grf = <&grf>;
	#clock-cells = <1>;
	#reset-cells = <1>;

	assigned-clocks =
	<&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
	<&pmucru SCLK_WIFI_PMU>;
	assigned-clock-rates =
	<1200000000>, <100000000>,
	<26000000>;
	};

	usb2phy_grf: syscon@ff2c0000 {
	compatible = "rockchip,px30-usb2phy-grf", "syscon",
	"simple-mfd";
	reg = <0x0 0xff2c0000 0x0 0x10000>;
	#address-cells = <1>;
	#size-cells = <1>;

	u2phy: usb2-phy@100 {
	compatible = "rockchip,px30-usb2phy";
	reg = <0x100 0x20>;
	clocks = <&pmucru SCLK_USBPHY_REF>;
	clock-names = "phyclk";
	#clock-cells = <0>;
	assigned-clocks = <&cru USB480M>;
	assigned-clock-parents = <&u2phy>;
	clock-output-names = "usb480m_phy";
	status = "disabled";

	u2phy_host: host-port {
	#phy-cells = <0>;
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "linestate";
	status = "disabled";
	};

	u2phy_otg: otg-port {
	#phy-cells = <0>;
	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "otg-bvalid", "otg-id",
	"linestate";
	status = "disabled";
	};
	};
	};

	dsi_dphy: phy@ff2e0000 {
	compatible = "rockchip,px30-dsi-dphy";
	reg = <0x0 0xff2e0000 0x0 0x10000>;
	clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
	clock-names = "ref", "pclk";
	resets = <&cru SRST_MIPIDSIPHY_P>;
	reset-names = "apb";
	#phy-cells = <0>;
	power-domains = <&power PX30_PD_VO>;
	status = "disabled";
	};

	usb20_otg: usb@ff300000 {
	compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
	"snps,dwc2";
	reg = <0x0 0xff300000 0x0 0x40000>;
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_OTG>;
	clock-names = "otg";
	dr_mode = "otg";
	g-np-tx-fifo-size = <16>;
	g-rx-fifo-size = <280>;
	g-tx-fifo-size = <256 128 128 64 32 16>;
	- g-use-dma;
	phys = <&u2phy_otg>;
	phy-names = "usb2-phy";
	power-domains = <&power PX30_PD_USB>;
	status = "disabled";
	};

	usb_host0_ehci: usb@ff340000 {
	compatible = "generic-ehci";
	reg = <0x0 0xff340000 0x0 0x10000>;
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_HOST>;
	- clock-names = "usbhost";
	phys = <&u2phy_host>;
	phy-names = "usb";
	power-domains = <&power PX30_PD_USB>;
	status = "disabled";
	};

	usb_host0_ohci: usb@ff350000 {
	compatible = "generic-ohci";
	reg = <0x0 0xff350000 0x0 0x10000>;
	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_HOST>;
	- clock-names = "usbhost";
	phys = <&u2phy_host>;
	phy-names = "usb";
	power-domains = <&power PX30_PD_USB>;
	status = "disabled";
	};

	gmac: ethernet@ff360000 {
	compatible = "rockchip,px30-gmac";
	reg = <0x0 0xff360000 0x0 0x10000>;
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
	<&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
	<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
	<&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
	clock-names = "stmmaceth", "mac_clk_rx",
	"mac_clk_tx", "clk_mac_ref",
	"clk_mac_refout", "aclk_mac",
	"pclk_mac", "clk_mac_speed";
	rockchip,grf = <&grf>;
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
	power-domains = <&power PX30_PD_GMAC>;
	resets = <&cru SRST_GMAC_A>;
	reset-names = "stmmaceth";
	status = "disabled";
	};

	sdmmc: mmc@ff370000 {
	compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x0 0xff370000 0x0 0x4000>;
	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
	<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	max-frequency = <150000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
	power-domains = <&power PX30_PD_SDCARD>;
	status = "disabled";
	};

	sdio: mmc@ff380000 {
	compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x0 0xff380000 0x0 0x4000>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
	<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	max-frequency = <150000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
	power-domains = <&power PX30_PD_MMC_NAND>;
	status = "disabled";
	};

	emmc: mmc@ff390000 {
	compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x0 0xff390000 0x0 0x4000>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
	<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	max-frequency = <150000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
	power-domains = <&power PX30_PD_MMC_NAND>;
	status = "disabled";
	};

	gpu: gpu@ff400000 {
	compatible = "rockchip,px30-mali", "arm,mali-bifrost";
	reg = <0x0 0xff400000 0x0 0x4000>;
	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "job", "mmu", "gpu";
	clocks = <&cru SCLK_GPU>;
	#cooling-cells = <2>;
	power-domains = <&power PX30_PD_GPU>;
	status = "disabled";
	};

	dsi: dsi@ff450000 {
	compatible = "rockchip,px30-mipi-dsi";
	reg = <0x0 0xff450000 0x0 0x10000>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_MIPI_DSI>;
	clock-names = "pclk";
	phys = <&dsi_dphy>;
	phy-names = "dphy";
	power-domains = <&power PX30_PD_VO>;
	resets = <&cru SRST_MIPIDSI_HOST_P>;
	reset-names = "apb";
	rockchip,grf = <&grf>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	#address-cells = <1>;
	#size-cells = <0>;

	dsi_in_vopb: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vopb_out_dsi>;
	};

	dsi_in_vopl: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vopl_out_dsi>;
	};
	};
	};
	};

	vopb: vop@ff460000 {
	compatible = "rockchip,px30-vop-big";
	reg = <0x0 0xff460000 0x0 0xefc>;
	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
	<&cru HCLK_VOPB>;
	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
	reset-names = "axi", "ahb", "dclk";
	iommus = <&vopb_mmu>;
	power-domains = <&power PX30_PD_VO>;
	- rockchip,grf = <&grf>;
	status = "disabled";

	vopb_out: port {
	#address-cells = <1>;
	#size-cells = <0>;

	vopb_out_dsi: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&dsi_in_vopb>;
	};

	vopb_out_lvds: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&lvds_vopb_in>;
	};
	};
	};

	vopb_mmu: iommu@ff460f00 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff460f00 0x0 0x100>;
	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "vopb_mmu";
	clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
	clock-names = "aclk", "iface";
	power-domains = <&power PX30_PD_VO>;
	#iommu-cells = <0>;
	status = "disabled";
	};

	vopl: vop@ff470000 {
	compatible = "rockchip,px30-vop-lit";
	reg = <0x0 0xff470000 0x0 0xefc>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
	<&cru HCLK_VOPL>;
	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
	reset-names = "axi", "ahb", "dclk";
	iommus = <&vopl_mmu>;
	power-domains = <&power PX30_PD_VO>;
	- rockchip,grf = <&grf>;
	status = "disabled";

	vopl_out: port {
	#address-cells = <1>;
	#size-cells = <0>;

	vopl_out_dsi: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&dsi_in_vopl>;
	};

	vopl_out_lvds: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&lvds_vopl_in>;
	};
	};
	};

	vopl_mmu: iommu@ff470f00 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff470f00 0x0 0x100>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "vopl_mmu";
	clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
	clock-names = "aclk", "iface";
	power-domains = <&power PX30_PD_VO>;
	#iommu-cells = <0>;
	status = "disabled";
	};

	qos_gmac: qos@ff518000 {
	compatible = "syscon";
	reg = <0x0 0xff518000 0x0 0x20>;
	};

	qos_gpu: qos@ff520000 {
	compatible = "syscon";
	reg = <0x0 0xff520000 0x0 0x20>;
	};

	qos_sdmmc: qos@ff52c000 {
	compatible = "syscon";
	reg = <0x0 0xff52c000 0x0 0x20>;
	};

	qos_emmc: qos@ff538000 {
	compatible = "syscon";
	reg = <0x0 0xff538000 0x0 0x20>;
	};

	qos_nand: qos@ff538080 {
	compatible = "syscon";
	reg = <0x0 0xff538080 0x0 0x20>;
	};

	qos_sdio: qos@ff538100 {
	compatible = "syscon";
	reg = <0x0 0xff538100 0x0 0x20>;
	};

	qos_sfc: qos@ff538180 {
	compatible = "syscon";
	reg = <0x0 0xff538180 0x0 0x20>;
	};

	qos_usb_host: qos@ff540000 {
	compatible = "syscon";
	reg = <0x0 0xff540000 0x0 0x20>;
	};

	qos_usb_otg: qos@ff540080 {
	compatible = "syscon";
	reg = <0x0 0xff540080 0x0 0x20>;
	};

	qos_isp_128: qos@ff548000 {
	compatible = "syscon";
	reg = <0x0 0xff548000 0x0 0x20>;
	};

	qos_isp_rd: qos@ff548080 {
	compatible = "syscon";
	reg = <0x0 0xff548080 0x0 0x20>;
	};

	qos_isp_wr: qos@ff548100 {
	compatible = "syscon";
	reg = <0x0 0xff548100 0x0 0x20>;
	};

	qos_isp_m1: qos@ff548180 {
	compatible = "syscon";
	reg = <0x0 0xff548180 0x0 0x20>;
	};

	qos_vip: qos@ff548200 {
	compatible = "syscon";
	reg = <0x0 0xff548200 0x0 0x20>;
	};

	qos_rga_rd: qos@ff550000 {
	compatible = "syscon";
	reg = <0x0 0xff550000 0x0 0x20>;
	};

	qos_rga_wr: qos@ff550080 {
	compatible = "syscon";
	reg = <0x0 0xff550080 0x0 0x20>;
	};

	qos_vop_m0: qos@ff550100 {
	compatible = "syscon";
	reg = <0x0 0xff550100 0x0 0x20>;
	};

	qos_vop_m1: qos@ff550180 {
	compatible = "syscon";
	reg = <0x0 0xff550180 0x0 0x20>;
	};

	qos_vpu: qos@ff558000 {
	compatible = "syscon";
	reg = <0x0 0xff558000 0x0 0x20>;
	};

	qos_vpu_r128: qos@ff558080 {
	compatible = "syscon";
	reg = <0x0 0xff558080 0x0 0x20>;
	};

	pinctrl: pinctrl {
	compatible = "rockchip,px30-pinctrl";
	rockchip,grf = <&grf>;
	rockchip,pmu = <&pmugrf>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	gpio0: gpio0@ff040000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff040000 0x0 0x100>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&pmucru PCLK_GPIO0_PMU>;
	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio1: gpio1@ff250000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff250000 0x0 0x100>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO1>;
	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio2@ff260000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff260000 0x0 0x100>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO2>;
	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio3@ff270000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff270000 0x0 0x100>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO3>;
	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	pcfg_pull_up: pcfg-pull-up {
	bias-pull-up;
	};

	pcfg_pull_down: pcfg-pull-down {
	bias-pull-down;
	};

	pcfg_pull_none: pcfg-pull-none {
	bias-disable;
	};

	pcfg_pull_none_2ma: pcfg-pull-none-2ma {
	bias-disable;
	drive-strength = <2>;
	};

	pcfg_pull_up_2ma: pcfg-pull-up-2ma {
	bias-pull-up;
	drive-strength = <2>;
	};

	pcfg_pull_up_4ma: pcfg-pull-up-4ma {
	bias-pull-up;
	drive-strength = <4>;
	};

	pcfg_pull_none_4ma: pcfg-pull-none-4ma {
	bias-disable;
	drive-strength = <4>;
	};

	pcfg_pull_down_4ma: pcfg-pull-down-4ma {
	bias-pull-down;
	drive-strength = <4>;
	};

	pcfg_pull_none_8ma: pcfg-pull-none-8ma {
	bias-disable;
	drive-strength = <8>;
	};

	pcfg_pull_up_8ma: pcfg-pull-up-8ma {
	bias-pull-up;
	drive-strength = <8>;
	};

	pcfg_pull_none_12ma: pcfg-pull-none-12ma {
	bias-disable;
	drive-strength = <12>;
	};

	pcfg_pull_up_12ma: pcfg-pull-up-12ma {
	bias-pull-up;
	drive-strength = <12>;
	};

	pcfg_pull_none_smt: pcfg-pull-none-smt {
	bias-disable;
	input-schmitt-enable;
	};

	pcfg_output_high: pcfg-output-high {
	output-high;
	};

	pcfg_output_low: pcfg-output-low {
	output-low;
	};

	pcfg_input_high: pcfg-input-high {
	bias-pull-up;
	input-enable;
	};

	pcfg_input: pcfg-input {
	input-enable;
	};

	i2c0 {
	i2c0_xfer: i2c0-xfer {
	rockchip,pins =
	<0 RK_PB0 1 &pcfg_pull_none_smt>,
	<0 RK_PB1 1 &pcfg_pull_none_smt>;
	};
	};

	i2c1 {
	i2c1_xfer: i2c1-xfer {
	rockchip,pins =
	<0 RK_PC2 1 &pcfg_pull_none_smt>,
	<0 RK_PC3 1 &pcfg_pull_none_smt>;
	};
	};

	i2c2 {
	i2c2_xfer: i2c2-xfer {
	rockchip,pins =
	<2 RK_PB7 2 &pcfg_pull_none_smt>,
	<2 RK_PC0 2 &pcfg_pull_none_smt>;
	};
	};

	i2c3 {
	i2c3_xfer: i2c3-xfer {
	rockchip,pins =
	<1 RK_PB4 4 &pcfg_pull_none_smt>,
	<1 RK_PB5 4 &pcfg_pull_none_smt>;
	};
	};

	tsadc {
	tsadc_otp_gpio: tsadc-otp-gpio {
	rockchip,pins =
	<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	tsadc_otp_out: tsadc-otp-out {
	rockchip,pins =
	<0 RK_PA6 1 &pcfg_pull_none>;
	};
	};

	uart0 {
	uart0_xfer: uart0-xfer {
	rockchip,pins =
	<0 RK_PB2 1 &pcfg_pull_up>,
	<0 RK_PB3 1 &pcfg_pull_up>;
	};

	uart0_cts: uart0-cts {
	rockchip,pins =
	<0 RK_PB4 1 &pcfg_pull_none>;
	};

	uart0_rts: uart0-rts {
	rockchip,pins =
	<0 RK_PB5 1 &pcfg_pull_none>;
	};
	};

	uart1 {
	uart1_xfer: uart1-xfer {
	rockchip,pins =
	<1 RK_PC1 1 &pcfg_pull_up>,
	<1 RK_PC0 1 &pcfg_pull_up>;
	};

	uart1_cts: uart1-cts {
	rockchip,pins =
	<1 RK_PC2 1 &pcfg_pull_none>;
	};

	uart1_rts: uart1-rts {
	rockchip,pins =
	<1 RK_PC3 1 &pcfg_pull_none>;
	};
	};

	uart2-m0 {
	uart2m0_xfer: uart2m0-xfer {
	rockchip,pins =
	<1 RK_PD2 2 &pcfg_pull_up>,
	<1 RK_PD3 2 &pcfg_pull_up>;
	};
	};

	uart2-m1 {
	uart2m1_xfer: uart2m1-xfer {
	rockchip,pins =
	<2 RK_PB4 2 &pcfg_pull_up>,
	<2 RK_PB6 2 &pcfg_pull_up>;
	};
	};

	uart3-m0 {
	uart3m0_xfer: uart3m0-xfer {
	rockchip,pins =
	<0 RK_PC0 2 &pcfg_pull_up>,
	<0 RK_PC1 2 &pcfg_pull_up>;
	};

	uart3m0_cts: uart3m0-cts {
	rockchip,pins =
	<0 RK_PC2 2 &pcfg_pull_none>;
	};

	uart3m0_rts: uart3m0-rts {
	rockchip,pins =
	<0 RK_PC3 2 &pcfg_pull_none>;
	};
	};

	uart3-m1 {
	uart3m1_xfer: uart3m1-xfer {
	rockchip,pins =
	<1 RK_PB6 2 &pcfg_pull_up>,
	<1 RK_PB7 2 &pcfg_pull_up>;
	};

	uart3m1_cts: uart3m1-cts {
	rockchip,pins =
	<1 RK_PB4 2 &pcfg_pull_none>;
	};

	uart3m1_rts: uart3m1-rts {
	rockchip,pins =
	<1 RK_PB5 2 &pcfg_pull_none>;
	};
	};

	uart4 {
	uart4_xfer: uart4-xfer {
	rockchip,pins =
	<1 RK_PD4 2 &pcfg_pull_up>,
	<1 RK_PD5 2 &pcfg_pull_up>;
	};

	uart4_cts: uart4-cts {
	rockchip,pins =
	<1 RK_PD6 2 &pcfg_pull_none>;
	};

	uart4_rts: uart4-rts {
	rockchip,pins =
	<1 RK_PD7 2 &pcfg_pull_none>;
	};
	};

	uart5 {
	uart5_xfer: uart5-xfer {
	rockchip,pins =
	<3 RK_PA2 4 &pcfg_pull_up>,
	<3 RK_PA1 4 &pcfg_pull_up>;
	};

	uart5_cts: uart5-cts {
	rockchip,pins =
	<3 RK_PA3 4 &pcfg_pull_none>;
	};

	uart5_rts: uart5-rts {
	rockchip,pins =
	<3 RK_PA5 4 &pcfg_pull_none>;
	};
	};

	spi0 {
	spi0_clk: spi0-clk {
	rockchip,pins =
	<1 RK_PB7 3 &pcfg_pull_up_4ma>;
	};

	spi0_csn: spi0-csn {
	rockchip,pins =
	<1 RK_PB6 3 &pcfg_pull_up_4ma>;
	};

	spi0_miso: spi0-miso {
	rockchip,pins =
	<1 RK_PB5 3 &pcfg_pull_up_4ma>;
	};

	spi0_mosi: spi0-mosi {
	rockchip,pins =
	<1 RK_PB4 3 &pcfg_pull_up_4ma>;
	};

	spi0_clk_hs: spi0-clk-hs {
	rockchip,pins =
	<1 RK_PB7 3 &pcfg_pull_up_8ma>;
	};

	spi0_miso_hs: spi0-miso-hs {
	rockchip,pins =
	<1 RK_PB5 3 &pcfg_pull_up_8ma>;
	};

	spi0_mosi_hs: spi0-mosi-hs {
	rockchip,pins =
	<1 RK_PB4 3 &pcfg_pull_up_8ma>;
	};
	};

	spi1 {
	spi1_clk: spi1-clk {
	rockchip,pins =
	<3 RK_PB7 4 &pcfg_pull_up_4ma>;
	};

	spi1_csn0: spi1-csn0 {
	rockchip,pins =
	<3 RK_PB1 4 &pcfg_pull_up_4ma>;
	};

	spi1_csn1: spi1-csn1 {
	rockchip,pins =
	<3 RK_PB2 2 &pcfg_pull_up_4ma>;
	};

	spi1_miso: spi1-miso {
	rockchip,pins =
	<3 RK_PB6 4 &pcfg_pull_up_4ma>;
	};

	spi1_mosi: spi1-mosi {
	rockchip,pins =
	<3 RK_PB4 4 &pcfg_pull_up_4ma>;
	};

	spi1_clk_hs: spi1-clk-hs {
	rockchip,pins =
	<3 RK_PB7 4 &pcfg_pull_up_8ma>;
	};

	spi1_miso_hs: spi1-miso-hs {
	rockchip,pins =
	<3 RK_PB6 4 &pcfg_pull_up_8ma>;
	};

	spi1_mosi_hs: spi1-mosi-hs {
	rockchip,pins =
	<3 RK_PB4 4 &pcfg_pull_up_8ma>;
	};
	};

	pdm {
	pdm_clk0m0: pdm-clk0m0 {
	rockchip,pins =
	<3 RK_PC6 2 &pcfg_pull_none>;
	};

	pdm_clk0m1: pdm-clk0m1 {
	rockchip,pins =
	<2 RK_PC6 1 &pcfg_pull_none>;
	};

	pdm_clk1: pdm-clk1 {
	rockchip,pins =
	<3 RK_PC7 2 &pcfg_pull_none>;
	};

	pdm_sdi0m0: pdm-sdi0m0 {
	rockchip,pins =
	<3 RK_PD3 2 &pcfg_pull_none>;
	};

	pdm_sdi0m1: pdm-sdi0m1 {
	rockchip,pins =
	<2 RK_PC5 2 &pcfg_pull_none>;
	};

	pdm_sdi1: pdm-sdi1 {
	rockchip,pins =
	<3 RK_PD0 2 &pcfg_pull_none>;
	};

	pdm_sdi2: pdm-sdi2 {
	rockchip,pins =
	<3 RK_PD1 2 &pcfg_pull_none>;
	};

	pdm_sdi3: pdm-sdi3 {
	rockchip,pins =
	<3 RK_PD2 2 &pcfg_pull_none>;
	};

	pdm_clk0m0_sleep: pdm-clk0m0-sleep {
	rockchip,pins =
	<3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
	};

	pdm_clk0m_sleep1: pdm-clk0m1-sleep {
	rockchip,pins =
	<2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
	};

	pdm_clk1_sleep: pdm-clk1-sleep {
	rockchip,pins =
	<3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
	};

	pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
	rockchip,pins =
	<3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
	};

	pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
	rockchip,pins =
	<2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
	};

	pdm_sdi1_sleep: pdm-sdi1-sleep {
	rockchip,pins =
	<3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
	};

	pdm_sdi2_sleep: pdm-sdi2-sleep {
	rockchip,pins =
	<3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
	};

	pdm_sdi3_sleep: pdm-sdi3-sleep {
	rockchip,pins =
	<3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
	};
	};

	i2s0 {
	i2s0_8ch_mclk: i2s0-8ch-mclk {
	rockchip,pins =
	<3 RK_PC1 2 &pcfg_pull_none>;
	};

	i2s0_8ch_sclktx: i2s0-8ch-sclktx {
	rockchip,pins =
	<3 RK_PC3 2 &pcfg_pull_none>;
	};

	i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
	rockchip,pins =
	<3 RK_PB4 2 &pcfg_pull_none>;
	};

	i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
	rockchip,pins =
	<3 RK_PC2 2 &pcfg_pull_none>;
	};

	i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
	rockchip,pins =
	<3 RK_PB5 2 &pcfg_pull_none>;
	};

	i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
	rockchip,pins =
	<3 RK_PC4 2 &pcfg_pull_none>;
	};

	i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
	rockchip,pins =
	<3 RK_PC0 2 &pcfg_pull_none>;
	};

	i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
	rockchip,pins =
	<3 RK_PB7 2 &pcfg_pull_none>;
	};

	i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
	rockchip,pins =
	<3 RK_PB6 2 &pcfg_pull_none>;
	};

	i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
	rockchip,pins =
	<3 RK_PC5 2 &pcfg_pull_none>;
	};

	i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
	rockchip,pins =
	<3 RK_PB3 2 &pcfg_pull_none>;
	};

	i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
	rockchip,pins =
	<3 RK_PB1 2 &pcfg_pull_none>;
	};

	i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
	rockchip,pins =
	<3 RK_PB0 2 &pcfg_pull_none>;
	};
	};

	i2s1 {
	i2s1_2ch_mclk: i2s1-2ch-mclk {
	rockchip,pins =
	<2 RK_PC3 1 &pcfg_pull_none>;
	};

	i2s1_2ch_sclk: i2s1-2ch-sclk {
	rockchip,pins =
	<2 RK_PC2 1 &pcfg_pull_none>;
	};

	i2s1_2ch_lrck: i2s1-2ch-lrck {
	rockchip,pins =
	<2 RK_PC1 1 &pcfg_pull_none>;
	};

	i2s1_2ch_sdi: i2s1-2ch-sdi {
	rockchip,pins =
	<2 RK_PC5 1 &pcfg_pull_none>;
	};

	i2s1_2ch_sdo: i2s1-2ch-sdo {
	rockchip,pins =
	<2 RK_PC4 1 &pcfg_pull_none>;
	};
	};

	i2s2 {
	i2s2_2ch_mclk: i2s2-2ch-mclk {
	rockchip,pins =
	<3 RK_PA1 2 &pcfg_pull_none>;
	};

	i2s2_2ch_sclk: i2s2-2ch-sclk {
	rockchip,pins =
	<3 RK_PA2 2 &pcfg_pull_none>;
	};

	i2s2_2ch_lrck: i2s2-2ch-lrck {
	rockchip,pins =
	<3 RK_PA3 2 &pcfg_pull_none>;
	};

	i2s2_2ch_sdi: i2s2-2ch-sdi {
	rockchip,pins =
	<3 RK_PA5 2 &pcfg_pull_none>;
	};

	i2s2_2ch_sdo: i2s2-2ch-sdo {
	rockchip,pins =
	<3 RK_PA7 2 &pcfg_pull_none>;
	};
	};

	sdmmc {
	sdmmc_clk: sdmmc-clk {
	rockchip,pins =
	<1 RK_PD6 1 &pcfg_pull_none_8ma>;
	};

	sdmmc_cmd: sdmmc-cmd {
	rockchip,pins =
	<1 RK_PD7 1 &pcfg_pull_up_8ma>;
	};

	sdmmc_det: sdmmc-det {
	rockchip,pins =
	<0 RK_PA3 1 &pcfg_pull_up_8ma>;
	};

	sdmmc_bus1: sdmmc-bus1 {
	rockchip,pins =
	<1 RK_PD2 1 &pcfg_pull_up_8ma>;
	};

	sdmmc_bus4: sdmmc-bus4 {
	rockchip,pins =
	<1 RK_PD2 1 &pcfg_pull_up_8ma>,
	<1 RK_PD3 1 &pcfg_pull_up_8ma>,
	<1 RK_PD4 1 &pcfg_pull_up_8ma>,
	<1 RK_PD5 1 &pcfg_pull_up_8ma>;
	};
	};

	sdio {
	sdio_clk: sdio-clk {
	rockchip,pins =
	<1 RK_PC5 1 &pcfg_pull_none>;
	};

	sdio_cmd: sdio-cmd {
	rockchip,pins =
	<1 RK_PC4 1 &pcfg_pull_up>;
	};

	sdio_bus4: sdio-bus4 {
	rockchip,pins =
	<1 RK_PC6 1 &pcfg_pull_up>,
	<1 RK_PC7 1 &pcfg_pull_up>,
	<1 RK_PD0 1 &pcfg_pull_up>,
	<1 RK_PD1 1 &pcfg_pull_up>;
	};
	};

	emmc {
	emmc_clk: emmc-clk {
	rockchip,pins =
	<1 RK_PB1 2 &pcfg_pull_none_8ma>;
	};

	emmc_cmd: emmc-cmd {
	rockchip,pins =
	<1 RK_PB2 2 &pcfg_pull_up_8ma>;
	};

	emmc_rstnout: emmc-rstnout {
	rockchip,pins =
	<1 RK_PB3 2 &pcfg_pull_none>;
	};

	emmc_bus1: emmc-bus1 {
	rockchip,pins =
	<1 RK_PA0 2 &pcfg_pull_up_8ma>;
	};

	emmc_bus4: emmc-bus4 {
	rockchip,pins =
	<1 RK_PA0 2 &pcfg_pull_up_8ma>,
	<1 RK_PA1 2 &pcfg_pull_up_8ma>,
	<1 RK_PA2 2 &pcfg_pull_up_8ma>,
	<1 RK_PA3 2 &pcfg_pull_up_8ma>;
	};

	emmc_bus8: emmc-bus8 {
	rockchip,pins =
	<1 RK_PA0 2 &pcfg_pull_up_8ma>,
	<1 RK_PA1 2 &pcfg_pull_up_8ma>,
	<1 RK_PA2 2 &pcfg_pull_up_8ma>,
	<1 RK_PA3 2 &pcfg_pull_up_8ma>,
	<1 RK_PA4 2 &pcfg_pull_up_8ma>,
	<1 RK_PA5 2 &pcfg_pull_up_8ma>,
	<1 RK_PA6 2 &pcfg_pull_up_8ma>,
	<1 RK_PA7 2 &pcfg_pull_up_8ma>;
	};
	};

	flash {
	flash_cs0: flash-cs0 {
	rockchip,pins =
	<1 RK_PB0 1 &pcfg_pull_none>;
	};

	flash_rdy: flash-rdy {
	rockchip,pins =
	<1 RK_PB1 1 &pcfg_pull_none>;
	};

	flash_dqs: flash-dqs {
	rockchip,pins =
	<1 RK_PB2 1 &pcfg_pull_none>;
	};

	flash_ale: flash-ale {
	rockchip,pins =
	<1 RK_PB3 1 &pcfg_pull_none>;
	};

	flash_cle: flash-cle {
	rockchip,pins =
	<1 RK_PB4 1 &pcfg_pull_none>;
	};

	flash_wrn: flash-wrn {
	rockchip,pins =
	<1 RK_PB5 1 &pcfg_pull_none>;
	};

	flash_csl: flash-csl {
	rockchip,pins =
	<1 RK_PB6 1 &pcfg_pull_none>;
	};

	flash_rdn: flash-rdn {
	rockchip,pins =
	<1 RK_PB7 1 &pcfg_pull_none>;
	};

	flash_bus8: flash-bus8 {
	rockchip,pins =
	<1 RK_PA0 1 &pcfg_pull_up_12ma>,
	<1 RK_PA1 1 &pcfg_pull_up_12ma>,
	<1 RK_PA2 1 &pcfg_pull_up_12ma>,
	<1 RK_PA3 1 &pcfg_pull_up_12ma>,
	<1 RK_PA4 1 &pcfg_pull_up_12ma>,
	<1 RK_PA5 1 &pcfg_pull_up_12ma>,
	<1 RK_PA6 1 &pcfg_pull_up_12ma>,
	<1 RK_PA7 1 &pcfg_pull_up_12ma>;
	};
	};

	lcdc {
	lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
	rockchip,pins =
	<3 RK_PA0 1 &pcfg_pull_none_12ma>;
	};

	lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
	rockchip,pins =
	<3 RK_PA1 1 &pcfg_pull_none_12ma>;
	};

	lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
	rockchip,pins =
	<3 RK_PA2 1 &pcfg_pull_none_12ma>;
	};

	lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
	rockchip,pins =
	<3 RK_PA3 1 &pcfg_pull_none_12ma>;
	};

	lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
	rockchip,pins =
	<3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
	<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
	<3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
	<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
	<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
	<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
	<3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
	<3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
	<3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
	<3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
	<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
	<3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
	<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
	<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
	<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
	<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
	<3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
	<3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
	<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
	<3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
	<3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
	<3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
	<3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
	<3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
	};

	lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
	rockchip,pins =
	<3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
	<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
	<3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
	<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
	<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
	<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
	<3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
	<3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
	<3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
	<3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
	<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
	<3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
	<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
	<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
	<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
	<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
	<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
	<3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
	};

	lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
	rockchip,pins =
	<3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
	<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
	<3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
	<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
	<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
	<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
	<3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
	<3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
	<3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
	<3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
	<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
	<3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
	<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
	<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
	<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
	<3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
	};

	lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
	rockchip,pins =
	<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
	<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
	<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
	<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
	<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
	<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
	<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
	<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
	<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
	<3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
	<3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
	<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
	<3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
	<3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
	<3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
	<3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
	<3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
	};

	lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
	rockchip,pins =
	<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
	<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
	<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
	<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
	<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
	<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
	<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
	<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
	<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
	<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
	<3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
	};

	lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
	rockchip,pins =
	<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
	<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
	<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
	<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
	<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
	<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
	<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
	<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
	<3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
	};
	};

	pwm0 {
	pwm0_pin: pwm0-pin {
	rockchip,pins =
	<0 RK_PB7 1 &pcfg_pull_none>;
	};
	};

	pwm1 {
	pwm1_pin: pwm1-pin {
	rockchip,pins =
	<0 RK_PC0 1 &pcfg_pull_none>;
	};
	};

	pwm2 {
	pwm2_pin: pwm2-pin {
	rockchip,pins =
	<2 RK_PB5 1 &pcfg_pull_none>;
	};
	};

	pwm3 {
	pwm3_pin: pwm3-pin {
	rockchip,pins =
	<0 RK_PC1 1 &pcfg_pull_none>;
	};
	};

	pwm4 {
	pwm4_pin: pwm4-pin {
	rockchip,pins =
	<3 RK_PC2 3 &pcfg_pull_none>;
	};
	};

	pwm5 {
	pwm5_pin: pwm5-pin {
	rockchip,pins =
	<3 RK_PC3 3 &pcfg_pull_none>;
	};
	};

	pwm6 {
	pwm6_pin: pwm6-pin {
	rockchip,pins =
	<3 RK_PC4 3 &pcfg_pull_none>;
	};
	};

	pwm7 {
	pwm7_pin: pwm7-pin {
	rockchip,pins =
	<3 RK_PC5 3 &pcfg_pull_none>;
	};
	};

	gmac {
	rmii_pins: rmii-pins {
	rockchip,pins =
	<2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
	<2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
	<2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
	<2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
	<2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
	<2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
	<2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
	<2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
	<2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
	};

	mac_refclk_12ma: mac-refclk-12ma {
	rockchip,pins =
	<2 RK_PB2 2 &pcfg_pull_none_12ma>;
	};

	mac_refclk: mac-refclk {
	rockchip,pins =
	<2 RK_PB2 2 &pcfg_pull_none>;
	};
	};

	cif-m0 {
	cif_clkout_m0: cif-clkout-m0 {
	rockchip,pins =
	<2 RK_PB3 1 &pcfg_pull_none>;
	};

	dvp_d2d9_m0: dvp-d2d9-m0 {
	rockchip,pins =
	<2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
	<2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
	<2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
	<2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
	<2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
	<2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
	<2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
	<2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
	<2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
	<2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
	<2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
	<2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
	};

	dvp_d0d1_m0: dvp-d0d1-m0 {
	rockchip,pins =
	<2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
	<2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
	};

	dvp_d10d11_m0:d10-d11-m0 {
	rockchip,pins =
	<2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
	<2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
	};
	};

	cif-m1 {
	cif_clkout_m1: cif-clkout-m1 {
	rockchip,pins =
	<3 RK_PD0 3 &pcfg_pull_none>;
	};

	dvp_d2d9_m1: dvp-d2d9-m1 {
	rockchip,pins =
	<3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
	<3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
	<3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
	<3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
	<3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
	<3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
	<3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
	<3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
	<3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
	<3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
	<3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
	<3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
	};

	dvp_d0d1_m1: dvp-d0d1-m1 {
	rockchip,pins =
	<3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
	<3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
	};

	dvp_d10d11_m1:d10-d11-m1 {
	rockchip,pins =
	<3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
	<3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
	};
	};

	isp {
	isp_prelight: isp-prelight {
	rockchip,pins =
	<3 RK_PD1 4 &pcfg_pull_none>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3308.dtsi b/sys/gnu/dts/arm64/rockchip/rk3308.dtsi
	index 116f1900effb..ac7f694079d0 100644
	--- a/sys/gnu/dts/arm64/rockchip/rk3308.dtsi
	+++ b/sys/gnu/dts/arm64/rockchip/rk3308.dtsi
	@@ -1,1739 +1,1739 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
	*
	*/

	#include <dt-bindings/clock/rk3308-cru.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/pinctrl/rockchip.h>
	#include <dt-bindings/soc/rockchip,boot-mode.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	compatible = "rockchip,rk3308";

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	serial0 = &uart0;
	serial1 = &uart1;
	serial2 = &uart2;
	serial3 = &uart3;
	serial4 = &uart4;
	spi0 = &spi0;
	spi1 = &spi1;
	spi2 = &spi2;
	};

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	- compatible = "arm,cortex-a35", "arm,armv8";
	+ compatible = "arm,cortex-a35";
	reg = <0x0 0x0>;
	enable-method = "psci";
	clocks = <&cru ARMCLK>;
	#cooling-cells = <2>;
	dynamic-power-coefficient = <90>;
	operating-points-v2 = <&cpu0_opp_table>;
	cpu-idle-states = <&CPU_SLEEP>;
	next-level-cache = <&l2>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	- compatible = "arm,cortex-a35", "arm,armv8";
	+ compatible = "arm,cortex-a35";
	reg = <0x0 0x1>;
	enable-method = "psci";
	operating-points-v2 = <&cpu0_opp_table>;
	cpu-idle-states = <&CPU_SLEEP>;
	next-level-cache = <&l2>;
	};

	cpu2: cpu@2 {
	device_type = "cpu";
	- compatible = "arm,cortex-a35", "arm,armv8";
	+ compatible = "arm,cortex-a35";
	reg = <0x0 0x2>;
	enable-method = "psci";
	operating-points-v2 = <&cpu0_opp_table>;
	cpu-idle-states = <&CPU_SLEEP>;
	next-level-cache = <&l2>;
	};

	cpu3: cpu@3 {
	device_type = "cpu";
	- compatible = "arm,cortex-a35", "arm,armv8";
	+ compatible = "arm,cortex-a35";
	reg = <0x0 0x3>;
	enable-method = "psci";
	operating-points-v2 = <&cpu0_opp_table>;
	cpu-idle-states = <&CPU_SLEEP>;
	next-level-cache = <&l2>;
	};

	idle-states {
	entry-method = "psci";

	CPU_SLEEP: cpu-sleep {
	compatible = "arm,idle-state";
	local-timer-stop;
	arm,psci-suspend-param = <0x0010000>;
	entry-latency-us = <120>;
	exit-latency-us = <250>;
	min-residency-us = <900>;
	};
	};

	l2: l2-cache {
	compatible = "cache";
	};
	};

	cpu0_opp_table: cpu0-opp-table {
	compatible = "operating-points-v2";
	opp-shared;

	opp-408000000 {
	opp-hz = /bits/ 64 <408000000>;
	opp-microvolt = <950000 950000 1340000>;
	clock-latency-ns = <40000>;
	opp-suspend;
	};
	opp-600000000 {
	opp-hz = /bits/ 64 <600000000>;
	opp-microvolt = <950000 950000 1340000>;
	clock-latency-ns = <40000>;
	};
	opp-816000000 {
	opp-hz = /bits/ 64 <816000000>;
	opp-microvolt = <1025000 1025000 1340000>;
	clock-latency-ns = <40000>;
	};
	opp-1008000000 {
	opp-hz = /bits/ 64 <1008000000>;
	opp-microvolt = <1125000 1125000 1340000>;
	clock-latency-ns = <40000>;
	};
	};

	arm-pmu {
	- compatible = "arm,cortex-a53-pmu";
	+ compatible = "arm,cortex-a35-pmu";
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	mac_clkin: external-mac-clock {
	compatible = "fixed-clock";
	clock-frequency = <50000000>;
	clock-output-names = "mac_clkin";
	#clock-cells = <0>;
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	xin24m: xin24m {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "xin24m";
	};

	grf: grf@ff000000 {
	compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
	reg = <0x0 0xff000000 0x0 0x10000>;

	reboot-mode {
	compatible = "syscon-reboot-mode";
	offset = <0x500>;
	mode-bootloader = <BOOT_BL_DOWNLOAD>;
	mode-loader = <BOOT_BL_DOWNLOAD>;
	mode-normal = <BOOT_NORMAL>;
	mode-recovery = <BOOT_RECOVERY>;
	mode-fastboot = <BOOT_FASTBOOT>;
	};
	};

	detect_grf: syscon@ff00b000 {
	compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
	reg = <0x0 0xff00b000 0x0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	};

	core_grf: syscon@ff00c000 {
	compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
	reg = <0x0 0xff00c000 0x0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	};

	i2c0: i2c@ff040000 {
	compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
	reg = <0x0 0xff040000 0x0 0x1000>;
	clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
	clock-names = "i2c", "pclk";
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c1: i2c@ff050000 {
	compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
	reg = <0x0 0xff050000 0x0 0x1000>;
	clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
	clock-names = "i2c", "pclk";
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c2: i2c@ff060000 {
	compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
	reg = <0x0 0xff060000 0x0 0x1000>;
	clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
	clock-names = "i2c", "pclk";
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c3: i2c@ff070000 {
	compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
	reg = <0x0 0xff070000 0x0 0x1000>;
	clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
	clock-names = "i2c", "pclk";
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3m0_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	wdt: watchdog@ff080000 {
	compatible = "snps,dw-wdt";
	reg = <0x0 0xff080000 0x0 0x100>;
	clocks = <&cru PCLK_WDT>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	uart0: serial@ff0a0000 {
	compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff0a0000 0x0 0x100>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
	clock-names = "baudclk", "apb_pclk";
	reg-shift = <2>;
	reg-io-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
	status = "disabled";
	};

	uart1: serial@ff0b0000 {
	compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff0b0000 0x0 0x100>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
	clock-names = "baudclk", "apb_pclk";
	reg-shift = <2>;
	reg-io-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
	status = "disabled";
	};

	uart2: serial@ff0c0000 {
	compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff0c0000 0x0 0x100>;
	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
	clock-names = "baudclk", "apb_pclk";
	reg-shift = <2>;
	reg-io-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart2m0_xfer>;
	status = "disabled";
	};

	uart3: serial@ff0d0000 {
	compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff0d0000 0x0 0x100>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
	clock-names = "baudclk", "apb_pclk";
	reg-shift = <2>;
	reg-io-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_xfer>;
	status = "disabled";
	};

	uart4: serial@ff0e0000 {
	compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff0e0000 0x0 0x100>;
	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
	clock-names = "baudclk", "apb_pclk";
	reg-shift = <2>;
	reg-io-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
	status = "disabled";
	};

	spi0: spi@ff120000 {
	compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
	reg = <0x0 0xff120000 0x0 0x1000>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
	clock-names = "spiclk", "apb_pclk";
	dmas = <&dmac0 0>, <&dmac0 1>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
	status = "disabled";
	};

	spi1: spi@ff130000 {
	compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
	reg = <0x0 0xff130000 0x0 0x1000>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
	clock-names = "spiclk", "apb_pclk";
	dmas = <&dmac0 2>, <&dmac0 3>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
	status = "disabled";
	};

	spi2: spi@ff140000 {
	compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
	reg = <0x0 0xff140000 0x0 0x1000>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
	clock-names = "spiclk", "apb_pclk";
	dmas = <&dmac1 16>, <&dmac1 17>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
	status = "disabled";
	};

	pwm8: pwm@ff160000 {
	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff160000 0x0 0x10>;
	clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm8_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm9: pwm@ff160010 {
	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff160010 0x0 0x10>;
	clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm9_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm10: pwm@ff160020 {
	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff160020 0x0 0x10>;
	clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm10_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm11: pwm@ff160030 {
	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff160030 0x0 0x10>;
	clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm11_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm4: pwm@ff170000 {
	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff170000 0x0 0x10>;
	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm4_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm5: pwm@ff170010 {
	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff170010 0x0 0x10>;
	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm5_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm6: pwm@ff170020 {
	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff170020 0x0 0x10>;
	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm6_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm7: pwm@ff170030 {
	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff170030 0x0 0x10>;
	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm7_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm0: pwm@ff180000 {
	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff180000 0x0 0x10>;
	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm1: pwm@ff180010 {
	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff180010 0x0 0x10>;
	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm2: pwm@ff180020 {
	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff180020 0x0 0x10>;
	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm3: pwm@ff180030 {
	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
	reg = <0x0 0xff180030 0x0 0x10>;
	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	rktimer: rktimer@ff1a0000 {
	compatible = "rockchip,rk3288-timer";
	reg = <0x0 0xff1a0000 0x0 0x20>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
	clock-names = "pclk", "timer";
	};

	saradc: saradc@ff1e0000 {
	compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
	reg = <0x0 0xff1e0000 0x0 0x100>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
	clock-names = "saradc", "apb_pclk";
	#io-channel-cells = <1>;
	resets = <&cru SRST_SARADC_P>;
	reset-names = "saradc-apb";
	status = "disabled";
	};

	- amba {
	+ amba: bus {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	dmac0: dma-controller@ff2c0000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x0 0xff2c0000 0x0 0x4000>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru ACLK_DMAC0>;
	clock-names = "apb_pclk";
	#dma-cells = <1>;
	};

	dmac1: dma-controller@ff2d0000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x0 0xff2d0000 0x0 0x4000>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru ACLK_DMAC1>;
	clock-names = "apb_pclk";
	#dma-cells = <1>;
	};
	};

	i2s_2ch_0: i2s@ff350000 {
	compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
	reg = <0x0 0xff350000 0x0 0x1000>;
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>;
	clock-names = "i2s_clk", "i2s_hclk";
	dmas = <&dmac1 8>, <&dmac1 9>;
	dma-names = "tx", "rx";
	resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>;
	reset-names = "reset-m", "reset-h";
	pinctrl-names = "default";
	pinctrl-0 = <&i2s_2ch_0_sclk
	&i2s_2ch_0_lrck
	&i2s_2ch_0_sdi
	&i2s_2ch_0_sdo>;
	status = "disabled";
	};

	i2s_2ch_1: i2s@ff360000 {
	compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
	reg = <0x0 0xff360000 0x0 0x1000>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>;
	clock-names = "i2s_clk", "i2s_hclk";
	dmas = <&dmac1 11>;
	dma-names = "rx";
	resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>;
	reset-names = "reset-m", "reset-h";
	status = "disabled";
	};

	spdif_tx: spdif-tx@ff3a0000 {
	compatible = "rockchip,rk3308-spdif", "rockchip,rk3328-spdif";
	reg = <0x0 0xff3a0000 0x0 0x1000>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
	clock-names = "mclk", "hclk";
	dmas = <&dmac1 13>;
	dma-names = "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&spdif_out>;
	status = "disabled";
	};

	sdmmc: mmc@ff480000 {
	compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x0 0xff480000 0x0 0x4000>;
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	bus-width = <4>;
	clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
	<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	max-frequency = <150000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
	status = "disabled";
	};

	emmc: mmc@ff490000 {
	compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x0 0xff490000 0x0 0x4000>;
	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	bus-width = <8>;
	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
	<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	max-frequency = <150000000>;
	status = "disabled";
	};

	sdio: mmc@ff4a0000 {
	compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x0 0xff4a0000 0x0 0x4000>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	bus-width = <4>;
	clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
	<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	max-frequency = <150000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
	status = "disabled";
	};

	cru: clock-controller@ff500000 {
	compatible = "rockchip,rk3308-cru";
	reg = <0x0 0xff500000 0x0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	rockchip,grf = <&grf>;

	assigned-clocks = <&cru SCLK_RTC32K>;
	assigned-clock-rates = <32768>;
	};

	gic: interrupt-controller@ff580000 {
	compatible = "arm,gic-400";
	reg = <0x0 0xff581000 0x0 0x1000>,
	<0x0 0xff582000 0x0 0x2000>,
	<0x0 0xff584000 0x0 0x2000>,
	<0x0 0xff586000 0x0 0x2000>;
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	#interrupt-cells = <3>;
	interrupt-controller;
	#address-cells = <0>;
	};

	sram: sram@fff80000 {
	compatible = "mmio-sram";
	reg = <0x0 0xfff80000 0x0 0x40000>;
	ranges = <0 0x0 0xfff80000 0x40000>;
	#address-cells = <1>;
	#size-cells = <1>;

	/* reserved for ddr dvfs and system suspend/resume */
	ddr-sram@0 {
	reg = <0x0 0x8000>;
	};

	/* reserved for vad audio buffer */
	vad_sram: vad-sram@8000 {
	reg = <0x8000 0x38000>;
	};
	};

	pinctrl: pinctrl {
	compatible = "rockchip,rk3308-pinctrl";
	rockchip,grf = <&grf>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	gpio0: gpio0@ff220000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff220000 0x0 0x100>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO0>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio1: gpio1@ff230000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff230000 0x0 0x100>;
	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO1>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio2@ff240000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff240000 0x0 0x100>;
	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO2>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio3@ff250000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff250000 0x0 0x100>;
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO3>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio4: gpio4@ff260000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff260000 0x0 0x100>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO4>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	pcfg_pull_up: pcfg-pull-up {
	bias-pull-up;
	};

	pcfg_pull_down: pcfg-pull-down {
	bias-pull-down;
	};

	pcfg_pull_none: pcfg-pull-none {
	bias-disable;
	};

	pcfg_pull_none_2ma: pcfg-pull-none-2ma {
	bias-disable;
	drive-strength = <2>;
	};

	pcfg_pull_up_2ma: pcfg-pull-up-2ma {
	bias-pull-up;
	drive-strength = <2>;
	};

	pcfg_pull_up_4ma: pcfg-pull-up-4ma {
	bias-pull-up;
	drive-strength = <4>;
	};

	pcfg_pull_none_4ma: pcfg-pull-none-4ma {
	bias-disable;
	drive-strength = <4>;
	};

	pcfg_pull_down_4ma: pcfg-pull-down-4ma {
	bias-pull-down;
	drive-strength = <4>;
	};

	pcfg_pull_none_8ma: pcfg-pull-none-8ma {
	bias-disable;
	drive-strength = <8>;
	};

	pcfg_pull_up_8ma: pcfg-pull-up-8ma {
	bias-pull-up;
	drive-strength = <8>;
	};

	pcfg_pull_none_12ma: pcfg-pull-none-12ma {
	bias-disable;
	drive-strength = <12>;
	};

	pcfg_pull_up_12ma: pcfg-pull-up-12ma {
	bias-pull-up;
	drive-strength = <12>;
	};

	pcfg_pull_none_smt: pcfg-pull-none-smt {
	bias-disable;
	input-schmitt-enable;
	};

	pcfg_output_high: pcfg-output-high {
	output-high;
	};

	pcfg_output_low: pcfg-output-low {
	output-low;
	};

	pcfg_input_high: pcfg-input-high {
	bias-pull-up;
	input-enable;
	};

	pcfg_input: pcfg-input {
	input-enable;
	};

	emmc {
	emmc_clk: emmc-clk {
	rockchip,pins =
	<3 RK_PB1 2 &pcfg_pull_none_8ma>;
	};

	emmc_cmd: emmc-cmd {
	rockchip,pins =
	<3 RK_PB0 2 &pcfg_pull_up_8ma>;
	};

	emmc_pwren: emmc-pwren {
	rockchip,pins =
	<3 RK_PB3 2 &pcfg_pull_none>;
	};

	emmc_rstn: emmc-rstn {
	rockchip,pins =
	<3 RK_PB2 2 &pcfg_pull_none>;
	};

	emmc_bus1: emmc-bus1 {
	rockchip,pins =
	<3 RK_PA0 2 &pcfg_pull_up_8ma>;
	};

	emmc_bus4: emmc-bus4 {
	rockchip,pins =
	<3 RK_PA0 2 &pcfg_pull_up_8ma>,
	<3 RK_PA1 2 &pcfg_pull_up_8ma>,
	<3 RK_PA2 2 &pcfg_pull_up_8ma>,
	<3 RK_PA3 2 &pcfg_pull_up_8ma>;
	};

	emmc_bus8: emmc-bus8 {
	rockchip,pins =
	<3 RK_PA0 2 &pcfg_pull_up_8ma>,
	<3 RK_PA1 2 &pcfg_pull_up_8ma>,
	<3 RK_PA2 2 &pcfg_pull_up_8ma>,
	<3 RK_PA3 2 &pcfg_pull_up_8ma>,
	<3 RK_PA4 2 &pcfg_pull_up_8ma>,
	<3 RK_PA5 2 &pcfg_pull_up_8ma>,
	<3 RK_PA6 2 &pcfg_pull_up_8ma>,
	<3 RK_PA7 2 &pcfg_pull_up_8ma>;
	};
	};

	flash {
	flash_csn0: flash-csn0 {
	rockchip,pins =
	<3 RK_PB5 1 &pcfg_pull_none>;
	};

	flash_rdy: flash-rdy {
	rockchip,pins =
	<3 RK_PB4 1 &pcfg_pull_none>;
	};

	flash_ale: flash-ale {
	rockchip,pins =
	<3 RK_PB3 1 &pcfg_pull_none>;
	};

	flash_cle: flash-cle {
	rockchip,pins =
	<3 RK_PB1 1 &pcfg_pull_none>;
	};

	flash_wrn: flash-wrn {
	rockchip,pins =
	<3 RK_PB0 1 &pcfg_pull_none>;
	};

	flash_rdn: flash-rdn {
	rockchip,pins =
	<3 RK_PB2 1 &pcfg_pull_none>;
	};

	flash_bus8: flash-bus8 {
	rockchip,pins =
	<3 RK_PA0 1 &pcfg_pull_up_12ma>,
	<3 RK_PA1 1 &pcfg_pull_up_12ma>,
	<3 RK_PA2 1 &pcfg_pull_up_12ma>,
	<3 RK_PA3 1 &pcfg_pull_up_12ma>,
	<3 RK_PA4 1 &pcfg_pull_up_12ma>,
	<3 RK_PA5 1 &pcfg_pull_up_12ma>,
	<3 RK_PA6 1 &pcfg_pull_up_12ma>,
	<3 RK_PA7 1 &pcfg_pull_up_12ma>;
	};
	};

	gmac {
	rmii_pins: rmii-pins {
	rockchip,pins =
	/* mac_txen */
	<1 RK_PC1 3 &pcfg_pull_none_12ma>,
	/* mac_txd1 */
	<1 RK_PC3 3 &pcfg_pull_none_12ma>,
	/* mac_txd0 */
	<1 RK_PC2 3 &pcfg_pull_none_12ma>,
	/* mac_rxd0 */
	<1 RK_PC4 3 &pcfg_pull_none>,
	/* mac_rxd1 */
	<1 RK_PC5 3 &pcfg_pull_none>,
	/* mac_rxer */
	<1 RK_PB7 3 &pcfg_pull_none>,
	/* mac_rxdv */
	<1 RK_PC0 3 &pcfg_pull_none>,
	/* mac_mdio */
	<1 RK_PB6 3 &pcfg_pull_none>,
	/* mac_mdc */
	<1 RK_PB5 3 &pcfg_pull_none>;
	};

	mac_refclk_12ma: mac-refclk-12ma {
	rockchip,pins =
	<1 RK_PB4 3 &pcfg_pull_none_12ma>;
	};

	mac_refclk: mac-refclk {
	rockchip,pins =
	<1 RK_PB4 3 &pcfg_pull_none>;
	};
	};

	gmac-m1 {
	rmiim1_pins: rmiim1-pins {
	rockchip,pins =
	/* mac_txen */
	<4 RK_PB7 2 &pcfg_pull_none_12ma>,
	/* mac_txd1 */
	<4 RK_PA5 2 &pcfg_pull_none_12ma>,
	/* mac_txd0 */
	<4 RK_PA4 2 &pcfg_pull_none_12ma>,
	/* mac_rxd0 */
	<4 RK_PA2 2 &pcfg_pull_none>,
	/* mac_rxd1 */
	<4 RK_PA3 2 &pcfg_pull_none>,
	/* mac_rxer */
	<4 RK_PA0 2 &pcfg_pull_none>,
	/* mac_rxdv */
	<4 RK_PA1 2 &pcfg_pull_none>,
	/* mac_mdio */
	<4 RK_PB6 2 &pcfg_pull_none>,
	/* mac_mdc */
	<4 RK_PB5 2 &pcfg_pull_none>;
	};

	macm1_refclk_12ma: macm1-refclk-12ma {
	rockchip,pins =
	<4 RK_PB4 2 &pcfg_pull_none_12ma>;
	};

	macm1_refclk: macm1-refclk {
	rockchip,pins =
	<4 RK_PB4 2 &pcfg_pull_none>;
	};
	};

	i2c0 {
	i2c0_xfer: i2c0-xfer {
	rockchip,pins =
	<1 RK_PD0 2 &pcfg_pull_none_smt>,
	<1 RK_PD1 2 &pcfg_pull_none_smt>;
	};
	};

	i2c1 {
	i2c1_xfer: i2c1-xfer {
	rockchip,pins =
	<0 RK_PB3 1 &pcfg_pull_none_smt>,
	<0 RK_PB4 1 &pcfg_pull_none_smt>;
	};
	};

	i2c2 {
	i2c2_xfer: i2c2-xfer {
	rockchip,pins =
	<2 RK_PA2 3 &pcfg_pull_none_smt>,
	<2 RK_PA3 3 &pcfg_pull_none_smt>;
	};
	};

	i2c3-m0 {
	i2c3m0_xfer: i2c3m0-xfer {
	rockchip,pins =
	<0 RK_PB7 2 &pcfg_pull_none_smt>,
	<0 RK_PC0 2 &pcfg_pull_none_smt>;
	};
	};

	i2c3-m1 {
	i2c3m1_xfer: i2c3m1-xfer {
	rockchip,pins =
	<3 RK_PB4 2 &pcfg_pull_none_smt>,
	<3 RK_PB5 2 &pcfg_pull_none_smt>;
	};
	};

	i2c3-m2 {
	i2c3m2_xfer: i2c3m2-xfer {
	rockchip,pins =
	<2 RK_PA1 3 &pcfg_pull_none_smt>,
	<2 RK_PA0 3 &pcfg_pull_none_smt>;
	};
	};

	i2s_2ch_0 {
	i2s_2ch_0_mclk: i2s-2ch-0-mclk {
	rockchip,pins =
	<4 RK_PB4 1 &pcfg_pull_none>;
	};

	i2s_2ch_0_sclk: i2s-2ch-0-sclk {
	rockchip,pins =
	<4 RK_PB5 1 &pcfg_pull_none>;
	};

	i2s_2ch_0_lrck: i2s-2ch-0-lrck {
	rockchip,pins =
	<4 RK_PB6 1 &pcfg_pull_none>;
	};

	i2s_2ch_0_sdo: i2s-2ch-0-sdo {
	rockchip,pins =
	<4 RK_PB7 1 &pcfg_pull_none>;
	};

	i2s_2ch_0_sdi: i2s-2ch-0-sdi {
	rockchip,pins =
	<4 RK_PC0 1 &pcfg_pull_none>;
	};
	};

	i2s_8ch_0 {
	i2s_8ch_0_mclk: i2s-8ch-0-mclk {
	rockchip,pins =
	<2 RK_PA4 1 &pcfg_pull_none>;
	};

	i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
	rockchip,pins =
	<2 RK_PA5 1 &pcfg_pull_none>;
	};

	i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
	rockchip,pins =
	<2 RK_PA6 1 &pcfg_pull_none>;
	};

	i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
	rockchip,pins =
	<2 RK_PA7 1 &pcfg_pull_none>;
	};

	i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
	rockchip,pins =
	<2 RK_PB0 1 &pcfg_pull_none>;
	};

	i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
	rockchip,pins =
	<2 RK_PB1 1 &pcfg_pull_none>;
	};

	i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
	rockchip,pins =
	<2 RK_PB2 1 &pcfg_pull_none>;
	};

	i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
	rockchip,pins =
	<2 RK_PB3 1 &pcfg_pull_none>;
	};

	i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
	rockchip,pins =
	<2 RK_PB4 1 &pcfg_pull_none>;
	};

	i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
	rockchip,pins =
	<2 RK_PB5 1 &pcfg_pull_none>;
	};

	i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
	rockchip,pins =
	<2 RK_PB6 1 &pcfg_pull_none>;
	};

	i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
	rockchip,pins =
	<2 RK_PB7 1 &pcfg_pull_none>;
	};

	i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
	rockchip,pins =
	<2 RK_PC0 1 &pcfg_pull_none>;
	};
	};

	i2s_8ch_1_m0 {
	i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
	rockchip,pins =
	<1 RK_PA2 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
	rockchip,pins =
	<1 RK_PA3 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
	rockchip,pins =
	<1 RK_PA4 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
	rockchip,pins =
	<1 RK_PA5 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
	rockchip,pins =
	<1 RK_PA6 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
	rockchip,pins =
	<1 RK_PA7 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
	rockchip,pins =
	<1 RK_PB0 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
	rockchip,pins =
	<1 RK_PB1 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
	rockchip,pins =
	<1 RK_PB2 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
	rockchip,pins =
	<1 RK_PB3 2 &pcfg_pull_none>;
	};
	};

	i2s_8ch_1_m1 {
	i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
	rockchip,pins =
	<1 RK_PB4 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
	rockchip,pins =
	<1 RK_PB5 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
	rockchip,pins =
	<1 RK_PB6 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
	rockchip,pins =
	<1 RK_PB7 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
	rockchip,pins =
	<1 RK_PC0 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
	rockchip,pins =
	<1 RK_PC1 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
	rockchip,pins =
	<1 RK_PC2 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
	rockchip,pins =
	<1 RK_PC3 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
	rockchip,pins =
	<1 RK_PC4 2 &pcfg_pull_none>;
	};

	i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
	rockchip,pins =
	<1 RK_PC5 2 &pcfg_pull_none>;
	};
	};

	pdm_m0 {
	pdm_m0_clk: pdm-m0-clk {
	rockchip,pins =
	<1 RK_PA4 3 &pcfg_pull_none>;
	};

	pdm_m0_sdi0: pdm-m0-sdi0 {
	rockchip,pins =
	<1 RK_PB3 3 &pcfg_pull_none>;
	};

	pdm_m0_sdi1: pdm-m0-sdi1 {
	rockchip,pins =
	<1 RK_PB2 3 &pcfg_pull_none>;
	};

	pdm_m0_sdi2: pdm-m0-sdi2 {
	rockchip,pins =
	<1 RK_PB1 3 &pcfg_pull_none>;
	};

	pdm_m0_sdi3: pdm-m0-sdi3 {
	rockchip,pins =
	<1 RK_PB0 3 &pcfg_pull_none>;
	};
	};

	pdm_m1 {
	pdm_m1_clk: pdm-m1-clk {
	rockchip,pins =
	<1 RK_PB6 4 &pcfg_pull_none>;
	};

	pdm_m1_sdi0: pdm-m1-sdi0 {
	rockchip,pins =
	<1 RK_PC5 4 &pcfg_pull_none>;
	};

	pdm_m1_sdi1: pdm-m1-sdi1 {
	rockchip,pins =
	<1 RK_PC4 4 &pcfg_pull_none>;
	};

	pdm_m1_sdi2: pdm-m1-sdi2 {
	rockchip,pins =
	<1 RK_PC3 4 &pcfg_pull_none>;
	};

	pdm_m1_sdi3: pdm-m1-sdi3 {
	rockchip,pins =
	<1 RK_PC2 4 &pcfg_pull_none>;
	};
	};

	pdm_m2 {
	pdm_m2_clkm: pdm-m2-clkm {
	rockchip,pins =
	<2 RK_PA4 3 &pcfg_pull_none>;
	};

	pdm_m2_clk: pdm-m2-clk {
	rockchip,pins =
	<2 RK_PA6 2 &pcfg_pull_none>;
	};

	pdm_m2_sdi0: pdm-m2-sdi0 {
	rockchip,pins =
	<2 RK_PB5 2 &pcfg_pull_none>;
	};

	pdm_m2_sdi1: pdm-m2-sdi1 {
	rockchip,pins =
	<2 RK_PB6 2 &pcfg_pull_none>;
	};

	pdm_m2_sdi2: pdm-m2-sdi2 {
	rockchip,pins =
	<2 RK_PB7 2 &pcfg_pull_none>;
	};

	pdm_m2_sdi3: pdm-m2-sdi3 {
	rockchip,pins =
	<2 RK_PC0 2 &pcfg_pull_none>;
	};
	};

	pwm0 {
	pwm0_pin: pwm0-pin {
	rockchip,pins =
	<0 RK_PB5 1 &pcfg_pull_none>;
	};

	pwm0_pin_pull_down: pwm0-pin-pull-down {
	rockchip,pins =
	<0 RK_PB5 1 &pcfg_pull_down>;
	};
	};

	pwm1 {
	pwm1_pin: pwm1-pin {
	rockchip,pins =
	<0 RK_PB6 1 &pcfg_pull_none>;
	};

	pwm1_pin_pull_down: pwm1-pin-pull-down {
	rockchip,pins =
	<0 RK_PB6 1 &pcfg_pull_down>;
	};
	};

	pwm2 {
	pwm2_pin: pwm2-pin {
	rockchip,pins =
	<0 RK_PB7 1 &pcfg_pull_none>;
	};

	pwm2_pin_pull_down: pwm2-pin-pull-down {
	rockchip,pins =
	<0 RK_PB7 1 &pcfg_pull_down>;
	};
	};

	pwm3 {
	pwm3_pin: pwm3-pin {
	rockchip,pins =
	<0 RK_PC0 1 &pcfg_pull_none>;
	};

	pwm3_pin_pull_down: pwm3-pin-pull-down {
	rockchip,pins =
	<0 RK_PC0 1 &pcfg_pull_down>;
	};
	};

	pwm4 {
	pwm4_pin: pwm4-pin {
	rockchip,pins =
	<0 RK_PA1 2 &pcfg_pull_none>;
	};

	pwm4_pin_pull_down: pwm4-pin-pull-down {
	rockchip,pins =
	<0 RK_PA1 2 &pcfg_pull_down>;
	};
	};

	pwm5 {
	pwm5_pin: pwm5-pin {
	rockchip,pins =
	<0 RK_PC1 2 &pcfg_pull_none>;
	};

	pwm5_pin_pull_down: pwm5-pin-pull-down {
	rockchip,pins =
	<0 RK_PC1 2 &pcfg_pull_down>;
	};
	};

	pwm6 {
	pwm6_pin: pwm6-pin {
	rockchip,pins =
	<0 RK_PC2 2 &pcfg_pull_none>;
	};

	pwm6_pin_pull_down: pwm6-pin-pull-down {
	rockchip,pins =
	<0 RK_PC2 2 &pcfg_pull_down>;
	};
	};

	pwm7 {
	pwm7_pin: pwm7-pin {
	rockchip,pins =
	<2 RK_PB0 2 &pcfg_pull_none>;
	};

	pwm7_pin_pull_down: pwm7-pin-pull-down {
	rockchip,pins =
	<2 RK_PB0 2 &pcfg_pull_down>;
	};
	};

	pwm8 {
	pwm8_pin: pwm8-pin {
	rockchip,pins =
	<2 RK_PB2 2 &pcfg_pull_none>;
	};

	pwm8_pin_pull_down: pwm8-pin-pull-down {
	rockchip,pins =
	<2 RK_PB2 2 &pcfg_pull_down>;
	};
	};

	pwm9 {
	pwm9_pin: pwm9-pin {
	rockchip,pins =
	<2 RK_PB3 2 &pcfg_pull_none>;
	};

	pwm9_pin_pull_down: pwm9-pin-pull-down {
	rockchip,pins =
	<2 RK_PB3 2 &pcfg_pull_down>;
	};
	};

	pwm10 {
	pwm10_pin: pwm10-pin {
	rockchip,pins =
	<2 RK_PB4 2 &pcfg_pull_none>;
	};

	pwm10_pin_pull_down: pwm10-pin-pull-down {
	rockchip,pins =
	<2 RK_PB4 2 &pcfg_pull_down>;
	};
	};

	pwm11 {
	pwm11_pin: pwm11-pin {
	rockchip,pins =
	<2 RK_PC0 4 &pcfg_pull_none>;
	};

	pwm11_pin_pull_down: pwm11-pin-pull-down {
	rockchip,pins =
	<2 RK_PC0 4 &pcfg_pull_down>;
	};
	};

	rtc {
	rtc_32k: rtc-32k {
	rockchip,pins =
	<0 RK_PC3 1 &pcfg_pull_none>;
	};
	};

	sdmmc {
	sdmmc_clk: sdmmc-clk {
	rockchip,pins =
	<4 RK_PD5 1 &pcfg_pull_none_4ma>;
	};

	sdmmc_cmd: sdmmc-cmd {
	rockchip,pins =
	<4 RK_PD4 1 &pcfg_pull_up_4ma>;
	};

	sdmmc_det: sdmmc-det {
	rockchip,pins =
	<0 RK_PA3 1 &pcfg_pull_up_4ma>;
	};

	sdmmc_pwren: sdmmc-pwren {
	rockchip,pins =
	<4 RK_PD6 1 &pcfg_pull_none_4ma>;
	};

	sdmmc_bus1: sdmmc-bus1 {
	rockchip,pins =
	<4 RK_PD0 1 &pcfg_pull_up_4ma>;
	};

	sdmmc_bus4: sdmmc-bus4 {
	rockchip,pins =
	<4 RK_PD0 1 &pcfg_pull_up_4ma>,
	<4 RK_PD1 1 &pcfg_pull_up_4ma>,
	<4 RK_PD2 1 &pcfg_pull_up_4ma>,
	<4 RK_PD3 1 &pcfg_pull_up_4ma>;
	};
	};

	sdio {
	sdio_clk: sdio-clk {
	rockchip,pins =
	<4 RK_PA5 1 &pcfg_pull_none_8ma>;
	};

	sdio_cmd: sdio-cmd {
	rockchip,pins =
	<4 RK_PA4 1 &pcfg_pull_up_8ma>;
	};

	sdio_pwren: sdio-pwren {
	rockchip,pins =
	<0 RK_PA2 1 &pcfg_pull_none_8ma>;
	};

	sdio_wrpt: sdio-wrpt {
	rockchip,pins =
	<0 RK_PA1 1 &pcfg_pull_none_8ma>;
	};

	sdio_intn: sdio-intn {
	rockchip,pins =
	<0 RK_PA0 1 &pcfg_pull_none_8ma>;
	};

	sdio_bus1: sdio-bus1 {
	rockchip,pins =
	<4 RK_PA0 1 &pcfg_pull_up_8ma>;
	};

	sdio_bus4: sdio-bus4 {
	rockchip,pins =
	<4 RK_PA0 1 &pcfg_pull_up_8ma>,
	<4 RK_PA1 1 &pcfg_pull_up_8ma>,
	<4 RK_PA2 1 &pcfg_pull_up_8ma>,
	<4 RK_PA3 1 &pcfg_pull_up_8ma>;
	};
	};

	spdif_in {
	spdif_in: spdif-in {
	rockchip,pins =
	<0 RK_PC2 1 &pcfg_pull_none>;
	};
	};

	spdif_out {
	spdif_out: spdif-out {
	rockchip,pins =
	<0 RK_PC1 1 &pcfg_pull_none>;
	};
	};

	spi0 {
	spi0_clk: spi0-clk {
	rockchip,pins =
	<2 RK_PA2 2 &pcfg_pull_up_4ma>;
	};

	spi0_csn0: spi0-csn0 {
	rockchip,pins =
	<2 RK_PA3 2 &pcfg_pull_up_4ma>;
	};

	spi0_miso: spi0-miso {
	rockchip,pins =
	<2 RK_PA0 2 &pcfg_pull_up_4ma>;
	};

	spi0_mosi: spi0-mosi {
	rockchip,pins =
	<2 RK_PA1 2 &pcfg_pull_up_4ma>;
	};
	};

	spi1 {
	spi1_clk: spi1-clk {
	rockchip,pins =
	<3 RK_PB3 3 &pcfg_pull_up_4ma>;
	};

	spi1_csn0: spi1-csn0 {
	rockchip,pins =
	<3 RK_PB5 3 &pcfg_pull_up_4ma>;
	};

	spi1_miso: spi1-miso {
	rockchip,pins =
	<3 RK_PB2 3 &pcfg_pull_up_4ma>;
	};

	spi1_mosi: spi1-mosi {
	rockchip,pins =
	<3 RK_PB4 3 &pcfg_pull_up_4ma>;
	};
	};

	spi1-m1 {
	spi1m1_miso: spi1m1-miso {
	rockchip,pins =
	<2 RK_PA4 2 &pcfg_pull_up_4ma>;
	};

	spi1m1_mosi: spi1m1-mosi {
	rockchip,pins =
	<2 RK_PA5 2 &pcfg_pull_up_4ma>;
	};

	spi1m1_clk: spi1m1-clk {
	rockchip,pins =
	<2 RK_PA7 2 &pcfg_pull_up_4ma>;
	};

	spi1m1_csn0: spi1m1-csn0 {
	rockchip,pins =
	<2 RK_PB1 2 &pcfg_pull_up_4ma>;
	};
	};

	spi2 {
	spi2_clk: spi2-clk {
	rockchip,pins =
	<1 RK_PD0 3 &pcfg_pull_up_4ma>;
	};

	spi2_csn0: spi2-csn0 {
	rockchip,pins =
	<1 RK_PD1 3 &pcfg_pull_up_4ma>;
	};

	spi2_miso: spi2-miso {
	rockchip,pins =
	<1 RK_PC6 3 &pcfg_pull_up_4ma>;
	};

	spi2_mosi: spi2-mosi {
	rockchip,pins =
	<1 RK_PC7 3 &pcfg_pull_up_4ma>;
	};
	};

	tsadc {
	tsadc_otp_gpio: tsadc-otp-gpio {
	rockchip,pins =
	<0 RK_PB2 0 &pcfg_pull_none>;
	};

	tsadc_otp_out: tsadc-otp-out {
	rockchip,pins =
	<0 RK_PB2 1 &pcfg_pull_none>;
	};
	};

	uart0 {
	uart0_xfer: uart0-xfer {
	rockchip,pins =
	<2 RK_PA1 1 &pcfg_pull_up>,
	<2 RK_PA0 1 &pcfg_pull_up>;
	};

	uart0_cts: uart0-cts {
	rockchip,pins =
	<2 RK_PA2 1 &pcfg_pull_none>;
	};

	uart0_rts: uart0-rts {
	rockchip,pins =
	<2 RK_PA3 1 &pcfg_pull_none>;
	};

	uart0_rts_gpio: uart0-rts-gpio {
	rockchip,pins =
	<2 RK_PA3 0 &pcfg_pull_none>;
	};
	};

	uart1 {
	uart1_xfer: uart1-xfer {
	rockchip,pins =
	<1 RK_PD1 1 &pcfg_pull_up>,
	<1 RK_PD0 1 &pcfg_pull_up>;
	};

	uart1_cts: uart1-cts {
	rockchip,pins =
	<1 RK_PC6 1 &pcfg_pull_none>;
	};

	uart1_rts: uart1-rts {
	rockchip,pins =
	<1 RK_PC7 1 &pcfg_pull_none>;
	};
	};

	uart2-m0 {
	uart2m0_xfer: uart2m0-xfer {
	rockchip,pins =
	<1 RK_PC7 2 &pcfg_pull_up>,
	<1 RK_PC6 2 &pcfg_pull_up>;
	};
	};

	uart2-m1 {
	uart2m1_xfer: uart2m1-xfer {
	rockchip,pins =
	<4 RK_PD3 2 &pcfg_pull_up>,
	<4 RK_PD2 2 &pcfg_pull_up>;
	};
	};

	uart3 {
	uart3_xfer: uart3-xfer {
	rockchip,pins =
	<3 RK_PB5 4 &pcfg_pull_up>,
	<3 RK_PB4 4 &pcfg_pull_up>;
	};
	};

	uart3-m1 {
	uart3m1_xfer: uart3m1-xfer {
	rockchip,pins =
	<0 RK_PC2 3 &pcfg_pull_up>,
	<0 RK_PC1 3 &pcfg_pull_up>;
	};
	};

	uart4 {
	uart4_xfer: uart4-xfer {
	rockchip,pins =
	<4 RK_PB1 1 &pcfg_pull_up>,
	<4 RK_PB0 1 &pcfg_pull_up>;
	};

	uart4_cts: uart4-cts {
	rockchip,pins =
	<4 RK_PA6 1 &pcfg_pull_none>;
	};

	uart4_rts: uart4-rts {
	rockchip,pins =
	<4 RK_PA7 1 &pcfg_pull_none>;
	};

	uart4_rts_gpio: uart4-rts-gpio {
	rockchip,pins =
	<4 RK_PA7 0 &pcfg_pull_none>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3328-a1.dts b/sys/gnu/dts/arm64/rockchip/rk3328-a1.dts
	index 16f1656d5203..797e90a3ac92 100644
	--- a/sys/gnu/dts/arm64/rockchip/rk3328-a1.dts
	+++ b/sys/gnu/dts/arm64/rockchip/rk3328-a1.dts
	@@ -1,360 +1,361 @@
	// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
	// Copyright (c) 2017-2019 Arm Ltd.

	/dts-v1/;
	#include "rk3328.dtsi"

	/ {
	model = "Beelink A1";
	compatible = "azw,beelink-a1", "rockchip,rk3328";

	/*
	* UART pins, as viewed with bottom of case removed:
	*
	* Front
	* /-------
	* L / o <- Gnd
	* e / o <-- Rx
	* f / o <--- Tx
	* t / o <---- +3.3v
	* \|
	*/
	chosen {
	stdout-path = "serial2:1500000n8";
	};

	gmac_clkin: external-gmac-clock {
	compatible = "fixed-clock";
	clock-frequency = <125000000>;
	clock-output-names = "gmac_clkin";
	#clock-cells = <0>;
	};

	vcc_host_5v: usb3-current-switch {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&usb30_host_drv>;
	regulator-name = "vcc_host_5v";
	vin-supply = <&vcc_sys>;
	};

	vcc_sys: vcc-sys {
	compatible = "regulator-fixed";
	regulator-name = "vcc_sys";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	};

	ir-receiver {
	compatible = "gpio-ir-receiver";
	gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
	linux,rc-map-name = "rc-beelink-gs1";
	};
	};

	&analog_sound {
	simple-audio-card,name = "Analog A/V";
	status = "okay";
	};

	&codec {
	+ mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
	status = "okay";
	};

	&cpu0 {
	cpu-supply = <&vdd_arm>;
	};

	&cpu1 {
	cpu-supply = <&vdd_arm>;
	};

	&cpu2 {
	cpu-supply = <&vdd_arm>;
	};

	&cpu3 {
	cpu-supply = <&vdd_arm>;
	};

	&emmc {
	bus-width = <8>;
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	no-sd;
	no-sdio;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
	vmmc-supply = <&vcc_io>;
	vqmmc-supply = <&vcc18_emmc>;
	status = "okay";
	};

	&gmac2io {
	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
	assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
	clock_in_out = "input";
	phy-handle = <&rtl8211f>;
	phy-mode = "rgmii";
	phy-supply = <&vcc_io>;
	pinctrl-names = "default";
	pinctrl-0 = <&rgmiim1_pins>;
	snps,aal;
	snps,pbl = <0x4>;
	tx_delay = <0x26>;
	rx_delay = <0x11>;
	status = "okay";

	mdio {
	compatible = "snps,dwmac-mdio";
	#address-cells = <1>;
	#size-cells = <0>;

	rtl8211f: phy@0 {
	reg = <0>;
	reset-assert-us = <10000>;
	reset-deassert-us = <30000>;
	reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_LOW>;
	};
	};
	};

	&gpu {
	mali-supply = <&vdd_logic>;
	};

	&hdmi {
	status = "okay";
	};

	&hdmiphy {
	status = "okay";
	};

	&hdmi_sound {
	status = "okay";
	};

	&i2c1 {
	clock-frequency = <1000000>;
	i2c-scl-falling-time-ns = <5>;
	i2c-scl-rising-time-ns = <83>;
	status = "okay";

	pmic@18 {
	compatible = "rockchip,rk805";
	reg = <0x18>;
	interrupt-parent = <&gpio2>;
	interrupts = <RK_PA6 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int_l>;
	rockchip,system-power-controller;
	wakeup-source;

	vcc1-supply = <&vcc_sys>;
	vcc2-supply = <&vcc_sys>;
	vcc3-supply = <&vcc_sys>;
	vcc4-supply = <&vcc_sys>;
	vcc5-supply = <&vcc_io>;
	vcc6-supply = <&vcc_io>;

	regulators {
	vdd_logic: DCDC_REG1 {
	regulator-name = "vdd_logic";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1000000>;
	};
	};

	vdd_arm: DCDC_REG2 {
	regulator-name = "vdd_arm";
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <950000>;
	};
	};

	vcc_ddr: DCDC_REG3 {
	regulator-name = "vcc_ddr";
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	vcc_io: DCDC_REG4 {
	regulator-name = "vcc_io";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3300000>;
	};
	};

	vdd_18: LDO_REG1 {
	regulator-name = "vdd_18";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc18_emmc: LDO_REG2 {
	regulator-name = "vcc_18emmc";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vdd_11: LDO_REG3 {
	regulator-name = "vdd_11";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1100000>;
	};
	};
	};
	};
	};

	&i2s0 {
	status = "okay";
	};

	&i2s1 {
	status = "okay";
	};

	&io_domains {
	vccio1-supply = <&vcc_io>;
	vccio2-supply = <&vcc18_emmc>;
	vccio3-supply = <&vcc_io>;
	vccio4-supply = <&vdd_18>;
	vccio5-supply = <&vcc_io>;
	vccio6-supply = <&vdd_18>;
	pmuio-supply = <&vcc_io>;
	status = "okay";
	};

	&pinctrl {
	pmic {
	pmic_int_l: pmic-int-l {
	rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	usb3 {
	usb30_host_drv: usb30-host-drv {
	rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	wifi {
	bt_dis: bt-dis {
	rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_output_low>;
	};

	bt_wake_host: bt-wake-host {
	rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
	};

	chip_en: chip-en {
	rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>;
	};

	host_wake_bt: host-wake-bt {
	rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_output_high>;
	};

	wl_dis: wl-dis {
	rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_output_low>;
	};

	wl_wake_host: wl-wake-host {
	rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};
	};

	&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	disable-wp;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
	vmmc-supply = <&vcc_io>;
	vqmmc-supply = <&vcc_io>;
	status = "okay";
	};

	&tsadc {
	rockchip,hw-tshut-mode = <0>;
	rockchip,hw-tshut-polarity = <0>;
	status = "okay";
	};

	&uart2 {
	status = "okay";
	};

	&u2phy {
	status = "okay";
	};

	&u2phy_host {
	status = "okay";
	};

	&u2phy_otg {
	status = "okay";
	};

	&usb20_otg {
	dr_mode = "host";
	status = "okay";
	};

	&usb_host0_ehci {
	pinctrl-names = "default";
	pinctrl-0 = <&bt_dis &bt_wake_host &chip_en &host_wake_bt &wl_dis &wl_wake_host>;
	status = "okay";
	};

	&vop {
	status = "okay";
	};

	&vop_mmu {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3328-evb.dts b/sys/gnu/dts/arm64/rockchip/rk3328-evb.dts
	index 49c4b96da3d4..ac29c2744d08 100644
	--- a/sys/gnu/dts/arm64/rockchip/rk3328-evb.dts
	+++ b/sys/gnu/dts/arm64/rockchip/rk3328-evb.dts
	@@ -1,271 +1,270 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
	*/

	/dts-v1/;
	#include "rk3328.dtsi"

	/ {
	model = "Rockchip RK3328 EVB";
	compatible = "rockchip,rk3328-evb", "rockchip,rk3328";

	chosen {
	stdout-path = "serial2:1500000n8";
	};

	dc_12v: dc-12v {
	compatible = "regulator-fixed";
	regulator-name = "dc_12v";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	};

	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	pinctrl-names = "default";
	pinctrl-0 = <&wifi_enable_h>;

	/*
	* On the module itself this is one of these (depending
	* on the actual card populated):
	* - SDIO_RESET_L_WL_REG_ON
	* - PDN (power down when low)
	*/
	reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
	};

	vcc_sd: sdmmc-regulator {
	compatible = "regulator-fixed";
	gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc0m1_gpio>;
	regulator-name = "vcc_sd";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vcc_io>;
	};

	vcc_sys: vcc-sys {
	compatible = "regulator-fixed";
	regulator-name = "vcc_sys";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&dc_12v>;
	};

	vcc_phy: vcc-phy-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vcc_phy";
	regulator-always-on;
	regulator-boot-on;
	};
	};

	&cpu0 {
	cpu-supply = <&vdd_arm>;
	};

	&emmc {
	bus-width = <8>;
	cap-mmc-highspeed;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
	status = "okay";
	};

	&gmac2phy {
	phy-supply = <&vcc_phy>;
	clock_in_out = "output";
	- assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
	assigned-clock-rate = <50000000>;
	assigned-clocks = <&cru SCLK_MAC2PHY>;
	assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
	-
	+ status = "okay";
	};

	&i2c1 {
	status = "okay";

	- rk805: rk805@18 {
	+ rk805: pmic@18 {
	compatible = "rockchip,rk805";
	reg = <0x18>;
	interrupt-parent = <&gpio2>;
	interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
	#clock-cells = <1>;
	clock-output-names = "xin32k", "rk805-clkout2";
	gpio-controller;
	#gpio-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int_l>;
	rockchip,system-power-controller;
	wakeup-source;

	vcc1-supply = <&vcc_sys>;
	vcc2-supply = <&vcc_sys>;
	vcc3-supply = <&vcc_sys>;
	vcc4-supply = <&vcc_sys>;
	vcc5-supply = <&vcc_io>;
	vcc6-supply = <&vcc_io>;

	regulators {
	vdd_logic: DCDC_REG1 {
	regulator-name = "vdd_logic";
	regulator-min-microvolt = <712500>;
	regulator-max-microvolt = <1450000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1000000>;
	};
	};

	vdd_arm: DCDC_REG2 {
	regulator-name = "vdd_arm";
	regulator-min-microvolt = <712500>;
	regulator-max-microvolt = <1450000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <950000>;
	};
	};

	vcc_ddr: DCDC_REG3 {
	regulator-name = "vcc_ddr";
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	vcc_io: DCDC_REG4 {
	regulator-name = "vcc_io";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3300000>;
	};
	};

	vcc_18: LDO_REG1 {
	regulator-name = "vcc_18";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc18_emmc: LDO_REG2 {
	regulator-name = "vcc18_emmc";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vdd_10: LDO_REG3 {
	regulator-name = "vdd_10";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1000000>;
	};
	};
	};
	};
	};

	&pinctrl {
	pmic {
	pmic_int_l: pmic-int-l {
	rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	sdio-pwrseq {
	wifi_enable_h: wifi-enable-h {
	rockchip,pins =
	<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};
	};

	&sdio {
	bus-width = <4>;
	cap-sd-highspeed;
	cap-sdio-irq;
	keep-power-in-suspend;
	max-frequency = <150000000>;
	mmc-pwrseq = <&sdio_pwrseq>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
	status = "okay";
	};

	&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	disable-wp;
	max-frequency = <150000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
	vmmc-supply = <&vcc_sd>;
	status = "okay";
	};

	&tsadc {
	status = "okay";
	};

	&uart2 {
	status = "okay";
	};

	&u2phy {
	status = "okay";
	};

	&u2phy_host {
	status = "okay";
	};

	&u2phy_otg {
	status = "okay";
	};

	&usb20_otg {
	status = "okay";
	};

	&usb_host0_ehci {
	status = "okay";
	};

	&usb_host0_ohci {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3328-rock64.dts b/sys/gnu/dts/arm64/rockchip/rk3328-rock64.dts
	index 62936b432f9a..ebf3eb222e1f 100644
	--- a/sys/gnu/dts/arm64/rockchip/rk3328-rock64.dts
	+++ b/sys/gnu/dts/arm64/rockchip/rk3328-rock64.dts
	@@ -1,400 +1,401 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2017 PINE64
	*/

	/dts-v1/;
	#include "rk3328.dtsi"

	/ {
	model = "Pine64 Rock64";
	compatible = "pine64,rock64", "rockchip,rk3328";

	chosen {
	stdout-path = "serial2:1500000n8";
	};

	gmac_clkin: external-gmac-clock {
	compatible = "fixed-clock";
	clock-frequency = <125000000>;
	clock-output-names = "gmac_clkin";
	#clock-cells = <0>;
	};

	vcc_sd: sdmmc-regulator {
	compatible = "regulator-fixed";
	gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc0m1_gpio>;
	regulator-name = "vcc_sd";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vcc_io>;
	};

	vcc_host_5v: vcc-host-5v-regulator {
	compatible = "regulator-fixed";
	gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&usb20_host_drv>;
	regulator-name = "vcc_host_5v";
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vcc_sys>;
	};

	vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
	compatible = "regulator-fixed";
	gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&usb20_host_drv>;
	regulator-name = "vcc_host1_5v";
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vcc_sys>;
	};

	vcc_sys: vcc-sys {
	compatible = "regulator-fixed";
	regulator-name = "vcc_sys";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	};

	ir-receiver {
	compatible = "gpio-ir-receiver";
	gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
	pinctrl-0 = <&ir_int>;
	pinctrl-names = "default";
	};

	leds {
	compatible = "gpio-leds";

	power {
	gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
	linux,default-trigger = "mmc0";
	};

	standby {
	gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
	linux,default-trigger = "heartbeat";
	};
	};

	sound {
	compatible = "audio-graph-card";
	label = "rockchip,rk3328";
	dais = <&i2s1_p0
	&spdif_p0>;
	};

	spdif-dit {
	compatible = "linux,spdif-dit";
	#sound-dai-cells = <0>;

	port {
	dit_p0_0: endpoint {
	remote-endpoint = <&spdif_p0_0>;
	};
	};
	};
	};

	&codec {
	+ mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
	status = "okay";

	port@0 {
	codec_p0_0: endpoint {
	remote-endpoint = <&i2s1_p0_0>;
	};
	};
	};

	&cpu0 {
	cpu-supply = <&vdd_arm>;
	};

	&cpu1 {
	cpu-supply = <&vdd_arm>;
	};

	&cpu2 {
	cpu-supply = <&vdd_arm>;
	};

	&cpu3 {
	cpu-supply = <&vdd_arm>;
	};

	&emmc {
	bus-width = <8>;
	cap-mmc-highspeed;
	mmc-hs200-1_8v;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
	vmmc-supply = <&vcc_io>;
	vqmmc-supply = <&vcc18_emmc>;
	status = "okay";
	};

	&gmac2io {
	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
	assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
	clock_in_out = "input";
	phy-supply = <&vcc_io>;
	phy-mode = "rgmii";
	pinctrl-names = "default";
	pinctrl-0 = <&rgmiim1_pins>;
	snps,force_thresh_dma_mode;
	snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;
	snps,reset-delays-us = <0 10000 50000>;
	tx_delay = <0x24>;
	rx_delay = <0x18>;
	status = "okay";
	};

	&hdmi {
	status = "okay";
	};

	&hdmiphy {
	status = "okay";
	};

	&i2c1 {
	status = "okay";

	- rk805: rk805@18 {
	+ rk805: pmic@18 {
	compatible = "rockchip,rk805";
	reg = <0x18>;
	interrupt-parent = <&gpio2>;
	interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
	#clock-cells = <1>;
	clock-output-names = "xin32k", "rk805-clkout2";
	gpio-controller;
	#gpio-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int_l>;
	rockchip,system-power-controller;
	wakeup-source;

	vcc1-supply = <&vcc_sys>;
	vcc2-supply = <&vcc_sys>;
	vcc3-supply = <&vcc_sys>;
	vcc4-supply = <&vcc_sys>;
	vcc5-supply = <&vcc_io>;
	vcc6-supply = <&vcc_sys>;

	regulators {
	vdd_logic: DCDC_REG1 {
	regulator-name = "vdd_logic";
	regulator-min-microvolt = <712500>;
	regulator-max-microvolt = <1450000>;
	regulator-ramp-delay = <12500>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1000000>;
	};
	};

	vdd_arm: DCDC_REG2 {
	regulator-name = "vdd_arm";
	regulator-min-microvolt = <712500>;
	regulator-max-microvolt = <1450000>;
	regulator-ramp-delay = <12500>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <950000>;
	};
	};

	vcc_ddr: DCDC_REG3 {
	regulator-name = "vcc_ddr";
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	vcc_io: DCDC_REG4 {
	regulator-name = "vcc_io";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3300000>;
	};
	};

	vcc_18: LDO_REG1 {
	regulator-name = "vcc_18";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc18_emmc: LDO_REG2 {
	regulator-name = "vcc18_emmc";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vdd_10: LDO_REG3 {
	regulator-name = "vdd_10";
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1000000>;
	};
	};
	};
	};
	};

	&i2s1 {
	status = "okay";

	i2s1_p0: port {
	i2s1_p0_0: endpoint {
	dai-format = "i2s";
	mclk-fs = <256>;
	remote-endpoint = <&codec_p0_0>;
	};
	};
	};

	&io_domains {
	status = "okay";

	vccio1-supply = <&vcc_io>;
	vccio2-supply = <&vcc18_emmc>;
	vccio3-supply = <&vcc_io>;
	vccio4-supply = <&vcc_18>;
	vccio5-supply = <&vcc_io>;
	vccio6-supply = <&vcc_io>;
	pmuio-supply = <&vcc_io>;
	};

	&pinctrl {
	ir {
	ir_int: ir-int {
	rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	pmic {
	pmic_int_l: pmic-int-l {
	rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	usb2 {
	usb20_host_drv: usb20-host-drv {
	rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};
	};

	&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	disable-wp;
	max-frequency = <150000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
	vmmc-supply = <&vcc_sd>;
	status = "okay";
	};

	&spdif {
	pinctrl-0 = <&spdifm0_tx>;
	status = "okay";

	spdif_p0: port {
	spdif_p0_0: endpoint {
	remote-endpoint = <&dit_p0_0>;
	};
	};
	};

	&spi0 {
	status = "okay";

	spiflash@0 {
	compatible = "jedec,spi-nor";
	reg = <0>;

	/* maximum speed for Rockchip SPI */
	spi-max-frequency = <50000000>;
	};
	};

	&tsadc {
	rockchip,hw-tshut-mode = <0>;
	rockchip,hw-tshut-polarity = <0>;
	status = "okay";
	};

	&uart2 {
	status = "okay";
	};

	&u2phy {
	status = "okay";

	u2phy_host: host-port {
	status = "okay";
	};

	u2phy_otg: otg-port {
	status = "okay";
	};
	};

	&usb20_otg {
	dr_mode = "host";
	status = "okay";
	};

	&usb_host0_ehci {
	status = "okay";
	};

	&usb_host0_ohci {
	status = "okay";
	};

	&vop {
	status = "okay";
	};

	&vop_mmu {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3328.dtsi b/sys/gnu/dts/arm64/rockchip/rk3328.dtsi
	index 1f53ead52c7f..a4d591d91533 100644
	--- a/sys/gnu/dts/arm64/rockchip/rk3328.dtsi
	+++ b/sys/gnu/dts/arm64/rockchip/rk3328.dtsi
	@@ -1,1914 +1,1895 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
	*/

	#include <dt-bindings/clock/rk3328-cru.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/pinctrl/rockchip.h>
	#include <dt-bindings/power/rk3328-power.h>
	#include <dt-bindings/soc/rockchip,boot-mode.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	compatible = "rockchip,rk3328";

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	serial0 = &uart0;
	serial1 = &uart1;
	serial2 = &uart2;
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	ethernet0 = &gmac2io;
	ethernet1 = &gmac2phy;
	};

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x0>;
	clocks = <&cru ARMCLK>;
	#cooling-cells = <2>;
	cpu-idle-states = <&CPU_SLEEP>;
	dynamic-power-coefficient = <120>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	operating-points-v2 = <&cpu0_opp_table>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x1>;
	clocks = <&cru ARMCLK>;
	#cooling-cells = <2>;
	cpu-idle-states = <&CPU_SLEEP>;
	dynamic-power-coefficient = <120>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	operating-points-v2 = <&cpu0_opp_table>;
	};

	cpu2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x2>;
	clocks = <&cru ARMCLK>;
	#cooling-cells = <2>;
	cpu-idle-states = <&CPU_SLEEP>;
	dynamic-power-coefficient = <120>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	operating-points-v2 = <&cpu0_opp_table>;
	};

	cpu3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x3>;
	clocks = <&cru ARMCLK>;
	#cooling-cells = <2>;
	cpu-idle-states = <&CPU_SLEEP>;
	dynamic-power-coefficient = <120>;
	enable-method = "psci";
	next-level-cache = <&l2>;
	operating-points-v2 = <&cpu0_opp_table>;
	};

	idle-states {
	entry-method = "psci";

	CPU_SLEEP: cpu-sleep {
	compatible = "arm,idle-state";
	local-timer-stop;
	arm,psci-suspend-param = <0x0010000>;
	entry-latency-us = <120>;
	exit-latency-us = <250>;
	min-residency-us = <900>;
	};
	};

	l2: l2-cache0 {
	compatible = "cache";
	};
	};

	cpu0_opp_table: opp_table0 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-408000000 {
	opp-hz = /bits/ 64 <408000000>;
	opp-microvolt = <950000>;
	clock-latency-ns = <40000>;
	opp-suspend;
	};
	opp-600000000 {
	opp-hz = /bits/ 64 <600000000>;
	opp-microvolt = <950000>;
	clock-latency-ns = <40000>;
	};
	opp-816000000 {
	opp-hz = /bits/ 64 <816000000>;
	opp-microvolt = <1000000>;
	clock-latency-ns = <40000>;
	};
	opp-1008000000 {
	opp-hz = /bits/ 64 <1008000000>;
	opp-microvolt = <1100000>;
	clock-latency-ns = <40000>;
	};
	opp-1200000000 {
	opp-hz = /bits/ 64 <1200000000>;
	opp-microvolt = <1225000>;
	clock-latency-ns = <40000>;
	};
	opp-1296000000 {
	opp-hz = /bits/ 64 <1296000000>;
	opp-microvolt = <1300000>;
	clock-latency-ns = <40000>;
	};
	};

	- amba {
	+ amba: bus {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	dmac: dmac@ff1f0000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x0 0xff1f0000 0x0 0x4000>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru ACLK_DMAC>;
	clock-names = "apb_pclk";
	#dma-cells = <1>;
	};
	};

	analog_sound: analog-sound {
	compatible = "simple-audio-card";
	simple-audio-card,format = "i2s";
	simple-audio-card,mclk-fs = <256>;
	simple-audio-card,name = "Analog";
	status = "disabled";

	simple-audio-card,cpu {
	sound-dai = <&i2s1>;
	};

	simple-audio-card,codec {
	sound-dai = <&codec>;
	};
	};

	arm-pmu {
	compatible = "arm,cortex-a53-pmu";
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	display_subsystem: display-subsystem {
	compatible = "rockchip,display-subsystem";
	ports = <&vop_out>;
	};

	hdmi_sound: hdmi-sound {
	compatible = "simple-audio-card";
	simple-audio-card,format = "i2s";
	simple-audio-card,mclk-fs = <128>;
	simple-audio-card,name = "HDMI";
	status = "disabled";

	simple-audio-card,cpu {
	sound-dai = <&i2s0>;
	};

	simple-audio-card,codec {
	sound-dai = <&hdmi>;
	};
	};

	psci {
	compatible = "arm,psci-1.0", "arm,psci-0.2";
	method = "smc";
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	xin24m: xin24m {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	clock-output-names = "xin24m";
	};

	i2s0: i2s@ff000000 {
	compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
	reg = <0x0 0xff000000 0x0 0x1000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
	clock-names = "i2s_clk", "i2s_hclk";
	dmas = <&dmac 11>, <&dmac 12>;
	dma-names = "tx", "rx";
	#sound-dai-cells = <0>;
	status = "disabled";
	};

	i2s1: i2s@ff010000 {
	compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
	reg = <0x0 0xff010000 0x0 0x1000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
	clock-names = "i2s_clk", "i2s_hclk";
	dmas = <&dmac 14>, <&dmac 15>;
	dma-names = "tx", "rx";
	#sound-dai-cells = <0>;
	status = "disabled";
	};

	i2s2: i2s@ff020000 {
	compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
	reg = <0x0 0xff020000 0x0 0x1000>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
	clock-names = "i2s_clk", "i2s_hclk";
	dmas = <&dmac 0>, <&dmac 1>;
	dma-names = "tx", "rx";
	#sound-dai-cells = <0>;
	status = "disabled";
	};

	spdif: spdif@ff030000 {
	compatible = "rockchip,rk3328-spdif";
	reg = <0x0 0xff030000 0x0 0x1000>;
	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
	clock-names = "mclk", "hclk";
	dmas = <&dmac 10>;
	dma-names = "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&spdifm2_tx>;
	#sound-dai-cells = <0>;
	status = "disabled";
	};

	pdm: pdm@ff040000 {
	compatible = "rockchip,pdm";
	reg = <0x0 0xff040000 0x0 0x1000>;
	clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
	clock-names = "pdm_clk", "pdm_hclk";
	dmas = <&dmac 16>;
	dma-names = "rx";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pdmm0_clk
	&pdmm0_sdi0
	&pdmm0_sdi1
	&pdmm0_sdi2
	&pdmm0_sdi3>;
	pinctrl-1 = <&pdmm0_clk_sleep
	&pdmm0_sdi0_sleep
	&pdmm0_sdi1_sleep
	&pdmm0_sdi2_sleep
	&pdmm0_sdi3_sleep>;
	status = "disabled";
	};

	grf: syscon@ff100000 {
	compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
	reg = <0x0 0xff100000 0x0 0x1000>;
	- #address-cells = <1>;
	- #size-cells = <1>;

	io_domains: io-domains {
	compatible = "rockchip,rk3328-io-voltage-domain";
	status = "disabled";
	};

	grf_gpio: grf-gpio {
	compatible = "rockchip,rk3328-grf-gpio";
	gpio-controller;
	#gpio-cells = <2>;
	};

	power: power-controller {
	compatible = "rockchip,rk3328-power-controller";
	#power-domain-cells = <1>;
	#address-cells = <1>;
	#size-cells = <0>;

	pd_hevc@RK3328_PD_HEVC {
	reg = <RK3328_PD_HEVC>;
	};
	pd_video@RK3328_PD_VIDEO {
	reg = <RK3328_PD_VIDEO>;
	};
	pd_vpu@RK3328_PD_VPU {
	reg = <RK3328_PD_VPU>;
	clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
	};
	};

	reboot-mode {
	compatible = "syscon-reboot-mode";
	offset = <0x5c8>;
	mode-normal = <BOOT_NORMAL>;
	mode-recovery = <BOOT_RECOVERY>;
	mode-bootloader = <BOOT_FASTBOOT>;
	mode-loader = <BOOT_BL_DOWNLOAD>;
	};
	};

	uart0: serial@ff110000 {
	compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff110000 0x0 0x100>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
	clock-names = "baudclk", "apb_pclk";
	dmas = <&dmac 2>, <&dmac 3>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
	reg-io-width = <4>;
	reg-shift = <2>;
	status = "disabled";
	};

	uart1: serial@ff120000 {
	compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff120000 0x0 0x100>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
	clock-names = "baudclk", "apb_pclk";
	dmas = <&dmac 4>, <&dmac 5>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
	reg-io-width = <4>;
	reg-shift = <2>;
	status = "disabled";
	};

	uart2: serial@ff130000 {
	compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff130000 0x0 0x100>;
	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
	clock-names = "baudclk", "apb_pclk";
	dmas = <&dmac 6>, <&dmac 7>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&uart2m1_xfer>;
	reg-io-width = <4>;
	reg-shift = <2>;
	status = "disabled";
	};

	i2c0: i2c@ff150000 {
	compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
	reg = <0x0 0xff150000 0x0 0x1000>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
	clock-names = "i2c", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
	status = "disabled";
	};

	i2c1: i2c@ff160000 {
	compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
	reg = <0x0 0xff160000 0x0 0x1000>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
	clock-names = "i2c", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
	status = "disabled";
	};

	i2c2: i2c@ff170000 {
	compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
	reg = <0x0 0xff170000 0x0 0x1000>;
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
	clock-names = "i2c", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
	status = "disabled";
	};

	i2c3: i2c@ff180000 {
	compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
	reg = <0x0 0xff180000 0x0 0x1000>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
	clock-names = "i2c", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
	status = "disabled";
	};

	spi0: spi@ff190000 {
	compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
	reg = <0x0 0xff190000 0x0 0x1000>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
	clock-names = "spiclk", "apb_pclk";
	dmas = <&dmac 8>, <&dmac 9>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
	status = "disabled";
	};

	wdt: watchdog@ff1a0000 {
	compatible = "snps,dw-wdt";
	reg = <0x0 0xff1a0000 0x0 0x100>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_WDT>;
	};

	pwm0: pwm@ff1b0000 {
	compatible = "rockchip,rk3328-pwm";
	reg = <0x0 0xff1b0000 0x0 0x10>;
	clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm1: pwm@ff1b0010 {
	compatible = "rockchip,rk3328-pwm";
	reg = <0x0 0xff1b0010 0x0 0x10>;
	clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm2: pwm@ff1b0020 {
	compatible = "rockchip,rk3328-pwm";
	reg = <0x0 0xff1b0020 0x0 0x10>;
	clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm3: pwm@ff1b0030 {
	compatible = "rockchip,rk3328-pwm";
	reg = <0x0 0xff1b0030 0x0 0x10>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
	clock-names = "pwm", "pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pwmir_pin>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	thermal-zones {
	soc_thermal: soc-thermal {
	polling-delay-passive = <20>;
	polling-delay = <1000>;
	sustainable-power = <1000>;

	thermal-sensors = <&tsadc 0>;

	trips {
	threshold: trip-point0 {
	temperature = <70000>;
	hysteresis = <2000>;
	type = "passive";
	};
	target: trip-point1 {
	temperature = <85000>;
	hysteresis = <2000>;
	type = "passive";
	};
	soc_crit: soc-crit {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&target>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	contribution = <4096>;
	};
	};
	};

	};

	tsadc: tsadc@ff250000 {
	compatible = "rockchip,rk3328-tsadc";
	reg = <0x0 0xff250000 0x0 0x100>;
	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	assigned-clocks = <&cru SCLK_TSADC>;
	assigned-clock-rates = <50000>;
	clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
	clock-names = "tsadc", "apb_pclk";
	pinctrl-names = "init", "default", "sleep";
	pinctrl-0 = <&otp_gpio>;
	pinctrl-1 = <&otp_out>;
	pinctrl-2 = <&otp_gpio>;
	resets = <&cru SRST_TSADC>;
	reset-names = "tsadc-apb";
	rockchip,grf = <&grf>;
	rockchip,hw-tshut-temp = <100000>;
	#thermal-sensor-cells = <1>;
	status = "disabled";
	};

	efuse: efuse@ff260000 {
	compatible = "rockchip,rk3328-efuse";
	reg = <0x0 0xff260000 0x0 0x50>;
	#address-cells = <1>;
	#size-cells = <1>;
	clocks = <&cru SCLK_EFUSE>;
	clock-names = "pclk_efuse";
	rockchip,efuse-size = <0x20>;

	/* Data cells */
	efuse_id: id@7 {
	reg = <0x07 0x10>;
	};
	cpu_leakage: cpu-leakage@17 {
	reg = <0x17 0x1>;
	};
	logic_leakage: logic-leakage@19 {
	reg = <0x19 0x1>;
	};
	efuse_cpu_version: cpu-version@1a {
	reg = <0x1a 0x1>;
	bits = <3 3>;
	};
	};

	saradc: adc@ff280000 {
	compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
	reg = <0x0 0xff280000 0x0 0x100>;
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	#io-channel-cells = <1>;
	clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
	clock-names = "saradc", "apb_pclk";
	resets = <&cru SRST_SARADC_P>;
	reset-names = "saradc-apb";
	status = "disabled";
	};

	gpu: gpu@ff300000 {
	compatible = "rockchip,rk3328-mali", "arm,mali-450";
	reg = <0x0 0xff300000 0x0 0x40000>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gp",
	"gpmmu",
	"pp",
	"pp0",
	"ppmmu0",
	"pp1",
	"ppmmu1";
	clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
	clock-names = "bus", "core";
	resets = <&cru SRST_GPU_A>;
	};

	h265e_mmu: iommu@ff330200 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff330200 0 0x100>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "h265e_mmu";
	clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	status = "disabled";
	};

	vepu_mmu: iommu@ff340800 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff340800 0x0 0x40>;
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "vepu_mmu";
	clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	status = "disabled";
	};

	vpu: video-codec@ff350000 {
	compatible = "rockchip,rk3328-vpu";
	reg = <0x0 0xff350000 0x0 0x800>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "vdpu";
	clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
	clock-names = "aclk", "hclk";
	iommus = <&vpu_mmu>;
	power-domains = <&power RK3328_PD_VPU>;
	};

	vpu_mmu: iommu@ff350800 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff350800 0x0 0x40>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "vpu_mmu";
	clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	power-domains = <&power RK3328_PD_VPU>;
	};

	rkvdec_mmu: iommu@ff360480 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "rkvdec_mmu";
	clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	status = "disabled";
	};

	vop: vop@ff370000 {
	compatible = "rockchip,rk3328-vop";
	reg = <0x0 0xff370000 0x0 0x3efc>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
	reset-names = "axi", "ahb", "dclk";
	iommus = <&vop_mmu>;
	status = "disabled";

	vop_out: port {
	#address-cells = <1>;
	#size-cells = <0>;

	vop_out_hdmi: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&hdmi_in_vop>;
	};
	};
	};

	vop_mmu: iommu@ff373f00 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff373f00 0x0 0x100>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "vop_mmu";
	clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	status = "disabled";
	};

	hdmi: hdmi@ff3c0000 {
	compatible = "rockchip,rk3328-dw-hdmi";
	reg = <0x0 0xff3c0000 0x0 0x20000>;
	reg-io-width = <4>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_HDMI>,
	<&cru SCLK_HDMI_SFC>,
	<&cru SCLK_RTC32K>;
	clock-names = "iahb",
	"isfr",
	"cec";
	phys = <&hdmiphy>;
	phy-names = "hdmi";
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
	rockchip,grf = <&grf>;
	#sound-dai-cells = <0>;
	status = "disabled";

	ports {
	hdmi_in: port {
	hdmi_in_vop: endpoint {
	remote-endpoint = <&vop_out_hdmi>;
	};
	};
	};
	};

	codec: codec@ff410000 {
	compatible = "rockchip,rk3328-codec";
	reg = <0x0 0xff410000 0x0 0x1000>;
	clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
	clock-names = "pclk", "mclk";
	rockchip,grf = <&grf>;
	#sound-dai-cells = <0>;
	status = "disabled";
	};

	hdmiphy: phy@ff430000 {
	compatible = "rockchip,rk3328-hdmi-phy";
	reg = <0x0 0xff430000 0x0 0x10000>;
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
	clock-names = "sysclk", "refoclk", "refpclk";
	clock-output-names = "hdmi_phy";
	#clock-cells = <0>;
	nvmem-cells = <&efuse_cpu_version>;
	nvmem-cell-names = "cpu-version";
	#phy-cells = <0>;
	status = "disabled";
	};

	cru: clock-controller@ff440000 {
	compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
	reg = <0x0 0xff440000 0x0 0x1000>;
	rockchip,grf = <&grf>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	assigned-clocks =
	/*
	* CPLL should run at 1200, but that is to high for
	* the initial dividers of most of its children.
	* We need set cpll child clk div first,
	* and then set the cpll frequency.
	*/
	<&cru DCLK_LCDC>, <&cru SCLK_PDM>,
	<&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
	<&cru SCLK_UART1>, <&cru SCLK_UART2>,
	<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
	<&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
	<&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
	<&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
	<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
	<&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
	<&cru SCLK_SDIO>, <&cru SCLK_TSP>,
	<&cru SCLK_WIFI>, <&cru ARMCLK>,
	<&cru PLL_GPLL>, <&cru PLL_CPLL>,
	<&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
	<&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
	<&cru HCLK_PERI>, <&cru PCLK_PERI>,
	<&cru SCLK_RTC32K>;
	assigned-clock-parents =
	<&cru HDMIPHY>, <&cru PLL_APLL>,
	<&cru PLL_GPLL>, <&xin24m>,
	<&xin24m>, <&xin24m>;
	assigned-clock-rates =
	<0>, <61440000>,
	<0>, <24000000>,
	<24000000>, <24000000>,
	<15000000>, <15000000>,
	<100000000>, <100000000>,
	<100000000>, <100000000>,
	<50000000>, <100000000>,
	<100000000>, <100000000>,
	<50000000>, <50000000>,
	<50000000>, <50000000>,
	<24000000>, <600000000>,
	<491520000>, <1200000000>,
	<150000000>, <75000000>,
	<75000000>, <150000000>,
	<75000000>, <75000000>,
	<32768>;
	};

	usb2phy_grf: syscon@ff450000 {
	compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
	"simple-mfd";
	reg = <0x0 0xff450000 0x0 0x10000>;
	#address-cells = <1>;
	#size-cells = <1>;

	u2phy: usb2-phy@100 {
	compatible = "rockchip,rk3328-usb2phy";
	reg = <0x100 0x10>;
	clocks = <&xin24m>;
	clock-names = "phyclk";
	clock-output-names = "usb480m_phy";
	#clock-cells = <0>;
	assigned-clocks = <&cru USB480M>;
	assigned-clock-parents = <&u2phy>;
	status = "disabled";

	u2phy_otg: otg-port {
	#phy-cells = <0>;
	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "otg-bvalid", "otg-id",
	"linestate";
	status = "disabled";
	};

	u2phy_host: host-port {
	#phy-cells = <0>;
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "linestate";
	status = "disabled";
	};
	};
	};

	sdmmc: mmc@ff500000 {
	compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x0 0xff500000 0x0 0x4000>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
	<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	max-frequency = <150000000>;
	status = "disabled";
	};

	sdio: mmc@ff510000 {
	compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x0 0xff510000 0x0 0x4000>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
	<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	max-frequency = <150000000>;
	status = "disabled";
	};

	emmc: mmc@ff520000 {
	compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x0 0xff520000 0x0 0x4000>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
	<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	max-frequency = <150000000>;
	status = "disabled";
	};

	gmac2io: ethernet@ff540000 {
	compatible = "rockchip,rk3328-gmac";
	reg = <0x0 0xff540000 0x0 0x10000>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
	<&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
	<&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
	<&cru PCLK_MAC2IO>;
	clock-names = "stmmaceth", "mac_clk_rx",
	"mac_clk_tx", "clk_mac_ref",
	"clk_mac_refout", "aclk_mac",
	"pclk_mac";
	resets = <&cru SRST_GMAC2IO_A>;
	reset-names = "stmmaceth";
	rockchip,grf = <&grf>;
	+ snps,txpbl = <0x4>;
	status = "disabled";
	};

	gmac2phy: ethernet@ff550000 {
	compatible = "rockchip,rk3328-gmac";
	reg = <0x0 0xff550000 0x0 0x10000>;
	rockchip,grf = <&grf>;
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
	<&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
	<&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
	<&cru SCLK_MAC2PHY_OUT>;
	clock-names = "stmmaceth", "mac_clk_rx",
	"mac_clk_tx", "clk_mac_ref",
	"aclk_mac", "pclk_mac",
	"clk_macphy";
	resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
	reset-names = "stmmaceth", "mac-phy";
	phy-mode = "rmii";
	phy-handle = <&phy>;
	+ snps,txpbl = <0x4>;
	status = "disabled";

	mdio {
	compatible = "snps,dwmac-mdio";
	#address-cells = <1>;
	#size-cells = <0>;

	phy: phy@0 {
	compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
	reg = <0>;
	clocks = <&cru SCLK_MAC2PHY_OUT>;
	resets = <&cru SRST_MACPHY>;
	pinctrl-names = "default";
	pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
	phy-is-integrated;
	};
	};
	};

	usb20_otg: usb@ff580000 {
	compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
	"snps,dwc2";
	reg = <0x0 0xff580000 0x0 0x40000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_OTG>;
	clock-names = "otg";
	dr_mode = "otg";
	g-np-tx-fifo-size = <16>;
	g-rx-fifo-size = <280>;
	g-tx-fifo-size = <256 128 128 64 32 16>;
	- g-use-dma;
	phys = <&u2phy_otg>;
	phy-names = "usb2-phy";
	status = "disabled";
	};

	usb_host0_ehci: usb@ff5c0000 {
	compatible = "generic-ehci";
	reg = <0x0 0xff5c0000 0x0 0x10000>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_HOST0>, <&u2phy>;
	- clock-names = "usbhost", "utmi";
	phys = <&u2phy_host>;
	phy-names = "usb";
	status = "disabled";
	};

	usb_host0_ohci: usb@ff5d0000 {
	compatible = "generic-ohci";
	reg = <0x0 0xff5d0000 0x0 0x10000>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_HOST0>, <&u2phy>;
	- clock-names = "usbhost", "utmi";
	phys = <&u2phy_host>;
	phy-names = "usb";
	status = "disabled";
	};

	gic: interrupt-controller@ff811000 {
	compatible = "arm,gic-400";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x0 0xff811000 0 0x1000>,
	<0x0 0xff812000 0 0x2000>,
	<0x0 0xff814000 0 0x2000>,
	<0x0 0xff816000 0 0x2000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	pinctrl: pinctrl {
	compatible = "rockchip,rk3328-pinctrl";
	rockchip,grf = <&grf>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	gpio0: gpio0@ff210000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff210000 0x0 0x100>;
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO0>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio1: gpio1@ff220000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff220000 0x0 0x100>;
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO1>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio2@ff230000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff230000 0x0 0x100>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO2>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio3@ff240000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff240000 0x0 0x100>;
	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_GPIO3>;

	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};

	pcfg_pull_up: pcfg-pull-up {
	bias-pull-up;
	};

	pcfg_pull_down: pcfg-pull-down {
	bias-pull-down;
	};

	pcfg_pull_none: pcfg-pull-none {
	bias-disable;
	};

	pcfg_pull_none_2ma: pcfg-pull-none-2ma {
	bias-disable;
	drive-strength = <2>;
	};

	pcfg_pull_up_2ma: pcfg-pull-up-2ma {
	bias-pull-up;
	drive-strength = <2>;
	};

	pcfg_pull_up_4ma: pcfg-pull-up-4ma {
	bias-pull-up;
	drive-strength = <4>;
	};

	pcfg_pull_none_4ma: pcfg-pull-none-4ma {
	bias-disable;
	drive-strength = <4>;
	};

	pcfg_pull_down_4ma: pcfg-pull-down-4ma {
	bias-pull-down;
	drive-strength = <4>;
	};

	pcfg_pull_none_8ma: pcfg-pull-none-8ma {
	bias-disable;
	drive-strength = <8>;
	};

	pcfg_pull_up_8ma: pcfg-pull-up-8ma {
	bias-pull-up;
	drive-strength = <8>;
	};

	pcfg_pull_none_12ma: pcfg-pull-none-12ma {
	bias-disable;
	drive-strength = <12>;
	};

	pcfg_pull_up_12ma: pcfg-pull-up-12ma {
	bias-pull-up;
	drive-strength = <12>;
	};

	pcfg_output_high: pcfg-output-high {
	output-high;
	};

	pcfg_output_low: pcfg-output-low {
	output-low;
	};

	pcfg_input_high: pcfg-input-high {
	bias-pull-up;
	input-enable;
	};

	pcfg_input: pcfg-input {
	input-enable;
	};

	i2c0 {
	i2c0_xfer: i2c0-xfer {
	rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
	<2 RK_PD1 1 &pcfg_pull_none>;
	};
	};

	i2c1 {
	i2c1_xfer: i2c1-xfer {
	rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
	<2 RK_PA5 2 &pcfg_pull_none>;
	};
	};

	i2c2 {
	i2c2_xfer: i2c2-xfer {
	rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
	<2 RK_PB6 1 &pcfg_pull_none>;
	};
	};

	i2c3 {
	i2c3_xfer: i2c3-xfer {
	rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
	<0 RK_PA6 2 &pcfg_pull_none>;
	};
	i2c3_gpio: i2c3-gpio {
	rockchip,pins =
	<0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
	<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	hdmi_i2c {
	hdmii2c_xfer: hdmii2c-xfer {
	rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
	<0 RK_PA6 1 &pcfg_pull_none>;
	};
	};

	pdm-0 {
	pdmm0_clk: pdmm0-clk {
	rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
	};

	pdmm0_fsync: pdmm0-fsync {
	rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
	};

	pdmm0_sdi0: pdmm0-sdi0 {
	rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
	};

	pdmm0_sdi1: pdmm0-sdi1 {
	rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
	};

	pdmm0_sdi2: pdmm0-sdi2 {
	rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
	};

	pdmm0_sdi3: pdmm0-sdi3 {
	rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
	};

	pdmm0_clk_sleep: pdmm0-clk-sleep {
	rockchip,pins =
	<2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
	};

	pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
	rockchip,pins =
	<2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
	};

	pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
	rockchip,pins =
	<2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
	};

	pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
	rockchip,pins =
	<2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
	};

	pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
	rockchip,pins =
	<2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
	};

	pdmm0_fsync_sleep: pdmm0-fsync-sleep {
	rockchip,pins =
	<2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
	};
	};

	tsadc {
	otp_gpio: otp-gpio {
	rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	otp_out: otp-out {
	rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
	};
	};

	uart0 {
	uart0_xfer: uart0-xfer {
	rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
	<1 RK_PB0 1 &pcfg_pull_none>;
	};

	uart0_cts: uart0-cts {
	rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
	};

	uart0_rts: uart0-rts {
	rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
	};

	uart0_rts_gpio: uart0-rts-gpio {
	rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	uart1 {
	uart1_xfer: uart1-xfer {
	rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
	<3 RK_PA6 4 &pcfg_pull_none>;
	};

	uart1_cts: uart1-cts {
	rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
	};

	uart1_rts: uart1-rts {
	rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
	};

	uart1_rts_gpio: uart1-rts-gpio {
	rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	uart2-0 {
	uart2m0_xfer: uart2m0-xfer {
	rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
	<1 RK_PA1 2 &pcfg_pull_none>;
	};
	};

	uart2-1 {
	uart2m1_xfer: uart2m1-xfer {
	rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
	<2 RK_PA1 1 &pcfg_pull_none>;
	};
	};

	spi0-0 {
	spi0m0_clk: spi0m0-clk {
	rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
	};

	spi0m0_cs0: spi0m0-cs0 {
	rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
	};

	spi0m0_tx: spi0m0-tx {
	rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
	};

	spi0m0_rx: spi0m0-rx {
	rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
	};

	spi0m0_cs1: spi0m0-cs1 {
	rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
	};
	};

	spi0-1 {
	spi0m1_clk: spi0m1-clk {
	rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
	};

	spi0m1_cs0: spi0m1-cs0 {
	rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
	};

	spi0m1_tx: spi0m1-tx {
	rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
	};

	spi0m1_rx: spi0m1-rx {
	rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
	};

	spi0m1_cs1: spi0m1-cs1 {
	rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
	};
	};

	spi0-2 {
	spi0m2_clk: spi0m2-clk {
	rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
	};

	spi0m2_cs0: spi0m2-cs0 {
	rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
	};

	spi0m2_tx: spi0m2-tx {
	rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
	};

	spi0m2_rx: spi0m2-rx {
	rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
	};
	};

	i2s1 {
	i2s1_mclk: i2s1-mclk {
	rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
	};

	i2s1_sclk: i2s1-sclk {
	rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
	};

	i2s1_lrckrx: i2s1-lrckrx {
	rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
	};

	i2s1_lrcktx: i2s1-lrcktx {
	rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
	};

	i2s1_sdi: i2s1-sdi {
	rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
	};

	i2s1_sdo: i2s1-sdo {
	rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
	};

	i2s1_sdio1: i2s1-sdio1 {
	rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
	};

	i2s1_sdio2: i2s1-sdio2 {
	rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
	};

	i2s1_sdio3: i2s1-sdio3 {
	rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
	};

	i2s1_sleep: i2s1-sleep {
	rockchip,pins =
	<2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
	<2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
	<2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
	<2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
	<2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
	<2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
	<2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
	<2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
	<2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
	};
	};

	i2s2-0 {
	i2s2m0_mclk: i2s2m0-mclk {
	rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
	};

	i2s2m0_sclk: i2s2m0-sclk {
	rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
	};

	i2s2m0_lrckrx: i2s2m0-lrckrx {
	rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
	};

	i2s2m0_lrcktx: i2s2m0-lrcktx {
	rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
	};

	i2s2m0_sdi: i2s2m0-sdi {
	rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
	};

	i2s2m0_sdo: i2s2m0-sdo {
	rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
	};

	i2s2m0_sleep: i2s2m0-sleep {
	rockchip,pins =
	<1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
	<1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
	<1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
	<1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
	<1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
	<1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
	};
	};

	i2s2-1 {
	i2s2m1_mclk: i2s2m1-mclk {
	rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
	};

	i2s2m1_sclk: i2s2m1-sclk {
	rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
	};

	i2s2m1_lrckrx: i2sm1-lrckrx {
	rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
	};

	i2s2m1_lrcktx: i2s2m1-lrcktx {
	rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
	};

	i2s2m1_sdi: i2s2m1-sdi {
	rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
	};

	i2s2m1_sdo: i2s2m1-sdo {
	rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
	};

	i2s2m1_sleep: i2s2m1-sleep {
	rockchip,pins =
	<1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
	<3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
	<3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
	<3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
	<3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
	};
	};

	spdif-0 {
	spdifm0_tx: spdifm0-tx {
	rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
	};
	};

	spdif-1 {
	spdifm1_tx: spdifm1-tx {
	rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
	};
	};

	spdif-2 {
	spdifm2_tx: spdifm2-tx {
	rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
	};
	};

	sdmmc0-0 {
	sdmmc0m0_pwren: sdmmc0m0-pwren {
	rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
	};

	sdmmc0m0_gpio: sdmmc0m0-gpio {
	rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
	};
	};

	sdmmc0-1 {
	sdmmc0m1_pwren: sdmmc0m1-pwren {
	rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
	};

	sdmmc0m1_gpio: sdmmc0m1-gpio {
	rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
	};
	};

	sdmmc0 {
	sdmmc0_clk: sdmmc0-clk {
	rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
	};

	sdmmc0_cmd: sdmmc0-cmd {
	rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
	};

	sdmmc0_dectn: sdmmc0-dectn {
	rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
	};

	sdmmc0_wrprt: sdmmc0-wrprt {
	rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
	};

	sdmmc0_bus1: sdmmc0-bus1 {
	rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
	};

	sdmmc0_bus4: sdmmc0-bus4 {
	rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
	<1 RK_PA1 1 &pcfg_pull_up_8ma>,
	<1 RK_PA2 1 &pcfg_pull_up_8ma>,
	<1 RK_PA3 1 &pcfg_pull_up_8ma>;
	};

	sdmmc0_gpio: sdmmc0-gpio {
	rockchip,pins =
	<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
	};
	};

	sdmmc0ext {
	sdmmc0ext_clk: sdmmc0ext-clk {
	rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
	};

	sdmmc0ext_cmd: sdmmc0ext-cmd {
	rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
	};

	sdmmc0ext_wrprt: sdmmc0ext-wrprt {
	rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
	};

	sdmmc0ext_dectn: sdmmc0ext-dectn {
	rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
	};

	sdmmc0ext_bus1: sdmmc0ext-bus1 {
	rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
	};

	sdmmc0ext_bus4: sdmmc0ext-bus4 {
	rockchip,pins =
	<3 RK_PA4 3 &pcfg_pull_up_4ma>,
	<3 RK_PA5 3 &pcfg_pull_up_4ma>,
	<3 RK_PA6 3 &pcfg_pull_up_4ma>,
	<3 RK_PA7 3 &pcfg_pull_up_4ma>;
	};

	sdmmc0ext_gpio: sdmmc0ext-gpio {
	rockchip,pins =
	<3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
	};
	};

	sdmmc1 {
	sdmmc1_clk: sdmmc1-clk {
	rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
	};

	sdmmc1_cmd: sdmmc1-cmd {
	rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
	};

	sdmmc1_pwren: sdmmc1-pwren {
	rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
	};

	sdmmc1_wrprt: sdmmc1-wrprt {
	rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
	};

	sdmmc1_dectn: sdmmc1-dectn {
	rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
	};

	sdmmc1_bus1: sdmmc1-bus1 {
	rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
	};

	sdmmc1_bus4: sdmmc1-bus4 {
	rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
	<1 RK_PB7 1 &pcfg_pull_up_8ma>,
	<1 RK_PC0 1 &pcfg_pull_up_8ma>,
	<1 RK_PC1 1 &pcfg_pull_up_8ma>;
	};

	sdmmc1_gpio: sdmmc1-gpio {
	rockchip,pins =
	<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	<1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
	};
	};

	emmc {
	emmc_clk: emmc-clk {
	rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
	};

	emmc_cmd: emmc-cmd {
	rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
	};

	emmc_pwren: emmc-pwren {
	rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
	};

	emmc_rstnout: emmc-rstnout {
	rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
	};

	emmc_bus1: emmc-bus1 {
	rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
	};

	emmc_bus4: emmc-bus4 {
	rockchip,pins =
	<0 RK_PA7 2 &pcfg_pull_up_12ma>,
	<2 RK_PD4 2 &pcfg_pull_up_12ma>,
	<2 RK_PD5 2 &pcfg_pull_up_12ma>,
	<2 RK_PD6 2 &pcfg_pull_up_12ma>;
	};

	emmc_bus8: emmc-bus8 {
	rockchip,pins =
	<0 RK_PA7 2 &pcfg_pull_up_12ma>,
	<2 RK_PD4 2 &pcfg_pull_up_12ma>,
	<2 RK_PD5 2 &pcfg_pull_up_12ma>,
	<2 RK_PD6 2 &pcfg_pull_up_12ma>,
	<2 RK_PD7 2 &pcfg_pull_up_12ma>,
	<3 RK_PC0 2 &pcfg_pull_up_12ma>,
	<3 RK_PC1 2 &pcfg_pull_up_12ma>,
	<3 RK_PC2 2 &pcfg_pull_up_12ma>;
	};
	};

	pwm0 {
	pwm0_pin: pwm0-pin {
	rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
	};
	};

	pwm1 {
	pwm1_pin: pwm1-pin {
	rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
	};
	};

	pwm2 {
	pwm2_pin: pwm2-pin {
	rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
	};
	};

	pwmir {
	pwmir_pin: pwmir-pin {
	rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
	};
	};

	gmac-1 {
	rgmiim1_pins: rgmiim1-pins {
	rockchip,pins =
	/* mac_txclk */
	<1 RK_PB4 2 &pcfg_pull_none_8ma>,
	/* mac_rxclk */
	<1 RK_PB5 2 &pcfg_pull_none_4ma>,
	/* mac_mdio */
	<1 RK_PC3 2 &pcfg_pull_none_4ma>,
	/* mac_txen */
	<1 RK_PD1 2 &pcfg_pull_none_8ma>,
	/* mac_clk */
	<1 RK_PC5 2 &pcfg_pull_none_4ma>,
	/* mac_rxdv */
	<1 RK_PC6 2 &pcfg_pull_none_4ma>,
	/* mac_mdc */
	<1 RK_PC7 2 &pcfg_pull_none_4ma>,
	/* mac_rxd1 */
	<1 RK_PB2 2 &pcfg_pull_none_4ma>,
	/* mac_rxd0 */
	<1 RK_PB3 2 &pcfg_pull_none_4ma>,
	/* mac_txd1 */
	<1 RK_PB0 2 &pcfg_pull_none_8ma>,
	/* mac_txd0 */
	<1 RK_PB1 2 &pcfg_pull_none_8ma>,
	/* mac_rxd3 */
	<1 RK_PB6 2 &pcfg_pull_none_4ma>,
	/* mac_rxd2 */
	<1 RK_PB7 2 &pcfg_pull_none_4ma>,
	/* mac_txd3 */
	<1 RK_PC0 2 &pcfg_pull_none_8ma>,
	/* mac_txd2 */
	<1 RK_PC1 2 &pcfg_pull_none_8ma>,

	/* mac_txclk */
	<0 RK_PB0 1 &pcfg_pull_none_8ma>,
	/* mac_txen */
	<0 RK_PB4 1 &pcfg_pull_none_8ma>,
	/* mac_clk */
	<0 RK_PD0 1 &pcfg_pull_none_4ma>,
	/* mac_txd1 */
	<0 RK_PC0 1 &pcfg_pull_none_8ma>,
	/* mac_txd0 */
	<0 RK_PC1 1 &pcfg_pull_none_8ma>,
	/* mac_txd3 */
	<0 RK_PC7 1 &pcfg_pull_none_8ma>,
	/* mac_txd2 */
	<0 RK_PC6 1 &pcfg_pull_none_8ma>;
	};

	rmiim1_pins: rmiim1-pins {
	rockchip,pins =
	/* mac_mdio */
	<1 RK_PC3 2 &pcfg_pull_none_2ma>,
	/* mac_txen */
	<1 RK_PD1 2 &pcfg_pull_none_12ma>,
	/* mac_clk */
	<1 RK_PC5 2 &pcfg_pull_none_2ma>,
	/* mac_rxer */
	<1 RK_PD0 2 &pcfg_pull_none_2ma>,
	/* mac_rxdv */
	<1 RK_PC6 2 &pcfg_pull_none_2ma>,
	/* mac_mdc */
	<1 RK_PC7 2 &pcfg_pull_none_2ma>,
	/* mac_rxd1 */
	<1 RK_PB2 2 &pcfg_pull_none_2ma>,
	/* mac_rxd0 */
	<1 RK_PB3 2 &pcfg_pull_none_2ma>,
	/* mac_txd1 */
	<1 RK_PB0 2 &pcfg_pull_none_12ma>,
	/* mac_txd0 */
	<1 RK_PB1 2 &pcfg_pull_none_12ma>,

	/* mac_mdio */
	<0 RK_PB3 1 &pcfg_pull_none>,
	/* mac_txen */
	<0 RK_PB4 1 &pcfg_pull_none>,
	/* mac_clk */
	<0 RK_PD0 1 &pcfg_pull_none>,
	/* mac_mdc */
	<0 RK_PC3 1 &pcfg_pull_none>,
	/* mac_txd1 */
	<0 RK_PC0 1 &pcfg_pull_none>,
	/* mac_txd0 */
	<0 RK_PC1 1 &pcfg_pull_none>;
	};
	};

	gmac2phy {
	- fephyled_speed100: fephyled-speed100 {
	- rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
	- };
	-
	fephyled_speed10: fephyled-speed10 {
	rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
	};

	fephyled_duplex: fephyled-duplex {
	rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
	};

	- fephyled_rxm0: fephyled-rxm0 {
	- rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
	- };
	-
	- fephyled_txm0: fephyled-txm0 {
	- rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
	- };
	-
	- fephyled_linkm0: fephyled-linkm0 {
	- rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
	- };
	-
	fephyled_rxm1: fephyled-rxm1 {
	rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
	};

	fephyled_txm1: fephyled-txm1 {
	rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
	};

	fephyled_linkm1: fephyled-linkm1 {
	rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
	};
	};

	tsadc_pin {
	tsadc_int: tsadc-int {
	rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
	};
	tsadc_gpio: tsadc-gpio {
	rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	hdmi_pin {
	hdmi_cec: hdmi-cec {
	rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
	};

	hdmi_hpd: hdmi-hpd {
	rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
	};
	};

	cif-0 {
	dvp_d2d9_m0:dvp-d2d9-m0 {
	rockchip,pins =
	/* cif_d0 */
	<3 RK_PA4 2 &pcfg_pull_none>,
	/* cif_d1 */
	<3 RK_PA5 2 &pcfg_pull_none>,
	/* cif_d2 */
	<3 RK_PA6 2 &pcfg_pull_none>,
	/* cif_d3 */
	<3 RK_PA7 2 &pcfg_pull_none>,
	/* cif_d4 */
	<3 RK_PB0 2 &pcfg_pull_none>,
	/* cif_d5m0 */
	<3 RK_PB1 2 &pcfg_pull_none>,
	/* cif_d6m0 */
	<3 RK_PB2 2 &pcfg_pull_none>,
	/* cif_d7m0 */
	<3 RK_PB3 2 &pcfg_pull_none>,
	/* cif_href */
	<3 RK_PA1 2 &pcfg_pull_none>,
	/* cif_vsync */
	<3 RK_PA0 2 &pcfg_pull_none>,
	/* cif_clkoutm0 */
	<3 RK_PA3 2 &pcfg_pull_none>,
	/* cif_clkin */
	<3 RK_PA2 2 &pcfg_pull_none>;
	};
	};

	cif-1 {
	dvp_d2d9_m1:dvp-d2d9-m1 {
	rockchip,pins =
	/* cif_d0 */
	<3 RK_PA4 2 &pcfg_pull_none>,
	/* cif_d1 */
	<3 RK_PA5 2 &pcfg_pull_none>,
	/* cif_d2 */
	<3 RK_PA6 2 &pcfg_pull_none>,
	/* cif_d3 */
	<3 RK_PA7 2 &pcfg_pull_none>,
	/* cif_d4 */
	<3 RK_PB0 2 &pcfg_pull_none>,
	/* cif_d5m1 */
	<2 RK_PC0 4 &pcfg_pull_none>,
	/* cif_d6m1 */
	<2 RK_PC1 4 &pcfg_pull_none>,
	/* cif_d7m1 */
	<2 RK_PC2 4 &pcfg_pull_none>,
	/* cif_href */
	<3 RK_PA1 2 &pcfg_pull_none>,
	/* cif_vsync */
	<3 RK_PA0 2 &pcfg_pull_none>,
	/* cif_clkoutm1 */
	<2 RK_PB7 4 &pcfg_pull_none>,
	/* cif_clkin */
	<3 RK_PA2 2 &pcfg_pull_none>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3368-px5-evb.dts b/sys/gnu/dts/arm64/rockchip/rk3368-px5-evb.dts
	index 231db0305a03..5ffd7b4d3036 100644
	--- a/sys/gnu/dts/arm64/rockchip/rk3368-px5-evb.dts
	+++ b/sys/gnu/dts/arm64/rockchip/rk3368-px5-evb.dts
	@@ -1,273 +1,272 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
	*/

	/dts-v1/;
	#include "rk3368.dtsi"
	#include <dt-bindings/input/input.h>

	/ {
	model = "Rockchip PX5 EVB";
	compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";

	chosen {
	stdout-path = "serial4:115200n8";
	};

	memory@0 {
	reg = <0x0 0x0 0x0 0x40000000>;
	device_type = "memory";
	};

	keys: gpio-keys {
	compatible = "gpio-keys";
	pinctrl-names = "default";
	pinctrl-0 = <&pwr_key>;

	power {
	gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
	label = "GPIO Power";
	linux,code = <KEY_POWER>;
	wakeup-source;
	};
	};

	vcc_sys: vcc-sys-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vcc_sys";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	regulator-boot-on;
	};
	};

	&emmc {
	status = "okay";
	bus-width = <8>;
	cap-mmc-highspeed;
	clock-frequency = <150000000>;
	mmc-hs200-1_8v;
	no-sdio;
	no-sd;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
	vmmc-supply = <&vcc_io>;
	vqmmc-supply = <&vcc18_flash>;
	};

	&i2c0 {
	status = "okay";

	rk808: pmic@1b {
	compatible = "rockchip,rk808";
	reg = <0x1b>;
	interrupt-parent = <&gpio0>;
	interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int>, <&pmic_sleep>;
	rockchip,system-power-controller;
	vcc1-supply = <&vcc_sys>;
	vcc2-supply = <&vcc_sys>;
	vcc3-supply = <&vcc_sys>;
	vcc4-supply = <&vcc_sys>;
	vcc6-supply = <&vcc_sys>;
	vcc7-supply = <&vcc_sys>;
	vcc8-supply = <&vcc_io>;
	vcc9-supply = <&vcc_sys>;
	vcc10-supply = <&vcc_sys>;
	vcc11-supply = <&vcc_sys>;
	vcc12-supply = <&vcc_io>;
	clock-output-names = "xin32k", "rk808-clkout2";
	#clock-cells = <1>;

	regulators {
	vdd_cpu: DCDC_REG1 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1500000>;
	regulator-name = "vdd_cpu";
	};

	vdd_log: DCDC_REG2 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1500000>;
	regulator-name = "vdd_log";
	};

	vcc_ddr: DCDC_REG3 {
	regulator-always-on;
	regulator-boot-on;
	regulator-name = "vcc_ddr";
	};

	vcc_io: DCDC_REG4 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc_io";
	};

	vcc18_flash: LDO_REG1 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc18_flash";
	};

	vcca_33: LDO_REG2 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcca_33";
	};

	vdd_10: LDO_REG3 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-name = "vdd_10";
	};

	avdd_33: LDO_REG4 {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "avdd_33";
	};

	vccio_sd: LDO_REG5 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vccio_sd";
	};

	vdd10_lcd: LDO_REG6 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1000000>;
	regulator-name = "vdd10_lcd";
	};

	vcc_18: LDO_REG7 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc_18";
	};

	vcc18_lcd: LDO_REG8 {
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc18_lcd";
	};

	vcc_sd: SWITCH_REG1 {
	regulator-name = "vcc_sd";
	};

	vcc33_lcd: SWITCH_REG2 {
	regulator-always-on;
	regulator-boot-on;
	regulator-name = "vcc33_lcd";
	};
	};
	};
	};

	&i2c1 {
	status = "okay";

	accelerometer@18 {
	compatible = "bosch,bma250";
	reg = <0x18>;
	interrupt-parent = <&gpio2>;
	interrupts = <RK_PC1 IRQ_TYPE_LEVEL_LOW>;
	};
	};

	&i2c2 {
	status = "okay";

	gsl1680: touchscreen@40 {
	compatible = "silead,gsl1680";
	reg = <0x40>;
	interrupt-parent = <&gpio3>;
	interrupts = <RK_PD4 IRQ_TYPE_EDGE_FALLING>;
	power-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
	touchscreen-size-x = <800>;
	touchscreen-size-y = <1280>;
	silead,max-fingers = <5>;
	};
	};

	&pinctrl {
	keys {
	pwr_key: pwr-key {
	rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	pmic {
	pmic_sleep: pmic-sleep {
	rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
	};

	pmic_int: pmic-int {
	rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};
	};

	&sdmmc {
	status = "okay";
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	card-detect-delay = <200>;
	- no-emmc;
	no-sdio;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_bus4>, <&sdmmc_cd>;
	rockchip,default-sample-phase = <90>;
	vmmc-supply = <&vcc_sd>;
	vqmmc-supply = <&vccio_sd>;
	};

	&tsadc {
	status = "okay";
	rockchip,hw-tshut-mode = <0>; /* CRU */
	rockchip,hw-tshut-polarity = <1>; /* high */
	};

	&uart4 {
	status = "okay";
	};

	&usb_host0_ehci {
	status = "okay";
	};

	&usb_otg {
	status = "okay";
	};

	&wdt {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3368.dtsi b/sys/gnu/dts/arm64/rockchip/rk3368.dtsi
	index a0df61c61925..1ebb0eef42da 100644
	--- a/sys/gnu/dts/arm64/rockchip/rk3368.dtsi
	+++ b/sys/gnu/dts/arm64/rockchip/rk3368.dtsi
	@@ -1,1226 +1,1225 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
	*/

	#include <dt-bindings/clock/rk3368-cru.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/pinctrl/rockchip.h>
	#include <dt-bindings/soc/rockchip,boot-mode.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	compatible = "rockchip,rk3368";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	ethernet0 = &gmac;
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	serial0 = &uart0;
	serial1 = &uart1;
	serial2 = &uart2;
	serial3 = &uart3;
	serial4 = &uart4;
	spi0 = &spi0;
	spi1 = &spi1;
	spi2 = &spi2;
	};

	cpus {
	#address-cells = <0x2>;
	#size-cells = <0x0>;

	cpu-map {
	cluster0 {
	core0 {
	cpu = <&cpu_b0>;
	};
	core1 {
	cpu = <&cpu_b1>;
	};
	core2 {
	cpu = <&cpu_b2>;
	};
	core3 {
	cpu = <&cpu_b3>;
	};
	};

	cluster1 {
	core0 {
	cpu = <&cpu_l0>;
	};
	core1 {
	cpu = <&cpu_l1>;
	};
	core2 {
	cpu = <&cpu_l2>;
	};
	core3 {
	cpu = <&cpu_l3>;
	};
	};
	};

	cpu_l0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x0>;
	enable-method = "psci";
	#cooling-cells = <2>; /* min followed by max */
	};

	cpu_l1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x1>;
	enable-method = "psci";
	#cooling-cells = <2>; /* min followed by max */
	};

	cpu_l2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x2>;
	enable-method = "psci";
	#cooling-cells = <2>; /* min followed by max */
	};

	cpu_l3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x3>;
	enable-method = "psci";
	#cooling-cells = <2>; /* min followed by max */
	};

	cpu_b0: cpu@100 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x100>;
	enable-method = "psci";
	#cooling-cells = <2>; /* min followed by max */
	};

	cpu_b1: cpu@101 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x101>;
	enable-method = "psci";
	#cooling-cells = <2>; /* min followed by max */
	};

	cpu_b2: cpu@102 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x102>;
	enable-method = "psci";
	#cooling-cells = <2>; /* min followed by max */
	};

	cpu_b3: cpu@103 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x103>;
	enable-method = "psci";
	#cooling-cells = <2>; /* min followed by max */
	};
	};

	- amba {
	+ amba: bus {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	dmac_peri: dma-controller@ff250000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x0 0xff250000 0x0 0x4000>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	arm,pl330-broken-no-flushp;
	clocks = <&cru ACLK_DMAC_PERI>;
	clock-names = "apb_pclk";
	};

	dmac_bus: dma-controller@ff600000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x0 0xff600000 0x0 0x4000>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	arm,pl330-broken-no-flushp;
	clocks = <&cru ACLK_DMAC_BUS>;
	clock-names = "apb_pclk";
	};
	};

	arm-pmu {
	compatible = "arm,armv8-pmuv3";
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
	<&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
	<&cpu_b2>, <&cpu_b3>;
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13
	(GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 14
	(GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 11
	(GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 10
	(GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	xin24m: oscillator {
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-output-names = "xin24m";
	#clock-cells = <0>;
	};

	sdmmc: mmc@ff0c0000 {
	compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x0 0xff0c0000 0x0 0x4000>;
	max-frequency = <150000000>;
	clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
	<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&cru SRST_MMC0>;
	reset-names = "reset";
	status = "disabled";
	};

	sdio0: mmc@ff0d0000 {
	compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x0 0xff0d0000 0x0 0x4000>;
	max-frequency = <150000000>;
	clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
	<&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&cru SRST_SDIO0>;
	reset-names = "reset";
	status = "disabled";
	};

	emmc: mmc@ff0f0000 {
	compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
	reg = <0x0 0xff0f0000 0x0 0x4000>;
	max-frequency = <150000000>;
	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
	<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&cru SRST_EMMC>;
	reset-names = "reset";
	status = "disabled";
	};

	saradc: saradc@ff100000 {
	compatible = "rockchip,saradc";
	reg = <0x0 0xff100000 0x0 0x100>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	#io-channel-cells = <1>;
	clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
	clock-names = "saradc", "apb_pclk";
	resets = <&cru SRST_SARADC>;
	reset-names = "saradc-apb";
	status = "disabled";
	};

	spi0: spi@ff110000 {
	compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
	reg = <0x0 0xff110000 0x0 0x1000>;
	clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
	clock-names = "spiclk", "apb_pclk";
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi1: spi@ff120000 {
	compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
	reg = <0x0 0xff120000 0x0 0x1000>;
	clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
	clock-names = "spiclk", "apb_pclk";
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi2: spi@ff130000 {
	compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
	reg = <0x0 0xff130000 0x0 0x1000>;
	clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
	clock-names = "spiclk", "apb_pclk";
	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c2: i2c@ff140000 {
	compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
	reg = <0x0 0xff140000 0x0 0x1000>;
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C2>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
	status = "disabled";
	};

	i2c3: i2c@ff150000 {
	compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
	reg = <0x0 0xff150000 0x0 0x1000>;
	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C3>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
	status = "disabled";
	};

	i2c4: i2c@ff160000 {
	compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
	reg = <0x0 0xff160000 0x0 0x1000>;
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C4>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_xfer>;
	status = "disabled";
	};

	i2c5: i2c@ff170000 {
	compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
	reg = <0x0 0xff170000 0x0 0x1000>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C5>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c5_xfer>;
	status = "disabled";
	};

	uart0: serial@ff180000 {
	compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff180000 0x0 0x100>;
	clock-frequency = <24000000>;
	clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
	clock-names = "baudclk", "apb_pclk";
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	status = "disabled";
	};

	uart1: serial@ff190000 {
	compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff190000 0x0 0x100>;
	clock-frequency = <24000000>;
	clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
	clock-names = "baudclk", "apb_pclk";
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	status = "disabled";
	};

	uart3: serial@ff1b0000 {
	compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff1b0000 0x0 0x100>;
	clock-frequency = <24000000>;
	clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
	clock-names = "baudclk", "apb_pclk";
	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	status = "disabled";
	};

	uart4: serial@ff1c0000 {
	compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff1c0000 0x0 0x100>;
	clock-frequency = <24000000>;
	clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
	clock-names = "baudclk", "apb_pclk";
	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	status = "disabled";
	};

	thermal-zones {
	cpu {
	polling-delay-passive = <100>; /* milliseconds */
	polling-delay = <5000>; /* milliseconds */

	thermal-sensors = <&tsadc 0>;

	trips {
	cpu_alert0: cpu_alert0 {
	temperature = <75000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "passive";
	};
	cpu_alert1: cpu_alert1 {
	temperature = <80000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "passive";
	};
	cpu_crit: cpu_crit {
	temperature = <95000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu_alert0>;
	cooling-device =
	<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu_alert1>;
	cooling-device =
	<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	gpu {
	polling-delay-passive = <100>; /* milliseconds */
	polling-delay = <5000>; /* milliseconds */

	thermal-sensors = <&tsadc 1>;

	trips {
	gpu_alert0: gpu_alert0 {
	temperature = <80000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "passive";
	};
	gpu_crit: gpu_crit {
	temperature = <115000>; /* millicelsius */
	hysteresis = <2000>; /* millicelsius */
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&gpu_alert0>;
	cooling-device =
	<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};
	};

	tsadc: tsadc@ff280000 {
	compatible = "rockchip,rk3368-tsadc";
	reg = <0x0 0xff280000 0x0 0x100>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
	clock-names = "tsadc", "apb_pclk";
	resets = <&cru SRST_TSADC>;
	reset-names = "tsadc-apb";
	pinctrl-names = "init", "default", "sleep";
	pinctrl-0 = <&otp_gpio>;
	pinctrl-1 = <&otp_out>;
	pinctrl-2 = <&otp_gpio>;
	#thermal-sensor-cells = <1>;
	rockchip,hw-tshut-temp = <95000>;
	status = "disabled";
	};

	gmac: ethernet@ff290000 {
	compatible = "rockchip,rk3368-gmac";
	reg = <0x0 0xff290000 0x0 0x10000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	rockchip,grf = <&grf>;
	clocks = <&cru SCLK_MAC>,
	<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
	<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
	<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
	clock-names = "stmmaceth",
	"mac_clk_rx", "mac_clk_tx",
	"clk_mac_ref", "clk_mac_refout",
	"aclk_mac", "pclk_mac";
	status = "disabled";
	};

	usb_host0_ehci: usb@ff500000 {
	compatible = "generic-ehci";
	reg = <0x0 0xff500000 0x0 0x100>;
	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_HOST0>;
	- clock-names = "usbhost";
	status = "disabled";
	};

	usb_otg: usb@ff580000 {
	compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
	"snps,dwc2";
	reg = <0x0 0xff580000 0x0 0x40000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru HCLK_OTG0>;
	clock-names = "otg";
	dr_mode = "otg";
	g-np-tx-fifo-size = <16>;
	g-rx-fifo-size = <275>;
	g-tx-fifo-size = <256 128 128 64 64 32>;
	status = "disabled";
	};

	i2c0: i2c@ff650000 {
	compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
	reg = <0x0 0xff650000 0x0 0x1000>;
	clocks = <&cru PCLK_I2C0>;
	clock-names = "i2c";
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c1: i2c@ff660000 {
	compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
	reg = <0x0 0xff660000 0x0 0x1000>;
	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "i2c";
	clocks = <&cru PCLK_I2C1>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
	status = "disabled";
	};

	pwm0: pwm@ff680000 {
	compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
	reg = <0x0 0xff680000 0x0 0x10>;
	#pwm-cells = <3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_pin>;
	clocks = <&cru PCLK_PWM1>;
	clock-names = "pwm";
	status = "disabled";
	};

	pwm1: pwm@ff680010 {
	compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
	reg = <0x0 0xff680010 0x0 0x10>;
	#pwm-cells = <3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_pin>;
	clocks = <&cru PCLK_PWM1>;
	clock-names = "pwm";
	status = "disabled";
	};

	pwm2: pwm@ff680020 {
	compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
	reg = <0x0 0xff680020 0x0 0x10>;
	#pwm-cells = <3>;
	clocks = <&cru PCLK_PWM1>;
	clock-names = "pwm";
	status = "disabled";
	};

	pwm3: pwm@ff680030 {
	compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
	reg = <0x0 0xff680030 0x0 0x10>;
	#pwm-cells = <3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_pin>;
	clocks = <&cru PCLK_PWM1>;
	clock-names = "pwm";
	status = "disabled";
	};

	uart2: serial@ff690000 {
	compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff690000 0x0 0x100>;
	clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
	clock-names = "baudclk", "apb_pclk";
	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_xfer>;
	reg-shift = <2>;
	reg-io-width = <4>;
	status = "disabled";
	};

	mbox: mbox@ff6b0000 {
	compatible = "rockchip,rk3368-mailbox";
	reg = <0x0 0xff6b0000 0x0 0x1000>;
	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru PCLK_MAILBOX>;
	clock-names = "pclk_mailbox";
	#mbox-cells = <1>;
	status = "disabled";
	};

	pmugrf: syscon@ff738000 {
	compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
	reg = <0x0 0xff738000 0x0 0x1000>;

	pmu_io_domains: io-domains {
	compatible = "rockchip,rk3368-pmu-io-voltage-domain";
	status = "disabled";
	};

	reboot-mode {
	compatible = "syscon-reboot-mode";
	offset = <0x200>;
	mode-normal = <BOOT_NORMAL>;
	mode-recovery = <BOOT_RECOVERY>;
	mode-bootloader = <BOOT_FASTBOOT>;
	mode-loader = <BOOT_BL_DOWNLOAD>;
	};
	};

	cru: clock-controller@ff760000 {
	compatible = "rockchip,rk3368-cru";
	reg = <0x0 0xff760000 0x0 0x1000>;
	rockchip,grf = <&grf>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	grf: syscon@ff770000 {
	compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
	reg = <0x0 0xff770000 0x0 0x1000>;

	io_domains: io-domains {
	compatible = "rockchip,rk3368-io-voltage-domain";
	status = "disabled";
	};
	};

	wdt: watchdog@ff800000 {
	compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
	reg = <0x0 0xff800000 0x0 0x100>;
	clocks = <&cru PCLK_WDT>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	timer@ff810000 {
	compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
	reg = <0x0 0xff810000 0x0 0x20>;
	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
	};

	spdif: spdif@ff880000 {
	compatible = "rockchip,rk3368-spdif";
	reg = <0x0 0xff880000 0x0 0x1000>;
	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
	clock-names = "mclk", "hclk";
	dmas = <&dmac_bus 3>;
	dma-names = "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&spdif_tx>;
	status = "disabled";
	};

	i2s_2ch: i2s-2ch@ff890000 {
	compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
	reg = <0x0 0xff890000 0x0 0x1000>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "i2s_clk", "i2s_hclk";
	clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
	dmas = <&dmac_bus 6>, <&dmac_bus 7>;
	dma-names = "tx", "rx";
	status = "disabled";
	};

	i2s_8ch: i2s-8ch@ff898000 {
	compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
	reg = <0x0 0xff898000 0x0 0x1000>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "i2s_clk", "i2s_hclk";
	clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
	dmas = <&dmac_bus 0>, <&dmac_bus 1>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&i2s_8ch_bus>;
	status = "disabled";
	};

	iep_mmu: iommu@ff900800 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff900800 0x0 0x100>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "iep_mmu";
	clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	status = "disabled";
	};

	isp_mmu: iommu@ff914000 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff914000 0x0 0x100>,
	<0x0 0xff915000 0x0 0x100>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "isp_mmu";
	clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	rockchip,disable-mmu-reset;
	status = "disabled";
	};

	vop_mmu: iommu@ff930300 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff930300 0x0 0x100>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "vop_mmu";
	clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	status = "disabled";
	};

	hevc_mmu: iommu@ff9a0440 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff9a0440 0x0 0x40>,
	<0x0 0xff9a0480 0x0 0x40>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hevc_mmu";
	clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	status = "disabled";
	};

	vpu_mmu: iommu@ff9a0800 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff9a0800 0x0 0x100>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "vepu_mmu", "vdpu_mmu";
	clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	status = "disabled";
	};

	efuse256: efuse@ffb00000 {
	compatible = "rockchip,rk3368-efuse";
	reg = <0x0 0xffb00000 0x0 0x20>;
	#address-cells = <1>;
	#size-cells = <1>;
	clocks = <&cru PCLK_EFUSE256>;
	clock-names = "pclk_efuse";

	cpu_leakage: cpu-leakage@17 {
	reg = <0x17 0x1>;
	};
	temp_adjust: temp-adjust@1f {
	reg = <0x1f 0x1>;
	};
	};

	gic: interrupt-controller@ffb71000 {
	compatible = "arm,gic-400";
	interrupt-controller;
	#interrupt-cells = <3>;
	#address-cells = <0>;

	reg = <0x0 0xffb71000 0x0 0x1000>,
	<0x0 0xffb72000 0x0 0x2000>,
	<0x0 0xffb74000 0x0 0x2000>,
	<0x0 0xffb76000 0x0 0x2000>;
	interrupts = <GIC_PPI 9
	(GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	pinctrl: pinctrl {
	compatible = "rockchip,rk3368-pinctrl";
	rockchip,grf = <&grf>;
	rockchip,pmu = <&pmugrf>;
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	ranges;

	gpio0: gpio0@ff750000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff750000 0x0 0x100>;
	clocks = <&cru PCLK_GPIO0>;
	interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;

	gpio-controller;
	#gpio-cells = <0x2>;

	interrupt-controller;
	#interrupt-cells = <0x2>;
	};

	gpio1: gpio1@ff780000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff780000 0x0 0x100>;
	clocks = <&cru PCLK_GPIO1>;
	interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;

	gpio-controller;
	#gpio-cells = <0x2>;

	interrupt-controller;
	#interrupt-cells = <0x2>;
	};

	gpio2: gpio2@ff790000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff790000 0x0 0x100>;
	clocks = <&cru PCLK_GPIO2>;
	interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;

	gpio-controller;
	#gpio-cells = <0x2>;

	interrupt-controller;
	#interrupt-cells = <0x2>;
	};

	gpio3: gpio3@ff7a0000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff7a0000 0x0 0x100>;
	clocks = <&cru PCLK_GPIO3>;
	interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;

	gpio-controller;
	#gpio-cells = <0x2>;

	interrupt-controller;
	#interrupt-cells = <0x2>;
	};

	pcfg_pull_up: pcfg-pull-up {
	bias-pull-up;
	};

	pcfg_pull_down: pcfg-pull-down {
	bias-pull-down;
	};

	pcfg_pull_none: pcfg-pull-none {
	bias-disable;
	};

	pcfg_pull_none_12ma: pcfg-pull-none-12ma {
	bias-disable;
	drive-strength = <12>;
	};

	emmc {
	emmc_clk: emmc-clk {
	rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
	};

	emmc_cmd: emmc-cmd {
	rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
	};

	emmc_pwr: emmc-pwr {
	rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
	};

	emmc_bus1: emmc-bus1 {
	rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>;
	};

	emmc_bus4: emmc-bus4 {
	rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
	<1 RK_PC3 2 &pcfg_pull_up>,
	<1 RK_PC4 2 &pcfg_pull_up>,
	<1 RK_PC5 2 &pcfg_pull_up>;
	};

	emmc_bus8: emmc-bus8 {
	rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
	<1 RK_PC3 2 &pcfg_pull_up>,
	<1 RK_PC4 2 &pcfg_pull_up>,
	<1 RK_PC5 2 &pcfg_pull_up>,
	<1 RK_PC6 2 &pcfg_pull_up>,
	<1 RK_PC7 2 &pcfg_pull_up>,
	<1 RK_PD0 2 &pcfg_pull_up>,
	<1 RK_PD1 2 &pcfg_pull_up>;
	};
	};

	gmac {
	rgmii_pins: rgmii-pins {
	rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
	<3 RK_PD0 1 &pcfg_pull_none>,
	<3 RK_PC3 1 &pcfg_pull_none>,
	<3 RK_PB0 1 &pcfg_pull_none_12ma>,
	<3 RK_PB1 1 &pcfg_pull_none_12ma>,
	<3 RK_PB2 1 &pcfg_pull_none_12ma>,
	<3 RK_PB6 1 &pcfg_pull_none_12ma>,
	<3 RK_PD4 1 &pcfg_pull_none_12ma>,
	<3 RK_PB5 1 &pcfg_pull_none_12ma>,
	<3 RK_PB7 1 &pcfg_pull_none>,
	<3 RK_PC0 1 &pcfg_pull_none>,
	<3 RK_PC1 1 &pcfg_pull_none>,
	<3 RK_PC2 1 &pcfg_pull_none>,
	<3 RK_PD1 1 &pcfg_pull_none>,
	<3 RK_PC4 1 &pcfg_pull_none>;
	};

	rmii_pins: rmii-pins {
	rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
	<3 RK_PD0 1 &pcfg_pull_none>,
	<3 RK_PC3 1 &pcfg_pull_none>,
	<3 RK_PB0 1 &pcfg_pull_none_12ma>,
	<3 RK_PB1 1 &pcfg_pull_none_12ma>,
	<3 RK_PB5 1 &pcfg_pull_none_12ma>,
	<3 RK_PB7 1 &pcfg_pull_none>,
	<3 RK_PC0 1 &pcfg_pull_none>,
	<3 RK_PC4 1 &pcfg_pull_none>,
	<3 RK_PC5 1 &pcfg_pull_none>;
	};
	};

	i2c0 {
	i2c0_xfer: i2c0-xfer {
	rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
	<0 RK_PA7 1 &pcfg_pull_none>;
	};
	};

	i2c1 {
	i2c1_xfer: i2c1-xfer {
	rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>,
	<2 RK_PC6 1 &pcfg_pull_none>;
	};
	};

	i2c2 {
	i2c2_xfer: i2c2-xfer {
	rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
	<3 RK_PD7 2 &pcfg_pull_none>;
	};
	};

	i2c3 {
	i2c3_xfer: i2c3-xfer {
	rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
	<1 RK_PC1 1 &pcfg_pull_none>;
	};
	};

	i2c4 {
	i2c4_xfer: i2c4-xfer {
	rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
	<3 RK_PD1 2 &pcfg_pull_none>;
	};
	};

	i2c5 {
	i2c5_xfer: i2c5-xfer {
	rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>,
	<3 RK_PD3 2 &pcfg_pull_none>;
	};
	};

	i2s {
	i2s_8ch_bus: i2s-8ch-bus {
	rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
	<2 RK_PB5 1 &pcfg_pull_none>,
	<2 RK_PB6 1 &pcfg_pull_none>,
	<2 RK_PB7 1 &pcfg_pull_none>,
	<2 RK_PC0 1 &pcfg_pull_none>,
	<2 RK_PC1 1 &pcfg_pull_none>,
	<2 RK_PC2 1 &pcfg_pull_none>,
	<2 RK_PC3 1 &pcfg_pull_none>,
	<2 RK_PC4 1 &pcfg_pull_none>;
	};
	};

	pwm0 {
	pwm0_pin: pwm0-pin {
	rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>;
	};
	};

	pwm1 {
	pwm1_pin: pwm1-pin {
	rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
	};
	};

	pwm3 {
	pwm3_pin: pwm3-pin {
	rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>;
	};
	};

	sdio0 {
	sdio0_bus1: sdio0-bus1 {
	rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>;
	};

	sdio0_bus4: sdio0-bus4 {
	rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>,
	<2 RK_PD5 1 &pcfg_pull_up>,
	<2 RK_PD6 1 &pcfg_pull_up>,
	<2 RK_PD7 1 &pcfg_pull_up>;
	};

	sdio0_cmd: sdio0-cmd {
	rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>;
	};

	sdio0_clk: sdio0-clk {
	rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
	};

	sdio0_cd: sdio0-cd {
	rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>;
	};

	sdio0_wp: sdio0-wp {
	rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>;
	};

	sdio0_pwr: sdio0-pwr {
	rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>;
	};

	sdio0_bkpwr: sdio0-bkpwr {
	rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>;
	};

	sdio0_int: sdio0-int {
	rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>;
	};
	};

	sdmmc {
	sdmmc_clk: sdmmc-clk {
	rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
	};

	sdmmc_cmd: sdmmc-cmd {
	rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
	};

	sdmmc_cd: sdmmc-cd {
	rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
	};

	sdmmc_bus1: sdmmc-bus1 {
	rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
	};

	sdmmc_bus4: sdmmc-bus4 {
	rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>,
	<2 RK_PA6 1 &pcfg_pull_up>,
	<2 RK_PA7 1 &pcfg_pull_up>,
	<2 RK_PB0 1 &pcfg_pull_up>;
	};
	};

	spdif {
	spdif_tx: spdif-tx {
	rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
	};
	};

	spi0 {
	spi0_clk: spi0-clk {
	rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>;
	};
	spi0_cs0: spi0-cs0 {
	rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>;
	};
	spi0_cs1: spi0-cs1 {
	rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>;
	};
	spi0_tx: spi0-tx {
	rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>;
	};
	spi0_rx: spi0-rx {
	rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>;
	};
	};

	spi1 {
	spi1_clk: spi1-clk {
	rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
	};
	spi1_cs0: spi1-cs0 {
	rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>;
	};
	spi1_cs1: spi1-cs1 {
	rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>;
	};
	spi1_rx: spi1-rx {
	rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>;
	};
	spi1_tx: spi1-tx {
	rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>;
	};
	};

	spi2 {
	spi2_clk: spi2-clk {
	rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
	};
	spi2_cs0: spi2-cs0 {
	rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
	};
	spi2_rx: spi2-rx {
	rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
	};
	spi2_tx: spi2-tx {
	rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
	};
	};

	tsadc {
	otp_gpio: otp-gpio {
	rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	otp_out: otp-out {
	rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
	};
	};

	uart0 {
	uart0_xfer: uart0-xfer {
	rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
	<2 RK_PD1 1 &pcfg_pull_none>;
	};

	uart0_cts: uart0-cts {
	rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
	};

	uart0_rts: uart0-rts {
	rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
	};
	};

	uart1 {
	uart1_xfer: uart1-xfer {
	rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
	<0 RK_PC5 3 &pcfg_pull_none>;
	};

	uart1_cts: uart1-cts {
	rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
	};

	uart1_rts: uart1-rts {
	rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
	};
	};

	uart2 {
	uart2_xfer: uart2-xfer {
	rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
	<2 RK_PA5 2 &pcfg_pull_none>;
	};
	/* no rts / cts for uart2 */
	};

	uart3 {
	uart3_xfer: uart3-xfer {
	rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
	<3 RK_PD6 3 &pcfg_pull_none>;
	};

	uart3_cts: uart3-cts {
	rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>;
	};

	uart3_rts: uart3-rts {
	rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>;
	};
	};

	uart4 {
	uart4_xfer: uart4-xfer {
	rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
	<0 RK_PD2 3 &pcfg_pull_none>;
	};

	uart4_cts: uart4-cts {
	rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
	};

	uart4_rts: uart4-rts {
	rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-evb.dts b/sys/gnu/dts/arm64/rockchip/rk3399-evb.dts
	index 77008dca45bc..694b0d08d644 100644
	--- a/sys/gnu/dts/arm64/rockchip/rk3399-evb.dts
	+++ b/sys/gnu/dts/arm64/rockchip/rk3399-evb.dts
	@@ -1,226 +1,480 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
	*/

	/dts-v1/;
	#include <dt-bindings/pwm/pwm.h>
	#include "rk3399.dtsi"

	/ {
	model = "Rockchip RK3399 Evaluation Board";
	- compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
	- "google,rk3399evb-rev2";
	+ compatible = "rockchip,rk3399-evb", "rockchip,rk3399";

	backlight: backlight {
	compatible = "pwm-backlight";
	brightness-levels = <
	0 1 2 3 4 5 6 7
	8 9 10 11 12 13 14 15
	16 17 18 19 20 21 22 23
	24 25 26 27 28 29 30 31
	32 33 34 35 36 37 38 39
	40 41 42 43 44 45 46 47
	48 49 50 51 52 53 54 55
	56 57 58 59 60 61 62 63
	64 65 66 67 68 69 70 71
	72 73 74 75 76 77 78 79
	80 81 82 83 84 85 86 87
	88 89 90 91 92 93 94 95
	96 97 98 99 100 101 102 103
	104 105 106 107 108 109 110 111
	112 113 114 115 116 117 118 119
	120 121 122 123 124 125 126 127
	128 129 130 131 132 133 134 135
	136 137 138 139 140 141 142 143
	144 145 146 147 148 149 150 151
	152 153 154 155 156 157 158 159
	160 161 162 163 164 165 166 167
	168 169 170 171 172 173 174 175
	176 177 178 179 180 181 182 183
	184 185 186 187 188 189 190 191
	192 193 194 195 196 197 198 199
	200 201 202 203 204 205 206 207
	208 209 210 211 212 213 214 215
	216 217 218 219 220 221 222 223
	224 225 226 227 228 229 230 231
	232 233 234 235 236 237 238 239
	240 241 242 243 244 245 246 247
	248 249 250 251 252 253 254 255>;
	default-brightness-level = <200>;
	- enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
	pwms = <&pwm0 0 25000 0>;
	};

	+ edp_panel: edp-panel {
	+ compatible ="lg,lp079qx1-sp0v";
	+ backlight = <&backlight>;
	+ enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
	+ power-supply = <&vcc3v3_s0>;
	+
	+ port {
	+ panel_in_edp: endpoint {
	+ remote-endpoint = <&edp_out_panel>;
	+ };
	+ };
	+ };
	+
	clkin_gmac: external-gmac-clock {
	compatible = "fixed-clock";
	clock-frequency = <125000000>;
	clock-output-names = "clkin_gmac";
	#clock-cells = <0>;
	};

	vdd_center: vdd-center {
	compatible = "pwm-regulator";
	pwms = <&pwm3 0 25000 0>;
	regulator-name = "vdd_center";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1400000>;
	regulator-always-on;
	regulator-boot-on;
	status = "okay";
	};

	vcc3v3_sys: vcc3v3-sys {
	compatible = "regulator-fixed";
	regulator-name = "vcc3v3_sys";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	vcc5v0_sys: vcc5v0-sys {
	compatible = "regulator-fixed";
	regulator-name = "vcc5v0_sys";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	};

	vcc5v0_host: vcc5v0-host-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&vcc5v0_host_en>;
	regulator-name = "vcc5v0_host";
	vin-supply = <&vcc5v0_sys>;
	};

	vcc_phy: vcc-phy-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vcc_phy";
	regulator-always-on;
	regulator-boot-on;
	};

	vcc_phy: vcc-phy-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vcc_phy";
	regulator-always-on;
	regulator-boot-on;
	};

	};

	+&edp {
	+ status = "okay";
	+ force-hpd;
	+
	+ ports {
	+ edp_out: port@1 {
	+ reg = <1>;
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ edp_out_panel: endpoint@0 {
	+ reg = <0>;
	+ remote-endpoint = <&panel_in_edp>;
	+ };
	+ };
	+ };
	+};
	+
	&emmc_phy {
	status = "okay";
	};

	&gmac {
	assigned-clocks = <&cru SCLK_RMII_SRC>;
	assigned-clock-parents = <&clkin_gmac>;
	clock_in_out = "input";
	phy-supply = <&vcc_phy>;
	phy-mode = "rgmii";
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins>;
	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;
	snps,reset-delays-us = <0 10000 50000>;
	tx_delay = <0x28>;
	rx_delay = <0x11>;
	status = "okay";
	};

	+&i2c0 {
	+ status = "okay";
	+
	+ rk808: pmic@1b {
	+ compatible = "rockchip,rk808";
	+ reg = <0x1b>;
	+ interrupt-parent = <&gpio1>;
	+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pmic_int_l>;
	+ rockchip,system-power-controller;
	+ wakeup-source;
	+ #clock-cells = <1>;
	+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
	+
	+ vcc1-supply = <&vcc3v3_sys>;
	+ vcc2-supply = <&vcc3v3_sys>;
	+ vcc3-supply = <&vcc3v3_sys>;
	+ vcc4-supply = <&vcc3v3_sys>;
	+ vcc6-supply = <&vcc3v3_sys>;
	+ vcc7-supply = <&vcc3v3_sys>;
	+ vcc8-supply = <&vcc3v3_sys>;
	+ vcc9-supply = <&vcc3v3_sys>;
	+ vcc10-supply = <&vcc3v3_sys>;
	+ vcc11-supply = <&vcc3v3_sys>;
	+ vcc12-supply = <&vcc3v3_sys>;
	+ vddio-supply = <&vcc1v8_pmu>;
	+
	+ regulators {
	+ vdd_log: DCDC_REG1 {
	+ regulator-name = "vdd_log";
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <1350000>;
	+ regulator-ramp-delay = <6001>;
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-state-mem {
	+ regulator-on-in-suspend;
	+ regulator-suspend-microvolt = <900000>;
	+ };
	+ };
	+
	+ vdd_cpu_l: DCDC_REG2 {
	+ regulator-name = "vdd_cpu_l";
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <1350000>;
	+ regulator-ramp-delay = <6001>;
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ vcc_ddr: DCDC_REG3 {
	+ regulator-name = "vcc_ddr";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-state-mem {
	+ regulator-on-in-suspend;
	+ };
	+ };
	+
	+ vcc_1v8: DCDC_REG4 {
	+ regulator-name = "vcc_1v8";
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-state-mem {
	+ regulator-on-in-suspend;
	+ regulator-suspend-microvolt = <1800000>;
	+ };
	+ };
	+
	+ vcc1v8_dvp: LDO_REG1 {
	+ regulator-name = "vcc1v8_dvp";
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ vcc3v0_tp: LDO_REG2 {
	+ regulator-name = "vcc3v0_tp";
	+ regulator-min-microvolt = <3000000>;
	+ regulator-max-microvolt = <3000000>;
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ vcc1v8_pmu: LDO_REG3 {
	+ regulator-name = "vcc1v8_pmu";
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-state-mem {
	+ regulator-on-in-suspend;
	+ regulator-suspend-microvolt = <1800000>;
	+ };
	+ };
	+
	+ vcc_sd: LDO_REG4 {
	+ regulator-name = "vcc_sd";
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <3000000>;
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-state-mem {
	+ regulator-on-in-suspend;
	+ regulator-suspend-microvolt = <3000000>;
	+ };
	+ };
	+
	+ vcca3v0_codec: LDO_REG5 {
	+ regulator-name = "vcca3v0_codec";
	+ regulator-min-microvolt = <3000000>;
	+ regulator-max-microvolt = <3000000>;
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ vcc_1v5: LDO_REG6 {
	+ regulator-name = "vcc_1v5";
	+ regulator-min-microvolt = <1500000>;
	+ regulator-max-microvolt = <1500000>;
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-state-mem {
	+ regulator-on-in-suspend;
	+ regulator-suspend-microvolt = <1500000>;
	+ };
	+ };
	+
	+ vcca1v8_codec: LDO_REG7 {
	+ regulator-name = "vcca1v8_codec";
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ vcc_3v0: LDO_REG8 {
	+ regulator-name = "vcc_3v0";
	+ regulator-min-microvolt = <3000000>;
	+ regulator-max-microvolt = <3000000>;
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-state-mem {
	+ regulator-on-in-suspend;
	+ regulator-suspend-microvolt = <3000000>;
	+ };
	+ };
	+
	+ vcc3v3_s3: SWITCH_REG1 {
	+ regulator-name = "vcc3v3_s3";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-state-mem {
	+ regulator-on-in-suspend;
	+ };
	+ };
	+
	+ vcc3v3_s0: SWITCH_REG2 {
	+ regulator-name = "vcc3v3_s0";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+ };
	+ };
	+
	+ vdd_cpu_b: regulator@40 {
	+ compatible = "silergy,syr827";
	+ reg = <0x40>;
	+ fcs,suspend-voltage-selector = <1>;
	+ regulator-name = "vdd_cpu_b";
	+ regulator-min-microvolt = <712500>;
	+ regulator-max-microvolt = <1500000>;
	+ regulator-ramp-delay = <1000>;
	+ regulator-always-on;
	+ regulator-boot-on;
	+ vin-supply = <&vcc5v0_sys>;
	+
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ vdd_gpu: regulator@41 {
	+ compatible = "silergy,syr828";
	+ reg = <0x41>;
	+ fcs,suspend-voltage-selector = <1>;
	+ regulator-name = "vdd_gpu";
	+ regulator-min-microvolt = <712500>;
	+ regulator-max-microvolt = <1500000>;
	+ regulator-ramp-delay = <1000>;
	+ regulator-always-on;
	+ regulator-boot-on;
	+ vin-supply = <&vcc5v0_sys>;
	+
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+};
	+
	&pwm0 {
	status = "okay";
	};

	&pwm2 {
	status = "okay";
	};

	&pwm3 {
	status = "okay";
	};

	&sdhci {
	bus-width = <8>;
	mmc-hs400-1_8v;
	mmc-hs400-enhanced-strobe;
	non-removable;
	status = "okay";
	};

	&pcie_phy {
	status = "disabled";
	};

	&pcie0 {
	ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
	num-lanes = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pcie_clkreqn_cpm>;
	status = "disabled";
	};

	&u2phy0 {
	status = "okay";
	};

	&u2phy0_host {
	phy-supply = <&vcc5v0_host>;
	status = "okay";
	};

	&u2phy1 {
	status = "okay";
	};

	&u2phy1_host {
	phy-supply = <&vcc5v0_host>;
	status = "okay";
	};

	&uart2 {
	status = "okay";
	};

	&usb_host0_ehci {
	status = "okay";
	};

	&usb_host0_ohci {
	status = "okay";
	};

	&usb_host1_ehci {
	status = "okay";
	};

	&usb_host1_ohci {
	status = "okay";
	};

	&pinctrl {
	pmic {
	pmic_int_l: pmic-int-l {
	rockchip,pins =
	<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	-
	- pmic_dvs2: pmic-dvs2 {
	- rockchip,pins =
	- <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
	- };
	};

	usb2 {
	vcc5v0_host_en: vcc5v0-host-en {
	rockchip,pins =
	<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};
	};
	+
	+&vopb {
	+ status = "okay";
	+};
	+
	+&vopb_mmu {
	+ status = "okay";
	+};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-gru-chromebook.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399-gru-chromebook.dtsi
	index 7cd6d470c1cb..1384dabbdf40 100644
	--- a/sys/gnu/dts/arm64/rockchip/rk3399-gru-chromebook.dtsi
	+++ b/sys/gnu/dts/arm64/rockchip/rk3399-gru-chromebook.dtsi
	@@ -1,402 +1,400 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Google Gru-Chromebook shared properties
	*
	* Copyright 2018 Google, Inc
	*/

	#include "rk3399-gru.dtsi"

	/ {
	pp900_ap: pp900-ap {
	compatible = "regulator-fixed";
	regulator-name = "pp900_ap";

	/* EC turns on w/ pp900_ap_en; always on for AP */
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <900000>;

	vin-supply = <&ppvar_sys>;
	};

	/* EC turns on w/ pp900_usb_en */
	pp900_usb: pp900-ap {
	};

	/* EC turns on w/ pp900_pcie_en */
	pp900_pcie: pp900-ap {
	};

	pp3000: pp3000 {
	compatible = "regulator-fixed";
	regulator-name = "pp3000";
	pinctrl-names = "default";
	pinctrl-0 = <&pp3000_en>;

	enable-active-high;
	gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;

	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;

	vin-supply = <&ppvar_sys>;
	};

	ppvar_centerlogic_pwm: ppvar-centerlogic-pwm {
	compatible = "pwm-regulator";
	regulator-name = "ppvar_centerlogic_pwm";

	pwms = <&pwm3 0 3337 0>;
	pwm-supply = <&ppvar_sys>;
	pwm-dutycycle-range = <100 0>;
	pwm-dutycycle-unit = <100>;

	/* EC turns on w/ ppvar_centerlogic_en; always on for AP */
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <799434>;
	regulator-max-microvolt = <1049925>;
	};

	ppvar_centerlogic: ppvar-centerlogic {
	compatible = "vctrl-regulator";
	regulator-name = "ppvar_centerlogic";

	regulator-min-microvolt = <799434>;
	regulator-max-microvolt = <1049925>;

	ctrl-supply = <&ppvar_centerlogic_pwm>;
	ctrl-voltage-range = <799434 1049925>;

	regulator-settling-time-up-us = <378>;
	min-slew-down-rate = <225>;
	ovp-threshold-percent = <16>;
	};

	/* Schematics call this PPVAR even though it's fixed */
	ppvar_logic: ppvar-logic {
	compatible = "regulator-fixed";
	regulator-name = "ppvar_logic";

	/* EC turns on w/ ppvar_logic_en; always on for AP */
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <900000>;

	vin-supply = <&ppvar_sys>;
	};

	pp1800_audio: pp1800-audio {
	compatible = "regulator-fixed";
	regulator-name = "pp1800_audio";
	pinctrl-names = "default";
	pinctrl-0 = <&pp1800_audio_en>;

	enable-active-high;
	gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>;

	regulator-always-on;
	regulator-boot-on;

	vin-supply = <&pp1800>;
	};

	/* gpio is shared with pp3300_wifi_bt */
	pp1800_pcie: pp1800-pcie {
	compatible = "regulator-fixed";
	regulator-name = "pp1800_pcie";
	pinctrl-names = "default";
	pinctrl-0 = <&wlan_module_pd_l>;

	enable-active-high;
	gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;

	/*
	* Need to wait 1ms + ramp-up time before we can power on WiFi.
	* This has been approximated as 8ms total.
	*/
	regulator-enable-ramp-delay = <8000>;

	vin-supply = <&pp1800>;
	};

	/* Always on; plain and simple */
	pp3000_ap: pp3000_emmc: pp3000 {
	};

	pp1500_ap_io: pp1500-ap-io {
	compatible = "regulator-fixed";
	regulator-name = "pp1500_ap_io";
	pinctrl-names = "default";
	pinctrl-0 = <&pp1500_en>;

	enable-active-high;
	gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;

	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1500000>;

	vin-supply = <&pp1800>;
	};

	pp3300_disp: pp3300-disp {
	compatible = "regulator-fixed";
	regulator-name = "pp3300_disp";
	pinctrl-names = "default";
	pinctrl-0 = <&pp3300_disp_en>;

	enable-active-high;
	gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;

	startup-delay-us = <2000>;
	vin-supply = <&pp3300>;
	};

	/* EC turns on w/ pp3300_usb_en_l */
	pp3300_usb: pp3300 {
	};

	/* gpio is shared with pp1800_pcie and pinctrl is set there */
	pp3300_wifi_bt: pp3300-wifi-bt {
	compatible = "regulator-fixed";
	regulator-name = "pp3300_wifi_bt";

	enable-active-high;
	gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;

	vin-supply = <&pp3300>;
	};

	/*
	* This is a bit of a hack. The WiFi module should be reset at least
	* 1ms after its regulators have ramped up (max rampup time is ~7ms).
	* With some stretching of the imagination, we can call the 1.8V
	* regulator a supply.
	*/
	wlan_pd_n: wlan-pd-n {
	compatible = "regulator-fixed";
	regulator-name = "wlan_pd_n";
	pinctrl-names = "default";
	pinctrl-0 = <&wlan_module_reset_l>;

	enable-active-high;
	gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;

	vin-supply = <&pp1800_pcie>;
	};

	backlight: backlight {
	compatible = "pwm-backlight";
	enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
	power-supply = <&pp3300_disp>;
	pinctrl-names = "default";
	pinctrl-0 = <&bl_en>;
	pwm-delay-us = <10000>;
	};

	gpio_keys: gpio-keys {
	compatible = "gpio-keys";
	pinctrl-names = "default";
	pinctrl-0 = <&bt_host_wake_l>;

	wake_on_bt: wake-on-bt {
	label = "Wake-on-Bluetooth";
	gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
	linux,code = <KEY_WAKEUP>;
	wakeup-source;
	};
	};
	};

	&ppvar_bigcpu {
	min-slew-down-rate = <225>;
	ovp-threshold-percent = <16>;
	};

	&ppvar_litcpu {
	min-slew-down-rate = <225>;
	ovp-threshold-percent = <16>;
	};

	&ppvar_gpu {
	min-slew-down-rate = <225>;
	ovp-threshold-percent = <16>;
	};

	&cdn_dp {
	extcon = <&usbc_extcon0>, <&usbc_extcon1>;
	};

	&edp {
	status = "okay";

	ports {
	edp_out: port@1 {
	reg = <1>;
	#address-cells = <1>;
	#size-cells = <0>;

	edp_out_panel: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&panel_in_edp>;
	};
	};
	};
	};

	ap_i2c_mic: &i2c1 {
	status = "okay";

	clock-frequency = <400000>;

	/* These are relatively safe rise/fall times */
	i2c-scl-falling-time-ns = <50>;
	i2c-scl-rising-time-ns = <300>;

	headsetcodec: rt5514@57 {
	compatible = "realtek,rt5514";
	reg = <0x57>;
	realtek,dmic-init-delay-ms = <20>;
	};
	};

	ap_i2c_tp: &i2c5 {
	status = "okay";

	clock-frequency = <400000>;

	/* These are relatively safe rise/fall times */
	i2c-scl-falling-time-ns = <50>;
	i2c-scl-rising-time-ns = <300>;

	/*
	* Note strange pullup enable. Apparently this avoids leakage but
	* still allows us to get nice 4.7K pullups for high speed i2c
	* transfers. Basically we want the pullup on whenever the ap is
	* alive, so the "en" pin just gets set to output high.
	*/
	pinctrl-0 = <&i2c5_xfer &ap_i2c_tp_pu_en>;
	};

	&cros_ec {
	cros_ec_pwm: ec-pwm {
	compatible = "google,cros-ec-pwm";
	#pwm-cells = <1>;
	};

	- usbc_extcon1: extcon@1 {
	+ usbc_extcon1: extcon1 {
	compatible = "google,extcon-usbc-cros-ec";
	google,usb-port-id = <1>;
	-
	- #extcon-cells = <0>;
	};
	};

	&sound {
	rockchip,codec = <&max98357a &headsetcodec
	&codec &wacky_spi_audio &cdn_dp>;
	};

	&spi2 {
	wacky_spi_audio: spi2@0 {
	compatible = "realtek,rt5514";
	reg = <0>;
	interrupt-parent = <&gpio1>;
	interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&mic_int>;
	/* May run faster once verified. */
	spi-max-frequency = <10000000>;
	wakeup-source;
	};
	};

	&pci_rootport {
	mvl_wifi: wifi@0,0 {
	compatible = "pci1b4b,2b42";
	reg = <0x83010000 0x0 0x00000000 0x0 0x00100000
	0x83010000 0x0 0x00100000 0x0 0x00100000>;
	interrupt-parent = <&gpio0>;
	interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&wlan_host_wake_l>;
	wakeup-source;
	};
	};

	&tcphy1 {
	status = "okay";
	extcon = <&usbc_extcon1>;
	};

	&u2phy1 {
	status = "okay";
	};

	&usb_host0_ehci {
	status = "okay";
	};

	&usb_host1_ehci {
	status = "okay";
	};

	&usb_host1_ohci {
	status = "okay";
	};

	&usbdrd3_1 {
	status = "okay";
	extcon = <&usbc_extcon1>;
	};

	&usbdrd_dwc3_1 {
	status = "okay";
	dr_mode = "host";
	};

	&pinctrl {
	discrete-regulators {
	pp1500_en: pp1500-en {
	rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO
	&pcfg_pull_none>;
	};

	pp1800_audio_en: pp1800-audio-en {
	rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO
	&pcfg_pull_down>;
	};

	pp3000_en: pp3000-en {
	rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO
	&pcfg_pull_none>;
	};

	pp3300_disp_en: pp3300-disp-en {
	rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO
	&pcfg_pull_none>;
	};

	wlan_module_pd_l: wlan-module-pd-l {
	rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO
	&pcfg_pull_down>;
	};
	};
	};

	&wifi {
	wifi_perst_l: wifi-perst-l {
	rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	wlan_host_wake_l: wlan-host-wake-l {
	rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-gru.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399-gru.dtsi
	index dd5624975c9b..2f3997740068 100644
	--- a/sys/gnu/dts/arm64/rockchip/rk3399-gru.dtsi
	+++ b/sys/gnu/dts/arm64/rockchip/rk3399-gru.dtsi
	@@ -1,826 +1,824 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Google Gru (and derivatives) board device tree source
	*
	* Copyright 2016-2017 Google, Inc
	*/

	#include <dt-bindings/input/input.h>
	#include "rk3399.dtsi"
	#include "rk3399-op1-opp.dtsi"

	/ {
	chosen {
	stdout-path = "serial2:115200n8";
	};

	/*
	* Power Tree
	*
	* In general an attempt is made to include all rails called out by
	* the schematic as long as those rails interact in some way with
	* the AP. AKA:
	* - Rails that only connect to the EC (or devices that the EC talks to)
	* are not included.
	* - Rails _are_ included if the rails go to the AP even if the AP
	* doesn't currently care about them / they are always on. The idea
	* here is that it makes it easier to map to the schematic or extend
	* later.
	*
	* If two rails are substantially the same from the AP's point of
	* view, though, we won't create a full fixed regulator. We'll just
	* put the child rail as an alias of the parent rail. Sometimes rails
	* look the same to the AP because one of these is true:
	* - The EC controls the enable and the EC always enables a rail as
	* long as the AP is running.
	* - The rails are actually connected to each other by a jumper and
	* the distinction is just there to add clarity/flexibility to the
	* schematic.
	*/

	ppvar_sys: ppvar-sys {
	compatible = "regulator-fixed";
	regulator-name = "ppvar_sys";
	regulator-always-on;
	regulator-boot-on;
	};

	pp1200_lpddr: pp1200-lpddr {
	compatible = "regulator-fixed";
	regulator-name = "pp1200_lpddr";

	/* EC turns on w/ lpddr_pwr_en; always on for AP */
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;

	vin-supply = <&ppvar_sys>;
	};

	pp1800: pp1800 {
	compatible = "regulator-fixed";
	regulator-name = "pp1800";

	/* Always on when ppvar_sys shows power good */
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;

	vin-supply = <&ppvar_sys>;
	};

	pp3300: pp3300 {
	compatible = "regulator-fixed";
	regulator-name = "pp3300";

	/* Always on; plain and simple */
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;

	vin-supply = <&ppvar_sys>;
	};

	pp5000: pp5000 {
	compatible = "regulator-fixed";
	regulator-name = "pp5000";

	/* EC turns on w/ pp5000_en; always on for AP */
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;

	vin-supply = <&ppvar_sys>;
	};

	ppvar_bigcpu_pwm: ppvar-bigcpu-pwm {
	compatible = "pwm-regulator";
	regulator-name = "ppvar_bigcpu_pwm";

	pwms = <&pwm1 0 3337 0>;
	pwm-supply = <&ppvar_sys>;
	pwm-dutycycle-range = <100 0>;
	pwm-dutycycle-unit = <100>;

	/* EC turns on w/ ap_core_en; always on for AP */
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <800107>;
	regulator-max-microvolt = <1302232>;
	};

	ppvar_bigcpu: ppvar-bigcpu {
	compatible = "vctrl-regulator";
	regulator-name = "ppvar_bigcpu";

	regulator-min-microvolt = <800107>;
	regulator-max-microvolt = <1302232>;

	ctrl-supply = <&ppvar_bigcpu_pwm>;
	ctrl-voltage-range = <800107 1302232>;

	regulator-settling-time-up-us = <322>;
	};

	ppvar_litcpu_pwm: ppvar-litcpu-pwm {
	compatible = "pwm-regulator";
	regulator-name = "ppvar_litcpu_pwm";

	pwms = <&pwm2 0 3337 0>;
	pwm-supply = <&ppvar_sys>;
	pwm-dutycycle-range = <100 0>;
	pwm-dutycycle-unit = <100>;

	/* EC turns on w/ ap_core_en; always on for AP */
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <797743>;
	regulator-max-microvolt = <1307837>;
	};

	ppvar_litcpu: ppvar-litcpu {
	compatible = "vctrl-regulator";
	regulator-name = "ppvar_litcpu";

	regulator-min-microvolt = <797743>;
	regulator-max-microvolt = <1307837>;

	ctrl-supply = <&ppvar_litcpu_pwm>;
	ctrl-voltage-range = <797743 1307837>;

	regulator-settling-time-up-us = <384>;
	};

	ppvar_gpu_pwm: ppvar-gpu-pwm {
	compatible = "pwm-regulator";
	regulator-name = "ppvar_gpu_pwm";

	pwms = <&pwm0 0 3337 0>;
	pwm-supply = <&ppvar_sys>;
	pwm-dutycycle-range = <100 0>;
	pwm-dutycycle-unit = <100>;

	/* EC turns on w/ ap_core_en; always on for AP */
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <786384>;
	regulator-max-microvolt = <1217747>;
	};

	ppvar_gpu: ppvar-gpu {
	compatible = "vctrl-regulator";
	regulator-name = "ppvar_gpu";

	regulator-min-microvolt = <786384>;
	regulator-max-microvolt = <1217747>;

	ctrl-supply = <&ppvar_gpu_pwm>;
	ctrl-voltage-range = <786384 1217747>;

	regulator-settling-time-up-us = <390>;
	};

	/* EC turns on w/ pp900_ddrpll_en */
	pp900_ddrpll: pp900-ap {
	};

	/* EC turns on w/ pp900_pll_en */
	pp900_pll: pp900-ap {
	};

	/* EC turns on w/ pp900_pmu_en */
	pp900_pmu: pp900-ap {
	};

	/* EC turns on w/ pp1800_s0_en_l */
	pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 {
	};

	/* EC turns on w/ pp1800_avdd_en_l */
	pp1800_avdd: pp1800 {
	};

	/* EC turns on w/ pp1800_lid_en_l */
	pp1800_lid: pp1800_mic: pp1800 {
	};

	/* EC turns on w/ lpddr_pwr_en */
	pp1800_lpddr: pp1800 {
	};

	/* EC turns on w/ pp1800_pmu_en_l */
	pp1800_pmu: pp1800 {
	};

	/* EC turns on w/ pp1800_usb_en_l */
	pp1800_usb: pp1800 {
	};

	pp3000_sd_slot: pp3000-sd-slot {
	compatible = "regulator-fixed";
	regulator-name = "pp3000_sd_slot";
	pinctrl-names = "default";
	pinctrl-0 = <&sd_slot_pwr_en>;

	enable-active-high;
	gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;

	vin-supply = <&pp3000>;
	};

	/*
	* Technically, this is a small abuse of 'regulator-gpio'; this
	* regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are
	* always on though, so it is sufficient to simply control the mux
	* here.
	*/
	ppvar_sd_card_io: ppvar-sd-card-io {
	compatible = "regulator-gpio";
	regulator-name = "ppvar_sd_card_io";
	pinctrl-names = "default";
	pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>;

	enable-active-high;
	enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
	gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
	states = <1800000 0x1
	3000000 0x0>;

	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3000000>;
	};

	/* EC turns on w/ pp3300_trackpad_en_l */
	pp3300_trackpad: pp3300-trackpad {
	};

	/* EC turns on w/ usb_a_en */
	pp5000_usb_a_vbus: pp5000 {
	};

	ap_rtc_clk: ap-rtc-clk {
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	clock-output-names = "xin32k";
	#clock-cells = <0>;
	};

	max98357a: max98357a {
	compatible = "maxim,max98357a";
	pinctrl-names = "default";
	pinctrl-0 = <&sdmode_en>;
	sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
	sdmode-delay = <2>;
	#sound-dai-cells = <0>;
	status = "okay";
	};

	sound: sound {
	compatible = "rockchip,rk3399-gru-sound";
	rockchip,cpu = <&i2s0 &i2s2>;
	};
	};

	&cdn_dp {
	status = "okay";
	};

	/*
	* Set some suspend operating points to avoid OVP in suspend
	*
	* When we go into S3 ARM Trusted Firmware will transition our PWM regulators
	* from wherever they're at back to the "default" operating point (whatever
	* voltage we get when we set the PWM pins to "input").
	*
	* This quick transition under light load has the possibility to trigger the
	* regulator "over voltage protection" (OVP).
	*
	* To make extra certain that we don't hit this OVP at suspend time, we'll
	* transition to a voltage that's much closer to the default (~1.0 V) so that
	* there will not be a big jump. Technically we only need to get within 200 mV
	* of the default voltage, but the speed here should be fast enough and we need
	* suspend/resume to be rock solid.
	*/

	&cluster0_opp {
	opp05 {
	opp-suspend;
	};
	};

	&cluster1_opp {
	opp06 {
	opp-suspend;
	};
	};

	&cpu_l0 {
	cpu-supply = <&ppvar_litcpu>;
	};

	&cpu_l1 {
	cpu-supply = <&ppvar_litcpu>;
	};

	&cpu_l2 {
	cpu-supply = <&ppvar_litcpu>;
	};

	&cpu_l3 {
	cpu-supply = <&ppvar_litcpu>;
	};

	&cpu_b0 {
	cpu-supply = <&ppvar_bigcpu>;
	};

	&cpu_b1 {
	cpu-supply = <&ppvar_bigcpu>;
	};


	&cru {
	assigned-clocks =
	<&cru PLL_GPLL>, <&cru PLL_CPLL>,
	<&cru PLL_NPLL>,
	<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
	<&cru PCLK_PERIHP>,
	<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
	<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
	<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
	<&cru ACLK_VIO>, <&cru ACLK_HDCP>,
	<&cru ACLK_GIC_PRE>,
	<&cru PCLK_DDR>;
	assigned-clock-rates =
	<600000000>, <800000000>,
	<1000000000>,
	<150000000>, <75000000>,
	<37500000>,
	<100000000>, <100000000>,
	<50000000>, <800000000>,
	<100000000>, <50000000>,
	<400000000>, <400000000>,
	<200000000>,
	<200000000>;
	};

	&emmc_phy {
	status = "okay";
	};

	&gpu {
	mali-supply = <&ppvar_gpu>;
	status = "okay";
	};

	ap_i2c_ts: &i2c3 {
	status = "okay";

	clock-frequency = <400000>;

	/* These are relatively safe rise/fall times */
	i2c-scl-falling-time-ns = <50>;
	i2c-scl-rising-time-ns = <300>;
	};

	ap_i2c_audio: &i2c8 {
	status = "okay";

	clock-frequency = <400000>;

	/* These are relatively safe rise/fall times */
	i2c-scl-falling-time-ns = <50>;
	i2c-scl-rising-time-ns = <300>;

	codec: da7219@1a {
	compatible = "dlg,da7219";
	reg = <0x1a>;
	interrupt-parent = <&gpio1>;
	interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&cru SCLK_I2S_8CH_OUT>;
	clock-names = "mclk";
	dlg,micbias-lvl = <2600>;
	dlg,mic-amp-in-sel = "diff";
	pinctrl-names = "default";
	pinctrl-0 = <&headset_int_l>;
	VDD-supply = <&pp1800>;
	VDDMIC-supply = <&pp3300>;
	VDDIO-supply = <&pp1800>;

	da7219_aad {
	dlg,adc-1bit-rpt = <1>;
	dlg,btn-avg = <4>;
	dlg,btn-cfg = <50>;
	dlg,mic-det-thr = <500>;
	dlg,jack-ins-deb = <20>;
	dlg,jack-det-rate = "32ms_64ms";
	dlg,jack-rem-deb = <1>;

	dlg,a-d-btn-thr = <0xa>;
	dlg,d-b-btn-thr = <0x16>;
	dlg,b-c-btn-thr = <0x21>;
	dlg,c-mic-btn-thr = <0x3E>;
	};
	};
	};

	&i2s0 {
	status = "okay";
	};

	&i2s2 {
	status = "okay";
	};

	&io_domains {
	status = "okay";

	audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */
	bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */
	gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */
	sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */
	};

	&pcie0 {
	status = "okay";

	ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>;
	vpcie3v3-supply = <&pp3300_wifi_bt>;
	vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */
	vpcie0v9-supply = <&pp900_pcie>;

	pci_rootport: pcie@0,0 {
	reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>;
	#address-cells = <3>;
	#size-cells = <2>;
	ranges;
	};
	};

	&pcie_phy {
	status = "okay";
	};

	&pmu_io_domains {
	status = "okay";

	pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */
	};

	&pwm0 {
	status = "okay";
	};

	&pwm1 {
	status = "okay";
	};

	&pwm2 {
	status = "okay";
	};

	&pwm3 {
	status = "okay";
	};

	&sdhci {
	/*
	* Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the
	* same (or nearly the same) performance for all eMMC that are intended
	* to be used.
	*/
	assigned-clock-rates = <150000000>;

	bus-width = <8>;
	mmc-hs400-1_8v;
	mmc-hs400-enhanced-strobe;
	non-removable;
	status = "okay";
	};

	&sdmmc {
	status = "okay";

	/*
	* Note: configure "sdmmc_cd" as card detect even though it's actually
	* hooked to ground. Because we specified "cd-gpios" below dw_mmc
	* should be ignoring card detect anyway. Specifying the pin as
	* sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag)
	* turned on that the system will still make sure the port is
	* configured as SDMMC and not JTAG.
	*/
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio
	&sdmmc_bus4>;

	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
	disable-wp;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	vmmc-supply = <&pp3000_sd_slot>;
	vqmmc-supply = <&ppvar_sd_card_io>;
	};

	&spi1 {
	status = "okay";

	pinctrl-names = "default", "sleep";
	pinctrl-1 = <&spi1_sleep>;

	spiflash@0 {
	compatible = "jedec,spi-nor";
	reg = <0>;

	/* May run faster once verified. */
	spi-max-frequency = <10000000>;
	};
	};

	&spi2 {
	status = "okay";
	};

	&spi5 {
	status = "okay";

	cros_ec: ec@0 {
	compatible = "google,cros-ec-spi";
	reg = <0>;
	interrupt-parent = <&gpio0>;
	interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&ec_ap_int_l>;
	spi-max-frequency = <3000000>;

	i2c_tunnel: i2c-tunnel {
	compatible = "google,cros-ec-i2c-tunnel";
	google,remote-bus = <4>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	- usbc_extcon0: extcon@0 {
	+ usbc_extcon0: extcon0 {
	compatible = "google,extcon-usbc-cros-ec";
	google,usb-port-id = <0>;
	-
	- #extcon-cells = <0>;
	};
	};
	};

	&tsadc {
	status = "okay";

	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
	};

	&tcphy0 {
	status = "okay";
	extcon = <&usbc_extcon0>;
	};

	&u2phy0 {
	status = "okay";
	};

	&u2phy0_host {
	status = "okay";
	};

	&u2phy1_host {
	status = "okay";
	};

	&u2phy0_otg {
	status = "okay";
	};

	&u2phy1_otg {
	status = "okay";
	};

	&uart2 {
	status = "okay";
	};

	&usb_host0_ohci {
	status = "okay";
	};

	&usbdrd3_0 {
	status = "okay";
	extcon = <&usbc_extcon0>;
	};

	&usbdrd_dwc3_0 {
	status = "okay";
	dr_mode = "host";
	};

	&vopb {
	status = "okay";
	};

	&vopb_mmu {
	status = "okay";
	};

	&vopl {
	status = "okay";
	};

	&vopl_mmu {
	status = "okay";
	};

	#include <arm/cros-ec-keyboard.dtsi>
	#include <arm/cros-ec-sbs.dtsi>

	&pinctrl {
	/*
	* pinctrl settings for pins that have no real owners.
	*
	* At the moment settings are identical for S0 and S3, but if we later
	* need to configure things differently for S3 we'll adjust here.
	*/
	pinctrl-names = "default";
	pinctrl-0 = <
	&ap_pwroff /* AP will auto-assert this when in S3 */
	&clk_32k /* This pin is always 32k on gru boards */
	>;

	pcfg_output_low: pcfg-output-low {
	output-low;
	};

	pcfg_output_high: pcfg-output-high {
	output-high;
	};

	pcfg_pull_none_8ma: pcfg-pull-none-8ma {
	bias-disable;
	drive-strength = <8>;
	};

	backlight-enable {
	bl_en: bl-en {
	rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	cros-ec {
	ec_ap_int_l: ec-ap-int-l {
	rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	discrete-regulators {
	sd_io_pwr_en: sd-io-pwr-en {
	rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO
	&pcfg_pull_none>;
	};

	sd_pwr_1800_sel: sd-pwr-1800-sel {
	rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO
	&pcfg_pull_none>;
	};

	sd_slot_pwr_en: sd-slot-pwr-en {
	rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO
	&pcfg_pull_none>;
	};
	};

	codec {
	/* Has external pullup */
	headset_int_l: headset-int-l {
	rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	mic_int: mic-int {
	rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
	};
	};

	max98357a {
	sdmode_en: sdmode-en {
	rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
	};
	};

	pcie {
	pcie_clkreqn_cpm: pci-clkreqn-cpm {
	/*
	* Since our pcie doesn't support ClockPM(CPM), we want
	* to hack this as gpio, so the EP could be able to
	* de-assert it along and make ClockPM(CPM) work.
	*/
	rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	sdmmc {
	/*
	* We run sdmmc at max speed; bump up drive strength.
	* We also have external pulls, so disable the internal ones.
	*/
	sdmmc_bus4: sdmmc-bus4 {
	rockchip,pins =
	<4 RK_PB0 1 &pcfg_pull_none_8ma>,
	<4 RK_PB1 1 &pcfg_pull_none_8ma>,
	<4 RK_PB2 1 &pcfg_pull_none_8ma>,
	<4 RK_PB3 1 &pcfg_pull_none_8ma>;
	};

	sdmmc_clk: sdmmc-clk {
	rockchip,pins =
	<4 RK_PB4 1 &pcfg_pull_none_8ma>;
	};

	sdmmc_cmd: sdmmc-cmd {
	rockchip,pins =
	<4 RK_PB5 1 &pcfg_pull_none_8ma>;
	};

	/*
	* In our case the official card detect is hooked to ground
	* to avoid getting access to JTAG just by sticking something
	* in the SD card slot (see the force_jtag bit in the TRM).
	*
	* We still configure it as card detect because it doesn't
	* hurt and dw_mmc will ignore it. We make sure to disable
	* the pull though so we don't burn needless power.
	*/
	sdmmc_cd: sdmmc-cd {
	rockchip,pins =
	<0 RK_PA7 1 &pcfg_pull_none>;
	};

	/* This is where we actually hook up CD; has external pull */
	sdmmc_cd_gpio: sdmmc-cd-gpio {
	rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	spi1 {
	spi1_sleep: spi1-sleep {
	/*
	* Pull down SPI1 CLK/CS/RX/TX during suspend, to
	* prevent leakage.
	*/
	rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>,
	<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>,
	<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>,
	<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
	};
	};

	touchscreen {
	touch_int_l: touch-int-l {
	rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
	};

	touch_reset_l: touch-reset-l {
	rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	trackpad {
	ap_i2c_tp_pu_en: ap-i2c-tp-pu-en {
	rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>;
	};

	trackpad_int_l: trackpad-int-l {
	rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	wifi: wifi {
	wlan_module_reset_l: wlan-module-reset-l {
	rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	bt_host_wake_l: bt-host-wake-l {
	/* Kevin has an external pull up, but Gru does not */
	rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	write-protect {
	ap_fw_wp: ap-fw-wp {
	rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-hugsun-x99.dts b/sys/gnu/dts/arm64/rockchip/rk3399-hugsun-x99.dts
	index d69a613fb65a..aee484a05181 100644
	--- a/sys/gnu/dts/arm64/rockchip/rk3399-hugsun-x99.dts
	+++ b/sys/gnu/dts/arm64/rockchip/rk3399-hugsun-x99.dts
	@@ -1,731 +1,758 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/dts-v1/;
	#include <dt-bindings/pwm/pwm.h>
	#include <dt-bindings/input/input.h>
	#include "rk3399.dtsi"
	#include "rk3399-opp.dtsi"

	/ {
	model = "Hugsun X99 TV BOX";
	compatible = "hugsun,x99", "rockchip,rk3399";

	chosen {
	stdout-path = "serial2:1500000n8";
	};

	clkin_gmac: external-gmac-clock {
	compatible = "fixed-clock";
	clock-frequency = <125000000>;
	clock-output-names = "clkin_gmac";
	#clock-cells = <0>;
	};

	dc_5v: dc-5v {
	compatible = "regulator-fixed";
	regulator-name = "dc_5v";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	};

	+ ir-receiver {
	+ compatible = "gpio-ir-receiver";
	+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&ir_rx>;
	+ };
	+
	+ leds {
	+ compatible = "gpio-leds";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&power_led_gpio>;
	+
	+ led-0 {
	+ label = "blue:power";
	+ gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
	+ default-state = "on";
	+ linux,default-trigger = "default-on";
	+ };
	+ };
	+
	vcc_sys: vcc-sys {
	compatible = "regulator-fixed";
	regulator-name = "vcc_sys";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	vin-supply = <&dc_5v>;
	};

	vcc_phy: vcc-phy-regulator {
	compatible = "regulator-fixed";
	regulator-name = "vcc_phy";
	regulator-always-on;
	regulator-boot-on;
	};

	vcc1v8_s0: vcc1v8-s0 {
	compatible = "regulator-fixed";
	regulator-name = "vcc1v8_s0";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	vcc3v3_sys: vcc3v3-sys {
	compatible = "regulator-fixed";
	regulator-name = "vcc3v3_sys";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	vin-supply = <&vcc_sys>;
	};

	vcc5v0_host: vcc5v0-host-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&host_vbus_drv>;
	regulator-name = "vcc5v0_host";
	regulator-always-on;
	};

	vcc5v0_typec: vcc5v0-typec-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&vcc5v0_typec_en>;
	regulator-name = "vcc5v0_typec";
	regulator-always-on;
	vin-supply = <&vcc5v0_usb>;
	};

	vcc5v0_usb: vcc5v0-usb {
	compatible = "regulator-fixed";
	regulator-name = "vcc5v0_usb";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&dc_5v>;
	};

	vdd_log: vdd-log {
	compatible = "pwm-regulator";
	pwms = <&pwm2 0 25000 1>;
	pwm-supply = <&vcc_sys>;
	regulator-name = "vdd_log";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1400000>;
	regulator-always-on;
	regulator-boot-on;
	};

	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	clocks = <&rk808 1>;
	clock-names = "ext_clock";
	pinctrl-names = "default";
	pinctrl-0 = <&wifi_reg_on_h>;
	reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
	};

	};

	&cpu_l0 {
	cpu-supply = <&vdd_cpu_l>;
	};

	&cpu_l1 {
	cpu-supply = <&vdd_cpu_l>;
	};

	&cpu_l2 {
	cpu-supply = <&vdd_cpu_l>;
	};

	&cpu_l3 {
	cpu-supply = <&vdd_cpu_l>;
	};

	&cpu_b0 {
	cpu-supply = <&vdd_cpu_b>;
	};

	&cpu_b1 {
	cpu-supply = <&vdd_cpu_b>;
	};

	&emmc_phy {
	status = "okay";
	};

	&gmac {
	assigned-clocks = <&cru SCLK_RMII_SRC>;
	assigned-clock-parents = <&clkin_gmac>;
	clock_in_out = "input";
	phy-supply = <&vcc_phy>;
	phy-mode = "rgmii";
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins>;
	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;
	snps,reset-delays-us = <0 10000 50000>;
	tx_delay = <0x28>;
	rx_delay = <0x11>;
	status = "okay";
	};

	&gpu {
	status = "okay";
	mali-supply = <&vdd_gpu>;
	};

	&hdmi {
	ddc-i2c-bus = <&i2c3>;
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_cec>;
	status = "okay";
	};

	&hdmi_sound {
	status = "okay";
	};

	&i2c0 {
	status = "okay";
	i2c-scl-rising-time-ns = <180>;
	i2c-scl-falling-time-ns = <30>;
	clock-frequency = <400000>;

	vdd_cpu_b: syr827@40 {
	compatible = "silergy,syr827";
	reg = <0x40>;
	regulator-compatible = "fan53555-reg";
	pinctrl-0 = <&vsel1_gpio>;
	regulator-name = "vdd_cpu_b";
	regulator-min-microvolt = <712500>;
	regulator-max-microvolt = <1500000>;
	regulator-ramp-delay = <1000>;
	fcs,suspend-voltage-selector = <1>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vcc_sys>;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_gpu: syr828@41 {
	compatible = "silergy,syr828";
	reg = <0x41>;
	regulator-compatible = "fan53555-reg";
	pinctrl-0 = <&vsel2_gpio>;
	regulator-name = "vdd_gpu";
	regulator-min-microvolt = <712500>;
	regulator-max-microvolt = <1500000>;
	regulator-ramp-delay = <1000>;
	fcs,suspend-voltage-selector = <1>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vcc_sys>;
	regulator-initial-mode = <1>;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	rk808: pmic@1b {
	compatible = "rockchip,rk808";
	reg = <0x1b>;
	interrupt-parent = <&gpio1>;
	interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int_l>;
	rockchip,system-power-controller;
	wakeup-source;
	#clock-cells = <1>;
	clock-output-names = "xin32k", "rtc_clko_wifi";

	vcc1-supply = <&vcc_sys>;
	vcc2-supply = <&vcc_sys>;
	vcc3-supply = <&vcc_sys>;
	vcc4-supply = <&vcc_sys>;
	vcc6-supply = <&vcc_sys>;
	vcc7-supply = <&vcc_sys>;
	vcc8-supply = <&vcc3v3_sys>;
	vcc9-supply = <&vcc_sys>;
	vcc10-supply = <&vcc_sys>;
	vcc11-supply = <&vcc_sys>;
	vcc12-supply = <&vcc3v3_sys>;
	vddio-supply = <&vcc_1v8>;

	regulators {
	vdd_center: DCDC_REG1 {
	regulator-name = "vdd_center";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <900000>;
	regulator-ramp-delay = <6001>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_cpu_l: DCDC_REG2 {
	regulator-name = "vdd_cpu_l";
	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <1350000>;
	regulator-ramp-delay = <6001>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vcc_ddr: DCDC_REG3 {
	regulator-name = "vcc_ddr";
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	vcc_1v8: DCDC_REG4 {
	regulator-name = "vcc_1v8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc1v8_dvp: LDO_REG1 {
	regulator-name = "vcc1v8_dvp";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcca1v8_hdmi: LDO_REG2 {
	regulator-name = "vcca1v8_hdmi";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcca_1v8: LDO_REG3 {
	regulator-name = "vcca_1v8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc_sd: LDO_REG4 {
	regulator-name = "vcc_sd";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3300000>;
	};
	};

	vcc3v0_sd: LDO_REG5 {
	regulator-name = "vcc3v0_sd";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3000000>;
	};
	};

	vcc_1v5: LDO_REG6 {
	regulator-name = "vcc_1v5";
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1500000>;
	};
	};

	vcca0v9_hdmi: LDO_REG7 {
	regulator-name = "vcca0v9_hdmi";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <900000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <900000>;
	};
	};

	vcc_3v0: LDO_REG8 {
	regulator-name = "vcc_3v0";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3000000>;
	};
	};

	vcc3v3_s3: SWITCH_REG1 {
	regulator-name = "vcc3v3_s3";
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	vcc3v3_s0: SWITCH_REG2 {
	regulator-name = "vcc3v3_s0";
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};
	};
	};
	};

	&i2c1 {
	i2c-scl-rising-time-ns = <300>;
	i2c-scl-falling-time-ns = <15>;
	status = "okay";
	};

	&i2c3 {
	i2c-scl-rising-time-ns = <450>;
	i2c-scl-falling-time-ns = <15>;
	status = "okay";
	};

	&i2c4 {
	i2c-scl-rising-time-ns = <600>;
	i2c-scl-falling-time-ns = <40>;
	status = "okay";

	fusb0: typec-portc@22 {
	compatible = "fcs,fusb302";
	reg = <0x22>;
	interrupt-parent = <&gpio1>;
	interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&fusb0_int>;
	vbus-supply = <&vcc5v0_typec>;
	status = "okay";
	};
	};

	&i2c7 {
	status = "okay";
	};

	&i2s0 {
	rockchip,playback-channels = <8>;
	rockchip,capture-channels = <8>;
	status = "okay";
	};

	&i2s1 {
	rockchip,playback-channels = <2>;
	rockchip,capture-channels = <2>;
	status = "okay";
	};

	&i2s2 {
	status = "okay";
	};

	&io_domains {
	status = "okay";
	audio-supply = <&vcc1v8_s0>;
	bt656-supply = <&vcc1v8_s0>;
	gpio1830-supply = <&vcc_3v0>;
	sdmmc-supply = <&vcc_sd>;
	};

	&pmu_io_domains {
	status = "okay";
	pmu1830-supply = <&vcc_1v8>;
	};

	&pinctrl {
	fusb30x {
	fusb0_int: fusb0-int {
	rockchip,pins =
	<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	gmac {
	rgmii_sleep_pins: rgmii-sleep-pins {
	rockchip,pins =
	<3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>;
	};
	};

	+ ir {
	+ ir_rx: ir-rx {
	+ rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>;
	+ };
	+ };
	+
	+ leds {
	+ power_led_gpio: power-led-gpio {
	+ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
	+ };
	+ };
	+
	pmic {
	pmic_int_l: pmic-int-l {
	rockchip,pins =
	<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
	};

	vsel1_gpio: vsel1-gpio {
	rockchip,pins =
	<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
	};

	vsel2_gpio: vsel2-gpio {
	rockchip,pins =
	<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
	};
	};

	sdio {
	bt_host_wake_l: bt-host-wake-l {
	rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	bt_reg_on_h: bt-reg-on-h {
	/* external pullup to VCC1V8_PMUPLL */
	rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	bt_wake_l: bt-wake-l {
	rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	wifi_reg_on_h: wifi-reg_on-h {
	rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	wifi {
	wifi_host_wake_l: wifi-host-wake-l {
	rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	usb-typec {
	vcc5v0_typec_en: vcc5v0_typec_en {
	rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	usb2 {
	host_vbus_drv: host-vbus-drv {
	rockchip,pins =
	<4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};
	};

	-&pwm0 {
	- status = "okay";
	-};
	-
	&pwm2 {
	status = "okay";
	pinctrl-0 = <&pwm2_pin_pull_down>;
	};

	&saradc {
	vref-supply = <&vcc1v8_s0>;
	status = "okay";
	};

	&sdmmc {
	clock-frequency = <150000000>;
	- clock-freq-min-max = <200000 150000000>;
	+ max-frequency = <150000000>;
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	disable-wp;
	vqmmc-supply = <&vcc_sd>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
	card-detect-delay = <800>;
	status = "okay";
	};

	&sdhci {
	bus-width = <8>;
	mmc-hs400-1_8v;
	mmc-hs400-enhanced-strobe;
	non-removable;
	keep-power-in-suspend;
	status = "okay";
	};

	&sdio0 {
	bus-width = <4>;
	clock-frequency = <50000000>;
	cap-sdio-irq;
	cap-sd-highspeed;
	keep-power-in-suspend;
	mmc-pwrseq = <&sdio_pwrseq>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
	sd-uhs-sdr104;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	brcmf: wifi@1 {
	compatible = "brcm,bcm4329-fmac";
	reg = <1>;
	interrupt-parent = <&gpio0>;
	interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
	interrupt-names = "host-wake";
	pinctrl-names = "default";
	pinctrl-0 = <&wifi_host_wake_l>;
	};
	};

	&spdif {
	status = "okay";
	pinctrl-0 = <&spdif_bus_1>;
	#sound-dai-cells = <0>;
	};

	&spi1 {
	status = "okay";
	- max-freq = <10000000>;

	flash@0 {
	compatible = "jedec,spi-nor";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0>;
	spi-max-frequency = <10000000>;
	};
	};

	&tcphy0 {
	status = "okay";
	};

	&tcphy1 {
	status = "okay";
	};

	&tsadc {
	/* tshut mode 0:CRU 1:GPIO */
	rockchip,hw-tshut-mode = <1>;
	/* tshut polarity 0:LOW 1:HIGH */
	rockchip,hw-tshut-polarity = <1>;
	rockchip,hw-tshut-temp = <110000>;
	status = "okay";
	};

	&u2phy0 {
	status = "okay";

	u2phy0_host: host-port {
	phy-supply = <&vcc5v0_typec>;
	status = "okay";
	};

	u2phy0_otg: otg-port {
	status = "okay";
	};
	};

	&u2phy1 {
	status = "okay";

	u2phy1_host: host-port {
	phy-supply = <&vcc5v0_host>;
	status = "okay";
	};

	u2phy1_otg: otg-port {
	status = "okay";
	};
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
	status = "okay";

	bluetooth {
	compatible = "brcm,bcm43438-bt";
	clocks = <&rk808 1>;
	clock-names = "ext_clock";
	device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
	host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
	shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
	max-speed = <4000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;
	vbat-supply = <&vcc3v3_sys>;
	vddio-supply = <&vcc_1v8>;
	};
	};

	&uart2 {
	status = "okay";
	};

	&usb_host0_ehci {
	status = "okay";
	};

	&usb_host0_ohci {
	status = "okay";
	};

	&usb_host1_ehci {
	status = "okay";
	};

	&usb_host1_ohci {
	status = "okay";
	};

	&usbdrd3_0 {
	status = "okay";
	};

	&usbdrd_dwc3_0 {
	status = "okay";
	dr_mode = "host";
	};

	&usbdrd3_1 {
	status = "okay";
	};

	&usbdrd_dwc3_1 {
	status = "okay";
	dr_mode = "host";
	};

	&vopb {
	status = "okay";
	};

	&vopb_mmu {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-orangepi.dts b/sys/gnu/dts/arm64/rockchip/rk3399-orangepi.dts
	index 9c659f3115c8..f9f7246d4d2f 100644
	--- a/sys/gnu/dts/arm64/rockchip/rk3399-orangepi.dts
	+++ b/sys/gnu/dts/arm64/rockchip/rk3399-orangepi.dts
	@@ -1,793 +1,828 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
	*/

	/dts-v1/;

	#include "dt-bindings/pwm/pwm.h"
	#include "dt-bindings/input/input.h"
	#include "rk3399.dtsi"
	#include "rk3399-opp.dtsi"

	/ {
	model = "Orange Pi RK3399 Board";
	compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399";

	chosen {
	stdout-path = "serial2:1500000n8";
	};

	clkin_gmac: external-gmac-clock {
	compatible = "fixed-clock";
	clock-frequency = <125000000>;
	clock-output-names = "clkin_gmac";
	#clock-cells = <0>;
	};

	adc-keys {
	compatible = "adc-keys";
	io-channels = <&saradc 1>;
	io-channel-names = "buttons";
	keyup-threshold-microvolt = <1800000>;
	poll-interval = <100>;

	button-up {
	label = "Volume Up";
	linux,code = <KEY_VOLUMEUP>;
	press-threshold-microvolt = <100000>;
	};

	button-down {
	label = "Volume Down";
	linux,code = <KEY_VOLUMEDOWN>;
	press-threshold-microvolt = <300000>;
	};

	back {
	label = "Back";
	linux,code = <KEY_BACK>;
	press-threshold-microvolt = <985000>;
	};

	menu {
	label = "Menu";
	linux,code = <KEY_MENU>;
	press-threshold-microvolt = <1314000>;
	};
	};

	dc_12v: dc-12v {
	compatible = "regulator-fixed";
	regulator-name = "dc_12v";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	};

	keys: gpio-keys {
	compatible = "gpio-keys";
	autorepeat;

	power {
	debounce-interval = <100>;
	gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
	label = "GPIO Power";
	linux,code = <KEY_POWER>;
	linux,input-type = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pwr_btn>;
	wakeup-source;
	};
	};

	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	clocks = <&rk808 1>;
	clock-names = "ext_clock";
	pinctrl-names = "default";
	pinctrl-0 = <&wifi_reg_on_h>;
	reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
	};

	/* switched by pmic_sleep */
	vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
	compatible = "regulator-fixed";
	regulator-name = "vcc1v8_s3";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	vin-supply = <&vcc_1v8>;
	};

	vcc3v0_sd: vcc3v0-sd {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc0_pwr_h>;
	regulator-boot-on;
	regulator-max-microvolt = <3000000>;
	regulator-min-microvolt = <3000000>;
	regulator-name = "vcc3v0_sd";
	vin-supply = <&vcc3v3_sys>;
	};

	vcc3v3_sys: vcc3v3-sys {
	compatible = "regulator-fixed";
	regulator-name = "vcc3v3_sys";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vcc_sys>;
	};

	vcc5v0_host: vcc5v0-host-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&vcc5v0_host_en>;
	regulator-name = "vcc5v0_host";
	regulator-always-on;
	vin-supply = <&vcc_sys>;
	};

	vbus_typec: vbus-typec-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&vcc5v0_typec_en>;
	regulator-name = "vbus_typec";
	vin-supply = <&vcc_sys>;
	};

	vcc_sys: vcc-sys {
	compatible = "regulator-fixed";
	regulator-name = "vcc_sys";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	vin-supply = <&dc_12v>;
	};

	vdd_log: vdd-log {
	compatible = "pwm-regulator";
	pwms = <&pwm2 0 25000 1>;
	regulator-name = "vdd_log";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <1400000>;
	vin-supply = <&vcc_sys>;
	};
	};

	&cpu_l0 {
	cpu-supply = <&vdd_cpu_l>;
	};

	&cpu_l1 {
	cpu-supply = <&vdd_cpu_l>;
	};

	&cpu_l2 {
	cpu-supply = <&vdd_cpu_l>;
	};

	&cpu_l3 {
	cpu-supply = <&vdd_cpu_l>;
	};

	&cpu_b0 {
	cpu-supply = <&vdd_cpu_b>;
	};

	&cpu_b1 {
	cpu-supply = <&vdd_cpu_b>;
	};

	&emmc_phy {
	status = "okay";
	};

	&gmac {
	assigned-clocks = <&cru SCLK_RMII_SRC>;
	assigned-clock-parents = <&clkin_gmac>;
	clock_in_out = "input";
	phy-supply = <&vcc3v3_s3>;
	phy-mode = "rgmii";
	+ phy-handle = <&rtl8211e>;
	pinctrl-names = "default";
	- pinctrl-0 = <&rgmii_pins>;
	- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
	- snps,reset-active-low;
	- snps,reset-delays-us = <0 10000 50000>;
	+ pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
	tx_delay = <0x28>;
	rx_delay = <0x11>;
	status = "okay";
	+
	+ mdio {
	+ compatible = "snps,dwmac-mdio";
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ rtl8211e: phy@1 {
	+ reg = <1>;
	+ interrupt-parent = <&gpio3>;
	+ interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
	+ reset-assert-us = <10000>;
	+ reset-deassert-us = <30000>;
	+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
	+ };
	+ };
	};

	&gpu {
	mali-supply = <&vdd_gpu>;
	status = "okay";
	};

	&hdmi {
	ddc-i2c-bus = <&i2c3>;
	status = "okay";
	};

	&hdmi_sound {
	status = "okay";
	};

	&i2c0 {
	clock-frequency = <400000>;
	i2c-scl-rising-time-ns = <168>;
	i2c-scl-falling-time-ns = <4>;
	status = "okay";

	rk808: pmic@1b {
	compatible = "rockchip,rk808";
	reg = <0x1b>;
	interrupt-parent = <&gpio1>;
	interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
	#clock-cells = <1>;
	clock-output-names = "rtc_clko_soc", "rtc_clko_wifi";
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int_l>;
	rockchip,system-power-controller;
	wakeup-source;

	vcc1-supply = <&vcc3v3_sys>;
	vcc2-supply = <&vcc3v3_sys>;
	vcc3-supply = <&vcc3v3_sys>;
	vcc4-supply = <&vcc3v3_sys>;
	vcc6-supply = <&vcc3v3_sys>;
	vcc7-supply = <&vcc3v3_sys>;
	vcc8-supply = <&vcc3v3_sys>;
	vcc9-supply = <&vcc3v3_sys>;
	vcc10-supply = <&vcc3v3_sys>;
	vcc11-supply = <&vcc3v3_sys>;
	vcc12-supply = <&vcc3v3_sys>;
	vddio-supply = <&vcc_3v0>;

	regulators {
	vdd_center: DCDC_REG1 {
	regulator-name = "vdd_center";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1500000>;
	regulator-ramp-delay = <6001>;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_cpu_l: DCDC_REG2 {
	regulator-name = "vdd_cpu_l";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1500000>;
	regulator-ramp-delay = <6001>;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vcc_ddr: DCDC_REG3 {
	regulator-name = "vcc_ddr";
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	vcc_1v8: DCDC_REG4 {
	regulator-name = "vcc_1v8";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc1v8_dvp: LDO_REG1 {
	regulator-name = "vcc1v8_dvp";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3400000>;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vcc3v0_tp: LDO_REG2 {
	regulator-name = "vcc3v0_tp";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3400000>;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vcc1v8_pmupll: LDO_REG3 {
	regulator-name = "vcc1v8_pmupll";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <2500000>;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc_sdio: LDO_REG4 {
	regulator-name = "vcc_sdio";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3400000>;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3000000>;
	};
	};

	vcca3v0_codec: LDO_REG5 {
	regulator-name = "vcca3v0_codec";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3400000>;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vcc_1v5: LDO_REG6 {
	regulator-name = "vcc_1v5";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <2500000>;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1500000>;
	};
	};

	vcca1v8_codec: LDO_REG7 {
	regulator-name = "vcca1v8_codec";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <2500000>;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vcc_3v0: LDO_REG8 {
	regulator-name = "vcc_3v0";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3400000>;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3000000>;
	};
	};

	vcc3v3_s3: SWITCH_REG1 {
	regulator-name = "vcc3v3_s3";
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vcc3v3_s0: SWITCH_REG2 {
	regulator-name = "vcc3v3_s0";
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};
	};
	};

	vdd_cpu_b: regulator@40 {
	compatible = "silergy,syr827";
	reg = <0x40>;
	fcs,suspend-voltage-selector = <1>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&cpu_b_sleep>;
	regulator-name = "vdd_cpu_b";
	regulator-min-microvolt = <712500>;
	regulator-max-microvolt = <1500000>;
	regulator-ramp-delay = <1000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vcc3v3_sys>;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_gpu: regulator@41 {
	compatible = "silergy,syr828";
	reg = <0x41>;
	fcs,suspend-voltage-selector = <1>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&gpu_sleep>;
	regulator-name = "vdd_gpu";
	regulator-min-microvolt = <712500>;
	regulator-max-microvolt = <1500000>;
	regulator-ramp-delay = <1000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vcc3v3_sys>;

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};
	};

	&i2c1 {
	i2c-scl-rising-time-ns = <450>;
	i2c-scl-falling-time-ns = <15>;
	status = "okay";
	};

	&i2c3 {
	i2c-scl-rising-time-ns = <450>;
	i2c-scl-falling-time-ns = <15>;
	status = "okay";
	};

	&i2c4 {
	clock-frequency = <400000>;
	i2c-scl-rising-time-ns = <450>;
	i2c-scl-falling-time-ns = <15>;
	status = "okay";

	ak09911@c {
	compatible = "asahi-kasei,ak09911";
	reg = <0x0c>;
	vdd-supply = <&vcc3v3_s3>;
	vid-supply = <&vcc3v3_s3>;
	};

	mpu6500@68 {
	compatible = "invensense,mpu6500";
	reg = <0x68>;
	interrupt-parent = <&gpio1>;
	interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>;
	pinctrl-names = "default";
	pinctrl-0 = <&gsensor_int_l>;
	vddio-supply = <&vcc3v3_s3>;
	};

	lsm6ds3@6a {
	compatible = "st,lsm6ds3";
	reg = <0x6a>;
	interrupt-parent = <&gpio1>;
	interrupts = <RK_PD0 IRQ_TYPE_EDGE_RISING>;
	pinctrl-names = "default";
	pinctrl-0 = <&gyr_int_l>;
	vdd-supply = <&vcc3v3_s3>;
	vddio-supply = <&vcc3v3_s3>;
	};

	cm32181@10 {
	compatible = "capella,cm32181";
	reg = <0x10>;
	interrupt-parent = <&gpio4>;
	interrupts = <RK_PD0 IRQ_TYPE_EDGE_RISING>;
	pinctrl-names = "default";
	pinctrl-0 = <&light_int_l>;
	vdd-supply = <&vcc3v3_s3>;
	};

	fusb302@22 {
	compatible = "fcs,fusb302";
	reg = <0x22>;
	interrupt-parent = <&gpio1>;
	interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&chg_cc_int_l>;
	vbus-supply = <&vbus_typec>;
	};
	};

	&io_domains {
	status = "okay";
	bt656-supply = <&vcc_3v0>;
	audio-supply = <&vcca1v8_codec>;
	sdmmc-supply = <&vcc_sdio>;
	gpio1830-supply = <&vcc_3v0>;
	};

	&pmu_io_domains {
	status = "okay";
	pmu1830-supply = <&vcc_3v0>;
	};

	&pinctrl {
	buttons {
	pwr_btn: pwr-btn {
	rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	+ phy {
	+ phy_intb: phy-intb {
	+ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
	+ };
	+
	+ phy_rstb: phy-rstb {
	+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
	+ };
	+ };
	+
	pmic {
	+ cpu_b_sleep: cpu-b-sleep {
	+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
	+ };
	+
	+ gpu_sleep: gpu-sleep {
	+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
	+ };
	+
	pmic_int_l: pmic-int-l {
	rockchip,pins =
	<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	sd {
	sdmmc0_pwr_h: sdmmc0-pwr-h {
	rockchip,pins =
	<0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	usb2 {
	vcc5v0_host_en: vcc5v0-host-en {
	rockchip,pins =
	<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	vcc5v0_typec_en: vcc5v0-typec-en {
	rockchip,pins =
	<1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	sdio-pwrseq {
	wifi_reg_on_h: wifi-reg-on-h {
	rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	wifi {
	wifi_host_wake_l: wifi-host-wake-l {
	rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	bluetooth {
	bt_reg_on_h: bt-enable-h {
	rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	bt_host_wake_l: bt-host-wake-l {
	rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	bt_wake_l: bt-wake-l {
	rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	mpu6500 {
	gsensor_int_l: gsensor-int-l {
	rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	lsm6ds3 {
	gyr_int_l: gyr-int-l {
	rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	cm32181 {
	light_int_l: light-int-l {
	rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	fusb302 {
	chg_cc_int_l: chg-cc-int-l {
	rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};
	};

	&pwm0 {
	status = "okay";
	};

	&pwm2 {
	status = "okay";
	};

	&saradc {
	vref-supply = <&vcca1v8_s3>;
	status = "okay";
	};

	&sdhci {
	bus-width = <8>;
	mmc-hs400-1_8v;
	mmc-hs400-enhanced-strobe;
	non-removable;
	status = "okay";
	};

	&sdio0 {
	bus-width = <4>;
	cap-sd-highspeed;
	cap-sdio-irq;
	clock-frequency = <50000000>;
	disable-wp;
	keep-power-in-suspend;
	max-frequency = <50000000>;
	mmc-pwrseq = <&sdio_pwrseq>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
	sd-uhs-sdr104;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	brcmf: wifi@1 {
	reg = <1>;
	compatible = "brcm,bcm4329-fmac";
	interrupt-parent = <&gpio0>;
	interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
	interrupt-names = "host-wake";
	pinctrl-names = "default";
	pinctrl-0 = <&wifi_host_wake_l>;
	};
	};

	&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
	clock-frequency = <150000000>;
	disable-wp;
	max-frequency = <150000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
	vmmc-supply = <&vcc3v0_sd>;
	vqmmc-supply = <&vcc_sdio>;
	status = "okay";
	};

	&tcphy0 {
	status = "okay";
	};

	&tcphy1 {
	status = "okay";
	};

	&tsadc {
	rockchip,hw-tshut-mode = <1>;
	rockchip,hw-tshut-polarity = <1>;
	status = "okay";
	};

	&u2phy0 {
	status = "okay";

	u2phy0_otg: otg-port {
	phy-supply = <&vbus_typec>;
	status = "okay";
	};

	u2phy0_host: host-port {
	phy-supply = <&vcc5v0_host>;
	status = "okay";
	};
	};

	&u2phy1 {
	status = "okay";

	u2phy1_otg: otg-port {
	status = "okay";
	};

	u2phy1_host: host-port {
	phy-supply = <&vcc5v0_host>;
	status = "okay";
	};
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
	status = "okay";

	bluetooth {
	compatible = "brcm,bcm43438-bt";
	clocks = <&rk808 1>;
	clock-names = "lpo";
	device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
	host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
	shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>;
	vbat-supply = <&vcc3v3_sys>;
	vddio-supply = <&vcc_1v8>;
	};
	};

	&uart2 {
	status = "okay";
	};

	&usb_host0_ehci {
	status = "okay";
	};

	&usb_host0_ohci {
	status = "okay";
	};

	&usb_host1_ehci {
	status = "okay";
	};

	&usb_host1_ohci {
	status = "okay";
	};

	&usbdrd3_0 {
	status = "okay";
	};

	&usbdrd_dwc3_0 {
	status = "okay";
	dr_mode = "otg";
	};

	&usbdrd3_1 {
	status = "okay";
	};

	&usbdrd_dwc3_1 {
	status = "okay";
	dr_mode = "host";
	};

	&vopb {
	status = "okay";
	};

	&vopb_mmu {
	status = "okay";
	};

	&vopl {
	status = "okay";
	};

	&vopl_mmu {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-pinebook-pro.dts b/sys/gnu/dts/arm64/rockchip/rk3399-pinebook-pro.dts
	new file mode 100644
	index 000000000000..c49982dfd8fc
	--- /dev/null
	+++ b/sys/gnu/dts/arm64/rockchip/rk3399-pinebook-pro.dts
	@@ -0,0 +1,1097 @@
	+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	+/*
	+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
	+ * Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
	+ * Copyright (c) 2020 Tobias Schramm <t.schramm@manjaro.org>
	+ */
	+
	+/dts-v1/;
	+#include <dt-bindings/input/gpio-keys.h>
	+#include <dt-bindings/input/linux-event-codes.h>
	+#include <dt-bindings/pwm/pwm.h>
	+#include <dt-bindings/usb/pd.h>
	+#include <dt-bindings/leds/common.h>
	+#include "rk3399.dtsi"
	+#include "rk3399-opp.dtsi"
	+
	+/ {
	+ model = "Pine64 Pinebook Pro";
	+ compatible = "pine64,pinebook-pro", "rockchip,rk3399";
	+
	+ chosen {
	+ stdout-path = "serial2:1500000n8";
	+ };
	+
	+ backlight: edp-backlight {
	+ compatible = "pwm-backlight";
	+ power-supply = <&vcc_12v>;
	+ pwms = <&pwm0 0 740740 0>;
	+ };
	+
	+ edp_panel: edp-panel {
	+ compatible = "boe,nv140fhmn49";
	+ backlight = <&backlight>;
	+ enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&panel_en_gpio>;
	+ power-supply = <&vcc3v3_panel>;
	+
	+ ports {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ port@0 {
	+ reg = <0>;
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ panel_in_edp: endpoint@0 {
	+ reg = <0>;
	+ remote-endpoint = <&edp_out_panel>;
	+ };
	+ };
	+ };
	+ };
	+
	+ /*
	+ * Use separate nodes for gpio-keys to allow for selective deactivation
	+ * of wakeup sources via sysfs without disabling the whole key
	+ */
	+ gpio-key-lid {
	+ compatible = "gpio-keys";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&lidbtn_gpio>;
	+
	+ lid {
	+ debounce-interval = <20>;
	+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>;
	+ label = "Lid";
	+ linux,code = <SW_LID>;
	+ linux,input-type = <EV_SW>;
	+ wakeup-event-action = <EV_ACT_DEASSERTED>;
	+ wakeup-source;
	+ };
	+ };
	+
	+ gpio-key-power {
	+ compatible = "gpio-keys";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pwrbtn_gpio>;
	+
	+ power {
	+ debounce-interval = <20>;
	+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
	+ label = "Power";
	+ linux,code = <KEY_POWER>;
	+ wakeup-source;
	+ };
	+ };
	+
	+ leds {
	+ compatible = "gpio-leds";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pwrled_gpio &slpled_gpio>;
	+
	+ green-led {
	+ color = <LED_COLOR_ID_GREEN>;
	+ default-state = "on";
	+ function = LED_FUNCTION_POWER;
	+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
	+ label = "green:power";
	+ };
	+
	+ red-led {
	+ color = <LED_COLOR_ID_RED>;
	+ default-state = "off";
	+ function = LED_FUNCTION_STANDBY;
	+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
	+ label = "red:standby";
	+ panic-indicator;
	+ retain-state-suspended;
	+ };
	+ };
	+
	+ /* Power sequence for SDIO WiFi module */
	+ sdio_pwrseq: sdio-pwrseq {
	+ compatible = "mmc-pwrseq-simple";
	+ clocks = <&rk808 1>;
	+ clock-names = "ext_clock";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&wifi_enable_h_gpio>;
	+ post-power-on-delay-ms = <100>;
	+ power-off-delay-us = <500000>;
	+
	+ /* WL_REG_ON on module */
	+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
	+ };
	+
	+ /* Audio components */
	+ es8316-sound {
	+ compatible = "simple-audio-card";
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&hp_det_gpio>;
	+ simple-audio-card,name = "rockchip,es8316-codec";
	+ simple-audio-card,format = "i2s";
	+ simple-audio-card,mclk-fs = <256>;
	+
	+ simple-audio-card,widgets =
	+ "Microphone", "Mic Jack",
	+ "Headphone", "Headphones",
	+ "Speaker", "Speaker";
	+ simple-audio-card,routing =
	+ "MIC1", "Mic Jack",
	+ "Headphones", "HPOL",
	+ "Headphones", "HPOR",
	+ "Speaker Amplifier INL", "HPOL",
	+ "Speaker Amplifier INR", "HPOR",
	+ "Speaker", "Speaker Amplifier OUTL",
	+ "Speaker", "Speaker Amplifier OUTR";
	+
	+ simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
	+ simple-audio-card,aux-devs = <&speaker_amp>;
	+ simple-audio-card,pin-switches = "Speaker";
	+
	+ simple-audio-card,cpu {
	+ sound-dai = <&i2s1>;
	+ };
	+
	+ simple-audio-card,codec {
	+ sound-dai = <&es8316>;
	+ };
	+ };
	+
	+ speaker_amp: speaker-amplifier {
	+ compatible = "simple-audio-amplifier";
	+ enable-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
	+ sound-name-prefix = "Speaker Amplifier";
	+ VCC-supply = <&pa_5v>;
	+ };
	+
	+ /* Power tree */
	+ /* Root power source */
	+ vcc_sysin: vcc-sysin {
	+ compatible = "regulator-fixed";
	+ regulator-name = "vcc_sysin";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ };
	+
	+ /* Regulators supplied by vcc_sysin */
	+ /* LCD backlight supply */
	+ vcc_12v: vcc-12v {
	+ compatible = "regulator-fixed";
	+ regulator-name = "vcc_12v";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-min-microvolt = <12000000>;
	+ regulator-max-microvolt = <12000000>;
	+ vin-supply = <&vcc_sysin>;
	+
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ /* Main 3.3 V supply */
	+ vcc3v3_sys: wifi_bat: vcc3v3-sys {
	+ compatible = "regulator-fixed";
	+ regulator-name = "vcc3v3_sys";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-min-microvolt = <3300000>;
	+ regulator-max-microvolt = <3300000>;
	+ vin-supply = <&vcc_sysin>;
	+
	+ regulator-state-mem {
	+ regulator-on-in-suspend;
	+ };
	+ };
	+
	+ /* 5 V USB power supply */
	+ vcc5v0_usb: pa_5v: vcc5v0-usb-regulator {
	+ compatible = "regulator-fixed";
	+ enable-active-high;
	+ gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pwr_5v_gpio>;
	+ regulator-name = "vcc5v0_usb";
	+ regulator-always-on;
	+ regulator-min-microvolt = <5000000>;
	+ regulator-max-microvolt = <5000000>;
	+ vin-supply = <&vcc_sysin>;
	+
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ /* RK3399 logic supply */
	+ vdd_log: vdd-log {
	+ compatible = "pwm-regulator";
	+ pwms = <&pwm2 0 25000 1>;
	+ regulator-name = "vdd_log";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-min-microvolt = <800000>;
	+ regulator-max-microvolt = <1400000>;
	+ vin-supply = <&vcc_sysin>;
	+
	+ regulator-state-mem {
	+ regulator-on-in-suspend;
	+ };
	+ };
	+
	+ /* Regulators supplied by vcc3v3_sys */
	+ /* 0.9 V supply, always on */
	+ vcc_0v9: vcc-0v9 {
	+ compatible = "regulator-fixed";
	+ regulator-name = "vcc_0v9";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-min-microvolt = <900000>;
	+ regulator-max-microvolt = <900000>;
	+ vin-supply = <&vcc3v3_sys>;
	+ };
	+
	+ /* S3 1.8 V supply, switched by vcc1v8_s3 */
	+ vcca1v8_s3: vcc1v8-s3 {
	+ compatible = "regulator-fixed";
	+ regulator-name = "vcca1v8_s3";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+ vin-supply = <&vcc3v3_sys>;
	+ };
	+
	+ /* micro SD card power */
	+ vcc3v0_sd: vcc3v0-sd {
	+ compatible = "regulator-fixed";
	+ enable-active-high;
	+ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&sdmmc0_pwr_h_gpio>;
	+ regulator-name = "vcc3v0_sd";
	+ regulator-always-on;
	+ regulator-min-microvolt = <3000000>;
	+ regulator-max-microvolt = <3000000>;
	+ vin-supply = <&vcc3v3_sys>;
	+
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ /* LCD panel power, called VCC3V3_S0 in schematic */
	+ vcc3v3_panel: vcc3v3-panel {
	+ compatible = "regulator-fixed";
	+ enable-active-high;
	+ gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&lcdvcc_en_gpio>;
	+ regulator-name = "vcc3v3_panel";
	+ regulator-always-on;
	+ regulator-min-microvolt = <3300000>;
	+ regulator-max-microvolt = <3300000>;
	+ regulator-enable-ramp-delay = <100000>;
	+ vin-supply = <&vcc3v3_sys>;
	+
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ /* M.2 adapter power, switched by vcc1v8_s3 */
	+ vcc3v3_ssd: vcc3v3-ssd {
	+ compatible = "regulator-fixed";
	+ regulator-name = "vcc3v3_ssd";
	+ regulator-min-microvolt = <3300000>;
	+ regulator-max-microvolt = <3300000>;
	+ vin-supply = <&vcc3v3_sys>;
	+ };
	+
	+ /* Regulators supplied by vcc5v0_usb */
	+ /* USB 3 port power supply regulator */
	+ vcc5v0_otg: vcc5v0-otg {
	+ compatible = "regulator-fixed";
	+ enable-active-high;
	+ gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&vcc5v0_host_en_gpio>;
	+ regulator-name = "vcc5v0_otg";
	+ regulator-always-on;
	+ regulator-min-microvolt = <5000000>;
	+ regulator-max-microvolt = <5000000>;
	+ vin-supply = <&vcc5v0_usb>;
	+
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ /* Regulators supplied by vcc5v0_usb */
	+ /* Type C port power supply regulator */
	+ vbus_5vout: vbus_typec: vbus-5vout {
	+ compatible = "regulator-fixed";
	+ enable-active-high;
	+ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&vcc5v0_typec0_en_gpio>;
	+ regulator-name = "vbus_5vout";
	+ regulator-min-microvolt = <5000000>;
	+ regulator-max-microvolt = <5000000>;
	+ vin-supply = <&vcc5v0_usb>;
	+
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ /* Regulators supplied by vcc_1v8 */
	+ /* Primary 0.9 V LDO */
	+ vcca0v9_s3: vcca0v9-s3 {
	+ compatible = "regulator-fixed";
	+ regulator-name = "vcc0v9_s3";
	+ regulator-min-microvolt = <5000000>;
	+ regulator-max-microvolt = <5000000>;
	+ vin-supply = <&vcc_1v8>;
	+
	+ regulator-state-mem {
	+ regulator-on-in-suspend;
	+ };
	+ };
	+
	+ mains_charger: dc-charger {
	+ compatible = "gpio-charger";
	+ charger-type = "mains";
	+ gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>;
	+
	+ /* Also triggered by USB charger */
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&dc_det_gpio>;
	+ };
	+};
	+
	+&cdn_dp {
	+ status = "okay";
	+};
	+
	+&cpu_b0 {
	+ cpu-supply = <&vdd_cpu_b>;
	+};
	+
	+&cpu_b1 {
	+ cpu-supply = <&vdd_cpu_b>;
	+};
	+
	+&cpu_l0 {
	+ cpu-supply = <&vdd_cpu_l>;
	+};
	+
	+&cpu_l1 {
	+ cpu-supply = <&vdd_cpu_l>;
	+};
	+
	+&cpu_l2 {
	+ cpu-supply = <&vdd_cpu_l>;
	+};
	+
	+&cpu_l3 {
	+ cpu-supply = <&vdd_cpu_l>;
	+};
	+
	+&edp {
	+ force-hpd;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&edp_hpd>;
	+ status = "okay";
	+
	+ ports {
	+ edp_out: port@1 {
	+ reg = <1>;
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ edp_out_panel: endpoint@0 {
	+ reg = <0>;
	+ remote-endpoint = <&panel_in_edp>;
	+ };
	+ };
	+ };
	+};
	+
	+&emmc_phy {
	+ status = "okay";
	+};
	+
	+&gpu {
	+ mali-supply = <&vdd_gpu>;
	+ status = "okay";
	+};
	+
	+&hdmi_sound {
	+ status = "okay";
	+};
	+
	+&i2c0 {
	+ clock-frequency = <400000>;
	+ i2c-scl-falling-time-ns = <4>;
	+ i2c-scl-rising-time-ns = <168>;
	+ status = "okay";
	+
	+ rk808: pmic@1b {
	+ compatible = "rockchip,rk808";
	+ reg = <0x1b>;
	+ #clock-cells = <1>;
	+ clock-output-names = "xin32k", "rk808-clkout2";
	+ interrupt-parent = <&gpio3>;
	+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pmic_int_l_gpio>;
	+ rockchip,system-power-controller;
	+ wakeup-source;
	+
	+ vcc1-supply = <&vcc_sysin>;
	+ vcc2-supply = <&vcc_sysin>;
	+ vcc3-supply = <&vcc_sysin>;
	+ vcc4-supply = <&vcc_sysin>;
	+ vcc6-supply = <&vcc_sysin>;
	+ vcc7-supply = <&vcc_sysin>;
	+ vcc8-supply = <&vcc3v3_sys>;
	+ vcc9-supply = <&vcc_sysin>;
	+ vcc10-supply = <&vcc_sysin>;
	+ vcc11-supply = <&vcc_sysin>;
	+ vcc12-supply = <&vcc3v3_sys>;
	+ vcc13-supply = <&vcc_sysin>;
	+ vcc14-supply = <&vcc_sysin>;
	+
	+ regulators {
	+ /* rk3399 center logic supply */
	+ vdd_center: DCDC_REG1 {
	+ regulator-name = "vdd_center";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <1350000>;
	+ regulator-ramp-delay = <6001>;
	+
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ vdd_cpu_l: DCDC_REG2 {
	+ regulator-name = "vdd_cpu_l";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-min-microvolt = <750000>;
	+ regulator-max-microvolt = <1350000>;
	+ regulator-ramp-delay = <6001>;
	+
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ vcc_ddr: DCDC_REG3 {
	+ regulator-name = "vcc_ddr";
	+ regulator-always-on;
	+ regulator-boot-on;
	+
	+ regulator-state-mem {
	+ regulator-on-in-suspend;
	+ };
	+ };
	+
	+ vcc_1v8: vcc_wl: DCDC_REG4 {
	+ regulator-name = "vcc_1v8";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+
	+ regulator-state-mem {
	+ regulator-on-in-suspend;
	+ regulator-suspend-microvolt = <1800000>;
	+ };
	+ };
	+
	+ /* not used */
	+ LDO_REG1 {
	+ };
	+
	+ /* not used */
	+ LDO_REG2 {
	+ };
	+
	+ vcc1v8_pmupll: LDO_REG3 {
	+ regulator-name = "vcc1v8_pmupll";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+
	+ regulator-state-mem {
	+ regulator-on-in-suspend;
	+ regulator-suspend-microvolt = <1800000>;
	+ };
	+ };
	+
	+ vcc_sdio: LDO_REG4 {
	+ regulator-name = "vcc_sdio";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <3000000>;
	+
	+ regulator-state-mem {
	+ regulator-on-in-suspend;
	+ regulator-suspend-microvolt = <3000000>;
	+ };
	+ };
	+
	+ vcca3v0_codec: LDO_REG5 {
	+ regulator-name = "vcca3v0_codec";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-min-microvolt = <3000000>;
	+ regulator-max-microvolt = <3000000>;
	+
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ vcc_1v5: LDO_REG6 {
	+ regulator-name = "vcc_1v5";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-min-microvolt = <1500000>;
	+ regulator-max-microvolt = <1500000>;
	+
	+ regulator-state-mem {
	+ regulator-on-in-suspend;
	+ regulator-suspend-microvolt = <1500000>;
	+ };
	+ };
	+
	+ vcca1v8_codec: LDO_REG7 {
	+ regulator-name = "vcca1v8_codec";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-min-microvolt = <1800000>;
	+ regulator-max-microvolt = <1800000>;
	+
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ vcc_3v0: LDO_REG8 {
	+ regulator-name = "vcc_3v0";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-min-microvolt = <3000000>;
	+ regulator-max-microvolt = <3000000>;
	+
	+ regulator-state-mem {
	+ regulator-on-in-suspend;
	+ regulator-suspend-microvolt = <3000000>;
	+ };
	+ };
	+
	+ vcc3v3_s3: SWITCH_REG1 {
	+ regulator-name = "vcc3v3_s3";
	+ regulator-always-on;
	+ regulator-boot-on;
	+
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ vcc3v3_s0: SWITCH_REG2 {
	+ regulator-name = "vcc3v3_s0";
	+ regulator-always-on;
	+ regulator-boot-on;
	+
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+ };
	+ };
	+
	+ vdd_cpu_b: regulator@40 {
	+ compatible = "silergy,syr827";
	+ reg = <0x40>;
	+ fcs,suspend-voltage-selector = <1>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&vsel1_gpio>;
	+ regulator-name = "vdd_cpu_b";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-min-microvolt = <712500>;
	+ regulator-max-microvolt = <1500000>;
	+ regulator-ramp-delay = <1000>;
	+ vin-supply = <&vcc_1v8>;
	+
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+
	+ vdd_gpu: regulator@41 {
	+ compatible = "silergy,syr828";
	+ reg = <0x41>;
	+ fcs,suspend-voltage-selector = <1>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&vsel2_gpio>;
	+ regulator-name = "vdd_gpu";
	+ regulator-always-on;
	+ regulator-boot-on;
	+ regulator-min-microvolt = <712500>;
	+ regulator-max-microvolt = <1500000>;
	+ regulator-ramp-delay = <1000>;
	+ vin-supply = <&vcc_1v8>;
	+
	+ regulator-state-mem {
	+ regulator-off-in-suspend;
	+ };
	+ };
	+};
	+
	+&i2c1 {
	+ clock-frequency = <100000>;
	+ i2c-scl-falling-time-ns = <4>;
	+ i2c-scl-rising-time-ns = <168>;
	+ status = "okay";
	+
	+ es8316: es8316@11 {
	+ compatible = "everest,es8316";
	+ reg = <0x11>;
	+ clocks = <&cru SCLK_I2S_8CH_OUT>;
	+ clock-names = "mclk";
	+ #sound-dai-cells = <0>;
	+ };
	+};
	+
	+&i2c3 {
	+ i2c-scl-falling-time-ns = <15>;
	+ i2c-scl-rising-time-ns = <450>;
	+ status = "okay";
	+};
	+
	+&i2c4 {
	+ i2c-scl-falling-time-ns = <20>;
	+ i2c-scl-rising-time-ns = <600>;
	+ status = "okay";
	+
	+ fusb0: fusb30x@22 {
	+ compatible = "fcs,fusb302";
	+ reg = <0x22>;
	+ interrupt-parent = <&gpio1>;
	+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&fusb0_int_gpio>;
	+ vbus-supply = <&vbus_typec>;
	+
	+ connector {
	+ compatible = "usb-c-connector";
	+ data-role = "host";
	+ label = "USB-C";
	+ op-sink-microwatt = <1000000>;
	+ power-role = "dual";
	+ sink-pdos =
	+ <PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
	+ source-pdos =
	+ <PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
	+ try-power-role = "sink";
	+
	+ ports {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ port@0 {
	+ reg = <0>;
	+
	+ usbc_hs: endpoint {
	+ remote-endpoint =
	+ <&u2phy0_typec_hs>;
	+ };
	+ };
	+
	+ port@1 {
	+ reg = <1>;
	+
	+ usbc_ss: endpoint {
	+ remote-endpoint =
	+ <&tcphy0_typec_ss>;
	+ };
	+ };
	+
	+ port@2 {
	+ reg = <2>;
	+
	+ usbc_dp: endpoint {
	+ remote-endpoint =
	+ <&tcphy0_typec_dp>;
	+ };
	+ };
	+ };
	+ };
	+ };
	+};
	+
	+&i2s1 {
	+ #sound-dai-cells = <0>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&i2s_8ch_mclk_gpio>, <&i2s1_2ch_bus>;
	+ rockchip,capture-channels = <8>;
	+ rockchip,playback-channels = <8>;
	+ status = "okay";
	+};
	+
	+&io_domains {
	+ audio-supply = <&vcc_3v0>;
	+ gpio1830-supply = <&vcc_3v0>;
	+ sdmmc-supply = <&vcc_sdio>;
	+ status = "okay";
	+};
	+
	+&pcie_phy {
	+ status = "okay";
	+};
	+
	+&pcie0 {
	+ bus-scan-delay-ms = <1000>;
	+ ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
	+ max-link-speed = <2>;
	+ num-lanes = <4>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&pcie_clkreqn_cpm>;
	+ vpcie0v9-supply = <&vcca0v9_s3>;
	+ vpcie1v8-supply = <&vcca1v8_s3>;
	+ vpcie3v3-supply = <&vcc3v3_ssd>;
	+ status = "okay";
	+};
	+
	+&pinctrl {
	+ buttons {
	+ pwrbtn_gpio: pwrbtn-gpio {
	+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
	+ };
	+
	+ lidbtn_gpio: lidbtn-gpio {
	+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
	+ };
	+ };
	+
	+ dc-charger {
	+ dc_det_gpio: dc-det-gpio {
	+ rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
	+ };
	+ };
	+
	+ es8316 {
	+ hp_det_gpio: hp-det-gpio {
	+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
	+ };
	+ };
	+
	+ fusb302x {
	+ fusb0_int_gpio: fusb0-int-gpio {
	+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
	+ };
	+ };
	+
	+ i2s1 {
	+ i2s_8ch_mclk_gpio: i2s-8ch-mclk-gpio {
	+ rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>;
	+ };
	+ };
	+
	+ lcd-panel {
	+ lcdvcc_en_gpio: lcdvcc-en-gpio {
	+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
	+ };
	+
	+ panel_en_gpio: panel-en-gpio {
	+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
	+ };
	+
	+ lcd_panel_reset_gpio: lcd-panel-reset-gpio {
	+ rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
	+ };
	+ };
	+
	+ leds {
	+ pwrled_gpio: pwrled_gpio {
	+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
	+ };
	+
	+ slpled_gpio: slpled_gpio {
	+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
	+ };
	+ };
	+
	+ pmic {
	+ pmic_int_l_gpio: pmic-int-l-gpio {
	+ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
	+ };
	+
	+ vsel1_gpio: vsel1-gpio {
	+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
	+ };
	+
	+ vsel2_gpio: vsel2-gpio {
	+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
	+ };
	+ };
	+
	+ sdcard {
	+ sdmmc0_pwr_h_gpio: sdmmc0-pwr-h-gpio {
	+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
	+ };
	+
	+ };
	+
	+ sdio-pwrseq {
	+ wifi_enable_h_gpio: wifi-enable-h-gpio {
	+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
	+ };
	+ };
	+
	+ usb-typec {
	+ vcc5v0_typec0_en_gpio: vcc5v0-typec0-en-gpio {
	+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
	+ };
	+ };
	+
	+ usb2 {
	+ pwr_5v_gpio: pwr-5v-gpio {
	+ rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
	+ };
	+
	+ vcc5v0_host_en_gpio: vcc5v0-host-en-gpio {
	+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
	+ };
	+ };
	+
	+ wireless-bluetooth {
	+ bt_wake_gpio: bt-wake-gpio {
	+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
	+ };
	+
	+ bt_host_wake_gpio: bt-host-wake-gpio {
	+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
	+ };
	+
	+ bt_reset_gpio: bt-reset-gpio {
	+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
	+ };
	+ };
	+};
	+
	+&pmu_io_domains {
	+ pmu1830-supply = <&vcc_3v0>;
	+ status = "okay";
	+};
	+
	+&pwm0 {
	+ status = "okay";
	+};
	+
	+&pwm2 {
	+ status = "okay";
	+};
	+
	+&saradc {
	+ vref-supply = <&vcca1v8_s3>;
	+ status = "okay";
	+};
	+
	+&sdmmc {
	+ bus-width = <4>;
	+ cap-mmc-highspeed;
	+ cap-sd-highspeed;
	+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
	+ disable-wp;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
	+ sd-uhs-sdr104;
	+ vmmc-supply = <&vcc3v0_sd>;
	+ vqmmc-supply = <&vcc_sdio>;
	+ status = "okay";
	+};
	+
	+&sdio0 {
	+ bus-width = <4>;
	+ cap-sd-highspeed;
	+ cap-sdio-irq;
	+ keep-power-in-suspend;
	+ mmc-pwrseq = <&sdio_pwrseq>;
	+ non-removable;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
	+ sd-uhs-sdr104;
	+ status = "okay";
	+};
	+
	+&sdhci {
	+ bus-width = <8>;
	+ mmc-hs200-1_8v;
	+ non-removable;
	+ status = "okay";
	+};
	+
	+&spi1 {
	+ max-freq = <10000000>;
	+ status = "okay";
	+
	+ spiflash: flash@0 {
	+ compatible = "jedec,spi-nor";
	+ reg = <0>;
	+ m25p,fast-read;
	+ spi-max-frequency = <10000000>;
	+ };
	+};
	+
	+&tcphy0 {
	+ status = "okay";
	+};
	+
	+&tcphy0_dp {
	+ port {
	+ tcphy0_typec_dp: endpoint {
	+ remote-endpoint = <&usbc_dp>;
	+ };
	+ };
	+};
	+
	+&tcphy0_usb3 {
	+ port {
	+ tcphy0_typec_ss: endpoint {
	+ remote-endpoint = <&usbc_ss>;
	+ };
	+ };
	+};
	+
	+&tcphy1 {
	+ status = "okay";
	+};
	+
	+&tsadc {
	+ /* tshut mode 0:CRU 1:GPIO */
	+ rockchip,hw-tshut-mode = <1>;
	+ /* tshut polarity 0:LOW 1:HIGH */
	+ rockchip,hw-tshut-polarity = <1>;
	+ status = "okay";
	+};
	+
	+&u2phy0 {
	+ status = "okay";
	+
	+ u2phy0_otg: otg-port {
	+ status = "okay";
	+ };
	+
	+ u2phy0_host: host-port {
	+ phy-supply = <&vcc5v0_otg>;
	+ status = "okay";
	+ };
	+
	+ port {
	+ u2phy0_typec_hs: endpoint {
	+ remote-endpoint = <&usbc_hs>;
	+ };
	+ };
	+};
	+
	+&u2phy1 {
	+ status = "okay";
	+
	+ u2phy1_otg: otg-port {
	+ status = "okay";
	+ };
	+
	+ u2phy1_host: host-port {
	+ phy-supply = <&vcc5v0_otg>;
	+ status = "okay";
	+ };
	+};
	+
	+&uart0 {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
	+ uart-has-rtscts;
	+ status = "okay";
	+
	+ bluetooth {
	+ compatible = "brcm,bcm4345c5";
	+ clocks = <&rk808 1>;
	+ clock-names = "lpo";
	+ device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
	+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
	+ max-speed = <1500000>;
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&bt_host_wake_gpio &bt_wake_gpio &bt_reset_gpio>;
	+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
	+ vbat-supply = <&wifi_bat>;
	+ vddio-supply = <&vcc_wl>;
	+ };
	+};
	+
	+&uart2 {
	+ status = "okay";
	+};
	+
	+&usb_host0_ehci {
	+ status = "okay";
	+};
	+
	+&usb_host0_ohci {
	+ status = "okay";
	+};
	+
	+&usb_host1_ehci {
	+ status = "okay";
	+};
	+
	+&usb_host1_ohci {
	+ status = "okay";
	+};
	+
	+&usbdrd3_0 {
	+ status = "okay";
	+};
	+
	+&usbdrd_dwc3_0 {
	+ dr_mode = "host";
	+ status = "okay";
	+};
	+
	+&usbdrd3_1 {
	+ status = "okay";
	+};
	+
	+&usbdrd_dwc3_1 {
	+ dr_mode = "host";
	+ status = "okay";
	+};
	+
	+&vopb {
	+ status = "okay";
	+};
	+
	+&vopb_mmu {
	+ status = "okay";
	+};
	+
	+&vopl {
	+ status = "okay";
	+};
	+
	+&vopl_mmu {
	+ status = "okay";
	+};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-puma.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399-puma.dtsi
	index c1edca3872c7..07694b196fdb 100644
	--- a/sys/gnu/dts/arm64/rockchip/rk3399-puma.dtsi
	+++ b/sys/gnu/dts/arm64/rockchip/rk3399-puma.dtsi
	@@ -1,534 +1,534 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
	*/

	#include <dt-bindings/pwm/pwm.h>
	#include "rk3399.dtsi"
	#include "rk3399-opp.dtsi"

	/ {
	leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	pinctrl-0 = <&led_pin_module>;

	module-led {
	label = "module_led";
	gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	panic-indicator;
	};
	};

	/*
	* Overwrite the opp-table for CPUB as this board uses a different
	* regulator (FAN53555) that only allows 10mV steps and therefore
	* can't reach the operation point target voltages from rk3399-opp.dtsi
	*/
	/delete-node/ opp-table1;
	cluster1_opp: opp-table1 {
	compatible = "operating-points-v2";
	opp-shared;

	opp00 {
	opp-hz = /bits/ 64 <408000000>;
	opp-microvolt = <800000>;
	clock-latency-ns = <40000>;
	};
	opp01 {
	opp-hz = /bits/ 64 <600000000>;
	opp-microvolt = <800000>;
	};
	opp02 {
	opp-hz = /bits/ 64 <816000000>;
	opp-microvolt = <830000>;
	opp-suspend;
	};
	opp03 {
	opp-hz = /bits/ 64 <1008000000>;
	opp-microvolt = <880000>;
	};
	opp04 {
	opp-hz = /bits/ 64 <1200000000>;
	opp-microvolt = <950000>;
	};
	opp05 {
	opp-hz = /bits/ 64 <1416000000>;
	opp-microvolt = <1030000>;
	};
	opp06 {
	opp-hz = /bits/ 64 <1608000000>;
	opp-microvolt = <1100000>;
	};
	opp07 {
	opp-hz = /bits/ 64 <1800000000>;
	opp-microvolt = <1200000>;
	};
	opp08 {
	opp-hz = /bits/ 64 <1992000000>;
	opp-microvolt = <1230000>;
	turbo-mode;
	};
	};

	clkin_gmac: external-gmac-clock {
	compatible = "fixed-clock";
	clock-frequency = <125000000>;
	clock-output-names = "clkin_gmac";
	#clock-cells = <0>;
	};

	vcc1v2_phy: vcc1v2-phy {
	compatible = "regulator-fixed";
	regulator-name = "vcc1v2_phy";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	vin-supply = <&vcc5v0_sys>;
	};

	vcc3v3_sys: vcc3v3-sys {
	compatible = "regulator-fixed";
	regulator-name = "vcc3v3_sys";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vcc5v0_sys>;
	};

	vcc5v0_host: vcc5v0-host-regulator {
	compatible = "regulator-fixed";
	gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
	enable-active-low;
	pinctrl-names = "default";
	pinctrl-0 = <&vcc5v0_host_en>;
	regulator-name = "vcc5v0_host";
	regulator-always-on;
	vin-supply = <&vcc5v0_sys>;
	};

	vcc5v0_sys: vcc5v0-sys {
	compatible = "regulator-fixed";
	regulator-name = "vcc5v0_sys";
	regulator-always-on;
	regulator-boot-on;
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	};
	};

	&cpu_b0 {
	cpu-supply = <&vdd_cpu_b>;
	};

	&cpu_b1 {
	cpu-supply = <&vdd_cpu_b>;
	};

	&cpu_l0 {
	cpu-supply = <&vdd_cpu_l>;
	};

	&cpu_l1 {
	cpu-supply = <&vdd_cpu_l>;
	};

	&cpu_l2 {
	cpu-supply = <&vdd_cpu_l>;
	};

	&cpu_l3 {
	cpu-supply = <&vdd_cpu_l>;
	};

	&emmc_phy {
	status = "okay";
	drive-impedance-ohm = <33>;
	};

	&gmac {
	assigned-clocks = <&cru SCLK_RMII_SRC>;
	assigned-clock-parents = <&clkin_gmac>;
	clock_in_out = "input";
	phy-supply = <&vcc1v2_phy>;
	phy-mode = "rgmii";
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins>;
	snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
	snps,reset-active-low;
	snps,reset-delays-us = <0 10000 50000>;
	tx_delay = <0x10>;
	rx_delay = <0x10>;
	status = "okay";
	};

	&gpu {
	mali-supply = <&vdd_gpu>;
	status = "okay";
	};

	&i2c0 {
	status = "okay";
	i2c-scl-rising-time-ns = <168>;
	i2c-scl-falling-time-ns = <4>;
	clock-frequency = <400000>;

	rk808: pmic@1b {
	compatible = "rockchip,rk808";
	reg = <0x1b>;
	interrupt-parent = <&gpio1>;
	interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
	#clock-cells = <1>;
	clock-output-names = "xin32k", "rk808-clkout2";
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int_l>;
	rockchip,system-power-controller;
	wakeup-source;

	vcc1-supply = <&vcc5v0_sys>;
	vcc2-supply = <&vcc5v0_sys>;
	vcc3-supply = <&vcc5v0_sys>;
	vcc4-supply = <&vcc5v0_sys>;
	vcc6-supply = <&vcc5v0_sys>;
	vcc7-supply = <&vcc5v0_sys>;
	vcc8-supply = <&vcc3v3_sys>;
	vcc9-supply = <&vcc5v0_sys>;
	vcc10-supply = <&vcc5v0_sys>;
	vcc11-supply = <&vcc5v0_sys>;
	vcc12-supply = <&vcc3v3_sys>;
	vddio-supply = <&vcc1v8_pmu>;

	regulators {
	vdd_center: DCDC_REG1 {
	regulator-name = "vdd_center";
	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <1350000>;
	regulator-ramp-delay = <6001>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_cpu_l: DCDC_REG2 {
	regulator-name = "vdd_cpu_l";
	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <1350000>;
	regulator-ramp-delay = <6001>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vcc_ddr: DCDC_REG3 {
	regulator-name = "vcc_ddr";
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	vcc_1v8: DCDC_REG4 {
	regulator-name = "vcc_1v8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc_ldo1: LDO_REG1 {
	regulator-name = "vcc_ldo1";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vcc1v8_hdmi: LDO_REG2 {
	regulator-name = "vcc1v8_hdmi";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vcc1v8_pmu: LDO_REG3 {
	regulator-name = "vcc1v8_pmu";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc_sd: LDO_REG4 {
	regulator-name = "vcc_sd";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3000000>;
	};
	};

	vcc_ldo5: LDO_REG5 {
	regulator-name = "vcc_ldo5";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vcc_ldo6: LDO_REG6 {
	regulator-name = "vcc_ldo6";
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1500000>;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vcc0v9_hdmi: LDO_REG7 {
	regulator-name = "vcc0v9_hdmi";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <900000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vcc_efuse: LDO_REG8 {
	regulator-name = "vcc_efuse";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vcc3v3_s3: SWITCH_REG1 {
	regulator-name = "vcc3v3_s3";
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vcc3v3_s0: SWITCH_REG2 {
	regulator-name = "vcc3v3_s0";
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};
	};
	};

	vdd_gpu: regulator@60 {
	compatible = "fcs,fan53555";
	reg = <0x60>;
	fcs,suspend-voltage-selector = <1>;
	regulator-name = "vdd_gpu";
	regulator-min-microvolt = <600000>;
	regulator-max-microvolt = <1230000>;
	regulator-ramp-delay = <1000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vcc5v0_sys>;
	};
	};

	&i2c7 {
	status = "okay";
	clock-frequency = <400000>;

	fan: fan@18 {
	compatible = "ti,amc6821";
	reg = <0x18>;
	#cooling-cells = <2>;
	};

	rtc_twi: rtc@6f {
	compatible = "isil,isl1208";
	reg = <0x6f>;
	};
	};

	&i2c8 {
	status = "okay";
	clock-frequency = <400000>;

	vdd_cpu_b: regulator@60 {
	compatible = "fcs,fan53555";
	reg = <0x60>;
	vin-supply = <&vcc5v0_sys>;
	regulator-name = "vdd_cpu_b";
	regulator-min-microvolt = <600000>;
	regulator-max-microvolt = <1230000>;
	regulator-ramp-delay = <1000>;
	fcs,suspend-voltage-selector = <1>;
	regulator-always-on;
	regulator-boot-on;
	};
	};

	&i2s0 {
	pinctrl-0 = <&i2s0_2ch_bus>;
	rockchip,playback-channels = <2>;
	rockchip,capture-channels = <2>;
	status = "okay";
	};

	/*
	* As Q7 does not specify neither a global nor a RX clock for I2S these
	* signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO.
	* Therefore we have to redefine the i2s0_2ch_bus definition to prevent
	* conflicts.
	*/
	&i2s0_2ch_bus {
	rockchip,pins =
	<3 RK_PD0 1 &pcfg_pull_none>,
	<3 RK_PD2 1 &pcfg_pull_none>,
	<3 RK_PD3 1 &pcfg_pull_none>,
	<3 RK_PD7 1 &pcfg_pull_none>;
	};

	&io_domains {
	status = "okay";
	bt656-supply = <&vcc_1v8>;
	audio-supply = <&vcc_1v8>;
	sdmmc-supply = <&vcc_sd>;
	gpio1830-supply = <&vcc_1v8>;
	};

	&pmu_io_domains {
	status = "okay";
	pmu1830-supply = <&vcc_1v8>;
	};

	&pwm2 {
	status = "okay";
	};

	&pinctrl {
	i2c8 {
	i2c8_xfer_a: i2c8-xfer {
	rockchip,pins =
	<1 RK_PC4 1 &pcfg_pull_up>,
	<1 RK_PC5 1 &pcfg_pull_up>;
	};
	};

	leds {
	led_pin_module: led-module-gpio {
	rockchip,pins =
	<2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	pmic {
	pmic_int_l: pmic-int-l {
	rockchip,pins =
	<1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};

	usb2 {
	vcc5v0_host_en: vcc5v0-host-en {
	rockchip,pins =
	<4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};
	};

	&sdhci {
	bus-width = <8>;
	mmc-hs400-1_8v;
	mmc-hs400-enhanced-strobe;
	non-removable;
	status = "okay";
	};

	&sdmmc {
	- vqmmc = <&vcc_sd>;
	+ vqmmc-supply = <&vcc_sd>;
	};

	&spi1 {
	status = "okay";

	norflash: flash@0 {
	compatible = "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <50000000>;
	};
	};

	&tcphy1 {
	status = "okay";
	};

	&tsadc {
	rockchip,hw-tshut-mode = <1>;
	rockchip,hw-tshut-polarity = <1>;
	status = "okay";
	};

	&u2phy1 {
	status = "okay";

	u2phy1_otg: otg-port {
	status = "okay";
	};

	u2phy1_host: host-port {
	phy-supply = <&vcc5v0_host>;
	status = "okay";
	};
	};

	&usbdrd3_1 {
	status = "okay";
	};

	&usbdrd_dwc3_1 {
	status = "okay";
	dr_mode = "host";
	};

	&usb_host1_ehci {
	status = "okay";
	};

	&usb_host1_ohci {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-rock960.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399-rock960.dtsi
	index b69f0f2cbd67..ba7c75c9f2a1 100644
	--- a/sys/gnu/dts/arm64/rockchip/rk3399-rock960.dtsi
	+++ b/sys/gnu/dts/arm64/rockchip/rk3399-rock960.dtsi
	@@ -1,664 +1,664 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2018 Collabora Ltd.
	* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
	* Copyright (c) 2018 Linaro Ltd.
	*/

	#include "rk3399.dtsi"
	#include "rk3399-opp.dtsi"

	/ {
	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	clocks = <&rk808 1>;
	clock-names = "ext_clock";
	pinctrl-names = "default";
	pinctrl-0 = <&wifi_enable_h>;
	reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
	};

	vcc12v_dcin: vcc12v-dcin {
	compatible = "regulator-fixed";
	regulator-name = "vcc12v_dcin";
	regulator-min-microvolt = <12000000>;
	regulator-max-microvolt = <12000000>;
	regulator-always-on;
	regulator-boot-on;
	};

	vcc1v8_s0: vcc1v8-s0 {
	compatible = "regulator-fixed";
	regulator-name = "vcc1v8_s0";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	vcc5v0_sys: vcc5v0-sys {
	compatible = "regulator-fixed";
	regulator-name = "vcc5v0_sys";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	vin-supply = <&vcc12v_dcin>;
	};

	vcc3v3_sys: vcc3v3-sys {
	compatible = "regulator-fixed";
	regulator-name = "vcc3v3_sys";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	vin-supply = <&vcc5v0_sys>;
	};

	vcc3v3_pcie: vcc3v3-pcie-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	pinctrl-names = "default";
	pinctrl-0 = <&pcie_drv>;
	regulator-boot-on;
	regulator-name = "vcc3v3_pcie";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	vin-supply = <&vcc3v3_sys>;
	};

	vcc5v0_host: vcc5v0-host-regulator {
	compatible = "regulator-fixed";
	enable-active-high;
	pinctrl-names = "default";
	pinctrl-0 = <&host_vbus_drv>;
	regulator-name = "vcc5v0_host";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	regulator-always-on;
	vin-supply = <&vcc5v0_sys>;
	};

	vcc_0v9: vcc-0v9 {
	compatible = "regulator-fixed";
	regulator-name = "vcc_0v9";
	regulator-always-on;
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <900000>;
	vin-supply = <&vcc3v3_sys>;
	};
	};

	&cpu_l0 {
	cpu-supply = <&vdd_cpu_l>;
	};

	&cpu_l1 {
	cpu-supply = <&vdd_cpu_l>;
	};

	&cpu_l2 {
	cpu-supply = <&vdd_cpu_l>;
	};

	&cpu_l3 {
	cpu-supply = <&vdd_cpu_l>;
	};

	&cpu_b0 {
	cpu-supply = <&vdd_cpu_b>;
	};

	&cpu_b1 {
	cpu-supply = <&vdd_cpu_b>;
	};

	&emmc_phy {
	status = "okay";
	};

	&gpu {
	mali-supply = <&vdd_gpu>;
	status = "okay";
	};

	&hdmi {
	ddc-i2c-bus = <&i2c3>;
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_cec>;
	status = "okay";
	};

	&hdmi_sound {
	status = "okay";
	};

	&i2c0 {
	clock-frequency = <400000>;
	i2c-scl-rising-time-ns = <168>;
	i2c-scl-falling-time-ns = <4>;
	status = "okay";

	vdd_cpu_b: regulator@40 {
	compatible = "silergy,syr827";
	reg = <0x40>;
	fcs,suspend-voltage-selector = <1>;
	regulator-name = "vdd_cpu_b";
	regulator-min-microvolt = <712500>;
	regulator-max-microvolt = <1500000>;
	regulator-ramp-delay = <1000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vcc5v0_sys>;
	status = "okay";

	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_gpu: regulator@41 {
	compatible = "silergy,syr828";
	reg = <0x41>;
	fcs,suspend-voltage-selector = <1>;
	regulator-name = "vdd_gpu";
	regulator-min-microvolt = <712500>;
	regulator-max-microvolt = <1500000>;
	regulator-ramp-delay = <1000>;
	regulator-always-on;
	regulator-boot-on;
	vin-supply = <&vcc5v0_sys>;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	rk808: pmic@1b {
	compatible = "rockchip,rk808";
	reg = <0x1b>;
	interrupt-parent = <&gpio1>;
	interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int_l>;
	rockchip,system-power-controller;
	wakeup-source;
	#clock-cells = <1>;
	clock-output-names = "xin32k", "rk808-clkout2";

	vcc1-supply = <&vcc5v0_sys>;
	vcc2-supply = <&vcc5v0_sys>;
	vcc3-supply = <&vcc5v0_sys>;
	vcc4-supply = <&vcc5v0_sys>;
	vcc6-supply = <&vcc5v0_sys>;
	vcc7-supply = <&vcc5v0_sys>;
	vcc8-supply = <&vcc3v3_sys>;
	vcc9-supply = <&vcc5v0_sys>;
	vcc10-supply = <&vcc5v0_sys>;
	vcc11-supply = <&vcc5v0_sys>;
	vcc12-supply = <&vcc3v3_sys>;
	vddio-supply = <&vcc_1v8>;

	regulators {
	vdd_center: DCDC_REG1 {
	regulator-name = "vdd_center";
	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vdd_cpu_l: DCDC_REG2 {
	regulator-name = "vdd_cpu_l";
	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <1350000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-off-in-suspend;
	};
	};

	vcc_ddr: DCDC_REG3 {
	regulator-name = "vcc_ddr";
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	vcc_1v8: DCDC_REG4 {
	regulator-name = "vcc_1v8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc1v8_dvp: LDO_REG1 {
	regulator-name = "vcc1v8_dvp";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcca1v8_hdmi: LDO_REG2 {
	regulator-name = "vcca1v8_hdmi";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcca_1v8: LDO_REG3 {
	regulator-name = "vcca_1v8";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1800000>;
	};
	};

	vcc_sd: LDO_REG4 {
	regulator-name = "vcc_sd";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3300000>;
	};
	};

	vcc3v0_sd: LDO_REG5 {
	regulator-name = "vcc3v0_sd";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3000000>;
	};
	};

	vcc_1v5: LDO_REG6 {
	regulator-name = "vcc_1v5";
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1500000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <1500000>;
	};
	};

	vcca0v9_hdmi: LDO_REG7 {
	regulator-name = "vcca0v9_hdmi";
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <900000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <900000>;
	};
	};

	vcc_3v0: LDO_REG8 {
	regulator-name = "vcc_3v0";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	regulator-suspend-microvolt = <3000000>;
	};
	};

	vcc3v3_s3: SWITCH_REG1 {
	regulator-name = "vcc3v3_s3";
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};

	vcc3v3_s0: SWITCH_REG2 {
	regulator-name = "vcc3v3_s0";
	regulator-always-on;
	regulator-boot-on;
	regulator-state-mem {
	regulator-on-in-suspend;
	};
	};
	};
	};
	};

	&i2c1 {
	status = "okay";
	};

	&i2c2 {
	status = "okay";
	};

	&i2c3 {
	status = "okay";
	};

	&i2c4 {
	status = "okay";
	};

	&i2s2 {
	status = "okay";
	};

	&io_domains {
	bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */
	audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */
	sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
	gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */
	status = "okay";
	};

	&pcie_phy {
	status = "okay";
	};

	&pcie0 {
	num-lanes = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pcie_clkreqn_cpm>;
	vpcie0v9-supply = <&vcc_0v9>;
	vpcie1v8-supply = <&vcca_1v8>;
	vpcie3v3-supply = <&vcc3v3_pcie>;
	status = "okay";
	};

	&pmu_io_domains {
	pmu1830-supply = <&vcc_1v8>;
	status = "okay";
	};

	&pinctrl {
	bt {
	bt_enable_h: bt-enable-h {
	rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	bt_host_wake_l: bt-host-wake-l {
	rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	bt_wake_l: bt-wake-l {
	rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	sdmmc {
	sdmmc_bus1: sdmmc-bus1 {
	rockchip,pins =
	<4 RK_PB0 1 &pcfg_pull_up_8ma>;
	};

	sdmmc_bus4: sdmmc-bus4 {
	rockchip,pins =
	<4 RK_PB0 1 &pcfg_pull_up_8ma>,
	<4 RK_PB1 1 &pcfg_pull_up_8ma>,
	<4 RK_PB2 1 &pcfg_pull_up_8ma>,
	<4 RK_PB3 1 &pcfg_pull_up_8ma>;
	};

	sdmmc_clk: sdmmc-clk {
	rockchip,pins =
	<4 RK_PB4 1 &pcfg_pull_none_18ma>;
	};

	sdmmc_cmd: sdmmc-cmd {
	rockchip,pins =
	<4 RK_PB5 1 &pcfg_pull_up_8ma>;
	};
	};

	sdio0 {
	sdio0_bus4: sdio0-bus4 {
	rockchip,pins =
	<2 RK_PC4 1 &pcfg_pull_up_20ma>,
	<2 RK_PC5 1 &pcfg_pull_up_20ma>,
	<2 RK_PC6 1 &pcfg_pull_up_20ma>,
	<2 RK_PC7 1 &pcfg_pull_up_20ma>;
	};

	sdio0_cmd: sdio0-cmd {
	rockchip,pins =
	<2 RK_PD0 1 &pcfg_pull_up_20ma>;
	};

	sdio0_clk: sdio0-clk {
	rockchip,pins =
	<2 RK_PD1 1 &pcfg_pull_none_20ma>;
	};
	};

	pmic {
	pmic_int_l: pmic-int-l {
	rockchip,pins =
	<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
	};

	vsel1_gpio: vsel1-gpio {
	rockchip,pins =
	<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
	};

	vsel2_gpio: vsel2-gpio {
	rockchip,pins =
	<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
	};
	};

	sdio-pwrseq {
	wifi_enable_h: wifi-enable-h {
	rockchip,pins =
	<0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	wifi {
	wifi_host_wake_l: wifi-host-wake-l {
	rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};
	};

	&pwm2 {
	status = "okay";
	};

	&pwm3 {
	status = "okay";
	};

	&sdio0 {
	bus-width = <4>;
	clock-frequency = <50000000>;
	cap-sdio-irq;
	cap-sd-highspeed;
	keep-power-in-suspend;
	mmc-pwrseq = <&sdio_pwrseq>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
	sd-uhs-sdr104;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	brcmf: wifi@1 {
	compatible = "brcm,bcm4329-fmac";
	reg = <1>;
	interrupt-parent = <&gpio0>;
	interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
	interrupt-names = "host-wake";
	pinctrl-names = "default";
	pinctrl-0 = <&wifi_host_wake_l>;
	};
	};

	&sdhci {
	bus-width = <8>;
	mmc-hs400-1_8v;
	mmc-hs400-enhanced-strobe;
	non-removable;
	status = "okay";
	};

	&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	clock-frequency = <100000000>;
	- clock-freq-min-max = <100000 100000000>;
	+ max-frequency = <100000000>;
	cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
	disable-wp;
	sd-uhs-sdr104;
	vqmmc-supply = <&vcc_sd>;
	card-detect-delay = <800>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
	status = "okay";
	};

	&tsadc {
	rockchip,hw-tshut-mode = <1>;
	rockchip,hw-tshut-polarity = <1>;
	rockchip,hw-tshut-temp = <110000>;
	status = "okay";
	};

	&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
	status = "okay";

	bluetooth {
	compatible = "brcm,bcm43438-bt";
	clocks = <&rk808 1>;
	clock-names = "ext_clock";
	device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
	host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
	shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
	};
	};

	&uart2 {
	status = "okay";
	};

	&tcphy0 {
	status = "okay";
	};

	&tcphy1 {
	status = "okay";
	};

	&u2phy0 {
	status = "okay";
	};

	&u2phy1 {
	status = "okay";
	};

	&u2phy0_host {
	phy-supply = <&vcc5v0_host>;
	status = "okay";
	};

	&u2phy1_host {
	phy-supply = <&vcc5v0_host>;
	status = "okay";
	};

	&u2phy0_otg {
	status = "okay";
	};

	&u2phy1_otg {
	status = "okay";
	};

	&usb_host0_ehci {
	status = "okay";
	};

	&usb_host0_ohci {
	status = "okay";
	};

	&usb_host1_ehci {
	status = "okay";
	};

	&usb_host1_ohci {
	status = "okay";
	};

	&usbdrd3_0 {
	status = "okay";
	};

	&usbdrd_dwc3_0 {
	status = "okay";
	};

	&usbdrd3_1 {
	status = "okay";
	};

	&usbdrd_dwc3_1 {
	status = "okay";
	};

	&vopb {
	status = "okay";
	};

	&vopb_mmu {
	status = "okay";
	};

	&vopl {
	status = "okay";
	};

	&vopl_mmu {
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-sapphire-excavator.dts b/sys/gnu/dts/arm64/rockchip/rk3399-sapphire-excavator.dts
	index b4d8f60b7e44..73e269a8ae0c 100644
	--- a/sys/gnu/dts/arm64/rockchip/rk3399-sapphire-excavator.dts
	+++ b/sys/gnu/dts/arm64/rockchip/rk3399-sapphire-excavator.dts
	@@ -1,236 +1,234 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
	*/

	/dts-v1/;
	#include "rk3399-sapphire.dtsi"

	/ {
	model = "Excavator-RK3399 Board";
	compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";

	adc-keys {
	compatible = "adc-keys";
	io-channels = <&saradc 1>;
	io-channel-names = "buttons";
	keyup-threshold-microvolt = <1800000>;
	poll-interval = <100>;

	button-up {
	label = "Volume Up";
	linux,code = <KEY_VOLUMEUP>;
	press-threshold-microvolt = <100000>;
	};

	button-down {
	label = "Volume Down";
	linux,code = <KEY_VOLUMEDOWN>;
	press-threshold-microvolt = <300000>;
	};

	back {
	label = "Back";
	linux,code = <KEY_BACK>;
	press-threshold-microvolt = <985000>;
	};

	menu {
	label = "Menu";
	linux,code = <KEY_MENU>;
	press-threshold-microvolt = <1314000>;
	};
	};

	backlight: backlight {
	compatible = "pwm-backlight";
	brightness-levels = <
	0 1 2 3 4 5 6 7
	8 9 10 11 12 13 14 15
	16 17 18 19 20 21 22 23
	24 25 26 27 28 29 30 31
	32 33 34 35 36 37 38 39
	40 41 42 43 44 45 46 47
	48 49 50 51 52 53 54 55
	56 57 58 59 60 61 62 63
	64 65 66 67 68 69 70 71
	72 73 74 75 76 77 78 79
	80 81 82 83 84 85 86 87
	88 89 90 91 92 93 94 95
	96 97 98 99 100 101 102 103
	104 105 106 107 108 109 110 111
	112 113 114 115 116 117 118 119
	120 121 122 123 124 125 126 127
	128 129 130 131 132 133 134 135
	136 137 138 139 140 141 142 143
	144 145 146 147 148 149 150 151
	152 153 154 155 156 157 158 159
	160 161 162 163 164 165 166 167
	168 169 170 171 172 173 174 175
	176 177 178 179 180 181 182 183
	184 185 186 187 188 189 190 191
	192 193 194 195 196 197 198 199
	200 201 202 203 204 205 206 207
	208 209 210 211 212 213 214 215
	216 217 218 219 220 221 222 223
	224 225 226 227 228 229 230 231
	232 233 234 235 236 237 238 239
	240 241 242 243 244 245 246 247
	248 249 250 251 252 253 254 255>;
	default-brightness-level = <200>;
	enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
	pwms = <&pwm0 0 25000 0>;
	status = "okay";
	};

	edp_panel: edp-panel {
	compatible ="lg,lp079qx1-sp0v";
	backlight = <&backlight>;
	enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&lcd_panel_reset>;
	power-supply = <&vcc3v3_s0>;

	port {
	panel_in_edp: endpoint {
	remote-endpoint = <&edp_out_panel>;
	};
	};
	};

	rt5651-sound {
	compatible = "simple-audio-card";
	simple-audio-card,name = "realtek,rt5651-codec";
	simple-audio-card,format = "i2s";
	simple-audio-card,mclk-fs = <256>;
	simple-audio-card,widgets =
	"Microphone", "Mic Jack",
	"Headphone", "Headphone Jack";
	simple-audio-card,routing =
	"Mic Jack", "MICBIAS1",
	"IN1P", "Mic Jack",
	"Headphone Jack", "HPOL",
	"Headphone Jack", "HPOR";
	simple-audio-card,cpu {
	sound-dai = <&i2s0>;
	};
	simple-audio-card,codec {
	sound-dai = <&rt5651>;
	};
	};

	sdio_pwrseq: sdio-pwrseq {
	compatible = "mmc-pwrseq-simple";
	clocks = <&rk808 1>;
	clock-names = "ext_clock";
	pinctrl-names = "default";
	pinctrl-0 = <&wifi_enable_h>;

	/*
	* On the module itself this is one of these (depending
	* on the actual card populated):
	* - SDIO_RESET_L_WL_REG_ON
	* - PDN (power down when low)
	*/
	reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
	};
	};

	&edp {
	status = "okay";

	ports {
	edp_out: port@1 {
	reg = <1>;
	#address-cells = <1>;
	#size-cells = <0>;

	edp_out_panel: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&panel_in_edp>;
	};
	};
	};
	};

	&i2c1 {
	i2c-scl-rising-time-ns = <300>;
	i2c-scl-falling-time-ns = <15>;
	status = "okay";

	rt5651: rt5651@1a {
	compatible = "rockchip,rt5651";
	reg = <0x1a>;
	clocks = <&cru SCLK_I2S_8CH_OUT>;
	clock-names = "mclk";
	hp-det-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
	spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
	#sound-dai-cells = <0>;
	};
	};

	&i2c4 {
	i2c-scl-rising-time-ns = <600>;
	i2c-scl-falling-time-ns = <20>;
	status = "okay";

	accelerometer@68 {
	compatible = "invensense,mpu6500";
	reg = <0x68>;
	interrupt-parent = <&gpio1>;
	interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>;
	};
	};

	&i2s0 {
	rockchip,playback-channels = <8>;
	rockchip,capture-channels = <8>;
	status = "okay";
	};

	&pcie_phy {
	status = "okay";
	};

	&pcie0 {
	ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
	num-lanes = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pcie_clkreqn_cpm>;
	status = "okay";
	};

	&pinctrl {
	sdio-pwrseq {
	wifi_enable_h: wifi-enable-h {
	rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	lcd-panel {
	lcd_panel_reset: lcd-panel-reset {
	rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
	};
	};
	};

	&sdio0 {
	bus-width = <4>;
	cap-sd-highspeed;
	cap-sdio-irq;
	clock-frequency = <50000000>;
	keep-power-in-suspend;
	max-frequency = <50000000>;
	mmc-pwrseq = <&sdio_pwrseq>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
	sd-uhs-sdr104;
	status = "okay";
	};

	&spdif {
	- i2c-scl-rising-time-ns = <450>;
	- i2c-scl-falling-time-ns = <15>;
	status = "okay";
	};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3399.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399.dtsi
	index 33cc21fcf4c1..1448f358ed0a 100644
	--- a/sys/gnu/dts/arm64/rockchip/rk3399.dtsi
	+++ b/sys/gnu/dts/arm64/rockchip/rk3399.dtsi
	@@ -1,2664 +1,2655 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
	*/

	#include <dt-bindings/clock/rk3399-cru.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/pinctrl/rockchip.h>
	#include <dt-bindings/power/rk3399-power.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	compatible = "rockchip,rk3399";

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	ethernet0 = &gmac;
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c4 = &i2c4;
	i2c5 = &i2c5;
	i2c6 = &i2c6;
	i2c7 = &i2c7;
	i2c8 = &i2c8;
	serial0 = &uart0;
	serial1 = &uart1;
	serial2 = &uart2;
	serial3 = &uart3;
	serial4 = &uart4;
	};

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	cpu-map {
	cluster0 {
	core0 {
	cpu = <&cpu_l0>;
	};
	core1 {
	cpu = <&cpu_l1>;
	};
	core2 {
	cpu = <&cpu_l2>;
	};
	core3 {
	cpu = <&cpu_l3>;
	};
	};

	cluster1 {
	core0 {
	cpu = <&cpu_b0>;
	};
	core1 {
	cpu = <&cpu_b1>;
	};
	};
	};

	cpu_l0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x0>;
	enable-method = "psci";
	capacity-dmips-mhz = <485>;
	clocks = <&cru ARMCLKL>;
	#cooling-cells = <2>; /* min followed by max */
	dynamic-power-coefficient = <100>;
	cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	};

	cpu_l1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x1>;
	enable-method = "psci";
	capacity-dmips-mhz = <485>;
	clocks = <&cru ARMCLKL>;
	#cooling-cells = <2>; /* min followed by max */
	dynamic-power-coefficient = <100>;
	cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	};

	cpu_l2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x2>;
	enable-method = "psci";
	capacity-dmips-mhz = <485>;
	clocks = <&cru ARMCLKL>;
	#cooling-cells = <2>; /* min followed by max */
	dynamic-power-coefficient = <100>;
	cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	};

	cpu_l3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0 0x3>;
	enable-method = "psci";
	capacity-dmips-mhz = <485>;
	clocks = <&cru ARMCLKL>;
	#cooling-cells = <2>; /* min followed by max */
	dynamic-power-coefficient = <100>;
	cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	};

	cpu_b0: cpu@100 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	reg = <0x0 0x100>;
	enable-method = "psci";
	capacity-dmips-mhz = <1024>;
	clocks = <&cru ARMCLKB>;
	#cooling-cells = <2>; /* min followed by max */
	dynamic-power-coefficient = <436>;
	cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	};

	cpu_b1: cpu@101 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	reg = <0x0 0x101>;
	enable-method = "psci";
	capacity-dmips-mhz = <1024>;
	clocks = <&cru ARMCLKB>;
	#cooling-cells = <2>; /* min followed by max */
	dynamic-power-coefficient = <436>;
	cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	};

	idle-states {
	entry-method = "psci";

	CPU_SLEEP: cpu-sleep {
	compatible = "arm,idle-state";
	local-timer-stop;
	arm,psci-suspend-param = <0x0010000>;
	entry-latency-us = <120>;
	exit-latency-us = <250>;
	min-residency-us = <900>;
	};

	CLUSTER_SLEEP: cluster-sleep {
	compatible = "arm,idle-state";
	local-timer-stop;
	arm,psci-suspend-param = <0x1010000>;
	entry-latency-us = <400>;
	exit-latency-us = <500>;
	min-residency-us = <2000>;
	};
	};
	};

	display-subsystem {
	compatible = "rockchip,display-subsystem";
	ports = <&vopl_out>, <&vopb_out>;
	};

	pmu_a53 {
	compatible = "arm,cortex-a53-pmu";
	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
	};

	pmu_a72 {
	compatible = "arm,cortex-a72-pmu";
	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
	arm,no-tick-in-suspend;
	};

	xin24m: xin24m {
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-output-names = "xin24m";
	#clock-cells = <0>;
	};

	- amba {
	+ amba: bus {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	dmac_bus: dma-controller@ff6d0000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x0 0xff6d0000 0x0 0x4000>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
	<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
	#dma-cells = <1>;
	clocks = <&cru ACLK_DMAC0_PERILP>;
	clock-names = "apb_pclk";
	};

	dmac_peri: dma-controller@ff6e0000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x0 0xff6e0000 0x0 0x4000>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
	#dma-cells = <1>;
	clocks = <&cru ACLK_DMAC1_PERILP>;
	clock-names = "apb_pclk";
	};
	};

	pcie0: pcie@f8000000 {
	compatible = "rockchip,rk3399-pcie";
	reg = <0x0 0xf8000000 0x0 0x2000000>,
	<0x0 0xfd000000 0x0 0x1000000>;
	reg-names = "axi-base", "apb-base";
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	aspm-no-l0s;
	bus-range = <0x0 0x1f>;
	clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
	<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
	clock-names = "aclk", "aclk-perf",
	"hclk", "pm";
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
	interrupt-names = "sys", "legacy", "client";
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0 0 0 1 &pcie0_intc 0>,
	<0 0 0 2 &pcie0_intc 1>,
	<0 0 0 3 &pcie0_intc 2>,
	<0 0 0 4 &pcie0_intc 3>;
	linux,pci-domain = <0>;
	max-link-speed = <1>;
	msi-map = <0x0 &its 0x0 0x1000>;
	phys = <&pcie_phy 0>, <&pcie_phy 1>,
	<&pcie_phy 2>, <&pcie_phy 3>;
	phy-names = "pcie-phy-0", "pcie-phy-1",
	"pcie-phy-2", "pcie-phy-3";
	ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
	0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
	resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
	<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
	<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
	<&cru SRST_A_PCIE>;
	reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
	"pm", "pclk", "aclk";
	status = "disabled";

	pcie0_intc: interrupt-controller {
	interrupt-controller;
	#address-cells = <0>;
	#interrupt-cells = <1>;
	};
	};

	gmac: ethernet@fe300000 {
	compatible = "rockchip,rk3399-gmac";
	reg = <0x0 0xfe300000 0x0 0x10000>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
	interrupt-names = "macirq";
	clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
	<&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
	<&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
	<&cru PCLK_GMAC>;
	clock-names = "stmmaceth", "mac_clk_rx",
	"mac_clk_tx", "clk_mac_ref",
	"clk_mac_refout", "aclk_mac",
	"pclk_mac";
	power-domains = <&power RK3399_PD_GMAC>;
	resets = <&cru SRST_A_GMAC>;
	reset-names = "stmmaceth";
	rockchip,grf = <&grf>;
	+ snps,txpbl = <0x4>;
	status = "disabled";
	};

	sdio0: mmc@fe310000 {
	compatible = "rockchip,rk3399-dw-mshc",
	"rockchip,rk3288-dw-mshc";
	reg = <0x0 0xfe310000 0x0 0x4000>;
	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
	max-frequency = <150000000>;
	clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
	<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	power-domains = <&power RK3399_PD_SDIOAUDIO>;
	resets = <&cru SRST_SDIO0>;
	reset-names = "reset";
	status = "disabled";
	};

	sdmmc: mmc@fe320000 {
	compatible = "rockchip,rk3399-dw-mshc",
	"rockchip,rk3288-dw-mshc";
	reg = <0x0 0xfe320000 0x0 0x4000>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
	max-frequency = <150000000>;
	assigned-clocks = <&cru HCLK_SD>;
	assigned-clock-rates = <200000000>;
	clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
	<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	fifo-depth = <0x100>;
	power-domains = <&power RK3399_PD_SD>;
	resets = <&cru SRST_SDMMC>;
	reset-names = "reset";
	status = "disabled";
	};

	sdhci: sdhci@fe330000 {
	compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
	reg = <0x0 0xfe330000 0x0 0x10000>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
	arasan,soc-ctl-syscon = <&grf>;
	assigned-clocks = <&cru SCLK_EMMC>;
	assigned-clock-rates = <200000000>;
	clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
	clock-names = "clk_xin", "clk_ahb";
	clock-output-names = "emmc_cardclock";
	#clock-cells = <0>;
	phys = <&emmc_phy>;
	phy-names = "phy_arasan";
	power-domains = <&power RK3399_PD_EMMC>;
	disable-cqe-dcmd;
	status = "disabled";
	};

	usb_host0_ehci: usb@fe380000 {
	compatible = "generic-ehci";
	reg = <0x0 0xfe380000 0x0 0x20000>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
	<&u2phy0>;
	- clock-names = "usbhost", "arbiter",
	- "utmi";
	phys = <&u2phy0_host>;
	phy-names = "usb";
	status = "disabled";
	};

	usb_host0_ohci: usb@fe3a0000 {
	compatible = "generic-ohci";
	reg = <0x0 0xfe3a0000 0x0 0x20000>;
	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
	<&u2phy0>;
	- clock-names = "usbhost", "arbiter",
	- "utmi";
	phys = <&u2phy0_host>;
	phy-names = "usb";
	status = "disabled";
	};

	usb_host1_ehci: usb@fe3c0000 {
	compatible = "generic-ehci";
	reg = <0x0 0xfe3c0000 0x0 0x20000>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
	<&u2phy1>;
	- clock-names = "usbhost", "arbiter",
	- "utmi";
	phys = <&u2phy1_host>;
	phy-names = "usb";
	status = "disabled";
	};

	usb_host1_ohci: usb@fe3e0000 {
	compatible = "generic-ohci";
	reg = <0x0 0xfe3e0000 0x0 0x20000>;
	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
	<&u2phy1>;
	- clock-names = "usbhost", "arbiter",
	- "utmi";
	phys = <&u2phy1_host>;
	phy-names = "usb";
	status = "disabled";
	};

	usbdrd3_0: usb@fe800000 {
	compatible = "rockchip,rk3399-dwc3";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
	<&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
	<&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
	clock-names = "ref_clk", "suspend_clk",
	"bus_clk", "aclk_usb3_rksoc_axi_perf",
	"aclk_usb3", "grf_clk";
	resets = <&cru SRST_A_USB3_OTG0>;
	reset-names = "usb3-otg";
	status = "disabled";

	- usbdrd_dwc3_0: dwc3 {
	+ usbdrd_dwc3_0: usb@fe800000 {
	compatible = "snps,dwc3";
	reg = <0x0 0xfe800000 0x0 0x100000>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
	<&cru SCLK_USB3OTG0_SUSPEND>;
	clock-names = "ref", "bus_early", "suspend";
	dr_mode = "otg";
	phys = <&u2phy0_otg>, <&tcphy0_usb3>;
	phy-names = "usb2-phy", "usb3-phy";
	phy_type = "utmi_wide";
	snps,dis_enblslpm_quirk;
	snps,dis-u2-freeclk-exists-quirk;
	snps,dis_u2_susphy_quirk;
	snps,dis-del-phy-power-chg-quirk;
	snps,dis-tx-ipgap-linecheck-quirk;
	power-domains = <&power RK3399_PD_USB3>;
	status = "disabled";
	};
	};

	usbdrd3_1: usb@fe900000 {
	compatible = "rockchip,rk3399-dwc3";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
	<&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
	<&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
	clock-names = "ref_clk", "suspend_clk",
	"bus_clk", "aclk_usb3_rksoc_axi_perf",
	"aclk_usb3", "grf_clk";
	resets = <&cru SRST_A_USB3_OTG1>;
	reset-names = "usb3-otg";
	status = "disabled";

	- usbdrd_dwc3_1: dwc3 {
	+ usbdrd_dwc3_1: usb@fe900000 {
	compatible = "snps,dwc3";
	reg = <0x0 0xfe900000 0x0 0x100000>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
	<&cru SCLK_USB3OTG1_SUSPEND>;
	clock-names = "ref", "bus_early", "suspend";
	dr_mode = "otg";
	phys = <&u2phy1_otg>, <&tcphy1_usb3>;
	phy-names = "usb2-phy", "usb3-phy";
	phy_type = "utmi_wide";
	snps,dis_enblslpm_quirk;
	snps,dis-u2-freeclk-exists-quirk;
	snps,dis_u2_susphy_quirk;
	snps,dis-del-phy-power-chg-quirk;
	snps,dis-tx-ipgap-linecheck-quirk;
	power-domains = <&power RK3399_PD_USB3>;
	status = "disabled";
	};
	};

	cdn_dp: dp@fec00000 {
	compatible = "rockchip,rk3399-cdn-dp";
	reg = <0x0 0xfec00000 0x0 0x100000>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
	assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
	assigned-clock-rates = <100000000>, <200000000>;
	clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
	<&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
	clock-names = "core-clk", "pclk", "spdif", "grf";
	phys = <&tcphy0_dp>, <&tcphy1_dp>;
	power-domains = <&power RK3399_PD_HDCP>;
	resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
	<&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
	reset-names = "spdif", "dptx", "apb", "core";
	rockchip,grf = <&grf>;
	#sound-dai-cells = <1>;
	status = "disabled";

	ports {
	dp_in: port {
	#address-cells = <1>;
	#size-cells = <0>;

	dp_in_vopb: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vopb_out_dp>;
	};

	dp_in_vopl: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vopl_out_dp>;
	};
	};
	};
	};

	gic: interrupt-controller@fee00000 {
	compatible = "arm,gic-v3";
	#interrupt-cells = <4>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	interrupt-controller;

	reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
	<0x0 0xfef00000 0 0xc0000>, /* GICR */
	<0x0 0xfff00000 0 0x10000>, /* GICC */
	<0x0 0xfff10000 0 0x10000>, /* GICH */
	<0x0 0xfff20000 0 0x10000>; /* GICV */
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
	its: interrupt-controller@fee20000 {
	compatible = "arm,gic-v3-its";
	msi-controller;
	#msi-cells = <1>;
	reg = <0x0 0xfee20000 0x0 0x20000>;
	};

	ppi-partitions {
	ppi_cluster0: interrupt-partition-0 {
	affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
	};

	ppi_cluster1: interrupt-partition-1 {
	affinity = <&cpu_b0 &cpu_b1>;
	};
	};
	};

	saradc: saradc@ff100000 {
	compatible = "rockchip,rk3399-saradc";
	reg = <0x0 0xff100000 0x0 0x100>;
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
	#io-channel-cells = <1>;
	clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
	clock-names = "saradc", "apb_pclk";
	resets = <&cru SRST_P_SARADC>;
	reset-names = "saradc-apb";
	status = "disabled";
	};

	i2c1: i2c@ff110000 {
	compatible = "rockchip,rk3399-i2c";
	reg = <0x0 0xff110000 0x0 0x1000>;
	assigned-clocks = <&cru SCLK_I2C1>;
	assigned-clock-rates = <200000000>;
	clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
	clock-names = "i2c", "pclk";
	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c2: i2c@ff120000 {
	compatible = "rockchip,rk3399-i2c";
	reg = <0x0 0xff120000 0x0 0x1000>;
	assigned-clocks = <&cru SCLK_I2C2>;
	assigned-clock-rates = <200000000>;
	clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
	clock-names = "i2c", "pclk";
	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c3: i2c@ff130000 {
	compatible = "rockchip,rk3399-i2c";
	reg = <0x0 0xff130000 0x0 0x1000>;
	assigned-clocks = <&cru SCLK_I2C3>;
	assigned-clock-rates = <200000000>;
	clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
	clock-names = "i2c", "pclk";
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c5: i2c@ff140000 {
	compatible = "rockchip,rk3399-i2c";
	reg = <0x0 0xff140000 0x0 0x1000>;
	assigned-clocks = <&cru SCLK_I2C5>;
	assigned-clock-rates = <200000000>;
	clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
	clock-names = "i2c", "pclk";
	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c5_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c6: i2c@ff150000 {
	compatible = "rockchip,rk3399-i2c";
	reg = <0x0 0xff150000 0x0 0x1000>;
	assigned-clocks = <&cru SCLK_I2C6>;
	assigned-clock-rates = <200000000>;
	clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
	clock-names = "i2c", "pclk";
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c6_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c7: i2c@ff160000 {
	compatible = "rockchip,rk3399-i2c";
	reg = <0x0 0xff160000 0x0 0x1000>;
	assigned-clocks = <&cru SCLK_I2C7>;
	assigned-clock-rates = <200000000>;
	clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
	clock-names = "i2c", "pclk";
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c7_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart0: serial@ff180000 {
	compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff180000 0x0 0x100>;
	clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
	clock-names = "baudclk", "apb_pclk";
	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
	reg-shift = <2>;
	reg-io-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer>;
	status = "disabled";
	};

	uart1: serial@ff190000 {
	compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff190000 0x0 0x100>;
	clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
	clock-names = "baudclk", "apb_pclk";
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
	reg-shift = <2>;
	reg-io-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer>;
	status = "disabled";
	};

	uart2: serial@ff1a0000 {
	compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff1a0000 0x0 0x100>;
	clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
	clock-names = "baudclk", "apb_pclk";
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
	reg-shift = <2>;
	reg-io-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart2c_xfer>;
	status = "disabled";
	};

	uart3: serial@ff1b0000 {
	compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff1b0000 0x0 0x100>;
	clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
	clock-names = "baudclk", "apb_pclk";
	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
	reg-shift = <2>;
	reg-io-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_xfer>;
	status = "disabled";
	};

	spi0: spi@ff1c0000 {
	compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
	reg = <0x0 0xff1c0000 0x0 0x1000>;
	clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
	clock-names = "spiclk", "apb_pclk";
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dmac_peri 10>, <&dmac_peri 11>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi1: spi@ff1d0000 {
	compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
	reg = <0x0 0xff1d0000 0x0 0x1000>;
	clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
	clock-names = "spiclk", "apb_pclk";
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dmac_peri 12>, <&dmac_peri 13>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi2: spi@ff1e0000 {
	compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
	reg = <0x0 0xff1e0000 0x0 0x1000>;
	clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
	clock-names = "spiclk", "apb_pclk";
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dmac_peri 14>, <&dmac_peri 15>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi4: spi@ff1f0000 {
	compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
	reg = <0x0 0xff1f0000 0x0 0x1000>;
	clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
	clock-names = "spiclk", "apb_pclk";
	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dmac_peri 18>, <&dmac_peri 19>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi5: spi@ff200000 {
	compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
	reg = <0x0 0xff200000 0x0 0x1000>;
	clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
	clock-names = "spiclk", "apb_pclk";
	interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dmac_bus 8>, <&dmac_bus 9>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
	power-domains = <&power RK3399_PD_SDIOAUDIO>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	thermal_zones: thermal-zones {
	cpu_thermal: cpu {
	polling-delay-passive = <100>;
	polling-delay = <1000>;

	thermal-sensors = <&tsadc 0>;

	trips {
	cpu_alert0: cpu_alert0 {
	temperature = <70000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu_alert1: cpu_alert1 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	cpu_crit: cpu_crit {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu_alert0>;
	cooling-device =
	<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	map1 {
	trip = <&cpu_alert1>;
	cooling-device =
	<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};

	gpu_thermal: gpu {
	polling-delay-passive = <100>;
	polling-delay = <1000>;

	thermal-sensors = <&tsadc 1>;

	trips {
	gpu_alert0: gpu_alert0 {
	temperature = <75000>;
	hysteresis = <2000>;
	type = "passive";
	};
	gpu_crit: gpu_crit {
	temperature = <95000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&gpu_alert0>;
	cooling-device =
	<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};
	};

	tsadc: tsadc@ff260000 {
	compatible = "rockchip,rk3399-tsadc";
	reg = <0x0 0xff260000 0x0 0x100>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
	assigned-clocks = <&cru SCLK_TSADC>;
	assigned-clock-rates = <750000>;
	clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
	clock-names = "tsadc", "apb_pclk";
	resets = <&cru SRST_TSADC>;
	reset-names = "tsadc-apb";
	rockchip,grf = <&grf>;
	rockchip,hw-tshut-temp = <95000>;
	pinctrl-names = "init", "default", "sleep";
	pinctrl-0 = <&otp_gpio>;
	pinctrl-1 = <&otp_out>;
	pinctrl-2 = <&otp_gpio>;
	#thermal-sensor-cells = <1>;
	status = "disabled";
	};

	qos_emmc: qos@ffa58000 {
	compatible = "syscon";
	reg = <0x0 0xffa58000 0x0 0x20>;
	};

	qos_gmac: qos@ffa5c000 {
	compatible = "syscon";
	reg = <0x0 0xffa5c000 0x0 0x20>;
	};

	qos_pcie: qos@ffa60080 {
	compatible = "syscon";
	reg = <0x0 0xffa60080 0x0 0x20>;
	};

	qos_usb_host0: qos@ffa60100 {
	compatible = "syscon";
	reg = <0x0 0xffa60100 0x0 0x20>;
	};

	qos_usb_host1: qos@ffa60180 {
	compatible = "syscon";
	reg = <0x0 0xffa60180 0x0 0x20>;
	};

	qos_usb_otg0: qos@ffa70000 {
	compatible = "syscon";
	reg = <0x0 0xffa70000 0x0 0x20>;
	};

	qos_usb_otg1: qos@ffa70080 {
	compatible = "syscon";
	reg = <0x0 0xffa70080 0x0 0x20>;
	};

	qos_sd: qos@ffa74000 {
	compatible = "syscon";
	reg = <0x0 0xffa74000 0x0 0x20>;
	};

	qos_sdioaudio: qos@ffa76000 {
	compatible = "syscon";
	reg = <0x0 0xffa76000 0x0 0x20>;
	};

	qos_hdcp: qos@ffa90000 {
	compatible = "syscon";
	reg = <0x0 0xffa90000 0x0 0x20>;
	};

	qos_iep: qos@ffa98000 {
	compatible = "syscon";
	reg = <0x0 0xffa98000 0x0 0x20>;
	};

	qos_isp0_m0: qos@ffaa0000 {
	compatible = "syscon";
	reg = <0x0 0xffaa0000 0x0 0x20>;
	};

	qos_isp0_m1: qos@ffaa0080 {
	compatible = "syscon";
	reg = <0x0 0xffaa0080 0x0 0x20>;
	};

	qos_isp1_m0: qos@ffaa8000 {
	compatible = "syscon";
	reg = <0x0 0xffaa8000 0x0 0x20>;
	};

	qos_isp1_m1: qos@ffaa8080 {
	compatible = "syscon";
	reg = <0x0 0xffaa8080 0x0 0x20>;
	};

	qos_rga_r: qos@ffab0000 {
	compatible = "syscon";
	reg = <0x0 0xffab0000 0x0 0x20>;
	};

	qos_rga_w: qos@ffab0080 {
	compatible = "syscon";
	reg = <0x0 0xffab0080 0x0 0x20>;
	};

	qos_video_m0: qos@ffab8000 {
	compatible = "syscon";
	reg = <0x0 0xffab8000 0x0 0x20>;
	};

	qos_video_m1_r: qos@ffac0000 {
	compatible = "syscon";
	reg = <0x0 0xffac0000 0x0 0x20>;
	};

	qos_video_m1_w: qos@ffac0080 {
	compatible = "syscon";
	reg = <0x0 0xffac0080 0x0 0x20>;
	};

	qos_vop_big_r: qos@ffac8000 {
	compatible = "syscon";
	reg = <0x0 0xffac8000 0x0 0x20>;
	};

	qos_vop_big_w: qos@ffac8080 {
	compatible = "syscon";
	reg = <0x0 0xffac8080 0x0 0x20>;
	};

	qos_vop_little: qos@ffad0000 {
	compatible = "syscon";
	reg = <0x0 0xffad0000 0x0 0x20>;
	};

	qos_perihp: qos@ffad8080 {
	compatible = "syscon";
	reg = <0x0 0xffad8080 0x0 0x20>;
	};

	qos_gpu: qos@ffae0000 {
	compatible = "syscon";
	reg = <0x0 0xffae0000 0x0 0x20>;
	};

	pmu: power-management@ff310000 {
	compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
	reg = <0x0 0xff310000 0x0 0x1000>;

	/*
	* Note: RK3399 supports 6 voltage domains including VD_CORE_L,
	* VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
	* Some of the power domains are grouped together for every
	* voltage domain.
	* The detail contents as below.
	*/
	power: power-controller {
	compatible = "rockchip,rk3399-power-controller";
	#power-domain-cells = <1>;
	#address-cells = <1>;
	#size-cells = <0>;

	/* These power domains are grouped by VD_CENTER */
	pd_iep@RK3399_PD_IEP {
	reg = <RK3399_PD_IEP>;
	clocks = <&cru ACLK_IEP>,
	<&cru HCLK_IEP>;
	pm_qos = <&qos_iep>;
	};
	pd_rga@RK3399_PD_RGA {
	reg = <RK3399_PD_RGA>;
	clocks = <&cru ACLK_RGA>,
	<&cru HCLK_RGA>;
	pm_qos = <&qos_rga_r>,
	<&qos_rga_w>;
	};
	pd_vcodec@RK3399_PD_VCODEC {
	reg = <RK3399_PD_VCODEC>;
	clocks = <&cru ACLK_VCODEC>,
	<&cru HCLK_VCODEC>;
	pm_qos = <&qos_video_m0>;
	};
	pd_vdu@RK3399_PD_VDU {
	reg = <RK3399_PD_VDU>;
	clocks = <&cru ACLK_VDU>,
	<&cru HCLK_VDU>;
	pm_qos = <&qos_video_m1_r>,
	<&qos_video_m1_w>;
	};

	/* These power domains are grouped by VD_GPU */
	pd_gpu@RK3399_PD_GPU {
	reg = <RK3399_PD_GPU>;
	clocks = <&cru ACLK_GPU>;
	pm_qos = <&qos_gpu>;
	};

	/* These power domains are grouped by VD_LOGIC */
	pd_edp@RK3399_PD_EDP {
	reg = <RK3399_PD_EDP>;
	clocks = <&cru PCLK_EDP_CTRL>;
	};
	pd_emmc@RK3399_PD_EMMC {
	reg = <RK3399_PD_EMMC>;
	clocks = <&cru ACLK_EMMC>;
	pm_qos = <&qos_emmc>;
	};
	pd_gmac@RK3399_PD_GMAC {
	reg = <RK3399_PD_GMAC>;
	clocks = <&cru ACLK_GMAC>,
	<&cru PCLK_GMAC>;
	pm_qos = <&qos_gmac>;
	};
	pd_sd@RK3399_PD_SD {
	reg = <RK3399_PD_SD>;
	clocks = <&cru HCLK_SDMMC>,
	<&cru SCLK_SDMMC>;
	pm_qos = <&qos_sd>;
	};
	pd_sdioaudio@RK3399_PD_SDIOAUDIO {
	reg = <RK3399_PD_SDIOAUDIO>;
	clocks = <&cru HCLK_SDIO>;
	pm_qos = <&qos_sdioaudio>;
	};
	pd_usb3@RK3399_PD_USB3 {
	reg = <RK3399_PD_USB3>;
	clocks = <&cru ACLK_USB3>;
	pm_qos = <&qos_usb_otg0>,
	<&qos_usb_otg1>;
	};
	pd_vio@RK3399_PD_VIO {
	reg = <RK3399_PD_VIO>;
	#address-cells = <1>;
	#size-cells = <0>;

	pd_hdcp@RK3399_PD_HDCP {
	reg = <RK3399_PD_HDCP>;
	clocks = <&cru ACLK_HDCP>,
	<&cru HCLK_HDCP>,
	<&cru PCLK_HDCP>;
	pm_qos = <&qos_hdcp>;
	};
	pd_isp0@RK3399_PD_ISP0 {
	reg = <RK3399_PD_ISP0>;
	clocks = <&cru ACLK_ISP0>,
	<&cru HCLK_ISP0>;
	pm_qos = <&qos_isp0_m0>,
	<&qos_isp0_m1>;
	};
	pd_isp1@RK3399_PD_ISP1 {
	reg = <RK3399_PD_ISP1>;
	clocks = <&cru ACLK_ISP1>,
	<&cru HCLK_ISP1>;
	pm_qos = <&qos_isp1_m0>,
	<&qos_isp1_m1>;
	};
	pd_tcpc0@RK3399_PD_TCPC0 {
	reg = <RK3399_PD_TCPD0>;
	clocks = <&cru SCLK_UPHY0_TCPDCORE>,
	<&cru SCLK_UPHY0_TCPDPHY_REF>;
	};
	pd_tcpc1@RK3399_PD_TCPC1 {
	reg = <RK3399_PD_TCPD1>;
	clocks = <&cru SCLK_UPHY1_TCPDCORE>,
	<&cru SCLK_UPHY1_TCPDPHY_REF>;
	};
	pd_vo@RK3399_PD_VO {
	reg = <RK3399_PD_VO>;
	#address-cells = <1>;
	#size-cells = <0>;

	pd_vopb@RK3399_PD_VOPB {
	reg = <RK3399_PD_VOPB>;
	clocks = <&cru ACLK_VOP0>,
	<&cru HCLK_VOP0>;
	pm_qos = <&qos_vop_big_r>,
	<&qos_vop_big_w>;
	};
	pd_vopl@RK3399_PD_VOPL {
	reg = <RK3399_PD_VOPL>;
	clocks = <&cru ACLK_VOP1>,
	<&cru HCLK_VOP1>;
	pm_qos = <&qos_vop_little>;
	};
	};
	};
	};
	};

	pmugrf: syscon@ff320000 {
	compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
	reg = <0x0 0xff320000 0x0 0x1000>;
	- #address-cells = <1>;
	- #size-cells = <1>;

	pmu_io_domains: io-domains {
	compatible = "rockchip,rk3399-pmu-io-voltage-domain";
	status = "disabled";
	};
	};

	spi3: spi@ff350000 {
	compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
	reg = <0x0 0xff350000 0x0 0x1000>;
	clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
	clock-names = "spiclk", "apb_pclk";
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	uart4: serial@ff370000 {
	compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
	reg = <0x0 0xff370000 0x0 0x100>;
	clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
	clock-names = "baudclk", "apb_pclk";
	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
	reg-shift = <2>;
	reg-io-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_xfer>;
	status = "disabled";
	};

	i2c0: i2c@ff3c0000 {
	compatible = "rockchip,rk3399-i2c";
	reg = <0x0 0xff3c0000 0x0 0x1000>;
	assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
	assigned-clock-rates = <200000000>;
	clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
	clock-names = "i2c", "pclk";
	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c4: i2c@ff3d0000 {
	compatible = "rockchip,rk3399-i2c";
	reg = <0x0 0xff3d0000 0x0 0x1000>;
	assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
	assigned-clock-rates = <200000000>;
	clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
	clock-names = "i2c", "pclk";
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c8: i2c@ff3e0000 {
	compatible = "rockchip,rk3399-i2c";
	reg = <0x0 0xff3e0000 0x0 0x1000>;
	assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
	assigned-clock-rates = <200000000>;
	clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
	clock-names = "i2c", "pclk";
	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c8_xfer>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	pwm0: pwm@ff420000 {
	compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
	reg = <0x0 0xff420000 0x0 0x10>;
	#pwm-cells = <3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_pin>;
	clocks = <&pmucru PCLK_RKPWM_PMU>;
	clock-names = "pwm";
	status = "disabled";
	};

	pwm1: pwm@ff420010 {
	compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
	reg = <0x0 0xff420010 0x0 0x10>;
	#pwm-cells = <3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_pin>;
	clocks = <&pmucru PCLK_RKPWM_PMU>;
	clock-names = "pwm";
	status = "disabled";
	};

	pwm2: pwm@ff420020 {
	compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
	reg = <0x0 0xff420020 0x0 0x10>;
	#pwm-cells = <3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_pin>;
	clocks = <&pmucru PCLK_RKPWM_PMU>;
	clock-names = "pwm";
	status = "disabled";
	};

	pwm3: pwm@ff420030 {
	compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
	reg = <0x0 0xff420030 0x0 0x10>;
	#pwm-cells = <3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3a_pin>;
	clocks = <&pmucru PCLK_RKPWM_PMU>;
	clock-names = "pwm";
	status = "disabled";
	};

	vpu: video-codec@ff650000 {
	compatible = "rockchip,rk3399-vpu";
	reg = <0x0 0xff650000 0x0 0x800>;
	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
	<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
	interrupt-names = "vepu", "vdpu";
	clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
	clock-names = "aclk", "hclk";
	iommus = <&vpu_mmu>;
	power-domains = <&power RK3399_PD_VCODEC>;
	};

	vpu_mmu: iommu@ff650800 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff650800 0x0 0x40>;
	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
	interrupt-names = "vpu_mmu";
	clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	power-domains = <&power RK3399_PD_VCODEC>;
	};

	vdec_mmu: iommu@ff660480 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
	interrupt-names = "vdec_mmu";
	clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	status = "disabled";
	};

	iep_mmu: iommu@ff670800 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff670800 0x0 0x40>;
	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
	interrupt-names = "iep_mmu";
	clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	status = "disabled";
	};

	rga: rga@ff680000 {
	compatible = "rockchip,rk3399-rga";
	reg = <0x0 0xff680000 0x0 0x10000>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
	clock-names = "aclk", "hclk", "sclk";
	resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
	reset-names = "core", "axi", "ahb";
	power-domains = <&power RK3399_PD_RGA>;
	};

	efuse0: efuse@ff690000 {
	compatible = "rockchip,rk3399-efuse";
	reg = <0x0 0xff690000 0x0 0x80>;
	#address-cells = <1>;
	#size-cells = <1>;
	clocks = <&cru PCLK_EFUSE1024NS>;
	clock-names = "pclk_efuse";

	/* Data cells */
	cpu_id: cpu-id@7 {
	reg = <0x07 0x10>;
	};
	cpub_leakage: cpu-leakage@17 {
	reg = <0x17 0x1>;
	};
	gpu_leakage: gpu-leakage@18 {
	reg = <0x18 0x1>;
	};
	center_leakage: center-leakage@19 {
	reg = <0x19 0x1>;
	};
	cpul_leakage: cpu-leakage@1a {
	reg = <0x1a 0x1>;
	};
	logic_leakage: logic-leakage@1b {
	reg = <0x1b 0x1>;
	};
	wafer_info: wafer-info@1c {
	reg = <0x1c 0x1>;
	};
	};

	pmucru: pmu-clock-controller@ff750000 {
	compatible = "rockchip,rk3399-pmucru";
	reg = <0x0 0xff750000 0x0 0x1000>;
	rockchip,grf = <&pmugrf>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	assigned-clocks = <&pmucru PLL_PPLL>;
	assigned-clock-rates = <676000000>;
	};

	cru: clock-controller@ff760000 {
	compatible = "rockchip,rk3399-cru";
	reg = <0x0 0xff760000 0x0 0x1000>;
	rockchip,grf = <&grf>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	assigned-clocks =
	<&cru PLL_GPLL>, <&cru PLL_CPLL>,
	<&cru PLL_NPLL>,
	<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
	<&cru PCLK_PERIHP>,
	<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
	<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
	<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
	<&cru ACLK_VIO>, <&cru ACLK_HDCP>,
	<&cru ACLK_GIC_PRE>,
	<&cru PCLK_DDR>;
	assigned-clock-rates =
	<594000000>, <800000000>,
	<1000000000>,
	<150000000>, <75000000>,
	<37500000>,
	<100000000>, <100000000>,
	<50000000>, <600000000>,
	<100000000>, <50000000>,
	<400000000>, <400000000>,
	<200000000>,
	<200000000>;
	};

	grf: syscon@ff770000 {
	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
	reg = <0x0 0xff770000 0x0 0x10000>;
	#address-cells = <1>;
	#size-cells = <1>;

	io_domains: io-domains {
	compatible = "rockchip,rk3399-io-voltage-domain";
	status = "disabled";
	};

	u2phy0: usb2-phy@e450 {
	compatible = "rockchip,rk3399-usb2phy";
	reg = <0xe450 0x10>;
	clocks = <&cru SCLK_USB2PHY0_REF>;
	clock-names = "phyclk";
	#clock-cells = <0>;
	clock-output-names = "clk_usbphy0_480m";
	status = "disabled";

	u2phy0_host: host-port {
	#phy-cells = <0>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
	interrupt-names = "linestate";
	status = "disabled";
	};

	u2phy0_otg: otg-port {
	#phy-cells = <0>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
	<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
	<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
	interrupt-names = "otg-bvalid", "otg-id",
	"linestate";
	status = "disabled";
	};
	};

	u2phy1: usb2-phy@e460 {
	compatible = "rockchip,rk3399-usb2phy";
	reg = <0xe460 0x10>;
	clocks = <&cru SCLK_USB2PHY1_REF>;
	clock-names = "phyclk";
	#clock-cells = <0>;
	clock-output-names = "clk_usbphy1_480m";
	status = "disabled";

	u2phy1_host: host-port {
	#phy-cells = <0>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
	interrupt-names = "linestate";
	status = "disabled";
	};

	u2phy1_otg: otg-port {
	#phy-cells = <0>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
	interrupt-names = "otg-bvalid", "otg-id",
	"linestate";
	status = "disabled";
	};
	};

	emmc_phy: phy@f780 {
	compatible = "rockchip,rk3399-emmc-phy";
	reg = <0xf780 0x24>;
	clocks = <&sdhci>;
	clock-names = "emmcclk";
	#phy-cells = <0>;
	status = "disabled";
	};

	pcie_phy: pcie-phy {
	compatible = "rockchip,rk3399-pcie-phy";
	clocks = <&cru SCLK_PCIEPHY_REF>;
	clock-names = "refclk";
	#phy-cells = <1>;
	resets = <&cru SRST_PCIEPHY>;
	drive-impedance-ohm = <50>;
	reset-names = "phy";
	status = "disabled";
	};
	};

	tcphy0: phy@ff7c0000 {
	compatible = "rockchip,rk3399-typec-phy";
	reg = <0x0 0xff7c0000 0x0 0x40000>;
	clocks = <&cru SCLK_UPHY0_TCPDCORE>,
	<&cru SCLK_UPHY0_TCPDPHY_REF>;
	clock-names = "tcpdcore", "tcpdphy-ref";
	assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
	assigned-clock-rates = <50000000>;
	power-domains = <&power RK3399_PD_TCPD0>;
	resets = <&cru SRST_UPHY0>,
	<&cru SRST_UPHY0_PIPE_L00>,
	<&cru SRST_P_UPHY0_TCPHY>;
	reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
	rockchip,grf = <&grf>;
	status = "disabled";

	tcphy0_dp: dp-port {
	#phy-cells = <0>;
	};

	tcphy0_usb3: usb3-port {
	#phy-cells = <0>;
	};
	};

	tcphy1: phy@ff800000 {
	compatible = "rockchip,rk3399-typec-phy";
	reg = <0x0 0xff800000 0x0 0x40000>;
	clocks = <&cru SCLK_UPHY1_TCPDCORE>,
	<&cru SCLK_UPHY1_TCPDPHY_REF>;
	clock-names = "tcpdcore", "tcpdphy-ref";
	assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
	assigned-clock-rates = <50000000>;
	power-domains = <&power RK3399_PD_TCPD1>;
	resets = <&cru SRST_UPHY1>,
	<&cru SRST_UPHY1_PIPE_L00>,
	<&cru SRST_P_UPHY1_TCPHY>;
	reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
	rockchip,grf = <&grf>;
	status = "disabled";

	tcphy1_dp: dp-port {
	#phy-cells = <0>;
	};

	tcphy1_usb3: usb3-port {
	#phy-cells = <0>;
	};
	};

	watchdog@ff848000 {
	compatible = "snps,dw-wdt";
	reg = <0x0 0xff848000 0x0 0x100>;
	clocks = <&cru PCLK_WDT>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
	};

	rktimer: rktimer@ff850000 {
	compatible = "rockchip,rk3399-timer";
	reg = <0x0 0xff850000 0x0 0x1000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
	clock-names = "pclk", "timer";
	};

	spdif: spdif@ff870000 {
	compatible = "rockchip,rk3399-spdif";
	reg = <0x0 0xff870000 0x0 0x1000>;
	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dmac_bus 7>;
	dma-names = "tx";
	clock-names = "mclk", "hclk";
	clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
	pinctrl-names = "default";
	pinctrl-0 = <&spdif_bus>;
	power-domains = <&power RK3399_PD_SDIOAUDIO>;
	#sound-dai-cells = <0>;
	status = "disabled";
	};

	i2s0: i2s@ff880000 {
	compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
	reg = <0x0 0xff880000 0x0 0x1000>;
	rockchip,grf = <&grf>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dmac_bus 0>, <&dmac_bus 1>;
	dma-names = "tx", "rx";
	clock-names = "i2s_clk", "i2s_hclk";
	clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2s0_8ch_bus>;
	power-domains = <&power RK3399_PD_SDIOAUDIO>;
	#sound-dai-cells = <0>;
	status = "disabled";
	};

	i2s1: i2s@ff890000 {
	compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
	reg = <0x0 0xff890000 0x0 0x1000>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dmac_bus 2>, <&dmac_bus 3>;
	dma-names = "tx", "rx";
	clock-names = "i2s_clk", "i2s_hclk";
	clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2s1_2ch_bus>;
	power-domains = <&power RK3399_PD_SDIOAUDIO>;
	#sound-dai-cells = <0>;
	status = "disabled";
	};

	i2s2: i2s@ff8a0000 {
	compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
	reg = <0x0 0xff8a0000 0x0 0x1000>;
	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
	dmas = <&dmac_bus 4>, <&dmac_bus 5>;
	dma-names = "tx", "rx";
	clock-names = "i2s_clk", "i2s_hclk";
	clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
	power-domains = <&power RK3399_PD_SDIOAUDIO>;
	#sound-dai-cells = <0>;
	status = "disabled";
	};

	vopl: vop@ff8f0000 {
	compatible = "rockchip,rk3399-vop-lit";
	reg = <0x0 0xff8f0000 0x0 0x3efc>;
	interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
	assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
	assigned-clock-rates = <400000000>, <100000000>;
	clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	iommus = <&vopl_mmu>;
	power-domains = <&power RK3399_PD_VOPL>;
	resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
	reset-names = "axi", "ahb", "dclk";
	status = "disabled";

	vopl_out: port {
	#address-cells = <1>;
	#size-cells = <0>;

	vopl_out_mipi: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&mipi_in_vopl>;
	};

	vopl_out_edp: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&edp_in_vopl>;
	};

	vopl_out_hdmi: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&hdmi_in_vopl>;
	};

	vopl_out_mipi1: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&mipi1_in_vopl>;
	};

	vopl_out_dp: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&dp_in_vopl>;
	};
	};
	};

	vopl_mmu: iommu@ff8f3f00 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff8f3f00 0x0 0x100>;
	interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
	interrupt-names = "vopl_mmu";
	clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
	clock-names = "aclk", "iface";
	power-domains = <&power RK3399_PD_VOPL>;
	#iommu-cells = <0>;
	status = "disabled";
	};

	vopb: vop@ff900000 {
	compatible = "rockchip,rk3399-vop-big";
	reg = <0x0 0xff900000 0x0 0x3efc>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
	assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
	assigned-clock-rates = <400000000>, <100000000>;
	clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	iommus = <&vopb_mmu>;
	power-domains = <&power RK3399_PD_VOPB>;
	resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
	reset-names = "axi", "ahb", "dclk";
	status = "disabled";

	vopb_out: port {
	#address-cells = <1>;
	#size-cells = <0>;

	vopb_out_edp: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&edp_in_vopb>;
	};

	vopb_out_mipi: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&mipi_in_vopb>;
	};

	vopb_out_hdmi: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&hdmi_in_vopb>;
	};

	vopb_out_mipi1: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&mipi1_in_vopb>;
	};

	vopb_out_dp: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&dp_in_vopb>;
	};
	};
	};

	vopb_mmu: iommu@ff903f00 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff903f00 0x0 0x100>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
	interrupt-names = "vopb_mmu";
	clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
	clock-names = "aclk", "iface";
	power-domains = <&power RK3399_PD_VOPB>;
	#iommu-cells = <0>;
	status = "disabled";
	};

	isp0_mmu: iommu@ff914000 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
	interrupt-names = "isp0_mmu";
	clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	power-domains = <&power RK3399_PD_ISP0>;
	rockchip,disable-mmu-reset;
	};

	isp1_mmu: iommu@ff924000 {
	compatible = "rockchip,iommu";
	reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
	interrupt-names = "isp1_mmu";
	clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
	clock-names = "aclk", "iface";
	#iommu-cells = <0>;
	power-domains = <&power RK3399_PD_ISP1>;
	rockchip,disable-mmu-reset;
	};

	hdmi_sound: hdmi-sound {
	compatible = "simple-audio-card";
	simple-audio-card,format = "i2s";
	simple-audio-card,mclk-fs = <256>;
	simple-audio-card,name = "hdmi-sound";
	status = "disabled";

	simple-audio-card,cpu {
	sound-dai = <&i2s2>;
	};
	simple-audio-card,codec {
	sound-dai = <&hdmi>;
	};
	};

	hdmi: hdmi@ff940000 {
	compatible = "rockchip,rk3399-dw-hdmi";
	reg = <0x0 0xff940000 0x0 0x20000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&cru PCLK_HDMI_CTRL>,
	<&cru SCLK_HDMI_SFR>,
	<&cru PLL_VPLL>,
	<&cru PCLK_VIO_GRF>,
	<&cru SCLK_HDMI_CEC>;
	clock-names = "iahb", "isfr", "vpll", "grf", "cec";
	power-domains = <&power RK3399_PD_HDCP>;
	reg-io-width = <4>;
	rockchip,grf = <&grf>;
	#sound-dai-cells = <0>;
	status = "disabled";

	ports {
	hdmi_in: port {
	#address-cells = <1>;
	#size-cells = <0>;

	hdmi_in_vopb: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vopb_out_hdmi>;
	};
	hdmi_in_vopl: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vopl_out_hdmi>;
	};
	};
	};
	};

	mipi_dsi: mipi@ff960000 {
	compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
	reg = <0x0 0xff960000 0x0 0x8000>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
	<&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
	clock-names = "ref", "pclk", "phy_cfg", "grf";
	power-domains = <&power RK3399_PD_VIO>;
	resets = <&cru SRST_P_MIPI_DSI0>;
	reset-names = "apb";
	rockchip,grf = <&grf>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	mipi_in: port@0 {
	reg = <0>;
	#address-cells = <1>;
	#size-cells = <0>;

	mipi_in_vopb: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vopb_out_mipi>;
	};
	mipi_in_vopl: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vopl_out_mipi>;
	};
	};
	};
	};

	mipi_dsi1: mipi@ff968000 {
	compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
	reg = <0x0 0xff968000 0x0 0x8000>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
	<&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
	clock-names = "ref", "pclk", "phy_cfg", "grf";
	power-domains = <&power RK3399_PD_VIO>;
	resets = <&cru SRST_P_MIPI_DSI1>;
	reset-names = "apb";
	rockchip,grf = <&grf>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	mipi1_in: port@0 {
	reg = <0>;
	#address-cells = <1>;
	#size-cells = <0>;

	mipi1_in_vopb: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vopb_out_mipi1>;
	};

	mipi1_in_vopl: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vopl_out_mipi1>;
	};
	};
	};
	};

	edp: edp@ff970000 {
	compatible = "rockchip,rk3399-edp";
	reg = <0x0 0xff970000 0x0 0x8000>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
	clock-names = "dp", "pclk", "grf";
	pinctrl-names = "default";
	pinctrl-0 = <&edp_hpd>;
	power-domains = <&power RK3399_PD_EDP>;
	resets = <&cru SRST_P_EDP_CTRL>;
	reset-names = "dp";
	rockchip,grf = <&grf>;
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;
	edp_in: port@0 {
	reg = <0>;
	#address-cells = <1>;
	#size-cells = <0>;

	edp_in_vopb: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&vopb_out_edp>;
	};

	edp_in_vopl: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&vopl_out_edp>;
	};
	};
	};
	};

	gpu: gpu@ff9a0000 {
	compatible = "rockchip,rk3399-mali", "arm,mali-t860";
	reg = <0x0 0xff9a0000 0x0 0x10000>;
	- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
	- <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
	- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
	- interrupt-names = "gpu", "job", "mmu";
	+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
	+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
	+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
	+ interrupt-names = "job", "mmu", "gpu";
	clocks = <&cru ACLK_GPU>;
	#cooling-cells = <2>;
	power-domains = <&power RK3399_PD_GPU>;
	status = "disabled";
	};

	pinctrl: pinctrl {
	compatible = "rockchip,rk3399-pinctrl";
	rockchip,grf = <&grf>;
	rockchip,pmu = <&pmugrf>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	gpio0: gpio0@ff720000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff720000 0x0 0x100>;
	clocks = <&pmucru PCLK_GPIO0_PMU>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;

	gpio-controller;
	#gpio-cells = <0x2>;

	interrupt-controller;
	#interrupt-cells = <0x2>;
	};

	gpio1: gpio1@ff730000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff730000 0x0 0x100>;
	clocks = <&pmucru PCLK_GPIO1_PMU>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;

	gpio-controller;
	#gpio-cells = <0x2>;

	interrupt-controller;
	#interrupt-cells = <0x2>;
	};

	gpio2: gpio2@ff780000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff780000 0x0 0x100>;
	clocks = <&cru PCLK_GPIO2>;
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;

	gpio-controller;
	#gpio-cells = <0x2>;

	interrupt-controller;
	#interrupt-cells = <0x2>;
	};

	gpio3: gpio3@ff788000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff788000 0x0 0x100>;
	clocks = <&cru PCLK_GPIO3>;
	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;

	gpio-controller;
	#gpio-cells = <0x2>;

	interrupt-controller;
	#interrupt-cells = <0x2>;
	};

	gpio4: gpio4@ff790000 {
	compatible = "rockchip,gpio-bank";
	reg = <0x0 0xff790000 0x0 0x100>;
	clocks = <&cru PCLK_GPIO4>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;

	gpio-controller;
	#gpio-cells = <0x2>;

	interrupt-controller;
	#interrupt-cells = <0x2>;
	};

	pcfg_pull_up: pcfg-pull-up {
	bias-pull-up;
	};

	pcfg_pull_down: pcfg-pull-down {
	bias-pull-down;
	};

	pcfg_pull_none: pcfg-pull-none {
	bias-disable;
	};

	pcfg_pull_none_12ma: pcfg-pull-none-12ma {
	bias-disable;
	drive-strength = <12>;
	};

	pcfg_pull_none_13ma: pcfg-pull-none-13ma {
	bias-disable;
	drive-strength = <13>;
	};

	pcfg_pull_none_18ma: pcfg-pull-none-18ma {
	bias-disable;
	drive-strength = <18>;
	};

	pcfg_pull_none_20ma: pcfg-pull-none-20ma {
	bias-disable;
	drive-strength = <20>;
	};

	pcfg_pull_up_2ma: pcfg-pull-up-2ma {
	bias-pull-up;
	drive-strength = <2>;
	};

	pcfg_pull_up_8ma: pcfg-pull-up-8ma {
	bias-pull-up;
	drive-strength = <8>;
	};

	pcfg_pull_up_18ma: pcfg-pull-up-18ma {
	bias-pull-up;
	drive-strength = <18>;
	};

	pcfg_pull_up_20ma: pcfg-pull-up-20ma {
	bias-pull-up;
	drive-strength = <20>;
	};

	pcfg_pull_down_4ma: pcfg-pull-down-4ma {
	bias-pull-down;
	drive-strength = <4>;
	};

	pcfg_pull_down_8ma: pcfg-pull-down-8ma {
	bias-pull-down;
	drive-strength = <8>;
	};

	pcfg_pull_down_12ma: pcfg-pull-down-12ma {
	bias-pull-down;
	drive-strength = <12>;
	};

	pcfg_pull_down_18ma: pcfg-pull-down-18ma {
	bias-pull-down;
	drive-strength = <18>;
	};

	pcfg_pull_down_20ma: pcfg-pull-down-20ma {
	bias-pull-down;
	drive-strength = <20>;
	};

	pcfg_output_high: pcfg-output-high {
	output-high;
	};

	pcfg_output_low: pcfg-output-low {
	output-low;
	};

	clock {
	clk_32k: clk-32k {
	rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
	};
	};

	edp {
	edp_hpd: edp-hpd {
	rockchip,pins =
	<4 RK_PC7 2 &pcfg_pull_none>;
	};
	};

	gmac {
	rgmii_pins: rgmii-pins {
	rockchip,pins =
	/* mac_txclk */
	<3 RK_PC1 1 &pcfg_pull_none_13ma>,
	/* mac_rxclk */
	<3 RK_PB6 1 &pcfg_pull_none>,
	/* mac_mdio */
	<3 RK_PB5 1 &pcfg_pull_none>,
	/* mac_txen */
	<3 RK_PB4 1 &pcfg_pull_none_13ma>,
	/* mac_clk */
	<3 RK_PB3 1 &pcfg_pull_none>,
	/* mac_rxdv */
	<3 RK_PB1 1 &pcfg_pull_none>,
	/* mac_mdc */
	<3 RK_PB0 1 &pcfg_pull_none>,
	/* mac_rxd1 */
	<3 RK_PA7 1 &pcfg_pull_none>,
	/* mac_rxd0 */
	<3 RK_PA6 1 &pcfg_pull_none>,
	/* mac_txd1 */
	<3 RK_PA5 1 &pcfg_pull_none_13ma>,
	/* mac_txd0 */
	<3 RK_PA4 1 &pcfg_pull_none_13ma>,
	/* mac_rxd3 */
	<3 RK_PA3 1 &pcfg_pull_none>,
	/* mac_rxd2 */
	<3 RK_PA2 1 &pcfg_pull_none>,
	/* mac_txd3 */
	<3 RK_PA1 1 &pcfg_pull_none_13ma>,
	/* mac_txd2 */
	<3 RK_PA0 1 &pcfg_pull_none_13ma>;
	};

	rmii_pins: rmii-pins {
	rockchip,pins =
	/* mac_mdio */
	<3 RK_PB5 1 &pcfg_pull_none>,
	/* mac_txen */
	<3 RK_PB4 1 &pcfg_pull_none_13ma>,
	/* mac_clk */
	<3 RK_PB3 1 &pcfg_pull_none>,
	/* mac_rxer */
	<3 RK_PB2 1 &pcfg_pull_none>,
	/* mac_rxdv */
	<3 RK_PB1 1 &pcfg_pull_none>,
	/* mac_mdc */
	<3 RK_PB0 1 &pcfg_pull_none>,
	/* mac_rxd1 */
	<3 RK_PA7 1 &pcfg_pull_none>,
	/* mac_rxd0 */
	<3 RK_PA6 1 &pcfg_pull_none>,
	/* mac_txd1 */
	<3 RK_PA5 1 &pcfg_pull_none_13ma>,
	/* mac_txd0 */
	<3 RK_PA4 1 &pcfg_pull_none_13ma>;
	};
	};

	i2c0 {
	i2c0_xfer: i2c0-xfer {
	rockchip,pins =
	<1 RK_PB7 2 &pcfg_pull_none>,
	<1 RK_PC0 2 &pcfg_pull_none>;
	};
	};

	i2c1 {
	i2c1_xfer: i2c1-xfer {
	rockchip,pins =
	<4 RK_PA2 1 &pcfg_pull_none>,
	<4 RK_PA1 1 &pcfg_pull_none>;
	};
	};

	i2c2 {
	i2c2_xfer: i2c2-xfer {
	rockchip,pins =
	<2 RK_PA1 2 &pcfg_pull_none_12ma>,
	<2 RK_PA0 2 &pcfg_pull_none_12ma>;
	};
	};

	i2c3 {
	i2c3_xfer: i2c3-xfer {
	rockchip,pins =
	<4 RK_PC1 1 &pcfg_pull_none>,
	<4 RK_PC0 1 &pcfg_pull_none>;
	};
	};

	i2c4 {
	i2c4_xfer: i2c4-xfer {
	rockchip,pins =
	<1 RK_PB4 1 &pcfg_pull_none>,
	<1 RK_PB3 1 &pcfg_pull_none>;
	};
	};

	i2c5 {
	i2c5_xfer: i2c5-xfer {
	rockchip,pins =
	<3 RK_PB3 2 &pcfg_pull_none>,
	<3 RK_PB2 2 &pcfg_pull_none>;
	};
	};

	i2c6 {
	i2c6_xfer: i2c6-xfer {
	rockchip,pins =
	<2 RK_PB2 2 &pcfg_pull_none>,
	<2 RK_PB1 2 &pcfg_pull_none>;
	};
	};

	i2c7 {
	i2c7_xfer: i2c7-xfer {
	rockchip,pins =
	<2 RK_PB0 2 &pcfg_pull_none>,
	<2 RK_PA7 2 &pcfg_pull_none>;
	};
	};

	i2c8 {
	i2c8_xfer: i2c8-xfer {
	rockchip,pins =
	<1 RK_PC5 1 &pcfg_pull_none>,
	<1 RK_PC4 1 &pcfg_pull_none>;
	};
	};

	i2s0 {
	i2s0_2ch_bus: i2s0-2ch-bus {
	rockchip,pins =
	<3 RK_PD0 1 &pcfg_pull_none>,
	<3 RK_PD1 1 &pcfg_pull_none>,
	<3 RK_PD2 1 &pcfg_pull_none>,
	<3 RK_PD3 1 &pcfg_pull_none>,
	<3 RK_PD7 1 &pcfg_pull_none>,
	<4 RK_PA0 1 &pcfg_pull_none>;
	};

	i2s0_8ch_bus: i2s0-8ch-bus {
	rockchip,pins =
	<3 RK_PD0 1 &pcfg_pull_none>,
	<3 RK_PD1 1 &pcfg_pull_none>,
	<3 RK_PD2 1 &pcfg_pull_none>,
	<3 RK_PD3 1 &pcfg_pull_none>,
	<3 RK_PD4 1 &pcfg_pull_none>,
	<3 RK_PD5 1 &pcfg_pull_none>,
	<3 RK_PD6 1 &pcfg_pull_none>,
	<3 RK_PD7 1 &pcfg_pull_none>,
	<4 RK_PA0 1 &pcfg_pull_none>;
	};
	};

	i2s1 {
	i2s1_2ch_bus: i2s1-2ch-bus {
	rockchip,pins =
	<4 RK_PA3 1 &pcfg_pull_none>,
	<4 RK_PA4 1 &pcfg_pull_none>,
	<4 RK_PA5 1 &pcfg_pull_none>,
	<4 RK_PA6 1 &pcfg_pull_none>,
	<4 RK_PA7 1 &pcfg_pull_none>;
	};
	};

	sdio0 {
	sdio0_bus1: sdio0-bus1 {
	rockchip,pins =
	<2 RK_PC4 1 &pcfg_pull_up>;
	};

	sdio0_bus4: sdio0-bus4 {
	rockchip,pins =
	<2 RK_PC4 1 &pcfg_pull_up>,
	<2 RK_PC5 1 &pcfg_pull_up>,
	<2 RK_PC6 1 &pcfg_pull_up>,
	<2 RK_PC7 1 &pcfg_pull_up>;
	};

	sdio0_cmd: sdio0-cmd {
	rockchip,pins =
	<2 RK_PD0 1 &pcfg_pull_up>;
	};

	sdio0_clk: sdio0-clk {
	rockchip,pins =
	<2 RK_PD1 1 &pcfg_pull_none>;
	};

	sdio0_cd: sdio0-cd {
	rockchip,pins =
	<2 RK_PD2 1 &pcfg_pull_up>;
	};

	sdio0_pwr: sdio0-pwr {
	rockchip,pins =
	<2 RK_PD3 1 &pcfg_pull_up>;
	};

	sdio0_bkpwr: sdio0-bkpwr {
	rockchip,pins =
	<2 RK_PD4 1 &pcfg_pull_up>;
	};

	sdio0_wp: sdio0-wp {
	rockchip,pins =
	<0 RK_PA3 1 &pcfg_pull_up>;
	};

	sdio0_int: sdio0-int {
	rockchip,pins =
	<0 RK_PA4 1 &pcfg_pull_up>;
	};
	};

	sdmmc {
	sdmmc_bus1: sdmmc-bus1 {
	rockchip,pins =
	<4 RK_PB0 1 &pcfg_pull_up>;
	};

	sdmmc_bus4: sdmmc-bus4 {
	rockchip,pins =
	<4 RK_PB0 1 &pcfg_pull_up>,
	<4 RK_PB1 1 &pcfg_pull_up>,
	<4 RK_PB2 1 &pcfg_pull_up>,
	<4 RK_PB3 1 &pcfg_pull_up>;
	};

	sdmmc_clk: sdmmc-clk {
	rockchip,pins =
	<4 RK_PB4 1 &pcfg_pull_none>;
	};

	sdmmc_cmd: sdmmc-cmd {
	rockchip,pins =
	<4 RK_PB5 1 &pcfg_pull_up>;
	};

	sdmmc_cd: sdmmc-cd {
	rockchip,pins =
	<0 RK_PA7 1 &pcfg_pull_up>;
	};

	sdmmc_wp: sdmmc-wp {
	rockchip,pins =
	<0 RK_PB0 1 &pcfg_pull_up>;
	};
	};

	sleep {
	ap_pwroff: ap-pwroff {
	rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
	};

	ddrio_pwroff: ddrio-pwroff {
	rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
	};
	};

	spdif {
	spdif_bus: spdif-bus {
	rockchip,pins =
	<4 RK_PC5 1 &pcfg_pull_none>;
	};

	spdif_bus_1: spdif-bus-1 {
	rockchip,pins =
	<3 RK_PC0 3 &pcfg_pull_none>;
	};
	};

	spi0 {
	spi0_clk: spi0-clk {
	rockchip,pins =
	<3 RK_PA6 2 &pcfg_pull_up>;
	};
	spi0_cs0: spi0-cs0 {
	rockchip,pins =
	<3 RK_PA7 2 &pcfg_pull_up>;
	};
	spi0_cs1: spi0-cs1 {
	rockchip,pins =
	<3 RK_PB0 2 &pcfg_pull_up>;
	};
	spi0_tx: spi0-tx {
	rockchip,pins =
	<3 RK_PA5 2 &pcfg_pull_up>;
	};
	spi0_rx: spi0-rx {
	rockchip,pins =
	<3 RK_PA4 2 &pcfg_pull_up>;
	};
	};

	spi1 {
	spi1_clk: spi1-clk {
	rockchip,pins =
	<1 RK_PB1 2 &pcfg_pull_up>;
	};
	spi1_cs0: spi1-cs0 {
	rockchip,pins =
	<1 RK_PB2 2 &pcfg_pull_up>;
	};
	spi1_rx: spi1-rx {
	rockchip,pins =
	<1 RK_PA7 2 &pcfg_pull_up>;
	};
	spi1_tx: spi1-tx {
	rockchip,pins =
	<1 RK_PB0 2 &pcfg_pull_up>;
	};
	};

	spi2 {
	spi2_clk: spi2-clk {
	rockchip,pins =
	<2 RK_PB3 1 &pcfg_pull_up>;
	};
	spi2_cs0: spi2-cs0 {
	rockchip,pins =
	<2 RK_PB4 1 &pcfg_pull_up>;
	};
	spi2_rx: spi2-rx {
	rockchip,pins =
	<2 RK_PB1 1 &pcfg_pull_up>;
	};
	spi2_tx: spi2-tx {
	rockchip,pins =
	<2 RK_PB2 1 &pcfg_pull_up>;
	};
	};

	spi3 {
	spi3_clk: spi3-clk {
	rockchip,pins =
	<1 RK_PC1 1 &pcfg_pull_up>;
	};
	spi3_cs0: spi3-cs0 {
	rockchip,pins =
	<1 RK_PC2 1 &pcfg_pull_up>;
	};
	spi3_rx: spi3-rx {
	rockchip,pins =
	<1 RK_PB7 1 &pcfg_pull_up>;
	};
	spi3_tx: spi3-tx {
	rockchip,pins =
	<1 RK_PC0 1 &pcfg_pull_up>;
	};
	};

	spi4 {
	spi4_clk: spi4-clk {
	rockchip,pins =
	<3 RK_PA2 2 &pcfg_pull_up>;
	};
	spi4_cs0: spi4-cs0 {
	rockchip,pins =
	<3 RK_PA3 2 &pcfg_pull_up>;
	};
	spi4_rx: spi4-rx {
	rockchip,pins =
	<3 RK_PA0 2 &pcfg_pull_up>;
	};
	spi4_tx: spi4-tx {
	rockchip,pins =
	<3 RK_PA1 2 &pcfg_pull_up>;
	};
	};

	spi5 {
	spi5_clk: spi5-clk {
	rockchip,pins =
	<2 RK_PC6 2 &pcfg_pull_up>;
	};
	spi5_cs0: spi5-cs0 {
	rockchip,pins =
	<2 RK_PC7 2 &pcfg_pull_up>;
	};
	spi5_rx: spi5-rx {
	rockchip,pins =
	<2 RK_PC4 2 &pcfg_pull_up>;
	};
	spi5_tx: spi5-tx {
	rockchip,pins =
	<2 RK_PC5 2 &pcfg_pull_up>;
	};
	};

	testclk {
	test_clkout0: test-clkout0 {
	rockchip,pins =
	<0 RK_PA0 1 &pcfg_pull_none>;
	};

	test_clkout1: test-clkout1 {
	rockchip,pins =
	<2 RK_PD1 2 &pcfg_pull_none>;
	};

	test_clkout2: test-clkout2 {
	rockchip,pins =
	<0 RK_PB0 3 &pcfg_pull_none>;
	};
	};

	tsadc {
	otp_gpio: otp-gpio {
	rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	otp_out: otp-out {
	rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
	};
	};

	uart0 {
	uart0_xfer: uart0-xfer {
	rockchip,pins =
	<2 RK_PC0 1 &pcfg_pull_up>,
	<2 RK_PC1 1 &pcfg_pull_none>;
	};

	uart0_cts: uart0-cts {
	rockchip,pins =
	<2 RK_PC2 1 &pcfg_pull_none>;
	};

	uart0_rts: uart0-rts {
	rockchip,pins =
	<2 RK_PC3 1 &pcfg_pull_none>;
	};
	};

	uart1 {
	uart1_xfer: uart1-xfer {
	rockchip,pins =
	<3 RK_PB4 2 &pcfg_pull_up>,
	<3 RK_PB5 2 &pcfg_pull_none>;
	};
	};

	uart2a {
	uart2a_xfer: uart2a-xfer {
	rockchip,pins =
	<4 RK_PB0 2 &pcfg_pull_up>,
	<4 RK_PB1 2 &pcfg_pull_none>;
	};
	};

	uart2b {
	uart2b_xfer: uart2b-xfer {
	rockchip,pins =
	<4 RK_PC0 2 &pcfg_pull_up>,
	<4 RK_PC1 2 &pcfg_pull_none>;
	};
	};

	uart2c {
	uart2c_xfer: uart2c-xfer {
	rockchip,pins =
	<4 RK_PC3 1 &pcfg_pull_up>,
	<4 RK_PC4 1 &pcfg_pull_none>;
	};
	};

	uart3 {
	uart3_xfer: uart3-xfer {
	rockchip,pins =
	<3 RK_PB6 2 &pcfg_pull_up>,
	<3 RK_PB7 2 &pcfg_pull_none>;
	};

	uart3_cts: uart3-cts {
	rockchip,pins =
	<3 RK_PC0 2 &pcfg_pull_none>;
	};

	uart3_rts: uart3-rts {
	rockchip,pins =
	<3 RK_PC1 2 &pcfg_pull_none>;
	};
	};

	uart4 {
	uart4_xfer: uart4-xfer {
	rockchip,pins =
	<1 RK_PA7 1 &pcfg_pull_up>,
	<1 RK_PB0 1 &pcfg_pull_none>;
	};
	};

	uarthdcp {
	uarthdcp_xfer: uarthdcp-xfer {
	rockchip,pins =
	<4 RK_PC5 2 &pcfg_pull_up>,
	<4 RK_PC6 2 &pcfg_pull_none>;
	};
	};

	pwm0 {
	pwm0_pin: pwm0-pin {
	rockchip,pins =
	<4 RK_PC2 1 &pcfg_pull_none>;
	};

	pwm0_pin_pull_down: pwm0-pin-pull-down {
	rockchip,pins =
	<4 RK_PC2 1 &pcfg_pull_down>;
	};

	vop0_pwm_pin: vop0-pwm-pin {
	rockchip,pins =
	<4 RK_PC2 2 &pcfg_pull_none>;
	};

	vop1_pwm_pin: vop1-pwm-pin {
	rockchip,pins =
	<4 RK_PC2 3 &pcfg_pull_none>;
	};
	};

	pwm1 {
	pwm1_pin: pwm1-pin {
	rockchip,pins =
	<4 RK_PC6 1 &pcfg_pull_none>;
	};

	pwm1_pin_pull_down: pwm1-pin-pull-down {
	rockchip,pins =
	<4 RK_PC6 1 &pcfg_pull_down>;
	};
	};

	pwm2 {
	pwm2_pin: pwm2-pin {
	rockchip,pins =
	<1 RK_PC3 1 &pcfg_pull_none>;
	};

	pwm2_pin_pull_down: pwm2-pin-pull-down {
	rockchip,pins =
	<1 RK_PC3 1 &pcfg_pull_down>;
	};
	};

	pwm3a {
	pwm3a_pin: pwm3a-pin {
	rockchip,pins =
	<0 RK_PA6 1 &pcfg_pull_none>;
	};
	};

	pwm3b {
	pwm3b_pin: pwm3b-pin {
	rockchip,pins =
	<1 RK_PB6 1 &pcfg_pull_none>;
	};
	};

	hdmi {
	hdmi_i2c_xfer: hdmi-i2c-xfer {
	rockchip,pins =
	<4 RK_PC1 3 &pcfg_pull_none>,
	<4 RK_PC0 3 &pcfg_pull_none>;
	};

	hdmi_cec: hdmi-cec {
	rockchip,pins =
	<4 RK_PC7 1 &pcfg_pull_none>;
	};
	};

	pcie {
	pcie_clkreqn_cpm: pci-clkreqn-cpm {
	rockchip,pins =
	<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
	rockchip,pins =
	<4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
	};
	};

	};
	};
	diff --git a/sys/gnu/dts/arm64/rockchip/rk3399pro-rock-pi-n10.dts b/sys/gnu/dts/arm64/rockchip/rk3399pro-rock-pi-n10.dts
	index b42f94179538..a1783e7f769a 100644
	--- a/sys/gnu/dts/arm64/rockchip/rk3399pro-rock-pi-n10.dts
	+++ b/sys/gnu/dts/arm64/rockchip/rk3399pro-rock-pi-n10.dts
	@@ -1,17 +1,18 @@
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
	* Copyright (c) 2019 Radxa Limited
	* Copyright (c) 2019 Amarula Solutions(India)
	*/

	/dts-v1/;
	#include "rk3399.dtsi"
	#include "rk3399-opp.dtsi"
	#include "rk3399pro-vmarc-som.dtsi"
	#include <arm/rockchip-radxa-dalang-carrier.dtsi>

	/ {
	model = "Radxa ROCK Pi N10";
	- compatible = "radxa,rockpi-n10", "rockchip,rk3399pro";
	+ compatible = "radxa,rockpi-n10", "vamrs,rk3399pro-vmarc-som",
	+ "rockchip,rk3399pro";
	};
	diff --git a/sys/gnu/dts/arm64/socionext/uniphier-ld11.dtsi b/sys/gnu/dts/arm64/socionext/uniphier-ld11.dtsi
	index 5b18bda9c5a6..2ca2d3dc8d6c 100644
	--- a/sys/gnu/dts/arm64/socionext/uniphier-ld11.dtsi
	+++ b/sys/gnu/dts/arm64/socionext/uniphier-ld11.dtsi
	@@ -1,651 +1,651 @@
	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	//
	// Device Tree Source for UniPhier LD11 SoC
	//
	// Copyright (C) 2016 Socionext Inc.
	// Author: Masahiro Yamada <yamada.masahiro@socionext.com>

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/gpio/uniphier-gpio.h>

	/ {
	compatible = "socionext,uniphier-ld11";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	cpu-map {
	cluster0 {
	core0 {
	cpu = <&cpu0>;
	};
	core1 {
	cpu = <&cpu1>;
	};
	};
	};

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0 0x000>;
	clocks = <&sys_clk 33>;
	enable-method = "psci";
	operating-points-v2 = <&cluster0_opp>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0 0x001>;
	clocks = <&sys_clk 33>;
	enable-method = "psci";
	operating-points-v2 = <&cluster0_opp>;
	};
	};

	cluster0_opp: opp-table {
	compatible = "operating-points-v2";
	opp-shared;

	opp-245000000 {
	opp-hz = /bits/ 64 <245000000>;
	clock-latency-ns = <300>;
	};
	opp-250000000 {
	opp-hz = /bits/ 64 <250000000>;
	clock-latency-ns = <300>;
	};
	opp-490000000 {
	opp-hz = /bits/ 64 <490000000>;
	clock-latency-ns = <300>;
	};
	opp-500000000 {
	opp-hz = /bits/ 64 <500000000>;
	clock-latency-ns = <300>;
	};
	opp-653334000 {
	opp-hz = /bits/ 64 <653334000>;
	clock-latency-ns = <300>;
	};
	opp-666667000 {
	opp-hz = /bits/ 64 <666667000>;
	clock-latency-ns = <300>;
	};
	opp-980000000 {
	opp-hz = /bits/ 64 <980000000>;
	clock-latency-ns = <300>;
	};
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	clocks {
	refclk: ref {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <25000000>;
	};
	};

	emmc_pwrseq: emmc-pwrseq {
	compatible = "mmc-pwrseq-emmc";
	reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <1 13 4>,
	<1 14 4>,
	<1 11 4>,
	<1 10 4>;
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	secure-memory@81000000 {
	reg = <0x0 0x81000000 0x0 0x01000000>;
	no-map;
	};
	};

	soc@0 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;

	spi0: spi@54006000 {
	compatible = "socionext,uniphier-scssi";
	status = "disabled";
	reg = <0x54006000 0x100>;
	interrupts = <0 39 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi0>;
	clocks = <&peri_clk 11>;
	resets = <&peri_rst 11>;
	};

	spi1: spi@54006100 {
	compatible = "socionext,uniphier-scssi";
	status = "disabled";
	reg = <0x54006100 0x100>;
	interrupts = <0 216 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi1>;
	- clocks = <&peri_clk 11>;
	- resets = <&peri_rst 11>;
	+ clocks = <&peri_clk 12>;
	+ resets = <&peri_rst 12>;
	};

	serial0: serial@54006800 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006800 0x40>;
	interrupts = <0 33 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	clocks = <&peri_clk 0>;
	resets = <&peri_rst 0>;
	};

	serial1: serial@54006900 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006900 0x40>;
	interrupts = <0 35 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	clocks = <&peri_clk 1>;
	resets = <&peri_rst 1>;
	};

	serial2: serial@54006a00 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006a00 0x40>;
	interrupts = <0 37 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	clocks = <&peri_clk 2>;
	resets = <&peri_rst 2>;
	};

	serial3: serial@54006b00 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006b00 0x40>;
	interrupts = <0 177 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	clocks = <&peri_clk 3>;
	resets = <&peri_rst 3>;
	};

	gpio: gpio@55000000 {
	compatible = "socionext,uniphier-gpio";
	reg = <0x55000000 0x200>;
	interrupt-parent = <&aidet>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 0 0>,
	<&pinctrl 43 0 0>,
	<&pinctrl 51 0 0>,
	<&pinctrl 96 0 0>,
	<&pinctrl 160 0 0>,
	<&pinctrl 184 0 0>;
	gpio-ranges-group-names = "gpio_range0",
	"gpio_range1",
	"gpio_range2",
	"gpio_range3",
	"gpio_range4",
	"gpio_range5";
	ngpios = <200>;
	socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
	<21 217 3>;
	};

	audio@56000000 {
	compatible = "socionext,uniphier-ld11-aio";
	reg = <0x56000000 0x80000>;
	interrupts = <0 144 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_aout1>,
	<&pinctrl_aoutiec1>;
	clock-names = "aio";
	clocks = <&sys_clk 40>;
	reset-names = "aio";
	resets = <&sys_rst 40>;
	#sound-dai-cells = <1>;
	socionext,syscon = <&soc_glue>;

	i2s_port0: port@0 {
	i2s_hdmi: endpoint {
	};
	};

	i2s_port1: port@1 {
	i2s_pcmin2: endpoint {
	};
	};

	i2s_port2: port@2 {
	i2s_line: endpoint {
	dai-format = "i2s";
	remote-endpoint = <&evea_line>;
	};
	};

	i2s_port3: port@3 {
	i2s_hpcmout1: endpoint {
	};
	};

	i2s_port4: port@4 {
	i2s_hp: endpoint {
	dai-format = "i2s";
	remote-endpoint = <&evea_hp>;
	};
	};

	spdif_port0: port@5 {
	spdif_hiecout1: endpoint {
	};
	};

	src_port0: port@6 {
	i2s_epcmout2: endpoint {
	};
	};

	src_port1: port@7 {
	i2s_epcmout3: endpoint {
	};
	};

	comp_spdif_port0: port@8 {
	comp_spdif_hiecout1: endpoint {
	};
	};
	};

	codec@57900000 {
	compatible = "socionext,uniphier-evea";
	reg = <0x57900000 0x1000>;
	clock-names = "evea", "exiv";
	clocks = <&sys_clk 41>, <&sys_clk 42>;
	reset-names = "evea", "exiv", "adamv";
	resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
	#sound-dai-cells = <1>;

	port@0 {
	evea_line: endpoint {
	remote-endpoint = <&i2s_line>;
	};
	};

	port@1 {
	evea_hp: endpoint {
	remote-endpoint = <&i2s_hp>;
	};
	};
	};

	adamv@57920000 {
	compatible = "socionext,uniphier-ld11-adamv",
	"simple-mfd", "syscon";
	reg = <0x57920000 0x1000>;

	adamv_rst: reset {
	compatible = "socionext,uniphier-ld11-adamv-reset";
	#reset-cells = <1>;
	};
	};

	i2c0: i2c@58780000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58780000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 41 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	clocks = <&peri_clk 4>;
	resets = <&peri_rst 4>;
	clock-frequency = <100000>;
	};

	i2c1: i2c@58781000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58781000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 42 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	clocks = <&peri_clk 5>;
	resets = <&peri_rst 5>;
	clock-frequency = <100000>;
	};

	i2c2: i2c@58782000 {
	compatible = "socionext,uniphier-fi2c";
	reg = <0x58782000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 43 4>;
	clocks = <&peri_clk 6>;
	resets = <&peri_rst 6>;
	clock-frequency = <400000>;
	};

	i2c3: i2c@58783000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58783000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 44 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	clocks = <&peri_clk 7>;
	resets = <&peri_rst 7>;
	clock-frequency = <100000>;
	};

	i2c4: i2c@58784000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58784000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 45 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	clocks = <&peri_clk 8>;
	resets = <&peri_rst 8>;
	clock-frequency = <100000>;
	};

	i2c5: i2c@58785000 {
	compatible = "socionext,uniphier-fi2c";
	reg = <0x58785000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 25 4>;
	clocks = <&peri_clk 9>;
	resets = <&peri_rst 9>;
	clock-frequency = <400000>;
	};

	system_bus: system-bus@58c00000 {
	compatible = "socionext,uniphier-system-bus";
	status = "disabled";
	reg = <0x58c00000 0x400>;
	#address-cells = <2>;
	#size-cells = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_system_bus>;
	};

	smpctrl@59801000 {
	compatible = "socionext,uniphier-smpctrl";
	reg = <0x59801000 0x400>;
	};

	sdctrl@59810000 {
	compatible = "socionext,uniphier-ld11-sdctrl",
	"simple-mfd", "syscon";
	reg = <0x59810000 0x400>;

	sd_rst: reset {
	compatible = "socionext,uniphier-ld11-sd-reset";
	#reset-cells = <1>;
	};
	};

	perictrl@59820000 {
	compatible = "socionext,uniphier-ld11-perictrl",
	"simple-mfd", "syscon";
	reg = <0x59820000 0x200>;

	peri_clk: clock {
	compatible = "socionext,uniphier-ld11-peri-clock";
	#clock-cells = <1>;
	};

	peri_rst: reset {
	compatible = "socionext,uniphier-ld11-peri-reset";
	#reset-cells = <1>;
	};
	};

	- emmc: sdhc@5a000000 {
	+ emmc: mmc@5a000000 {
	compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
	reg = <0x5a000000 0x400>;
	interrupts = <0 78 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_emmc>;
	clocks = <&sys_clk 4>;
	resets = <&sys_rst 4>;
	bus-width = <8>;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	mmc-pwrseq = <&emmc_pwrseq>;
	cdns,phy-input-delay-legacy = <9>;
	cdns,phy-input-delay-mmc-highspeed = <2>;
	cdns,phy-input-delay-mmc-ddr = <3>;
	cdns,phy-dll-delay-sdclk = <21>;
	cdns,phy-dll-delay-sdclk-hsmmc = <21>;
	};

	usb0: usb@5a800100 {
	compatible = "socionext,uniphier-ehci", "generic-ehci";
	status = "disabled";
	reg = <0x5a800100 0x100>;
	interrupts = <0 243 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb0>;
	clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
	<&mio_clk 12>;
	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
	<&mio_rst 12>;
	phy-names = "usb";
	phys = <&usb_phy0>;
	has-transaction-translator;
	};

	usb1: usb@5a810100 {
	compatible = "socionext,uniphier-ehci", "generic-ehci";
	status = "disabled";
	reg = <0x5a810100 0x100>;
	interrupts = <0 244 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb1>;
	clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
	<&mio_clk 13>;
	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
	<&mio_rst 13>;
	phy-names = "usb";
	phys = <&usb_phy1>;
	has-transaction-translator;
	};

	usb2: usb@5a820100 {
	compatible = "socionext,uniphier-ehci", "generic-ehci";
	status = "disabled";
	reg = <0x5a820100 0x100>;
	interrupts = <0 245 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb2>;
	clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
	<&mio_clk 14>;
	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
	<&mio_rst 14>;
	phy-names = "usb";
	phys = <&usb_phy2>;
	has-transaction-translator;
	};

	mioctrl@5b3e0000 {
	compatible = "socionext,uniphier-ld11-mioctrl",
	"simple-mfd", "syscon";
	reg = <0x5b3e0000 0x800>;

	mio_clk: clock {
	compatible = "socionext,uniphier-ld11-mio-clock";
	#clock-cells = <1>;
	};

	mio_rst: reset {
	compatible = "socionext,uniphier-ld11-mio-reset";
	#reset-cells = <1>;
	resets = <&sys_rst 7>;
	};
	};

	soc_glue: soc-glue@5f800000 {
	compatible = "socionext,uniphier-ld11-soc-glue",
	"simple-mfd", "syscon";
	reg = <0x5f800000 0x2000>;

	pinctrl: pinctrl {
	compatible = "socionext,uniphier-ld11-pinctrl";
	};

	usb-phy {
	compatible = "socionext,uniphier-ld11-usb2-phy";
	#address-cells = <1>;
	#size-cells = <0>;

	usb_phy0: phy@0 {
	reg = <0>;
	#phy-cells = <0>;
	};

	usb_phy1: phy@1 {
	reg = <1>;
	#phy-cells = <0>;
	};

	usb_phy2: phy@2 {
	reg = <2>;
	#phy-cells = <0>;
	};
	};
	};

	soc-glue@5f900000 {
	compatible = "socionext,uniphier-ld11-soc-glue-debug",
	"simple-mfd";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x5f900000 0x2000>;

	efuse@100 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x100 0x28>;
	};

	efuse@200 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x200 0x68>;
	};
	};

	- aidet: aidet@5fc20000 {
	+ aidet: interrupt-controller@5fc20000 {
	compatible = "socionext,uniphier-ld11-aidet";
	reg = <0x5fc20000 0x200>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gic: interrupt-controller@5fe00000 {
	compatible = "arm,gic-v3";
	reg = <0x5fe00000 0x10000>, /* GICD */
	<0x5fe40000 0x80000>; /* GICR */
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupts = <1 9 4>;
	};

	sysctrl@61840000 {
	compatible = "socionext,uniphier-ld11-sysctrl",
	"simple-mfd", "syscon";
	reg = <0x61840000 0x10000>;

	sys_clk: clock {
	compatible = "socionext,uniphier-ld11-clock";
	#clock-cells = <1>;
	};

	sys_rst: reset {
	compatible = "socionext,uniphier-ld11-reset";
	#reset-cells = <1>;
	};

	watchdog {
	compatible = "socionext,uniphier-wdt";
	};
	};

	eth: ethernet@65000000 {
	compatible = "socionext,uniphier-ld11-ave4";
	status = "disabled";
	reg = <0x65000000 0x8500>;
	interrupts = <0 66 4>;
	clock-names = "ether";
	clocks = <&sys_clk 6>;
	reset-names = "ether";
	resets = <&sys_rst 6>;
	phy-mode = "internal";
	local-mac-address = [00 00 00 00 00 00];
	socionext,syscon-phy-mode = <&soc_glue 0>;

	mdio: mdio {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	- nand: nand@68000000 {
	+ nand: nand-controller@68000000 {
	compatible = "socionext,uniphier-denali-nand-v5b";
	status = "disabled";
	reg-names = "nand_data", "denali_reg";
	reg = <0x68000000 0x20>, <0x68100000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 65 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nand>;
	clock-names = "nand", "nand_x", "ecc";
	clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
	reset-names = "nand", "reg";
	resets = <&sys_rst 2>, <&sys_rst 2>;
	};
	};
	};

	#include "uniphier-pinctrl.dtsi"

	&pinctrl_aoutiec1 {
	drive-strength = <4>; /* default: 4mA */

	ao1arc {
	pins = "AO1ARC";
	drive-strength = <8>; /* 8mA */
	};
	};
	diff --git a/sys/gnu/dts/arm64/socionext/uniphier-ld20.dtsi b/sys/gnu/dts/arm64/socionext/uniphier-ld20.dtsi
	index f2dc5f695020..a93148c2088f 100644
	--- a/sys/gnu/dts/arm64/socionext/uniphier-ld20.dtsi
	+++ b/sys/gnu/dts/arm64/socionext/uniphier-ld20.dtsi
	@@ -1,964 +1,964 @@
	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	//
	// Device Tree Source for UniPhier LD20 SoC
	//
	// Copyright (C) 2015-2016 Socionext Inc.
	// Author: Masahiro Yamada <yamada.masahiro@socionext.com>

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/gpio/uniphier-gpio.h>
	#include <dt-bindings/thermal/thermal.h>

	/ {
	compatible = "socionext,uniphier-ld20";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	cpu-map {
	cluster0 {
	core0 {
	cpu = <&cpu0>;
	};
	core1 {
	cpu = <&cpu1>;
	};
	};

	cluster1 {
	core0 {
	cpu = <&cpu2>;
	};
	core1 {
	cpu = <&cpu3>;
	};
	};
	};

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	reg = <0 0x000>;
	clocks = <&sys_clk 32>;
	enable-method = "psci";
	operating-points-v2 = <&cluster0_opp>;
	#cooling-cells = <2>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a72";
	reg = <0 0x001>;
	clocks = <&sys_clk 32>;
	enable-method = "psci";
	operating-points-v2 = <&cluster0_opp>;
	#cooling-cells = <2>;
	};

	cpu2: cpu@100 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0 0x100>;
	clocks = <&sys_clk 33>;
	enable-method = "psci";
	operating-points-v2 = <&cluster1_opp>;
	#cooling-cells = <2>;
	};

	cpu3: cpu@101 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0 0x101>;
	clocks = <&sys_clk 33>;
	enable-method = "psci";
	operating-points-v2 = <&cluster1_opp>;
	#cooling-cells = <2>;
	};
	};

	cluster0_opp: opp-table0 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-250000000 {
	opp-hz = /bits/ 64 <250000000>;
	clock-latency-ns = <300>;
	};
	opp-275000000 {
	opp-hz = /bits/ 64 <275000000>;
	clock-latency-ns = <300>;
	};
	opp-500000000 {
	opp-hz = /bits/ 64 <500000000>;
	clock-latency-ns = <300>;
	};
	opp-550000000 {
	opp-hz = /bits/ 64 <550000000>;
	clock-latency-ns = <300>;
	};
	opp-666667000 {
	opp-hz = /bits/ 64 <666667000>;
	clock-latency-ns = <300>;
	};
	opp-733334000 {
	opp-hz = /bits/ 64 <733334000>;
	clock-latency-ns = <300>;
	};
	opp-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	clock-latency-ns = <300>;
	};
	opp-1100000000 {
	opp-hz = /bits/ 64 <1100000000>;
	clock-latency-ns = <300>;
	};
	};

	cluster1_opp: opp-table1 {
	compatible = "operating-points-v2";
	opp-shared;

	opp-250000000 {
	opp-hz = /bits/ 64 <250000000>;
	clock-latency-ns = <300>;
	};
	opp-275000000 {
	opp-hz = /bits/ 64 <275000000>;
	clock-latency-ns = <300>;
	};
	opp-500000000 {
	opp-hz = /bits/ 64 <500000000>;
	clock-latency-ns = <300>;
	};
	opp-550000000 {
	opp-hz = /bits/ 64 <550000000>;
	clock-latency-ns = <300>;
	};
	opp-666667000 {
	opp-hz = /bits/ 64 <666667000>;
	clock-latency-ns = <300>;
	};
	opp-733334000 {
	opp-hz = /bits/ 64 <733334000>;
	clock-latency-ns = <300>;
	};
	opp-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	clock-latency-ns = <300>;
	};
	opp-1100000000 {
	opp-hz = /bits/ 64 <1100000000>;
	clock-latency-ns = <300>;
	};
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	clocks {
	refclk: ref {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <25000000>;
	};
	};

	emmc_pwrseq: emmc-pwrseq {
	compatible = "mmc-pwrseq-emmc";
	reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <1 13 4>,
	<1 14 4>,
	<1 11 4>,
	<1 10 4>;
	};

	thermal-zones {
	cpu-thermal {
	polling-delay-passive = <250>; /* 250ms */
	polling-delay = <1000>; /* 1000ms */
	thermal-sensors = <&pvtctl>;

	trips {
	cpu_crit: cpu-crit {
	temperature = <110000>; /* 110C */
	hysteresis = <2000>;
	type = "critical";
	};
	cpu_alert: cpu-alert {
	temperature = <100000>; /* 100C */
	hysteresis = <2000>;
	type = "passive";
	};
	};

	cooling-maps {
	map0 {
	trip = <&cpu_alert>;
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	secure-memory@81000000 {
	reg = <0x0 0x81000000 0x0 0x01000000>;
	no-map;
	};
	};

	soc@0 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;

	spi0: spi@54006000 {
	compatible = "socionext,uniphier-scssi";
	status = "disabled";
	reg = <0x54006000 0x100>;
	interrupts = <0 39 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi0>;
	clocks = <&peri_clk 11>;
	resets = <&peri_rst 11>;
	};

	spi1: spi@54006100 {
	compatible = "socionext,uniphier-scssi";
	status = "disabled";
	reg = <0x54006100 0x100>;
	interrupts = <0 216 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi1>;
	- clocks = <&peri_clk 11>;
	- resets = <&peri_rst 11>;
	+ clocks = <&peri_clk 12>;
	+ resets = <&peri_rst 12>;
	};

	spi2: spi@54006200 {
	compatible = "socionext,uniphier-scssi";
	status = "disabled";
	reg = <0x54006200 0x100>;
	interrupts = <0 229 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi2>;
	- clocks = <&peri_clk 11>;
	- resets = <&peri_rst 11>;
	+ clocks = <&peri_clk 13>;
	+ resets = <&peri_rst 13>;
	};

	spi3: spi@54006300 {
	compatible = "socionext,uniphier-scssi";
	status = "disabled";
	reg = <0x54006300 0x100>;
	interrupts = <0 230 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi3>;
	- clocks = <&peri_clk 11>;
	- resets = <&peri_rst 11>;
	+ clocks = <&peri_clk 14>;
	+ resets = <&peri_rst 14>;
	};

	serial0: serial@54006800 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006800 0x40>;
	interrupts = <0 33 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	clocks = <&peri_clk 0>;
	resets = <&peri_rst 0>;
	};

	serial1: serial@54006900 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006900 0x40>;
	interrupts = <0 35 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	clocks = <&peri_clk 1>;
	resets = <&peri_rst 1>;
	};

	serial2: serial@54006a00 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006a00 0x40>;
	interrupts = <0 37 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	clocks = <&peri_clk 2>;
	resets = <&peri_rst 2>;
	};

	serial3: serial@54006b00 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006b00 0x40>;
	interrupts = <0 177 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	clocks = <&peri_clk 3>;
	resets = <&peri_rst 3>;
	};

	gpio: gpio@55000000 {
	compatible = "socionext,uniphier-gpio";
	reg = <0x55000000 0x200>;
	interrupt-parent = <&aidet>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 0 0>,
	<&pinctrl 96 0 0>,
	<&pinctrl 160 0 0>;
	gpio-ranges-group-names = "gpio_range0",
	"gpio_range1",
	"gpio_range2";
	ngpios = <205>;
	socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
	<21 217 3>;
	};

	audio@56000000 {
	compatible = "socionext,uniphier-ld20-aio";
	reg = <0x56000000 0x80000>;
	interrupts = <0 144 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_aout1>,
	<&pinctrl_aoutiec1>;
	clock-names = "aio";
	clocks = <&sys_clk 40>;
	reset-names = "aio";
	resets = <&sys_rst 40>;
	#sound-dai-cells = <1>;
	socionext,syscon = <&soc_glue>;

	i2s_port0: port@0 {
	i2s_hdmi: endpoint {
	};
	};

	i2s_port1: port@1 {
	i2s_pcmin2: endpoint {
	};
	};

	i2s_port2: port@2 {
	i2s_line: endpoint {
	dai-format = "i2s";
	remote-endpoint = <&evea_line>;
	};
	};

	i2s_port3: port@3 {
	i2s_hpcmout1: endpoint {
	};
	};

	i2s_port4: port@4 {
	i2s_hp: endpoint {
	dai-format = "i2s";
	remote-endpoint = <&evea_hp>;
	};
	};

	spdif_port0: port@5 {
	spdif_hiecout1: endpoint {
	};
	};

	src_port0: port@6 {
	i2s_epcmout2: endpoint {
	};
	};

	src_port1: port@7 {
	i2s_epcmout3: endpoint {
	};
	};

	comp_spdif_port0: port@8 {
	comp_spdif_hiecout1: endpoint {
	};
	};
	};

	codec@57900000 {
	compatible = "socionext,uniphier-evea";
	reg = <0x57900000 0x1000>;
	clock-names = "evea", "exiv";
	clocks = <&sys_clk 41>, <&sys_clk 42>;
	reset-names = "evea", "exiv", "adamv";
	resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
	#sound-dai-cells = <1>;

	port@0 {
	evea_line: endpoint {
	remote-endpoint = <&i2s_line>;
	};
	};

	port@1 {
	evea_hp: endpoint {
	remote-endpoint = <&i2s_hp>;
	};
	};
	};

	adamv@57920000 {
	compatible = "socionext,uniphier-ld20-adamv",
	"simple-mfd", "syscon";
	reg = <0x57920000 0x1000>;

	adamv_rst: reset {
	compatible = "socionext,uniphier-ld20-adamv-reset";
	#reset-cells = <1>;
	};
	};

	i2c0: i2c@58780000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58780000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 41 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	clocks = <&peri_clk 4>;
	resets = <&peri_rst 4>;
	clock-frequency = <100000>;
	};

	i2c1: i2c@58781000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58781000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 42 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	clocks = <&peri_clk 5>;
	resets = <&peri_rst 5>;
	clock-frequency = <100000>;
	};

	i2c2: i2c@58782000 {
	compatible = "socionext,uniphier-fi2c";
	reg = <0x58782000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 43 4>;
	clocks = <&peri_clk 6>;
	resets = <&peri_rst 6>;
	clock-frequency = <400000>;
	};

	i2c3: i2c@58783000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58783000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 44 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	clocks = <&peri_clk 7>;
	resets = <&peri_rst 7>;
	clock-frequency = <100000>;
	};

	i2c4: i2c@58784000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58784000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 45 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	clocks = <&peri_clk 8>;
	resets = <&peri_rst 8>;
	clock-frequency = <100000>;
	};

	i2c5: i2c@58785000 {
	compatible = "socionext,uniphier-fi2c";
	reg = <0x58785000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 25 4>;
	clocks = <&peri_clk 9>;
	resets = <&peri_rst 9>;
	clock-frequency = <400000>;
	};

	system_bus: system-bus@58c00000 {
	compatible = "socionext,uniphier-system-bus";
	status = "disabled";
	reg = <0x58c00000 0x400>;
	#address-cells = <2>;
	#size-cells = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_system_bus>;
	};

	smpctrl@59801000 {
	compatible = "socionext,uniphier-smpctrl";
	reg = <0x59801000 0x400>;
	};

	sdctrl@59810000 {
	compatible = "socionext,uniphier-ld20-sdctrl",
	"simple-mfd", "syscon";
	reg = <0x59810000 0x400>;

	sd_clk: clock {
	compatible = "socionext,uniphier-ld20-sd-clock";
	#clock-cells = <1>;
	};

	sd_rst: reset {
	compatible = "socionext,uniphier-ld20-sd-reset";
	#reset-cells = <1>;
	};
	};

	perictrl@59820000 {
	compatible = "socionext,uniphier-ld20-perictrl",
	"simple-mfd", "syscon";
	reg = <0x59820000 0x200>;

	peri_clk: clock {
	compatible = "socionext,uniphier-ld20-peri-clock";
	#clock-cells = <1>;
	};

	peri_rst: reset {
	compatible = "socionext,uniphier-ld20-peri-reset";
	#reset-cells = <1>;
	};
	};

	- emmc: sdhc@5a000000 {
	+ emmc: mmc@5a000000 {
	compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
	reg = <0x5a000000 0x400>;
	interrupts = <0 78 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_emmc>;
	clocks = <&sys_clk 4>;
	resets = <&sys_rst 4>;
	bus-width = <8>;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	mmc-pwrseq = <&emmc_pwrseq>;
	cdns,phy-input-delay-legacy = <9>;
	cdns,phy-input-delay-mmc-highspeed = <2>;
	cdns,phy-input-delay-mmc-ddr = <3>;
	cdns,phy-dll-delay-sdclk = <21>;
	cdns,phy-dll-delay-sdclk-hsmmc = <21>;
	};

	- sd: sdhc@5a400000 {
	+ sd: mmc@5a400000 {
	compatible = "socionext,uniphier-sd-v3.1.1";
	status = "disabled";
	reg = <0x5a400000 0x800>;
	interrupts = <0 76 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sd>;
	clocks = <&sd_clk 0>;
	reset-names = "host";
	resets = <&sd_rst 0>;
	bus-width = <4>;
	cap-sd-highspeed;
	};

	soc_glue: soc-glue@5f800000 {
	compatible = "socionext,uniphier-ld20-soc-glue",
	"simple-mfd", "syscon";
	reg = <0x5f800000 0x2000>;

	pinctrl: pinctrl {
	compatible = "socionext,uniphier-ld20-pinctrl";
	};
	};

	soc-glue@5f900000 {
	compatible = "socionext,uniphier-ld20-soc-glue-debug",
	"simple-mfd";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x5f900000 0x2000>;

	efuse@100 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x100 0x28>;
	};

	efuse@200 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x200 0x68>;
	#address-cells = <1>;
	#size-cells = <1>;

	/* USB cells */
	usb_rterm0: trim@54,4 {
	reg = <0x54 1>;
	bits = <4 2>;
	};
	usb_rterm1: trim@55,4 {
	reg = <0x55 1>;
	bits = <4 2>;
	};
	usb_rterm2: trim@58,4 {
	reg = <0x58 1>;
	bits = <4 2>;
	};
	usb_rterm3: trim@59,4 {
	reg = <0x59 1>;
	bits = <4 2>;
	};
	usb_sel_t0: trim@54,0 {
	reg = <0x54 1>;
	bits = <0 4>;
	};
	usb_sel_t1: trim@55,0 {
	reg = <0x55 1>;
	bits = <0 4>;
	};
	usb_sel_t2: trim@58,0 {
	reg = <0x58 1>;
	bits = <0 4>;
	};
	usb_sel_t3: trim@59,0 {
	reg = <0x59 1>;
	bits = <0 4>;
	};
	usb_hs_i0: trim@56,0 {
	reg = <0x56 1>;
	bits = <0 4>;
	};
	usb_hs_i2: trim@5a,0 {
	reg = <0x5a 1>;
	bits = <0 4>;
	};
	};
	};

	- aidet: aidet@5fc20000 {
	+ aidet: interrupt-controller@5fc20000 {
	compatible = "socionext,uniphier-ld20-aidet";
	reg = <0x5fc20000 0x200>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gic: interrupt-controller@5fe00000 {
	compatible = "arm,gic-v3";
	reg = <0x5fe00000 0x10000>, /* GICD */
	<0x5fe80000 0x80000>; /* GICR */
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupts = <1 9 4>;
	};

	sysctrl@61840000 {
	compatible = "socionext,uniphier-ld20-sysctrl",
	"simple-mfd", "syscon";
	reg = <0x61840000 0x10000>;

	sys_clk: clock {
	compatible = "socionext,uniphier-ld20-clock";
	#clock-cells = <1>;
	};

	sys_rst: reset {
	compatible = "socionext,uniphier-ld20-reset";
	#reset-cells = <1>;
	};

	watchdog {
	compatible = "socionext,uniphier-wdt";
	};

	pvtctl: pvtctl {
	compatible = "socionext,uniphier-ld20-thermal";
	interrupts = <0 3 4>;
	#thermal-sensor-cells = <0>;
	socionext,tmod-calibration = <0x0f22 0x68ee>;
	};
	};

	eth: ethernet@65000000 {
	compatible = "socionext,uniphier-ld20-ave4";
	status = "disabled";
	reg = <0x65000000 0x8500>;
	interrupts = <0 66 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ether_rgmii>;
	clock-names = "ether";
	clocks = <&sys_clk 6>;
	reset-names = "ether";
	resets = <&sys_rst 6>;
	phy-mode = "rgmii";
	local-mac-address = [00 00 00 00 00 00];
	socionext,syscon-phy-mode = <&soc_glue 0>;

	mdio: mdio {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	usb: usb@65a00000 {
	compatible = "socionext,uniphier-dwc3", "snps,dwc3";
	status = "disabled";
	reg = <0x65a00000 0xcd00>;
	interrupt-names = "host";
	interrupts = <0 134 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
	<&pinctrl_usb2>, <&pinctrl_usb3>;
	clock-names = "ref", "bus_early", "suspend";
	clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
	resets = <&usb_rst 15>;
	phys = <&usb_hsphy0>, <&usb_hsphy1>,
	<&usb_hsphy2>, <&usb_hsphy3>,
	<&usb_ssphy0>, <&usb_ssphy1>;
	dr_mode = "host";
	};

	usb-glue@65b00000 {
	compatible = "socionext,uniphier-ld20-dwc3-glue",
	"simple-mfd";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x65b00000 0x400>;

	usb_rst: reset@0 {
	compatible = "socionext,uniphier-ld20-usb3-reset";
	reg = <0x0 0x4>;
	#reset-cells = <1>;
	clock-names = "link";
	clocks = <&sys_clk 14>;
	reset-names = "link";
	resets = <&sys_rst 14>;
	};

	usb_vbus0: regulator@100 {
	compatible = "socionext,uniphier-ld20-usb3-regulator";
	reg = <0x100 0x10>;
	clock-names = "link";
	clocks = <&sys_clk 14>;
	reset-names = "link";
	resets = <&sys_rst 14>;
	};

	usb_vbus1: regulator@110 {
	compatible = "socionext,uniphier-ld20-usb3-regulator";
	reg = <0x110 0x10>;
	clock-names = "link";
	clocks = <&sys_clk 14>;
	reset-names = "link";
	resets = <&sys_rst 14>;
	};

	usb_vbus2: regulator@120 {
	compatible = "socionext,uniphier-ld20-usb3-regulator";
	reg = <0x120 0x10>;
	clock-names = "link";
	clocks = <&sys_clk 14>;
	reset-names = "link";
	resets = <&sys_rst 14>;
	};

	usb_vbus3: regulator@130 {
	compatible = "socionext,uniphier-ld20-usb3-regulator";
	reg = <0x130 0x10>;
	clock-names = "link";
	clocks = <&sys_clk 14>;
	reset-names = "link";
	resets = <&sys_rst 14>;
	};

	usb_hsphy0: hs-phy@200 {
	compatible = "socionext,uniphier-ld20-usb3-hsphy";
	reg = <0x200 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy";
	clocks = <&sys_clk 14>, <&sys_clk 16>;
	reset-names = "link", "phy";
	resets = <&sys_rst 14>, <&sys_rst 16>;
	vbus-supply = <&usb_vbus0>;
	nvmem-cell-names = "rterm", "sel_t", "hs_i";
	nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
	<&usb_hs_i0>;
	};

	usb_hsphy1: hs-phy@210 {
	compatible = "socionext,uniphier-ld20-usb3-hsphy";
	reg = <0x210 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy";
	clocks = <&sys_clk 14>, <&sys_clk 16>;
	reset-names = "link", "phy";
	resets = <&sys_rst 14>, <&sys_rst 16>;
	vbus-supply = <&usb_vbus1>;
	nvmem-cell-names = "rterm", "sel_t", "hs_i";
	nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
	<&usb_hs_i0>;
	};

	usb_hsphy2: hs-phy@220 {
	compatible = "socionext,uniphier-ld20-usb3-hsphy";
	reg = <0x220 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy";
	clocks = <&sys_clk 14>, <&sys_clk 17>;
	reset-names = "link", "phy";
	resets = <&sys_rst 14>, <&sys_rst 17>;
	vbus-supply = <&usb_vbus2>;
	nvmem-cell-names = "rterm", "sel_t", "hs_i";
	nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
	<&usb_hs_i2>;
	};

	usb_hsphy3: hs-phy@230 {
	compatible = "socionext,uniphier-ld20-usb3-hsphy";
	reg = <0x230 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy";
	clocks = <&sys_clk 14>, <&sys_clk 17>;
	reset-names = "link", "phy";
	resets = <&sys_rst 14>, <&sys_rst 17>;
	vbus-supply = <&usb_vbus3>;
	nvmem-cell-names = "rterm", "sel_t", "hs_i";
	nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
	<&usb_hs_i2>;
	};

	usb_ssphy0: ss-phy@300 {
	compatible = "socionext,uniphier-ld20-usb3-ssphy";
	reg = <0x300 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy";
	clocks = <&sys_clk 14>, <&sys_clk 18>;
	reset-names = "link", "phy";
	resets = <&sys_rst 14>, <&sys_rst 18>;
	vbus-supply = <&usb_vbus0>;
	};

	usb_ssphy1: ss-phy@310 {
	compatible = "socionext,uniphier-ld20-usb3-ssphy";
	reg = <0x310 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy";
	clocks = <&sys_clk 14>, <&sys_clk 19>;
	reset-names = "link", "phy";
	resets = <&sys_rst 14>, <&sys_rst 19>;
	vbus-supply = <&usb_vbus1>;
	};
	};

	pcie: pcie@66000000 {
	compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
	status = "disabled";
	reg-names = "dbi", "link", "config";
	reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
	<0x2fff0000 0x10000>;
	#address-cells = <3>;
	#size-cells = <2>;
	clocks = <&sys_clk 24>;
	resets = <&sys_rst 24>;
	num-lanes = <1>;
	num-viewport = <1>;
	bus-range = <0x0 0xff>;
	device_type = "pci";
	ranges =
	/* downstream I/O */
	<0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
	/* non-prefetchable memory */
	<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
	#interrupt-cells = <1>;
	interrupt-names = "dma", "msi";
	interrupts = <0 224 4>, <0 225 4>;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
	<0 0 0 2 &pcie_intc 1>, /* INTB */
	<0 0 0 3 &pcie_intc 2>, /* INTC */
	<0 0 0 4 &pcie_intc 3>; /* INTD */
	phy-names = "pcie-phy";
	phys = <&pcie_phy>;

	pcie_intc: legacy-interrupt-controller {
	interrupt-controller;
	#interrupt-cells = <1>;
	interrupt-parent = <&gic>;
	interrupts = <0 226 4>;
	};
	};

	pcie_phy: phy@66038000 {
	compatible = "socionext,uniphier-ld20-pcie-phy";
	reg = <0x66038000 0x4000>;
	#phy-cells = <0>;
	clocks = <&sys_clk 24>;
	resets = <&sys_rst 24>;
	socionext,syscon = <&soc_glue>;
	};

	- nand: nand@68000000 {
	+ nand: nand-controller@68000000 {
	compatible = "socionext,uniphier-denali-nand-v5b";
	status = "disabled";
	reg-names = "nand_data", "denali_reg";
	reg = <0x68000000 0x20>, <0x68100000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 65 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nand>;
	clock-names = "nand", "nand_x", "ecc";
	clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
	reset-names = "nand", "reg";
	resets = <&sys_rst 2>, <&sys_rst 2>;
	};
	};
	};

	#include "uniphier-pinctrl.dtsi"

	&pinctrl_aout1 {
	drive-strength = <4>; /* default: 3.5mA */

	ao1dacck {
	pins = "AO1DACCK";
	drive-strength = <5>; /* 5mA */
	};
	};

	&pinctrl_aoutiec1 {
	drive-strength = <4>; /* default: 3.5mA */

	ao1arc {
	pins = "AO1ARC";
	drive-strength = <11>; /* 11mA */
	};
	};
	diff --git a/sys/gnu/dts/arm64/socionext/uniphier-pxs3-ref.dts b/sys/gnu/dts/arm64/socionext/uniphier-pxs3-ref.dts
	index 754315bbd1c8..4d00ff9548e1 100644
	--- a/sys/gnu/dts/arm64/socionext/uniphier-pxs3-ref.dts
	+++ b/sys/gnu/dts/arm64/socionext/uniphier-pxs3-ref.dts
	@@ -1,122 +1,132 @@
	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	//
	// Device Tree Source for UniPhier PXs3 Reference Board
	//
	// Copyright (C) 2017 Socionext Inc.
	// Author: Masahiro Yamada <yamada.masahiro@socionext.com>

	/dts-v1/;
	#include "uniphier-pxs3.dtsi"
	#include "uniphier-support-card.dtsi"

	/ {
	model = "UniPhier PXs3 Reference Board";
	compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";

	chosen {
	stdout-path = "serial0:115200n8";
	};

	aliases {
	serial0 = &serial0;
	serial1 = &serial1;
	serial2 = &serial2;
	serial3 = &serial3;
	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;
	i2c6 = &i2c6;
	+ spi0 = &spi0;
	+ spi1 = &spi1;
	};

	memory@80000000 {
	device_type = "memory";
	reg = <0 0x80000000 0 0xa0000000>;
	};
	};

	&ethsc {
	interrupts = <4 8>;
	};

	+&spi0 {
	+ status = "okay";
	+};
	+
	+&spi1 {
	+ status = "okay";
	+};
	+
	&serial0 {
	status = "okay";
	};

	&serial2 {
	status = "okay";
	};

	&serial3 {
	status = "okay";
	};

	&gpio {
	xirq4 {
	gpio-hog;
	gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
	input;
	};
	};

	&i2c0 {
	status = "okay";
	};

	&i2c1 {
	status = "okay";
	};

	&i2c2 {
	status = "okay";
	};

	&i2c3 {
	status = "okay";
	};

	&sd {
	status = "okay";
	};

	&eth0 {
	status = "okay";
	phy-handle = <&ethphy0>;
	};

	&mdio0 {
	ethphy0: ethphy@0 {
	reg = <0>;
	};
	};

	&eth1 {
	status = "okay";
	phy-handle = <&ethphy1>;
	};

	&mdio1 {
	ethphy1: ethphy@0 {
	reg = <0>;
	};
	};

	&usb0 {
	status = "okay";
	};

	&usb1 {
	status = "okay";
	};

	&pcie {
	status = "okay";
	};

	&nand {
	status = "okay";

	nand@0 {
	reg = <0>;
	};
	};
	diff --git a/sys/gnu/dts/arm64/socionext/uniphier-pxs3.dtsi b/sys/gnu/dts/arm64/socionext/uniphier-pxs3.dtsi
	index 73e7e1203b09..616835b38106 100644
	--- a/sys/gnu/dts/arm64/socionext/uniphier-pxs3.dtsi
	+++ b/sys/gnu/dts/arm64/socionext/uniphier-pxs3.dtsi
	@@ -1,804 +1,847 @@
	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	//
	// Device Tree Source for UniPhier PXs3 SoC
	//
	// Copyright (C) 2017 Socionext Inc.
	// Author: Masahiro Yamada <yamada.masahiro@socionext.com>

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/gpio/uniphier-gpio.h>
	+#include <dt-bindings/thermal/thermal.h>

	/ {
	compatible = "socionext,uniphier-pxs3";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	cpu-map {
	cluster0 {
	core0 {
	cpu = <&cpu0>;
	};
	core1 {
	cpu = <&cpu1>;
	};
	core2 {
	cpu = <&cpu2>;
	};
	core3 {
	cpu = <&cpu3>;
	};
	};
	};

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0 0x000>;
	clocks = <&sys_clk 33>;
	enable-method = "psci";
	operating-points-v2 = <&cluster0_opp>;
	+ #cooling-cells = <2>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0 0x001>;
	clocks = <&sys_clk 33>;
	enable-method = "psci";
	operating-points-v2 = <&cluster0_opp>;
	+ #cooling-cells = <2>;
	};

	cpu2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0 0x002>;
	clocks = <&sys_clk 33>;
	enable-method = "psci";
	operating-points-v2 = <&cluster0_opp>;
	+ #cooling-cells = <2>;
	};

	cpu3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0 0x003>;
	clocks = <&sys_clk 33>;
	enable-method = "psci";
	operating-points-v2 = <&cluster0_opp>;
	+ #cooling-cells = <2>;
	};
	};

	cluster0_opp: opp-table {
	compatible = "operating-points-v2";
	opp-shared;

	opp-250000000 {
	opp-hz = /bits/ 64 <250000000>;
	clock-latency-ns = <300>;
	};
	opp-325000000 {
	opp-hz = /bits/ 64 <325000000>;
	clock-latency-ns = <300>;
	};
	opp-500000000 {
	opp-hz = /bits/ 64 <500000000>;
	clock-latency-ns = <300>;
	};
	opp-650000000 {
	opp-hz = /bits/ 64 <650000000>;
	clock-latency-ns = <300>;
	};
	opp-666667000 {
	opp-hz = /bits/ 64 <666667000>;
	clock-latency-ns = <300>;
	};
	opp-866667000 {
	opp-hz = /bits/ 64 <866667000>;
	clock-latency-ns = <300>;
	};
	opp-1000000000 {
	opp-hz = /bits/ 64 <1000000000>;
	clock-latency-ns = <300>;
	};
	opp-1300000000 {
	opp-hz = /bits/ 64 <1300000000>;
	clock-latency-ns = <300>;
	};
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	clocks {
	refclk: ref {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <25000000>;
	};
	};

	emmc_pwrseq: emmc-pwrseq {
	compatible = "mmc-pwrseq-emmc";
	reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <1 13 4>,
	<1 14 4>,
	<1 11 4>,
	<1 10 4>;
	};

	+ thermal-zones {
	+ cpu-thermal {
	+ polling-delay-passive = <250>; /* 250ms */
	+ polling-delay = <1000>; /* 1000ms */
	+ thermal-sensors = <&pvtctl>;
	+
	+ trips {
	+ cpu_crit: cpu-crit {
	+ temperature = <110000>; /* 110C */
	+ hysteresis = <2000>;
	+ type = "critical";
	+ };
	+ cpu_alert: cpu-alert {
	+ temperature = <100000>; /* 100C */
	+ hysteresis = <2000>;
	+ type = "passive";
	+ };
	+ };
	+
	+ cooling-maps {
	+ map0 {
	+ trip = <&cpu_alert>;
	+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	+ };
	+ };
	+ };
	+ };
	+
	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	secure-memory@81000000 {
	reg = <0x0 0x81000000 0x0 0x01000000>;
	no-map;
	};
	};

	soc@0 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;

	spi0: spi@54006000 {
	compatible = "socionext,uniphier-scssi";
	status = "disabled";
	reg = <0x54006000 0x100>;
	interrupts = <0 39 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi0>;
	clocks = <&peri_clk 11>;
	resets = <&peri_rst 11>;
	};

	spi1: spi@54006100 {
	compatible = "socionext,uniphier-scssi";
	status = "disabled";
	reg = <0x54006100 0x100>;
	interrupts = <0 216 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi1>;
	- clocks = <&peri_clk 11>;
	- resets = <&peri_rst 11>;
	+ clocks = <&peri_clk 12>;
	+ resets = <&peri_rst 12>;
	};

	serial0: serial@54006800 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006800 0x40>;
	interrupts = <0 33 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	clocks = <&peri_clk 0>;
	resets = <&peri_rst 0>;
	};

	serial1: serial@54006900 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006900 0x40>;
	interrupts = <0 35 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	clocks = <&peri_clk 1>;
	resets = <&peri_rst 1>;
	};

	serial2: serial@54006a00 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006a00 0x40>;
	interrupts = <0 37 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	clocks = <&peri_clk 2>;
	resets = <&peri_rst 2>;
	};

	serial3: serial@54006b00 {
	compatible = "socionext,uniphier-uart";
	status = "disabled";
	reg = <0x54006b00 0x40>;
	interrupts = <0 177 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	clocks = <&peri_clk 3>;
	resets = <&peri_rst 3>;
	};

	gpio: gpio@55000000 {
	compatible = "socionext,uniphier-gpio";
	reg = <0x55000000 0x200>;
	interrupt-parent = <&aidet>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl 0 0 0>,
	<&pinctrl 104 0 0>,
	<&pinctrl 168 0 0>;
	gpio-ranges-group-names = "gpio_range0",
	"gpio_range1",
	"gpio_range2";
	ngpios = <286>;
	socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
	<21 217 3>;
	};

	i2c0: i2c@58780000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58780000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 41 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	clocks = <&peri_clk 4>;
	resets = <&peri_rst 4>;
	clock-frequency = <100000>;
	};

	i2c1: i2c@58781000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58781000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 42 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	clocks = <&peri_clk 5>;
	resets = <&peri_rst 5>;
	clock-frequency = <100000>;
	};

	i2c2: i2c@58782000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58782000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 43 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	clocks = <&peri_clk 6>;
	resets = <&peri_rst 6>;
	clock-frequency = <100000>;
	};

	i2c3: i2c@58783000 {
	compatible = "socionext,uniphier-fi2c";
	status = "disabled";
	reg = <0x58783000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 44 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	clocks = <&peri_clk 7>;
	resets = <&peri_rst 7>;
	clock-frequency = <100000>;
	};

	/* chip-internal connection for HDMI */
	i2c6: i2c@58786000 {
	compatible = "socionext,uniphier-fi2c";
	reg = <0x58786000 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 26 4>;
	clocks = <&peri_clk 10>;
	resets = <&peri_rst 10>;
	clock-frequency = <400000>;
	};

	system_bus: system-bus@58c00000 {
	compatible = "socionext,uniphier-system-bus";
	status = "disabled";
	reg = <0x58c00000 0x400>;
	#address-cells = <2>;
	#size-cells = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_system_bus>;
	};

	smpctrl@59801000 {
	compatible = "socionext,uniphier-smpctrl";
	reg = <0x59801000 0x400>;
	};

	sdctrl@59810000 {
	compatible = "socionext,uniphier-pxs3-sdctrl",
	"simple-mfd", "syscon";
	reg = <0x59810000 0x400>;

	sd_clk: clock {
	compatible = "socionext,uniphier-pxs3-sd-clock";
	#clock-cells = <1>;
	};

	sd_rst: reset {
	compatible = "socionext,uniphier-pxs3-sd-reset";
	#reset-cells = <1>;
	};
	};

	perictrl@59820000 {
	compatible = "socionext,uniphier-pxs3-perictrl",
	"simple-mfd", "syscon";
	reg = <0x59820000 0x200>;

	peri_clk: clock {
	compatible = "socionext,uniphier-pxs3-peri-clock";
	#clock-cells = <1>;
	};

	peri_rst: reset {
	compatible = "socionext,uniphier-pxs3-peri-reset";
	#reset-cells = <1>;
	};
	};

	- emmc: sdhc@5a000000 {
	+ emmc: mmc@5a000000 {
	compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
	reg = <0x5a000000 0x400>;
	interrupts = <0 78 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_emmc>;
	clocks = <&sys_clk 4>;
	resets = <&sys_rst 4>;
	bus-width = <8>;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	mmc-pwrseq = <&emmc_pwrseq>;
	cdns,phy-input-delay-legacy = <9>;
	cdns,phy-input-delay-mmc-highspeed = <2>;
	cdns,phy-input-delay-mmc-ddr = <3>;
	cdns,phy-dll-delay-sdclk = <21>;
	cdns,phy-dll-delay-sdclk-hsmmc = <21>;
	};

	- sd: sdhc@5a400000 {
	+ sd: mmc@5a400000 {
	compatible = "socionext,uniphier-sd-v3.1.1";
	status = "disabled";
	reg = <0x5a400000 0x800>;
	interrupts = <0 76 4>;
	pinctrl-names = "default", "uhs";
	pinctrl-0 = <&pinctrl_sd>;
	pinctrl-1 = <&pinctrl_sd_uhs>;
	clocks = <&sd_clk 0>;
	reset-names = "host";
	resets = <&sd_rst 0>;
	bus-width = <4>;
	cap-sd-highspeed;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	};

	soc_glue: soc-glue@5f800000 {
	compatible = "socionext,uniphier-pxs3-soc-glue",
	"simple-mfd", "syscon";
	reg = <0x5f800000 0x2000>;

	pinctrl: pinctrl {
	compatible = "socionext,uniphier-pxs3-pinctrl";
	};
	};

	soc-glue@5f900000 {
	compatible = "socionext,uniphier-pxs3-soc-glue-debug",
	"simple-mfd";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x5f900000 0x2000>;

	efuse@100 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x100 0x28>;
	};

	efuse@200 {
	compatible = "socionext,uniphier-efuse";
	reg = <0x200 0x68>;
	#address-cells = <1>;
	#size-cells = <1>;

	/* USB cells */
	usb_rterm0: trim@54,4 {
	reg = <0x54 1>;
	bits = <4 2>;
	};
	usb_rterm1: trim@55,4 {
	reg = <0x55 1>;
	bits = <4 2>;
	};
	usb_rterm2: trim@58,4 {
	reg = <0x58 1>;
	bits = <4 2>;
	};
	usb_rterm3: trim@59,4 {
	reg = <0x59 1>;
	bits = <4 2>;
	};
	usb_sel_t0: trim@54,0 {
	reg = <0x54 1>;
	bits = <0 4>;
	};
	usb_sel_t1: trim@55,0 {
	reg = <0x55 1>;
	bits = <0 4>;
	};
	usb_sel_t2: trim@58,0 {
	reg = <0x58 1>;
	bits = <0 4>;
	};
	usb_sel_t3: trim@59,0 {
	reg = <0x59 1>;
	bits = <0 4>;
	};
	usb_hs_i0: trim@56,0 {
	reg = <0x56 1>;
	bits = <0 4>;
	};
	usb_hs_i2: trim@5a,0 {
	reg = <0x5a 1>;
	bits = <0 4>;
	};
	};
	};

	- aidet: aidet@5fc20000 {
	+ aidet: interrupt-controller@5fc20000 {
	compatible = "socionext,uniphier-pxs3-aidet";
	reg = <0x5fc20000 0x200>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gic: interrupt-controller@5fe00000 {
	compatible = "arm,gic-v3";
	reg = <0x5fe00000 0x10000>, /* GICD */
	<0x5fe80000 0x80000>; /* GICR */
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupts = <1 9 4>;
	};

	sysctrl@61840000 {
	compatible = "socionext,uniphier-pxs3-sysctrl",
	"simple-mfd", "syscon";
	reg = <0x61840000 0x10000>;

	sys_clk: clock {
	compatible = "socionext,uniphier-pxs3-clock";
	#clock-cells = <1>;
	};

	sys_rst: reset {
	compatible = "socionext,uniphier-pxs3-reset";
	#reset-cells = <1>;
	};

	watchdog {
	compatible = "socionext,uniphier-wdt";
	};
	+
	+ pvtctl: pvtctl {
	+ compatible = "socionext,uniphier-pxs3-thermal";
	+ interrupts = <0 3 4>;
	+ #thermal-sensor-cells = <0>;
	+ socionext,tmod-calibration = <0x0f22 0x68ee>;
	+ };
	};

	eth0: ethernet@65000000 {
	compatible = "socionext,uniphier-pxs3-ave4";
	status = "disabled";
	reg = <0x65000000 0x8500>;
	interrupts = <0 66 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ether_rgmii>;
	clock-names = "ether";
	clocks = <&sys_clk 6>;
	reset-names = "ether";
	resets = <&sys_rst 6>;
	phy-mode = "rgmii";
	local-mac-address = [00 00 00 00 00 00];
	socionext,syscon-phy-mode = <&soc_glue 0>;

	mdio0: mdio {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	eth1: ethernet@65200000 {
	compatible = "socionext,uniphier-pxs3-ave4";
	status = "disabled";
	reg = <0x65200000 0x8500>;
	interrupts = <0 67 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ether1_rgmii>;
	clock-names = "ether";
	clocks = <&sys_clk 7>;
	reset-names = "ether";
	resets = <&sys_rst 7>;
	phy-mode = "rgmii";
	local-mac-address = [00 00 00 00 00 00];
	socionext,syscon-phy-mode = <&soc_glue 1>;

	mdio1: mdio {
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	usb0: usb@65a00000 {
	compatible = "socionext,uniphier-dwc3", "snps,dwc3";
	status = "disabled";
	reg = <0x65a00000 0xcd00>;
	interrupt-names = "host", "peripheral";
	interrupts = <0 134 4>, <0 135 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
	clock-names = "ref", "bus_early", "suspend";
	clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
	resets = <&usb0_rst 15>;
	phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
	<&usb0_ssphy0>, <&usb0_ssphy1>;
	dr_mode = "host";
	};

	usb-glue@65b00000 {
	compatible = "socionext,uniphier-pxs3-dwc3-glue",
	"simple-mfd";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x65b00000 0x400>;

	usb0_rst: reset@0 {
	compatible = "socionext,uniphier-pxs3-usb3-reset";
	reg = <0x0 0x4>;
	#reset-cells = <1>;
	clock-names = "link";
	clocks = <&sys_clk 12>;
	reset-names = "link";
	resets = <&sys_rst 12>;
	};

	usb0_vbus0: regulator@100 {
	compatible = "socionext,uniphier-pxs3-usb3-regulator";
	reg = <0x100 0x10>;
	clock-names = "link";
	clocks = <&sys_clk 12>;
	reset-names = "link";
	resets = <&sys_rst 12>;
	};

	usb0_vbus1: regulator@110 {
	compatible = "socionext,uniphier-pxs3-usb3-regulator";
	reg = <0x110 0x10>;
	clock-names = "link";
	clocks = <&sys_clk 12>;
	reset-names = "link";
	resets = <&sys_rst 12>;
	};

	usb0_hsphy0: hs-phy@200 {
	compatible = "socionext,uniphier-pxs3-usb3-hsphy";
	reg = <0x200 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy";
	clocks = <&sys_clk 12>, <&sys_clk 16>;
	reset-names = "link", "phy";
	resets = <&sys_rst 12>, <&sys_rst 16>;
	vbus-supply = <&usb0_vbus0>;
	nvmem-cell-names = "rterm", "sel_t", "hs_i";
	nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
	<&usb_hs_i0>;
	};

	usb0_hsphy1: hs-phy@210 {
	compatible = "socionext,uniphier-pxs3-usb3-hsphy";
	reg = <0x210 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy";
	clocks = <&sys_clk 12>, <&sys_clk 16>;
	reset-names = "link", "phy";
	resets = <&sys_rst 12>, <&sys_rst 16>;
	vbus-supply = <&usb0_vbus1>;
	nvmem-cell-names = "rterm", "sel_t", "hs_i";
	nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
	<&usb_hs_i0>;
	};

	usb0_ssphy0: ss-phy@300 {
	compatible = "socionext,uniphier-pxs3-usb3-ssphy";
	reg = <0x300 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy";
	clocks = <&sys_clk 12>, <&sys_clk 17>;
	reset-names = "link", "phy";
	resets = <&sys_rst 12>, <&sys_rst 17>;
	vbus-supply = <&usb0_vbus0>;
	};

	usb0_ssphy1: ss-phy@310 {
	compatible = "socionext,uniphier-pxs3-usb3-ssphy";
	reg = <0x310 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy";
	clocks = <&sys_clk 12>, <&sys_clk 18>;
	reset-names = "link", "phy";
	resets = <&sys_rst 12>, <&sys_rst 18>;
	vbus-supply = <&usb0_vbus1>;
	};
	};

	usb1: usb@65c00000 {
	compatible = "socionext,uniphier-dwc3", "snps,dwc3";
	status = "disabled";
	reg = <0x65c00000 0xcd00>;
	interrupt-names = "host", "peripheral";
	interrupts = <0 137 4>, <0 138 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
	clock-names = "ref", "bus_early", "suspend";
	clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
	resets = <&usb1_rst 15>;
	phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
	<&usb1_ssphy0>;
	dr_mode = "host";
	};

	usb-glue@65d00000 {
	compatible = "socionext,uniphier-pxs3-dwc3-glue",
	"simple-mfd";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x65d00000 0x400>;

	usb1_rst: reset@0 {
	compatible = "socionext,uniphier-pxs3-usb3-reset";
	reg = <0x0 0x4>;
	#reset-cells = <1>;
	clock-names = "link";
	clocks = <&sys_clk 13>;
	reset-names = "link";
	resets = <&sys_rst 13>;
	};

	usb1_vbus0: regulator@100 {
	compatible = "socionext,uniphier-pxs3-usb3-regulator";
	reg = <0x100 0x10>;
	clock-names = "link";
	clocks = <&sys_clk 13>;
	reset-names = "link";
	resets = <&sys_rst 13>;
	};

	usb1_vbus1: regulator@110 {
	compatible = "socionext,uniphier-pxs3-usb3-regulator";
	reg = <0x110 0x10>;
	clock-names = "link";
	clocks = <&sys_clk 13>;
	reset-names = "link";
	resets = <&sys_rst 13>;
	};

	usb1_hsphy0: hs-phy@200 {
	compatible = "socionext,uniphier-pxs3-usb3-hsphy";
	reg = <0x200 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy", "phy-ext";
	clocks = <&sys_clk 13>, <&sys_clk 20>,
	<&sys_clk 14>;
	reset-names = "link", "phy";
	resets = <&sys_rst 13>, <&sys_rst 20>;
	vbus-supply = <&usb1_vbus0>;
	nvmem-cell-names = "rterm", "sel_t", "hs_i";
	nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
	<&usb_hs_i2>;
	};

	usb1_hsphy1: hs-phy@210 {
	compatible = "socionext,uniphier-pxs3-usb3-hsphy";
	reg = <0x210 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy", "phy-ext";
	clocks = <&sys_clk 13>, <&sys_clk 20>,
	<&sys_clk 14>;
	reset-names = "link", "phy";
	resets = <&sys_rst 13>, <&sys_rst 20>;
	vbus-supply = <&usb1_vbus1>;
	nvmem-cell-names = "rterm", "sel_t", "hs_i";
	nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
	<&usb_hs_i2>;
	};

	usb1_ssphy0: ss-phy@300 {
	compatible = "socionext,uniphier-pxs3-usb3-ssphy";
	reg = <0x300 0x10>;
	#phy-cells = <0>;
	clock-names = "link", "phy", "phy-ext";
	clocks = <&sys_clk 13>, <&sys_clk 21>,
	<&sys_clk 14>;
	reset-names = "link", "phy";
	resets = <&sys_rst 13>, <&sys_rst 21>;
	vbus-supply = <&usb1_vbus0>;
	};
	};

	pcie: pcie@66000000 {
	compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
	status = "disabled";
	reg-names = "dbi", "link", "config";
	reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
	<0x2fff0000 0x10000>;
	#address-cells = <3>;
	#size-cells = <2>;
	clocks = <&sys_clk 24>;
	resets = <&sys_rst 24>;
	num-lanes = <1>;
	num-viewport = <1>;
	bus-range = <0x0 0xff>;
	device_type = "pci";
	ranges =
	/* downstream I/O */
	<0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
	/* non-prefetchable memory */
	<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
	#interrupt-cells = <1>;
	interrupt-names = "dma", "msi";
	interrupts = <0 224 4>, <0 225 4>;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
	<0 0 0 2 &pcie_intc 1>, /* INTB */
	<0 0 0 3 &pcie_intc 2>, /* INTC */
	<0 0 0 4 &pcie_intc 3>; /* INTD */
	phy-names = "pcie-phy";
	phys = <&pcie_phy>;

	pcie_intc: legacy-interrupt-controller {
	interrupt-controller;
	#interrupt-cells = <1>;
	interrupt-parent = <&gic>;
	interrupts = <0 226 4>;
	};
	};

	pcie_phy: phy@66038000 {
	compatible = "socionext,uniphier-pxs3-pcie-phy";
	reg = <0x66038000 0x4000>;
	#phy-cells = <0>;
	clocks = <&sys_clk 24>;
	resets = <&sys_rst 24>;
	socionext,syscon = <&soc_glue>;
	};

	- nand: nand@68000000 {
	+ nand: nand-controller@68000000 {
	compatible = "socionext,uniphier-denali-nand-v5b";
	status = "disabled";
	reg-names = "nand_data", "denali_reg";
	reg = <0x68000000 0x20>, <0x68100000 0x1000>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <0 65 4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nand>;
	clock-names = "nand", "nand_x", "ecc";
	clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
	reset-names = "nand", "reg";
	resets = <&sys_rst 2>, <&sys_rst 2>;
	};
	};
	};

	#include "uniphier-pinctrl.dtsi"
	diff --git a/sys/gnu/dts/arm64/ti/k3-am65-main.dtsi b/sys/gnu/dts/arm64/ti/k3-am65-main.dtsi
	index e5df20a2d2f9..11887c72f23a 100644
	--- a/sys/gnu/dts/arm64/ti/k3-am65-main.dtsi
	+++ b/sys/gnu/dts/arm64/ti/k3-am65-main.dtsi
	@@ -1,745 +1,749 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for AM6 SoC Family Main Domain peripherals
	*
	* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
	*/
	#include <dt-bindings/phy/phy-am654-serdes.h>

	&cbass_main {
	msmc_ram: sram@70000000 {
	compatible = "mmio-sram";
	reg = <0x0 0x70000000 0x0 0x200000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x70000000 0x200000>;

	atf-sram@0 {
	reg = <0x0 0x20000>;
	};

	sysfw-sram@f0000 {
	reg = <0xf0000 0x10000>;
	};

	l3cache-sram@100000 {
	reg = <0x100000 0x100000>;
	};
	};

	gic500: interrupt-controller@1800000 {
	compatible = "arm,gic-v3";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
	<0x00 0x01880000 0x00 0x90000>; /* GICR */
	/*
	* vcpumntirq:
	* virtual CPU interface maintenance interrupt
	*/
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

	gic_its: gic-its@1820000 {
	compatible = "arm,gic-v3-its";
	reg = <0x00 0x01820000 0x00 0x10000>;
	socionext,synquacer-pre-its = <0x1000000 0x400000>;
	msi-controller;
	#msi-cells = <1>;
	};
	};

	serdes0: serdes@900000 {
	compatible = "ti,phy-am654-serdes";
	reg = <0x0 0x900000 0x0 0x2000>;
	reg-names = "serdes";
	#phy-cells = <2>;
	power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
	clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
	clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
	assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
	assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
	ti,serdes-clk = <&serdes0_clk>;
	#clock-cells = <1>;
	mux-controls = <&serdes_mux 0>;
	};

	serdes1: serdes@910000 {
	compatible = "ti,phy-am654-serdes";
	reg = <0x0 0x910000 0x0 0x2000>;
	reg-names = "serdes";
	#phy-cells = <2>;
	power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
	clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
	clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
	assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
	assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
	ti,serdes-clk = <&serdes1_clk>;
	#clock-cells = <1>;
	mux-controls = <&serdes_mux 1>;
	};

	main_uart0: serial@2800000 {
	compatible = "ti,am654-uart";
	reg = <0x00 0x02800000 0x00 0x100>;
	reg-shift = <2>;
	reg-io-width = <4>;
	interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <48000000>;
	current-speed = <115200>;
	power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart1: serial@2810000 {
	compatible = "ti,am654-uart";
	reg = <0x00 0x02810000 0x00 0x100>;
	reg-shift = <2>;
	reg-io-width = <4>;
	interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <48000000>;
	power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart2: serial@2820000 {
	compatible = "ti,am654-uart";
	reg = <0x00 0x02820000 0x00 0x100>;
	reg-shift = <2>;
	reg-io-width = <4>;
	interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <48000000>;
	power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
	};

	main_pmx0: pinmux@11c000 {
	compatible = "pinctrl-single";
	reg = <0x0 0x11c000 0x0 0x2e4>;
	#pinctrl-cells = <1>;
	pinctrl-single,register-width = <32>;
	pinctrl-single,function-mask = <0xffffffff>;
	};

	main_pmx1: pinmux@11c2e8 {
	compatible = "pinctrl-single";
	reg = <0x0 0x11c2e8 0x0 0x24>;
	#pinctrl-cells = <1>;
	pinctrl-single,register-width = <32>;
	pinctrl-single,function-mask = <0xffffffff>;
	};

	main_i2c0: i2c@2000000 {
	compatible = "ti,am654-i2c", "ti,omap4-i2c";
	reg = <0x0 0x2000000 0x0 0x100>;
	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "fck";
	clocks = <&k3_clks 110 1>;
	power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c1: i2c@2010000 {
	compatible = "ti,am654-i2c", "ti,omap4-i2c";
	reg = <0x0 0x2010000 0x0 0x100>;
	interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "fck";
	clocks = <&k3_clks 111 1>;
	power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c2: i2c@2020000 {
	compatible = "ti,am654-i2c", "ti,omap4-i2c";
	reg = <0x0 0x2020000 0x0 0x100>;
	interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "fck";
	clocks = <&k3_clks 112 1>;
	power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c3: i2c@2030000 {
	compatible = "ti,am654-i2c", "ti,omap4-i2c";
	reg = <0x0 0x2030000 0x0 0x100>;
	interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "fck";
	clocks = <&k3_clks 113 1>;
	power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
	};

	ecap0: pwm@3100000 {
	compatible = "ti,am654-ecap", "ti,am3352-ecap";
	#pwm-cells = <3>;
	reg = <0x0 0x03100000 0x0 0x60>;
	power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
	clocks = <&k3_clks 39 0>;
	clock-names = "fck";
	};

	main_spi0: spi@2100000 {
	compatible = "ti,am654-mcspi","ti,omap4-mcspi";
	reg = <0x0 0x2100000 0x0 0x400>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&k3_clks 137 1>;
	power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
	#address-cells = <1>;
	#size-cells = <0>;
	+ dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
	+ dma-names = "tx0", "rx0";
	};

	main_spi1: spi@2110000 {
	compatible = "ti,am654-mcspi","ti,omap4-mcspi";
	reg = <0x0 0x2110000 0x0 0x400>;
	interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&k3_clks 138 1>;
	power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
	#address-cells = <1>;
	#size-cells = <0>;
	assigned-clocks = <&k3_clks 137 1>;
	assigned-clock-rates = <48000000>;
	};

	main_spi2: spi@2120000 {
	compatible = "ti,am654-mcspi","ti,omap4-mcspi";
	reg = <0x0 0x2120000 0x0 0x400>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&k3_clks 139 1>;
	power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	main_spi3: spi@2130000 {
	compatible = "ti,am654-mcspi","ti,omap4-mcspi";
	reg = <0x0 0x2130000 0x0 0x400>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&k3_clks 140 1>;
	power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	main_spi4: spi@2140000 {
	compatible = "ti,am654-mcspi","ti,omap4-mcspi";
	reg = <0x0 0x2140000 0x0 0x400>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&k3_clks 141 1>;
	power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	sdhci0: sdhci@4f80000 {
	compatible = "ti,am654-sdhci-5.1";
	reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
	power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
	clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
	clock-names = "clk_ahb", "clk_xin";
	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	ti,otap-del-sel = <0x2>;
	ti,trm-icp = <0x8>;
	dma-coherent;
	};

	scm_conf: scm_conf@100000 {
	compatible = "syscon", "simple-mfd";
	reg = <0 0x00100000 0 0x1c000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x00100000 0x1c000>;

	pcie0_mode: pcie-mode@4060 {
	compatible = "syscon";
	reg = <0x00004060 0x4>;
	};

	pcie1_mode: pcie-mode@4070 {
	compatible = "syscon";
	reg = <0x00004070 0x4>;
	};

	pcie_devid: pcie-devid@210 {
	compatible = "syscon";
	reg = <0x00000210 0x4>;
	};

	serdes0_clk: serdes_clk@4080 {
	compatible = "syscon";
	reg = <0x00004080 0x4>;
	};

	serdes1_clk: serdes_clk@4090 {
	compatible = "syscon";
	reg = <0x00004090 0x4>;
	};

	serdes_mux: mux-controller {
	compatible = "mmio-mux";
	#mux-control-cells = <1>;
	mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
	<0x4090 0x3>; /* SERDES1 lane select */
	};
	};

	dwc3_0: dwc3@4000000 {
	compatible = "ti,am654-dwc3";
	reg = <0x0 0x4000000 0x0 0x4000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x4000000 0x20000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	dma-coherent;
	power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
	+ clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
	assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
	assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
	<&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */

	usb0: usb@10000 {
	compatible = "snps,dwc3";
	reg = <0x10000 0x10000>;
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "peripheral",
	"host",
	"otg";
	maximum-speed = "high-speed";
	dr_mode = "otg";
	phys = <&usb0_phy>;
	phy-names = "usb2-phy";
	snps,dis_u3_susphy_quirk;
	};
	};

	usb0_phy: phy@4100000 {
	compatible = "ti,am654-usb2", "ti,omap-usb2";
	reg = <0x0 0x4100000 0x0 0x54>;
	syscon-phy-power = <&scm_conf 0x4000>;
	clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
	clock-names = "wkupclk", "refclk";
	#phy-cells = <0>;
	};

	dwc3_1: dwc3@4020000 {
	compatible = "ti,am654-dwc3";
	reg = <0x0 0x4020000 0x0 0x4000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x4020000 0x20000>;
	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	dma-coherent;
	power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
	+ clocks = <&k3_clks 152 2>;
	assigned-clocks = <&k3_clks 152 2>;
	assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */

	usb1: usb@10000 {
	compatible = "snps,dwc3";
	reg = <0x10000 0x10000>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "peripheral",
	"host",
	"otg";
	maximum-speed = "high-speed";
	dr_mode = "otg";
	phys = <&usb1_phy>;
	phy-names = "usb2-phy";
	};
	};

	usb1_phy: phy@4110000 {
	compatible = "ti,am654-usb2", "ti,omap-usb2";
	reg = <0x0 0x4110000 0x0 0x54>;
	syscon-phy-power = <&scm_conf 0x4020>;
	clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
	clock-names = "wkupclk", "refclk";
	#phy-cells = <0>;
	};

	intr_main_gpio: interrupt-controller0 {
	compatible = "ti,sci-intr";
	ti,intr-trigger-type = <1>;
	interrupt-controller;
	interrupt-parent = <&gic500>;
	#interrupt-cells = <2>;
	ti,sci = <&dmsc>;
	ti,sci-dst-id = <56>;
	ti,sci-rm-range-girq = <0x1>;
	};

	main_navss {
	compatible = "simple-mfd";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	dma-coherent;
	dma-ranges;

	ti,sci-dev-id = <118>;

	intr_main_navss: interrupt-controller1 {
	compatible = "ti,sci-intr";
	ti,intr-trigger-type = <4>;
	interrupt-controller;
	interrupt-parent = <&gic500>;
	#interrupt-cells = <2>;
	ti,sci = <&dmsc>;
	ti,sci-dst-id = <56>;
	ti,sci-rm-range-girq = <0x0>, <0x2>;
	};

	inta_main_udmass: interrupt-controller@33d00000 {
	compatible = "ti,sci-inta";
	reg = <0x0 0x33d00000 0x0 0x100000>;
	interrupt-controller;
	interrupt-parent = <&intr_main_navss>;
	msi-controller;
	ti,sci = <&dmsc>;
	ti,sci-dev-id = <179>;
	ti,sci-rm-range-vint = <0x0>;
	ti,sci-rm-range-global-event = <0x1>;
	};

	secure_proxy_main: mailbox@32c00000 {
	compatible = "ti,am654-secure-proxy";
	#mbox-cells = <1>;
	reg-names = "target_data", "rt", "scfg";
	reg = <0x00 0x32c00000 0x00 0x100000>,
	<0x00 0x32400000 0x00 0x100000>,
	<0x00 0x32800000 0x00 0x100000>;
	interrupt-names = "rx_011";
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	};

	hwspinlock: spinlock@30e00000 {
	compatible = "ti,am654-hwspinlock";
	reg = <0x00 0x30e00000 0x00 0x1000>;
	#hwlock-cells = <1>;
	};

	mailbox0_cluster0: mailbox@31f80000 {
	compatible = "ti,am654-mailbox";
	reg = <0x00 0x31f80000 0x00 0x200>;
	#mbox-cells = <1>;
	ti,mbox-num-users = <4>;
	ti,mbox-num-fifos = <16>;
	interrupt-parent = <&intr_main_navss>;
	};

	mailbox0_cluster1: mailbox@31f81000 {
	compatible = "ti,am654-mailbox";
	reg = <0x00 0x31f81000 0x00 0x200>;
	#mbox-cells = <1>;
	ti,mbox-num-users = <4>;
	ti,mbox-num-fifos = <16>;
	interrupt-parent = <&intr_main_navss>;
	};

	mailbox0_cluster2: mailbox@31f82000 {
	compatible = "ti,am654-mailbox";
	reg = <0x00 0x31f82000 0x00 0x200>;
	#mbox-cells = <1>;
	ti,mbox-num-users = <4>;
	ti,mbox-num-fifos = <16>;
	interrupt-parent = <&intr_main_navss>;
	};

	mailbox0_cluster3: mailbox@31f83000 {
	compatible = "ti,am654-mailbox";
	reg = <0x00 0x31f83000 0x00 0x200>;
	#mbox-cells = <1>;
	ti,mbox-num-users = <4>;
	ti,mbox-num-fifos = <16>;
	interrupt-parent = <&intr_main_navss>;
	};

	mailbox0_cluster4: mailbox@31f84000 {
	compatible = "ti,am654-mailbox";
	reg = <0x00 0x31f84000 0x00 0x200>;
	#mbox-cells = <1>;
	ti,mbox-num-users = <4>;
	ti,mbox-num-fifos = <16>;
	interrupt-parent = <&intr_main_navss>;
	};

	mailbox0_cluster5: mailbox@31f85000 {
	compatible = "ti,am654-mailbox";
	reg = <0x00 0x31f85000 0x00 0x200>;
	#mbox-cells = <1>;
	ti,mbox-num-users = <4>;
	ti,mbox-num-fifos = <16>;
	interrupt-parent = <&intr_main_navss>;
	};

	mailbox0_cluster6: mailbox@31f86000 {
	compatible = "ti,am654-mailbox";
	reg = <0x00 0x31f86000 0x00 0x200>;
	#mbox-cells = <1>;
	ti,mbox-num-users = <4>;
	ti,mbox-num-fifos = <16>;
	interrupt-parent = <&intr_main_navss>;
	};

	mailbox0_cluster7: mailbox@31f87000 {
	compatible = "ti,am654-mailbox";
	reg = <0x00 0x31f87000 0x00 0x200>;
	#mbox-cells = <1>;
	ti,mbox-num-users = <4>;
	ti,mbox-num-fifos = <16>;
	interrupt-parent = <&intr_main_navss>;
	};

	mailbox0_cluster8: mailbox@31f88000 {
	compatible = "ti,am654-mailbox";
	reg = <0x00 0x31f88000 0x00 0x200>;
	#mbox-cells = <1>;
	ti,mbox-num-users = <4>;
	ti,mbox-num-fifos = <16>;
	interrupt-parent = <&intr_main_navss>;
	};

	mailbox0_cluster9: mailbox@31f89000 {
	compatible = "ti,am654-mailbox";
	reg = <0x00 0x31f89000 0x00 0x200>;
	#mbox-cells = <1>;
	ti,mbox-num-users = <4>;
	ti,mbox-num-fifos = <16>;
	interrupt-parent = <&intr_main_navss>;
	};

	mailbox0_cluster10: mailbox@31f8a000 {
	compatible = "ti,am654-mailbox";
	reg = <0x00 0x31f8a000 0x00 0x200>;
	#mbox-cells = <1>;
	ti,mbox-num-users = <4>;
	ti,mbox-num-fifos = <16>;
	interrupt-parent = <&intr_main_navss>;
	};

	mailbox0_cluster11: mailbox@31f8b000 {
	compatible = "ti,am654-mailbox";
	reg = <0x00 0x31f8b000 0x00 0x200>;
	#mbox-cells = <1>;
	ti,mbox-num-users = <4>;
	ti,mbox-num-fifos = <16>;
	interrupt-parent = <&intr_main_navss>;
	};

	ringacc: ringacc@3c000000 {
	compatible = "ti,am654-navss-ringacc";
	reg = <0x0 0x3c000000 0x0 0x400000>,
	<0x0 0x38000000 0x0 0x400000>,
	<0x0 0x31120000 0x0 0x100>,
	<0x0 0x33000000 0x0 0x40000>;
	reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
	ti,num-rings = <818>;
	ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
	ti,dma-ring-reset-quirk;
	ti,sci = <&dmsc>;
	ti,sci-dev-id = <187>;
	msi-parent = <&inta_main_udmass>;
	};

	main_udmap: dma-controller@31150000 {
	compatible = "ti,am654-navss-main-udmap";
	reg = <0x0 0x31150000 0x0 0x100>,
	<0x0 0x34000000 0x0 0x100000>,
	<0x0 0x35000000 0x0 0x100000>;
	reg-names = "gcfg", "rchanrt", "tchanrt";
	msi-parent = <&inta_main_udmass>;
	#dma-cells = <1>;

	ti,sci = <&dmsc>;
	ti,sci-dev-id = <188>;
	ti,ringacc = <&ringacc>;

	ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
	<0x2>; /* TX_CHAN */
	ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
	<0x5>; /* RX_CHAN */
	ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
	};
	};

	main_gpio0: main_gpio0@600000 {
	compatible = "ti,am654-gpio", "ti,keystone-gpio";
	reg = <0x0 0x600000 0x0 0x100>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-parent = <&intr_main_gpio>;
	interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>,
	<57 261>;
	interrupt-controller;
	#interrupt-cells = <2>;
	ti,ngpio = <96>;
	ti,davinci-gpio-unbanked = <0>;
	clocks = <&k3_clks 57 0>;
	clock-names = "gpio";
	};

	main_gpio1: main_gpio1@601000 {
	compatible = "ti,am654-gpio", "ti,keystone-gpio";
	reg = <0x0 0x601000 0x0 0x100>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-parent = <&intr_main_gpio>;
	interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>,
	<58 261>;
	interrupt-controller;
	#interrupt-cells = <2>;
	ti,ngpio = <90>;
	ti,davinci-gpio-unbanked = <0>;
	clocks = <&k3_clks 58 0>;
	clock-names = "gpio";
	};

	pcie0_rc: pcie@5500000 {
	compatible = "ti,am654-pcie-rc";
	reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
	reg-names = "app", "dbics", "config", "atu";
	power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
	#address-cells = <3>;
	#size-cells = <2>;
	ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
	0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
	ti,syscon-pcie-id = <&pcie_devid>;
	ti,syscon-pcie-mode = <&pcie0_mode>;
	bus-range = <0x0 0xff>;
	num-viewport = <16>;
	max-link-speed = <3>;
	dma-coherent;
	interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
	msi-map = <0x0 &gic_its 0x0 0x10000>;
	};

	pcie0_ep: pcie-ep@5500000 {
	compatible = "ti,am654-pcie-ep";
	reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
	reg-names = "app", "dbics", "addr_space", "atu";
	power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
	ti,syscon-pcie-mode = <&pcie0_mode>;
	num-ib-windows = <16>;
	num-ob-windows = <16>;
	max-link-speed = <3>;
	dma-coherent;
	interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
	};

	pcie1_rc: pcie@5600000 {
	compatible = "ti,am654-pcie-rc";
	reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
	reg-names = "app", "dbics", "config", "atu";
	power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
	#address-cells = <3>;
	#size-cells = <2>;
	ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
	0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
	ti,syscon-pcie-id = <&pcie_devid>;
	ti,syscon-pcie-mode = <&pcie1_mode>;
	bus-range = <0x0 0xff>;
	num-viewport = <16>;
	max-link-speed = <3>;
	dma-coherent;
	interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
	msi-map = <0x0 &gic_its 0x10000 0x10000>;
	};

	pcie1_ep: pcie-ep@5600000 {
	compatible = "ti,am654-pcie-ep";
	reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
	reg-names = "app", "dbics", "addr_space", "atu";
	power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
	ti,syscon-pcie-mode = <&pcie1_mode>;
	num-ib-windows = <16>;
	num-ob-windows = <16>;
	max-link-speed = <3>;
	dma-coherent;
	interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
	};

	mcasp0: mcasp@2b00000 {
	compatible = "ti,am33xx-mcasp-audio";
	reg = <0x0 0x02b00000 0x0 0x2000>,
	<0x0 0x02b08000 0x0 0x1000>;
	reg-names = "mpu","dat";
	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "tx", "rx";

	dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
	dma-names = "tx", "rx";

	clocks = <&k3_clks 104 0>;
	clock-names = "fck";
	power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;

	status = "disabled";
	};

	mcasp1: mcasp@2b10000 {
	compatible = "ti,am33xx-mcasp-audio";
	reg = <0x0 0x02b10000 0x0 0x2000>,
	<0x0 0x02b18000 0x0 0x1000>;
	reg-names = "mpu","dat";
	interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "tx", "rx";

	dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
	dma-names = "tx", "rx";

	clocks = <&k3_clks 105 0>;
	clock-names = "fck";
	power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;

	status = "disabled";
	};

	mcasp2: mcasp@2b20000 {
	compatible = "ti,am33xx-mcasp-audio";
	reg = <0x0 0x02b20000 0x0 0x2000>,
	<0x0 0x02b28000 0x0 0x1000>;
	reg-names = "mpu","dat";
	interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "tx", "rx";

	dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
	dma-names = "tx", "rx";

	clocks = <&k3_clks 106 0>;
	clock-names = "fck";
	power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;

	status = "disabled";
	};

	cal: cal@6f03000 {
	compatible = "ti,am654-cal";
	reg = <0x0 0x06f03000 0x0 0x400>,
	<0x0 0x06f03800 0x0 0x40>;
	reg-names = "cal_top",
	"cal_rx_core0";
	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	ti,camerrx-control = <&scm_conf 0x40c0>;
	clock-names = "fck";
	clocks = <&k3_clks 2 0>;
	power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	csi2_0: port@0 {
	reg = <0>;
	};
	};
	};
	};
	diff --git a/sys/gnu/dts/arm64/ti/k3-am65-mcu.dtsi b/sys/gnu/dts/arm64/ti/k3-am65-mcu.dtsi
	index 92629cbdc184..353d1e2532a7 100644
	--- a/sys/gnu/dts/arm64/ti/k3-am65-mcu.dtsi
	+++ b/sys/gnu/dts/arm64/ti/k3-am65-mcu.dtsi
	@@ -1,190 +1,251 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for AM6 SoC Family MCU Domain peripherals
	*
	* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
	*/

	&cbass_mcu {
	mcu_conf: scm_conf@40f00000 {
	compatible = "syscon", "simple-mfd";
	reg = <0x0 0x40f00000 0x0 0x20000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x40f00000 0x20000>;
	+
	+ phy_gmii_sel: phy@4040 {
	+ compatible = "ti,am654-phy-gmii-sel";
	+ reg = <0x4040 0x4>;
	+ #phy-cells = <1>;
	+ };
	};

	mcu_uart0: serial@40a00000 {
	compatible = "ti,am654-uart";
	reg = <0x00 0x40a00000 0x00 0x100>;
	reg-shift = <2>;
	reg-io-width = <4>;
	interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <96000000>;
	current-speed = <115200>;
	power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
	};

	mcu_ram: sram@41c00000 {
	compatible = "mmio-sram";
	reg = <0x00 0x41c00000 0x00 0x80000>;
	ranges = <0x0 0x00 0x41c00000 0x80000>;
	#address-cells = <1>;
	#size-cells = <1>;
	};

	mcu_i2c0: i2c@40b00000 {
	compatible = "ti,am654-i2c", "ti,omap4-i2c";
	reg = <0x0 0x40b00000 0x0 0x100>;
	interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "fck";
	clocks = <&k3_clks 114 1>;
	power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
	};

	mcu_spi0: spi@40300000 {
	compatible = "ti,am654-mcspi","ti,omap4-mcspi";
	reg = <0x0 0x40300000 0x0 0x400>;
	interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&k3_clks 142 1>;
	power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mcu_spi1: spi@40310000 {
	compatible = "ti,am654-mcspi","ti,omap4-mcspi";
	reg = <0x0 0x40310000 0x0 0x400>;
	interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&k3_clks 143 1>;
	power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mcu_spi2: spi@40320000 {
	compatible = "ti,am654-mcspi","ti,omap4-mcspi";
	reg = <0x0 0x40320000 0x0 0x400>;
	interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&k3_clks 144 1>;
	power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	tscadc0: tscadc@40200000 {
	compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
	reg = <0x0 0x40200000 0x0 0x1000>;
	interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&k3_clks 0 2>;
	assigned-clocks = <&k3_clks 0 2>;
	assigned-clock-rates = <60000000>;
	clock-names = "adc_tsc_fck";
	+ dmas = <&mcu_udmap 0x7100>,
	+ <&mcu_udmap 0x7101 >;
	+ dma-names = "fifo0", "fifo1";

	adc {
	#io-channel-cells = <1>;
	compatible = "ti,am654-adc", "ti,am3359-adc";
	};
	};

	tscadc1: tscadc@40210000 {
	compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
	reg = <0x0 0x40210000 0x0 0x1000>;
	interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&k3_clks 1 2>;
	assigned-clocks = <&k3_clks 1 2>;
	assigned-clock-rates = <60000000>;
	clock-names = "adc_tsc_fck";
	+ dmas = <&mcu_udmap 0x7102>,
	+ <&mcu_udmap 0x7103>;
	+ dma-names = "fifo0", "fifo1";

	adc {
	#io-channel-cells = <1>;
	compatible = "ti,am654-adc", "ti,am3359-adc";
	};
	};

	mcu_navss {
	compatible = "simple-mfd";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	dma-coherent;
	dma-ranges;

	ti,sci-dev-id = <119>;

	mcu_ringacc: ringacc@2b800000 {
	compatible = "ti,am654-navss-ringacc";
	reg = <0x0 0x2b800000 0x0 0x400000>,
	<0x0 0x2b000000 0x0 0x400000>,
	<0x0 0x28590000 0x0 0x100>,
	<0x0 0x2a500000 0x0 0x40000>;
	reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
	ti,num-rings = <286>;
	ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
	ti,dma-ring-reset-quirk;
	ti,sci = <&dmsc>;
	ti,sci-dev-id = <195>;
	msi-parent = <&inta_main_udmass>;
	};

	mcu_udmap: dma-controller@285c0000 {
	compatible = "ti,am654-navss-mcu-udmap";
	reg = <0x0 0x285c0000 0x0 0x100>,
	<0x0 0x2a800000 0x0 0x40000>,
	<0x0 0x2aa00000 0x0 0x40000>;
	reg-names = "gcfg", "rchanrt", "tchanrt";
	msi-parent = <&inta_main_udmass>;
	#dma-cells = <1>;

	ti,sci = <&dmsc>;
	ti,sci-dev-id = <194>;
	ti,ringacc = <&mcu_ringacc>;

	ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
	<0x2>; /* TX_CHAN */
	ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
	<0x4>; /* RX_CHAN */
	ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
	};
	};

	fss: fss@47000000 {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	ospi0: spi@47040000 {
	compatible = "ti,am654-ospi", "cdns,qspi-nor";
	reg = <0x0 0x47040000 0x0 0x100>,
	<0x5 0x00000000 0x1 0x0000000>;
	interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
	cdns,fifo-depth = <256>;
	cdns,fifo-width = <4>;
	cdns,trigger-address = <0x0>;
	clocks = <&k3_clks 248 0>;
	assigned-clocks = <&k3_clks 248 0>;
	assigned-clock-parents = <&k3_clks 248 2>;
	assigned-clock-rates = <166666666>;
	power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	ospi1: spi@47050000 {
	compatible = "ti,am654-ospi", "cdns,qspi-nor";
	reg = <0x0 0x47050000 0x0 0x100>,
	<0x7 0x00000000 0x1 0x00000000>;
	interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
	cdns,fifo-depth = <256>;
	cdns,fifo-width = <4>;
	cdns,trigger-address = <0x0>;
	clocks = <&k3_clks 249 6>;
	power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};
	+
	+ mcu_cpsw: ethernet@46000000 {
	+ compatible = "ti,am654-cpsw-nuss";
	+ #address-cells = <2>;
	+ #size-cells = <2>;
	+ reg = <0x0 0x46000000 0x0 0x200000>;
	+ reg-names = "cpsw_nuss";
	+ ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
	+ dma-coherent;
	+ clocks = <&k3_clks 5 10>;
	+ clock-names = "fck";
	+ power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
	+
	+ dmas = <&mcu_udmap 0xf000>,
	+ <&mcu_udmap 0xf001>,
	+ <&mcu_udmap 0xf002>,
	+ <&mcu_udmap 0xf003>,
	+ <&mcu_udmap 0xf004>,
	+ <&mcu_udmap 0xf005>,
	+ <&mcu_udmap 0xf006>,
	+ <&mcu_udmap 0xf007>,
	+ <&mcu_udmap 0x7000>;
	+ dma-names = "tx0", "tx1", "tx2", "tx3",
	+ "tx4", "tx5", "tx6", "tx7",
	+ "rx";
	+
	+ ethernet-ports {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ cpsw_port1: port@1 {
	+ reg = <1>;
	+ ti,mac-only;
	+ label = "port1";
	+ ti,syscon-efuse = <&mcu_conf 0x200>;
	+ phys = <&phy_gmii_sel 1>;
	+ };
	+ };
	+
	+ davinci_mdio: mdio@f00 {
	+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
	+ reg = <0x0 0xf00 0x0 0x100>;
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ clocks = <&k3_clks 5 10>;
	+ clock-names = "fck";
	+ bus_freq = <1000000>;
	+ };
	+ };
	};
	diff --git a/sys/gnu/dts/arm64/ti/k3-am65.dtsi b/sys/gnu/dts/arm64/ti/k3-am65.dtsi
	index aea36e29dd32..5be75e430965 100644
	--- a/sys/gnu/dts/arm64/ti/k3-am65.dtsi
	+++ b/sys/gnu/dts/arm64/ti/k3-am65.dtsi
	@@ -1,122 +1,123 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for AM6 SoC Family
	*
	* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
	*/

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/pinctrl/k3.h>
	#include <dt-bindings/soc/ti,sci_pm_domain.h>

	/ {
	model = "Texas Instruments K3 AM654 SoC";
	compatible = "ti,am654";
	interrupt-parent = <&gic500>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	serial0 = &wkup_uart0;
	serial1 = &mcu_uart0;
	serial2 = &main_uart0;
	serial3 = &main_uart1;
	serial4 = &main_uart2;
	i2c0 = &wkup_i2c0;
	i2c1 = &mcu_i2c0;
	i2c2 = &main_i2c0;
	i2c3 = &main_i2c1;
	i2c4 = &main_i2c2;
	i2c5 = &main_i2c3;
	+ ethernet0 = &cpsw_port1;
	};

	chosen { };

	firmware {
	optee {
	compatible = "linaro,optee-tz";
	method = "smc";
	};

	psci: psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};
	};

	a53_timer0: timer-cl0-cpu0 {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
	};

	pmu: pmu {
	compatible = "arm,armv8-pmuv3";
	/* Recommendation from GIC500 TRM Table A.3 */
	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	cbass_main: interconnect@100000 {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
	<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
	<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
	<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
	<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
	<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
	<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
	/* MCUSS Range */
	<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
	<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
	<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
	<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
	<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
	<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
	<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
	<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
	<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
	<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
	<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
	<0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
	<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
	<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;

	cbass_mcu: interconnect@28380000 {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
	<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
	<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
	<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
	<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
	<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
	<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
	<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
	<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
	<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
	<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /* FSS OSPI0 data region 1 */
	<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
	<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/

	cbass_wakeup: interconnect@42040000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	/* WKUP Basic peripherals */
	ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
	};
	};
	};
	};

	/* Now include the peripherals for each bus segments */
	#include "k3-am65-main.dtsi"
	#include "k3-am65-mcu.dtsi"
	#include "k3-am65-wakeup.dtsi"
	diff --git a/sys/gnu/dts/arm64/ti/k3-am654-base-board.dts b/sys/gnu/dts/arm64/ti/k3-am654-base-board.dts
	index 1700996800eb..2f3d3316a1cf 100644
	--- a/sys/gnu/dts/arm64/ti/k3-am654-base-board.dts
	+++ b/sys/gnu/dts/arm64/ti/k3-am654-base-board.dts
	@@ -1,421 +1,463 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
	*/

	/dts-v1/;

	#include "k3-am654.dtsi"
	#include <dt-bindings/input/input.h>
	+#include <dt-bindings/net/ti-dp83867.h>

	/ {
	compatible = "ti,am654-evm", "ti,am654";
	model = "Texas Instruments AM654 Base Board";

	chosen {
	stdout-path = "serial2:115200n8";
	bootargs = "earlycon=ns16550a,mmio32,0x02800000";
	};

	memory@80000000 {
	device_type = "memory";
	/* 4G RAM */
	reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
	<0x00000008 0x80000000 0x00000000 0x80000000>;
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	secure_ddr: secure_ddr@9e800000 {
	reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
	alignment = <0x1000>;
	no-map;
	};
	};

	gpio-keys {
	compatible = "gpio-keys";
	autorepeat;
	pinctrl-names = "default";
	pinctrl-0 = <&push_button_pins_default>;

	sw5 {
	label = "GPIO Key USER1";
	linux,code = <BTN_0>;
	gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
	};

	sw6 {
	label = "GPIO Key USER2";
	linux,code = <BTN_1>;
	gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
	};
	};

	clk_ov5640_fixed: clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <24000000>;
	};
	};

	&wkup_pmx0 {
	wkup_i2c0_pins_default: wkup-i2c0-pins-default {
	pinctrl-single,pins = <
	AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
	AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
	>;
	};

	push_button_pins_default: push_button__pins_default {
	pinctrl-single,pins = <
	AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
	AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
	>;
	};

	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
	pinctrl-single,pins = <
	AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
	AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
	AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */
	AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */
	AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */
	AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */
	AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */
	AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */
	AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */
	AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
	AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
	>;
	};

	wkup_pca554_default: wkup_pca554_default {
	pinctrl-single,pins = <
	AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
	+ >;
	+ };
	+
	+ mcu_cpsw_pins_default: mcu_cpsw_pins_default {
	+ pinctrl-single,pins = <
	+ AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
	+ AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
	+ AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
	+ AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
	+ AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
	+ AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
	+ AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
	+ AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
	+ AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
	+ AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
	+ AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
	+ AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
	+ >;
	+ };

	+ mcu_mdio_pins_default: mcu_mdio1_pins_default {
	+ pinctrl-single,pins = <
	+ AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
	+ AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
	>;
	};
	};

	&main_pmx0 {
	main_uart0_pins_default: main-uart0-pins-default {
	pinctrl-single,pins = <
	AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
	AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
	AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
	AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
	>;
	};

	main_i2c2_pins_default: main-i2c2-pins-default {
	pinctrl-single,pins = <
	AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */
	AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
	>;
	};

	main_spi0_pins_default: main-spi0-pins-default {
	pinctrl-single,pins = <
	AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
	AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
	AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */
	AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */
	>;
	};

	main_mmc0_pins_default: main-mmc0-pins-default {
	pinctrl-single,pins = <
	AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
	AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
	AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
	AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
	AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
	AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
	AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
	AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
	AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
	AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
	AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
	AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
	>;
	};

	usb1_pins_default: usb1_pins_default {
	pinctrl-single,pins = <
	AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
	>;
	};
	};

	&main_pmx1 {
	main_i2c0_pins_default: main-i2c0-pins-default {
	pinctrl-single,pins = <
	AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
	AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
	>;
	};

	main_i2c1_pins_default: main-i2c1-pins-default {
	pinctrl-single,pins = <
	AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
	AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
	>;
	};

	ecap0_pins_default: ecap0-pins-default {
	pinctrl-single,pins = <
	AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
	>;
	};
	};

	&wkup_uart0 {
	/* Wakeup UART is used by System firmware */
	status = "disabled";
	};

	&main_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart0_pins_default>;
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
	};

	&wkup_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_i2c0_pins_default>;
	clock-frequency = <400000>;

	pca9554: gpio@39 {
	compatible = "nxp,pca9554";
	reg = <0x39>;
	gpio-controller;
	#gpio-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_pca554_default>;
	interrupt-parent = <&wkup_gpio0>;
	interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	&main_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;

	pca9555: gpio@21 {
	compatible = "nxp,pca9555";
	reg = <0x21>;
	gpio-controller;
	#gpio-cells = <2>;
	};
	};

	&main_i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c1_pins_default>;
	clock-frequency = <400000>;

	ov5640@3c {
	compatible = "ovti,ov5640";
	reg = <0x3c>;

	clocks = <&clk_ov5640_fixed>;
	clock-names = "xclk";

	port {
	csi2_cam0: endpoint {
	remote-endpoint = <&csi2_phy0>;
	clock-lanes = <0>;
	data-lanes = <1 2>;
	};
	};
	};

	};

	&main_i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c2_pins_default>;
	clock-frequency = <400000>;
	};

	&ecap0 {
	pinctrl-names = "default";
	pinctrl-0 = <&ecap0_pins_default>;
	};

	&main_spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_spi0_pins_default>;
	#address-cells = <1>;
	#size-cells= <0>;
	ti,pindir-d0-out-d1-in = <1>;

	flash@0{
	compatible = "jedec,spi-nor";
	reg = <0x0>;
	spi-tx-bus-width = <1>;
	spi-rx-bus-width = <1>;
	spi-max-frequency = <48000000>;
	#address-cells = <1>;
	#size-cells= <1>;
	};
	};

	&sdhci0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc0_pins_default>;
	bus-width = <8>;
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
	};

	&dwc3_1 {
	status = "okay";
	};

	&usb1_phy {
	status = "okay";
	};

	&usb1 {
	pinctrl-names = "default";
	pinctrl-0 = <&usb1_pins_default>;
	dr_mode = "otg";
	};

	&dwc3_0 {
	status = "disabled";
	};

	&usb0_phy {
	status = "disabled";
	};

	&tscadc0 {
	adc {
	ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
	};

	&tscadc1 {
	adc {
	ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
	};

	&serdes0 {
	status = "disabled";
	};

	&serdes1 {
	status = "disabled";
	};

	&pcie0_rc {
	status = "disabled";
	};

	&pcie0_ep {
	status = "disabled";
	};

	&pcie1_rc {
	status = "disabled";
	};

	&pcie1_ep {
	status = "disabled";
	};

	&mailbox0_cluster0 {
	interrupts = <164 0>;

	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
	ti,mbox-tx = <1 0 0>;
	ti,mbox-rx = <0 0 0>;
	};
	};

	&mailbox0_cluster1 {
	interrupts = <165 0>;

	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
	ti,mbox-tx = <1 0 0>;
	ti,mbox-rx = <0 0 0>;
	};
	};

	&mailbox0_cluster2 {
	status = "disabled";
	};

	&mailbox0_cluster3 {
	status = "disabled";
	};

	&mailbox0_cluster4 {
	status = "disabled";
	};

	&mailbox0_cluster5 {
	status = "disabled";
	};

	&mailbox0_cluster6 {
	status = "disabled";
	};

	&mailbox0_cluster7 {
	status = "disabled";
	};

	&mailbox0_cluster8 {
	status = "disabled";
	};

	&mailbox0_cluster9 {
	status = "disabled";
	};

	&mailbox0_cluster10 {
	status = "disabled";
	};

	&mailbox0_cluster11 {
	status = "disabled";
	};

	&ospi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;

	flash@0{
	compatible = "jedec,spi-nor";
	reg = <0x0>;
	spi-tx-bus-width = <1>;
	spi-rx-bus-width = <8>;
	spi-max-frequency = <40000000>;
	cdns,tshsl-ns = <60>;
	cdns,tsd2d-ns = <60>;
	cdns,tchsh-ns = <60>;
	cdns,tslch-ns = <60>;
	cdns,read-delay = <0>;
	#address-cells = <1>;
	#size-cells = <1>;
	};
	};

	&csi2_0 {
	csi2_phy0: endpoint {
	remote-endpoint = <&csi2_cam0>;
	clock-lanes = <0>;
	data-lanes = <1 2>;
	};
	};
	+
	+&mcu_cpsw {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
	+};
	+
	+&davinci_mdio {
	+ phy0: ethernet-phy@0 {
	+ reg = <0>;
	+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
	+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	+ };
	+};
	+
	+&cpsw_port1 {
	+ phy-mode = "rgmii-rxid";
	+ phy-handle = <&phy0>;
	+};
	diff --git a/sys/gnu/dts/arm64/ti/k3-j721e-common-proc-board.dts b/sys/gnu/dts/arm64/ti/k3-j721e-common-proc-board.dts
	index 7a5c3d4adadd..98e5e17e3ff7 100644
	--- a/sys/gnu/dts/arm64/ti/k3-j721e-common-proc-board.dts
	+++ b/sys/gnu/dts/arm64/ti/k3-j721e-common-proc-board.dts
	@@ -1,431 +1,474 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
	*/

	/dts-v1/;

	#include "k3-j721e-som-p0.dtsi"
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/input/input.h>
	+#include <dt-bindings/net/ti-dp83867.h>

	/ {
	chosen {
	stdout-path = "serial2:115200n8";
	bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
	};

	gpio_keys: gpio-keys {
	compatible = "gpio-keys";
	autorepeat;
	pinctrl-names = "default";
	pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;

	sw10: sw10 {
	label = "GPIO Key USER1";
	linux,code = <BTN_0>;
	gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
	};

	sw11: sw11 {
	label = "GPIO Key USER2";
	linux,code = <BTN_1>;
	gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
	};
	};
	};

	&main_pmx0 {
	sw10_button_pins_default: sw10_button_pins_default {
	pinctrl-single,pins = <
	J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
	>;
	};

	main_mmc1_pins_default: main_mmc1_pins_default {
	pinctrl-single,pins = <
	J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
	J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
	J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
	J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
	J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
	J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
	J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
	J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
	J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
	>;
	};

	main_usbss0_pins_default: main_usbss0_pins_default {
	pinctrl-single,pins = <
	J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
	>;
	};

	main_usbss1_pins_default: main_usbss1_pins_default {
	pinctrl-single,pins = <
	J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
	>;
	};

	main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
	pinctrl-single,pins = <
	J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
	>;
	};

	main_i2c0_pins_default: main-i2c0-pins-default {
	pinctrl-single,pins = <
	J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
	J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
	>;
	};

	main_i2c1_pins_default: main-i2c1-pins-default {
	pinctrl-single,pins = <
	J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
	J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
	>;
	};

	main_i2c3_pins_default: main-i2c3-pins-default {
	pinctrl-single,pins = <
	J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
	J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
	>;
	};

	main_i2c6_pins_default: main-i2c6-pins-default {
	pinctrl-single,pins = <
	J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
	J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
	>;
	};

	main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
	pinctrl-single,pins = <
	J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
	>;
	};
	};

	&wkup_pmx0 {
	sw11_button_pins_default: sw11_button_pins_default {
	pinctrl-single,pins = <
	J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
	>;
	};

	mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
	pinctrl-single,pins = <
	J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
	J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
	J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
	J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
	J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
	J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
	J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
	J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
	>;
	};
	+
	+ mcu_cpsw_pins_default: mcu_cpsw_pins_default {
	+ pinctrl-single,pins = <
	+ J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
	+ J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
	+ J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
	+ J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
	+ J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
	+ J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
	+ J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
	+ J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
	+ J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
	+ J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
	+ J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
	+ J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
	+ >;
	+ };
	+
	+ mcu_mdio_pins_default: mcu_mdio1_pins_default {
	+ pinctrl-single,pins = <
	+ J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
	+ J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
	+ >;
	+ };
	};

	&wkup_uart0 {
	/* Wakeup UART is used by System firmware */
	status = "disabled";
	};

	&main_uart0 {
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
	};

	&main_uart3 {
	/* UART not brought out */
	status = "disabled";
	};

	&main_uart5 {
	/* UART not brought out */
	status = "disabled";
	};

	&main_uart6 {
	/* UART not brought out */
	status = "disabled";
	};

	&main_uart7 {
	/* UART not brought out */
	status = "disabled";
	};

	&main_uart8 {
	/* UART not brought out */
	status = "disabled";
	};

	&main_uart9 {
	/* UART not brought out */
	status = "disabled";
	};

	&main_gpio2 {
	status = "disabled";
	};

	&main_gpio3 {
	status = "disabled";
	};

	&main_gpio4 {
	status = "disabled";
	};

	&main_gpio5 {
	status = "disabled";
	};

	&main_gpio6 {
	status = "disabled";
	};

	&main_gpio7 {
	status = "disabled";
	};

	&wkup_gpio1 {
	status = "disabled";
	};

	&mailbox0_cluster0 {
	interrupts = <214 0>;

	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
	ti,mbox-rx = <0 0 0>;
	ti,mbox-tx = <1 0 0>;
	};

	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
	ti,mbox-rx = <2 0 0>;
	ti,mbox-tx = <3 0 0>;
	};
	};

	&mailbox0_cluster1 {
	interrupts = <215 0>;

	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
	ti,mbox-rx = <0 0 0>;
	ti,mbox-tx = <1 0 0>;
	};

	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
	ti,mbox-rx = <2 0 0>;
	ti,mbox-tx = <3 0 0>;
	};
	};

	&mailbox0_cluster2 {
	interrupts = <216 0>;

	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
	ti,mbox-rx = <0 0 0>;
	ti,mbox-tx = <1 0 0>;
	};

	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
	ti,mbox-rx = <2 0 0>;
	ti,mbox-tx = <3 0 0>;
	};
	};

	&mailbox0_cluster3 {
	interrupts = <217 0>;

	mbox_c66_0: mbox-c66-0 {
	ti,mbox-rx = <0 0 0>;
	ti,mbox-tx = <1 0 0>;
	};

	mbox_c66_1: mbox-c66-1 {
	ti,mbox-rx = <2 0 0>;
	ti,mbox-tx = <3 0 0>;
	};
	};

	&mailbox0_cluster4 {
	interrupts = <218 0>;

	mbox_c71_0: mbox-c71-0 {
	ti,mbox-rx = <0 0 0>;
	ti,mbox-tx = <1 0 0>;
	};
	};

	&mailbox0_cluster5 {
	status = "disabled";
	};

	&mailbox0_cluster6 {
	status = "disabled";
	};

	&mailbox0_cluster7 {
	status = "disabled";
	};

	&mailbox0_cluster8 {
	status = "disabled";
	};

	&mailbox0_cluster9 {
	status = "disabled";
	};

	&mailbox0_cluster10 {
	status = "disabled";
	};

	&mailbox0_cluster11 {
	status = "disabled";
	};

	&main_sdhci0 {
	/* eMMC */
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
	};

	&main_sdhci1 {
	/* SD/MMC */
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc1_pins_default>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
	};

	&main_sdhci2 {
	/* Unused */
	status = "disabled";
	};

	&usbss0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_usbss0_pins_default>;
	ti,usb2-only;
	ti,vbus-divider;
	};

	&usb0 {
	dr_mode = "otg";
	maximum-speed = "high-speed";
	};

	&usbss1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_usbss1_pins_default>;
	ti,usb2-only;
	};

	&usb1 {
	dr_mode = "host";
	maximum-speed = "high-speed";
	};

	&ospi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;

	flash@0{
	compatible = "jedec,spi-nor";
	reg = <0x0>;
	spi-tx-bus-width = <1>;
	spi-rx-bus-width = <4>;
	spi-max-frequency = <40000000>;
	cdns,tshsl-ns = <60>;
	cdns,tsd2d-ns = <60>;
	cdns,tchsh-ns = <60>;
	cdns,tslch-ns = <60>;
	cdns,read-delay = <2>;
	#address-cells = <1>;
	#size-cells = <1>;
	};
	};

	&tscadc0 {
	adc {
	ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
	};

	&tscadc1 {
	adc {
	ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
	};

	&main_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;

	exp1: gpio@20 {
	compatible = "ti,tca6416";
	reg = <0x20>;
	gpio-controller;
	#gpio-cells = <2>;
	};

	exp2: gpio@22 {
	compatible = "ti,tca6424";
	reg = <0x22>;
	gpio-controller;
	#gpio-cells = <2>;
	};
	};

	&main_i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c1_pins_default>;
	clock-frequency = <400000>;

	exp4: gpio@20 {
	compatible = "ti,tca6408";
	reg = <0x20>;
	gpio-controller;
	#gpio-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c1_exp4_pins_default>;
	interrupt-parent = <&main_gpio1>;
	interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	&main_i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c3_pins_default>;
	clock-frequency = <400000>;

	exp3: gpio@20 {
	compatible = "ti,tca6408";
	reg = <0x20>;
	gpio-controller;
	#gpio-cells = <2>;
	};
	};

	&main_i2c6 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c6_pins_default>;
	clock-frequency = <400000>;

	exp5: gpio@20 {
	compatible = "ti,tca6408";
	reg = <0x20>;
	gpio-controller;
	#gpio-cells = <2>;
	};
	};
	+
	+&mcu_cpsw {
	+ pinctrl-names = "default";
	+ pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
	+};
	+
	+&davinci_mdio {
	+ phy0: ethernet-phy@0 {
	+ reg = <0>;
	+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
	+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	+ };
	+};
	+
	+&cpsw_port1 {
	+ phy-mode = "rgmii-rxid";
	+ phy-handle = <&phy0>;
	+};
	diff --git a/sys/gnu/dts/arm64/ti/k3-j721e-mcu-wakeup.dtsi b/sys/gnu/dts/arm64/ti/k3-j721e-mcu-wakeup.dtsi
	index 16c874bfd49a..3d6064125b40 100644
	--- a/sys/gnu/dts/arm64/ti/k3-j721e-mcu-wakeup.dtsi
	+++ b/sys/gnu/dts/arm64/ti/k3-j721e-mcu-wakeup.dtsi
	@@ -1,273 +1,342 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
	*
	* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
	*/

	&cbass_mcu_wakeup {
	dmsc: dmsc@44083000 {
	compatible = "ti,k2g-sci";
	ti,host-id = <12>;

	mbox-names = "rx", "tx";

	mboxes= <&secure_proxy_main 11>,
	<&secure_proxy_main 13>;

	reg-names = "debug_messages";
	reg = <0x00 0x44083000 0x0 0x1000>;

	k3_pds: power-controller {
	compatible = "ti,sci-pm-domain";
	#power-domain-cells = <2>;
	};

	k3_clks: clocks {
	compatible = "ti,k2g-sci-clk";
	#clock-cells = <2>;
	};

	k3_reset: reset-controller {
	compatible = "ti,sci-reset";
	#reset-cells = <2>;
	};
	};

	+ mcu_conf: syscon@40f00000 {
	+ compatible = "syscon", "simple-mfd";
	+ reg = <0x0 0x40f00000 0x0 0x20000>;
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ ranges = <0x0 0x0 0x40f00000 0x20000>;
	+
	+ phy_gmii_sel: phy@4040 {
	+ compatible = "ti,am654-phy-gmii-sel";
	+ reg = <0x4040 0x4>;
	+ #phy-cells = <1>;
	+ };
	+ };
	+
	wkup_pmx0: pinmux@4301c000 {
	compatible = "pinctrl-single";
	/* Proxy 0 addressing */
	reg = <0x00 0x4301c000 0x00 0x178>;
	#pinctrl-cells = <1>;
	pinctrl-single,register-width = <32>;
	pinctrl-single,function-mask = <0xffffffff>;
	};

	mcu_ram: sram@41c00000 {
	compatible = "mmio-sram";
	reg = <0x00 0x41c00000 0x00 0x100000>;
	ranges = <0x0 0x00 0x41c00000 0x100000>;
	#address-cells = <1>;
	#size-cells = <1>;
	};

	wkup_uart0: serial@42300000 {
	compatible = "ti,j721e-uart", "ti,am654-uart";
	reg = <0x00 0x42300000 0x00 0x100>;
	reg-shift = <2>;
	reg-io-width = <4>;
	interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <48000000>;
	current-speed = <115200>;
	power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
	clocks = <&k3_clks 287 0>;
	clock-names = "fclk";
	};

	mcu_uart0: serial@40a00000 {
	compatible = "ti,j721e-uart", "ti,am654-uart";
	reg = <0x00 0x40a00000 0x00 0x100>;
	reg-shift = <2>;
	reg-io-width = <4>;
	interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
	clock-frequency = <96000000>;
	current-speed = <115200>;
	power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
	clocks = <&k3_clks 149 0>;
	clock-names = "fclk";
	};

	wkup_gpio_intr: interrupt-controller2 {
	compatible = "ti,sci-intr";
	ti,intr-trigger-type = <1>;
	interrupt-controller;
	interrupt-parent = <&gic500>;
	#interrupt-cells = <2>;
	ti,sci = <&dmsc>;
	ti,sci-dst-id = <14>;
	ti,sci-rm-range-girq = <0x5>;
	};

	wkup_gpio0: gpio@42110000 {
	compatible = "ti,j721e-gpio", "ti,keystone-gpio";
	reg = <0x0 0x42110000 0x0 0x100>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-parent = <&wkup_gpio_intr>;
	interrupts = <113 0>, <113 1>, <113 2>,
	<113 3>, <113 4>, <113 5>;
	interrupt-controller;
	#interrupt-cells = <2>;
	ti,ngpio = <84>;
	ti,davinci-gpio-unbanked = <0>;
	power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
	clocks = <&k3_clks 113 0>;
	clock-names = "gpio";
	};

	wkup_gpio1: gpio@42100000 {
	compatible = "ti,j721e-gpio", "ti,keystone-gpio";
	reg = <0x0 0x42100000 0x0 0x100>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-parent = <&wkup_gpio_intr>;
	interrupts = <114 0>, <114 1>, <114 2>,
	<114 3>, <114 4>, <114 5>;
	interrupt-controller;
	#interrupt-cells = <2>;
	ti,ngpio = <84>;
	ti,davinci-gpio-unbanked = <0>;
	power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
	clocks = <&k3_clks 114 0>;
	clock-names = "gpio";
	};

	mcu_i2c0: i2c@40b00000 {
	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
	reg = <0x0 0x40b00000 0x0 0x100>;
	interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "fck";
	clocks = <&k3_clks 194 0>;
	power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
	};

	mcu_i2c1: i2c@40b10000 {
	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
	reg = <0x0 0x40b10000 0x0 0x100>;
	interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "fck";
	clocks = <&k3_clks 195 0>;
	power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
	};

	wkup_i2c0: i2c@42120000 {
	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
	reg = <0x0 0x42120000 0x0 0x100>;
	interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "fck";
	clocks = <&k3_clks 197 0>;
	power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
	};

	fss: fss@47000000 {
	compatible = "simple-bus";
	reg = <0x0 0x47000000 0x0 0x100>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	ospi0: spi@47040000 {
	compatible = "ti,am654-ospi";
	reg = <0x0 0x47040000 0x0 0x100>,
	<0x5 0x00000000 0x1 0x0000000>;
	interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
	cdns,fifo-depth = <256>;
	cdns,fifo-width = <4>;
	cdns,trigger-address = <0x0>;
	clocks = <&k3_clks 103 0>;
	assigned-clocks = <&k3_clks 103 0>;
	assigned-clock-parents = <&k3_clks 103 2>;
	assigned-clock-rates = <166666666>;
	power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	ospi1: spi@47050000 {
	compatible = "ti,am654-ospi";
	reg = <0x0 0x47050000 0x0 0x100>,
	<0x7 0x00000000 0x1 0x00000000>;
	interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
	cdns,fifo-depth = <256>;
	cdns,fifo-width = <4>;
	cdns,trigger-address = <0x0>;
	clocks = <&k3_clks 104 0>;
	power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};

	tscadc0: tscadc@40200000 {
	compatible = "ti,am3359-tscadc";
	reg = <0x0 0x40200000 0x0 0x1000>;
	interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
	clocks = <&k3_clks 0 1>;
	assigned-clocks = <&k3_clks 0 3>;
	assigned-clock-rates = <60000000>;
	clock-names = "adc_tsc_fck";
	+ dmas = <&main_udmap 0x7400>,
	+ <&main_udmap 0x7401>;
	+ dma-names = "fifo0", "fifo1";

	adc {
	#io-channel-cells = <1>;
	compatible = "ti,am3359-adc";
	};
	};

	tscadc1: tscadc@40210000 {
	compatible = "ti,am3359-tscadc";
	reg = <0x0 0x40210000 0x0 0x1000>;
	interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
	power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
	clocks = <&k3_clks 1 1>;
	assigned-clocks = <&k3_clks 1 3>;
	assigned-clock-rates = <60000000>;
	clock-names = "adc_tsc_fck";
	+ dmas = <&main_udmap 0x7402>,
	+ <&main_udmap 0x7403>;
	+ dma-names = "fifo0", "fifo1";

	adc {
	#io-channel-cells = <1>;
	compatible = "ti,am3359-adc";
	};
	};

	mcu_navss {
	compatible = "simple-mfd";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	dma-coherent;
	dma-ranges;

	ti,sci-dev-id = <232>;

	mcu_ringacc: ringacc@2b800000 {
	compatible = "ti,am654-navss-ringacc";
	reg = <0x0 0x2b800000 0x0 0x400000>,
	<0x0 0x2b000000 0x0 0x400000>,
	<0x0 0x28590000 0x0 0x100>,
	<0x0 0x2a500000 0x0 0x40000>;
	reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
	ti,num-rings = <286>;
	ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
	ti,sci = <&dmsc>;
	ti,sci-dev-id = <235>;
	msi-parent = <&main_udmass_inta>;
	};

	mcu_udmap: dma-controller@285c0000 {
	compatible = "ti,j721e-navss-mcu-udmap";
	reg = <0x0 0x285c0000 0x0 0x100>,
	<0x0 0x2a800000 0x0 0x40000>,
	<0x0 0x2aa00000 0x0 0x40000>;
	reg-names = "gcfg", "rchanrt", "tchanrt";
	msi-parent = <&main_udmass_inta>;
	#dma-cells = <1>;

	ti,sci = <&dmsc>;
	ti,sci-dev-id = <236>;
	ti,ringacc = <&mcu_ringacc>;

	ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
	<0x0f>; /* TX_HCHAN */
	ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
	<0x0b>; /* RX_HCHAN */
	ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
	};
	};
	+
	+ mcu_cpsw: ethernet@46000000 {
	+ compatible = "ti,j721e-cpsw-nuss";
	+ #address-cells = <2>;
	+ #size-cells = <2>;
	+ reg = <0x0 0x46000000 0x0 0x200000>;
	+ reg-names = "cpsw_nuss";
	+ ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
	+ dma-coherent;
	+ clocks = <&k3_clks 18 22>;
	+ clock-names = "fck";
	+ power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
	+
	+ dmas = <&mcu_udmap 0xf000>,
	+ <&mcu_udmap 0xf001>,
	+ <&mcu_udmap 0xf002>,
	+ <&mcu_udmap 0xf003>,
	+ <&mcu_udmap 0xf004>,
	+ <&mcu_udmap 0xf005>,
	+ <&mcu_udmap 0xf006>,
	+ <&mcu_udmap 0xf007>,
	+ <&mcu_udmap 0x7000>;
	+ dma-names = "tx0", "tx1", "tx2", "tx3",
	+ "tx4", "tx5", "tx6", "tx7",
	+ "rx";
	+
	+ ethernet-ports {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ cpsw_port1: port@1 {
	+ reg = <1>;
	+ ti,mac-only;
	+ label = "port1";
	+ ti,syscon-efuse = <&mcu_conf 0x200>;
	+ phys = <&phy_gmii_sel 1>;
	+ };
	+ };
	+
	+ davinci_mdio: mdio@f00 {
	+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
	+ reg = <0x0 0xf00 0x0 0x100>;
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ clocks = <&k3_clks 18 22>;
	+ clock-names = "fck";
	+ bus_freq = <1000000>;
	+ };
	+ };
	};
	diff --git a/sys/gnu/dts/arm64/ti/k3-j721e.dtsi b/sys/gnu/dts/arm64/ti/k3-j721e.dtsi
	index 027bd1febafa..2f9a56d9b114 100644
	--- a/sys/gnu/dts/arm64/ti/k3-j721e.dtsi
	+++ b/sys/gnu/dts/arm64/ti/k3-j721e.dtsi
	@@ -1,180 +1,181 @@
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Device Tree Source for J721E SoC Family
	*
	* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
	*/

	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/pinctrl/k3.h>
	#include <dt-bindings/soc/ti,sci_pm_domain.h>

	/ {
	model = "Texas Instruments K3 J721E SoC";
	compatible = "ti,j721e";
	interrupt-parent = <&gic500>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
	serial0 = &wkup_uart0;
	serial1 = &mcu_uart0;
	serial2 = &main_uart0;
	serial3 = &main_uart1;
	serial4 = &main_uart2;
	serial5 = &main_uart3;
	serial6 = &main_uart4;
	serial7 = &main_uart5;
	serial8 = &main_uart6;
	serial9 = &main_uart7;
	serial10 = &main_uart8;
	serial11 = &main_uart9;
	+ ethernet0 = &cpsw_port1;
	};

	chosen { };

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	cpu-map {
	cluster0: cluster0 {
	core0 {
	cpu = <&cpu0>;
	};

	core1 {
	cpu = <&cpu1>;
	};
	};

	};

	cpu0: cpu@0 {
	compatible = "arm,cortex-a72";
	reg = <0x000>;
	device_type = "cpu";
	enable-method = "psci";
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <256>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	next-level-cache = <&L2_0>;
	};

	cpu1: cpu@1 {
	compatible = "arm,cortex-a72";
	reg = <0x001>;
	device_type = "cpu";
	enable-method = "psci";
	i-cache-size = <0xC000>;
	i-cache-line-size = <64>;
	i-cache-sets = <256>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	next-level-cache = <&L2_0>;
	};
	};

	L2_0: l2-cache0 {
	compatible = "cache";
	cache-level = <2>;
	cache-size = <0x100000>;
	cache-line-size = <64>;
	cache-sets = <2048>;
	next-level-cache = <&msmc_l3>;
	};

	msmc_l3: l3-cache0 {
	compatible = "cache";
	cache-level = <3>;
	};

	firmware {
	optee {
	compatible = "linaro,optee-tz";
	method = "smc";
	};

	psci: psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};
	};

	a72_timer0: timer-cl0-cpu0 {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
	};

	pmu: pmu {
	compatible = "arm,armv8-pmuv3";
	/* Recommendation from GIC500 TRM Table A.3 */
	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	cbass_main: interconnect@100000 {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
	<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
	<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
	<0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
	<0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
	<0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
	<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
	<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
	<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
	<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
	<0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
	<0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
	<0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
	<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
	<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */

	/* MCUSS_WKUP Range */
	<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
	<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
	<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
	<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
	<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
	<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
	<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
	<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
	<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
	<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
	<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
	<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
	<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;

	cbass_mcu_wakeup: interconnect@28380000 {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
	<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
	<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
	<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
	<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
	<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
	<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
	<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
	<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
	<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
	<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
	<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
	<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
	};
	};
	};

	/* Now include the peripherals for each bus segments */
	#include "k3-j721e-main.dtsi"
	#include "k3-j721e-mcu-wakeup.dtsi"
	diff --git a/sys/gnu/dts/include/dt-bindings/arm/coresight-cti-dt.h b/sys/gnu/dts/include/dt-bindings/arm/coresight-cti-dt.h
	new file mode 100644
	index 000000000000..61e7bdf8ea6e
	--- /dev/null
	+++ b/sys/gnu/dts/include/dt-bindings/arm/coresight-cti-dt.h
	@@ -0,0 +1,37 @@
	+/* SPDX-License-Identifier: GPL-2.0 */
	+/*
	+ * This header provides constants for the defined trigger signal
	+ * types on CoreSight CTI.
	+ */
	+
	+#ifndef _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H
	+#define _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H
	+
	+#define GEN_IO 0
	+#define GEN_INTREQ 1
	+#define GEN_INTACK 2
	+#define GEN_HALTREQ 3
	+#define GEN_RESTARTREQ 4
	+#define PE_EDBGREQ 5
	+#define PE_DBGRESTART 6
	+#define PE_CTIIRQ 7
	+#define PE_PMUIRQ 8
	+#define PE_DBGTRIGGER 9
	+#define ETM_EXTOUT 10
	+#define ETM_EXTIN 11
	+#define SNK_FULL 12
	+#define SNK_ACQCOMP 13
	+#define SNK_FLUSHCOMP 14
	+#define SNK_FLUSHIN 15
	+#define SNK_TRIGIN 16
	+#define STM_ASYNCOUT 17
	+#define STM_TOUT_SPTE 18
	+#define STM_TOUT_SW 19
	+#define STM_TOUT_HETE 20
	+#define STM_HWEVENT 21
	+#define ELA_TSTART 22
	+#define ELA_TSTOP 23
	+#define ELA_DBGREQ 24
	+#define CTI_TRIG_MAX 25
	+
	+#endif /_DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H /
	diff --git a/sys/gnu/dts/include/dt-bindings/bus/ti-sysc.h b/sys/gnu/dts/include/dt-bindings/bus/ti-sysc.h
	index babd08a1d226..76b07826ed05 100644
	--- a/sys/gnu/dts/include/dt-bindings/bus/ti-sysc.h
	+++ b/sys/gnu/dts/include/dt-bindings/bus/ti-sysc.h
	@@ -1,25 +1,29 @@
	/* SPDX-License-Identifier: GPL-2.0 */
	/* TI sysc interconnect target module defines */

	/* Generic sysc found on omap2 and later, also known as type1 */
	#define SYSC_OMAP2_CLOCKACTIVITY (3 << 8)
	#define SYSC_OMAP2_EMUFREE (1 << 5)
	#define SYSC_OMAP2_ENAWAKEUP (1 << 2)
	#define SYSC_OMAP2_SOFTRESET (1 << 1)
	#define SYSC_OMAP2_AUTOIDLE (1 << 0)

	/* Generic sysc found on omap4 and later, also known as type2 */
	#define SYSC_OMAP4_DMADISABLE (1 << 16)
	#define SYSC_OMAP4_FREEEMU (1 << 1) /* Also known as EMUFREE */
	#define SYSC_OMAP4_SOFTRESET (1 << 0)

	/* SmartReflex sysc found on 36xx and later */
	#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26)

	#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4)

	+/* PRUSS sysc found on AM33xx/AM43xx/AM57xx */
	+#define SYSC_PRUSS_SUB_MWAIT (1 << 5)
	+#define SYSC_PRUSS_STANDBY_INIT (1 << 4)
	+
	/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */
	#define SYSC_IDLE_FORCE 0
	#define SYSC_IDLE_NO 1
	#define SYSC_IDLE_SMART 2
	#define SYSC_IDLE_SMART_WKUP 3
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/dm814.h b/sys/gnu/dts/include/dt-bindings/clock/dm814.h
	index f0f04e0a249e..33b8826d936b 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/dm814.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/dm814.h
	@@ -1,37 +1,42 @@
	/* SPDX-License-Identifier: GPL-2.0-only */
	/*
	* Copyright 2017 Texas Instruments, Inc.
	*/
	#ifndef __DT_BINDINGS_CLK_DM814_H
	#define __DT_BINDINGS_CLK_DM814_H

	#define DM814_CLKCTRL_OFFSET 0x0
	#define DM814_CLKCTRL_INDEX(offset) ((offset) - DM814_CLKCTRL_OFFSET)

	/* default clocks */
	#define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)

	/* alwon clocks */
	#define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
	#define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
	#define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
	#define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
	#define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
	#define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
	#define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
	#define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
	#define DM814_MCSPI1_CLKCTRL DM814_CLKCTRL_INDEX(0x190)
	#define DM814_GPMC_CLKCTRL DM814_CLKCTRL_INDEX(0x1d0)
	#define DM814_CPGMAC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1d4)
	#define DM814_MPU_CLKCTRL DM814_CLKCTRL_INDEX(0x1dc)
	#define DM814_RTC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f0)
	#define DM814_TPCC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f4)
	#define DM814_TPTC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1f8)
	#define DM814_TPTC1_CLKCTRL DM814_CLKCTRL_INDEX(0x1fc)
	#define DM814_TPTC2_CLKCTRL DM814_CLKCTRL_INDEX(0x200)
	#define DM814_TPTC3_CLKCTRL DM814_CLKCTRL_INDEX(0x204)
	#define DM814_MMC1_CLKCTRL DM814_CLKCTRL_INDEX(0x21c)
	#define DM814_MMC2_CLKCTRL DM814_CLKCTRL_INDEX(0x220)
	#define DM814_MMC3_CLKCTRL DM814_CLKCTRL_INDEX(0x224)

	+/* alwon_ethernet clocks */
	+#define DM814_ETHERNET_CLKCTRL_OFFSET 0x1d4
	+#define DM814_ETHERNET_CLKCTRL_INDEX(offset) ((offset) - DM814_ETHERNET_CLKCTRL_OFFSET)
	+#define DM814_ETHERNET_CPGMAC0_CLKCTRL DM814_ETHERNET_CLKCTRL_INDEX(0x1d4)
	+
	#endif
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/g12a-clkc.h b/sys/gnu/dts/include/dt-bindings/clock/g12a-clkc.h
	index 0837c1a7ae49..b0d65d73db96 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/g12a-clkc.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/g12a-clkc.h
	@@ -1,147 +1,149 @@
	/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
	/*
	* Meson-G12A clock tree IDs
	*
	* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
	*/

	#ifndef __G12A_CLKC_H
	#define __G12A_CLKC_H

	#define CLKID_SYS_PLL 0
	#define CLKID_FIXED_PLL 1
	#define CLKID_FCLK_DIV2 2
	#define CLKID_FCLK_DIV3 3
	#define CLKID_FCLK_DIV4 4
	#define CLKID_FCLK_DIV5 5
	#define CLKID_FCLK_DIV7 6
	#define CLKID_GP0_PLL 7
	#define CLKID_CLK81 10
	#define CLKID_MPLL0 11
	#define CLKID_MPLL1 12
	#define CLKID_MPLL2 13
	#define CLKID_MPLL3 14
	#define CLKID_DDR 15
	#define CLKID_DOS 16
	#define CLKID_AUDIO_LOCKER 17
	#define CLKID_MIPI_DSI_HOST 18
	#define CLKID_ETH_PHY 19
	#define CLKID_ISA 20
	#define CLKID_PL301 21
	#define CLKID_PERIPHS 22
	#define CLKID_SPICC0 23
	#define CLKID_I2C 24
	#define CLKID_SANA 25
	#define CLKID_SD 26
	#define CLKID_RNG0 27
	#define CLKID_UART0 28
	#define CLKID_SPICC1 29
	#define CLKID_HIU_IFACE 30
	#define CLKID_MIPI_DSI_PHY 31
	#define CLKID_ASSIST_MISC 32
	#define CLKID_SD_EMMC_A 33
	#define CLKID_SD_EMMC_B 34
	#define CLKID_SD_EMMC_C 35
	#define CLKID_AUDIO_CODEC 36
	#define CLKID_AUDIO 37
	#define CLKID_ETH 38
	#define CLKID_DEMUX 39
	#define CLKID_AUDIO_IFIFO 40
	#define CLKID_ADC 41
	#define CLKID_UART1 42
	#define CLKID_G2D 43
	#define CLKID_RESET 44
	#define CLKID_PCIE_COMB 45
	#define CLKID_PARSER 46
	#define CLKID_USB 47
	#define CLKID_PCIE_PHY 48
	#define CLKID_AHB_ARB0 49
	#define CLKID_AHB_DATA_BUS 50
	#define CLKID_AHB_CTRL_BUS 51
	#define CLKID_HTX_HDCP22 52
	#define CLKID_HTX_PCLK 53
	#define CLKID_BT656 54
	#define CLKID_USB1_DDR_BRIDGE 55
	#define CLKID_MMC_PCLK 56
	#define CLKID_UART2 57
	#define CLKID_VPU_INTR 58
	#define CLKID_GIC 59
	#define CLKID_SD_EMMC_A_CLK0 60
	#define CLKID_SD_EMMC_B_CLK0 61
	#define CLKID_SD_EMMC_C_CLK0 62
	#define CLKID_HIFI_PLL 74
	#define CLKID_VCLK2_VENCI0 80
	#define CLKID_VCLK2_VENCI1 81
	#define CLKID_VCLK2_VENCP0 82
	#define CLKID_VCLK2_VENCP1 83
	#define CLKID_VCLK2_VENCT0 84
	#define CLKID_VCLK2_VENCT1 85
	#define CLKID_VCLK2_OTHER 86
	#define CLKID_VCLK2_ENCI 87
	#define CLKID_VCLK2_ENCP 88
	#define CLKID_DAC_CLK 89
	#define CLKID_AOCLK 90
	#define CLKID_IEC958 91
	#define CLKID_ENC480P 92
	#define CLKID_RNG1 93
	#define CLKID_VCLK2_ENCT 94
	#define CLKID_VCLK2_ENCL 95
	#define CLKID_VCLK2_VENCLMMC 96
	#define CLKID_VCLK2_VENCL 97
	#define CLKID_VCLK2_OTHER1 98
	#define CLKID_FCLK_DIV2P5 99
	#define CLKID_DMA 105
	#define CLKID_EFUSE 106
	#define CLKID_ROM_BOOT 107
	#define CLKID_RESET_SEC 108
	#define CLKID_SEC_AHB_APB3 109
	#define CLKID_VPU_0_SEL 110
	#define CLKID_VPU_0 112
	#define CLKID_VPU_1_SEL 113
	#define CLKID_VPU_1 115
	#define CLKID_VPU 116
	#define CLKID_VAPB_0_SEL 117
	#define CLKID_VAPB_0 119
	#define CLKID_VAPB_1_SEL 120
	#define CLKID_VAPB_1 122
	#define CLKID_VAPB_SEL 123
	#define CLKID_VAPB 124
	#define CLKID_HDMI_PLL 128
	#define CLKID_VID_PLL 129
	#define CLKID_VCLK 138
	#define CLKID_VCLK2 139
	#define CLKID_VCLK_DIV1 148
	#define CLKID_VCLK_DIV2 149
	#define CLKID_VCLK_DIV4 150
	#define CLKID_VCLK_DIV6 151
	#define CLKID_VCLK_DIV12 152
	#define CLKID_VCLK2_DIV1 153
	#define CLKID_VCLK2_DIV2 154
	#define CLKID_VCLK2_DIV4 155
	#define CLKID_VCLK2_DIV6 156
	#define CLKID_VCLK2_DIV12 157
	#define CLKID_CTS_ENCI 162
	#define CLKID_CTS_ENCP 163
	#define CLKID_CTS_VDAC 164
	#define CLKID_HDMI_TX 165
	#define CLKID_HDMI 168
	#define CLKID_MALI_0_SEL 169
	#define CLKID_MALI_0 171
	#define CLKID_MALI_1_SEL 172
	#define CLKID_MALI_1 174
	#define CLKID_MALI 175
	#define CLKID_MPLL_50M 177
	#define CLKID_CPU_CLK 187
	#define CLKID_PCIE_PLL 201
	#define CLKID_VDEC_1 204
	#define CLKID_VDEC_HEVC 207
	#define CLKID_VDEC_HEVCF 210
	#define CLKID_TS 212
	#define CLKID_CPUB_CLK 224
	#define CLKID_GP1_PLL 243
	#define CLKID_DSU_CLK 252
	#define CLKID_CPU1_CLK 253
	#define CLKID_CPU2_CLK 254
	#define CLKID_CPU3_CLK 255
	+#define CLKID_SPICC0_SCLK 258
	+#define CLKID_SPICC1_SCLK 261

	#endif /* __G12A_CLKC_H */
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/gxbb-clkc.h b/sys/gnu/dts/include/dt-bindings/clock/gxbb-clkc.h
	index db0763e96173..4073eb7a9da1 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/gxbb-clkc.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/gxbb-clkc.h
	@@ -1,150 +1,151 @@
	/* SPDX-License-Identifier: GPL-2.0 */
	/*
	* GXBB clock tree IDs
	*/

	#ifndef __GXBB_CLKC_H
	#define __GXBB_CLKC_H

	#define CLKID_SYS_PLL 0
	#define CLKID_HDMI_PLL 2
	#define CLKID_FIXED_PLL 3
	#define CLKID_FCLK_DIV2 4
	#define CLKID_FCLK_DIV3 5
	#define CLKID_FCLK_DIV4 6
	#define CLKID_FCLK_DIV5 7
	#define CLKID_FCLK_DIV7 8
	#define CLKID_GP0_PLL 9
	#define CLKID_CLK81 12
	#define CLKID_MPLL0 13
	#define CLKID_MPLL1 14
	#define CLKID_MPLL2 15
	#define CLKID_DDR 16
	#define CLKID_DOS 17
	#define CLKID_ISA 18
	#define CLKID_PL301 19
	#define CLKID_PERIPHS 20
	#define CLKID_SPICC 21
	#define CLKID_I2C 22
	#define CLKID_SAR_ADC 23
	#define CLKID_SMART_CARD 24
	#define CLKID_RNG0 25
	#define CLKID_UART0 26
	#define CLKID_SDHC 27
	#define CLKID_STREAM 28
	#define CLKID_ASYNC_FIFO 29
	#define CLKID_SDIO 30
	#define CLKID_ABUF 31
	#define CLKID_HIU_IFACE 32
	#define CLKID_ASSIST_MISC 33
	#define CLKID_SPI 34
	#define CLKID_ETH 36
	#define CLKID_I2S_SPDIF 35
	#define CLKID_DEMUX 37
	#define CLKID_AIU_GLUE 38
	#define CLKID_IEC958 39
	#define CLKID_I2S_OUT 40
	#define CLKID_AMCLK 41
	#define CLKID_AIFIFO2 42
	#define CLKID_MIXER 43
	#define CLKID_MIXER_IFACE 44
	#define CLKID_ADC 45
	#define CLKID_BLKMV 46
	#define CLKID_AIU 47
	#define CLKID_UART1 48
	#define CLKID_G2D 49
	#define CLKID_USB0 50
	#define CLKID_USB1 51
	#define CLKID_RESET 52
	#define CLKID_NAND 53
	#define CLKID_DOS_PARSER 54
	#define CLKID_USB 55
	#define CLKID_VDIN1 56
	#define CLKID_AHB_ARB0 57
	#define CLKID_EFUSE 58
	#define CLKID_BOOT_ROM 59
	#define CLKID_AHB_DATA_BUS 60
	#define CLKID_AHB_CTRL_BUS 61
	#define CLKID_HDMI_INTR_SYNC 62
	#define CLKID_HDMI_PCLK 63
	#define CLKID_USB1_DDR_BRIDGE 64
	#define CLKID_USB0_DDR_BRIDGE 65
	#define CLKID_MMC_PCLK 66
	#define CLKID_DVIN 67
	#define CLKID_UART2 68
	#define CLKID_SANA 69
	#define CLKID_VPU_INTR 70
	#define CLKID_SEC_AHB_AHB3_BRIDGE 71
	#define CLKID_CLK81_A53 72
	#define CLKID_VCLK2_VENCI0 73
	#define CLKID_VCLK2_VENCI1 74
	#define CLKID_VCLK2_VENCP0 75
	#define CLKID_VCLK2_VENCP1 76
	#define CLKID_GCLK_VENCI_INT0 77
	#define CLKID_GCLK_VENCI_INT 78
	#define CLKID_DAC_CLK 79
	#define CLKID_AOCLK_GATE 80
	#define CLKID_IEC958_GATE 81
	#define CLKID_ENC480P 82
	#define CLKID_RNG1 83
	#define CLKID_GCLK_VENCI_INT1 84
	#define CLKID_VCLK2_VENCLMCC 85
	#define CLKID_VCLK2_VENCL 86
	#define CLKID_VCLK_OTHER 87
	#define CLKID_EDP 88
	#define CLKID_AO_MEDIA_CPU 89
	#define CLKID_AO_AHB_SRAM 90
	#define CLKID_AO_AHB_BUS 91
	#define CLKID_AO_IFACE 92
	#define CLKID_AO_I2C 93
	#define CLKID_SD_EMMC_A 94
	#define CLKID_SD_EMMC_B 95
	#define CLKID_SD_EMMC_C 96
	#define CLKID_SAR_ADC_CLK 97
	#define CLKID_SAR_ADC_SEL 98
	#define CLKID_MALI_0_SEL 100
	#define CLKID_MALI_0 102
	#define CLKID_MALI_1_SEL 103
	#define CLKID_MALI_1 105
	#define CLKID_MALI 106
	#define CLKID_CTS_AMCLK 107
	#define CLKID_CTS_MCLK_I958 110
	#define CLKID_CTS_I958 113
	#define CLKID_32K_CLK 114
	#define CLKID_SD_EMMC_A_CLK0 119
	#define CLKID_SD_EMMC_B_CLK0 122
	#define CLKID_SD_EMMC_C_CLK0 125
	#define CLKID_VPU_0_SEL 126
	#define CLKID_VPU_0 128
	#define CLKID_VPU_1_SEL 129
	#define CLKID_VPU_1 131
	#define CLKID_VPU 132
	#define CLKID_VAPB_0_SEL 133
	#define CLKID_VAPB_0 135
	#define CLKID_VAPB_1_SEL 136
	#define CLKID_VAPB_1 138
	#define CLKID_VAPB_SEL 139
	#define CLKID_VAPB 140
	#define CLKID_VDEC_1 153
	#define CLKID_VDEC_HEVC 156
	#define CLKID_GEN_CLK 159
	#define CLKID_VID_PLL 166
	#define CLKID_VCLK 175
	#define CLKID_VCLK2 176
	#define CLKID_VCLK_DIV1 185
	#define CLKID_VCLK_DIV2 186
	#define CLKID_VCLK_DIV4 187
	#define CLKID_VCLK_DIV6 188
	#define CLKID_VCLK_DIV12 189
	#define CLKID_VCLK2_DIV1 190
	#define CLKID_VCLK2_DIV2 191
	#define CLKID_VCLK2_DIV4 192
	#define CLKID_VCLK2_DIV6 193
	#define CLKID_VCLK2_DIV12 194
	#define CLKID_CTS_ENCI 199
	#define CLKID_CTS_ENCP 200
	#define CLKID_CTS_VDAC 201
	#define CLKID_HDMI_TX 202
	#define CLKID_HDMI 205
	+#define CLKID_ACODEC 206

	#endif /* __GXBB_CLKC_H */
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx7d-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx7d-clock.h
	index e6a670e1a3f8..1d4c0dfe0202 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/imx7d-clock.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/imx7d-clock.h
	@@ -1,455 +1,456 @@
	/* SPDX-License-Identifier: GPL-2.0-only */
	/*
	* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
	*/

	#ifndef __DT_BINDINGS_CLOCK_IMX7D_H
	#define __DT_BINDINGS_CLOCK_IMX7D_H

	#define IMX7D_OSC_24M_CLK 0
	#define IMX7D_PLL_ARM_MAIN 1
	#define IMX7D_PLL_ARM_MAIN_CLK 2
	#define IMX7D_PLL_ARM_MAIN_SRC 3
	#define IMX7D_PLL_ARM_MAIN_BYPASS 4
	#define IMX7D_PLL_SYS_MAIN 5
	#define IMX7D_PLL_SYS_MAIN_CLK 6
	#define IMX7D_PLL_SYS_MAIN_SRC 7
	#define IMX7D_PLL_SYS_MAIN_BYPASS 8
	#define IMX7D_PLL_SYS_MAIN_480M 9
	#define IMX7D_PLL_SYS_MAIN_240M 10
	#define IMX7D_PLL_SYS_MAIN_120M 11
	#define IMX7D_PLL_SYS_MAIN_480M_CLK 12
	#define IMX7D_PLL_SYS_MAIN_240M_CLK 13
	#define IMX7D_PLL_SYS_MAIN_120M_CLK 14
	#define IMX7D_PLL_SYS_PFD0_392M_CLK 15
	#define IMX7D_PLL_SYS_PFD0_196M 16
	#define IMX7D_PLL_SYS_PFD0_196M_CLK 17
	#define IMX7D_PLL_SYS_PFD1_332M_CLK 18
	#define IMX7D_PLL_SYS_PFD1_166M 19
	#define IMX7D_PLL_SYS_PFD1_166M_CLK 20
	#define IMX7D_PLL_SYS_PFD2_270M_CLK 21
	#define IMX7D_PLL_SYS_PFD2_135M 22
	#define IMX7D_PLL_SYS_PFD2_135M_CLK 23
	#define IMX7D_PLL_SYS_PFD3_CLK 24
	#define IMX7D_PLL_SYS_PFD4_CLK 25
	#define IMX7D_PLL_SYS_PFD5_CLK 26
	#define IMX7D_PLL_SYS_PFD6_CLK 27
	#define IMX7D_PLL_SYS_PFD7_CLK 28
	#define IMX7D_PLL_ENET_MAIN 29
	#define IMX7D_PLL_ENET_MAIN_CLK 30
	#define IMX7D_PLL_ENET_MAIN_SRC 31
	#define IMX7D_PLL_ENET_MAIN_BYPASS 32
	#define IMX7D_PLL_ENET_MAIN_500M 33
	#define IMX7D_PLL_ENET_MAIN_250M 34
	#define IMX7D_PLL_ENET_MAIN_125M 35
	#define IMX7D_PLL_ENET_MAIN_100M 36
	#define IMX7D_PLL_ENET_MAIN_50M 37
	#define IMX7D_PLL_ENET_MAIN_40M 38
	#define IMX7D_PLL_ENET_MAIN_25M 39
	#define IMX7D_PLL_ENET_MAIN_500M_CLK 40
	#define IMX7D_PLL_ENET_MAIN_250M_CLK 41
	#define IMX7D_PLL_ENET_MAIN_125M_CLK 42
	#define IMX7D_PLL_ENET_MAIN_100M_CLK 43
	#define IMX7D_PLL_ENET_MAIN_50M_CLK 44
	#define IMX7D_PLL_ENET_MAIN_40M_CLK 45
	#define IMX7D_PLL_ENET_MAIN_25M_CLK 46
	#define IMX7D_PLL_DRAM_MAIN 47
	#define IMX7D_PLL_DRAM_MAIN_CLK 48
	#define IMX7D_PLL_DRAM_MAIN_SRC 49
	#define IMX7D_PLL_DRAM_MAIN_BYPASS 50
	#define IMX7D_PLL_DRAM_MAIN_533M 51
	#define IMX7D_PLL_DRAM_MAIN_533M_CLK 52
	#define IMX7D_PLL_AUDIO_MAIN 53
	#define IMX7D_PLL_AUDIO_MAIN_CLK 54
	#define IMX7D_PLL_AUDIO_MAIN_SRC 55
	#define IMX7D_PLL_AUDIO_MAIN_BYPASS 56
	#define IMX7D_PLL_VIDEO_MAIN_CLK 57
	#define IMX7D_PLL_VIDEO_MAIN 58
	#define IMX7D_PLL_VIDEO_MAIN_SRC 59
	#define IMX7D_PLL_VIDEO_MAIN_BYPASS 60
	#define IMX7D_USB_MAIN_480M_CLK 61
	#define IMX7D_ARM_A7_ROOT_CLK 62
	#define IMX7D_ARM_A7_ROOT_SRC 63
	#define IMX7D_ARM_A7_ROOT_CG 64
	#define IMX7D_ARM_A7_ROOT_DIV 65
	#define IMX7D_ARM_M4_ROOT_CLK 66
	#define IMX7D_ARM_M4_ROOT_SRC 67
	#define IMX7D_ARM_M4_ROOT_CG 68
	#define IMX7D_ARM_M4_ROOT_DIV 69
	#define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */
	#define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */
	#define IMX7D_ARM_M0_ROOT_CG 72 /* unused */
	#define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */
	#define IMX7D_MAIN_AXI_ROOT_CLK 74
	#define IMX7D_MAIN_AXI_ROOT_SRC 75
	#define IMX7D_MAIN_AXI_ROOT_CG 76
	#define IMX7D_MAIN_AXI_ROOT_DIV 77
	#define IMX7D_DISP_AXI_ROOT_CLK 78
	#define IMX7D_DISP_AXI_ROOT_SRC 79
	#define IMX7D_DISP_AXI_ROOT_CG 80
	#define IMX7D_DISP_AXI_ROOT_DIV 81
	#define IMX7D_ENET_AXI_ROOT_CLK 82
	#define IMX7D_ENET_AXI_ROOT_SRC 83
	#define IMX7D_ENET_AXI_ROOT_CG 84
	#define IMX7D_ENET_AXI_ROOT_DIV 85
	#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86
	#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87
	#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88
	#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89
	#define IMX7D_AHB_CHANNEL_ROOT_CLK 90
	#define IMX7D_AHB_CHANNEL_ROOT_SRC 91
	#define IMX7D_AHB_CHANNEL_ROOT_CG 92
	#define IMX7D_AHB_CHANNEL_ROOT_DIV 93
	#define IMX7D_DRAM_PHYM_ROOT_CLK 94
	#define IMX7D_DRAM_PHYM_ROOT_SRC 95
	#define IMX7D_DRAM_PHYM_ROOT_CG 96
	#define IMX7D_DRAM_PHYM_ROOT_DIV 97
	#define IMX7D_DRAM_ROOT_CLK 98
	#define IMX7D_DRAM_ROOT_SRC 99
	#define IMX7D_DRAM_ROOT_CG 100
	#define IMX7D_DRAM_ROOT_DIV 101
	#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102
	#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103
	#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104
	#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105
	#define IMX7D_DRAM_ALT_ROOT_CLK 106
	#define IMX7D_DRAM_ALT_ROOT_SRC 107
	#define IMX7D_DRAM_ALT_ROOT_CG 108
	#define IMX7D_DRAM_ALT_ROOT_DIV 109
	#define IMX7D_USB_HSIC_ROOT_CLK 110
	#define IMX7D_USB_HSIC_ROOT_SRC 111
	#define IMX7D_USB_HSIC_ROOT_CG 112
	#define IMX7D_USB_HSIC_ROOT_DIV 113
	#define IMX7D_PCIE_CTRL_ROOT_CLK 114
	#define IMX7D_PCIE_CTRL_ROOT_SRC 115
	#define IMX7D_PCIE_CTRL_ROOT_CG 116
	#define IMX7D_PCIE_CTRL_ROOT_DIV 117
	#define IMX7D_PCIE_PHY_ROOT_CLK 118
	#define IMX7D_PCIE_PHY_ROOT_SRC 119
	#define IMX7D_PCIE_PHY_ROOT_CG 120
	#define IMX7D_PCIE_PHY_ROOT_DIV 121
	#define IMX7D_EPDC_PIXEL_ROOT_CLK 122
	#define IMX7D_EPDC_PIXEL_ROOT_SRC 123
	#define IMX7D_EPDC_PIXEL_ROOT_CG 124
	#define IMX7D_EPDC_PIXEL_ROOT_DIV 125
	#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126
	#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127
	#define IMX7D_LCDIF_PIXEL_ROOT_CG 128
	#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129
	#define IMX7D_MIPI_DSI_ROOT_CLK 130
	#define IMX7D_MIPI_DSI_ROOT_SRC 131
	#define IMX7D_MIPI_DSI_ROOT_CG 132
	#define IMX7D_MIPI_DSI_ROOT_DIV 133
	#define IMX7D_MIPI_CSI_ROOT_CLK 134
	#define IMX7D_MIPI_CSI_ROOT_SRC 135
	#define IMX7D_MIPI_CSI_ROOT_CG 136
	#define IMX7D_MIPI_CSI_ROOT_DIV 137
	#define IMX7D_MIPI_DPHY_ROOT_CLK 138
	#define IMX7D_MIPI_DPHY_ROOT_SRC 139
	#define IMX7D_MIPI_DPHY_ROOT_CG 140
	#define IMX7D_MIPI_DPHY_ROOT_DIV 141
	#define IMX7D_SAI1_ROOT_CLK 142
	#define IMX7D_SAI1_ROOT_SRC 143
	#define IMX7D_SAI1_ROOT_CG 144
	#define IMX7D_SAI1_ROOT_DIV 145
	#define IMX7D_SAI2_ROOT_CLK 146
	#define IMX7D_SAI2_ROOT_SRC 147
	#define IMX7D_SAI2_ROOT_CG 148
	#define IMX7D_SAI2_ROOT_DIV 149
	#define IMX7D_SAI3_ROOT_CLK 150
	#define IMX7D_SAI3_ROOT_SRC 151
	#define IMX7D_SAI3_ROOT_CG 152
	#define IMX7D_SAI3_ROOT_DIV 153
	#define IMX7D_SPDIF_ROOT_CLK 154
	#define IMX7D_SPDIF_ROOT_SRC 155
	#define IMX7D_SPDIF_ROOT_CG 156
	#define IMX7D_SPDIF_ROOT_DIV 157
	#define IMX7D_ENET1_IPG_ROOT_CLK 158
	#define IMX7D_ENET1_REF_ROOT_SRC 159
	#define IMX7D_ENET1_REF_ROOT_CG 160
	#define IMX7D_ENET1_REF_ROOT_DIV 161
	#define IMX7D_ENET1_TIME_ROOT_CLK 162
	#define IMX7D_ENET1_TIME_ROOT_SRC 163
	#define IMX7D_ENET1_TIME_ROOT_CG 164
	#define IMX7D_ENET1_TIME_ROOT_DIV 165
	#define IMX7D_ENET2_IPG_ROOT_CLK 166
	#define IMX7D_ENET2_REF_ROOT_SRC 167
	#define IMX7D_ENET2_REF_ROOT_CG 168
	#define IMX7D_ENET2_REF_ROOT_DIV 169
	#define IMX7D_ENET2_TIME_ROOT_CLK 170
	#define IMX7D_ENET2_TIME_ROOT_SRC 171
	#define IMX7D_ENET2_TIME_ROOT_CG 172
	#define IMX7D_ENET2_TIME_ROOT_DIV 173
	#define IMX7D_ENET_PHY_REF_ROOT_CLK 174
	#define IMX7D_ENET_PHY_REF_ROOT_SRC 175
	#define IMX7D_ENET_PHY_REF_ROOT_CG 176
	#define IMX7D_ENET_PHY_REF_ROOT_DIV 177
	#define IMX7D_EIM_ROOT_CLK 178
	#define IMX7D_EIM_ROOT_SRC 179
	#define IMX7D_EIM_ROOT_CG 180
	#define IMX7D_EIM_ROOT_DIV 181
	#define IMX7D_NAND_ROOT_CLK 182
	#define IMX7D_NAND_ROOT_SRC 183
	#define IMX7D_NAND_ROOT_CG 184
	#define IMX7D_NAND_ROOT_DIV 185
	#define IMX7D_QSPI_ROOT_CLK 186
	#define IMX7D_QSPI_ROOT_SRC 187
	#define IMX7D_QSPI_ROOT_CG 188
	#define IMX7D_QSPI_ROOT_DIV 189
	#define IMX7D_USDHC1_ROOT_CLK 190
	#define IMX7D_USDHC1_ROOT_SRC 191
	#define IMX7D_USDHC1_ROOT_CG 192
	#define IMX7D_USDHC1_ROOT_DIV 193
	#define IMX7D_USDHC2_ROOT_CLK 194
	#define IMX7D_USDHC2_ROOT_SRC 195
	#define IMX7D_USDHC2_ROOT_CG 196
	#define IMX7D_USDHC2_ROOT_DIV 197
	#define IMX7D_USDHC3_ROOT_CLK 198
	#define IMX7D_USDHC3_ROOT_SRC 199
	#define IMX7D_USDHC3_ROOT_CG 200
	#define IMX7D_USDHC3_ROOT_DIV 201
	#define IMX7D_CAN1_ROOT_CLK 202
	#define IMX7D_CAN1_ROOT_SRC 203
	#define IMX7D_CAN1_ROOT_CG 204
	#define IMX7D_CAN1_ROOT_DIV 205
	#define IMX7D_CAN2_ROOT_CLK 206
	#define IMX7D_CAN2_ROOT_SRC 207
	#define IMX7D_CAN2_ROOT_CG 208
	#define IMX7D_CAN2_ROOT_DIV 209
	#define IMX7D_I2C1_ROOT_CLK 210
	#define IMX7D_I2C1_ROOT_SRC 211
	#define IMX7D_I2C1_ROOT_CG 212
	#define IMX7D_I2C1_ROOT_DIV 213
	#define IMX7D_I2C2_ROOT_CLK 214
	#define IMX7D_I2C2_ROOT_SRC 215
	#define IMX7D_I2C2_ROOT_CG 216
	#define IMX7D_I2C2_ROOT_DIV 217
	#define IMX7D_I2C3_ROOT_CLK 218
	#define IMX7D_I2C3_ROOT_SRC 219
	#define IMX7D_I2C3_ROOT_CG 220
	#define IMX7D_I2C3_ROOT_DIV 221
	#define IMX7D_I2C4_ROOT_CLK 222
	#define IMX7D_I2C4_ROOT_SRC 223
	#define IMX7D_I2C4_ROOT_CG 224
	#define IMX7D_I2C4_ROOT_DIV 225
	#define IMX7D_UART1_ROOT_CLK 226
	#define IMX7D_UART1_ROOT_SRC 227
	#define IMX7D_UART1_ROOT_CG 228
	#define IMX7D_UART1_ROOT_DIV 229
	#define IMX7D_UART2_ROOT_CLK 230
	#define IMX7D_UART2_ROOT_SRC 231
	#define IMX7D_UART2_ROOT_CG 232
	#define IMX7D_UART2_ROOT_DIV 233
	#define IMX7D_UART3_ROOT_CLK 234
	#define IMX7D_UART3_ROOT_SRC 235
	#define IMX7D_UART3_ROOT_CG 236
	#define IMX7D_UART3_ROOT_DIV 237
	#define IMX7D_UART4_ROOT_CLK 238
	#define IMX7D_UART4_ROOT_SRC 239
	#define IMX7D_UART4_ROOT_CG 240
	#define IMX7D_UART4_ROOT_DIV 241
	#define IMX7D_UART5_ROOT_CLK 242
	#define IMX7D_UART5_ROOT_SRC 243
	#define IMX7D_UART5_ROOT_CG 244
	#define IMX7D_UART5_ROOT_DIV 245
	#define IMX7D_UART6_ROOT_CLK 246
	#define IMX7D_UART6_ROOT_SRC 247
	#define IMX7D_UART6_ROOT_CG 248
	#define IMX7D_UART6_ROOT_DIV 249
	#define IMX7D_UART7_ROOT_CLK 250
	#define IMX7D_UART7_ROOT_SRC 251
	#define IMX7D_UART7_ROOT_CG 252
	#define IMX7D_UART7_ROOT_DIV 253
	#define IMX7D_ECSPI1_ROOT_CLK 254
	#define IMX7D_ECSPI1_ROOT_SRC 255
	#define IMX7D_ECSPI1_ROOT_CG 256
	#define IMX7D_ECSPI1_ROOT_DIV 257
	#define IMX7D_ECSPI2_ROOT_CLK 258
	#define IMX7D_ECSPI2_ROOT_SRC 259
	#define IMX7D_ECSPI2_ROOT_CG 260
	#define IMX7D_ECSPI2_ROOT_DIV 261
	#define IMX7D_ECSPI3_ROOT_CLK 262
	#define IMX7D_ECSPI3_ROOT_SRC 263
	#define IMX7D_ECSPI3_ROOT_CG 264
	#define IMX7D_ECSPI3_ROOT_DIV 265
	#define IMX7D_ECSPI4_ROOT_CLK 266
	#define IMX7D_ECSPI4_ROOT_SRC 267
	#define IMX7D_ECSPI4_ROOT_CG 268
	#define IMX7D_ECSPI4_ROOT_DIV 269
	#define IMX7D_PWM1_ROOT_CLK 270
	#define IMX7D_PWM1_ROOT_SRC 271
	#define IMX7D_PWM1_ROOT_CG 272
	#define IMX7D_PWM1_ROOT_DIV 273
	#define IMX7D_PWM2_ROOT_CLK 274
	#define IMX7D_PWM2_ROOT_SRC 275
	#define IMX7D_PWM2_ROOT_CG 276
	#define IMX7D_PWM2_ROOT_DIV 277
	#define IMX7D_PWM3_ROOT_CLK 278
	#define IMX7D_PWM3_ROOT_SRC 279
	#define IMX7D_PWM3_ROOT_CG 280
	#define IMX7D_PWM3_ROOT_DIV 281
	#define IMX7D_PWM4_ROOT_CLK 282
	#define IMX7D_PWM4_ROOT_SRC 283
	#define IMX7D_PWM4_ROOT_CG 284
	#define IMX7D_PWM4_ROOT_DIV 285
	#define IMX7D_FLEXTIMER1_ROOT_CLK 286
	#define IMX7D_FLEXTIMER1_ROOT_SRC 287
	#define IMX7D_FLEXTIMER1_ROOT_CG 288
	#define IMX7D_FLEXTIMER1_ROOT_DIV 289
	#define IMX7D_FLEXTIMER2_ROOT_CLK 290
	#define IMX7D_FLEXTIMER2_ROOT_SRC 291
	#define IMX7D_FLEXTIMER2_ROOT_CG 292
	#define IMX7D_FLEXTIMER2_ROOT_DIV 293
	#define IMX7D_SIM1_ROOT_CLK 294
	#define IMX7D_SIM1_ROOT_SRC 295
	#define IMX7D_SIM1_ROOT_CG 296
	#define IMX7D_SIM1_ROOT_DIV 297
	#define IMX7D_SIM2_ROOT_CLK 298
	#define IMX7D_SIM2_ROOT_SRC 299
	#define IMX7D_SIM2_ROOT_CG 300
	#define IMX7D_SIM2_ROOT_DIV 301
	#define IMX7D_GPT1_ROOT_CLK 302
	#define IMX7D_GPT1_ROOT_SRC 303
	#define IMX7D_GPT1_ROOT_CG 304
	#define IMX7D_GPT1_ROOT_DIV 305
	#define IMX7D_GPT2_ROOT_CLK 306
	#define IMX7D_GPT2_ROOT_SRC 307
	#define IMX7D_GPT2_ROOT_CG 308
	#define IMX7D_GPT2_ROOT_DIV 309
	#define IMX7D_GPT3_ROOT_CLK 310
	#define IMX7D_GPT3_ROOT_SRC 311
	#define IMX7D_GPT3_ROOT_CG 312
	#define IMX7D_GPT3_ROOT_DIV 313
	#define IMX7D_GPT4_ROOT_CLK 314
	#define IMX7D_GPT4_ROOT_SRC 315
	#define IMX7D_GPT4_ROOT_CG 316
	#define IMX7D_GPT4_ROOT_DIV 317
	#define IMX7D_TRACE_ROOT_CLK 318
	#define IMX7D_TRACE_ROOT_SRC 319
	#define IMX7D_TRACE_ROOT_CG 320
	#define IMX7D_TRACE_ROOT_DIV 321
	#define IMX7D_WDOG1_ROOT_CLK 322
	#define IMX7D_WDOG_ROOT_SRC 323
	#define IMX7D_WDOG_ROOT_CG 324
	#define IMX7D_WDOG_ROOT_DIV 325
	#define IMX7D_CSI_MCLK_ROOT_CLK 326
	#define IMX7D_CSI_MCLK_ROOT_SRC 327
	#define IMX7D_CSI_MCLK_ROOT_CG 328
	#define IMX7D_CSI_MCLK_ROOT_DIV 329
	#define IMX7D_AUDIO_MCLK_ROOT_CLK 330
	#define IMX7D_AUDIO_MCLK_ROOT_SRC 331
	#define IMX7D_AUDIO_MCLK_ROOT_CG 332
	#define IMX7D_AUDIO_MCLK_ROOT_DIV 333
	#define IMX7D_WRCLK_ROOT_CLK 334
	#define IMX7D_WRCLK_ROOT_SRC 335
	#define IMX7D_WRCLK_ROOT_CG 336
	#define IMX7D_WRCLK_ROOT_DIV 337
	#define IMX7D_CLKO1_ROOT_SRC 338
	#define IMX7D_CLKO1_ROOT_CG 339
	#define IMX7D_CLKO1_ROOT_DIV 340
	#define IMX7D_CLKO2_ROOT_SRC 341
	#define IMX7D_CLKO2_ROOT_CG 342
	#define IMX7D_CLKO2_ROOT_DIV 343
	#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344
	#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345
	#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346
	#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347
	#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348
	#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349
	#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350
	#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351
	#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352
	#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353
	#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354
	#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355
	#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356
	#define IMX7D_SAI1_ROOT_PRE_DIV 357
	#define IMX7D_SAI2_ROOT_PRE_DIV 358
	#define IMX7D_SAI3_ROOT_PRE_DIV 359
	#define IMX7D_SPDIF_ROOT_PRE_DIV 360
	#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361
	#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362
	#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363
	#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364
	#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365
	#define IMX7D_EIM_ROOT_PRE_DIV 366
	#define IMX7D_NAND_ROOT_PRE_DIV 367
	#define IMX7D_QSPI_ROOT_PRE_DIV 368
	#define IMX7D_USDHC1_ROOT_PRE_DIV 369
	#define IMX7D_USDHC2_ROOT_PRE_DIV 370
	#define IMX7D_USDHC3_ROOT_PRE_DIV 371
	#define IMX7D_CAN1_ROOT_PRE_DIV 372
	#define IMX7D_CAN2_ROOT_PRE_DIV 373
	#define IMX7D_I2C1_ROOT_PRE_DIV 374
	#define IMX7D_I2C2_ROOT_PRE_DIV 375
	#define IMX7D_I2C3_ROOT_PRE_DIV 376
	#define IMX7D_I2C4_ROOT_PRE_DIV 377
	#define IMX7D_UART1_ROOT_PRE_DIV 378
	#define IMX7D_UART2_ROOT_PRE_DIV 379
	#define IMX7D_UART3_ROOT_PRE_DIV 380
	#define IMX7D_UART4_ROOT_PRE_DIV 381
	#define IMX7D_UART5_ROOT_PRE_DIV 382
	#define IMX7D_UART6_ROOT_PRE_DIV 383
	#define IMX7D_UART7_ROOT_PRE_DIV 384
	#define IMX7D_ECSPI1_ROOT_PRE_DIV 385
	#define IMX7D_ECSPI2_ROOT_PRE_DIV 386
	#define IMX7D_ECSPI3_ROOT_PRE_DIV 387
	#define IMX7D_ECSPI4_ROOT_PRE_DIV 388
	#define IMX7D_PWM1_ROOT_PRE_DIV 389
	#define IMX7D_PWM2_ROOT_PRE_DIV 390
	#define IMX7D_PWM3_ROOT_PRE_DIV 391
	#define IMX7D_PWM4_ROOT_PRE_DIV 392
	#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393
	#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394
	#define IMX7D_SIM1_ROOT_PRE_DIV 395
	#define IMX7D_SIM2_ROOT_PRE_DIV 396
	#define IMX7D_GPT1_ROOT_PRE_DIV 397
	#define IMX7D_GPT2_ROOT_PRE_DIV 398
	#define IMX7D_GPT3_ROOT_PRE_DIV 399
	#define IMX7D_GPT4_ROOT_PRE_DIV 400
	#define IMX7D_TRACE_ROOT_PRE_DIV 401
	#define IMX7D_WDOG_ROOT_PRE_DIV 402
	#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403
	#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404
	#define IMX7D_WRCLK_ROOT_PRE_DIV 405
	#define IMX7D_CLKO1_ROOT_PRE_DIV 406
	#define IMX7D_CLKO2_ROOT_PRE_DIV 407
	#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408
	#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409
	#define IMX7D_LVDS1_IN_CLK 410
	#define IMX7D_LVDS1_OUT_SEL 411
	#define IMX7D_LVDS1_OUT_CLK 412
	#define IMX7D_CLK_DUMMY 413
	#define IMX7D_GPT_3M_CLK 414
	#define IMX7D_OCRAM_CLK 415
	#define IMX7D_OCRAM_S_CLK 416
	#define IMX7D_WDOG2_ROOT_CLK 417
	#define IMX7D_WDOG3_ROOT_CLK 418
	#define IMX7D_WDOG4_ROOT_CLK 419
	#define IMX7D_SDMA_CORE_CLK 420
	#define IMX7D_USB1_MAIN_480M_CLK 421
	#define IMX7D_USB_CTRL_CLK 422
	#define IMX7D_USB_PHY1_CLK 423
	#define IMX7D_USB_PHY2_CLK 424
	#define IMX7D_IPG_ROOT_CLK 425
	#define IMX7D_SAI1_IPG_CLK 426
	#define IMX7D_SAI2_IPG_CLK 427
	#define IMX7D_SAI3_IPG_CLK 428
	#define IMX7D_PLL_AUDIO_TEST_DIV 429
	#define IMX7D_PLL_AUDIO_POST_DIV 430
	#define IMX7D_PLL_VIDEO_TEST_DIV 431
	#define IMX7D_PLL_VIDEO_POST_DIV 432
	#define IMX7D_MU_ROOT_CLK 433
	#define IMX7D_SEMA4_HS_ROOT_CLK 434
	#define IMX7D_PLL_DRAM_TEST_DIV 435
	#define IMX7D_ADC_ROOT_CLK 436
	#define IMX7D_CLK_ARM 437
	#define IMX7D_CKIL 438
	#define IMX7D_OCOTP_CLK 439
	#define IMX7D_NAND_RAWNAND_CLK 440
	#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
	#define IMX7D_SNVS_CLK 442
	#define IMX7D_CAAM_CLK 443
	#define IMX7D_KPP_ROOT_CLK 444
	-#define IMX7D_CLK_END 445
	+#define IMX7D_PXP_CLK 445
	+#define IMX7D_CLK_END 446
	#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx8mm-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx8mm-clock.h
	index edeece2289f0..e63a5530aed7 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/imx8mm-clock.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/imx8mm-clock.h
	@@ -1,270 +1,279 @@
	/* SPDX-License-Identifier: GPL-2.0 */
	/*
	* Copyright 2017-2018 NXP
	*/

	#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H
	#define __DT_BINDINGS_CLOCK_IMX8MM_H

	#define IMX8MM_CLK_DUMMY 0
	#define IMX8MM_CLK_32K 1
	#define IMX8MM_CLK_24M 2
	#define IMX8MM_OSC_HDMI_CLK 3
	#define IMX8MM_CLK_EXT1 4
	#define IMX8MM_CLK_EXT2 5
	#define IMX8MM_CLK_EXT3 6
	#define IMX8MM_CLK_EXT4 7
	#define IMX8MM_AUDIO_PLL1_REF_SEL 8
	#define IMX8MM_AUDIO_PLL2_REF_SEL 9
	#define IMX8MM_VIDEO_PLL1_REF_SEL 10
	#define IMX8MM_DRAM_PLL_REF_SEL 11
	#define IMX8MM_GPU_PLL_REF_SEL 12
	#define IMX8MM_VPU_PLL_REF_SEL 13
	#define IMX8MM_ARM_PLL_REF_SEL 14
	#define IMX8MM_SYS_PLL1_REF_SEL 15
	#define IMX8MM_SYS_PLL2_REF_SEL 16
	#define IMX8MM_SYS_PLL3_REF_SEL 17
	#define IMX8MM_AUDIO_PLL1 18
	#define IMX8MM_AUDIO_PLL2 19
	#define IMX8MM_VIDEO_PLL1 20
	#define IMX8MM_DRAM_PLL 21
	#define IMX8MM_GPU_PLL 22
	#define IMX8MM_VPU_PLL 23
	#define IMX8MM_ARM_PLL 24
	#define IMX8MM_SYS_PLL1 25
	#define IMX8MM_SYS_PLL2 26
	#define IMX8MM_SYS_PLL3 27
	#define IMX8MM_AUDIO_PLL1_BYPASS 28
	#define IMX8MM_AUDIO_PLL2_BYPASS 29
	#define IMX8MM_VIDEO_PLL1_BYPASS 30
	#define IMX8MM_DRAM_PLL_BYPASS 31
	#define IMX8MM_GPU_PLL_BYPASS 32
	#define IMX8MM_VPU_PLL_BYPASS 33
	#define IMX8MM_ARM_PLL_BYPASS 34
	#define IMX8MM_SYS_PLL1_BYPASS 35
	#define IMX8MM_SYS_PLL2_BYPASS 36
	#define IMX8MM_SYS_PLL3_BYPASS 37
	#define IMX8MM_AUDIO_PLL1_OUT 38
	#define IMX8MM_AUDIO_PLL2_OUT 39
	#define IMX8MM_VIDEO_PLL1_OUT 40
	#define IMX8MM_DRAM_PLL_OUT 41
	#define IMX8MM_GPU_PLL_OUT 42
	#define IMX8MM_VPU_PLL_OUT 43
	#define IMX8MM_ARM_PLL_OUT 44
	#define IMX8MM_SYS_PLL1_OUT 45
	#define IMX8MM_SYS_PLL2_OUT 46
	#define IMX8MM_SYS_PLL3_OUT 47
	#define IMX8MM_SYS_PLL1_40M 48
	#define IMX8MM_SYS_PLL1_80M 49
	#define IMX8MM_SYS_PLL1_100M 50
	#define IMX8MM_SYS_PLL1_133M 51
	#define IMX8MM_SYS_PLL1_160M 52
	#define IMX8MM_SYS_PLL1_200M 53
	#define IMX8MM_SYS_PLL1_266M 54
	#define IMX8MM_SYS_PLL1_400M 55
	#define IMX8MM_SYS_PLL1_800M 56
	#define IMX8MM_SYS_PLL2_50M 57
	#define IMX8MM_SYS_PLL2_100M 58
	#define IMX8MM_SYS_PLL2_125M 59
	#define IMX8MM_SYS_PLL2_166M 60
	#define IMX8MM_SYS_PLL2_200M 61
	#define IMX8MM_SYS_PLL2_250M 62
	#define IMX8MM_SYS_PLL2_333M 63
	#define IMX8MM_SYS_PLL2_500M 64
	#define IMX8MM_SYS_PLL2_1000M 65

	/* core */
	#define IMX8MM_CLK_A53_SRC 66
	#define IMX8MM_CLK_M4_SRC 67
	#define IMX8MM_CLK_VPU_SRC 68
	#define IMX8MM_CLK_GPU3D_SRC 69
	#define IMX8MM_CLK_GPU2D_SRC 70
	#define IMX8MM_CLK_A53_CG 71
	#define IMX8MM_CLK_M4_CG 72
	#define IMX8MM_CLK_VPU_CG 73
	#define IMX8MM_CLK_GPU3D_CG 74
	#define IMX8MM_CLK_GPU2D_CG 75
	#define IMX8MM_CLK_A53_DIV 76
	#define IMX8MM_CLK_M4_DIV 77
	#define IMX8MM_CLK_VPU_DIV 78
	#define IMX8MM_CLK_GPU3D_DIV 79
	#define IMX8MM_CLK_GPU2D_DIV 80

	/* bus */
	#define IMX8MM_CLK_MAIN_AXI 81
	#define IMX8MM_CLK_ENET_AXI 82
	#define IMX8MM_CLK_NAND_USDHC_BUS 83
	#define IMX8MM_CLK_VPU_BUS 84
	#define IMX8MM_CLK_DISP_AXI 85
	#define IMX8MM_CLK_DISP_APB 86
	#define IMX8MM_CLK_DISP_RTRM 87
	#define IMX8MM_CLK_USB_BUS 88
	#define IMX8MM_CLK_GPU_AXI 89
	#define IMX8MM_CLK_GPU_AHB 90
	#define IMX8MM_CLK_NOC 91
	#define IMX8MM_CLK_NOC_APB 92

	#define IMX8MM_CLK_AHB 93
	#define IMX8MM_CLK_AUDIO_AHB 94
	#define IMX8MM_CLK_IPG_ROOT 95
	#define IMX8MM_CLK_IPG_AUDIO_ROOT 96

	#define IMX8MM_CLK_DRAM_ALT 97
	#define IMX8MM_CLK_DRAM_APB 98
	#define IMX8MM_CLK_VPU_G1 99
	#define IMX8MM_CLK_VPU_G2 100
	#define IMX8MM_CLK_DISP_DTRC 101
	#define IMX8MM_CLK_DISP_DC8000 102
	#define IMX8MM_CLK_PCIE1_CTRL 103
	#define IMX8MM_CLK_PCIE1_PHY 104
	#define IMX8MM_CLK_PCIE1_AUX 105
	#define IMX8MM_CLK_DC_PIXEL 106
	#define IMX8MM_CLK_LCDIF_PIXEL 107
	#define IMX8MM_CLK_SAI1 108
	#define IMX8MM_CLK_SAI2 109
	#define IMX8MM_CLK_SAI3 110
	#define IMX8MM_CLK_SAI4 111
	#define IMX8MM_CLK_SAI5 112
	#define IMX8MM_CLK_SAI6 113
	#define IMX8MM_CLK_SPDIF1 114
	#define IMX8MM_CLK_SPDIF2 115
	#define IMX8MM_CLK_ENET_REF 116
	#define IMX8MM_CLK_ENET_TIMER 117
	#define IMX8MM_CLK_ENET_PHY_REF 118
	#define IMX8MM_CLK_NAND 119
	#define IMX8MM_CLK_QSPI 120
	#define IMX8MM_CLK_USDHC1 121
	#define IMX8MM_CLK_USDHC2 122
	#define IMX8MM_CLK_I2C1 123
	#define IMX8MM_CLK_I2C2 124
	#define IMX8MM_CLK_I2C3 125
	#define IMX8MM_CLK_I2C4 126
	#define IMX8MM_CLK_UART1 127
	#define IMX8MM_CLK_UART2 128
	#define IMX8MM_CLK_UART3 129
	#define IMX8MM_CLK_UART4 130
	#define IMX8MM_CLK_USB_CORE_REF 131
	#define IMX8MM_CLK_USB_PHY_REF 132
	#define IMX8MM_CLK_ECSPI1 133
	#define IMX8MM_CLK_ECSPI2 134
	#define IMX8MM_CLK_PWM1 135
	#define IMX8MM_CLK_PWM2 136
	#define IMX8MM_CLK_PWM3 137
	#define IMX8MM_CLK_PWM4 138
	#define IMX8MM_CLK_GPT1 139
	#define IMX8MM_CLK_WDOG 140
	#define IMX8MM_CLK_WRCLK 141
	#define IMX8MM_CLK_DSI_CORE 142
	#define IMX8MM_CLK_DSI_PHY_REF 143
	#define IMX8MM_CLK_DSI_DBI 144
	#define IMX8MM_CLK_USDHC3 145
	#define IMX8MM_CLK_CSI1_CORE 146
	#define IMX8MM_CLK_CSI1_PHY_REF 147
	#define IMX8MM_CLK_CSI1_ESC 148
	#define IMX8MM_CLK_CSI2_CORE 149
	#define IMX8MM_CLK_CSI2_PHY_REF 150
	#define IMX8MM_CLK_CSI2_ESC 151
	#define IMX8MM_CLK_PCIE2_CTRL 152
	#define IMX8MM_CLK_PCIE2_PHY 153
	#define IMX8MM_CLK_PCIE2_AUX 154
	#define IMX8MM_CLK_ECSPI3 155
	#define IMX8MM_CLK_PDM 156
	#define IMX8MM_CLK_VPU_H1 157
	#define IMX8MM_CLK_CLKO1 158

	#define IMX8MM_CLK_ECSPI1_ROOT 159
	#define IMX8MM_CLK_ECSPI2_ROOT 160
	#define IMX8MM_CLK_ECSPI3_ROOT 161
	#define IMX8MM_CLK_ENET1_ROOT 162
	#define IMX8MM_CLK_GPT1_ROOT 163
	#define IMX8MM_CLK_I2C1_ROOT 164
	#define IMX8MM_CLK_I2C2_ROOT 165
	#define IMX8MM_CLK_I2C3_ROOT 166
	#define IMX8MM_CLK_I2C4_ROOT 167
	#define IMX8MM_CLK_OCOTP_ROOT 168
	#define IMX8MM_CLK_PCIE1_ROOT 169
	#define IMX8MM_CLK_PWM1_ROOT 170
	#define IMX8MM_CLK_PWM2_ROOT 171
	#define IMX8MM_CLK_PWM3_ROOT 172
	#define IMX8MM_CLK_PWM4_ROOT 173
	#define IMX8MM_CLK_QSPI_ROOT 174
	#define IMX8MM_CLK_NAND_ROOT 175
	#define IMX8MM_CLK_SAI1_ROOT 176
	#define IMX8MM_CLK_SAI1_IPG 177
	#define IMX8MM_CLK_SAI2_ROOT 178
	#define IMX8MM_CLK_SAI2_IPG 179
	#define IMX8MM_CLK_SAI3_ROOT 180
	#define IMX8MM_CLK_SAI3_IPG 181
	#define IMX8MM_CLK_SAI4_ROOT 182
	#define IMX8MM_CLK_SAI4_IPG 183
	#define IMX8MM_CLK_SAI5_ROOT 184
	#define IMX8MM_CLK_SAI5_IPG 185
	#define IMX8MM_CLK_SAI6_ROOT 186
	#define IMX8MM_CLK_SAI6_IPG 187
	#define IMX8MM_CLK_UART1_ROOT 188
	#define IMX8MM_CLK_UART2_ROOT 189
	#define IMX8MM_CLK_UART3_ROOT 190
	#define IMX8MM_CLK_UART4_ROOT 191
	#define IMX8MM_CLK_USB1_CTRL_ROOT 192
	#define IMX8MM_CLK_GPU3D_ROOT 193
	#define IMX8MM_CLK_USDHC1_ROOT 194
	#define IMX8MM_CLK_USDHC2_ROOT 195
	#define IMX8MM_CLK_WDOG1_ROOT 196
	#define IMX8MM_CLK_WDOG2_ROOT 197
	#define IMX8MM_CLK_WDOG3_ROOT 198
	#define IMX8MM_CLK_VPU_G1_ROOT 199
	#define IMX8MM_CLK_GPU_BUS_ROOT 200
	#define IMX8MM_CLK_VPU_H1_ROOT 201
	#define IMX8MM_CLK_VPU_G2_ROOT 202
	#define IMX8MM_CLK_PDM_ROOT 203
	#define IMX8MM_CLK_DISP_ROOT 204
	#define IMX8MM_CLK_DISP_AXI_ROOT 205
	#define IMX8MM_CLK_DISP_APB_ROOT 206
	#define IMX8MM_CLK_DISP_RTRM_ROOT 207
	#define IMX8MM_CLK_USDHC3_ROOT 208
	#define IMX8MM_CLK_TMU_ROOT 209
	#define IMX8MM_CLK_VPU_DEC_ROOT 210
	#define IMX8MM_CLK_SDMA1_ROOT 211
	#define IMX8MM_CLK_SDMA2_ROOT 212
	#define IMX8MM_CLK_SDMA3_ROOT 213
	#define IMX8MM_CLK_GPT_3M 214
	#define IMX8MM_CLK_ARM 215
	#define IMX8MM_CLK_PDM_IPG 216
	#define IMX8MM_CLK_GPU2D_ROOT 217
	#define IMX8MM_CLK_MU_ROOT 218
	#define IMX8MM_CLK_CSI1_ROOT 219

	#define IMX8MM_CLK_DRAM_CORE 220
	#define IMX8MM_CLK_DRAM_ALT_ROOT 221

	#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222

	#define IMX8MM_CLK_GPIO1_ROOT 223
	#define IMX8MM_CLK_GPIO2_ROOT 224
	#define IMX8MM_CLK_GPIO3_ROOT 225
	#define IMX8MM_CLK_GPIO4_ROOT 226
	#define IMX8MM_CLK_GPIO5_ROOT 227

	#define IMX8MM_CLK_SNVS_ROOT 228
	#define IMX8MM_CLK_GIC 229

	#define IMX8MM_SYS_PLL1_40M_CG 230
	#define IMX8MM_SYS_PLL1_80M_CG 231
	#define IMX8MM_SYS_PLL1_100M_CG 232
	#define IMX8MM_SYS_PLL1_133M_CG 233
	#define IMX8MM_SYS_PLL1_160M_CG 234
	#define IMX8MM_SYS_PLL1_200M_CG 235
	#define IMX8MM_SYS_PLL1_266M_CG 236
	#define IMX8MM_SYS_PLL1_400M_CG 237
	#define IMX8MM_SYS_PLL2_50M_CG 238
	#define IMX8MM_SYS_PLL2_100M_CG 239
	#define IMX8MM_SYS_PLL2_125M_CG 240
	#define IMX8MM_SYS_PLL2_166M_CG 241
	#define IMX8MM_SYS_PLL2_200M_CG 242
	#define IMX8MM_SYS_PLL2_250M_CG 243
	#define IMX8MM_SYS_PLL2_333M_CG 244
	#define IMX8MM_SYS_PLL2_500M_CG 245

	-#define IMX8MM_CLK_END 246
	+#define IMX8MM_CLK_M4_CORE 246
	+#define IMX8MM_CLK_VPU_CORE 247
	+#define IMX8MM_CLK_GPU3D_CORE 248
	+#define IMX8MM_CLK_GPU2D_CORE 249
	+
	+#define IMX8MM_CLK_CLKO2 250
	+
	+#define IMX8MM_CLK_A53_CORE 251
	+
	+#define IMX8MM_CLK_END 252

	#endif
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx8mn-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx8mn-clock.h
	index 65ac6eb6c733..621ea0e87c67 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/imx8mn-clock.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/imx8mn-clock.h
	@@ -1,233 +1,239 @@
	/* SPDX-License-Identifier: GPL-2.0 */
	/*
	* Copyright 2018-2019 NXP
	*/

	#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H
	#define __DT_BINDINGS_CLOCK_IMX8MN_H

	#define IMX8MN_CLK_DUMMY 0
	#define IMX8MN_CLK_32K 1
	#define IMX8MN_CLK_24M 2
	#define IMX8MN_OSC_HDMI_CLK 3
	#define IMX8MN_CLK_EXT1 4
	#define IMX8MN_CLK_EXT2 5
	#define IMX8MN_CLK_EXT3 6
	#define IMX8MN_CLK_EXT4 7
	#define IMX8MN_AUDIO_PLL1_REF_SEL 8
	#define IMX8MN_AUDIO_PLL2_REF_SEL 9
	#define IMX8MN_VIDEO_PLL1_REF_SEL 10
	#define IMX8MN_DRAM_PLL_REF_SEL 11
	#define IMX8MN_GPU_PLL_REF_SEL 12
	#define IMX8MN_VPU_PLL_REF_SEL 13
	#define IMX8MN_ARM_PLL_REF_SEL 14
	#define IMX8MN_SYS_PLL1_REF_SEL 15
	#define IMX8MN_SYS_PLL2_REF_SEL 16
	#define IMX8MN_SYS_PLL3_REF_SEL 17
	#define IMX8MN_AUDIO_PLL1 18
	#define IMX8MN_AUDIO_PLL2 19
	#define IMX8MN_VIDEO_PLL1 20
	#define IMX8MN_DRAM_PLL 21
	#define IMX8MN_GPU_PLL 22
	#define IMX8MN_VPU_PLL 23
	#define IMX8MN_ARM_PLL 24
	#define IMX8MN_SYS_PLL1 25
	#define IMX8MN_SYS_PLL2 26
	#define IMX8MN_SYS_PLL3 27
	#define IMX8MN_AUDIO_PLL1_BYPASS 28
	#define IMX8MN_AUDIO_PLL2_BYPASS 29
	#define IMX8MN_VIDEO_PLL1_BYPASS 30
	#define IMX8MN_DRAM_PLL_BYPASS 31
	#define IMX8MN_GPU_PLL_BYPASS 32
	#define IMX8MN_VPU_PLL_BYPASS 33
	#define IMX8MN_ARM_PLL_BYPASS 34
	#define IMX8MN_SYS_PLL1_BYPASS 35
	#define IMX8MN_SYS_PLL2_BYPASS 36
	#define IMX8MN_SYS_PLL3_BYPASS 37
	#define IMX8MN_AUDIO_PLL1_OUT 38
	#define IMX8MN_AUDIO_PLL2_OUT 39
	#define IMX8MN_VIDEO_PLL1_OUT 40
	#define IMX8MN_DRAM_PLL_OUT 41
	#define IMX8MN_GPU_PLL_OUT 42
	#define IMX8MN_VPU_PLL_OUT 43
	#define IMX8MN_ARM_PLL_OUT 44
	#define IMX8MN_SYS_PLL1_OUT 45
	#define IMX8MN_SYS_PLL2_OUT 46
	#define IMX8MN_SYS_PLL3_OUT 47
	#define IMX8MN_SYS_PLL1_40M 48
	#define IMX8MN_SYS_PLL1_80M 49
	#define IMX8MN_SYS_PLL1_100M 50
	#define IMX8MN_SYS_PLL1_133M 51
	#define IMX8MN_SYS_PLL1_160M 52
	#define IMX8MN_SYS_PLL1_200M 53
	#define IMX8MN_SYS_PLL1_266M 54
	#define IMX8MN_SYS_PLL1_400M 55
	#define IMX8MN_SYS_PLL1_800M 56
	#define IMX8MN_SYS_PLL2_50M 57
	#define IMX8MN_SYS_PLL2_100M 58
	#define IMX8MN_SYS_PLL2_125M 59
	#define IMX8MN_SYS_PLL2_166M 60
	#define IMX8MN_SYS_PLL2_200M 61
	#define IMX8MN_SYS_PLL2_250M 62
	#define IMX8MN_SYS_PLL2_333M 63
	#define IMX8MN_SYS_PLL2_500M 64
	#define IMX8MN_SYS_PLL2_1000M 65

	/* CORE CLOCK ROOT */
	#define IMX8MN_CLK_A53_SRC 66
	#define IMX8MN_CLK_GPU_CORE_SRC 67
	#define IMX8MN_CLK_GPU_SHADER_SRC 68
	#define IMX8MN_CLK_A53_CG 69
	#define IMX8MN_CLK_GPU_CORE_CG 70
	#define IMX8MN_CLK_GPU_SHADER_CG 71
	#define IMX8MN_CLK_A53_DIV 72
	#define IMX8MN_CLK_GPU_CORE_DIV 73
	#define IMX8MN_CLK_GPU_SHADER_DIV 74

	/* BUS CLOCK ROOT */
	#define IMX8MN_CLK_MAIN_AXI 75
	#define IMX8MN_CLK_ENET_AXI 76
	#define IMX8MN_CLK_NAND_USDHC_BUS 77
	#define IMX8MN_CLK_DISP_AXI 78
	#define IMX8MN_CLK_DISP_APB 79
	#define IMX8MN_CLK_USB_BUS 80
	#define IMX8MN_CLK_GPU_AXI 81
	#define IMX8MN_CLK_GPU_AHB 82
	#define IMX8MN_CLK_NOC 83
	#define IMX8MN_CLK_AHB 84
	#define IMX8MN_CLK_AUDIO_AHB 85

	/* IPG CLOCK ROOT */
	#define IMX8MN_CLK_IPG_ROOT 86
	#define IMX8MN_CLK_IPG_AUDIO_ROOT 87

	/* IP */
	#define IMX8MN_CLK_DRAM_CORE 88
	#define IMX8MN_CLK_DRAM_ALT 89
	#define IMX8MN_CLK_DRAM_APB 90
	#define IMX8MN_CLK_DRAM_ALT_ROOT 91
	#define IMX8MN_CLK_DISP_PIXEL 92
	#define IMX8MN_CLK_SAI2 93
	#define IMX8MN_CLK_SAI3 94
	#define IMX8MN_CLK_SAI5 95
	#define IMX8MN_CLK_SAI6 96
	#define IMX8MN_CLK_SPDIF1 97
	#define IMX8MN_CLK_ENET_REF 98
	#define IMX8MN_CLK_ENET_TIMER 99
	#define IMX8MN_CLK_ENET_PHY_REF 100
	#define IMX8MN_CLK_NAND 101
	#define IMX8MN_CLK_QSPI 102
	#define IMX8MN_CLK_USDHC1 103
	#define IMX8MN_CLK_USDHC2 104
	#define IMX8MN_CLK_I2C1 105
	#define IMX8MN_CLK_I2C2 106
	#define IMX8MN_CLK_I2C3 107
	#define IMX8MN_CLK_I2C4 108
	#define IMX8MN_CLK_UART1 109
	#define IMX8MN_CLK_UART2 110
	#define IMX8MN_CLK_UART3 111
	#define IMX8MN_CLK_UART4 112
	#define IMX8MN_CLK_USB_CORE_REF 113
	#define IMX8MN_CLK_USB_PHY_REF 114
	#define IMX8MN_CLK_ECSPI1 115
	#define IMX8MN_CLK_ECSPI2 116
	#define IMX8MN_CLK_PWM1 117
	#define IMX8MN_CLK_PWM2 118
	#define IMX8MN_CLK_PWM3 119
	#define IMX8MN_CLK_PWM4 120
	#define IMX8MN_CLK_WDOG 121
	#define IMX8MN_CLK_WRCLK 122
	#define IMX8MN_CLK_CLKO1 123
	#define IMX8MN_CLK_CLKO2 124
	#define IMX8MN_CLK_DSI_CORE 125
	#define IMX8MN_CLK_DSI_PHY_REF 126
	#define IMX8MN_CLK_DSI_DBI 127
	#define IMX8MN_CLK_USDHC3 128
	#define IMX8MN_CLK_CAMERA_PIXEL 129
	#define IMX8MN_CLK_CSI1_PHY_REF 130
	#define IMX8MN_CLK_CSI2_PHY_REF 131
	#define IMX8MN_CLK_CSI2_ESC 132
	#define IMX8MN_CLK_ECSPI3 133
	#define IMX8MN_CLK_PDM 134
	#define IMX8MN_CLK_SAI7 135

	#define IMX8MN_CLK_ECSPI1_ROOT 136
	#define IMX8MN_CLK_ECSPI2_ROOT 137
	#define IMX8MN_CLK_ECSPI3_ROOT 138
	#define IMX8MN_CLK_ENET1_ROOT 139
	#define IMX8MN_CLK_GPIO1_ROOT 140
	#define IMX8MN_CLK_GPIO2_ROOT 141
	#define IMX8MN_CLK_GPIO3_ROOT 142
	#define IMX8MN_CLK_GPIO4_ROOT 143
	#define IMX8MN_CLK_GPIO5_ROOT 144
	#define IMX8MN_CLK_I2C1_ROOT 145
	#define IMX8MN_CLK_I2C2_ROOT 146
	#define IMX8MN_CLK_I2C3_ROOT 147
	#define IMX8MN_CLK_I2C4_ROOT 148
	#define IMX8MN_CLK_MU_ROOT 149
	#define IMX8MN_CLK_OCOTP_ROOT 150
	#define IMX8MN_CLK_PWM1_ROOT 151
	#define IMX8MN_CLK_PWM2_ROOT 152
	#define IMX8MN_CLK_PWM3_ROOT 153
	#define IMX8MN_CLK_PWM4_ROOT 154
	#define IMX8MN_CLK_QSPI_ROOT 155
	#define IMX8MN_CLK_NAND_ROOT 156
	#define IMX8MN_CLK_SAI2_ROOT 157
	#define IMX8MN_CLK_SAI2_IPG 158
	#define IMX8MN_CLK_SAI3_ROOT 159
	#define IMX8MN_CLK_SAI3_IPG 160
	#define IMX8MN_CLK_SAI5_ROOT 161
	#define IMX8MN_CLK_SAI5_IPG 162
	#define IMX8MN_CLK_SAI6_ROOT 163
	#define IMX8MN_CLK_SAI6_IPG 164
	#define IMX8MN_CLK_SAI7_ROOT 165
	#define IMX8MN_CLK_SAI7_IPG 166
	#define IMX8MN_CLK_SDMA1_ROOT 167
	#define IMX8MN_CLK_SDMA2_ROOT 168
	#define IMX8MN_CLK_UART1_ROOT 169
	#define IMX8MN_CLK_UART2_ROOT 170
	#define IMX8MN_CLK_UART3_ROOT 171
	#define IMX8MN_CLK_UART4_ROOT 172
	#define IMX8MN_CLK_USB1_CTRL_ROOT 173
	#define IMX8MN_CLK_USDHC1_ROOT 174
	#define IMX8MN_CLK_USDHC2_ROOT 175
	#define IMX8MN_CLK_WDOG1_ROOT 176
	#define IMX8MN_CLK_WDOG2_ROOT 177
	#define IMX8MN_CLK_WDOG3_ROOT 178
	#define IMX8MN_CLK_GPU_BUS_ROOT 179
	#define IMX8MN_CLK_ASRC_ROOT 180
	#define IMX8MN_CLK_GPU3D_ROOT 181
	#define IMX8MN_CLK_PDM_ROOT 182
	#define IMX8MN_CLK_PDM_IPG 183
	#define IMX8MN_CLK_DISP_AXI_ROOT 184
	#define IMX8MN_CLK_DISP_APB_ROOT 185
	#define IMX8MN_CLK_DISP_PIXEL_ROOT 186
	#define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187
	#define IMX8MN_CLK_USDHC3_ROOT 188
	#define IMX8MN_CLK_SDMA3_ROOT 189
	#define IMX8MN_CLK_TMU_ROOT 190
	#define IMX8MN_CLK_ARM 191
	#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192
	#define IMX8MN_CLK_GPU_CORE_ROOT 193
	#define IMX8MN_CLK_GIC 194

	#define IMX8MN_SYS_PLL1_40M_CG 195
	#define IMX8MN_SYS_PLL1_80M_CG 196
	#define IMX8MN_SYS_PLL1_100M_CG 197
	#define IMX8MN_SYS_PLL1_133M_CG 198
	#define IMX8MN_SYS_PLL1_160M_CG 199
	#define IMX8MN_SYS_PLL1_200M_CG 200
	#define IMX8MN_SYS_PLL1_266M_CG 201
	#define IMX8MN_SYS_PLL1_400M_CG 202
	#define IMX8MN_SYS_PLL2_50M_CG 203
	#define IMX8MN_SYS_PLL2_100M_CG 204
	#define IMX8MN_SYS_PLL2_125M_CG 205
	#define IMX8MN_SYS_PLL2_166M_CG 206
	#define IMX8MN_SYS_PLL2_200M_CG 207
	#define IMX8MN_SYS_PLL2_250M_CG 208
	#define IMX8MN_SYS_PLL2_333M_CG 209
	#define IMX8MN_SYS_PLL2_500M_CG 210

	-#define IMX8MN_CLK_END 211
	+#define IMX8MN_CLK_SNVS_ROOT 211
	+#define IMX8MN_CLK_GPU_CORE 212
	+#define IMX8MN_CLK_GPU_SHADER 213
	+
	+#define IMX8MN_CLK_A53_CORE 214
	+
	+#define IMX8MN_CLK_END 215

	#endif
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx8mp-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx8mp-clock.h
	index 2fab63186bca..47ab082238b4 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/imx8mp-clock.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/imx8mp-clock.h
	@@ -1,300 +1,301 @@
	/* SPDX-License-Identifier: GPL-2.0 */
	/*
	* Copyright 2019 NXP
	*/

	#ifndef __DT_BINDINGS_CLOCK_IMX8MP_H
	#define __DT_BINDINGS_CLOCK_IMX8MP_H

	#define IMX8MP_CLK_DUMMY 0
	#define IMX8MP_CLK_32K 1
	#define IMX8MP_CLK_24M 2
	#define IMX8MP_OSC_HDMI_CLK 3
	#define IMX8MP_CLK_EXT1 4
	#define IMX8MP_CLK_EXT2 5
	#define IMX8MP_CLK_EXT3 6
	#define IMX8MP_CLK_EXT4 7
	#define IMX8MP_AUDIO_PLL1_REF_SEL 8
	#define IMX8MP_AUDIO_PLL2_REF_SEL 9
	#define IMX8MP_VIDEO_PLL1_REF_SEL 10
	#define IMX8MP_DRAM_PLL_REF_SEL 11
	#define IMX8MP_GPU_PLL_REF_SEL 12
	#define IMX8MP_VPU_PLL_REF_SEL 13
	#define IMX8MP_ARM_PLL_REF_SEL 14
	#define IMX8MP_SYS_PLL1_REF_SEL 15
	#define IMX8MP_SYS_PLL2_REF_SEL 16
	#define IMX8MP_SYS_PLL3_REF_SEL 17
	#define IMX8MP_AUDIO_PLL1 18
	#define IMX8MP_AUDIO_PLL2 19
	#define IMX8MP_VIDEO_PLL1 20
	#define IMX8MP_DRAM_PLL 21
	#define IMX8MP_GPU_PLL 22
	#define IMX8MP_VPU_PLL 23
	#define IMX8MP_ARM_PLL 24
	#define IMX8MP_SYS_PLL1 25
	#define IMX8MP_SYS_PLL2 26
	#define IMX8MP_SYS_PLL3 27
	#define IMX8MP_AUDIO_PLL1_BYPASS 28
	#define IMX8MP_AUDIO_PLL2_BYPASS 29
	#define IMX8MP_VIDEO_PLL1_BYPASS 30
	#define IMX8MP_DRAM_PLL_BYPASS 31
	#define IMX8MP_GPU_PLL_BYPASS 32
	#define IMX8MP_VPU_PLL_BYPASS 33
	#define IMX8MP_ARM_PLL_BYPASS 34
	#define IMX8MP_SYS_PLL1_BYPASS 35
	#define IMX8MP_SYS_PLL2_BYPASS 36
	#define IMX8MP_SYS_PLL3_BYPASS 37
	#define IMX8MP_AUDIO_PLL1_OUT 38
	#define IMX8MP_AUDIO_PLL2_OUT 39
	#define IMX8MP_VIDEO_PLL1_OUT 40
	#define IMX8MP_DRAM_PLL_OUT 41
	#define IMX8MP_GPU_PLL_OUT 42
	#define IMX8MP_VPU_PLL_OUT 43
	#define IMX8MP_ARM_PLL_OUT 44
	#define IMX8MP_SYS_PLL1_OUT 45
	#define IMX8MP_SYS_PLL2_OUT 46
	#define IMX8MP_SYS_PLL3_OUT 47
	#define IMX8MP_SYS_PLL1_40M 48
	#define IMX8MP_SYS_PLL1_80M 49
	#define IMX8MP_SYS_PLL1_100M 50
	#define IMX8MP_SYS_PLL1_133M 51
	#define IMX8MP_SYS_PLL1_160M 52
	#define IMX8MP_SYS_PLL1_200M 53
	#define IMX8MP_SYS_PLL1_266M 54
	#define IMX8MP_SYS_PLL1_400M 55
	#define IMX8MP_SYS_PLL1_800M 56
	#define IMX8MP_SYS_PLL2_50M 57
	#define IMX8MP_SYS_PLL2_100M 58
	#define IMX8MP_SYS_PLL2_125M 59
	#define IMX8MP_SYS_PLL2_166M 60
	#define IMX8MP_SYS_PLL2_200M 61
	#define IMX8MP_SYS_PLL2_250M 62
	#define IMX8MP_SYS_PLL2_333M 63
	#define IMX8MP_SYS_PLL2_500M 64
	#define IMX8MP_SYS_PLL2_1000M 65
	#define IMX8MP_CLK_A53_SRC 66
	#define IMX8MP_CLK_M7_SRC 67
	#define IMX8MP_CLK_ML_SRC 68
	#define IMX8MP_CLK_GPU3D_CORE_SRC 69
	#define IMX8MP_CLK_GPU3D_SHADER_SRC 70
	#define IMX8MP_CLK_GPU2D_SRC 71
	#define IMX8MP_CLK_AUDIO_AXI_SRC 72
	#define IMX8MP_CLK_HSIO_AXI_SRC 73
	#define IMX8MP_CLK_MEDIA_ISP_SRC 74
	#define IMX8MP_CLK_A53_CG 75
	#define IMX8MP_CLK_M4_CG 76
	#define IMX8MP_CLK_ML_CG 77
	#define IMX8MP_CLK_GPU3D_CORE_CG 78
	#define IMX8MP_CLK_GPU3D_SHADER_CG 79
	#define IMX8MP_CLK_GPU2D_CG 80
	#define IMX8MP_CLK_AUDIO_AXI_CG 81
	#define IMX8MP_CLK_HSIO_AXI_CG 82
	#define IMX8MP_CLK_MEDIA_ISP_CG 83
	#define IMX8MP_CLK_A53_DIV 84
	#define IMX8MP_CLK_M7_DIV 85
	#define IMX8MP_CLK_ML_DIV 86
	#define IMX8MP_CLK_GPU3D_CORE_DIV 87
	#define IMX8MP_CLK_GPU3D_SHADER_DIV 88
	#define IMX8MP_CLK_GPU2D_DIV 89
	#define IMX8MP_CLK_AUDIO_AXI_DIV 90
	#define IMX8MP_CLK_HSIO_AXI_DIV 91
	#define IMX8MP_CLK_MEDIA_ISP_DIV 92
	#define IMX8MP_CLK_MAIN_AXI 93
	#define IMX8MP_CLK_ENET_AXI 94
	#define IMX8MP_CLK_NAND_USDHC_BUS 95
	#define IMX8MP_CLK_VPU_BUS 96
	#define IMX8MP_CLK_MEDIA_AXI 97
	#define IMX8MP_CLK_MEDIA_APB 98
	#define IMX8MP_CLK_HDMI_APB 99
	#define IMX8MP_CLK_HDMI_AXI 100
	#define IMX8MP_CLK_GPU_AXI 101
	#define IMX8MP_CLK_GPU_AHB 102
	#define IMX8MP_CLK_NOC 103
	#define IMX8MP_CLK_NOC_IO 104
	#define IMX8MP_CLK_ML_AXI 105
	#define IMX8MP_CLK_ML_AHB 106
	#define IMX8MP_CLK_AHB 107
	#define IMX8MP_CLK_AUDIO_AHB 108
	#define IMX8MP_CLK_MIPI_DSI_ESC_RX 109
	#define IMX8MP_CLK_IPG_ROOT 110
	#define IMX8MP_CLK_IPG_AUDIO_ROOT 111
	#define IMX8MP_CLK_DRAM_ALT 112
	#define IMX8MP_CLK_DRAM_APB 113
	#define IMX8MP_CLK_VPU_G1 114
	#define IMX8MP_CLK_VPU_G2 115
	#define IMX8MP_CLK_CAN1 116
	#define IMX8MP_CLK_CAN2 117
	#define IMX8MP_CLK_MEMREPAIR 118
	#define IMX8MP_CLK_PCIE_PHY 119
	#define IMX8MP_CLK_PCIE_AUX 120
	#define IMX8MP_CLK_I2C5 121
	#define IMX8MP_CLK_I2C6 122
	#define IMX8MP_CLK_SAI1 123
	#define IMX8MP_CLK_SAI2 124
	#define IMX8MP_CLK_SAI3 125
	#define IMX8MP_CLK_SAI4 126
	#define IMX8MP_CLK_SAI5 127
	#define IMX8MP_CLK_SAI6 128
	#define IMX8MP_CLK_ENET_QOS 129
	#define IMX8MP_CLK_ENET_QOS_TIMER 130
	#define IMX8MP_CLK_ENET_REF 131
	#define IMX8MP_CLK_ENET_TIMER 132
	#define IMX8MP_CLK_ENET_PHY_REF 133
	#define IMX8MP_CLK_NAND 134
	#define IMX8MP_CLK_QSPI 135
	#define IMX8MP_CLK_USDHC1 136
	#define IMX8MP_CLK_USDHC2 137
	#define IMX8MP_CLK_I2C1 138
	#define IMX8MP_CLK_I2C2 139
	#define IMX8MP_CLK_I2C3 140
	#define IMX8MP_CLK_I2C4 141
	#define IMX8MP_CLK_UART1 142
	#define IMX8MP_CLK_UART2 143
	#define IMX8MP_CLK_UART3 144
	#define IMX8MP_CLK_UART4 145
	#define IMX8MP_CLK_USB_CORE_REF 146
	#define IMX8MP_CLK_USB_PHY_REF 147
	#define IMX8MP_CLK_GIC 148
	#define IMX8MP_CLK_ECSPI1 149
	#define IMX8MP_CLK_ECSPI2 150
	#define IMX8MP_CLK_PWM1 151
	#define IMX8MP_CLK_PWM2 152
	#define IMX8MP_CLK_PWM3 153
	#define IMX8MP_CLK_PWM4 154
	#define IMX8MP_CLK_GPT1 155
	#define IMX8MP_CLK_GPT2 156
	#define IMX8MP_CLK_GPT3 157
	#define IMX8MP_CLK_GPT4 158
	#define IMX8MP_CLK_GPT5 159
	#define IMX8MP_CLK_GPT6 160
	#define IMX8MP_CLK_TRACE 161
	#define IMX8MP_CLK_WDOG 162
	#define IMX8MP_CLK_WRCLK 163
	#define IMX8MP_CLK_IPP_DO_CLKO1 164
	#define IMX8MP_CLK_IPP_DO_CLKO2 165
	#define IMX8MP_CLK_HDMI_FDCC_TST 166
	-#define IMX8MP_CLK_HDMI_27M 167
	+#define IMX8MP_CLK_HDMI_24M 167
	#define IMX8MP_CLK_HDMI_REF_266M 168
	#define IMX8MP_CLK_USDHC3 169
	#define IMX8MP_CLK_MEDIA_CAM1_PIX 170
	#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171
	#define IMX8MP_CLK_MEDIA_DISP1_PIX 172
	#define IMX8MP_CLK_MEDIA_CAM2_PIX 173
	#define IMX8MP_CLK_MEDIA_MIPI_PHY2_REF 174
	#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175
	#define IMX8MP_CLK_PCIE2_CTRL 176
	#define IMX8MP_CLK_PCIE2_PHY 177
	#define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178
	#define IMX8MP_CLK_ECSPI3 179
	#define IMX8MP_CLK_PDM 180
	#define IMX8MP_CLK_VPU_VC8000E 181
	#define IMX8MP_CLK_SAI7 182
	#define IMX8MP_CLK_GPC_ROOT 183
	#define IMX8MP_CLK_ANAMIX_ROOT 184
	#define IMX8MP_CLK_CPU_ROOT 185
	#define IMX8MP_CLK_CSU_ROOT 186
	#define IMX8MP_CLK_DEBUG_ROOT 187
	#define IMX8MP_CLK_DRAM1_ROOT 188
	#define IMX8MP_CLK_ECSPI1_ROOT 189
	#define IMX8MP_CLK_ECSPI2_ROOT 190
	#define IMX8MP_CLK_ECSPI3_ROOT 191
	#define IMX8MP_CLK_ENET1_ROOT 192
	#define IMX8MP_CLK_GPIO1_ROOT 193
	#define IMX8MP_CLK_GPIO2_ROOT 194
	#define IMX8MP_CLK_GPIO3_ROOT 195
	#define IMX8MP_CLK_GPIO4_ROOT 196
	#define IMX8MP_CLK_GPIO5_ROOT 197
	#define IMX8MP_CLK_GPT1_ROOT 198
	#define IMX8MP_CLK_GPT2_ROOT 199
	#define IMX8MP_CLK_GPT3_ROOT 200
	#define IMX8MP_CLK_GPT4_ROOT 201
	#define IMX8MP_CLK_GPT5_ROOT 202
	#define IMX8MP_CLK_GPT6_ROOT 203
	#define IMX8MP_CLK_HS_ROOT 204
	#define IMX8MP_CLK_I2C1_ROOT 205
	#define IMX8MP_CLK_I2C2_ROOT 206
	#define IMX8MP_CLK_I2C3_ROOT 207
	#define IMX8MP_CLK_I2C4_ROOT 208
	#define IMX8MP_CLK_IOMUX_ROOT 209
	#define IMX8MP_CLK_IPMUX1_ROOT 210
	#define IMX8MP_CLK_IPMUX2_ROOT 211
	#define IMX8MP_CLK_IPMUX3_ROOT 212
	#define IMX8MP_CLK_MU_ROOT 213
	#define IMX8MP_CLK_OCOTP_ROOT 214
	#define IMX8MP_CLK_OCRAM_ROOT 215
	#define IMX8MP_CLK_OCRAM_S_ROOT 216
	#define IMX8MP_CLK_PCIE_ROOT 217
	#define IMX8MP_CLK_PERFMON1_ROOT 218
	#define IMX8MP_CLK_PERFMON2_ROOT 219
	#define IMX8MP_CLK_PWM1_ROOT 220
	#define IMX8MP_CLK_PWM2_ROOT 221
	#define IMX8MP_CLK_PWM3_ROOT 222
	#define IMX8MP_CLK_PWM4_ROOT 223
	#define IMX8MP_CLK_QOS_ROOT 224
	#define IMX8MP_CLK_QOS_ENET_ROOT 225
	#define IMX8MP_CLK_QSPI_ROOT 226
	#define IMX8MP_CLK_NAND_ROOT 227
	#define IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK 228
	#define IMX8MP_CLK_RDC_ROOT 229
	#define IMX8MP_CLK_ROM_ROOT 230
	#define IMX8MP_CLK_I2C5_ROOT 231
	#define IMX8MP_CLK_I2C6_ROOT 232
	#define IMX8MP_CLK_CAN1_ROOT 233
	#define IMX8MP_CLK_CAN2_ROOT 234
	#define IMX8MP_CLK_SCTR_ROOT 235
	#define IMX8MP_CLK_SDMA1_ROOT 236
	#define IMX8MP_CLK_ENET_QOS_ROOT 237
	#define IMX8MP_CLK_SEC_DEBUG_ROOT 238
	#define IMX8MP_CLK_SEMA1_ROOT 239
	#define IMX8MP_CLK_SEMA2_ROOT 240
	#define IMX8MP_CLK_IRQ_STEER_ROOT 241
	#define IMX8MP_CLK_SIM_ENET_ROOT 242
	#define IMX8MP_CLK_SIM_M_ROOT 243
	#define IMX8MP_CLK_SIM_MAIN_ROOT 244
	#define IMX8MP_CLK_SIM_S_ROOT 245
	#define IMX8MP_CLK_SIM_WAKEUP_ROOT 246
	#define IMX8MP_CLK_GPU2D_ROOT 247
	#define IMX8MP_CLK_GPU3D_ROOT 248
	#define IMX8MP_CLK_SNVS_ROOT 249
	#define IMX8MP_CLK_TRACE_ROOT 250
	#define IMX8MP_CLK_UART1_ROOT 251
	#define IMX8MP_CLK_UART2_ROOT 252
	#define IMX8MP_CLK_UART3_ROOT 253
	#define IMX8MP_CLK_UART4_ROOT 254
	#define IMX8MP_CLK_USB_ROOT 255
	#define IMX8MP_CLK_USB_PHY_ROOT 256
	#define IMX8MP_CLK_USDHC1_ROOT 257
	#define IMX8MP_CLK_USDHC2_ROOT 258
	#define IMX8MP_CLK_WDOG1_ROOT 259
	#define IMX8MP_CLK_WDOG2_ROOT 260
	#define IMX8MP_CLK_WDOG3_ROOT 261
	#define IMX8MP_CLK_VPU_G1_ROOT 262
	#define IMX8MP_CLK_GPU_ROOT 263
	#define IMX8MP_CLK_NOC_WRAPPER_ROOT 264
	#define IMX8MP_CLK_VPU_VC8KE_ROOT 265
	#define IMX8MP_CLK_VPU_G2_ROOT 266
	#define IMX8MP_CLK_NPU_ROOT 267
	#define IMX8MP_CLK_HSIO_ROOT 268
	#define IMX8MP_CLK_MEDIA_APB_ROOT 269
	#define IMX8MP_CLK_MEDIA_AXI_ROOT 270
	#define IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT 271
	#define IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT 272
	#define IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT 273
	#define IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT 274
	#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT 275
	#define IMX8MP_CLK_MEDIA_ISP_ROOT 276
	#define IMX8MP_CLK_USDHC3_ROOT 277
	#define IMX8MP_CLK_HDMI_ROOT 278
	#define IMX8MP_CLK_XTAL_ROOT 279
	#define IMX8MP_CLK_PLL_ROOT 280
	#define IMX8MP_CLK_TSENSOR_ROOT 281
	#define IMX8MP_CLK_VPU_ROOT 282
	#define IMX8MP_CLK_MRPR_ROOT 283
	#define IMX8MP_CLK_AUDIO_ROOT 284
	#define IMX8MP_CLK_DRAM_ALT_ROOT 285
	#define IMX8MP_CLK_DRAM_CORE 286
	#define IMX8MP_CLK_ARM 287
	+#define IMX8MP_CLK_A53_CORE 288

	-#define IMX8MP_CLK_END 288
	+#define IMX8MP_CLK_END 289

	#endif
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx8mq-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx8mq-clock.h
	index 3bab9b21c8d7..9b8045d75b8b 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/imx8mq-clock.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/imx8mq-clock.h
	@@ -1,429 +1,436 @@
	/* SPDX-License-Identifier: GPL-2.0 */
	/*
	* Copyright 2016 Freescale Semiconductor, Inc.
	* Copyright 2017 NXP
	*/

	#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
	#define __DT_BINDINGS_CLOCK_IMX8MQ_H

	#define IMX8MQ_CLK_DUMMY 0
	#define IMX8MQ_CLK_32K 1
	#define IMX8MQ_CLK_25M 2
	#define IMX8MQ_CLK_27M 3
	#define IMX8MQ_CLK_EXT1 4
	#define IMX8MQ_CLK_EXT2 5
	#define IMX8MQ_CLK_EXT3 6
	#define IMX8MQ_CLK_EXT4 7

	/* ANAMIX PLL clocks */
	/* FRAC PLLs */
	/* ARM PLL */
	#define IMX8MQ_ARM_PLL_REF_SEL 8
	#define IMX8MQ_ARM_PLL_REF_DIV 9
	#define IMX8MQ_ARM_PLL 10
	#define IMX8MQ_ARM_PLL_BYPASS 11
	#define IMX8MQ_ARM_PLL_OUT 12

	/* GPU PLL */
	#define IMX8MQ_GPU_PLL_REF_SEL 13
	#define IMX8MQ_GPU_PLL_REF_DIV 14
	#define IMX8MQ_GPU_PLL 15
	#define IMX8MQ_GPU_PLL_BYPASS 16
	#define IMX8MQ_GPU_PLL_OUT 17

	/* VPU PLL */
	#define IMX8MQ_VPU_PLL_REF_SEL 18
	#define IMX8MQ_VPU_PLL_REF_DIV 19
	#define IMX8MQ_VPU_PLL 20
	#define IMX8MQ_VPU_PLL_BYPASS 21
	#define IMX8MQ_VPU_PLL_OUT 22

	/* AUDIO PLL1 */
	#define IMX8MQ_AUDIO_PLL1_REF_SEL 23
	#define IMX8MQ_AUDIO_PLL1_REF_DIV 24
	#define IMX8MQ_AUDIO_PLL1 25
	#define IMX8MQ_AUDIO_PLL1_BYPASS 26
	#define IMX8MQ_AUDIO_PLL1_OUT 27

	/* AUDIO PLL2 */
	#define IMX8MQ_AUDIO_PLL2_REF_SEL 28
	#define IMX8MQ_AUDIO_PLL2_REF_DIV 29
	#define IMX8MQ_AUDIO_PLL2 30
	#define IMX8MQ_AUDIO_PLL2_BYPASS 31
	#define IMX8MQ_AUDIO_PLL2_OUT 32

	/* VIDEO PLL1 */
	#define IMX8MQ_VIDEO_PLL1_REF_SEL 33
	#define IMX8MQ_VIDEO_PLL1_REF_DIV 34
	#define IMX8MQ_VIDEO_PLL1 35
	#define IMX8MQ_VIDEO_PLL1_BYPASS 36
	#define IMX8MQ_VIDEO_PLL1_OUT 37

	/* SYS1 PLL */
	#define IMX8MQ_SYS1_PLL1_REF_SEL 38
	#define IMX8MQ_SYS1_PLL1_REF_DIV 39
	#define IMX8MQ_SYS1_PLL1 40
	#define IMX8MQ_SYS1_PLL1_OUT 41
	#define IMX8MQ_SYS1_PLL1_OUT_DIV 42
	#define IMX8MQ_SYS1_PLL2 43
	#define IMX8MQ_SYS1_PLL2_DIV 44
	#define IMX8MQ_SYS1_PLL2_OUT 45

	/* SYS2 PLL */
	#define IMX8MQ_SYS2_PLL1_REF_SEL 46
	#define IMX8MQ_SYS2_PLL1_REF_DIV 47
	#define IMX8MQ_SYS2_PLL1 48
	#define IMX8MQ_SYS2_PLL1_OUT 49
	#define IMX8MQ_SYS2_PLL1_OUT_DIV 50
	#define IMX8MQ_SYS2_PLL2 51
	#define IMX8MQ_SYS2_PLL2_DIV 52
	#define IMX8MQ_SYS2_PLL2_OUT 53

	/* SYS3 PLL */
	#define IMX8MQ_SYS3_PLL1_REF_SEL 54
	#define IMX8MQ_SYS3_PLL1_REF_DIV 55
	#define IMX8MQ_SYS3_PLL1 56
	#define IMX8MQ_SYS3_PLL1_OUT 57
	#define IMX8MQ_SYS3_PLL1_OUT_DIV 58
	#define IMX8MQ_SYS3_PLL2 59
	#define IMX8MQ_SYS3_PLL2_DIV 60
	#define IMX8MQ_SYS3_PLL2_OUT 61

	/* DRAM PLL */
	#define IMX8MQ_DRAM_PLL1_REF_SEL 62
	#define IMX8MQ_DRAM_PLL1_REF_DIV 63
	#define IMX8MQ_DRAM_PLL1 64
	#define IMX8MQ_DRAM_PLL1_OUT 65
	#define IMX8MQ_DRAM_PLL1_OUT_DIV 66
	#define IMX8MQ_DRAM_PLL2 67
	#define IMX8MQ_DRAM_PLL2_DIV 68
	#define IMX8MQ_DRAM_PLL2_OUT 69

	/* SYS PLL DIV */
	#define IMX8MQ_SYS1_PLL_40M 70
	#define IMX8MQ_SYS1_PLL_80M 71
	#define IMX8MQ_SYS1_PLL_100M 72
	#define IMX8MQ_SYS1_PLL_133M 73
	#define IMX8MQ_SYS1_PLL_160M 74
	#define IMX8MQ_SYS1_PLL_200M 75
	#define IMX8MQ_SYS1_PLL_266M 76
	#define IMX8MQ_SYS1_PLL_400M 77
	#define IMX8MQ_SYS1_PLL_800M 78

	#define IMX8MQ_SYS2_PLL_50M 79
	#define IMX8MQ_SYS2_PLL_100M 80
	#define IMX8MQ_SYS2_PLL_125M 81
	#define IMX8MQ_SYS2_PLL_166M 82
	#define IMX8MQ_SYS2_PLL_200M 83
	#define IMX8MQ_SYS2_PLL_250M 84
	#define IMX8MQ_SYS2_PLL_333M 85
	#define IMX8MQ_SYS2_PLL_500M 86
	#define IMX8MQ_SYS2_PLL_1000M 87

	/* CCM ROOT clocks */
	/* A53 */
	#define IMX8MQ_CLK_A53_SRC 88
	#define IMX8MQ_CLK_A53_CG 89
	#define IMX8MQ_CLK_A53_DIV 90
	/* M4 */
	#define IMX8MQ_CLK_M4_SRC 91
	#define IMX8MQ_CLK_M4_CG 92
	#define IMX8MQ_CLK_M4_DIV 93
	/* VPU */
	#define IMX8MQ_CLK_VPU_SRC 94
	#define IMX8MQ_CLK_VPU_CG 95
	#define IMX8MQ_CLK_VPU_DIV 96
	/* GPU CORE */
	#define IMX8MQ_CLK_GPU_CORE_SRC 97
	#define IMX8MQ_CLK_GPU_CORE_CG 98
	#define IMX8MQ_CLK_GPU_CORE_DIV 99
	/* GPU SHADER */
	#define IMX8MQ_CLK_GPU_SHADER_SRC 100
	#define IMX8MQ_CLK_GPU_SHADER_CG 101
	#define IMX8MQ_CLK_GPU_SHADER_DIV 102

	/* BUS TYPE */
	/* MAIN AXI */
	#define IMX8MQ_CLK_MAIN_AXI 103
	/* ENET AXI */
	#define IMX8MQ_CLK_ENET_AXI 104
	/* NAND_USDHC_BUS */
	#define IMX8MQ_CLK_NAND_USDHC_BUS 105
	/* VPU BUS */
	#define IMX8MQ_CLK_VPU_BUS 106
	/* DISP_AXI */
	#define IMX8MQ_CLK_DISP_AXI 107
	/* DISP APB */
	#define IMX8MQ_CLK_DISP_APB 108
	/* DISP RTRM */
	#define IMX8MQ_CLK_DISP_RTRM 109
	/* USB_BUS */
	#define IMX8MQ_CLK_USB_BUS 110
	/* GPU_AXI */
	#define IMX8MQ_CLK_GPU_AXI 111
	/* GPU_AHB */
	#define IMX8MQ_CLK_GPU_AHB 112
	/* NOC */
	#define IMX8MQ_CLK_NOC 113
	/* NOC_APB */
	#define IMX8MQ_CLK_NOC_APB 115

	/* AHB */
	#define IMX8MQ_CLK_AHB 116
	/* AUDIO AHB */
	#define IMX8MQ_CLK_AUDIO_AHB 117

	/* DRAM_ALT */
	#define IMX8MQ_CLK_DRAM_ALT 118
	/* DRAM APB */
	#define IMX8MQ_CLK_DRAM_APB 119
	/* VPU_G1 */
	#define IMX8MQ_CLK_VPU_G1 120
	/* VPU_G2 */
	#define IMX8MQ_CLK_VPU_G2 121
	/* DISP_DTRC */
	#define IMX8MQ_CLK_DISP_DTRC 122
	/* DISP_DC8000 */
	#define IMX8MQ_CLK_DISP_DC8000 123
	/* PCIE_CTRL */
	#define IMX8MQ_CLK_PCIE1_CTRL 124
	/* PCIE_PHY */
	#define IMX8MQ_CLK_PCIE1_PHY 125
	/* PCIE_AUX */
	#define IMX8MQ_CLK_PCIE1_AUX 126
	/* DC_PIXEL */
	#define IMX8MQ_CLK_DC_PIXEL 127
	/* LCDIF_PIXEL */
	#define IMX8MQ_CLK_LCDIF_PIXEL 128
	/* SAI1~6 */
	#define IMX8MQ_CLK_SAI1 129

	#define IMX8MQ_CLK_SAI2 130

	#define IMX8MQ_CLK_SAI3 131

	#define IMX8MQ_CLK_SAI4 132

	#define IMX8MQ_CLK_SAI5 133

	#define IMX8MQ_CLK_SAI6 134
	/* SPDIF1 */
	#define IMX8MQ_CLK_SPDIF1 135
	/* SPDIF2 */
	#define IMX8MQ_CLK_SPDIF2 136
	/* ENET_REF */
	#define IMX8MQ_CLK_ENET_REF 137
	/* ENET_TIMER */
	#define IMX8MQ_CLK_ENET_TIMER 138
	/* ENET_PHY */
	#define IMX8MQ_CLK_ENET_PHY_REF 139
	/* NAND */
	#define IMX8MQ_CLK_NAND 140
	/* QSPI */
	#define IMX8MQ_CLK_QSPI 141
	/* USDHC1 */
	#define IMX8MQ_CLK_USDHC1 142
	/* USDHC2 */
	#define IMX8MQ_CLK_USDHC2 143
	/* I2C1 */
	#define IMX8MQ_CLK_I2C1 144
	/* I2C2 */
	#define IMX8MQ_CLK_I2C2 145
	/* I2C3 */
	#define IMX8MQ_CLK_I2C3 146
	/* I2C4 */
	#define IMX8MQ_CLK_I2C4 147
	/* UART1 */
	#define IMX8MQ_CLK_UART1 148
	/* UART2 */
	#define IMX8MQ_CLK_UART2 149
	/* UART3 */
	#define IMX8MQ_CLK_UART3 150
	/* UART4 */
	#define IMX8MQ_CLK_UART4 151
	/* USB_CORE_REF */
	#define IMX8MQ_CLK_USB_CORE_REF 152
	/* USB_PHY_REF */
	#define IMX8MQ_CLK_USB_PHY_REF 153
	/* ECSPI1 */
	#define IMX8MQ_CLK_ECSPI1 154
	/* ECSPI2 */
	#define IMX8MQ_CLK_ECSPI2 155
	/* PWM1 */
	#define IMX8MQ_CLK_PWM1 156
	/* PWM2 */
	#define IMX8MQ_CLK_PWM2 157
	/* PWM3 */
	#define IMX8MQ_CLK_PWM3 158
	/* PWM4 */
	#define IMX8MQ_CLK_PWM4 159
	/* GPT1 */
	#define IMX8MQ_CLK_GPT1 160
	/* WDOG */
	#define IMX8MQ_CLK_WDOG 161
	/* WRCLK */
	#define IMX8MQ_CLK_WRCLK 162
	/* DSI_CORE */
	#define IMX8MQ_CLK_DSI_CORE 163
	/* DSI_PHY */
	#define IMX8MQ_CLK_DSI_PHY_REF 164
	/* DSI_DBI */
	#define IMX8MQ_CLK_DSI_DBI 165
	/DSI_ESC /
	#define IMX8MQ_CLK_DSI_ESC 166
	/* CSI1_CORE */
	#define IMX8MQ_CLK_CSI1_CORE 167
	/* CSI1_PHY */
	#define IMX8MQ_CLK_CSI1_PHY_REF 168
	/* CSI_ESC */
	#define IMX8MQ_CLK_CSI1_ESC 169
	/* CSI2_CORE */
	#define IMX8MQ_CLK_CSI2_CORE 170
	/* CSI2_PHY */
	#define IMX8MQ_CLK_CSI2_PHY_REF 171
	/* CSI2_ESC */
	#define IMX8MQ_CLK_CSI2_ESC 172
	/* PCIE2_CTRL */
	#define IMX8MQ_CLK_PCIE2_CTRL 173
	/* PCIE2_PHY */
	#define IMX8MQ_CLK_PCIE2_PHY 174
	/* PCIE2_AUX */
	#define IMX8MQ_CLK_PCIE2_AUX 175
	/* ECSPI3 */
	#define IMX8MQ_CLK_ECSPI3 176

	/* CCGR clocks */
	#define IMX8MQ_CLK_A53_ROOT 177
	#define IMX8MQ_CLK_DRAM_ROOT 178
	#define IMX8MQ_CLK_ECSPI1_ROOT 179
	#define IMX8MQ_CLK_ECSPI2_ROOT 180
	#define IMX8MQ_CLK_ECSPI3_ROOT 181
	#define IMX8MQ_CLK_ENET1_ROOT 182
	#define IMX8MQ_CLK_GPT1_ROOT 183
	#define IMX8MQ_CLK_I2C1_ROOT 184
	#define IMX8MQ_CLK_I2C2_ROOT 185
	#define IMX8MQ_CLK_I2C3_ROOT 186
	#define IMX8MQ_CLK_I2C4_ROOT 187
	#define IMX8MQ_CLK_M4_ROOT 188
	#define IMX8MQ_CLK_PCIE1_ROOT 189
	#define IMX8MQ_CLK_PCIE2_ROOT 190
	#define IMX8MQ_CLK_PWM1_ROOT 191
	#define IMX8MQ_CLK_PWM2_ROOT 192
	#define IMX8MQ_CLK_PWM3_ROOT 193
	#define IMX8MQ_CLK_PWM4_ROOT 194
	#define IMX8MQ_CLK_QSPI_ROOT 195
	#define IMX8MQ_CLK_SAI1_ROOT 196
	#define IMX8MQ_CLK_SAI2_ROOT 197
	#define IMX8MQ_CLK_SAI3_ROOT 198
	#define IMX8MQ_CLK_SAI4_ROOT 199
	#define IMX8MQ_CLK_SAI5_ROOT 200
	#define IMX8MQ_CLK_SAI6_ROOT 201
	#define IMX8MQ_CLK_UART1_ROOT 202
	#define IMX8MQ_CLK_UART2_ROOT 203
	#define IMX8MQ_CLK_UART3_ROOT 204
	#define IMX8MQ_CLK_UART4_ROOT 205
	#define IMX8MQ_CLK_USB1_CTRL_ROOT 206
	#define IMX8MQ_CLK_USB2_CTRL_ROOT 207
	#define IMX8MQ_CLK_USB1_PHY_ROOT 208
	#define IMX8MQ_CLK_USB2_PHY_ROOT 209
	#define IMX8MQ_CLK_USDHC1_ROOT 210
	#define IMX8MQ_CLK_USDHC2_ROOT 211
	#define IMX8MQ_CLK_WDOG1_ROOT 212
	#define IMX8MQ_CLK_WDOG2_ROOT 213
	#define IMX8MQ_CLK_WDOG3_ROOT 214
	#define IMX8MQ_CLK_GPU_ROOT 215
	#define IMX8MQ_CLK_HEVC_ROOT 216
	#define IMX8MQ_CLK_AVC_ROOT 217
	#define IMX8MQ_CLK_VP9_ROOT 218
	#define IMX8MQ_CLK_HEVC_INTER_ROOT 219
	#define IMX8MQ_CLK_DISP_ROOT 220
	#define IMX8MQ_CLK_HDMI_ROOT 221
	#define IMX8MQ_CLK_HDMI_PHY_ROOT 222
	#define IMX8MQ_CLK_VPU_DEC_ROOT 223
	#define IMX8MQ_CLK_CSI1_ROOT 224
	#define IMX8MQ_CLK_CSI2_ROOT 225
	#define IMX8MQ_CLK_RAWNAND_ROOT 226
	#define IMX8MQ_CLK_SDMA1_ROOT 227
	#define IMX8MQ_CLK_SDMA2_ROOT 228
	#define IMX8MQ_CLK_VPU_G1_ROOT 229
	#define IMX8MQ_CLK_VPU_G2_ROOT 230

	/* SCCG PLL GATE */
	#define IMX8MQ_SYS1_PLL_OUT 231
	#define IMX8MQ_SYS2_PLL_OUT 232
	#define IMX8MQ_SYS3_PLL_OUT 233
	#define IMX8MQ_DRAM_PLL_OUT 234

	#define IMX8MQ_GPT_3M_CLK 235

	#define IMX8MQ_CLK_IPG_ROOT 236
	#define IMX8MQ_CLK_IPG_AUDIO_ROOT 237
	#define IMX8MQ_CLK_SAI1_IPG 238
	#define IMX8MQ_CLK_SAI2_IPG 239
	#define IMX8MQ_CLK_SAI3_IPG 240
	#define IMX8MQ_CLK_SAI4_IPG 241
	#define IMX8MQ_CLK_SAI5_IPG 242
	#define IMX8MQ_CLK_SAI6_IPG 243

	/* DSI AHB/IPG clocks */
	/* rxesc clock */
	#define IMX8MQ_CLK_DSI_AHB 244
	/* txesc clock */
	#define IMX8MQ_CLK_DSI_IPG_DIV 245

	#define IMX8MQ_CLK_TMU_ROOT 246

	/* Display root clocks */
	#define IMX8MQ_CLK_DISP_AXI_ROOT 247
	#define IMX8MQ_CLK_DISP_APB_ROOT 248
	#define IMX8MQ_CLK_DISP_RTRM_ROOT 249

	#define IMX8MQ_CLK_OCOTP_ROOT 250

	#define IMX8MQ_CLK_DRAM_ALT_ROOT 251
	#define IMX8MQ_CLK_DRAM_CORE 252

	#define IMX8MQ_CLK_MU_ROOT 253
	#define IMX8MQ_VIDEO2_PLL_OUT 254

	#define IMX8MQ_CLK_CLKO2 255

	#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 256

	#define IMX8MQ_CLK_CLKO1 257
	#define IMX8MQ_CLK_ARM 258

	#define IMX8MQ_CLK_GPIO1_ROOT 259
	#define IMX8MQ_CLK_GPIO2_ROOT 260
	#define IMX8MQ_CLK_GPIO3_ROOT 261
	#define IMX8MQ_CLK_GPIO4_ROOT 262
	#define IMX8MQ_CLK_GPIO5_ROOT 263

	#define IMX8MQ_CLK_SNVS_ROOT 264
	#define IMX8MQ_CLK_GIC 265

	#define IMX8MQ_VIDEO2_PLL1_REF_SEL 266

	#define IMX8MQ_SYS1_PLL_40M_CG 267
	#define IMX8MQ_SYS1_PLL_80M_CG 268
	#define IMX8MQ_SYS1_PLL_100M_CG 269
	#define IMX8MQ_SYS1_PLL_133M_CG 270
	#define IMX8MQ_SYS1_PLL_160M_CG 271
	#define IMX8MQ_SYS1_PLL_200M_CG 272
	#define IMX8MQ_SYS1_PLL_266M_CG 273
	#define IMX8MQ_SYS1_PLL_400M_CG 274
	#define IMX8MQ_SYS1_PLL_800M_CG 275
	#define IMX8MQ_SYS2_PLL_50M_CG 276
	#define IMX8MQ_SYS2_PLL_100M_CG 277
	#define IMX8MQ_SYS2_PLL_125M_CG 278
	#define IMX8MQ_SYS2_PLL_166M_CG 279
	#define IMX8MQ_SYS2_PLL_200M_CG 280
	#define IMX8MQ_SYS2_PLL_250M_CG 281
	#define IMX8MQ_SYS2_PLL_333M_CG 282
	#define IMX8MQ_SYS2_PLL_500M_CG 283
	#define IMX8MQ_SYS2_PLL_1000M_CG 284

	-#define IMX8MQ_CLK_END 285
	+#define IMX8MQ_CLK_GPU_CORE 285
	+#define IMX8MQ_CLK_GPU_SHADER 286
	+#define IMX8MQ_CLK_M4_CORE 287
	+#define IMX8MQ_CLK_VPU_CORE 288
	+
	+#define IMX8MQ_CLK_A53_CORE 289
	+
	+#define IMX8MQ_CLK_END 290

	#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/k210-clk.h b/sys/gnu/dts/include/dt-bindings/clock/k210-clk.h
	new file mode 100644
	index 000000000000..5a2fd64d1a49
	--- /dev/null
	+++ b/sys/gnu/dts/include/dt-bindings/clock/k210-clk.h
	@@ -0,0 +1,20 @@
	+/* SPDX-License-Identifier: GPL-2.0-or-later */
	+/*
	+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
	+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
	+ */
	+#ifndef K210_CLK_H
	+#define K210_CLK_H
	+
	+/*
	+ * Arbitrary identifiers for clocks.
	+ * The structure is: in0 -> pll0 -> aclk -> cpu
	+ *
	+ * Since we use the hardware defaults for now, set all these to the same clock.
	+ */
	+#define K210_CLK_PLL0 0
	+#define K210_CLK_PLL1 0
	+#define K210_CLK_ACLK 0
	+#define K210_CLK_CPU 0
	+
	+#endif /* K210_CLK_H */
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/marvell,mmp2.h b/sys/gnu/dts/include/dt-bindings/clock/marvell,mmp2.h
	index 4b1a7724f20d..06bb7fe4c62f 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/marvell,mmp2.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/marvell,mmp2.h
	@@ -1,79 +1,92 @@
	/* SPDX-License-Identifier: GPL-2.0 */
	#ifndef __DTS_MARVELL_MMP2_CLOCK_H
	#define __DTS_MARVELL_MMP2_CLOCK_H

	/* fixed clocks and plls */
	#define MMP2_CLK_CLK32 1
	#define MMP2_CLK_VCTCXO 2
	#define MMP2_CLK_PLL1 3
	#define MMP2_CLK_PLL1_2 8
	#define MMP2_CLK_PLL1_4 9
	#define MMP2_CLK_PLL1_8 10
	#define MMP2_CLK_PLL1_16 11
	#define MMP2_CLK_PLL1_3 12
	#define MMP2_CLK_PLL1_6 13
	#define MMP2_CLK_PLL1_12 14
	#define MMP2_CLK_PLL1_20 15
	#define MMP2_CLK_PLL2 16
	#define MMP2_CLK_PLL2_2 17
	#define MMP2_CLK_PLL2_4 18
	#define MMP2_CLK_PLL2_8 19
	#define MMP2_CLK_PLL2_16 20
	#define MMP2_CLK_PLL2_3 21
	#define MMP2_CLK_PLL2_6 22
	#define MMP2_CLK_PLL2_12 23
	#define MMP2_CLK_VCTCXO_2 24
	#define MMP2_CLK_VCTCXO_4 25
	#define MMP2_CLK_UART_PLL 26
	#define MMP2_CLK_USB_PLL 27
	+#define MMP3_CLK_PLL1_P 28
	+#define MMP3_CLK_PLL2_P 29
	+#define MMP3_CLK_PLL3 30

	/* apb periphrals */
	#define MMP2_CLK_TWSI0 60
	#define MMP2_CLK_TWSI1 61
	#define MMP2_CLK_TWSI2 62
	#define MMP2_CLK_TWSI3 63
	#define MMP2_CLK_TWSI4 64
	#define MMP2_CLK_TWSI5 65
	#define MMP2_CLK_GPIO 66
	#define MMP2_CLK_KPC 67
	#define MMP2_CLK_RTC 68
	#define MMP2_CLK_PWM0 69
	#define MMP2_CLK_PWM1 70
	#define MMP2_CLK_PWM2 71
	#define MMP2_CLK_PWM3 72
	#define MMP2_CLK_UART0 73
	#define MMP2_CLK_UART1 74
	#define MMP2_CLK_UART2 75
	#define MMP2_CLK_UART3 76
	#define MMP2_CLK_SSP0 77
	#define MMP2_CLK_SSP1 78
	#define MMP2_CLK_SSP2 79
	#define MMP2_CLK_SSP3 80
	#define MMP2_CLK_TIMER 81
	+#define MMP2_CLK_THERMAL0 82
	+#define MMP3_CLK_THERMAL1 83
	+#define MMP3_CLK_THERMAL2 84
	+#define MMP3_CLK_THERMAL3 85

	/* axi periphrals */
	#define MMP2_CLK_SDH0 101
	#define MMP2_CLK_SDH1 102
	#define MMP2_CLK_SDH2 103
	#define MMP2_CLK_SDH3 104
	#define MMP2_CLK_USB 105
	#define MMP2_CLK_DISP0 106
	#define MMP2_CLK_DISP0_MUX 107
	#define MMP2_CLK_DISP0_SPHY 108
	#define MMP2_CLK_DISP1 109
	#define MMP2_CLK_DISP1_MUX 110
	#define MMP2_CLK_CCIC_ARBITER 111
	#define MMP2_CLK_CCIC0 112
	#define MMP2_CLK_CCIC0_MIX 113
	#define MMP2_CLK_CCIC0_PHY 114
	#define MMP2_CLK_CCIC0_SPHY 115
	#define MMP2_CLK_CCIC1 116
	#define MMP2_CLK_CCIC1_MIX 117
	#define MMP2_CLK_CCIC1_PHY 118
	#define MMP2_CLK_CCIC1_SPHY 119
	#define MMP2_CLK_DISP0_LCDC 120
	#define MMP2_CLK_USBHSIC0 121
	#define MMP2_CLK_USBHSIC1 122
	+#define MMP2_CLK_GPU_BUS 123
	+#define MMP3_CLK_GPU_BUS MMP2_CLK_GPU_BUS
	+#define MMP2_CLK_GPU_3D 124
	+#define MMP3_CLK_GPU_3D MMP2_CLK_GPU_3D
	+#define MMP3_CLK_GPU_2D 125
	+#define MMP3_CLK_SDH4 126

	#define MMP2_NR_CLKS 200
	#endif
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sc7180.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sc7180.h
	index e8029b2e92d7..1258fd05db68 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sc7180.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sc7180.h
	@@ -1,155 +1,160 @@
	/* SPDX-License-Identifier: GPL-2.0-only */
	/*
	- * Copyright (c) 2019, The Linux Foundation. All rights reserved.
	+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
	*/

	#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
	#define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H

	/* GCC clocks */
	#define GCC_GPLL0_MAIN_DIV_CDIV 0
	#define GPLL0 1
	#define GPLL0_OUT_EVEN 2
	#define GPLL1 3
	#define GPLL4 4
	#define GPLL6 5
	#define GPLL7 6
	#define GCC_AGGRE_UFS_PHY_AXI_CLK 7
	#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8
	#define GCC_BOOT_ROM_AHB_CLK 9
	#define GCC_CAMERA_AHB_CLK 10
	#define GCC_CAMERA_HF_AXI_CLK 11
	#define GCC_CAMERA_THROTTLE_HF_AXI_CLK 12
	#define GCC_CAMERA_XO_CLK 13
	#define GCC_CE1_AHB_CLK 14
	#define GCC_CE1_AXI_CLK 15
	#define GCC_CE1_CLK 16
	#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17
	#define GCC_CPUSS_AHB_CLK 18
	#define GCC_CPUSS_AHB_CLK_SRC 19
	#define GCC_CPUSS_GNOC_CLK 20
	#define GCC_CPUSS_RBCPR_CLK 21
	#define GCC_DDRSS_GPU_AXI_CLK 22
	#define GCC_DISP_AHB_CLK 23
	#define GCC_DISP_GPLL0_CLK_SRC 24
	#define GCC_DISP_GPLL0_DIV_CLK_SRC 25
	#define GCC_DISP_HF_AXI_CLK 26
	#define GCC_DISP_THROTTLE_HF_AXI_CLK 27
	#define GCC_DISP_XO_CLK 28
	#define GCC_GP1_CLK 29
	#define GCC_GP1_CLK_SRC 30
	#define GCC_GP2_CLK 31
	#define GCC_GP2_CLK_SRC 32
	#define GCC_GP3_CLK 33
	#define GCC_GP3_CLK_SRC 34
	#define GCC_GPU_CFG_AHB_CLK 35
	#define GCC_GPU_GPLL0_CLK_SRC 36
	#define GCC_GPU_GPLL0_DIV_CLK_SRC 37
	#define GCC_GPU_MEMNOC_GFX_CLK 38
	#define GCC_GPU_SNOC_DVM_GFX_CLK 39
	#define GCC_NPU_AXI_CLK 40
	#define GCC_NPU_BWMON_AXI_CLK 41
	#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 42
	#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 43
	#define GCC_NPU_CFG_AHB_CLK 44
	#define GCC_NPU_DMA_CLK 45
	#define GCC_NPU_GPLL0_CLK_SRC 46
	#define GCC_NPU_GPLL0_DIV_CLK_SRC 47
	#define GCC_PDM2_CLK 48
	#define GCC_PDM2_CLK_SRC 49
	#define GCC_PDM_AHB_CLK 50
	#define GCC_PDM_XO4_CLK 51
	#define GCC_PRNG_AHB_CLK 52
	#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 53
	#define GCC_QSPI_CORE_CLK 54
	#define GCC_QSPI_CORE_CLK_SRC 55
	#define GCC_QUPV3_WRAP0_CORE_2X_CLK 56
	#define GCC_QUPV3_WRAP0_CORE_CLK 57
	#define GCC_QUPV3_WRAP0_S0_CLK 58
	#define GCC_QUPV3_WRAP0_S0_CLK_SRC 59
	#define GCC_QUPV3_WRAP0_S1_CLK 60
	#define GCC_QUPV3_WRAP0_S1_CLK_SRC 61
	#define GCC_QUPV3_WRAP0_S2_CLK 62
	#define GCC_QUPV3_WRAP0_S2_CLK_SRC 63
	#define GCC_QUPV3_WRAP0_S3_CLK 64
	#define GCC_QUPV3_WRAP0_S3_CLK_SRC 65
	#define GCC_QUPV3_WRAP0_S4_CLK 66
	#define GCC_QUPV3_WRAP0_S4_CLK_SRC 67
	#define GCC_QUPV3_WRAP0_S5_CLK 68
	#define GCC_QUPV3_WRAP0_S5_CLK_SRC 69
	#define GCC_QUPV3_WRAP1_CORE_2X_CLK 70
	#define GCC_QUPV3_WRAP1_CORE_CLK 71
	#define GCC_QUPV3_WRAP1_S0_CLK 72
	#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73
	#define GCC_QUPV3_WRAP1_S1_CLK 74
	#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75
	#define GCC_QUPV3_WRAP1_S2_CLK 76
	#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77
	#define GCC_QUPV3_WRAP1_S3_CLK 78
	#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79
	#define GCC_QUPV3_WRAP1_S4_CLK 80
	#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81
	#define GCC_QUPV3_WRAP1_S5_CLK 82
	#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83
	#define GCC_QUPV3_WRAP_0_M_AHB_CLK 84
	#define GCC_QUPV3_WRAP_0_S_AHB_CLK 85
	#define GCC_QUPV3_WRAP_1_M_AHB_CLK 86
	#define GCC_QUPV3_WRAP_1_S_AHB_CLK 87
	#define GCC_SDCC1_AHB_CLK 88
	#define GCC_SDCC1_APPS_CLK 89
	#define GCC_SDCC1_APPS_CLK_SRC 90
	#define GCC_SDCC1_ICE_CORE_CLK 91
	#define GCC_SDCC1_ICE_CORE_CLK_SRC 92
	#define GCC_SDCC2_AHB_CLK 93
	#define GCC_SDCC2_APPS_CLK 94
	#define GCC_SDCC2_APPS_CLK_SRC 95
	#define GCC_SYS_NOC_CPUSS_AHB_CLK 96
	#define GCC_UFS_MEM_CLKREF_CLK 97
	#define GCC_UFS_PHY_AHB_CLK 98
	#define GCC_UFS_PHY_AXI_CLK 99
	#define GCC_UFS_PHY_AXI_CLK_SRC 100
	#define GCC_UFS_PHY_ICE_CORE_CLK 101
	#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102
	#define GCC_UFS_PHY_PHY_AUX_CLK 103
	#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104
	#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105
	#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106
	#define GCC_UFS_PHY_UNIPRO_CORE_CLK 107
	#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108
	#define GCC_USB30_PRIM_MASTER_CLK 109
	#define GCC_USB30_PRIM_MASTER_CLK_SRC 110
	#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111
	#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112
	#define GCC_USB30_PRIM_SLEEP_CLK 113
	#define GCC_USB3_PRIM_CLKREF_CLK 114
	#define GCC_USB3_PRIM_PHY_AUX_CLK 115
	#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116
	#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117
	#define GCC_USB3_PRIM_PHY_PIPE_CLK 118
	#define GCC_USB_PHY_CFG_AHB2PHY_CLK 119
	#define GCC_VIDEO_AHB_CLK 120
	#define GCC_VIDEO_AXI_CLK 121
	#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122
	#define GCC_VIDEO_THROTTLE_AXI_CLK 123
	#define GCC_VIDEO_XO_CLK 124
	+#define GCC_MSS_CFG_AHB_CLK 125
	+#define GCC_MSS_MFAB_AXIS_CLK 126
	+#define GCC_MSS_NAV_AXI_CLK 127
	+#define GCC_MSS_Q6_MEMNOC_AXI_CLK 128
	+#define GCC_MSS_SNOC_AXI_CLK 129

	/* GCC resets */
	#define GCC_QUSB2PHY_PRIM_BCR 0
	#define GCC_QUSB2PHY_SEC_BCR 1
	#define GCC_UFS_PHY_BCR 2
	#define GCC_USB30_PRIM_BCR 3
	#define GCC_USB3_DP_PHY_PRIM_BCR 4
	#define GCC_USB3_DP_PHY_SEC_BCR 5
	#define GCC_USB3_PHY_PRIM_BCR 6
	#define GCC_USB3_PHY_SEC_BCR 7
	#define GCC_USB3PHY_PHY_PRIM_BCR 8
	#define GCC_USB3PHY_PHY_SEC_BCR 9
	#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10

	/* GCC GDSCRs */
	#define UFS_PHY_GDSC 0
	#define USB30_PRIM_GDSC 1
	#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2
	#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3

	#endif
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sm8150.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sm8150.h
	index 90d60ef94c64..3e1a91876610 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sm8150.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sm8150.h
	@@ -1,243 +1,247 @@
	/* SPDX-License-Identifier: GPL-2.0 */
	/*
	* Copyright (c) 2019, The Linux Foundation. All rights reserved.
	*/

	#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H
	#define _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H

	/* GCC clocks */
	#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
	#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
	#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 2
	#define GCC_AGGRE_UFS_PHY_AXI_CLK 3
	#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 4
	#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5
	#define GCC_AGGRE_USB3_SEC_AXI_CLK 6
	#define GCC_BOOT_ROM_AHB_CLK 7
	#define GCC_CAMERA_AHB_CLK 8
	#define GCC_CAMERA_HF_AXI_CLK 9
	#define GCC_CAMERA_SF_AXI_CLK 10
	#define GCC_CAMERA_XO_CLK 11
	#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
	#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13
	#define GCC_CPUSS_AHB_CLK 14
	#define GCC_CPUSS_AHB_CLK_SRC 15
	#define GCC_CPUSS_DVM_BUS_CLK 16
	#define GCC_CPUSS_GNOC_CLK 17
	#define GCC_CPUSS_RBCPR_CLK 18
	#define GCC_DDRSS_GPU_AXI_CLK 19
	#define GCC_DISP_AHB_CLK 20
	#define GCC_DISP_HF_AXI_CLK 21
	#define GCC_DISP_SF_AXI_CLK 22
	#define GCC_DISP_XO_CLK 23
	#define GCC_EMAC_AXI_CLK 24
	#define GCC_EMAC_PTP_CLK 25
	#define GCC_EMAC_PTP_CLK_SRC 26
	#define GCC_EMAC_RGMII_CLK 27
	#define GCC_EMAC_RGMII_CLK_SRC 28
	#define GCC_EMAC_SLV_AHB_CLK 29
	#define GCC_GP1_CLK 30
	#define GCC_GP1_CLK_SRC 31
	#define GCC_GP2_CLK 32
	#define GCC_GP2_CLK_SRC 33
	#define GCC_GP3_CLK 34
	#define GCC_GP3_CLK_SRC 35
	#define GCC_GPU_CFG_AHB_CLK 36
	#define GCC_GPU_GPLL0_CLK_SRC 37
	#define GCC_GPU_GPLL0_DIV_CLK_SRC 38
	#define GCC_GPU_IREF_CLK 39
	#define GCC_GPU_MEMNOC_GFX_CLK 40
	#define GCC_GPU_SNOC_DVM_GFX_CLK 41
	#define GCC_NPU_AT_CLK 42
	#define GCC_NPU_AXI_CLK 43
	#define GCC_NPU_CFG_AHB_CLK 44
	#define GCC_NPU_GPLL0_CLK_SRC 45
	#define GCC_NPU_GPLL0_DIV_CLK_SRC 46
	#define GCC_NPU_TRIG_CLK 47
	#define GCC_PCIE0_PHY_REFGEN_CLK 48
	#define GCC_PCIE1_PHY_REFGEN_CLK 49
	#define GCC_PCIE_0_AUX_CLK 50
	#define GCC_PCIE_0_AUX_CLK_SRC 51
	#define GCC_PCIE_0_CFG_AHB_CLK 52
	#define GCC_PCIE_0_CLKREF_CLK 53
	#define GCC_PCIE_0_MSTR_AXI_CLK 54
	#define GCC_PCIE_0_PIPE_CLK 55
	#define GCC_PCIE_0_SLV_AXI_CLK 56
	#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57
	#define GCC_PCIE_1_AUX_CLK 58
	#define GCC_PCIE_1_AUX_CLK_SRC 59
	#define GCC_PCIE_1_CFG_AHB_CLK 60
	#define GCC_PCIE_1_CLKREF_CLK 61
	#define GCC_PCIE_1_MSTR_AXI_CLK 62
	#define GCC_PCIE_1_PIPE_CLK 63
	#define GCC_PCIE_1_SLV_AXI_CLK 64
	#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 65
	#define GCC_PCIE_PHY_AUX_CLK 66
	#define GCC_PCIE_PHY_REFGEN_CLK_SRC 67
	#define GCC_PDM2_CLK 68
	#define GCC_PDM2_CLK_SRC 69
	#define GCC_PDM_AHB_CLK 70
	#define GCC_PDM_XO4_CLK 71
	#define GCC_PRNG_AHB_CLK 72
	#define GCC_QMIP_CAMERA_NRT_AHB_CLK 73
	#define GCC_QMIP_CAMERA_RT_AHB_CLK 74
	#define GCC_QMIP_DISP_AHB_CLK 75
	#define GCC_QMIP_VIDEO_CVP_AHB_CLK 76
	#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 77
	#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 78
	#define GCC_QSPI_CORE_CLK 79
	#define GCC_QSPI_CORE_CLK_SRC 80
	#define GCC_QUPV3_WRAP0_S0_CLK 81
	#define GCC_QUPV3_WRAP0_S0_CLK_SRC 82
	#define GCC_QUPV3_WRAP0_S1_CLK 83
	#define GCC_QUPV3_WRAP0_S1_CLK_SRC 84
	#define GCC_QUPV3_WRAP0_S2_CLK 85
	#define GCC_QUPV3_WRAP0_S2_CLK_SRC 86
	#define GCC_QUPV3_WRAP0_S3_CLK 87
	#define GCC_QUPV3_WRAP0_S3_CLK_SRC 88
	#define GCC_QUPV3_WRAP0_S4_CLK 89
	#define GCC_QUPV3_WRAP0_S4_CLK_SRC 90
	#define GCC_QUPV3_WRAP0_S5_CLK 91
	#define GCC_QUPV3_WRAP0_S5_CLK_SRC 92
	#define GCC_QUPV3_WRAP0_S6_CLK 93
	#define GCC_QUPV3_WRAP0_S6_CLK_SRC 94
	#define GCC_QUPV3_WRAP0_S7_CLK 95
	#define GCC_QUPV3_WRAP0_S7_CLK_SRC 96
	#define GCC_QUPV3_WRAP1_S0_CLK 97
	#define GCC_QUPV3_WRAP1_S0_CLK_SRC 98
	#define GCC_QUPV3_WRAP1_S1_CLK 99
	#define GCC_QUPV3_WRAP1_S1_CLK_SRC 100
	#define GCC_QUPV3_WRAP1_S2_CLK 101
	#define GCC_QUPV3_WRAP1_S2_CLK_SRC 102
	#define GCC_QUPV3_WRAP1_S3_CLK 103
	#define GCC_QUPV3_WRAP1_S3_CLK_SRC 104
	#define GCC_QUPV3_WRAP1_S4_CLK 105
	#define GCC_QUPV3_WRAP1_S4_CLK_SRC 106
	#define GCC_QUPV3_WRAP1_S5_CLK 107
	#define GCC_QUPV3_WRAP1_S5_CLK_SRC 108
	#define GCC_QUPV3_WRAP2_S0_CLK 109
	#define GCC_QUPV3_WRAP2_S0_CLK_SRC 110
	#define GCC_QUPV3_WRAP2_S1_CLK 111
	#define GCC_QUPV3_WRAP2_S1_CLK_SRC 112
	#define GCC_QUPV3_WRAP2_S2_CLK 113
	#define GCC_QUPV3_WRAP2_S2_CLK_SRC 114
	#define GCC_QUPV3_WRAP2_S3_CLK 115
	#define GCC_QUPV3_WRAP2_S3_CLK_SRC 116
	#define GCC_QUPV3_WRAP2_S4_CLK 117
	#define GCC_QUPV3_WRAP2_S4_CLK_SRC 118
	#define GCC_QUPV3_WRAP2_S5_CLK 119
	#define GCC_QUPV3_WRAP2_S5_CLK_SRC 120
	#define GCC_QUPV3_WRAP_0_M_AHB_CLK 121
	#define GCC_QUPV3_WRAP_0_S_AHB_CLK 122
	#define GCC_QUPV3_WRAP_1_M_AHB_CLK 123
	#define GCC_QUPV3_WRAP_1_S_AHB_CLK 124
	#define GCC_QUPV3_WRAP_2_M_AHB_CLK 125
	#define GCC_QUPV3_WRAP_2_S_AHB_CLK 126
	#define GCC_SDCC2_AHB_CLK 127
	#define GCC_SDCC2_APPS_CLK 128
	#define GCC_SDCC2_APPS_CLK_SRC 129
	#define GCC_SDCC4_AHB_CLK 130
	#define GCC_SDCC4_APPS_CLK 131
	#define GCC_SDCC4_APPS_CLK_SRC 132
	#define GCC_SYS_NOC_CPUSS_AHB_CLK 133
	#define GCC_TSIF_AHB_CLK 134
	#define GCC_TSIF_INACTIVITY_TIMERS_CLK 135
	#define GCC_TSIF_REF_CLK 136
	#define GCC_TSIF_REF_CLK_SRC 137
	#define GCC_UFS_CARD_AHB_CLK 138
	#define GCC_UFS_CARD_AXI_CLK 139
	#define GCC_UFS_CARD_AXI_CLK_SRC 140
	#define GCC_UFS_CARD_AXI_HW_CTL_CLK 141
	#define GCC_UFS_CARD_CLKREF_CLK 142
	#define GCC_UFS_CARD_ICE_CORE_CLK 143
	#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 144
	#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 145
	#define GCC_UFS_CARD_PHY_AUX_CLK 146
	#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 147
	#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 148
	#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 149
	#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 150
	#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 151
	#define GCC_UFS_CARD_UNIPRO_CORE_CLK 152
	#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 153
	#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 154
	#define GCC_UFS_MEM_CLKREF_CLK 155
	#define GCC_UFS_PHY_AHB_CLK 156
	#define GCC_UFS_PHY_AXI_CLK 157
	#define GCC_UFS_PHY_AXI_CLK_SRC 158
	#define GCC_UFS_PHY_AXI_HW_CTL_CLK 159
	#define GCC_UFS_PHY_ICE_CORE_CLK 160
	#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 161
	#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 162
	#define GCC_UFS_PHY_PHY_AUX_CLK 163
	#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 164
	#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 165
	#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 166
	#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 167
	#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168
	#define GCC_UFS_PHY_UNIPRO_CORE_CLK 169
	#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 170
	#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 171
	#define GCC_USB30_PRIM_MASTER_CLK 172
	#define GCC_USB30_PRIM_MASTER_CLK_SRC 173
	#define GCC_USB30_PRIM_MOCK_UTMI_CLK 174
	#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 175
	#define GCC_USB30_PRIM_SLEEP_CLK 176
	#define GCC_USB30_SEC_MASTER_CLK 177
	#define GCC_USB30_SEC_MASTER_CLK_SRC 178
	#define GCC_USB30_SEC_MOCK_UTMI_CLK 179
	#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 180
	#define GCC_USB30_SEC_SLEEP_CLK 181
	#define GCC_USB3_PRIM_CLKREF_CLK 182
	#define GCC_USB3_PRIM_PHY_AUX_CLK 183
	#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 184
	#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 185
	#define GCC_USB3_PRIM_PHY_PIPE_CLK 186
	#define GCC_USB3_SEC_CLKREF_CLK 187
	#define GCC_USB3_SEC_PHY_AUX_CLK 188
	#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 189
	#define GCC_USB3_SEC_PHY_COM_AUX_CLK 190
	#define GCC_USB3_SEC_PHY_PIPE_CLK 191
	#define GCC_VIDEO_AHB_CLK 192
	#define GCC_VIDEO_AXI0_CLK 193
	#define GCC_VIDEO_AXI1_CLK 194
	#define GCC_VIDEO_AXIC_CLK 195
	#define GCC_VIDEO_XO_CLK 196
	#define GPLL0 197
	#define GPLL0_OUT_EVEN 198
	#define GPLL7 199
	#define GPLL9 200

	/* Reset clocks */
	#define GCC_EMAC_BCR 0
	#define GCC_GPU_BCR 1
	#define GCC_MMSS_BCR 2
	#define GCC_NPU_BCR 3
	#define GCC_PCIE_0_BCR 4
	#define GCC_PCIE_0_PHY_BCR 5
	#define GCC_PCIE_1_BCR 6
	#define GCC_PCIE_1_PHY_BCR 7
	#define GCC_PCIE_PHY_BCR 8
	#define GCC_PDM_BCR 9
	#define GCC_PRNG_BCR 10
	#define GCC_QSPI_BCR 11
	#define GCC_QUPV3_WRAPPER_0_BCR 12
	#define GCC_QUPV3_WRAPPER_1_BCR 13
	#define GCC_QUPV3_WRAPPER_2_BCR 14
	#define GCC_QUSB2PHY_PRIM_BCR 15
	#define GCC_QUSB2PHY_SEC_BCR 16
	#define GCC_USB3_PHY_PRIM_BCR 17
	#define GCC_USB3_DP_PHY_PRIM_BCR 18
	#define GCC_USB3_PHY_SEC_BCR 19
	#define GCC_USB3PHY_PHY_SEC_BCR 20
	#define GCC_SDCC2_BCR 21
	#define GCC_SDCC4_BCR 22
	#define GCC_TSIF_BCR 23
	#define GCC_UFS_CARD_BCR 24
	#define GCC_UFS_PHY_BCR 25
	#define GCC_USB30_PRIM_BCR 26
	#define GCC_USB30_SEC_BCR 27
	#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28

	+/* GCC GDSCRs */
	+#define USB30_PRIM_GDSC 4
	+#define USB30_SEC_GDSC 5
	+
	#endif
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sm8250.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sm8250.h
	new file mode 100644
	index 000000000000..7b7abe327e37
	--- /dev/null
	+++ b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sm8250.h
	@@ -0,0 +1,271 @@
	+/* SPDX-License-Identifier: GPL-2.0-only */
	+/*
	+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
	+ */
	+
	+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
	+#define _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
	+
	+/* GCC clocks */
	+#define GPLL0 0
	+#define GPLL0_OUT_EVEN 1
	+#define GPLL4 2
	+#define GPLL9 3
	+#define GCC_AGGRE_NOC_PCIE_TBU_CLK 4
	+#define GCC_AGGRE_UFS_CARD_AXI_CLK 5
	+#define GCC_AGGRE_UFS_PHY_AXI_CLK 6
	+#define GCC_AGGRE_USB3_PRIM_AXI_CLK 7
	+#define GCC_AGGRE_USB3_SEC_AXI_CLK 8
	+#define GCC_BOOT_ROM_AHB_CLK 9
	+#define GCC_CAMERA_AHB_CLK 10
	+#define GCC_CAMERA_HF_AXI_CLK 11
	+#define GCC_CAMERA_SF_AXI_CLK 12
	+#define GCC_CAMERA_XO_CLK 13
	+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 14
	+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 15
	+#define GCC_CPUSS_AHB_CLK 16
	+#define GCC_CPUSS_AHB_CLK_SRC 17
	+#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 18
	+#define GCC_CPUSS_DVM_BUS_CLK 19
	+#define GCC_CPUSS_RBCPR_CLK 20
	+#define GCC_DDRSS_GPU_AXI_CLK 21
	+#define GCC_DDRSS_PCIE_SF_TBU_CLK 22
	+#define GCC_DISP_AHB_CLK 23
	+#define GCC_DISP_HF_AXI_CLK 24
	+#define GCC_DISP_SF_AXI_CLK 25
	+#define GCC_DISP_XO_CLK 26
	+#define GCC_GP1_CLK 27
	+#define GCC_GP1_CLK_SRC 28
	+#define GCC_GP2_CLK 29
	+#define GCC_GP2_CLK_SRC 30
	+#define GCC_GP3_CLK 31
	+#define GCC_GP3_CLK_SRC 32
	+#define GCC_GPU_CFG_AHB_CLK 33
	+#define GCC_GPU_GPLL0_CLK_SRC 34
	+#define GCC_GPU_GPLL0_DIV_CLK_SRC 35
	+#define GCC_GPU_IREF_EN 36
	+#define GCC_GPU_MEMNOC_GFX_CLK 37
	+#define GCC_GPU_SNOC_DVM_GFX_CLK 38
	+#define GCC_NPU_AXI_CLK 39
	+#define GCC_NPU_BWMON_AXI_CLK 40
	+#define GCC_NPU_BWMON_CFG_AHB_CLK 41
	+#define GCC_NPU_CFG_AHB_CLK 42
	+#define GCC_NPU_DMA_CLK 43
	+#define GCC_NPU_GPLL0_CLK_SRC 44
	+#define GCC_NPU_GPLL0_DIV_CLK_SRC 45
	+#define GCC_PCIE0_PHY_REFGEN_CLK 46
	+#define GCC_PCIE1_PHY_REFGEN_CLK 47
	+#define GCC_PCIE2_PHY_REFGEN_CLK 48
	+#define GCC_PCIE_0_AUX_CLK 49
	+#define GCC_PCIE_0_AUX_CLK_SRC 50
	+#define GCC_PCIE_0_CFG_AHB_CLK 51
	+#define GCC_PCIE_0_MSTR_AXI_CLK 52
	+#define GCC_PCIE_0_PIPE_CLK 53
	+#define GCC_PCIE_0_SLV_AXI_CLK 54
	+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 55
	+#define GCC_PCIE_1_AUX_CLK 56
	+#define GCC_PCIE_1_AUX_CLK_SRC 57
	+#define GCC_PCIE_1_CFG_AHB_CLK 58
	+#define GCC_PCIE_1_MSTR_AXI_CLK 59
	+#define GCC_PCIE_1_PIPE_CLK 60
	+#define GCC_PCIE_1_SLV_AXI_CLK 61
	+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 62
	+#define GCC_PCIE_2_AUX_CLK 63
	+#define GCC_PCIE_2_AUX_CLK_SRC 64
	+#define GCC_PCIE_2_CFG_AHB_CLK 65
	+#define GCC_PCIE_2_MSTR_AXI_CLK 66
	+#define GCC_PCIE_2_PIPE_CLK 67
	+#define GCC_PCIE_2_SLV_AXI_CLK 68
	+#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 69
	+#define GCC_PCIE_MDM_CLKREF_EN 70
	+#define GCC_PCIE_PHY_AUX_CLK 71
	+#define GCC_PCIE_PHY_REFGEN_CLK_SRC 72
	+#define GCC_PCIE_WIFI_CLKREF_EN 73
	+#define GCC_PCIE_WIGIG_CLKREF_EN 74
	+#define GCC_PDM2_CLK 75
	+#define GCC_PDM2_CLK_SRC 76
	+#define GCC_PDM_AHB_CLK 77
	+#define GCC_PDM_XO4_CLK 78
	+#define GCC_PRNG_AHB_CLK 79
	+#define GCC_QMIP_CAMERA_NRT_AHB_CLK 80
	+#define GCC_QMIP_CAMERA_RT_AHB_CLK 81
	+#define GCC_QMIP_DISP_AHB_CLK 82
	+#define GCC_QMIP_VIDEO_CVP_AHB_CLK 83
	+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 84
	+#define GCC_QUPV3_WRAP0_CORE_2X_CLK 85
	+#define GCC_QUPV3_WRAP0_CORE_CLK 86
	+#define GCC_QUPV3_WRAP0_S0_CLK 87
	+#define GCC_QUPV3_WRAP0_S0_CLK_SRC 88
	+#define GCC_QUPV3_WRAP0_S1_CLK 89
	+#define GCC_QUPV3_WRAP0_S1_CLK_SRC 90
	+#define GCC_QUPV3_WRAP0_S2_CLK 91
	+#define GCC_QUPV3_WRAP0_S2_CLK_SRC 92
	+#define GCC_QUPV3_WRAP0_S3_CLK 93
	+#define GCC_QUPV3_WRAP0_S3_CLK_SRC 94
	+#define GCC_QUPV3_WRAP0_S4_CLK 95
	+#define GCC_QUPV3_WRAP0_S4_CLK_SRC 96
	+#define GCC_QUPV3_WRAP0_S5_CLK 97
	+#define GCC_QUPV3_WRAP0_S5_CLK_SRC 98
	+#define GCC_QUPV3_WRAP0_S6_CLK 99
	+#define GCC_QUPV3_WRAP0_S6_CLK_SRC 100
	+#define GCC_QUPV3_WRAP0_S7_CLK 101
	+#define GCC_QUPV3_WRAP0_S7_CLK_SRC 102
	+#define GCC_QUPV3_WRAP1_CORE_2X_CLK 103
	+#define GCC_QUPV3_WRAP1_CORE_CLK 104
	+#define GCC_QUPV3_WRAP1_S0_CLK 105
	+#define GCC_QUPV3_WRAP1_S0_CLK_SRC 106
	+#define GCC_QUPV3_WRAP1_S1_CLK 107
	+#define GCC_QUPV3_WRAP1_S1_CLK_SRC 108
	+#define GCC_QUPV3_WRAP1_S2_CLK 109
	+#define GCC_QUPV3_WRAP1_S2_CLK_SRC 110
	+#define GCC_QUPV3_WRAP1_S3_CLK 111
	+#define GCC_QUPV3_WRAP1_S3_CLK_SRC 112
	+#define GCC_QUPV3_WRAP1_S4_CLK 113
	+#define GCC_QUPV3_WRAP1_S4_CLK_SRC 114
	+#define GCC_QUPV3_WRAP1_S5_CLK 115
	+#define GCC_QUPV3_WRAP1_S5_CLK_SRC 116
	+#define GCC_QUPV3_WRAP2_CORE_2X_CLK 117
	+#define GCC_QUPV3_WRAP2_CORE_CLK 118
	+#define GCC_QUPV3_WRAP2_S0_CLK 119
	+#define GCC_QUPV3_WRAP2_S0_CLK_SRC 120
	+#define GCC_QUPV3_WRAP2_S1_CLK 121
	+#define GCC_QUPV3_WRAP2_S1_CLK_SRC 122
	+#define GCC_QUPV3_WRAP2_S2_CLK 123
	+#define GCC_QUPV3_WRAP2_S2_CLK_SRC 124
	+#define GCC_QUPV3_WRAP2_S3_CLK 125
	+#define GCC_QUPV3_WRAP2_S3_CLK_SRC 126
	+#define GCC_QUPV3_WRAP2_S4_CLK 127
	+#define GCC_QUPV3_WRAP2_S4_CLK_SRC 128
	+#define GCC_QUPV3_WRAP2_S5_CLK 129
	+#define GCC_QUPV3_WRAP2_S5_CLK_SRC 130
	+#define GCC_QUPV3_WRAP_0_M_AHB_CLK 131
	+#define GCC_QUPV3_WRAP_0_S_AHB_CLK 132
	+#define GCC_QUPV3_WRAP_1_M_AHB_CLK 133
	+#define GCC_QUPV3_WRAP_1_S_AHB_CLK 134
	+#define GCC_QUPV3_WRAP_2_M_AHB_CLK 135
	+#define GCC_QUPV3_WRAP_2_S_AHB_CLK 136
	+#define GCC_SDCC2_AHB_CLK 137
	+#define GCC_SDCC2_APPS_CLK 138
	+#define GCC_SDCC2_APPS_CLK_SRC 139
	+#define GCC_SDCC4_AHB_CLK 140
	+#define GCC_SDCC4_APPS_CLK 141
	+#define GCC_SDCC4_APPS_CLK_SRC 142
	+#define GCC_SYS_NOC_CPUSS_AHB_CLK 143
	+#define GCC_TSIF_AHB_CLK 144
	+#define GCC_TSIF_INACTIVITY_TIMERS_CLK 145
	+#define GCC_TSIF_REF_CLK 146
	+#define GCC_TSIF_REF_CLK_SRC 147
	+#define GCC_UFS_1X_CLKREF_EN 148
	+#define GCC_UFS_CARD_AHB_CLK 149
	+#define GCC_UFS_CARD_AXI_CLK 150
	+#define GCC_UFS_CARD_AXI_CLK_SRC 151
	+#define GCC_UFS_CARD_ICE_CORE_CLK 152
	+#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 153
	+#define GCC_UFS_CARD_PHY_AUX_CLK 154
	+#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 155
	+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 156
	+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 157
	+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 158
	+#define GCC_UFS_CARD_UNIPRO_CORE_CLK 159
	+#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 160
	+#define GCC_UFS_PHY_AHB_CLK 161
	+#define GCC_UFS_PHY_AXI_CLK 162
	+#define GCC_UFS_PHY_AXI_CLK_SRC 163
	+#define GCC_UFS_PHY_ICE_CORE_CLK 164
	+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 165
	+#define GCC_UFS_PHY_PHY_AUX_CLK 166
	+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 167
	+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 168
	+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 169
	+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 170
	+#define GCC_UFS_PHY_UNIPRO_CORE_CLK 171
	+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 172
	+#define GCC_USB30_PRIM_MASTER_CLK 173
	+#define GCC_USB30_PRIM_MASTER_CLK_SRC 174
	+#define GCC_USB30_PRIM_MOCK_UTMI_CLK 175
	+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176
	+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177
	+#define GCC_USB30_PRIM_SLEEP_CLK 178
	+#define GCC_USB30_SEC_MASTER_CLK 179
	+#define GCC_USB30_SEC_MASTER_CLK_SRC 180
	+#define GCC_USB30_SEC_MOCK_UTMI_CLK 181
	+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 182
	+#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 183
	+#define GCC_USB30_SEC_SLEEP_CLK 184
	+#define GCC_USB3_PRIM_PHY_AUX_CLK 185
	+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 186
	+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 187
	+#define GCC_USB3_PRIM_PHY_PIPE_CLK 188
	+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 189
	+#define GCC_USB3_SEC_CLKREF_EN 190
	+#define GCC_USB3_SEC_PHY_AUX_CLK 191
	+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 192
	+#define GCC_USB3_SEC_PHY_COM_AUX_CLK 193
	+#define GCC_USB3_SEC_PHY_PIPE_CLK 194
	+#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 195
	+#define GCC_VIDEO_AHB_CLK 196
	+#define GCC_VIDEO_AXI0_CLK 197
	+#define GCC_VIDEO_AXI1_CLK 198
	+#define GCC_VIDEO_XO_CLK 199
	+
	+/* GCC resets */
	+#define GCC_GPU_BCR 0
	+#define GCC_MMSS_BCR 1
	+#define GCC_NPU_BWMON_BCR 2
	+#define GCC_NPU_BCR 3
	+#define GCC_PCIE_0_BCR 4
	+#define GCC_PCIE_0_LINK_DOWN_BCR 5
	+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
	+#define GCC_PCIE_0_PHY_BCR 7
	+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
	+#define GCC_PCIE_1_BCR 9
	+#define GCC_PCIE_1_LINK_DOWN_BCR 10
	+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11
	+#define GCC_PCIE_1_PHY_BCR 12
	+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13
	+#define GCC_PCIE_2_BCR 14
	+#define GCC_PCIE_2_LINK_DOWN_BCR 15
	+#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 16
	+#define GCC_PCIE_2_PHY_BCR 17
	+#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 18
	+#define GCC_PCIE_PHY_BCR 19
	+#define GCC_PCIE_PHY_CFG_AHB_BCR 20
	+#define GCC_PCIE_PHY_COM_BCR 21
	+#define GCC_PDM_BCR 22
	+#define GCC_PRNG_BCR 23
	+#define GCC_QUPV3_WRAPPER_0_BCR 24
	+#define GCC_QUPV3_WRAPPER_1_BCR 25
	+#define GCC_QUPV3_WRAPPER_2_BCR 26
	+#define GCC_QUSB2PHY_PRIM_BCR 27
	+#define GCC_QUSB2PHY_SEC_BCR 28
	+#define GCC_SDCC2_BCR 29
	+#define GCC_SDCC4_BCR 30
	+#define GCC_TSIF_BCR 31
	+#define GCC_UFS_CARD_BCR 32
	+#define GCC_UFS_PHY_BCR 33
	+#define GCC_USB30_PRIM_BCR 34
	+#define GCC_USB30_SEC_BCR 35
	+#define GCC_USB3_DP_PHY_PRIM_BCR 36
	+#define GCC_USB3_DP_PHY_SEC_BCR 37
	+#define GCC_USB3_PHY_PRIM_BCR 38
	+#define GCC_USB3_PHY_SEC_BCR 39
	+#define GCC_USB3PHY_PHY_PRIM_BCR 40
	+#define GCC_USB3PHY_PHY_SEC_BCR 41
	+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 42
	+#define GCC_VIDEO_AXI0_CLK_ARES 43
	+#define GCC_VIDEO_AXI1_CLK_ARES 44
	+
	+/* GCC power domains */
	+#define PCIE_0_GDSC 0
	+#define PCIE_1_GDSC 1
	+#define PCIE_2_GDSC 2
	+#define UFS_CARD_GDSC 3
	+#define UFS_PHY_GDSC 4
	+#define USB30_PRIM_GDSC 5
	+#define USB30_SEC_GDSC 6
	+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 7
	+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 8
	+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 9
	+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 10
	+
	+#endif
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gpucc-sc7180.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gpucc-sc7180.h
	index 0e4643b08b49..65e706d7d9c6 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gpucc-sc7180.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/qcom,gpucc-sc7180.h
	@@ -1,21 +1,22 @@
	/* SPDX-License-Identifier: GPL-2.0-only */
	/*
	* Copyright (c) 2019, The Linux Foundation. All rights reserved.
	*/

	#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7180_H
	#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7180_H

	#define GPU_CC_PLL1 0
	#define GPU_CC_AHB_CLK 1
	#define GPU_CC_CRC_AHB_CLK 2
	#define GPU_CC_CX_GMU_CLK 3
	#define GPU_CC_CX_SNOC_DVM_CLK 4
	#define GPU_CC_CXO_AON_CLK 5
	#define GPU_CC_CXO_CLK 6
	#define GPU_CC_GMU_CLK_SRC 7

	-/* CAM_CC GDSCRs */
	+/* GPU_CC GDSCRs */
	#define CX_GDSC 0
	+#define GX_GDSC 1

	#endif
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,mss-sc7180.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,mss-sc7180.h
	new file mode 100644
	index 000000000000..f15a9ded2961
	--- /dev/null
	+++ b/sys/gnu/dts/include/dt-bindings/clock/qcom,mss-sc7180.h
	@@ -0,0 +1,12 @@
	+/* SPDX-License-Identifier: GPL-2.0-only */
	+/*
	+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
	+ */
	+
	+#ifndef _DT_BINDINGS_CLK_QCOM_MSS_SC7180_H
	+#define _DT_BINDINGS_CLK_QCOM_MSS_SC7180_H
	+
	+#define MSS_AXI_CRYPTO_CLK 0
	+#define MSS_AXI_NAV_CLK 1
	+
	+#endif
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,rpmcc.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,rpmcc.h
	index 8e3095720552..ae74c43c485d 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/qcom,rpmcc.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/qcom,rpmcc.h
	@@ -1,133 +1,137 @@
	/* SPDX-License-Identifier: GPL-2.0-only */
	/*
	* Copyright 2015 Linaro Limited
	*/

	#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
	#define _DT_BINDINGS_CLK_MSM_RPMCC_H

	/* RPM clocks */
	#define RPM_PXO_CLK 0
	#define RPM_PXO_A_CLK 1
	#define RPM_CXO_CLK 2
	#define RPM_CXO_A_CLK 3
	#define RPM_APPS_FABRIC_CLK 4
	#define RPM_APPS_FABRIC_A_CLK 5
	#define RPM_CFPB_CLK 6
	#define RPM_CFPB_A_CLK 7
	#define RPM_QDSS_CLK 8
	#define RPM_QDSS_A_CLK 9
	#define RPM_DAYTONA_FABRIC_CLK 10
	#define RPM_DAYTONA_FABRIC_A_CLK 11
	#define RPM_EBI1_CLK 12
	#define RPM_EBI1_A_CLK 13
	#define RPM_MM_FABRIC_CLK 14
	#define RPM_MM_FABRIC_A_CLK 15
	#define RPM_MMFPB_CLK 16
	#define RPM_MMFPB_A_CLK 17
	#define RPM_SYS_FABRIC_CLK 18
	#define RPM_SYS_FABRIC_A_CLK 19
	#define RPM_SFPB_CLK 20
	#define RPM_SFPB_A_CLK 21
	#define RPM_SMI_CLK 22
	#define RPM_SMI_A_CLK 23
	#define RPM_PLL4_CLK 24
	#define RPM_XO_D0 25
	#define RPM_XO_D1 26
	#define RPM_XO_A0 27
	#define RPM_XO_A1 28
	#define RPM_XO_A2 29
	+#define RPM_NSS_FABRIC_0_CLK 30
	+#define RPM_NSS_FABRIC_0_A_CLK 31
	+#define RPM_NSS_FABRIC_1_CLK 32
	+#define RPM_NSS_FABRIC_1_A_CLK 33

	/* SMD RPM clocks */
	#define RPM_SMD_XO_CLK_SRC 0
	#define RPM_SMD_XO_A_CLK_SRC 1
	#define RPM_SMD_PCNOC_CLK 2
	#define RPM_SMD_PCNOC_A_CLK 3
	#define RPM_SMD_SNOC_CLK 4
	#define RPM_SMD_SNOC_A_CLK 5
	#define RPM_SMD_BIMC_CLK 6
	#define RPM_SMD_BIMC_A_CLK 7
	#define RPM_SMD_QDSS_CLK 8
	#define RPM_SMD_QDSS_A_CLK 9
	#define RPM_SMD_BB_CLK1 10
	#define RPM_SMD_BB_CLK1_A 11
	#define RPM_SMD_BB_CLK2 12
	#define RPM_SMD_BB_CLK2_A 13
	#define RPM_SMD_RF_CLK1 14
	#define RPM_SMD_RF_CLK1_A 15
	#define RPM_SMD_RF_CLK2 16
	#define RPM_SMD_RF_CLK2_A 17
	#define RPM_SMD_BB_CLK1_PIN 18
	#define RPM_SMD_BB_CLK1_A_PIN 19
	#define RPM_SMD_BB_CLK2_PIN 20
	#define RPM_SMD_BB_CLK2_A_PIN 21
	#define RPM_SMD_RF_CLK1_PIN 22
	#define RPM_SMD_RF_CLK1_A_PIN 23
	#define RPM_SMD_RF_CLK2_PIN 24
	#define RPM_SMD_RF_CLK2_A_PIN 25
	#define RPM_SMD_PNOC_CLK 26
	#define RPM_SMD_PNOC_A_CLK 27
	#define RPM_SMD_CNOC_CLK 28
	#define RPM_SMD_CNOC_A_CLK 29
	#define RPM_SMD_MMSSNOC_AHB_CLK 30
	#define RPM_SMD_MMSSNOC_AHB_A_CLK 31
	#define RPM_SMD_GFX3D_CLK_SRC 32
	#define RPM_SMD_GFX3D_A_CLK_SRC 33
	#define RPM_SMD_OCMEMGX_CLK 34
	#define RPM_SMD_OCMEMGX_A_CLK 35
	#define RPM_SMD_CXO_D0 36
	#define RPM_SMD_CXO_D0_A 37
	#define RPM_SMD_CXO_D1 38
	#define RPM_SMD_CXO_D1_A 39
	#define RPM_SMD_CXO_A0 40
	#define RPM_SMD_CXO_A0_A 41
	#define RPM_SMD_CXO_A1 42
	#define RPM_SMD_CXO_A1_A 43
	#define RPM_SMD_CXO_A2 44
	#define RPM_SMD_CXO_A2_A 45
	#define RPM_SMD_DIV_CLK1 46
	#define RPM_SMD_DIV_A_CLK1 47
	#define RPM_SMD_DIV_CLK2 48
	#define RPM_SMD_DIV_A_CLK2 49
	#define RPM_SMD_DIFF_CLK 50
	#define RPM_SMD_DIFF_A_CLK 51
	#define RPM_SMD_CXO_D0_PIN 52
	#define RPM_SMD_CXO_D0_A_PIN 53
	#define RPM_SMD_CXO_D1_PIN 54
	#define RPM_SMD_CXO_D1_A_PIN 55
	#define RPM_SMD_CXO_A0_PIN 56
	#define RPM_SMD_CXO_A0_A_PIN 57
	#define RPM_SMD_CXO_A1_PIN 58
	#define RPM_SMD_CXO_A1_A_PIN 59
	#define RPM_SMD_CXO_A2_PIN 60
	#define RPM_SMD_CXO_A2_A_PIN 61
	#define RPM_SMD_AGGR1_NOC_CLK 62
	#define RPM_SMD_AGGR1_NOC_A_CLK 63
	#define RPM_SMD_AGGR2_NOC_CLK 64
	#define RPM_SMD_AGGR2_NOC_A_CLK 65
	#define RPM_SMD_MMAXI_CLK 66
	#define RPM_SMD_MMAXI_A_CLK 67
	#define RPM_SMD_IPA_CLK 68
	#define RPM_SMD_IPA_A_CLK 69
	#define RPM_SMD_CE1_CLK 70
	#define RPM_SMD_CE1_A_CLK 71
	#define RPM_SMD_DIV_CLK3 72
	#define RPM_SMD_DIV_A_CLK3 73
	#define RPM_SMD_LN_BB_CLK 74
	#define RPM_SMD_LN_BB_A_CLK 75
	#define RPM_SMD_BIMC_GPU_CLK 76
	#define RPM_SMD_BIMC_GPU_A_CLK 77
	#define RPM_SMD_QPIC_CLK 78
	#define RPM_SMD_QPIC_CLK_A 79
	#define RPM_SMD_LN_BB_CLK1 80
	#define RPM_SMD_LN_BB_CLK1_A 81
	#define RPM_SMD_LN_BB_CLK2 82
	#define RPM_SMD_LN_BB_CLK2_A 83
	#define RPM_SMD_LN_BB_CLK3_PIN 84
	#define RPM_SMD_LN_BB_CLK3_A_PIN 85
	#define RPM_SMD_RF_CLK3 86
	#define RPM_SMD_RF_CLK3_A 87
	#define RPM_SMD_RF_CLK3_PIN 88
	#define RPM_SMD_RF_CLK3_A_PIN 89

	#endif
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,rpmh.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,rpmh.h
	index edcab3f7b7d3..2e6c54e65455 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/qcom,rpmh.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/qcom,rpmh.h
	@@ -1,23 +1,25 @@
	/* SPDX-License-Identifier: GPL-2.0 */
	-/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
	+/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */


	#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
	#define _DT_BINDINGS_CLK_MSM_RPMH_H

	/* RPMh controlled clocks */
	#define RPMH_CXO_CLK 0
	#define RPMH_CXO_CLK_A 1
	#define RPMH_LN_BB_CLK2 2
	#define RPMH_LN_BB_CLK2_A 3
	#define RPMH_LN_BB_CLK3 4
	#define RPMH_LN_BB_CLK3_A 5
	#define RPMH_RF_CLK1 6
	#define RPMH_RF_CLK1_A 7
	#define RPMH_RF_CLK2 8
	#define RPMH_RF_CLK2_A 9
	#define RPMH_RF_CLK3 10
	#define RPMH_RF_CLK3_A 11
	#define RPMH_IPA_CLK 12
	+#define RPMH_LN_BB_CLK1 13
	+#define RPMH_LN_BB_CLK1_A 14

	#endif
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/sprd,sc9863a-clk.h b/sys/gnu/dts/include/dt-bindings/clock/sprd,sc9863a-clk.h
	new file mode 100644
	index 000000000000..901ba59676c2
	--- /dev/null
	+++ b/sys/gnu/dts/include/dt-bindings/clock/sprd,sc9863a-clk.h
	@@ -0,0 +1,334 @@
	+/* SPDX-License-Identifier: GPL-2.0-only */
	+/*
	+ * Unisoc SC9863A platform clocks
	+ *
	+ * Copyright (C) 2019, Unisoc Communications Inc.
	+ */
	+
	+#ifndef _DT_BINDINGS_CLK_SC9863A_H_
	+#define _DT_BINDINGS_CLK_SC9863A_H_
	+
	+#define CLK_MPLL0_GATE 0
	+#define CLK_DPLL0_GATE 1
	+#define CLK_LPLL_GATE 2
	+#define CLK_GPLL_GATE 3
	+#define CLK_DPLL1_GATE 4
	+#define CLK_MPLL1_GATE 5
	+#define CLK_MPLL2_GATE 6
	+#define CLK_ISPPLL_GATE 7
	+#define CLK_PMU_APB_NUM (CLK_ISPPLL_GATE + 1)
	+
	+#define CLK_AUDIO_GATE 0
	+#define CLK_RPLL 1
	+#define CLK_RPLL_390M 2
	+#define CLK_RPLL_260M 3
	+#define CLK_RPLL_195M 4
	+#define CLK_RPLL_26M 5
	+#define CLK_ANLG_PHY_G5_NUM (CLK_RPLL_26M + 1)
	+
	+#define CLK_TWPLL 0
	+#define CLK_TWPLL_768M 1
	+#define CLK_TWPLL_384M 2
	+#define CLK_TWPLL_192M 3
	+#define CLK_TWPLL_96M 4
	+#define CLK_TWPLL_48M 5
	+#define CLK_TWPLL_24M 6
	+#define CLK_TWPLL_12M 7
	+#define CLK_TWPLL_512M 8
	+#define CLK_TWPLL_256M 9
	+#define CLK_TWPLL_128M 10
	+#define CLK_TWPLL_64M 11
	+#define CLK_TWPLL_307M2 12
	+#define CLK_TWPLL_219M4 13
	+#define CLK_TWPLL_170M6 14
	+#define CLK_TWPLL_153M6 15
	+#define CLK_TWPLL_76M8 16
	+#define CLK_TWPLL_51M2 17
	+#define CLK_TWPLL_38M4 18
	+#define CLK_TWPLL_19M2 19
	+#define CLK_LPLL 20
	+#define CLK_LPLL_409M6 21
	+#define CLK_LPLL_245M76 22
	+#define CLK_GPLL 23
	+#define CLK_ISPPLL 24
	+#define CLK_ISPPLL_468M 25
	+#define CLK_ANLG_PHY_G1_NUM (CLK_ISPPLL_468M + 1)
	+
	+#define CLK_DPLL0 0
	+#define CLK_DPLL1 1
	+#define CLK_DPLL0_933M 2
	+#define CLK_DPLL0_622M3 3
	+#define CLK_DPLL0_400M 4
	+#define CLK_DPLL0_266M7 5
	+#define CLK_DPLL0_123M1 6
	+#define CLK_DPLL0_50M 7
	+#define CLK_ANLG_PHY_G7_NUM (CLK_DPLL0_50M + 1)
	+
	+#define CLK_MPLL0 0
	+#define CLK_MPLL1 1
	+#define CLK_MPLL2 2
	+#define CLK_MPLL2_675M 3
	+#define CLK_ANLG_PHY_G4_NUM (CLK_MPLL2_675M + 1)
	+
	+#define CLK_AP_APB 0
	+#define CLK_AP_CE 1
	+#define CLK_NANDC_ECC 2
	+#define CLK_NANDC_26M 3
	+#define CLK_EMMC_32K 4
	+#define CLK_SDIO0_32K 5
	+#define CLK_SDIO1_32K 6
	+#define CLK_SDIO2_32K 7
	+#define CLK_OTG_UTMI 8
	+#define CLK_AP_UART0 9
	+#define CLK_AP_UART1 10
	+#define CLK_AP_UART2 11
	+#define CLK_AP_UART3 12
	+#define CLK_AP_UART4 13
	+#define CLK_AP_I2C0 14
	+#define CLK_AP_I2C1 15
	+#define CLK_AP_I2C2 16
	+#define CLK_AP_I2C3 17
	+#define CLK_AP_I2C4 18
	+#define CLK_AP_I2C5 19
	+#define CLK_AP_I2C6 20
	+#define CLK_AP_SPI0 21
	+#define CLK_AP_SPI1 22
	+#define CLK_AP_SPI2 23
	+#define CLK_AP_SPI3 24
	+#define CLK_AP_IIS0 25
	+#define CLK_AP_IIS1 26
	+#define CLK_AP_IIS2 27
	+#define CLK_SIM0 28
	+#define CLK_SIM0_32K 29
	+#define CLK_AP_CLK_NUM (CLK_SIM0_32K + 1)
	+
	+#define CLK_13M 0
	+#define CLK_6M5 1
	+#define CLK_4M3 2
	+#define CLK_2M 3
	+#define CLK_250K 4
	+#define CLK_RCO_25M 5
	+#define CLK_RCO_4M 6
	+#define CLK_RCO_2M 7
	+#define CLK_EMC 8
	+#define CLK_AON_APB 9
	+#define CLK_ADI 10
	+#define CLK_AUX0 11
	+#define CLK_AUX1 12
	+#define CLK_AUX2 13
	+#define CLK_PROBE 14
	+#define CLK_PWM0 15
	+#define CLK_PWM1 16
	+#define CLK_PWM2 17
	+#define CLK_AON_THM 18
	+#define CLK_AUDIF 19
	+#define CLK_CPU_DAP 20
	+#define CLK_CPU_TS 21
	+#define CLK_DJTAG_TCK 22
	+#define CLK_EMC_REF 23
	+#define CLK_CSSYS 24
	+#define CLK_AON_PMU 25
	+#define CLK_PMU_26M 26
	+#define CLK_AON_TMR 27
	+#define CLK_POWER_CPU 28
	+#define CLK_AP_AXI 29
	+#define CLK_SDIO0_2X 30
	+#define CLK_SDIO1_2X 31
	+#define CLK_SDIO2_2X 32
	+#define CLK_EMMC_2X 33
	+#define CLK_DPU 34
	+#define CLK_DPU_DPI 35
	+#define CLK_OTG_REF 36
	+#define CLK_SDPHY_APB 37
	+#define CLK_ALG_IO_APB 38
	+#define CLK_GPU_CORE 39
	+#define CLK_GPU_SOC 40
	+#define CLK_MM_EMC 41
	+#define CLK_MM_AHB 42
	+#define CLK_BPC 43
	+#define CLK_DCAM_IF 44
	+#define CLK_ISP 45
	+#define CLK_JPG 46
	+#define CLK_CPP 47
	+#define CLK_SENSOR0 48
	+#define CLK_SENSOR1 49
	+#define CLK_SENSOR2 50
	+#define CLK_MM_VEMC 51
	+#define CLK_MM_VAHB 52
	+#define CLK_VSP 53
	+#define CLK_CORE0 54
	+#define CLK_CORE1 55
	+#define CLK_CORE2 56
	+#define CLK_CORE3 57
	+#define CLK_CORE4 58
	+#define CLK_CORE5 59
	+#define CLK_CORE6 60
	+#define CLK_CORE7 61
	+#define CLK_SCU 62
	+#define CLK_ACE 63
	+#define CLK_AXI_PERIPH 64
	+#define CLK_AXI_ACP 65
	+#define CLK_ATB 66
	+#define CLK_DEBUG_APB 67
	+#define CLK_GIC 68
	+#define CLK_PERIPH 69
	+#define CLK_AON_CLK_NUM (CLK_VSP + 1)
	+
	+#define CLK_OTG_EB 0
	+#define CLK_DMA_EB 1
	+#define CLK_CE_EB 2
	+#define CLK_NANDC_EB 3
	+#define CLK_SDIO0_EB 4
	+#define CLK_SDIO1_EB 5
	+#define CLK_SDIO2_EB 6
	+#define CLK_EMMC_EB 7
	+#define CLK_EMMC_32K_EB 8
	+#define CLK_SDIO0_32K_EB 9
	+#define CLK_SDIO1_32K_EB 10
	+#define CLK_SDIO2_32K_EB 11
	+#define CLK_NANDC_26M_EB 12
	+#define CLK_DMA_EB2 13
	+#define CLK_CE_EB2 14
	+#define CLK_AP_AHB_GATE_NUM (CLK_CE_EB2 + 1)
	+
	+#define CLK_GPIO_EB 0
	+#define CLK_PWM0_EB 1
	+#define CLK_PWM1_EB 2
	+#define CLK_PWM2_EB 3
	+#define CLK_PWM3_EB 4
	+#define CLK_KPD_EB 5
	+#define CLK_AON_SYST_EB 6
	+#define CLK_AP_SYST_EB 7
	+#define CLK_AON_TMR_EB 8
	+#define CLK_EFUSE_EB 9
	+#define CLK_EIC_EB 10
	+#define CLK_INTC_EB 11
	+#define CLK_ADI_EB 12
	+#define CLK_AUDIF_EB 13
	+#define CLK_AUD_EB 14
	+#define CLK_VBC_EB 15
	+#define CLK_PIN_EB 16
	+#define CLK_AP_WDG_EB 17
	+#define CLK_MM_EB 18
	+#define CLK_AON_APB_CKG_EB 19
	+#define CLK_CA53_TS0_EB 20
	+#define CLK_CA53_TS1_EB 21
	+#define CLK_CS53_DAP_EB 22
	+#define CLK_PMU_EB 23
	+#define CLK_THM_EB 24
	+#define CLK_AUX0_EB 25
	+#define CLK_AUX1_EB 26
	+#define CLK_AUX2_EB 27
	+#define CLK_PROBE_EB 28
	+#define CLK_EMC_REF_EB 29
	+#define CLK_CA53_WDG_EB 30
	+#define CLK_AP_TMR1_EB 31
	+#define CLK_AP_TMR2_EB 32
	+#define CLK_DISP_EMC_EB 33
	+#define CLK_ZIP_EMC_EB 34
	+#define CLK_GSP_EMC_EB 35
	+#define CLK_MM_VSP_EB 36
	+#define CLK_MDAR_EB 37
	+#define CLK_RTC4M0_CAL_EB 38
	+#define CLK_RTC4M1_CAL_EB 39
	+#define CLK_DJTAG_EB 40
	+#define CLK_MBOX_EB 41
	+#define CLK_AON_DMA_EB 42
	+#define CLK_AON_APB_DEF_EB 43
	+#define CLK_CA5_TS0_EB 44
	+#define CLK_DBG_EB 45
	+#define CLK_DBG_EMC_EB 46
	+#define CLK_CROSS_TRIG_EB 47
	+#define CLK_SERDES_DPHY_EB 48
	+#define CLK_ARCH_RTC_EB 49
	+#define CLK_KPD_RTC_EB 50
	+#define CLK_AON_SYST_RTC_EB 51
	+#define CLK_AP_SYST_RTC_EB 52
	+#define CLK_AON_TMR_RTC_EB 53
	+#define CLK_AP_TMR0_RTC_EB 54
	+#define CLK_EIC_RTC_EB 55
	+#define CLK_EIC_RTCDV5_EB 56
	+#define CLK_AP_WDG_RTC_EB 57
	+#define CLK_CA53_WDG_RTC_EB 58
	+#define CLK_THM_RTC_EB 59
	+#define CLK_ATHMA_RTC_EB 60
	+#define CLK_GTHMA_RTC_EB 61
	+#define CLK_ATHMA_RTC_A_EB 62
	+#define CLK_GTHMA_RTC_A_EB 63
	+#define CLK_AP_TMR1_RTC_EB 64
	+#define CLK_AP_TMR2_RTC_EB 65
	+#define CLK_DXCO_LC_RTC_EB 66
	+#define CLK_BB_CAL_RTC_EB 67
	+#define CLK_GNU_EB 68
	+#define CLK_DISP_EB 69
	+#define CLK_MM_EMC_EB 70
	+#define CLK_POWER_CPU_EB 71
	+#define CLK_HW_I2C_EB 72
	+#define CLK_MM_VSP_EMC_EB 73
	+#define CLK_VSP_EB 74
	+#define CLK_CSSYS_EB 75
	+#define CLK_DMC_EB 76
	+#define CLK_ROSC_EB 77
	+#define CLK_S_D_CFG_EB 78
	+#define CLK_S_D_REF_EB 79
	+#define CLK_B_DMA_EB 80
	+#define CLK_ANLG_EB 81
	+#define CLK_ANLG_APB_EB 82
	+#define CLK_BSMTMR_EB 83
	+#define CLK_AP_AXI_EB 84
	+#define CLK_AP_INTC0_EB 85
	+#define CLK_AP_INTC1_EB 86
	+#define CLK_AP_INTC2_EB 87
	+#define CLK_AP_INTC3_EB 88
	+#define CLK_AP_INTC4_EB 89
	+#define CLK_AP_INTC5_EB 90
	+#define CLK_SCC_EB 91
	+#define CLK_DPHY_CFG_EB 92
	+#define CLK_DPHY_REF_EB 93
	+#define CLK_CPHY_CFG_EB 94
	+#define CLK_OTG_REF_EB 95
	+#define CLK_SERDES_EB 96
	+#define CLK_AON_AP_EMC_EB 97
	+#define CLK_AON_APB_GATE_NUM (CLK_AON_AP_EMC_EB + 1)
	+
	+#define CLK_MAHB_CKG_EB 0
	+#define CLK_MDCAM_EB 1
	+#define CLK_MISP_EB 2
	+#define CLK_MAHBCSI_EB 3
	+#define CLK_MCSI_S_EB 4
	+#define CLK_MCSI_T_EB 5
	+#define CLK_DCAM_AXI_EB 6
	+#define CLK_ISP_AXI_EB 7
	+#define CLK_MCSI_EB 8
	+#define CLK_MCSI_S_CKG_EB 9
	+#define CLK_MCSI_T_CKG_EB 10
	+#define CLK_SENSOR0_EB 11
	+#define CLK_SENSOR1_EB 12
	+#define CLK_SENSOR2_EB 13
	+#define CLK_MCPHY_CFG_EB 14
	+#define CLK_MM_GATE_NUM (CLK_MCPHY_CFG_EB + 1)
	+
	+#define CLK_SIM0_EB 0
	+#define CLK_IIS0_EB 1
	+#define CLK_IIS1_EB 2
	+#define CLK_IIS2_EB 3
	+#define CLK_SPI0_EB 4
	+#define CLK_SPI1_EB 5
	+#define CLK_SPI2_EB 6
	+#define CLK_I2C0_EB 7
	+#define CLK_I2C1_EB 8
	+#define CLK_I2C2_EB 9
	+#define CLK_I2C3_EB 10
	+#define CLK_I2C4_EB 11
	+#define CLK_UART0_EB 12
	+#define CLK_UART1_EB 13
	+#define CLK_UART2_EB 14
	+#define CLK_UART3_EB 15
	+#define CLK_UART4_EB 16
	+#define CLK_SIM0_32K_EB 17
	+#define CLK_SPI3_EB 18
	+#define CLK_I2C5_EB 19
	+#define CLK_I2C6_EB 20
	+#define CLK_AP_APB_GATE_NUM (CLK_I2C6_EB + 1)
	+
	+#endif /* _DT_BINDINGS_CLK_SC9863A_H_ */
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun50i-a64-ccu.h b/sys/gnu/dts/include/dt-bindings/clock/sun50i-a64-ccu.h
	index e512a1c9b0fc..318eb15c414c 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/sun50i-a64-ccu.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/sun50i-a64-ccu.h
	@@ -1,138 +1,138 @@
	/*
	* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
	#define _DT_BINDINGS_CLK_SUN50I_A64_H_

	#define CLK_PLL_VIDEO0 7
	#define CLK_PLL_PERIPH0 11

	#define CLK_CPUX 21
	#define CLK_BUS_MIPI_DSI 28
	#define CLK_BUS_CE 29
	#define CLK_BUS_DMA 30
	#define CLK_BUS_MMC0 31
	#define CLK_BUS_MMC1 32
	#define CLK_BUS_MMC2 33
	#define CLK_BUS_NAND 34
	#define CLK_BUS_DRAM 35
	#define CLK_BUS_EMAC 36
	#define CLK_BUS_TS 37
	#define CLK_BUS_HSTIMER 38
	#define CLK_BUS_SPI0 39
	#define CLK_BUS_SPI1 40
	#define CLK_BUS_OTG 41
	#define CLK_BUS_EHCI0 42
	#define CLK_BUS_EHCI1 43
	#define CLK_BUS_OHCI0 44
	#define CLK_BUS_OHCI1 45
	#define CLK_BUS_VE 46
	#define CLK_BUS_TCON0 47
	#define CLK_BUS_TCON1 48
	#define CLK_BUS_DEINTERLACE 49
	#define CLK_BUS_CSI 50
	#define CLK_BUS_HDMI 51
	#define CLK_BUS_DE 52
	#define CLK_BUS_GPU 53
	#define CLK_BUS_MSGBOX 54
	#define CLK_BUS_SPINLOCK 55
	#define CLK_BUS_CODEC 56
	#define CLK_BUS_SPDIF 57
	#define CLK_BUS_PIO 58
	#define CLK_BUS_THS 59
	#define CLK_BUS_I2S0 60
	#define CLK_BUS_I2S1 61
	#define CLK_BUS_I2S2 62
	#define CLK_BUS_I2C0 63
	#define CLK_BUS_I2C1 64
	#define CLK_BUS_I2C2 65
	#define CLK_BUS_SCR 66
	#define CLK_BUS_UART0 67
	#define CLK_BUS_UART1 68
	#define CLK_BUS_UART2 69
	#define CLK_BUS_UART3 70
	#define CLK_BUS_UART4 71
	#define CLK_BUS_DBG 72
	#define CLK_THS 73
	#define CLK_NAND 74
	#define CLK_MMC0 75
	#define CLK_MMC1 76
	#define CLK_MMC2 77
	#define CLK_TS 78
	#define CLK_CE 79
	#define CLK_SPI0 80
	#define CLK_SPI1 81
	#define CLK_I2S0 82
	#define CLK_I2S1 83
	#define CLK_I2S2 84
	#define CLK_SPDIF 85
	#define CLK_USB_PHY0 86
	#define CLK_USB_PHY1 87
	#define CLK_USB_HSIC 88
	#define CLK_USB_HSIC_12M 89

	#define CLK_USB_OHCI0 91

	#define CLK_USB_OHCI1 93

	#define CLK_DRAM_VE 95
	#define CLK_DRAM_CSI 96
	#define CLK_DRAM_DEINTERLACE 97
	#define CLK_DRAM_TS 98
	#define CLK_DE 99
	#define CLK_TCON0 100
	#define CLK_TCON1 101
	#define CLK_DEINTERLACE 102
	#define CLK_CSI_MISC 103
	#define CLK_CSI_SCLK 104
	#define CLK_CSI_MCLK 105
	#define CLK_VE 106
	#define CLK_AC_DIG 107
	#define CLK_AC_DIG_4X 108
	#define CLK_AVS 109
	#define CLK_HDMI 110
	#define CLK_HDMI_DDC 111
	-
	+#define CLK_MBUS 112
	#define CLK_DSI_DPHY 113
	#define CLK_GPU 114

	#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/tegra114-car.h b/sys/gnu/dts/include/dt-bindings/clock/tegra114-car.h
	index bb5c2c999c05..df59aaf5bf34 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/tegra114-car.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/tegra114-car.h
	@@ -1,344 +1,346 @@
	/* SPDX-License-Identifier: GPL-2.0 */
	/*
	* This header provides constants for binding nvidia,tegra114-car.
	*
	* The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
	* registers. These IDs often match those in the CAR's RST_DEVICES registers,
	* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
	* this case, those clocks are assigned IDs above 160 in order to highlight
	* this issue. Implementations that interpret these clock IDs as bit values
	* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
	* explicitly handle these special cases.
	*
	* The balance of the clocks controlled by the CAR are assigned IDs of 160 and
	* above.
	*/

	#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
	#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H

	/* 0 */
	/* 1 */
	/* 2 */
	/* 3 */
	#define TEGRA114_CLK_RTC 4
	#define TEGRA114_CLK_TIMER 5
	#define TEGRA114_CLK_UARTA 6
	/* 7 (register bit affects uartb and vfir) */
	/* 8 */
	#define TEGRA114_CLK_SDMMC2 9
	/* 10 (register bit affects spdif_in and spdif_out) */
	#define TEGRA114_CLK_I2S1 11
	#define TEGRA114_CLK_I2C1 12
	#define TEGRA114_CLK_NDFLASH 13
	#define TEGRA114_CLK_SDMMC1 14
	#define TEGRA114_CLK_SDMMC4 15
	/* 16 */
	#define TEGRA114_CLK_PWM 17
	#define TEGRA114_CLK_I2S2 18
	#define TEGRA114_CLK_EPP 19
	/* 20 (register bit affects vi and vi_sensor) */
	#define TEGRA114_CLK_GR2D 21
	#define TEGRA114_CLK_USBD 22
	#define TEGRA114_CLK_ISP 23
	#define TEGRA114_CLK_GR3D 24
	/* 25 */
	#define TEGRA114_CLK_DISP2 26
	#define TEGRA114_CLK_DISP1 27
	#define TEGRA114_CLK_HOST1X 28
	#define TEGRA114_CLK_VCP 29
	#define TEGRA114_CLK_I2S0 30
	/* 31 */

	#define TEGRA114_CLK_MC 32
	/* 33 */
	#define TEGRA114_CLK_APBDMA 34
	/* 35 */
	#define TEGRA114_CLK_KBC 36
	/* 37 */
	/* 38 */
	/* 39 (register bit affects fuse and fuse_burn) */
	#define TEGRA114_CLK_KFUSE 40
	#define TEGRA114_CLK_SBC1 41
	#define TEGRA114_CLK_NOR 42
	/* 43 */
	#define TEGRA114_CLK_SBC2 44
	/* 45 */
	#define TEGRA114_CLK_SBC3 46
	#define TEGRA114_CLK_I2C5 47
	#define TEGRA114_CLK_DSIA 48
	/* 49 */
	#define TEGRA114_CLK_MIPI 50
	#define TEGRA114_CLK_HDMI 51
	#define TEGRA114_CLK_CSI 52
	/* 53 */
	#define TEGRA114_CLK_I2C2 54
	#define TEGRA114_CLK_UARTC 55
	#define TEGRA114_CLK_MIPI_CAL 56
	#define TEGRA114_CLK_EMC 57
	#define TEGRA114_CLK_USB2 58
	#define TEGRA114_CLK_USB3 59
	/* 60 */
	#define TEGRA114_CLK_VDE 61
	#define TEGRA114_CLK_BSEA 62
	#define TEGRA114_CLK_BSEV 63

	/* 64 */
	#define TEGRA114_CLK_UARTD 65
	/* 66 */
	#define TEGRA114_CLK_I2C3 67
	#define TEGRA114_CLK_SBC4 68
	#define TEGRA114_CLK_SDMMC3 69
	/* 70 */
	#define TEGRA114_CLK_OWR 71
	/* 72 */
	#define TEGRA114_CLK_CSITE 73
	/* 74 */
	/* 75 */
	#define TEGRA114_CLK_LA 76
	#define TEGRA114_CLK_TRACE 77
	#define TEGRA114_CLK_SOC_THERM 78
	#define TEGRA114_CLK_DTV 79
	#define TEGRA114_CLK_NDSPEED 80
	#define TEGRA114_CLK_I2CSLOW 81
	#define TEGRA114_CLK_DSIB 82
	#define TEGRA114_CLK_TSEC 83
	/* 84 */
	/* 85 */
	/* 86 */
	/* 87 */
	/* 88 */
	#define TEGRA114_CLK_XUSB_HOST 89
	/* 90 */
	#define TEGRA114_CLK_MSENC 91
	#define TEGRA114_CLK_CSUS 92
	/* 93 */
	/* 94 */
	/* 95 (bit affects xusb_dev and xusb_dev_src) */

	/* 96 */
	/* 97 */
	/* 98 */
	#define TEGRA114_CLK_MSELECT 99
	#define TEGRA114_CLK_TSENSOR 100
	#define TEGRA114_CLK_I2S3 101
	#define TEGRA114_CLK_I2S4 102
	#define TEGRA114_CLK_I2C4 103
	#define TEGRA114_CLK_SBC5 104
	#define TEGRA114_CLK_SBC6 105
	#define TEGRA114_CLK_D_AUDIO 106
	#define TEGRA114_CLK_APBIF 107
	#define TEGRA114_CLK_DAM0 108
	#define TEGRA114_CLK_DAM1 109
	#define TEGRA114_CLK_DAM2 110
	#define TEGRA114_CLK_HDA2CODEC_2X 111
	/* 112 */
	#define TEGRA114_CLK_AUDIO0_2X 113
	#define TEGRA114_CLK_AUDIO1_2X 114
	#define TEGRA114_CLK_AUDIO2_2X 115
	#define TEGRA114_CLK_AUDIO3_2X 116
	#define TEGRA114_CLK_AUDIO4_2X 117
	#define TEGRA114_CLK_SPDIF_2X 118
	#define TEGRA114_CLK_ACTMON 119
	#define TEGRA114_CLK_EXTERN1 120
	#define TEGRA114_CLK_EXTERN2 121
	#define TEGRA114_CLK_EXTERN3 122
	/* 123 */
	/* 124 */
	#define TEGRA114_CLK_HDA 125
	/* 126 */
	#define TEGRA114_CLK_SE 127

	#define TEGRA114_CLK_HDA2HDMI 128
	/* 129 */
	/* 130 */
	/* 131 */
	/* 132 */
	/* 133 */
	/* 134 */
	/* 135 */
	#define TEGRA114_CLK_CEC 136
	/* 137 */
	/* 138 */
	/* 139 */
	/* 140 */
	/* 141 */
	/* 142 */
	/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
	/* xusb_host_src and xusb_ss_src) */
	#define TEGRA114_CLK_CILAB 144
	#define TEGRA114_CLK_CILCD 145
	#define TEGRA114_CLK_CILE 146
	#define TEGRA114_CLK_DSIALP 147
	#define TEGRA114_CLK_DSIBLP 148
	/* 149 */
	#define TEGRA114_CLK_DDS 150
	/* 151 */
	#define TEGRA114_CLK_DP2 152
	#define TEGRA114_CLK_AMX 153
	#define TEGRA114_CLK_ADX 154
	/* 155 (bit affects dfll_ref and dfll_soc) */
	#define TEGRA114_CLK_XUSB_SS 156
	/* 157 */
	/* 158 */
	/* 159 */

	/* 160 */
	/* 161 */
	/* 162 */
	/* 163 */
	/* 164 */
	/* 165 */
	/* 166 */
	/* 167 */
	/* 168 */
	/* 169 */
	/* 170 */
	/* 171 */
	/* 172 */
	/* 173 */
	/* 174 */
	/* 175 */
	/* 176 */
	/* 177 */
	/* 178 */
	/* 179 */
	/* 180 */
	/* 181 */
	/* 182 */
	/* 183 */
	/* 184 */
	/* 185 */
	/* 186 */
	/* 187 */
	/* 188 */
	/* 189 */
	/* 190 */
	/* 191 */

	#define TEGRA114_CLK_UARTB 192
	#define TEGRA114_CLK_VFIR 193
	#define TEGRA114_CLK_SPDIF_IN 194
	#define TEGRA114_CLK_SPDIF_OUT 195
	#define TEGRA114_CLK_VI 196
	#define TEGRA114_CLK_VI_SENSOR 197
	#define TEGRA114_CLK_FUSE 198
	#define TEGRA114_CLK_FUSE_BURN 199
	#define TEGRA114_CLK_CLK_32K 200
	#define TEGRA114_CLK_CLK_M 201
	#define TEGRA114_CLK_CLK_M_DIV2 202
	#define TEGRA114_CLK_CLK_M_DIV4 203
	+#define TEGRA114_CLK_OSC_DIV2 202
	+#define TEGRA114_CLK_OSC_DIV4 203
	#define TEGRA114_CLK_PLL_REF 204
	#define TEGRA114_CLK_PLL_C 205
	#define TEGRA114_CLK_PLL_C_OUT1 206
	#define TEGRA114_CLK_PLL_C2 207
	#define TEGRA114_CLK_PLL_C3 208
	#define TEGRA114_CLK_PLL_M 209
	#define TEGRA114_CLK_PLL_M_OUT1 210
	#define TEGRA114_CLK_PLL_P 211
	#define TEGRA114_CLK_PLL_P_OUT1 212
	#define TEGRA114_CLK_PLL_P_OUT2 213
	#define TEGRA114_CLK_PLL_P_OUT3 214
	#define TEGRA114_CLK_PLL_P_OUT4 215
	#define TEGRA114_CLK_PLL_A 216
	#define TEGRA114_CLK_PLL_A_OUT0 217
	#define TEGRA114_CLK_PLL_D 218
	#define TEGRA114_CLK_PLL_D_OUT0 219
	#define TEGRA114_CLK_PLL_D2 220
	#define TEGRA114_CLK_PLL_D2_OUT0 221
	#define TEGRA114_CLK_PLL_U 222
	#define TEGRA114_CLK_PLL_U_480M 223

	#define TEGRA114_CLK_PLL_U_60M 224
	#define TEGRA114_CLK_PLL_U_48M 225
	#define TEGRA114_CLK_PLL_U_12M 226
	#define TEGRA114_CLK_PLL_X 227
	#define TEGRA114_CLK_PLL_X_OUT0 228
	#define TEGRA114_CLK_PLL_RE_VCO 229
	#define TEGRA114_CLK_PLL_RE_OUT 230
	#define TEGRA114_CLK_PLL_E_OUT0 231
	#define TEGRA114_CLK_SPDIF_IN_SYNC 232
	#define TEGRA114_CLK_I2S0_SYNC 233
	#define TEGRA114_CLK_I2S1_SYNC 234
	#define TEGRA114_CLK_I2S2_SYNC 235
	#define TEGRA114_CLK_I2S3_SYNC 236
	#define TEGRA114_CLK_I2S4_SYNC 237
	#define TEGRA114_CLK_VIMCLK_SYNC 238
	#define TEGRA114_CLK_AUDIO0 239
	#define TEGRA114_CLK_AUDIO1 240
	#define TEGRA114_CLK_AUDIO2 241
	#define TEGRA114_CLK_AUDIO3 242
	#define TEGRA114_CLK_AUDIO4 243
	#define TEGRA114_CLK_SPDIF 244
	#define TEGRA114_CLK_CLK_OUT_1 245
	#define TEGRA114_CLK_CLK_OUT_2 246
	#define TEGRA114_CLK_CLK_OUT_3 247
	#define TEGRA114_CLK_BLINK 248
	-/* 249 */
	+#define TEGRA114_CLK_OSC 249
	/* 250 */
	/* 251 */
	#define TEGRA114_CLK_XUSB_HOST_SRC 252
	#define TEGRA114_CLK_XUSB_FALCON_SRC 253
	#define TEGRA114_CLK_XUSB_FS_SRC 254
	#define TEGRA114_CLK_XUSB_SS_SRC 255

	#define TEGRA114_CLK_XUSB_DEV_SRC 256
	#define TEGRA114_CLK_XUSB_DEV 257
	#define TEGRA114_CLK_XUSB_HS_SRC 258
	#define TEGRA114_CLK_SCLK 259
	#define TEGRA114_CLK_HCLK 260
	#define TEGRA114_CLK_PCLK 261
	#define TEGRA114_CLK_CCLK_G 262
	#define TEGRA114_CLK_CCLK_LP 263
	#define TEGRA114_CLK_DFLL_REF 264
	#define TEGRA114_CLK_DFLL_SOC 265
	/* 266 */
	/* 267 */
	/* 268 */
	/* 269 */
	/* 270 */
	/* 271 */
	/* 272 */
	/* 273 */
	/* 274 */
	/* 275 */
	/* 276 */
	/* 277 */
	/* 278 */
	/* 279 */
	/* 280 */
	/* 281 */
	/* 282 */
	/* 283 */
	/* 284 */
	/* 285 */
	/* 286 */
	/* 287 */

	/* 288 */
	/* 289 */
	/* 290 */
	/* 291 */
	/* 292 */
	/* 293 */
	/* 294 */
	/* 295 */
	/* 296 */
	/* 297 */
	/* 298 */
	/* 299 */
	#define TEGRA114_CLK_AUDIO0_MUX 300
	#define TEGRA114_CLK_AUDIO1_MUX 301
	#define TEGRA114_CLK_AUDIO2_MUX 302
	#define TEGRA114_CLK_AUDIO3_MUX 303
	#define TEGRA114_CLK_AUDIO4_MUX 304
	#define TEGRA114_CLK_SPDIF_MUX 305
	#define TEGRA114_CLK_CLK_OUT_1_MUX 306
	#define TEGRA114_CLK_CLK_OUT_2_MUX 307
	#define TEGRA114_CLK_CLK_OUT_3_MUX 308
	#define TEGRA114_CLK_DSIA_MUX 309
	#define TEGRA114_CLK_DSIB_MUX 310
	#define TEGRA114_CLK_XUSB_SS_DIV2 311
	#define TEGRA114_CLK_CLK_MAX 312

	#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/tegra124-car-common.h b/sys/gnu/dts/include/dt-bindings/clock/tegra124-car-common.h
	index 0c4f5be0a742..2a9acd592bff 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/tegra124-car-common.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/tegra124-car-common.h
	@@ -1,347 +1,349 @@
	/* SPDX-License-Identifier: GPL-2.0 */
	/*
	* This header provides constants for binding nvidia,tegra124-car or
	* nvidia,tegra132-car.
	*
	* The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
	* registers. These IDs often match those in the CAR's RST_DEVICES registers,
	* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
	* this case, those clocks are assigned IDs above 185 in order to highlight
	* this issue. Implementations that interpret these clock IDs as bit values
	* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
	* explicitly handle these special cases.
	*
	* The balance of the clocks controlled by the CAR are assigned IDs of 185 and
	* above.
	*/

	#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
	#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H

	/* 0 */
	/* 1 */
	/* 2 */
	#define TEGRA124_CLK_ISPB 3
	#define TEGRA124_CLK_RTC 4
	#define TEGRA124_CLK_TIMER 5
	#define TEGRA124_CLK_UARTA 6
	/* 7 (register bit affects uartb and vfir) */
	/* 8 */
	#define TEGRA124_CLK_SDMMC2 9
	/* 10 (register bit affects spdif_in and spdif_out) */
	#define TEGRA124_CLK_I2S1 11
	#define TEGRA124_CLK_I2C1 12
	/* 13 */
	#define TEGRA124_CLK_SDMMC1 14
	#define TEGRA124_CLK_SDMMC4 15
	/* 16 */
	#define TEGRA124_CLK_PWM 17
	#define TEGRA124_CLK_I2S2 18
	/* 20 (register bit affects vi and vi_sensor) */
	/* 21 */
	#define TEGRA124_CLK_USBD 22
	#define TEGRA124_CLK_ISP 23
	/* 26 */
	/* 25 */
	#define TEGRA124_CLK_DISP2 26
	#define TEGRA124_CLK_DISP1 27
	#define TEGRA124_CLK_HOST1X 28
	#define TEGRA124_CLK_VCP 29
	#define TEGRA124_CLK_I2S0 30
	/* 31 */

	#define TEGRA124_CLK_MC 32
	/* 33 */
	#define TEGRA124_CLK_APBDMA 34
	/* 35 */
	#define TEGRA124_CLK_KBC 36
	/* 37 */
	/* 38 */
	/* 39 (register bit affects fuse and fuse_burn) */
	#define TEGRA124_CLK_KFUSE 40
	#define TEGRA124_CLK_SBC1 41
	#define TEGRA124_CLK_NOR 42
	/* 43 */
	#define TEGRA124_CLK_SBC2 44
	/* 45 */
	#define TEGRA124_CLK_SBC3 46
	#define TEGRA124_CLK_I2C5 47
	#define TEGRA124_CLK_DSIA 48
	/* 49 */
	#define TEGRA124_CLK_MIPI 50
	#define TEGRA124_CLK_HDMI 51
	#define TEGRA124_CLK_CSI 52
	/* 53 */
	#define TEGRA124_CLK_I2C2 54
	#define TEGRA124_CLK_UARTC 55
	#define TEGRA124_CLK_MIPI_CAL 56
	#define TEGRA124_CLK_EMC 57
	#define TEGRA124_CLK_USB2 58
	#define TEGRA124_CLK_USB3 59
	/* 60 */
	#define TEGRA124_CLK_VDE 61
	#define TEGRA124_CLK_BSEA 62
	#define TEGRA124_CLK_BSEV 63

	/* 64 */
	#define TEGRA124_CLK_UARTD 65
	/* 66 */
	#define TEGRA124_CLK_I2C3 67
	#define TEGRA124_CLK_SBC4 68
	#define TEGRA124_CLK_SDMMC3 69
	#define TEGRA124_CLK_PCIE 70
	#define TEGRA124_CLK_OWR 71
	#define TEGRA124_CLK_AFI 72
	#define TEGRA124_CLK_CSITE 73
	/* 74 */
	/* 75 */
	#define TEGRA124_CLK_LA 76
	#define TEGRA124_CLK_TRACE 77
	#define TEGRA124_CLK_SOC_THERM 78
	#define TEGRA124_CLK_DTV 79
	/* 80 */
	#define TEGRA124_CLK_I2CSLOW 81
	#define TEGRA124_CLK_DSIB 82
	#define TEGRA124_CLK_TSEC 83
	/* 84 */
	/* 85 */
	/* 86 */
	/* 87 */
	/* 88 */
	#define TEGRA124_CLK_XUSB_HOST 89
	/* 90 */
	#define TEGRA124_CLK_MSENC 91
	#define TEGRA124_CLK_CSUS 92
	/* 93 */
	/* 94 */
	/* 95 (bit affects xusb_dev and xusb_dev_src) */

	/* 96 */
	/* 97 */
	/* 98 */
	#define TEGRA124_CLK_MSELECT 99
	#define TEGRA124_CLK_TSENSOR 100
	#define TEGRA124_CLK_I2S3 101
	#define TEGRA124_CLK_I2S4 102
	#define TEGRA124_CLK_I2C4 103
	#define TEGRA124_CLK_SBC5 104
	#define TEGRA124_CLK_SBC6 105
	#define TEGRA124_CLK_D_AUDIO 106
	#define TEGRA124_CLK_APBIF 107
	#define TEGRA124_CLK_DAM0 108
	#define TEGRA124_CLK_DAM1 109
	#define TEGRA124_CLK_DAM2 110
	#define TEGRA124_CLK_HDA2CODEC_2X 111
	/* 112 */
	#define TEGRA124_CLK_AUDIO0_2X 113
	#define TEGRA124_CLK_AUDIO1_2X 114
	#define TEGRA124_CLK_AUDIO2_2X 115
	#define TEGRA124_CLK_AUDIO3_2X 116
	#define TEGRA124_CLK_AUDIO4_2X 117
	#define TEGRA124_CLK_SPDIF_2X 118
	#define TEGRA124_CLK_ACTMON 119
	#define TEGRA124_CLK_EXTERN1 120
	#define TEGRA124_CLK_EXTERN2 121
	#define TEGRA124_CLK_EXTERN3 122
	#define TEGRA124_CLK_SATA_OOB 123
	#define TEGRA124_CLK_SATA 124
	#define TEGRA124_CLK_HDA 125
	/* 126 */
	#define TEGRA124_CLK_SE 127

	#define TEGRA124_CLK_HDA2HDMI 128
	#define TEGRA124_CLK_SATA_COLD 129
	/* 130 */
	/* 131 */
	/* 132 */
	/* 133 */
	/* 134 */
	/* 135 */
	#define TEGRA124_CLK_CEC 136
	/* 137 */
	/* 138 */
	/* 139 */
	/* 140 */
	/* 141 */
	/* 142 */
	/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
	/* xusb_host_src and xusb_ss_src) */
	#define TEGRA124_CLK_CILAB 144
	#define TEGRA124_CLK_CILCD 145
	#define TEGRA124_CLK_CILE 146
	#define TEGRA124_CLK_DSIALP 147
	#define TEGRA124_CLK_DSIBLP 148
	#define TEGRA124_CLK_ENTROPY 149
	#define TEGRA124_CLK_DDS 150
	/* 151 */
	#define TEGRA124_CLK_DP2 152
	#define TEGRA124_CLK_AMX 153
	#define TEGRA124_CLK_ADX 154
	/* 155 (bit affects dfll_ref and dfll_soc) */
	#define TEGRA124_CLK_XUSB_SS 156
	/* 157 */
	/* 158 */
	/* 159 */

	/* 160 */
	/* 161 */
	/* 162 */
	/* 163 */
	/* 164 */
	/* 165 */
	#define TEGRA124_CLK_I2C6 166
	/* 167 */
	/* 168 */
	/* 169 */
	/* 170 */
	#define TEGRA124_CLK_VIM2_CLK 171
	/* 172 */
	/* 173 */
	/* 174 */
	/* 175 */
	#define TEGRA124_CLK_HDMI_AUDIO 176
	#define TEGRA124_CLK_CLK72MHZ 177
	#define TEGRA124_CLK_VIC03 178
	/* 179 */
	#define TEGRA124_CLK_ADX1 180
	#define TEGRA124_CLK_DPAUX 181
	#define TEGRA124_CLK_SOR0 182
	/* 183 */
	#define TEGRA124_CLK_GPU 184
	#define TEGRA124_CLK_AMX1 185
	/* 186 */
	/* 187 */
	/* 188 */
	/* 189 */
	/* 190 */
	/* 191 */
	#define TEGRA124_CLK_UARTB 192
	#define TEGRA124_CLK_VFIR 193
	#define TEGRA124_CLK_SPDIF_IN 194
	#define TEGRA124_CLK_SPDIF_OUT 195
	#define TEGRA124_CLK_VI 196
	#define TEGRA124_CLK_VI_SENSOR 197
	#define TEGRA124_CLK_FUSE 198
	#define TEGRA124_CLK_FUSE_BURN 199
	#define TEGRA124_CLK_CLK_32K 200
	#define TEGRA124_CLK_CLK_M 201
	#define TEGRA124_CLK_CLK_M_DIV2 202
	#define TEGRA124_CLK_CLK_M_DIV4 203
	+#define TEGRA124_CLK_OSC_DIV2 202
	+#define TEGRA124_CLK_OSC_DIV4 203
	#define TEGRA124_CLK_PLL_REF 204
	#define TEGRA124_CLK_PLL_C 205
	#define TEGRA124_CLK_PLL_C_OUT1 206
	#define TEGRA124_CLK_PLL_C2 207
	#define TEGRA124_CLK_PLL_C3 208
	#define TEGRA124_CLK_PLL_M 209
	#define TEGRA124_CLK_PLL_M_OUT1 210
	#define TEGRA124_CLK_PLL_P 211
	#define TEGRA124_CLK_PLL_P_OUT1 212
	#define TEGRA124_CLK_PLL_P_OUT2 213
	#define TEGRA124_CLK_PLL_P_OUT3 214
	#define TEGRA124_CLK_PLL_P_OUT4 215
	#define TEGRA124_CLK_PLL_A 216
	#define TEGRA124_CLK_PLL_A_OUT0 217
	#define TEGRA124_CLK_PLL_D 218
	#define TEGRA124_CLK_PLL_D_OUT0 219
	#define TEGRA124_CLK_PLL_D2 220
	#define TEGRA124_CLK_PLL_D2_OUT0 221
	#define TEGRA124_CLK_PLL_U 222
	#define TEGRA124_CLK_PLL_U_480M 223

	#define TEGRA124_CLK_PLL_U_60M 224
	#define TEGRA124_CLK_PLL_U_48M 225
	#define TEGRA124_CLK_PLL_U_12M 226
	/* 227 */
	/* 228 */
	#define TEGRA124_CLK_PLL_RE_VCO 229
	#define TEGRA124_CLK_PLL_RE_OUT 230
	#define TEGRA124_CLK_PLL_E 231
	#define TEGRA124_CLK_SPDIF_IN_SYNC 232
	#define TEGRA124_CLK_I2S0_SYNC 233
	#define TEGRA124_CLK_I2S1_SYNC 234
	#define TEGRA124_CLK_I2S2_SYNC 235
	#define TEGRA124_CLK_I2S3_SYNC 236
	#define TEGRA124_CLK_I2S4_SYNC 237
	#define TEGRA124_CLK_VIMCLK_SYNC 238
	#define TEGRA124_CLK_AUDIO0 239
	#define TEGRA124_CLK_AUDIO1 240
	#define TEGRA124_CLK_AUDIO2 241
	#define TEGRA124_CLK_AUDIO3 242
	#define TEGRA124_CLK_AUDIO4 243
	#define TEGRA124_CLK_SPDIF 244
	#define TEGRA124_CLK_CLK_OUT_1 245
	#define TEGRA124_CLK_CLK_OUT_2 246
	#define TEGRA124_CLK_CLK_OUT_3 247
	#define TEGRA124_CLK_BLINK 248
	-/* 249 */
	+#define TEGRA124_CLK_OSC 249
	/* 250 */
	/* 251 */
	#define TEGRA124_CLK_XUSB_HOST_SRC 252
	#define TEGRA124_CLK_XUSB_FALCON_SRC 253
	#define TEGRA124_CLK_XUSB_FS_SRC 254
	#define TEGRA124_CLK_XUSB_SS_SRC 255

	#define TEGRA124_CLK_XUSB_DEV_SRC 256
	#define TEGRA124_CLK_XUSB_DEV 257
	#define TEGRA124_CLK_XUSB_HS_SRC 258
	#define TEGRA124_CLK_SCLK 259
	#define TEGRA124_CLK_HCLK 260
	#define TEGRA124_CLK_PCLK 261
	/* 262 */
	/* 263 */
	#define TEGRA124_CLK_DFLL_REF 264
	#define TEGRA124_CLK_DFLL_SOC 265
	#define TEGRA124_CLK_VI_SENSOR2 266
	#define TEGRA124_CLK_PLL_P_OUT5 267
	#define TEGRA124_CLK_CML0 268
	#define TEGRA124_CLK_CML1 269
	#define TEGRA124_CLK_PLL_C4 270
	#define TEGRA124_CLK_PLL_DP 271
	#define TEGRA124_CLK_PLL_E_MUX 272
	#define TEGRA124_CLK_PLL_D_DSI_OUT 273
	/* 274 */
	/* 275 */
	/* 276 */
	/* 277 */
	/* 278 */
	/* 279 */
	/* 280 */
	/* 281 */
	/* 282 */
	/* 283 */
	/* 284 */
	/* 285 */
	/* 286 */
	/* 287 */

	/* 288 */
	/* 289 */
	/* 290 */
	/* 291 */
	/* 292 */
	/* 293 */
	/* 294 */
	/* 295 */
	/* 296 */
	/* 297 */
	/* 298 */
	/* 299 */
	#define TEGRA124_CLK_AUDIO0_MUX 300
	#define TEGRA124_CLK_AUDIO1_MUX 301
	#define TEGRA124_CLK_AUDIO2_MUX 302
	#define TEGRA124_CLK_AUDIO3_MUX 303
	#define TEGRA124_CLK_AUDIO4_MUX 304
	#define TEGRA124_CLK_SPDIF_MUX 305
	#define TEGRA124_CLK_CLK_OUT_1_MUX 306
	#define TEGRA124_CLK_CLK_OUT_2_MUX 307
	#define TEGRA124_CLK_CLK_OUT_3_MUX 308
	/* 309 */
	/* 310 */
	#define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */
	#define TEGRA124_CLK_SOR0_OUT 311
	#define TEGRA124_CLK_XUSB_SS_DIV2 312

	#define TEGRA124_CLK_PLL_M_UD 313
	#define TEGRA124_CLK_PLL_C_UD 314

	#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/tegra210-car.h b/sys/gnu/dts/include/dt-bindings/clock/tegra210-car.h
	index 44f60623f99b..7a8f10b9a66d 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/tegra210-car.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/tegra210-car.h
	@@ -1,412 +1,414 @@
	/* SPDX-License-Identifier: GPL-2.0 */
	/*
	* This header provides constants for binding nvidia,tegra210-car.
	*
	* The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
	* registers. These IDs often match those in the CAR's RST_DEVICES registers,
	* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
	* this case, those clocks are assigned IDs above 224 in order to highlight
	* this issue. Implementations that interpret these clock IDs as bit values
	* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
	* explicitly handle these special cases.
	*
	* The balance of the clocks controlled by the CAR are assigned IDs of 224 and
	* above.
	*/

	#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
	#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H

	/* 0 */
	/* 1 */
	/* 2 */
	#define TEGRA210_CLK_ISPB 3
	#define TEGRA210_CLK_RTC 4
	#define TEGRA210_CLK_TIMER 5
	#define TEGRA210_CLK_UARTA 6
	/* 7 (register bit affects uartb and vfir) */
	#define TEGRA210_CLK_GPIO 8
	#define TEGRA210_CLK_SDMMC2 9
	/* 10 (register bit affects spdif_in and spdif_out) */
	#define TEGRA210_CLK_I2S1 11
	#define TEGRA210_CLK_I2C1 12
	/* 13 */
	#define TEGRA210_CLK_SDMMC1 14
	#define TEGRA210_CLK_SDMMC4 15
	/* 16 */
	#define TEGRA210_CLK_PWM 17
	#define TEGRA210_CLK_I2S2 18
	/* 19 */
	/* 20 (register bit affects vi and vi_sensor) */
	/* 21 */
	#define TEGRA210_CLK_USBD 22
	#define TEGRA210_CLK_ISPA 23
	/* 24 */
	/* 25 */
	#define TEGRA210_CLK_DISP2 26
	#define TEGRA210_CLK_DISP1 27
	#define TEGRA210_CLK_HOST1X 28
	/* 29 */
	#define TEGRA210_CLK_I2S0 30
	/* 31 */

	#define TEGRA210_CLK_MC 32
	#define TEGRA210_CLK_AHBDMA 33
	#define TEGRA210_CLK_APBDMA 34
	/* 35 */
	/* 36 */
	/* 37 */
	#define TEGRA210_CLK_PMC 38
	/* 39 (register bit affects fuse and fuse_burn) */
	#define TEGRA210_CLK_KFUSE 40
	#define TEGRA210_CLK_SBC1 41
	/* 42 */
	/* 43 */
	#define TEGRA210_CLK_SBC2 44
	/* 45 */
	#define TEGRA210_CLK_SBC3 46
	#define TEGRA210_CLK_I2C5 47
	#define TEGRA210_CLK_DSIA 48
	/* 49 */
	/* 50 */
	/* 51 */
	#define TEGRA210_CLK_CSI 52
	/* 53 */
	#define TEGRA210_CLK_I2C2 54
	#define TEGRA210_CLK_UARTC 55
	#define TEGRA210_CLK_MIPI_CAL 56
	#define TEGRA210_CLK_EMC 57
	#define TEGRA210_CLK_USB2 58
	/* 59 */
	/* 60 */
	/* 61 */
	/* 62 */
	#define TEGRA210_CLK_BSEV 63

	/* 64 */
	#define TEGRA210_CLK_UARTD 65
	/* 66 */
	#define TEGRA210_CLK_I2C3 67
	#define TEGRA210_CLK_SBC4 68
	#define TEGRA210_CLK_SDMMC3 69
	#define TEGRA210_CLK_PCIE 70
	#define TEGRA210_CLK_OWR 71
	#define TEGRA210_CLK_AFI 72
	#define TEGRA210_CLK_CSITE 73
	/* 74 */
	/* 75 */
	#define TEGRA210_CLK_LA 76
	/* 77 */
	#define TEGRA210_CLK_SOC_THERM 78
	#define TEGRA210_CLK_DTV 79
	/* 80 */
	#define TEGRA210_CLK_I2CSLOW 81
	#define TEGRA210_CLK_DSIB 82
	#define TEGRA210_CLK_TSEC 83
	/* 84 */
	/* 85 */
	/* 86 */
	/* 87 */
	/* 88 */
	#define TEGRA210_CLK_XUSB_HOST 89
	/* 90 */
	/* 91 */
	#define TEGRA210_CLK_CSUS 92
	/* 93 */
	/* 94 */
	/* 95 (bit affects xusb_dev and xusb_dev_src) */

	/* 96 */
	/* 97 */
	/* 98 */
	#define TEGRA210_CLK_MSELECT 99
	#define TEGRA210_CLK_TSENSOR 100
	#define TEGRA210_CLK_I2S3 101
	#define TEGRA210_CLK_I2S4 102
	#define TEGRA210_CLK_I2C4 103
	/* 104 */
	/* 105 */
	#define TEGRA210_CLK_D_AUDIO 106
	#define TEGRA210_CLK_APB2APE 107
	/* 108 */
	/* 109 */
	/* 110 */
	#define TEGRA210_CLK_HDA2CODEC_2X 111
	/* 112 */
	/* 113 */
	/* 114 */
	/* 115 */
	/* 116 */
	/* 117 */
	#define TEGRA210_CLK_SPDIF_2X 118
	#define TEGRA210_CLK_ACTMON 119
	#define TEGRA210_CLK_EXTERN1 120
	#define TEGRA210_CLK_EXTERN2 121
	#define TEGRA210_CLK_EXTERN3 122
	#define TEGRA210_CLK_SATA_OOB 123
	#define TEGRA210_CLK_SATA 124
	#define TEGRA210_CLK_HDA 125
	/* 126 */
	/* 127 */

	#define TEGRA210_CLK_HDA2HDMI 128
	/* 129 */
	/* 130 */
	/* 131 */
	/* 132 */
	/* 133 */
	/* 134 */
	/* 135 */
	#define TEGRA210_CLK_CEC 136
	/* 137 */
	/* 138 */
	/* 139 */
	/* 140 */
	/* 141 */
	/* 142 */
	/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */
	#define TEGRA210_CLK_XUSB_GATE 143
	#define TEGRA210_CLK_CILAB 144
	#define TEGRA210_CLK_CILCD 145
	#define TEGRA210_CLK_CILE 146
	#define TEGRA210_CLK_DSIALP 147
	#define TEGRA210_CLK_DSIBLP 148
	#define TEGRA210_CLK_ENTROPY 149
	/* 150 */
	/* 151 */
	#define TEGRA210_CLK_DP2 152
	/* 153 */
	/* 154 */
	/* 155 (bit affects dfll_ref and dfll_soc) */
	#define TEGRA210_CLK_XUSB_SS 156
	/* 157 */
	/* 158 */
	/* 159 */

	/* 160 */
	#define TEGRA210_CLK_DMIC1 161
	#define TEGRA210_CLK_DMIC2 162
	/* 163 */
	/* 164 */
	/* 165 */
	#define TEGRA210_CLK_I2C6 166
	/* 167 */
	/* 168 */
	/* 169 */
	/* 170 */
	#define TEGRA210_CLK_VIM2_CLK 171
	/* 172 */
	#define TEGRA210_CLK_MIPIBIF 173
	/* 174 */
	/* 175 */
	/* 176 */
	#define TEGRA210_CLK_CLK72MHZ 177
	#define TEGRA210_CLK_VIC03 178
	/* 179 */
	/* 180 */
	#define TEGRA210_CLK_DPAUX 181
	#define TEGRA210_CLK_SOR0 182
	#define TEGRA210_CLK_SOR1 183
	#define TEGRA210_CLK_GPU 184
	#define TEGRA210_CLK_DBGAPB 185
	/* 186 */
	#define TEGRA210_CLK_PLL_P_OUT_ADSP 187
	/* 188 ((bit affects pll_a_out_adsp and pll_a_out0_out_adsp)*/
	#define TEGRA210_CLK_PLL_G_REF 189
	/* 190 */
	/* 191 */

	/* 192 */
	#define TEGRA210_CLK_SDMMC_LEGACY 193
	#define TEGRA210_CLK_NVDEC 194
	#define TEGRA210_CLK_NVJPG 195
	/* 196 */
	#define TEGRA210_CLK_DMIC3 197
	#define TEGRA210_CLK_APE 198
	#define TEGRA210_CLK_ADSP 199
	/* 200 */
	/* 201 */
	#define TEGRA210_CLK_MAUD 202
	/* 203 */
	/* 204 */
	/* 205 */
	#define TEGRA210_CLK_TSECB 206
	#define TEGRA210_CLK_DPAUX1 207
	#define TEGRA210_CLK_VI_I2C 208
	#define TEGRA210_CLK_HSIC_TRK 209
	#define TEGRA210_CLK_USB2_TRK 210
	#define TEGRA210_CLK_QSPI 211
	#define TEGRA210_CLK_UARTAPE 212
	/* 213 */
	/* 214 */
	/* 215 */
	/* 216 */
	/* 217 */
	#define TEGRA210_CLK_ADSP_NEON 218
	#define TEGRA210_CLK_NVENC 219
	#define TEGRA210_CLK_IQC2 220
	#define TEGRA210_CLK_IQC1 221
	#define TEGRA210_CLK_SOR_SAFE 222
	#define TEGRA210_CLK_PLL_P_OUT_CPU 223


	#define TEGRA210_CLK_UARTB 224
	#define TEGRA210_CLK_VFIR 225
	#define TEGRA210_CLK_SPDIF_IN 226
	#define TEGRA210_CLK_SPDIF_OUT 227
	#define TEGRA210_CLK_VI 228
	#define TEGRA210_CLK_VI_SENSOR 229
	#define TEGRA210_CLK_FUSE 230
	#define TEGRA210_CLK_FUSE_BURN 231
	#define TEGRA210_CLK_CLK_32K 232
	#define TEGRA210_CLK_CLK_M 233
	#define TEGRA210_CLK_CLK_M_DIV2 234
	#define TEGRA210_CLK_CLK_M_DIV4 235
	+#define TEGRA210_CLK_OSC_DIV2 234
	+#define TEGRA210_CLK_OSC_DIV4 235
	#define TEGRA210_CLK_PLL_REF 236
	#define TEGRA210_CLK_PLL_C 237
	#define TEGRA210_CLK_PLL_C_OUT1 238
	#define TEGRA210_CLK_PLL_C2 239
	#define TEGRA210_CLK_PLL_C3 240
	#define TEGRA210_CLK_PLL_M 241
	#define TEGRA210_CLK_PLL_M_OUT1 242
	#define TEGRA210_CLK_PLL_P 243
	#define TEGRA210_CLK_PLL_P_OUT1 244
	#define TEGRA210_CLK_PLL_P_OUT2 245
	#define TEGRA210_CLK_PLL_P_OUT3 246
	#define TEGRA210_CLK_PLL_P_OUT4 247
	#define TEGRA210_CLK_PLL_A 248
	#define TEGRA210_CLK_PLL_A_OUT0 249
	#define TEGRA210_CLK_PLL_D 250
	#define TEGRA210_CLK_PLL_D_OUT0 251
	#define TEGRA210_CLK_PLL_D2 252
	#define TEGRA210_CLK_PLL_D2_OUT0 253
	#define TEGRA210_CLK_PLL_U 254
	#define TEGRA210_CLK_PLL_U_480M 255

	#define TEGRA210_CLK_PLL_U_60M 256
	#define TEGRA210_CLK_PLL_U_48M 257
	/* 258 */
	#define TEGRA210_CLK_PLL_X 259
	#define TEGRA210_CLK_PLL_X_OUT0 260
	#define TEGRA210_CLK_PLL_RE_VCO 261
	#define TEGRA210_CLK_PLL_RE_OUT 262
	#define TEGRA210_CLK_PLL_E 263
	#define TEGRA210_CLK_SPDIF_IN_SYNC 264
	#define TEGRA210_CLK_I2S0_SYNC 265
	#define TEGRA210_CLK_I2S1_SYNC 266
	#define TEGRA210_CLK_I2S2_SYNC 267
	#define TEGRA210_CLK_I2S3_SYNC 268
	#define TEGRA210_CLK_I2S4_SYNC 269
	#define TEGRA210_CLK_VIMCLK_SYNC 270
	#define TEGRA210_CLK_AUDIO0 271
	#define TEGRA210_CLK_AUDIO1 272
	#define TEGRA210_CLK_AUDIO2 273
	#define TEGRA210_CLK_AUDIO3 274
	#define TEGRA210_CLK_AUDIO4 275
	#define TEGRA210_CLK_SPDIF 276
	#define TEGRA210_CLK_CLK_OUT_1 277
	#define TEGRA210_CLK_CLK_OUT_2 278
	#define TEGRA210_CLK_CLK_OUT_3 279
	#define TEGRA210_CLK_BLINK 280
	#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */
	#define TEGRA210_CLK_SOR0_OUT 281
	#define TEGRA210_CLK_SOR1_OUT 282
	/* 283 */
	#define TEGRA210_CLK_XUSB_HOST_SRC 284
	#define TEGRA210_CLK_XUSB_FALCON_SRC 285
	#define TEGRA210_CLK_XUSB_FS_SRC 286
	#define TEGRA210_CLK_XUSB_SS_SRC 287

	#define TEGRA210_CLK_XUSB_DEV_SRC 288
	#define TEGRA210_CLK_XUSB_DEV 289
	#define TEGRA210_CLK_XUSB_HS_SRC 290
	#define TEGRA210_CLK_SCLK 291
	#define TEGRA210_CLK_HCLK 292
	#define TEGRA210_CLK_PCLK 293
	#define TEGRA210_CLK_CCLK_G 294
	#define TEGRA210_CLK_CCLK_LP 295
	#define TEGRA210_CLK_DFLL_REF 296
	#define TEGRA210_CLK_DFLL_SOC 297
	#define TEGRA210_CLK_VI_SENSOR2 298
	#define TEGRA210_CLK_PLL_P_OUT5 299
	#define TEGRA210_CLK_CML0 300
	#define TEGRA210_CLK_CML1 301
	#define TEGRA210_CLK_PLL_C4 302
	#define TEGRA210_CLK_PLL_DP 303
	#define TEGRA210_CLK_PLL_E_MUX 304
	#define TEGRA210_CLK_PLL_MB 305
	#define TEGRA210_CLK_PLL_A1 306
	#define TEGRA210_CLK_PLL_D_DSI_OUT 307
	#define TEGRA210_CLK_PLL_C4_OUT0 308
	#define TEGRA210_CLK_PLL_C4_OUT1 309
	#define TEGRA210_CLK_PLL_C4_OUT2 310
	#define TEGRA210_CLK_PLL_C4_OUT3 311
	#define TEGRA210_CLK_PLL_U_OUT 312
	#define TEGRA210_CLK_PLL_U_OUT1 313
	#define TEGRA210_CLK_PLL_U_OUT2 314
	#define TEGRA210_CLK_USB2_HSIC_TRK 315
	#define TEGRA210_CLK_PLL_P_OUT_HSIO 316
	#define TEGRA210_CLK_PLL_P_OUT_XUSB 317
	#define TEGRA210_CLK_XUSB_SSP_SRC 318
	#define TEGRA210_CLK_PLL_RE_OUT1 319
	/* 320 */
	/* 321 */
	#define TEGRA210_CLK_ISP 322
	#define TEGRA210_CLK_PLL_A_OUT_ADSP 323
	#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
	/* 325 */
	-/* 326 */
	+#define TEGRA210_CLK_OSC 326
	/* 327 */
	/* 328 */
	/* 329 */
	/* 330 */
	/* 331 */
	/* 332 */
	/* 333 */
	/* 334 */
	/* 335 */
	/* 336 */
	/* 337 */
	/* 338 */
	/* 339 */
	/* 340 */
	/* 341 */
	/* 342 */
	/* 343 */
	/* 344 */
	/* 345 */
	/* 346 */
	/* 347 */
	/* 348 */
	/* 349 */

	#define TEGRA210_CLK_AUDIO0_MUX 350
	#define TEGRA210_CLK_AUDIO1_MUX 351
	#define TEGRA210_CLK_AUDIO2_MUX 352
	#define TEGRA210_CLK_AUDIO3_MUX 353
	#define TEGRA210_CLK_AUDIO4_MUX 354
	#define TEGRA210_CLK_SPDIF_MUX 355
	#define TEGRA210_CLK_CLK_OUT_1_MUX 356
	#define TEGRA210_CLK_CLK_OUT_2_MUX 357
	#define TEGRA210_CLK_CLK_OUT_3_MUX 358
	#define TEGRA210_CLK_DSIA_MUX 359
	#define TEGRA210_CLK_DSIB_MUX 360
	/* 361 */
	#define TEGRA210_CLK_XUSB_SS_DIV2 362

	#define TEGRA210_CLK_PLL_M_UD 363
	#define TEGRA210_CLK_PLL_C_UD 364
	#define TEGRA210_CLK_SCLK_MUX 365

	#define TEGRA210_CLK_ACLK 370

	#define TEGRA210_CLK_DMIC1_SYNC_CLK 388
	#define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389
	#define TEGRA210_CLK_DMIC2_SYNC_CLK 390
	#define TEGRA210_CLK_DMIC2_SYNC_CLK_MUX 391
	#define TEGRA210_CLK_DMIC3_SYNC_CLK 392
	#define TEGRA210_CLK_DMIC3_SYNC_CLK_MUX 393

	#define TEGRA210_CLK_CLK_MAX 394

	#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */
	diff --git a/sys/gnu/dts/include/dt-bindings/clock/tegra30-car.h b/sys/gnu/dts/include/dt-bindings/clock/tegra30-car.h
	index 3c90f1535551..7b542c10fc27 100644
	--- a/sys/gnu/dts/include/dt-bindings/clock/tegra30-car.h
	+++ b/sys/gnu/dts/include/dt-bindings/clock/tegra30-car.h
	@@ -1,274 +1,276 @@
	/* SPDX-License-Identifier: GPL-2.0 */
	/*
	* This header provides constants for binding nvidia,tegra30-car.
	*
	* The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
	* registers. These IDs often match those in the CAR's RST_DEVICES registers,
	* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
	* this case, those clocks are assigned IDs above 160 in order to highlight
	* this issue. Implementations that interpret these clock IDs as bit values
	* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
	* explicitly handle these special cases.
	*
	* The balance of the clocks controlled by the CAR are assigned IDs of 160 and
	* above.
	*/

	#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
	#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H

	#define TEGRA30_CLK_CPU 0
	/* 1 */
	/* 2 */
	/* 3 */
	#define TEGRA30_CLK_RTC 4
	#define TEGRA30_CLK_TIMER 5
	#define TEGRA30_CLK_UARTA 6
	/* 7 (register bit affects uartb and vfir) */
	#define TEGRA30_CLK_GPIO 8
	#define TEGRA30_CLK_SDMMC2 9
	/* 10 (register bit affects spdif_in and spdif_out) */
	#define TEGRA30_CLK_I2S1 11
	#define TEGRA30_CLK_I2C1 12
	#define TEGRA30_CLK_NDFLASH 13
	#define TEGRA30_CLK_SDMMC1 14
	#define TEGRA30_CLK_SDMMC4 15
	/* 16 */
	#define TEGRA30_CLK_PWM 17
	#define TEGRA30_CLK_I2S2 18
	#define TEGRA30_CLK_EPP 19
	/* 20 (register bit affects vi and vi_sensor) */
	#define TEGRA30_CLK_GR2D 21
	#define TEGRA30_CLK_USBD 22
	#define TEGRA30_CLK_ISP 23
	#define TEGRA30_CLK_GR3D 24
	/* 25 */
	#define TEGRA30_CLK_DISP2 26
	#define TEGRA30_CLK_DISP1 27
	#define TEGRA30_CLK_HOST1X 28
	#define TEGRA30_CLK_VCP 29
	#define TEGRA30_CLK_I2S0 30
	#define TEGRA30_CLK_COP_CACHE 31

	#define TEGRA30_CLK_MC 32
	#define TEGRA30_CLK_AHBDMA 33
	#define TEGRA30_CLK_APBDMA 34
	/* 35 */
	#define TEGRA30_CLK_KBC 36
	#define TEGRA30_CLK_STATMON 37
	#define TEGRA30_CLK_PMC 38
	/* 39 (register bit affects fuse and fuse_burn) */
	#define TEGRA30_CLK_KFUSE 40
	#define TEGRA30_CLK_SBC1 41
	#define TEGRA30_CLK_NOR 42
	/* 43 */
	#define TEGRA30_CLK_SBC2 44
	/* 45 */
	#define TEGRA30_CLK_SBC3 46
	#define TEGRA30_CLK_I2C5 47
	#define TEGRA30_CLK_DSIA 48
	/* 49 (register bit affects cve and tvo) */
	#define TEGRA30_CLK_MIPI 50
	#define TEGRA30_CLK_HDMI 51
	#define TEGRA30_CLK_CSI 52
	#define TEGRA30_CLK_TVDAC 53
	#define TEGRA30_CLK_I2C2 54
	#define TEGRA30_CLK_UARTC 55
	/* 56 */
	#define TEGRA30_CLK_EMC 57
	#define TEGRA30_CLK_USB2 58
	#define TEGRA30_CLK_USB3 59
	#define TEGRA30_CLK_MPE 60
	#define TEGRA30_CLK_VDE 61
	#define TEGRA30_CLK_BSEA 62
	#define TEGRA30_CLK_BSEV 63

	#define TEGRA30_CLK_SPEEDO 64
	#define TEGRA30_CLK_UARTD 65
	#define TEGRA30_CLK_UARTE 66
	#define TEGRA30_CLK_I2C3 67
	#define TEGRA30_CLK_SBC4 68
	#define TEGRA30_CLK_SDMMC3 69
	#define TEGRA30_CLK_PCIE 70
	#define TEGRA30_CLK_OWR 71
	#define TEGRA30_CLK_AFI 72
	#define TEGRA30_CLK_CSITE 73
	/* 74 */
	#define TEGRA30_CLK_AVPUCQ 75
	#define TEGRA30_CLK_LA 76
	/* 77 */
	/* 78 */
	#define TEGRA30_CLK_DTV 79
	#define TEGRA30_CLK_NDSPEED 80
	#define TEGRA30_CLK_I2CSLOW 81
	#define TEGRA30_CLK_DSIB 82
	/* 83 */
	#define TEGRA30_CLK_IRAMA 84
	#define TEGRA30_CLK_IRAMB 85
	#define TEGRA30_CLK_IRAMC 86
	#define TEGRA30_CLK_IRAMD 87
	#define TEGRA30_CLK_CRAM2 88
	/* 89 */
	#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
	/* 91 */
	#define TEGRA30_CLK_CSUS 92
	#define TEGRA30_CLK_CDEV2 93
	#define TEGRA30_CLK_CDEV1 94
	/* 95 */

	#define TEGRA30_CLK_CPU_G 96
	#define TEGRA30_CLK_CPU_LP 97
	#define TEGRA30_CLK_GR3D2 98
	#define TEGRA30_CLK_MSELECT 99
	#define TEGRA30_CLK_TSENSOR 100
	#define TEGRA30_CLK_I2S3 101
	#define TEGRA30_CLK_I2S4 102
	#define TEGRA30_CLK_I2C4 103
	#define TEGRA30_CLK_SBC5 104
	#define TEGRA30_CLK_SBC6 105
	#define TEGRA30_CLK_D_AUDIO 106
	#define TEGRA30_CLK_APBIF 107
	#define TEGRA30_CLK_DAM0 108
	#define TEGRA30_CLK_DAM1 109
	#define TEGRA30_CLK_DAM2 110
	#define TEGRA30_CLK_HDA2CODEC_2X 111
	#define TEGRA30_CLK_ATOMICS 112
	#define TEGRA30_CLK_AUDIO0_2X 113
	#define TEGRA30_CLK_AUDIO1_2X 114
	#define TEGRA30_CLK_AUDIO2_2X 115
	#define TEGRA30_CLK_AUDIO3_2X 116
	#define TEGRA30_CLK_AUDIO4_2X 117
	#define TEGRA30_CLK_SPDIF_2X 118
	#define TEGRA30_CLK_ACTMON 119
	#define TEGRA30_CLK_EXTERN1 120
	#define TEGRA30_CLK_EXTERN2 121
	#define TEGRA30_CLK_EXTERN3 122
	#define TEGRA30_CLK_SATA_OOB 123
	#define TEGRA30_CLK_SATA 124
	#define TEGRA30_CLK_HDA 125
	/* 126 */
	#define TEGRA30_CLK_SE 127

	#define TEGRA30_CLK_HDA2HDMI 128
	#define TEGRA30_CLK_SATA_COLD 129
	/* 130 */
	/* 131 */
	/* 132 */
	/* 133 */
	/* 134 */
	/* 135 */
	#define TEGRA30_CLK_CEC 136
	/* 137 */
	/* 138 */
	/* 139 */
	/* 140 */
	/* 141 */
	/* 142 */
	/* 143 */
	/* 144 */
	/* 145 */
	/* 146 */
	/* 147 */
	/* 148 */
	/* 149 */
	/* 150 */
	/* 151 */
	/* 152 */
	/* 153 */
	/* 154 */
	/* 155 */
	/* 156 */
	/* 157 */
	/* 158 */
	/* 159 */

	#define TEGRA30_CLK_UARTB 160
	#define TEGRA30_CLK_VFIR 161
	#define TEGRA30_CLK_SPDIF_IN 162
	#define TEGRA30_CLK_SPDIF_OUT 163
	#define TEGRA30_CLK_VI 164
	#define TEGRA30_CLK_VI_SENSOR 165
	#define TEGRA30_CLK_FUSE 166
	#define TEGRA30_CLK_FUSE_BURN 167
	#define TEGRA30_CLK_CVE 168
	#define TEGRA30_CLK_TVO 169
	#define TEGRA30_CLK_CLK_32K 170
	#define TEGRA30_CLK_CLK_M 171
	#define TEGRA30_CLK_CLK_M_DIV2 172
	#define TEGRA30_CLK_CLK_M_DIV4 173
	+#define TEGRA30_CLK_OSC_DIV2 172
	+#define TEGRA30_CLK_OSC_DIV4 173
	#define TEGRA30_CLK_PLL_REF 174
	#define TEGRA30_CLK_PLL_C 175
	#define TEGRA30_CLK_PLL_C_OUT1 176
	#define TEGRA30_CLK_PLL_M 177
	#define TEGRA30_CLK_PLL_M_OUT1 178
	#define TEGRA30_CLK_PLL_P 179
	#define TEGRA30_CLK_PLL_P_OUT1 180
	#define TEGRA30_CLK_PLL_P_OUT2 181
	#define TEGRA30_CLK_PLL_P_OUT3 182
	#define TEGRA30_CLK_PLL_P_OUT4 183
	#define TEGRA30_CLK_PLL_A 184
	#define TEGRA30_CLK_PLL_A_OUT0 185
	#define TEGRA30_CLK_PLL_D 186
	#define TEGRA30_CLK_PLL_D_OUT0 187
	#define TEGRA30_CLK_PLL_D2 188
	#define TEGRA30_CLK_PLL_D2_OUT0 189
	#define TEGRA30_CLK_PLL_U 190
	#define TEGRA30_CLK_PLL_X 191

	#define TEGRA30_CLK_PLL_X_OUT0 192
	#define TEGRA30_CLK_PLL_E 193
	#define TEGRA30_CLK_SPDIF_IN_SYNC 194
	#define TEGRA30_CLK_I2S0_SYNC 195
	#define TEGRA30_CLK_I2S1_SYNC 196
	#define TEGRA30_CLK_I2S2_SYNC 197
	#define TEGRA30_CLK_I2S3_SYNC 198
	#define TEGRA30_CLK_I2S4_SYNC 199
	#define TEGRA30_CLK_VIMCLK_SYNC 200
	#define TEGRA30_CLK_AUDIO0 201
	#define TEGRA30_CLK_AUDIO1 202
	#define TEGRA30_CLK_AUDIO2 203
	#define TEGRA30_CLK_AUDIO3 204
	#define TEGRA30_CLK_AUDIO4 205
	#define TEGRA30_CLK_SPDIF 206
	#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
	#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
	#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
	#define TEGRA30_CLK_SCLK 210
	#define TEGRA30_CLK_BLINK 211
	#define TEGRA30_CLK_CCLK_G 212
	#define TEGRA30_CLK_CCLK_LP 213
	#define TEGRA30_CLK_TWD 214
	#define TEGRA30_CLK_CML0 215
	#define TEGRA30_CLK_CML1 216
	#define TEGRA30_CLK_HCLK 217
	#define TEGRA30_CLK_PCLK 218
	/* 219 */
	-/* 220 */
	+#define TEGRA30_CLK_OSC 220
	/* 221 */
	/* 222 */
	/* 223 */

	/* 288 */
	/* 289 */
	/* 290 */
	/* 291 */
	/* 292 */
	/* 293 */
	/* 294 */
	/* 295 */
	/* 296 */
	/* 297 */
	/* 298 */
	/* 299 */
	#define TEGRA30_CLK_CLK_OUT_1_MUX 300
	#define TEGRA30_CLK_CLK_OUT_2_MUX 301
	#define TEGRA30_CLK_CLK_OUT_3_MUX 302
	#define TEGRA30_CLK_AUDIO0_MUX 303
	#define TEGRA30_CLK_AUDIO1_MUX 304
	#define TEGRA30_CLK_AUDIO2_MUX 305
	#define TEGRA30_CLK_AUDIO3_MUX 306
	#define TEGRA30_CLK_AUDIO4_MUX 307
	#define TEGRA30_CLK_SPDIF_MUX 308
	#define TEGRA30_CLK_CLK_MAX 309

	#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */
	diff --git a/sys/gnu/dts/include/dt-bindings/display/sdtv-standards.h b/sys/gnu/dts/include/dt-bindings/display/sdtv-standards.h
	new file mode 100644
	index 000000000000..fbc1a3db2ea7
	--- /dev/null
	+++ b/sys/gnu/dts/include/dt-bindings/display/sdtv-standards.h
	@@ -0,0 +1,76 @@
	+/* SPDX-License-Identifier: GPL-2.0-only or X11 */
	+/*
	+ * Copyright 2019 Pengutronix, Marco Felsch <kernel@pengutronix.de>
	+ */
	+
	+#ifndef _DT_BINDINGS_DISPLAY_SDTV_STDS_H
	+#define _DT_BINDINGS_DISPLAY_SDTV_STDS_H
	+
	+/*
	+ * Attention: Keep the SDTV_STD_* bit definitions in sync with
	+ * include/uapi/linux/videodev2.h V4L2_STD_* bit definitions.
	+ */
	+/* One bit for each standard */
	+#define SDTV_STD_PAL_B 0x00000001
	+#define SDTV_STD_PAL_B1 0x00000002
	+#define SDTV_STD_PAL_G 0x00000004
	+#define SDTV_STD_PAL_H 0x00000008
	+#define SDTV_STD_PAL_I 0x00000010
	+#define SDTV_STD_PAL_D 0x00000020
	+#define SDTV_STD_PAL_D1 0x00000040
	+#define SDTV_STD_PAL_K 0x00000080
	+
	+#define SDTV_STD_PAL (SDTV_STD_PAL_B \| \
	+ SDTV_STD_PAL_B1 \| \
	+ SDTV_STD_PAL_G \| \
	+ SDTV_STD_PAL_H \| \
	+ SDTV_STD_PAL_I \| \
	+ SDTV_STD_PAL_D \| \
	+ SDTV_STD_PAL_D1 \| \
	+ SDTV_STD_PAL_K)
	+
	+#define SDTV_STD_PAL_M 0x00000100
	+#define SDTV_STD_PAL_N 0x00000200
	+#define SDTV_STD_PAL_Nc 0x00000400
	+#define SDTV_STD_PAL_60 0x00000800
	+
	+#define SDTV_STD_NTSC_M 0x00001000 /* BTSC */
	+#define SDTV_STD_NTSC_M_JP 0x00002000 /* EIA-J */
	+#define SDTV_STD_NTSC_443 0x00004000
	+#define SDTV_STD_NTSC_M_KR 0x00008000 /* FM A2 */
	+
	+#define SDTV_STD_NTSC (SDTV_STD_NTSC_M \| \
	+ SDTV_STD_NTSC_M_JP \| \
	+ SDTV_STD_NTSC_M_KR)
	+
	+#define SDTV_STD_SECAM_B 0x00010000
	+#define SDTV_STD_SECAM_D 0x00020000
	+#define SDTV_STD_SECAM_G 0x00040000
	+#define SDTV_STD_SECAM_H 0x00080000
	+#define SDTV_STD_SECAM_K 0x00100000
	+#define SDTV_STD_SECAM_K1 0x00200000
	+#define SDTV_STD_SECAM_L 0x00400000
	+#define SDTV_STD_SECAM_LC 0x00800000
	+
	+#define SDTV_STD_SECAM (SDTV_STD_SECAM_B \| \
	+ SDTV_STD_SECAM_D \| \
	+ SDTV_STD_SECAM_G \| \
	+ SDTV_STD_SECAM_H \| \
	+ SDTV_STD_SECAM_K \| \
	+ SDTV_STD_SECAM_K1 \| \
	+ SDTV_STD_SECAM_L \| \
	+ SDTV_STD_SECAM_LC)
	+
	+/* Standards for Countries with 60Hz Line frequency */
	+#define SDTV_STD_525_60 (SDTV_STD_PAL_M \| \
	+ SDTV_STD_PAL_60 \| \
	+ SDTV_STD_NTSC \| \
	+ SDTV_STD_NTSC_443)
	+
	+/* Standards for Countries with 50Hz Line frequency */
	+#define SDTV_STD_625_50 (SDTV_STD_PAL \| \
	+ SDTV_STD_PAL_N \| \
	+ SDTV_STD_PAL_Nc \| \
	+ SDTV_STD_SECAM)
	+
	+#endif /* _DT_BINDINGS_DISPLAY_SDTV_STDS_H */
	diff --git a/sys/gnu/dts/include/dt-bindings/input/linux-event-codes.h b/sys/gnu/dts/include/dt-bindings/input/linux-event-codes.h
	index 6923dc7e0298..b6a835d37826 100644
	--- a/sys/gnu/dts/include/dt-bindings/input/linux-event-codes.h
	+++ b/sys/gnu/dts/include/dt-bindings/input/linux-event-codes.h
	@@ -1,944 +1,944 @@
	-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
	+/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
	/*
	* Input event codes
	*
	* * IMPORTANT *
	* This file is not only included from C-code but also from devicetree source
	* files. As such this file MUST only contain comments and defines.
	*
	* Copyright (c) 1999-2002 Vojtech Pavlik
	* Copyright (c) 2015 Hans de Goede <hdegoede@redhat.com>
	*
	* This program is free software; you can redistribute it and/or modify it
	* under the terms of the GNU General Public License version 2 as published by
	* the Free Software Foundation.
	*/
	#ifndef _UAPI_INPUT_EVENT_CODES_H
	#define _UAPI_INPUT_EVENT_CODES_H

	/*
	* Device properties and quirks
	*/

	#define INPUT_PROP_POINTER 0x00 /* needs a pointer */
	#define INPUT_PROP_DIRECT 0x01 /* direct input devices */
	#define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */
	#define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */
	#define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */
	#define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */
	#define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */

	#define INPUT_PROP_MAX 0x1f
	#define INPUT_PROP_CNT (INPUT_PROP_MAX + 1)

	/*
	* Event types
	*/

	#define EV_SYN 0x00
	#define EV_KEY 0x01
	#define EV_REL 0x02
	#define EV_ABS 0x03
	#define EV_MSC 0x04
	#define EV_SW 0x05
	#define EV_LED 0x11
	#define EV_SND 0x12
	#define EV_REP 0x14
	#define EV_FF 0x15
	#define EV_PWR 0x16
	#define EV_FF_STATUS 0x17
	#define EV_MAX 0x1f
	#define EV_CNT (EV_MAX+1)

	/*
	* Synchronization events.
	*/

	#define SYN_REPORT 0
	#define SYN_CONFIG 1
	#define SYN_MT_REPORT 2
	#define SYN_DROPPED 3
	#define SYN_MAX 0xf
	#define SYN_CNT (SYN_MAX+1)

	/*
	* Keys and buttons
	*
	* Most of the keys/buttons are modeled after USB HUT 1.12
	* (see http://www.usb.org/developers/hidpage).
	* Abbreviations in the comments:
	* AC - Application Control
	* AL - Application Launch Button
	* SC - System Control
	*/

	#define KEY_RESERVED 0
	#define KEY_ESC 1
	#define KEY_1 2
	#define KEY_2 3
	#define KEY_3 4
	#define KEY_4 5
	#define KEY_5 6
	#define KEY_6 7
	#define KEY_7 8
	#define KEY_8 9
	#define KEY_9 10
	#define KEY_0 11
	#define KEY_MINUS 12
	#define KEY_EQUAL 13
	#define KEY_BACKSPACE 14
	#define KEY_TAB 15
	#define KEY_Q 16
	#define KEY_W 17
	#define KEY_E 18
	#define KEY_R 19
	#define KEY_T 20
	#define KEY_Y 21
	#define KEY_U 22
	#define KEY_I 23
	#define KEY_O 24
	#define KEY_P 25
	#define KEY_LEFTBRACE 26
	#define KEY_RIGHTBRACE 27
	#define KEY_ENTER 28
	#define KEY_LEFTCTRL 29
	#define KEY_A 30
	#define KEY_S 31
	#define KEY_D 32
	#define KEY_F 33
	#define KEY_G 34
	#define KEY_H 35
	#define KEY_J 36
	#define KEY_K 37
	#define KEY_L 38
	#define KEY_SEMICOLON 39
	#define KEY_APOSTROPHE 40
	#define KEY_GRAVE 41
	#define KEY_LEFTSHIFT 42
	#define KEY_BACKSLASH 43
	#define KEY_Z 44
	#define KEY_X 45
	#define KEY_C 46
	#define KEY_V 47
	#define KEY_B 48
	#define KEY_N 49
	#define KEY_M 50
	#define KEY_COMMA 51
	#define KEY_DOT 52
	#define KEY_SLASH 53
	#define KEY_RIGHTSHIFT 54
	#define KEY_KPASTERISK 55
	#define KEY_LEFTALT 56
	#define KEY_SPACE 57
	#define KEY_CAPSLOCK 58
	#define KEY_F1 59
	#define KEY_F2 60
	#define KEY_F3 61
	#define KEY_F4 62
	#define KEY_F5 63
	#define KEY_F6 64
	#define KEY_F7 65
	#define KEY_F8 66
	#define KEY_F9 67
	#define KEY_F10 68
	#define KEY_NUMLOCK 69
	#define KEY_SCROLLLOCK 70
	#define KEY_KP7 71
	#define KEY_KP8 72
	#define KEY_KP9 73
	#define KEY_KPMINUS 74
	#define KEY_KP4 75
	#define KEY_KP5 76
	#define KEY_KP6 77
	#define KEY_KPPLUS 78
	#define KEY_KP1 79
	#define KEY_KP2 80
	#define KEY_KP3 81
	#define KEY_KP0 82
	#define KEY_KPDOT 83

	#define KEY_ZENKAKUHANKAKU 85
	#define KEY_102ND 86
	#define KEY_F11 87
	#define KEY_F12 88
	#define KEY_RO 89
	#define KEY_KATAKANA 90
	#define KEY_HIRAGANA 91
	#define KEY_HENKAN 92
	#define KEY_KATAKANAHIRAGANA 93
	#define KEY_MUHENKAN 94
	#define KEY_KPJPCOMMA 95
	#define KEY_KPENTER 96
	#define KEY_RIGHTCTRL 97
	#define KEY_KPSLASH 98
	#define KEY_SYSRQ 99
	#define KEY_RIGHTALT 100
	#define KEY_LINEFEED 101
	#define KEY_HOME 102
	#define KEY_UP 103
	#define KEY_PAGEUP 104
	#define KEY_LEFT 105
	#define KEY_RIGHT 106
	#define KEY_END 107
	#define KEY_DOWN 108
	#define KEY_PAGEDOWN 109
	#define KEY_INSERT 110
	#define KEY_DELETE 111
	#define KEY_MACRO 112
	#define KEY_MUTE 113
	#define KEY_VOLUMEDOWN 114
	#define KEY_VOLUMEUP 115
	#define KEY_POWER 116 /* SC System Power Down */
	#define KEY_KPEQUAL 117
	#define KEY_KPPLUSMINUS 118
	#define KEY_PAUSE 119
	#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */

	#define KEY_KPCOMMA 121
	#define KEY_HANGEUL 122
	#define KEY_HANGUEL KEY_HANGEUL
	#define KEY_HANJA 123
	#define KEY_YEN 124
	#define KEY_LEFTMETA 125
	#define KEY_RIGHTMETA 126
	#define KEY_COMPOSE 127

	#define KEY_STOP 128 /* AC Stop */
	#define KEY_AGAIN 129
	#define KEY_PROPS 130 /* AC Properties */
	#define KEY_UNDO 131 /* AC Undo */
	#define KEY_FRONT 132
	#define KEY_COPY 133 /* AC Copy */
	#define KEY_OPEN 134 /* AC Open */
	#define KEY_PASTE 135 /* AC Paste */
	#define KEY_FIND 136 /* AC Search */
	#define KEY_CUT 137 /* AC Cut */
	#define KEY_HELP 138 /* AL Integrated Help Center */
	#define KEY_MENU 139 /* Menu (show menu) */
	#define KEY_CALC 140 /* AL Calculator */
	#define KEY_SETUP 141
	#define KEY_SLEEP 142 /* SC System Sleep */
	#define KEY_WAKEUP 143 /* System Wake Up */
	#define KEY_FILE 144 /* AL Local Machine Browser */
	#define KEY_SENDFILE 145
	#define KEY_DELETEFILE 146
	#define KEY_XFER 147
	#define KEY_PROG1 148
	#define KEY_PROG2 149
	#define KEY_WWW 150 /* AL Internet Browser */
	#define KEY_MSDOS 151
	#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */
	#define KEY_SCREENLOCK KEY_COFFEE
	#define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */
	#define KEY_DIRECTION KEY_ROTATE_DISPLAY
	#define KEY_CYCLEWINDOWS 154
	#define KEY_MAIL 155
	#define KEY_BOOKMARKS 156 /* AC Bookmarks */
	#define KEY_COMPUTER 157
	#define KEY_BACK 158 /* AC Back */
	#define KEY_FORWARD 159 /* AC Forward */
	#define KEY_CLOSECD 160
	#define KEY_EJECTCD 161
	#define KEY_EJECTCLOSECD 162
	#define KEY_NEXTSONG 163
	#define KEY_PLAYPAUSE 164
	#define KEY_PREVIOUSSONG 165
	#define KEY_STOPCD 166
	#define KEY_RECORD 167
	#define KEY_REWIND 168
	#define KEY_PHONE 169 /* Media Select Telephone */
	#define KEY_ISO 170
	#define KEY_CONFIG 171 /* AL Consumer Control Configuration */
	#define KEY_HOMEPAGE 172 /* AC Home */
	#define KEY_REFRESH 173 /* AC Refresh */
	#define KEY_EXIT 174 /* AC Exit */
	#define KEY_MOVE 175
	#define KEY_EDIT 176
	#define KEY_SCROLLUP 177
	#define KEY_SCROLLDOWN 178
	#define KEY_KPLEFTPAREN 179
	#define KEY_KPRIGHTPAREN 180
	#define KEY_NEW 181 /* AC New */
	#define KEY_REDO 182 /* AC Redo/Repeat */

	#define KEY_F13 183
	#define KEY_F14 184
	#define KEY_F15 185
	#define KEY_F16 186
	#define KEY_F17 187
	#define KEY_F18 188
	#define KEY_F19 189
	#define KEY_F20 190
	#define KEY_F21 191
	#define KEY_F22 192
	#define KEY_F23 193
	#define KEY_F24 194

	#define KEY_PLAYCD 200
	#define KEY_PAUSECD 201
	#define KEY_PROG3 202
	#define KEY_PROG4 203
	#define KEY_DASHBOARD 204 /* AL Dashboard */
	#define KEY_SUSPEND 205
	#define KEY_CLOSE 206 /* AC Close */
	#define KEY_PLAY 207
	#define KEY_FASTFORWARD 208
	#define KEY_BASSBOOST 209
	#define KEY_PRINT 210 /* AC Print */
	#define KEY_HP 211
	#define KEY_CAMERA 212
	#define KEY_SOUND 213
	#define KEY_QUESTION 214
	#define KEY_EMAIL 215
	#define KEY_CHAT 216
	#define KEY_SEARCH 217
	#define KEY_CONNECT 218
	#define KEY_FINANCE 219 /* AL Checkbook/Finance */
	#define KEY_SPORT 220
	#define KEY_SHOP 221
	#define KEY_ALTERASE 222
	#define KEY_CANCEL 223 /* AC Cancel */
	#define KEY_BRIGHTNESSDOWN 224
	#define KEY_BRIGHTNESSUP 225
	#define KEY_MEDIA 226

	#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video
	outputs (Monitor/LCD/TV-out/etc) */
	#define KEY_KBDILLUMTOGGLE 228
	#define KEY_KBDILLUMDOWN 229
	#define KEY_KBDILLUMUP 230

	#define KEY_SEND 231 /* AC Send */
	#define KEY_REPLY 232 /* AC Reply */
	#define KEY_FORWARDMAIL 233 /* AC Forward Msg */
	#define KEY_SAVE 234 /* AC Save */
	#define KEY_DOCUMENTS 235

	#define KEY_BATTERY 236

	#define KEY_BLUETOOTH 237
	#define KEY_WLAN 238
	#define KEY_UWB 239

	#define KEY_UNKNOWN 240

	#define KEY_VIDEO_NEXT 241 /* drive next video source */
	#define KEY_VIDEO_PREV 242 /* drive previous video source */
	#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */
	#define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual
	brightness control is off,
	rely on ambient */
	#define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO
	#define KEY_DISPLAY_OFF 245 /* display device to off state */

	#define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */
	#define KEY_WIMAX KEY_WWAN
	#define KEY_RFKILL 247 /* Key that controls all radios */

	#define KEY_MICMUTE 248 /* Mute / unmute the microphone */

	/* Code 255 is reserved for special needs of AT keyboard driver */

	#define BTN_MISC 0x100
	#define BTN_0 0x100
	#define BTN_1 0x101
	#define BTN_2 0x102
	#define BTN_3 0x103
	#define BTN_4 0x104
	#define BTN_5 0x105
	#define BTN_6 0x106
	#define BTN_7 0x107
	#define BTN_8 0x108
	#define BTN_9 0x109

	#define BTN_MOUSE 0x110
	#define BTN_LEFT 0x110
	#define BTN_RIGHT 0x111
	#define BTN_MIDDLE 0x112
	#define BTN_SIDE 0x113
	#define BTN_EXTRA 0x114
	#define BTN_FORWARD 0x115
	#define BTN_BACK 0x116
	#define BTN_TASK 0x117

	#define BTN_JOYSTICK 0x120
	#define BTN_TRIGGER 0x120
	#define BTN_THUMB 0x121
	#define BTN_THUMB2 0x122
	#define BTN_TOP 0x123
	#define BTN_TOP2 0x124
	#define BTN_PINKIE 0x125
	#define BTN_BASE 0x126
	#define BTN_BASE2 0x127
	#define BTN_BASE3 0x128
	#define BTN_BASE4 0x129
	#define BTN_BASE5 0x12a
	#define BTN_BASE6 0x12b
	#define BTN_DEAD 0x12f

	#define BTN_GAMEPAD 0x130
	#define BTN_SOUTH 0x130
	#define BTN_A BTN_SOUTH
	#define BTN_EAST 0x131
	#define BTN_B BTN_EAST
	#define BTN_C 0x132
	#define BTN_NORTH 0x133
	#define BTN_X BTN_NORTH
	#define BTN_WEST 0x134
	#define BTN_Y BTN_WEST
	#define BTN_Z 0x135
	#define BTN_TL 0x136
	#define BTN_TR 0x137
	#define BTN_TL2 0x138
	#define BTN_TR2 0x139
	#define BTN_SELECT 0x13a
	#define BTN_START 0x13b
	#define BTN_MODE 0x13c
	#define BTN_THUMBL 0x13d
	#define BTN_THUMBR 0x13e

	#define BTN_DIGI 0x140
	#define BTN_TOOL_PEN 0x140
	#define BTN_TOOL_RUBBER 0x141
	#define BTN_TOOL_BRUSH 0x142
	#define BTN_TOOL_PENCIL 0x143
	#define BTN_TOOL_AIRBRUSH 0x144
	#define BTN_TOOL_FINGER 0x145
	#define BTN_TOOL_MOUSE 0x146
	#define BTN_TOOL_LENS 0x147
	#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */
	#define BTN_STYLUS3 0x149
	#define BTN_TOUCH 0x14a
	#define BTN_STYLUS 0x14b
	#define BTN_STYLUS2 0x14c
	#define BTN_TOOL_DOUBLETAP 0x14d
	#define BTN_TOOL_TRIPLETAP 0x14e
	#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */

	#define BTN_WHEEL 0x150
	#define BTN_GEAR_DOWN 0x150
	#define BTN_GEAR_UP 0x151

	#define KEY_OK 0x160
	#define KEY_SELECT 0x161
	#define KEY_GOTO 0x162
	#define KEY_CLEAR 0x163
	#define KEY_POWER2 0x164
	#define KEY_OPTION 0x165
	#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */
	#define KEY_TIME 0x167
	#define KEY_VENDOR 0x168
	#define KEY_ARCHIVE 0x169
	#define KEY_PROGRAM 0x16a /* Media Select Program Guide */
	#define KEY_CHANNEL 0x16b
	#define KEY_FAVORITES 0x16c
	#define KEY_EPG 0x16d
	#define KEY_PVR 0x16e /* Media Select Home */
	#define KEY_MHP 0x16f
	#define KEY_LANGUAGE 0x170
	#define KEY_TITLE 0x171
	#define KEY_SUBTITLE 0x172
	#define KEY_ANGLE 0x173
	#define KEY_FULL_SCREEN 0x174 /* AC View Toggle */
	#define KEY_ZOOM KEY_FULL_SCREEN
	#define KEY_MODE 0x175
	#define KEY_KEYBOARD 0x176
	#define KEY_ASPECT_RATIO 0x177 /* HUTRR37: Aspect */
	#define KEY_SCREEN KEY_ASPECT_RATIO
	#define KEY_PC 0x178 /* Media Select Computer */
	#define KEY_TV 0x179 /* Media Select TV */
	#define KEY_TV2 0x17a /* Media Select Cable */
	#define KEY_VCR 0x17b /* Media Select VCR */
	#define KEY_VCR2 0x17c /* VCR Plus */
	#define KEY_SAT 0x17d /* Media Select Satellite */
	#define KEY_SAT2 0x17e
	#define KEY_CD 0x17f /* Media Select CD */
	#define KEY_TAPE 0x180 /* Media Select Tape */
	#define KEY_RADIO 0x181
	#define KEY_TUNER 0x182 /* Media Select Tuner */
	#define KEY_PLAYER 0x183
	#define KEY_TEXT 0x184
	#define KEY_DVD 0x185 /* Media Select DVD */
	#define KEY_AUX 0x186
	#define KEY_MP3 0x187
	#define KEY_AUDIO 0x188 /* AL Audio Browser */
	#define KEY_VIDEO 0x189 /* AL Movie Browser */
	#define KEY_DIRECTORY 0x18a
	#define KEY_LIST 0x18b
	#define KEY_MEMO 0x18c /* Media Select Messages */
	#define KEY_CALENDAR 0x18d
	#define KEY_RED 0x18e
	#define KEY_GREEN 0x18f
	#define KEY_YELLOW 0x190
	#define KEY_BLUE 0x191
	#define KEY_CHANNELUP 0x192 /* Channel Increment */
	#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */
	#define KEY_FIRST 0x194
	#define KEY_LAST 0x195 /* Recall Last */
	#define KEY_AB 0x196
	#define KEY_NEXT 0x197
	#define KEY_RESTART 0x198
	#define KEY_SLOW 0x199
	#define KEY_SHUFFLE 0x19a
	#define KEY_BREAK 0x19b
	#define KEY_PREVIOUS 0x19c
	#define KEY_DIGITS 0x19d
	#define KEY_TEEN 0x19e
	#define KEY_TWEN 0x19f
	#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */
	#define KEY_GAMES 0x1a1 /* Media Select Games */
	#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */
	#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */
	#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */
	#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */
	#define KEY_EDITOR 0x1a6 /* AL Text Editor */
	#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */
	#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */
	#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */
	#define KEY_DATABASE 0x1aa /* AL Database App */
	#define KEY_NEWS 0x1ab /* AL Newsreader */
	#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */
	#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */
	#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */
	#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */
	#define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE
	#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */
	#define KEY_LOGOFF 0x1b1 /* AL Logoff */

	#define KEY_DOLLAR 0x1b2
	#define KEY_EURO 0x1b3

	#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */
	#define KEY_FRAMEFORWARD 0x1b5
	#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */
	#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */
	#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */
	#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */
	#define KEY_IMAGES 0x1ba /* AL Image Browser */

	#define KEY_DEL_EOL 0x1c0
	#define KEY_DEL_EOS 0x1c1
	#define KEY_INS_LINE 0x1c2
	#define KEY_DEL_LINE 0x1c3

	#define KEY_FN 0x1d0
	#define KEY_FN_ESC 0x1d1
	#define KEY_FN_F1 0x1d2
	#define KEY_FN_F2 0x1d3
	#define KEY_FN_F3 0x1d4
	#define KEY_FN_F4 0x1d5
	#define KEY_FN_F5 0x1d6
	#define KEY_FN_F6 0x1d7
	#define KEY_FN_F7 0x1d8
	#define KEY_FN_F8 0x1d9
	#define KEY_FN_F9 0x1da
	#define KEY_FN_F10 0x1db
	#define KEY_FN_F11 0x1dc
	#define KEY_FN_F12 0x1dd
	#define KEY_FN_1 0x1de
	#define KEY_FN_2 0x1df
	#define KEY_FN_D 0x1e0
	#define KEY_FN_E 0x1e1
	#define KEY_FN_F 0x1e2
	#define KEY_FN_S 0x1e3
	#define KEY_FN_B 0x1e4

	#define KEY_BRL_DOT1 0x1f1
	#define KEY_BRL_DOT2 0x1f2
	#define KEY_BRL_DOT3 0x1f3
	#define KEY_BRL_DOT4 0x1f4
	#define KEY_BRL_DOT5 0x1f5
	#define KEY_BRL_DOT6 0x1f6
	#define KEY_BRL_DOT7 0x1f7
	#define KEY_BRL_DOT8 0x1f8
	#define KEY_BRL_DOT9 0x1f9
	#define KEY_BRL_DOT10 0x1fa

	#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */
	#define KEY_NUMERIC_1 0x201 /* and other keypads */
	#define KEY_NUMERIC_2 0x202
	#define KEY_NUMERIC_3 0x203
	#define KEY_NUMERIC_4 0x204
	#define KEY_NUMERIC_5 0x205
	#define KEY_NUMERIC_6 0x206
	#define KEY_NUMERIC_7 0x207
	#define KEY_NUMERIC_8 0x208
	#define KEY_NUMERIC_9 0x209
	#define KEY_NUMERIC_STAR 0x20a
	#define KEY_NUMERIC_POUND 0x20b
	#define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */
	#define KEY_NUMERIC_B 0x20d
	#define KEY_NUMERIC_C 0x20e
	#define KEY_NUMERIC_D 0x20f

	#define KEY_CAMERA_FOCUS 0x210
	#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */

	#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */
	#define KEY_TOUCHPAD_ON 0x213
	#define KEY_TOUCHPAD_OFF 0x214

	#define KEY_CAMERA_ZOOMIN 0x215
	#define KEY_CAMERA_ZOOMOUT 0x216
	#define KEY_CAMERA_UP 0x217
	#define KEY_CAMERA_DOWN 0x218
	#define KEY_CAMERA_LEFT 0x219
	#define KEY_CAMERA_RIGHT 0x21a

	#define KEY_ATTENDANT_ON 0x21b
	#define KEY_ATTENDANT_OFF 0x21c
	#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */
	#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */

	#define BTN_DPAD_UP 0x220
	#define BTN_DPAD_DOWN 0x221
	#define BTN_DPAD_LEFT 0x222
	#define BTN_DPAD_RIGHT 0x223

	#define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */
	#define KEY_ROTATE_LOCK_TOGGLE 0x231 /* Display rotation lock */

	#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */
	#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */
	#define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */
	#define KEY_CONTROLPANEL 0x243 /* AL Control Panel */
	#define KEY_APPSELECT 0x244 /* AL Select Task/Application */
	#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */
	#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */
	#define KEY_ASSISTANT 0x247 /* AL Context-aware desktop assistant */
	#define KEY_KBD_LAYOUT_NEXT 0x248 /* AC Next Keyboard Layout Select */

	#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */
	#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */

	#define KEY_KBDINPUTASSIST_PREV 0x260
	#define KEY_KBDINPUTASSIST_NEXT 0x261
	#define KEY_KBDINPUTASSIST_PREVGROUP 0x262
	#define KEY_KBDINPUTASSIST_NEXTGROUP 0x263
	#define KEY_KBDINPUTASSIST_ACCEPT 0x264
	#define KEY_KBDINPUTASSIST_CANCEL 0x265

	/* Diagonal movement keys */
	#define KEY_RIGHT_UP 0x266
	#define KEY_RIGHT_DOWN 0x267
	#define KEY_LEFT_UP 0x268
	#define KEY_LEFT_DOWN 0x269

	#define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */
	/* Show Top Menu of the Media (e.g. DVD) */
	#define KEY_MEDIA_TOP_MENU 0x26b
	#define KEY_NUMERIC_11 0x26c
	#define KEY_NUMERIC_12 0x26d
	/*
	* Toggle Audio Description: refers to an audio service that helps blind and
	* visually impaired consumers understand the action in a program. Note: in
	* some countries this is referred to as "Video Description".
	*/
	#define KEY_AUDIO_DESC 0x26e
	#define KEY_3D_MODE 0x26f
	#define KEY_NEXT_FAVORITE 0x270
	#define KEY_STOP_RECORD 0x271
	#define KEY_PAUSE_RECORD 0x272
	#define KEY_VOD 0x273 /* Video on Demand */
	#define KEY_UNMUTE 0x274
	#define KEY_FASTREVERSE 0x275
	#define KEY_SLOWREVERSE 0x276
	/*
	* Control a data application associated with the currently viewed channel,
	* e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)
	*/
	#define KEY_DATA 0x277
	#define KEY_ONSCREEN_KEYBOARD 0x278
	/* Electronic privacy screen control */
	#define KEY_PRIVACY_SCREEN_TOGGLE 0x279

	/* Select an area of screen to be copied */
	#define KEY_SELECTIVE_SCREENSHOT 0x27a

	/*
	* Some keyboards have keys which do not have a defined meaning, these keys
	* are intended to be programmed / bound to macros by the user. For most
	* keyboards with these macro-keys the key-sequence to inject, or action to
	* take, is all handled by software on the host side. So from the kernel's
	* point of view these are just normal keys.
	*
	* The KEY_MACRO# codes below are intended for such keys, which may be labeled
	* e.g. G1-G18, or S1 - S30. The KEY_MACRO# codes MUST NOT be used for keys
	* where the marking on the key does indicate a defined meaning / purpose.
	*
	* The KEY_MACRO# codes MUST also NOT be used as fallback for when no existing
	* KEY_FOO define matches the marking / purpose. In this case a new KEY_FOO
	* define MUST be added.
	*/
	#define KEY_MACRO1 0x290
	#define KEY_MACRO2 0x291
	#define KEY_MACRO3 0x292
	#define KEY_MACRO4 0x293
	#define KEY_MACRO5 0x294
	#define KEY_MACRO6 0x295
	#define KEY_MACRO7 0x296
	#define KEY_MACRO8 0x297
	#define KEY_MACRO9 0x298
	#define KEY_MACRO10 0x299
	#define KEY_MACRO11 0x29a
	#define KEY_MACRO12 0x29b
	#define KEY_MACRO13 0x29c
	#define KEY_MACRO14 0x29d
	#define KEY_MACRO15 0x29e
	#define KEY_MACRO16 0x29f
	#define KEY_MACRO17 0x2a0
	#define KEY_MACRO18 0x2a1
	#define KEY_MACRO19 0x2a2
	#define KEY_MACRO20 0x2a3
	#define KEY_MACRO21 0x2a4
	#define KEY_MACRO22 0x2a5
	#define KEY_MACRO23 0x2a6
	#define KEY_MACRO24 0x2a7
	#define KEY_MACRO25 0x2a8
	#define KEY_MACRO26 0x2a9
	#define KEY_MACRO27 0x2aa
	#define KEY_MACRO28 0x2ab
	#define KEY_MACRO29 0x2ac
	#define KEY_MACRO30 0x2ad

	/*
	* Some keyboards with the macro-keys described above have some extra keys
	* for controlling the host-side software responsible for the macro handling:
	* -A macro recording start/stop key. Note that not all keyboards which emit
	* KEY_MACRO_RECORD_START will also emit KEY_MACRO_RECORD_STOP if
	* KEY_MACRO_RECORD_STOP is not advertised, then KEY_MACRO_RECORD_START
	* should be interpreted as a recording start/stop toggle;
	* -Keys for switching between different macro (pre)sets, either a key for
	* cycling through the configured presets or keys to directly select a preset.
	*/
	#define KEY_MACRO_RECORD_START 0x2b0
	#define KEY_MACRO_RECORD_STOP 0x2b1
	#define KEY_MACRO_PRESET_CYCLE 0x2b2
	#define KEY_MACRO_PRESET1 0x2b3
	#define KEY_MACRO_PRESET2 0x2b4
	#define KEY_MACRO_PRESET3 0x2b5

	/*
	* Some keyboards have a buildin LCD panel where the contents are controlled
	* by the host. Often these have a number of keys directly below the LCD
	* intended for controlling a menu shown on the LCD. These keys often don't
	* have any labeling so we just name them KEY_KBD_LCD_MENU#
	*/
	#define KEY_KBD_LCD_MENU1 0x2b8
	#define KEY_KBD_LCD_MENU2 0x2b9
	#define KEY_KBD_LCD_MENU3 0x2ba
	#define KEY_KBD_LCD_MENU4 0x2bb
	#define KEY_KBD_LCD_MENU5 0x2bc

	#define BTN_TRIGGER_HAPPY 0x2c0
	#define BTN_TRIGGER_HAPPY1 0x2c0
	#define BTN_TRIGGER_HAPPY2 0x2c1
	#define BTN_TRIGGER_HAPPY3 0x2c2
	#define BTN_TRIGGER_HAPPY4 0x2c3
	#define BTN_TRIGGER_HAPPY5 0x2c4
	#define BTN_TRIGGER_HAPPY6 0x2c5
	#define BTN_TRIGGER_HAPPY7 0x2c6
	#define BTN_TRIGGER_HAPPY8 0x2c7
	#define BTN_TRIGGER_HAPPY9 0x2c8
	#define BTN_TRIGGER_HAPPY10 0x2c9
	#define BTN_TRIGGER_HAPPY11 0x2ca
	#define BTN_TRIGGER_HAPPY12 0x2cb
	#define BTN_TRIGGER_HAPPY13 0x2cc
	#define BTN_TRIGGER_HAPPY14 0x2cd
	#define BTN_TRIGGER_HAPPY15 0x2ce
	#define BTN_TRIGGER_HAPPY16 0x2cf
	#define BTN_TRIGGER_HAPPY17 0x2d0
	#define BTN_TRIGGER_HAPPY18 0x2d1
	#define BTN_TRIGGER_HAPPY19 0x2d2
	#define BTN_TRIGGER_HAPPY20 0x2d3
	#define BTN_TRIGGER_HAPPY21 0x2d4
	#define BTN_TRIGGER_HAPPY22 0x2d5
	#define BTN_TRIGGER_HAPPY23 0x2d6
	#define BTN_TRIGGER_HAPPY24 0x2d7
	#define BTN_TRIGGER_HAPPY25 0x2d8
	#define BTN_TRIGGER_HAPPY26 0x2d9
	#define BTN_TRIGGER_HAPPY27 0x2da
	#define BTN_TRIGGER_HAPPY28 0x2db
	#define BTN_TRIGGER_HAPPY29 0x2dc
	#define BTN_TRIGGER_HAPPY30 0x2dd
	#define BTN_TRIGGER_HAPPY31 0x2de
	#define BTN_TRIGGER_HAPPY32 0x2df
	#define BTN_TRIGGER_HAPPY33 0x2e0
	#define BTN_TRIGGER_HAPPY34 0x2e1
	#define BTN_TRIGGER_HAPPY35 0x2e2
	#define BTN_TRIGGER_HAPPY36 0x2e3
	#define BTN_TRIGGER_HAPPY37 0x2e4
	#define BTN_TRIGGER_HAPPY38 0x2e5
	#define BTN_TRIGGER_HAPPY39 0x2e6
	#define BTN_TRIGGER_HAPPY40 0x2e7

	/* We avoid low common keys in module aliases so they don't get huge. */
	#define KEY_MIN_INTERESTING KEY_MUTE
	#define KEY_MAX 0x2ff
	#define KEY_CNT (KEY_MAX+1)

	/*
	* Relative axes
	*/

	#define REL_X 0x00
	#define REL_Y 0x01
	#define REL_Z 0x02
	#define REL_RX 0x03
	#define REL_RY 0x04
	#define REL_RZ 0x05
	#define REL_HWHEEL 0x06
	#define REL_DIAL 0x07
	#define REL_WHEEL 0x08
	#define REL_MISC 0x09
	/*
	* 0x0a is reserved and should not be used in input drivers.
	* It was used by HID as REL_MISC+1 and userspace needs to detect if
	* the next REL_* event is correct or is just REL_MISC + n.
	* We define here REL_RESERVED so userspace can rely on it and detect
	* the situation described above.
	*/
	#define REL_RESERVED 0x0a
	#define REL_WHEEL_HI_RES 0x0b
	#define REL_HWHEEL_HI_RES 0x0c
	#define REL_MAX 0x0f
	#define REL_CNT (REL_MAX+1)

	/*
	* Absolute axes
	*/

	#define ABS_X 0x00
	#define ABS_Y 0x01
	#define ABS_Z 0x02
	#define ABS_RX 0x03
	#define ABS_RY 0x04
	#define ABS_RZ 0x05
	#define ABS_THROTTLE 0x06
	#define ABS_RUDDER 0x07
	#define ABS_WHEEL 0x08
	#define ABS_GAS 0x09
	#define ABS_BRAKE 0x0a
	#define ABS_HAT0X 0x10
	#define ABS_HAT0Y 0x11
	#define ABS_HAT1X 0x12
	#define ABS_HAT1Y 0x13
	#define ABS_HAT2X 0x14
	#define ABS_HAT2Y 0x15
	#define ABS_HAT3X 0x16
	#define ABS_HAT3Y 0x17
	#define ABS_PRESSURE 0x18
	#define ABS_DISTANCE 0x19
	#define ABS_TILT_X 0x1a
	#define ABS_TILT_Y 0x1b
	#define ABS_TOOL_WIDTH 0x1c

	#define ABS_VOLUME 0x20

	#define ABS_MISC 0x28

	/*
	* 0x2e is reserved and should not be used in input drivers.
	* It was used by HID as ABS_MISC+6 and userspace needs to detect if
	* the next ABS_* event is correct or is just ABS_MISC + n.
	* We define here ABS_RESERVED so userspace can rely on it and detect
	* the situation described above.
	*/
	#define ABS_RESERVED 0x2e

	#define ABS_MT_SLOT 0x2f /* MT slot being modified */
	#define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */
	#define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */
	#define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */
	#define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */
	#define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */
	#define ABS_MT_POSITION_X 0x35 /* Center X touch position */
	#define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */
	#define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */
	#define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */
	#define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */
	#define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */
	#define ABS_MT_DISTANCE 0x3b /* Contact hover distance */
	#define ABS_MT_TOOL_X 0x3c /* Center X tool position */
	#define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */


	#define ABS_MAX 0x3f
	#define ABS_CNT (ABS_MAX+1)

	/*
	* Switch events
	*/

	#define SW_LID 0x00 /* set = lid shut */
	#define SW_TABLET_MODE 0x01 /* set = tablet mode */
	#define SW_HEADPHONE_INSERT 0x02 /* set = inserted */
	#define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any"
	set = radio enabled */
	#define SW_RADIO SW_RFKILL_ALL /* deprecated */
	#define SW_MICROPHONE_INSERT 0x04 /* set = inserted */
	#define SW_DOCK 0x05 /* set = plugged into dock */
	#define SW_LINEOUT_INSERT 0x06 /* set = inserted */
	#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */
	#define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */
	#define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */
	#define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */
	#define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */
	#define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */
	#define SW_LINEIN_INSERT 0x0d /* set = inserted */
	#define SW_MUTE_DEVICE 0x0e /* set = device disabled */
	#define SW_PEN_INSERTED 0x0f /* set = pen inserted */
	#define SW_MAX 0x0f
	#define SW_CNT (SW_MAX+1)

	/*
	* Misc events
	*/

	#define MSC_SERIAL 0x00
	#define MSC_PULSELED 0x01
	#define MSC_GESTURE 0x02
	#define MSC_RAW 0x03
	#define MSC_SCAN 0x04
	#define MSC_TIMESTAMP 0x05
	#define MSC_MAX 0x07
	#define MSC_CNT (MSC_MAX+1)

	/*
	* LEDs
	*/

	#define LED_NUML 0x00
	#define LED_CAPSL 0x01
	#define LED_SCROLLL 0x02
	#define LED_COMPOSE 0x03
	#define LED_KANA 0x04
	#define LED_SLEEP 0x05
	#define LED_SUSPEND 0x06
	#define LED_MUTE 0x07
	#define LED_MISC 0x08
	#define LED_MAIL 0x09
	#define LED_CHARGING 0x0a
	#define LED_MAX 0x0f
	#define LED_CNT (LED_MAX+1)

	/*
	* Autorepeat values
	*/

	#define REP_DELAY 0x00
	#define REP_PERIOD 0x01
	#define REP_MAX 0x01
	#define REP_CNT (REP_MAX+1)

	/*
	* Sounds
	*/

	#define SND_CLICK 0x00
	#define SND_BELL 0x01
	#define SND_TONE 0x02
	#define SND_MAX 0x07
	#define SND_CNT (SND_MAX+1)

	#endif
	diff --git a/sys/gnu/dts/include/dt-bindings/interconnect/qcom,osm-l3.h b/sys/gnu/dts/include/dt-bindings/interconnect/qcom,osm-l3.h
	new file mode 100644
	index 000000000000..54858ff7674d
	--- /dev/null
	+++ b/sys/gnu/dts/include/dt-bindings/interconnect/qcom,osm-l3.h
	@@ -0,0 +1,12 @@
	+/* SPDX-License-Identifier: GPL-2.0 */
	+/*
	+ * Copyright (C) 2019 The Linux Foundation. All rights reserved.
	+ */
	+
	+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
	+#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
	+
	+#define MASTER_OSM_L3_APPS 0
	+#define SLAVE_OSM_L3 1
	+
	+#endif
	diff --git a/sys/gnu/dts/include/dt-bindings/interconnect/qcom,sc7180.h b/sys/gnu/dts/include/dt-bindings/interconnect/qcom,sc7180.h
	new file mode 100644
	index 000000000000..f9970f6032eb
	--- /dev/null
	+++ b/sys/gnu/dts/include/dt-bindings/interconnect/qcom,sc7180.h
	@@ -0,0 +1,161 @@
	+/* SPDX-License-Identifier: GPL-2.0 */
	+/*
	+ * Qualcomm SC7180 interconnect IDs
	+ *
	+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
	+ */
	+
	+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SC7180_H
	+#define __DT_BINDINGS_INTERCONNECT_QCOM_SC7180_H
	+
	+#define MASTER_A1NOC_CFG 0
	+#define MASTER_QSPI 1
	+#define MASTER_QUP_0 2
	+#define MASTER_SDCC_2 3
	+#define MASTER_EMMC 4
	+#define MASTER_UFS_MEM 5
	+#define SLAVE_A1NOC_SNOC 6
	+#define SLAVE_SERVICE_A1NOC 7
	+
	+#define MASTER_A2NOC_CFG 0
	+#define MASTER_QDSS_BAM 1
	+#define MASTER_QUP_1 2
	+#define MASTER_USB3 3
	+#define MASTER_CRYPTO 4
	+#define MASTER_IPA 5
	+#define MASTER_QDSS_ETR 6
	+#define SLAVE_A2NOC_SNOC 7
	+#define SLAVE_SERVICE_A2NOC 8
	+
	+#define MASTER_CAMNOC_HF0_UNCOMP 0
	+#define MASTER_CAMNOC_HF1_UNCOMP 1
	+#define MASTER_CAMNOC_SF_UNCOMP 2
	+#define SLAVE_CAMNOC_UNCOMP 3
	+
	+#define MASTER_NPU 0
	+#define MASTER_NPU_PROC 1
	+#define SLAVE_CDSP_GEM_NOC 2
	+
	+#define MASTER_SNOC_CNOC 0
	+#define MASTER_QDSS_DAP 1
	+#define SLAVE_A1NOC_CFG 2
	+#define SLAVE_A2NOC_CFG 3
	+#define SLAVE_AHB2PHY_SOUTH 4
	+#define SLAVE_AHB2PHY_CENTER 5
	+#define SLAVE_AOP 6
	+#define SLAVE_AOSS 7
	+#define SLAVE_BOOT_ROM 8
	+#define SLAVE_CAMERA_CFG 9
	+#define SLAVE_CAMERA_NRT_THROTTLE_CFG 10
	+#define SLAVE_CAMERA_RT_THROTTLE_CFG 11
	+#define SLAVE_CLK_CTL 12
	+#define SLAVE_RBCPR_CX_CFG 13
	+#define SLAVE_RBCPR_MX_CFG 14
	+#define SLAVE_CRYPTO_0_CFG 15
	+#define SLAVE_DCC_CFG 16
	+#define SLAVE_CNOC_DDRSS 17
	+#define SLAVE_DISPLAY_CFG 18
	+#define SLAVE_DISPLAY_RT_THROTTLE_CFG 19
	+#define SLAVE_DISPLAY_THROTTLE_CFG 20
	+#define SLAVE_EMMC_CFG 21
	+#define SLAVE_GLM 22
	+#define SLAVE_GFX3D_CFG 23
	+#define SLAVE_IMEM_CFG 24
	+#define SLAVE_IPA_CFG 25
	+#define SLAVE_CNOC_MNOC_CFG 26
	+#define SLAVE_CNOC_MSS 27
	+#define SLAVE_NPU_CFG 28
	+#define SLAVE_NPU_DMA_BWMON_CFG 29
	+#define SLAVE_NPU_PROC_BWMON_CFG 30
	+#define SLAVE_PDM 31
	+#define SLAVE_PIMEM_CFG 32
	+#define SLAVE_PRNG 33
	+#define SLAVE_QDSS_CFG 34
	+#define SLAVE_QM_CFG 35
	+#define SLAVE_QM_MPU_CFG 36
	+#define SLAVE_QSPI_0 37
	+#define SLAVE_QUP_0 38
	+#define SLAVE_QUP_1 39
	+#define SLAVE_SDCC_2 40
	+#define SLAVE_SECURITY 41
	+#define SLAVE_SNOC_CFG 42
	+#define SLAVE_TCSR 43
	+#define SLAVE_TLMM_WEST 44
	+#define SLAVE_TLMM_NORTH 45
	+#define SLAVE_TLMM_SOUTH 46
	+#define SLAVE_UFS_MEM_CFG 47
	+#define SLAVE_USB3 48
	+#define SLAVE_VENUS_CFG 49
	+#define SLAVE_VENUS_THROTTLE_CFG 50
	+#define SLAVE_VSENSE_CTRL_CFG 51
	+#define SLAVE_SERVICE_CNOC 52
	+
	+#define MASTER_CNOC_DC_NOC 0
	+#define SLAVE_GEM_NOC_CFG 1
	+#define SLAVE_LLCC_CFG 2
	+
	+#define MASTER_APPSS_PROC 0
	+#define MASTER_SYS_TCU 1
	+#define MASTER_GEM_NOC_CFG 2
	+#define MASTER_COMPUTE_NOC 3
	+#define MASTER_MNOC_HF_MEM_NOC 4
	+#define MASTER_MNOC_SF_MEM_NOC 5
	+#define MASTER_SNOC_GC_MEM_NOC 6
	+#define MASTER_SNOC_SF_MEM_NOC 7
	+#define MASTER_GFX3D 8
	+#define SLAVE_MSS_PROC_MS_MPU_CFG 9
	+#define SLAVE_GEM_NOC_SNOC 10
	+#define SLAVE_LLCC 11
	+#define SLAVE_SERVICE_GEM_NOC 12
	+
	+#define MASTER_IPA_CORE 0
	+#define SLAVE_IPA_CORE 1
	+
	+#define MASTER_LLCC 0
	+#define SLAVE_EBI1 1
	+
	+#define MASTER_CNOC_MNOC_CFG 0
	+#define MASTER_CAMNOC_HF0 1
	+#define MASTER_CAMNOC_HF1 2
	+#define MASTER_CAMNOC_SF 3
	+#define MASTER_MDP0 4
	+#define MASTER_ROTATOR 5
	+#define MASTER_VIDEO_P0 6
	+#define MASTER_VIDEO_PROC 7
	+#define SLAVE_MNOC_HF_MEM_NOC 8
	+#define SLAVE_MNOC_SF_MEM_NOC 9
	+#define SLAVE_SERVICE_MNOC 10
	+
	+#define MASTER_NPU_SYS 0
	+#define MASTER_NPU_NOC_CFG 1
	+#define SLAVE_NPU_CAL_DP0 2
	+#define SLAVE_NPU_CP 3
	+#define SLAVE_NPU_INT_DMA_BWMON_CFG 4
	+#define SLAVE_NPU_DPM 5
	+#define SLAVE_ISENSE_CFG 6
	+#define SLAVE_NPU_LLM_CFG 7
	+#define SLAVE_NPU_TCM 8
	+#define SLAVE_NPU_COMPUTE_NOC 9
	+#define SLAVE_SERVICE_NPU_NOC 10
	+
	+#define MASTER_QUP_CORE_0 0
	+#define MASTER_QUP_CORE_1 1
	+#define SLAVE_QUP_CORE_0 2
	+#define SLAVE_QUP_CORE_1 3
	+
	+#define MASTER_SNOC_CFG 0
	+#define MASTER_A1NOC_SNOC 1
	+#define MASTER_A2NOC_SNOC 2
	+#define MASTER_GEM_NOC_SNOC 3
	+#define MASTER_PIMEM 4
	+#define SLAVE_APPSS 5
	+#define SLAVE_SNOC_CNOC 6
	+#define SLAVE_SNOC_GEM_NOC_GC 7
	+#define SLAVE_SNOC_GEM_NOC_SF 8
	+#define SLAVE_IMEM 9
	+#define SLAVE_PIMEM 10
	+#define SLAVE_SERVICE_SNOC 11
	+#define SLAVE_QDSS_STM 12
	+#define SLAVE_TCU 13
	+
	+#endif
	diff --git a/sys/gnu/dts/include/dt-bindings/interconnect/qcom,sdm845.h b/sys/gnu/dts/include/dt-bindings/interconnect/qcom,sdm845.h
	index 7b2393be7361..290be38f40e6 100644
	--- a/sys/gnu/dts/include/dt-bindings/interconnect/qcom,sdm845.h
	+++ b/sys/gnu/dts/include/dt-bindings/interconnect/qcom,sdm845.h
	@@ -1,143 +1,148 @@
	/* SPDX-License-Identifier: GPL-2.0 */
	/*
	* Qualcomm SDM845 interconnect IDs
	*
	* Copyright (c) 2018, Linaro Ltd.
	* Author: Georgi Djakov <georgi.djakov@linaro.org>
	*/

	#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H
	#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H

	#define MASTER_A1NOC_CFG 0
	-#define MASTER_BLSP_1 1
	-#define MASTER_TSIF 2
	-#define MASTER_SDCC_2 3
	-#define MASTER_SDCC_4 4
	-#define MASTER_UFS_CARD 5
	-#define MASTER_UFS_MEM 6
	-#define MASTER_PCIE_0 7
	-#define MASTER_A2NOC_CFG 8
	-#define MASTER_QDSS_BAM 9
	-#define MASTER_BLSP_2 10
	-#define MASTER_CNOC_A2NOC 11
	-#define MASTER_CRYPTO 12
	-#define MASTER_IPA 13
	-#define MASTER_PCIE_1 14
	-#define MASTER_QDSS_ETR 15
	-#define MASTER_USB3_0 16
	-#define MASTER_USB3_1 17
	-#define MASTER_CAMNOC_HF0_UNCOMP 18
	-#define MASTER_CAMNOC_HF1_UNCOMP 19
	-#define MASTER_CAMNOC_SF_UNCOMP 20
	-#define MASTER_SPDM 21
	-#define MASTER_TIC 22
	-#define MASTER_SNOC_CNOC 23
	-#define MASTER_QDSS_DAP 24
	-#define MASTER_CNOC_DC_NOC 25
	-#define MASTER_APPSS_PROC 26
	-#define MASTER_GNOC_CFG 27
	-#define MASTER_LLCC 28
	-#define MASTER_TCU_0 29
	-#define MASTER_MEM_NOC_CFG 30
	-#define MASTER_GNOC_MEM_NOC 31
	-#define MASTER_MNOC_HF_MEM_NOC 32
	-#define MASTER_MNOC_SF_MEM_NOC 33
	-#define MASTER_SNOC_GC_MEM_NOC 34
	-#define MASTER_SNOC_SF_MEM_NOC 35
	-#define MASTER_GFX3D 36
	-#define MASTER_CNOC_MNOC_CFG 37
	-#define MASTER_CAMNOC_HF0 38
	-#define MASTER_CAMNOC_HF1 39
	-#define MASTER_CAMNOC_SF 40
	-#define MASTER_MDP0 41
	-#define MASTER_MDP1 42
	-#define MASTER_ROTATOR 43
	-#define MASTER_VIDEO_P0 44
	-#define MASTER_VIDEO_P1 45
	-#define MASTER_VIDEO_PROC 46
	-#define MASTER_SNOC_CFG 47
	-#define MASTER_A1NOC_SNOC 48
	-#define MASTER_A2NOC_SNOC 49
	-#define MASTER_GNOC_SNOC 50
	-#define MASTER_MEM_NOC_SNOC 51
	-#define MASTER_ANOC_PCIE_SNOC 52
	-#define MASTER_PIMEM 53
	-#define MASTER_GIC 54
	-#define SLAVE_A1NOC_SNOC 55
	-#define SLAVE_SERVICE_A1NOC 56
	-#define SLAVE_ANOC_PCIE_A1NOC_SNOC 57
	-#define SLAVE_A2NOC_SNOC 58
	-#define SLAVE_ANOC_PCIE_SNOC 59
	-#define SLAVE_SERVICE_A2NOC 60
	-#define SLAVE_CAMNOC_UNCOMP 61
	-#define SLAVE_A1NOC_CFG 62
	-#define SLAVE_A2NOC_CFG 63
	-#define SLAVE_AOP 64
	-#define SLAVE_AOSS 65
	-#define SLAVE_CAMERA_CFG 66
	-#define SLAVE_CLK_CTL 67
	-#define SLAVE_CDSP_CFG 68
	-#define SLAVE_RBCPR_CX_CFG 69
	-#define SLAVE_CRYPTO_0_CFG 70
	-#define SLAVE_DCC_CFG 71
	-#define SLAVE_CNOC_DDRSS 72
	-#define SLAVE_DISPLAY_CFG 73
	-#define SLAVE_GLM 74
	-#define SLAVE_GFX3D_CFG 75
	-#define SLAVE_IMEM_CFG 76
	-#define SLAVE_IPA_CFG 77
	-#define SLAVE_CNOC_MNOC_CFG 78
	-#define SLAVE_PCIE_0_CFG 79
	-#define SLAVE_PCIE_1_CFG 80
	-#define SLAVE_PDM 81
	-#define SLAVE_SOUTH_PHY_CFG 82
	-#define SLAVE_PIMEM_CFG 83
	-#define SLAVE_PRNG 84
	-#define SLAVE_QDSS_CFG 85
	-#define SLAVE_BLSP_2 86
	-#define SLAVE_BLSP_1 87
	-#define SLAVE_SDCC_2 88
	-#define SLAVE_SDCC_4 89
	-#define SLAVE_SNOC_CFG 90
	-#define SLAVE_SPDM_WRAPPER 91
	-#define SLAVE_SPSS_CFG 92
	-#define SLAVE_TCSR 93
	-#define SLAVE_TLMM_NORTH 94
	-#define SLAVE_TLMM_SOUTH 95
	-#define SLAVE_TSIF 96
	-#define SLAVE_UFS_CARD_CFG 97
	-#define SLAVE_UFS_MEM_CFG 98
	-#define SLAVE_USB3_0 99
	-#define SLAVE_USB3_1 100
	-#define SLAVE_VENUS_CFG 101
	-#define SLAVE_VSENSE_CTRL_CFG 102
	-#define SLAVE_CNOC_A2NOC 103
	-#define SLAVE_SERVICE_CNOC 104
	-#define SLAVE_LLCC_CFG 105
	-#define SLAVE_MEM_NOC_CFG 106
	-#define SLAVE_GNOC_SNOC 107
	-#define SLAVE_GNOC_MEM_NOC 108
	-#define SLAVE_SERVICE_GNOC 109
	-#define SLAVE_EBI1 110
	-#define SLAVE_MSS_PROC_MS_MPU_CFG 111
	-#define SLAVE_MEM_NOC_GNOC 112
	-#define SLAVE_LLCC 113
	-#define SLAVE_MEM_NOC_SNOC 114
	-#define SLAVE_SERVICE_MEM_NOC 115
	-#define SLAVE_MNOC_SF_MEM_NOC 116
	-#define SLAVE_MNOC_HF_MEM_NOC 117
	-#define SLAVE_SERVICE_MNOC 118
	-#define SLAVE_APPSS 119
	-#define SLAVE_SNOC_CNOC 120
	-#define SLAVE_SNOC_MEM_NOC_GC 121
	-#define SLAVE_SNOC_MEM_NOC_SF 122
	-#define SLAVE_IMEM 123
	-#define SLAVE_PCIE_0 124
	-#define SLAVE_PCIE_1 125
	-#define SLAVE_PIMEM 126
	-#define SLAVE_SERVICE_SNOC 127
	-#define SLAVE_QDSS_STM 128
	-#define SLAVE_TCU 129
	+#define MASTER_TSIF 1
	+#define MASTER_SDCC_2 2
	+#define MASTER_SDCC_4 3
	+#define MASTER_UFS_CARD 4
	+#define MASTER_UFS_MEM 5
	+#define MASTER_PCIE_0 6
	+#define SLAVE_A1NOC_SNOC 7
	+#define SLAVE_SERVICE_A1NOC 8
	+#define SLAVE_ANOC_PCIE_A1NOC_SNOC 9
	+
	+#define MASTER_A2NOC_CFG 0
	+#define MASTER_QDSS_BAM 1
	+#define MASTER_CNOC_A2NOC 2
	+#define MASTER_CRYPTO 3
	+#define MASTER_IPA 4
	+#define MASTER_PCIE_1 5
	+#define MASTER_QDSS_ETR 6
	+#define MASTER_USB3_0 7
	+#define MASTER_USB3_1 8
	+#define SLAVE_A2NOC_SNOC 9
	+#define SLAVE_ANOC_PCIE_SNOC 10
	+#define SLAVE_SERVICE_A2NOC 11
	+
	+#define MASTER_SPDM 0
	+#define MASTER_TIC 1
	+#define MASTER_SNOC_CNOC 2
	+#define MASTER_QDSS_DAP 3
	+#define SLAVE_A1NOC_CFG 4
	+#define SLAVE_A2NOC_CFG 5
	+#define SLAVE_AOP 6
	+#define SLAVE_AOSS 7
	+#define SLAVE_CAMERA_CFG 8
	+#define SLAVE_CLK_CTL 9
	+#define SLAVE_CDSP_CFG 10
	+#define SLAVE_RBCPR_CX_CFG 11
	+#define SLAVE_CRYPTO_0_CFG 12
	+#define SLAVE_DCC_CFG 13
	+#define SLAVE_CNOC_DDRSS 14
	+#define SLAVE_DISPLAY_CFG 15
	+#define SLAVE_GLM 16
	+#define SLAVE_GFX3D_CFG 17
	+#define SLAVE_IMEM_CFG 18
	+#define SLAVE_IPA_CFG 19
	+#define SLAVE_CNOC_MNOC_CFG 20
	+#define SLAVE_PCIE_0_CFG 21
	+#define SLAVE_PCIE_1_CFG 22
	+#define SLAVE_PDM 23
	+#define SLAVE_SOUTH_PHY_CFG 24
	+#define SLAVE_PIMEM_CFG 25
	+#define SLAVE_PRNG 26
	+#define SLAVE_QDSS_CFG 27
	+#define SLAVE_BLSP_2 28
	+#define SLAVE_BLSP_1 29
	+#define SLAVE_SDCC_2 30
	+#define SLAVE_SDCC_4 31
	+#define SLAVE_SNOC_CFG 32
	+#define SLAVE_SPDM_WRAPPER 33
	+#define SLAVE_SPSS_CFG 34
	+#define SLAVE_TCSR 35
	+#define SLAVE_TLMM_NORTH 36
	+#define SLAVE_TLMM_SOUTH 37
	+#define SLAVE_TSIF 38
	+#define SLAVE_UFS_CARD_CFG 39
	+#define SLAVE_UFS_MEM_CFG 40
	+#define SLAVE_USB3_0 41
	+#define SLAVE_USB3_1 42
	+#define SLAVE_VENUS_CFG 43
	+#define SLAVE_VSENSE_CTRL_CFG 44
	+#define SLAVE_CNOC_A2NOC 45
	+#define SLAVE_SERVICE_CNOC 46
	+
	+#define MASTER_CNOC_DC_NOC 0
	+#define SLAVE_LLCC_CFG 1
	+#define SLAVE_MEM_NOC_CFG 2
	+
	+#define MASTER_APPSS_PROC 0
	+#define MASTER_GNOC_CFG 1
	+#define SLAVE_GNOC_SNOC 2
	+#define SLAVE_GNOC_MEM_NOC 3
	+#define SLAVE_SERVICE_GNOC 4
	+
	+#define MASTER_TCU_0 0
	+#define MASTER_MEM_NOC_CFG 1
	+#define MASTER_GNOC_MEM_NOC 2
	+#define MASTER_MNOC_HF_MEM_NOC 3
	+#define MASTER_MNOC_SF_MEM_NOC 4
	+#define MASTER_SNOC_GC_MEM_NOC 5
	+#define MASTER_SNOC_SF_MEM_NOC 6
	+#define MASTER_GFX3D 7
	+#define SLAVE_MSS_PROC_MS_MPU_CFG 8
	+#define SLAVE_MEM_NOC_GNOC 9
	+#define SLAVE_LLCC 10
	+#define SLAVE_MEM_NOC_SNOC 11
	+#define SLAVE_SERVICE_MEM_NOC 12
	+#define MASTER_LLCC 13
	+#define SLAVE_EBI1 14
	+
	+#define MASTER_CNOC_MNOC_CFG 0
	+#define MASTER_CAMNOC_HF0 1
	+#define MASTER_CAMNOC_HF1 2
	+#define MASTER_CAMNOC_SF 3
	+#define MASTER_MDP0 4
	+#define MASTER_MDP1 5
	+#define MASTER_ROTATOR 6
	+#define MASTER_VIDEO_P0 7
	+#define MASTER_VIDEO_P1 8
	+#define MASTER_VIDEO_PROC 9
	+#define SLAVE_MNOC_SF_MEM_NOC 10
	+#define SLAVE_MNOC_HF_MEM_NOC 11
	+#define SLAVE_SERVICE_MNOC 12
	+#define MASTER_CAMNOC_HF0_UNCOMP 13
	+#define MASTER_CAMNOC_HF1_UNCOMP 14
	+#define MASTER_CAMNOC_SF_UNCOMP 15
	+#define SLAVE_CAMNOC_UNCOMP 16
	+
	+#define MASTER_SNOC_CFG 0
	+#define MASTER_A1NOC_SNOC 1
	+#define MASTER_A2NOC_SNOC 2
	+#define MASTER_GNOC_SNOC 3
	+#define MASTER_MEM_NOC_SNOC 4
	+#define MASTER_ANOC_PCIE_SNOC 5
	+#define MASTER_PIMEM 6
	+#define MASTER_GIC 7
	+#define SLAVE_APPSS 8
	+#define SLAVE_SNOC_CNOC 9
	+#define SLAVE_SNOC_MEM_NOC_GC 10
	+#define SLAVE_SNOC_MEM_NOC_SF 11
	+#define SLAVE_IMEM 12
	+#define SLAVE_PCIE_0 13
	+#define SLAVE_PCIE_1 14
	+#define SLAVE_PIMEM 15
	+#define SLAVE_SERVICE_SNOC 16
	+#define SLAVE_QDSS_STM 17
	+#define SLAVE_TCU 18

	#endif
	diff --git a/sys/gnu/dts/include/dt-bindings/leds/common.h b/sys/gnu/dts/include/dt-bindings/leds/common.h
	index 9e1256a7c1bf..0ce7dfc00dcb 100644
	--- a/sys/gnu/dts/include/dt-bindings/leds/common.h
	+++ b/sys/gnu/dts/include/dt-bindings/leds/common.h
	@@ -1,75 +1,91 @@
	/* SPDX-License-Identifier: GPL-2.0 */
	/*
	* This header provides macros for the common LEDs device tree bindings.
	*
	* Copyright (C) 2015, Samsung Electronics Co., Ltd.
	* Author: Jacek Anaszewski <j.anaszewski@samsung.com>
	*
	* Copyright (C) 2019 Jacek Anaszewski <jacek.anaszewski@gmail.com>
	+ * Copyright (C) 2020 Pavel Machek <pavel@ucw.cz>
	*/

	#ifndef __DT_BINDINGS_LEDS_H
	#define __DT_BINDINGS_LEDS_H

	/* External trigger type */
	#define LEDS_TRIG_TYPE_EDGE 0
	#define LEDS_TRIG_TYPE_LEVEL 1

	/* Boost modes */
	#define LEDS_BOOST_OFF 0
	#define LEDS_BOOST_ADAPTIVE 1
	#define LEDS_BOOST_FIXED 2

	/* Standard LED colors */
	#define LED_COLOR_ID_WHITE 0
	#define LED_COLOR_ID_RED 1
	#define LED_COLOR_ID_GREEN 2
	#define LED_COLOR_ID_BLUE 3
	#define LED_COLOR_ID_AMBER 4
	#define LED_COLOR_ID_VIOLET 5
	#define LED_COLOR_ID_YELLOW 6
	#define LED_COLOR_ID_IR 7
	#define LED_COLOR_ID_MAX 8

	/* Standard LED functions */
	+/* Keyboard LEDs, usually it would be input4::capslock etc. */
	+/* Obsolete equivalent: "shift-key-light" */
	+#define LED_FUNCTION_CAPSLOCK "capslock"
	+#define LED_FUNCTION_SCROLLLOCK "scrolllock"
	+#define LED_FUNCTION_NUMLOCK "numlock"
	+/* Obsolete equivalents: "tpacpi::thinklight" (IBM/Lenovo Thinkpads),
	+ "lp5523:kb{1,2,3,4,5,6}" (Nokia N900) */
	+#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight"
	+
	+/* System LEDs, usually found on system body.
	+ platform::mute (etc) is sometimes seen, :mute would be better */
	+#define LED_FUNCTION_POWER "power"
	+#define LED_FUNCTION_DISK "disk"
	+
	+/* Obsolete: "platform::charging" (allwinner sun50i) /
	+#define LED_FUNCTION_CHARGING "charging"
	+/* Used RGB notification LEDs common on phones.
	+ Obsolete equivalents: "status-led:{red,green,blue}" (Motorola Droid 4),
	+ "lp5523:{r,g,b}" (Nokia N900) */
	+#define LED_FUNCTION_STATUS "status"
	+
	+#define LED_FUNCTION_MICMUTE "micmute"
	+#define LED_FUNCTION_MUTE "mute"
	+
	+/* Miscelleaus functions. Use functions above if you can. */
	#define LED_FUNCTION_ACTIVITY "activity"
	#define LED_FUNCTION_ALARM "alarm"
	#define LED_FUNCTION_BACKLIGHT "backlight"
	#define LED_FUNCTION_BLUETOOTH "bluetooth"
	#define LED_FUNCTION_BOOT "boot"
	#define LED_FUNCTION_CPU "cpu"
	-#define LED_FUNCTION_CAPSLOCK "capslock"
	-#define LED_FUNCTION_CHARGING "charging"
	#define LED_FUNCTION_DEBUG "debug"
	-#define LED_FUNCTION_DISK "disk"
	#define LED_FUNCTION_DISK_ACTIVITY "disk-activity"
	#define LED_FUNCTION_DISK_ERR "disk-err"
	#define LED_FUNCTION_DISK_READ "disk-read"
	#define LED_FUNCTION_DISK_WRITE "disk-write"
	#define LED_FUNCTION_FAULT "fault"
	#define LED_FUNCTION_FLASH "flash"
	#define LED_FUNCTION_HEARTBEAT "heartbeat"
	#define LED_FUNCTION_INDICATOR "indicator"
	-#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight"
	#define LED_FUNCTION_LAN "lan"
	#define LED_FUNCTION_MAIL "mail"
	#define LED_FUNCTION_MTD "mtd"
	-#define LED_FUNCTION_MICMUTE "micmute"
	-#define LED_FUNCTION_MUTE "mute"
	-#define LED_FUNCTION_NUMLOCK "numlock"
	#define LED_FUNCTION_PANIC "panic"
	#define LED_FUNCTION_PROGRAMMING "programming"
	-#define LED_FUNCTION_POWER "power"
	#define LED_FUNCTION_RX "rx"
	#define LED_FUNCTION_SD "sd"
	-#define LED_FUNCTION_SCROLLLOCK "scrolllock"
	#define LED_FUNCTION_STANDBY "standby"
	-#define LED_FUNCTION_STATUS "status"
	#define LED_FUNCTION_TORCH "torch"
	#define LED_FUNCTION_TX "tx"
	#define LED_FUNCTION_USB "usb"
	#define LED_FUNCTION_WAN "wan"
	#define LED_FUNCTION_WLAN "wlan"
	#define LED_FUNCTION_WPS "wps"

	#endif /* __DT_BINDINGS_LEDS_H */
	diff --git a/sys/gnu/dts/include/dt-bindings/media/tvp5150.h b/sys/gnu/dts/include/dt-bindings/media/tvp5150.h
	index 01eedf4985b8..dda00c038530 100644
	--- a/sys/gnu/dts/include/dt-bindings/media/tvp5150.h
	+++ b/sys/gnu/dts/include/dt-bindings/media/tvp5150.h
	@@ -1,23 +1,21 @@
	/* SPDX-License-Identifier: GPL-2.0-or-later */
	/*
	tvp5150.h - definition for tvp5150 inputs

	Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)

	*/

	#ifndef _DT_BINDINGS_MEDIA_TVP5150_H
	#define _DT_BINDINGS_MEDIA_TVP5150_H

	/* TVP5150 HW inputs */
	#define TVP5150_COMPOSITE0 0
	#define TVP5150_COMPOSITE1 1
	#define TVP5150_SVIDEO 2

	-#define TVP5150_INPUT_NUM 3
	-
	/* TVP5150 HW outputs */
	#define TVP5150_NORMAL 0
	#define TVP5150_BLACK_SCREEN 1

	#endif /* _DT_BINDINGS_MEDIA_TVP5150_H */
	diff --git a/sys/gnu/dts/include/dt-bindings/power/meson-a1-power.h b/sys/gnu/dts/include/dt-bindings/power/meson-a1-power.h
	new file mode 100644
	index 000000000000..6cf50bfb8ccf
	--- /dev/null
	+++ b/sys/gnu/dts/include/dt-bindings/power/meson-a1-power.h
	@@ -0,0 +1,32 @@
	+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
	+/*
	+ * Copyright (c) 2019 Amlogic, Inc.
	+ * Author: Jianxin Pan <jianxin.pan@amlogic.com>
	+ */
	+
	+#ifndef _DT_BINDINGS_MESON_A1_POWER_H
	+#define _DT_BINDINGS_MESON_A1_POWER_H
	+
	+#define PWRC_DSPA_ID 8
	+#define PWRC_DSPB_ID 9
	+#define PWRC_UART_ID 10
	+#define PWRC_DMC_ID 11
	+#define PWRC_I2C_ID 12
	+#define PWRC_PSRAM_ID 13
	+#define PWRC_ACODEC_ID 14
	+#define PWRC_AUDIO_ID 15
	+#define PWRC_OTP_ID 16
	+#define PWRC_DMA_ID 17
	+#define PWRC_SD_EMMC_ID 18
	+#define PWRC_RAMA_ID 19
	+#define PWRC_RAMB_ID 20
	+#define PWRC_IR_ID 21
	+#define PWRC_SPICC_ID 22
	+#define PWRC_SPIFC_ID 23
	+#define PWRC_USB_ID 24
	+#define PWRC_NIC_ID 25
	+#define PWRC_PDMIN_ID 26
	+#define PWRC_RSA_ID 27
	+#define PWRC_MAX_ID 28
	+
	+#endif
	diff --git a/sys/gnu/dts/include/dt-bindings/soc/tegra-pmc.h b/sys/gnu/dts/include/dt-bindings/soc/tegra-pmc.h
	new file mode 100644
	index 000000000000..a99a457471ee
	--- /dev/null
	+++ b/sys/gnu/dts/include/dt-bindings/soc/tegra-pmc.h
	@@ -0,0 +1,16 @@
	+/* SPDX-License-Identifier: GPL-2.0-only */
	+/*
	+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
	+ */
	+
	+#ifndef _DT_BINDINGS_SOC_TEGRA_PMC_H
	+#define _DT_BINDINGS_SOC_TEGRA_PMC_H
	+
	+#define TEGRA_PMC_CLK_OUT_1 0
	+#define TEGRA_PMC_CLK_OUT_2 1
	+#define TEGRA_PMC_CLK_OUT_3 2
	+#define TEGRA_PMC_CLK_BLINK 3
	+
	+#define TEGRA_PMC_CLK_MAX 4
	+
	+#endif /* _DT_BINDINGS_SOC_TEGRA_PMC_H */
	diff --git a/sys/gnu/dts/include/dt-bindings/sound/meson-aiu.h b/sys/gnu/dts/include/dt-bindings/sound/meson-aiu.h
	new file mode 100644
	index 000000000000..1051b8af298b
	--- /dev/null
	+++ b/sys/gnu/dts/include/dt-bindings/sound/meson-aiu.h
	@@ -0,0 +1,18 @@
	+/* SPDX-License-Identifier: GPL-2.0 */
	+#ifndef __DT_MESON_AIU_H
	+#define __DT_MESON_AIU_H
	+
	+#define AIU_CPU 0
	+#define AIU_HDMI 1
	+#define AIU_ACODEC 2
	+
	+#define CPU_I2S_FIFO 0
	+#define CPU_SPDIF_FIFO 1
	+#define CPU_I2S_ENCODER 2
	+#define CPU_SPDIF_ENCODER 3
	+
	+#define CTRL_I2S 0
	+#define CTRL_PCM 1
	+#define CTRL_OUT 2
	+
	+#endif /* __DT_MESON_AIU_H */
	diff --git a/sys/gnu/dts/include/dt-bindings/sound/meson-g12a-toacodec.h b/sys/gnu/dts/include/dt-bindings/sound/meson-g12a-toacodec.h
	new file mode 100644
	index 000000000000..69d7a75592a2
	--- /dev/null
	+++ b/sys/gnu/dts/include/dt-bindings/sound/meson-g12a-toacodec.h
	@@ -0,0 +1,10 @@
	+/* SPDX-License-Identifier: GPL-2.0 */
	+#ifndef __DT_MESON_G12A_TOACODEC_H
	+#define __DT_MESON_G12A_TOACODEC_H
	+
	+#define TOACODEC_IN_A 0
	+#define TOACODEC_IN_B 1
	+#define TOACODEC_IN_C 2
	+#define TOACODEC_OUT 3
	+
	+#endif /* __DT_MESON_G12A_TOACODEC_H */
	diff --git a/sys/gnu/dts/riscv/kendryte/k210.dts b/sys/gnu/dts/riscv/kendryte/k210.dts
	new file mode 100644
	index 000000000000..0d1f28fce6b2
	--- /dev/null
	+++ b/sys/gnu/dts/riscv/kendryte/k210.dts
	@@ -0,0 +1,23 @@
	+// SPDX-License-Identifier: GPL-2.0+
	+/*
	+ * Copyright (C) 2020 Western Digital Corporation or its affiliates.
	+ */
	+
	+/dts-v1/;
	+
	+#include "k210.dtsi"
	+
	+/ {
	+ model = "Kendryte K210 generic";
	+ compatible = "kendryte,k210";
	+
	+ chosen {
	+ bootargs = "earlycon console=ttySIF0";
	+ stdout-path = "serial0";
	+ };
	+};
	+
	+&uarths0 {
	+ status = "okay";
	+};
	+
	diff --git a/sys/gnu/dts/riscv/kendryte/k210.dtsi b/sys/gnu/dts/riscv/kendryte/k210.dtsi
	new file mode 100644
	index 000000000000..c1df56ccb8d5
	--- /dev/null
	+++ b/sys/gnu/dts/riscv/kendryte/k210.dtsi
	@@ -0,0 +1,123 @@
	+// SPDX-License-Identifier: GPL-2.0+
	+/*
	+ * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
	+ * Copyright (C) 2020 Western Digital Corporation or its affiliates.
	+ */
	+#include <dt-bindings/clock/k210-clk.h>
	+
	+/ {
	+ /*
	+ * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
	+ * wide, and the upper half of all addresses is ignored.
	+ */
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ compatible = "kendryte,k210";
	+
	+ aliases {
	+ serial0 = &uarths0;
	+ };
	+
	+ /*
	+ * The K210 has an sv39 MMU following the priviledge specification v1.9.
	+ * Since this is a non-ratified draft specification, the kernel does not
	+ * support it and the K210 support enabled only for the !MMU case.
	+ * Be consistent with this by setting the CPUs MMU type to "none".
	+ */
	+ cpus {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+ timebase-frequency = <7800000>;
	+ cpu0: cpu@0 {
	+ device_type = "cpu";
	+ reg = <0>;
	+ compatible = "kendryte,k210", "sifive,rocket0", "riscv";
	+ riscv,isa = "rv64imafdc";
	+ mmu-type = "none";
	+ i-cache-size = <0x8000>;
	+ i-cache-block-size = <64>;
	+ d-cache-size = <0x8000>;
	+ d-cache-block-size = <64>;
	+ clocks = <&sysctl K210_CLK_CPU>;
	+ clock-frequency = <390000000>;
	+ cpu0_intc: interrupt-controller {
	+ #interrupt-cells = <1>;
	+ interrupt-controller;
	+ compatible = "riscv,cpu-intc";
	+ };
	+ };
	+ cpu1: cpu@1 {
	+ device_type = "cpu";
	+ reg = <1>;
	+ compatible = "kendryte,k210", "sifive,rocket0", "riscv";
	+ riscv,isa = "rv64imafdc";
	+ mmu-type = "none";
	+ i-cache-size = <0x8000>;
	+ i-cache-block-size = <64>;
	+ d-cache-size = <0x8000>;
	+ d-cache-block-size = <64>;
	+ clocks = <&sysctl K210_CLK_CPU>;
	+ clock-frequency = <390000000>;
	+ cpu1_intc: interrupt-controller {
	+ #interrupt-cells = <1>;
	+ interrupt-controller;
	+ compatible = "riscv,cpu-intc";
	+ };
	+ };
	+ };
	+
	+ sram: memory@80000000 {
	+ device_type = "memory";
	+ reg = <0x80000000 0x400000>,
	+ <0x80400000 0x200000>,
	+ <0x80600000 0x200000>;
	+ reg-names = "sram0", "sram1", "aisram";
	+ };
	+
	+ clocks {
	+ in0: oscillator {
	+ compatible = "fixed-clock";
	+ #clock-cells = <0>;
	+ clock-frequency = <26000000>;
	+ };
	+ };
	+
	+ soc {
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ compatible = "kendryte,k210-soc", "simple-bus";
	+ ranges;
	+ interrupt-parent = <&plic0>;
	+
	+ sysctl: sysctl@50440000 {
	+ compatible = "kendryte,k210-sysctl", "simple-mfd";
	+ reg = <0x50440000 0x1000>;
	+ #clock-cells = <1>;
	+ };
	+
	+ clint0: interrupt-controller@2000000 {
	+ compatible = "riscv,clint0";
	+ reg = <0x2000000 0xC000>;
	+ interrupts-extended = <&cpu0_intc 3>, <&cpu1_intc 3>;
	+ clocks = <&sysctl K210_CLK_ACLK>;
	+ };
	+
	+ plic0: interrupt-controller@c000000 {
	+ #interrupt-cells = <1>;
	+ interrupt-controller;
	+ compatible = "kendryte,k210-plic0", "riscv,plic0";
	+ reg = <0xC000000 0x4000000>;
	+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 0xffffffff>,
	+ <&cpu1_intc 11>, <&cpu1_intc 0xffffffff>;
	+ riscv,ndev = <65>;
	+ riscv,max-priority = <7>;
	+ };
	+
	+ uarths0: serial@38000000 {
	+ compatible = "kendryte,k210-uarths", "sifive,uart0";
	+ reg = <0x38000000 0x1000>;
	+ interrupts = <33>;
	+ clocks = <&sysctl K210_CLK_CPU>;
	+ };
	+ };
	+};

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