diff --git a/sys/gnu/dts/arm/am335x-baltos.dtsi b/sys/gnu/dts/arm/am335x-baltos.dtsi index 05e7b5d4a95b..ed235f263e29 100644 --- a/sys/gnu/dts/arm/am335x-baltos.dtsi +++ b/sys/gnu/dts/arm/am335x-baltos.dtsi @@ -1,402 +1,414 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ /* * VScom OnRISC * http://www.vscom.de */ #include "am33xx.dtsi" #include #include / { compatible = "vscom,onrisc", "ti,am33xx"; cpus { cpu@0 { cpu0-supply = <&vdd1_reg>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-boot-on; }; wl12xx_vmmc: fixedregulator2 { pinctrl-names = "default"; pinctrl-0 = <&wl12xx_gpio>; compatible = "regulator-fixed"; regulator-name = "vwl1271"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio3 8 0>; startup-delay-us = <70000>; enable-active-high; }; }; &am33xx_pinmux { mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */ AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLUP, MUX_MODE7) /* emu0.gpio3[7] */ >; }; wl12xx_gpio: pinmux_wl12xx_gpio { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */ >; }; tps65910_pins: pinmux_tps65910_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ben1.gpio1[28] */ >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_tx_en.rmii1_txen */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ /* Slave 2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* Slave 2 reset value*/ AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data.mdio_data */ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk.mdio_clk */ >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; nandflash_pins_s0: nandflash_pins_s0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) /* gpmc_wen.gpmc_wen */ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ >; }; }; &elm { status = "okay"; }; &gpmc { pinctrl-names = "default"; pinctrl-0 = <&nandflash_pins_s0>; ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ status = "okay"; nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ nand-bus-width = <8>; ti,nand-ecc-opt = "bch8"; ti,nand-xfer-type = "polled"; gpmc,device-nand = "true"; gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <44>; gpmc,cs-wr-off-ns = <44>; gpmc,adv-on-ns = <6>; gpmc,adv-rd-off-ns = <34>; gpmc,adv-wr-off-ns = <44>; gpmc,we-on-ns = <0>; gpmc,we-off-ns = <40>; gpmc,oe-on-ns = <0>; gpmc,oe-off-ns = <54>; gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; #address-cells = <1>; #size-cells = <1>; ti,elm-id = <&elm>; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; status = "okay"; clock-frequency = <400000>; tps: tps@2d { reg = <0x2d>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&gpio1>; interrupts = <28 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&tps65910_pins>; }; at24@50 { compatible = "atmel,24c02"; pagesize = <8>; reg = <0x50>; }; }; +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&cppi41dma { + status = "okay"; +}; + #include "tps65910.dtsi" &tps { vcc1-supply = <&vbat>; vcc2-supply = <&vbat>; vcc3-supply = <&vbat>; vcc4-supply = <&vbat>; vcc5-supply = <&vbat>; vcc6-supply = <&vbat>; vcc7-supply = <&vbat>; vccio-supply = <&vbat>; ti,en-ck32k-xtal = <1>; regulators { vrtc_reg: regulator@0 { regulator-always-on; }; vio_reg: regulator@1 { regulator-always-on; }; vdd1_reg: regulator@2 { /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1312500>; regulator-boot-on; regulator-always-on; }; vdd2_reg: regulator@3 { /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ regulator-name = "vdd_core"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; vdd3_reg: regulator@4 { regulator-always-on; }; vdig1_reg: regulator@5 { regulator-always-on; }; vdig2_reg: regulator@6 { regulator-always-on; }; vpll_reg: regulator@7 { regulator-always-on; }; vdac_reg: regulator@8 { regulator-always-on; }; vaux1_reg: regulator@9 { regulator-always-on; }; vaux2_reg: regulator@10 { regulator-always-on; }; vaux33_reg: regulator@11 { regulator-always-on; }; vmmc_reg: regulator@12 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; }; &mac { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; dual_emac = <1>; status = "okay"; }; &davinci_mdio { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; phy1: ethernet-phy@1 { reg = <7>; eee-broken-100tx; eee-broken-1000t; }; }; &mmc1 { vmmc-supply = <&vmmc_reg>; status = "okay"; }; &mmc2 { status = "okay"; vmmc-supply = <&wl12xx_vmmc>; ti,non-removable; bus-width = <4>; cap-power-off-card; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio3>; interrupts = <7 IRQ_TYPE_EDGE_RISING>; }; }; &sham { status = "okay"; }; &aes { status = "okay"; }; &gpio0 { ti,no-reset-on-init; }; &gpio3 { ti,no-reset-on-init; }; diff --git a/sys/gnu/dts/arm/am335x-bone-common.dtsi b/sys/gnu/dts/arm/am335x-bone-common.dtsi index 6c9187bc0f17..89b4cf2cb7f8 100644 --- a/sys/gnu/dts/arm/am335x-bone-common.dtsi +++ b/sys/gnu/dts/arm/am335x-bone-common.dtsi @@ -1,399 +1,421 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ / { cpus { cpu@0 { cpu0-supply = <&dcdc2_reg>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; chosen { stdout-path = &uart0; }; leds { pinctrl-names = "default"; pinctrl-0 = <&user_leds_s0>; compatible = "gpio-leds"; led2 { label = "beaglebone:green:heartbeat"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; led3 { label = "beaglebone:green:mmc0"; gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; led4 { label = "beaglebone:green:usr2"; gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "cpu0"; default-state = "off"; }; led5 { label = "beaglebone:green:usr3"; gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc1"; default-state = "off"; }; }; vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; }; &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&clkout2_pin>; user_leds_s0: user_leds_s0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spio0_cs1.gpio0_6 */ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) >; }; emmc_pins: pinmux_emmc_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ >; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + &usb0 { + status = "okay"; dr_mode = "peripheral"; interrupts-extended = <&intc 18 &tps 0>; interrupt-names = "mc", "vbus"; }; &usb1 { + status = "okay"; dr_mode = "host"; }; +&cppi41dma { + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; status = "okay"; clock-frequency = <400000>; tps: tps@24 { reg = <0x24>; }; baseboard_eeprom: baseboard_eeprom@50 { compatible = "atmel,24c256"; reg = <0x50>; #address-cells = <1>; #size-cells = <1>; baseboard_data: baseboard_data@0 { reg = <0 0x100>; }; }; }; &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; status = "okay"; clock-frequency = <100000>; cape_eeprom0: cape_eeprom0@54 { compatible = "atmel,24c256"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; cape0_data: cape_data@0 { reg = <0 0x100>; }; }; cape_eeprom1: cape_eeprom1@55 { compatible = "atmel,24c256"; reg = <0x55>; #address-cells = <1>; #size-cells = <1>; cape1_data: cape_data@0 { reg = <0 0x100>; }; }; cape_eeprom2: cape_eeprom2@56 { compatible = "atmel,24c256"; reg = <0x56>; #address-cells = <1>; #size-cells = <1>; cape2_data: cape_data@0 { reg = <0 0x100>; }; }; cape_eeprom3: cape_eeprom3@57 { compatible = "atmel,24c256"; reg = <0x57>; #address-cells = <1>; #size-cells = <1>; cape3_data: cape_data@0 { reg = <0 0x100>; }; }; }; /include/ "tps65217.dtsi" &tps { /* * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only * mode") at poweroff. Most BeagleBone versions do not support RTC-only * mode and risk hardware damage if this mode is entered. * * For details, see linux-omap mailing list May 2015 thread * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller * In particular, messages: * http://www.spinics.net/lists/linux-omap/msg118585.html * http://www.spinics.net/lists/linux-omap/msg118615.html * * You can override this later with * &tps { /delete-property/ ti,pmic-shutdown-controller; } * if you want to use RTC-only mode and made sure you are not affected * by the hardware problems. (Tip: double-check by performing a current * measurement after shutdown: it should be less than 1 mA.) */ interrupts = <7>; /* NMI */ interrupt-parent = <&intc>; ti,pmic-shutdown-controller; charger { status = "okay"; }; pwrbutton { status = "okay"; }; regulators { dcdc1_reg: regulator@0 { regulator-name = "vdds_dpr"; regulator-always-on; }; dcdc2_reg: regulator@1 { /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <925000>; regulator-max-microvolt = <1351500>; regulator-boot-on; regulator-always-on; }; dcdc3_reg: regulator@2 { /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ regulator-name = "vdd_core"; regulator-min-microvolt = <925000>; regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; ldo1_reg: regulator@3 { regulator-name = "vio,vrtc,vdds"; regulator-always-on; }; ldo2_reg: regulator@4 { regulator-name = "vdd_3v3aux"; regulator-always-on; }; ldo3_reg: regulator@5 { regulator-name = "vdd_1v8"; regulator-always-on; }; ldo4_reg: regulator@6 { regulator-name = "vdd_3v3a"; regulator-always-on; }; }; }; &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "mii"; }; &mac { slaves = <1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; status = "okay"; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; status = "okay"; ethphy0: ethernet-phy@0 { reg = <0>; }; }; &mmc1 { status = "okay"; bus-width = <0x4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; &aes { status = "okay"; }; &sham { status = "okay"; }; &rtc { clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; diff --git a/sys/gnu/dts/arm/am335x-boneblack-common.dtsi b/sys/gnu/dts/arm/am335x-boneblack-common.dtsi index 91f93bc89716..7ad079861efd 100644 --- a/sys/gnu/dts/arm/am335x-boneblack-common.dtsi +++ b/sys/gnu/dts/arm/am335x-boneblack-common.dtsi @@ -1,168 +1,163 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ #include #include &ldo3_reg { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; &mmc1 { vmmc-supply = <&vmmcsd_fixed>; }; &mmc2 { vmmc-supply = <&vmmcsd_fixed>; pinctrl-names = "default"; pinctrl-0 = <&emmc_pins>; bus-width = <8>; status = "okay"; }; &am33xx_pinmux { nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) >; }; mcasp0_pins: mcasp0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ >; }; }; &lcdc { status = "okay"; /* If you want to get 24 bit RGB and 16 BGR mode instead of * current 16 bit RGB and 24 BGR modes, set the propety * below to "crossed" and uncomment the video-ports -property * in tda19988 node. */ blue-and-red-wiring = "straight"; port { lcdc_0: endpoint@0 { remote-endpoint = <&hdmi_0>; }; }; }; &i2c0 { tda19988: tda19988@70 { compatible = "nxp,tda998x"; reg = <0x70>; nxp,calib-gpios = <&gpio1 25 0>; interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default", "off"; pinctrl-0 = <&nxp_hdmi_bonelt_pins>; pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ /* video-ports = <0x234501>; */ #sound-dai-cells = <0>; audio-ports = < TDA998x_I2S 0x03>; ports { port@0 { hdmi_0: endpoint@0 { remote-endpoint = <&lcdc_0>; }; }; }; }; }; &rtc { system-power-controller; }; &mcasp0 { #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcasp0_pins>; status = "okay"; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 0 0 1 0 >; tx-num-evt = <32>; rx-num-evt = <32>; }; / { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - clk_mcasp0_fixed: clk_mcasp0_fixed { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24576000>; }; clk_mcasp0: clk_mcasp0 { #clock-cells = <0>; compatible = "gpio-gate-clock"; clocks = <&clk_mcasp0_fixed>; enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ }; sound { compatible = "simple-audio-card"; simple-audio-card,name = "TI BeagleBone Black"; simple-audio-card,format = "i2s"; simple-audio-card,bitclock-master = <&dailink0_master>; simple-audio-card,frame-master = <&dailink0_master>; dailink0_master: simple-audio-card,cpu { sound-dai = <&mcasp0>; clocks = <&clk_mcasp0>; }; simple-audio-card,codec { sound-dai = <&tda19988>; }; }; }; diff --git a/sys/gnu/dts/arm/am335x-boneblue.dts b/sys/gnu/dts/arm/am335x-boneblue.dts index 5811fb8d4fdf..2f6652ef9a15 100644 --- a/sys/gnu/dts/arm/am335x-boneblue.dts +++ b/sys/gnu/dts/arm/am335x-boneblue.dts @@ -1,422 +1,444 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; #include "am33xx.dtsi" #include "am335x-osd335x-common.dtsi" #include / { model = "TI AM335x BeagleBone Blue"; compatible = "ti,am335x-bone-blue", "ti,am33xx"; chosen { stdout-path = &uart0; }; leds { pinctrl-names = "default"; pinctrl-0 = <&user_leds_s0>; compatible = "gpio-leds"; usr_0_led { label = "beaglebone:green:usr0"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; usr_1_led { label = "beaglebone:green:usr1"; gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; usr_2_led { label = "beaglebone:green:usr2"; gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "cpu0"; default-state = "off"; }; usr_3_led { label = "beaglebone:green:usr3"; gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc1"; default-state = "off"; }; wifi_led { label = "wifi"; gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "phy0assoc"; }; red_led { label = "red"; gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; default-state = "off"; }; green_led { label = "green"; gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; batt_1_led { label = "bat25"; gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; default-state = "off"; }; batt_2_led { label = "bat50"; gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; default-state = "off"; }; batt_3_led { label = "bat75"; gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; default-state = "off"; }; batt_4_led { label = "bat100"; gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; wlan_en_reg: fixedregulator@2 { compatible = "regulator-fixed"; regulator-name = "wlan-en-regulator"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; startup-delay-us= <70000>; /* WL_EN */ gpio = <&gpio3 9 0>; enable-active-high; }; }; &am33xx_pinmux { user_leds_s0: user_leds_s0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] - WIFI_LED */ AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) /* (R7) gpmc_advn_ale.gpio2[2] - P8.7, LED_RED, GP1_PIN_5 */ AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE7) /* (T7) gpmc_oen_ren.gpio2[3] - P8.8, LED_GREEN, GP1_PIN_6 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* (U12) gpmc_ad11.gpio0[27] - P8.17, BATT_LED_1 */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) /* (T5) lcd_data15.gpio0[11] - P8.32, BATT_LED_2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE7) /* (V6) gpmc_csn0.gpio1[29] - P8.26, BATT_LED_3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* (T11) gpmc_ad10.gpio0[26] - P8.14, BATT_LED_4 */ >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ >; }; /* UT0 */ uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; /* UT1 */ uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; /* GPS */ uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE1) /* (A17) spi0_sclk.uart2_rxd */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (B17) spi0_d0.uart2_txd */ >; }; /* DSM2 */ uart4_pins: pinmux_uart4_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ >; }; /* UT5 */ uart5_pins: pinmux_uart5_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* (U2) lcd_data9.uart5_rxd */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* (U1) lcd_data8.uart5_txd */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ >; }; mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* (U9) gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* (V9) gpmc_csn2.mmc1_cmd */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* (U7) gpmc_ad0.mmc1_dat0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* (V7) gpmc_ad1.mmc1_dat1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* (R8) gpmc_ad2.mmc1_dat2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (T8) gpmc_ad3.mmc1_dat3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* (U8) gpmc_ad4.mmc1_dat4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* (V8) gpmc_ad5.mmc1_dat5 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* (R9) gpmc_ad6.mmc1_dat6 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* (T9) gpmc_ad7.mmc1_dat7 */ >; }; mmc3_pins: pinmux_mmc3_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6) /* (L15) gmii1_rxd1.mmc2_clk */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6) /* (J16) gmii1_txen.mmc2_cmd */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5) /* (J17) gmii1_rxdv.mmc2_dat0 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5) /* (J18) gmii1_txd3.mmc2_dat1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5) /* (K15) gmii1_txd2.mmc2_dat2 */ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5) /* (H16) gmii1_col.mmc2_dat3 */ >; }; bt_pins: pinmux_bt_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (K17) gmii1_txd0.gpio0[28] - BT_EN */ >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* (M17) mdio_data.uart3_ctsn */ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* (M18) mdio_clk.uart3_rtsn */ >; }; wl18xx_pins: pinmux_wl18xx_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */ >; }; /* DCAN */ dcan1_pins: pinmux_dcan1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* (E17) uart0_rtsn.dcan1_rx */ AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* (E18) uart0_ctsn.dcan1_tx */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_OUTPUT, MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ >; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; status = "okay"; }; &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins>; status = "okay"; }; &uart5 { pinctrl-names = "default"; pinctrl-0 = <&uart5_pins>; status = "okay"; }; +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + &usb0 { + status = "okay"; dr_mode = "peripheral"; interrupts-extended = <&intc 18 &tps 0>; interrupt-names = "mc", "vbus"; }; &usb1 { + status = "okay"; dr_mode = "host"; }; +&cppi41dma { + status = "okay"; +}; + &i2c0 { baseboard_eeprom: baseboard_eeprom@50 { compatible = "atmel,24c256"; reg = <0x50>; #address-cells = <1>; #size-cells = <1>; baseboard_data: baseboard_data@0 { reg = <0 0x100>; }; }; }; &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; status = "okay"; clock-frequency = <400000>; mpu9250@68 { compatible = "invensense,mpu9250"; reg = <0x68>; interrupt-parent = <&gpio3>; interrupts = <21 IRQ_TYPE_EDGE_RISING>; i2c-gate { #address-cells = <1>; #size-cells = <0>; ax8975@c { compatible = "ak,ak8975"; reg = <0x0c>; }; }; }; pressure@76 { compatible = "bosch,bmp280"; reg = <0x76>; }; }; /include/ "tps65217.dtsi" &tps { /delete-property/ ti,pmic-shutdown-controller; charger { interrupts = <0>, <1>; interrupt-names = "USB", "AC"; status = "okay"; }; }; &mmc1 { status = "okay"; vmmc-supply = <&vmmcsd_fixed>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; &mmc2 { status = "okay"; vmmc-supply = <&vmmcsd_fixed>; bus-width = <8>; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; }; &mmc3 { dmas = <&edma_xbar 12 0 1 &edma_xbar 13 0 2>; dma-names = "tx", "rx"; status = "okay"; vmmc-supply = <&wlan_en_reg>; bus-width = <4>; non-removable; cap-power-off-card; ti,needs-special-hs-handling; keep-power-in-suspend; pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins &wl18xx_pins>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio0>; interrupts = <21 IRQ_TYPE_EDGE_RISING>; }; }; &tscadc { status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins &bt_pins>; status = "okay"; bluetooth { compatible = "ti,wl1835-st"; enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; }; }; &rtc { system-power-controller; clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; &dcan1 { pinctrl-names = "default"; pinctrl-0 = <&dcan1_pins>; status = "okay"; }; &gpio3 { ls_buf_en { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; output-high; line-name = "LS_BUF_EN"; }; }; diff --git a/sys/gnu/dts/arm/am335x-chiliboard.dts b/sys/gnu/dts/arm/am335x-chiliboard.dts index b14a2759c69b..8cd81dc0cc72 100644 --- a/sys/gnu/dts/arm/am335x-chiliboard.dts +++ b/sys/gnu/dts/arm/am335x-chiliboard.dts @@ -1,183 +1,201 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ * Author: Rostislav Lisovy */ /dts-v1/; #include "am335x-chilisom.dtsi" / { model = "AM335x Chiliboard"; compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom", "ti,am33xx"; chosen { stdout-path = &uart0; }; leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&led_gpio_pins>; led0 { label = "led0"; gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; default-state = "keep"; linux,default-trigger = "heartbeat"; }; led1 { label = "led1"; gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; default-state = "keep"; }; }; }; &am33xx_pinmux { uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* mdio_data.mdio_data */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_clk.mdio_clk */ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; usb1_drvvbus: usb1_drvvbus { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; sd_pins: pinmux_sd_card { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; led_gpio_pins: led_gpio_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_OUTPUT, MUX_MODE7) /* emu0.gpio3_7 */ AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT, MUX_MODE7) /* emu1.gpio3_8 */ >; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; &ldo4_reg { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; /* Ethernet */ &mac { slaves = <1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; status = "okay"; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; status = "okay"; ethphy0: ethernet-phy@0 { reg = <0>; }; }; &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "rmii"; }; /* USB */ +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + &usb1 { pinctrl-names = "default"; pinctrl-0 = <&usb1_drvvbus>; + + status = "okay"; dr_mode = "host"; }; +&cppi41dma { + status = "okay"; +}; + /* microSD */ &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&sd_pins>; vmmc-supply = <&ldo4_reg>; bus-width = <0x4>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; status = "okay"; }; &tps { interrupt-parent = <&intc>; interrupts = <7>; /* NNMI */ charger { status = "okay"; }; pwrbutton { status = "okay"; }; }; diff --git a/sys/gnu/dts/arm/am335x-cm-t335.dts b/sys/gnu/dts/arm/am335x-cm-t335.dts index c6fe9db660e2..1fe3b566ba3d 100644 --- a/sys/gnu/dts/arm/am335x-cm-t335.dts +++ b/sys/gnu/dts/arm/am335x-cm-t335.dts @@ -1,513 +1,533 @@ // SPDX-License-Identifier: GPL-2.0-only /* * am335x-cm-t335.dts - Device Tree file for Compulab CM-T335 * * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ */ /dts-v1/; #include "am33xx.dtsi" #include / { model = "CompuLab CM-T335"; compatible = "compulab,cm-t335", "ti,am33xx"; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x8000000>; /* 128 MB */ }; leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&gpio_led_pins>; led0 { label = "cm_t335:green"; gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* gpio2_0 */ linux,default-trigger = "heartbeat"; }; }; /* regulator for mmc */ vmmc_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmc_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; /* Regulator for WiFi */ vwlan_fixed: fixedregulator2 { compatible = "regulator-fixed"; regulator-name = "vwlan_fixed"; gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; /* gpio0_20 */ enable-active-high; }; backlight { compatible = "pwm-backlight"; pwms = <&ecap0 0 50000 0>; brightness-levels = <0 51 53 56 62 75 101 152 255>; default-brightness-level = <8>; }; sound { compatible = "simple-audio-card"; simple-audio-card,name = "cm-t335"; simple-audio-card,widgets = "Microphone", "Mic Jack", "Line", "Line In", "Headphone", "Headphone Jack"; simple-audio-card,routing = "Headphone Jack", "LHPOUT", "Headphone Jack", "RHPOUT", "LLINEIN", "Line In", "RLINEIN", "Line In", "MICIN", "Mic Jack"; simple-audio-card,format = "i2s"; simple-audio-card,bitclock-master = <&sound_master>; simple-audio-card,frame-master = <&sound_master>; simple-audio-card,cpu { sound-dai = <&mcasp1>; }; sound_master: simple-audio-card,codec { sound-dai = <&tlv320aic23>; system-clock-frequency = <12000000>; }; }; }; &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&bluetooth_pins>; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < /* uart0_ctsn.i2c1_sda */ AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.i2c1_scl */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) >; }; gpio_led_pins: pinmux_gpio_led_pins { pinctrl-single,pins = < /* gpmc_csn3.gpio2_0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE7) >; }; nandflash_pins: pinmux_nandflash_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wpn.gpio0_30 */ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; dcan0_pins: pinmux_dcan0_pins { pinctrl-single,pins = < /* uart1_ctsn.dcan0_tx */ AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart1_rtsn.dcan0_rx */ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2) >; }; dcan1_pins: pinmux_dcan1_pins { pinctrl-single,pins = < /* uart1_rxd.dcan1_tx */ AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT, MUX_MODE2) /* uart1_txd.dcan1_rx */ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE2) >; }; ecap0_pins: pinmux_ecap0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ /* mii1_tx_en.rgmii1_tctl */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) >; }; spi0_pins: pinmux_spi0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_OUTPUT, MUX_MODE0) >; }; /* wl1271 bluetooth */ bluetooth_pins: pinmux_bluetooth_pins { pinctrl-single,pins = < /* XDMA_EVENT_INTR0.gpio0_19 - bluetooth enable */ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLUP, MUX_MODE7) >; }; /* TLV320AIC23B codec */ mcasp1_pins: pinmux_mcasp1_pins { pinctrl-single,pins = < /* MII1_CRS.mcasp1_aclkx */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* MII1_RX_ER.mcasp1_fsx */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* MII1_COL.mcasp1_axr2 */ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE4) /* RMII1_REF_CLK.mcasp1_axr3 */ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) >; }; /* wl1271 WiFi */ wifi_pins: pinmux_wifi_pins { pinctrl-single,pins = < /* EMU1.gpio3_8 - WiFi IRQ */ AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) /* XDMA_EVENT_INTR1.gpio0_20 - WiFi enable */ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) >; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; /* WLS1271 bluetooth */ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; status = "okay"; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; status = "okay"; clock-frequency = <400000>; /* CM-T335 board EEPROM */ eeprom: 24c02@50 { compatible = "atmel,24c02"; reg = <0x50>; pagesize = <16>; }; /* Real Time Clock */ ext_rtc: em3027@56 { compatible = "emmicro,em3027"; reg = <0x56>; }; /* Audio codec */ tlv320aic23: codec@1a { compatible = "ti,tlv320aic23"; reg = <0x1a>; #sound-dai-cells= <0>; status = "okay"; }; }; +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&cppi41dma { + status = "okay"; +}; + &epwmss0 { status = "okay"; ecap0: ecap@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins>; }; }; &gpmc { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&nandflash_pins>; ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <8>; gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <44>; gpmc,cs-wr-off-ns = <44>; gpmc,adv-on-ns = <6>; gpmc,adv-rd-off-ns = <34>; gpmc,adv-wr-off-ns = <44>; gpmc,we-on-ns = <0>; gpmc,we-off-ns = <40>; gpmc,oe-on-ns = <0>; gpmc,oe-off-ns = <54>; gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spl"; reg = <0x00000000 0x00200000>; }; partition@1 { label = "uboot"; reg = <0x00200000 0x00100000>; }; partition@2 { label = "uboot environment"; reg = <0x00300000 0x00100000>; }; partition@3 { label = "dtb"; reg = <0x00400000 0x00100000>; }; partition@4 { label = "splash"; reg = <0x00500000 0x00400000>; }; partition@5 { label = "linux"; reg = <0x00900000 0x00600000>; }; partition@6 { label = "rootfs"; reg = <0x00F00000 0>; }; }; }; &elm { status = "okay"; }; &mac { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; slaves = <1>; status = "okay"; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; status = "okay"; ethphy0: ethernet-phy@0 { reg = <0>; }; }; &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "rgmii-txid"; }; &mmc1 { status = "okay"; vmmc-supply = <&vmmc_fixed>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; }; &dcan0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dcan0_pins>; }; &dcan1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dcan1_pins>; }; /* Touschscreen and analog digital converter */ &tscadc { status = "okay"; tsc { ti,wires = <4>; ti,x-plate-resistance = <200>; ti,coordinate-readouts = <5>; ti,wire-config = <0x01 0x10 0x23 0x32>; ti,charge-delay = <0x400>; }; adc { ti,adc-channels = <4 5 6 7>; }; }; /* CPU audio */ &mcasp1 { pinctrl-names = "default"; pinctrl-0 = <&mcasp1_pins>; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; /* 16 serializers */ num-serializer = <16>; serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 >; tx-num-evt = <1>; rx-num-evt = <1>; #sound-dai-cells= <0>; status = "okay"; }; &spi0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; ti,pindir-d0-out-d1-in = <1>; /* WLS1271 WiFi */ wlcore: wlcore@1 { compatible = "ti,wl1271"; pinctrl-names = "default"; pinctrl-0 = <&wifi_pins>; reg = <1>; spi-max-frequency = <48000000>; clock-xtal; ref-clock-frequency = <38400000>; interrupt-parent = <&gpio3>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; vwlan-supply = <&vwlan_fixed>; }; }; diff --git a/sys/gnu/dts/arm/am335x-evm.dts b/sys/gnu/dts/arm/am335x-evm.dts index 68252dab32c3..a00145705c9b 100644 --- a/sys/gnu/dts/arm/am335x-evm.dts +++ b/sys/gnu/dts/arm/am335x-evm.dts @@ -1,778 +1,817 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; #include "am33xx.dtsi" #include / { model = "TI AM335x EVM"; compatible = "ti,am335x-evm", "ti,am33xx"; cpus { cpu@0 { cpu0-supply = <&vdd1_reg>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; chosen { stdout-path = &uart0; }; vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-boot-on; }; lis3_reg: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "lis3_reg"; regulator-boot-on; }; wlan_en_reg: fixedregulator2 { compatible = "regulator-fixed"; regulator-name = "wlan-en-regulator"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; /* WLAN_EN GPIO for this board - Bank1, pin16 */ gpio = <&gpio1 16 0>; /* WLAN card specific delay */ startup-delay-us = <70000>; enable-active-high; }; /* TPS79501 */ v1_8d_reg: fixedregulator-v1_8d { compatible = "regulator-fixed"; regulator-name = "v1_8d"; vin-supply = <&vbat>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; /* TPS79501 */ v3_3d_reg: fixedregulator-v3_3d { compatible = "regulator-fixed"; regulator-name = "v3_3d"; vin-supply = <&vbat>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; matrix_keypad: matrix_keypad0 { compatible = "gpio-matrix-keypad"; debounce-delay-ms = <5>; col-scan-delay-us = <2>; row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ linux,keymap = <0x0000008b /* MENU */ 0x0100009e /* BACK */ 0x02000069 /* LEFT */ 0x0001006a /* RIGHT */ 0x0101001c /* ENTER */ 0x0201006c>; /* DOWN */ }; gpio_keys: volume_keys0 { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; switch9 { label = "volume-up"; linux,code = <115>; gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; wakeup-source; }; switch10 { label = "volume-down"; linux,code = <114>; gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; wakeup-source; }; }; - backlight: backlight { + backlight { compatible = "pwm-backlight"; pwms = <&ecap0 0 50000 0>; brightness-levels = <0 51 53 56 62 75 101 152 255>; default-brightness-level = <8>; }; panel { - compatible = "tfc,s9700rtwv43tr-01b"; - + compatible = "ti,tilcdc,panel"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&lcd_pins_s0>; - backlight = <&backlight>; + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <32>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; - port { - panel_0: endpoint@0 { - remote-endpoint = <&lcdc_0>; + display-timings { + 800x480p62 { + clock-frequency = <30000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <39>; + hback-porch = <39>; + hsync-len = <47>; + vback-porch = <29>; + vfront-porch = <13>; + vsync-len = <2>; + hsync-active = <1>; + vsync-active = <1>; }; }; }; sound { compatible = "simple-audio-card"; simple-audio-card,name = "AM335x-EVM"; simple-audio-card,widgets = "Headphone", "Headphone Jack", "Line", "Line In"; simple-audio-card,routing = "Headphone Jack", "HPLOUT", "Headphone Jack", "HPROUT", "LINE1L", "Line In", "LINE1R", "Line In"; simple-audio-card,format = "dsp_b"; simple-audio-card,bitclock-master = <&sound_master>; simple-audio-card,frame-master = <&sound_master>; simple-audio-card,bitclock-inversion; simple-audio-card,cpu { sound-dai = <&mcasp1>; }; sound_master: simple-audio-card,codec { sound-dai = <&tlv320aic3106>; system-clock-frequency = <12000000>; }; }; }; &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; matrix_keypad_s0: matrix_keypad_s0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a6.gpio1_22 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a9.gpio1_25 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a10.gpio1_26 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ >; }; volume_keys_s0: volume_keys_s0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_sclk.gpio0_2 */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_d0.gpio0_3 */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; nandflash_pins_s0: nandflash_pins_s0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) >; }; ecap0_pins: backlight_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */ >; }; mmc3_pins: pinmux_mmc3_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ >; }; wlan_pins: pinmux_wlan_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a0.gpio1_16 */ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ >; }; lcd_pins_s0: lcd_pins_s0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; mcasp1_pins: mcasp1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ >; }; mcasp1_pins_sleep: mcasp1_pins_sleep { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; dcan1_pins_default: dcan1_pins_default { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ >; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; status = "okay"; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; status = "okay"; clock-frequency = <400000>; tps: tps@2d { reg = <0x2d>; }; }; +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + &usb1 { + status = "okay"; dr_mode = "host"; }; +&cppi41dma { + status = "okay"; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; status = "okay"; clock-frequency = <100000>; lis331dlh: lis331dlh@18 { compatible = "st,lis331dlh", "st,lis3lv02d"; reg = <0x18>; Vdd-supply = <&lis3_reg>; Vdd_IO-supply = <&lis3_reg>; st,click-single-x; st,click-single-y; st,click-single-z; st,click-thresh-x = <10>; st,click-thresh-y = <10>; st,click-thresh-z = <10>; st,irq1-click; st,irq2-click; st,wakeup-x-lo; st,wakeup-x-hi; st,wakeup-y-lo; st,wakeup-y-hi; st,wakeup-z-lo; st,wakeup-z-hi; st,min-limit-x = <120>; st,min-limit-y = <120>; st,min-limit-z = <140>; st,max-limit-x = <550>; st,max-limit-y = <550>; st,max-limit-z = <750>; }; tsl2550: tsl2550@39 { compatible = "taos,tsl2550"; reg = <0x39>; }; tmp275: tmp275@48 { compatible = "ti,tmp275"; reg = <0x48>; }; tlv320aic3106: tlv320aic3106@1b { #sound-dai-cells = <0>; compatible = "ti,tlv320aic3106"; reg = <0x1b>; status = "okay"; /* Regulators */ AVDD-supply = <&v3_3d_reg>; IOVDD-supply = <&v3_3d_reg>; DRVDD-supply = <&v3_3d_reg>; DVDD-supply = <&v1_8d_reg>; }; }; &lcdc { status = "okay"; blue-and-red-wiring = "crossed"; - - port { - lcdc_0: endpoint@0 { - remote-endpoint = <&panel_0>; - }; - }; }; &elm { status = "okay"; }; &epwmss0 { status = "okay"; ecap0: ecap@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins>; }; }; &gpmc { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&nandflash_pins_s0>; ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-xfer-type = "prefetch-dma"; ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <8>; gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <44>; gpmc,cs-wr-off-ns = <44>; gpmc,adv-on-ns = <6>; gpmc,adv-rd-off-ns = <34>; gpmc,adv-wr-off-ns = <44>; gpmc,we-on-ns = <0>; gpmc,we-off-ns = <40>; gpmc,oe-on-ns = <0>; gpmc,oe-off-ns = <54>; gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ /* All SPL-* partitions are sized to minimal length * which can be independently programmable. For * NAND flash this is equal to size of erase-block */ #address-cells = <1>; #size-cells = <1>; partition@0 { label = "NAND.SPL"; reg = <0x00000000 0x000020000>; }; partition@1 { label = "NAND.SPL.backup1"; reg = <0x00020000 0x00020000>; }; partition@2 { label = "NAND.SPL.backup2"; reg = <0x00040000 0x00020000>; }; partition@3 { label = "NAND.SPL.backup3"; reg = <0x00060000 0x00020000>; }; partition@4 { label = "NAND.u-boot-spl-os"; reg = <0x00080000 0x00040000>; }; partition@5 { label = "NAND.u-boot"; reg = <0x000C0000 0x00100000>; }; partition@6 { label = "NAND.u-boot-env"; reg = <0x001C0000 0x00020000>; }; partition@7 { label = "NAND.u-boot-env.backup1"; reg = <0x001E0000 0x00020000>; }; partition@8 { label = "NAND.kernel"; reg = <0x00200000 0x00800000>; }; partition@9 { label = "NAND.file-system"; reg = <0x00A00000 0x0F600000>; }; }; }; #include "tps65910.dtsi" &mcasp1 { #sound-dai-cells = <0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&mcasp1_pins>; pinctrl-1 = <&mcasp1_pins_sleep>; status = "okay"; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; /* 4 serializers */ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 0 0 1 2 >; tx-num-evt = <32>; rx-num-evt = <32>; }; &tps { vcc1-supply = <&vbat>; vcc2-supply = <&vbat>; vcc3-supply = <&vbat>; vcc4-supply = <&vbat>; vcc5-supply = <&vbat>; vcc6-supply = <&vbat>; vcc7-supply = <&vbat>; vccio-supply = <&vbat>; regulators { vrtc_reg: regulator@0 { regulator-always-on; }; vio_reg: regulator@1 { regulator-always-on; }; vdd1_reg: regulator@2 { /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1351500>; regulator-boot-on; regulator-always-on; }; vdd2_reg: regulator@3 { /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ regulator-name = "vdd_core"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; vdd3_reg: regulator@4 { regulator-always-on; }; vdig1_reg: regulator@5 { regulator-always-on; }; vdig2_reg: regulator@6 { regulator-always-on; }; vpll_reg: regulator@7 { regulator-always-on; }; vdac_reg: regulator@8 { regulator-always-on; }; vaux1_reg: regulator@9 { regulator-always-on; }; vaux2_reg: regulator@10 { regulator-always-on; }; vaux33_reg: regulator@11 { regulator-always-on; }; vmmc_reg: regulator@12 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; }; &mac { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; status = "okay"; slaves = <1>; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; status = "okay"; ethphy0: ethernet-phy@0 { reg = <0>; }; }; &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "rgmii-id"; }; &tscadc { status = "okay"; tsc { ti,wires = <4>; ti,x-plate-resistance = <200>; ti,coordinate-readouts = <5>; ti,wire-config = <0x00 0x11 0x22 0x33>; ti,charge-delay = <0x400>; }; adc { ti,adc-channels = <4 5 6 7>; }; }; &mmc1 { status = "okay"; vmmc-supply = <&vmmc_reg>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; &mmc3 { /* these are on the crossbar and are outlined in the xbar-event-map element */ dmas = <&edma_xbar 12 0 1 &edma_xbar 13 0 2>; dma-names = "tx", "rx"; status = "okay"; vmmc-supply = <&wlan_en_reg>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins &wlan_pins>; ti,non-removable; ti,needs-special-hs-handling; cap-power-off-card; keep-power-in-suspend; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@0 { compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio3>; interrupts = <17 IRQ_TYPE_EDGE_RISING>; }; }; &sham { status = "okay"; }; &aes { status = "okay"; }; &dcan1 { status = "disabled"; /* Enable only if Profile 1 is selected */ pinctrl-names = "default"; pinctrl-0 = <&dcan1_pins_default>; }; &rtc { clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; diff --git a/sys/gnu/dts/arm/am335x-evmsk.dts b/sys/gnu/dts/arm/am335x-evmsk.dts index 32f515a295ee..e28a5b82fdf3 100644 --- a/sys/gnu/dts/arm/am335x-evmsk.dts +++ b/sys/gnu/dts/arm/am335x-evmsk.dts @@ -1,719 +1,758 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ /* * AM335x Starter Kit * http://www.ti.com/tool/tmdssk3358 */ /dts-v1/; #include "am33xx.dtsi" #include #include / { model = "TI AM335x EVM-SK"; compatible = "ti,am335x-evmsk", "ti,am33xx"; cpus { cpu@0 { cpu0-supply = <&vdd1_reg>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; chosen { stdout-path = &uart0; }; vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-boot-on; }; lis3_reg: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "lis3_reg"; regulator-boot-on; }; wl12xx_vmmc: fixedregulator2 { pinctrl-names = "default"; pinctrl-0 = <&wl12xx_gpio>; compatible = "regulator-fixed"; regulator-name = "vwl1271"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&gpio1 29 0>; startup-delay-us = <70000>; enable-active-high; }; vtt_fixed: fixedregulator3 { compatible = "regulator-fixed"; regulator-name = "vtt"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>; regulator-always-on; regulator-boot-on; enable-active-high; }; /* TPS79518 */ v1_8d_reg: fixedregulator-v1_8d { compatible = "regulator-fixed"; regulator-name = "v1_8d"; vin-supply = <&vbat>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; /* TPS78633 */ v3_3d_reg: fixedregulator-v3_3d { compatible = "regulator-fixed"; regulator-name = "v3_3d"; vin-supply = <&vbat>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; leds { pinctrl-names = "default"; pinctrl-0 = <&user_leds_s0>; compatible = "gpio-leds"; led1 { label = "evmsk:green:usr0"; gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led2 { label = "evmsk:green:usr1"; gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led3 { label = "evmsk:green:mmc0"; gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; led4 { label = "evmsk:green:heartbeat"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; }; gpio_buttons: gpio_buttons0 { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; switch1 { label = "button0"; linux,code = <0x100>; gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; }; switch2 { label = "button1"; linux,code = <0x101>; gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; }; switch3 { label = "button2"; linux,code = <0x102>; gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; wakeup-source; }; switch4 { label = "button3"; linux,code = <0x103>; gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; }; }; lcd_bl: backlight { compatible = "pwm-backlight"; pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 58 61 66 75 90 125 170 255>; default-brightness-level = <8>; }; sound { compatible = "simple-audio-card"; simple-audio-card,name = "AM335x-EVMSK"; simple-audio-card,widgets = "Headphone", "Headphone Jack"; simple-audio-card,routing = "Headphone Jack", "HPLOUT", "Headphone Jack", "HPROUT"; simple-audio-card,format = "dsp_b"; simple-audio-card,bitclock-master = <&sound_master>; simple-audio-card,frame-master = <&sound_master>; simple-audio-card,bitclock-inversion; simple-audio-card,cpu { sound-dai = <&mcasp1>; }; sound_master: simple-audio-card,codec { sound-dai = <&tlv320aic3106>; system-clock-frequency = <24000000>; }; }; panel { - compatible = "newhaven,nhd-4.3-480272ef-atxl"; - + compatible = "ti,tilcdc,panel"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&lcd_pins_default>; pinctrl-1 = <&lcd_pins_sleep>; backlight = <&lcd_bl>; - - port { - panel_0: endpoint@0 { - remote-endpoint = <&lcdc_0>; + status = "okay"; + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <32>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + display-timings { + 480x272 { + hactive = <480>; + vactive = <272>; + hback-porch = <43>; + hfront-porch = <8>; + hsync-len = <4>; + vback-porch = <12>; + vfront-porch = <4>; + vsync-len = <10>; + clock-frequency = <9000000>; + hsync-active = <0>; + vsync-active = <0>; }; }; }; }; &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; lcd_pins_default: lcd_pins_default { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; lcd_pins_sleep: lcd_pins_sleep { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad8.lcd_data23 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad9.lcd_data22 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.lcd_data21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.lcd_data20 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.lcd_data19 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.lcd_data18 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.lcd_data17 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.lcd_data16 */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; user_leds_s0: user_leds_s0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad4.gpio1_4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad5.gpio1_5 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad6.gpio1_6 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad7.gpio1_7 */ >; }; gpio_keys_s0: gpio_keys_s0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_wait0.gpio0_30 */ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; ecap2_pins: backlight_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ /* Slave 2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* Slave 2 reset value*/ AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */ >; }; mcasp1_pins: mcasp1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ >; }; mcasp1_pins_sleep: mcasp1_pins_sleep { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ >; }; wl12xx_gpio: pinmux_wl12xx_gpio { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */ >; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; status = "okay"; clock-frequency = <400000>; tps: tps@2d { reg = <0x2d>; }; lis331dlh: lis331dlh@18 { compatible = "st,lis331dlh", "st,lis3lv02d"; reg = <0x18>; Vdd-supply = <&lis3_reg>; Vdd_IO-supply = <&lis3_reg>; st,click-single-x; st,click-single-y; st,click-single-z; st,click-thresh-x = <10>; st,click-thresh-y = <10>; st,click-thresh-z = <10>; st,irq1-click; st,irq2-click; st,wakeup-x-lo; st,wakeup-x-hi; st,wakeup-y-lo; st,wakeup-y-hi; st,wakeup-z-lo; st,wakeup-z-hi; st,min-limit-x = <120>; st,min-limit-y = <120>; st,min-limit-z = <140>; st,max-limit-x = <550>; st,max-limit-y = <550>; st,max-limit-z = <750>; }; tlv320aic3106: tlv320aic3106@1b { #sound-dai-cells = <0>; compatible = "ti,tlv320aic3106"; reg = <0x1b>; status = "okay"; /* Regulators */ AVDD-supply = <&v3_3d_reg>; IOVDD-supply = <&v3_3d_reg>; DRVDD-supply = <&v3_3d_reg>; DVDD-supply = <&v1_8d_reg>; }; }; +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + &usb1 { + status = "okay"; dr_mode = "host"; }; +&cppi41dma { + status = "okay"; +}; + &epwmss2 { status = "okay"; ecap2: ecap@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap2_pins>; }; }; #include "tps65910.dtsi" &tps { vcc1-supply = <&vbat>; vcc2-supply = <&vbat>; vcc3-supply = <&vbat>; vcc4-supply = <&vbat>; vcc5-supply = <&vbat>; vcc6-supply = <&vbat>; vcc7-supply = <&vbat>; vccio-supply = <&vbat>; regulators { vrtc_reg: regulator@0 { regulator-always-on; }; vio_reg: regulator@1 { regulator-always-on; }; vdd1_reg: regulator@2 { /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1351500>; regulator-boot-on; regulator-always-on; }; vdd2_reg: regulator@3 { /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ regulator-name = "vdd_core"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; vdd3_reg: regulator@4 { regulator-always-on; }; vdig1_reg: regulator@5 { regulator-always-on; }; vdig2_reg: regulator@6 { regulator-always-on; }; vpll_reg: regulator@7 { regulator-always-on; }; vdac_reg: regulator@8 { regulator-always-on; }; vaux1_reg: regulator@9 { regulator-always-on; }; vaux2_reg: regulator@10 { regulator-always-on; }; vaux33_reg: regulator@11 { regulator-always-on; }; vmmc_reg: regulator@12 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; }; &mac { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; dual_emac = <1>; status = "okay"; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; status = "okay"; ethphy0: ethernet-phy@0 { reg = <0>; }; ethphy1: ethernet-phy@1 { reg = <1>; }; }; &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "rgmii-id"; dual_emac_res_vlan = <1>; }; &cpsw_emac1 { phy-handle = <ðphy1>; phy-mode = "rgmii-id"; dual_emac_res_vlan = <2>; }; &mmc1 { status = "okay"; vmmc-supply = <&vmmc_reg>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; &sham { status = "okay"; }; &aes { status = "okay"; }; &gpio0 { ti,no-reset-on-init; }; &mmc2 { status = "okay"; vmmc-supply = <&wl12xx_vmmc>; ti,non-removable; bus-width = <4>; cap-power-off-card; keep-power-in-suspend; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio0>; interrupts = <31 IRQ_TYPE_EDGE_RISING>; /* gpio 31 */ ref-clock-frequency = <38400000>; }; }; &mcasp1 { #sound-dai-cells = <0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&mcasp1_pins>; pinctrl-1 = <&mcasp1_pins_sleep>; status = "okay"; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; /* 4 serializers */ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 0 0 1 2 >; tx-num-evt = <32>; rx-num-evt = <32>; }; &tscadc { status = "okay"; tsc { ti,wires = <4>; ti,x-plate-resistance = <200>; ti,coordinate-readouts = <5>; ti,wire-config = <0x00 0x11 0x22 0x33>; }; }; &lcdc { status = "okay"; blue-and-red-wiring = "crossed"; - - port { - lcdc_0: endpoint@0 { - remote-endpoint = <&panel_0>; - }; - }; }; &rtc { clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; diff --git a/sys/gnu/dts/arm/am335x-guardian.dts b/sys/gnu/dts/arm/am335x-guardian.dts index 81e0f63e94d3..c9611ea4b884 100644 --- a/sys/gnu/dts/arm/am335x-guardian.dts +++ b/sys/gnu/dts/arm/am335x-guardian.dts @@ -1,489 +1,511 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * Copyright (C) 2018 Robert Bosch Power Tools GmbH */ /dts-v1/; #include "am33xx.dtsi" #include #include / { model = "Bosch AM335x Guardian"; compatible = "bosch,am335x-guardian", "ti,am33xx"; chosen { stdout-path = &uart0; tick-timer = &timer2; }; cpus { cpu@0 { cpu0-supply = <&dcdc2_reg>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; gpio_keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pins>; button21 { label = "guardian-power-button"; linux,code = ; gpios = <&gpio2 21 0>; wakeup-source; }; }; leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&leds_pins>; led1 { label = "green:heartbeat"; gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; led2 { label = "green:mmc0"; gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; }; panel { compatible = "ti,tilcdc,panel"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&lcd_pins_default &lcd_disen_pins>; pinctrl-1 = <&lcd_pins_sleep>; display-timings { 320x240 { hactive = <320>; vactive = <240>; hback-porch = <68>; hfront-porch = <20>; hsync-len = <1>; vback-porch = <18>; vfront-porch = <4>; vsync-len = <1>; clock-frequency = <9000000>; hsync-active = <0>; vsync-active = <0>; }; }; panel-info { ac-bias = <255>; ac-bias-intrpt = <0>; dma-burst-sz = <16>; bpp = <24>; bus-width = <16>; fdd = <0x80>; sync-edge = <0>; sync-ctrl = <1>; raster-order = <0>; fifo-th = <0>; }; }; pwm7: dmtimer-pwm { compatible = "ti,omap-dmtimer-pwm"; ti,timers = <&timer7>; pinctrl-names = "default"; pinctrl-0 = <&dmtimer7_pins>; }; vmmcsd_fixed: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; }; +&cppi41dma { + status = "okay"; +}; + &elm { status = "okay"; }; &gpmc { pinctrl-names = "default"; pinctrl-0 = <&nandflash_pins>; ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ status = "okay"; nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-ecc-opt = "bch16"; ti,elm-id = <&elm>; nand-bus-width = <8>; gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <44>; gpmc,cs-wr-off-ns = <44>; gpmc,adv-on-ns = <6>; gpmc,adv-rd-off-ns = <34>; gpmc,adv-wr-off-ns = <44>; gpmc,we-on-ns = <0>; gpmc,we-off-ns = <40>; gpmc,oe-on-ns = <0>; gpmc,oe-off-ns = <54>; gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; /* * MTD partition table * * All SPL-* partitions are sized to minimal length which can * be independently programmable. For NAND flash this is equal * to size of erase-block. */ #address-cells = <1>; #size-cells = <1>; partition@0 { label = "SPL"; reg = <0x0 0x40000>; }; partition@1 { label = "SPL.backup1"; reg = <0x40000 0x40000>; }; partition@2 { label = "SPL.backup2"; reg = <0x80000 0x40000>; }; partition@3 { label = "SPL.backup3"; reg = <0xc0000 0x40000>; }; partition@4 { label = "u-boot"; reg = <0x100000 0x100000>; }; partition@5 { label = "u-boot.backup1"; reg = <0x200000 0x100000>; }; partition@6 { label = "u-boot-env"; reg = <0x300000 0x40000>; }; partition@7 { label = "u-boot-env.backup1"; reg = <0x340000 0x40000>; }; partition@8 { label = "UBI"; reg = <0x380000 0x1fc80000>; }; }; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; clock-frequency = <400000>; status = "okay"; tps: tps@24 { reg = <0x24>; }; }; &lcdc { blue-and-red-wiring = "crossed"; status = "okay"; }; &mmc1 { bus-width = <0x4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; vmmc-supply = <&vmmcsd_fixed>; status = "okay"; }; &rtc { clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; system-power-controller; }; &spi0 { ti,pindir-d0-out-d1-in; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; status = "okay"; }; #include "tps65217.dtsi" &tps { ti,pmic-shutdown-controller; interrupt-parent = <&intc>; interrupts = <7>; /* NMI */ backlight { isel = <1>; /* 1 - ISET1, 2 ISET2 */ fdim = <100>; /* TPS65217_BL_FDIM_100HZ */ default-brightness = <100>; }; regulators { dcdc1_reg: regulator@0 { regulator-name = "vdds_dpr"; regulator-always-on; }; dcdc2_reg: regulator@1 { regulator-name = "vdd_mpu"; regulator-min-microvolt = <925000>; regulator-max-microvolt = <1351500>; regulator-boot-on; regulator-always-on; }; dcdc3_reg: regulator@2 { regulator-name = "vdd_core"; regulator-min-microvolt = <925000>; regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; ldo1_reg: regulator@3 { regulator-name = "vio,vrtc,vdds"; regulator-always-on; }; ldo2_reg: regulator@4 { regulator-name = "vdd_3v3aux"; regulator-always-on; }; ldo3_reg: regulator@5 { regulator-name = "vdd_1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; ldo4_reg: regulator@6 { regulator-name = "vdd_3v3a"; regulator-always-on; }; }; }; &tscadc { status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5 6>; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + &usb0 { dr_mode = "peripheral"; + status = "okay"; +}; + +&usb0_phy { + status = "okay"; }; &usb1 { dr_mode = "host"; + status = "okay"; +}; + +&usb1_phy { + status = "okay"; }; &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&clkout2_pin &gpio_pins>; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) >; }; dmtimer7_pins: pinmux_dmtimer7_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) >; }; gpio_keys_pins: pinmux_gpio_keys_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) >; }; gpio_pins: pinmux_gpio_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7) AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7) >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) >; }; lcd_disen_pins: pinmux_lcd_disen_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7) >; }; lcd_pins_default: pinmux_lcd_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) >; }; lcd_pins_sleep: pinmux_lcd_pins_sleep { pinctrl-single,pins = < AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) >; }; leds_pins: pinmux_leds_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) >; }; spi0_pins: pinmux_spi0_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0) AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0) AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0) >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) >; }; nandflash_pins: pinmux_nandflash_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0) AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0) AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0) AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0) AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0) AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0) AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0) AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) >; }; }; diff --git a/sys/gnu/dts/arm/am335x-icev2.dts b/sys/gnu/dts/arm/am335x-icev2.dts index 021eb57261fe..204bccfcc110 100644 --- a/sys/gnu/dts/arm/am335x-icev2.dts +++ b/sys/gnu/dts/arm/am335x-icev2.dts @@ -1,512 +1,499 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ */ /* * AM335x ICE V2 board * http://www.ti.com/tool/tmdsice3359 */ /dts-v1/; #include "am33xx.dtsi" / { model = "TI AM3359 ICE-V2"; compatible = "ti,am3359-icev2", "ti,am33xx"; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; chosen { stdout-path = &uart3; }; vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-boot-on; }; vtt_fixed: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "vtt"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; regulator-always-on; regulator-boot-on; enable-active-high; }; leds-iio { status = "disabled"; compatible = "gpio-leds"; led-out0 { label = "out0"; gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out1 { label = "out1"; gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out2 { label = "out2"; gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out3 { label = "out3"; gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out4 { label = "out4"; gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out5 { label = "out5"; gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out6 { label = "out6"; gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out7 { label = "out7"; gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; /* Tricolor status LEDs */ leds1 { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&user_leds>; led0 { label = "status0:red:cpu0"; gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "cpu0"; }; led1 { label = "status0:green:usr"; gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led2 { label = "status0:yellow:usr"; gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led3 { label = "status1:red:mmc0"; gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "mmc0"; }; led4 { label = "status1:green:usr"; gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led5 { label = "status1:yellow:usr"; gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; gpio-decoder { compatible = "gpio-decoder"; gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, <&pca9536 2 GPIO_ACTIVE_HIGH>, <&pca9536 1 GPIO_ACTIVE_HIGH>, <&pca9536 0 GPIO_ACTIVE_HIGH>; linux,axis = <0>; /* ABS_X */ decoder-max-value = <9>; }; }; &am33xx_pinmux { user_leds: user_leds { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */ >; }; mmc0_pins_default: mmc0_pins_default { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) >; }; i2c0_pins_default: i2c0_pins_default { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) >; }; spi0_pins_default: spi0_pins_default { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */ >; }; uart3_pins_default: uart3_pins_default { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1, RMII mode */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */ /* Slave 2, RMII mode */ AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wait0.rmii2_crs_dv */ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_col.rmii2_refclk */ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wpn.rmii2_rxerr */ AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a5.rmii2_txd0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a4.rmii2_txd1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a0.rmii2_txen */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* Slave 2 reset value */ AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_default>; status = "okay"; clock-frequency = <400000>; tps: power-controller@2d { reg = <0x2d>; }; tpic2810: gpio@60 { compatible = "ti,tpic2810"; reg = <0x60>; gpio-controller; #gpio-cells = <2>; }; pca9536: gpio@41 { compatible = "ti,pca9536"; reg = <0x41>; gpio-controller; #gpio-cells = <2>; }; - - /* osd9616p0899-10 */ - display@3c { - compatible = "solomon,ssd1306fb-i2c"; - reg = <0x3c>; - solomon,height = <16>; - solomon,width = <96>; - solomon,com-seq; - solomon,com-invdir; - solomon,page-offset = <0>; - solomon,prechargep1 = <2>; - solomon,prechargep2 = <13>; - }; }; &spi0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins_default>; sn65hvs882@1 { compatible = "pisosr-gpio"; gpio-controller; #gpio-cells = <2>; load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; reg = <1>; spi-max-frequency = <1000000>; spi-cpol; }; spi_nor: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "winbond,w25q64", "jedec,spi-nor"; spi-max-frequency = <80000000>; m25p,fast-read; reg = <0>; partition@0 { label = "u-boot-spl"; reg = <0x0 0x80000>; read-only; }; partition@1 { label = "u-boot"; reg = <0x80000 0x100000>; read-only; }; partition@2 { label = "u-boot-env"; reg = <0x180000 0x20000>; read-only; }; partition@3 { label = "misc"; reg = <0x1A0000 0x660000>; }; }; }; &tscadc { status = "okay"; adc { ti,adc-channels = <1 2 3 4 5 6 7>; }; }; #include "tps65910.dtsi" &tps { vcc1-supply = <&vbat>; vcc2-supply = <&vbat>; vcc3-supply = <&vbat>; vcc4-supply = <&vbat>; vcc5-supply = <&vbat>; vcc6-supply = <&vbat>; vcc7-supply = <&vbat>; vccio-supply = <&vbat>; regulators { vrtc_reg: regulator@0 { regulator-always-on; }; vio_reg: regulator@1 { regulator-always-on; }; vdd1_reg: regulator@2 { regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1326000>; regulator-boot-on; regulator-always-on; }; vdd2_reg: regulator@3 { regulator-name = "vdd_core"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1144000>; regulator-boot-on; regulator-always-on; }; vdd3_reg: regulator@4 { regulator-always-on; }; vdig1_reg: regulator@5 { regulator-always-on; }; vdig2_reg: regulator@6 { regulator-always-on; }; vpll_reg: regulator@7 { regulator-always-on; }; vdac_reg: regulator@8 { regulator-always-on; }; vaux1_reg: regulator@9 { regulator-always-on; }; vaux2_reg: regulator@10 { regulator-always-on; }; vaux33_reg: regulator@11 { regulator-always-on; }; vmmc_reg: regulator@12 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; }; &mmc1 { status = "okay"; vmmc-supply = <&vmmc_reg>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_default>; }; &gpio0_target { /* Do not idle the GPIO used for holding the VTT regulator */ ti,no-reset-on-init; ti,no-idle-on-init; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins_default>; status = "okay"; }; &gpio3 { p4 { gpio-hog; gpios = <4 GPIO_ACTIVE_HIGH>; output-high; line-name = "PR1_MII_CTRL"; }; p10 { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */ output-high; line-name = "MUX_MII_CTL1"; }; }; &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "rmii"; dual_emac_res_vlan = <1>; }; &cpsw_emac1 { phy-handle = <ðphy1>; phy-mode = "rmii"; dual_emac_res_vlan = <2>; }; &mac { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; status = "okay"; dual_emac; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; status = "okay"; reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; reset-delay-us = <2>; /* PHY datasheet states 1uS min */ ethphy0: ethernet-phy@1 { reg = <1>; }; ethphy1: ethernet-phy@3 { reg = <3>; }; }; diff --git a/sys/gnu/dts/arm/am335x-igep0033.dtsi b/sys/gnu/dts/arm/am335x-igep0033.dtsi index c9f354fc984a..eabcc8b2e4ea 100644 --- a/sys/gnu/dts/arm/am335x-igep0033.dtsi +++ b/sys/gnu/dts/arm/am335x-igep0033.dtsi @@ -1,300 +1,325 @@ // SPDX-License-Identifier: GPL-2.0-only /* * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x * * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz */ /dts-v1/; #include "am33xx.dtsi" #include / { cpus { cpu@0 { cpu0-supply = <&vdd1_reg>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; leds { pinctrl-names = "default"; pinctrl-0 = <&leds_pins>; compatible = "gpio-leds"; led0 { label = "com:green:user"; gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-boot-on; }; vmmc: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "vmmc"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; }; &am33xx_pinmux { i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; nandflash_pins: pinmux_nandflash_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; leds_pins: pinmux_leds_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ >; }; }; &mac { status = "okay"; }; &davinci_mdio { status = "okay"; ethphy0: ethernet-phy@0 { reg = <0>; }; ethphy1: ethernet-phy@1 { reg = <1>; }; }; &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "rmii"; }; &cpsw_emac1 { phy-handle = <ðphy1>; phy-mode = "rmii"; }; &elm { status = "okay"; }; &gpmc { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&nandflash_pins>; ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ nand-bus-width = <8>; ti,nand-ecc-opt = "bch8"; gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <44>; gpmc,cs-wr-off-ns = <44>; gpmc,adv-on-ns = <6>; gpmc,adv-rd-off-ns = <34>; gpmc,adv-wr-off-ns = <44>; gpmc,we-on-ns = <0>; gpmc,we-off-ns = <40>; gpmc,oe-on-ns = <0>; gpmc,oe-off-ns = <54>; gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; #address-cells = <1>; #size-cells = <1>; ti,elm-id = <&elm>; /* MTD partition table */ partition@0 { label = "SPL"; reg = <0x00000000 0x000080000>; }; partition@1 { label = "U-boot"; reg = <0x00080000 0x001e0000>; }; partition@2 { label = "U-Boot Env"; reg = <0x00260000 0x00020000>; }; partition@3 { label = "Kernel"; reg = <0x00280000 0x00500000>; }; partition@4 { label = "File System"; reg = <0x00780000 0x007880000>; }; }; }; &i2c0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; clock-frequency = <400000>; tps: tps@2d { reg = <0x2d>; }; }; &mmc1 { status = "okay"; vmmc-supply = <&vmmc>; bus-width = <4>; }; &uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; }; +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + &usb1 { + status = "okay"; dr_mode = "host"; }; +&cppi41dma { + status = "okay"; +}; + #include "tps65910.dtsi" &tps { vcc1-supply = <&vbat>; vcc2-supply = <&vbat>; vcc3-supply = <&vbat>; vcc4-supply = <&vbat>; vcc5-supply = <&vbat>; vcc6-supply = <&vbat>; vcc7-supply = <&vbat>; vccio-supply = <&vbat>; regulators { vrtc_reg: regulator@0 { regulator-always-on; }; vio_reg: regulator@1 { regulator-always-on; }; vdd1_reg: regulator@2 { /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1312500>; regulator-boot-on; regulator-always-on; }; vdd2_reg: regulator@3 { /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ regulator-name = "vdd_core"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; vdd3_reg: regulator@4 { regulator-always-on; }; vdig1_reg: regulator@5 { regulator-always-on; }; vdig2_reg: regulator@6 { regulator-always-on; }; vpll_reg: regulator@7 { regulator-always-on; }; vdac_reg: regulator@8 { regulator-always-on; }; vaux1_reg: regulator@9 { regulator-always-on; }; vaux2_reg: regulator@10 { regulator-always-on; }; vaux33_reg: regulator@11 { regulator-always-on; }; vmmc_reg: regulator@12 { regulator-always-on; }; }; }; diff --git a/sys/gnu/dts/arm/am335x-lxm.dts b/sys/gnu/dts/arm/am335x-lxm.dts index fef582852820..a8005e975ea2 100644 --- a/sys/gnu/dts/arm/am335x-lxm.dts +++ b/sys/gnu/dts/arm/am335x-lxm.dts @@ -1,345 +1,367 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 NovaTech LLC - http://www.novatechweb.com */ /dts-v1/; #include "am33xx.dtsi" / { model = "NovaTech OrionLXm"; compatible = "novatech,am335x-lxm", "ti,am33xx"; cpus { cpu@0 { cpu0-supply = <&vdd1_reg>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; /* Power supply provides a fixed 5V @2A */ vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-boot-on; }; /* Power supply provides a fixed 3.3V @3A */ vmmcsd_fixed: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; }; }; &am33xx_pinmux { mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_crs_dv */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rxer */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_txen */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td0 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd0 */ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) /* Slave 2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_crs_dv */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rxer */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_txen */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td0 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd0 */ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk */ /* Slave 2 reset value*/ AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_txen */ AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_crs_dv */ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rxer */ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_refclk */ >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; emmc_pins: pinmux_emmc_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; status = "okay"; clock-frequency = <400000>; serial_config1: serial_config1@20 { compatible = "nxp,pca9539"; reg = <0x20>; }; serial_config2: serial_config2@21 { compatible = "nxp,pca9539"; reg = <0x21>; }; tps: tps@2d { compatible = "ti,tps65910"; reg = <0x2d>; }; }; /include/ "tps65910.dtsi" &tps { vcc1-supply = <&vbat>; vcc2-supply = <&vbat>; vcc3-supply = <&vbat>; vcc4-supply = <&vbat>; vcc5-supply = <&vbat>; vcc6-supply = <&vbat>; vcc7-supply = <&vbat>; vccio-supply = <&vbat>; regulators { /* vrtc - unused */ vio_reg: regulator@1 { regulator-name = "vio_1v5,ddr"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; vdd1_reg: regulator@2 { regulator-name = "vdd1,mpu"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; vdd2_reg: regulator@3 { regulator-name = "vdd2_1v1,core"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-boot-on; regulator-always-on; }; /* vdd3 - unused */ /* vdig1 - unused */ vdig2_reg: regulator@6 { regulator-name = "vdig2_1v8,vdds_pll"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; /* vpll - unused */ vdac_reg: regulator@8 { regulator-name = "vdac_1v8,vdds"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; vaux1_reg: regulator@9 { regulator-name = "vaux1_1v8,usb"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; vaux2_reg: regulator@10 { regulator-name = "vaux2_3v3,io"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; vaux33_reg: regulator@11 { regulator-name = "vaux33_3v3,usb"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; vmmc_reg: regulator@12 { regulator-name = "vmmc_3v3,io"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; }; }; &sham { status = "okay"; }; &aes { status = "okay"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + &usb0 { + status = "okay"; dr_mode = "host"; }; &usb1 { + status = "okay"; dr_mode = "host"; }; +&cppi41dma { + status = "okay"; +}; + &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "rmii"; dual_emac_res_vlan = <2>; }; &cpsw_emac1 { phy-handle = <ðphy1>; phy-mode = "rmii"; dual_emac_res_vlan = <3>; }; &mac { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; dual_emac = <1>; status = "okay"; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; status = "okay"; ethphy0: ethernet-phy@5 { reg = <5>; }; ethphy1: ethernet-phy@4 { reg = <4>; }; }; &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; vmmc-supply = <&vmmcsd_fixed>; bus-width = <4>; status = "okay"; }; &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&emmc_pins>; vmmc-supply = <&vmmcsd_fixed>; bus-width = <8>; ti,non-removable; status = "okay"; }; diff --git a/sys/gnu/dts/arm/am335x-moxa-uc-2100-common.dtsi b/sys/gnu/dts/arm/am335x-moxa-uc-2100-common.dtsi index 6495a125c01f..671d4a5da9c4 100644 --- a/sys/gnu/dts/arm/am335x-moxa-uc-2100-common.dtsi +++ b/sys/gnu/dts/arm/am335x-moxa-uc-2100-common.dtsi @@ -1,227 +1,244 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/ * * Authors: SZ Lin (林上智) * Wes Huang (黃淵河) * Fero JD Zhou (周俊達) */ #include "am33xx.dtsi" / { vbat: vbat-regulator { compatible = "regulator-fixed"; }; /* Power supply provides a fixed 3.3V @3A */ vmmcsd_fixed: vmmcsd-regulator { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; }; buttons: push_button { compatible = "gpio-keys"; }; }; &am33xx_pinmux { pinctrl-names = "default"; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; push_button_pins: pinmux_push_button { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_23 */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; mmc1_pins_default: pinmux_mmc1_pins { pinctrl-single,pins = < /* eMMC */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad12.mmc1_dat0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad13.mmc1_dat1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad14.mmc1_dat2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad15.mmc1_dat3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad8.mmc1_dat4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad9.mmc1_dat5 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad10.mmc1_dat6 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad11.mmc1_dat7 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ >; }; spi0_pins: pinmux_spi0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) >; }; }; &uart0 { /* Console */ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; status = "okay"; clock-frequency = <400000>; eeprom: eeprom@50 { compatible = "atmel,24c16"; pagesize = <16>; reg = <0x50>; }; rtc_wdt: rtc_wdt@68 { compatible = "dallas,ds1374"; reg = <0x68>; }; }; +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + &usb0 { + status = "okay"; dr_mode = "host"; }; +&cppi41dma { + status = "okay"; +}; + /* Power */ &vbat { regulator-name = "vbat"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; &mac { pinctrl-names = "default"; pinctrl-0 = <&cpsw_default>; status = "okay"; }; &davinci_mdio { pinctrl-names = "default"; pinctrl-0 = <&davinci_mdio_default>; status = "okay"; }; &cpsw_emac0 { status = "okay"; }; &cpsw_emac1 { status = "okay"; }; &sham { status = "okay"; }; &aes { status = "okay"; }; &gpio0 { ti,no-reset-on-init; }; &mmc2 { pinctrl-names = "default"; vmmc-supply = <&vmmcsd_fixed>; bus-width = <8>; pinctrl-0 = <&mmc1_pins_default>; ti,non-removable; status = "okay"; }; &buttons { pinctrl-names = "default"; pinctrl-0 = <&push_button_pins>; #address-cells = <1>; #size-cells = <0>; button@0 { label = "push_button"; linux,code = <0x100>; gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; }; }; /* SPI Busses */ &spi0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; m25p80@0 { compatible = "mx25l6405d"; spi-max-frequency = <40000000>; reg = <0>; spi-cpol; spi-cpha; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; /* reg : The partition's offset and size within the mtd bank. */ partitions@0 { label = "MLO"; reg = <0x0 0x80000>; }; partitions@1 { label = "U-Boot"; reg = <0x80000 0x100000>; }; partitions@2 { label = "U-Boot Env"; reg = <0x180000 0x40000>; }; }; }; }; &spi1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi1_pins>; tpm_spi_tis@0 { compatible = "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <500000>; }; }; diff --git a/sys/gnu/dts/arm/am335x-moxa-uc-8100-me-t.dts b/sys/gnu/dts/arm/am335x-moxa-uc-8100-me-t.dts index 244df9c5a537..783d411f2cef 100644 --- a/sys/gnu/dts/arm/am335x-moxa-uc-8100-me-t.dts +++ b/sys/gnu/dts/arm/am335x-moxa-uc-8100-me-t.dts @@ -1,503 +1,525 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2017 MOXA Inc. - https://www.moxa.com/ * * Author: SZ Lin (林上智) */ /dts-v1/; #include "am33xx.dtsi" / { model = "Moxa UC-8100-ME-T"; compatible = "moxa,uc-8100-me-t", "ti,am33xx"; cpus { cpu@0 { cpu0-supply = <&vdd1_reg>; }; }; memory { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; vbat: vbat-regulator { compatible = "regulator-fixed"; }; /* Power supply provides a fixed 3.3V @3A */ vmmcsd_fixed: vmmcsd-regulator { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; }; leds { compatible = "gpio-leds"; led1 { label = "uc8100me:CEL1"; gpios = <&gpio_xten 8 0>; default-state = "off"; }; led2 { label = "uc8100me:CEL2"; gpios = <&gpio_xten 9 0>; default-state = "off"; }; led3 { label = "uc8100me:CEL3"; gpios = <&gpio_xten 10 0>; default-state = "off"; }; led4 { label = "uc8100me:DIA1"; gpios = <&gpio_xten 11 0>; default-state = "off"; }; led5 { label = "uc8100me:DIA2"; gpios = <&gpio_xten 12 0>; default-state = "off"; }; led6 { label = "uc8100me:DIA3"; gpios = <&gpio_xten 13 0>; default-state = "off"; }; led7 { label = "uc8100me:SD"; gpios = <&gpio_xten 14 0>; default-state = "off"; }; led8 { label = "uc8100me:USB"; gpios = <&gpio_xten 15 0>; default-state = "off"; }; led9 { label = "uc8100me:USER"; gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; buttons: push_button { compatible = "gpio-keys"; }; }; &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&minipcie_pins>; minipcie_pins: pinmux_minipcie { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */ AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/ >; }; push_button_pins: pinmux_push_button { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) >; }; uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* lcd_data9.uart5_rxd */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4) /* lcd_data8.uart5_txd */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) /* Slave 2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; mmc0_pins_default: pinmux_mmc0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */ AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */ >; }; mmc2_pins_default: pinmux_mmc2_pins { pinctrl-single,pins = < /* eMMC */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ >; }; spi0_pins: pinmux_spi0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) >; }; }; &uart0 { /* Console */ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; }; &uart1 { /* UART 1 setting */ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; }; &uart5 { /* UART 2 setting */ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; status = "okay"; clock-frequency = <400000>; tpm: tpm@20 { compatible = "infineon,slb9645tt"; reg = <0x20>; }; tps: tps@2d { compatible = "ti,tps65910"; reg = <0x2d>; }; eeprom: eeprom@50 { compatible = "atmel,24c16"; pagesize = <16>; reg = <0x50>; }; rtc_wdt: rtc_wdt@68 { compatible = "dallas,ds1374"; reg = <0x68>; }; }; &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; status = "okay"; clock-frequency = <400000>; gpio_xten: gpio_xten@27 { compatible = "nxp,pca9535"; gpio-controller; #gpio-cells = <2>; reg = <0x27>; }; }; +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + &usb0 { + status = "okay"; dr_mode = "host"; }; &usb1 { + status = "okay"; dr_mode = "host"; }; +&cppi41dma { + status = "okay"; +}; + #include "tps65910.dtsi" &tps { vcc1-supply = <&vbat>; vcc2-supply = <&vbat>; vcc3-supply = <&vbat>; vcc4-supply = <&vbat>; vcc5-supply = <&vbat>; vcc6-supply = <&vbat>; vcc7-supply = <&vbat>; vccio-supply = <&vbat>; regulators { vrtc_reg: regulator@0 { regulator-always-on; }; vio_reg: regulator@1 { regulator-always-on; }; vdd1_reg: regulator@2 { /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1378000>; regulator-boot-on; regulator-always-on; }; vdd2_reg: regulator@3 { /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ regulator-name = "vdd_core"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; vdd3_reg: regulator@4 { regulator-always-on; }; vdig1_reg: regulator@5 { regulator-always-on; }; vdig2_reg: regulator@6 { regulator-always-on; }; vpll_reg: regulator@7 { regulator-always-on; }; vdac_reg: regulator@8 { regulator-always-on; }; vaux1_reg: regulator@9 { regulator-always-on; }; vaux2_reg: regulator@10 { regulator-always-on; }; vaux33_reg: regulator@11 { regulator-always-on; }; vmmc_reg: regulator@12 { compatible = "regulator-fixed"; regulator-name = "vmmc_reg"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; }; /* Power */ &vbat { regulator-name = "vbat"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; &mac { pinctrl-names = "default"; pinctrl-0 = <&cpsw_default>; dual_emac = <1>; status = "okay"; }; &davinci_mdio { pinctrl-names = "default"; pinctrl-0 = <&davinci_mdio_default>; status = "okay"; ethphy0: ethernet-phy@4 { reg = <4>; }; ethphy1: ethernet-phy@5 { reg = <5>; }; }; &cpsw_emac0 { status = "okay"; phy-handle = <ðphy0>; phy-mode = "rmii"; dual_emac_res_vlan = <1>; }; &cpsw_emac1 { status = "okay"; phy-handle = <ðphy1>; phy-mode = "rmii"; dual_emac_res_vlan = <2>; }; &sham { status = "okay"; }; &aes { status = "okay"; }; &gpio0 { ti,no-reset-on-init; }; &mmc1 { pinctrl-names = "default"; vmmc-supply = <&vmmcsd_fixed>; bus-width = <4>; pinctrl-0 = <&mmc0_pins_default>; cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; status = "okay"; }; &mmc3 { dmas = <&edma_xbar 12 0 1 &edma_xbar 13 0 2>; dma-names = "tx", "rx"; pinctrl-names = "default"; vmmc-supply = <&vmmcsd_fixed>; bus-width = <8>; pinctrl-0 = <&mmc2_pins_default>; ti,non-removable; status = "okay"; }; &buttons { pinctrl-names = "default"; pinctrl-0 = <&push_button_pins>; #address-cells = <1>; #size-cells = <0>; button@0 { label = "push_button"; linux,code = <0x100>; gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; }; }; /* SPI Busses */ &spi0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; m25p80@0 { compatible = "mx25l6405d"; spi-max-frequency = <40000000>; reg = <0>; spi-cpol; spi-cpha; #address-cells = <1>; #size-cells = <1>; /* reg : The partition's offset and size within the mtd bank. */ partitions@0 { label = "MLO"; reg = <0x0 0x80000>; }; partitions@1 { label = "U-Boot"; reg = <0x80000 0x100000>; }; partitions@2 { label = "U-Boot Env"; reg = <0x180000 0x20000>; }; }; }; diff --git a/sys/gnu/dts/arm/am335x-netcan-plus-1xx.dts b/sys/gnu/dts/arm/am335x-netcan-plus-1xx.dts index 1e4dbc85c120..e69de29bb2d1 100644 --- a/sys/gnu/dts/arm/am335x-netcan-plus-1xx.dts +++ b/sys/gnu/dts/arm/am335x-netcan-plus-1xx.dts @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -/dts-v1/; - -#include "am335x-baltos.dtsi" -#include "am335x-baltos-leds.dtsi" - -/ { - model = "NetCAN"; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - led@1 { - label = "can_data"; - linux,default-trigger = "netdev"; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - led@2 { - label = "can_error"; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; -}; - -&am33xx_pinmux { - user_leds_s0: user_leds_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* CAN Data LED */ - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* CAN Error LED */ - >; - }; - - dcan1_pins: pinmux_dcan1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* CAN TX */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* CAN RX */ - >; - }; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <1>; - }; -}; - -&cpsw_emac0 { - phy-mode = "rmii"; - dual_emac_res_vlan = <1>; - phy-handle = <&phy0>; -}; - -&cpsw_emac1 { - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; - phy-handle = <&phy1>; -}; - -&dcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/am335x-netcom-plus-2xx.dts b/sys/gnu/dts/arm/am335x-netcom-plus-2xx.dts index 9a6cd8ef821f..e69de29bb2d1 100644 --- a/sys/gnu/dts/arm/am335x-netcom-plus-2xx.dts +++ b/sys/gnu/dts/arm/am335x-netcom-plus-2xx.dts @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -/dts-v1/; - -#include "am335x-baltos.dtsi" -#include "am335x-baltos-leds.dtsi" - -/ { - model = "NetCom Plus"; -}; - -&am33xx_pinmux { - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) /* RX */ - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) /* TX */ - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) /* CTS */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* RTS */ - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */ - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */ - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */ - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* RX */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* TX */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* CTS */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* RTS */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */ - >; - }; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <1>; - }; -}; - -&cpsw_emac0 { - phy-mode = "rmii"; - dual_emac_res_vlan = <1>; - phy-handle = <&phy0>; -}; - -&cpsw_emac1 { - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; - phy-handle = <&phy1>; -}; diff --git a/sys/gnu/dts/arm/am335x-netcom-plus-8xx.dts b/sys/gnu/dts/arm/am335x-netcom-plus-8xx.dts index 2298563f7334..e69de29bb2d1 100644 --- a/sys/gnu/dts/arm/am335x-netcom-plus-8xx.dts +++ b/sys/gnu/dts/arm/am335x-netcom-plus-8xx.dts @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -/dts-v1/; - -#include "am335x-baltos.dtsi" - -/ { - model = "NetCom Plus"; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&dip_switches>; - - dip_switches: pinmux_dip_switches { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - tca6416_pins: pinmux_tca6416_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE3) - >; - }; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&i2c1 { - tca6416a: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio0>; - interrupts = <20 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&tca6416_pins>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tca6416b: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - tca6416c: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <1>; - }; -}; - -&cpsw_emac0 { - phy-mode = "rmii"; - dual_emac_res_vlan = <1>; - phy-handle = <&phy0>; -}; - -&cpsw_emac1 { - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; - phy-handle = <&phy1>; -}; diff --git a/sys/gnu/dts/arm/am335x-osd3358-sm-red.dts b/sys/gnu/dts/arm/am335x-osd3358-sm-red.dts index 1d2902083483..f47cc9fea253 100644 --- a/sys/gnu/dts/arm/am335x-osd3358-sm-red.dts +++ b/sys/gnu/dts/arm/am335x-osd3358-sm-red.dts @@ -1,439 +1,461 @@ //SPDX-License-Identifier: GPL-2.0 /* Copyright (C) 2018 Octavo Systems LLC - http://www.octavosystems.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ /dts-v1/; #include "am33xx.dtsi" #include "am335x-osd335x-common.dtsi" #include #include / { model = "Octavo Systems OSD3358-SM-RED"; compatible = "oct,osd3358-sm-refdesign", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; }; &ldo3_reg { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; &mmc1 { vmmc-supply = <&vmmcsd_fixed>; }; &mmc2 { vmmc-supply = <&vmmcsd_fixed>; pinctrl-names = "default"; pinctrl-0 = <&emmc_pins>; bus-width = <8>; status = "okay"; }; &am33xx_pinmux { nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) >; }; mcasp0_pins: mcasp0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ >; }; flash_enable: flash-enable { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ >; }; imu_interrupt: imu-interrupt { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */ >; }; ethernet_interrupt: ethernet-interrupt{ pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */ >; }; }; &lcdc { status = "okay"; /* If you want to get 24 bit RGB and 16 BGR mode instead of * current 16 bit RGB and 24 BGR modes, set the propety * below to "crossed" and uncomment the video-ports -property * in tda19988 node. * AM335x errata for wiring: * http://www.ti.com/lit/er/sprz360i/sprz360i.pdf */ blue-and-red-wiring = "straight"; port { lcdc_0: endpoint { remote-endpoint = <&hdmi_0>; }; }; }; &i2c0 { tda19988: hdmi-encoder@70 { compatible = "nxp,tda998x"; reg = <0x70>; pinctrl-names = "default", "off"; pinctrl-0 = <&nxp_hdmi_bonelt_pins>; pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ /* video-ports = <0x234501>; */ #sound-dai-cells = <0>; audio-ports = < TDA998x_I2S 0x03>; port { hdmi_0: endpoint { remote-endpoint = <&lcdc_0>; }; }; }; mpu9250: imu@68 { compatible = "invensense,mpu6050"; reg = <0x68>; interrupt-parent = <&gpio3>; interrupts = <21 IRQ_TYPE_EDGE_RISING>; i2c-gate { #address-cells = <1>; #size-cells = <0>; ax8975@c { compatible = "ak,ak8975"; reg = <0x0c>; }; }; /*invensense,int_config = <0x10>; invensense,level_shifter = <0>; invensense,orientation = [01 00 00 00 01 00 00 00 01]; invensense,sec_slave_type = <0>; invensense,key = [4e cc 7e eb f6 1e 35 22 00 34 0d 65 32 e9 94 89];*/ }; bmp280: pressure@76 { compatible = "bosch,bmp280"; reg = <0x76>; }; }; &rtc { system-power-controller; }; &mcasp0 { #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcasp0_pins>; status = "okay"; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 0 0 1 0 >; tx-num-evt = <32>; rx-num-evt = <32>; }; / { clk_mcasp0_fixed: clk-mcasp0-fixed { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24576000>; }; clk_mcasp0: clk-mcasp0 { #clock-cells = <0>; compatible = "gpio-gate-clock"; clocks = <&clk_mcasp0_fixed>; enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ }; sound { compatible = "simple-audio-card"; simple-audio-card,name = "TI BeagleBone Black"; simple-audio-card,format = "i2s"; simple-audio-card,bitclock-master = <&dailink0_master>; simple-audio-card,frame-master = <&dailink0_master>; dailink0_master: simple-audio-card,cpu { sound-dai = <&mcasp0>; clocks = <&clk_mcasp0>; }; simple-audio-card,codec { sound-dai = <&tda19988>; }; }; chosen { stdout-path = &uart0; }; leds { pinctrl-names = "default"; pinctrl-0 = <&user_leds_s0>; compatible = "gpio-leds"; led2 { label = "beaglebone:green:usr0"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; led3 { label = "beaglebone:green:usr1"; gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; led4 { label = "beaglebone:green:usr2"; gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "cpu0"; default-state = "off"; }; led5 { label = "beaglebone:green:usr3"; gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc1"; default-state = "off"; }; }; vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; }; &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&clkout2_pin>; user_leds_s0: user-leds-s0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ >; }; i2c2_pins: pinmux-i2c2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ >; }; uart0_pins: pinmux-uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; clkout2_pin: pinmux-clkout2-pin { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; cpsw_default: cpsw-default { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) >; }; cpsw_sleep: cpsw-sleep { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci-mdio-default { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci-mdio-sleep { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc1_pins: pinmux-mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) >; }; emmc_pins: pinmux-emmc-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ >; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + &usb0 { + status = "okay"; dr_mode = "peripheral"; interrupts-extended = <&intc 18 &tps 0>; interrupt-names = "mc", "vbus"; }; &usb1 { + status = "okay"; dr_mode = "host"; }; +&cppi41dma { + status = "okay"; +}; + &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; status = "okay"; clock-frequency = <100000>; }; &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "rgmii-txid"; }; &mac { slaves = <1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; status = "okay"; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; status = "okay"; ethphy0: ethernet-phy@4 { reg = <4>; }; }; &mmc1 { status = "okay"; bus-width = <0x4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; &rtc { clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; diff --git a/sys/gnu/dts/arm/am335x-pcm-953.dtsi b/sys/gnu/dts/arm/am335x-pcm-953.dtsi index 6c547c83e5dd..9bfa032bcada 100644 --- a/sys/gnu/dts/arm/am335x-pcm-953.dtsi +++ b/sys/gnu/dts/arm/am335x-pcm-953.dtsi @@ -1,242 +1,267 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014-2017 Phytec Messtechnik GmbH * Author: Wadim Egorov * Teresa Remmet */ #include / { model = "Phytec AM335x PCM-953"; compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"; /* Power */ regulators { vcc3v3: fixedregulator@1 { compatible = "regulator-fixed"; regulator-name = "vcc3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; }; vcc1v8: fixedregulator@2 { compatible = "regulator-fixed"; regulator-name = "vcc1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; }; }; /* User IO */ user_leds: user_leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&user_leds_pins>; user-led0 { gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; linux,default-trigger = "gpio"; default-state = "on"; }; user-led1 { gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; linux,default-trigger = "gpio"; default-state = "on"; }; }; user_buttons: user_buttons { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&user_buttons_pins>; button@0 { label = "home"; linux,code = ; gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; wakeup-source; }; button@1 { label = "menu"; linux,code = ; gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; wakeup-source; }; }; }; &am33xx_pinmux { user_buttons_pins: pinmux_user_buttons { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu0.gpio3_7 */ AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu1.gpio3_8 */ >; }; user_leds_pins: pinmux_user_leds { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn1.gpio1_30 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn2.gpio1_31 */ >; }; }; /* CAN */ &am33xx_pinmux { dcan1_pins: pinmux_dcan1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart1_rxd.dcan1_tx_mux2 */ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLUP, MUX_MODE2) /* uart1_txd.dcan1_rx_mux2 */ >; }; }; &dcan1 { pinctrl-names = "default"; pinctrl-0 = <&dcan1_pins>; status = "okay"; }; /* Ethernet */ &am33xx_pinmux { ethernet1_pins: pinmux_ethernet1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ >; }; }; &cpsw_emac1 { phy-handle = <&phy1>; phy-mode = "rgmii-id"; dual_emac_res_vlan = <2>; status = "okay"; }; &davinci_mdio { phy1: ethernet-phy@2 { reg = <2>; }; }; &mac { slaves = <2>; pinctrl-names = "default"; pinctrl-0 = <ðernet0_pins ðernet1_pins>; dual_emac; }; /* Misc */ &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&cb_gpio_pins>; cb_gpio_pins: pinmux_cb_gpio { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ >; }; }; /* MMC */ &am33xx_pinmux { mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ >; }; }; &mmc1 { vmmc-supply = <&vcc3v3>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; status = "okay"; }; /* UARTs */ &am33xx_pinmux { uart0_pins: pinmux_uart0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart2_pins: pinmux_uart2 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ >; }; uart3_pins: pinmux_uart3 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd3.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd2.uart3_txd */ >; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; status = "okay"; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; status = "okay"; }; /* USB */ +&cppi41dma { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + &usb1 { + status = "okay"; dr_mode = "host"; }; + +&usb1_phy { + status = "okay"; +}; diff --git a/sys/gnu/dts/arm/am335x-pdu001.dts b/sys/gnu/dts/arm/am335x-pdu001.dts index e4dcfa087a1b..3141255f72c2 100644 --- a/sys/gnu/dts/arm/am335x-pdu001.dts +++ b/sys/gnu/dts/arm/am335x-pdu001.dts @@ -1,575 +1,603 @@ /* * pdu001.dts * * EETS GmbH PDU001 board device tree file * * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ * * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ * * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; #include "am33xx.dtsi" #include #include / { model = "EETS,PDU001"; compatible = "ti,am33xx"; chosen { stdout-path = &uart3; }; cpus { cpu@0 { cpu0-supply = <&vdd1_reg>; }; }; memory { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; vbat: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <3600000>; regulator-max-microvolt = <3600000>; regulator-boot-on; }; lis3_reg: fixedregulator@1 { compatible = "regulator-fixed"; regulator-name = "lis3_reg"; regulator-boot-on; }; panel { compatible = "ti,tilcdc,panel"; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&lcd_pins_s0>; panel-info { ac-bias = <255>; ac-bias-intrpt = <0>; dma-burst-sz = <16>; bpp = <16>; fdd = <0x80>; sync-edge = <0>; sync-ctrl = <1>; raster-order = <0>; fifo-th = <0>; }; display-timings { 240x320p16 { clock-frequency = <6500000>; hactive = <240>; vactive = <320>; hfront-porch = <6>; hback-porch = <6>; hsync-len = <1>; vback-porch = <6>; vfront-porch = <6>; vsync-len = <1>; hsync-active = <0>; vsync-active = <0>; pixelclk-active = <1>; de-active = <0>; }; }; }; }; &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&clkout2_pin>; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_clk.i2c2_sda */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d0.i2c2_scl */ >; }; spi1_pins: pinmux_spi1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1) /* spi0_cs1.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ >; }; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Port 1 (emac0) */ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE0) /* Port 2 (emac1) */ AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* mii2_txen.gpmc_a0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT, MUX_MODE1) /* mii2_rxdv.gpmc_a1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* mii2_txd3.gpmc_a2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* mii2_txd2.gpmc_a3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* mii2_txd1.gpmc_a4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* mii2_txd0.gpmc_a5 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT, MUX_MODE1) /* mii2_txclk.gpmc_a6 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT, MUX_MODE1) /* mii2_rxclk.gpmc_a7 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE1) /* mii2_rxd3.gpmc_a8 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE1) /* mii2_rxd2.gpmc_a9 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE1) /* mii2_rxd1.gpmc_a10 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE1) /* mii2_rxd0.gpmc_a11 */ AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE1) /* mii2_crs.gpmc_wait0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT, MUX_MODE1) /* mii2_rxer.gpmc_wpn */ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT, MUX_MODE1) /* mii2_col.gpmc_ben1 */ >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; mmc1_pins: pinmux_mmc1_pins { /* eMMC */ pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) >; }; mmc2_pins: pinmux_mmc2_pins { /* SD cardcage */ pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ /* card change signal for frontpanel SD cardcage */ AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ >; }; lcd_pins_s0: lcd_pins_s0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; dcan0_pins: pinmux_dcan0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart1_ctsn.d_can0_tx */ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart1_rtsn.d_can0_rx */ >; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; rs485-rts-active-high; rs485-rts-delay = <0 0>; linux,rs485-enabled-at-boot-time; status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; status = "okay"; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; status = "okay"; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; status = "okay"; clock-frequency = <400000>; tps: tps@2d { reg = <0x2d>; }; m2_eeprom: m2_eeprom@50 { compatible = "atmel,24c256"; reg = <0x50>; status = "okay"; }; }; &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; status = "okay"; clock-frequency = <100000>; board_24aa025e48: board_24aa025e48@50 { compatible = "atmel,24c02"; reg = <0x50>; }; backplane_24aa025e48: backplane_24aa025e48@53 { compatible = "atmel,24c02"; reg = <0x53>; }; pca9532: pca9532@60 { compatible = "nxp,pca9532"; reg = <0x60>; psc0 = <0x97>; pwm0 = <0x80>; psc1 = <0x97>; pwm1 = <0x10>; run.red@0 { type = ; }; run.green@1 { type = ; default-state = "on"; }; s2.red@2 { type = ; }; s2.green@3 { type = ; }; s1.yellow@4 { type = ; }; s1.green@5 { type = ; }; }; pca9530: pca9530@61 { compatible = "nxp,pca9530"; reg = <0x61>; tft-panel@0 { type = ; linux,default-trigger = "backlight"; default-state = "on"; }; }; mcp79400: mcp79400@6f { compatible = "microchip,mcp7940x"; reg = <0x6f>; }; }; &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; status = "okay"; clock-frequency = <100000>; }; &spi1 { pinctrl-names = "default"; pinctrl-0 = <&spi1_pins>; ti,pindir-d0-out-d1-in; status = "okay"; display-controller@0 { compatible = "orisetech,otm3225a"; reg = <0>; spi-max-frequency = <1000000>; // SPI mode 3 spi-cpol; spi-cpha; status = "okay"; }; }; +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&cppi41dma { + status = "okay"; +}; + /* * Disable soc's rtc as we have no VBAT for it. This makes the board * rtc (Microchip MCP79400) the default rtc device 'rtc0'. */ &rtc { status = "disabled"; }; &lcdc { status = "okay"; }; &elm { status = "okay"; }; #include "tps65910.dtsi" &tps { vcc1-supply = <&vbat>; vcc2-supply = <&vbat>; vcc3-supply = <&vbat>; vcc4-supply = <&vbat>; vcc5-supply = <&vbat>; vcc6-supply = <&vbat>; vcc7-supply = <&vbat>; vccio-supply = <&vbat>; regulators { vrtc_reg: regulator@0 { regulator-name = "ldo_vrtc"; regulator-always-on; }; vio_reg: regulator@1 { regulator-name = "buck_vdd_ddr"; regulator-always-on; }; vdd1_reg: regulator@2 { /* VDD_MPU voltage limits */ regulator-name = "buck_vdd_mpu"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1312500>; regulator-boot-on; regulator-always-on; }; vdd2_reg: regulator@3 { /* VDD_CORE voltage limits */ regulator-name = "buck_vdd_core"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; vdd3_reg: regulator@4 { regulator-name = "boost_res"; regulator-always-on; }; vdig1_reg: regulator@5 { regulator-name = "ldo_vdig1"; regulator-always-on; }; vdig2_reg: regulator@6 { regulator-name = "ldo_vdig2"; regulator-always-on; }; vpll_reg: regulator@7 { regulator-name = "ldo_vpll"; regulator-always-on; }; vdac_reg: regulator@8 { regulator-name = "ldo_vdac"; regulator-always-on; }; vaux1_reg: regulator@9 { regulator-name = "ldo_vaux1"; regulator-always-on; }; vaux2_reg: regulator@10 { regulator-name = "ldo_vaux2"; regulator-always-on; }; vaux33_reg: regulator@11 { regulator-name = "ldo_vaux33"; regulator-always-on; }; vmmc_reg: regulator@12 { regulator-name = "ldo_vmmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; vbb_reg: regulator@13 { regulator-name = "bat_vbb"; }; }; }; &mac { pinctrl-names = "default"; pinctrl-0 = <&cpsw_default>; dual_emac; /* no switch, two distinct MACs */ status = "okay"; }; &davinci_mdio { pinctrl-names = "default"; pinctrl-0 = <&davinci_mdio_default>; status = "okay"; ethphy0: ethernet-phy@0 { reg = <0>; }; ethphy1: ethernet-phy@1 { reg = <1>; }; }; &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "mii"; dual_emac_res_vlan = <1>; }; &cpsw_emac1 { phy-handle = <ðphy1>; phy-mode = "mii"; dual_emac_res_vlan = <2>; }; &tscadc { status = "okay"; tsc { ti,wires = <4>; ti,x-plate-resistance = <200>; ti,coordinate-readouts = <5>; ti,wire-config = <0x01 0x10 0x22 0x33>; ti,charge-delay = <0x400>; }; adc { ti,adc-channels = <4 5 6 7>; }; }; &mmc1 { status = "okay"; vmmc-supply = <&vmmc_reg>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; non-removable; }; &mmc2 { status = "okay"; vmmc-supply = <&vmmc_reg>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; }; &sham { status = "okay"; }; &aes { status = "okay"; }; &dcan0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dcan0_pins>; }; diff --git a/sys/gnu/dts/arm/am335x-pepper.dts b/sys/gnu/dts/arm/am335x-pepper.dts index 6d7608d9377b..e7764ecdf65f 100644 --- a/sys/gnu/dts/arm/am335x-pepper.dts +++ b/sys/gnu/dts/arm/am335x-pepper.dts @@ -1,641 +1,661 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Gumstix, Inc. - https://www.gumstix.com/ */ /dts-v1/; #include #include "am33xx.dtsi" / { model = "Gumstix Pepper"; compatible = "gumstix,am335x-pepper", "ti,am33xx"; cpus { cpu@0 { cpu0-supply = <&dcdc3_reg>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; buttons: user_buttons { compatible = "gpio-keys"; }; leds: user_leds { compatible = "gpio-leds"; }; panel: lcd_panel { compatible = "ti,tilcdc,panel"; }; sound: sound_iface { compatible = "ti,da830-evm-audio"; }; vbat: fixedregulator0 { compatible = "regulator-fixed"; }; v3v3c_reg: fixedregulator1 { compatible = "regulator-fixed"; }; vdd5_reg: fixedregulator2 { compatible = "regulator-fixed"; }; }; /* I2C Busses */ &i2c0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; clock-frequency = <400000>; tps: tps@24 { reg = <0x24>; }; eeprom: eeprom@50 { compatible = "atmel,24c256"; reg = <0x50>; }; audio_codec: tlv320aic3106@1b { compatible = "ti,tlv320aic3106"; reg = <0x1b>; ai3x-micbias-vg = <0x2>; }; accel: lis331dlh@1d { compatible = "st,lis3lv02d"; reg = <0x1d>; }; }; &i2c1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; clock-frequency = <400000>; }; &am33xx_pinmux { i2c0_pins: pinmux_i2c0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; i2c1_pins: pinmux_i2c1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE3) /* mii1_crs,i2c1_sda */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE3) /* mii1_rxerr,i2c1_scl */ >; }; }; /* Accelerometer */ &accel { pinctrl-names = "default"; pinctrl-0 = <&accel_pins>; Vdd-supply = <&ldo3_reg>; Vdd_IO-supply = <&ldo3_reg>; st,irq1-click; st,wakeup-x-lo; st,wakeup-x-hi; st,wakeup-y-lo; st,wakeup-y-hi; st,wakeup-z-lo; st,wakeup-z-hi; st,min-limit-x = <92>; st,max-limit-x = <14>; st,min-limit-y = <14>; st,max-limit-y = <92>; st,min-limit-z = <92>; st,max-limit-z = <14>; }; &am33xx_pinmux { accel_pins: pinmux_accel { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */ >; }; }; /* Audio */ &audio_codec { status = "okay"; reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; AVDD-supply = <&ldo3_reg>; IOVDD-supply = <&ldo3_reg>; DRVDD-supply = <&ldo3_reg>; DVDD-supply = <&dcdc1_reg>; }; &sound { ti,model = "AM335x-EVM"; ti,audio-codec = <&audio_codec>; ti,mcasp-controller = <&mcasp0>; ti,codec-clock-rate = <12000000>; ti,audio-routing = "Headphone Jack", "HPLOUT", "Headphone Jack", "HPROUT", "MIC3L", "Mic3L Switch"; }; &mcasp0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&audio_pins>; op-mode = <0>; /* MCASP_ISS_MODE */ tdm-slots = <2>; serial-dir = < 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 >; tx-num-evt = <1>; rx-num-evt = <1>; }; &am33xx_pinmux { audio_pins: pinmux_audio { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7) /* gpmc_a0.gpio1_16 */ >; }; }; /* Display: 24-bit LCD Screen */ &panel { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&lcd_pins>; panel-info { ac-bias = <255>; ac-bias-intrpt = <0>; dma-burst-sz = <16>; bpp = <32>; fdd = <0x80>; sync-edge = <0>; sync-ctrl = <1>; raster-order = <0>; fifo-th = <0>; }; display-timings { native-mode = <&timing0>; timing0: 480x272 { clock-frequency = <18400000>; hactive = <480>; vactive = <272>; hfront-porch = <8>; hback-porch = <4>; hsync-len = <41>; vfront-porch = <4>; vback-porch = <2>; vsync-len = <10>; hsync-active = <1>; vsync-active = <1>; }; }; }; &lcdc { status = "okay"; }; &am33xx_pinmux { lcd_pins: pinmux_lcd { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data16 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data17 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data18 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data19 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data20 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data22 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data23 */ AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) /* Display Enable */ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a11.gpio1_27 */ >; }; }; /* Ethernet */ &cpsw_emac0 { status = "okay"; phy-handle = <ðphy0>; phy-mode = "rgmii"; }; &cpsw_emac1 { status = "okay"; phy-handle = <ðphy1>; phy-mode = "rgmii"; }; &davinci_mdio { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mdio_pins>; ethphy0: ethernet-phy@0 { reg = <0>; }; ethphy1: ethernet-phy@1 { reg = <1>; }; }; &mac { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <ðernet_pins>; }; &am33xx_pinmux { ethernet_pins: pinmux_ethernet { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE2) /* ethernet interrupt */ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE7) /* rmii2_refclk.gpio0_29 */ /* ethernet PHY nReset */ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLUP, MUX_MODE7) /* mii1_col.gpio3_0 */ >; }; mdio_pins: pinmux_mdio { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; }; /* MMC */ &mmc1 { /* Bootable SD card slot */ status = "okay"; vmmc-supply = <&ldo3_reg>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&sd_pins>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; &mmc2 { /* eMMC (not populated) on MMC #2 */ status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&emmc_pins>; vmmc-supply = <&ldo3_reg>; bus-width = <8>; ti,non-removable; }; &mmc3 { /* Wifi & Bluetooth on MMC #3 */ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wireless_pins>; vmmmc-supply = <&v3v3c_reg>; bus-width = <4>; ti,non-removable; dmas = <&edma_xbar 12 0 1 &edma_xbar 13 0 2>; dma-names = "tx", "rx"; }; &am33xx_pinmux { sd_pins: pinmux_sd_card { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; emmc_pins: pinmux_emmc { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ /* EMMC nReset */ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ >; }; wireless_pins: pinmux_wireless { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc1_clk */ /* WLAN nReset */ AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ /* WLAN nPower down */ AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_wait0.gpio0_30 */ /* 32kHz Clock */ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; }; /* Power */ &vbat { regulator-name = "vbat"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; &v3v3c_reg { regulator-name = "v3v3c_reg"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <&vbat>; }; &vdd5_reg { regulator-name = "vdd5_reg"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; vin-supply = <&vbat>; }; /include/ "tps65217.dtsi" &tps { backlight { isel = <1>; /* ISET1 */ fdim = <200>; /* TPS65217_BL_FDIM_200HZ */ default-brightness = <80>; }; regulators { dcdc1_reg: regulator@0 { /* VDD_1V8 system supply */ regulator-always-on; }; dcdc2_reg: regulator@1 { /* VDD_CORE voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_core"; regulator-min-microvolt = <925000>; regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; dcdc3_reg: regulator@2 { /* VDD_MPU voltage limits 0.95V - 1.1V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <925000>; regulator-max-microvolt = <1325000>; regulator-boot-on; regulator-always-on; }; ldo1_reg: regulator@3 { /* VRTC 1.8V always-on supply */ regulator-name = "vrtc,vdds"; regulator-always-on; }; ldo2_reg: regulator@4 { /* 3.3V rail */ regulator-name = "vdd_3v3aux"; regulator-always-on; }; ldo3_reg: regulator@5 { /* VDD_3V3A 3.3V rail */ regulator-name = "vdd_3v3a"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: regulator@6 { /* VDD_3V3B 3.3V rail */ regulator-name = "vdd_3v3b"; regulator-always-on; }; }; }; /* SPI Busses */ &spi0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; }; &am33xx_pinmux { spi0_pins: pinmux_spi0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) >; }; }; /* Touch Screen */ &tscadc { status = "okay"; tsc { ti,wires = <4>; ti,x-plate-resistance = <200>; ti,coordinate-readouts = <5>; ti,wire-config = <0x00 0x11 0x22 0x33>; }; adc { ti,adc-channels = <4 5 6 7>; }; }; /* UARTs */ &uart0 { /* Serial Console */ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; }; &uart1 { /* Broken out to J6 header */ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; }; &am33xx_pinmux { uart0_pins: pinmux_uart0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; }; /* USB */ &usb { + status = "okay"; + pinctrl-names = "default"; pinctrl-0 = <&usb_pins>; }; +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + &usb0 { + status = "okay"; dr_mode = "host"; }; &usb1 { + status = "okay"; dr_mode = "host"; }; +&cppi41dma { + status = "okay"; +}; + &am33xx_pinmux { usb_pins: pinmux_usb { pinctrl-single,pins = < /* USB0 Over-Current (active low) */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7) /* gpmc_a9.gpio1_25 */ /* USB1 Over-Current (active low) */ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_26 */ >; }; }; /* User IO */ &leds { pinctrl-names = "default"; pinctrl-0 = <&user_leds_pins>; led0 { label = "pepper:user0:blue"; gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "off"; }; led1 { label = "pepper:user1:red"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "off"; }; }; &buttons { pinctrl-names = "default"; pinctrl-0 = <&user_buttons_pins>; #address-cells = <1>; #size-cells = <0>; button0 { label = "home"; linux,code = ; gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; wakeup-source; }; button1 { label = "menu"; linux,code = ; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; wakeup-source; }; buttons2 { label = "power"; linux,code = ; gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; wakeup-source; }; }; &am33xx_pinmux { user_leds_pins: pinmux_user_leds { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE7) /* gpmc_a4.gpio1_20 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ >; }; user_buttons_pins: pinmux_user_buttons { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a7.gpio1_21 */ AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio0_7 */ >; }; }; diff --git a/sys/gnu/dts/arm/am335x-pocketbeagle.dts b/sys/gnu/dts/arm/am335x-pocketbeagle.dts index 4da719098028..ff4f919d22f6 100644 --- a/sys/gnu/dts/arm/am335x-pocketbeagle.dts +++ b/sys/gnu/dts/arm/am335x-pocketbeagle.dts @@ -1,215 +1,237 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * * Author: Robert Nelson */ /dts-v1/; #include "am33xx.dtsi" #include "am335x-osd335x-common.dtsi" / { model = "TI AM335x PocketBeagle"; compatible = "ti,am335x-pocketbeagle", "ti,am335x-bone", "ti,am33xx"; chosen { stdout-path = &uart0; }; leds { pinctrl-names = "default"; pinctrl-0 = <&usr_leds_pins>; compatible = "gpio-leds"; usr0 { label = "beaglebone:green:usr0"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; usr1 { label = "beaglebone:green:usr1"; gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; usr2 { label = "beaglebone:green:usr2"; gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "cpu0"; default-state = "off"; }; usr3 { label = "beaglebone:green:usr3"; gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; }; &am33xx_pinmux { i2c2_pins: pinmux-i2c2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ >; }; ehrpwm0_pins: pinmux-ehrpwm0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (A13) mcasp0_aclkx.ehrpwm0A */ >; }; ehrpwm1_pins: pinmux-ehrpwm1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U14) gpmc_a2.ehrpwm1A */ >; }; mmc0_pins: pinmux-mmc0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* (B12) mcasp0_aclkr.mmc0_sdwp */ >; }; spi0_pins: pinmux-spi0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) >; }; spi1_pins: pinmux-spi1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* (C18) eCAP0_in_PWM0_out.spi1_sclk */ AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E18) uart0_ctsn.spi1_d0 */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E17) uart0_rtsn.spi1_d1 */ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE4) /* (A15) xdma_event_intr0.spi1_cs1 */ >; }; usr_leds_pins: pinmux-usr-leds-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ >; }; uart0_pins: pinmux-uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart4_pins: pinmux-uart4-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U17) gpmc_wpn.uart4_txd */ >; }; }; &epwmss0 { status = "okay"; }; &ehrpwm0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ehrpwm0_pins>; }; &epwmss1 { status = "okay"; }; &ehrpwm1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ehrpwm1_pins>; }; &i2c0 { eeprom: eeprom@50 { compatible = "atmel,24c256"; reg = <0x50>; }; }; &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; status = "okay"; clock-frequency = <400000>; }; &mmc1 { status = "okay"; vmmc-supply = <&vmmcsd_fixed>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; &rtc { system-power-controller; }; &tscadc { status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; ti,chan-step-avg = <16 16 16 16 16 16 16 16>; ti,chan-step-opendelay = <0x98 0x98 0x98 0x98 0x98 0x98 0x98 0x98>; ti,chan-step-sampledelay = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins>; status = "okay"; }; +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + &usb0 { + status = "okay"; dr_mode = "otg"; }; +&usb1_phy { + status = "okay"; +}; + &usb1 { + status = "okay"; dr_mode = "host"; }; + +&cppi41dma { + status = "okay"; +}; diff --git a/sys/gnu/dts/arm/am335x-regor.dtsi b/sys/gnu/dts/arm/am335x-regor.dtsi index 6fbf4ac739e7..5aff02a95766 100644 --- a/sys/gnu/dts/arm/am335x-regor.dtsi +++ b/sys/gnu/dts/arm/am335x-regor.dtsi @@ -1,202 +1,223 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Phytec Messtechnik GmbH * Author: Teresa Remmet * */ / { model = "Phytec AM335x phyBOARD-REGOR"; compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx"; vcc3v3: fixedregulator@1 { compatible = "regulator-fixed"; regulator-name = "vcc3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; }; /* User IO */ user_leds: user_leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&user_leds_pins>; run_stop-led { gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; linux,default-trigger = "gpio"; default-state = "off"; }; error-led { gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; linux,default-trigger = "gpio"; default-state = "off"; }; }; }; /* User Leds */ &am33xx_pinmux { user_leds_pins: pinmux_user_leds { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_22 */ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_fsx.gpio3_15 */ >; }; }; /* CAN Busses */ &am33xx_pinmux { dcan1_pins: pinmux_dcan1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ >; }; }; &dcan1 { pinctrl-names = "default"; pinctrl-0 = <&dcan1_pins>; status = "okay"; }; /* Ethernet */ &am33xx_pinmux { ethernet1_pins: pinmux_ethernet1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */ AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */ AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */ >; }; }; &cpsw_emac1 { phy-handle = <&phy1>; phy-mode = "mii"; dual_emac_res_vlan = <2>; }; &davinci_mdio { phy1: ethernet-phy@1 { reg = <1>; }; }; &mac { slaves = <2>; pinctrl-names = "default"; pinctrl-0 = <ðernet0_pins ðernet1_pins>; dual_emac = <1>; }; /* GPIOs */ &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&user_gpios_pins>; user_gpios_pins: pinmux_user_gpios { pinctrl-single,pins = < /* DIGIN 1-4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7) /* gpmc_ad11.gpio0_27 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT, MUX_MODE7) /* gpmc_ad9.gpio0_23 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT, MUX_MODE7) /* gpmc_ad8.gpio0_22 */ /* DIGOUT 1-4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad15.gpio1_15 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad14.gpio1_14 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad13.gpio1_13 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad12.gpio1_12 */ >; }; }; /* MMC */ &am33xx_pinmux { mmc1_pins: pinmux_mmc1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ >; }; }; &mmc1 { vmmc-supply = <&vcc3v3>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; status = "okay"; }; /* RTC */ &i2c_rtc { status = "okay"; }; /* UARTs */ &am33xx_pinmux { uart0_pins: pinmux_uart0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart2_pins: pinmux_uart2 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ >; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; status = "okay"; }; /* RS485 - UART1 */ &am33xx_pinmux { uart1_rs485_pins: pinmux_uart1_rs485_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_rs485_pins>; status = "okay"; linux,rs485-enabled-at-boot-time; }; + +/* USB */ +&cppi41dma { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; diff --git a/sys/gnu/dts/arm/am335x-sancloud-bbe.dts b/sys/gnu/dts/arm/am335x-sancloud-bbe.dts index e5fdb7abb0d5..8678e6e35493 100644 --- a/sys/gnu/dts/arm/am335x-sancloud-bbe.dts +++ b/sys/gnu/dts/arm/am335x-sancloud-bbe.dts @@ -1,137 +1,137 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; #include "am33xx.dtsi" #include "am335x-bone-common.dtsi" #include "am335x-boneblack-common.dtsi" #include / { model = "SanCloud BeagleBone Enhanced"; compatible = "sancloud,am335x-boneenhanced", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; }; &am33xx_pinmux { pinctrl-names = "default"; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; usb_hub_ctrl: usb_hub_ctrl { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* rmii1_refclk.gpio0_29 */ >; }; mpu6050_pins: pinmux_mpu6050_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ >; }; lps3331ap_pins: pinmux_lps3331ap_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_26 */ >; }; }; &mac { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; status = "okay"; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; status = "okay"; ethphy0: ethernet-phy@0 { reg = <0>; }; }; &cpsw_emac0 { phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii-txid"; }; &i2c0 { lps331ap: barometer@5c { compatible = "st,lps331ap-press"; st,drdy-int-pin = <1>; reg = <0x5c>; interrupt-parent = <&gpio1>; interrupts = <26 IRQ_TYPE_EDGE_RISING>; }; mpu6050: accelerometer@68 { compatible = "invensense,mpu6050"; reg = <0x68>; interrupt-parent = <&gpio0>; interrupts = <2 IRQ_TYPE_EDGE_RISING>; orientation = <0xff 0 0 0 1 0 0 0 0xff>; }; usb2512b: usb-hub@2c { compatible = "microchip,usb2512b"; reg = <0x2c>; reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; /* wifi on port 4 */ }; }; diff --git a/sys/gnu/dts/arm/am335x-shc.dts b/sys/gnu/dts/arm/am335x-shc.dts index 1eaa26533466..5b0368504015 100644 --- a/sys/gnu/dts/arm/am335x-shc.dts +++ b/sys/gnu/dts/arm/am335x-shc.dts @@ -1,555 +1,572 @@ // SPDX-License-Identifier: GPL-2.0 /* * support for the bosch am335x based shc c3 board * * Copyright, C) 2015 Heiko Schocher * */ /dts-v1/; #include "am33xx.dtsi" #include / { model = "Bosch SHC"; compatible = "ti,am335x-shc", "ti,am335x-bone", "ti,am33xx"; aliases { mmcblk0 = &mmc1; mmcblk1 = &mmc2; }; cpus { cpu@0 { /* * To consider voltage drop between PMIC and SoC, * tolerance value is reduced to 2% from 4% and * voltage value is increased as a precaution. */ operating-points = < /* kHz uV */ 594000 1225000 294000 1125000 >; voltage-tolerance = <2>; /* 2 percentage */ cpu0-supply = <&dcdc2_reg>; }; }; gpio_keys { compatible = "gpio-keys"; back_button { label = "Back Button"; gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; linux,code = ; debounce-interval = <1000>; wakeup-source; }; front_button { label = "Front Button"; gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; linux,code = ; debounce-interval = <1000>; wakeup-source; }; }; leds { pinctrl-names = "default"; pinctrl-0 = <&user_leds_s0>; compatible = "gpio-leds"; led1 { label = "shc:power:red"; gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led2 { label = "shc:power:bl"; gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; linux,default-trigger = "timer"; default-state = "on"; }; led3 { label = "shc:lan:red"; gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led4 { label = "shc:lan:bl"; gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led5 { label = "shc:cloud:red"; gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led6 { label = "shc:cloud:bl"; gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; }; &aes { status = "okay"; }; +&cppi41dma { + status = "okay"; +}; + &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; status = "okay"; ethernetphy0: ethernet-phy@0 { reg = <0>; smsc,disable-energy-detect; }; }; &epwmss1 { status = "okay"; ehrpwm1: pwm@200 { pinctrl-names = "default"; pinctrl-0 = <&ehrpwm1_pins>; status = "okay"; }; }; &gpio1 { hmtc_rst { gpio-hog; gpios = <24 GPIO_ACTIVE_LOW>; output-high; line-name = "homematic_reset"; }; hmtc_prog { gpio-hog; gpios = <27 GPIO_ACTIVE_LOW>; output-high; line-name = "homematic_program"; }; }; &gpio3 { zgb_rst { gpio-hog; gpios = <18 GPIO_ACTIVE_LOW>; output-low; line-name = "zigbee_reset"; }; zgb_boot { gpio-hog; gpios = <19 GPIO_ACTIVE_HIGH>; output-high; line-name = "zigbee_boot"; }; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; status = "okay"; clock-frequency = <400000>; tps: tps@24 { reg = <0x24>; }; at24@50 { compatible = "atmel,24c32"; pagesize = <32>; reg = <0x50>; }; pcf8563@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; &mac { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; status = "okay"; slaves = <1>; cpsw_emac0: slave@200 { phy-mode = "mii"; phy-handle = <ðernetphy0>; }; }; &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; bus-width = <0x4>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; cd-inverted; max-frequency = <26000000>; vmmc-supply = <&vmmcsd_fixed>; status = "okay"; }; &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&emmc_pins>; bus-width = <8>; max-frequency = <26000000>; sd-uhs-sdr25; vmmc-supply = <&vmmcsd_fixed>; status = "okay"; }; &mmc3 { pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins>; bus-width = <4>; cap-power-off-card; max-frequency = <26000000>; sd-uhs-sdr25; vmmc-supply = <&vmmcsd_fixed>; status = "okay"; }; &rtc { ti,no-init; }; &sham { status = "okay"; }; &tps { compatible = "ti,tps65217"; ti,pmic-shutdown-controller; regulators { #address-cells = <1>; #size-cells = <0>; dcdc1_reg: regulator@0 { reg = <0>; regulator-name = "vdds_dpr"; regulator-compatible = "dcdc1"; regulator-min-microvolt = <1300000>; regulator-max-microvolt = <1450000>; regulator-boot-on; regulator-always-on; }; dcdc2_reg: regulator@1 { reg = <1>; /* * VDD_MPU voltage limits 0.95V - 1.26V with * +/-4% tolerance */ regulator-compatible = "dcdc2"; regulator-name = "vdd_mpu"; regulator-min-microvolt = <925000>; regulator-max-microvolt = <1375000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <70000>; }; dcdc3_reg: regulator@2 { reg = <2>; /* * VDD_CORE voltage limits 0.95V - 1.1V with * +/-4% tolerance */ regulator-name = "vdd_core"; regulator-compatible = "dcdc3"; regulator-min-microvolt = <925000>; regulator-max-microvolt = <1125000>; regulator-boot-on; regulator-always-on; }; ldo1_reg: regulator@3 { reg = <3>; regulator-name = "vio,vrtc,vdds"; regulator-compatible = "ldo1"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; ldo2_reg: regulator@4 { reg = <4>; regulator-name = "vdd_3v3aux"; regulator-compatible = "ldo2"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; ldo3_reg: regulator@5 { reg = <5>; regulator-name = "vdd_1v8"; regulator-compatible = "ldo3"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; ldo4_reg: regulator@6 { reg = <6>; regulator-name = "vdd_3v3a"; regulator-compatible = "ldo4"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; status = "okay"; }; &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins>; status = "okay"; }; +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + &usb1 { + status = "okay"; dr_mode = "host"; }; &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&clkout2_pin>; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < /* xdma_event_intr1.clkout2 */ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT, MUX_MODE6) >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE0) >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; ehrpwm1_pins: pinmux_ehrpwm1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.gpio1_19 */ >; }; emmc_pins: pinmux_emmc_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE5) >; }; mmc3_pins: pinmux_mmc3_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE3) AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE3) AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT, MUX_MODE3) AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE3) AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT, MUX_MODE3) AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT, MUX_MODE3) >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0) >; }; uart1_pins: pinmux_uart1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) >; }; uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) >; }; uart4_pins: pinmux_uart4_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE6) >; }; user_leds_s0: user_leds_s0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLUP, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLUP, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7) >; }; }; diff --git a/sys/gnu/dts/arm/am335x-sl50.dts b/sys/gnu/dts/arm/am335x-sl50.dts index f4684c8eaffe..2f82095e7210 100644 --- a/sys/gnu/dts/arm/am335x-sl50.dts +++ b/sys/gnu/dts/arm/am335x-sl50.dts @@ -1,717 +1,739 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/ */ /dts-v1/; #include "am33xx.dtsi" #include #include / { model = "Toby Churchill SL50 Series"; compatible = "tcl,am335x-sl50", "ti,am33xx"; cpus { cpu@0 { cpu0-supply = <&dcdc2_reg>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; chosen { stdout-path = &uart0; }; leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&led_pins>; led0 { label = "sl50:red:usr0"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; default-state = "off"; }; led1 { label = "sl50:green:usr1"; gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; default-state = "off"; }; led2 { label = "sl50:red:usr2"; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; default-state = "off"; }; led3 { label = "sl50:green:usr3"; gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; default-state = "off"; }; }; backlight0: disp0 { compatible = "pwm-backlight"; pinctrl-names = "default"; pinctrl-0 = <&backlight0_pins>; pwms = <&ehrpwm1 0 500000 PWM_POLARITY_INVERTED>; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; default-brightness-level = <50>; enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; power-supply = <&vdd_sys_reg>; }; backlight1: disp1 { compatible = "pwm-backlight"; pinctrl-names = "default"; pinctrl-0 = <&backlight1_pins>; pwms = <&ehrpwm1 1 500000 PWM_POLARITY_INVERTED>; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; default-brightness-level = <50>; enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; power-supply = <&vdd_sys_reg>; }; clocks { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; /* audio external oscillator */ audio_mclk_fixed: oscillator@0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; /* 24.576MHz */ }; audio_mclk: audio_mclk_gate@0 { compatible = "gpio-gate-clock"; #clock-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&audio_mclk_pins>; clocks = <&audio_mclk_fixed>; enable-gpios = <&gpio1 27 0>; }; }; panel: lcd_panel { compatible = "ti,tilcdc,panel"; pinctrl-names = "default"; pinctrl-0 = <&lcd_pins>; panel-info { ac-bias = <255>; ac-bias-intrpt = <0>; dma-burst-sz = <16>; bpp = <16>; fdd = <0x80>; tft-alt-mode = <0>; mono-8bit-mode = <0>; sync-edge = <0>; sync-ctrl = <1>; raster-order = <0>; fifo-th = <0>; }; display-timings { native-mode = <&timing0>; timing0: 960x128 { clock-frequency = <18000000>; hactive = <960>; vactive = <272>; hback-porch = <40>; hfront-porch = <16>; hsync-len = <24>; hsync-active = <0>; vback-porch = <3>; vfront-porch = <8>; vsync-len = <4>; vsync-active = <0>; }; }; }; sound { compatible = "audio-graph-card"; label = "sound-card"; pinctrl-names = "default"; pinctrl-0 = <&audio_pa_pins>; widgets = "Headphone", "Headphone Jack", "Speaker", "Speaker External", "Line", "Line In", "Microphone", "Microphone Jack"; routing = "Headphone Jack", "HPLOUT", "Headphone Jack", "HPROUT", "Amplifier", "MONO_LOUT", "Speaker External", "Amplifier", "LINE1R", "Line In", "LINE1L", "Line In", "MIC3L", "Microphone Jack", "MIC3R", "Microphone Jack", "Microphone Jack", "Mic Bias"; dais = <&cpu_port>; pa-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; }; emmc_pwrseq: pwrseq@0 { compatible = "mmc-pwrseq-emmc"; pinctrl-names = "default"; pinctrl-0 = <&emmc_pwrseq_pins>; reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; }; vdd_sys_reg: regulator@0 { compatible = "regulator-fixed"; regulator-name = "vdd_sys_reg"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; }; vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; }; &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&lwb_pins>; audio_pins: pinmux_audio_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) >; }; audio_pa_pins: pinmux_audio_pa_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE7) /* SoundPA_en - mcasp0_aclkr.gpio3_18 */ >; }; audio_mclk_pins: pinmux_audio_mclk_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ >; }; backlight0_pins: pinmux_backlight0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */ >; }; backlight1_pins: pinmux_backlight1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */ >; }; lcd_pins: pinmux_lcd_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; led_pins: pinmux_led_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* gpmc_a6.gpio1_22 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* gpmc_a7.gpio1_23 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* gpmc_a8.gpio1_24 */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart4_pins: pinmux_uart4_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* gpmc_wait0.uart4_rxd */ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* gpmc_wpn.uart4_txd */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* Ethernet */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) /* Ethernet_nRST - gpmc_ad14.gpio1_14 */ >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ >; }; emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a4.gpio1_20 */ >; }; emmc_pins: pinmux_emmc_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ >; }; ehrpwm1_pins: pinmux_ehrpwm1a_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE6) /* gpmc_a2.ehrpwm1a */ AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.ehrpwm1b */ >; }; rtc0_irq_pins: pinmux_rtc0_irq_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ad9.gpio0_23 */ >; }; spi0_pins: pinmux_spi0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MOSI */ AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MISO */ AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS0 (NBATTSS) */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS1 (FPGA_FLASH_NCS) */ >; }; lwb_pins: pinmux_lwb_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ /* PDI Bus - Battery system */ AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */ /* FPGA */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_DONE - gpmc_ad8.gpio0_22 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_NRST - gpmc_a0.gpio1_16 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* FPGA_RUN - gpmc_a1.gpio1_17 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) /* ENFPGA - gpmc_a9.gpio1_25 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* FPGA_PROGRAM - gpmc_a10.gpio1_26 */ >; }; }; &i2c0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; clock-frequency = <400000>; tps: tps@24 { reg = <0x24>; }; rtc0: rtc@68 { compatible = "dallas,ds1339"; pinctrl-names = "default"; pinctrl-0 = <&rtc0_irq_pins>; interrupt-parent = <&gpio0>; interrupts = <23 IRQ_TYPE_EDGE_FALLING>; /* gpio 23 */ wakeup-source; trickle-resistor-ohms = <2000>; reg = <0x68>; }; eeprom: eeprom@50 { compatible = "atmel,24c256"; reg = <0x50>; }; gpio_exp: mcp23017@20 { compatible = "microchip,mcp23017"; reg = <0x20>; }; }; &i2c2 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; clock-frequency = <400000>; audio_codec: tlv320aic3106@1b { status = "okay"; compatible = "ti,tlv320aic3106"; #sound-dai-cells = <0>; reg = <0x1b>; ai3x-micbias-vg = <2>; /* 2.5V */ AVDD-supply = <&ldo4_reg>; IOVDD-supply = <&ldo4_reg>; DRVDD-supply = <&ldo4_reg>; DVDD-supply = <&ldo3_reg>; codec_port: port { codec_endpoint: endpoint { remote-endpoint = <&cpu_endpoint>; clocks = <&audio_mclk>; }; }; }; /* Ambient Light Sensor */ als: isl29023@44 { compatible = "isil,isl29023"; reg = <0x44>; }; }; &rtc { status = "disabled"; }; +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + &usb0 { + status = "okay"; dr_mode = "otg"; }; &usb1 { + status = "okay"; dr_mode = "host"; }; +&cppi41dma { + status = "okay"; +}; + &mmc1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; bus-width = <4>; cd-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; vmmc-supply = <&vmmcsd_fixed>; }; &mmc2 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&emmc_pins>; bus-width = <8>; vmmc-supply = <&vmmcsd_fixed>; mmc-pwrseq = <&emmc_pwrseq>; }; &mcasp0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&audio_pins>; #sound-dai-cells = <0>; op-mode = <0>; /* MCASP_ISS_MODE */ tdm-slots = <2>; /* 4 serializers */ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 0 0 1 2 >; tx-num-evt = <32>; rx-num-evt = <32>; cpu_port: port { cpu_endpoint: endpoint { remote-endpoint = <&codec_endpoint>; dai-format = "dsp_b"; bitclock-master = <&codec_port>; frame-master = <&codec_port>; bitclock-inversion; clocks = <&audio_mclk>; }; }; }; &uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; }; &uart1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; }; &uart4 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart4_pins>; }; &spi0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; flash: n25q032@1 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q032"; reg = <1>; spi-max-frequency = <5000000>; }; }; #include "tps65217.dtsi" &tps { ti,pmic-shutdown-controller; interrupt-parent = <&intc>; interrupts = <7>; /* NNMI */ regulators { dcdc1_reg: regulator@0 { /* VDDS_DDR */ regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; regulator-always-on; }; dcdc2_reg: regulator@1 { /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <925000>; regulator-max-microvolt = <1325000>; regulator-boot-on; regulator-always-on; }; dcdc3_reg: regulator@2 { /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ regulator-name = "vdd_core"; regulator-min-microvolt = <925000>; regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; ldo1_reg: regulator@3 { /* VRTC / VIO / VDDS*/ regulator-always-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; ldo2_reg: regulator@4 { /* VDD_3V3AUX */ regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo3_reg: regulator@5 { /* VDD_1V8 */ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; ldo4_reg: regulator@6 { /* VDD_3V3A */ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; }; &cpsw_emac0 { phy-mode = "mii"; phy-handle = <ðphy0>; }; &mac { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; }; &davinci_mdio { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; reset-delay-us = <100>; /* PHY datasheet states 100us min */ ethphy0: ethernet-phy@0 { reg = <0>; }; }; &sham { status = "okay"; }; &aes { status = "okay"; }; &epwmss1 { status = "okay"; }; &ehrpwm1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ehrpwm1_pins>; }; &lcdc { status = "okay"; }; &tscadc { status = "okay"; }; &am335x_adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; diff --git a/sys/gnu/dts/arm/am335x-wega.dtsi b/sys/gnu/dts/arm/am335x-wega.dtsi index 1359bf8715e6..61fc4cd2d164 100644 --- a/sys/gnu/dts/arm/am335x-wega.dtsi +++ b/sys/gnu/dts/arm/am335x-wega.dtsi @@ -1,196 +1,222 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 Phytec Messtechnik GmbH * Author: Teresa Remmet */ / { model = "Phytec AM335x phyBOARD-WEGA"; compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"; sound: sound_iface { compatible = "ti,da830-evm-audio"; }; vcc3v3: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "vcc3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; }; }; /* Audio */ &am33xx_pinmux { mcasp0_pins: pinmux_mcasp0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; }; &i2c0 { tlv320aic3007: tlv320aic3007@18 { compatible = "ti,tlv320aic3007"; reg = <0x18>; AVDD-supply = <&vcc3v3>; IOVDD-supply = <&vcc3v3>; DRVDD-supply = <&vcc3v3>; DVDD-supply = <&vdig1_reg>; status = "okay"; }; }; &mcasp0 { pinctrl-names = "default"; pinctrl-0 = <&mcasp0_pins>; op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ tdm-slots = <2>; serial-dir = < 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */ >; tx-num-evt = <16>; rt-num-evt = <16>; status = "okay"; }; &sound { ti,model = "AM335x-Wega"; ti,audio-codec = <&tlv320aic3007>; ti,mcasp-controller = <&mcasp0>; ti,audio-routing = "Line Out", "LLOUT", "Line Out", "RLOUT", "LINE1L", "Line In", "LINE1R", "Line In"; clocks = <&mcasp0_fck>; clock-names = "mclk"; status = "okay"; }; /* CAN Busses */ &am33xx_pinmux { dcan1_pins: pinmux_dcan1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ >; }; }; &dcan1 { pinctrl-names = "default"; pinctrl-0 = <&dcan1_pins>; status = "okay"; }; /* Ethernet */ &am33xx_pinmux { ethernet1_pins: pinmux_ethernet1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */ AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */ AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */ >; }; }; &cpsw_emac1 { phy-handle = <&phy1>; phy-mode = "mii"; dual_emac_res_vlan = <2>; }; &davinci_mdio { phy1: ethernet-phy@1 { reg = <1>; }; }; &mac { slaves = <2>; pinctrl-names = "default"; pinctrl-0 = <ðernet0_pins ðernet1_pins>; dual_emac = <1>; }; /* MMC */ &am33xx_pinmux { mmc1_pins: pinmux_mmc1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ >; }; }; &mmc1 { vmmc-supply = <&vcc3v3>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; status = "okay"; }; /* Power */ &vdig1_reg { regulator-boot-on; regulator-always-on; }; /* UARTs */ &am33xx_pinmux { uart0_pins: pinmux_uart0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; status = "okay"; }; +/* USB */ +&cppi41dma { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + &usb1 { dr_mode = "host"; + status = "okay"; +}; + +&usb1_phy { + status = "okay"; }; diff --git a/sys/gnu/dts/arm/am33xx-l4.dtsi b/sys/gnu/dts/arm/am33xx-l4.dtsi index 4e2986f0c604..7a9eb2b0d45b 100644 --- a/sys/gnu/dts/arm/am33xx-l4.dtsi +++ b/sys/gnu/dts/arm/am33xx-l4.dtsi @@ -1,2106 +1,2135 @@ &l4_wkup { /* 0x44c00000 */ compatible = "ti,am33xx-l4-wkup", "simple-bus"; reg = <0x44c00000 0x800>, <0x44c00800 0x800>, <0x44c01000 0x400>, <0x44c01400 0x400>; reg-names = "ap", "la", "ia0", "ia1"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ <0x00100000 0x44d00000 0x100000>, /* segment 1 */ <0x00200000 0x44e00000 0x100000>; /* segment 2 */ segment@0 { /* 0x44c00000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00000800 0x00000800 0x000800>, /* ap 1 */ <0x00001000 0x00001000 0x000400>, /* ap 2 */ <0x00001400 0x00001400 0x000400>; /* ap 3 */ }; segment@100000 { /* 0x44d00000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ <0x00004000 0x00104000 0x001000>, /* ap 5 */ <0x00080000 0x00180000 0x002000>, /* ap 6 */ <0x00082000 0x00182000 0x001000>; /* ap 7 */ target-module@0 { /* 0x44d00000, ap 4 28.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x0 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x4000>; status = "disabled"; }; target-module@80000 { /* 0x44d80000, ap 6 10.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000 0x2000>; }; }; segment@200000 { /* 0x44e00000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */ <0x00002000 0x00202000 0x001000>, /* ap 9 */ <0x00003000 0x00203000 0x001000>, /* ap 10 */ <0x00004000 0x00204000 0x001000>, /* ap 11 */ <0x00005000 0x00205000 0x001000>, /* ap 12 */ <0x00006000 0x00206000 0x001000>, /* ap 13 */ <0x00007000 0x00207000 0x001000>, /* ap 14 */ <0x00008000 0x00208000 0x001000>, /* ap 15 */ <0x00009000 0x00209000 0x001000>, /* ap 16 */ <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ <0x00010000 0x00210000 0x010000>, /* ap 22 */ <0x00020000 0x00220000 0x010000>, /* ap 23 */ <0x00030000 0x00230000 0x001000>, /* ap 24 */ <0x00031000 0x00231000 0x001000>, /* ap 25 */ <0x00032000 0x00232000 0x001000>, /* ap 26 */ <0x00033000 0x00233000 0x001000>, /* ap 27 */ <0x00034000 0x00234000 0x001000>, /* ap 28 */ <0x00035000 0x00235000 0x001000>, /* ap 29 */ <0x00036000 0x00236000 0x001000>, /* ap 30 */ <0x00037000 0x00237000 0x001000>, /* ap 31 */ <0x00038000 0x00238000 0x001000>, /* ap 32 */ <0x00039000 0x00239000 0x001000>, /* ap 33 */ <0x0003a000 0x0023a000 0x001000>, /* ap 34 */ <0x0003e000 0x0023e000 0x001000>, /* ap 35 */ <0x0003f000 0x0023f000 0x001000>, /* ap 36 */ <0x0000e000 0x0020e000 0x001000>, /* ap 37 */ <0x00040000 0x00240000 0x040000>, /* ap 38 */ <0x00080000 0x00280000 0x001000>; /* ap 39 */ target-module@0 { /* 0x44e00000, ap 8 58.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x2000>; prcm: prcm@0 { compatible = "ti,am3-prcm", "simple-bus"; reg = <0 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x2000>; prcm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; prcm_clockdomains: clockdomains { }; }; }; target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3000 0x1000>; }; target-module@5000 { /* 0x44e05000, ap 12 30.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5000 0x1000>; }; gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio1"; reg = <0x7000 0x4>, <0x7010 0x4>, <0x7114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>, <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x7000 0x1000>; gpio0: gpio@0 { compatible = "ti,omap4-gpio"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x1000>; interrupts = <96>; }; }; target-module@9000 { /* 0x44e09000, ap 16 04.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart1"; reg = <0x9050 0x4>, <0x9054 0x4>, <0x9058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9000 0x1000>; uart0: serial@0 { compatible = "ti,am3352-uart", "ti,omap3-uart"; clock-frequency = <48000000>; reg = <0x0 0x1000>; interrupts = <72>; status = "disabled"; dmas = <&edma 26 0>, <&edma 27 0>; dma-names = "tx", "rx"; }; }; target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c1"; reg = <0xb000 0x8>, <0xb010 0x8>, <0xb090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb000 0x1000>; i2c0: i2c@0 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x1000>; interrupts = <70>; status = "disabled"; }; }; target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "adc_tsc"; reg = <0xd000 0x4>, <0xd010 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , , ; /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x0000d000 0x00001000>, <0x00001000 0x0000e000 0x00001000>; tscadc: tscadc@0 { compatible = "ti,am3359-tscadc"; reg = <0x0 0x1000>; interrupts = <16>; status = "disabled"; dmas = <&edma 53 0>, <&edma 57 0>; dma-names = "fifo0", "fifo1"; tsc { compatible = "ti,am3359-tsc"; }; am335x_adc: adc { #io-channel-cells = <1>; compatible = "ti,am3359-adc"; }; }; }; target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x10000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00010000 0x00010000>, <0x00010000 0x00020000 0x00010000>; scm: scm@0 { compatible = "ti,am3-scm", "simple-bus"; reg = <0x0 0x2000>; #address-cells = <1>; #size-cells = <1>; #pinctrl-cells = <1>; ranges = <0 0 0x2000>; am33xx_pinmux: pinmux@800 { compatible = "pinctrl-single"; reg = <0x800 0x238>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x7f>; }; scm_conf: scm_conf@0 { compatible = "syscon", "simple-bus"; reg = <0x0 0x800>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x800>; phy_gmii_sel: phy-gmii-sel { compatible = "ti,am3352-phy-gmii-sel"; reg = <0x650 0x4>; #phy-cells = <2>; }; scm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; }; - usb_ctrl_mod: control@620 { - compatible = "ti,am335x-usb-ctrl-module"; - reg = <0x620 0x10>, - <0x648 0x4>; - reg-names = "phy_ctrl", "wakeup"; - }; - wkup_m3_ipc: wkup_m3_ipc@1324 { compatible = "ti,am3352-wkup-m3-ipc"; reg = <0x1324 0x24>; interrupts = <78>; ti,rproc = <&wkup_m3>; mboxes = <&mailbox &mbox_wkupm3>; }; edma_xbar: dma-router@f90 { compatible = "ti,am335x-edma-crossbar"; reg = <0xf90 0x40>; #dma-cells = <3>; dma-requests = <32>; dma-masters = <&edma>; }; scm_clockdomains: clockdomains { }; }; }; target-module@31000 { /* 0x44e31000, ap 25 40.0 */ compatible = "ti,sysc-omap2-timer", "ti,sysc"; ti,hwmods = "timer1"; reg = <0x31000 0x4>, <0x31010 0x4>, <0x31014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x31000 0x1000>; timer1: timer@0 { compatible = "ti,am335x-timer-1ms"; reg = <0x0 0x400>; interrupts = <67>; ti,timer-alwon; clocks = <&timer1_fck>; clock-names = "fck"; }; }; target-module@33000 { /* 0x44e33000, ap 27 18.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x33000 0x1000>; }; target-module@35000 { /* 0x44e35000, ap 29 50.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "wd_timer2"; reg = <0x35000 0x4>, <0x35010 0x4>, <0x35014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x35000 0x1000>; wdt2: wdt@0 { compatible = "ti,omap3-wdt"; reg = <0x0 0x1000>; interrupts = <91>; }; }; target-module@37000 { /* 0x44e37000, ap 31 08.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x37000 0x1000>; }; target-module@39000 { /* 0x44e39000, ap 33 02.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x39000 0x1000>; }; target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */ compatible = "ti,sysc-omap4-simple", "ti,sysc"; ti,hwmods = "rtc"; reg = <0x3e074 0x4>, <0x3e078 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , , ; /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3e000 0x1000>; rtc: rtc@0 { compatible = "ti,am3352-rtc", "ti,da830-rtc"; reg = <0x0 0x1000>; interrupts = <75 76>; }; }; target-module@40000 { /* 0x44e40000, ap 38 68.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x40000 0x40000>; }; }; }; &l4_fw { /* 0x47c00000 */ compatible = "ti,am33xx-l4-fw", "simple-bus"; reg = <0x47c00000 0x800>, <0x47c00800 0x800>, <0x47c01000 0x400>; reg-names = "ap", "la", "ia0"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */ segment@0 { /* 0x47c00000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00000800 0x00000800 0x000800>, /* ap 1 */ <0x00001000 0x00001000 0x000400>, /* ap 2 */ <0x0000c000 0x0000c000 0x001000>, /* ap 3 */ <0x0000d000 0x0000d000 0x001000>, /* ap 4 */ <0x0000e000 0x0000e000 0x001000>, /* ap 5 */ <0x0000f000 0x0000f000 0x001000>, /* ap 6 */ <0x00010000 0x00010000 0x001000>, /* ap 7 */ <0x00011000 0x00011000 0x001000>, /* ap 8 */ <0x0001a000 0x0001a000 0x001000>, /* ap 9 */ <0x0001b000 0x0001b000 0x001000>, /* ap 10 */ <0x00024000 0x00024000 0x001000>, /* ap 11 */ <0x00025000 0x00025000 0x001000>, /* ap 12 */ <0x00026000 0x00026000 0x001000>, /* ap 13 */ <0x00027000 0x00027000 0x001000>, /* ap 14 */ <0x00030000 0x00030000 0x001000>, /* ap 15 */ <0x00031000 0x00031000 0x001000>, /* ap 16 */ <0x00038000 0x00038000 0x001000>, /* ap 17 */ <0x00039000 0x00039000 0x001000>, /* ap 18 */ <0x0003a000 0x0003a000 0x001000>, /* ap 19 */ <0x0003b000 0x0003b000 0x001000>, /* ap 20 */ <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ <0x0003f000 0x0003f000 0x001000>, /* ap 22 */ <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ <0x00040000 0x00040000 0x001000>, /* ap 24 */ <0x00046000 0x00046000 0x001000>, /* ap 25 */ <0x00047000 0x00047000 0x001000>, /* ap 26 */ <0x00044000 0x00044000 0x001000>, /* ap 27 */ <0x00045000 0x00045000 0x001000>, /* ap 28 */ <0x00028000 0x00028000 0x001000>, /* ap 29 */ <0x00029000 0x00029000 0x001000>, /* ap 30 */ <0x00032000 0x00032000 0x001000>, /* ap 31 */ <0x00033000 0x00033000 0x001000>, /* ap 32 */ <0x0003d000 0x0003d000 0x001000>, /* ap 33 */ <0x00041000 0x00041000 0x001000>, /* ap 34 */ <0x00042000 0x00042000 0x001000>, /* ap 35 */ <0x00043000 0x00043000 0x001000>, /* ap 36 */ <0x00014000 0x00014000 0x001000>, /* ap 37 */ <0x00015000 0x00015000 0x001000>; /* ap 38 */ target-module@c000 { /* 0x47c0c000, ap 3 04.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc000 0x1000>; }; target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe000 0x1000>; }; target-module@10000 { /* 0x47c10000, ap 7 20.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x10000 0x1000>; }; target-module@14000 { /* 0x47c14000, ap 37 3c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x14000 0x1000>; }; target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1a000 0x1000>; }; target-module@24000 { /* 0x47c24000, ap 11 28.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x24000 0x1000>; }; target-module@26000 { /* 0x47c26000, ap 13 30.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x26000 0x1000>; }; target-module@28000 { /* 0x47c28000, ap 29 40.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x28000 0x1000>; }; target-module@30000 { /* 0x47c30000, ap 15 14.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x30000 0x1000>; }; target-module@32000 { /* 0x47c32000, ap 31 06.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x32000 0x1000>; }; target-module@38000 { /* 0x47c38000, ap 17 18.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x38000 0x1000>; }; target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3a000 0x1000>; }; target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3c000 0x1000>; }; target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3e000 0x1000>; }; target-module@40000 { /* 0x47c40000, ap 24 02.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x40000 0x1000>; }; target-module@42000 { /* 0x47c42000, ap 35 34.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x42000 0x1000>; }; target-module@44000 { /* 0x47c44000, ap 27 24.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x44000 0x1000>; }; target-module@46000 { /* 0x47c46000, ap 25 2c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x46000 0x1000>; }; }; }; &l4_fast { /* 0x4a000000 */ compatible = "ti,am33xx-l4-fast", "simple-bus"; reg = <0x4a000000 0x800>, <0x4a000800 0x800>, <0x4a001000 0x400>; reg-names = "ap", "la", "ia0"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ segment@0 { /* 0x4a000000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00000800 0x00000800 0x000800>, /* ap 1 */ <0x00001000 0x00001000 0x000400>, /* ap 2 */ <0x00100000 0x00100000 0x008000>, /* ap 3 */ <0x00108000 0x00108000 0x001000>, /* ap 4 */ <0x00180000 0x00180000 0x020000>, /* ap 5 */ <0x001a0000 0x001a0000 0x001000>, /* ap 6 */ <0x00200000 0x00200000 0x080000>, /* ap 7 */ <0x00280000 0x00280000 0x001000>, /* ap 8 */ <0x00300000 0x00300000 0x080000>, /* ap 9 */ <0x00380000 0x00380000 0x001000>; /* ap 10 */ target-module@100000 { /* 0x4a100000, ap 3 08.0 */ compatible = "ti,sysc-omap4-simple", "ti,sysc"; reg = <0x101200 0x4>, <0x101208 0x4>, <0x101204 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <0>; ti,sysc-midle = , ; ti,sysc-sidle = , ; ti,syss-mask = <1>; clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x100000 0x8000>; mac: ethernet@0 { compatible = "ti,am335x-cpsw","ti,cpsw"; clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; clock-names = "fck", "cpts"; cpdma_channels = <8>; ale_entries = <1024>; bd_ram_size = <0x2000>; mac_control = <0x20>; slaves = <2>; active_slave = <0>; cpts_clock_mult = <0x80000000>; cpts_clock_shift = <29>; reg = <0x0 0x800 0x1200 0x100>; #address-cells = <1>; #size-cells = <1>; /* * c0_rx_thresh_pend * c0_rx_pend * c0_tx_pend * c0_misc_pend */ interrupts = <40 41 42 43>; ranges = <0 0 0x8000>; syscon = <&scm_conf>; status = "disabled"; davinci_mdio: mdio@1000 { compatible = "ti,cpsw-mdio","ti,davinci_mdio"; clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; reg = <0x1000 0x100>; status = "disabled"; }; cpsw_emac0: slave@200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; phys = <&phy_gmii_sel 1 1>; }; cpsw_emac1: slave@300 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; phys = <&phy_gmii_sel 2 1>; }; }; }; target-module@180000 { /* 0x4a180000, ap 5 10.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x180000 0x20000>; }; target-module@200000 { /* 0x4a200000, ap 7 02.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x200000 0x80000>; }; target-module@300000 { /* 0x4a300000, ap 9 04.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x300000 0x80000>; }; }; }; &l4_mpuss { /* 0x4b140000 */ compatible = "ti,am33xx-l4-mpuss", "simple-bus"; reg = <0x4b144400 0x100>, <0x4b144800 0x400>; reg-names = "la", "ap"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */ segment@0 { /* 0x4b140000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */ <0x00001000 0x00001000 0x001000>, /* ap 1 */ <0x00002000 0x00002000 0x001000>, /* ap 2 */ <0x00004000 0x00004000 0x000400>, /* ap 3 */ <0x00005000 0x00005000 0x000400>, /* ap 4 */ <0x00000000 0x00000000 0x001000>, /* ap 5 */ <0x00003000 0x00003000 0x001000>, /* ap 6 */ <0x00000800 0x00000800 0x000800>; /* ap 7 */ target-module@0 { /* 0x4b140000, ap 5 02.2 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x00001000>, <0x00001000 0x00001000 0x00001000>, <0x00002000 0x00002000 0x00001000>; }; target-module@3000 { /* 0x4b143000, ap 6 04.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3000 0x1000>; }; }; }; &l4_per { /* 0x48000000 */ compatible = "ti,am33xx-l4-per", "simple-bus"; reg = <0x48000000 0x800>, <0x48000800 0x800>, <0x48001000 0x400>, <0x48001400 0x400>, <0x48001800 0x400>, <0x48001c00 0x400>; reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ <0x00100000 0x48100000 0x100000>, /* segment 1 */ <0x00200000 0x48200000 0x100000>, /* segment 2 */ <0x00300000 0x48300000 0x100000>, /* segment 3 */ <0x46000000 0x46000000 0x400000>, /* l3 data port */ <0x46400000 0x46400000 0x400000>; /* l3 data port */ segment@0 { /* 0x48000000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00000800 0x00000800 0x000800>, /* ap 1 */ <0x00001000 0x00001000 0x000400>, /* ap 2 */ <0x00001400 0x00001400 0x000400>, /* ap 3 */ <0x00001800 0x00001800 0x000400>, /* ap 4 */ <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ <0x00008000 0x00008000 0x001000>, /* ap 6 */ <0x00009000 0x00009000 0x001000>, /* ap 7 */ <0x00016000 0x00016000 0x001000>, /* ap 8 */ <0x00017000 0x00017000 0x001000>, /* ap 9 */ <0x00022000 0x00022000 0x001000>, /* ap 10 */ <0x00023000 0x00023000 0x001000>, /* ap 11 */ <0x00024000 0x00024000 0x001000>, /* ap 12 */ <0x00025000 0x00025000 0x001000>, /* ap 13 */ <0x0002a000 0x0002a000 0x001000>, /* ap 14 */ <0x0002b000 0x0002b000 0x001000>, /* ap 15 */ <0x00038000 0x00038000 0x002000>, /* ap 16 */ <0x0003a000 0x0003a000 0x001000>, /* ap 17 */ <0x00014000 0x00014000 0x001000>, /* ap 18 */ <0x00015000 0x00015000 0x001000>, /* ap 19 */ <0x0003c000 0x0003c000 0x002000>, /* ap 20 */ <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ <0x00040000 0x00040000 0x001000>, /* ap 22 */ <0x00041000 0x00041000 0x001000>, /* ap 23 */ <0x00042000 0x00042000 0x001000>, /* ap 24 */ <0x00043000 0x00043000 0x001000>, /* ap 25 */ <0x00044000 0x00044000 0x001000>, /* ap 26 */ <0x00045000 0x00045000 0x001000>, /* ap 27 */ <0x00046000 0x00046000 0x001000>, /* ap 28 */ <0x00047000 0x00047000 0x001000>, /* ap 29 */ <0x00048000 0x00048000 0x001000>, /* ap 30 */ <0x00049000 0x00049000 0x001000>, /* ap 31 */ <0x0004c000 0x0004c000 0x001000>, /* ap 32 */ <0x0004d000 0x0004d000 0x001000>, /* ap 33 */ <0x00050000 0x00050000 0x002000>, /* ap 34 */ <0x00052000 0x00052000 0x001000>, /* ap 35 */ <0x00060000 0x00060000 0x001000>, /* ap 36 */ <0x00061000 0x00061000 0x001000>, /* ap 37 */ <0x00080000 0x00080000 0x010000>, /* ap 38 */ <0x00090000 0x00090000 0x001000>, /* ap 39 */ <0x000a0000 0x000a0000 0x010000>, /* ap 40 */ <0x000b0000 0x000b0000 0x001000>, /* ap 41 */ <0x00030000 0x00030000 0x001000>, /* ap 77 */ <0x00031000 0x00031000 0x001000>, /* ap 78 */ <0x0004a000 0x0004a000 0x001000>, /* ap 85 */ <0x0004b000 0x0004b000 0x001000>, /* ap 86 */ <0x000c8000 0x000c8000 0x001000>, /* ap 87 */ <0x000c9000 0x000c9000 0x001000>, /* ap 88 */ <0x000cc000 0x000cc000 0x001000>, /* ap 89 */ <0x000cd000 0x000cd000 0x001000>, /* ap 90 */ <0x000ca000 0x000ca000 0x001000>, /* ap 91 */ <0x000cb000 0x000cb000 0x001000>, /* ap 92 */ <0x46000000 0x46000000 0x400000>, /* l3 data port */ <0x46400000 0x46400000 0x400000>; /* l3 data port */ target-module@8000 { /* 0x48008000, ap 6 10.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x1000>; }; target-module@14000 { /* 0x48014000, ap 18 58.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x14000 0x1000>; }; target-module@16000 { /* 0x48016000, ap 8 3c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x16000 0x1000>; }; target-module@22000 { /* 0x48022000, ap 10 12.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart2"; reg = <0x22050 0x4>, <0x22054 0x4>, <0x22058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x22000 0x1000>; uart1: serial@0 { compatible = "ti,am3352-uart", "ti,omap3-uart"; clock-frequency = <48000000>; reg = <0x0 0x1000>; interrupts = <73>; status = "disabled"; dmas = <&edma 28 0>, <&edma 29 0>; dma-names = "tx", "rx"; }; }; target-module@24000 { /* 0x48024000, ap 12 14.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart3"; reg = <0x24050 0x4>, <0x24054 0x4>, <0x24058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x24000 0x1000>; uart2: serial@0 { compatible = "ti,am3352-uart", "ti,omap3-uart"; clock-frequency = <48000000>; reg = <0x0 0x1000>; interrupts = <74>; status = "disabled"; dmas = <&edma 30 0>, <&edma 31 0>; dma-names = "tx", "rx"; }; }; target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c2"; reg = <0x2a000 0x8>, <0x2a010 0x8>, <0x2a090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2a000 0x1000>; i2c1: i2c@0 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x1000>; interrupts = <71>; status = "disabled"; }; }; target-module@30000 { /* 0x48030000, ap 77 08.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spi0"; reg = <0x30000 0x4>, <0x30110 0x4>, <0x30114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x30000 0x1000>; spi0: spi@0 { compatible = "ti,omap4-mcspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x400>; interrupts = <65>; ti,spi-num-cs = <2>; dmas = <&edma 16 0 &edma 17 0 &edma 18 0 &edma 19 0>; dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; }; target-module@38000 { /* 0x48038000, ap 16 02.0 */ compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "mcasp0"; reg = <0x38000 0x4>, <0x38004 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , ; /* Domains (P, C): per_pwrdm, l3s_clkdm */ clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x38000 0x2000>, <0x46000000 0x46000000 0x400000>; mcasp0: mcasp@0 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x2000>, <0x46000000 0x400000>; reg-names = "mpu", "dat"; interrupts = <80>, <81>; interrupt-names = "tx", "rx"; status = "disabled"; dmas = <&edma 8 2>, <&edma 9 2>; dma-names = "tx", "rx"; }; }; target-module@3c000 { /* 0x4803c000, ap 20 32.0 */ compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "mcasp1"; reg = <0x3c000 0x4>, <0x3c004 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , ; /* Domains (P, C): per_pwrdm, l3s_clkdm */ clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3c000 0x2000>, <0x46400000 0x46400000 0x400000>; mcasp1: mcasp@0 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x2000>, <0x46400000 0x400000>; reg-names = "mpu", "dat"; interrupts = <82>, <83>; interrupt-names = "tx", "rx"; status = "disabled"; dmas = <&edma 10 2>, <&edma 11 2>; dma-names = "tx", "rx"; }; }; target-module@40000 { /* 0x48040000, ap 22 1e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; ti,hwmods = "timer2"; reg = <0x40000 0x4>, <0x40010 0x4>, <0x40014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x40000 0x1000>; timer2: timer@0 { compatible = "ti,am335x-timer"; reg = <0x0 0x400>; interrupts = <68>; clocks = <&timer2_fck>; clock-names = "fck"; }; }; target-module@42000 { /* 0x48042000, ap 24 1c.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer3"; reg = <0x42000 0x4>, <0x42010 0x4>, <0x42014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x42000 0x1000>; timer3: timer@0 { compatible = "ti,am335x-timer"; reg = <0x0 0x400>; interrupts = <69>; }; }; target-module@44000 { /* 0x48044000, ap 26 26.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer4"; reg = <0x44000 0x4>, <0x44010 0x4>, <0x44014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x44000 0x1000>; timer4: timer@0 { compatible = "ti,am335x-timer"; reg = <0x0 0x400>; interrupts = <92>; ti,timer-pwm; }; }; target-module@46000 { /* 0x48046000, ap 28 28.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer5"; reg = <0x46000 0x4>, <0x46010 0x4>, <0x46014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x46000 0x1000>; timer5: timer@0 { compatible = "ti,am335x-timer"; reg = <0x0 0x400>; interrupts = <93>; ti,timer-pwm; }; }; target-module@48000 { /* 0x48048000, ap 30 22.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer6"; reg = <0x48000 0x4>, <0x48010 0x4>, <0x48014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x48000 0x1000>; timer6: timer@0 { compatible = "ti,am335x-timer"; reg = <0x0 0x400>; interrupts = <94>; ti,timer-pwm; }; }; target-module@4a000 { /* 0x4804a000, ap 85 60.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer7"; reg = <0x4a000 0x4>, <0x4a010 0x4>, <0x4a014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4a000 0x1000>; timer7: timer@0 { compatible = "ti,am335x-timer"; reg = <0x0 0x400>; interrupts = <95>; ti,timer-pwm; }; }; target-module@4c000 { /* 0x4804c000, ap 32 36.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio2"; reg = <0x4c000 0x4>, <0x4c010 0x4>, <0x4c114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>, <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4c000 0x1000>; gpio1: gpio@0 { compatible = "ti,omap4-gpio"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x1000>; interrupts = <98>; }; }; target-module@50000 { /* 0x48050000, ap 34 2c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x50000 0x2000>; }; target-module@60000 { /* 0x48060000, ap 36 0c.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mmc1"; reg = <0x602fc 0x4>, <0x60110 0x4>, <0x60114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x60000 0x1000>; mmc1: mmc@0 { compatible = "ti,omap4-hsmmc"; ti,dual-volt; ti,needs-special-reset; ti,needs-special-hs-handling; dmas = <&edma_xbar 24 0 0 &edma_xbar 25 0 0>; dma-names = "tx", "rx"; interrupts = <64>; reg = <0x0 0x1000>; status = "disabled"; }; }; target-module@80000 { /* 0x48080000, ap 38 18.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "elm"; reg = <0x80000 0x4>, <0x80010 0x4>, <0x80014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000 0x10000>; elm: elm@0 { compatible = "ti,am3352-elm"; reg = <0x0 0x2000>; interrupts = <4>; status = "disabled"; }; }; target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa0000 0x10000>; }; target-module@c8000 { /* 0x480c8000, ap 87 06.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox"; reg = <0xc8000 0x4>, <0xc8010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc8000 0x1000>; mailbox: mailbox@0 { compatible = "ti,omap4-mailbox"; reg = <0x0 0x200>; interrupts = <77>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; mbox_wkupm3: wkup_m3 { ti,mbox-send-noirq; ti,mbox-tx = <0 0 0>; ti,mbox-rx = <0 0 3>; }; }; }; target-module@ca000 { /* 0x480ca000, ap 91 40.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spinlock"; reg = <0xca000 0x4>, <0xca010 0x4>, <0xca014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xca000 0x1000>; hwspinlock: spinlock@0 { compatible = "ti,omap4-hwspinlock"; reg = <0x0 0x1000>; #hwlock-cells = <1>; }; }; target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xcc000 0x1000>; }; }; segment@100000 { /* 0x48100000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */ <0x0008d000 0x0018d000 0x001000>, /* ap 43 */ <0x0008e000 0x0018e000 0x001000>, /* ap 44 */ <0x0008f000 0x0018f000 0x001000>, /* ap 45 */ <0x0009c000 0x0019c000 0x001000>, /* ap 46 */ <0x0009d000 0x0019d000 0x001000>, /* ap 47 */ <0x000a6000 0x001a6000 0x001000>, /* ap 48 */ <0x000a7000 0x001a7000 0x001000>, /* ap 49 */ <0x000a8000 0x001a8000 0x001000>, /* ap 50 */ <0x000a9000 0x001a9000 0x001000>, /* ap 51 */ <0x000aa000 0x001aa000 0x001000>, /* ap 52 */ <0x000ab000 0x001ab000 0x001000>, /* ap 53 */ <0x000ac000 0x001ac000 0x001000>, /* ap 54 */ <0x000ad000 0x001ad000 0x001000>, /* ap 55 */ <0x000ae000 0x001ae000 0x001000>, /* ap 56 */ <0x000af000 0x001af000 0x001000>, /* ap 57 */ <0x000b0000 0x001b0000 0x010000>, /* ap 58 */ <0x000c0000 0x001c0000 0x001000>, /* ap 59 */ <0x000cc000 0x001cc000 0x002000>, /* ap 60 */ <0x000ce000 0x001ce000 0x002000>, /* ap 61 */ <0x000d0000 0x001d0000 0x002000>, /* ap 62 */ <0x000d2000 0x001d2000 0x002000>, /* ap 63 */ <0x000d8000 0x001d8000 0x001000>, /* ap 64 */ <0x000d9000 0x001d9000 0x001000>, /* ap 65 */ <0x000a0000 0x001a0000 0x001000>, /* ap 79 */ <0x000a1000 0x001a1000 0x001000>, /* ap 80 */ <0x000a2000 0x001a2000 0x001000>, /* ap 81 */ <0x000a3000 0x001a3000 0x001000>, /* ap 82 */ <0x000a4000 0x001a4000 0x001000>, /* ap 83 */ <0x000a5000 0x001a5000 0x001000>; /* ap 84 */ target-module@8c000 { /* 0x4818c000, ap 42 04.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8c000 0x1000>; }; target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8e000 0x1000>; }; target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c3"; reg = <0x9c000 0x8>, <0x9c010 0x8>, <0x9c090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9c000 0x1000>; i2c2: i2c@0 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x1000>; interrupts = <30>; status = "disabled"; }; }; target-module@a0000 { /* 0x481a0000, ap 79 24.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spi1"; reg = <0xa0000 0x4>, <0xa0110 0x4>, <0xa0114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa0000 0x1000>; spi1: spi@0 { compatible = "ti,omap4-mcspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x400>; interrupts = <125>; ti,spi-num-cs = <2>; dmas = <&edma 42 0 &edma 43 0 &edma 44 0 &edma 45 0>; dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; }; target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa2000 0x1000>; }; target-module@a4000 { /* 0x481a4000, ap 83 30.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa4000 0x1000>; }; target-module@a6000 { /* 0x481a6000, ap 48 16.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart4"; reg = <0xa6050 0x4>, <0xa6054 0x4>, <0xa6058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa6000 0x1000>; uart3: serial@0 { compatible = "ti,am3352-uart", "ti,omap3-uart"; clock-frequency = <48000000>; reg = <0x0 0x1000>; interrupts = <44>; status = "disabled"; }; }; target-module@a8000 { /* 0x481a8000, ap 50 20.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart5"; reg = <0xa8050 0x4>, <0xa8054 0x4>, <0xa8058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa8000 0x1000>; uart4: serial@0 { compatible = "ti,am3352-uart", "ti,omap3-uart"; clock-frequency = <48000000>; reg = <0x0 0x1000>; interrupts = <45>; status = "disabled"; }; }; target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart6"; reg = <0xaa050 0x4>, <0xaa054 0x4>, <0xaa058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xaa000 0x1000>; uart5: serial@0 { compatible = "ti,am3352-uart", "ti,omap3-uart"; clock-frequency = <48000000>; reg = <0x0 0x1000>; interrupts = <46>; status = "disabled"; }; }; target-module@ac000 { /* 0x481ac000, ap 54 38.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio3"; reg = <0xac000 0x4>, <0xac010 0x4>, <0xac114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>, <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xac000 0x1000>; gpio2: gpio@0 { compatible = "ti,omap4-gpio"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x1000>; interrupts = <32>; }; }; target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio4"; reg = <0xae000 0x4>, <0xae010 0x4>, <0xae114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>, <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xae000 0x1000>; gpio3: gpio@0 { compatible = "ti,omap4-gpio"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x1000>; interrupts = <62>; }; }; target-module@b0000 { /* 0x481b0000, ap 58 50.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb0000 0x10000>; }; target-module@cc000 { /* 0x481cc000, ap 60 46.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xcc020 0x4>; reg-names = "rev"; + ti,hwmods = "d_can0"; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>, <&dcan0_fck>; clock-names = "fck", "osc"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xcc000 0x2000>; dcan0: can@0 { compatible = "ti,am3352-d_can"; reg = <0x0 0x2000>; clocks = <&dcan0_fck>; clock-names = "fck"; syscon-raminit = <&scm_conf 0x644 0>; interrupts = <52>; status = "disabled"; }; }; target-module@d0000 { /* 0x481d0000, ap 62 42.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xd0020 0x4>; reg-names = "rev"; + ti,hwmods = "d_can1"; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>, <&dcan1_fck>; clock-names = "fck", "osc"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd0000 0x2000>; dcan1: can@0 { compatible = "ti,am3352-d_can"; reg = <0x0 0x2000>; clocks = <&dcan1_fck>; clock-names = "fck"; syscon-raminit = <&scm_conf 0x644 1>; interrupts = <55>; status = "disabled"; }; }; target-module@d8000 { /* 0x481d8000, ap 64 66.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mmc2"; reg = <0xd82fc 0x4>, <0xd8110 0x4>, <0xd8114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd8000 0x1000>; mmc2: mmc@0 { compatible = "ti,omap4-hsmmc"; ti,needs-special-reset; dmas = <&edma 2 0 &edma 3 0>; dma-names = "tx", "rx"; interrupts = <28>; reg = <0x0 0x1000>; status = "disabled"; }; }; }; segment@200000 { /* 0x48200000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; }; segment@300000 { /* 0x48300000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */ <0x00001000 0x00301000 0x001000>, /* ap 67 */ <0x00002000 0x00302000 0x001000>, /* ap 68 */ <0x00003000 0x00303000 0x001000>, /* ap 69 */ <0x00004000 0x00304000 0x001000>, /* ap 70 */ <0x00005000 0x00305000 0x001000>, /* ap 71 */ <0x0000e000 0x0030e000 0x001000>, /* ap 72 */ <0x0000f000 0x0030f000 0x001000>, /* ap 73 */ <0x00018000 0x00318000 0x004000>, /* ap 74 */ <0x0001c000 0x0031c000 0x001000>, /* ap 75 */ <0x00010000 0x00310000 0x002000>, /* ap 76 */ <0x00012000 0x00312000 0x001000>, /* ap 93 */ <0x00015000 0x00315000 0x001000>, /* ap 94 */ <0x00016000 0x00316000 0x001000>, /* ap 95 */ <0x00017000 0x00317000 0x001000>, /* ap 96 */ <0x00013000 0x00313000 0x001000>, /* ap 97 */ <0x00014000 0x00314000 0x001000>, /* ap 98 */ <0x00020000 0x00320000 0x001000>, /* ap 99 */ <0x00021000 0x00321000 0x001000>, /* ap 100 */ <0x00022000 0x00322000 0x001000>, /* ap 101 */ <0x00023000 0x00323000 0x001000>, /* ap 102 */ <0x00024000 0x00324000 0x001000>, /* ap 103 */ <0x00025000 0x00325000 0x001000>; /* ap 104 */ target-module@0 { /* 0x48300000, ap 66 48.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss0"; reg = <0x0 0x4>, <0x4 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x1000>; epwmss0: epwmss@0 { compatible = "ti,am33xx-pwmss"; reg = <0x0 0x10>; #address-cells = <1>; #size-cells = <1>; status = "disabled"; ranges = <0 0 0x1000>; ecap0: ecap@100 { compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; interrupts = <31>; interrupt-names = "ecap0"; status = "disabled"; }; ehrpwm0: pwm@200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; }; }; }; target-module@2000 { /* 0x48302000, ap 68 52.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss1"; reg = <0x2000 0x4>, <0x2004 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x1000>; epwmss1: epwmss@0 { compatible = "ti,am33xx-pwmss"; reg = <0x0 0x10>; #address-cells = <1>; #size-cells = <1>; status = "disabled"; ranges = <0 0 0x1000>; ecap1: ecap@100 { compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; interrupts = <47>; interrupt-names = "ecap1"; status = "disabled"; }; ehrpwm1: pwm@200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; }; }; }; target-module@4000 { /* 0x48304000, ap 70 44.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss2"; reg = <0x4000 0x4>, <0x4004 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; epwmss2: epwmss@0 { compatible = "ti,am33xx-pwmss"; reg = <0x0 0x10>; #address-cells = <1>; #size-cells = <1>; status = "disabled"; ranges = <0 0 0x1000>; ecap2: ecap@100 { compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; interrupts = <61>; interrupt-names = "ecap2"; status = "disabled"; }; ehrpwm2: pwm@200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; }; }; }; target-module@e000 { /* 0x4830e000, ap 72 4a.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "lcdc"; reg = <0xe000 0x4>, <0xe054 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = , , ; ti,sysc-sidle = , , ; /* Domains (P, C): per_pwrdm, lcdc_clkdm */ clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe000 0x1000>; lcdc: lcdc@0 { compatible = "ti,am33xx-tilcdc"; reg = <0x0 0x1000>; interrupts = <36>; status = "disabled"; }; }; target-module@10000 { /* 0x48310000, ap 76 4e.1 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "rng"; reg = <0x11fe0 0x4>, <0x11fe4 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x10000 0x2000>; rng: rng@0 { compatible = "ti,omap4-rng"; reg = <0x0 0x2000>; interrupts = <111>; }; }; target-module@13000 { /* 0x48313000, ap 97 62.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x13000 0x1000>; }; target-module@15000 { /* 0x48315000, ap 94 56.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00015000 0x00001000>, <0x00001000 0x00016000 0x00001000>; }; target-module@18000 { /* 0x48318000, ap 74 4c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x18000 0x4000>; }; target-module@20000 { /* 0x48320000, ap 99 34.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x1000>; }; target-module@22000 { /* 0x48322000, ap 101 3e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x22000 0x1000>; }; target-module@24000 { /* 0x48324000, ap 103 68.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x24000 0x1000>; }; }; }; diff --git a/sys/gnu/dts/arm/am33xx.dtsi b/sys/gnu/dts/arm/am33xx.dtsi index 2b9ca5c609e5..b3a1fd9e39fa 100644 --- a/sys/gnu/dts/arm/am33xx.dtsi +++ b/sys/gnu/dts/arm/am33xx.dtsi @@ -1,555 +1,468 @@ /* * Device Tree Source for AM33XX SoC * * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ #include #include #include #include / { compatible = "ti,am33xx"; interrupt-parent = <&intc>; #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; d-can0 = &dcan0; d-can1 = &dcan1; usb0 = &usb0; usb1 = &usb1; phy0 = &usb0_phy; phy1 = &usb1_phy; ethernet0 = &cpsw_emac0; ethernet1 = &cpsw_emac1; spi0 = &spi0; spi1 = &spi1; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a8"; device_type = "cpu"; reg = <0>; operating-points-v2 = <&cpu0_opp_table>; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; clock-latency = <300000>; /* From omap-cpufreq driver */ }; }; cpu0_opp_table: opp-table { compatible = "operating-points-v2-ti-cpu"; syscon = <&scm_conf>; /* * The three following nodes are marked with opp-suspend * because the can not be enabled simultaneously on a * single SoC. */ opp50-300000000 { opp-hz = /bits/ 64 <300000000>; opp-microvolt = <950000 931000 969000>; opp-supported-hw = <0x06 0x0010>; opp-suspend; }; opp100-275000000 { opp-hz = /bits/ 64 <275000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0x01 0x00FF>; opp-suspend; }; opp100-300000000 { opp-hz = /bits/ 64 <300000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0x06 0x0020>; opp-suspend; }; opp100-500000000 { opp-hz = /bits/ 64 <500000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0x01 0xFFFF>; }; opp100-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0x06 0x0040>; }; opp120-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1200000 1176000 1224000>; opp-supported-hw = <0x01 0xFFFF>; }; opp120-720000000 { opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1200000 1176000 1224000>; opp-supported-hw = <0x06 0x0080>; }; oppturbo-720000000 { opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1260000 1234800 1285200>; opp-supported-hw = <0x01 0xFFFF>; }; oppturbo-800000000 { opp-hz = /bits/ 64 <800000000>; opp-microvolt = <1260000 1234800 1285200>; opp-supported-hw = <0x06 0x0100>; }; oppnitro-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <1325000 1298500 1351500>; opp-supported-hw = <0x04 0x0200>; }; }; pmu@4b000000 { compatible = "arm,cortex-a8-pmu"; interrupts = <3>; reg = <0x4b000000 0x1000000>; ti,hwmods = "debugss"; }; /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself. */ soc { compatible = "ti,omap-infra"; mpu { compatible = "ti,omap3-mpu"; ti,hwmods = "mpu"; pm-sram = <&pm_sram_code &pm_sram_data>; }; }; /* * XXX: Use a flat representation of the AM33XX interconnect. * The real AM33XX interconnect network is quite complex. Since * it will not bring real advantage to represent that in DT * for the moment, just use a fake OCP bus entry to represent * the whole bus hierarchy. */ ocp { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; ti,hwmods = "l3_main"; l4_wkup: interconnect@44c00000 { wkup_m3: wkup_m3@100000 { compatible = "ti,am3352-wkup-m3"; reg = <0x100000 0x4000>, <0x180000 0x2000>; reg-names = "umem", "dmem"; ti,hwmods = "wkup_m3"; ti,pm-firmware = "am335x-pm-firmware.elf"; }; }; l4_per: interconnect@48000000 { }; l4_fw: interconnect@47c00000 { }; l4_fast: interconnect@4a000000 { }; l4_mpuss: interconnect@4b140000 { }; intc: interrupt-controller@48200000 { compatible = "ti,am33xx-intc"; interrupt-controller; #interrupt-cells = <1>; reg = <0x48200000 0x1000>; }; edma: edma@49000000 { compatible = "ti,edma3-tpcc"; ti,hwmods = "tpcc"; reg = <0x49000000 0x10000>; reg-names = "edma3_cc"; interrupts = <12 13 14>; interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; dma-requests = <64>; #dma-cells = <2>; ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, <&edma_tptc2 0>; ti,edma-memcpy-channels = <20 21>; }; edma_tptc0: tptc@49800000 { compatible = "ti,edma3-tptc"; ti,hwmods = "tptc0"; reg = <0x49800000 0x100000>; interrupts = <112>; interrupt-names = "edma3_tcerrint"; }; edma_tptc1: tptc@49900000 { compatible = "ti,edma3-tptc"; ti,hwmods = "tptc1"; reg = <0x49900000 0x100000>; interrupts = <113>; interrupt-names = "edma3_tcerrint"; }; edma_tptc2: tptc@49a00000 { compatible = "ti,edma3-tptc"; ti,hwmods = "tptc2"; reg = <0x49a00000 0x100000>; interrupts = <114>; interrupt-names = "edma3_tcerrint"; }; target-module@47810000 { compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mmc3"; reg = <0x478102fc 0x4>, <0x47810110 0x4>, <0x47810114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x47810000 0x1000>; mmc3: mmc@0 { compatible = "ti,omap4-hsmmc"; ti,needs-special-reset; interrupts = <29>; reg = <0x0 0x1000>; status = "disabled"; }; }; - usb: target-module@47400000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x47400000 0x4>, - <0x47400010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - , - ; - clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>; - clock-names = "fck"; + usb: usb@47400000 { + compatible = "ti,am33xx-usb"; + reg = <0x47400000 0x1000>; + ranges; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x47400000 0x5000>; + ti,hwmods = "usb_otg_hs"; + status = "disabled"; + + usb_ctrl_mod: control@44e10620 { + compatible = "ti,am335x-usb-ctrl-module"; + reg = <0x44e10620 0x10 + 0x44e10648 0x4>; + reg-names = "phy_ctrl", "wakeup"; + status = "disabled"; + }; - usb0_phy: usb-phy@1300 { + usb0_phy: usb-phy@47401300 { compatible = "ti,am335x-usb-phy"; - reg = <0x1300 0x100>; + reg = <0x47401300 0x100>; reg-names = "phy"; + status = "disabled"; ti,ctrl_mod = <&usb_ctrl_mod>; #phy-cells = <0>; }; - usb0: usb@1400 { + usb0: usb@47401000 { compatible = "ti,musb-am33xx"; - reg = <0x1400 0x400>, - <0x1000 0x200>; + status = "disabled"; + reg = <0x47401400 0x400 + 0x47401000 0x200>; reg-names = "mc", "control"; interrupts = <18>; interrupt-names = "mc"; dr_mode = "otg"; mentor,multipoint = <1>; mentor,num-eps = <16>; mentor,ram-bits = <12>; mentor,power = <500>; phys = <&usb0_phy>; dmas = <&cppi41dma 0 0 &cppi41dma 1 0 &cppi41dma 2 0 &cppi41dma 3 0 &cppi41dma 4 0 &cppi41dma 5 0 &cppi41dma 6 0 &cppi41dma 7 0 &cppi41dma 8 0 &cppi41dma 9 0 &cppi41dma 10 0 &cppi41dma 11 0 &cppi41dma 12 0 &cppi41dma 13 0 &cppi41dma 14 0 &cppi41dma 0 1 &cppi41dma 1 1 &cppi41dma 2 1 &cppi41dma 3 1 &cppi41dma 4 1 &cppi41dma 5 1 &cppi41dma 6 1 &cppi41dma 7 1 &cppi41dma 8 1 &cppi41dma 9 1 &cppi41dma 10 1 &cppi41dma 11 1 &cppi41dma 12 1 &cppi41dma 13 1 &cppi41dma 14 1>; dma-names = "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", "tx14", "tx15"; }; - usb1_phy: usb-phy@1b00 { + usb1_phy: usb-phy@47401b00 { compatible = "ti,am335x-usb-phy"; - reg = <0x1b00 0x100>; + reg = <0x47401b00 0x100>; reg-names = "phy"; + status = "disabled"; ti,ctrl_mod = <&usb_ctrl_mod>; #phy-cells = <0>; }; - usb1: usb@1800 { + usb1: usb@47401800 { compatible = "ti,musb-am33xx"; - reg = <0x1c00 0x400>, - <0x1800 0x200>; + status = "disabled"; + reg = <0x47401c00 0x400 + 0x47401800 0x200>; reg-names = "mc", "control"; interrupts = <19>; interrupt-names = "mc"; dr_mode = "otg"; mentor,multipoint = <1>; mentor,num-eps = <16>; mentor,ram-bits = <12>; mentor,power = <500>; phys = <&usb1_phy>; dmas = <&cppi41dma 15 0 &cppi41dma 16 0 &cppi41dma 17 0 &cppi41dma 18 0 &cppi41dma 19 0 &cppi41dma 20 0 &cppi41dma 21 0 &cppi41dma 22 0 &cppi41dma 23 0 &cppi41dma 24 0 &cppi41dma 25 0 &cppi41dma 26 0 &cppi41dma 27 0 &cppi41dma 28 0 &cppi41dma 29 0 &cppi41dma 15 1 &cppi41dma 16 1 &cppi41dma 17 1 &cppi41dma 18 1 &cppi41dma 19 1 &cppi41dma 20 1 &cppi41dma 21 1 &cppi41dma 22 1 &cppi41dma 23 1 &cppi41dma 24 1 &cppi41dma 25 1 &cppi41dma 26 1 &cppi41dma 27 1 &cppi41dma 28 1 &cppi41dma 29 1>; dma-names = "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", "tx14", "tx15"; }; - cppi41dma: dma-controller@2000 { + cppi41dma: dma-controller@47402000 { compatible = "ti,am3359-cppi41"; - reg = <0x0000 0x1000>, - <0x2000 0x1000>, - <0x3000 0x1000>, - <0x4000 0x4000>; + reg = <0x47400000 0x1000 + 0x47402000 0x1000 + 0x47403000 0x1000 + 0x47404000 0x4000>; reg-names = "glue", "controller", "scheduler", "queuemgr"; interrupts = <17>; interrupt-names = "glue"; #dma-cells = <2>; #dma-channels = <30>; #dma-requests = <256>; + status = "disabled"; }; }; - ocmcram: sram@40300000 { + ocmcram: ocmcram@40300000 { compatible = "mmio-sram"; reg = <0x40300000 0x10000>; /* 64k */ ranges = <0x0 0x40300000 0x10000>; #address-cells = <1>; #size-cells = <1>; - pm_sram_code: pm-code-sram@0 { + pm_sram_code: pm-sram-code@0 { compatible = "ti,sram"; reg = <0x0 0x1000>; protect-exec; }; - pm_sram_data: pm-data-sram@1000 { + pm_sram_data: pm-sram-data@1000 { compatible = "ti,sram"; reg = <0x1000 0x1000>; pool; }; }; emif: emif@4c000000 { compatible = "ti,emif-am3352"; reg = <0x4c000000 0x1000000>; ti,hwmods = "emif"; interrupts = <101>; sram = <&pm_sram_code &pm_sram_data>; ti,no-idle; }; gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; ti,no-idle-on-init; reg = <0x50000000 0x2000>; interrupts = <100>; dmas = <&edma 52 0>; dma-names = "rxtx"; gpmc,num-cs = <7>; gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; interrupt-controller; #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - sham_target: target-module@53100000 { - compatible = "ti,sysc-omap3-sham", "ti,sysc"; - reg = <0x53100100 0x4>, - <0x53100110 0x4>, - <0x53100114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l3_clkdm */ - clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53100000 0x1000>; - - sham: sham@0 { - compatible = "ti,omap4-sham"; - reg = <0 0x200>; - interrupts = <109>; - dmas = <&edma 36 0>; - dma-names = "rx"; - }; - }; - - aes_target: target-module@53500000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x53500080 0x4>, - <0x53500084 0x4>, - <0x53500088 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l3_clkdm */ - clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53500000 0x1000>; - - aes: aes@0 { - compatible = "ti,omap4-aes"; - reg = <0 0xa0>; - interrupts = <103>; - dmas = <&edma 6 0>, - <&edma 5 0>; - dma-names = "tx", "rx"; - }; + sham: sham@53100000 { + compatible = "ti,omap4-sham"; + ti,hwmods = "sham"; + reg = <0x53100000 0x200>; + interrupts = <109>; + dmas = <&edma 36 0>; + dma-names = "rx"; }; - target-module@56000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5600fe00 0x4>, - <0x5600fe10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_gfx 0>; - reset-names = "rstctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x56000000 0x1000000>; - - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + aes: aes@53500000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes"; + reg = <0x53500000 0xa0>; + interrupts = <103>; + dmas = <&edma 6 0>, + <&edma 5 0>; + dma-names = "tx", "rx"; }; }; }; #include "am33xx-l4.dtsi" #include "am33xx-clocks.dtsi" - -&prcm { - prm_per: prm@c00 { - compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; - reg = <0xc00 0x100>; - #reset-cells = <1>; - }; - - prm_wkup: prm@d00 { - compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; - reg = <0xd00 0x100>; - #reset-cells = <1>; - }; - - prm_device: prm@f00 { - compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; - reg = <0xf00 0x100>; - #reset-cells = <1>; - }; - - prm_gfx: prm@1100 { - compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; - reg = <0x1100 0x100>; - #reset-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/am3517.dtsi b/sys/gnu/dts/arm/am3517.dtsi index e0b5a00e2078..bf3002009b00 100644 --- a/sys/gnu/dts/arm/am3517.dtsi +++ b/sys/gnu/dts/arm/am3517.dtsi @@ -1,173 +1,136 @@ /* * Device Tree Source for am3517 SoC * * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ #include "omap3.dtsi" / { aliases { serial3 = &uart4; can = &hecc; }; - cpus { - cpu: cpu@0 { - /* Based on OMAP3630 variants OPP50 and OPP100 */ - operating-points-v2 = <&cpu0_opp_table>; - - clock-latency = <300000>; /* From legacy driver */ - }; - }; - - cpu0_opp_table: opp-table { - compatible = "operating-points-v2-ti-cpu"; - syscon = <&scm_conf>; - /* - * AM3517 TRM only lists 600MHz @ 1.2V, but omap36xx - * appear to operate at 300MHz as well. Since AM3517 only - * lists one operating voltage, it will remain fixed at 1.2V - */ - opp50-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <1200000>; - opp-supported-hw = <0xffffffff 0xffffffff>; - opp-suspend; - }; - - opp100-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1200000>; - opp-supported-hw = <0xffffffff 0xffffffff>; - }; - }; - ocp@68000000 { am35x_otg_hs: am35x_otg_hs@5c040000 { compatible = "ti,omap3-musb"; ti,hwmods = "am35x_otg_hs"; status = "disabled"; reg = <0x5c040000 0x1000>; interrupts = <71>; interrupt-names = "mc"; }; davinci_emac: ethernet@5c000000 { compatible = "ti,am3517-emac"; ti,hwmods = "davinci_emac"; status = "disabled"; reg = <0x5c000000 0x30000>; interrupts = <67 68 69 70>; syscon = <&scm_conf>; ti,davinci-ctrl-reg-offset = <0x10000>; ti,davinci-ctrl-mod-reg-offset = <0>; ti,davinci-ctrl-ram-offset = <0x20000>; ti,davinci-ctrl-ram-size = <0x2000>; ti,davinci-rmii-en = /bits/ 8 <1>; local-mac-address = [ 00 00 00 00 00 00 ]; clocks = <&emac_ick>; clock-names = "ick"; }; - davinci_mdio: mdio@5c030000 { + davinci_mdio: ethernet@5c030000 { compatible = "ti,davinci_mdio"; ti,hwmods = "davinci_mdio"; status = "disabled"; reg = <0x5c030000 0x1000>; bus_freq = <1000000>; #address-cells = <1>; #size-cells = <0>; clocks = <&emac_fck>; clock-names = "fck"; }; uart4: serial@4809e000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart4"; status = "disabled"; reg = <0x4809e000 0x400>; interrupts = <84>; dmas = <&sdma 55 &sdma 54>; dma-names = "tx", "rx"; clock-frequency = <48000000>; }; omap3_pmx_core2: pinmux@480025d8 { compatible = "ti,omap3-padconf", "pinctrl-single"; reg = <0x480025d8 0x24>; #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xff1f>; }; hecc: can@5c050000 { compatible = "ti,am3517-hecc"; status = "disabled"; reg = <0x5c050000 0x80>, <0x5c053000 0x180>, <0x5c052000 0x200>; reg-names = "hecc", "hecc-ram", "mbx"; interrupts = <24>; clocks = <&hecc_ck>; }; /* * On am3517 the OCP registers do not seem to be accessible * similar to the omap34xx. Maybe SGX is permanently set to * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is * write-only at 0x50000e10. We detect SGX based on the SGX * revision register instead of the unreadable OCP revision * register. */ sgx_module: target-module@50000000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x50000014 0x4>; reg-names = "rev"; clocks = <&sgx_fck>, <&sgx_ick>; clock-names = "fck", "ick"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x50000000 0x4000>; /* * Closed source PowerVR driver, no child device * binding or driver in mainline */ }; }; }; -/* Not currently working, probably needs at least different clocks */ -&rng_target { - status = "disabled"; - /delete-property/ clocks; -}; - /* Table Table 5-79 of the TRM shows 480ab000 is reserved */ &usb_otg_hs { status = "disabled"; }; &iva { status = "disabled"; }; &mailbox { status = "disabled"; }; &mmu_isp { status = "disabled"; }; /include/ "am35xx-clocks.dtsi" /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/sys/gnu/dts/arm/am3517_mt_ventoux.dts b/sys/gnu/dts/arm/am3517_mt_ventoux.dts index e7d7124a34ba..e507e4ae0d88 100644 --- a/sys/gnu/dts/arm/am3517_mt_ventoux.dts +++ b/sys/gnu/dts/arm/am3517_mt_ventoux.dts @@ -1,24 +1,24 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2011 Ilya Yanok, EmCraft Systems */ /dts-v1/; #include "omap34xx.dtsi" / { model = "TeeJet Mt.Ventoux"; - compatible = "teejet,mt_ventoux", "ti,am3517", "ti,omap3"; + compatible = "teejet,mt_ventoux", "ti,omap3"; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; /* AM35xx doesn't have IVA */ soc { iva { status = "disabled"; }; }; }; diff --git a/sys/gnu/dts/arm/am3703.dtsi b/sys/gnu/dts/arm/am3703.dtsi index 2b994ae790c9..e69de29bb2d1 100644 --- a/sys/gnu/dts/arm/am3703.dtsi +++ b/sys/gnu/dts/arm/am3703.dtsi @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2020 André Hentschel - */ - -#include "omap36xx.dtsi" - -&iva { - status = "disabled"; -}; - -&sgx_module { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/am3715.dtsi b/sys/gnu/dts/arm/am3715.dtsi index ab328e8c0bd8..e69de29bb2d1 100644 --- a/sys/gnu/dts/arm/am3715.dtsi +++ b/sys/gnu/dts/arm/am3715.dtsi @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2020 André Hentschel - */ - -#include "omap36xx.dtsi" - -&iva { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/am4372.dtsi b/sys/gnu/dts/arm/am4372.dtsi index faa14dc0faff..14bbc438055f 100644 --- a/sys/gnu/dts/arm/am4372.dtsi +++ b/sys/gnu/dts/arm/am4372.dtsi @@ -1,498 +1,377 @@ /* * Device Tree Source for AM4372 SoC * * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ #include #include #include #include / { compatible = "ti,am4372", "ti,am43"; interrupt-parent = <&wakeupgen>; #address-cells = <1>; #size-cells = <1>; chosen { }; memory@0 { device_type = "memory"; reg = <0 0>; }; aliases { i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; ethernet0 = &cpsw_emac0; ethernet1 = &cpsw_emac1; spi0 = &qspi; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; clock-latency = <300000>; /* From omap-cpufreq driver */ }; }; cpu0_opp_table: opp-table { compatible = "operating-points-v2-ti-cpu"; syscon = <&scm_conf>; opp50-300000000 { opp-hz = /bits/ 64 <300000000>; opp-microvolt = <950000 931000 969000>; opp-supported-hw = <0xFF 0x01>; opp-suspend; }; opp100-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0xFF 0x04>; }; opp120-720000000 { opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1200000 1176000 1224000>; opp-supported-hw = <0xFF 0x08>; }; oppturbo-800000000 { opp-hz = /bits/ 64 <800000000>; opp-microvolt = <1260000 1234800 1285200>; opp-supported-hw = <0xFF 0x10>; }; oppnitro-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <1325000 1298500 1351500>; opp-supported-hw = <0xFF 0x20>; }; }; soc { compatible = "ti,omap-infra"; mpu { compatible = "ti,omap4-mpu"; ti,hwmods = "mpu"; pm-sram = <&pm_sram_code &pm_sram_data>; }; }; gic: interrupt-controller@48241000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; #interrupt-cells = <3>; reg = <0x48241000 0x1000>, <0x48240100 0x0100>; interrupt-parent = <&gic>; }; wakeupgen: interrupt-controller@48281000 { compatible = "ti,omap4-wugen-mpu"; interrupt-controller; #interrupt-cells = <3>; reg = <0x48281000 0x1000>; interrupt-parent = <&gic>; }; scu: scu@48240000 { compatible = "arm,cortex-a9-scu"; reg = <0x48240000 0x100>; }; global_timer: timer@48240200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x48240200 0x100>; interrupts = ; interrupt-parent = <&gic>; clocks = <&mpu_periphclk>; }; local_timer: timer@48240600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x48240600 0x100>; interrupts = ; interrupt-parent = <&gic>; clocks = <&mpu_periphclk>; }; l2-cache-controller@48242000 { compatible = "arm,pl310-cache"; reg = <0x48242000 0x1000>; cache-unified; cache-level = <2>; }; ocp@44000000 { compatible = "ti,am4372-l3-noc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; ti,hwmods = "l3_main"; ti,no-idle; reg = <0x44000000 0x400000 0x44800000 0x400000>; interrupts = , ; l4_wkup: interconnect@44c00000 { wkup_m3: wkup_m3@100000 { compatible = "ti,am4372-wkup-m3"; reg = <0x100000 0x4000>, <0x180000 0x2000>; reg-names = "umem", "dmem"; ti,hwmods = "wkup_m3"; ti,pm-firmware = "am335x-pm-firmware.elf"; }; }; l4_per: interconnect@48000000 { }; l4_fast: interconnect@4a000000 { }; emif: emif@4c000000 { compatible = "ti,emif-am4372"; reg = <0x4c000000 0x1000000>; ti,hwmods = "emif"; interrupts = ; ti,no-idle; sram = <&pm_sram_code &pm_sram_data>; }; edma: edma@49000000 { compatible = "ti,edma3-tpcc"; ti,hwmods = "tpcc"; reg = <0x49000000 0x10000>; reg-names = "edma3_cc"; interrupts = , , ; interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; dma-requests = <64>; #dma-cells = <2>; ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, <&edma_tptc2 0>; ti,edma-memcpy-channels = <58 59>; }; edma_tptc0: tptc@49800000 { compatible = "ti,edma3-tptc"; ti,hwmods = "tptc0"; reg = <0x49800000 0x100000>; interrupts = ; interrupt-names = "edma3_tcerrint"; }; edma_tptc1: tptc@49900000 { compatible = "ti,edma3-tptc"; ti,hwmods = "tptc1"; reg = <0x49900000 0x100000>; interrupts = ; interrupt-names = "edma3_tcerrint"; }; edma_tptc2: tptc@49a00000 { compatible = "ti,edma3-tptc"; ti,hwmods = "tptc2"; reg = <0x49a00000 0x100000>; interrupts = ; interrupt-names = "edma3_tcerrint"; }; target-module@47810000 { compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mmc3"; reg = <0x478102fc 0x4>, <0x47810110 0x4>, <0x47810114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x47810000 0x1000>; mmc3: mmc@0 { compatible = "ti,omap4-hsmmc"; ti,needs-special-reset; interrupts = ; reg = <0x0 0x1000>; }; }; - sham_target: target-module@53100000 { - compatible = "ti,sysc-omap3-sham", "ti,sysc"; - reg = <0x53100100 0x4>, - <0x53100110 0x4>, - <0x53100114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l3_clkdm */ - clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53100000 0x1000>; - - sham: sham@0 { - compatible = "ti,omap5-sham"; - reg = <0 0x300>; - dmas = <&edma 36 0>; - dma-names = "rx"; - interrupts = ; - }; + sham: sham@53100000 { + compatible = "ti,omap5-sham"; + ti,hwmods = "sham"; + reg = <0x53100000 0x300>; + dmas = <&edma 36 0>; + dma-names = "rx"; + interrupts = ; }; - aes_target: target-module@53501000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x53501080 0x4>, - <0x53501084 0x4>, - <0x53501088 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l3_clkdm */ - clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53501000 0x1000>; - - aes: aes@0 { - compatible = "ti,omap4-aes"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&edma 6 0>, - <&edma 5 0>; - dma-names = "tx", "rx"; - }; + aes: aes@53501000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes"; + reg = <0x53501000 0xa0>; + interrupts = ; + dmas = <&edma 6 0>, + <&edma 5 0>; + dma-names = "tx", "rx"; }; - des_target: target-module@53701000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x53701030 0x4>, - <0x53701034 0x4>, - <0x53701038 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l3_clkdm */ - clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x53701000 0x1000>; - - des: des@0 { - compatible = "ti,omap4-des"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&edma 34 0>, - <&edma 33 0>; - dma-names = "tx", "rx"; - }; + des: des@53701000 { + compatible = "ti,omap4-des"; + ti,hwmods = "des"; + reg = <0x53701000 0xa0>; + interrupts = ; + dmas = <&edma 34 0>, + <&edma 33 0>; + dma-names = "tx", "rx"; }; gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; dmas = <&edma 52 0>; dma-names = "rxtx"; clocks = <&l3s_gclk>; clock-names = "fck"; reg = <0x50000000 0x2000>; interrupts = ; gpmc,num-cs = <7>; gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; interrupt-controller; #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - target-module@47900000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x47900000 0x4>, - <0x47900010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>; - clock-names = "fck"; + qspi: spi@47900000 { + compatible = "ti,am4372-qspi"; + reg = <0x47900000 0x100>, + <0x30000000 0x4000000>; + reg-names = "qspi_base", "qspi_mmap"; #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x47900000 0x1000>, - <0x30000000 0x30000000 0x4000000>; - - qspi: spi@0 { - compatible = "ti,am4372-qspi"; - reg = <0 0x100>, - <0x30000000 0x4000000>; - reg-names = "qspi_base", "qspi_mmap"; - clocks = <&dpll_per_m2_div4_ck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 138 0x4>; - num-cs = <4>; - }; + #size-cells = <0>; + ti,hwmods = "qspi"; + interrupts = <0 138 0x4>; + num-cs = <4>; + status = "disabled"; }; dss: dss@4832a000 { compatible = "ti,omap3-dss"; reg = <0x4832a000 0x200>; status = "disabled"; ti,hwmods = "dss_core"; clocks = <&disp_clk>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges; dispc: dispc@4832a400 { compatible = "ti,omap3-dispc"; reg = <0x4832a400 0x400>; interrupts = ; ti,hwmods = "dss_dispc"; clocks = <&disp_clk>; clock-names = "fck"; max-memory-bandwidth = <230000000>; }; rfbi: rfbi@4832a800 { compatible = "ti,omap3-rfbi"; reg = <0x4832a800 0x100>; ti,hwmods = "dss_rfbi"; clocks = <&disp_clk>; clock-names = "fck"; status = "disabled"; }; }; - ocmcram: sram@40300000 { + ocmcram: ocmcram@40300000 { compatible = "mmio-sram"; reg = <0x40300000 0x40000>; /* 256k */ ranges = <0x0 0x40300000 0x40000>; #address-cells = <1>; #size-cells = <1>; - pm_sram_code: pm-code-sram@0 { + pm_sram_code: pm-sram-code@0 { compatible = "ti,sram"; reg = <0x0 0x1000>; protect-exec; }; - pm_sram_data: pm-data-sram@1000 { + pm_sram_data: pm-sram-data@1000 { compatible = "ti,sram"; reg = <0x1000 0x1000>; pool; }; }; - - target-module@56000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5600fe00 0x4>, - <0x5600fe10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_gfx 0>; - reset-names = "rstctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x56000000 0x1000000>; - }; }; }; #include "am437x-l4.dtsi" #include "am43xx-clocks.dtsi" - -&prcm { - prm_gfx: prm@400 { - compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; - reg = <0x400 0x100>; - #reset-cells = <1>; - }; - - prm_per: prm@800 { - compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; - reg = <0x800 0x100>; - #reset-cells = <1>; - }; - - prm_wkup: prm@2000 { - compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; - reg = <0x2000 0x100>; - #reset-cells = <1>; - }; - - prm_device: prm@4000 { - compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; - reg = <0x4000 0x100>; - #reset-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/am437x-gp-evm.dts b/sys/gnu/dts/arm/am437x-gp-evm.dts index 811c8cae315b..cae4500194fe 100644 --- a/sys/gnu/dts/arm/am437x-gp-evm.dts +++ b/sys/gnu/dts/arm/am437x-gp-evm.dts @@ -1,1130 +1,1130 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ */ /* AM437x GP EVM */ /dts-v1/; #include "am4372.dtsi" #include #include #include / { model = "TI AM437x GP EVM"; compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43"; aliases { display0 = &lcd0; }; chosen { stdout-path = &uart0; }; evm_v3_3d: fixedregulator-v3_3d { compatible = "regulator-fixed"; regulator-name = "evm_v3_3d"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; }; vtt_fixed: fixedregulator-vtt { compatible = "regulator-fixed"; regulator-name = "vtt_fixed"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; regulator-always-on; regulator-boot-on; enable-active-high; gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; }; vmmcwl_fixed: fixedregulator-mmcwl { compatible = "regulator-fixed"; regulator-name = "vmmcwl_fixed"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; enable-active-high; }; lcd_bl: backlight { compatible = "pwm-backlight"; pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 51 53 56 62 75 101 152 255>; default-brightness-level = <8>; }; matrix_keypad: matrix_keypad0 { compatible = "gpio-matrix-keypad"; debounce-delay-ms = <5>; col-scan-delay-us = <2>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&matrix_keypad_default>; pinctrl-1 = <&matrix_keypad_sleep>; wakeup-source; row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */ &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */ &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */ col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */ &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */ linux,keymap = <0x00000201 /* P1 */ 0x00010202 /* P2 */ 0x01000067 /* UP */ 0x0101006a /* RIGHT */ 0x02000069 /* LEFT */ 0x0201006c>; /* DOWN */ }; lcd0: display { - compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; + compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; label = "lcd"; backlight = <&lcd_bl>; panel-timing { clock-frequency = <33000000>; hactive = <800>; vactive = <480>; hfront-porch = <210>; hback-porch = <16>; hsync-len = <30>; vback-porch = <10>; vfront-porch = <22>; vsync-len = <13>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <1>; }; port { lcd_in: endpoint { remote-endpoint = <&dpi_out>; }; }; }; /* fixed 12MHz oscillator */ refclk: oscillator { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <12000000>; }; /* fixed 32k external oscillator clock */ clk_32k_rtc: clk_32k_rtc { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; sound0: sound0 { compatible = "simple-audio-card"; simple-audio-card,name = "AM437x-GP-EVM"; simple-audio-card,widgets = "Headphone", "Headphone Jack", "Line", "Line In"; simple-audio-card,routing = "Headphone Jack", "HPLOUT", "Headphone Jack", "HPROUT", "LINE1L", "Line In", "LINE1R", "Line In"; simple-audio-card,format = "dsp_b"; simple-audio-card,bitclock-master = <&sound0_master>; simple-audio-card,frame-master = <&sound0_master>; simple-audio-card,bitclock-inversion; simple-audio-card,cpu { sound-dai = <&mcasp1>; system-clock-frequency = <12000000>; }; sound0_master: simple-audio-card,codec { sound-dai = <&tlv320aic3106>; system-clock-frequency = <12000000>; }; }; beeper: beeper { compatible = "gpio-beeper"; pinctrl-names = "default"; pinctrl-0 = <&beeper_pins_default>; pinctrl-1 = <&beeper_pins_sleep>; gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; }; }; &am43xx_pinmux { pinctrl-names = "default", "sleep"; pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins &debugss_pins>; pinctrl-1 = <&wlan_pins_sleep>; ddr3_vtt_toggle_default: ddr_vtt_toggle_default { pinctrl-single,pins = < 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */ >; }; i2c0_pins: i2c0_pins { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; i2c1_pins: i2c1_pins { pinctrl-single,pins = < AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; ecap0_pins: backlight_pins { pinctrl-single,pins = < AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ >; }; pixcir_ts_pins: pixcir_ts_pins { pinctrl-single,pins = < AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; nand_flash_x8: nand_flash_x8 { pinctrl-single,pins = < AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ >; }; dss_pins: dss_pins { pinctrl-single,pins = < AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ >; }; display_mux_pins: display_mux_pins { pinctrl-single,pins = < /* GPIO 5_8 to select LCD / HDMI */ AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; dcan0_default: dcan0_default_pins { pinctrl-single,pins = < AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ >; }; dcan0_sleep: dcan0_sleep_pins { pinctrl-single,pins = < AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ >; }; dcan1_default: dcan1_default_pins { pinctrl-single,pins = < AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */ AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ >; }; dcan1_sleep: dcan1_sleep_pins { pinctrl-single,pins = < AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */ AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */ >; }; vpfe0_pins_default: vpfe0_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ >; }; vpfe0_pins_sleep: vpfe0_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/ AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/ AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/ AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/ AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/ AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/ AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/ AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/ AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/ AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/ AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/ AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/ AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/ >; }; vpfe1_pins_default: vpfe1_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/ AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/ AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/ AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/ AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/ AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/ AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/ AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/ AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/ AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/ AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/ AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/ AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/ >; }; vpfe1_pins_sleep: vpfe1_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/ AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/ AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/ AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/ AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/ AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/ AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/ AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/ AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/ AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/ AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/ AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/ AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/ >; }; mmc3_pins_default: pinmux_mmc3_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */ >; }; mmc3_pins_sleep: pinmux_mmc3_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */ AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */ AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */ AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */ AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */ AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */ >; }; wlan_pins_default: pinmux_wlan_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ >; }; wlan_pins_sleep: pinmux_wlan_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ >; }; uart3_pins: uart3_pins { pinctrl-single,pins = < AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */ AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */ AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */ AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */ >; }; mcasp1_pins: mcasp1_pins { pinctrl-single,pins = < AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ >; }; mcasp1_sleep_pins: mcasp1_sleep_pins { pinctrl-single,pins = < AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; gpio0_pins: gpio0_pins { pinctrl-single,pins = < AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */ >; }; emmc_pins_default: emmc_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ >; }; emmc_pins_sleep: emmc_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */ AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */ AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */ AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */ AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */ AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */ >; }; beeper_pins_default: beeper_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */ >; }; beeper_pins_sleep: beeper_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x9e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam1_field.gpio4_12 */ >; }; unused_pins: unused_pins { pinctrl-single,pins = < AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xa3c, PIN_INPUT | PULL_DISABLE | MUX_MODE7) AM4372_IOPAD(0xa40, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xa44, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xa48, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xa4c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xa50, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xa54, PIN_INPUT | PULL_DISABLE | MUX_MODE7) AM4372_IOPAD(0xa58, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xa60, PIN_INPUT | PULL_DISABLE | MUX_MODE7) AM4372_IOPAD(0xa68, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xa70, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xa78, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xa7c, PIN_INPUT | PULL_DISABLE) AM4372_IOPAD(0xac8, PIN_INPUT_PULLDOWN) AM4372_IOPAD(0xad4, PIN_INPUT_PULLDOWN) AM4372_IOPAD(0xad8, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xadc, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xae0, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xae4, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xae8, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xaec, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xaf0, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xaf4, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xaf8, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xafc, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xb00, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xb04, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xb08, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xb0c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xb10, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xb14, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xb18, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; debugss_pins: pinmux_debugss_pins { pinctrl-single,pins = < AM4372_IOPAD(0xa90, PIN_INPUT_PULLDOWN) AM4372_IOPAD(0xa94, PIN_INPUT_PULLDOWN) AM4372_IOPAD(0xa98, PIN_INPUT_PULLDOWN) AM4372_IOPAD(0xa9c, PIN_INPUT_PULLDOWN) AM4372_IOPAD(0xaa0, PIN_INPUT_PULLDOWN) AM4372_IOPAD(0xaa4, PIN_INPUT_PULLDOWN) AM4372_IOPAD(0xaa8, PIN_INPUT_PULLDOWN) >; }; uart0_pins_default: uart0_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ >; }; uart0_pins_sleep: uart0_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_ctsn.uart0_ctsn */ AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_rtsn.uart0_rtsn */ AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ AM4372_IOPAD(0x974, PIN_INPUT_PULLDOWN | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ >; }; matrix_keypad_default: matrix_keypad_default { pinctrl-single,pins = < AM4372_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) AM4372_IOPAD(0x9a8, PIN_OUTPUT | MUX_MODE7) AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9) AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) >; }; matrix_keypad_sleep: matrix_keypad_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x9a4, PULL_UP | MUX_MODE7) AM4372_IOPAD(0x9a8, PULL_UP | MUX_MODE7) AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9) AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) >; }; }; &uart0 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart0_pins_default>; pinctrl-1 = <&uart0_pins_sleep>; }; &i2c0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; clock-frequency = <100000>; tps65218: tps65218@24 { reg = <0x24>; compatible = "ti,tps65218"; interrupts = ; /* NMIn */ interrupt-controller; #interrupt-cells = <2>; dcdc1: regulator-dcdc1 { regulator-name = "vdd_core"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1144000>; regulator-boot-on; regulator-always-on; }; dcdc2: regulator-dcdc2 { regulator-name = "vdd_mpu"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1378000>; regulator-boot-on; regulator-always-on; }; dcdc3: regulator-dcdc3 { regulator-name = "vdcdc3"; regulator-boot-on; regulator-always-on; regulator-state-mem { regulator-on-in-suspend; }; regulator-state-disk { regulator-off-in-suspend; }; }; dcdc5: regulator-dcdc5 { regulator-name = "v1_0bat"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; regulator-state-mem { regulator-on-in-suspend; }; }; dcdc6: regulator-dcdc6 { regulator-name = "v1_8bat"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; regulator-state-mem { regulator-on-in-suspend; }; }; ldo1: regulator-ldo1 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; }; ov2659@30 { compatible = "ovti,ov2659"; reg = <0x30>; clocks = <&refclk 0>; clock-names = "xvclk"; port { ov2659_0: endpoint { remote-endpoint = <&vpfe1_ep>; link-frequencies = /bits/ 64 <70000000>; }; }; }; }; &i2c1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; pixcir_ts@5c { compatible = "pixcir,pixcir_tangoc"; pinctrl-names = "default"; pinctrl-0 = <&pixcir_ts_pins>; reg = <0x5c>; attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* * 0x264 represents the offset of padconf register of * gpio3_22 from am43xx_pinmux base. */ interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>, <&am43xx_pinmux 0x264>; interrupt-names = "tsc", "wakeup"; touchscreen-size-x = <1024>; touchscreen-size-y = <600>; wakeup-source; }; ov2659@30 { compatible = "ovti,ov2659"; reg = <0x30>; clocks = <&refclk 0>; clock-names = "xvclk"; port { ov2659_1: endpoint { remote-endpoint = <&vpfe0_ep>; link-frequencies = /bits/ 64 <70000000>; }; }; }; tlv320aic3106: tlv320aic3106@1b { #sound-dai-cells = <0>; compatible = "ti,tlv320aic3106"; reg = <0x1b>; status = "okay"; /* Regulators */ IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> EN: V1_8D -> VBAT */ AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */ }; }; &epwmss0 { status = "okay"; }; &tscadc { status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; &ecap0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins>; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&gpio0_pins>; status = "okay"; p23 { gpio-hog; gpios = <23 GPIO_ACTIVE_HIGH>; /* SelEMMCorNAND selects between eMMC and NAND: * Low: NAND * High: eMMC * When changing this line make sure the newly * selected device node is enabled and the previously * selected device node is disabled. */ output-low; line-name = "SelEMMCorNAND"; }; }; &gpio1 { status = "okay"; }; &gpio3 { status = "okay"; }; &gpio4 { status = "okay"; }; &gpio5 { pinctrl-names = "default"; pinctrl-0 = <&display_mux_pins>; status = "okay"; ti,no-reset-on-init; p8 { /* * SelLCDorHDMI selects between display and audio paths: * Low: HDMI display with audio via HDMI * High: LCD display with analog audio via aic3111 codec */ gpio-hog; gpios = <8 GPIO_ACTIVE_HIGH>; output-high; line-name = "SelLCDorHDMI"; }; }; &mmc1 { status = "okay"; vmmc-supply = <&evm_v3_3d>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; /* eMMC sits on mmc2 */ &mmc2 { /* * When enabling eMMC, disable GPMC/NAND and set * SelEMMCorNAND to output-high */ status = "disabled"; vmmc-supply = <&evm_v3_3d>; bus-width = <8>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&emmc_pins_default>; pinctrl-1 = <&emmc_pins_sleep>; ti,non-removable; }; &mmc3 { status = "okay"; /* these are on the crossbar and are outlined in the xbar-event-map element */ dmas = <&edma_xbar 30 0 1>, <&edma_xbar 31 0 2>; dma-names = "tx", "rx"; vmmc-supply = <&vmmcwl_fixed>; bus-width = <4>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&mmc3_pins_default>; pinctrl-1 = <&mmc3_pins_sleep>; cap-power-off-card; keep-power-in-suspend; ti,non-removable; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@0 { compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio1>; interrupts = <23 IRQ_TYPE_EDGE_RISING>; }; }; &uart3 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; &usb2_phy1 { status = "okay"; }; &usb1 { dr_mode = "otg"; status = "okay"; }; &usb2_phy2 { status = "okay"; }; &usb2 { dr_mode = "host"; status = "okay"; }; &mac { slaves = <1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; status = "okay"; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; status = "okay"; ethphy0: ethernet-phy@0 { reg = <0>; }; }; &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "rgmii"; }; &elm { status = "okay"; }; &gpmc { /* * When enabling GPMC, disable eMMC and set * SelEMMCorNAND to output-low */ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&nand_flash_x8>; ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* device IO registers */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-xfer-type = "prefetch-dma"; ti,nand-ecc-opt = "bch16"; ti,elm-id = <&elm>; nand-bus-width = <8>; gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <40>; gpmc,cs-wr-off-ns = <40>; gpmc,adv-on-ns = <0>; gpmc,adv-rd-off-ns = <25>; gpmc,adv-wr-off-ns = <25>; gpmc,we-on-ns = <0>; gpmc,we-off-ns = <20>; gpmc,oe-on-ns = <3>; gpmc,oe-off-ns = <30>; gpmc,access-ns = <30>; gpmc,rd-cycle-ns = <40>; gpmc,wr-cycle-ns = <40>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ /* All SPL-* partitions are sized to minimal length * which can be independently programmable. For * NAND flash this is equal to size of erase-block */ #address-cells = <1>; #size-cells = <1>; partition@0 { label = "NAND.SPL"; reg = <0x00000000 0x00040000>; }; partition@1 { label = "NAND.SPL.backup1"; reg = <0x00040000 0x00040000>; }; partition@2 { label = "NAND.SPL.backup2"; reg = <0x00080000 0x00040000>; }; partition@3 { label = "NAND.SPL.backup3"; reg = <0x000c0000 0x00040000>; }; partition@4 { label = "NAND.u-boot-spl-os"; reg = <0x00100000 0x00080000>; }; partition@5 { label = "NAND.u-boot"; reg = <0x00180000 0x00100000>; }; partition@6 { label = "NAND.u-boot-env"; reg = <0x00280000 0x00040000>; }; partition@7 { label = "NAND.u-boot-env.backup1"; reg = <0x002c0000 0x00040000>; }; partition@8 { label = "NAND.kernel"; reg = <0x00300000 0x00700000>; }; partition@9 { label = "NAND.file-system"; reg = <0x00a00000 0x1f600000>; }; }; }; &dss { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&dss_pins>; port { dpi_out: endpoint { remote-endpoint = <&lcd_in>; data-lines = <24>; }; }; }; &dcan0 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&dcan0_default>; pinctrl-1 = <&dcan0_sleep>; status = "okay"; }; &dcan1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&dcan1_default>; pinctrl-1 = <&dcan1_sleep>; status = "okay"; }; &vpfe0 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&vpfe0_pins_default>; pinctrl-1 = <&vpfe0_pins_sleep>; port { vpfe0_ep: endpoint { remote-endpoint = <&ov2659_1>; ti,am437x-vpfe-interface = <0>; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; }; }; }; &vpfe1 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&vpfe1_pins_default>; pinctrl-1 = <&vpfe1_pins_sleep>; port { vpfe1_ep: endpoint { remote-endpoint = <&ov2659_0>; ti,am437x-vpfe-interface = <0>; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; }; }; }; &mcasp1 { #sound-dai-cells = <0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&mcasp1_pins>; pinctrl-1 = <&mcasp1_sleep_pins>; status = "okay"; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; /* 4 serializers */ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 0 0 1 2 >; tx-num-evt = <32>; rx-num-evt = <32>; }; &rtc { clocks = <&clk_32k_rtc>, <&clk_32768_ck>; clock-names = "ext-clk", "int-clk"; status = "okay"; }; &cpu { cpu0-supply = <&dcdc2>; }; diff --git a/sys/gnu/dts/arm/am437x-idk-evm.dts b/sys/gnu/dts/arm/am437x-idk-evm.dts index 9f66f96d09c9..f3ced6df0c9b 100644 --- a/sys/gnu/dts/arm/am437x-idk-evm.dts +++ b/sys/gnu/dts/arm/am437x-idk-evm.dts @@ -1,536 +1,536 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; #include "am4372.dtsi" #include #include #include #include / { model = "TI AM437x Industrial Development Kit"; compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43"; chosen { stdout-path = &uart0; }; v24_0d: fixed-regulator-v24_0d { compatible = "regulator-fixed"; regulator-name = "V24_0D"; regulator-min-microvolt = <24000000>; regulator-max-microvolt = <24000000>; regulator-always-on; regulator-boot-on; }; v3_3d: fixed-regulator-v3_3d { compatible = "regulator-fixed"; regulator-name = "V3_3D"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; vin-supply = <&v24_0d>; }; vdd_corereg: fixed-regulator-vdd_corereg { compatible = "regulator-fixed"; regulator-name = "VDD_COREREG"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; regulator-boot-on; vin-supply = <&v24_0d>; }; vdd_core: fixed-regulator-vdd_core { compatible = "regulator-fixed"; regulator-name = "VDD_CORE"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; regulator-boot-on; vin-supply = <&vdd_corereg>; }; v1_8dreg: fixed-regulator-v1_8dreg{ compatible = "regulator-fixed"; regulator-name = "V1_8DREG"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; vin-supply = <&v24_0d>; }; v1_8d: fixed-regulator-v1_8d{ compatible = "regulator-fixed"; regulator-name = "V1_8D"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; vin-supply = <&v1_8dreg>; }; v1_5dreg: fixed-regulator-v1_5dreg{ compatible = "regulator-fixed"; regulator-name = "V1_5DREG"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; regulator-always-on; regulator-boot-on; vin-supply = <&v24_0d>; }; v1_5d: fixed-regulator-v1_5d{ compatible = "regulator-fixed"; regulator-name = "V1_5D"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; regulator-always-on; regulator-boot-on; vin-supply = <&v1_5dreg>; }; gpio_keys: gpio_keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pins_default>; #address-cells = <1>; #size-cells = <0>; switch0 { label = "power-button"; linux,code = ; gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; }; }; /* fixed 32k external oscillator clock */ clk_32k_rtc: clk_32k_rtc { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; leds-iio { status = "disabled"; compatible = "gpio-leds"; led-out0 { label = "out0"; gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out1 { label = "out1"; gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out2 { label = "out2"; gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out3 { label = "out3"; gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out4 { label = "out4"; gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out5 { label = "out5"; gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out6 { label = "out6"; gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out7 { label = "out7"; gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; }; &am43xx_pinmux { gpio_keys_pins_default: gpio_keys_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */ >; }; i2c0_pins_default: i2c0_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; i2c0_pins_sleep: i2c0_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; i2c2_pins_default: i2c2_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x9e8, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */ AM4372_IOPAD(0x9ec, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */ >; }; i2c2_pins_sleep: i2c2_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x9e8, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x9ec, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; mmc1_pins_default: pinmux_mmc1_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ AM4372_IOPAD(0x9f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ AM4372_IOPAD(0x9f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ AM4372_IOPAD(0x9f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ AM4372_IOPAD(0x9fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; mmc1_pins_sleep: pinmux_mmc1_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x900, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x904, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x960, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; spi1_pins_default: spi1_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x908, PIN_INPUT | MUX_MODE2) /* mii1_col.spi1_sclk */ AM4372_IOPAD(0x910, PIN_INPUT | MUX_MODE2) /* mii1_rx_er.spi1_d1 */ AM4372_IOPAD(0x944, PIN_OUTPUT | MUX_MODE2) /* rmii1_ref_clk.spi1_cs0 */ AM4372_IOPAD(0x90c, PIN_OUTPUT | MUX_MODE7) /* mii1_crs.gpio3_1 */ >; }; spi1_pins_sleep: spi1_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; ecap0_pins_default: backlight_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; qspi_pins_default: qspi_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */ AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */ AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ >; }; qspi_pins_sleep: qspi_pins_sleep{ pinctrl-single,pins = < AM4372_IOPAD(0x87c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x898, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; }; &i2c0 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c0_pins_default>; pinctrl-1 = <&i2c0_pins_sleep>; clock-frequency = <400000>; at24@50 { compatible = "atmel,24c256"; pagesize = <64>; reg = <0x50>; }; tps: tps62362@60 { compatible = "ti,tps62362"; reg = <0x60>; regulator-name = "VDD_MPU"; regulator-min-microvolt = <950000>; regulator-max-microvolt = <1330000>; regulator-boot-on; regulator-always-on; ti,vsel0-state-high; ti,vsel1-state-high; vin-supply = <&v3_3d>; }; }; &i2c2 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c2_pins_default>; pinctrl-1 = <&i2c2_pins_sleep>; clock-frequency = <100000>; tpic2810: tpic2810@60 { compatible = "ti,tpic2810"; reg = <0x60>; gpio-controller; #gpio-cells = <2>; }; }; &spi1 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi1_pins_default>; pinctrl-1 = <&spi1_pins_sleep>; ti,pindir-d0-out-d1-in; sn65hvs882: sn65hvs882@0 { compatible = "pisosr-gpio"; gpio-controller; #gpio-cells = <2>; load-gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; reg = <0>; spi-max-frequency = <1000000>; spi-cpol; }; }; &epwmss0 { status = "okay"; }; &ecap0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins_default>; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &gpio3 { status = "okay"; }; &gpio4 { status = "okay"; }; &gpio5 { status = "okay"; }; &mmc1 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&mmc1_pins_default>; pinctrl-1 = <&mmc1_pins_sleep>; vmmc-supply = <&v3_3d>; bus-width = <4>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; &qspi { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qspi_pins_default>; pinctrl-1 = <&qspi_pins_sleep>; spi-max-frequency = <48000000>; m25p80@0 { compatible = "mx66l51235l"; spi-max-frequency = <48000000>; reg = <0>; spi-cpol; spi-cpha; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <1>; /* * MTD partition table. The ROM checks the first 512KiB for a * valid file to boot(XIP). */ partition@0 { label = "QSPI.U_BOOT"; reg = <0x00000000 0x000080000>; }; partition@1 { label = "QSPI.U_BOOT.backup"; reg = <0x00080000 0x00080000>; }; partition@2 { label = "QSPI.U-BOOT-SPL_OS"; reg = <0x00100000 0x00010000>; }; partition@3 { label = "QSPI.U_BOOT_ENV"; reg = <0x00110000 0x00010000>; }; partition@4 { label = "QSPI.U-BOOT-ENV.backup"; reg = <0x00120000 0x00010000>; }; partition@5 { label = "QSPI.KERNEL"; reg = <0x00130000 0x0800000>; }; partition@6 { label = "QSPI.FILESYSTEM"; reg = <0x00930000 0x36D0000>; }; }; }; &mac { slaves = <1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; status = "okay"; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; status = "okay"; ethphy0: ethernet-phy@0 { reg = <0>; }; }; &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "rgmii"; }; &rtc { clocks = <&clk_32k_rtc>, <&clk_32768_ck>; clock-names = "ext-clk", "int-clk"; status = "okay"; }; &wdt { status = "okay"; }; &cpu { cpu0-supply = <&tps>; }; &cpu0_opp_table { /* * Supply voltage supervisor on board will not allow opp50 so * disable it and set opp100 as suspend OPP. */ - opp50-300000000 { + opp50@300000000 { status = "disabled"; }; - opp100-600000000 { + opp100@600000000 { opp-suspend; }; }; diff --git a/sys/gnu/dts/arm/am437x-l4.dtsi b/sys/gnu/dts/arm/am437x-l4.dtsi index e18e17d31272..59770dd3785e 100644 --- a/sys/gnu/dts/arm/am437x-l4.dtsi +++ b/sys/gnu/dts/arm/am437x-l4.dtsi @@ -1,2452 +1,2504 @@ &l4_wkup { /* 0x44c00000 */ compatible = "ti,am4-l4-wkup", "simple-bus"; reg = <0x44c00000 0x800>, <0x44c00800 0x800>, <0x44c01000 0x400>, <0x44c01400 0x400>; reg-names = "ap", "la", "ia0", "ia1"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ <0x00100000 0x44d00000 0x100000>, /* segment 1 */ <0x00200000 0x44e00000 0x100000>; /* segment 2 */ segment@0 { /* 0x44c00000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00000800 0x00000800 0x000800>, /* ap 1 */ <0x00001000 0x00001000 0x000400>, /* ap 2 */ <0x00001400 0x00001400 0x000400>; /* ap 3 */ }; segment@100000 { /* 0x44d00000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ <0x00004000 0x00104000 0x001000>, /* ap 5 */ <0x00080000 0x00180000 0x002000>, /* ap 6 */ <0x00082000 0x00182000 0x001000>, /* ap 7 */ <0x000f0000 0x001f0000 0x010000>; /* ap 8 */ target-module@0 { /* 0x44d00000, ap 4 28.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x4000>; }; target-module@80000 { /* 0x44d80000, ap 6 10.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000 0x2000>; }; target-module@f0000 { /* 0x44df0000, ap 8 58.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xf0000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xf0000 0x10000>; prcm: prcm@0 { compatible = "ti,am4-prcm", "simple-bus"; reg = <0x0 0x11000>; interrupts = ; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x11000>; prcm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; prcm_clockdomains: clockdomains { }; }; }; }; segment@200000 { /* 0x44e00000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00200000 0x001000>, /* ap 9 */ <0x00003000 0x00203000 0x001000>, /* ap 10 */ <0x00004000 0x00204000 0x001000>, /* ap 11 */ <0x00005000 0x00205000 0x001000>, /* ap 12 */ <0x00006000 0x00206000 0x001000>, /* ap 13 */ <0x00007000 0x00207000 0x001000>, /* ap 14 */ <0x00008000 0x00208000 0x001000>, /* ap 15 */ <0x00009000 0x00209000 0x001000>, /* ap 16 */ <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ <0x00010000 0x00210000 0x010000>, /* ap 22 */ <0x00030000 0x00230000 0x001000>, /* ap 23 */ <0x00031000 0x00231000 0x001000>, /* ap 24 */ <0x00032000 0x00232000 0x001000>, /* ap 25 */ <0x00033000 0x00233000 0x001000>, /* ap 26 */ <0x00034000 0x00234000 0x001000>, /* ap 27 */ <0x00035000 0x00235000 0x001000>, /* ap 28 */ <0x00036000 0x00236000 0x001000>, /* ap 29 */ <0x00037000 0x00237000 0x001000>, /* ap 30 */ <0x00038000 0x00238000 0x001000>, /* ap 31 */ <0x00039000 0x00239000 0x001000>, /* ap 32 */ <0x0003a000 0x0023a000 0x001000>, /* ap 33 */ <0x0003e000 0x0023e000 0x001000>, /* ap 34 */ <0x0003f000 0x0023f000 0x001000>, /* ap 35 */ <0x00040000 0x00240000 0x040000>, /* ap 36 */ <0x00080000 0x00280000 0x001000>, /* ap 37 */ <0x00088000 0x00288000 0x008000>, /* ap 38 */ <0x00092000 0x00292000 0x001000>, /* ap 39 */ <0x00086000 0x00286000 0x001000>, /* ap 40 */ <0x00087000 0x00287000 0x001000>, /* ap 41 */ <0x00090000 0x00290000 0x001000>, /* ap 42 */ <0x00091000 0x00291000 0x001000>; /* ap 43 */ target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3000 0x1000>; }; target-module@5000 { /* 0x44e05000, ap 12 30.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5000 0x1000>; }; target-module@7000 { /* 0x44e07000, ap 14 20.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio1"; reg = <0x7000 0x4>, <0x7010 0x4>, <0x7114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 0>, <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x7000 0x1000>; gpio0: gpio@0 { compatible = "ti,am4372-gpio","ti,omap4-gpio"; reg = <0x0 0x1000>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; }; target-module@9000 { /* 0x44e09000, ap 16 04.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart1"; reg = <0x9050 0x4>, <0x9054 0x4>, <0x9058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_UART1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9000 0x1000>; uart0: serial@0 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x0 0x2000>; interrupts = ; }; }; target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c1"; reg = <0xb000 0x8>, <0xb010 0x8>, <0xb090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_I2C1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb000 0x1000>; i2c0: i2c@0 { compatible = "ti,am4372-i2c","ti,omap4-i2c"; reg = <0x0 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "adc_tsc"; reg = <0xd000 0x4>, <0xd010 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , , ; /* Domains (P, C): wkup_pwrdm, l3s_tsc_clkdm */ clocks = <&l3s_tsc_clkctrl AM4_L3S_TSC_ADC_TSC_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd000 0x1000>; tscadc: tscadc@0 { compatible = "ti,am3359-tscadc"; reg = <0x0 0x1000>; interrupts = ; clocks = <&adc_tsc_fck>; clock-names = "fck"; status = "disabled"; dmas = <&edma 53 0>, <&edma 57 0>; dma-names = "fifo0", "fifo1"; tsc { compatible = "ti,am3359-tsc"; }; adc { #io-channel-cells = <1>; compatible = "ti,am3359-adc"; }; }; }; target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x10000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x10000 0x10000>; scm: scm@0 { compatible = "ti,am4-scm", "simple-bus"; reg = <0x0 0x4000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x4000>; am43xx_pinmux: pinmux@800 { compatible = "ti,am437-padconf", "pinctrl-single"; reg = <0x800 0x31c>; #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; scm_conf: scm_conf@0 { compatible = "syscon", "simple-bus"; reg = <0x0 0x800>; #address-cells = <1>; #size-cells = <1>; phy_gmii_sel: phy-gmii-sel { compatible = "ti,am43xx-phy-gmii-sel"; reg = <0x650 0x4>; #phy-cells = <2>; }; scm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; }; wkup_m3_ipc: wkup_m3_ipc@1324 { compatible = "ti,am4372-wkup-m3-ipc"; reg = <0x1324 0x44>; interrupts = ; ti,rproc = <&wkup_m3>; mboxes = <&mailbox &mbox_wkupm3>; }; edma_xbar: dma-router@f90 { compatible = "ti,am335x-edma-crossbar"; reg = <0xf90 0x40>; #dma-cells = <3>; dma-requests = <64>; dma-masters = <&edma>; }; scm_clockdomains: clockdomains { }; }; }; target-module@31000 { /* 0x44e31000, ap 24 40.0 */ compatible = "ti,sysc-omap2-timer", "ti,sysc"; ti,hwmods = "timer1"; reg = <0x31000 0x4>, <0x31010 0x4>, <0x31014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x31000 0x1000>; timer1: timer@0 { compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; reg = <0x0 0x400>; interrupts = ; ti,timer-alwon; clocks = <&timer1_fck>; clock-names = "fck"; }; }; target-module@33000 { /* 0x44e33000, ap 26 18.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x33000 0x1000>; }; target-module@35000 { /* 0x44e35000, ap 28 50.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "wd_timer2"; reg = <0x35000 0x4>, <0x35010 0x4>, <0x35014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_WD_TIMER2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x35000 0x1000>; wdt: wdt@0 { compatible = "ti,am4372-wdt","ti,omap3-wdt"; reg = <0x0 0x1000>; interrupts = ; }; }; target-module@37000 { /* 0x44e37000, ap 30 08.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x37000 0x1000>; }; target-module@39000 { /* 0x44e39000, ap 32 02.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x39000 0x1000>; }; target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */ compatible = "ti,sysc-omap4-simple", "ti,sysc"; ti,hwmods = "rtc"; reg = <0x3e074 0x4>, <0x3e078 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , , ; /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ clocks = <&l4_rtc_clkctrl AM4_L4_RTC_RTC_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3e000 0x1000>; rtc: rtc@0 { compatible = "ti,am4372-rtc", "ti,am3352-rtc", "ti,da830-rtc"; reg = <0x0 0x1000>; interrupts = ; clocks = <&clk_32768_ck>; clock-names = "int-clk"; system-power-controller; status = "disabled"; }; }; target-module@40000 { /* 0x44e40000, ap 36 68.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x40000 0x40000>; }; target-module@86000 { /* 0x44e86000, ap 40 70.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "counter_32k"; reg = <0x86000 0x4>, <0x86004 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , ; /* Domains (P, C): wkup_pwrdm, l4_wkup_aon_clkdm */ clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x86000 0x1000>; counter32k: counter@0 { compatible = "ti,am4372-counter32k","ti,omap-counter32k"; reg = <0x0 0x40>; }; }; target-module@88000 { /* 0x44e88000, ap 38 12.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00088000 0x00008000>, <0x00008000 0x00090000 0x00001000>, <0x00009000 0x00091000 0x00001000>; }; }; }; &l4_fast { /* 0x4a000000 */ compatible = "ti,am4-l4-fast", "simple-bus"; reg = <0x4a000000 0x800>, <0x4a000800 0x800>, <0x4a001000 0x400>; reg-names = "ap", "la", "ia0"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ segment@0 { /* 0x4a000000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00000800 0x00000800 0x000800>, /* ap 1 */ <0x00001000 0x00001000 0x000400>, /* ap 2 */ <0x00100000 0x00100000 0x008000>, /* ap 3 */ <0x00108000 0x00108000 0x001000>, /* ap 4 */ <0x00400000 0x00400000 0x002000>, /* ap 5 */ <0x00402000 0x00402000 0x001000>, /* ap 6 */ <0x00200000 0x00200000 0x080000>, /* ap 7 */ <0x00280000 0x00280000 0x001000>; /* ap 8 */ target-module@100000 { /* 0x4a100000, ap 3 04.0 */ compatible = "ti,sysc-omap4-simple", "ti,sysc"; reg = <0x101200 0x4>, <0x101208 0x4>, <0x101204 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <0>; ti,sysc-midle = , ; ti,sysc-sidle = , ; ti,syss-mask = <1>; clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x100000 0x8000>; mac: ethernet@0 { compatible = "ti,am4372-cpsw","ti,cpsw"; reg = <0x0 0x800 0x1200 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <1>; clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>, <&dpll_clksel_mac_clk>; clock-names = "fck", "cpts", "50mclk"; assigned-clocks = <&dpll_clksel_mac_clk>; assigned-clock-rates = <50000000>; status = "disabled"; cpdma_channels = <8>; ale_entries = <1024>; bd_ram_size = <0x2000>; mac_control = <0x20>; slaves = <2>; active_slave = <0>; cpts_clock_mult = <0x80000000>; cpts_clock_shift = <29>; ranges = <0 0 0x8000>; syscon = <&scm_conf>; davinci_mdio: mdio@1000 { compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio"; reg = <0x1000 0x100>; clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; status = "disabled"; }; cpsw_emac0: slave@200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; phys = <&phy_gmii_sel 1 0>; }; cpsw_emac1: slave@300 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; phys = <&phy_gmii_sel 2 0>; }; }; }; target-module@200000 { /* 0x4a200000, ap 7 02.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x200000 0x80000>; }; target-module@400000 { /* 0x4a400000, ap 5 08.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x400000 0x2000>; }; }; }; &l4_per { /* 0x48000000 */ compatible = "ti,am4-l4-per", "simple-bus"; reg = <0x48000000 0x800>, <0x48000800 0x800>, <0x48001000 0x400>, <0x48001400 0x400>, <0x48001800 0x400>, <0x48001c00 0x400>; reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ <0x00100000 0x48100000 0x100000>, /* segment 1 */ <0x00200000 0x48200000 0x100000>, /* segment 2 */ <0x00300000 0x48300000 0x100000>, /* segment 3 */ <0x46000000 0x46000000 0x400000>, /* l3 data port */ <0x46400000 0x46400000 0x400000>; /* l3 data port */ segment@0 { /* 0x48000000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00000800 0x00000800 0x000800>, /* ap 1 */ <0x00001000 0x00001000 0x000400>, /* ap 2 */ <0x00001400 0x00001400 0x000400>, /* ap 3 */ <0x00001800 0x00001800 0x000400>, /* ap 4 */ <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ <0x00008000 0x00008000 0x001000>, /* ap 6 */ <0x00009000 0x00009000 0x001000>, /* ap 7 */ <0x00022000 0x00022000 0x001000>, /* ap 8 */ <0x00023000 0x00023000 0x001000>, /* ap 9 */ <0x00024000 0x00024000 0x001000>, /* ap 10 */ <0x00025000 0x00025000 0x001000>, /* ap 11 */ <0x0002a000 0x0002a000 0x001000>, /* ap 12 */ <0x0002b000 0x0002b000 0x001000>, /* ap 13 */ <0x00038000 0x00038000 0x002000>, /* ap 14 */ <0x0003a000 0x0003a000 0x001000>, /* ap 15 */ <0x0003c000 0x0003c000 0x002000>, /* ap 16 */ <0x0003e000 0x0003e000 0x001000>, /* ap 17 */ <0x00040000 0x00040000 0x001000>, /* ap 18 */ <0x00041000 0x00041000 0x001000>, /* ap 19 */ <0x00042000 0x00042000 0x001000>, /* ap 20 */ <0x00043000 0x00043000 0x001000>, /* ap 21 */ <0x00044000 0x00044000 0x001000>, /* ap 22 */ <0x00045000 0x00045000 0x001000>, /* ap 23 */ <0x00046000 0x00046000 0x001000>, /* ap 24 */ <0x00047000 0x00047000 0x001000>, /* ap 25 */ <0x00048000 0x00048000 0x001000>, /* ap 26 */ <0x00049000 0x00049000 0x001000>, /* ap 27 */ <0x0004c000 0x0004c000 0x001000>, /* ap 28 */ <0x0004d000 0x0004d000 0x001000>, /* ap 29 */ <0x00060000 0x00060000 0x001000>, /* ap 30 */ <0x00061000 0x00061000 0x001000>, /* ap 31 */ <0x00080000 0x00080000 0x010000>, /* ap 32 */ <0x00090000 0x00090000 0x001000>, /* ap 33 */ <0x00030000 0x00030000 0x001000>, /* ap 65 */ <0x00031000 0x00031000 0x001000>, /* ap 66 */ <0x0004a000 0x0004a000 0x001000>, /* ap 71 */ <0x0004b000 0x0004b000 0x001000>, /* ap 72 */ <0x000c8000 0x000c8000 0x001000>, /* ap 73 */ <0x000c9000 0x000c9000 0x001000>, /* ap 74 */ <0x000ca000 0x000ca000 0x001000>, /* ap 77 */ <0x000cb000 0x000cb000 0x001000>, /* ap 78 */ <0x00034000 0x00034000 0x001000>, /* ap 80 */ <0x00035000 0x00035000 0x001000>, /* ap 81 */ <0x00036000 0x00036000 0x001000>, /* ap 84 */ <0x00037000 0x00037000 0x001000>, /* ap 85 */ <0x46000000 0x46000000 0x400000>, /* l3 data port */ <0x46400000 0x46400000 0x400000>; /* l3 data port */ target-module@8000 { /* 0x48008000, ap 6 10.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x1000>; }; target-module@22000 { /* 0x48022000, ap 8 0a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart2"; reg = <0x22050 0x4>, <0x22054 0x4>, <0x22058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_UART2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x22000 0x1000>; uart1: serial@0 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x0 0x2000>; interrupts = ; status = "disabled"; }; }; target-module@24000 { /* 0x48024000, ap 10 1c.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart3"; reg = <0x24050 0x4>, <0x24054 0x4>, <0x24058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_UART3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x24000 0x1000>; uart2: serial@0 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x0 0x2000>; interrupts = ; status = "disabled"; }; }; target-module@2a000 { /* 0x4802a000, ap 12 22.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c2"; reg = <0x2a000 0x8>, <0x2a010 0x8>, <0x2a090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_I2C2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2a000 0x1000>; i2c1: i2c@0 { compatible = "ti,am4372-i2c","ti,omap4-i2c"; reg = <0x0 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; target-module@30000 { /* 0x48030000, ap 65 08.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spi0"; reg = <0x30000 0x4>, <0x30110 0x4>, <0x30114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_SPI0_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x30000 0x1000>; spi0: spi@0 { compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; reg = <0x0 0x400>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; target-module@34000 { /* 0x48034000, ap 80 56.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x34000 0x1000>; }; target-module@36000 { /* 0x48036000, ap 84 3e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x36000 0x1000>; }; target-module@38000 { /* 0x48038000, ap 14 04.0 */ compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "mcasp0"; reg = <0x38000 0x4>, <0x38004 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , ; /* Domains (P, C): per_pwrdm, l3s_clkdm */ clocks = <&l3s_clkctrl AM4_L3S_MCASP0_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x38000 0x2000>, <0x46000000 0x46000000 0x400000>; mcasp0: mcasp@0 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x2000>, <0x46000000 0x400000>; reg-names = "mpu", "dat"; interrupts = , ; interrupt-names = "tx", "rx"; status = "disabled"; dmas = <&edma 8 2>, <&edma 9 2>; dma-names = "tx", "rx"; }; }; target-module@3c000 { /* 0x4803c000, ap 16 2a.0 */ compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "mcasp1"; reg = <0x3c000 0x4>, <0x3c004 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , ; /* Domains (P, C): per_pwrdm, l3s_clkdm */ clocks = <&l3s_clkctrl AM4_L3S_MCASP1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3c000 0x2000>, <0x46400000 0x46400000 0x400000>; mcasp1: mcasp@0 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x2000>, <0x46400000 0x400000>; reg-names = "mpu", "dat"; interrupts = , ; interrupt-names = "tx", "rx"; status = "disabled"; dmas = <&edma 10 2>, <&edma 11 2>; dma-names = "tx", "rx"; }; }; target-module@40000 { /* 0x48040000, ap 18 1e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; ti,hwmods = "timer2"; reg = <0x40000 0x4>, <0x40010 0x4>, <0x40014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x40000 0x1000>; timer2: timer@0 { compatible = "ti,am4372-timer","ti,am335x-timer"; reg = <0x0 0x400>; interrupts = ; clocks = <&timer2_fck>; clock-names = "fck"; }; }; target-module@42000 { /* 0x48042000, ap 20 24.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer3"; reg = <0x42000 0x4>, <0x42010 0x4>, <0x42014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x42000 0x1000>; timer3: timer@0 { compatible = "ti,am4372-timer","ti,am335x-timer"; reg = <0x0 0x400>; interrupts = ; status = "disabled"; }; }; target-module@44000 { /* 0x48044000, ap 22 26.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer4"; reg = <0x44000 0x4>, <0x44010 0x4>, <0x44014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x44000 0x1000>; timer4: timer@0 { compatible = "ti,am4372-timer","ti,am335x-timer"; reg = <0x0 0x400>; interrupts = ; ti,timer-pwm; status = "disabled"; }; }; target-module@46000 { /* 0x48046000, ap 24 28.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer5"; reg = <0x46000 0x4>, <0x46010 0x4>, <0x46014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER5_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x46000 0x1000>; timer5: timer@0 { compatible = "ti,am4372-timer","ti,am335x-timer"; reg = <0x0 0x400>; interrupts = ; ti,timer-pwm; status = "disabled"; }; }; target-module@48000 { /* 0x48048000, ap 26 1a.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer6"; reg = <0x48000 0x4>, <0x48010 0x4>, <0x48014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER6_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x48000 0x1000>; timer6: timer@0 { compatible = "ti,am4372-timer","ti,am335x-timer"; reg = <0x0 0x400>; interrupts = ; ti,timer-pwm; status = "disabled"; }; }; target-module@4a000 { /* 0x4804a000, ap 71 48.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer7"; reg = <0x4a000 0x4>, <0x4a010 0x4>, <0x4a014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER7_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4a000 0x1000>; timer7: timer@0 { compatible = "ti,am4372-timer","ti,am335x-timer"; reg = <0x0 0x400>; interrupts = ; ti,timer-pwm; status = "disabled"; }; }; target-module@4c000 { /* 0x4804c000, ap 28 36.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio2"; reg = <0x4c000 0x4>, <0x4c010 0x4>, <0x4c114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 0>, <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4c000 0x1000>; gpio1: gpio@0 { compatible = "ti,am4372-gpio","ti,omap4-gpio"; reg = <0x0 0x1000>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; }; target-module@60000 { /* 0x48060000, ap 30 14.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mmc1"; reg = <0x602fc 0x4>, <0x60110 0x4>, <0x60114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_MMC1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x60000 0x1000>; mmc1: mmc@0 { compatible = "ti,omap4-hsmmc"; reg = <0x0 0x1000>; ti,dual-volt; ti,needs-special-reset; dmas = <&edma 24 0>, <&edma 25 0>; dma-names = "tx", "rx"; interrupts = ; status = "disabled"; }; }; target-module@80000 { /* 0x48080000, ap 32 18.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "elm"; reg = <0x80000 0x4>, <0x80010 0x4>, <0x80014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_ELM_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000 0x10000>; elm: elm@0 { compatible = "ti,am3352-elm"; reg = <0x0 0x2000>; interrupts = ; clocks = <&l4ls_gclk>; clock-names = "fck"; status = "disabled"; }; }; target-module@c8000 { /* 0x480c8000, ap 73 06.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox"; reg = <0xc8000 0x4>, <0xc8010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_MAILBOX_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc8000 0x1000>; mailbox: mailbox@0 { compatible = "ti,omap4-mailbox"; reg = <0x0 0x200>; interrupts = ; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; mbox_wkupm3: wkup_m3 { ti,mbox-send-noirq; ti,mbox-tx = <0 0 0>; ti,mbox-rx = <0 0 3>; }; }; }; target-module@ca000 { /* 0x480ca000, ap 77 38.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spinlock"; reg = <0xca000 0x4>, <0xca010 0x4>, <0xca014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_SPINLOCK_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xca000 0x1000>; hwspinlock: spinlock@0 { compatible = "ti,omap4-hwspinlock"; reg = <0x0 0x1000>; #hwlock-cells = <1>; }; }; }; segment@100000 { /* 0x48100000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 34 */ <0x0008d000 0x0018d000 0x001000>, /* ap 35 */ <0x0008e000 0x0018e000 0x001000>, /* ap 36 */ <0x0008f000 0x0018f000 0x001000>, /* ap 37 */ <0x0009c000 0x0019c000 0x001000>, /* ap 38 */ <0x0009d000 0x0019d000 0x001000>, /* ap 39 */ <0x000a6000 0x001a6000 0x001000>, /* ap 40 */ <0x000a7000 0x001a7000 0x001000>, /* ap 41 */ <0x000a8000 0x001a8000 0x001000>, /* ap 42 */ <0x000a9000 0x001a9000 0x001000>, /* ap 43 */ <0x000aa000 0x001aa000 0x001000>, /* ap 44 */ <0x000ab000 0x001ab000 0x001000>, /* ap 45 */ <0x000ac000 0x001ac000 0x001000>, /* ap 46 */ <0x000ad000 0x001ad000 0x001000>, /* ap 47 */ <0x000ae000 0x001ae000 0x001000>, /* ap 48 */ <0x000af000 0x001af000 0x001000>, /* ap 49 */ <0x000cc000 0x001cc000 0x002000>, /* ap 50 */ <0x000ce000 0x001ce000 0x002000>, /* ap 51 */ <0x000d0000 0x001d0000 0x002000>, /* ap 52 */ <0x000d2000 0x001d2000 0x002000>, /* ap 53 */ <0x000d8000 0x001d8000 0x001000>, /* ap 54 */ <0x000d9000 0x001d9000 0x001000>, /* ap 55 */ <0x000a0000 0x001a0000 0x001000>, /* ap 67 */ <0x000a1000 0x001a1000 0x001000>, /* ap 68 */ <0x000a2000 0x001a2000 0x001000>, /* ap 69 */ <0x000a3000 0x001a3000 0x001000>, /* ap 70 */ <0x000a4000 0x001a4000 0x001000>, /* ap 92 */ <0x000a5000 0x001a5000 0x001000>, /* ap 93 */ <0x000c1000 0x001c1000 0x001000>, /* ap 94 */ <0x000c2000 0x001c2000 0x001000>; /* ap 95 */ target-module@8c000 { /* 0x4818c000, ap 34 0c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8c000 0x1000>; }; target-module@8e000 { /* 0x4818e000, ap 36 02.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8e000 0x1000>; }; target-module@9c000 { /* 0x4819c000, ap 38 52.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c3"; reg = <0x9c000 0x8>, <0x9c010 0x8>, <0x9c090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_I2C3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9c000 0x1000>; i2c2: i2c@0 { compatible = "ti,am4372-i2c","ti,omap4-i2c"; reg = <0x0 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spi1"; reg = <0xa0000 0x4>, <0xa0110 0x4>, <0xa0114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_SPI1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa0000 0x1000>; spi1: spi@0 { compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; reg = <0x0 0x400>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spi2"; reg = <0xa2000 0x4>, <0xa2110 0x4>, <0xa2114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_SPI2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa2000 0x1000>; spi2: spi@0 { compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; reg = <0x0 0x400>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; target-module@a4000 { /* 0x481a4000, ap 92 62.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spi3"; reg = <0xa4000 0x4>, <0xa4110 0x4>, <0xa4114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_SPI3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa4000 0x1000>; spi3: spi@0 { compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; reg = <0x0 0x400>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; target-module@a6000 { /* 0x481a6000, ap 40 16.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart4"; reg = <0xa6050 0x4>, <0xa6054 0x4>, <0xa6058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_UART4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa6000 0x1000>; uart3: serial@0 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x0 0x2000>; interrupts = ; status = "disabled"; }; }; target-module@a8000 { /* 0x481a8000, ap 42 20.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart5"; reg = <0xa8050 0x4>, <0xa8054 0x4>, <0xa8058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_UART5_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa8000 0x1000>; uart4: serial@0 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x0 0x2000>; interrupts = ; status = "disabled"; }; }; target-module@aa000 { /* 0x481aa000, ap 44 12.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart6"; reg = <0xaa050 0x4>, <0xaa054 0x4>, <0xaa058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_UART6_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xaa000 0x1000>; uart5: serial@0 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x0 0x2000>; interrupts = ; status = "disabled"; }; }; target-module@ac000 { /* 0x481ac000, ap 46 30.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio3"; reg = <0xac000 0x4>, <0xac010 0x4>, <0xac114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 0>, <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xac000 0x1000>; gpio2: gpio@0 { compatible = "ti,am4372-gpio","ti,omap4-gpio"; reg = <0x0 0x1000>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; }; target-module@ae000 { /* 0x481ae000, ap 48 32.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio4"; reg = <0xae000 0x4>, <0xae010 0x4>, <0xae114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 0>, <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xae000 0x1000>; gpio3: gpio@0 { compatible = "ti,am4372-gpio","ti,omap4-gpio"; reg = <0x0 0x1000>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; }; target-module@c1000 { /* 0x481c1000, ap 94 68.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer8"; reg = <0xc1000 0x4>, <0xc1010 0x4>, <0xc1014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER8_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc1000 0x1000>; timer8: timer@0 { compatible = "ti,am4372-timer","ti,am335x-timer"; reg = <0x0 0x400>; interrupts = ; status = "disabled"; }; }; target-module@cc000 { /* 0x481cc000, ap 50 46.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xcc020 0x4>; reg-names = "rev"; + ti,hwmods = "d_can0"; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xcc000 0x2000>; dcan0: can@0 { compatible = "ti,am4372-d_can", "ti,am3352-d_can"; reg = <0x0 0x2000>; syscon-raminit = <&scm_conf 0x644 0>; interrupts = ; status = "disabled"; }; }; target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xd0020 0x4>; reg-names = "rev"; + ti,hwmods = "d_can1"; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd0000 0x2000>; dcan1: can@0 { compatible = "ti,am4372-d_can", "ti,am3352-d_can"; reg = <0x0 0x2000>; syscon-raminit = <&scm_conf 0x644 1>; interrupts = ; status = "disabled"; }; }; target-module@d8000 { /* 0x481d8000, ap 54 5e.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mmc2"; reg = <0xd82fc 0x4>, <0xd8110 0x4>, <0xd8114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_MMC2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd8000 0x1000>; mmc2: mmc@0 { compatible = "ti,omap4-hsmmc"; reg = <0x0 0x1000>; ti,needs-special-reset; dmas = <&edma 2 0>, <&edma 3 0>; dma-names = "tx", "rx"; interrupts = ; status = "disabled"; }; }; }; segment@200000 { /* 0x48200000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; }; segment@300000 { /* 0x48300000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00300000 0x001000>, /* ap 56 */ <0x00001000 0x00301000 0x001000>, /* ap 57 */ <0x00002000 0x00302000 0x001000>, /* ap 58 */ <0x00003000 0x00303000 0x001000>, /* ap 59 */ <0x00004000 0x00304000 0x001000>, /* ap 60 */ <0x00005000 0x00305000 0x001000>, /* ap 61 */ <0x00018000 0x00318000 0x004000>, /* ap 62 */ <0x0001c000 0x0031c000 0x001000>, /* ap 63 */ <0x00010000 0x00310000 0x002000>, /* ap 64 */ <0x00028000 0x00328000 0x001000>, /* ap 75 */ <0x00029000 0x00329000 0x001000>, /* ap 76 */ <0x00012000 0x00312000 0x001000>, /* ap 79 */ <0x00020000 0x00320000 0x001000>, /* ap 82 */ <0x00021000 0x00321000 0x001000>, /* ap 83 */ <0x00026000 0x00326000 0x001000>, /* ap 86 */ <0x00027000 0x00327000 0x001000>, /* ap 87 */ <0x0002a000 0x0032a000 0x000400>, /* ap 88 */ <0x0002c000 0x0032c000 0x001000>, /* ap 89 */ <0x00013000 0x00313000 0x001000>, /* ap 90 */ <0x00014000 0x00314000 0x001000>, /* ap 91 */ <0x00006000 0x00306000 0x001000>, /* ap 96 */ <0x00007000 0x00307000 0x001000>, /* ap 97 */ <0x00008000 0x00308000 0x001000>, /* ap 98 */ <0x00009000 0x00309000 0x001000>, /* ap 99 */ <0x0000a000 0x0030a000 0x001000>, /* ap 100 */ <0x0000b000 0x0030b000 0x001000>, /* ap 101 */ <0x0003d000 0x0033d000 0x001000>, /* ap 102 */ <0x0003e000 0x0033e000 0x001000>, /* ap 103 */ <0x0003f000 0x0033f000 0x001000>, /* ap 104 */ <0x00040000 0x00340000 0x001000>, /* ap 105 */ <0x00041000 0x00341000 0x001000>, /* ap 106 */ <0x00042000 0x00342000 0x001000>, /* ap 107 */ <0x00045000 0x00345000 0x001000>, /* ap 108 */ <0x00046000 0x00346000 0x001000>, /* ap 109 */ <0x00047000 0x00347000 0x001000>, /* ap 110 */ <0x00048000 0x00348000 0x001000>, /* ap 111 */ <0x000f2000 0x003f2000 0x002000>, /* ap 112 */ <0x000f4000 0x003f4000 0x001000>, /* ap 113 */ <0x0004c000 0x0034c000 0x002000>, /* ap 114 */ <0x0004e000 0x0034e000 0x001000>, /* ap 115 */ <0x00022000 0x00322000 0x001000>, /* ap 116 */ <0x00023000 0x00323000 0x001000>, /* ap 117 */ <0x000f0000 0x003f0000 0x001000>, /* ap 118 */ <0x0002a400 0x0032a400 0x000400>, /* ap 119 */ <0x0002a800 0x0032a800 0x000400>, /* ap 120 */ <0x0002ac00 0x0032ac00 0x000400>, /* ap 121 */ <0x0002b000 0x0032b000 0x001000>, /* ap 122 */ <0x00080000 0x00380000 0x020000>, /* ap 123 */ <0x000a0000 0x003a0000 0x001000>, /* ap 124 */ <0x000a8000 0x003a8000 0x008000>, /* ap 125 */ <0x000b0000 0x003b0000 0x001000>, /* ap 126 */ <0x000c0000 0x003c0000 0x020000>, /* ap 127 */ <0x000e0000 0x003e0000 0x001000>, /* ap 128 */ <0x000e8000 0x003e8000 0x008000>; /* ap 129 */ target-module@0 { /* 0x48300000, ap 56 40.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss0"; reg = <0x0 0x4>, <0x4 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS0_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x1000>; epwmss0: epwmss@0 { compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; reg = <0x0 0x10>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x1000>; status = "disabled"; ecap0: ecap@100 { compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; status = "disabled"; }; ehrpwm0: pwm@200 { compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; }; }; }; target-module@2000 { /* 0x48302000, ap 58 4a.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss1"; reg = <0x2000 0x4>, <0x2004 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x1000>; epwmss1: epwmss@0 { compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; reg = <0x0 0x10>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x1000>; status = "disabled"; ecap1: ecap@100 { compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; status = "disabled"; }; ehrpwm1: pwm@200 { compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; }; }; }; target-module@4000 { /* 0x48304000, ap 60 44.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss2"; reg = <0x4000 0x4>, <0x4004 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; epwmss2: epwmss@0 { compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; reg = <0x0 0x10>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x1000>; status = "disabled"; ecap2: ecap@100 { compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; status = "disabled"; }; ehrpwm2: pwm@200 { compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; }; }; }; target-module@6000 { /* 0x48306000, ap 96 58.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss3"; reg = <0x6000 0x4>, <0x6004 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6000 0x1000>; epwmss3: epwmss@0 { compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; reg = <0x0 0x10>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x1000>; status = "disabled"; ehrpwm3: pwm@200 { compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; }; }; }; target-module@8000 { /* 0x48308000, ap 98 54.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss4"; reg = <0x8000 0x4>, <0x8004 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x1000>; epwmss4: epwmss@0 { compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; reg = <0x0 0x10>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x1000>; status = "disabled"; ehrpwm4: pwm@48308200 { compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; }; }; }; target-module@a000 { /* 0x4830a000, ap 100 60.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss5"; reg = <0xa000 0x4>, <0xa004 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS5_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa000 0x1000>; epwmss5: epwmss@0 { compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; reg = <0x0 0x10>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x1000>; status = "disabled"; ehrpwm5: pwm@200 { compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; }; }; }; target-module@10000 { /* 0x48310000, ap 64 4e.1 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "rng"; reg = <0x11fe0 0x4>, <0x11fe4 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_RNG_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x10000 0x2000>; rng: rng@0 { compatible = "ti,omap4-rng"; reg = <0x0 0x2000>; interrupts = ; }; }; target-module@13000 { /* 0x48313000, ap 90 50.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x13000 0x1000>; }; target-module@18000 { /* 0x48318000, ap 62 4c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x18000 0x4000>; }; target-module@20000 { /* 0x48320000, ap 82 34.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio5"; reg = <0x20000 0x4>, <0x20010 0x4>, <0x20114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 0>, <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x1000>; gpio4: gpio@0 { compatible = "ti,am4372-gpio","ti,omap4-gpio"; reg = <0x0 0x1000>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; }; target-module@22000 { /* 0x48322000, ap 116 64.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio6"; reg = <0x22000 0x4>, <0x22010 0x4>, <0x22114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 0>, <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x22000 0x1000>; gpio5: gpio@0 { compatible = "ti,am4372-gpio","ti,omap4-gpio"; reg = <0x0 0x1000>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; }; target-module@26000 { /* 0x48326000, ap 86 66.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "vpfe0"; reg = <0x26000 0x4>, <0x26104 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = , , ; ti,sysc-sidle = , , ; /* Domains (P, C): per_pwrdm, l3s_clkdm */ clocks = <&l3s_clkctrl AM4_L3S_VPFE0_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x26000 0x1000>; vpfe0: vpfe@0 { compatible = "ti,am437x-vpfe"; reg = <0x0 0x2000>; interrupts = ; status = "disabled"; }; }; target-module@28000 { /* 0x48328000, ap 75 0e.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "vpfe1"; reg = <0x28000 0x4>, <0x28104 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = , , ; ti,sysc-sidle = , , ; /* Domains (P, C): per_pwrdm, l3s_clkdm */ clocks = <&l3s_clkctrl AM4_L3S_VPFE1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x28000 0x1000>; vpfe1: vpfe@0 { compatible = "ti,am437x-vpfe"; reg = <0x0 0x2000>; interrupts = ; status = "disabled"; }; }; target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "dss_core"; reg = <0x2a000 0x4>, <0x2a010 0x4>, <0x2a014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, dss_clkdm */ clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x0002a000 0x00000400>, <0x00000400 0x0002a400 0x00000400>, <0x00000800 0x0002a800 0x00000400>, <0x00000c00 0x0002ac00 0x00000400>, <0x00001000 0x0002b000 0x00001000>; }; target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer9"; reg = <0x3d000 0x4>, <0x3d010 0x4>, <0x3d014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER9_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3d000 0x1000>; timer9: timer@0 { compatible = "ti,am4372-timer","ti,am335x-timer"; reg = <0x0 0x400>; interrupts = ; status = "disabled"; }; }; target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer10"; reg = <0x3f000 0x4>, <0x3f010 0x4>, <0x3f014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER10_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3f000 0x1000>; timer10: timer@0 { compatible = "ti,am4372-timer","ti,am335x-timer"; reg = <0x0 0x400>; interrupts = ; status = "disabled"; }; }; target-module@41000 { /* 0x48341000, ap 106 76.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer11"; reg = <0x41000 0x4>, <0x41010 0x4>, <0x41014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER11_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x41000 0x1000>; timer11: timer@0 { compatible = "ti,am4372-timer","ti,am335x-timer"; reg = <0x0 0x400>; interrupts = ; status = "disabled"; }; }; target-module@45000 { /* 0x48345000, ap 108 6a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spi4"; reg = <0x45000 0x4>, <0x45110 0x4>, <0x45114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_SPI4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x45000 0x1000>; spi4: spi@0 { compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; reg = <0x0 0x400>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; target-module@47000 { /* 0x48347000, ap 110 70.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "hdq1w"; reg = <0x47000 0x4>, <0x47014 0x4>, <0x47018 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_HDQ1W_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x47000 0x1000>; hdq: hdq@0 { compatible = "ti,am4372-hdq"; reg = <0x0 0x1000>; interrupts = ; clocks = <&func_12m_clk>; clock-names = "fck"; status = "disabled"; }; }; target-module@4c000 { /* 0x4834c000, ap 114 72.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4c000 0x2000>; }; target-module@80000 { /* 0x48380000, ap 123 42.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "usb_otg_ss0"; reg = <0x80000 0x4>, <0x80010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l3s_clkdm */ clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000 0x20000>; dwc3_1: omap_dwc3@0 { compatible = "ti,am437x-dwc3"; reg = <0x0 0x10000>; interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <1>; ranges = <0 0 0x20000>; usb1: usb@10000 { compatible = "synopsys,dwc3"; reg = <0x10000 0x10000>; interrupts = , , ; interrupt-names = "peripheral", "host", "otg"; phys = <&usb2_phy1>; phy-names = "usb2-phy"; maximum-speed = "high-speed"; dr_mode = "otg"; status = "disabled"; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; }; }; }; target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "ocp2scp0"; reg = <0xa8000 0x4>; reg-names = "rev"; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP0_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa8000 0x8000>; ocp2scp0: ocp2scp@0 { compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x8000>; usb2_phy1: phy@8000 { compatible = "ti,am437x-usb2"; reg = <0x0 0x8000>; syscon-phy-power = <&scm_conf 0x620>; clocks = <&usb_phy0_always_on_clk32k>, <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 8>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; status = "disabled"; }; }; }; target-module@c0000 { /* 0x483c0000, ap 127 7a.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "usb_otg_ss1"; reg = <0xc0000 0x4>, <0xc0010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): per_pwrdm, l3s_clkdm */ clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc0000 0x20000>; dwc3_2: omap_dwc3@0 { compatible = "ti,am437x-dwc3"; reg = <0x0 0x10000>; interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <1>; ranges = <0 0 0x20000>; usb2: usb@10000 { compatible = "synopsys,dwc3"; reg = <0x10000 0x10000>; interrupts = , , ; interrupt-names = "peripheral", "host", "otg"; phys = <&usb2_phy2>; phy-names = "usb2-phy"; maximum-speed = "high-speed"; dr_mode = "otg"; status = "disabled"; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; }; }; }; target-module@e8000 { /* 0x483e8000, ap 129 78.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "ocp2scp1"; reg = <0xe8000 0x4>; reg-names = "rev"; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe8000 0x8000>; ocp2scp1: ocp2scp@0 { compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x8000>; usb2_phy2: phy@8000 { compatible = "ti,am437x-usb2"; reg = <0x0 0x8000>; syscon-phy-power = <&scm_conf 0x628>; clocks = <&usb_phy1_always_on_clk32k>, <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 8>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; status = "disabled"; }; }; }; target-module@f2000 { /* 0x483f2000, ap 112 5a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xf2000 0x2000>; }; }; }; diff --git a/sys/gnu/dts/arm/am437x-sk-evm.dts b/sys/gnu/dts/arm/am437x-sk-evm.dts index 25222497f828..74eaa6a3b258 100644 --- a/sys/gnu/dts/arm/am437x-sk-evm.dts +++ b/sys/gnu/dts/arm/am437x-sk-evm.dts @@ -1,912 +1,887 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ */ /* AM437x SK EVM */ /dts-v1/; #include "am4372.dtsi" #include #include #include #include #include / { model = "TI AM437x SK EVM"; compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43"; aliases { display0 = &lcd0; }; chosen { stdout-path = &uart0; }; /* fixed 32k external oscillator clock */ clk_32k_rtc: clk_32k_rtc { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; lcd_bl: backlight { compatible = "pwm-backlight"; pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 51 53 56 62 75 101 152 255>; default-brightness-level = <8>; }; sound { compatible = "simple-audio-card"; simple-audio-card,name = "AM437x-SK-EVM"; simple-audio-card,widgets = "Headphone", "Headphone Jack", "Line", "Line In"; simple-audio-card,routing = "Headphone Jack", "HPLOUT", "Headphone Jack", "HPROUT", "LINE1L", "Line In", "LINE1R", "Line In"; simple-audio-card,format = "dsp_b"; simple-audio-card,bitclock-master = <&sound_master>; simple-audio-card,frame-master = <&sound_master>; simple-audio-card,bitclock-inversion; simple-audio-card,cpu { sound-dai = <&mcasp1>; }; sound_master: simple-audio-card,codec { sound-dai = <&tlv320aic3106>; system-clock-frequency = <24000000>; }; }; matrix_keypad: matrix_keypad0 { compatible = "gpio-matrix-keypad"; pinctrl-names = "default"; pinctrl-0 = <&matrix_keypad_pins>; debounce-delay-ms = <5>; col-scan-delay-us = <5>; row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */ &gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */ linux,keymap = < MATRIX_KEY(0, 0, KEY_DOWN) MATRIX_KEY(0, 1, KEY_RIGHT) MATRIX_KEY(1, 0, KEY_LEFT) MATRIX_KEY(1, 1, KEY_UP) >; }; leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&leds_pins>; led0 { label = "am437x-sk:red:heartbeat"; gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */ linux,default-trigger = "heartbeat"; default-state = "off"; }; led1 { label = "am437x-sk:green:mmc1"; gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */ linux,default-trigger = "mmc0"; default-state = "off"; }; led2 { label = "am437x-sk:blue:cpu0"; gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */ linux,default-trigger = "cpu0"; default-state = "off"; }; led3 { label = "am437x-sk:blue:usr3"; gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */ default-state = "off"; }; }; lcd0: display { compatible = "newhaven,nhd-4.3-480272ef-atxl", "panel-dpi"; label = "lcd"; pinctrl-names = "default"; pinctrl-0 = <&lcd_pins>; backlight = <&lcd_bl>; enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; panel-timing { clock-frequency = <9000000>; hactive = <480>; vactive = <272>; hfront-porch = <2>; hback-porch = <2>; hsync-len = <41>; vfront-porch = <2>; vback-porch = <2>; vsync-len = <10>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <1>; }; port { lcd_in: endpoint { remote-endpoint = <&dpi_out>; }; }; }; vmmcwl_fixed: fixedregulator-mmcwl { /* * WL_EN is not SDIO standard compliant. It is an out of band * signal and hard to be dealt with in a standard way by the * SDIO core driver. * So modelling the WL_EN line as a regulator was a natural * choice as the MMC core already deals with MMC supplies. */ compatible = "regulator-fixed"; regulator-name = "vmmcwl_fixed"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; &am43xx_pinmux { matrix_keypad_pins: matrix_keypad_pins { pinctrl-single,pins = < AM4372_IOPAD(0xa4c, PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */ AM4372_IOPAD(0xa50, PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */ AM4372_IOPAD(0xa54, PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */ AM4372_IOPAD(0xa58, PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */ >; }; leds_pins: leds_pins { pinctrl-single,pins = < AM4372_IOPAD(0xa28, PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */ AM4372_IOPAD(0xa2c, PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */ AM4372_IOPAD(0xa30, PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */ AM4372_IOPAD(0xa34, PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */ >; }; i2c0_pins: i2c0_pins { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; i2c1_pins: i2c1_pins { pinctrl-single,pins = < AM4372_IOPAD(0x95c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ AM4372_IOPAD(0x958, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < AM4372_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ AM4372_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ AM4372_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ AM4372_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; ecap0_pins: backlight_pins { pinctrl-single,pins = < AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ >; }; edt_ft5306_ts_pins: edt_ft5306_ts_pins { pinctrl-single,pins = < AM4372_IOPAD(0x874, PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ AM4372_IOPAD(0x878, PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ >; }; vpfe0_pins_default: vpfe0_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ AM4372_IOPAD(0x9b8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/ AM4372_IOPAD(0x9bc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/ AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ >; }; vpfe0_pins_sleep: vpfe0_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9b8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9bc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) >; }; - clkout1_pin: pinmux_clkout1_pin { - pinctrl-single,pins = < - 0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */ - >; - }; - cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ AM4372_IOPAD(0x914, PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ AM4372_IOPAD(0x928, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ AM4372_IOPAD(0x924, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ AM4372_IOPAD(0x920, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ AM4372_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ AM4372_IOPAD(0x930, PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ AM4372_IOPAD(0x918, PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ AM4372_IOPAD(0x940, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ AM4372_IOPAD(0x93c, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ AM4372_IOPAD(0x938, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ AM4372_IOPAD(0x934, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ /* Slave 2 */ AM4372_IOPAD(0x858, PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ AM4372_IOPAD(0x840, PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ AM4372_IOPAD(0x854, PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ AM4372_IOPAD(0x850, PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ AM4372_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ AM4372_IOPAD(0x848, PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ AM4372_IOPAD(0x85c, PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ AM4372_IOPAD(0x844, PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ AM4372_IOPAD(0x86c, PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ AM4372_IOPAD(0x868, PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ AM4372_IOPAD(0x864, PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ AM4372_IOPAD(0x860, PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) /* Slave 2 reset value */ AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ AM4372_IOPAD(0x948, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ AM4372_IOPAD(0x94c, PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; dss_pins: dss_pins { pinctrl-single,pins = < AM4372_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ AM4372_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) AM4372_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) AM4372_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) AM4372_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) AM4372_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) AM4372_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) AM4372_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */ AM4372_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */ AM4372_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) AM4372_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) AM4372_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) AM4372_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) AM4372_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) AM4372_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) AM4372_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) AM4372_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) AM4372_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) AM4372_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) AM4372_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) AM4372_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) AM4372_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) AM4372_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) AM4372_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */ AM4372_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */ AM4372_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */ AM4372_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */ AM4372_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ >; }; qspi_pins: qspi_pins { pinctrl-single,pins = < AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */ AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ AM4372_IOPAD(0x890, PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ AM4372_IOPAD(0x894, PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ AM4372_IOPAD(0x898, PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */ AM4372_IOPAD(0x89c, PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ >; }; mcasp1_pins: mcasp1_pins { pinctrl-single,pins = < AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ >; }; mcasp1_pins_sleep: mcasp1_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; lcd_pins: lcd_pins { pinctrl-single,pins = < AM4372_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ >; }; usb1_pins: usb1_pins { pinctrl-single,pins = < AM4372_IOPAD(0xac0, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ >; }; usb2_pins: usb2_pins { pinctrl-single,pins = < AM4372_IOPAD(0xac4, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ >; }; mmc3_pins_default: pinmux_mmc3_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD21) cam1_data2.mmc2_clk */ AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE22) cam1_data3.mmc2_cmd */ AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD22) cam1_data4.mmc2_dat0 */ AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE23) cam1_data5.mmc2_dat1 */ AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD23) cam1_data6.mmc2_dat2 */ AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE24) cam1_data7.mmc2_dat3 */ >; }; mmc3_pins_sleep: pinmux_mmc3_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD21) cam1_data2.mmc2_clk */ AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE22) cam1_data3.mmc2_cmd */ AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD22) cam1_data4.mmc2_dat0 */ AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE23) cam1_data5.mmc2_dat1 */ AM4372_IOPAD(0xa00, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD23) cam1_data6.mmc2_dat2 */ AM4372_IOPAD(0xa04, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE24) cam1_data7.mmc2_dat3 */ >; }; wlan_pins_default: pinmux_wlan_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */ AM4372_IOPAD(0x9e4, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */ >; }; wlan_pins_sleep: pinmux_wlan_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */ AM4372_IOPAD(0x9e4, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */ >; }; uart1_bt_pins_default: pinmux_uart1_bt_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd.uart1_rxd */ AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ AM4372_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data9.gpio4_7 BT_EN */ >; }; uart1_bt_pins_sleep: pinmux_uart1_bt_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x980, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.uart1_rxd */ AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.uart1_txd */ AM4372_IOPAD(0x978, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */ AM4372_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */ AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_data9.gpio4_7 BT_EN */ >; }; }; &i2c0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; clock-frequency = <100000>; tps@24 { compatible = "ti,tps65218"; reg = <0x24>; interrupts = ; interrupt-controller; #interrupt-cells = <2>; dcdc1: regulator-dcdc1 { /* VDD_CORE limits min of OPP50 and max of OPP100 */ regulator-name = "vdd_core"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1144000>; regulator-boot-on; regulator-always-on; }; dcdc2: regulator-dcdc2 { /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1378000>; regulator-boot-on; regulator-always-on; }; dcdc3: regulator-dcdc3 { regulator-name = "vdds_ddr"; regulator-boot-on; regulator-always-on; regulator-state-mem { regulator-on-in-suspend; }; regulator-state-disk { regulator-off-in-suspend; }; }; dcdc4: regulator-dcdc4 { regulator-name = "v3_3d"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; dcdc5: regulator-dcdc5 { compatible = "ti,tps65218-dcdc5"; regulator-name = "v1_0bat"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; regulator-state-mem { regulator-on-in-suspend; }; }; dcdc6: regulator-dcdc6 { compatible = "ti,tps65218-dcdc6"; regulator-name = "v1_8bat"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; regulator-state-mem { regulator-on-in-suspend; }; }; ldo1: regulator-ldo1 { regulator-name = "v1_8d"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; power-button { compatible = "ti,tps65218-pwrbutton"; status = "okay"; interrupts = <3 IRQ_TYPE_EDGE_BOTH>; }; }; at24@50 { compatible = "atmel,24c256"; pagesize = <64>; reg = <0x50>; }; }; &i2c1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; clock-frequency = <400000>; - ov2659@30 { - compatible = "ovti,ov2659"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&clkout1_pin>; - - clocks = <&clkout1_mux_ck>; - clock-names = "xvclk"; - assigned-clocks = <&clkout1_mux_ck>; - assigned-clock-parents = <&clkout1_osc_div_ck>; - - port { - ov2659_1: endpoint { - remote-endpoint = <&vpfe0_ep>; - link-frequencies = /bits/ 64 <70000000>; - }; - }; - }; - edt-ft5306@38 { status = "okay"; compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; pinctrl-names = "default"; pinctrl-0 = <&edt_ft5306_ts_pins>; reg = <0x38>; interrupt-parent = <&gpio0>; interrupts = <31 IRQ_TYPE_EDGE_FALLING>; reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; touchscreen-size-x = <480>; touchscreen-size-y = <272>; wakeup-source; }; tlv320aic3106: tlv320aic3106@1b { #sound-dai-cells = <0>; compatible = "ti,tlv320aic3106"; reg = <0x1b>; status = "okay"; /* Regulators */ AVDD-supply = <&dcdc4>; IOVDD-supply = <&dcdc4>; DRVDD-supply = <&dcdc4>; DVDD-supply = <&ldo1>; }; lis331dlh@18 { compatible = "st,lis331dlh"; reg = <0x18>; status = "okay"; Vdd-supply = <&dcdc4>; Vdd_IO-supply = <&dcdc4>; interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>; }; }; &epwmss0 { status = "okay"; }; &ecap0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins>; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &gpio4 { status = "okay"; }; &gpio5 { status = "okay"; }; &mmc1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; vmmc-supply = <&dcdc4>; bus-width = <4>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; &uart1 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart1_bt_pins_default>; pinctrl-1 = <&uart1_bt_pins_sleep>; }; &mmc3 { status = "okay"; /* * these are on the crossbar and are outlined in the * xbar-event-map element */ dmas = <&edma_xbar 30 0 1>, <&edma_xbar 31 0 2>; dma-names = "tx", "rx"; vmmc-supply = <&vmmcwl_fixed>; bus-width = <4>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&mmc3_pins_default>; pinctrl-1 = <&mmc3_pins_sleep>; cap-power-off-card; keep-power-in-suspend; ti,non-removable; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1835"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&wlan_pins_default>; pinctrl-1 = <&wlan_pins_sleep>; reg = <2>; interrupt-parent = <&gpio4>; interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; }; }; &usb2_phy1 { status = "okay"; }; &usb1 { dr_mode = "otg"; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&usb1_pins>; }; &usb2_phy2 { status = "okay"; }; &usb2 { dr_mode = "host"; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&usb2_pins>; }; &qspi { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&qspi_pins>; spi-max-frequency = <48000000>; m25p80@0 { compatible = "mx66l51235l"; spi-max-frequency = <48000000>; reg = <0>; spi-cpol; spi-cpha; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <1>; /* MTD partition table. * The ROM checks the first 512KiB * for a valid file to boot(XIP). */ partition@0 { label = "QSPI.U_BOOT"; reg = <0x00000000 0x000080000>; }; partition@1 { label = "QSPI.U_BOOT.backup"; reg = <0x00080000 0x00080000>; }; partition@2 { label = "QSPI.U-BOOT-SPL_OS"; reg = <0x00100000 0x00010000>; }; partition@3 { label = "QSPI.U_BOOT_ENV"; reg = <0x00110000 0x00010000>; }; partition@4 { label = "QSPI.U-BOOT-ENV.backup"; reg = <0x00120000 0x00010000>; }; partition@5 { label = "QSPI.KERNEL"; reg = <0x00130000 0x0800000>; }; partition@6 { label = "QSPI.FILESYSTEM"; reg = <0x00930000 0x36D0000>; }; }; }; &mac { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; dual_emac = <1>; status = "okay"; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; status = "okay"; ethphy0: ethernet-phy@4 { reg = <4>; }; ethphy1: ethernet-phy@5 { reg = <5>; }; }; &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "rgmii"; dual_emac_res_vlan = <1>; }; &cpsw_emac1 { phy-handle = <ðphy1>; phy-mode = "rgmii"; dual_emac_res_vlan = <2>; }; &elm { status = "okay"; }; &mcasp1 { #sound-dai-cells = <0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&mcasp1_pins>; pinctrl-1 = <&mcasp1_pins_sleep>; status = "okay"; op-mode = <0>; tdm-slots = <2>; serial-dir = < 0 0 1 2 >; tx-num-evt = <1>; rx-num-evt = <1>; }; &dss { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_pins>; port { dpi_out: endpoint@0 { remote-endpoint = <&lcd_in>; data-lines = <24>; }; }; }; &rtc { clocks = <&clk_32k_rtc>, <&clk_32768_ck>; clock-names = "ext-clk", "int-clk"; status = "okay"; }; &wdt { status = "okay"; }; &cpu { cpu0-supply = <&dcdc2>; }; &vpfe0 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&vpfe0_pins_default>; pinctrl-1 = <&vpfe0_pins_sleep>; /* Camera port */ port { vpfe0_ep: endpoint { - remote-endpoint = <&ov2659_1>; + /* remote-endpoint = <&sensor>; add once we have it */ ti,am437x-vpfe-interface = <0>; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; }; }; }; diff --git a/sys/gnu/dts/arm/am43x-epos-evm.dts b/sys/gnu/dts/arm/am43x-epos-evm.dts index 27259fd6f741..95314121d111 100644 --- a/sys/gnu/dts/arm/am43x-epos-evm.dts +++ b/sys/gnu/dts/arm/am43x-epos-evm.dts @@ -1,1029 +1,1006 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ */ /* AM43x EPOS EVM */ /dts-v1/; #include "am4372.dtsi" #include #include #include #include / { model = "TI AM43x EPOS EVM"; compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43"; aliases { display0 = &lcd0; }; chosen { stdout-path = &uart0; }; vmmcsd_fixed: fixedregulator-sd { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; }; vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-boot-on; }; lcd0: display { - compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; + compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; label = "lcd"; backlight = <&lcd_bl>; panel-timing { clock-frequency = <33000000>; hactive = <800>; vactive = <480>; hfront-porch = <210>; hback-porch = <16>; hsync-len = <30>; vback-porch = <10>; vfront-porch = <22>; vsync-len = <13>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <1>; }; port { lcd_in: endpoint { remote-endpoint = <&dpi_out>; }; }; }; matrix_keypad: matrix_keypad0 { compatible = "gpio-matrix-keypad"; debounce-delay-ms = <5>; col-scan-delay-us = <2>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&matrix_keypad_default>; pinctrl-1 = <&matrix_keypad_sleep>; wakeup-source; row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ linux,keymap = <0x00000201 /* P1 */ 0x01000204 /* P4 */ 0x02000207 /* P7 */ 0x0300020a /* NUMERIC_STAR */ 0x00010202 /* P2 */ 0x01010205 /* P5 */ 0x02010208 /* P8 */ 0x03010200 /* P0 */ 0x00020203 /* P3 */ 0x01020206 /* P6 */ 0x02020209 /* P9 */ 0x0302020b /* NUMERIC_POUND */ 0x00030067 /* UP */ 0x0103006a /* RIGHT */ 0x0203006c /* DOWN */ 0x03030069>; /* LEFT */ }; lcd_bl: backlight { compatible = "pwm-backlight"; pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 51 53 56 62 75 101 152 255>; default-brightness-level = <8>; }; sound0: sound0 { compatible = "simple-audio-card"; simple-audio-card,name = "AM43-EPOS-EVM"; simple-audio-card,widgets = "Microphone", "Microphone Jack", "Headphone", "Headphone Jack", "Speaker", "Speaker"; simple-audio-card,routing = "MIC1LP", "Microphone Jack", "MIC1RP", "Microphone Jack", "MIC1LP", "MICBIAS", "MIC1RP", "MICBIAS", "Headphone Jack", "HPL", "Headphone Jack", "HPR", "Speaker", "SPL", "Speaker", "SPR"; simple-audio-card,format = "dsp_b"; simple-audio-card,bitclock-master = <&sound0_master>; simple-audio-card,frame-master = <&sound0_master>; simple-audio-card,bitclock-inversion; simple-audio-card,cpu { sound-dai = <&mcasp1>; system-clock-frequency = <12000000>; }; sound0_master: simple-audio-card,codec { sound-dai = <&tlv320aic3111>; system-clock-frequency = <12000000>; }; }; - - audio_mstrclk: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; }; &am43xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&unused_pins>; unused_pins: unused_pins { pinctrl-single,pins = < AM4372_IOPAD(0x848, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x850, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x858, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x860, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x864, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x868, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x86c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x878, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x908, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x91c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x920, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x9e0, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xA0c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xA38, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xA3c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xA40, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xA44, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xA48, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xA4c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xA50, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xA54, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xA58, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xA5c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xA60, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xA64, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0xA68, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xA6C, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xA74, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0xA78, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; nand_flash_x8_default: nand_flash_x8_default { pinctrl-single,pins = < AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ >; }; nand_flash_x8_sleep: nand_flash_x8_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x840, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x800, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x804, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x808, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x80c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x810, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x814, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x818, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x81c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x870, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x874, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; ecap0_pins_default: backlight_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ >; }; ecap0_pins_sleep: backlight_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x964, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ >; }; spi0_pins_default: pinmux_spi0_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ >; }; spi0_pins_sleep: pinmux_spi0_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x950, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x954, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x958, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x95c, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; spi1_pins_default: pinmux_spi1_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ >; }; spi1_pins_sleep: pinmux_spi1_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x990, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x994, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x998, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x99c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) >; }; mmc1_pins_default: pinmux_mmc1_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; mmc1_pins_sleep: pinmux_mmc1_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x960, DS0_PIN_OUTPUT_PULLUP | PIN_INPUT | MUX_MODE7) >; }; matrix_keypad_default: matrix_keypad_default { pinctrl-single,pins = < AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* mii1_tx_clk.gpio3_9 */ AM4372_IOPAD(0x930, PIN_OUTPUT | MUX_MODE7) /* mii1_rx_clk.gpio3_10 */ AM4372_IOPAD(0x934, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd3.gpio2_18 */ AM4372_IOPAD(0x938, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd2.gpio2_19 */ AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.gpio0_14 */ AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.gpio0_15 */ >; }; matrix_keypad_sleep: matrix_keypad_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; qspi1_pins_default: qspi1_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3) AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) >; }; qspi1_pins_sleep: qspi1_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x888, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; pixcir_ts_pins_default: pixcir_ts_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ >; }; pixcir_ts_pins_sleep: pixcir_ts_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x844, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ >; }; hdq_pins: pinmux_hdq_pins { pinctrl-single,pins = < AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ >; }; dss_pins: dss_pins { pinctrl-single,pins = < AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ >; }; display_mux_pins: display_mux_pins { pinctrl-single,pins = < /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; vpfe1_pins_default: vpfe1_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */ AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */ AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */ AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */ AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */ AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */ AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */ AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */ AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */ AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */ AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */ AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */ AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */ >; }; vpfe1_pins_sleep: vpfe1_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) >; }; uart0_pins_default: uart0_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ >; }; uart0_pins_sleep: uart0_pins_sleep { pinctrl-single,pins = < AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) >; }; usb2_phy1_default: usb2_phy1_default { pinctrl-single,pins = < AM4372_IOPAD(0xac0, PIN_INPUT_PULLDOWN | MUX_MODE0) >; }; usb2_phy1_sleep: usb2_phy1_sleep { pinctrl-single,pins = < AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; usb2_phy2_default: usb2_phy2_default { pinctrl-single,pins = < AM4372_IOPAD(0xac4, PIN_INPUT_PULLDOWN | MUX_MODE0) >; }; usb2_phy2_sleep: usb2_phy2_sleep { pinctrl-single,pins = < AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; mcasp1_pins: mcasp1_pins { pinctrl-single,pins = < AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */ AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */ AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */ >; }; mcasp1_sleep_pins: mcasp1_sleep_pins { pinctrl-single,pins = < AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; }; &mmc1 { status = "okay"; vmmc-supply = <&vmmcsd_fixed>; bus-width = <4>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&mmc1_pins_default>; pinctrl-1 = <&mmc1_pins_sleep>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; &mac { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; status = "okay"; slaves = <1>; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; status = "okay"; ethphy0: ethernet-phy@16 { reg = <16>; }; }; &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "rmii"; phys = <&phy_gmii_sel 1 1>; }; &i2c0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; clock-frequency = <400000>; tps65218: tps65218@24 { reg = <0x24>; compatible = "ti,tps65218"; interrupts = ; /* NMIn */ interrupt-controller; #interrupt-cells = <2>; dcdc1: regulator-dcdc1 { regulator-name = "vdd_core"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1144000>; regulator-boot-on; regulator-always-on; }; dcdc2: regulator-dcdc2 { regulator-name = "vdd_mpu"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1378000>; regulator-boot-on; regulator-always-on; }; dcdc3: regulator-dcdc3 { regulator-name = "vdcdc3"; regulator-boot-on; regulator-always-on; regulator-state-mem { regulator-on-in-suspend; }; regulator-state-disk { regulator-off-in-suspend; }; }; dcdc4: regulator-dcdc4 { regulator-name = "vdcdc4"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; dcdc5: regulator-dcdc5 { regulator-name = "v1_0bat"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; dcdc6: regulator-dcdc6 { regulator-name = "v1_8bat"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; ldo1: regulator-ldo1 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; }; at24@50 { compatible = "atmel,24c256"; pagesize = <64>; reg = <0x50>; }; pixcir_ts@5c { compatible = "pixcir,pixcir_tangoc"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&pixcir_ts_pins_default>; pinctrl-1 = <&pixcir_ts_pins_sleep>; reg = <0x5c>; interrupt-parent = <&gpio1>; interrupts = <17 IRQ_TYPE_EDGE_FALLING>; attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; touchscreen-size-x = <1024>; touchscreen-size-y = <600>; }; tlv320aic3111: tlv320aic3111@18 { #sound-dai-cells = <0>; compatible = "ti,tlv320aic3111"; reg = <0x18>; status = "okay"; ai31xx-micbias-vg = ; /* Regulators */ HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ SPRVDD-supply = <&vbat>; /* vbat */ SPLVDD-supply = <&vbat>; /* vbat */ AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ }; - - ov2659@30 { - compatible = "ovti,ov2659"; - reg = <0x30>; - - clocks = <&audio_mstrclk>; - clock-names = "xvclk"; - - port { - ov2659_1: endpoint { - remote-endpoint = <&vpfe1_ep>; - link-frequencies = /bits/ 64 <70000000>; - }; - }; - }; }; &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &gpio2 { pinctrl-names = "default"; pinctrl-0 = <&display_mux_pins>; status = "okay"; p1 { /* * SelLCDorHDMI selects between display and audio paths: * Low: HDMI display with audio via HDMI * High: LCD display with analog audio via aic3111 codec */ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; output-high; line-name = "SelLCDorHDMI"; }; }; &gpio3 { status = "okay"; }; &elm { status = "okay"; }; &gpmc { status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ pinctrl-names = "default", "sleep"; pinctrl-0 = <&nand_flash_x8_default>; pinctrl-1 = <&nand_flash_x8_sleep>; ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-xfer-type = "prefetch-dma"; ti,nand-ecc-opt = "bch16"; ti,elm-id = <&elm>; nand-bus-width = <8>; gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ gpmc,cs-wr-off-ns = <40>; gpmc,adv-on-ns = <0>; /* cs-on-ns */ gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ gpmc,we-on-ns = <0>; /* cs-on-ns */ gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ gpmc,access-ns = <30>; /* tCEA + 4*/ gpmc,rd-cycle-ns = <40>; gpmc,wr-cycle-ns = <40>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ /* All SPL-* partitions are sized to minimal length * which can be independently programmable. For * NAND flash this is equal to size of erase-block */ #address-cells = <1>; #size-cells = <1>; partition@0 { label = "NAND.SPL"; reg = <0x00000000 0x00040000>; }; partition@1 { label = "NAND.SPL.backup1"; reg = <0x00040000 0x00040000>; }; partition@2 { label = "NAND.SPL.backup2"; reg = <0x00080000 0x00040000>; }; partition@3 { label = "NAND.SPL.backup3"; reg = <0x000C0000 0x00040000>; }; partition@4 { label = "NAND.u-boot-spl-os"; reg = <0x00100000 0x00080000>; }; partition@5 { label = "NAND.u-boot"; reg = <0x00180000 0x00100000>; }; partition@6 { label = "NAND.u-boot-env"; reg = <0x00280000 0x00040000>; }; partition@7 { label = "NAND.u-boot-env.backup1"; reg = <0x002C0000 0x00040000>; }; partition@8 { label = "NAND.kernel"; reg = <0x00300000 0x00700000>; }; partition@9 { label = "NAND.file-system"; reg = <0x00a00000 0x1f600000>; }; }; }; &epwmss0 { status = "okay"; }; &tscadc { status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; &ecap0 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&ecap0_pins_default>; pinctrl-1 = <&ecap0_pins_sleep>; }; &spi0 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi0_pins_default>; pinctrl-1 = <&spi0_pins_sleep>; - ti,pindir-d0-out-d1-in = <1>; }; &spi1 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi1_pins_default>; pinctrl-1 = <&spi1_pins_sleep>; - ti,pindir-d0-out-d1-in = <1>; }; &usb2_phy1 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb2_phy1_default>; pinctrl-1 = <&usb2_phy1_sleep>; }; &usb1 { dr_mode = "otg"; status = "okay"; }; &usb2_phy2 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb2_phy2_default>; pinctrl-1 = <&usb2_phy2_sleep>; }; &usb2 { dr_mode = "host"; status = "okay"; }; &qspi { status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qspi1_pins_default>; pinctrl-1 = <&qspi1_pins_sleep>; spi-max-frequency = <48000000>; m25p80@0 { compatible = "mx66l51235l"; spi-max-frequency = <48000000>; reg = <0>; spi-cpol; spi-cpha; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <1>; /* MTD partition table. * The ROM checks the first 512KiB * for a valid file to boot(XIP). */ partition@0 { label = "QSPI.U_BOOT"; reg = <0x00000000 0x000080000>; }; partition@1 { label = "QSPI.U_BOOT.backup"; reg = <0x00080000 0x00080000>; }; partition@2 { label = "QSPI.U-BOOT-SPL_OS"; reg = <0x00100000 0x00010000>; }; partition@3 { label = "QSPI.U_BOOT_ENV"; reg = <0x00110000 0x00010000>; }; partition@4 { label = "QSPI.U-BOOT-ENV.backup"; reg = <0x00120000 0x00010000>; }; partition@5 { label = "QSPI.KERNEL"; reg = <0x00130000 0x0800000>; }; partition@6 { label = "QSPI.FILESYSTEM"; reg = <0x00930000 0x36D0000>; }; }; }; &hdq { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&hdq_pins>; }; &dss { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&dss_pins>; port { dpi_out: endpoint { remote-endpoint = <&lcd_in>; data-lines = <24>; }; }; }; &vpfe1 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&vpfe1_pins_default>; pinctrl-1 = <&vpfe1_pins_sleep>; port { vpfe1_ep: endpoint { - remote-endpoint = <&ov2659_1>; + /* remote-endpoint = <&sensor>; add once we have it */ ti,am437x-vpfe-interface = <0>; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; }; }; }; &uart0 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart0_pins_default>; pinctrl-1 = <&uart0_pins_sleep>; }; &mcasp1 { #sound-dai-cells = <0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&mcasp1_pins>; pinctrl-1 = <&mcasp1_sleep_pins>; status = "okay"; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; /* 4 serializer */ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1 2 0 0 >; tx-num-evt = <32>; rx-num-evt = <32>; }; &mux_synctimer32k_ck { assigned-clocks = <&mux_synctimer32k_ck>; assigned-clock-parents = <&clkdiv32k_ick>; }; &cpu { cpu0-supply = <&dcdc2>; }; diff --git a/sys/gnu/dts/arm/am43xx-clocks.dtsi b/sys/gnu/dts/arm/am43xx-clocks.dtsi index c726cd8dbdf1..091356f2a8c1 100644 --- a/sys/gnu/dts/arm/am43xx-clocks.dtsi +++ b/sys/gnu/dts/arm/am43xx-clocks.dtsi @@ -1,883 +1,829 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for AM43xx clock data * * Copyright (C) 2013 Texas Instruments, Inc. */ &scm_clocks { sys_clkin_ck: sys_clkin_ck@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; ti,bit-shift = <31>; reg = <0x0040>; }; crystal_freq_sel_ck: crystal_freq_sel_ck@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; ti,bit-shift = <29>; reg = <0x0040>; }; sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; ti,bit-shift = <22>; reg = <0x0040>; }; adc_tsc_fck: adc_tsc_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; dcan0_fck: dcan0_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; dcan1_fck: dcan1_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; mcasp0_fck: mcasp0_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; mcasp1_fck: mcasp1_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; smartreflex0_fck: smartreflex0_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; smartreflex1_fck: smartreflex1_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; sha0_fck: sha0_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; aes0_fck: aes0_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; rng_fck: rng_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; ehrpwm0_tbclk: ehrpwm0_tbclk@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>; ti,bit-shift = <0>; reg = <0x0664>; }; ehrpwm1_tbclk: ehrpwm1_tbclk@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>; ti,bit-shift = <1>; reg = <0x0664>; }; ehrpwm2_tbclk: ehrpwm2_tbclk@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>; ti,bit-shift = <2>; reg = <0x0664>; }; ehrpwm3_tbclk: ehrpwm3_tbclk@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>; ti,bit-shift = <4>; reg = <0x0664>; }; ehrpwm4_tbclk: ehrpwm4_tbclk@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>; ti,bit-shift = <5>; reg = <0x0664>; }; ehrpwm5_tbclk: ehrpwm5_tbclk@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>; ti,bit-shift = <6>; reg = <0x0664>; }; }; &prcm_clocks { clk_32768_ck: clk_32768_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; clk_rc32k_ck: clk_rc32k_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; virt_19200000_ck: virt_19200000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <19200000>; }; virt_24000000_ck: virt_24000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; }; virt_25000000_ck: virt_25000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <25000000>; }; virt_26000000_ck: virt_26000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <26000000>; }; tclkin_ck: tclkin_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <26000000>; }; dpll_core_ck: dpll_core_ck@2d20 { #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2d20>, <0x2d24>, <0x2d2c>; }; dpll_core_x2_ck: dpll_core_x2_ck { #clock-cells = <0>; compatible = "ti,am3-dpll-x2-clock"; clocks = <&dpll_core_ck>; }; dpll_core_m4_ck: dpll_core_m4_ck@2d38 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x2d38>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_core_m5_ck: dpll_core_m5_ck@2d3c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x2d3c>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_core_m6_ck: dpll_core_m6_ck@2d40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x2d40>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_mpu_ck: dpll_mpu_ck@2d60 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2d60>, <0x2d64>, <0x2d6c>; }; dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x2d70>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; mpu_periphclk: mpu_periphclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_mpu_m2_ck>; clock-mult = <1>; clock-div = <2>; }; dpll_ddr_ck: dpll_ddr_ck@2da0 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2da0>, <0x2da4>, <0x2dac>; }; dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x2db0>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_disp_ck: dpll_disp_ck@2e20 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2e20>, <0x2e24>, <0x2e2c>; }; dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_disp_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x2e30>; ti,index-starts-at-one; ti,invert-autoidle-bit; ti,set-rate-parent; }; dpll_per_ck: dpll_per_ck@2de0 { #clock-cells = <0>; compatible = "ti,am3-dpll-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2de0>, <0x2de4>, <0x2dec>; }; dpll_per_m2_ck: dpll_per_m2_ck@2df0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; reg = <0x2df0>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; clk_24mhz: clk_24mhz { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <8>; }; clkdiv32k_ck: clkdiv32k_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&clk_24mhz>; clock-mult = <1>; clock-div = <732>; }; clkdiv32k_ick: clkdiv32k_ick@2a38 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ck>; ti,bit-shift = <8>; reg = <0x2a38>; }; sysclk_div: sysclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; pruss_ocp_gclk: pruss_ocp_gclk@4248 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; reg = <0x4248>; }; clk_32k_tpm_ck: clk_32k_tpm_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; timer1_fck: timer1_fck@4200 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; reg = <0x4200>; }; timer2_fck: timer2_fck@4204 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4204>; }; timer3_fck: timer3_fck@4208 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4208>; }; timer4_fck: timer4_fck@420c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x420c>; }; timer5_fck: timer5_fck@4210 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4210>; }; timer6_fck: timer6_fck@4214 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4214>; }; timer7_fck: timer7_fck@4218 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4218>; }; wdt1_fck: wdt1_fck@422c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; reg = <0x422c>; }; l3_gclk: l3_gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sysclk_div>; clock-mult = <1>; clock-div = <2>; }; l4hs_gclk: l4hs_gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; l3s_gclk: l3s_gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m4_div2_ck>; clock-mult = <1>; clock-div = <1>; }; l4ls_gclk: l4ls_gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m4_div2_ck>; clock-mult = <1>; clock-div = <1>; }; cpsw_125mhz_gclk: cpsw_125mhz_gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m5_ck>; clock-mult = <1>; clock-div = <2>; }; cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; reg = <0x4238>; }; dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_m5_ck>; reg = <0x4234>; ti,bit-shift = <2>; ti,dividers = <2>, <5>; }; clk_32k_mosc_ck: clk_32k_mosc_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; reg = <0x4240>; }; mmc_clk: mmc_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <2>; }; gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sysclk_div>, <&dpll_per_m2_ck>; ti,bit-shift = <1>; reg = <0x423c>; }; gfx_fck_div_ck: gfx_fck_div_ck@423c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&gfx_fclk_clksel_ck>; reg = <0x423c>; ti,max-div = <2>; }; disp_clk: disp_clk@4244 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; reg = <0x4244>; ti,set-rate-parent; }; dpll_extdev_ck: dpll_extdev_ck@2e60 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2e60>, <0x2e64>, <0x2e6c>; }; dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_extdev_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; reg = <0x2e70>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; mux_synctimer32k_ck: mux_synctimer32k_ck@4230 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; reg = <0x4230>; }; timer8_fck: timer8_fck@421c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x421c>; }; timer9_fck: timer9_fck@4220 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x4220>; }; timer10_fck: timer10_fck@4224 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x4224>; }; timer11_fck: timer11_fck@4228 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x4228>; }; cpsw_50m_clkdiv: cpsw_50m_clkdiv { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m5_ck>; clock-mult = <1>; clock-div = <1>; }; cpsw_5m_clkdiv: cpsw_5m_clkdiv { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&cpsw_50m_clkdiv>; clock-mult = <1>; clock-div = <10>; }; dpll_ddr_x2_ck: dpll_ddr_x2_ck { #clock-cells = <0>; compatible = "ti,am3-dpll-x2-clock"; clocks = <&dpll_ddr_ck>; }; dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x2db8>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; clocks = <&dpll_per_ck>; ti,clock-mult = <1>; ti,clock-div = <1>; ti,autoidle-shift = <8>; reg = <0x2e14>; ti,invert-autoidle-bit; }; dll_aging_clk_div: dll_aging_clk_div@4250 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin_ck>; reg = <0x4250>; ti,dividers = <8>, <16>, <32>; }; div_core_25m_ck: div_core_25m_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sysclk_div>; clock-mult = <1>; clock-div = <8>; }; func_12m_clk: func_12m_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <16>; }; vtp_clk_div: vtp_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <2>; }; usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; reg = <0x4260>; }; usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&usbphy_32khz_clkmux>; ti,bit-shift = <8>; reg = <0x2a40>; }; usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&usbphy_32khz_clkmux>; ti,bit-shift = <8>; reg = <0x2a48>; }; - - clkout1_osc_div_ck: clkout1-osc-div-ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin_ck>; - ti,bit-shift = <20>; - ti,max-div = <4>; - reg = <0x4100>; - }; - - clkout1_src2_mux_ck: clkout1-src2-mux-ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, - <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, - <&dpll_mpu_m2_ck>; - reg = <0x4100>; - }; - - clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout1_src2_mux_ck>; - ti,bit-shift = <4>; - ti,max-div = <8>; - reg = <0x4100>; - }; - - clkout1_src2_post_div_ck: clkout1-src2-post-div-ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout1_src2_pre_div_ck>; - ti,bit-shift = <8>; - ti,max-div = <32>; - ti,index-power-of-two; - reg = <0x4100>; - }; - - clkout1_mux_ck: clkout1-mux-ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, - <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; - ti,bit-shift = <16>; - reg = <0x4100>; - }; - - clkout1_ck: clkout1-ck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkout1_mux_ck>; - ti,bit-shift = <23>; - reg = <0x4100>; - }; }; &prcm { wkup_cm: wkup-cm@2800 { compatible = "ti,omap4-cm"; reg = <0x2800 0x400>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x2800 0x400>; l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 { compatible = "ti,clkctrl"; reg = <0x120 0x4>; #clock-cells = <2>; }; l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 { compatible = "ti,clkctrl"; reg = <0x228 0xc>; #clock-cells = <2>; }; l4_wkup_clkctrl: l4-wkup-clkctrl@220 { compatible = "ti,clkctrl"; reg = <0x220 0x4>, <0x328 0x44>; #clock-cells = <2>; }; }; mpu_cm: mpu-cm@8300 { compatible = "ti,omap4-cm"; reg = <0x8300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8300 0x100>; mpu_clkctrl: mpu-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; gfx_l3_cm: gfx-l3-cm@8400 { compatible = "ti,omap4-cm"; reg = <0x8400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8400 0x100>; gfx_l3_clkctrl: gfx-l3-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; l4_rtc_cm: l4-rtc-cm@8500 { compatible = "ti,omap4-cm"; reg = <0x8500 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8500 0x100>; l4_rtc_clkctrl: l4-rtc-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; per_cm: per-cm@8800 { compatible = "ti,omap4-cm"; reg = <0x8800 0xc00>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8800 0xc00>; l3_clkctrl: l3-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x3c>, <0x78 0x2c>; #clock-cells = <2>; }; l3s_clkctrl: l3s-clkctrl@68 { compatible = "ti,clkctrl"; reg = <0x68 0xc>, <0x220 0x4c>; #clock-cells = <2>; }; pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 { compatible = "ti,clkctrl"; reg = <0x320 0x4>; #clock-cells = <2>; }; l4ls_clkctrl: l4ls-clkctrl@420 { compatible = "ti,clkctrl"; reg = <0x420 0x1a4>; #clock-cells = <2>; }; emif_clkctrl: emif-clkctrl@720 { compatible = "ti,clkctrl"; reg = <0x720 0x4>; #clock-cells = <2>; }; dss_clkctrl: dss-clkctrl@a20 { compatible = "ti,clkctrl"; reg = <0xa20 0x4>; #clock-cells = <2>; }; cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 { compatible = "ti,clkctrl"; reg = <0xb20 0x4>; #clock-cells = <2>; }; }; }; diff --git a/sys/gnu/dts/arm/am571x-idk.dts b/sys/gnu/dts/arm/am571x-idk.dts index 669559c9c95b..0aaacea1d887 100644 --- a/sys/gnu/dts/arm/am571x-idk.dts +++ b/sys/gnu/dts/arm/am571x-idk.dts @@ -1,211 +1,188 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; #include "am5718.dtsi" #include #include #include "dra7-mmc-iodelay.dtsi" #include "dra72x-mmc-iodelay.dtsi" #include "am57xx-idk-common.dtsi" / { model = "TI AM5718 IDK"; compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7"; memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; }; leds { compatible = "gpio-leds"; cpu0-led { label = "status0:red:cpu0"; gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "cpu0"; }; usr0-led { label = "status0:green:usr"; gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; default-state = "off"; }; heartbeat-led { label = "status0:blue:heartbeat"; gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "heartbeat"; }; usr1-led { label = "status1:red:usr"; gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; default-state = "off"; }; usr2-led { label = "status1:green:usr"; gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; default-state = "off"; }; mmc0-led { label = "status1:blue:mmc0"; gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "mmc0"; }; }; idk-leds { status = "disabled"; compatible = "gpio-leds"; red0-led { label = "idk:red0"; gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; default-state = "off"; }; green0-led { label = "idk:green0"; gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; blue0-led { label = "idk:blue0"; gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; default-state = "off"; }; red1-led { label = "idk:red1"; gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; default-state = "off"; }; green1-led { label = "idk:green1"; gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; default-state = "off"; }; blue1-led { label = "idk:blue1"; gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; default-state = "off"; }; red2-led { label = "idk:red2"; gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; default-state = "off"; }; green2-led { label = "idk:green2"; gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; default-state = "off"; }; blue2-led { label = "idk:blue2"; gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; default-state = "off"; }; red3-led { label = "idk:red3"; gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; default-state = "off"; }; green3-led { label = "idk:green3"; gpios = <&gpio7 25 GPIO_ACTIVE_HIGH>; default-state = "off"; }; blue3-led { label = "idk:blue3"; gpios = <&gpio7 24 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; }; &extcon_usb2 { id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>; }; &sn65hvs882 { load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; }; &mailbox5 { status = "okay"; mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { status = "okay"; }; mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { status = "okay"; }; }; &pcie1_rc { status = "okay"; - gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; +}; + +&pcie1_ep { + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; }; &mmc1 { pinctrl-names = "default", "hs"; pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; pinctrl-1 = <&mmc1_pins_hs>; }; &mmc2 { pinctrl-names = "default", "hs", "ddr_3_3v"; pinctrl-0 = <&mmc2_pins_default>; pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; }; - -&mac_sw { - pinctrl-names = "default", "sleep"; - status = "okay"; -}; - -&cpsw_port1 { - phy-handle = <ðphy0_sw>; - phy-mode = "rgmii"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <ðphy1_sw>; - phy-mode = "rgmii"; - ti,dual-emac-pvid = <2>; -}; - -&davinci_mdio_sw { - ethphy0_sw: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1_sw: ethernet-phy@1 { - reg = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/am572x-idk-common.dtsi b/sys/gnu/dts/arm/am572x-idk-common.dtsi index ddf123620e96..a064f13b3880 100644 --- a/sys/gnu/dts/arm/am572x-idk-common.dtsi +++ b/sys/gnu/dts/arm/am572x-idk-common.dtsi @@ -1,168 +1,172 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ */ #include #include #include "am57xx-idk-common.dtsi" / { memory@0 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x80000000>; }; status-leds { compatible = "gpio-leds"; cpu0-led { label = "status0:red:cpu0"; gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "cpu0"; }; usr0-led { label = "status0:green:usr"; gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; default-state = "off"; }; heartbeat-led { label = "status0:blue:heartbeat"; gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "heartbeat"; }; cpu1-led { label = "status1:red:cpu1"; gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "cpu1"; }; usr1-led { label = "status1:green:usr"; gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>; default-state = "off"; }; mmc0-led { label = "status1:blue:mmc0"; gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "mmc0"; }; }; idk-leds { status = "disabled"; compatible = "gpio-leds"; red0-led { label = "idk:red0"; gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; default-state = "off"; }; green0-led { label = "idk:green0"; gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; default-state = "off"; }; blue0-led { label = "idk:blue0"; gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; default-state = "off"; }; red1-led { label = "idk:red1"; gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; default-state = "off"; }; green1-led { label = "idk:green1"; gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; default-state = "off"; }; blue1-led { label = "idk:blue1"; gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; default-state = "off"; }; red2-led { label = "idk:red2"; gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; default-state = "off"; }; green2-led { label = "idk:green2"; gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; default-state = "off"; }; blue2-led { label = "idk:blue2"; gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; default-state = "off"; }; red3-led { label = "idk:red3"; gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; default-state = "off"; }; green3-led { label = "idk:green3"; gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; default-state = "off"; }; blue3-led { label = "idk:blue3"; gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; }; &extcon_usb2 { id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; }; &sn65hvs882 { load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; }; &pcie1_rc { status = "okay"; gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; }; +&pcie1_ep { + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; +}; + &mailbox5 { status = "okay"; mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { status = "okay"; }; mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { status = "okay"; }; mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { status = "okay"; }; }; diff --git a/sys/gnu/dts/arm/am572x-idk.dts b/sys/gnu/dts/arm/am572x-idk.dts index c3d966904d64..ea1c119feaa5 100644 --- a/sys/gnu/dts/arm/am572x-idk.dts +++ b/sys/gnu/dts/arm/am572x-idk.dts @@ -1,34 +1,29 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; #include "am5728.dtsi" #include "dra7-mmc-iodelay.dtsi" #include "dra74x-mmc-iodelay.dtsi" #include "am572x-idk-common.dtsi" / { model = "TI AM5728 IDK"; compatible = "ti,am5728-idk", "ti,am5728", "ti,dra7"; }; &mmc1 { pinctrl-names = "default", "hs"; pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; pinctrl-1 = <&mmc1_pins_hs>; }; &mmc2 { pinctrl-names = "default", "hs", "ddr_3_3v"; pinctrl-0 = <&mmc2_pins_default>; pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_rev20>; }; - -&mac { - status = "okay"; - dual_emac; -}; diff --git a/sys/gnu/dts/arm/am574x-idk.dts b/sys/gnu/dts/arm/am574x-idk.dts index fa0088025b2c..7935d70874ce 100644 --- a/sys/gnu/dts/arm/am574x-idk.dts +++ b/sys/gnu/dts/arm/am574x-idk.dts @@ -1,42 +1,37 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; #include "am5748.dtsi" #include "dra7-mmc-iodelay.dtsi" #include "dra76x-mmc-iodelay.dtsi" #include "am572x-idk-common.dtsi" / { model = "TI AM5748 IDK"; compatible = "ti,am5748-idk", "ti,am5748", "ti,dra762", "ti,dra7"; }; &qspi { spi-max-frequency = <96000000>; m25p80@0 { spi-max-frequency = <96000000>; }; }; &mmc1 { pinctrl-names = "default", "hs"; pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; pinctrl-1 = <&mmc1_pins_hs>; }; &mmc2 { pinctrl-names = "default", "hs", "ddr_3_3v"; pinctrl-0 = <&mmc2_pins_default>; pinctrl-1 = <&mmc2_pins_default>; pinctrl-2 = <&mmc2_pins_default>; }; - -&mac { - status = "okay"; - dual_emac; -}; diff --git a/sys/gnu/dts/arm/am57xx-beagle-x15-common.dtsi b/sys/gnu/dts/arm/am57xx-beagle-x15-common.dtsi index a813a0cf3ff3..bc76f1705c0f 100644 --- a/sys/gnu/dts/arm/am57xx-beagle-x15-common.dtsi +++ b/sys/gnu/dts/arm/am57xx-beagle-x15-common.dtsi @@ -1,605 +1,588 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; #include "am5728.dtsi" #include "am57xx-commercial-grade.dtsi" #include "dra74x-mmc-iodelay.dtsi" #include #include / { compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; aliases { rtc0 = &mcp_rtc; rtc1 = &tps659038_rtc; rtc2 = &rtc; display0 = &hdmi0; }; chosen { stdout-path = &uart3; }; memory@0 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x80000000>; }; - main_12v0: fixedregulator-main_12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "main_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - evm_5v0: fixedregulator-evm_5v0 { - /* Output of TPS54531D */ - compatible = "regulator-fixed"; - regulator-name = "evm_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&main_12v0>; - regulator-always-on; - regulator-boot-on; - }; - vdd_3v3: fixedregulator-vdd_3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; vin-supply = <®en1>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; aic_dvdd: fixedregulator-aic_dvdd { compatible = "regulator-fixed"; regulator-name = "aic_dvdd_fixed"; vin-supply = <&vdd_3v3>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; vtt_fixed: fixedregulator-vtt { /* TPS51200 */ compatible = "regulator-fixed"; regulator-name = "vtt_fixed"; vin-supply = <&smps3_reg>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; enable-active-high; gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; }; leds { compatible = "gpio-leds"; led0 { label = "beagle-x15:usr0"; gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; led1 { label = "beagle-x15:usr1"; gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "cpu0"; default-state = "off"; }; led2 { label = "beagle-x15:usr2"; gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; led3 { label = "beagle-x15:usr3"; gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; linux,default-trigger = "disk-activity"; default-state = "off"; }; }; gpio_fan: gpio_fan { /* Based on 5v 500mA AFB02505HHB */ compatible = "gpio-fan"; gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; gpio-fan,speed-map = <0 0>, <13000 1>; #cooling-cells = <2>; }; hdmi0: connector { compatible = "hdmi-connector"; label = "hdmi"; type = "a"; port { hdmi_connector_in: endpoint { remote-endpoint = <&tpd12s015_out>; }; }; }; tpd12s015: encoder { compatible = "ti,tpd12s015"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; tpd12s015_in: endpoint { remote-endpoint = <&hdmi_out>; }; }; port@1 { reg = <1>; tpd12s015_out: endpoint { remote-endpoint = <&hdmi_connector_in>; }; }; }; }; sound0: sound0 { compatible = "simple-audio-card"; simple-audio-card,name = "BeagleBoard-X15"; simple-audio-card,widgets = "Line", "Line Out", "Line", "Line In"; simple-audio-card,routing = "Line Out", "LLOUT", "Line Out", "RLOUT", "MIC2L", "Line In", "MIC2R", "Line In"; simple-audio-card,format = "dsp_b"; simple-audio-card,bitclock-master = <&sound0_master>; simple-audio-card,frame-master = <&sound0_master>; simple-audio-card,bitclock-inversion; simple-audio-card,cpu { sound-dai = <&mcasp3>; }; sound0_master: simple-audio-card,codec { sound-dai = <&tlv320aic3104>; clocks = <&clkout2_clk>; }; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; tps659038: tps659038@58 { compatible = "ti,tps659038"; reg = <0x58>; interrupt-parent = <&gpio1>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; #interrupt-cells = <2>; interrupt-controller; ti,system-power-controller; ti,palmas-override-powerhold; tps659038_pmic { compatible = "ti,tps659038-pmic"; regulators { smps12_reg: smps12 { /* VDD_MPU */ regulator-name = "smps12"; regulator-min-microvolt = < 850000>; regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; smps3_reg: smps3 { /* VDD_DDR */ regulator-name = "smps3"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-boot-on; }; smps45_reg: smps45 { /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ regulator-name = "smps45"; regulator-min-microvolt = < 850000>; regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; smps6_reg: smps6 { /* VDD_CORE */ regulator-name = "smps6"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1150000>; regulator-always-on; regulator-boot-on; }; /* SMPS7 unused */ smps8_reg: smps8 { /* VDD_1V8 */ regulator-name = "smps8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; /* SMPS9 unused */ ldo1_reg: ldo1 { /* VDD_SD / VDDSHV8 */ regulator-name = "ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; ldo2_reg: ldo2 { /* VDD_SHV5 */ regulator-name = "ldo2"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; ldo3_reg: ldo3 { /* VDDA_1V8_PHYA */ regulator-name = "ldo3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; ldo4_reg: ldo4 { /* VDDA_1V8_PHYB */ regulator-name = "ldo4"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; ldo9_reg: ldo9 { /* VDD_RTC */ regulator-name = "ldo9"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; regulator-always-on; regulator-boot-on; }; ldoln_reg: ldoln { /* VDDA_1V8_PLL */ regulator-name = "ldoln"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; ldousb_reg: ldousb { /* VDDA_3V_USB: VDDA_USBHS33 */ regulator-name = "ldousb"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; }; regen1: regen1 { /* VDD_3V3_ON */ regulator-name = "regen1"; regulator-boot-on; regulator-always-on; }; }; }; tps659038_rtc: tps659038_rtc { compatible = "ti,palmas-rtc"; interrupt-parent = <&tps659038>; interrupts = <8 IRQ_TYPE_EDGE_FALLING>; wakeup-source; }; tps659038_pwr_button: tps659038_pwr_button { compatible = "ti,palmas-pwrbutton"; interrupt-parent = <&tps659038>; interrupts = <1 IRQ_TYPE_EDGE_FALLING>; wakeup-source; ti,palmas-long-press-seconds = <12>; }; tps659038_gpio: tps659038_gpio { compatible = "ti,palmas-gpio"; gpio-controller; #gpio-cells = <2>; }; extcon_usb2: tps659038_usb { compatible = "ti,palmas-usb-vid"; ti,enable-vbus-detection; vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; }; }; tmp102: tmp102@48 { compatible = "ti,tmp102"; reg = <0x48>; interrupt-parent = <&gpio7>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>; #thermal-sensor-cells = <1>; }; tlv320aic3104: tlv320aic3104@18 { #sound-dai-cells = <0>; compatible = "ti,tlv320aic3104"; reg = <0x18>; assigned-clocks = <&clkoutmux2_clk_mux>; assigned-clock-parents = <&sys_clk2_dclk_div>; status = "okay"; adc-settle-ms = <40>; AVDD-supply = <&vdd_3v3>; IOVDD-supply = <&vdd_3v3>; DRVDD-supply = <&vdd_3v3>; DVDD-supply = <&aic_dvdd>; }; eeprom: eeprom@50 { compatible = "atmel,24c32"; reg = <0x50>; }; }; &i2c3 { status = "okay"; clock-frequency = <400000>; mcp_rtc: rtc@6f { compatible = "microchip,mcp7941x"; reg = <0x6f>; interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>, <&dra7_pmx_core 0x424>; interrupt-names = "irq", "wakeup"; vcc-supply = <&vdd_3v3>; wakeup-source; }; }; &gpio7_target { ti,no-reset-on-init; ti,no-idle-on-init; }; &cpu0 { vdd-supply = <&smps12_reg>; voltage-tolerance = <1>; }; &uart3 { status = "okay"; interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, <&dra7_pmx_core 0x3f8>; }; &davinci_mdio { phy0: ethernet-phy@1 { reg = <1>; }; phy1: ethernet-phy@2 { reg = <2>; }; }; &mac { status = "okay"; dual_emac; }; &cpsw_emac0 { phy-handle = <&phy0>; phy-mode = "rgmii"; dual_emac_res_vlan = <1>; }; &cpsw_emac1 { phy-handle = <&phy1>; phy-mode = "rgmii"; dual_emac_res_vlan = <2>; }; &mmc1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_default>; bus-width = <4>; cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ no-1-8-v; }; &mmc2 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins_default>; vmmc-supply = <&vdd_3v3>; vqmmc-supply = <&vdd_3v3>; bus-width = <8>; non-removable; no-1-8-v; }; &sata { status = "okay"; }; &usb2_phy1 { phy-supply = <&ldousb_reg>; }; &usb2_phy2 { phy-supply = <&ldousb_reg>; }; &usb1 { dr_mode = "host"; }; &omap_dwc3_2 { extcon = <&extcon_usb2>; }; &usb2 { /* * Stand alone usage is peripheral only. * However, with some resistor modifications * this port can be used via expansion connectors * as "host" or "dual-role". If so, provide * the necessary dr_mode override in the expansion * board's DT. */ dr_mode = "peripheral"; }; &cpu_trips { cpu_alert1: cpu_alert1 { temperature = <50000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "active"; }; }; &cpu_cooling_maps { map1 { trip = <&cpu_alert1>; cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; &thermal_zones { board_thermal: board_thermal { polling-delay-passive = <1250>; /* milliseconds */ polling-delay = <1500>; /* milliseconds */ /* sensor ID */ thermal-sensors = <&tmp102 0>; board_trips: trips { board_alert0: board_alert { temperature = <40000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "active"; }; board_crit: board_crit { temperature = <105000>; /* millicelsius */ hysteresis = <0>; /* millicelsius */ type = "critical"; }; }; board_cooling_maps: cooling-maps { map0 { trip = <&board_alert0>; cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; &dss { status = "ok"; vdda_video-supply = <&ldoln_reg>; }; &hdmi { status = "ok"; vdda-supply = <&ldo4_reg>; port { hdmi_out: endpoint { remote-endpoint = <&tpd12s015_in>; }; }; }; &pcie1_rc { status = "ok"; gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; }; +&pcie1_ep { + gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; +}; + &mcasp3 { #sound-dai-cells = <0>; assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; assigned-clock-parents = <&sys_clkin2>; status = "okay"; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; /* 4 serializers */ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1 2 0 0 >; tx-num-evt = <32>; rx-num-evt = <32>; }; &mailbox5 { status = "okay"; mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { status = "okay"; }; mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { status = "okay"; }; mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { status = "okay"; }; }; diff --git a/sys/gnu/dts/arm/am57xx-beagle-x15-revb1.dts b/sys/gnu/dts/arm/am57xx-beagle-x15-revb1.dts index 39d1c4ff5749..7b113b52c3fb 100644 --- a/sys/gnu/dts/arm/am57xx-beagle-x15-revb1.dts +++ b/sys/gnu/dts/arm/am57xx-beagle-x15-revb1.dts @@ -1,36 +1,36 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ */ #include "am57xx-beagle-x15-common.dtsi" / { model = "TI AM5728 BeagleBoard-X15 rev B1"; }; &tpd12s015 { gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ }; &mmc1 { pinctrl-names = "default", "hs"; pinctrl-0 = <&mmc1_pins_default>; pinctrl-1 = <&mmc1_pins_hs>; vmmc-supply = <&vdd_3v3>; vqmmc-supply = <&ldo1_reg>; }; &mmc2 { - pinctrl-names = "default", "hs", "ddr_3_3v"; + pinctrl-names = "default", "hs", "ddr_1_8v"; pinctrl-0 = <&mmc2_pins_default>; pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>; }; /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */ &phy1 { max-speed = <100>; }; diff --git a/sys/gnu/dts/arm/am57xx-beagle-x15-revc.dts b/sys/gnu/dts/arm/am57xx-beagle-x15-revc.dts index 4187a9729f96..30c500b15b21 100644 --- a/sys/gnu/dts/arm/am57xx-beagle-x15-revc.dts +++ b/sys/gnu/dts/arm/am57xx-beagle-x15-revc.dts @@ -1,31 +1,31 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ */ #include "am57xx-beagle-x15-common.dtsi" / { model = "TI AM5728 BeagleBoard-X15 rev C"; }; &tpd12s015 { gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ }; &mmc1 { pinctrl-names = "default", "hs"; pinctrl-0 = <&mmc1_pins_default>; pinctrl-1 = <&mmc1_pins_hs>; vmmc-supply = <&vdd_3v3>; vqmmc-supply = <&ldo1_reg>; }; &mmc2 { - pinctrl-names = "default", "hs", "ddr_3_3v"; + pinctrl-names = "default", "hs", "ddr_1_8v"; pinctrl-0 = <&mmc2_pins_default>; pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_rev20>; }; diff --git a/sys/gnu/dts/arm/am57xx-idk-common.dtsi b/sys/gnu/dts/arm/am57xx-idk-common.dtsi index aa5e55f98179..423855a2a2d6 100644 --- a/sys/gnu/dts/arm/am57xx-idk-common.dtsi +++ b/sys/gnu/dts/arm/am57xx-idk-common.dtsi @@ -1,546 +1,492 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ */ #include "am57xx-industrial-grade.dtsi" / { aliases { rtc0 = &tps659038_rtc; rtc1 = &rtc; - display0 = &hdmi0; }; chosen { stdout-path = &uart3; }; vmain: fixedregulator-vmain { compatible = "regulator-fixed"; regulator-name = "VMAIN"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; regulator-boot-on; }; v3_3d: fixedregulator-v3_3d { compatible = "regulator-fixed"; regulator-name = "V3_3D"; vin-supply = <&smps9_reg>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; vtt_fixed: fixedregulator-vtt { /* TPS51200 */ compatible = "regulator-fixed"; regulator-name = "vtt_fixed"; vin-supply = <&v3_3d>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; leds-iio { status = "disabled"; compatible = "gpio-leds"; led-out0 { label = "out0"; gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out1 { label = "out1"; gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out2 { label = "out2"; gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out3 { label = "out3"; gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out4 { label = "out4"; gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out5 { label = "out5"; gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out6 { label = "out6"; gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led-out7 { label = "out7"; gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; - - hdmi0: connector@0 { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - tpd12s015: encoder@0 { - compatible = "ti,tpd12s016", "ti,tpd12s015"; - - gpios = <0>, /* optional CT_CP_HPD */ - <0>, /* optional LS_OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint@0 { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint@0 { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; }; &dra7_pmx_core { dcan1_pins_default: dcan1_pins_default { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ DRA7XX_CORE_IOPAD(0x37d4, PIN_INPUT_PULLUP | MUX_MODE0) /* dcan1_rx */ >; }; dcan1_pins_sleep: dcan1_pins_sleep { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */ >; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; tps659038: tps659038@58 { compatible = "ti,tps659038"; reg = <0x58>; interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_HIGH &dra7_pmx_core 0x418>; #interrupt-cells = <2>; interrupt-controller; ti,system-power-controller; ti,palmas-override-powerhold; tps659038_pmic { compatible = "ti,tps659038-pmic"; smps12-in-supply = <&vmain>; smps3-in-supply = <&vmain>; smps45-in-supply = <&vmain>; smps6-in-supply = <&vmain>; smps7-in-supply = <&vmain>; smps8-in-supply = <&vmain>; smps9-in-supply = <&vmain>; ldo1-in-supply = <&vmain>; ldo2-in-supply = <&vmain>; ldo3-in-supply = <&vmain>; ldo4-in-supply = <&vmain>; ldo9-in-supply = <&vmain>; ldoln-in-supply = <&vmain>; ldousb-in-supply = <&vmain>; ldortc-in-supply = <&vmain>; regulators { smps12_reg: smps12 { /* VDD_MPU */ regulator-name = "smps12"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; smps3_reg: smps3 { /* VDD_DDR EMIF1 EMIF2 */ regulator-name = "smps3"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-boot-on; }; smps45_reg: smps45 { /* VDD_DSPEVE on AM572 */ /* VDD_IVA + VDD_DSP on AM571 */ regulator-name = "smps45"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; smps6_reg: smps6 { /* VDD_GPU */ regulator-name = "smps6"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; smps7_reg: smps7 { /* VDD_CORE */ regulator-name = "smps7"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1150000>; regulator-always-on; regulator-boot-on; }; smps8_reg: smps8 { /* 5728 - VDD_IVAHD */ /* 5718 - N.C. test point */ regulator-name = "smps8"; }; smps9_reg: smps9 { /* VDD_3_3D */ regulator-name = "smps9"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; ldo1_reg: ldo1 { /* VDDSHV8 - VSDMMC */ /* NOTE: on rev 1.3a, data supply */ regulator-name = "ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; ldo2_reg: ldo2 { /* VDDSH18V */ regulator-name = "ldo2"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; ldo3_reg: ldo3 { /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ regulator-name = "ldo3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; ldo4_reg: ldo4 { /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/ regulator-name = "ldo4"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; /* LDO5-8 unused */ ldo9_reg: ldo9 { /* VDD_RTC */ regulator-name = "ldo9"; regulator-min-microvolt = <840000>; regulator-max-microvolt = <1160000>; regulator-always-on; regulator-boot-on; }; ldoln_reg: ldoln { /* VDDA_1V8_PLL */ regulator-name = "ldoln"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; ldousb_reg: ldousb { /* VDDA_3V_USB: VDDA_USBHS33 */ regulator-name = "ldousb"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; ldortc_reg: ldortc { /* VDDA_RTC */ regulator-name = "ldortc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; regen1: regen1 { /* VDD_3V3_ON */ regulator-name = "regen1"; regulator-boot-on; regulator-always-on; }; regen2: regen2 { /* Needed for PMIC internal resource */ regulator-name = "regen2"; regulator-boot-on; regulator-always-on; }; }; }; tps659038_rtc: tps659038_rtc { compatible = "ti,palmas-rtc"; interrupt-parent = <&tps659038>; interrupts = <8 IRQ_TYPE_EDGE_FALLING>; wakeup-source; }; tps659038_pwr_button: tps659038_pwr_button { compatible = "ti,palmas-pwrbutton"; interrupt-parent = <&tps659038>; interrupts = <1 IRQ_TYPE_EDGE_FALLING>; wakeup-source; ti,palmas-long-press-seconds = <12>; }; tps659038_gpio: tps659038_gpio { compatible = "ti,palmas-gpio"; gpio-controller; #gpio-cells = <2>; }; extcon_usb2: tps659038_usb { compatible = "ti,palmas-usb-vid"; ti,enable-vbus-detection; ti,enable-id-detection; /* ID & VBUS GPIOs provided in board dts */ }; }; tpic2810: tpic2810@60 { compatible = "ti,tpic2810"; reg = <0x60>; gpio-controller; #gpio-cells = <2>; }; }; &mcspi3 { status = "okay"; ti,pindir-d0-out-d1-in; sn65hvs882: sn65hvs882@0 { compatible = "pisosr-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0>; spi-max-frequency = <1000000>; spi-cpol; }; }; &uart3 { status = "okay"; interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH &dra7_pmx_core 0x248>; }; &rtc { status = "okay"; ext-clk-src; }; +&mac { + status = "okay"; + dual_emac; +}; + &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "rgmii"; dual_emac_res_vlan = <1>; }; &cpsw_emac1 { phy-handle = <ðphy1>; phy-mode = "rgmii"; dual_emac_res_vlan = <2>; }; &davinci_mdio { ethphy0: ethernet-phy@0 { reg = <0>; }; ethphy1: ethernet-phy@1 { reg = <1>; }; }; &usb2_phy1 { phy-supply = <&ldousb_reg>; }; &usb2_phy2 { phy-supply = <&ldousb_reg>; }; &usb1 { dr_mode = "host"; }; &omap_dwc3_2 { extcon = <&extcon_usb2>; }; &usb2 { extcon = <&extcon_usb2>; dr_mode = "otg"; }; &mmc1 { status = "okay"; vmmc-supply = <&v3_3d>; vqmmc-supply = <&ldo1_reg>; bus-width = <4>; cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ no-1-8-v; }; &mmc2 { status = "okay"; vmmc-supply = <&v3_3d>; vqmmc-supply = <&v3_3d>; bus-width = <8>; non-removable; max-frequency = <96000000>; no-1-8-v; }; &dcan1 { status = "okay"; pinctrl-names = "default", "sleep", "active"; pinctrl-0 = <&dcan1_pins_sleep>; pinctrl-1 = <&dcan1_pins_sleep>; pinctrl-2 = <&dcan1_pins_default>; }; &qspi { status = "okay"; spi-max-frequency = <76800000>; m25p80@0 { compatible = "s25fl256s1", "jedec,spi-nor"; spi-max-frequency = <76800000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <1>; /* MTD partition table. * The ROM checks the first four physical blocks * for a valid file to boot and the flash here is * 64KiB block size. */ partition@0 { label = "QSPI.SPL"; reg = <0x00000000 0x000040000>; }; partition@1 { label = "QSPI.u-boot"; reg = <0x00040000 0x00100000>; }; partition@2 { label = "QSPI.u-boot-spl-os"; reg = <0x00140000 0x00080000>; }; partition@3 { label = "QSPI.u-boot-env"; reg = <0x001c0000 0x00010000>; }; partition@4 { label = "QSPI.u-boot-env.backup1"; reg = <0x001d0000 0x0010000>; }; partition@5 { label = "QSPI.kernel"; reg = <0x001e0000 0x0800000>; }; partition@6 { label = "QSPI.file-system"; reg = <0x009e0000 0x01620000>; }; }; }; &cpu0 { vdd-supply = <&smps12_reg>; }; - -&hdmi { - status = "okay"; - - vdda-supply = <&ldo4_reg>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; - -&dss { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/dm3725.dtsi b/sys/gnu/dts/arm/dm3725.dtsi index d24e906a14b1..e69de29bb2d1 100644 --- a/sys/gnu/dts/arm/dm3725.dtsi +++ b/sys/gnu/dts/arm/dm3725.dtsi @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2020 André Hentschel - */ - -#include "omap36xx.dtsi" - -&sgx_module { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/dra62x-j5eco-evm.dts b/sys/gnu/dts/arm/dra62x-j5eco-evm.dts index c16e183822be..861ab90a3f3a 100644 --- a/sys/gnu/dts/arm/dra62x-j5eco-evm.dts +++ b/sys/gnu/dts/arm/dra62x-j5eco-evm.dts @@ -1,144 +1,144 @@ // SPDX-License-Identifier: GPL-2.0-only /dts-v1/; #include "dra62x.dtsi" #include / { model = "DRA62x J5 Eco EVM"; compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148", "ti,dm814"; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; /* MIC94060YC6 controlled by SD1_POW pin */ vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; }; &cpsw_emac0 { phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; }; &cpsw_emac1 { phy-handle = <ðphy1>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; }; &davinci_mdio { ethphy0: ethernet-phy@0 { reg = <0>; }; ethphy1: ethernet-phy@1 { reg = <1>; }; }; &gpmc { ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ linux,mtd-name= "micron,mt29f2g16aadwp"; #address-cells = <1>; #size-cells = <1>; ti,nand-ecc-opt = "bch8"; nand-bus-width = <16>; gpmc,device-width = <2>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <44>; gpmc,cs-wr-off-ns = <44>; gpmc,adv-on-ns = <6>; gpmc,adv-rd-off-ns = <34>; gpmc,adv-wr-off-ns = <44>; gpmc,we-on-ns = <0>; gpmc,we-off-ns = <40>; gpmc,oe-on-ns = <0>; gpmc,oe-off-ns = <54>; gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; partition@0 { label = "X-Loader"; reg = <0 0x80000>; }; partition@80000 { label = "U-Boot"; reg = <0x80000 0x1c0000>; }; partition@1c0000 { label = "Environment"; reg = <0x240000 0x40000>; }; partition@280000 { label = "Kernel"; reg = <0x280000 0x500000>; }; partition@780000 { label = "Filesystem"; reg = <0x780000 0xf880000>; }; }; }; &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&sd1_pins>; vmmc-supply = <&vmmcsd_fixed>; bus-width = <4>; cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; }; &pincntl { sd1_pins: pinmux_sd1_pins { pinctrl-single,pins = < DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ DM814X_IOPAD(0x0924, PIN_OUTPUT | 0x40) /* SD1_POW */ DM814X_IOPAD(0x093C, PIN_INPUT_PULLUP | 0x80) /* GP1[6] */ >; }; usb0_pins: pinmux_usb0_pins { pinctrl-single,pins = < DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ >; }; }; /* USB0_ID pin state: SW10[1] = 0 cable detection, SW10[1] = 1 ID grounded */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&usb0_pins>; dr_mode = "otg"; }; &usb1_phy { status = "disabled"; }; &usb1 { status = "disabled"; }; diff --git a/sys/gnu/dts/arm/dra7-evm-common.dtsi b/sys/gnu/dts/arm/dra7-evm-common.dtsi index 23244b5a9942..82eeba8faef1 100644 --- a/sys/gnu/dts/arm/dra7-evm-common.dtsi +++ b/sys/gnu/dts/arm/dra7-evm-common.dtsi @@ -1,284 +1,284 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ */ #include -#include +#include #include / { chosen { stdout-path = &uart1; }; extcon_usb1: extcon_usb1 { compatible = "linux,extcon-usb-gpio"; id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; }; extcon_usb2: extcon_usb2 { compatible = "linux,extcon-usb-gpio"; id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; }; sound0: sound0 { compatible = "simple-audio-card"; simple-audio-card,name = "DRA7xx-EVM"; simple-audio-card,widgets = "Headphone", "Headphone Jack", "Line", "Line Out", "Microphone", "Mic Jack", "Line", "Line In"; simple-audio-card,routing = "Headphone Jack", "HPLOUT", "Headphone Jack", "HPROUT", "Line Out", "LLOUT", "Line Out", "RLOUT", "MIC3L", "Mic Jack", "MIC3R", "Mic Jack", "Mic Jack", "Mic Bias", "LINE1L", "Line In", "LINE1R", "Line In"; simple-audio-card,format = "dsp_b"; simple-audio-card,bitclock-master = <&sound0_master>; simple-audio-card,frame-master = <&sound0_master>; simple-audio-card,bitclock-inversion; sound0_master: simple-audio-card,cpu { sound-dai = <&mcasp3>; system-clock-frequency = <5644800>; }; simple-audio-card,codec { sound-dai = <&tlv320aic3106>; clocks = <&atl_clkin2_ck>; }; }; leds { compatible = "gpio-leds"; led0 { label = "dra7:usr1"; gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>; default-state = "off"; }; led1 { label = "dra7:usr2"; gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>; default-state = "off"; }; led2 { label = "dra7:usr3"; gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>; default-state = "off"; }; led3 { label = "dra7:usr4"; gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>; default-state = "off"; }; }; gpio_keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; USER1 { label = "btnUser1"; linux,code = ; gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>; }; USER2 { label = "btnUser2"; linux,code = ; gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>; }; }; }; &i2c3 { status = "okay"; clock-frequency = <400000>; }; &mcspi1 { status = "okay"; }; &mcspi2 { status = "okay"; }; &uart1 { status = "okay"; interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, <&dra7_pmx_core 0x3e0>; }; &uart2 { status = "okay"; }; &uart3 { status = "okay"; }; &qspi { status = "okay"; spi-max-frequency = <76800000>; m25p80@0 { compatible = "s25fl256s1"; spi-max-frequency = <76800000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <1>; /* MTD partition table. * The ROM checks the first four physical blocks * for a valid file to boot and the flash here is * 64KiB block size. */ partition@0 { label = "QSPI.SPL"; reg = <0x00000000 0x000010000>; }; partition@1 { label = "QSPI.SPL.backup1"; reg = <0x00010000 0x00010000>; }; partition@2 { label = "QSPI.SPL.backup2"; reg = <0x00020000 0x00010000>; }; partition@3 { label = "QSPI.SPL.backup3"; reg = <0x00030000 0x00010000>; }; partition@4 { label = "QSPI.u-boot"; reg = <0x00040000 0x00100000>; }; partition@5 { label = "QSPI.u-boot-spl-os"; reg = <0x00140000 0x00080000>; }; partition@6 { label = "QSPI.u-boot-env"; reg = <0x001c0000 0x00010000>; }; partition@7 { label = "QSPI.u-boot-env.backup1"; reg = <0x001d0000 0x0010000>; }; partition@8 { label = "QSPI.kernel"; reg = <0x001e0000 0x0800000>; }; partition@9 { label = "QSPI.file-system"; reg = <0x009e0000 0x01620000>; }; }; }; &omap_dwc3_1 { extcon = <&extcon_usb1>; }; &usb1 { dr_mode = "otg"; extcon = <&extcon_usb1>; }; &omap_dwc3_2 { extcon = <&extcon_usb2>; }; &usb2 { dr_mode = "host"; extcon = <&extcon_usb2>; }; &atl { assigned-clocks = <&abe_dpll_sys_clk_mux>, <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>, <&dpll_abe_ck>, <&dpll_abe_m2x2_ck>, <&atl_clkin2_ck>; assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; status = "okay"; atl2 { bws = ; aws = ; }; }; &mcasp3 { #sound-dai-cells = <0>; assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; assigned-clock-parents = <&atl_clkin2_ck>; status = "okay"; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; /* 4 serializer */ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1 2 0 0 >; tx-num-evt = <32>; rx-num-evt = <32>; }; &mailbox5 { status = "okay"; mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { status = "okay"; }; mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { status = "okay"; }; mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { status = "okay"; }; }; &pcie1_rc { status = "okay"; }; &mmc4 { bus-width = <4>; cap-power-off-card; keep-power-in-suspend; non-removable; #address-cells = <1>; #size-cells = <0>; wifi@2 { compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio5>; interrupts = <7 IRQ_TYPE_EDGE_RISING>; }; }; diff --git a/sys/gnu/dts/arm/dra7-evm.dts b/sys/gnu/dts/arm/dra7-evm.dts index af06a55d1c5c..de7f85efaa51 100644 --- a/sys/gnu/dts/arm/dra7-evm.dts +++ b/sys/gnu/dts/arm/dra7-evm.dts @@ -1,539 +1,539 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; #include "dra74x.dtsi" #include "dra7-evm-common.dtsi" #include "dra74x-mmc-iodelay.dtsi" / { model = "TI DRA742"; compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; memory@0 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ }; evm_12v0: fixedregulator-evm_12v0 { /* main supply */ compatible = "regulator-fixed"; regulator-name = "evm_12v0"; regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; regulator-always-on; regulator-boot-on; }; evm_1v8_sw: fixedregulator-evm_1v8 { compatible = "regulator-fixed"; regulator-name = "evm_1v8"; vin-supply = <&smps9_reg>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; evm_3v3_sd: fixedregulator-sd { compatible = "regulator-fixed"; regulator-name = "evm_3v3_sd"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; }; evm_3v3_sw: fixedregulator-evm_3v3_sw { compatible = "regulator-fixed"; regulator-name = "evm_3v3_sw"; vin-supply = <&sysen1>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; aic_dvdd: fixedregulator-aic_dvdd { /* TPS77018DBVT */ compatible = "regulator-fixed"; regulator-name = "aic_dvdd"; vin-supply = <&evm_3v3_sw>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vsys_3v3: fixedregulator-vsys3v3 { + evm_3v3: fixedregulator-evm3v3 { /* Output of Cntlr A of TPS43351-Q1 on dra7-evm */ compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; + regulator-name = "evm_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <&evm_12v0>; regulator-always-on; regulator-boot-on; }; evm_5v0: fixedregulator-evm_5v0 { /* Output of Cntlr B of TPS43351-Q1 on dra7-evm */ compatible = "regulator-fixed"; regulator-name = "evm_5v0"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; vin-supply = <&evm_12v0>; regulator-always-on; regulator-boot-on; }; evm_3v6: fixedregulator-evm_3v6 { compatible = "regulator-fixed"; regulator-name = "evm_3v6"; regulator-min-microvolt = <3600000>; regulator-max-microvolt = <3600000>; vin-supply = <&evm_5v0>; regulator-always-on; regulator-boot-on; }; vmmcwl_fixed: fixedregulator-mmcwl { compatible = "regulator-fixed"; regulator-name = "vmmcwl_fixed"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&gpio5 8 0>; startup-delay-us = <70000>; enable-active-high; }; vtt_fixed: fixedregulator-vtt { compatible = "regulator-fixed"; regulator-name = "vtt_fixed"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-boot-on; enable-active-high; vin-supply = <&sysen2>; gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; }; }; &dra7_pmx_core { dcan1_pins_default: dcan1_pins_default { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ >; }; dcan1_pins_sleep: dcan1_pins_sleep { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ >; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; tps659038: tps659038@58 { compatible = "ti,tps659038"; reg = <0x58>; ti,palmas-override-powerhold; ti,system-power-controller; tps659038_pmic { compatible = "ti,tps659038-pmic"; regulators { smps123_reg: smps123 { /* VDD_MPU */ regulator-name = "smps123"; regulator-min-microvolt = < 850000>; regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; smps45_reg: smps45 { /* VDD_DSPEVE */ regulator-name = "smps45"; regulator-min-microvolt = < 850000>; regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; smps6_reg: smps6 { /* VDD_GPU - over VDD_SMPS6 */ regulator-name = "smps6"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; smps7_reg: smps7 { /* CORE_VDD */ regulator-name = "smps7"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1150000>; regulator-always-on; regulator-boot-on; }; smps8_reg: smps8 { /* VDD_IVAHD */ regulator-name = "smps8"; regulator-min-microvolt = < 850000>; regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; smps9_reg: smps9 { /* VDDS1V8 */ regulator-name = "smps9"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; ldo1_reg: ldo1 { /* LDO1_OUT --> SDIO */ regulator-name = "ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; ldo2_reg: ldo2 { /* VDD_RTCIO */ /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ regulator-name = "ldo2"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; ldo3_reg: ldo3 { /* VDDA_1V8_PHY */ regulator-name = "ldo3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; ldo9_reg: ldo9 { /* VDD_RTC */ regulator-name = "ldo9"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; regulator-always-on; regulator-boot-on; regulator-allow-bypass; }; ldoln_reg: ldoln { /* VDDA_1V8_PLL */ regulator-name = "ldoln"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; ldousb_reg: ldousb { /* VDDA_3V_USB: VDDA_USBHS33 */ regulator-name = "ldousb"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; }; /* REGEN1 is unused */ regen2: regen2 { /* Needed for PMIC internal resources */ regulator-name = "regen2"; regulator-boot-on; regulator-always-on; }; /* REGEN3 is unused */ sysen1: sysen1 { /* PMIC_REGEN_3V3 */ regulator-name = "sysen1"; regulator-boot-on; regulator-always-on; }; sysen2: sysen2 { /* PMIC_REGEN_DDR */ regulator-name = "sysen2"; regulator-boot-on; regulator-always-on; }; }; }; }; pcf_lcd: gpio@20 { compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&gpio6>; interrupts = <11 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; }; pcf_gpio_21: gpio@21 { compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x21>; lines-initial-states = <0x1408>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&gpio6>; interrupts = <11 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; }; tlv320aic3106: tlv320aic3106@19 { #sound-dai-cells = <0>; compatible = "ti,tlv320aic3106"; reg = <0x19>; adc-settle-ms = <40>; ai3x-micbias-vg = <1>; /* 2.0V */ status = "okay"; /* Regulators */ AVDD-supply = <&evm_3v3_sw>; IOVDD-supply = <&evm_3v3_sw>; DRVDD-supply = <&evm_3v3_sw>; DVDD-supply = <&aic_dvdd>; }; }; &i2c2 { status = "okay"; clock-frequency = <400000>; pcf_hdmi: gpio@26 { compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x26>; gpio-controller; #gpio-cells = <2>; p1 { /* vin6_sel_s0: high: VIN6, low: audio */ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; output-low; line-name = "vin6_sel_s0"; }; }; }; &mmc1 { status = "okay"; vmmc-supply = <&evm_3v3_sd>; vqmmc-supply = <&ldo1_reg>; bus-width = <4>; /* * SDCD signal is not being used here - using the fact that GPIO mode * is always hardwired. */ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104"; pinctrl-0 = <&mmc1_pins_default>; pinctrl-1 = <&mmc1_pins_hs>; pinctrl-2 = <&mmc1_pins_sdr12>; pinctrl-3 = <&mmc1_pins_sdr25>; pinctrl-4 = <&mmc1_pins_sdr50>; pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>; pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>; pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; }; &mmc2 { status = "okay"; vmmc-supply = <&evm_1v8_sw>; vqmmc-supply = <&evm_1v8_sw>; bus-width = <8>; non-removable; pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v"; pinctrl-0 = <&mmc2_pins_default>; pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>; pinctrl-3 = <&mmc2_pins_ddr_rev20>; pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>; pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; }; &mmc4 { status = "okay"; vmmc-supply = <&evm_3v6>; vqmmc-supply = <&vmmcwl_fixed>; pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25"; pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>; pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>; pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; }; &cpu0 { vdd-supply = <&smps123_reg>; }; &elm { status = "okay"; }; &gpmc { /* * For the existing IOdelay configuration via U-Boot we don't * support NAND on dra7-evm. Keep it disabled. Enabling it * requires a different configuration by U-Boot. */ status = "disabled"; ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* device IO registers */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ ti,nand-xfer-type = "prefetch-dma"; ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; gpmc,device-width = <2>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <80>; gpmc,cs-wr-off-ns = <80>; gpmc,adv-on-ns = <0>; gpmc,adv-rd-off-ns = <60>; gpmc,adv-wr-off-ns = <60>; gpmc,we-on-ns = <10>; gpmc,we-off-ns = <50>; gpmc,oe-on-ns = <4>; gpmc,oe-off-ns = <40>; gpmc,access-ns = <40>; gpmc,wr-access-ns = <80>; gpmc,rd-cycle-ns = <80>; gpmc,wr-cycle-ns = <80>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ /* All SPL-* partitions are sized to minimal length * which can be independently programmable. For * NAND flash this is equal to size of erase-block */ #address-cells = <1>; #size-cells = <1>; partition@0 { label = "NAND.SPL"; reg = <0x00000000 0x000020000>; }; partition@1 { label = "NAND.SPL.backup1"; reg = <0x00020000 0x00020000>; }; partition@2 { label = "NAND.SPL.backup2"; reg = <0x00040000 0x00020000>; }; partition@3 { label = "NAND.SPL.backup3"; reg = <0x00060000 0x00020000>; }; partition@4 { label = "NAND.u-boot-spl-os"; reg = <0x00080000 0x00040000>; }; partition@5 { label = "NAND.u-boot"; reg = <0x000c0000 0x00100000>; }; partition@6 { label = "NAND.u-boot-env"; reg = <0x001c0000 0x00020000>; }; partition@7 { label = "NAND.u-boot-env.backup1"; reg = <0x001e0000 0x00020000>; }; partition@8 { label = "NAND.kernel"; reg = <0x00200000 0x00800000>; }; partition@9 { label = "NAND.file-system"; reg = <0x00a00000 0x0f600000>; }; }; }; &usb2_phy1 { phy-supply = <&ldousb_reg>; }; &usb2_phy2 { phy-supply = <&ldousb_reg>; }; &gpio7_target { ti,no-reset-on-init; ti,no-idle-on-init; }; &mac { status = "okay"; dual_emac; }; &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "rgmii"; dual_emac_res_vlan = <1>; }; &cpsw_emac1 { phy-handle = <ðphy1>; phy-mode = "rgmii"; dual_emac_res_vlan = <2>; }; &davinci_mdio { ethphy0: ethernet-phy@2 { reg = <2>; }; ethphy1: ethernet-phy@3 { reg = <3>; }; }; &dcan1 { status = "ok"; pinctrl-names = "default", "sleep", "active"; pinctrl-0 = <&dcan1_pins_sleep>; pinctrl-1 = <&dcan1_pins_sleep>; pinctrl-2 = <&dcan1_pins_default>; }; diff --git a/sys/gnu/dts/arm/dra7-l4.dtsi b/sys/gnu/dts/arm/dra7-l4.dtsi index 2119a78e9c15..5cac2dd58241 100644 --- a/sys/gnu/dts/arm/dra7-l4.dtsi +++ b/sys/gnu/dts/arm/dra7-l4.dtsi @@ -1,4656 +1,4554 @@ &l4_cfg { /* 0x4a000000 */ compatible = "ti,dra7-l4-cfg", "simple-bus"; reg = <0x4a000000 0x800>, <0x4a000800 0x800>, <0x4a001000 0x1000>; reg-names = "ap", "la", "ia0"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */ <0x00100000 0x4a100000 0x100000>, /* segment 1 */ <0x00200000 0x4a200000 0x100000>; /* segment 2 */ segment@0 { /* 0x4a000000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00000800 0x00000800 0x000800>, /* ap 1 */ <0x00001000 0x00001000 0x001000>, /* ap 2 */ <0x00002000 0x00002000 0x002000>, /* ap 3 */ <0x00004000 0x00004000 0x001000>, /* ap 4 */ <0x00005000 0x00005000 0x001000>, /* ap 5 */ <0x00006000 0x00006000 0x001000>, /* ap 6 */ <0x00008000 0x00008000 0x002000>, /* ap 7 */ <0x0000a000 0x0000a000 0x001000>, /* ap 8 */ <0x00056000 0x00056000 0x001000>, /* ap 9 */ <0x00057000 0x00057000 0x001000>, /* ap 10 */ <0x0005e000 0x0005e000 0x002000>, /* ap 11 */ <0x00060000 0x00060000 0x001000>, /* ap 12 */ <0x00080000 0x00080000 0x008000>, /* ap 13 */ <0x00088000 0x00088000 0x001000>, /* ap 14 */ <0x000a0000 0x000a0000 0x008000>, /* ap 15 */ <0x000a8000 0x000a8000 0x001000>, /* ap 16 */ <0x000d9000 0x000d9000 0x001000>, /* ap 17 */ <0x000da000 0x000da000 0x001000>, /* ap 18 */ <0x000dd000 0x000dd000 0x001000>, /* ap 19 */ <0x000de000 0x000de000 0x001000>, /* ap 20 */ <0x000e0000 0x000e0000 0x001000>, /* ap 21 */ <0x000e1000 0x000e1000 0x001000>, /* ap 22 */ <0x000f4000 0x000f4000 0x001000>, /* ap 23 */ <0x000f5000 0x000f5000 0x001000>, /* ap 24 */ <0x000f6000 0x000f6000 0x001000>, /* ap 25 */ <0x000f7000 0x000f7000 0x001000>, /* ap 26 */ <0x00090000 0x00090000 0x008000>, /* ap 59 */ <0x00098000 0x00098000 0x001000>; /* ap 60 */ target-module@2000 { /* 0x4a002000, ap 3 08.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x2000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x2000>; scm: scm@0 { compatible = "ti,dra7-scm-core", "simple-bus"; reg = <0 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x2000>; scm_conf: scm_conf@0 { compatible = "syscon", "simple-bus"; reg = <0x0 0x1400>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0x1400>; pbias_regulator: pbias_regulator@e00 { compatible = "ti,pbias-dra7", "ti,pbias-omap"; reg = <0xe00 0x4>; syscon = <&scm_conf>; pbias_mmc_reg: pbias_mmc_omap5 { regulator-name = "pbias_mmc_omap5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; }; phy_gmii_sel: phy-gmii-sel { compatible = "ti,dra7xx-phy-gmii-sel"; reg = <0x554 0x4>; #phy-cells = <1>; }; scm_conf_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; }; dra7_pmx_core: pinmux@1400 { compatible = "ti,dra7-padconf", "pinctrl-single"; reg = <0x1400 0x0468>; #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x3fffffff>; }; scm_conf1: scm_conf@1c04 { compatible = "syscon"; reg = <0x1c04 0x0020>; #syscon-cells = <2>; }; scm_conf_pcie: scm_conf@1c24 { compatible = "syscon"; reg = <0x1c24 0x0024>; }; sdma_xbar: dma-router@b78 { compatible = "ti,dra7-dma-crossbar"; reg = <0xb78 0xfc>; #dma-cells = <1>; dma-requests = <205>; ti,dma-safe-map = <0>; dma-masters = <&sdma>; }; edma_xbar: dma-router@c78 { compatible = "ti,dra7-dma-crossbar"; reg = <0xc78 0x7c>; #dma-cells = <2>; dma-requests = <204>; ti,dma-safe-map = <0>; dma-masters = <&edma>; }; }; }; target-module@5000 { /* 0x4a005000, ap 5 10.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x5000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5000 0x1000>; cm_core_aon: cm_core_aon@0 { compatible = "ti,dra7-cm-core-aon", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0 0x2000>; ranges = <0 0 0x2000>; cm_core_aon_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; cm_core_aon_clockdomains: clockdomains { }; }; }; target-module@8000 { /* 0x4a008000, ap 7 0e.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x8000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x2000>; cm_core: cm_core@0 { compatible = "ti,dra7-cm-core", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0 0x3000>; ranges = <0 0 0x3000>; cm_core_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; cm_core_clockdomains: clockdomains { }; }; }; target-module@56000 { /* 0x4a056000, ap 9 02.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "dma_system"; reg = <0x56000 0x4>, <0x5602c 0x4>, <0x56028 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): core_pwrdm, dma_clkdm */ clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x56000 0x1000>; sdma: dma-controller@0 { - compatible = "ti,omap4430-sdma", "ti,omap-sdma"; + compatible = "ti,omap4430-sdma"; reg = <0x0 0x1000>; interrupts = , , , ; #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; }; }; target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5e000 0x2000>; }; target-module@80000 { /* 0x4a080000, ap 13 20.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "ocp2scp1"; reg = <0x80000 0x4>, <0x80010 0x4>, <0x80014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000 0x8000>; ocp2scp@0 { compatible = "ti,omap-ocp2scp"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x8000>; reg = <0x0 0x20>; usb2_phy1: phy@4000 { compatible = "ti,dra7x-usb2", "ti,omap-usb2"; reg = <0x4000 0x400>; syscon-phy-power = <&scm_conf 0x300>; clocks = <&usb_phy1_always_on_clk32k>, <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; }; usb2_phy2: phy@5000 { compatible = "ti,dra7x-usb2-phy2", "ti,omap-usb2"; reg = <0x5000 0x400>; syscon-phy-power = <&scm_conf 0xe74>; clocks = <&usb_phy2_always_on_clk32k>, <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; }; usb3_phy1: phy@4400 { compatible = "ti,omap-usb3"; reg = <0x4400 0x80>, <0x4800 0x64>, <0x4c00 0x40>; reg-names = "phy_rx", "phy_tx", "pll_ctrl"; syscon-phy-power = <&scm_conf 0x370>; clocks = <&usb_phy3_always_on_clk32k>, <&sys_clkin1>, <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; clock-names = "wkupclk", "sysclk", "refclk"; #phy-cells = <0>; }; }; }; target-module@90000 { /* 0x4a090000, ap 59 42.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "ocp2scp3"; reg = <0x90000 0x4>, <0x90010 0x4>, <0x90014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x90000 0x8000>; ocp2scp@0 { compatible = "ti,omap-ocp2scp"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x8000>; reg = <0x0 0x20>; pcie1_phy: pciephy@4000 { compatible = "ti,phy-pipe3-pcie"; reg = <0x4000 0x80>, /* phy_rx */ <0x4400 0x64>; /* phy_tx */ reg-names = "phy_rx", "phy_tx"; syscon-phy-power = <&scm_conf_pcie 0x1c>; syscon-pcs = <&scm_conf_pcie 0x10>; clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_m2ldo_ck>, <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>, <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>, <&optfclk_pciephy_div>, <&sys_clkin1>; clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div", "sysclk"; #phy-cells = <0>; }; pcie2_phy: pciephy@5000 { compatible = "ti,phy-pipe3-pcie"; reg = <0x5000 0x80>, /* phy_rx */ <0x5400 0x64>; /* phy_tx */ reg-names = "phy_rx", "phy_tx"; syscon-phy-power = <&scm_conf_pcie 0x20>; syscon-pcs = <&scm_conf_pcie 0x10>; clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_m2ldo_ck>, <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>, <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>, <&optfclk_pciephy_div>, <&sys_clkin1>; clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div", "sysclk"; #phy-cells = <0>; status = "disabled"; }; sata_phy: phy@6000 { compatible = "ti,phy-pipe3-sata"; reg = <0x6000 0x80>, /* phy_rx */ <0x6400 0x64>, /* phy_tx */ <0x6800 0x40>; /* pll_ctrl */ reg-names = "phy_rx", "phy_tx", "pll_ctrl"; syscon-phy-power = <&scm_conf 0x374>; clocks = <&sys_clkin1>, <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; clock-names = "sysclk", "refclk"; syscon-pllreset = <&scm_conf 0x3fc>; #phy-cells = <0>; }; }; }; target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa0000 0x8000>; }; target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */ compatible = "ti,sysc-omap4-sr", "ti,sysc"; + ti,hwmods = "smartreflex_mpu"; reg = <0xd9038 0x4>; reg-names = "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd9000 0x1000>; /* SmartReflex child device marked reserved in TRM */ }; target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */ compatible = "ti,sysc-omap4-sr", "ti,sysc"; + ti,hwmods = "smartreflex_core"; reg = <0xdd038 0x4>; reg-names = "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xdd000 0x1000>; /* SmartReflex child device marked reserved in TRM */ }; target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe0000 0x1000>; }; target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox1"; reg = <0xf4000 0x4>, <0xf4010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xf4000 0x1000>; mailbox1: mailbox@0 { compatible = "ti,omap4-mailbox"; reg = <0x0 0x200>; interrupts = , , ; #mbox-cells = <1>; ti,mbox-num-users = <3>; ti,mbox-num-fifos = <8>; status = "disabled"; }; }; target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spinlock"; reg = <0xf6000 0x4>, <0xf6010 0x4>, <0xf6014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xf6000 0x1000>; hwspinlock: spinlock@0 { compatible = "ti,omap4-hwspinlock"; reg = <0x0 0x1000>; #hwlock-cells = <1>; }; }; }; segment@100000 { /* 0x4a100000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */ <0x00003000 0x00103000 0x001000>, /* ap 28 */ <0x00008000 0x00108000 0x001000>, /* ap 29 */ <0x00009000 0x00109000 0x001000>, /* ap 30 */ <0x00040000 0x00140000 0x010000>, /* ap 31 */ <0x00050000 0x00150000 0x001000>, /* ap 32 */ <0x00051000 0x00151000 0x001000>, /* ap 33 */ <0x00052000 0x00152000 0x001000>, /* ap 34 */ <0x00053000 0x00153000 0x001000>, /* ap 35 */ <0x00054000 0x00154000 0x001000>, /* ap 36 */ <0x00055000 0x00155000 0x001000>, /* ap 37 */ <0x00056000 0x00156000 0x001000>, /* ap 38 */ <0x00057000 0x00157000 0x001000>, /* ap 39 */ <0x00058000 0x00158000 0x001000>, /* ap 40 */ <0x0005b000 0x0015b000 0x001000>, /* ap 41 */ <0x0005c000 0x0015c000 0x001000>, /* ap 42 */ <0x0005d000 0x0015d000 0x001000>, /* ap 45 */ <0x0005e000 0x0015e000 0x001000>, /* ap 46 */ <0x0005f000 0x0015f000 0x001000>, /* ap 47 */ <0x00060000 0x00160000 0x001000>, /* ap 48 */ <0x00061000 0x00161000 0x001000>, /* ap 49 */ <0x00062000 0x00162000 0x001000>, /* ap 50 */ <0x00063000 0x00163000 0x001000>, /* ap 51 */ <0x00064000 0x00164000 0x001000>, /* ap 52 */ <0x00065000 0x00165000 0x001000>, /* ap 53 */ <0x00066000 0x00166000 0x001000>, /* ap 54 */ <0x00067000 0x00167000 0x001000>, /* ap 55 */ <0x00068000 0x00168000 0x001000>, /* ap 56 */ <0x0006d000 0x0016d000 0x001000>, /* ap 57 */ <0x0006e000 0x0016e000 0x001000>, /* ap 58 */ <0x00071000 0x00171000 0x001000>, /* ap 61 */ <0x00072000 0x00172000 0x001000>, /* ap 62 */ <0x00073000 0x00173000 0x001000>, /* ap 63 */ <0x00074000 0x00174000 0x001000>, /* ap 64 */ <0x00075000 0x00175000 0x001000>, /* ap 65 */ <0x00076000 0x00176000 0x001000>, /* ap 66 */ <0x00077000 0x00177000 0x001000>, /* ap 67 */ <0x00078000 0x00178000 0x001000>, /* ap 68 */ <0x00081000 0x00181000 0x001000>, /* ap 69 */ <0x00082000 0x00182000 0x001000>, /* ap 70 */ <0x00083000 0x00183000 0x001000>, /* ap 71 */ <0x00084000 0x00184000 0x001000>, /* ap 72 */ <0x00085000 0x00185000 0x001000>, /* ap 73 */ <0x00086000 0x00186000 0x001000>, /* ap 74 */ <0x00087000 0x00187000 0x001000>, /* ap 75 */ <0x00088000 0x00188000 0x001000>, /* ap 76 */ <0x00069000 0x00169000 0x001000>, /* ap 103 */ <0x0006a000 0x0016a000 0x001000>, /* ap 104 */ <0x00079000 0x00179000 0x001000>, /* ap 105 */ <0x0007a000 0x0017a000 0x001000>, /* ap 106 */ <0x0006b000 0x0016b000 0x001000>, /* ap 107 */ <0x0006c000 0x0016c000 0x001000>, /* ap 108 */ <0x0007b000 0x0017b000 0x001000>, /* ap 121 */ <0x0007c000 0x0017c000 0x001000>, /* ap 122 */ <0x0007d000 0x0017d000 0x001000>, /* ap 123 */ <0x0007e000 0x0017e000 0x001000>, /* ap 124 */ <0x00059000 0x00159000 0x001000>, /* ap 125 */ <0x0005a000 0x0015a000 0x001000>; /* ap 126 */ target-module@2000 { /* 0x4a102000, ap 27 3c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x1000>; }; target-module@8000 { /* 0x4a108000, ap 29 1e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x1000>; }; target-module@40000 { /* 0x4a140000, ap 31 06.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x40000 0x10000>; }; target-module@51000 { /* 0x4a151000, ap 33 50.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x51000 0x1000>; }; target-module@53000 { /* 0x4a153000, ap 35 54.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x53000 0x1000>; }; target-module@55000 { /* 0x4a155000, ap 37 46.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x55000 0x1000>; }; target-module@57000 { /* 0x4a157000, ap 39 58.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x57000 0x1000>; }; target-module@59000 { /* 0x4a159000, ap 125 6a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x59000 0x1000>; }; target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5b000 0x1000>; }; target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5d000 0x1000>; }; target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5f000 0x1000>; }; target-module@61000 { /* 0x4a161000, ap 49 32.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x61000 0x1000>; }; target-module@63000 { /* 0x4a163000, ap 51 5c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x63000 0x1000>; }; target-module@65000 { /* 0x4a165000, ap 53 4e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x65000 0x1000>; }; target-module@67000 { /* 0x4a167000, ap 55 5e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x67000 0x1000>; }; target-module@69000 { /* 0x4a169000, ap 103 4a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x69000 0x1000>; }; target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6b000 0x1000>; }; target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6d000 0x1000>; }; target-module@71000 { /* 0x4a171000, ap 61 48.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x71000 0x1000>; }; target-module@73000 { /* 0x4a173000, ap 63 2a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x73000 0x1000>; }; target-module@75000 { /* 0x4a175000, ap 65 64.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x75000 0x1000>; }; target-module@77000 { /* 0x4a177000, ap 67 66.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x77000 0x1000>; }; target-module@79000 { /* 0x4a179000, ap 105 34.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x79000 0x1000>; }; target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x7b000 0x1000>; }; target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x7d000 0x1000>; }; target-module@81000 { /* 0x4a181000, ap 69 26.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x81000 0x1000>; }; target-module@83000 { /* 0x4a183000, ap 71 2e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x83000 0x1000>; }; target-module@85000 { /* 0x4a185000, ap 73 36.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x85000 0x1000>; }; target-module@87000 { /* 0x4a187000, ap 75 74.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x87000 0x1000>; }; }; segment@200000 { /* 0x4a200000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */ <0x00019000 0x00219000 0x001000>, /* ap 44 */ <0x00000000 0x00200000 0x001000>, /* ap 77 */ <0x00001000 0x00201000 0x001000>, /* ap 78 */ <0x0000a000 0x0020a000 0x001000>, /* ap 79 */ <0x0000b000 0x0020b000 0x001000>, /* ap 80 */ <0x0000c000 0x0020c000 0x001000>, /* ap 81 */ <0x0000d000 0x0020d000 0x001000>, /* ap 82 */ <0x0000e000 0x0020e000 0x001000>, /* ap 83 */ <0x0000f000 0x0020f000 0x001000>, /* ap 84 */ <0x00010000 0x00210000 0x001000>, /* ap 85 */ <0x00011000 0x00211000 0x001000>, /* ap 86 */ <0x00012000 0x00212000 0x001000>, /* ap 87 */ <0x00013000 0x00213000 0x001000>, /* ap 88 */ <0x00014000 0x00214000 0x001000>, /* ap 89 */ <0x00015000 0x00215000 0x001000>, /* ap 90 */ <0x0002a000 0x0022a000 0x001000>, /* ap 91 */ <0x0002b000 0x0022b000 0x001000>, /* ap 92 */ <0x0001c000 0x0021c000 0x001000>, /* ap 93 */ <0x0001d000 0x0021d000 0x001000>, /* ap 94 */ <0x0001e000 0x0021e000 0x001000>, /* ap 95 */ <0x0001f000 0x0021f000 0x001000>, /* ap 96 */ <0x00020000 0x00220000 0x001000>, /* ap 97 */ <0x00021000 0x00221000 0x001000>, /* ap 98 */ <0x00024000 0x00224000 0x001000>, /* ap 99 */ <0x00025000 0x00225000 0x001000>, /* ap 100 */ <0x00026000 0x00226000 0x001000>, /* ap 101 */ <0x00027000 0x00227000 0x001000>, /* ap 102 */ <0x0002c000 0x0022c000 0x001000>, /* ap 109 */ <0x0002d000 0x0022d000 0x001000>, /* ap 110 */ <0x0002e000 0x0022e000 0x001000>, /* ap 111 */ <0x0002f000 0x0022f000 0x001000>, /* ap 112 */ <0x00030000 0x00230000 0x001000>, /* ap 113 */ <0x00031000 0x00231000 0x001000>, /* ap 114 */ <0x00032000 0x00232000 0x001000>, /* ap 115 */ <0x00033000 0x00233000 0x001000>, /* ap 116 */ <0x00034000 0x00234000 0x001000>, /* ap 117 */ <0x00035000 0x00235000 0x001000>, /* ap 118 */ <0x00036000 0x00236000 0x001000>, /* ap 119 */ <0x00037000 0x00237000 0x001000>, /* ap 120 */ <0x0001a000 0x0021a000 0x001000>, /* ap 127 */ <0x0001b000 0x0021b000 0x001000>; /* ap 128 */ target-module@0 { /* 0x4a200000, ap 77 3e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x1000>; }; target-module@a000 { /* 0x4a20a000, ap 79 30.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa000 0x1000>; }; target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc000 0x1000>; }; target-module@e000 { /* 0x4a20e000, ap 83 22.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe000 0x1000>; }; target-module@10000 { /* 0x4a210000, ap 85 14.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x10000 0x1000>; }; target-module@12000 { /* 0x4a212000, ap 87 16.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x12000 0x1000>; }; target-module@14000 { /* 0x4a214000, ap 89 1c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x14000 0x1000>; }; target-module@18000 { /* 0x4a218000, ap 43 12.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x18000 0x1000>; }; target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1a000 0x1000>; }; target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1c000 0x1000>; }; target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1e000 0x1000>; }; target-module@20000 { /* 0x4a220000, ap 97 24.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x1000>; }; target-module@24000 { /* 0x4a224000, ap 99 44.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x24000 0x1000>; }; target-module@26000 { /* 0x4a226000, ap 101 2c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x26000 0x1000>; }; target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2a000 0x1000>; }; target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2c000 0x1000>; }; target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2e000 0x1000>; }; target-module@30000 { /* 0x4a230000, ap 113 70.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x30000 0x1000>; }; target-module@32000 { /* 0x4a232000, ap 115 5a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x32000 0x1000>; }; target-module@34000 { /* 0x4a234000, ap 117 76.1 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x34000 0x1000>; }; target-module@36000 { /* 0x4a236000, ap 119 62.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x36000 0x1000>; }; }; }; &l4_per1 { /* 0x48000000 */ compatible = "ti,dra7-l4-per1", "simple-bus"; reg = <0x48000000 0x800>, <0x48000800 0x800>, <0x48001000 0x400>, <0x48001400 0x400>, <0x48001800 0x400>, <0x48001c00 0x400>; reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ <0x00200000 0x48200000 0x200000>; /* segment 1 */ segment@0 { /* 0x48000000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00001000 0x00001000 0x000400>, /* ap 1 */ <0x00000800 0x00000800 0x000800>, /* ap 2 */ <0x00020000 0x00020000 0x001000>, /* ap 3 */ <0x00021000 0x00021000 0x001000>, /* ap 4 */ <0x00032000 0x00032000 0x001000>, /* ap 5 */ <0x00033000 0x00033000 0x001000>, /* ap 6 */ <0x00034000 0x00034000 0x001000>, /* ap 7 */ <0x00035000 0x00035000 0x001000>, /* ap 8 */ <0x00036000 0x00036000 0x001000>, /* ap 9 */ <0x00037000 0x00037000 0x001000>, /* ap 10 */ <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ <0x00055000 0x00055000 0x001000>, /* ap 13 */ <0x00056000 0x00056000 0x001000>, /* ap 14 */ <0x00057000 0x00057000 0x001000>, /* ap 15 */ <0x00058000 0x00058000 0x001000>, /* ap 16 */ <0x00059000 0x00059000 0x001000>, /* ap 17 */ <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ <0x00060000 0x00060000 0x001000>, /* ap 23 */ <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ <0x00070000 0x00070000 0x001000>, /* ap 30 */ <0x00071000 0x00071000 0x001000>, /* ap 31 */ <0x00072000 0x00072000 0x001000>, /* ap 32 */ <0x00073000 0x00073000 0x001000>, /* ap 33 */ <0x00061000 0x00061000 0x001000>, /* ap 34 */ <0x00053000 0x00053000 0x001000>, /* ap 35 */ <0x00054000 0x00054000 0x001000>, /* ap 36 */ <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ <0x00078000 0x00078000 0x001000>, /* ap 39 */ <0x00079000 0x00079000 0x001000>, /* ap 40 */ <0x00086000 0x00086000 0x001000>, /* ap 41 */ <0x00087000 0x00087000 0x001000>, /* ap 42 */ <0x00088000 0x00088000 0x001000>, /* ap 43 */ <0x00089000 0x00089000 0x001000>, /* ap 44 */ <0x00051000 0x00051000 0x001000>, /* ap 45 */ <0x00052000 0x00052000 0x001000>, /* ap 46 */ <0x00098000 0x00098000 0x001000>, /* ap 47 */ <0x00099000 0x00099000 0x001000>, /* ap 48 */ <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ <0x00068000 0x00068000 0x001000>, /* ap 53 */ <0x00069000 0x00069000 0x001000>, /* ap 54 */ <0x00090000 0x00090000 0x002000>, /* ap 55 */ <0x00092000 0x00092000 0x001000>, /* ap 56 */ <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ <0x00066000 0x00066000 0x001000>, /* ap 63 */ <0x00067000 0x00067000 0x001000>, /* ap 64 */ <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ <0x00001400 0x00001400 0x000400>, /* ap 77 */ <0x00001800 0x00001800 0x000400>, /* ap 78 */ <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ target-module@20000 { /* 0x48020000, ap 3 04.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x20050 0x4>, <0x20054 0x4>, <0x20058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x1000>; uart3: serial@0 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; status = "disabled"; dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; dma-names = "tx", "rx"; }; }; target-module@32000 { /* 0x48032000, ap 5 3e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; ti,hwmods = "timer2"; reg = <0x32000 0x4>, <0x32010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x32000 0x1000>; timer2: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>; clock-names = "fck"; interrupts = ; }; }; target-module@34000 { /* 0x48034000, ap 7 46.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; ti,hwmods = "timer3"; reg = <0x34000 0x4>, <0x34010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x34000 0x1000>; timer3: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>; clock-names = "fck"; interrupts = ; }; }; target-module@36000 { /* 0x48036000, ap 9 4e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; ti,hwmods = "timer4"; reg = <0x36000 0x4>, <0x36010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x36000 0x1000>; timer4: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>; clock-names = "fck"; interrupts = ; }; }; target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer9"; reg = <0x3e000 0x4>, <0x3e010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3e000 0x1000>; timer9: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>; clock-names = "fck"; interrupts = ; }; }; gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x51000 0x4>, <0x51010 0x4>, <0x51114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>, <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x51000 0x1000>; gpio7: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@53000 { /* 0x48053000, ap 35 36.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x53000 0x4>, <0x53010 0x4>, <0x53114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>, <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x53000 0x1000>; gpio8: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@55000 { /* 0x48055000, ap 13 0e.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x55000 0x4>, <0x55010 0x4>, <0x55114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>, <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x55000 0x1000>; gpio2: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@57000 { /* 0x48057000, ap 15 06.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x57000 0x4>, <0x57010 0x4>, <0x57114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>, <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x57000 0x1000>; gpio3: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@59000 { /* 0x48059000, ap 17 16.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x59000 0x4>, <0x59010 0x4>, <0x59114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>, <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x59000 0x1000>; gpio4: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x5b000 0x4>, <0x5b010 0x4>, <0x5b114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>, <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5b000 0x1000>; gpio5: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x5d000 0x4>, <0x5d010 0x4>, <0x5d114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>, <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5d000 0x1000>; gpio6: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@60000 { /* 0x48060000, ap 23 32.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x60000 0x8>, <0x60010 0x8>, <0x60090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x60000 0x1000>; i2c3: i2c@0 { compatible = "ti,omap4-i2c"; reg = <0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; target-module@66000 { /* 0x48066000, ap 63 14.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x66050 0x4>, <0x66054 0x4>, <0x66058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x66000 0x1000>; uart5: serial@0 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; status = "disabled"; dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; dma-names = "tx", "rx"; }; }; target-module@68000 { /* 0x48068000, ap 53 1c.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x68050 0x4>, <0x68054 0x4>, <0x68058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x68000 0x1000>; uart6: serial@0 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; status = "disabled"; dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; dma-names = "tx", "rx"; }; }; target-module@6a000 { /* 0x4806a000, ap 24 24.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x6a050 0x4>, <0x6a054 0x4>, <0x6a058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6a000 0x1000>; uart1: serial@0 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x0 0x100>; interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; status = "disabled"; dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; dma-names = "tx", "rx"; }; }; target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x6c050 0x4>, <0x6c054 0x4>, <0x6c058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6c000 0x1000>; uart2: serial@0 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; status = "disabled"; dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; dma-names = "tx", "rx"; }; }; target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x6e050 0x4>, <0x6e054 0x4>, <0x6e058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6e000 0x1000>; uart4: serial@0 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; status = "disabled"; dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; dma-names = "tx", "rx"; }; }; target-module@70000 { /* 0x48070000, ap 30 22.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x70000 0x8>, <0x70010 0x8>, <0x70090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x70000 0x1000>; i2c1: i2c@0 { compatible = "ti,omap4-i2c"; reg = <0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; target-module@72000 { /* 0x48072000, ap 32 2a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x72000 0x8>, <0x72010 0x8>, <0x72090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x72000 0x1000>; i2c2: i2c@0 { compatible = "ti,omap4-i2c"; reg = <0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; target-module@78000 { /* 0x48078000, ap 39 0a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "elm"; reg = <0x78000 0x4>, <0x78010 0x4>, <0x78014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x78000 0x1000>; elm: elm@0 { compatible = "ti,am3352-elm"; reg = <0x0 0xfc0>; /* device IO registers */ interrupts = ; status = "disabled"; }; }; target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x7a000 0x8>, <0x7a010 0x8>, <0x7a090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x7a000 0x1000>; i2c4: i2c@0 { compatible = "ti,omap4-i2c"; reg = <0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x7c000 0x8>, <0x7c010 0x8>, <0x7c090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x7c000 0x1000>; i2c5: i2c@0 { compatible = "ti,omap4-i2c"; reg = <0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; target-module@86000 { /* 0x48086000, ap 41 5e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer10"; reg = <0x86000 0x4>, <0x86010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x86000 0x1000>; timer10: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>; clock-names = "fck"; interrupts = ; }; }; target-module@88000 { /* 0x48088000, ap 43 66.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer11"; reg = <0x88000 0x4>, <0x88010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x88000 0x1000>; timer11: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>; clock-names = "fck"; interrupts = ; }; }; target-module@90000 { /* 0x48090000, ap 55 12.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "rng"; reg = <0x91fe0 0x4>, <0x91fe4 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , ; /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x90000 0x2000>; rng: rng@0 { compatible = "ti,omap4-rng"; reg = <0x0 0x2000>; interrupts = ; clocks = <&l3_iclk_div>; clock-names = "fck"; }; }; target-module@98000 { /* 0x48098000, ap 47 08.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x98000 0x4>, <0x98010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x98000 0x1000>; mcspi1: spi@0 { compatible = "ti,omap4-mcspi"; reg = <0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,spi-num-cs = <4>; dmas = <&sdma_xbar 35>, <&sdma_xbar 36>, <&sdma_xbar 37>, <&sdma_xbar 38>, <&sdma_xbar 39>, <&sdma_xbar 40>, <&sdma_xbar 41>, <&sdma_xbar 42>; dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3"; status = "disabled"; }; }; target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x9a000 0x4>, <0x9a010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9a000 0x1000>; mcspi2: spi@0 { compatible = "ti,omap4-mcspi"; reg = <0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,spi-num-cs = <2>; dmas = <&sdma_xbar 43>, <&sdma_xbar 44>, <&sdma_xbar 45>, <&sdma_xbar 46>; dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; }; target-module@9c000 { /* 0x4809c000, ap 51 38.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x9c000 0x4>, <0x9c010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9c000 0x1000>; mmc1: mmc@0 { compatible = "ti,dra7-sdhci"; reg = <0x0 0x400>; interrupts = ; status = "disabled"; pbias-supply = <&pbias_mmc_reg>; max-frequency = <192000000>; mmc-ddr-1_8v; mmc-ddr-3_3v; }; }; target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa2000 0x1000>; }; target-module@a4000 { /* 0x480a4000, ap 57 42.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x000a4000 0x00001000>, <0x00001000 0x000a5000 0x00001000>; }; - des_target: target-module@a5000 { /* 0x480a5000 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xa5030 0x4>, - <0xa5034 0x4>, - <0xa5038 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xa5000 0x00001000>; - - des: des@0 { - compatible = "ti,omap4-des"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; - dma-names = "tx", "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - }; - target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa8000 0x4000>; }; target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xad000 0x4>, <0xad010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xad000 0x1000>; mmc3: mmc@0 { compatible = "ti,dra7-sdhci"; reg = <0x0 0x400>; interrupts = ; status = "disabled"; /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ max-frequency = <64000000>; /* SDMA is not supported */ sdhci-caps-mask = <0x0 0x400000>; }; }; target-module@b2000 { /* 0x480b2000, ap 37 52.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "hdq1w"; reg = <0xb2000 0x4>, <0xb2014 0x4>, <0xb2018 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,syss-mask = <1>; ti,no-reset-on-init; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb2000 0x1000>; hdqw1w: 1w@0 { compatible = "ti,omap3-1w"; reg = <0x0 0x1000>; interrupts = ; }; }; target-module@b4000 { /* 0x480b4000, ap 65 40.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xb4000 0x4>, <0xb4010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb4000 0x1000>; mmc2: mmc@0 { compatible = "ti,dra7-sdhci"; reg = <0x0 0x400>; interrupts = ; status = "disabled"; max-frequency = <192000000>; /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */ sdhci-caps-mask = <0x7 0x0>; mmc-hs200-1_8v; mmc-ddr-1_8v; mmc-ddr-3_3v; }; }; target-module@b8000 { /* 0x480b8000, ap 67 48.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xb8000 0x4>, <0xb8010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb8000 0x1000>; mcspi3: spi@0 { compatible = "ti,omap4-mcspi"; reg = <0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,spi-num-cs = <2>; dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; dma-names = "tx0", "rx0"; status = "disabled"; }; }; target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xba000 0x4>, <0xba010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xba000 0x1000>; mcspi4: spi@0 { compatible = "ti,omap4-mcspi"; reg = <0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,spi-num-cs = <1>; dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; dma-names = "tx0", "rx0"; status = "disabled"; }; }; target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xd1000 0x4>, <0xd1010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd1000 0x1000>; mmc4: mmc@0 { compatible = "ti,dra7-sdhci"; reg = <0x0 0x400>; interrupts = ; status = "disabled"; max-frequency = <192000000>; /* SDMA is not supported */ sdhci-caps-mask = <0x0 0x400000>; }; }; target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd5000 0x1000>; }; }; segment@200000 { /* 0x48200000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; }; }; &l4_per2 { /* 0x48400000 */ compatible = "ti,dra7-l4-per2", "simple-bus"; reg = <0x48400000 0x800>, <0x48400800 0x800>, <0x48401000 0x400>, <0x48401400 0x400>, <0x48401800 0x400>; reg-names = "ap", "la", "ia0", "ia1", "ia2"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */ <0x45800000 0x45800000 0x400000>, /* L3 data port */ <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ <0x46000000 0x46000000 0x400000>, /* L3 data port */ <0x48436000 0x48436000 0x400000>, /* L3 data port */ <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ <0x48450000 0x48450000 0x400000>, /* L3 data port */ <0x48454000 0x48454000 0x400000>; /* L3 data port */ segment@0 { /* 0x48400000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00001000 0x00001000 0x000400>, /* ap 1 */ <0x00000800 0x00000800 0x000800>, /* ap 2 */ <0x00084000 0x00084000 0x004000>, /* ap 3 */ <0x00001400 0x00001400 0x000400>, /* ap 4 */ <0x00001800 0x00001800 0x000400>, /* ap 5 */ <0x00088000 0x00088000 0x001000>, /* ap 6 */ <0x0002c000 0x0002c000 0x001000>, /* ap 7 */ <0x0002d000 0x0002d000 0x001000>, /* ap 8 */ <0x00060000 0x00060000 0x002000>, /* ap 9 */ <0x00062000 0x00062000 0x001000>, /* ap 10 */ <0x00064000 0x00064000 0x002000>, /* ap 11 */ <0x00066000 0x00066000 0x001000>, /* ap 12 */ <0x00068000 0x00068000 0x002000>, /* ap 13 */ <0x0006a000 0x0006a000 0x001000>, /* ap 14 */ <0x0006c000 0x0006c000 0x002000>, /* ap 15 */ <0x0006e000 0x0006e000 0x001000>, /* ap 16 */ <0x00036000 0x00036000 0x001000>, /* ap 17 */ <0x00037000 0x00037000 0x001000>, /* ap 18 */ <0x00070000 0x00070000 0x002000>, /* ap 19 */ <0x00072000 0x00072000 0x001000>, /* ap 20 */ <0x0003a000 0x0003a000 0x001000>, /* ap 21 */ <0x0003b000 0x0003b000 0x001000>, /* ap 22 */ <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ <0x0003d000 0x0003d000 0x001000>, /* ap 24 */ <0x0003e000 0x0003e000 0x001000>, /* ap 25 */ <0x0003f000 0x0003f000 0x001000>, /* ap 26 */ <0x00040000 0x00040000 0x001000>, /* ap 27 */ <0x00041000 0x00041000 0x001000>, /* ap 28 */ <0x00042000 0x00042000 0x001000>, /* ap 29 */ <0x00043000 0x00043000 0x001000>, /* ap 30 */ <0x00080000 0x00080000 0x002000>, /* ap 31 */ <0x00082000 0x00082000 0x001000>, /* ap 32 */ <0x0004a000 0x0004a000 0x001000>, /* ap 33 */ <0x0004b000 0x0004b000 0x001000>, /* ap 34 */ <0x00074000 0x00074000 0x002000>, /* ap 35 */ <0x00076000 0x00076000 0x001000>, /* ap 36 */ <0x00050000 0x00050000 0x001000>, /* ap 37 */ <0x00051000 0x00051000 0x001000>, /* ap 38 */ <0x00078000 0x00078000 0x002000>, /* ap 39 */ <0x0007a000 0x0007a000 0x001000>, /* ap 40 */ <0x00054000 0x00054000 0x001000>, /* ap 41 */ <0x00055000 0x00055000 0x001000>, /* ap 42 */ <0x0007c000 0x0007c000 0x002000>, /* ap 43 */ <0x0007e000 0x0007e000 0x001000>, /* ap 44 */ <0x0004c000 0x0004c000 0x001000>, /* ap 45 */ <0x0004d000 0x0004d000 0x001000>, /* ap 46 */ <0x00020000 0x00020000 0x001000>, /* ap 47 */ <0x00021000 0x00021000 0x001000>, /* ap 48 */ <0x00022000 0x00022000 0x001000>, /* ap 49 */ <0x00023000 0x00023000 0x001000>, /* ap 50 */ <0x00024000 0x00024000 0x001000>, /* ap 51 */ <0x00025000 0x00025000 0x001000>, /* ap 52 */ <0x00046000 0x00046000 0x001000>, /* ap 53 */ <0x00047000 0x00047000 0x001000>, /* ap 54 */ <0x00048000 0x00048000 0x001000>, /* ap 55 */ <0x00049000 0x00049000 0x001000>, /* ap 56 */ <0x00058000 0x00058000 0x002000>, /* ap 57 */ <0x0005a000 0x0005a000 0x001000>, /* ap 58 */ <0x0005b000 0x0005b000 0x001000>, /* ap 59 */ <0x0005c000 0x0005c000 0x001000>, /* ap 60 */ <0x0005d000 0x0005d000 0x001000>, /* ap 61 */ <0x0005e000 0x0005e000 0x001000>, /* ap 62 */ <0x45800000 0x45800000 0x400000>, /* L3 data port */ <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ <0x46000000 0x46000000 0x400000>, /* L3 data port */ <0x48436000 0x48436000 0x400000>, /* L3 data port */ <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ <0x48450000 0x48450000 0x400000>, /* L3 data port */ <0x48454000 0x48454000 0x400000>; /* L3 data port */ target-module@20000 { /* 0x48420000, ap 47 02.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x20050 0x4>, <0x20054 0x4>, <0x20058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x1000>; uart7: serial@0 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; status = "disabled"; }; }; target-module@22000 { /* 0x48422000, ap 49 0a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x22050 0x4>, <0x22054 0x4>, <0x22058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x22000 0x1000>; uart8: serial@0 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; status = "disabled"; }; }; target-module@24000 { /* 0x48424000, ap 51 12.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x24050 0x4>, <0x24054 0x4>, <0x24058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x24000 0x1000>; uart9: serial@0 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; status = "disabled"; }; }; target-module@2c000 { /* 0x4842c000, ap 7 18.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2c000 0x1000>; }; target-module@36000 { /* 0x48436000, ap 17 06.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x36000 0x1000>; }; target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3a000 0x1000>; }; atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x3c000 0x4>; reg-names = "rev"; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3c000 0x1000>; atl: atl@0 { compatible = "ti,dra7-atl"; reg = <0x0 0x3ff>; ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, <&atl_clkin2_ck>, <&atl_clkin3_ck>; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; clock-names = "fck"; status = "disabled"; }; }; target-module@3e000 { /* 0x4843e000, ap 25 30.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss0"; reg = <0x3e000 0x4>, <0x3e004 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3e000 0x1000>; epwmss0: epwmss@0 { compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; reg = <0x0 0x30>; #address-cells = <1>; #size-cells = <1>; status = "disabled"; ranges = <0 0 0x1000>; ecap0: ecap@100 { compatible = "ti,dra746-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4_root_clk_div>; clock-names = "fck"; status = "disabled"; }; ehrpwm0: pwm@200 { compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; clock-names = "tbclk", "fck"; status = "disabled"; }; }; }; target-module@40000 { /* 0x48440000, ap 27 38.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss1"; reg = <0x40000 0x4>, <0x40004 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x40000 0x1000>; epwmss1: epwmss@0 { compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; reg = <0x0 0x30>; #address-cells = <1>; #size-cells = <1>; status = "disabled"; ranges = <0 0 0x1000>; ecap1: ecap@100 { compatible = "ti,dra746-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4_root_clk_div>; clock-names = "fck"; status = "disabled"; }; ehrpwm1: pwm@200 { compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; clock-names = "tbclk", "fck"; status = "disabled"; }; }; }; target-module@42000 { /* 0x48442000, ap 29 20.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss2"; reg = <0x42000 0x4>, <0x42004 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x42000 0x1000>; epwmss2: epwmss@0 { compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; reg = <0x0 0x30>; #address-cells = <1>; #size-cells = <1>; status = "disabled"; ranges = <0 0 0x1000>; ecap2: ecap@100 { compatible = "ti,dra746-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4_root_clk_div>; clock-names = "fck"; status = "disabled"; }; ehrpwm2: pwm@200 { compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; clock-names = "tbclk", "fck"; status = "disabled"; }; }; }; target-module@46000 { /* 0x48446000, ap 53 40.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x46000 0x1000>; }; target-module@48000 { /* 0x48448000, ap 55 48.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x48000 0x1000>; }; target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4a000 0x1000>; }; target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4c000 0x1000>; }; target-module@50000 { /* 0x48450000, ap 37 24.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x50000 0x1000>; }; target-module@54000 { /* 0x48454000, ap 41 2c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x54000 0x1000>; }; target-module@58000 { /* 0x48458000, ap 57 28.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x58000 0x2000>; }; target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5b000 0x1000>; }; target-module@5d000 { /* 0x4845d000, ap 61 22.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5d000 0x1000>; }; target-module@60000 { /* 0x48460000, ap 9 0e.0 */ compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; reg = <0x60000 0x4>, <0x60004 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , ; /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x60000 0x2000>, <0x45800000 0x45800000 0x400000>; mcasp1: mcasp@0 { compatible = "ti,dra7-mcasp-audio"; reg = <0x0 0x2000>, <0x45800000 0x1000>; /* L3 data port */ reg-names = "mpu","dat"; interrupts = , ; interrupt-names = "tx", "rx"; dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; dma-names = "tx", "rx"; clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; status = "disabled"; }; }; target-module@64000 { /* 0x48464000, ap 11 1e.0 */ compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; reg = <0x64000 0x4>, <0x64004 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , ; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x64000 0x2000>, <0x45c00000 0x45c00000 0x400000>; mcasp2: mcasp@0 { compatible = "ti,dra7-mcasp-audio"; reg = <0x0 0x2000>, <0x45c00000 0x1000>; /* L3 data port */ reg-names = "mpu","dat"; interrupts = , ; interrupt-names = "tx", "rx"; dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; status = "disabled"; }; }; target-module@68000 { /* 0x48468000, ap 13 26.0 */ compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; reg = <0x68000 0x4>, <0x68004 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , ; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x68000 0x2000>, <0x46000000 0x46000000 0x400000>; mcasp3: mcasp@0 { compatible = "ti,dra7-mcasp-audio"; reg = <0x0 0x2000>, <0x46000000 0x1000>; /* L3 data port */ reg-names = "mpu","dat"; interrupts = , ; interrupt-names = "tx", "rx"; dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; }; target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */ compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; reg = <0x6c000 0x4>, <0x6c004 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , ; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6c000 0x2000>, <0x48436000 0x48436000 0x400000>; mcasp4: mcasp@0 { compatible = "ti,dra7-mcasp-audio"; reg = <0x0 0x2000>, <0x48436000 0x1000>; /* L3 data port */ reg-names = "mpu","dat"; interrupts = , ; interrupt-names = "tx", "rx"; dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; }; target-module@70000 { /* 0x48470000, ap 19 36.0 */ compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; reg = <0x70000 0x4>, <0x70004 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , ; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x70000 0x2000>, <0x4843a000 0x4843a000 0x400000>; mcasp5: mcasp@0 { compatible = "ti,dra7-mcasp-audio"; reg = <0x0 0x2000>, <0x4843a000 0x1000>; /* L3 data port */ reg-names = "mpu","dat"; interrupts = , ; interrupt-names = "tx", "rx"; dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; }; target-module@74000 { /* 0x48474000, ap 35 14.0 */ compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; reg = <0x74000 0x4>, <0x74004 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , ; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x74000 0x2000>, <0x4844c000 0x4844c000 0x400000>; mcasp6: mcasp@0 { compatible = "ti,dra7-mcasp-audio"; reg = <0x0 0x2000>, <0x4844c000 0x1000>; /* L3 data port */ reg-names = "mpu","dat"; interrupts = , ; interrupt-names = "tx", "rx"; dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; }; target-module@78000 { /* 0x48478000, ap 39 0c.0 */ compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; reg = <0x78000 0x4>, <0x78004 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , ; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x78000 0x2000>, <0x48450000 0x48450000 0x400000>; mcasp7: mcasp@0 { compatible = "ti,dra7-mcasp-audio"; reg = <0x0 0x2000>, <0x48450000 0x1000>; /* L3 data port */ reg-names = "mpu","dat"; interrupts = , ; interrupt-names = "tx", "rx"; dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; }; target-module@7c000 { /* 0x4847c000, ap 43 04.0 */ compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; reg = <0x7c000 0x4>, <0x7c004 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , ; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x7c000 0x2000>, <0x48454000 0x48454000 0x400000>; mcasp8: mcasp@0 { compatible = "ti,dra7-mcasp-audio"; reg = <0x0 0x2000>, <0x48454000 0x1000>; /* L3 data port */ reg-names = "mpu","dat"; interrupts = , ; interrupt-names = "tx", "rx"; dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; }; target-module@80000 { /* 0x48480000, ap 31 16.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x80020 0x4>; reg-names = "rev"; clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000 0x2000>; dcan2: can@0 { compatible = "ti,dra7-d_can"; reg = <0x0 0x2000>; syscon-raminit = <&scm_conf 0x558 1>; interrupts = ; clocks = <&sys_clkin1>; status = "disabled"; }; }; target-module@84000 { /* 0x48484000, ap 3 10.0 */ compatible = "ti,sysc-omap4-simple", "ti,sysc"; reg = <0x85200 0x4>, <0x85208 0x4>, <0x85204 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <0>; ti,sysc-midle = , ; ti,sysc-sidle = , ; ti,syss-mask = <1>; clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x84000 0x4000>; /* * Do not allow gating of cpsw clock as workaround * for errata i877. Keeping internal clock disabled * causes the device switching characteristics * to degrade over time and eventually fail to meet * the data manual delay time/skew specs. */ ti,no-idle; mac: ethernet@0 { compatible = "ti,dra7-cpsw","ti,cpsw"; clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; clock-names = "fck", "cpts"; cpdma_channels = <8>; ale_entries = <1024>; bd_ram_size = <0x2000>; mac_control = <0x20>; slaves = <2>; active_slave = <0>; cpts_clock_mult = <0x784CFE14>; cpts_clock_shift = <29>; reg = <0x0 0x1000 0x1200 0x2e00>; #address-cells = <1>; #size-cells = <1>; /* * rx_thresh_pend * rx_pend * tx_pend * misc_pend */ interrupts = , , , ; ranges = <0 0 0x4000>; syscon = <&scm_conf>; status = "disabled"; davinci_mdio: mdio@1000 { compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - clocks = <&gmac_main_clk>; + clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; reg = <0x1000 0x100>; }; cpsw_emac0: slave@200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; phys = <&phy_gmii_sel 1>; }; cpsw_emac1: slave@300 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; phys = <&phy_gmii_sel 2>; }; }; - - mac_sw: switch@0 { - compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch"; - reg = <0x0 0x4000>; - ranges = <0 0 0x4000>; - clocks = <&gmac_main_clk>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - syscon = <&scm_conf>; - status = "disabled"; - - interrupts = , - , - , - ; - interrupt-names = "rx_thresh", "rx", "tx", "misc"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - label = "port1"; - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 1>; - }; - - cpsw_port2: port@2 { - reg = <2>; - label = "port2"; - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 2>; - }; - }; - - davinci_mdio_sw: mdio@1000 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - clocks = <&gmac_main_clk>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - reg = <0x1000 0x100>; - }; - - cpts { - clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; - clock-names = "cpts"; - }; - }; }; }; }; &l4_per3 { /* 0x48800000 */ compatible = "ti,dra7-l4-per3", "simple-bus"; reg = <0x48800000 0x800>, <0x48800800 0x800>, <0x48801000 0x400>, <0x48801400 0x400>, <0x48801800 0x400>; reg-names = "ap", "la", "ia0", "ia1", "ia2"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */ segment@0 { /* 0x48800000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00000800 0x00000800 0x000800>, /* ap 1 */ <0x00001000 0x00001000 0x000400>, /* ap 2 */ <0x00001400 0x00001400 0x000400>, /* ap 3 */ <0x00001800 0x00001800 0x000400>, /* ap 4 */ <0x00020000 0x00020000 0x001000>, /* ap 5 */ <0x00021000 0x00021000 0x001000>, /* ap 6 */ <0x00022000 0x00022000 0x001000>, /* ap 7 */ <0x00023000 0x00023000 0x001000>, /* ap 8 */ <0x00024000 0x00024000 0x001000>, /* ap 9 */ <0x00025000 0x00025000 0x001000>, /* ap 10 */ <0x00026000 0x00026000 0x001000>, /* ap 11 */ <0x00027000 0x00027000 0x001000>, /* ap 12 */ <0x00028000 0x00028000 0x001000>, /* ap 13 */ <0x00029000 0x00029000 0x001000>, /* ap 14 */ <0x0002a000 0x0002a000 0x001000>, /* ap 15 */ <0x0002b000 0x0002b000 0x001000>, /* ap 16 */ <0x0002c000 0x0002c000 0x001000>, /* ap 17 */ <0x0002d000 0x0002d000 0x001000>, /* ap 18 */ <0x0002e000 0x0002e000 0x001000>, /* ap 19 */ <0x0002f000 0x0002f000 0x001000>, /* ap 20 */ <0x00170000 0x00170000 0x010000>, /* ap 21 */ <0x00180000 0x00180000 0x001000>, /* ap 22 */ <0x00190000 0x00190000 0x010000>, /* ap 23 */ <0x001a0000 0x001a0000 0x001000>, /* ap 24 */ <0x001b0000 0x001b0000 0x010000>, /* ap 25 */ <0x001c0000 0x001c0000 0x001000>, /* ap 26 */ <0x001d0000 0x001d0000 0x010000>, /* ap 27 */ <0x001e0000 0x001e0000 0x001000>, /* ap 28 */ <0x00038000 0x00038000 0x001000>, /* ap 29 */ <0x00039000 0x00039000 0x001000>, /* ap 30 */ <0x0005c000 0x0005c000 0x001000>, /* ap 31 */ <0x0005d000 0x0005d000 0x001000>, /* ap 32 */ <0x0003a000 0x0003a000 0x001000>, /* ap 33 */ <0x0003b000 0x0003b000 0x001000>, /* ap 34 */ <0x0003c000 0x0003c000 0x001000>, /* ap 35 */ <0x0003d000 0x0003d000 0x001000>, /* ap 36 */ <0x0003e000 0x0003e000 0x001000>, /* ap 37 */ <0x0003f000 0x0003f000 0x001000>, /* ap 38 */ <0x00040000 0x00040000 0x001000>, /* ap 39 */ <0x00041000 0x00041000 0x001000>, /* ap 40 */ <0x00042000 0x00042000 0x001000>, /* ap 41 */ <0x00043000 0x00043000 0x001000>, /* ap 42 */ <0x00044000 0x00044000 0x001000>, /* ap 43 */ <0x00045000 0x00045000 0x001000>, /* ap 44 */ <0x00046000 0x00046000 0x001000>, /* ap 45 */ <0x00047000 0x00047000 0x001000>, /* ap 46 */ <0x00048000 0x00048000 0x001000>, /* ap 47 */ <0x00049000 0x00049000 0x001000>, /* ap 48 */ <0x0004a000 0x0004a000 0x001000>, /* ap 49 */ <0x0004b000 0x0004b000 0x001000>, /* ap 50 */ <0x0004c000 0x0004c000 0x001000>, /* ap 51 */ <0x0004d000 0x0004d000 0x001000>, /* ap 52 */ <0x0004e000 0x0004e000 0x001000>, /* ap 53 */ <0x0004f000 0x0004f000 0x001000>, /* ap 54 */ <0x00050000 0x00050000 0x001000>, /* ap 55 */ <0x00051000 0x00051000 0x001000>, /* ap 56 */ <0x00052000 0x00052000 0x001000>, /* ap 57 */ <0x00053000 0x00053000 0x001000>, /* ap 58 */ <0x00054000 0x00054000 0x001000>, /* ap 59 */ <0x00055000 0x00055000 0x001000>, /* ap 60 */ <0x00056000 0x00056000 0x001000>, /* ap 61 */ <0x00057000 0x00057000 0x001000>, /* ap 62 */ <0x00058000 0x00058000 0x001000>, /* ap 63 */ <0x00059000 0x00059000 0x001000>, /* ap 64 */ <0x0005a000 0x0005a000 0x001000>, /* ap 65 */ <0x0005b000 0x0005b000 0x001000>, /* ap 66 */ <0x00064000 0x00064000 0x001000>, /* ap 67 */ <0x00065000 0x00065000 0x001000>, /* ap 68 */ <0x0005e000 0x0005e000 0x001000>, /* ap 69 */ <0x0005f000 0x0005f000 0x001000>, /* ap 70 */ <0x00060000 0x00060000 0x001000>, /* ap 71 */ <0x00061000 0x00061000 0x001000>, /* ap 72 */ <0x00062000 0x00062000 0x001000>, /* ap 73 */ <0x00063000 0x00063000 0x001000>, /* ap 74 */ <0x00140000 0x00140000 0x020000>, /* ap 75 */ <0x00160000 0x00160000 0x001000>, /* ap 76 */ <0x00016000 0x00016000 0x001000>, /* ap 77 */ <0x00017000 0x00017000 0x001000>, /* ap 78 */ <0x000c0000 0x000c0000 0x020000>, /* ap 79 */ <0x000e0000 0x000e0000 0x001000>, /* ap 80 */ <0x00004000 0x00004000 0x001000>, /* ap 81 */ <0x00005000 0x00005000 0x001000>, /* ap 82 */ <0x00080000 0x00080000 0x020000>, /* ap 83 */ <0x000a0000 0x000a0000 0x001000>, /* ap 84 */ <0x00100000 0x00100000 0x020000>, /* ap 85 */ <0x00120000 0x00120000 0x001000>, /* ap 86 */ <0x00010000 0x00010000 0x001000>, /* ap 87 */ <0x00011000 0x00011000 0x001000>, /* ap 88 */ <0x0000a000 0x0000a000 0x001000>, /* ap 89 */ <0x0000b000 0x0000b000 0x001000>, /* ap 90 */ <0x0001c000 0x0001c000 0x001000>, /* ap 91 */ <0x0001d000 0x0001d000 0x001000>, /* ap 92 */ <0x0001e000 0x0001e000 0x001000>, /* ap 93 */ <0x0001f000 0x0001f000 0x001000>, /* ap 94 */ <0x00002000 0x00002000 0x001000>, /* ap 95 */ <0x00003000 0x00003000 0x001000>; /* ap 96 */ target-module@2000 { /* 0x48802000, ap 95 7c.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox13"; reg = <0x2000 0x4>, <0x2010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x1000>; mailbox13: mailbox@0 { compatible = "ti,omap4-mailbox"; reg = <0x0 0x200>; interrupts = , , , ; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; }; }; target-module@4000 { /* 0x48804000, ap 81 20.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; }; target-module@a000 { /* 0x4880a000, ap 89 18.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa000 0x1000>; }; target-module@10000 { /* 0x48810000, ap 87 28.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x10000 0x1000>; }; target-module@16000 { /* 0x48816000, ap 77 1e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x16000 0x1000>; }; target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1c000 0x1000>; }; target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1e000 0x1000>; }; target-module@20000 { /* 0x48820000, ap 5 08.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer5"; reg = <0x20000 0x4>, <0x20010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x1000>; timer5: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>; clock-names = "fck"; interrupts = ; }; }; target-module@22000 { /* 0x48822000, ap 7 24.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer6"; reg = <0x22000 0x4>, <0x22010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x22000 0x1000>; timer6: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>; clock-names = "fck"; interrupts = ; }; }; target-module@24000 { /* 0x48824000, ap 9 26.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer7"; reg = <0x24000 0x4>, <0x24010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x24000 0x1000>; timer7: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>; clock-names = "fck"; interrupts = ; }; }; target-module@26000 { /* 0x48826000, ap 11 0c.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer8"; reg = <0x26000 0x4>, <0x26010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x26000 0x1000>; timer8: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>; clock-names = "fck"; interrupts = ; }; }; target-module@28000 { /* 0x48828000, ap 13 16.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer13"; reg = <0x28000 0x4>, <0x28010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x28000 0x1000>; timer13: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>; clock-names = "fck"; interrupts = ; - ti,timer-pwm; }; }; target-module@2a000 { /* 0x4882a000, ap 15 10.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer14"; reg = <0x2a000 0x4>, <0x2a010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2a000 0x1000>; timer14: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>; clock-names = "fck"; interrupts = ; - ti,timer-pwm; }; }; target-module@2c000 { /* 0x4882c000, ap 17 02.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer15"; reg = <0x2c000 0x4>, <0x2c010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2c000 0x1000>; timer15: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>; clock-names = "fck"; interrupts = ; - ti,timer-pwm; }; }; target-module@2e000 { /* 0x4882e000, ap 19 14.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer16"; reg = <0x2e000 0x4>, <0x2e010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2e000 0x1000>; timer16: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>; clock-names = "fck"; interrupts = ; - ti,timer-pwm; }; }; rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */ compatible = "ti,sysc-omap4-simple", "ti,sysc"; ti,hwmods = "rtcss"; reg = <0x38074 0x4>, <0x38078 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , , ; /* Domains (P, C): rtc_pwrdm, rtc_clkdm */ clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x38000 0x1000>; rtc: rtc@0 { compatible = "ti,am3352-rtc"; reg = <0x0 0x100>; interrupts = , ; clocks = <&sys_32k_ck>; }; }; target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox2"; reg = <0x3a000 0x4>, <0x3a010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3a000 0x1000>; mailbox2: mailbox@0 { compatible = "ti,omap4-mailbox"; reg = <0x0 0x200>; interrupts = , , , ; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; }; }; target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox3"; reg = <0x3c000 0x4>, <0x3c010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3c000 0x1000>; mailbox3: mailbox@0 { compatible = "ti,omap4-mailbox"; reg = <0x0 0x200>; interrupts = , , , ; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; }; }; target-module@3e000 { /* 0x4883e000, ap 37 46.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox4"; reg = <0x3e000 0x4>, <0x3e010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3e000 0x1000>; mailbox4: mailbox@0 { compatible = "ti,omap4-mailbox"; reg = <0x0 0x200>; interrupts = , , , ; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; }; }; target-module@40000 { /* 0x48840000, ap 39 64.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox5"; reg = <0x40000 0x4>, <0x40010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x40000 0x1000>; mailbox5: mailbox@0 { compatible = "ti,omap4-mailbox"; reg = <0x0 0x200>; interrupts = , , , ; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; }; }; target-module@42000 { /* 0x48842000, ap 41 4e.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox6"; reg = <0x42000 0x4>, <0x42010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x42000 0x1000>; mailbox6: mailbox@0 { compatible = "ti,omap4-mailbox"; reg = <0x0 0x200>; interrupts = , , , ; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; }; }; target-module@44000 { /* 0x48844000, ap 43 42.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox7"; reg = <0x44000 0x4>, <0x44010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x44000 0x1000>; mailbox7: mailbox@0 { compatible = "ti,omap4-mailbox"; reg = <0x0 0x200>; interrupts = , , , ; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; }; }; target-module@46000 { /* 0x48846000, ap 45 48.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox8"; reg = <0x46000 0x4>, <0x46010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x46000 0x1000>; mailbox8: mailbox@0 { compatible = "ti,omap4-mailbox"; reg = <0x0 0x200>; interrupts = , , , ; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; }; }; target-module@48000 { /* 0x48848000, ap 47 36.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x48000 0x1000>; }; target-module@4a000 { /* 0x4884a000, ap 49 38.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4a000 0x1000>; }; target-module@4c000 { /* 0x4884c000, ap 51 44.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4c000 0x1000>; }; target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4e000 0x1000>; }; target-module@50000 { /* 0x48850000, ap 55 40.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x50000 0x1000>; }; target-module@52000 { /* 0x48852000, ap 57 54.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x52000 0x1000>; }; target-module@54000 { /* 0x48854000, ap 59 1a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x54000 0x1000>; }; target-module@56000 { /* 0x48856000, ap 61 22.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x56000 0x1000>; }; target-module@58000 { /* 0x48858000, ap 63 2a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x58000 0x1000>; }; target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5a000 0x1000>; }; target-module@5c000 { /* 0x4885c000, ap 31 32.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5c000 0x1000>; }; target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox9"; reg = <0x5e000 0x4>, <0x5e010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5e000 0x1000>; mailbox9: mailbox@0 { compatible = "ti,omap4-mailbox"; reg = <0x0 0x200>; interrupts = , , , ; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; }; }; target-module@60000 { /* 0x48860000, ap 71 4a.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox10"; reg = <0x60000 0x4>, <0x60010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x60000 0x1000>; mailbox10: mailbox@0 { compatible = "ti,omap4-mailbox"; reg = <0x0 0x200>; interrupts = , , , ; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; }; }; target-module@62000 { /* 0x48862000, ap 73 74.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox11"; reg = <0x62000 0x4>, <0x62010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x62000 0x1000>; mailbox11: mailbox@0 { compatible = "ti,omap4-mailbox"; reg = <0x0 0x200>; interrupts = , , , ; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; }; }; target-module@64000 { /* 0x48864000, ap 67 52.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox12"; reg = <0x64000 0x4>, <0x64010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x64000 0x1000>; mailbox12: mailbox@0 { compatible = "ti,omap4-mailbox"; reg = <0x0 0x200>; interrupts = , , , ; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; }; }; target-module@80000 { /* 0x48880000, ap 83 0e.1 */ compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "usb_otg_ss1"; reg = <0x80000 0x4>, <0x80010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000 0x20000>; omap_dwc3_1: omap_dwc3_1@0 { compatible = "ti,dwc3"; reg = <0x0 0x10000>; interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; ranges = <0 0 0x20000>; usb1: usb@10000 { compatible = "snps,dwc3"; reg = <0x10000 0x17000>; interrupts = , , ; interrupt-names = "peripheral", "host", "otg"; phys = <&usb2_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; maximum-speed = "super-speed"; dr_mode = "otg"; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; }; }; }; target-module@c0000 { /* 0x488c0000, ap 79 06.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "usb_otg_ss2"; reg = <0xc0000 0x4>, <0xc0010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc0000 0x20000>; omap_dwc3_2: omap_dwc3_2@0 { compatible = "ti,dwc3"; reg = <0x0 0x10000>; interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; ranges = <0 0 0x20000>; usb2: usb@10000 { compatible = "snps,dwc3"; reg = <0x10000 0x17000>; interrupts = , , ; interrupt-names = "peripheral", "host", "otg"; phys = <&usb2_phy2>; phy-names = "usb2-phy"; maximum-speed = "high-speed"; dr_mode = "otg"; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; snps,dis_metastability_quirk; }; }; }; usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "usb_otg_ss3"; reg = <0x100000 0x4>, <0x100010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x100000 0x20000>; omap_dwc3_3: omap_dwc3_3@0 { compatible = "ti,dwc3"; reg = <0x0 0x10000>; interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; ranges = <0 0 0x20000>; status = "disabled"; usb3: usb@10000 { compatible = "snps,dwc3"; reg = <0x10000 0x17000>; interrupts = , , ; interrupt-names = "peripheral", "host", "otg"; maximum-speed = "high-speed"; dr_mode = "otg"; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; }; }; }; usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "usb_otg_ss4"; reg = <0x140000 0x4>, <0x140010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x140000 0x20000>; }; target-module@170000 { /* 0x48970000, ap 21 0a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x170010 0x4>; - reg-names = "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>; - clock-names = "fck"; + compatible = "ti,sysc"; + status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x170000 0x10000>; - status = "disabled"; }; target-module@190000 { /* 0x48990000, ap 23 2e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x190010 0x4>; - reg-names = "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; - clock-names = "fck"; + compatible = "ti,sysc"; + status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x190000 0x10000>; - status = "disabled"; }; target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x1b0000 0x4>, - <0x1b0010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; - clock-names = "fck"; + compatible = "ti,sysc"; + status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1b0000 0x10000>; - status = "disabled"; }; - target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x1d0010 0x4>; - reg-names = "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>; - clock-names = "fck"; + target-module@1d0000 { /* 0x489d0000, ap 27 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1d0000 0x10000>; - - vpe: vpe@0 { - compatible = "ti,dra7-vpe"; - reg = <0x0000 0x120>, - <0x0700 0x80>, - <0x5700 0x18>, - <0xd000 0x400>; - reg-names = "vpe_top", - "sc", - "csc", - "vpdma"; - interrupts = ; - }; }; }; }; &l4_wkup { /* 0x4ae00000 */ compatible = "ti,dra7-l4-wkup", "simple-bus"; reg = <0x4ae00000 0x800>, <0x4ae00800 0x800>, <0x4ae01000 0x1000>; reg-names = "ap", "la", "ia0"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ <0x00020000 0x4ae20000 0x010000>, /* segment 2 */ <0x00030000 0x4ae30000 0x010000>; /* segment 3 */ segment@0 { /* 0x4ae00000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00001000 0x00001000 0x001000>, /* ap 1 */ <0x00000800 0x00000800 0x000800>, /* ap 2 */ <0x00006000 0x00006000 0x002000>, /* ap 3 */ <0x00008000 0x00008000 0x001000>, /* ap 4 */ <0x00004000 0x00004000 0x001000>, /* ap 15 */ <0x00005000 0x00005000 0x001000>, /* ap 16 */ <0x0000c000 0x0000c000 0x001000>, /* ap 17 */ <0x0000d000 0x0000d000 0x001000>; /* ap 18 */ target-module@4000 { /* 0x4ae04000, ap 15 40.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "counter_32k"; reg = <0x4000 0x4>, <0x4010 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , , ; /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; counter32k: counter@0 { compatible = "ti,omap-counter32k"; reg = <0x0 0x40>; }; }; target-module@6000 { /* 0x4ae06000, ap 3 10.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x6000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6000 0x2000>; prm: prm@0 { compatible = "ti,dra7-prm", "simple-bus"; reg = <0 0x3000>; interrupts = ; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x3000>; prm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; prm_clockdomains: clockdomains { }; }; }; target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xc000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc000 0x1000>; scm_wkup: scm_conf@0 { compatible = "syscon"; reg = <0 0x1000>; }; }; }; segment@10000 { /* 0x4ae10000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ <0x00001000 0x00011000 0x001000>, /* ap 6 */ <0x00004000 0x00014000 0x001000>, /* ap 7 */ <0x00005000 0x00015000 0x001000>, /* ap 8 */ <0x00008000 0x00018000 0x001000>, /* ap 9 */ <0x00009000 0x00019000 0x001000>, /* ap 10 */ <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ target-module@0 { /* 0x4ae10000, ap 5 20.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x0 0x4>, <0x10 0x4>, <0x114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>, <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x1000>; gpio1: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@4000 { /* 0x4ae14000, ap 7 28.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "wd_timer2"; reg = <0x4000 0x4>, <0x4010 0x4>, <0x4014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; wdt2: wdt@0 { compatible = "ti,omap3-wdt"; reg = <0x0 0x80>; interrupts = ; }; }; target-module@8000 { /* 0x4ae18000, ap 9 30.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; ti,hwmods = "timer1"; reg = <0x8000 0x4>, <0x8010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x1000>; timer1: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; clock-names = "fck"; interrupts = ; ti,timer-alwon; }; }; target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc000 0x1000>; }; }; segment@20000 { /* 0x4ae20000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ <0x00000000 0x00020000 0x001000>, /* ap 19 */ <0x00001000 0x00021000 0x001000>, /* ap 20 */ <0x00002000 0x00022000 0x001000>, /* ap 21 */ <0x00003000 0x00023000 0x001000>, /* ap 22 */ <0x00007000 0x00027000 0x000400>, /* ap 23 */ <0x00008000 0x00028000 0x000800>, /* ap 24 */ <0x00009000 0x00029000 0x000100>, /* ap 25 */ <0x00008800 0x00028800 0x000200>, /* ap 26 */ <0x00008a00 0x00028a00 0x000100>, /* ap 27 */ <0x0000b000 0x0002b000 0x001000>, /* ap 28 */ <0x0000c000 0x0002c000 0x001000>, /* ap 29 */ <0x0000f000 0x0002f000 0x001000>; /* ap 32 */ target-module@0 { /* 0x4ae20000, ap 19 08.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer12"; reg = <0x0 0x4>, <0x10 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x1000>; timer12: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; interrupts = ; ti,timer-alwon; ti,timer-secure; }; }; target-module@2000 { /* 0x4ae22000, ap 21 18.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x1000>; }; target-module@6000 { /* 0x4ae26000, ap 13 48.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00006000 0x00001000>, <0x00001000 0x00007000 0x00000400>, <0x00002000 0x00008000 0x00000800>, <0x00002800 0x00008800 0x00000200>, <0x00002a00 0x00008a00 0x00000100>, <0x00003000 0x00009000 0x00000100>; }; target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0xb050 0x4>, <0xb054 0x4>, <0xb058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb000 0x1000>; uart10: serial@0 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; status = "disabled"; }; }; target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xf000 0x1000>; }; }; segment@30000 { /* 0x4ae30000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */ <0x0000e000 0x0003e000 0x001000>, /* ap 31 */ <0x00000000 0x00030000 0x001000>, /* ap 33 */ <0x00001000 0x00031000 0x001000>, /* ap 34 */ <0x00002000 0x00032000 0x001000>, /* ap 35 */ <0x00003000 0x00033000 0x001000>, /* ap 36 */ <0x00004000 0x00034000 0x001000>, /* ap 37 */ <0x00005000 0x00035000 0x001000>, /* ap 38 */ <0x00006000 0x00036000 0x001000>, /* ap 39 */ <0x00007000 0x00037000 0x001000>, /* ap 40 */ <0x00008000 0x00038000 0x001000>, /* ap 41 */ <0x00009000 0x00039000 0x001000>, /* ap 42 */ <0x0000a000 0x0003a000 0x001000>; /* ap 43 */ target-module@1000 { /* 0x4ae31000, ap 34 60.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1000 0x1000>; }; target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3000 0x1000>; }; target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5000 0x1000>; }; target-module@7000 { /* 0x4ae37000, ap 40 68.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x7000 0x1000>; }; target-module@9000 { /* 0x4ae39000, ap 42 70.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9000 0x1000>; }; target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xc020 0x4>; reg-names = "rev"; clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc000 0x2000>; dcan1: can@0 { compatible = "ti,dra7-d_can"; reg = <0x0 0x2000>; syscon-raminit = <&scm_conf 0x558 0>; interrupts = ; clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>; status = "disabled"; }; }; }; }; diff --git a/sys/gnu/dts/arm/dra7.dtsi b/sys/gnu/dts/arm/dra7.dtsi index 5f5ee16f07a3..953f0ffce2a9 100644 --- a/sys/gnu/dts/arm/dra7.dtsi +++ b/sys/gnu/dts/arm/dra7.dtsi @@ -1,961 +1,765 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ * * Based on "omap4.dtsi" */ #include #include #include #include #include #define MAX_SOURCES 400 / { #address-cells = <2>; #size-cells = <2>; compatible = "ti,dra7xx"; interrupt-parent = <&crossbar_mpu>; chosen { }; aliases { i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; i2c4 = &i2c5; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; serial5 = &uart6; serial6 = &uart7; serial7 = &uart8; serial8 = &uart9; serial9 = &uart10; ethernet0 = &cpsw_emac0; ethernet1 = &cpsw_emac1; d_can0 = &dcan1; d_can1 = &dcan2; spi0 = &qspi; }; timer { compatible = "arm,armv7-timer"; interrupts = , , , ; interrupt-parent = <&gic>; }; gic: interrupt-controller@48211000 { compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; reg = <0x0 0x48211000 0x0 0x1000>, <0x0 0x48212000 0x0 0x2000>, <0x0 0x48214000 0x0 0x2000>, <0x0 0x48216000 0x0 0x2000>; interrupts = ; interrupt-parent = <&gic>; }; wakeupgen: interrupt-controller@48281000 { compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; interrupt-controller; #interrupt-cells = <3>; reg = <0x0 0x48281000 0x0 0x1000>; interrupt-parent = <&gic>; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; operating-points-v2 = <&cpu0_opp_table>; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; clock-latency = <300000>; /* From omap-cpufreq driver */ /* cooling options */ #cooling-cells = <2>; /* min followed by max */ vbb-supply = <&abb_mpu>; }; }; cpu0_opp_table: opp-table { compatible = "operating-points-v2-ti-cpu"; syscon = <&scm_wkup>; opp_nom-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <1060000 850000 1150000>, <1060000 850000 1150000>; opp-supported-hw = <0xFF 0x01>; opp-suspend; }; opp_od-1176000000 { opp-hz = /bits/ 64 <1176000000>; opp-microvolt = <1160000 885000 1160000>, <1160000 885000 1160000>; opp-supported-hw = <0xFF 0x02>; }; opp_high@1500000000 { opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <1210000 950000 1250000>, <1210000 950000 1250000>; opp-supported-hw = <0xFF 0x04>; }; }; /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself. */ soc { compatible = "ti,omap-infra"; mpu { compatible = "ti,omap5-mpu"; ti,hwmods = "mpu"; }; }; /* * XXX: Use a flat representation of the SOC interconnect. * The real OMAP interconnect network is quite complex. * Since it will not bring real advantage to represent that in DT for * the moment, just use a fake OCP bus entry to represent the whole bus * hierarchy. */ ocp { compatible = "ti,dra7-l3-noc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0xc0000000>; - dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; ti,hwmods = "l3_main_1", "l3_main_2"; reg = <0x0 0x44000000 0x0 0x1000000>, <0x0 0x45000000 0x0 0x1000>; interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; l4_cfg: interconnect@4a000000 { }; l4_wkup: interconnect@4ae00000 { }; l4_per1: interconnect@48000000 { }; l4_per2: interconnect@48400000 { }; l4_per3: interconnect@48800000 { }; axi@0 { compatible = "simple-bus"; #size-cells = <1>; #address-cells = <1>; ranges = <0x51000000 0x51000000 0x3000 0x0 0x20000000 0x10000000>; /** * To enable PCI endpoint mode, disable the pcie1_rc * node and enable pcie1_ep mode. */ pcie1_rc: pcie@51000000 { reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; reg-names = "rc_dbics", "ti_conf", "config"; interrupts = <0 232 0x4>, <0 233 0x4>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; ranges = <0x81000000 0 0 0x03000 0 0x00010000 0x82000000 0 0x20013000 0x13000 0 0xffed000>; - dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>; bus-range = <0x00 0xff>; #interrupt-cells = <1>; num-lanes = <1>; linux,pci-domain = <0>; ti,hwmods = "pcie1"; phys = <&pcie1_phy>; phy-names = "pcie-phy0"; ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie1_intc 1>, <0 0 0 2 &pcie1_intc 2>, <0 0 0 3 &pcie1_intc 3>, <0 0 0 4 &pcie1_intc 4>; ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; status = "disabled"; pcie1_intc: interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; pcie1_ep: pcie_ep@51000000 { reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; interrupts = <0 232 0x4>; num-lanes = <1>; num-ib-windows = <4>; num-ob-windows = <16>; ti,hwmods = "pcie1"; phys = <&pcie1_phy>; phy-names = "pcie-phy0"; ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; status = "disabled"; }; }; axi@1 { compatible = "simple-bus"; #size-cells = <1>; #address-cells = <1>; ranges = <0x51800000 0x51800000 0x3000 0x0 0x30000000 0x10000000>; status = "disabled"; pcie2_rc: pcie@51800000 { reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; reg-names = "rc_dbics", "ti_conf", "config"; interrupts = <0 355 0x4>, <0 356 0x4>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; ranges = <0x81000000 0 0 0x03000 0 0x00010000 0x82000000 0 0x30013000 0x13000 0 0xffed000>; - dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>; bus-range = <0x00 0xff>; #interrupt-cells = <1>; num-lanes = <1>; linux,pci-domain = <1>; ti,hwmods = "pcie2"; phys = <&pcie2_phy>; phy-names = "pcie-phy0"; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie2_intc 1>, <0 0 0 2 &pcie2_intc 2>, <0 0 0 3 &pcie2_intc 3>, <0 0 0 4 &pcie2_intc 4>; ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; pcie2_intc: interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; }; ocmcram1: ocmcram@40300000 { compatible = "mmio-sram"; reg = <0x40300000 0x80000>; ranges = <0x0 0x40300000 0x80000>; #address-cells = <1>; #size-cells = <1>; /* * This is a placeholder for an optional reserved * region for use by secure software. The size * of this region is not known until runtime so it * is set as zero to either be updated to reserve * space or left unchanged to leave all SRAM for use. * On HS parts that that require the reserved region * either the bootloader can update the size to * the required amount or the node can be overridden * from the board dts file for the secure platform. */ sram-hs@0 { compatible = "ti,secure-ram"; reg = <0x0 0x0>; }; }; /* * NOTE: ocmcram2 and ocmcram3 are not available on all * DRA7xx and AM57xx variants. Confirm availability in * the data manual for the exact part number in use * before enabling these nodes in the board dts file. */ ocmcram2: ocmcram@40400000 { status = "disabled"; compatible = "mmio-sram"; reg = <0x40400000 0x100000>; ranges = <0x0 0x40400000 0x100000>; #address-cells = <1>; #size-cells = <1>; }; ocmcram3: ocmcram@40500000 { status = "disabled"; compatible = "mmio-sram"; reg = <0x40500000 0x100000>; ranges = <0x0 0x40500000 0x100000>; #address-cells = <1>; #size-cells = <1>; }; bandgap: bandgap@4a0021e0 { reg = <0x4a0021e0 0xc 0x4a00232c 0xc 0x4a002380 0x2c 0x4a0023C0 0x3c 0x4a002564 0x8 0x4a002574 0x50>; compatible = "ti,dra752-bandgap"; interrupts = ; #thermal-sensor-cells = <1>; }; dsp1_system: dsp_system@40d00000 { compatible = "syscon"; reg = <0x40d00000 0x100>; }; dra7_iodelay_core: padconf@4844a000 { compatible = "ti,dra7-iodelay"; reg = <0x4844a000 0x0d1c>; #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <2>; }; edma: edma@43300000 { compatible = "ti,edma3-tpcc"; ti,hwmods = "tpcc"; reg = <0x43300000 0x100000>; reg-names = "edma3_cc"; interrupts = , , ; interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; dma-requests = <64>; #dma-cells = <2>; ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; /* * memcpy is disabled, can be enabled with: * ti,edma-memcpy-channels = <20 21>; * for example. Note that these channels need to be * masked in the xbar as well. */ }; edma_tptc0: tptc@43400000 { compatible = "ti,edma3-tptc"; ti,hwmods = "tptc0"; reg = <0x43400000 0x100000>; interrupts = ; interrupt-names = "edma3_tcerrint"; }; edma_tptc1: tptc@43500000 { compatible = "ti,edma3-tptc"; ti,hwmods = "tptc1"; reg = <0x43500000 0x100000>; interrupts = ; interrupt-names = "edma3_tcerrint"; }; dmm@4e000000 { compatible = "ti,omap5-dmm"; reg = <0x4e000000 0x800>; interrupts = ; ti,hwmods = "dmm"; }; - target-module@40d01000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x40d01000 0x4>, - <0x40d01010 0x4>, - <0x40d01014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_dsp1 1>; - reset-names = "rstctrl"; - ranges = <0x0 0x40d01000 0x1000>; - #size-cells = <1>; - #address-cells = <1>; - - mmu0_dsp1: mmu@0 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp1_system 0x0>; - }; + mmu0_dsp1: mmu@40d01000 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x40d01000 0x100>; + interrupts = ; + ti,hwmods = "mmu0_dsp1"; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp1_system 0x0>; + status = "disabled"; }; - target-module@40d02000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x40d02000 0x4>, - <0x40d02010 0x4>, - <0x40d02014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_dsp1 1>; - reset-names = "rstctrl"; - ranges = <0x0 0x40d02000 0x1000>; - #size-cells = <1>; - #address-cells = <1>; - - mmu1_dsp1: mmu@0 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp1_system 0x1>; - }; + mmu1_dsp1: mmu@40d02000 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x40d02000 0x100>; + interrupts = ; + ti,hwmods = "mmu1_dsp1"; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp1_system 0x1>; + status = "disabled"; }; - target-module@58882000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x58882000 0x4>, - <0x58882010 0x4>, - <0x58882014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_ipu 2>; - reset-names = "rstctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x58882000 0x100>; - - mmu_ipu1: mmu@0 { - compatible = "ti,dra7-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - }; + mmu_ipu1: mmu@58882000 { + compatible = "ti,dra7-iommu"; + reg = <0x58882000 0x100>; + interrupts = ; + ti,hwmods = "mmu_ipu1"; + #iommu-cells = <0>; + ti,iommu-bus-err-back; + status = "disabled"; }; - target-module@55082000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x55082000 0x4>, - <0x55082010 0x4>, - <0x55082014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_core 2>; - reset-names = "rstctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x55082000 0x100>; - - mmu_ipu2: mmu@0 { - compatible = "ti,dra7-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - }; + mmu_ipu2: mmu@55082000 { + compatible = "ti,dra7-iommu"; + reg = <0x55082000 0x100>; + interrupts = ; + ti,hwmods = "mmu_ipu2"; + #iommu-cells = <0>; + ti,iommu-bus-err-back; + status = "disabled"; }; abb_mpu: regulator-abb-mpu { compatible = "ti,abb-v3"; regulator-name = "abb_mpu"; #address-cells = <0>; #size-cells = <0>; clocks = <&sys_clkin1>; ti,settling-time = <50>; ti,clock-cycles = <16>; reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, <0x4ae06014 0x4>, <0x4a003b20 0xc>, <0x4ae0c158 0x4>; reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address"; ti,tranxdone-status-mask = <0x80>; /* LDOVBBMPU_FBB_MUX_CTRL */ ti,ldovbb-override-mask = <0x400>; /* LDOVBBMPU_FBB_VSET_OUT */ ti,ldovbb-vset-mask = <0x1F>; /* * NOTE: only FBB mode used but actual vset will * determine final biasing */ ti,abb_info = < /*uV ABB efuse rbb_m fbb_m vset_m*/ 1060000 0 0x0 0 0x02000000 0x01F00000 1160000 0 0x4 0 0x02000000 0x01F00000 1210000 0 0x8 0 0x02000000 0x01F00000 >; }; abb_ivahd: regulator-abb-ivahd { compatible = "ti,abb-v3"; regulator-name = "abb_ivahd"; #address-cells = <0>; #size-cells = <0>; clocks = <&sys_clkin1>; ti,settling-time = <50>; ti,clock-cycles = <16>; reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, <0x4ae06010 0x4>, <0x4a0025cc 0xc>, <0x4a002470 0x4>; reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address"; ti,tranxdone-status-mask = <0x40000000>; /* LDOVBBIVA_FBB_MUX_CTRL */ ti,ldovbb-override-mask = <0x400>; /* LDOVBBIVA_FBB_VSET_OUT */ ti,ldovbb-vset-mask = <0x1F>; /* * NOTE: only FBB mode used but actual vset will * determine final biasing */ ti,abb_info = < /*uV ABB efuse rbb_m fbb_m vset_m*/ 1055000 0 0x0 0 0x02000000 0x01F00000 1150000 0 0x4 0 0x02000000 0x01F00000 1250000 0 0x8 0 0x02000000 0x01F00000 >; }; abb_dspeve: regulator-abb-dspeve { compatible = "ti,abb-v3"; regulator-name = "abb_dspeve"; #address-cells = <0>; #size-cells = <0>; clocks = <&sys_clkin1>; ti,settling-time = <50>; ti,clock-cycles = <16>; reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, <0x4ae06010 0x4>, <0x4a0025e0 0xc>, <0x4a00246c 0x4>; reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address"; ti,tranxdone-status-mask = <0x20000000>; /* LDOVBBDSPEVE_FBB_MUX_CTRL */ ti,ldovbb-override-mask = <0x400>; /* LDOVBBDSPEVE_FBB_VSET_OUT */ ti,ldovbb-vset-mask = <0x1F>; /* * NOTE: only FBB mode used but actual vset will * determine final biasing */ ti,abb_info = < /*uV ABB efuse rbb_m fbb_m vset_m*/ 1055000 0 0x0 0 0x02000000 0x01F00000 1150000 0 0x4 0 0x02000000 0x01F00000 1250000 0 0x8 0 0x02000000 0x01F00000 >; }; abb_gpu: regulator-abb-gpu { compatible = "ti,abb-v3"; regulator-name = "abb_gpu"; #address-cells = <0>; #size-cells = <0>; clocks = <&sys_clkin1>; ti,settling-time = <50>; ti,clock-cycles = <16>; reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, <0x4ae06010 0x4>, <0x4a003b08 0xc>, <0x4ae0c154 0x4>; reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address"; ti,tranxdone-status-mask = <0x10000000>; /* LDOVBBGPU_FBB_MUX_CTRL */ ti,ldovbb-override-mask = <0x400>; /* LDOVBBGPU_FBB_VSET_OUT */ ti,ldovbb-vset-mask = <0x1F>; /* * NOTE: only FBB mode used but actual vset will * determine final biasing */ ti,abb_info = < /*uV ABB efuse rbb_m fbb_m vset_m*/ 1090000 0 0x0 0 0x02000000 0x01F00000 1210000 0 0x4 0 0x02000000 0x01F00000 1280000 0 0x8 0 0x02000000 0x01F00000 >; }; qspi: spi@4b300000 { compatible = "ti,dra7xxx-qspi"; reg = <0x4b300000 0x100>, <0x5c000000 0x4000000>; reg-names = "qspi_base", "qspi_mmap"; syscon-chipselects = <&scm_conf 0x558>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "qspi"; clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>; clock-names = "fck"; num-cs = <4>; interrupts = ; status = "disabled"; }; /* OCP2SCP3 */ sata: sata@4a141100 { compatible = "snps,dwc-ahci"; reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; interrupts = ; phys = <&sata_phy>; phy-names = "sata-phy"; clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; ti,hwmods = "sata"; ports-implemented = <0x1>; }; /* OCP2SCP1 */ /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; reg = <0x50000000 0x37c>; /* device IO registers */ interrupts = ; dmas = <&edma_xbar 4 0>; dma-names = "rxtx"; gpmc,num-cs = <8>; gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; interrupt-controller; #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - target-module@56000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5600fe00 0x4>, - <0x5600fe10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x56000000 0x2000000>; - }; - crossbar_mpu: crossbar@4a002a48 { compatible = "ti,irq-crossbar"; reg = <0x4a002a48 0x130>; interrupt-controller; interrupt-parent = <&wakeupgen>; #interrupt-cells = <3>; ti,max-irqs = <160>; ti,max-crossbar-sources = ; ti,reg-size = <2>; ti,irqs-reserved = <0 1 2 3 5 6 131 132>; ti,irqs-skip = <10 133 139 140>; ti,irqs-safe-map = <0>; }; dss: dss@58000000 { compatible = "ti,dra7-dss"; /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ status = "disabled"; ti,hwmods = "dss_core"; /* CTRL_CORE_DSS_PLL_CONTROL */ syscon-pll-ctrl = <&scm_conf 0x538>; #address-cells = <1>; #size-cells = <1>; ranges; dispc@58001000 { compatible = "ti,dra7-dispc"; reg = <0x58001000 0x1000>; interrupts = ; ti,hwmods = "dss_dispc"; clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; /* CTRL_CORE_SMA_SW_1 */ syscon-pol = <&scm_conf 0x534>; }; hdmi: encoder@58060000 { compatible = "ti,dra7-hdmi"; reg = <0x58040000 0x200>, <0x58040200 0x80>, <0x58040300 0x80>, <0x58060000 0x19000>; reg-names = "wp", "pll", "phy", "core"; interrupts = ; status = "disabled"; ti,hwmods = "dss_hdmi"; clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; dmas = <&sdma_xbar 76>; dma-names = "audio_tx"; }; }; - aes1_target: target-module@4b500000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4b500080 0x4>, - <0x4b500084 0x4>, - <0x4b500088 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>; + aes1: aes@4b500000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes1"; + reg = <0x4b500000 0xa0>; + interrupts = ; + dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; + dma-names = "tx", "rx"; + clocks = <&l3_iclk_div>; clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4b500000 0x1000>; - - aes1: aes@0 { - compatible = "ti,omap4-aes"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; - dma-names = "tx", "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; }; - aes2_target: target-module@4b700000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4b700080 0x4>, - <0x4b700084 0x4>, - <0x4b700088 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>; + aes2: aes@4b700000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes2"; + reg = <0x4b700000 0xa0>; + interrupts = ; + dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; + dma-names = "tx", "rx"; + clocks = <&l3_iclk_div>; clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4b700000 0x1000>; - - aes2: aes@0 { - compatible = "ti,omap4-aes"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; - dma-names = "tx", "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; }; - sham_target: target-module@4b101000 { - compatible = "ti,sysc-omap3-sham", "ti,sysc"; - reg = <0x4b101100 0x4>, - <0x4b101110 0x4>, - <0x4b101114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>; + des: des@480a5000 { + compatible = "ti,omap4-des"; + ti,hwmods = "des"; + reg = <0x480a5000 0xa0>; + interrupts = ; + dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; + dma-names = "tx", "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; + + sham: sham@53100000 { + compatible = "ti,omap5-sham"; + ti,hwmods = "sham"; + reg = <0x4b101000 0x300>; + interrupts = ; + dmas = <&edma_xbar 119 0>; + dma-names = "rx"; + clocks = <&l3_iclk_div>; clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4b101000 0x1000>; - - sham: sham@0 { - compatible = "ti,omap5-sham"; - reg = <0 0x300>; - interrupts = ; - dmas = <&edma_xbar 119 0>; - dma-names = "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; }; opp_supply_mpu: opp-supply@4a003b20 { compatible = "ti,omap5-opp-supply"; reg = <0x4a003b20 0xc>; ti,efuse-settings = < /* uV offset */ 1060000 0x0 1160000 0x4 1210000 0x8 >; ti,absolute-max-voltage-uv = <1500000>; }; }; thermal_zones: thermal-zones { #include "omap4-cpu-thermal.dtsi" #include "omap5-gpu-thermal.dtsi" #include "omap5-core-thermal.dtsi" #include "dra7-dspeve-thermal.dtsi" #include "dra7-iva-thermal.dtsi" }; }; &cpu_thermal { polling-delay = <500>; /* milliseconds */ coefficients = <0 2000>; }; &gpu_thermal { coefficients = <0 2000>; }; &core_thermal { coefficients = <0 2000>; }; &dspeve_thermal { coefficients = <0 2000>; }; &iva_thermal { coefficients = <0 2000>; }; &cpu_crit { temperature = <120000>; /* milli Celsius */ }; &core_crit { temperature = <120000>; /* milli Celsius */ }; &gpu_crit { temperature = <120000>; /* milli Celsius */ }; &dspeve_crit { temperature = <120000>; /* milli Celsius */ }; &iva_crit { temperature = <120000>; /* milli Celsius */ }; #include "dra7-l4.dtsi" #include "dra7xx-clocks.dtsi" - -&prm { - prm_dsp1: prm@400 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x400 0x100>; - #reset-cells = <1>; - }; - - prm_ipu: prm@500 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x500 0x100>; - #reset-cells = <1>; - }; - - prm_core: prm@700 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x700 0x100>; - #reset-cells = <1>; - }; - - prm_iva: prm@f00 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0xf00 0x100>; - }; - - prm_dsp2: prm@1b00 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1b00 0x40>; - #reset-cells = <1>; - }; - - prm_eve1: prm@1b40 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1b40 0x40>; - }; - - prm_eve2: prm@1b80 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1b80 0x40>; - }; - - prm_eve3: prm@1bc0 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1bc0 0x40>; - }; - - prm_eve4: prm@1c00 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1c00 0x60>; - }; -}; diff --git a/sys/gnu/dts/arm/dra72-evm-common.dtsi b/sys/gnu/dts/arm/dra72-evm-common.dtsi index 01558a86af82..8641a3d7d8ad 100644 --- a/sys/gnu/dts/arm/dra72-evm-common.dtsi +++ b/sys/gnu/dts/arm/dra72-evm-common.dtsi @@ -1,613 +1,582 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; #include "dra72x.dtsi" #include -#include +#include / { compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; aliases { display0 = &hdmi0; }; chosen { stdout-path = &uart1; }; evm_12v0: fixedregulator-evm12v0 { /* main supply */ compatible = "regulator-fixed"; regulator-name = "evm_12v0"; regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; regulator-always-on; regulator-boot-on; }; evm_5v0: fixedregulator-evm5v0 { /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */ /* Output 1 of LM5140QRWGTQ1 on dra71-evm */ compatible = "regulator-fixed"; regulator-name = "evm_5v0"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; vin-supply = <&evm_12v0>; regulator-always-on; regulator-boot-on; }; evm_3v6: fixedregulator-evm_3v6 { compatible = "regulator-fixed"; regulator-name = "evm_3v6"; regulator-min-microvolt = <3600000>; regulator-max-microvolt = <3600000>; vin-supply = <&evm_5v0>; regulator-always-on; regulator-boot-on; }; vsys_3v3: fixedregulator-vsys3v3 { /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */ /* Output 2 of LM5140QRWGTQ1 on dra71-evm */ compatible = "regulator-fixed"; regulator-name = "vsys_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <&evm_12v0>; regulator-always-on; regulator-boot-on; }; evm_3v3_sw: fixedregulator-evm_3v3 { /* TPS22965DSG */ compatible = "regulator-fixed"; regulator-name = "evm_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <&vsys_3v3>; regulator-always-on; regulator-boot-on; }; aic_dvdd: fixedregulator-aic_dvdd { /* TPS77018DBVT */ compatible = "regulator-fixed"; regulator-name = "aic_dvdd"; vin-supply = <&evm_3v3_sw>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; evm_3v3_sd: fixedregulator-sd { compatible = "regulator-fixed"; regulator-name = "evm_3v3_sd"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <&evm_3v3_sw>; enable-active-high; gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; }; extcon_usb1: extcon_usb1 { compatible = "linux,extcon-usb-gpio"; id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; }; extcon_usb2: extcon_usb2 { compatible = "linux,extcon-usb-gpio"; id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; }; hdmi0: connector { compatible = "hdmi-connector"; label = "hdmi"; type = "a"; port { hdmi_connector_in: endpoint { remote-endpoint = <&tpd12s015_out>; }; }; }; tpd12s015: encoder { compatible = "ti,tpd12s015"; gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; tpd12s015_in: endpoint { remote-endpoint = <&hdmi_out>; }; }; port@1 { reg = <1>; tpd12s015_out: endpoint { remote-endpoint = <&hdmi_connector_in>; }; }; }; }; sound0: sound0 { compatible = "simple-audio-card"; simple-audio-card,name = "DRA7xx-EVM"; simple-audio-card,widgets = "Headphone", "Headphone Jack", "Line", "Line Out", "Microphone", "Mic Jack", "Line", "Line In"; simple-audio-card,routing = "Headphone Jack", "HPLOUT", "Headphone Jack", "HPROUT", "Line Out", "LLOUT", "Line Out", "RLOUT", "MIC3L", "Mic Jack", "MIC3R", "Mic Jack", "Mic Jack", "Mic Bias", "LINE1L", "Line In", "LINE1R", "Line In"; simple-audio-card,format = "dsp_b"; simple-audio-card,bitclock-master = <&sound0_master>; simple-audio-card,frame-master = <&sound0_master>; simple-audio-card,bitclock-inversion; sound0_master: simple-audio-card,cpu { sound-dai = <&mcasp3>; system-clock-frequency = <5644800>; }; simple-audio-card,codec { sound-dai = <&tlv320aic3106>; clocks = <&atl_clkin2_ck>; }; }; vmmcwl_fixed: fixedregulator-mmcwl { compatible = "regulator-fixed"; regulator-name = "vmmcwl_fixed"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; enable-active-high; }; - - clk_ov5640_fixed: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; }; &dra7_pmx_core { dcan1_pins_default: dcan1_pins_default { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ >; }; dcan1_pins_sleep: dcan1_pins_sleep { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ >; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; pcf_lcd: gpio@20 { compatible = "nxp,pcf8575"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; pcf_gpio_21: gpio@21 { compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x21>; lines-initial-states = <0x1408>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; tlv320aic3106: tlv320aic3106@19 { #sound-dai-cells = <0>; compatible = "ti,tlv320aic3106"; reg = <0x19>; adc-settle-ms = <40>; ai3x-micbias-vg = <1>; /* 2.0V */ status = "okay"; /* Regulators */ AVDD-supply = <&evm_3v3_sw>; IOVDD-supply = <&evm_3v3_sw>; DRVDD-supply = <&evm_3v3_sw>; DVDD-supply = <&aic_dvdd>; }; }; &i2c5 { status = "okay"; clock-frequency = <400000>; pcf_hdmi: pcf8575@26 { compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x26>; gpio-controller; #gpio-cells = <2>; /* * initial state is used here to keep the mdio interface * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and * VIN2_S0 driven high otherwise Ethernet stops working * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 */ lines-initial-states = <0x0f2b>; p1 { /* vin6_sel_s0: high: VIN6, low: audio */ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; output-low; line-name = "vin6_sel_s0"; }; }; - - ov5640@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - - clocks = <&clk_ov5640_fixed>; - clock-names = "xclk"; - - port { - csi2_cam0: endpoint { - remote-endpoint = <&csi2_phy0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - }; &uart1 { status = "okay"; interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, <&dra7_pmx_core 0x3e0>; }; &elm { status = "okay"; }; &gpmc { /* * For the existing IOdelay configuration via U-Boot we don't * support NAND on dra72-evm. Keep it disabled. Enabling it * requires a different configuration by U-Boot. */ status = "disabled"; ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ nand@0,0 { /* To use NAND, DIP switch SW5 must be set like so: * SW5.1 (NAND_SELn) = ON (LOW) * SW5.9 (GPMC_WPN) = OFF (HIGH) */ compatible = "ti,omap2-nand"; reg = <0 0 4>; /* device IO registers */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ ti,nand-xfer-type = "prefetch-dma"; ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; gpmc,device-width = <2>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <80>; gpmc,cs-wr-off-ns = <80>; gpmc,adv-on-ns = <0>; gpmc,adv-rd-off-ns = <60>; gpmc,adv-wr-off-ns = <60>; gpmc,we-on-ns = <10>; gpmc,we-off-ns = <50>; gpmc,oe-on-ns = <4>; gpmc,oe-off-ns = <40>; gpmc,access-ns = <40>; gpmc,wr-access-ns = <80>; gpmc,rd-cycle-ns = <80>; gpmc,wr-cycle-ns = <80>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ /* All SPL-* partitions are sized to minimal length * which can be independently programmable. For * NAND flash this is equal to size of erase-block */ #address-cells = <1>; #size-cells = <1>; partition@0 { label = "NAND.SPL"; reg = <0x00000000 0x000020000>; }; partition@1 { label = "NAND.SPL.backup1"; reg = <0x00020000 0x00020000>; }; partition@2 { label = "NAND.SPL.backup2"; reg = <0x00040000 0x00020000>; }; partition@3 { label = "NAND.SPL.backup3"; reg = <0x00060000 0x00020000>; }; partition@4 { label = "NAND.u-boot-spl-os"; reg = <0x00080000 0x00040000>; }; partition@5 { label = "NAND.u-boot"; reg = <0x000c0000 0x00100000>; }; partition@6 { label = "NAND.u-boot-env"; reg = <0x001c0000 0x00020000>; }; partition@7 { label = "NAND.u-boot-env.backup1"; reg = <0x001e0000 0x00020000>; }; partition@8 { label = "NAND.kernel"; reg = <0x00200000 0x00800000>; }; partition@9 { label = "NAND.file-system"; reg = <0x00a00000 0x0f600000>; }; }; }; &omap_dwc3_1 { extcon = <&extcon_usb1>; }; &omap_dwc3_2 { extcon = <&extcon_usb2>; }; &usb1 { dr_mode = "otg"; extcon = <&extcon_usb1>; }; &usb2 { dr_mode = "host"; extcon = <&extcon_usb2>; }; &mmc1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_default>; vmmc-supply = <&evm_3v3_sd>; bus-width = <4>; /* * SDCD signal is not being used here - using the fact that GPIO mode * is a viable alternative */ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; max-frequency = <192000000>; }; &mmc2 { /* SW5-3 in ON position */ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins_default>; bus-width = <8>; non-removable; max-frequency = <192000000>; }; &mmc4 { status = "okay"; vmmc-supply = <&evm_3v6>; vqmmc-supply = <&vmmcwl_fixed>; bus-width = <4>; cap-power-off-card; keep-power-in-suspend; non-removable; pinctrl-names = "default", "hs", "sdr12", "sdr25"; pinctrl-0 = <&mmc4_pins_default>; pinctrl-1 = <&mmc4_pins_default>; pinctrl-2 = <&mmc4_pins_default>; pinctrl-3 = <&mmc4_pins_default>; #address-cells = <1>; #size-cells = <0>; wifi@2 { compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio5>; interrupts = <7 IRQ_TYPE_EDGE_RISING>; }; }; &mac { status = "okay"; }; &dcan1 { status = "ok"; pinctrl-names = "default", "sleep", "active"; pinctrl-0 = <&dcan1_pins_sleep>; pinctrl-1 = <&dcan1_pins_sleep>; pinctrl-2 = <&dcan1_pins_default>; }; &qspi { status = "okay"; spi-max-frequency = <76800000>; m25p80@0 { compatible = "s25fl256s1"; spi-max-frequency = <76800000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <1>; /* MTD partition table. * The ROM checks the first four physical blocks * for a valid file to boot and the flash here is * 64KiB block size. */ partition@0 { label = "QSPI.SPL"; reg = <0x00000000 0x000010000>; }; partition@1 { label = "QSPI.SPL.backup1"; reg = <0x00010000 0x00010000>; }; partition@2 { label = "QSPI.SPL.backup2"; reg = <0x00020000 0x00010000>; }; partition@3 { label = "QSPI.SPL.backup3"; reg = <0x00030000 0x00010000>; }; partition@4 { label = "QSPI.u-boot"; reg = <0x00040000 0x00100000>; }; partition@5 { label = "QSPI.u-boot-spl-os"; reg = <0x00140000 0x00080000>; }; partition@6 { label = "QSPI.u-boot-env"; reg = <0x001c0000 0x00010000>; }; partition@7 { label = "QSPI.u-boot-env.backup1"; reg = <0x001d0000 0x0010000>; }; partition@8 { label = "QSPI.kernel"; reg = <0x001e0000 0x0800000>; }; partition@9 { label = "QSPI.file-system"; reg = <0x009e0000 0x01620000>; }; }; }; &dss { status = "ok"; }; &hdmi { status = "ok"; port { hdmi_out: endpoint { remote-endpoint = <&tpd12s015_in>; }; }; }; &atl { assigned-clocks = <&abe_dpll_sys_clk_mux>, <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>, <&dpll_abe_ck>, <&dpll_abe_m2x2_ck>, <&atl_clkin2_ck>; assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; status = "okay"; atl2 { bws = ; aws = ; }; }; &mcasp3 { #sound-dai-cells = <0>; assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; assigned-clock-parents = <&atl_clkin2_ck>; status = "okay"; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; /* 4 serializer */ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1 2 0 0 >; tx-num-evt = <32>; rx-num-evt = <32>; }; &mailbox5 { status = "okay"; mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { status = "okay"; }; mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { status = "okay"; }; }; &pcie1_rc { status = "okay"; }; - -&csi2_0 { - csi2_phy0: endpoint { - remote-endpoint = <&csi2_cam0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; -}; diff --git a/sys/gnu/dts/arm/dra72x.dtsi b/sys/gnu/dts/arm/dra72x.dtsi index 82b57a35abc0..f5762709c853 100644 --- a/sys/gnu/dts/arm/dra72x.dtsi +++ b/sys/gnu/dts/arm/dra72x.dtsi @@ -1,108 +1,66 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ * * Based on "omap4.dtsi" */ #include "dra7.dtsi" / { compatible = "ti,dra722", "ti,dra72", "ti,dra7"; pmu { compatible = "arm,cortex-a15-pmu"; interrupt-parent = <&wakeupgen>; interrupts = ; }; }; -&l4_per2 { - target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5b000 0x4>, - <0x5b010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - ; - ti,sysc-sidle = , - ; - clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - - cal: cal@0 { - compatible = "ti,dra72-cal"; - reg = <0x0000 0x400>, - <0x0800 0x40>, - <0x0900 0x40>; - reg-names = "cal_top", - "cal_rx_core0", - "cal_rx_core1"; - interrupts = ; - ti,camerrx-control = <&scm_conf 0xE94>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - csi2_0: port@0 { - reg = <0>; - }; - csi2_1: port@1 { - reg = <1>; - }; - }; - }; - }; -}; - &dss { reg = <0x58000000 0x80>, <0x58004054 0x4>, <0x58004300 0x20>; reg-names = "dss", "pll1_clkctrl", "pll1"; clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>, <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>; clock-names = "fck", "video1_clk"; }; &mailbox5 { mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; }; mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { ti,mbox-tx = <5 2 2>; ti,mbox-rx = <1 2 2>; status = "disabled"; }; }; &mailbox6 { mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; }; }; &pcie1_rc { compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; }; &pcie1_ep { compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep"; }; &pcie2_rc { compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; }; &usb4_tm { status = "disabled"; }; diff --git a/sys/gnu/dts/arm/dra74x.dtsi b/sys/gnu/dts/arm/dra74x.dtsi index c5abc436ca1f..d1b5b76bc5a8 100644 --- a/sys/gnu/dts/arm/dra74x.dtsi +++ b/sys/gnu/dts/arm/dra74x.dtsi @@ -1,185 +1,146 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ * * Based on "omap4.dtsi" */ #include "dra7.dtsi" / { compatible = "ti,dra742", "ti,dra74", "ti,dra7"; cpus { cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; operating-points-v2 = <&cpu0_opp_table>; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; clock-latency = <300000>; /* From omap-cpufreq driver */ /* cooling options */ #cooling-cells = <2>; /* min followed by max */ vbb-supply = <&abb_mpu>; }; }; pmu { compatible = "arm,cortex-a15-pmu"; interrupt-parent = <&wakeupgen>; interrupts = , ; }; ocp { dsp2_system: dsp_system@41500000 { compatible = "syscon"; reg = <0x41500000 0x100>; }; omap_dwc3_4: omap_dwc3_4@48940000 { compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss4"; reg = <0x48940000 0x10000>; interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; ranges; status = "disabled"; usb4: usb@48950000 { compatible = "snps,dwc3"; reg = <0x48950000 0x17000>; interrupts = , , ; interrupt-names = "peripheral", "host", "otg"; maximum-speed = "high-speed"; dr_mode = "otg"; }; }; - target-module@41501000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x41501000 0x4>, - <0x41501010 0x4>, - <0x41501014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_dsp2 1>; - reset-names = "rstctrl"; - ranges = <0x0 0x41501000 0x1000>; - #size-cells = <1>; - #address-cells = <1>; - - mmu0_dsp2: mmu@0 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x0>; - }; + mmu0_dsp2: mmu@41501000 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x41501000 0x100>; + interrupts = ; + ti,hwmods = "mmu0_dsp2"; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp2_system 0x0>; + status = "disabled"; }; - target-module@41502000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x41502000 0x4>, - <0x41502010 0x4>, - <0x41502014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - - clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_dsp2 1>; - reset-names = "rstctrl"; - ranges = <0x0 0x41502000 0x1000>; - #size-cells = <1>; - #address-cells = <1>; - - mmu1_dsp2: mmu@0 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x1>; - }; + mmu1_dsp2: mmu@41502000 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x41502000 0x100>; + interrupts = ; + ti,hwmods = "mmu1_dsp2"; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp2_system 0x1>; + status = "disabled"; }; }; }; &cpu0_opp_table { opp-shared; }; &dss { reg = <0x58000000 0x80>, <0x58004054 0x4>, <0x58004300 0x20>, <0x58009054 0x4>, <0x58009300 0x20>; reg-names = "dss", "pll1_clkctrl", "pll1", "pll2_clkctrl", "pll2"; clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>, <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>, <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>; clock-names = "fck", "video1_clk", "video2_clk"; }; &mailbox5 { mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; }; mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { ti,mbox-tx = <5 2 2>; ti,mbox-rx = <1 2 2>; status = "disabled"; }; }; &mailbox6 { mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; }; mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { ti,mbox-tx = <5 2 2>; ti,mbox-rx = <1 2 2>; status = "disabled"; }; }; &pcie1_rc { compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie"; }; &pcie1_ep { compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep"; }; &pcie2_rc { compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie"; }; diff --git a/sys/gnu/dts/arm/dra76-evm.dts b/sys/gnu/dts/arm/dra76-evm.dts index e958cb3d1b31..1fb6f13fb5e2 100644 --- a/sys/gnu/dts/arm/dra76-evm.dts +++ b/sys/gnu/dts/arm/dra76-evm.dts @@ -1,550 +1,449 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; #include "dra76x.dtsi" #include "dra7-evm-common.dtsi" #include "dra76x-mmc-iodelay.dtsi" #include / { model = "TI DRA762 EVM"; compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7"; - aliases { - display0 = &hdmi0; - - sound0 = &sound0; - sound1 = &hdmi; - }; - memory@0 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x80000000>; }; vsys_12v0: fixedregulator-vsys12v0 { /* main supply */ compatible = "regulator-fixed"; regulator-name = "vsys_12v0"; regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; regulator-always-on; regulator-boot-on; }; vsys_5v0: fixedregulator-vsys5v0 { /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */ compatible = "regulator-fixed"; regulator-name = "vsys_5v0"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; vin-supply = <&vsys_12v0>; regulator-always-on; regulator-boot-on; }; vio_3v6: fixedregulator-vio_3v6 { compatible = "regulator-fixed"; regulator-name = "vio_3v6"; regulator-min-microvolt = <3600000>; regulator-max-microvolt = <3600000>; vin-supply = <&vsys_5v0>; regulator-always-on; regulator-boot-on; }; vsys_3v3: fixedregulator-vsys3v3 { /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */ compatible = "regulator-fixed"; regulator-name = "vsys_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <&vsys_12v0>; regulator-always-on; regulator-boot-on; }; vio_3v3: fixedregulator-vio_3v3 { compatible = "regulator-fixed"; regulator-name = "vio_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <&vsys_3v3>; regulator-always-on; regulator-boot-on; }; vio_3v3_sd: fixedregulator-sd { compatible = "regulator-fixed"; regulator-name = "vio_3v3_sd"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <&vio_3v3>; enable-active-high; gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; }; vio_1v8: fixedregulator-vio_1v8 { compatible = "regulator-fixed"; regulator-name = "vio_1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; vin-supply = <&smps5_reg>; }; vmmcwl_fixed: fixedregulator-mmcwl { compatible = "regulator-fixed"; regulator-name = "vmmcwl_fixed"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&gpio5 8 0>; /* gpio5_8 */ startup-delay-us = <70000>; enable-active-high; }; vtt_fixed: fixedregulator-vtt { compatible = "regulator-fixed"; regulator-name = "vtt_fixed"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; vin-supply = <&vsys_3v3>; regulator-always-on; regulator-boot-on; }; aic_dvdd: fixedregulator-aic_dvdd { /* TPS77018DBVT */ compatible = "regulator-fixed"; regulator-name = "aic_dvdd"; vin-supply = <&vio_3v3>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - - clk_ov5640_fixed: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>, /* gpio7_30, CT CP HPD */ - <&gpio7 31 GPIO_ACTIVE_HIGH>, /* gpio7_31, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; tps65917: tps65917@58 { compatible = "ti,tps65917"; reg = <0x58>; ti,system-power-controller; ti,palmas-override-powerhold; interrupt-controller; #interrupt-cells = <2>; tps65917_pmic { compatible = "ti,tps65917-pmic"; smps12-in-supply = <&vsys_3v3>; smps3-in-supply = <&vsys_3v3>; smps4-in-supply = <&vsys_3v3>; smps5-in-supply = <&vsys_3v3>; ldo1-in-supply = <&vsys_3v3>; ldo2-in-supply = <&vsys_3v3>; ldo3-in-supply = <&vsys_5v0>; ldo4-in-supply = <&vsys_5v0>; ldo5-in-supply = <&vsys_3v3>; tps65917_regulators: regulators { smps12_reg: smps12 { /* VDD_DSPEVE */ regulator-name = "smps12"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; smps3_reg: smps3 { /* VDD_CORE */ regulator-name = "smps3"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1250000>; regulator-boot-on; regulator-always-on; }; smps4_reg: smps4 { /* VDD_IVA */ regulator-name = "smps4"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; smps5_reg: smps5 { /* VDDS1V8 */ regulator-name = "smps5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; ldo1_reg: ldo1 { /* LDO1_OUT --> VDA_PHY1_1V8 */ regulator-name = "ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; regulator-allow-bypass; }; ldo2_reg: ldo2 { /* LDO2_OUT --> VDA_PHY2_1V8 */ regulator-name = "ldo2"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-allow-bypass; regulator-always-on; }; ldo3_reg: ldo3 { /* VDA_USB_3V3 */ regulator-name = "ldo3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; ldo5_reg: ldo5 { /* VDDA_1V8_PLL */ regulator-name = "ldo5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; ldo4_reg: ldo4 { /* VDD_SDIO_DV */ regulator-name = "ldo4"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; }; }; tps65917_power_button { compatible = "ti,palmas-pwrbutton"; interrupt-parent = <&tps65917>; interrupts = <1 IRQ_TYPE_NONE>; wakeup-source; ti,palmas-long-press-seconds = <6>; }; }; lp87565: lp87565@60 { compatible = "ti,lp87565-q1"; reg = <0x60>; buck10-in-supply =<&vsys_3v3>; buck23-in-supply =<&vsys_3v3>; regulators: regulators { buck10_reg: buck10 { /*VDD_MPU*/ regulator-name = "buck10"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; buck23_reg: buck23 { /* VDD_GPU*/ regulator-name = "buck23"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1250000>; regulator-boot-on; regulator-always-on; }; }; }; pcf_lcd: pcf8757@20 { compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&gpio1>; interrupts = <3 IRQ_TYPE_EDGE_FALLING>; }; pcf_gpio_21: pcf8757@21 { compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&gpio1>; interrupts = <3 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; }; pcf_hdmi: pcf8575@26 { compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x26>; gpio-controller; #gpio-cells = <2>; p1 { /* vin6_sel_s0: high: VIN6, low: audio */ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; output-low; line-name = "vin6_sel_s0"; }; }; tlv320aic3106: tlv320aic3106@19 { #sound-dai-cells = <0>; compatible = "ti,tlv320aic3106"; reg = <0x19>; adc-settle-ms = <40>; ai3x-micbias-vg = <1>; /* 2.0V */ status = "okay"; /* Regulators */ AVDD-supply = <&vio_3v3>; IOVDD-supply = <&vio_3v3>; DRVDD-supply = <&vio_3v3>; DVDD-supply = <&aic_dvdd>; }; }; -&i2c5 { - status = "okay"; - clock-frequency = <400000>; - - ov5640@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - - clocks = <&clk_ov5640_fixed>; - clock-names = "xclk"; - - port { - csi2_cam0: endpoint { - remote-endpoint = <&csi2_phy0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; -}; - &cpu0 { vdd-supply = <&buck10_reg>; }; &mmc1 { status = "okay"; vmmc-supply = <&vio_3v3_sd>; vqmmc-supply = <&ldo4_reg>; bus-width = <4>; /* * SDCD signal is not being used here - using the fact that GPIO mode * is always hardwired. */ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; pinctrl-names = "default", "hs"; pinctrl-0 = <&mmc1_pins_default>; pinctrl-1 = <&mmc1_pins_hs>; }; &mmc2 { status = "okay"; vmmc-supply = <&vio_1v8>; vqmmc-supply = <&vio_1v8>; bus-width = <8>; non-removable; pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; pinctrl-0 = <&mmc2_pins_default>; pinctrl-1 = <&mmc2_pins_default>; pinctrl-2 = <&mmc2_pins_default>; pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>; }; &mmc4 { status = "okay"; vmmc-supply = <&vio_3v6>; vqmmc-supply = <&vmmcwl_fixed>; pinctrl-names = "default", "hs", "sdr12", "sdr25"; pinctrl-0 = <&mmc4_pins_hs &mmc4_iodelay_default_conf>; pinctrl-1 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; }; /* No RTC on this device */ &rtc { status = "disabled"; }; &mac { status = "okay"; dual_emac; }; &cpsw_emac0 { phy-handle = <&dp83867_0>; phy-mode = "rgmii-id"; dual_emac_res_vlan = <1>; }; &cpsw_emac1 { phy-handle = <&dp83867_1>; phy-mode = "rgmii-id"; dual_emac_res_vlan = <2>; }; &davinci_mdio { dp83867_0: ethernet-phy@2 { reg = <2>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; ti,min-output-impedance; ti,dp83867-rxctrl-strap-quirk; }; dp83867_1: ethernet-phy@3 { reg = <3>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; ti,min-output-impedance; ti,dp83867-rxctrl-strap-quirk; }; }; &usb2_phy1 { phy-supply = <&ldo3_reg>; }; &usb2_phy2 { phy-supply = <&ldo3_reg>; }; -&dss { - status = "ok"; - vdda_video-supply = <&ldo5_reg>; -}; - -&hdmi { - status = "ok"; - - vdda-supply = <&ldo1_reg>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; - &qspi { spi-max-frequency = <96000000>; m25p80@0 { spi-max-frequency = <96000000>; }; }; &pcie2_phy { status = "okay"; }; &pcie1_rc { num-lanes = <2>; phys = <&pcie1_phy>, <&pcie2_phy>; phy-names = "pcie-phy0", "pcie-phy1"; }; &pcie1_ep { num-lanes = <2>; phys = <&pcie1_phy>, <&pcie2_phy>; phy-names = "pcie-phy0", "pcie-phy1"; }; &extcon_usb1 { vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>; }; &extcon_usb2 { vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; }; &m_can0 { can-transceiver { max-bitrate = <5000000>; }; }; - -&csi2_0 { - csi2_phy0: endpoint { - remote-endpoint = <&csi2_cam0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; -}; diff --git a/sys/gnu/dts/arm/dra76x.dtsi b/sys/gnu/dts/arm/dra76x.dtsi index 42b8a205b64f..cdcba3f561c4 100644 --- a/sys/gnu/dts/arm/dra76x.dtsi +++ b/sys/gnu/dts/arm/dra76x.dtsi @@ -1,135 +1,88 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ */ #include "dra74x.dtsi" / { compatible = "ti,dra762", "ti,dra7"; ocp { target-module@42c01900 { compatible = "ti,sysc-dra7-mcan", "ti,sysc"; ranges = <0x0 0x42c00000 0x2000>; #address-cells = <1>; #size-cells = <1>; reg = <0x42c01900 0x4>, <0x42c01904 0x4>, <0x42c01908 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET | SYSC_DRA7_MCAN_ENAWAKEUP)>; ti,syss-mask = <1>; clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>; clock-names = "fck"; m_can0: mcan@1a00 { compatible = "bosch,m_can"; reg = <0x1a00 0x4000>, <0x0 0x18FC>; reg-names = "m_can", "message_ram"; interrupt-parent = <&gic>; interrupts = , ; interrupt-names = "int0", "int1"; clocks = <&mcan_clk>, <&l3_iclk_div>; clock-names = "cclk", "hclk"; bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>; }; }; }; }; -&l4_per3 { - target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x1b0000 0x4>, - <0x1b0010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - ; - ti,sysc-sidle = , - ; - clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1b0000 0x10000>; - - cal: cal@0 { - compatible = "ti,dra76-cal"; - reg = <0x0000 0x400>, - <0x0800 0x40>, - <0x0900 0x40>; - reg-names = "cal_top", - "cal_rx_core0", - "cal_rx_core1"; - interrupts = ; - ti,camerrx-control = <&scm_conf 0x6dc>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - csi2_0: port@0 { - reg = <0>; - }; - csi2_1: port@1 { - reg = <1>; - }; - }; - }; - }; -}; - /* MCAN interrupts are hard-wired to irqs 67, 68 */ &crossbar_mpu { ti,irqs-skip = <10 67 68 133 139 140>; }; &scm_conf_clocks { dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_x2_ck>; ti,max-div = <63>; reg = <0x03fc>; ti,bit-shift=<20>; ti,latch-bit=<26>; assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>; assigned-clock-rates = <80000000>; }; dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>; reg = <0x3fc>; ti,bit-shift = <29>; ti,latch-bit=<26>; assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>; }; mcan_clk: mcan_clk@3fc { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; ti,bit-shift = <27>; reg = <0x3fc>; }; }; &rtctarget { status = "disabled"; }; &usb4_tm { status = "disabled"; }; - -&mmc3 { - /* dra76x is not affected by i887 */ - max-frequency = <96000000>; -}; diff --git a/sys/gnu/dts/arm/dra7xx-clocks.dtsi b/sys/gnu/dts/arm/dra7xx-clocks.dtsi index dc0a93bccbf1..93e1eb83bed9 100644 --- a/sys/gnu/dts/arm/dra7xx-clocks.dtsi +++ b/sys/gnu/dts/arm/dra7xx-clocks.dtsi @@ -1,1849 +1,1815 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for DRA7xx clock data * * Copyright (C) 2013 Texas Instruments, Inc. */ &cm_core_aon_clocks { atl_clkin0_ck: atl_clkin0_ck { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; atl_clkin1_ck: atl_clkin1_ck { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; atl_clkin2_ck: atl_clkin2_ck { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; atl_clkin3_ck: atl_clkin3_ck { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; hdmi_clkin_ck: hdmi_clkin_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; mlb_clkin_ck: mlb_clkin_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; mlbp_clkin_ck: mlbp_clkin_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; pciesref_acs_clk_ck: pciesref_acs_clk_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <100000000>; }; ref_clkin0_ck: ref_clkin0_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; ref_clkin1_ck: ref_clkin1_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; ref_clkin2_ck: ref_clkin2_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; ref_clkin3_ck: ref_clkin3_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; rmii_clk_ck: rmii_clk_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; sdvenc_clkin_ck: sdvenc_clkin_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; secure_32k_clk_src_ck: secure_32k_clk_src_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; sys_clk32_crystal_ck: sys_clk32_crystal_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; sys_clk32_pseudo_ck: sys_clk32_pseudo_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin1>; clock-mult = <1>; clock-div = <610>; }; virt_12000000_ck: virt_12000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <12000000>; }; virt_13000000_ck: virt_13000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <13000000>; }; virt_16800000_ck: virt_16800000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <16800000>; }; virt_19200000_ck: virt_19200000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <19200000>; }; virt_20000000_ck: virt_20000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <20000000>; }; virt_26000000_ck: virt_26000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <26000000>; }; virt_27000000_ck: virt_27000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <27000000>; }; virt_38400000_ck: virt_38400000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <38400000>; }; sys_clkin2: sys_clkin2 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <22579200>; }; usb_otg_clkin_ck: usb_otg_clkin_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; video1_clkin_ck: video1_clkin_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; video1_m2_clkin_ck: video1_m2_clkin_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; video2_clkin_ck: video2_clkin_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; video2_m2_clkin_ck: video2_m2_clkin_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; dpll_abe_ck: dpll_abe_ck@1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; }; dpll_abe_x2_ck: dpll_abe_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_abe_ck>; }; dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x01f0>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; abe_clk: abe_clk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2x2_ck>; ti,max-div = <4>; reg = <0x0108>; ti,index-power-of-two; }; dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x01f0>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x01f4>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_core_byp_mux: dpll_core_byp_mux@12c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x012c>; }; dpll_core_ck: dpll_core_ck@120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; clocks = <&sys_clkin1>, <&dpll_core_byp_mux>; reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; }; dpll_core_x2_ck: dpll_core_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_core_ck>; }; dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; reg = <0x013c>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; dpll_mpu_ck: dpll_mpu_ck@160 { #clock-cells = <0>; compatible = "ti,omap5-mpu-dpll-clock"; clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0170>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; mpu_dclk_div: mpu_dclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_mpu_m2_ck>; clock-mult = <1>; clock-div = <1>; }; dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x0240>; }; dpll_dsp_ck: dpll_dsp_ck@234 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; assigned-clocks = <&dpll_dsp_ck>; assigned-clock-rates = <600000000>; }; dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_dsp_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0244>; ti,index-starts-at-one; ti,invert-autoidle-bit; assigned-clocks = <&dpll_dsp_m2_ck>; assigned-clock-rates = <600000000>; }; iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x01ac>; }; dpll_iva_ck: dpll_iva_ck@1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; assigned-clocks = <&dpll_iva_ck>; assigned-clock-rates = <1165000000>; }; dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_iva_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x01b0>; ti,index-starts-at-one; ti,invert-autoidle-bit; assigned-clocks = <&dpll_iva_m2_ck>; assigned-clock-rates = <388333334>; }; iva_dclk: iva_dclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_iva_m2_ck>; clock-mult = <1>; clock-div = <1>; }; dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x02e4>; }; dpll_gpu_ck: dpll_gpu_ck@2d8 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; assigned-clocks = <&dpll_gpu_ck>; assigned-clock-rates = <1277000000>; }; dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gpu_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x02e8>; ti,index-starts-at-one; ti,invert-autoidle-bit; assigned-clocks = <&dpll_gpu_m2_ck>; assigned-clock-rates = <425666667>; }; dpll_core_m2_ck: dpll_core_m2_ck@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0130>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; core_dpll_out_dclk_div: core_dpll_out_dclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m2_ck>; clock-mult = <1>; clock-div = <1>; }; dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x021c>; }; dpll_ddr_ck: dpll_ddr_ck@210 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; }; dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0220>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x02b4>; }; dpll_gmac_ck: dpll_gmac_ck@2a8 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; }; dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x02b8>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; video2_dclk_div: video2_dclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&video2_m2_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; video1_dclk_div: video1_dclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&video1_m2_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; hdmi_dclk_div: hdmi_dclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&hdmi_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; per_dpll_hs_clk_div: per_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <2>; }; usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <3>; }; eve_dpll_hs_clk_div: eve_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; dpll_eve_byp_mux: dpll_eve_byp_mux@290 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x0290>; }; dpll_eve_ck: dpll_eve_ck@284 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; }; dpll_eve_m2_ck: dpll_eve_m2_ck@294 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_eve_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0294>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; eve_dclk_div: eve_dclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_eve_m2_ck>; clock-mult = <1>; clock-div = <1>; }; dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; reg = <0x0140>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; reg = <0x0144>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; reg = <0x0154>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; reg = <0x0158>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; reg = <0x015c>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_ddr_x2_ck: dpll_ddr_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_ddr_ck>; }; dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; reg = <0x0228>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_dsp_x2_ck: dpll_dsp_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_dsp_ck>; }; dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_dsp_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0248>; ti,index-starts-at-one; ti,invert-autoidle-bit; assigned-clocks = <&dpll_dsp_m3x2_ck>; assigned-clock-rates = <400000000>; }; dpll_gmac_x2_ck: dpll_gmac_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_gmac_ck>; }; dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; reg = <0x02c0>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; reg = <0x02c4>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; reg = <0x02c8>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x02bc>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; gmii_m_clk_div: gmii_m_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_gmac_h11x2_ck>; clock-mult = <1>; clock-div = <2>; }; hdmi_clk2_div: hdmi_clk2_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&hdmi_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; hdmi_div_clk: hdmi_div_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&hdmi_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; l3_iclk_div: l3_iclk_div@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; ti,max-div = <2>; ti,bit-shift = <4>; reg = <0x0100>; clocks = <&dpll_core_h12x2_ck>; ti,index-power-of-two; }; l4_root_clk_div: l4_root_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&l3_iclk_div>; clock-mult = <1>; clock-div = <2>; }; video1_clk2_div: video1_clk2_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&video1_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; video1_div_clk: video1_div_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&video1_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; video2_clk2_div: video2_clk2_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&video2_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; video2_div_clk: video2_div_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&video2_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; + ipu1_gfclk_mux: ipu1_gfclk_mux@520 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>; + ti,bit-shift = <24>; + reg = <0x0520>; + assigned-clocks = <&ipu1_gfclk_mux>; + assigned-clock-parents = <&dpll_core_h22x2_ck>; + }; + dummy_ck: dummy_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; }; &prm_clocks { sys_clkin1: sys_clkin1@110 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; reg = <0x0110>; ti,index-starts-at-one; }; abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0118>; }; abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; reg = <0x0114>; }; abe_dpll_clk_mux: abe_dpll_clk_mux@10c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; reg = <0x010c>; }; abe_24m_fclk: abe_24m_fclk@11c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2x2_ck>; reg = <0x011c>; ti,dividers = <8>, <16>; }; aess_fclk: aess_fclk@178 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&abe_clk>; reg = <0x0178>; ti,max-div = <2>; }; abe_giclk_div: abe_giclk_div@174 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&aess_fclk>; reg = <0x0174>; ti,max-div = <2>; }; abe_lp_clk_div: abe_lp_clk_div@1d8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2x2_ck>; reg = <0x01d8>; ti,dividers = <16>, <32>; }; abe_sys_clk_div: abe_sys_clk_div@120 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>; reg = <0x0120>; ti,max-div = <2>; }; adc_gfclk_mux: adc_gfclk_mux@1dc { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; reg = <0x01dc>; }; sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>; ti,max-div = <64>; reg = <0x01c8>; ti,index-power-of-two; }; sys_clk2_dclk_div: sys_clk2_dclk_div@1cc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin2>; ti,max-div = <64>; reg = <0x01cc>; ti,index-power-of-two; }; per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2_ck>; ti,max-div = <64>; reg = <0x01bc>; ti,index-power-of-two; }; dsp_gclk_div: dsp_gclk_div@18c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_dsp_m2_ck>; ti,max-div = <64>; reg = <0x018c>; ti,index-power-of-two; }; gpu_dclk: gpu_dclk@1a0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gpu_m2_ck>; ti,max-div = <64>; reg = <0x01a0>; ti,index-power-of-two; }; emif_phy_dclk_div: emif_phy_dclk_div@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_m2_ck>; ti,max-div = <64>; reg = <0x0190>; ti,index-power-of-two; }; gmac_250m_dclk_div: gmac_250m_dclk_div@19c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_m2_ck>; ti,max-div = <64>; reg = <0x019c>; ti,index-power-of-two; }; gmac_main_clk: gmac_main_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&gmac_250m_dclk_div>; clock-mult = <1>; clock-div = <2>; }; l3init_480m_dclk_div: l3init_480m_dclk_div@1ac { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_m2_ck>; ti,max-div = <64>; reg = <0x01ac>; ti,index-power-of-two; }; usb_otg_dclk_div: usb_otg_dclk_div@184 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&usb_otg_clkin_ck>; ti,max-div = <64>; reg = <0x0184>; ti,index-power-of-two; }; sata_dclk_div: sata_dclk_div@1c0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>; ti,max-div = <64>; reg = <0x01c0>; ti,index-power-of-two; }; pcie2_dclk_div: pcie2_dclk_div@1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_pcie_ref_m2_ck>; ti,max-div = <64>; reg = <0x01b8>; ti,index-power-of-two; }; pcie_dclk_div: pcie_dclk_div@1b4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&apll_pcie_m2_ck>; ti,max-div = <64>; reg = <0x01b4>; ti,index-power-of-two; }; emu_dclk_div: emu_dclk_div@194 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>; ti,max-div = <64>; reg = <0x0194>; ti,index-power-of-two; }; secure_32k_dclk_div: secure_32k_dclk_div@1c4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&secure_32k_clk_src_ck>; ti,max-div = <64>; reg = <0x01c4>; ti,index-power-of-two; }; clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x0158>; }; clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x015c>; }; clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x0160>; }; custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin1>; clock-mult = <1>; clock-div = <2>; }; eve_clk: eve_clk@180 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; reg = <0x0180>; }; hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0164>; }; mlb_clk: mlb_clk@134 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mlb_clkin_ck>; ti,max-div = <64>; reg = <0x0134>; ti,index-power-of-two; }; mlbp_clk: mlbp_clk@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mlbp_clkin_ck>; ti,max-div = <64>; reg = <0x0130>; ti,index-power-of-two; }; per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2_ck>; ti,max-div = <64>; reg = <0x0138>; ti,index-power-of-two; }; timer_sys_clk_div: timer_sys_clk_div@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>; reg = <0x0144>; ti,max-div = <2>; }; video1_dpll_clk_mux: video1_dpll_clk_mux@168 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0168>; }; video2_dpll_clk_mux: video2_dpll_clk_mux@16c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x016c>; }; wkupaon_iclk_mux: wkupaon_iclk_mux@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&abe_lp_clk_div>; reg = <0x0108>; }; }; &cm_core_clocks { dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&sys_clkin1>; reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; }; dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_pcie_ref_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0210>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { compatible = "ti,mux-clock"; clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; #clock-cells = <0>; reg = <0x021c 0x4>; ti,bit-shift = <7>; }; apll_pcie_ck: apll_pcie_ck@21c { #clock-cells = <0>; compatible = "ti,dra7-apll-clock"; clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; reg = <0x021c>, <0x0220>; }; optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { compatible = "ti,divider-clock"; clocks = <&apll_pcie_ck>; #clock-cells = <0>; reg = <0x021c>; ti,dividers = <2>, <1>; ti,bit-shift = <8>; ti,max-div = <2>; }; apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&apll_pcie_ck>; clock-mult = <1>; clock-div = <1>; }; apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&apll_pcie_ck>; clock-mult = <1>; clock-div = <1>; }; apll_pcie_m2_ck: apll_pcie_m2_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&apll_pcie_ck>; clock-mult = <1>; clock-div = <1>; }; dpll_per_byp_mux: dpll_per_byp_mux@14c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x014c>; }; dpll_per_ck: dpll_per_ck@140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; }; dpll_per_m2_ck: dpll_per_m2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0150>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; func_96m_aon_dclk_div: func_96m_aon_dclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <1>; }; dpll_usb_byp_mux: dpll_usb_byp_mux@18c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x018c>; }; dpll_usb_ck: dpll_usb_ck@180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; }; dpll_usb_m2_ck: dpll_usb_m2_ck@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; reg = <0x0190>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_pcie_ref_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; reg = <0x0210>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_per_x2_ck: dpll_per_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_per_ck>; }; dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; reg = <0x0158>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; reg = <0x015c>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; reg = <0x0160>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; reg = <0x0164>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0150>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_usb_ck>; clock-mult = <1>; clock-div = <1>; }; func_128m_clk: func_128m_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_h11x2_ck>; clock-mult = <1>; clock-div = <2>; }; func_12m_fclk: func_12m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <16>; }; func_24m_clk: func_24m_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; func_48m_fclk: func_48m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <4>; }; func_96m_fclk: func_96m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <2>; }; l3init_60m_fclk: l3init_60m_fclk@104 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_m2_ck>; reg = <0x0104>; ti,dividers = <1>, <8>; }; clkout2_clk: clkout2_clk@6b0 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkoutmux2_clk_mux>; ti,bit-shift = <8>; reg = <0x06b0>; }; l3init_960m_gfclk: l3init_960m_gfclk@6c0 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_usb_clkdcoldo>; ti,bit-shift = <8>; reg = <0x06c0>; }; usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0640>; }; usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0688>; }; usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0698>; }; gpu_core_gclk_mux: gpu_core_gclk_mux@1220 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; ti,bit-shift = <24>; reg = <0x1220>; assigned-clocks = <&gpu_core_gclk_mux>; assigned-clock-parents = <&dpll_gpu_m2_ck>; }; gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; ti,bit-shift = <26>; reg = <0x1220>; assigned-clocks = <&gpu_hyd_gclk_mux>; assigned-clock-parents = <&dpll_gpu_m2_ck>; }; l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&wkupaon_iclk_mux>; ti,bit-shift = <24>; reg = <0x0e50>; ti,dividers = <8>, <16>, <32>; }; vip1_gclk_mux: vip1_gclk_mux@1020 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; ti,bit-shift = <24>; reg = <0x1020>; }; vip2_gclk_mux: vip2_gclk_mux@1028 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; ti,bit-shift = <24>; reg = <0x1028>; }; vip3_gclk_mux: vip3_gclk_mux@1030 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; ti,bit-shift = <24>; reg = <0x1030>; }; }; &cm_core_clockdomains { coreaon_clkdm: coreaon_clkdm { compatible = "ti,clockdomain"; clocks = <&dpll_usb_ck>; }; }; &scm_conf_clocks { dss_deshdcp_clk: dss_deshdcp_clk@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3_iclk_div>; ti,bit-shift = <0>; reg = <0x558>; }; ehrpwm0_tbclk: ehrpwm0_tbclk@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4_root_clk_div>; ti,bit-shift = <20>; reg = <0x0558>; }; ehrpwm1_tbclk: ehrpwm1_tbclk@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4_root_clk_div>; ti,bit-shift = <21>; reg = <0x0558>; }; ehrpwm2_tbclk: ehrpwm2_tbclk@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4_root_clk_div>; ti,bit-shift = <22>; reg = <0x0558>; }; sys_32k_ck: sys_32k_ck { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>; ti,bit-shift = <8>; reg = <0x6c4>; }; }; &cm_core_aon { mpu_cm: mpu-cm@300 { compatible = "ti,omap4-cm"; reg = <0x300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x300 0x100>; mpu_clkctrl: mpu-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; dsp1_cm: dsp1-cm@400 { compatible = "ti,omap4-cm"; reg = <0x400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x400 0x100>; dsp1_clkctrl: dsp1-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; ipu_cm: ipu-cm@500 { compatible = "ti,omap4-cm"; reg = <0x500 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x500 0x100>; ipu1_clkctrl: ipu1-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; - assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>; - assigned-clock-parents = <&dpll_core_h22x2_ck>; }; ipu_clkctrl: ipu-clkctrl@50 { compatible = "ti,clkctrl"; reg = <0x50 0x34>; #clock-cells = <2>; }; }; dsp2_cm: dsp2-cm@600 { compatible = "ti,omap4-cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x600 0x100>; dsp2_clkctrl: dsp2-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; rtc_cm: rtc-cm@700 { compatible = "ti,omap4-cm"; - reg = <0x700 0x60>; + reg = <0x700 0x100>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x700 0x60>; + ranges = <0 0x700 0x100>; rtc_clkctrl: rtc-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x28>; #clock-cells = <2>; }; }; - vpe_cm: vpe-cm@760 { - compatible = "ti,omap4-cm"; - reg = <0x760 0xc>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x760 0xc>; - - vpe_clkctrl: vpe-clkctrl@0 { - compatible = "ti,clkctrl"; - reg = <0x0 0xc>; - #clock-cells = <2>; - }; - }; - }; &cm_core { coreaon_cm: coreaon-cm@600 { compatible = "ti,omap4-cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x600 0x100>; coreaon_clkctrl: coreaon-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x1c>; #clock-cells = <2>; }; }; l3main1_cm: l3main1-cm@700 { compatible = "ti,omap4-cm"; reg = <0x700 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x700 0x100>; l3main1_clkctrl: l3main1-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x74>; #clock-cells = <2>; }; }; ipu2_cm: ipu2-cm@900 { compatible = "ti,omap4-cm"; reg = <0x900 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x900 0x100>; ipu2_clkctrl: ipu2-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; dma_cm: dma-cm@a00 { compatible = "ti,omap4-cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xa00 0x100>; dma_clkctrl: dma-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; emif_cm: emif-cm@b00 { compatible = "ti,omap4-cm"; reg = <0xb00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xb00 0x100>; emif_clkctrl: emif-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; atl_cm: atl-cm@c00 { compatible = "ti,omap4-cm"; reg = <0xc00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xc00 0x100>; atl_clkctrl: atl-clkctrl@0 { compatible = "ti,clkctrl"; reg = <0x0 0x4>; #clock-cells = <2>; }; }; l4cfg_cm: l4cfg-cm@d00 { compatible = "ti,omap4-cm"; reg = <0xd00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xd00 0x100>; l4cfg_clkctrl: l4cfg-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x84>; #clock-cells = <2>; }; }; l3instr_cm: l3instr-cm@e00 { compatible = "ti,omap4-cm"; reg = <0xe00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xe00 0x100>; l3instr_clkctrl: l3instr-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; }; - cam_cm: cam-cm@1000 { - compatible = "ti,omap4-cm"; - reg = <0x1000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000 0x100>; - - cam_clkctrl: cam-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x2c>; - #clock-cells = <2>; - }; - }; - dss_cm: dss-cm@1100 { compatible = "ti,omap4-cm"; reg = <0x1100 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1100 0x100>; dss_clkctrl: dss-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x14>; #clock-cells = <2>; }; }; - gpu_cm: gpu-cm@1200 { - compatible = "ti,omap4-cm"; - reg = <0x1200 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1200 0x100>; - - gpu_clkctrl: gpu-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - l3init_cm: l3init-cm@1300 { compatible = "ti,omap4-cm"; reg = <0x1300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1300 0x100>; l3init_clkctrl: l3init-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x6c>, <0xe0 0x14>; #clock-cells = <2>; }; pcie_clkctrl: pcie-clkctrl@b0 { compatible = "ti,clkctrl"; reg = <0xb0 0xc>; #clock-cells = <2>; }; gmac_clkctrl: gmac-clkctrl@d0 { compatible = "ti,clkctrl"; reg = <0xd0 0x4>; #clock-cells = <2>; }; }; l4per_cm: l4per-cm@1700 { compatible = "ti,omap4-cm"; reg = <0x1700 0x300>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1700 0x300>; l4per_clkctrl: l4per-clkctrl@28 { compatible = "ti,clkctrl"; reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>; #clock-cells = <2>; assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; assigned-clock-parents = <&abe_24m_fclk>; }; l4sec_clkctrl: l4sec-clkctrl@1a0 { compatible = "ti,clkctrl"; reg = <0x1a0 0x2c>; #clock-cells = <2>; }; l4per2_clkctrl: l4per2-clkctrl@c { compatible = "ti,clkctrl"; reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>; #clock-cells = <2>; }; l4per3_clkctrl: l4per3-clkctrl@14 { compatible = "ti,clkctrl"; reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>; #clock-cells = <2>; }; }; }; &prm { wkupaon_cm: wkupaon-cm@1800 { compatible = "ti,omap4-cm"; reg = <0x1800 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1800 0x100>; wkupaon_clkctrl: wkupaon-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x6c>; #clock-cells = <2>; }; }; }; diff --git a/sys/gnu/dts/arm/omap2.dtsi b/sys/gnu/dts/arm/omap2.dtsi index 0e453fec2e3a..000bf16de651 100644 --- a/sys/gnu/dts/arm/omap2.dtsi +++ b/sys/gnu/dts/arm/omap2.dtsi @@ -1,320 +1,299 @@ /* * Device Tree Source for OMAP2 SoC * * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ -#include #include #include #include / { compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; interrupt-parent = <&intc>; #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; i2c0 = &i2c1; i2c1 = &i2c2; }; cpus { #address-cells = <0>; #size-cells = <0>; cpu { compatible = "arm,arm1136jf-s"; device_type = "cpu"; }; }; pmu { compatible = "arm,arm1136-pmu"; interrupts = <3>; }; soc { compatible = "ti,omap-infra"; mpu { compatible = "ti,omap2-mpu"; ti,hwmods = "mpu"; }; }; ocp { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; ti,hwmods = "l3_main"; aes: aes@480a6000 { compatible = "ti,omap2-aes"; ti,hwmods = "aes"; reg = <0x480a6000 0x50>; dmas = <&sdma 9 &sdma 10>; dma-names = "tx", "rx"; }; hdq1w: 1w@480b2000 { compatible = "ti,omap2420-1w"; ti,hwmods = "hdq1w"; reg = <0x480b2000 0x1000>; interrupts = <58>; }; intc: interrupt-controller@1 { compatible = "ti,omap2-intc"; interrupt-controller; #interrupt-cells = <1>; reg = <0x480FE000 0x1000>; }; - target-module@48056000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x48056000 0x4>, - <0x4805602c 0x4>, - <0x48056028 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - ; - ti,syss-mask = <1>; - clocks = <&core_l3_ck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48056000 0x1000>; - - sdma: dma-controller@0 { - compatible = "ti,omap2420-sdma", "ti,omap-sdma"; - reg = <0 0x1000>; - interrupts = <12>, - <13>, - <14>, - <15>; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <64>; - }; + sdma: dma-controller@48056000 { + compatible = "ti,omap2430-sdma", "ti,omap2420-sdma"; + ti,hwmods = "dma"; + reg = <0x48056000 0x1000>; + interrupts = <12>, + <13>, + <14>, + <15>; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <64>; }; i2c1: i2c@48070000 { compatible = "ti,omap2-i2c"; ti,hwmods = "i2c1"; reg = <0x48070000 0x80>; #address-cells = <1>; #size-cells = <0>; interrupts = <56>; dmas = <&sdma 27 &sdma 28>; dma-names = "tx", "rx"; }; i2c2: i2c@48072000 { compatible = "ti,omap2-i2c"; ti,hwmods = "i2c2"; reg = <0x48072000 0x80>; #address-cells = <1>; #size-cells = <0>; interrupts = <57>; dmas = <&sdma 29 &sdma 30>; dma-names = "tx", "rx"; }; mcspi1: spi@48098000 { compatible = "ti,omap2-mcspi"; ti,hwmods = "mcspi1"; reg = <0x48098000 0x100>; interrupts = <65>; dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38 &sdma 39 &sdma 40 &sdma 41 &sdma 42>; dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3"; }; mcspi2: spi@4809a000 { compatible = "ti,omap2-mcspi"; ti,hwmods = "mcspi2"; reg = <0x4809a000 0x100>; interrupts = <66>; dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>; dma-names = "tx0", "rx0", "tx1", "rx1"; }; rng: rng@480a0000 { compatible = "ti,omap2-rng"; ti,hwmods = "rng"; reg = <0x480a0000 0x50>; interrupts = <52>; }; sham: sham@480a4000 { compatible = "ti,omap2-sham"; ti,hwmods = "sham"; reg = <0x480a4000 0x64>; interrupts = <51>; dmas = <&sdma 13>; dma-names = "rx"; }; uart1: serial@4806a000 { compatible = "ti,omap2-uart"; ti,hwmods = "uart1"; reg = <0x4806a000 0x2000>; interrupts = <72>; dmas = <&sdma 49 &sdma 50>; dma-names = "tx", "rx"; clock-frequency = <48000000>; }; uart2: serial@4806c000 { compatible = "ti,omap2-uart"; ti,hwmods = "uart2"; reg = <0x4806c000 0x400>; interrupts = <73>; dmas = <&sdma 51 &sdma 52>; dma-names = "tx", "rx"; clock-frequency = <48000000>; }; uart3: serial@4806e000 { compatible = "ti,omap2-uart"; ti,hwmods = "uart3"; reg = <0x4806e000 0x400>; interrupts = <74>; dmas = <&sdma 53 &sdma 54>; dma-names = "tx", "rx"; clock-frequency = <48000000>; }; timer2: timer@4802a000 { compatible = "ti,omap2420-timer"; reg = <0x4802a000 0x400>; interrupts = <38>; ti,hwmods = "timer2"; }; timer3: timer@48078000 { compatible = "ti,omap2420-timer"; reg = <0x48078000 0x400>; interrupts = <39>; ti,hwmods = "timer3"; }; timer4: timer@4807a000 { compatible = "ti,omap2420-timer"; reg = <0x4807a000 0x400>; interrupts = <40>; ti,hwmods = "timer4"; }; timer5: timer@4807c000 { compatible = "ti,omap2420-timer"; reg = <0x4807c000 0x400>; interrupts = <41>; ti,hwmods = "timer5"; ti,timer-dsp; }; timer6: timer@4807e000 { compatible = "ti,omap2420-timer"; reg = <0x4807e000 0x400>; interrupts = <42>; ti,hwmods = "timer6"; ti,timer-dsp; }; timer7: timer@48080000 { compatible = "ti,omap2420-timer"; reg = <0x48080000 0x400>; interrupts = <43>; ti,hwmods = "timer7"; ti,timer-dsp; }; timer8: timer@48082000 { compatible = "ti,omap2420-timer"; reg = <0x48082000 0x400>; interrupts = <44>; ti,hwmods = "timer8"; ti,timer-dsp; }; timer9: timer@48084000 { compatible = "ti,omap2420-timer"; reg = <0x48084000 0x400>; interrupts = <45>; ti,hwmods = "timer9"; ti,timer-pwm; }; timer10: timer@48086000 { compatible = "ti,omap2420-timer"; reg = <0x48086000 0x400>; interrupts = <46>; ti,hwmods = "timer10"; ti,timer-pwm; }; timer11: timer@48088000 { compatible = "ti,omap2420-timer"; reg = <0x48088000 0x400>; interrupts = <47>; ti,hwmods = "timer11"; ti,timer-pwm; }; timer12: timer@4808a000 { compatible = "ti,omap2420-timer"; reg = <0x4808a000 0x400>; interrupts = <48>; ti,hwmods = "timer12"; ti,timer-pwm; }; dss: dss@48050000 { compatible = "ti,omap2-dss"; reg = <0x48050000 0x400>; status = "disabled"; ti,hwmods = "dss_core"; #address-cells = <1>; #size-cells = <1>; ranges; dispc@48050400 { compatible = "ti,omap2-dispc"; reg = <0x48050400 0x400>; interrupts = <25>; ti,hwmods = "dss_dispc"; }; rfbi: encoder@48050800 { compatible = "ti,omap2-rfbi"; reg = <0x48050800 0x400>; status = "disabled"; ti,hwmods = "dss_rfbi"; }; venc: encoder@48050c00 { compatible = "ti,omap2-venc"; reg = <0x48050c00 0x400>; status = "disabled"; ti,hwmods = "dss_venc"; }; }; }; }; diff --git a/sys/gnu/dts/arm/omap2430.dtsi b/sys/gnu/dts/arm/omap2430.dtsi index 15ef7593be12..7f57af2f10ac 100644 --- a/sys/gnu/dts/arm/omap2430.dtsi +++ b/sys/gnu/dts/arm/omap2430.dtsi @@ -1,325 +1,321 @@ /* * Device Tree Source for OMAP243x SoC * * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ #include "omap2.dtsi" / { compatible = "ti,omap2430", "ti,omap2"; ocp { l4_wkup: l4_wkup@49000000 { compatible = "ti,omap2-l4-wkup", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x49000000 0x31000>; prcm: prcm@6000 { compatible = "ti,omap2-prcm"; reg = <0x6000 0x1000>; prcm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; prcm_clockdomains: clockdomains { }; }; scm: scm@2000 { compatible = "ti,omap2-scm", "simple-bus"; reg = <0x2000 0x1000>; #address-cells = <1>; #size-cells = <1>; #pinctrl-cells = <1>; ranges = <0 0x2000 0x1000>; omap2430_pmx: pinmux@30 { compatible = "ti,omap2430-padconf", "pinctrl-single"; reg = <0x30 0x0154>; #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <1>; pinctrl-single,register-width = <8>; pinctrl-single,function-mask = <0x3f>; }; scm_conf: scm_conf@270 { compatible = "syscon", "simple-bus"; reg = <0x270 0x240>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x270 0x240>; scm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; pbias_regulator: pbias_regulator@230 { compatible = "ti,pbias-omap2", "ti,pbias-omap"; reg = <0x230 0x4>; syscon = <&scm_conf>; pbias_mmc_reg: pbias_mmc_omap2430 { regulator-name = "pbias_mmc_omap2430"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; }; }; }; scm_clockdomains: clockdomains { }; }; counter32k: counter@20000 { compatible = "ti,omap-counter32k"; reg = <0x20000 0x20>; ti,hwmods = "counter_32k"; }; }; gpio1: gpio@4900c000 { compatible = "ti,omap2-gpio"; reg = <0x4900c000 0x200>; interrupts = <29>; ti,hwmods = "gpio1"; ti,gpio-always-on; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio2: gpio@4900e000 { compatible = "ti,omap2-gpio"; reg = <0x4900e000 0x200>; interrupts = <30>; ti,hwmods = "gpio2"; ti,gpio-always-on; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio3: gpio@49010000 { compatible = "ti,omap2-gpio"; reg = <0x49010000 0x200>; interrupts = <31>; ti,hwmods = "gpio3"; ti,gpio-always-on; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio4: gpio@49012000 { compatible = "ti,omap2-gpio"; reg = <0x49012000 0x200>; interrupts = <32>; ti,hwmods = "gpio4"; ti,gpio-always-on; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio5: gpio@480b6000 { compatible = "ti,omap2-gpio"; reg = <0x480b6000 0x200>; interrupts = <33>; ti,hwmods = "gpio5"; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpmc: gpmc@6e000000 { compatible = "ti,omap2430-gpmc"; reg = <0x6e000000 0x1000>; #address-cells = <2>; #size-cells = <1>; interrupts = <20>; gpmc,num-cs = <8>; gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; interrupt-controller; #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; }; mcbsp1: mcbsp@48074000 { compatible = "ti,omap2430-mcbsp"; reg = <0x48074000 0xff>; reg-names = "mpu"; interrupts = <64>, /* OCP compliant interrupt */ <59>, /* TX interrupt */ <60>, /* RX interrupt */ <61>; /* RX overflow interrupt */ interrupt-names = "common", "tx", "rx", "rx_overflow"; ti,buffer-size = <128>; ti,hwmods = "mcbsp1"; dmas = <&sdma 31>, <&sdma 32>; dma-names = "tx", "rx"; status = "disabled"; }; mcbsp2: mcbsp@48076000 { compatible = "ti,omap2430-mcbsp"; reg = <0x48076000 0xff>; reg-names = "mpu"; interrupts = <16>, /* OCP compliant interrupt */ <62>, /* TX interrupt */ <63>; /* RX interrupt */ interrupt-names = "common", "tx", "rx"; ti,buffer-size = <128>; ti,hwmods = "mcbsp2"; dmas = <&sdma 33>, <&sdma 34>; dma-names = "tx", "rx"; status = "disabled"; }; mcbsp3: mcbsp@4808c000 { compatible = "ti,omap2430-mcbsp"; reg = <0x4808c000 0xff>; reg-names = "mpu"; interrupts = <17>, /* OCP compliant interrupt */ <89>, /* TX interrupt */ <90>; /* RX interrupt */ interrupt-names = "common", "tx", "rx"; ti,buffer-size = <128>; ti,hwmods = "mcbsp3"; dmas = <&sdma 17>, <&sdma 18>; dma-names = "tx", "rx"; status = "disabled"; }; mcbsp4: mcbsp@4808e000 { compatible = "ti,omap2430-mcbsp"; reg = <0x4808e000 0xff>; reg-names = "mpu"; interrupts = <18>, /* OCP compliant interrupt */ <54>, /* TX interrupt */ <55>; /* RX interrupt */ interrupt-names = "common", "tx", "rx"; ti,buffer-size = <128>; ti,hwmods = "mcbsp4"; dmas = <&sdma 19>, <&sdma 20>; dma-names = "tx", "rx"; status = "disabled"; }; mcbsp5: mcbsp@48096000 { compatible = "ti,omap2430-mcbsp"; reg = <0x48096000 0xff>; reg-names = "mpu"; interrupts = <19>, /* OCP compliant interrupt */ <81>, /* TX interrupt */ <82>; /* RX interrupt */ interrupt-names = "common", "tx", "rx"; ti,buffer-size = <128>; ti,hwmods = "mcbsp5"; dmas = <&sdma 21>, <&sdma 22>; dma-names = "tx", "rx"; status = "disabled"; }; mmc1: mmc@4809c000 { compatible = "ti,omap2-hsmmc"; reg = <0x4809c000 0x200>; interrupts = <83>; ti,hwmods = "mmc1"; ti,dual-volt; dmas = <&sdma 61>, <&sdma 62>; dma-names = "tx", "rx"; pbias-supply = <&pbias_mmc_reg>; }; mmc2: mmc@480b4000 { compatible = "ti,omap2-hsmmc"; reg = <0x480b4000 0x200>; interrupts = <86>; ti,hwmods = "mmc2"; dmas = <&sdma 47>, <&sdma 48>; dma-names = "tx", "rx"; }; mailbox: mailbox@48094000 { compatible = "ti,omap2-mailbox"; reg = <0x48094000 0x200>; interrupts = <26>; ti,hwmods = "mailbox"; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <6>; mbox_dsp: dsp { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; }; timer1: timer@49018000 { compatible = "ti,omap2420-timer"; reg = <0x49018000 0x400>; interrupts = <37>; ti,hwmods = "timer1"; ti,timer-alwon; }; mcspi3: spi@480b8000 { compatible = "ti,omap2-mcspi"; ti,hwmods = "mcspi3"; reg = <0x480b8000 0x100>; interrupts = <91>; dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>; dma-names = "tx0", "rx0", "tx1", "rx1"; }; usb_otg_hs: usb_otg_hs@480ac000 { compatible = "ti,omap2-musb"; ti,hwmods = "usb_otg_hs"; reg = <0x480ac000 0x1000>; interrupts = <93>; }; wd_timer2: wdt@49016000 { compatible = "ti,omap2-wdt"; ti,hwmods = "wd_timer2"; reg = <0x49016000 0x80>; }; }; }; -&sdma { - compatible = "ti,omap2430-sdma", "ti,omap-sdma"; -}; - &i2c1 { compatible = "ti,omap2430-i2c"; }; &i2c2 { compatible = "ti,omap2430-i2c"; }; /include/ "omap24xx-clocks.dtsi" /include/ "omap2430-clocks.dtsi" diff --git a/sys/gnu/dts/arm/omap3-beagle-xm.dts b/sys/gnu/dts/arm/omap3-beagle-xm.dts index 125ed933ca75..1aa99fc1487a 100644 --- a/sys/gnu/dts/arm/omap3-beagle-xm.dts +++ b/sys/gnu/dts/arm/omap3-beagle-xm.dts @@ -1,419 +1,419 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; #include "omap36xx.dtsi" / { model = "TI OMAP3 BeagleBoard xM"; - compatible = "ti,omap3-beagle-xm", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "ti,omap3-beagle-xm", "ti,omap36xx", "ti,omap3"; cpus { cpu@0 { cpu0-supply = <&vcc>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; aliases { display0 = &dvi0; display1 = &tv0; ethernet = ðernet; }; /* fixed 26MHz oscillator */ hfclk_26m: oscillator { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <26000000>; }; leds { compatible = "gpio-leds"; heartbeat { label = "beagleboard::usr0"; gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ linux,default-trigger = "heartbeat"; }; mmc { label = "beagleboard::usr1"; gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ linux,default-trigger = "mmc0"; }; }; pwmleds { compatible = "pwm-leds"; pmu_stat { label = "beagleboard::pmu_stat"; pwms = <&twl_pwmled 1 7812500>; max-brightness = <127>; }; }; sound { compatible = "ti,omap-twl4030"; ti,model = "omap3beagle"; ti,mcbsp = <&mcbsp2>; }; gpio_keys { compatible = "gpio-keys"; user { label = "user"; gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; linux,code = <0x114>; wakeup-source; }; }; /* HS USB Port 2 Power */ hsusb2_power: hsusb2_power_reg { compatible = "regulator-fixed"; regulator-name = "hsusb2_vbus"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ startup-delay-us = <70000>; }; /* HS USB Host PHY on PORT 2 */ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ vcc-supply = <&hsusb2_power>; #phy-cells = <0>; }; tfp410: encoder0 { compatible = "ti,tfp410"; powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>; /* XXX pinctrl from twl */ ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; tfp410_in: endpoint { remote-endpoint = <&dpi_out>; }; }; port@1 { reg = <1>; tfp410_out: endpoint { remote-endpoint = <&dvi_connector_in>; }; }; }; }; dvi0: connector0 { compatible = "dvi-connector"; label = "dvi"; digital; ddc-i2c-bus = <&i2c3>; port { dvi_connector_in: endpoint { remote-endpoint = <&tfp410_out>; }; }; }; tv0: connector1 { compatible = "svideo-connector"; label = "tv"; port { tv_connector_in: endpoint { remote-endpoint = <&venc_out>; }; }; }; etb@5401b000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0x5401b000 0x1000>; clocks = <&emu_src_ck>; clock-names = "apb_pclk"; in-ports { port { etb_in: endpoint { remote-endpoint = <&etm_out>; }; }; }; }; etm@54010000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0x54010000 0x1000>; clocks = <&emu_src_ck>; clock-names = "apb_pclk"; out-ports { port { etm_out: endpoint { remote-endpoint = <&etb_in>; }; }; }; }; }; &omap3_pmx_wkup { gpio1_pins: pinmux_gpio1_pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */ >; }; dss_dpi_pins2: pinmux_dss_dpi_pins1 { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ >; }; }; &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = < &hsusb2_pins >; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ >; }; hsusb2_pins: pinmux_hsusb2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ >; }; dss_dpi_pins1: pinmux_dss_dpi_pins2 { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ >; }; }; &omap3_pmx_core2 { pinctrl-names = "default"; pinctrl-0 = < &hsusb2_2_pins >; hsusb2_2_pins: pinmux_hsusb2_2_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ >; }; }; &i2c1 { clock-frequency = <2600000>; twl: twl@48 { reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; clocks = <&hfclk_26m>; clock-names = "fck"; twl_audio: audio { compatible = "ti,twl4030-audio"; codec { }; }; twl_power: power { compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off"; ti,use_poweroff; }; }; }; #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" &i2c2 { clock-frequency = <400000>; }; &i2c3 { clock-frequency = <100000>; }; &mmc1 { vmmc-supply = <&vmmc1>; vqmmc-supply = <&vsim>; bus-width = <8>; }; &mmc2 { status = "disabled"; }; &mmc3 { status = "disabled"; }; &twl_gpio { ti,use-leds; /* pullups: BIT(1) */ ti,pullups = <0x000002>; /* * pulldowns: * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) * BIT(15), BIT(16), BIT(17) */ ti,pulldowns = <0x03a1c4>; }; &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; phys = <&usb2_phy>; phy-names = "usb2-phy"; mode = <3>; power = <50>; }; &uart3 { interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; &gpio1 { pinctrl-names = "default"; pinctrl-0 = <&gpio1_pins>; }; &usbhshost { port2-mode = "ehci-phy"; }; &usbhsehci { phys = <0 &hsusb2_phy>; #address-cells = <1>; #size-cells = <0>; hub@2 { compatible = "usb424,9514"; reg = <2>; #address-cells = <1>; #size-cells = <0>; ethernet: usbether@1 { compatible = "usb424,ec00"; reg = <1>; }; }; }; &vaux2 { regulator-name = "usb_1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; &mcbsp2 { status = "okay"; }; &dss { status = "ok"; pinctrl-names = "default"; pinctrl-0 = < &dss_dpi_pins1 &dss_dpi_pins2 >; port { dpi_out: endpoint { remote-endpoint = <&tfp410_in>; data-lines = <24>; }; }; }; &venc { status = "ok"; vdda-supply = <&vdac>; port { venc_out: endpoint { remote-endpoint = <&tv_connector_in>; ti,channels = <2>; }; }; }; diff --git a/sys/gnu/dts/arm/omap3-beagle.dts b/sys/gnu/dts/arm/omap3-beagle.dts index 4ed3f93f5841..e3df3c166902 100644 --- a/sys/gnu/dts/arm/omap3-beagle.dts +++ b/sys/gnu/dts/arm/omap3-beagle.dts @@ -1,436 +1,436 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; #include "omap34xx.dtsi" / { model = "TI OMAP3 BeagleBoard"; - compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3"; + compatible = "ti,omap3-beagle", "ti,omap3"; cpus { cpu@0 { cpu0-supply = <&vcc>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; aliases { display0 = &dvi0; display1 = &tv0; }; leds { compatible = "gpio-leds"; pmu_stat { label = "beagleboard::pmu_stat"; gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ }; heartbeat { label = "beagleboard::usr0"; gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ linux,default-trigger = "heartbeat"; }; mmc { label = "beagleboard::usr1"; gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ linux,default-trigger = "mmc0"; }; }; /* HS USB Port 2 Power */ hsusb2_power: hsusb2_power_reg { compatible = "regulator-fixed"; regulator-name = "hsusb2_vbus"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ startup-delay-us = <70000>; }; /* HS USB Host PHY on PORT 2 */ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ vcc-supply = <&hsusb2_power>; #phy-cells = <0>; }; sound { compatible = "ti,omap-twl4030"; ti,model = "omap3beagle"; ti,mcbsp = <&mcbsp2>; }; gpio_keys { compatible = "gpio-keys"; user { label = "user"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; linux,code = <0x114>; wakeup-source; }; }; tfp410: encoder0 { compatible = "ti,tfp410"; powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ pinctrl-names = "default"; pinctrl-0 = <&tfp410_pins>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; tfp410_in: endpoint { remote-endpoint = <&dpi_out>; }; }; port@1 { reg = <1>; tfp410_out: endpoint { remote-endpoint = <&dvi_connector_in>; }; }; }; }; dvi0: connector0 { compatible = "dvi-connector"; label = "dvi"; digital; ddc-i2c-bus = <&i2c3>; port { dvi_connector_in: endpoint { remote-endpoint = <&tfp410_out>; }; }; }; tv0: connector1 { compatible = "svideo-connector"; label = "tv"; port { tv_connector_in: endpoint { remote-endpoint = <&venc_out>; }; }; }; etb@540000000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0x5401b000 0x1000>; clocks = <&emu_src_ck>; clock-names = "apb_pclk"; in-ports { port { etb_in: endpoint { remote-endpoint = <&etm_out>; }; }; }; }; etm@54010000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0x54010000 0x1000>; clocks = <&emu_src_ck>; clock-names = "apb_pclk"; out-ports { port { etm_out: endpoint { remote-endpoint = <&etb_in>; }; }; }; }; }; &omap3_pmx_wkup { gpio1_pins: pinmux_gpio1_pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ >; }; }; &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = < &hsusb2_pins >; hsusb2_pins: pinmux_hsusb2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; tfp410_pins: pinmux_tfp410_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ >; }; dss_dpi_pins: pinmux_dss_dpi_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ >; }; }; &omap3_pmx_core2 { pinctrl-names = "default"; pinctrl-0 = < &hsusb2_2_pins >; hsusb2_2_pins: pinmux_hsusb2_2_pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ >; }; }; &i2c1 { clock-frequency = <2600000>; twl: twl@48 { reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; twl_audio: audio { compatible = "ti,twl4030-audio"; codec { }; }; }; }; #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" &i2c3 { clock-frequency = <100000>; }; &mmc1 { vmmc-supply = <&vmmc1>; vqmmc-supply = <&vsim>; bus-width = <8>; }; &mmc2 { status = "disabled"; }; &mmc3 { status = "disabled"; }; &usbhshost { port2-mode = "ehci-phy"; }; &usbhsehci { phys = <0 &hsusb2_phy>; }; &twl_gpio { ti,use-leds; /* pullups: BIT(1) */ ti,pullups = <0x000002>; /* * pulldowns: * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) * BIT(15), BIT(16), BIT(17) */ ti,pulldowns = <0x03a1c4>; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; }; &gpio1 { pinctrl-names = "default"; pinctrl-0 = <&gpio1_pins>; }; &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; phys = <&usb2_phy>; phy-names = "usb2-phy"; mode = <3>; power = <50>; }; &vaux2 { regulator-name = "vdd_ehci"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; &mcbsp2 { status = "okay"; }; /* Needed to power the DPI pins */ &vpll2 { regulator-always-on; }; &dss { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; port { dpi_out: endpoint { remote-endpoint = <&tfp410_in>; data-lines = <24>; }; }; }; &venc { status = "ok"; vdda-supply = <&vdac>; port { venc_out: endpoint { remote-endpoint = <&tv_connector_in>; ti,channels = <2>; }; }; }; &gpmc { status = "ok"; ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */ /* Chip select 0 */ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* NAND I/O window, 4 bytes */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ ti,nand-ecc-opt = "ham1"; rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ nand-bus-width = <16>; #address-cells = <1>; #size-cells = <1>; gpmc,device-width = <2>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <36>; gpmc,cs-wr-off-ns = <36>; gpmc,adv-on-ns = <6>; gpmc,adv-rd-off-ns = <24>; gpmc,adv-wr-off-ns = <36>; gpmc,oe-on-ns = <6>; gpmc,oe-off-ns = <48>; gpmc,we-on-ns = <6>; gpmc,we-off-ns = <30>; gpmc,rd-cycle-ns = <72>; gpmc,wr-cycle-ns = <72>; gpmc,access-ns = <54>; gpmc,wr-access-ns = <30>; partition@0 { label = "X-Loader"; reg = <0 0x80000>; }; partition@80000 { label = "U-Boot"; reg = <0x80000 0x1e0000>; }; partition@1c0000 { label = "U-Boot Env"; reg = <0x260000 0x20000>; }; partition@280000 { label = "Kernel"; reg = <0x280000 0x400000>; }; partition@780000 { label = "Filesystem"; reg = <0x680000 0xf980000>; }; }; }; diff --git a/sys/gnu/dts/arm/omap3-cm-t3530.dts b/sys/gnu/dts/arm/omap3-cm-t3530.dts index 32dbaeaed147..76e52c78cbb4 100644 --- a/sys/gnu/dts/arm/omap3-cm-t3530.dts +++ b/sys/gnu/dts/arm/omap3-cm-t3530.dts @@ -1,60 +1,60 @@ // SPDX-License-Identifier: GPL-2.0 /* * Support for CompuLab CM-T3530 */ /dts-v1/; #include "omap34xx.dtsi" #include "omap3-cm-t3x30.dtsi" / { model = "CompuLab CM-T3530"; - compatible = "compulab,omap3-cm-t3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; + compatible = "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3"; /* Regulator to trigger the reset signal of the Wifi module */ mmc2_sdio_reset: regulator-mmc2-sdio-reset { compatible = "regulator-fixed"; regulator-name = "regulator-mmc2-sdio-reset"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; &omap3_pmx_core { mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ >; }; }; &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; vmmc-supply = <&mmc2_sdio_reset>; non-removable; bus-width = <4>; cap-power-off-card; }; &dss { status = "ok"; pinctrl-names = "default"; pinctrl-0 = < &dss_dpi_pins_common &dss_dpi_pins_cm_t35x >; }; diff --git a/sys/gnu/dts/arm/omap3-cm-t3730.dts b/sys/gnu/dts/arm/omap3-cm-t3730.dts index 683819bf0915..6e944dfa0f3d 100644 --- a/sys/gnu/dts/arm/omap3-cm-t3730.dts +++ b/sys/gnu/dts/arm/omap3-cm-t3730.dts @@ -1,98 +1,98 @@ // SPDX-License-Identifier: GPL-2.0 /* * Support for CompuLab CM-T3730 */ /dts-v1/; #include "omap36xx.dtsi" #include "omap3-cm-t3x30.dtsi" / { model = "CompuLab CM-T3730"; - compatible = "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3"; wl12xx_vmmc2: wl12xx_vmmc2 { compatible = "regulator-fixed"; regulator-name = "vw1271"; pinctrl-names = "default"; pinctrl-0 = <&wl12xx_gpio>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; /* gpio73 */ startup-delay-us = <20000>; enable-active-high; }; wl12xx_vaux2: wl12xx_vaux2 { compatible = "regulator-fixed"; regulator-name = "vwl1271_vaux2"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; vin-supply = <&vaux2>; }; }; &omap3_pmx_wkup { dss_dpi_pins_cm_t3730: pinmux_dss_dpi_pins_cm_t3730 { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a08, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ >; }; }; &omap3_pmx_core { mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ >; }; wl12xx_gpio: pinmux_wl12xx_gpio { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* dss_data3.gpio_73 */ OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 */ >; }; }; &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; vmmc-supply = <&wl12xx_vmmc2>; vqmmc-supply = <&wl12xx_vaux2>; non-removable; bus-width = <4>; cap-power-off-card; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio5>; interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */ ref-clock-frequency = <38400000>; }; }; &dss { status = "ok"; pinctrl-names = "default"; pinctrl-0 = < &dss_dpi_pins_common &dss_dpi_pins_cm_t3730 >; }; diff --git a/sys/gnu/dts/arm/omap3-devkit8000-lcd43.dts b/sys/gnu/dts/arm/omap3-devkit8000-lcd43.dts index afed85078ad8..a80fc60bc773 100644 --- a/sys/gnu/dts/arm/omap3-devkit8000-lcd43.dts +++ b/sys/gnu/dts/arm/omap3-devkit8000-lcd43.dts @@ -1,34 +1,34 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Author: Anthoine Bourgeois */ /dts-v1/; /* * 4.3'' LCD panel sold with devkit8000 board */ #include "omap3-devkit8000-lcd-common.dtsi" / { model = "TimLL OMAP3 Devkit8000 with 4.3'' LCD panel"; - compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3"; + compatible = "timll,omap3-devkit8000", "ti,omap3"; lcd0: display { panel-timing { clock-frequency = <10164705>; hactive = <480>; vactive = <272>; hfront-porch = <2>; hback-porch = <2>; hsync-len = <41>; vback-porch = <2>; vfront-porch = <2>; vsync-len = <10>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <1>; }; }; }; diff --git a/sys/gnu/dts/arm/omap3-devkit8000-lcd70.dts b/sys/gnu/dts/arm/omap3-devkit8000-lcd70.dts index 07c51a105c0d..0753776071f8 100644 --- a/sys/gnu/dts/arm/omap3-devkit8000-lcd70.dts +++ b/sys/gnu/dts/arm/omap3-devkit8000-lcd70.dts @@ -1,34 +1,34 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Author: Anthoine Bourgeois */ /dts-v1/; /* * 7.0'' LCD panel sold with some devkit8000 board */ #include "omap3-devkit8000-lcd-common.dtsi" / { model = "TimLL OMAP3 Devkit8000 with 7.0'' LCD panel"; - compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3"; + compatible = "timll,omap3-devkit8000", "ti,omap3"; lcd0: display { panel-timing { clock-frequency = <40000000>; hactive = <800>; vactive = <480>; hfront-porch = <1>; hback-porch = <1>; hsync-len = <48>; vback-porch = <25>; vfront-porch = <12>; vsync-len = <3>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <1>; }; }; }; diff --git a/sys/gnu/dts/arm/omap3-devkit8000.dts b/sys/gnu/dts/arm/omap3-devkit8000.dts index 162d0726b008..faafc48d8f61 100644 --- a/sys/gnu/dts/arm/omap3-devkit8000.dts +++ b/sys/gnu/dts/arm/omap3-devkit8000.dts @@ -1,16 +1,16 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Author: Anthoine Bourgeois */ /dts-v1/; #include "omap3-devkit8000-common.dtsi" / { model = "TimLL OMAP3 Devkit8000"; - compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3"; + compatible = "timll,omap3-devkit8000", "ti,omap3"; aliases { display1 = &dvi0; display2 = &tv0; }; }; diff --git a/sys/gnu/dts/arm/omap3-echo.dts b/sys/gnu/dts/arm/omap3-echo.dts index 93ffeddada1e..e69de29bb2d1 100644 --- a/sys/gnu/dts/arm/omap3-echo.dts +++ b/sys/gnu/dts/arm/omap3-echo.dts @@ -1,461 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2019 André Hentschel - */ -/dts-v1/; - -#include "dm3725.dtsi" - -#include - -/ { - model = "Amazon Echo (first generation)"; - compatible = "amazon,omap3-echo", "ti,omap3630", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0xc600000>; /* 198 MB */ - }; - - vcc5v: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc3v3: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc1v8: fixedregulator2 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <40>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - - mute-button { - label = "mute"; - linux,code = ; - gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; /* GPIO_70 */ - wakeup-source; - }; - - help-button { - label = "help"; - linux,code = ; - gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; /* GPIO_72 */ - wakeup-source; - }; - }; - - rotary: rotary-encoder { - compatible = "rotary-encoder"; - gpios = < - &gpio3 5 GPIO_ACTIVE_HIGH /* GPIO_69 */ - &gpio3 12 GPIO_ACTIVE_HIGH /* GPIO_76 */ - >; - linux,axis = ; - rotary-encoder,relative-axis; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - - lp5523A: lp5523A@32 { - compatible = "national,lp5523"; - label = "q1"; - reg = <0x32>; - clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ - enable-gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* GPIO_109 */ - - chan0 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan1 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan2 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan3 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan4 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan5 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan6 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan7 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan8 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - }; - - lp5523B: lp5523B@33 { - compatible = "national,lp5523"; - label = "q3"; - reg = <0x33>; - clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ - - chan0 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan1 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan2 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan3 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan4 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan5 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan6 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan7 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan8 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - }; - - lp5523C: lp5523C@34 { - compatible = "national,lp5523"; - label = "q4"; - reg = <0x34>; - clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ - - chan0 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan1 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan2 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan3 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan4 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan5 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan6 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan7 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan8 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - }; - - lp5523D: lp552D@35 { - compatible = "national,lp5523"; - label = "q2"; - reg = <0x35>; - clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ - - chan0 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan1 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan2 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan3 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan4 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan5 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan6 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan7 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - chan8 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - }; - }; -}; - -#include "tps65910.dtsi" - -&omap3_pmx_core { - tps_pins: pinmux_tps_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_INPUT_PULLUP | PIN_OFF_OUTPUT_LOW | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20dc, PIN_INPUT | MUX_MODE4) /* dss_data0.gpio_70 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* dss_data2.gpio_72 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */ - >; - }; -}; - -&omap3_pmx_core2 { - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ - OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ - >; - }; -}; - -&mmc1 { - status = "okay"; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc_reg>; -}; - -&mmc2 { - status = "okay"; - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vmmc_reg>; -}; - -&mmc3 { - status = "okay"; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - non-removable; - disable-wp; - mmc-pwrseq = <&sdio_pwrseq>; - vmmc-supply = <&vcc3v3>; - vqmmc-supply = <&vcc1v8>; -}; - -&tps { - pinctrl-names = "default"; - pinctrl-0 = <&tps_pins>; - - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - ti,en-ck32k-xtal; - ti,system-power-controller; - - vcc1-supply = <&vcc5v>; - vcc2-supply = <&vcc5v>; - vcc3-supply = <&vcc5v>; - vcc4-supply = <&vcc5v>; - vcc5-supply = <&vcc5v>; - vcc6-supply = <&vcc5v>; - vcc7-supply = <&vcc5v>; - vccio-supply = <&vcc5v>; - - regulators { - - vio_reg: regulator@1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - regulator-name = "vdd_dsp"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-gta04.dtsi b/sys/gnu/dts/arm/omap3-gta04.dtsi index 409a758c99f1..b6ef1a7ac8a4 100644 --- a/sys/gnu/dts/arm/omap3-gta04.dtsi +++ b/sys/gnu/dts/arm/omap3-gta04.dtsi @@ -1,873 +1,873 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 Marek Belisko * * Based on omap3-beagle-xm.dts */ /dts-v1/; #include "omap36xx.dtsi" #include / { model = "OMAP3 GTA04"; - compatible = "ti,omap3-gta04", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "ti,omap3-gta04", "ti,omap36xx", "ti,omap3"; cpus { cpu@0 { cpu0-supply = <&vcc>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; chosen { stdout-path = &uart3; }; aliases { display0 = &lcd; display1 = &tv0; }; ldo_3v3: fixedregulator { compatible = "regulator-fixed"; regulator-name = "ldo_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; /* fixed 26MHz oscillator */ hfclk_26m: oscillator { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <26000000>; }; gpio-keys { compatible = "gpio-keys"; aux-button { label = "aux"; linux,code = ; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; wakeup-source; }; }; antenna-detect { compatible = "gpio-keys"; gps_antenna_button: gps-antenna-button { label = "GPS_EXT_ANT"; linux,input-type = ; linux,code = ; gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* GPIO144 */ interrupt-parent = <&gpio5>; interrupts = <16 IRQ_TYPE_EDGE_BOTH>; debounce-interval = <10>; wakeup-source; }; }; sound { compatible = "ti,omap-twl4030"; ti,model = "gta04"; ti,mcbsp = <&mcbsp2>; }; /* GSM audio */ sound_telephony { compatible = "simple-audio-card"; simple-audio-card,name = "GTA04 voice"; simple-audio-card,bitclock-master = <&telephony_link_master>; simple-audio-card,frame-master = <&telephony_link_master>; simple-audio-card,format = "i2s"; simple-audio-card,bitclock-inversion; simple-audio-card,frame-inversion; simple-audio-card,cpu { sound-dai = <&mcbsp4>; }; telephony_link_master: simple-audio-card,codec { sound-dai = <>m601_codec>; }; }; gtm601_codec: gsm_codec { compatible = "option,gtm601"; #sound-dai-cells = <0>; }; spi_lcd: spi_lcd { compatible = "spi-gpio"; #address-cells = <0x1>; #size-cells = <0x0>; pinctrl-names = "default"; pinctrl-0 = <&spi_gpio_pins>; gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>; gpio-miso = <&gpio1 18 GPIO_ACTIVE_HIGH>; gpio-mosi = <&gpio1 20 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; /* lcd panel */ lcd: td028ttec1@0 { compatible = "tpo,td028ttec1"; reg = <0>; spi-max-frequency = <100000>; spi-cpol; spi-cpha; spi-cs-high; backlight= <&backlight>; label = "lcd"; port { lcd_in: endpoint { remote-endpoint = <&dpi_out>; }; }; }; }; backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm11 0 12000000 0>; pwm-names = "backlight"; brightness-levels = <0 11 20 30 40 50 60 70 80 90 100>; default-brightness-level = <9>; /* => 90 */ pinctrl-names = "default"; pinctrl-0 = <&backlight_pins>; }; pwm11: dmtimer-pwm { compatible = "ti,omap-dmtimer-pwm"; ti,timers = <&timer11>; #pwm-cells = <3>; }; hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; #phy-cells = <0>; }; tv0: connector { compatible = "composite-video-connector"; label = "tv"; port { tv_connector_in: endpoint { remote-endpoint = <&opa_out>; }; }; }; tv_amp: opa362 { compatible = "ti,opa362"; enable-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; /* GPIO_23 to enable video out amplifier */ ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; opa_in: endpoint { remote-endpoint = <&venc_out>; }; }; port@1 { reg = <1>; opa_out: endpoint { remote-endpoint = <&tv_connector_in>; }; }; }; }; wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&tca6507 0 GPIO_ACTIVE_LOW>; /* W2CBW003 reset through tca6507 */ }; /* devconf0 setup for mcbsp1 clock pins */ pinmux_mcbsp1@48002274 { compatible = "pinctrl-single"; reg = <0x48002274 4>; /* CONTROL_DEVCONF0 */ #address-cells = <1>; #size-cells = <0>; pinctrl-single,bit-per-mux; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x7>; /* MCBSP1 CLK pinmux */ #pinctrl-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp1_devconf0_pins>; mcbsp1_devconf0_pins: pinmux_mcbsp1_devconf0_pins { /* offset bits mask */ pinctrl-single,bits = <0x00 0x08 0x1c>; /* set MCBSP1_CLKR */ }; }; /* devconf1 setup for tvout pins */ pinmux_tv_out@480022d8 { compatible = "pinctrl-single"; reg = <0x480022d8 4>; /* CONTROL_DEVCONF1 */ #address-cells = <1>; #size-cells = <0>; pinctrl-single,bit-per-mux; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x81>; /* TV out pin control */ #pinctrl-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&tv_acbias_devconf1_pins>; tv_acbias_devconf1_pins: pinmux_tv_acbias_devconf1_pins { /* offset bits mask */ pinctrl-single,bits = <0x00 0x40800 0x40800>; /* set TVOUTBYPASS and TVOUTACEN */ }; }; }; &omap3_pmx_wkup { gpio1_pins: pinmux_gpio1_pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_clkout.gpio_10 */ >; }; }; &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = < &hsusb2_pins >; hsusb2_pins: pinmux_hsusb2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ >; }; uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ >; }; backlight_pins: backlight_pins_pinmux { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20ba, MUX_MODE3) /* gpt11/gpio57 */ >; }; dss_dpi_pins: pinmux_dss_dpi_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ >; }; gps_pins: pinmux_gps_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* gpio145 */ >; }; hdq_pins: hdq_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.hdq */ >; }; bmp085_pins: pinmux_bmp085_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2136, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio113 */ >; }; bma180_pins: pinmux_bma180_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213a, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio115 */ >; }; itg3200_pins: pinmux_itg3200_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio56 */ >; }; hmc5843_pins: pinmux_hmc5843_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2134, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio112 */ >; }; penirq_pins: pinmux_penirq_pins { pinctrl-single,pins = < /* here we could enable to wakeup the cpu from suspend by a pen touch */ OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio160 */ >; }; camera_pins: pinmux_camera_pins { pinctrl-single,pins = < /* set up parallel camera interface */ OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_hs */ OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_vs */ OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */ OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_pclk */ OMAP3_CORE1_IOPAD(0x2114, PIN_OUTPUT | MUX_MODE4) /* cam_fld = gpio_98 */ OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d0 */ OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d1 */ OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d2 */ OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d3 */ OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d4 */ OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d5 */ OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d6 */ OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d7 */ OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d8 */ OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d9 */ OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d10 */ OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d10 */ OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE0) /* cam_xclkb */ OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* cam_wen = gpio_167 */ OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLDOWN | MUX_MODE4) /* cam_strobe */ >; }; mcbsp1_pins: pinmux_mcbsp1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkr.mcbsp1_clkr - gpio_156 FM interrupt */ OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_clkr.mcbsp1_fsr */ OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dx */ OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dr */ /* mcbsp_clks is used as PENIRQ */ /* OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT | MUX_MODE0) mcbsp_clks.mcbsp_clks */ OMAP3_CORE1_IOPAD(0x2196, PIN_INPUT | MUX_MODE0) /* mcbsp_clks.mcbsp1_fsx */ OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0) /* mcbsp1_clkx.mcbsp1_clkx */ >; }; mcbsp2_pins: pinmux_mcbsp2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_clkx */ OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2_dr */ OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2_dx */ >; }; mcbsp3_pins: pinmux_mcbsp3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.mcbsp3_dx */ OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dx.mcbsp3_dr */ OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clkx.mcbsp3_clkx */ OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_clkx.mcbsp3_fsx */ >; }; mcbsp4_pins: pinmux_mcbsp4_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_clkx.mcbsp4_clkx */ OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_clkx.mcbsp4_dr */ OMAP3_CORE1_IOPAD(0x218a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_dx.mcbsp4_fsx */ >; }; }; &omap3_pmx_core2 { pinctrl-names = "default"; pinctrl-0 = < &hsusb2_2_pins >; hsusb2_2_pins: pinmux_hsusb2_2_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ >; }; spi_gpio_pins: spi_gpio_pinmux { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */ OMAP3630_CORE2_IOPAD(0x25e6, PIN_OUTPUT | MUX_MODE4) /* cs */ OMAP3630_CORE2_IOPAD(0x25e8, PIN_OUTPUT | MUX_MODE4) /* tx */ OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE4) /* rx */ >; }; }; &i2c1 { clock-frequency = <2600000>; twl: twl@48 { reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; clocks = <&hfclk_26m>; clock-names = "fck"; twl_audio: audio { compatible = "ti,twl4030-audio"; ti,enable-vibra = <1>; codec { ti,ramp_delay_value = <3>; }; }; twl_power: power { compatible = "ti,twl4030-power"; ti,use_poweroff; }; }; }; #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" &i2c2 { clock-frequency = <400000>; /* pressure sensor */ bmp085@77 { compatible = "bosch,bmp085"; reg = <0x77>; pinctrl-names = "default"; pinctrl-0 = <&bmp085_pins>; interrupt-parent = <&gpio4>; interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* GPIO_113 */ }; /* accelerometer */ bma180@41 { compatible = "bosch,bma180"; reg = <0x41>; pinctrl-names = "default"; pintcrl-0 = <&bma180_pins>; interrupt-parent = <&gpio4>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_115 */ }; /* gyroscope */ itg3200@68 { compatible = "invensense,itg3200"; reg = <0x68>; pinctrl-names = "default"; pinctrl-0 = <&itg3200_pins>; interrupt-parent = <&gpio2>; interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* GPIO_56 */ }; /* leds + gpios */ tca6507: tca6507@45 { compatible = "ti,tca6507"; #address-cells = <1>; #size-cells = <0>; reg = <0x45>; gpio-controller; #gpio-cells = <2>; gta04_led0: red_aux@0 { label = "gta04:red:aux"; reg = <0x0>; }; gta04_led1: green_aux@1 { label = "gta04:green:aux"; reg = <0x1>; }; gta04_led3: red_power@3 { label = "gta04:red:power"; reg = <0x3>; linux,default-trigger = "default-on"; }; gta04_led4: green_power@4 { label = "gta04:green:power"; reg = <0x4>; }; wifi_reset: wifi_reset@6 { /* reference as <&tca_gpios 0 0> since it is currently the only GPIO */ reg = <0x6>; compatible = "gpio"; }; }; /* compass aka magnetometer */ hmc5843@1e { compatible = "honeywell,hmc5883l"; reg = <0x1e>; pinctrl-names = "default"; pinctrl-0 = <&hmc5843_pins>; interrupt-parent = <&gpio4>; interrupts = <16 IRQ_TYPE_EDGE_FALLING>; /* gpio112 */ }; /* touchscreen */ tsc2007@48 { compatible = "ti,tsc2007"; reg = <0x48>; pinctrl-names = "default"; pinctrl-0 = <&penirq_pins>; interrupt-parent = <&gpio6>; interrupts = <0 IRQ_TYPE_EDGE_FALLING>; /* GPIO_160 */ gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* GPIO_160 */ ti,x-plate-ohms = <600>; touchscreen-size-x = <480>; touchscreen-size-y = <640>; touchscreen-max-pressure = <1000>; touchscreen-fuzz-x = <3>; touchscreen-fuzz-y = <8>; touchscreen-fuzz-pressure = <10>; touchscreen-inverted-y; }; /* RFID EEPROM */ m24lr64@50 { compatible = "atmel,24c64"; reg = <0x50>; }; }; &i2c3 { clock-frequency = <100000>; }; &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; phys = <&usb2_phy>; phy-names = "usb2-phy"; mode = <3>; power = <50>; }; &usbhshost { port2-mode = "ehci-phy"; }; &usbhsehci { phys = <0 &hsusb2_phy>; }; &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; vmmc-supply = <&vmmc1>; bus-width = <4>; ti,non-removable; broken-cd; /* hardware has no CD */ }; &mmc2 { vmmc-supply = <&vaux4>; bus-width = <4>; ti,non-removable; cap-power-off-card; mmc-pwrseq = <&wifi_pwrseq>; }; &mmc3 { status = "disabled"; }; #define BIT(x) (1 << (x)) &twl_gpio { /* pullups: BIT(2) */ ti,pullups = ; /* * pulldowns: * BIT(0), BIT(1), BIT(6), BIT(7), BIT(8), BIT(13) * BIT(15), BIT(16), BIT(17) */ ti,pulldowns = <(BIT(0) | BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(13) | BIT(15) | BIT(16) | BIT(17))>; }; &twl_keypad { status = "disabled"; }; &gpio1 { pinctrl-names = "default"; pinctrl-0 = <&gpio1_pins>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; gnss: gnss { compatible = "wi2wi,w2sg0004"; pinctrl-names = "default"; pinctrl-0 = <&gps_pins>; sirf,onoff-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; lna-supply = <&vsim>; vcc-supply = <&ldo_3v3>; }; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; }; &charger { ti,bb-uvolt = <3200000>; ti,bb-uamp = <150>; }; /* spare */ &vaux1 { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3000000>; }; /* sensors */ &vaux2 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; /* we should never switch off while vio is on! */ }; /* camera */ &vaux3 { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; }; /* WLAN/BT */ &vaux4 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3150000>; }; /* GPS LNA */ &vsim { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3150000>; }; /* Needed to power the DPI pins */ &vpll2 { regulator-always-on; }; &dss { pinctrl-names = "default"; pinctrl-0 = < &dss_dpi_pins >; status = "okay"; vdds_dsi-supply = <&vpll2>; port { dpi_out: endpoint { remote-endpoint = <&lcd_in>; data-lines = <24>; }; }; }; &venc { status = "okay"; vdda-supply = <&vdac>; port { venc_out: endpoint { remote-endpoint = <&opa_in>; ti,channels = <1>; ti,invert-polarity; }; }; }; &gpmc { ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ ti,nand-ecc-opt = "ham1"; rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ nand-bus-width = <16>; #address-cells = <1>; #size-cells = <1>; gpmc,device-width = <2>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <44>; gpmc,cs-wr-off-ns = <44>; gpmc,adv-on-ns = <6>; gpmc,adv-rd-off-ns = <34>; gpmc,adv-wr-off-ns = <44>; gpmc,oe-off-ns = <54>; gpmc,we-off-ns = <40>; gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; gpmc,sync-clk-ps = <0>; x-loader@0 { label = "X-Loader"; reg = <0 0x80000>; }; bootloaders@80000 { label = "U-Boot"; reg = <0x80000 0x1c0000>; }; bootloaders_env@240000 { label = "U-Boot Env"; reg = <0x240000 0x40000>; }; kernel@280000 { label = "Kernel"; reg = <0x280000 0x600000>; }; filesystem@880000 { label = "File System"; reg = <0x880000 0>; /* 0 = MTDPART_SIZ_FULL */ }; }; }; &mcbsp1 { /* FM Transceiver PCM */ status = "ok"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp1_pins>; }; &mcbsp2 { /* TPS65950 I2S */ status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&mcbsp2_pins>; }; &mcbsp3 { /* Bluetooth PCM */ status = "ok"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp3_pins>; }; &mcbsp4 { /* GSM voice PCM */ status = "ok"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp4_pins>; }; &hdqw1w { pinctrl-names = "default"; pinctrl-0 = <&hdq_pins>; }; /* image signal processor within OMAP3 SoC */ &isp { ports { port@0 { reg = <0>; parallel_ep: endpoint { ti,isp-clock-divisor = <1>; ti,strobe-mode; bus-width = <8>;/* Used data lines */ data-shift = <2>; /* Lines 9:2 are used */ hsync-active = <0>; /* Active low */ vsync-active = <1>; /* Active high */ data-active = <1>;/* Active high */ pclk-sample = <1>;/* Falling */ }; }; /* port@1 and port@2 are not used by GTA04 */ }; }; diff --git a/sys/gnu/dts/arm/omap3-ha-lcd.dts b/sys/gnu/dts/arm/omap3-ha-lcd.dts index c9ecbc45c8e2..badb9b3c8897 100644 --- a/sys/gnu/dts/arm/omap3-ha-lcd.dts +++ b/sys/gnu/dts/arm/omap3-ha-lcd.dts @@ -1,162 +1,162 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * Copyright (C) 2014 Stefan Roese */ #include "omap3-ha-common.dtsi" / { model = "TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOM"; - compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; + compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3"; }; &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = < &hsusbb2_pins &powerdown_input_pins &fpga_boot0_pins &fpga_boot1_pins &led_blue_pins &led_green_pins &led_red_pins &touchscreen_wake_pins >; touchscreen_irq_pins: pinmux_touchscreen_irq_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_136, Touchscreen IRQ */ >; }; touchscreen_wake_pins: pinmux_touchscreen_wake_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x212c, PIN_OUTPUT_PULLUP | MUX_MODE4) /* gpio_110, Touchscreen Wake */ >; }; dss_dpi_pins: pinmux_dss_dpi_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ >; }; lte430_pins: pinmux_lte430_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ >; }; backlight_pins: pinmux_backlight_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ >; }; }; /* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */ &i2c2 { status = "disabled"; }; &i2c3 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; }; /* Needed to power the DPI pins */ &vpll2 { regulator-always-on; }; &dss { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; port { dpi_out: endpoint { remote-endpoint = <&lcd_in>; data-lines = <24>; }; }; }; / { aliases { display0 = &lcd0; }; lcd0: display { compatible = "panel-dpi"; label = "lcd"; pinctrl-names = "default"; pinctrl-0 = <<e430_pins>; enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */ port { lcd_in: endpoint { remote-endpoint = <&dpi_out>; }; }; panel-timing { clock-frequency = <31250000>; hactive = <800>; vactive = <480>; hfront-porch = <40>; hback-porch = <86>; hsync-len = <1>; vback-porch = <30>; vfront-porch = <13>; vsync-len = <3>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <1>; }; }; backlight { compatible = "gpio-backlight"; pinctrl-names = "default"; pinctrl-0 = <&backlight_pins>; gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */ default-on; }; }; diff --git a/sys/gnu/dts/arm/omap3-ha.dts b/sys/gnu/dts/arm/omap3-ha.dts index 35c4e15abeb7..a5365252bfbe 100644 --- a/sys/gnu/dts/arm/omap3-ha.dts +++ b/sys/gnu/dts/arm/omap3-ha.dts @@ -1,25 +1,25 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * Copyright (C) 2014 Stefan Roese */ #include "omap3-ha-common.dtsi" / { model = "TI OMAP3 HEAD acoustics baseboard with TAO3530 SOM"; - compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; + compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3"; }; &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = < &hsusbb2_pins &powerdown_input_pins &fpga_boot0_pins &fpga_boot1_pins &led_blue_pins &led_green_pins &led_red_pins >; }; diff --git a/sys/gnu/dts/arm/omap3-igep0020-rev-f.dts b/sys/gnu/dts/arm/omap3-igep0020-rev-f.dts index 567232584f08..03dcd05fb8a0 100644 --- a/sys/gnu/dts/arm/omap3-igep0020-rev-f.dts +++ b/sys/gnu/dts/arm/omap3-igep0020-rev-f.dts @@ -1,59 +1,51 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for IGEPv2 Rev. F (TI OMAP AM/DM37x) * * Copyright (C) 2012 Javier Martinez Canillas * Copyright (C) 2012 Enric Balletbo i Serra */ #include "omap3-igep0020-common.dtsi" / { model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0020-rev-f", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "isee,omap3-igep0020-rev-f", "ti,omap36xx", "ti,omap3"; /* Regulator to trigger the WL_EN signal of the Wifi module */ lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { compatible = "regulator-fixed"; regulator-name = "regulator-lbep5clwmc-wlen"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */ enable-active-high; }; }; &omap3_pmx_core { lbep5clwmc_pins: pinmux_lbep5clwmc_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT | MUX_MODE4) /* mcspi1_cs3.gpio_177 - W_IRQ */ OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */ >; }; }; &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>; vmmc-supply = <&lbep5clwmc_wlen>; bus-width = <4>; non-removable; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio6>; interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* gpio 177 */ }; }; - -&uart2 { - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; /* gpio 137 */ - max-speed = <300000>; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-igep0020.dts b/sys/gnu/dts/arm/omap3-igep0020.dts index e341535a7162..6d0519e3dfd0 100644 --- a/sys/gnu/dts/arm/omap3-igep0020.dts +++ b/sys/gnu/dts/arm/omap3-igep0020.dts @@ -1,47 +1,47 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x) * * Copyright (C) 2012 Javier Martinez Canillas * Copyright (C) 2012 Enric Balletbo i Serra */ #include "omap3-igep0020-common.dtsi" / { model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0020", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3"; vmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "vmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; mmc2_pwrseq: mmc2_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>, /* gpio_139 - RESET_N_W */ <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 - WIFI_PDN */ }; }; &omap3_pmx_core { lbee1usjyc_pins: pinmux_lbee1usjyc_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */ >; }; }; /* On board Wifi module */ &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>; vmmc-supply = <&vmmcsdio_fixed>; mmc-pwrseq = <&mmc2_pwrseq>; bus-width = <4>; non-removable; }; diff --git a/sys/gnu/dts/arm/omap3-igep0030-rev-g.dts b/sys/gnu/dts/arm/omap3-igep0030-rev-g.dts index df6ba1219830..060acd1e803a 100644 --- a/sys/gnu/dts/arm/omap3-igep0030-rev-g.dts +++ b/sys/gnu/dts/arm/omap3-igep0030-rev-g.dts @@ -1,81 +1,73 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for IGEP COM MODULE Rev. G (TI OMAP AM/DM37x) * * Copyright (C) 2014 Javier Martinez Canillas * Copyright (C) 2014 Enric Balletbo i Serra */ #include "omap3-igep0030-common.dtsi" / { model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0030-rev-g", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "isee,omap3-igep0030-rev-g", "ti,omap36xx", "ti,omap3"; /* Regulator to trigger the WL_EN signal of the Wifi module */ lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { compatible = "regulator-fixed"; regulator-name = "regulator-lbep5clwmc-wlen"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */ enable-active-high; }; }; &omap3_pmx_core { lbep5clwmc_pins: pinmux_lbep5clwmc_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 - W_IRQ */ OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */ >; }; leds_pins: pinmux_leds_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */ >; }; }; &i2c2 { status = "disabled"; }; &leds { pinctrl-names = "default"; pinctrl-0 = <&leds_pins &leds_core2_pins>; boot { label = "omap3:green:boot"; gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>; vmmc-supply = <&lbep5clwmc_wlen>; bus-width = <4>; non-removable; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio5>; interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */ }; }; - -&uart2 { - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; /* gpio 137 */ - max-speed = <300000>; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-igep0030.dts b/sys/gnu/dts/arm/omap3-igep0030.dts index 32f31035daa2..25170bd3c573 100644 --- a/sys/gnu/dts/arm/omap3-igep0030.dts +++ b/sys/gnu/dts/arm/omap3-igep0030.dts @@ -1,59 +1,59 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for IGEP COM MODULE Rev. E (TI OMAP AM/DM37x) * * Copyright (C) 2012 Javier Martinez Canillas * Copyright (C) 2012 Enric Balletbo i Serra */ #include "omap3-igep0030-common.dtsi" / { model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0030", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3"; vmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "vmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; mmc2_pwrseq: mmc2_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>, /* gpio_139 - RESET_N_W */ <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 - WIFI_PDN */ }; }; &omap3_pmx_core { lbee1usjyc_pins: pinmux_lbee1usjyc_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */ >; }; }; &leds { pinctrl-names = "default"; pinctrl-0 = <&leds_core2_pins>; boot { label = "omap3:green:boot"; gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; /* LEDSYNC */ default-state = "on"; }; }; /* On board Wifi module */ &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>; vmmc-supply = <&vmmcsdio_fixed>; mmc-pwrseq = <&mmc2_pwrseq>; bus-width = <4>; non-removable; }; diff --git a/sys/gnu/dts/arm/omap3-ldp.dts b/sys/gnu/dts/arm/omap3-ldp.dts index ec9ba04ef43b..9a5fde2d9bce 100644 --- a/sys/gnu/dts/arm/omap3-ldp.dts +++ b/sys/gnu/dts/arm/omap3-ldp.dts @@ -1,305 +1,305 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; #include #include "omap34xx.dtsi" #include "omap-gpmc-smsc911x.dtsi" / { model = "TI OMAP3430 LDP (Zoom1 Labrador)"; - compatible = "ti,omap3-ldp", "ti,omap3430", "ti,omap3"; + compatible = "ti,omap3-ldp", "ti,omap3"; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x8000000>; /* 128 MB */ }; cpus { cpu@0 { cpu0-supply = <&vcc>; }; }; gpio_keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_key_pins>; key_enter { label = "enter"; gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* gpio101 */ linux,code = ; wakeup-source; }; key_f1 { label = "f1"; gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* gpio102 */ linux,code = ; wakeup-source; }; key_f2 { label = "f2"; gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* gpio103 */ linux,code = ; wakeup-source; }; key_f3 { label = "f3"; gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* gpio104 */ linux,code = ; wakeup-source; }; key_f4 { label = "f4"; gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* gpio105 */ linux,code = ; wakeup-source; }; key_left { label = "left"; gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* gpio106 */ linux,code = ; wakeup-source; }; key_right { label = "right"; gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* gpio107 */ linux,code = ; wakeup-source; }; key_up { label = "up"; gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* gpio108 */ linux,code = ; wakeup-source; }; key_down { label = "down"; gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* gpio109 */ linux,code = ; wakeup-source; }; }; }; &gpmc { ranges = <0 0 0x30000000 0x1000000>, /* CS0 space, 16MB */ <1 0 0x08000000 0x1000000>; /* CS1 space, 16MB */ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ linux,mtd-name= "micron,nand"; nand-bus-width = <16>; gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <44>; gpmc,cs-wr-off-ns = <44>; gpmc,adv-on-ns = <6>; gpmc,adv-rd-off-ns = <34>; gpmc,adv-wr-off-ns = <44>; gpmc,we-off-ns = <40>; gpmc,oe-off-ns = <54>; gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "X-Loader"; reg = <0 0x80000>; }; partition@80000 { label = "U-Boot"; reg = <0x80000 0x140000>; }; partition@1c0000 { label = "Environment"; reg = <0x1c0000 0x40000>; }; partition@200000 { label = "Kernel"; reg = <0x200000 0x1e00000>; }; partition@2000000 { label = "Filesystem"; reg = <0x2000000 0x6000000>; }; }; ethernet@gpmc { interrupt-parent = <&gpio5>; interrupts = <24 IRQ_TYPE_LEVEL_LOW>; reg = <1 0 0xff>; }; }; &i2c1 { clock-frequency = <2600000>; twl: twl@48 { reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; twl_power: power { compatible = "ti,twl4030-power-idle"; ti,use_poweroff; }; }; }; #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" #include "omap3-panel-sharp-ls037v7dw01.dtsi" &backlight0 { gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; }; &i2c2 { clock-frequency = <400000>; }; &i2c3 { clock-frequency = <400000>; }; /* tps61130rsa enabled by twl4030 regen */ &lcd_3v3 { regulator-always-on; }; &lcd0 { enable-gpios = <&twl_gpio 15 GPIO_ACTIVE_HIGH>; /* lcd INI */ reset-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; /* gpio55, lcd RESB */ mode-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio56, lcd MO */ }; &mcspi1 { tsc2046@0 { interrupt-parent = <&gpio2>; interrupts = <22 0>; /* gpio54 */ pendown-gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; }; }; &mmc1 { /* See 35xx errata 2.1.1.128 in SPRZ278F */ compatible = "ti,omap3-pre-es3-hsmmc"; vmmc-supply = <&vmmc1>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; }; &mmc2 { status="disabled"; }; &mmc3 { status="disabled"; }; &omap3_pmx_core { gpio_key_pins: pinmux_gpio_key_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2.gpio_101 */ OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4) /* cam_d3.gpio_102 */ OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE4) /* cam_d4.gpio_103 */ OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE4) /* cam_d5.gpio_104 */ OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE4) /* cam_d6.gpio_105 */ OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE4) /* cam_d7.gpio_106 */ OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE4) /* cam_d8.gpio_107 */ OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE4) /* cam_d9.gpio_108 */ OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ >; }; musb_pins: pinmux_musb_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ OMAP3_CORE1_IOPAD(0x214A, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ OMAP3_CORE1_IOPAD(0x214C, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ >; }; }; &twl_keypad { linux,keymap = ; }; &uart3 { interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; }; &usb_otg_hs { pinctrl-names = "default"; pinctrl-0 = <&musb_pins>; interface-type = <0>; usb-phy = <&usb2_phy>; mode = <3>; power = <50>; }; &vaux1 { /* Needed for ads7846 */ regulator-name = "vcc"; }; diff --git a/sys/gnu/dts/arm/omap3-lilly-a83x.dtsi b/sys/gnu/dts/arm/omap3-lilly-a83x.dtsi index 73d477898ec2..c22833d4e568 100644 --- a/sys/gnu/dts/arm/omap3-lilly-a83x.dtsi +++ b/sys/gnu/dts/arm/omap3-lilly-a83x.dtsi @@ -1,459 +1,459 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2014 Christoph Fritz */ #include "omap36xx.dtsi" / { model = "INCOstartec LILLY-A83X module (DM3730)"; - compatible = "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3"; chosen { bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0"; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x8000000>; /* 128 MB */ }; leds { compatible = "gpio-leds"; led1 { label = "lilly-a83x::led1"; gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; }; sound { compatible = "ti,omap-twl4030"; ti,model = "lilly-a83x"; ti,mcbsp = <&mcbsp2>; }; reg_vcc3: vcc3 { compatible = "regulator-fixed"; regulator-name = "VCC3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; hsusb1_phy: hsusb1_phy { compatible = "usb-nop-xceiv"; vcc-supply = <®_vcc3>; #phy-cells = <0>; }; }; &omap3_pmx_wkup { pinctrl-names = "default"; lan9221_pins: pinmux_lan9221_pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ >; }; tsc2048_pins: pinmux_tsc2048_pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a16, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot6.gpio_8 */ >; }; mmc1cd_pins: pinmux_mmc1cd_pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 */ >; }; }; &omap3_pmx_core { pinctrl-names = "default"; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ >; }; uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clkx.uart2_tx */ OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */ >; }; i2c3_pins: pinmux_i2c3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ >; }; hsusb1_pins: pinmux_hsusb1_pins { pinctrl-single,pins = < /* GPIO 182 controls USB-Hub reset. But USB-Phy its * reset can't be controlled. So we clamp this GPIO to * high (PIN_OFF_OUTPUT_HIGH) to always enable USB-Hub. */ OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT_PULLUP | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcspi2_cs1.gpio_182 */ >; }; hsusb_otg_pins: pinmux_hsusb_otg_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ >; }; spi2_pins: pinmux_spi2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_clk.mcspi2_clk */ OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_simo.mcspi2_simo */ OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_somi.mcspi2_somi */ OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0.mcspi2_cs0 */ >; }; }; &omap3_pmx_core2 { pinctrl-names = "default"; hsusb1_2_pins: pinmux_hsusb1_2_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */ OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */ OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */ OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */ OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */ OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */ OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */ OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */ OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */ OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */ >; }; gpio1_pins: pinmux_gpio1_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* etk_d15.gpio_29 */ >; }; }; &gpio1 { pinctrl-names = "default"; pinctrl-0 = <&gpio1_pins>; }; &gpio6 { pinctrl-names = "default"; pinctrl-0 = <&hsusb1_pins>; }; &i2c1 { clock-frequency = <2600000>; pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; twl: twl@48 { reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; twl_audio: audio { compatible = "ti,twl4030-audio"; codec { }; }; }; }; #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" &twl { vmmc1: regulator-vmmc1 { regulator-always-on; }; vdd1: regulator-vdd1 { regulator-always-on; }; vdd2: regulator-vdd2 { regulator-always-on; }; }; &i2c2 { clock-frequency = <2600000>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; }; &i2c3 { clock-frequency = <2600000>; pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; gpiom1: gpio@20 { compatible = "microchip,mcp23017"; gpio-controller; #gpio-cells = <2>; reg = <0x20>; }; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; &uart4 { status = "disabled"; }; &mmc1 { cd-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; cd-inverted; vmmc-supply = <&vmmc1>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins &mmc1cd_pins>; cap-sdio-irq; cap-sd-highspeed; cap-mmc-highspeed; }; &mmc2 { status = "disabled"; }; &mmc3 { status = "disabled"; }; &mcspi2 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi2_pins>; tsc2046@0 { reg = <0>; /* CS0 */ compatible = "ti,tsc2046"; interrupt-parent = <&gpio1>; interrupts = <8 0>; /* boot6 / gpio_8 */ spi-max-frequency = <1000000>; pendown-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; vcc-supply = <®_vcc3>; pinctrl-names = "default"; pinctrl-0 = <&tsc2048_pins>; ti,x-min = /bits/ 16 <300>; ti,x-max = /bits/ 16 <3000>; ti,y-min = /bits/ 16 <600>; ti,y-max = /bits/ 16 <3600>; ti,x-plate-ohms = /bits/ 16 <80>; ti,pressure-max = /bits/ 16 <255>; ti,swap-xy; wakeup-source; }; }; &usbhsehci { phys = <&hsusb1_phy>; }; &usbhshost { pinctrl-names = "default"; pinctrl-0 = <&hsusb1_2_pins>; num-ports = <2>; port1-mode = "ehci-phy"; }; &usb_otg_hs { pinctrl-names = "default"; pinctrl-0 = <&hsusb_otg_pins>; interface-type = <0>; usb-phy = <&usb2_phy>; phys = <&usb2_phy>; phy-names = "usb2-phy"; mode = <3>; power = <50>; }; &mcbsp2 { status = "okay"; }; &gpmc { ranges = <0 0 0x30000000 0x1000000>, <7 0 0x15000000 0x01000000>; nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ nand-bus-width = <16>; ti,nand-ecc-opt = "bch8"; /* no elm on omap3 */ gpmc,mux-add-data = <0>; gpmc,device-width = <2>; gpmc,wait-pin = <0>; gpmc,wait-monitoring-ns = <0>; gpmc,burst-length= <4>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <100>; gpmc,cs-wr-off-ns = <100>; gpmc,adv-on-ns = <0>; gpmc,adv-rd-off-ns = <100>; gpmc,adv-wr-off-ns = <100>; gpmc,oe-on-ns = <5>; gpmc,oe-off-ns = <75>; gpmc,we-on-ns = <5>; gpmc,we-off-ns = <75>; gpmc,rd-cycle-ns = <100>; gpmc,wr-cycle-ns = <100>; gpmc,access-ns = <60>; gpmc,page-burst-access-ns = <5>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-samecsen; gpmc,cycle2cycle-delay-ns = <50>; gpmc,wr-data-mux-bus-ns = <75>; gpmc,wr-access-ns = <155>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "MLO"; reg = <0 0x80000>; }; partition@80000 { label = "u-boot"; reg = <0x80000 0x1e0000>; }; partition@260000 { label = "u-boot-environment"; reg = <0x260000 0x20000>; }; partition@280000 { label = "kernel"; reg = <0x280000 0x500000>; }; partition@780000 { label = "filesystem"; reg = <0x780000 0xf880000>; }; }; ethernet@7,0 { compatible = "smsc,lan9221", "smsc,lan9115"; bank-width = <2>; gpmc,mux-add-data = <2>; gpmc,cs-on-ns = <10>; gpmc,cs-rd-off-ns = <60>; gpmc,cs-wr-off-ns = <60>; gpmc,adv-on-ns = <0>; gpmc,adv-rd-off-ns = <10>; gpmc,adv-wr-off-ns = <10>; gpmc,oe-on-ns = <10>; gpmc,oe-off-ns = <60>; gpmc,we-on-ns = <10>; gpmc,we-off-ns = <60>; gpmc,rd-cycle-ns = <100>; gpmc,wr-cycle-ns = <100>; gpmc,access-ns = <50>; gpmc,page-burst-access-ns = <5>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <75>; gpmc,wr-data-mux-bus-ns = <15>; gpmc,wr-access-ns = <75>; gpmc,cycle2cycle-samecsen; gpmc,cycle2cycle-diffcsen; vddvario-supply = <®_vcc3>; vdd33a-supply = <®_vcc3>; reg-io-width = <4>; interrupt-parent = <&gpio5>; interrupts = <1 0x2>; reg = <7 0 0xff>; pinctrl-names = "default"; pinctrl-0 = <&lan9221_pins>; phy-mode = "mii"; }; }; diff --git a/sys/gnu/dts/arm/omap3-lilly-dbb056.dts b/sys/gnu/dts/arm/omap3-lilly-dbb056.dts index ecb4ef738e07..fec335400074 100644 --- a/sys/gnu/dts/arm/omap3-lilly-dbb056.dts +++ b/sys/gnu/dts/arm/omap3-lilly-dbb056.dts @@ -1,166 +1,166 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2014 Christoph Fritz */ /dts-v1/; #include "omap3-lilly-a83x.dtsi" / { model = "INCOstartec LILLY-DBB056 (DM3730)"; - compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3"; }; &twl { vaux2: regulator-vaux2 { compatible = "ti,twl4030-vaux2"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; }; }; &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = <&lcd_pins>; lan9117_pins: pinmux_lan9117_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* cam_fld.gpio_98 */ >; }; gpio4_pins: pinmux_gpio4_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* cam_xclkb.gpio_111 -> sja1000 IRQ */ >; }; gpio5_pins: pinmux_gpio5_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcbsp1_clk.gpio_156 -> enable DSS */ >; }; lcd_pins: pinmux_lcd_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ >; }; mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 -> wp */ OMAP3_CORE1_IOPAD(0x219c, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_rts_sd.gpio_164 -> cd */ >; }; spi1_pins: pinmux_spi1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ >; }; }; &gpio4 { pinctrl-names = "default"; pinctrl-0 = <&gpio4_pins>; }; &gpio5 { pinctrl-names = "default"; pinctrl-0 = <&gpio5_pins>; }; &mmc2 { status = "okay"; bus-width = <4>; vmmc-supply = <&vmmc1>; cd-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio_164 */ wp-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* gpio_163 */ pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; ti,dual-volt; }; &mcspi1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi1_pins>; }; &gpmc { ranges = <0 0 0x30000000 0x1000000>, /* nand assigned by COM a83x */ <4 0 0x20000000 0x01000000>, <7 0 0x15000000 0x01000000>; /* eth assigend by COM a83x */ ethernet@4,0 { compatible = "smsc,lan9117", "smsc,lan9115"; bank-width = <2>; gpmc,mux-add-data = <2>; gpmc,cs-on-ns = <10>; gpmc,cs-rd-off-ns = <65>; gpmc,cs-wr-off-ns = <65>; gpmc,adv-on-ns = <0>; gpmc,adv-rd-off-ns = <10>; gpmc,adv-wr-off-ns = <10>; gpmc,oe-on-ns = <10>; gpmc,oe-off-ns = <65>; gpmc,we-on-ns = <10>; gpmc,we-off-ns = <65>; gpmc,rd-cycle-ns = <100>; gpmc,wr-cycle-ns = <100>; gpmc,access-ns = <60>; gpmc,page-burst-access-ns = <5>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <75>; gpmc,wr-data-mux-bus-ns = <15>; gpmc,wr-access-ns = <75>; gpmc,cycle2cycle-samecsen; gpmc,cycle2cycle-diffcsen; vddvario-supply = <®_vcc3>; vdd33a-supply = <®_vcc3>; reg-io-width = <4>; interrupt-parent = <&gpio4>; interrupts = <2 0x2>; reg = <4 0 0xff>; pinctrl-names = "default"; pinctrl-0 = <&lan9117_pins>; phy-mode = "mii"; smsc,force-internal-phy; }; }; diff --git a/sys/gnu/dts/arm/omap3-n9.dts b/sys/gnu/dts/arm/omap3-n9.dts index 2495a696cec6..74c0ff2350d3 100644 --- a/sys/gnu/dts/arm/omap3-n9.dts +++ b/sys/gnu/dts/arm/omap3-n9.dts @@ -1,85 +1,85 @@ // SPDX-License-Identifier: GPL-2.0-only /* * omap3-n9.dts - Device Tree file for Nokia N9 * * Written by: Aaro Koskinen */ /dts-v1/; #include "omap3-n950-n9.dtsi" #include / { model = "Nokia N9"; - compatible = "nokia,omap3-n9", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "nokia,omap3-n9", "ti,omap36xx", "ti,omap3"; }; &i2c2 { smia_1: camera@10 { compatible = "nokia,smia"; reg = <0x10>; /* No reset gpio */ vana-supply = <&vaux3>; clocks = <&isp 0>; clock-frequency = <9600000>; nokia,nvm-size = <(16 * 64)>; flash-leds = <&as3645a_flash &as3645a_indicator>; port { smia_1_1: endpoint { link-frequencies = /bits/ 64 <199200000 210000000 499200000>; clock-lanes = <0>; data-lanes = <1 2>; remote-endpoint = <&csi2a_ep>; }; }; }; }; &i2c3 { ak8975@f { compatible = "asahi-kasei,ak8975"; reg = <0x0f>; }; }; &isp { vdd-csiphy1-supply = <&vaux2>; vdd-csiphy2-supply = <&vaux2>; ports { port@2 { reg = <2>; csi2a_ep: endpoint { remote-endpoint = <&smia_1_1>; clock-lanes = <2>; data-lanes = <1 3>; crc = <1>; lane-polarities = <1 1 1>; }; }; }; }; &modem { compatible = "nokia,n9-modem"; }; &lis302 { st,axis-x = <1>; /* LIS3_DEV_X */ st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */ st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ st,min-limit-x = <(-46)>; st,min-limit-y = <3>; st,min-limit-z = <3>; st,max-limit-x = <(-3)>; st,max-limit-y = <46>; st,max-limit-z = <46>; }; &twl_keypad { linux,keymap = < MATRIX_KEY(6, 8, KEY_VOLUMEUP) MATRIX_KEY(7, 8, KEY_VOLUMEDOWN) >; }; diff --git a/sys/gnu/dts/arm/omap3-n900.dts b/sys/gnu/dts/arm/omap3-n900.dts index 4089d97405c9..84a5ade1e865 100644 --- a/sys/gnu/dts/arm/omap3-n900.dts +++ b/sys/gnu/dts/arm/omap3-n900.dts @@ -1,1156 +1,1128 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Pavel Machek * Copyright (C) 2013-2014 Aaro Koskinen */ /dts-v1/; #include "omap34xx.dtsi" #include /* * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall * for omap AES HW crypto support. When linux kernel try to access memory of AES * blocks then kernel receive "Unhandled fault: external abort on non-linefetch" * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no * crash anymore) omap AES support will be disabled for all Nokia N900 devices. * There is "unofficial" version of bootloader which enables AES in L3 firewall * but it is not widely used and to prevent kernel crash rather AES is disabled. * There is also no runtime detection code if AES is disabled in L3 firewall... */ &aes { status = "disabled"; }; / { model = "Nokia N900"; compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3"; aliases { i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; display0 = &lcd; display1 = &tv; }; cpus { cpu@0 { cpu0-supply = <&vcc>; }; }; leds { compatible = "gpio-leds"; heartbeat { label = "debug::sleep"; gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* 162 */ linux,default-trigger = "default-on"; pinctrl-names = "default"; pinctrl-0 = <&debug_leds>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; gpio_keys { compatible = "gpio-keys"; camera_lens_cover { label = "Camera Lens Cover"; gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */ linux,input-type = ; linux,code = ; linux,can-disable; }; camera_focus { label = "Camera Focus"; gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */ linux,code = ; linux,can-disable; }; camera_capture { label = "Camera Capture"; gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */ linux,code = ; linux,can-disable; }; lock_button { label = "Lock Button"; gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */ linux,code = ; linux,can-disable; }; keypad_slide { label = "Keypad Slide"; gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */ linux,input-type = ; linux,code = ; linux,can-disable; }; proximity_sensor { label = "Proximity Sensor"; gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */ linux,input-type = ; linux,code = ; linux,can-disable; }; }; isp1707: isp1707 { compatible = "nxp,isp1707"; nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; usb-phy = <&usb2_phy>; }; tv: connector { compatible = "composite-video-connector"; label = "tv"; port { tv_connector_in: endpoint { remote-endpoint = <&venc_out>; }; }; }; sound: n900-audio { compatible = "nokia,n900-audio"; nokia,cpu-dai = <&mcbsp2>; nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>; nokia,headphone-amplifier = <&tpa6130a2>; tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */ jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */ eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */ speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; }; battery: n900-battery { compatible = "nokia,n900-battery"; io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>; io-channel-names = "temp", "bsi", "vbat"; }; pwm9: dmtimer-pwm { compatible = "ti,omap-dmtimer-pwm"; #pwm-cells = <3>; ti,timers = <&timer9>; ti,clock-source = <0x00>; /* timer_sys_ck */ }; ir: n900-ir { compatible = "nokia,n900-ir"; pwms = <&pwm9 0 26316 0>; /* 38000 Hz */ }; - rom_rng: rng { - compatible = "nokia,n900-rom-rng"; - clocks = <&rng_ick>; - clock-names = "ick"; - }; - /* controlled (enabled/disabled) directly by bcm2048 and wl1251 */ vctcxo: vctcxo { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <38400000>; }; }; &isp { vdds_csib-supply = <&vaux2>; pinctrl-names = "default"; pinctrl-0 = <&camera_pins>; ports { port@1 { reg = <1>; csi_isp: endpoint { remote-endpoint = <&csi_cam1>; bus-type = <3>; /* CCP2 */ clock-lanes = <1>; data-lanes = <0>; lane-polarity = <0 0>; /* Select strobe = <1> for back camera, <0> for front camera */ strobe = <1>; }; }; }; }; &omap3_pmx_core { pinctrl-names = "default"; uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */ OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx */ >; }; ethernet_pins: pinmux_ethernet_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */ OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ >; }; gpmc_pins: pinmux_gpmc_pins { pinctrl-single,pins = < /* address lines */ OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ /* data lines, gpmc_d0..d7 not muxable according to TRM */ OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ /* * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable * according to TRM. OneNAND seems to require PIN_INPUT on clock. */ OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ >; }; i2c3_pins: pinmux_i2c3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ >; }; debug_leds: pinmux_debug_led_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */ >; }; mcspi4_pins: pinmux_mcspi4_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */ OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */ OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ >; }; mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */ OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */ OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */ OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */ >; }; acx565akm_pins: pinmux_acx565akm_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */ >; }; dss_sdi_pins: pinmux_dss_sdi_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */ OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */ OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */ OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */ OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */ >; }; wl1251_pins: pinmux_wl1251 { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */ OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */ >; }; ssi_pins: pinmux_ssi { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ >; }; modem_pins: pinmux_modem { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */ OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */ OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */ OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */ OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */ OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */ >; }; camera_pins: pinmux_camera { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x210c, PIN_OUTPUT | MUX_MODE7) /* cam_hs */ OMAP3_CORE1_IOPAD(0x210e, PIN_OUTPUT | MUX_MODE7) /* cam_vs */ OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */ OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE7) /* cam_d4 */ OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6 */ OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7 */ OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE0) /* cam_d8 */ OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE0) /* cam_d9 */ OMAP3_CORE1_IOPAD(0x212a, PIN_OUTPUT | MUX_MODE7) /* cam_d10 */ OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE7) /* cam_xclkb */ OMAP3_CORE1_IOPAD(0x2132, PIN_OUTPUT | MUX_MODE0) /* cam_strobe */ >; }; }; &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; clock-frequency = <2200000>; twl: twl@48 { reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; }; }; #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" &vaux1 { regulator-name = "V28"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ regulator-always-on; /* due to battery cover sensor */ }; &vaux2 { regulator-name = "VCSI"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ }; &vaux3 { regulator-name = "VMMC2_30"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3000000>; regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ }; &vaux4 { regulator-name = "VCAM_ANA_28"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ }; &vmmc1 { regulator-name = "VMMC1"; regulator-min-microvolt = <1850000>; regulator-max-microvolt = <3150000>; regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ }; &vmmc2 { regulator-name = "V28_A"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3000000>; regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ regulator-always-on; /* due VIO leak to AIC34 VDDs */ }; &vpll1 { regulator-name = "VPLL"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ regulator-always-on; }; &vpll2 { regulator-name = "VSDI_CSI"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ regulator-always-on; }; &vsim { regulator-name = "VMMC2_IO_18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ }; &vio { regulator-name = "VIO"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; &vintana1 { regulator-name = "VINTANA1"; /* fixed to 1500000 */ regulator-always-on; }; &vintana2 { regulator-name = "VINTANA2"; regulator-min-microvolt = <2750000>; regulator-max-microvolt = <2750000>; regulator-always-on; }; &vintdig { regulator-name = "VINTDIG"; /* fixed to 1500000 */ regulator-always-on; }; -/* First two dma channels are reserved on secure omap3 */ -&sdma { - dma-channel-mask = <0xfffffffc>; -}; - &twl { twl_audio: audio { compatible = "ti,twl4030-audio"; ti,enable-vibra = <1>; }; twl_power: power { compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off"; ti,use_poweroff; }; }; &twl_keypad { linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q) MATRIX_KEY(0x00, 0x01, KEY_O) MATRIX_KEY(0x00, 0x02, KEY_P) MATRIX_KEY(0x00, 0x03, KEY_COMMA) MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE) MATRIX_KEY(0x00, 0x06, KEY_A) MATRIX_KEY(0x00, 0x07, KEY_S) MATRIX_KEY(0x01, 0x00, KEY_W) MATRIX_KEY(0x01, 0x01, KEY_D) MATRIX_KEY(0x01, 0x02, KEY_F) MATRIX_KEY(0x01, 0x03, KEY_G) MATRIX_KEY(0x01, 0x04, KEY_H) MATRIX_KEY(0x01, 0x05, KEY_J) MATRIX_KEY(0x01, 0x06, KEY_K) MATRIX_KEY(0x01, 0x07, KEY_L) MATRIX_KEY(0x02, 0x00, KEY_E) MATRIX_KEY(0x02, 0x01, KEY_DOT) MATRIX_KEY(0x02, 0x02, KEY_UP) MATRIX_KEY(0x02, 0x03, KEY_ENTER) MATRIX_KEY(0x02, 0x05, KEY_Z) MATRIX_KEY(0x02, 0x06, KEY_X) MATRIX_KEY(0x02, 0x07, KEY_C) MATRIX_KEY(0x02, 0x08, KEY_F9) MATRIX_KEY(0x03, 0x00, KEY_R) MATRIX_KEY(0x03, 0x01, KEY_V) MATRIX_KEY(0x03, 0x02, KEY_B) MATRIX_KEY(0x03, 0x03, KEY_N) MATRIX_KEY(0x03, 0x04, KEY_M) MATRIX_KEY(0x03, 0x05, KEY_SPACE) MATRIX_KEY(0x03, 0x06, KEY_SPACE) MATRIX_KEY(0x03, 0x07, KEY_LEFT) MATRIX_KEY(0x04, 0x00, KEY_T) MATRIX_KEY(0x04, 0x01, KEY_DOWN) MATRIX_KEY(0x04, 0x02, KEY_RIGHT) MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL) MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT) MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT) MATRIX_KEY(0x04, 0x08, KEY_F10) MATRIX_KEY(0x05, 0x00, KEY_Y) MATRIX_KEY(0x05, 0x08, KEY_F11) MATRIX_KEY(0x06, 0x00, KEY_U) MATRIX_KEY(0x07, 0x00, KEY_I) MATRIX_KEY(0x07, 0x01, KEY_F7) MATRIX_KEY(0x07, 0x02, KEY_F8) >; }; &twl_gpio { ti,pullups = <0x0>; ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ }; &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; clock-frequency = <100000>; tlv320aic3x: tlv320aic3x@18 { compatible = "ti,tlv320aic3x"; reg = <0x18>; reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */ ai3x-gpio-func = < 0 /* AIC3X_GPIO1_FUNC_DISABLED */ 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */ >; AVDD-supply = <&vmmc2>; DRVDD-supply = <&vmmc2>; IOVDD-supply = <&vio>; DVDD-supply = <&vio>; ai3x-micbias-vg = <1>; }; tlv320aic3x_aux: tlv320aic3x@19 { compatible = "ti,tlv320aic3x"; reg = <0x19>; reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */ AVDD-supply = <&vmmc2>; DRVDD-supply = <&vmmc2>; IOVDD-supply = <&vio>; DVDD-supply = <&vio>; ai3x-micbias-vg = <2>; }; tsl2563: tsl2563@29 { compatible = "amstaos,tsl2563"; reg = <0x29>; amstaos,cover-comp-gain = <16>; }; adp1653: led-controller@30 { compatible = "adi,adp1653"; reg = <0x30>; enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */ flash { flash-timeout-us = <500000>; flash-max-microamp = <320000>; led-max-microamp = <50000>; }; indicator { led-max-microamp = <17500>; }; }; lp5523: lp5523@32 { compatible = "national,lp5523"; reg = <0x32>; clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */ chan0 { chan-name = "lp5523:kb1"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; }; chan1 { chan-name = "lp5523:kb2"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; }; chan2 { chan-name = "lp5523:kb3"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; }; chan3 { chan-name = "lp5523:kb4"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; }; chan4 { chan-name = "lp5523:b"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; }; chan5 { chan-name = "lp5523:g"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; }; chan6 { chan-name = "lp5523:r"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; }; chan7 { chan-name = "lp5523:kb5"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; }; chan8 { chan-name = "lp5523:kb6"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; }; }; bq27200: bq27200@55 { compatible = "ti,bq27200"; reg = <0x55>; power-supplies = <&bq24150a>; }; /* Stereo headphone amplifier */ tpa6130a2: tpa6130a2@60 { compatible = "ti,tpa6130a2"; reg = <0x60>; Vdd-supply = <&vmmc2>; power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */ }; si4713: si4713@63 { compatible = "silabs,si4713"; reg = <0x63>; interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */ reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */ vio-supply = <&vio>; vdd-supply = <&vaux1>; }; bq24150a: bq24150a@6b { compatible = "ti,bq24150a"; reg = <0x6b>; ti,current-limit = <100>; ti,weak-battery-voltage = <3400>; ti,battery-regulation-voltage = <4200>; ti,charge-current = <650>; ti,termination-current = <100>; ti,resistor-sense = <68>; ti,usb-charger-detection = <&isp1707>; }; }; &i2c3 { pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; clock-frequency = <400000>; lis302dl: lis3lv02d@1d { compatible = "st,lis3lv02d"; reg = <0x1d>; Vdd-supply = <&vaux1>; Vdd_IO-supply = <&vio>; interrupt-parent = <&gpio6>; interrupts = <21 20>; /* 181 and 180 */ /* click flags */ st,click-single-x; st,click-single-y; st,click-single-z; /* Limits are 0.5g * value */ st,click-threshold-x = <8>; st,click-threshold-y = <8>; st,click-threshold-z = <10>; /* Click must be longer than time limit */ st,click-time-limit = <9>; /* Kind of debounce filter */ st,click-latency = <50>; /* Interrupt line 2 for click detection */ st,irq2-click; st,wakeup-x-hi; st,wakeup-y-hi; st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */ st,wakeup2-z-hi; st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */ st,hipass1-disable; st,hipass2-disable; st,axis-x = <1>; /* LIS3_DEV_X */ st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */ st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ st,min-limit-x = <(-32)>; st,min-limit-y = <3>; st,min-limit-z = <3>; st,max-limit-x = <(-3)>; st,max-limit-y = <32>; st,max-limit-z = <32>; }; cam1: camera@3e { compatible = "toshiba,et8ek8"; reg = <0x3e>; vana-supply = <&vaux4>; clocks = <&isp 0>; clock-names = "extclk"; clock-frequency = <9600000>; reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ lens-focus = <&ad5820>; port { csi_cam1: endpoint { bus-type = <3>; /* CCP2 */ strobe = <1>; clock-inv = <0>; crc = <1>; remote-endpoint = <&csi_isp>; }; }; }; /* D/A converter for auto-focus */ ad5820: dac@c { compatible = "adi,ad5820"; reg = <0x0c>; VANA-supply = <&vaux4>; #io-channel-cells = <0>; }; }; &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; vmmc-supply = <&vmmc1>; bus-width = <4>; /* For debugging, it is often good idea to remove this GPIO. It means you can remove back cover (to reboot by removing battery) and still use the MMC card. */ cd-gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* 160 */ }; /* most boards use vaux3, only some old versions use vmmc2 instead */ &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; vmmc-supply = <&vaux3>; vqmmc-supply = <&vsim>; bus-width = <8>; non-removable; no-sdio; no-sd; }; &mmc3 { status = "disabled"; }; &gpmc { ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ pinctrl-names = "default"; pinctrl-0 = <&gpmc_pins>; /* sys_ndmareq1 could be used by the driver, not as gpio65 though */ onenand@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "ti,omap2-onenand"; reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ - /* - * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported - * bootloader set values when booted with v5.1 - * (OneNAND Manufacturer: Samsung): - * - * cs0 GPMC_CS_CONFIG1: 0xfb001202 - * cs0 GPMC_CS_CONFIG2: 0x00111100 - * cs0 GPMC_CS_CONFIG3: 0x00020200 - * cs0 GPMC_CS_CONFIG4: 0x11001102 - * cs0 GPMC_CS_CONFIG5: 0x03101616 - * cs0 GPMC_CS_CONFIG6: 0x90060000 - */ gpmc,sync-read; gpmc,sync-write; gpmc,burst-length = <16>; gpmc,burst-read; gpmc,burst-wrap; gpmc,burst-write; - gpmc,device-width = <2>; - gpmc,mux-add-data = <2>; + gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ + gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */ gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <102>; - gpmc,cs-wr-off-ns = <102>; + gpmc,cs-rd-off-ns = <87>; + gpmc,cs-wr-off-ns = <87>; gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <12>; - gpmc,adv-wr-off-ns = <12>; - gpmc,oe-on-ns = <12>; - gpmc,oe-off-ns = <102>; + gpmc,adv-rd-off-ns = <10>; + gpmc,adv-wr-off-ns = <10>; + gpmc,oe-on-ns = <15>; + gpmc,oe-off-ns = <87>; gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <102>; - gpmc,rd-cycle-ns = <132>; - gpmc,wr-cycle-ns = <132>; - gpmc,access-ns = <96>; - gpmc,page-burst-access-ns = <18>; + gpmc,we-off-ns = <87>; + gpmc,rd-cycle-ns = <112>; + gpmc,wr-cycle-ns = <112>; + gpmc,access-ns = <81>; + gpmc,page-burst-access-ns = <15>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <6>; - gpmc,wr-data-mux-bus-ns = <36>; - gpmc,wr-access-ns = <96>; + gpmc,clk-activation-ns = <5>; + gpmc,wr-data-mux-bus-ns = <30>; + gpmc,wr-access-ns = <81>; gpmc,sync-clk-ps = <15000>; /* * MTD partition table corresponding to Nokia's * Maemo 5 (Fremantle) release. */ partition@0 { label = "bootloader"; reg = <0x00000000 0x00020000>; read-only; }; partition@1 { label = "config"; reg = <0x00020000 0x00060000>; }; partition@2 { label = "log"; reg = <0x00080000 0x00040000>; }; partition@3 { label = "kernel"; reg = <0x000c0000 0x00200000>; }; partition@4 { label = "initfs"; reg = <0x002c0000 0x00200000>; }; partition@5 { label = "rootfs"; reg = <0x004c0000 0x0fb40000>; }; }; /* Ethernet is on some early development boards and qemu */ ethernet@gpmc { compatible = "smsc,lan91c94"; interrupt-parent = <&gpio2>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */ reg = <1 0 0xf>; /* 16 byte IO range */ bank-width = <2>; pinctrl-names = "default"; pinctrl-0 = <ðernet_pins>; power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */ reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */ gpmc,device-width = <2>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <48>; gpmc,cs-wr-off-ns = <24>; gpmc,adv-on-ns = <0>; gpmc,adv-rd-off-ns = <0>; gpmc,adv-wr-off-ns = <0>; gpmc,we-on-ns = <12>; gpmc,we-off-ns = <18>; gpmc,oe-on-ns = <12>; gpmc,oe-off-ns = <48>; gpmc,page-burst-access-ns = <0>; gpmc,access-ns = <42>; gpmc,rd-cycle-ns = <180>; gpmc,wr-cycle-ns = <180>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,wait-monitoring-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wr-access-ns = <0>; gpmc,wr-data-mux-bus-ns = <12>; }; }; &mcspi1 { /* * For some reason, touchscreen is necessary for screen to work at * all on real hw. It works well without it on emulator. * * Also... order in the device tree actually matters here. */ tsc2005@0 { compatible = "ti,tsc2005"; spi-max-frequency = <6000000>; reg = <0>; vio-supply = <&vio>; reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */ interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>; /* 100 */ touchscreen-fuzz-x = <4>; touchscreen-fuzz-y = <7>; touchscreen-fuzz-pressure = <2>; touchscreen-size-x = <4096>; touchscreen-size-y = <4096>; touchscreen-max-pressure = <2048>; ti,x-plate-ohms = <280>; ti,esd-recovery-timeout-ms = <8000>; }; lcd: acx565akm@2 { compatible = "sony,acx565akm"; spi-max-frequency = <6000000>; reg = <2>; pinctrl-names = "default"; pinctrl-0 = <&acx565akm_pins>; label = "lcd"; reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */ port { lcd_in: endpoint { remote-endpoint = <&sdi_out>; }; }; }; }; &mcspi4 { pinctrl-names = "default"; pinctrl-0 = <&mcspi4_pins>; wl1251@0 { pinctrl-names = "default"; pinctrl-0 = <&wl1251_pins>; vio-supply = <&vio>; compatible = "ti,wl1251"; reg = <0>; spi-max-frequency = <48000000>; spi-cpol; spi-cpha; ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ interrupt-parent = <&gpio2>; interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */ clocks = <&vctcxo>; }; }; -/* RNG not directly accessible on n900, see omap3-rom-rng instead */ -&rng_target { - status = "disabled"; -}; - &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; phys = <&usb2_phy>; phy-names = "usb2-phy"; mode = <2>; power = <50>; }; &uart1 { status = "disabled"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; bcm2048: bluetooth { compatible = "brcm,bcm2048-nokia", "nokia,h4p-bluetooth"; reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; /* 91 */ host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */ bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */ clocks = <&vctcxo>; clock-names = "sysclk"; }; }; &uart3 { interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; &dss { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&dss_sdi_pins>; vdds_sdi-supply = <&vaux1>; ports { #address-cells = <1>; #size-cells = <0>; port@1 { reg = <1>; sdi_out: endpoint { remote-endpoint = <&lcd_in>; datapairs = <2>; }; }; }; }; &venc { status = "ok"; vdda-supply = <&vdac>; port { venc_out: endpoint { remote-endpoint = <&tv_connector_in>; ti,channels = <1>; }; }; }; &mcbsp2 { status = "ok"; }; &ssi_port1 { pinctrl-names = "default"; pinctrl-0 = <&ssi_pins>; ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ modem: hsi-client { compatible = "nokia,n900-modem"; pinctrl-names = "default"; pinctrl-0 = <&modem_pins>; hsi-channel-ids = <0>, <1>, <2>, <3>; hsi-channel-names = "mcsaab-control", "speech-control", "speech-data", "mcsaab-data"; hsi-speed-kbps = <55000>; hsi-mode = "frame"; hsi-flow = "synchronized"; hsi-arb-mode = "round-robin"; interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */ gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */ <&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */ <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */ <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */ <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */ gpio-names = "cmt_apeslpx", "cmt_rst_rq", "cmt_en", "cmt_rst", "cmt_bsi"; }; }; &ssi_port2 { status = "disabled"; }; diff --git a/sys/gnu/dts/arm/omap3-n950-n9.dtsi b/sys/gnu/dts/arm/omap3-n950-n9.dtsi index a075b63f3087..6681d4519e97 100644 --- a/sys/gnu/dts/arm/omap3-n950-n9.dtsi +++ b/sys/gnu/dts/arm/omap3-n950-n9.dtsi @@ -1,491 +1,498 @@ // SPDX-License-Identifier: GPL-2.0-only /* * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff) * * Written by: Aaro Koskinen */ #include "omap36xx.dtsi" / { cpus { cpu@0 { cpu0-supply = <&vcc>; + operating-points = < + /* kHz uV */ + 300000 1012500 + 600000 1200000 + 800000 1325000 + 1000000 1375000 + >; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; vemmc: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "VEMMC"; regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; gpio = <&gpio5 29 GPIO_ACTIVE_HIGH>; /* gpio line 157 */ startup-delay-us = <150>; enable-active-high; }; vwlan_fixed: fixedregulator2 { compatible = "regulator-fixed"; regulator-name = "VWLAN"; gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; /* gpio 35 */ enable-active-high; }; leds { compatible = "gpio-leds"; heartbeat { label = "debug::sleep"; gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; /* gpio92 */ linux,default-trigger = "default-on"; pinctrl-names = "default"; pinctrl-0 = <&debug_leds>; }; }; /* controlled (enabled/disabled) directly by wl1271 */ vctcxo: vctcxo { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <38400000>; }; }; &omap3_pmx_core { accelerator_pins: pinmux_accelerator_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT | MUX_MODE4) /* mcspi2_somi.gpio_180 -> LIS302 INT1 */ OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT | MUX_MODE4) /* mcspi2_cs0.gpio_181 -> LIS302 INT2 */ >; }; debug_leds: pinmux_debug_led_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE4) /* dss_data22.gpio_92 */ >; }; mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */ OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ >; }; wlan_pins: pinmux_wlan_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE4) /* gpio 35 - wlan enable */ OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 - wlan irq */ >; }; ssi_pins: pinmux_ssi_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ >; }; ssi_pins_idle: pinmux_ssi_pins_idle { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */ OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */ OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7) /* ssi1_rdy_tx */ OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7) /* ssi1_dat_rx */ OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7) /* ssi1_flag_rx */ OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* ssi1_rdy_rx */ OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE7) /* ssi1_wake */ >; }; modem_pins1: pinmux_modem_core1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | MUX_MODE4) /* gpio_34 (ape_rst_rq) */ OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4) /* gpio_93 (cmt_apeslpx) */ >; }; uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */ OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ >; }; }; &omap3_pmx_core2 { modem_pins2: pinmux_modem_core2_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* gpio_23 (cmt_en) */ >; }; }; &i2c1 { clock-frequency = <2900000>; twl: twl@48 { reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; }; }; /include/ "twl4030.dtsi" &twl { compatible = "ti,twl5031"; twl_power: power { compatible = "ti,twl4030-power"; ti,use_poweroff; }; }; &twl_gpio { ti,pullups = <0x000001>; /* BIT(0) */ ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */ }; &vdac { regulator-name = "vdac"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; &vpll1 { regulator-name = "vpll1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; &vpll2 { regulator-name = "vpll2"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; &vaux1 { regulator-name = "vaux1"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; /* CSI-2 receiver */ &vaux2 { regulator-name = "vaux2"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; /* Cameras */ &vaux3 { regulator-name = "vaux3"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; &vaux4 { regulator-name = "vaux4"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; &vmmc1 { regulator-name = "vmmc1"; regulator-min-microvolt = <1850000>; regulator-max-microvolt = <3150000>; }; &vmmc2 { regulator-name = "vmmc2"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; }; &vintana1 { regulator-name = "vintana1"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; }; &vintana2 { regulator-name = "vintana2"; regulator-min-microvolt = <2750000>; regulator-max-microvolt = <2750000>; }; &vintdig { regulator-name = "vintdig"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; }; &vsim { regulator-name = "vsim"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; &vio { regulator-name = "vio"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; &i2c2 { clock-frequency = <400000>; as3645a@30 { #address-cells = <1>; #size-cells = <0>; reg = <0x30>; compatible = "ams,as3645a"; as3645a_flash: flash@0 { reg = <0x0>; flash-timeout-us = <150000>; flash-max-microamp = <320000>; led-max-microamp = <60000>; ams,input-max-microamp = <1750000>; }; as3645a_indicator: indicator@1 { reg = <0x1>; led-max-microamp = <10000>; }; }; }; &i2c3 { clock-frequency = <400000>; lis302: lis302@1d { compatible = "st,lis3lv02d"; reg = <0x1d>; Vdd-supply = <&vaux1>; Vdd_IO-supply = <&vio>; pinctrl-names = "default"; pinctrl-0 = <&accelerator_pins>; interrupts-extended = <&gpio6 20 IRQ_TYPE_EDGE_FALLING>, <&gpio6 21 IRQ_TYPE_EDGE_FALLING>; /* 180, 181 */ /* click flags */ st,click-single-x; st,click-single-y; st,click-single-z; /* Limits are 0.5g * value */ st,click-threshold-x = <8>; st,click-threshold-y = <8>; st,click-threshold-z = <10>; /* Click must be longer than time limit */ st,click-time-limit = <9>; /* Kind of debounce filter */ st,click-latency = <50>; st,wakeup-x-hi; st,wakeup-y-hi; st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */ st,wakeup2-z-hi; st,wakeup2-threshold = <(1000/18)>; /* millig-value / 18 to get HW values */ st,highpass-cutoff-hz = <2>; /* Interrupt line 1 for thresholds */ st,irq1-ff-wu-1; st,irq1-ff-wu-2; /* Interrupt line 2 for click detection */ st,irq2-click; st,wu-duration-1 = <8>; st,wu-duration-2 = <8>; }; }; &mmc1 { status = "disabled"; }; &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; vmmc-supply = <&vemmc>; bus-width = <4>; ti,non-removable; }; &mmc3 { status = "disabled"; }; &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; phys = <&usb2_phy>; phy-names = "usb2-phy"; mode = <3>; power = <50>; }; &gpmc { ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ onenand@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "ti,omap2-onenand"; reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ /* * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported * bootloader set values when booted with v4.19 using both N950 * and N9 devices (OneNAND Manufacturer: Samsung): * * gpmc cs0 before gpmc_cs_program_settings: * cs0 GPMC_CS_CONFIG1: 0xfd001202 * cs0 GPMC_CS_CONFIG2: 0x00181800 * cs0 GPMC_CS_CONFIG3: 0x00030300 * cs0 GPMC_CS_CONFIG4: 0x18001804 * cs0 GPMC_CS_CONFIG5: 0x03171d1d * cs0 GPMC_CS_CONFIG6: 0x97080000 */ gpmc,sync-read; gpmc,sync-write; gpmc,burst-length = <16>; gpmc,burst-read; gpmc,burst-wrap; gpmc,burst-write; gpmc,device-width = <2>; gpmc,mux-add-data = <2>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <122>; gpmc,cs-wr-off-ns = <122>; gpmc,adv-on-ns = <0>; gpmc,adv-rd-off-ns = <15>; gpmc,adv-wr-off-ns = <15>; gpmc,oe-on-ns = <20>; gpmc,oe-off-ns = <122>; gpmc,we-on-ns = <0>; gpmc,we-off-ns = <122>; gpmc,rd-cycle-ns = <148>; gpmc,wr-cycle-ns = <148>; gpmc,access-ns = <117>; gpmc,page-burst-access-ns = <15>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,wait-monitoring-ns = <0>; gpmc,clk-activation-ns = <10>; gpmc,wr-data-mux-bus-ns = <40>; gpmc,wr-access-ns = <117>; gpmc,sync-clk-ps = <15000>; /* TBC; Where this value came? */ /* * MTD partition table corresponding to Nokia's MeeGo 1.2 * Harmattan release. */ partition@0 { label = "bootloader"; reg = <0x00000000 0x00100000>; }; partition@1 { label = "config"; reg = <0x00100000 0x002c0000>; }; partition@2 { label = "kernel"; reg = <0x003c0000 0x01000000>; }; partition@3 { label = "log"; reg = <0x013c0000 0x00200000>; }; partition@4 { label = "var"; reg = <0x015c0000 0x1ca40000>; }; partition@5 { label = "moslo"; reg = <0x1e000000 0x02000000>; }; partition@6 { label = "omap2-onenand"; reg = <0x00000000 0x20000000>; }; }; }; &ssi_port1 { pinctrl-names = "default", "idle"; pinctrl-0 = <&ssi_pins>; pinctrl-1 = <&ssi_pins_idle>; ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ modem: hsi-client { pinctrl-names = "default"; pinctrl-0 = <&modem_pins1 &modem_pins2>; hsi-channel-ids = <0>, <1>, <2>, <3>; hsi-channel-names = "mcsaab-control", "speech-control", "speech-data", "mcsaab-data"; hsi-speed-kbps = <96000>; hsi-mode = "frame"; hsi-flow = "synchronized"; hsi-arb-mode = "round-robin"; interrupts-extended = <&gpio2 2 IRQ_TYPE_EDGE_RISING>; /* gpio 34 */ gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>, /* gpio 93 */ <&gpio3 24 GPIO_ACTIVE_HIGH>, /* gpio 88 */ <&gpio1 23 GPIO_ACTIVE_HIGH>; /* gpio 23 */ gpio-names = "cmt_apeslpx", "cmt_rst_rq", "cmt_en"; }; }; &ssi_port2 { status = "disabled"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; bluetooth { compatible = "ti,wl1271-bluetooth-nokia", "nokia,h4p-bluetooth"; reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; /* 26 */ host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */ bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */ clocks = <&vctcxo>; clock-names = "sysclk"; }; }; diff --git a/sys/gnu/dts/arm/omap3-n950.dts b/sys/gnu/dts/arm/omap3-n950.dts index 31d47a1fad84..9886bf8b90ab 100644 --- a/sys/gnu/dts/arm/omap3-n950.dts +++ b/sys/gnu/dts/arm/omap3-n950.dts @@ -1,273 +1,273 @@ // SPDX-License-Identifier: GPL-2.0-only /* * omap3-n950.dts - Device Tree file for Nokia N950 * * Written by: Aaro Koskinen */ /dts-v1/; #include "omap3-n950-n9.dtsi" #include / { model = "Nokia N950"; - compatible = "nokia,omap3-n950", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3"; keys { compatible = "gpio-keys"; keypad_slide { label = "Keypad Slide"; gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* 109 */ linux,input-type = ; linux,code = ; wakeup-source; pinctrl-names = "default"; pinctrl-0 = <&keypad_slide_pins>; }; }; }; &omap3_pmx_core { keypad_slide_pins: pinmux_debug_led_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ >; }; }; &omap3_pmx_core { spi4_pins: pinmux_spi4_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ >; }; }; &omap3_pmx_core { dsi_pins: pinmux_dsi_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE1) /* dsi_dx0 - data0+ */ OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE1) /* dsi_dy0 - data0- */ OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE1) /* dsi_dx1 - clk+ */ OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE1) /* dsi_dy1 - clk- */ OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE1) /* dsi_dx2 - data1+ */ OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE1) /* dsi_dy2 - data1- */ >; }; display_pins: pinmux_display_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20ca, PIN_INPUT | MUX_MODE4) /* gpio 62 - display te */ OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 - display reset */ >; }; }; &i2c2 { smia_1: camera@10 { compatible = "nokia,smia"; reg = <0x10>; /* No reset gpio */ vana-supply = <&vaux3>; clocks = <&isp 0>; clock-frequency = <9600000>; nokia,nvm-size = <(16 * 64)>; flash-leds = <&as3645a_flash &as3645a_indicator>; port { smia_1_1: endpoint { link-frequencies = /bits/ 64 <210000000 333600000 398400000>; clock-lanes = <0>; data-lanes = <1 2>; remote-endpoint = <&csi2a_ep>; }; }; }; }; &isp { vdd-csiphy1-supply = <&vaux2>; vdd-csiphy2-supply = <&vaux2>; ports { port@2 { reg = <2>; csi2a_ep: endpoint { remote-endpoint = <&smia_1_1>; clock-lanes = <2>; data-lanes = <3 1>; crc = <1>; lane-polarities = <1 1 1>; }; }; }; }; &mcspi4 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi4_pins>; wlcore: wlcore@0 { compatible = "ti,wl1271"; pinctrl-names = "default"; pinctrl-0 = <&wlan_pins>; reg = <0>; spi-max-frequency = <48000000>; clock-xtal; ref-clock-frequency = <38400000>; interrupts-extended = <&gpio2 10 IRQ_TYPE_LEVEL_HIGH>; /* gpio 42 */ vwlan-supply = <&vwlan_fixed>; }; }; &modem { compatible = "nokia,n950-modem"; }; &twl { twl_audio: audio { compatible = "ti,twl4030-audio"; ti,enable-vibra = <1>; }; }; &twl_keypad { linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_BACKSLASH) MATRIX_KEY(0x01, 0x00, KEY_LEFTSHIFT) MATRIX_KEY(0x02, 0x00, KEY_COMPOSE) MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA) MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) MATRIX_KEY(0x05, 0x00, KEY_BACKSPACE) MATRIX_KEY(0x06, 0x00, KEY_VOLUMEDOWN) MATRIX_KEY(0x07, 0x00, KEY_VOLUMEUP) MATRIX_KEY(0x03, 0x01, KEY_Z) MATRIX_KEY(0x04, 0x01, KEY_A) MATRIX_KEY(0x05, 0x01, KEY_Q) MATRIX_KEY(0x06, 0x01, KEY_W) MATRIX_KEY(0x07, 0x01, KEY_E) MATRIX_KEY(0x03, 0x02, KEY_X) MATRIX_KEY(0x04, 0x02, KEY_S) MATRIX_KEY(0x05, 0x02, KEY_D) MATRIX_KEY(0x06, 0x02, KEY_C) MATRIX_KEY(0x07, 0x02, KEY_V) MATRIX_KEY(0x03, 0x03, KEY_O) MATRIX_KEY(0x04, 0x03, KEY_I) MATRIX_KEY(0x05, 0x03, KEY_U) MATRIX_KEY(0x06, 0x03, KEY_L) MATRIX_KEY(0x07, 0x03, KEY_APOSTROPHE) MATRIX_KEY(0x03, 0x04, KEY_Y) MATRIX_KEY(0x04, 0x04, KEY_K) MATRIX_KEY(0x05, 0x04, KEY_J) MATRIX_KEY(0x06, 0x04, KEY_H) MATRIX_KEY(0x07, 0x04, KEY_G) MATRIX_KEY(0x03, 0x05, KEY_B) MATRIX_KEY(0x04, 0x05, KEY_COMMA) MATRIX_KEY(0x05, 0x05, KEY_M) MATRIX_KEY(0x06, 0x05, KEY_N) MATRIX_KEY(0x07, 0x05, KEY_DOT) MATRIX_KEY(0x00, 0x06, KEY_SPACE) MATRIX_KEY(0x03, 0x06, KEY_T) MATRIX_KEY(0x04, 0x06, KEY_UP) MATRIX_KEY(0x05, 0x06, KEY_LEFT) MATRIX_KEY(0x06, 0x06, KEY_RIGHT) MATRIX_KEY(0x07, 0x06, KEY_DOWN) MATRIX_KEY(0x03, 0x07, KEY_P) MATRIX_KEY(0x04, 0x07, KEY_ENTER) MATRIX_KEY(0x05, 0x07, KEY_SLASH) MATRIX_KEY(0x06, 0x07, KEY_F) MATRIX_KEY(0x07, 0x07, KEY_R) >; }; &lis302 { st,axis-x = <(-2)>; /* LIS3_INV_DEV_Y */ st,axis-y = <(-1)>; /* LIS3_INV_DEV_X */ st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ st,min-limit-x = <(-32)>; st,min-limit-y = <3>; st,min-limit-z = <3>; st,max-limit-x = <(-3)>; st,max-limit-y = <32>; st,max-limit-z = <32>; }; &dss { status = "ok"; vdda_video-supply = <&vdac>; }; &dsi { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&dsi_pins>; vdd-supply = <&vpll2>; port { dsi_out_ep: endpoint { remote-endpoint = <&lcd0_in>; lanes = <2 3 0 1 4 5>; }; }; lcd0: display { compatible = "nokia,himalaya", "panel-dsi-cm"; label = "lcd0"; pinctrl-names = "default"; pinctrl-0 = <&display_pins>; vpnl-supply = <&vmmc2>; vddi-supply = <&vio>; reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ te-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; /* 62 */ width-mm = <49>; /* 48.960 mm */ height-mm = <88>; /* 88.128 mm */ /* TODO: * - panel is upside-down * - top + bottom 5px are not visible */ panel-timing { clock-frequency = <0>; /* Calculated by dsi */ hback-porch = <2>; hactive = <480>; hfront-porch = <0>; hsync-len = <2>; vback-porch = <1>; vactive = <864>; vfront-porch = <0>; vsync-len = <1>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <1>; }; port { lcd0_in: endpoint { remote-endpoint = <&dsi_out_ep>; }; }; }; }; diff --git a/sys/gnu/dts/arm/omap3-overo-storm-alto35.dts b/sys/gnu/dts/arm/omap3-overo-storm-alto35.dts index 7f04dfad8203..18338576c41d 100644 --- a/sys/gnu/dts/arm/omap3-overo-storm-alto35.dts +++ b/sys/gnu/dts/arm/omap3-overo-storm-alto35.dts @@ -1,18 +1,18 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group */ /* * Alto35 expansion board is manufactured by Gumstix Inc. */ /dts-v1/; #include "omap3-overo-storm.dtsi" #include "omap3-overo-alto35-common.dtsi" / { model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Alto35"; - compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; }; diff --git a/sys/gnu/dts/arm/omap3-overo-storm-chestnut43.dts b/sys/gnu/dts/arm/omap3-overo-storm-chestnut43.dts index bc5a04e03336..f204c8af8281 100644 --- a/sys/gnu/dts/arm/omap3-overo-storm-chestnut43.dts +++ b/sys/gnu/dts/arm/omap3-overo-storm-chestnut43.dts @@ -1,35 +1,35 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group */ /* * Chestnut43 expansion board is manufactured by Gumstix Inc. */ /dts-v1/; #include "omap3-overo-storm.dtsi" #include "omap3-overo-chestnut43-common.dtsi" / { model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Chestnut43"; - compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; }; &omap3_pmx_core2 { led_pins: pinmux_led_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; button_pins: pinmux_button_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ >; }; }; diff --git a/sys/gnu/dts/arm/omap3-overo-storm-gallop43.dts b/sys/gnu/dts/arm/omap3-overo-storm-gallop43.dts index 065c31cbf0e2..c633f7cee68e 100644 --- a/sys/gnu/dts/arm/omap3-overo-storm-gallop43.dts +++ b/sys/gnu/dts/arm/omap3-overo-storm-gallop43.dts @@ -1,35 +1,35 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group */ /* * Gallop43 expansion board is manufactured by Gumstix Inc. */ /dts-v1/; #include "omap3-overo-storm.dtsi" #include "omap3-overo-gallop43-common.dtsi" / { model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Gallop43"; - compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; }; &omap3_pmx_core2 { led_pins: pinmux_led_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; button_pins: pinmux_button_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ >; }; }; diff --git a/sys/gnu/dts/arm/omap3-overo-storm-palo35.dts b/sys/gnu/dts/arm/omap3-overo-storm-palo35.dts index e38c1c51392c..fb88ebc9858c 100644 --- a/sys/gnu/dts/arm/omap3-overo-storm-palo35.dts +++ b/sys/gnu/dts/arm/omap3-overo-storm-palo35.dts @@ -1,34 +1,34 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 Ash Charles, Gumstix, Inc. */ /* * Palo35 expansion board is manufactured by Gumstix Inc. */ /dts-v1/; #include "omap3-overo-storm.dtsi" #include "omap3-overo-palo35-common.dtsi" / { model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo35"; - compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; }; &omap3_pmx_core2 { led_pins: pinmux_led_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; button_pins: pinmux_button_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ >; }; }; diff --git a/sys/gnu/dts/arm/omap3-overo-storm-palo43.dts b/sys/gnu/dts/arm/omap3-overo-storm-palo43.dts index e6dc23159c4d..76cca00d97b6 100644 --- a/sys/gnu/dts/arm/omap3-overo-storm-palo43.dts +++ b/sys/gnu/dts/arm/omap3-overo-storm-palo43.dts @@ -1,35 +1,35 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group */ /* * Palo43 expansion board is manufactured by Gumstix Inc. */ /dts-v1/; #include "omap3-overo-storm.dtsi" #include "omap3-overo-palo43-common.dtsi" / { model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo43"; - compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; }; &omap3_pmx_core2 { led_pins: pinmux_led_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; button_pins: pinmux_button_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ >; }; }; diff --git a/sys/gnu/dts/arm/omap3-overo-storm-summit.dts b/sys/gnu/dts/arm/omap3-overo-storm-summit.dts index 587c08ce282d..cc081a9e4c1e 100644 --- a/sys/gnu/dts/arm/omap3-overo-storm-summit.dts +++ b/sys/gnu/dts/arm/omap3-overo-storm-summit.dts @@ -1,27 +1,27 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group */ /* * Summit expansion board is manufactured by Gumstix Inc. */ /dts-v1/; #include "omap3-overo-storm.dtsi" #include "omap3-overo-summit-common.dtsi" / { model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Summit"; - compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; }; &omap3_pmx_core2 { led_pins: pinmux_led_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ >; }; }; diff --git a/sys/gnu/dts/arm/omap3-overo-storm-tobi.dts b/sys/gnu/dts/arm/omap3-overo-storm-tobi.dts index f57de6010994..1de41c0826e0 100644 --- a/sys/gnu/dts/arm/omap3-overo-storm-tobi.dts +++ b/sys/gnu/dts/arm/omap3-overo-storm-tobi.dts @@ -1,19 +1,19 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group */ /* * Tobi expansion board is manufactured by Gumstix Inc. */ /dts-v1/; #include "omap3-overo-storm.dtsi" #include "omap3-overo-tobi-common.dtsi" / { model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Tobi"; - compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; }; diff --git a/sys/gnu/dts/arm/omap3-overo-storm-tobiduo.dts b/sys/gnu/dts/arm/omap3-overo-storm-tobiduo.dts index 281af6c113be..9ed13118ed8e 100644 --- a/sys/gnu/dts/arm/omap3-overo-storm-tobiduo.dts +++ b/sys/gnu/dts/arm/omap3-overo-storm-tobiduo.dts @@ -1,18 +1,18 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 Ash Charles, Gumstix, Inc. */ /* * TobiDuo expansion board is manufactured by Gumstix Inc. */ /dts-v1/; #include "omap3-overo-storm.dtsi" #include "omap3-overo-tobiduo-common.dtsi" / { model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on TobiDuo"; - compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; }; diff --git a/sys/gnu/dts/arm/omap3-pandora-1ghz.dts b/sys/gnu/dts/arm/omap3-pandora-1ghz.dts index ea509956d7ac..81b957f33c9f 100644 --- a/sys/gnu/dts/arm/omap3-pandora-1ghz.dts +++ b/sys/gnu/dts/arm/omap3-pandora-1ghz.dts @@ -1,67 +1,67 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 * Nikolaus Schaller */ /* * device tree for OpenPandora 1GHz with DM3730 */ /dts-v1/; #include "omap36xx.dtsi" #include "omap3-pandora-common.dtsi" / { model = "Pandora Handheld Console 1GHz"; - compatible = "openpandora,omap3-pandora-1ghz", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "openpandora,omap3-pandora-1ghz", "ti,omap36xx", "ti,omap3"; }; &omap3_pmx_core2 { pinctrl-names = "default"; pinctrl-0 = < &hsusb2_2_pins &control_pins >; hsusb2_2_pins: pinmux_hsusb2_2_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ >; }; mmc3_pins: pinmux_mmc3_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ >; }; control_pins: pinmux_control_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ OMAP3630_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 = RESET_USB_HOST */ OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4) /* etk_d7.gpio_21 = WIFI IRQ */ OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 = MSECURE */ OMAP3630_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4) /* etk_d9.gpio_23 = WIFI_POWER */ OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT | MUX_MODE4) /* reserved.gpio_127 = MMC2_WP */ OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 = MMC1_WP */ OMAP3_WKUP_IOPAD(0x2a58, PIN_OUTPUT | MUX_MODE4) /* reserved.gpio_128 = LED_MMC1 */ OMAP3_WKUP_IOPAD(0x2a5a, PIN_OUTPUT | MUX_MODE4) /* reserved.gpio_129 = LED_MMC2 */ >; }; }; diff --git a/sys/gnu/dts/arm/omap3-pandora-common.dtsi b/sys/gnu/dts/arm/omap3-pandora-common.dtsi index 150d5be42d27..ec5891718ae6 100644 --- a/sys/gnu/dts/arm/omap3-pandora-common.dtsi +++ b/sys/gnu/dts/arm/omap3-pandora-common.dtsi @@ -1,730 +1,698 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 * Nikolaus Schaller * * Common device tree include for OpenPandora devices. */ #include / { cpus { cpu@0 { cpu0-supply = <&vcc>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; aliases { display0 = &lcd; }; /* fixed 26MHz oscillator */ hfclk_26m: oscillator { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <26000000>; }; tv: connector { compatible = "connector-analog-tv"; label = "tv"; port { tv_connector_in: endpoint { remote-endpoint = <&venc_out>; }; }; }; gpio-leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&led_pins>; led1 { label = "pandora::sd1"; gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* GPIO_128 */ linux,default-trigger = "mmc0"; default-state = "off"; }; led2 { label = "pandora::sd2"; gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* GPIO_129 */ linux,default-trigger = "mmc1"; default-state = "off"; }; led3 { label = "pandora::bluetooth"; gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; /* GPIO_158 */ linux,default-trigger = "heartbeat"; default-state = "off"; }; led4 { label = "pandora::wifi"; gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; /* GPIO_159 */ linux,default-trigger = "mmc2"; default-state = "off"; }; }; gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&button_pins>; up-button { label = "up"; linux,code = ; gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* GPIO_110 */ wakeup-source; }; down-button { label = "down"; linux,code = ; gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* GPIO_103 */ wakeup-source; }; left-button { label = "left"; linux,code = ; gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; /* GPIO_96 */ wakeup-source; }; right-button { label = "right"; linux,code = ; gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; /* GPIO_98 */ wakeup-source; }; pageup-button { label = "game 1"; linux,code = ; gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* GPIO_109 */ wakeup-source; }; pagedown-button { label = "game 3"; linux,code = ; gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* GPIO_106 */ wakeup-source; }; home-button { label = "game 4"; linux,code = ; gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* GPIO_101 */ wakeup-source; }; end-button { label = "game 2"; linux,code = ; gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* GPIO_111 */ wakeup-source; }; right-shift { label = "l"; linux,code = ; gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* GPIO_102 */ wakeup-source; }; kp-plus { label = "l2"; linux,code = ; gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; /* GPIO_97 */ wakeup-source; }; right-ctrl { label = "r"; linux,code = ; gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* GPIO_105 */ wakeup-source; }; kp-minus { label = "r2"; linux,code = ; gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* GPIO_107 */ wakeup-source; }; left-ctrl { label = "ctrl"; linux,code = ; gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* GPIO_104 */ wakeup-source; }; menu { label = "menu"; linux,code = ; gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; /* GPIO_99 */ wakeup-source; }; hold { label = "hold"; linux,code = ; gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* GPIO_176 */ wakeup-source; }; left-alt { label = "alt"; linux,code = ; gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; /* GPIO_100 */ wakeup-source; }; lid { label = "lid"; linux,code = <0x00>; /* SW_LID lid shut */ linux,input-type = <0x05>; /* EV_SW */ gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; /* GPIO_108 */ }; }; /* HS USB Host PHY on PORT 2 */ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* GPIO_16 */ vcc-supply = <&vaux2>; #phy-cells = <0>; }; /* HS USB Host VBUS supply * disabling this regulator causes current leakage, and LCD flicker * on earlier (CC) board revisions, so keep it always on */ usb_host_5v: fixed-regulator-usb_host_5v { compatible = "regulator-fixed"; regulator-name = "usb_host_5v"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; regulator-boot-on; enable-active-high; gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* GPIO_164 */ }; - /* wl1251 wifi+bt module */ - wlan_en: fixed-regulator-wg7210_en { - compatible = "regulator-fixed"; - regulator-name = "vwlan"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <50000>; - enable-active-high; - gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; - }; - /* wg7210 (wifi+bt module) 32k clock buffer */ wg7210_32k: fixed-regulator-wg7210_32k { compatible = "regulator-fixed"; regulator-name = "wg7210_32k"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; enable-active-high; gpio = <&twl_gpio 13 GPIO_ACTIVE_HIGH>; }; }; &omap3_pmx_core { mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ >; }; mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dirdat0 */ OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dirdat1 */ OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dircmd */ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ >; }; dss_dpi_pins: pinmux_dss_dpi_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* GPIO_157 = lcd reset */ >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; led_pins: pinmux_leds_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2154, PIN_OUTPUT | MUX_MODE4) /* GPIO_128 */ OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* GPIO_129 */ OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE4) /* GPIO_158 */ OMAP3_CORE1_IOPAD(0x2192, PIN_OUTPUT | MUX_MODE4) /* GPIO_159 */ >; }; button_pins: pinmux_button_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE4) /* GPIO_96 */ OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE4) /* GPIO_97 */ OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* GPIO_98 */ OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE4) /* GPIO_99 */ OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE4) /* GPIO_100 */ OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* GPIO_101 */ OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4) /* GPIO_102 */ OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE4) /* GPIO_103 */ OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE4) /* GPIO_104 */ OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE4) /* GPIO_105 */ OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE4) /* GPIO_106 */ OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE4) /* GPIO_107 */ OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE4) /* GPIO_108 */ OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* GPIO_109 */ OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT | MUX_MODE4) /* GPIO_110 */ OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* GPIO_111 */ OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* GPIO_176 */ >; }; penirq_pins: pinmux_penirq_pins { pinctrl-single,pins = < /* here we could enable to wakeup the cpu from suspend by a pen touch */ OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE4) /* GPIO_94 */ >; }; }; &omap3_pmx_core2 { /* define in CPU specific file that includes this one * use either OMAP3430_CORE2_IOPAD() or OMAP3630_CORE2_IOPAD() */ }; &i2c1 { clock-frequency = <2600000>; twl: twl@48 { reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; clocks = <&hfclk_26m>; clock-names = "fck"; twl_power: power { compatible = "ti,twl4030-power-reset"; ti,use_poweroff; }; twl_audio: audio { compatible = "ti,twl4030-audio"; codec { ti,ramp_delay_value = <3>; }; }; }; }; #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" &twl_keypad { keypad,num-rows = <8>; keypad,num-columns = <6>; linux,keymap = < MATRIX_KEY(0, 0, KEY_9) MATRIX_KEY(0, 1, KEY_8) MATRIX_KEY(0, 2, KEY_I) MATRIX_KEY(0, 3, KEY_J) MATRIX_KEY(0, 4, KEY_N) MATRIX_KEY(0, 5, KEY_M) MATRIX_KEY(1, 0, KEY_0) MATRIX_KEY(1, 1, KEY_7) MATRIX_KEY(1, 2, KEY_U) MATRIX_KEY(1, 3, KEY_H) MATRIX_KEY(1, 4, KEY_B) MATRIX_KEY(1, 5, KEY_SPACE) MATRIX_KEY(2, 0, KEY_BACKSPACE) MATRIX_KEY(2, 1, KEY_6) MATRIX_KEY(2, 2, KEY_Y) MATRIX_KEY(2, 3, KEY_G) MATRIX_KEY(2, 4, KEY_V) MATRIX_KEY(2, 5, KEY_FN) MATRIX_KEY(3, 0, KEY_O) MATRIX_KEY(3, 1, KEY_5) MATRIX_KEY(3, 2, KEY_T) MATRIX_KEY(3, 3, KEY_F) MATRIX_KEY(3, 4, KEY_C) MATRIX_KEY(4, 0, KEY_P) MATRIX_KEY(4, 1, KEY_4) MATRIX_KEY(4, 2, KEY_R) MATRIX_KEY(4, 3, KEY_D) MATRIX_KEY(4, 4, KEY_X) MATRIX_KEY(5, 0, KEY_K) MATRIX_KEY(5, 1, KEY_3) MATRIX_KEY(5, 2, KEY_E) MATRIX_KEY(5, 3, KEY_S) MATRIX_KEY(5, 4, KEY_Z) MATRIX_KEY(6, 0, KEY_L) MATRIX_KEY(6, 1, KEY_2) MATRIX_KEY(6, 2, KEY_W) MATRIX_KEY(6, 3, KEY_A) MATRIX_KEY(6, 4, KEY_RIGHTBRACE) MATRIX_KEY(7, 0, KEY_ENTER) MATRIX_KEY(7, 1, KEY_1) MATRIX_KEY(7, 2, KEY_Q) MATRIX_KEY(7, 3, KEY_LEFTSHIFT) MATRIX_KEY(7, 4, KEY_LEFTBRACE ) >; }; /* backup battery charger */ &charger { ti,bb-uvolt = <3200000>; ti,bb-uamp = <150>; }; /* MMC2 */ &vmmc2 { regulator-min-microvolt = <1850000>; regulator-max-microvolt = <3150000>; }; /* LCD */ &vaux1 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; }; /* USB Host PHY */ &vaux2 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; /* available on expansion connector */ &vaux3 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; /* ADS7846 and nubs */ &vaux4 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; /* power audio DAC and LID sensor */ &vsim { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; }; &i2c2 { clock-frequency = <100000>; /* no clients so we should disable clock */ }; &i2c3 { clock-frequency = <100000>; bq27500@55 { compatible = "ti,bq27500"; reg = <0x55>; }; }; &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; phys = <&usb2_phy>; phy-names = "usb2-phy"; mode = <3>; power = <50>; }; /* * Many pandora boards have been produced with defective write-protect switches * on either slot, so it was decided not to use this feature. If you know * your board has good switches, feel free to uncomment wp-gpios below. */ &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; vmmc-supply = <&vmmc1>; bus-width = <4>; cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; /*wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;*/ /* GPIO_126 */ }; &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; vmmc-supply = <&vmmc2>; bus-width = <4>; cd-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>; /*wp-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;*/ /* GPIO_127 */ }; +/* mmc3 is probed using pdata-quirks to pass wl1251 card data */ &mmc3 { - vmmc-supply = <&wlan_en>; - - bus-width = <4>; - non-removable; - ti,non-removable; - cap-power-off-card; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - - #address-cells = <1>; - #size-cells = <0>; - - wlan: wifi@1 { - compatible = "ti,wl1251"; - - reg = <1>; - - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_21 */ - - ti,wl1251-has-eeprom; - }; + status = "disabled"; }; /* bluetooth*/ &uart1 { }; /* spare (expansion connector) */ &uart2 { }; /* console (expansion connector) */ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; }; &usbhshost { port2-mode = "ehci-phy"; }; &usbhsehci { phys = <0 &hsusb2_phy>; }; &gpmc { ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ nand-bus-width = <16>; ti,nand-ecc-opt = "sw"; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <44>; gpmc,cs-wr-off-ns = <44>; gpmc,adv-on-ns = <6>; gpmc,adv-rd-off-ns = <34>; gpmc,adv-wr-off-ns = <44>; gpmc,we-off-ns = <40>; gpmc,oe-off-ns = <54>; gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; gpmc,device-width = <2>; #address-cells = <1>; #size-cells = <1>; /* u-boot uses mtdparts=nand:512k(xloader),1920k(uboot),128k(uboot-env),10m(boot),-(rootfs) */ x-loader@0 { label = "xloader"; reg = <0 0x80000>; }; bootloaders@80000 { label = "uboot"; reg = <0x80000 0x1e0000>; }; bootloaders_env@260000 { label = "uboot-env"; reg = <0x260000 0x20000>; }; kernel@280000 { label = "boot"; reg = <0x280000 0xa00000>; }; filesystem@c80000 { label = "rootfs"; reg = <0xc80000 0>; /* 0 = MTDPART_SIZ_FULL */ }; }; }; &mcspi1 { tsc2046@0 { reg = <0>; /* CS0 */ compatible = "ti,tsc2046"; spi-max-frequency = <1000000>; pinctrl-names = "default"; pinctrl-0 = <&penirq_pins>; interrupt-parent = <&gpio3>; interrupts = <30 IRQ_TYPE_NONE>; /* GPIO_94 */ pendown-gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; vcc-supply = <&vaux4>; ti,x-min = /bits/ 16 <0>; ti,x-max = /bits/ 16 <8000>; ti,y-min = /bits/ 16 <0>; ti,y-max = /bits/ 16 <4800>; ti,x-plate-ohms = /bits/ 16 <40>; ti,pressure-max = /bits/ 16 <255>; wakeup-source; }; lcd: lcd@1 { reg = <1>; /* CS1 */ compatible = "tpo,td043mtea1"; spi-max-frequency = <100000>; spi-cpol; spi-cpha; label = "lcd"; reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; /* GPIO_157 */ vcc-supply = <&vaux1>; port { lcd_in: endpoint { remote-endpoint = <&dpi_out>; }; }; }; }; /* n/a - used as GPIOs */ &mcbsp1 { }; /* audio DAC */ &mcbsp2 { }; /* bluetooth */ &mcbsp3 { }; /* to twl4030*/ &mcbsp4 { }; &venc { status = "ok"; vdda-supply = <&vdac>; port { venc_out: endpoint { remote-endpoint = <&tv_connector_in>; ti,channels = <2>; }; }; }; &dss { pinctrl-names = "default"; pinctrl-0 = < &dss_dpi_pins >; status = "ok"; vdds_dsi-supply = <&vpll2>; port { dpi_out: endpoint { remote-endpoint = <&lcd_in>; data-lines = <24>; }; }; }; diff --git a/sys/gnu/dts/arm/omap3-sbc-t3530.dts b/sys/gnu/dts/arm/omap3-sbc-t3530.dts index 24bf3fd86641..ae96002abb3b 100644 --- a/sys/gnu/dts/arm/omap3-sbc-t3530.dts +++ b/sys/gnu/dts/arm/omap3-sbc-t3530.dts @@ -1,48 +1,48 @@ // SPDX-License-Identifier: GPL-2.0 /* * Suppport for CompuLab SBC-T3530 with CM-T3530 */ #include "omap3-cm-t3530.dts" #include "omap3-sb-t35.dtsi" / { model = "CompuLab SBC-T3530 with CM-T3530"; - compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; + compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3"; aliases { display0 = &dvi0; display1 = &tv0; }; }; &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = <&sb_t35_usb_hub_pins>; sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ >; }; }; &gpmc { ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ }; &mmc1 { cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>; }; &dss { port { dpi_out: endpoint { remote-endpoint = <&tfp410_in>; data-lines = <24>; }; }; }; diff --git a/sys/gnu/dts/arm/omap3-sbc-t3730.dts b/sys/gnu/dts/arm/omap3-sbc-t3730.dts index eb3893b9535e..7de6df16fc17 100644 --- a/sys/gnu/dts/arm/omap3-sbc-t3730.dts +++ b/sys/gnu/dts/arm/omap3-sbc-t3730.dts @@ -1,44 +1,44 @@ // SPDX-License-Identifier: GPL-2.0 /* * Suppport for CompuLab SBC-T3730 with CM-T3730 */ #include "omap3-cm-t3730.dts" #include "omap3-sb-t35.dtsi" / { model = "CompuLab SBC-T3730 with CM-T3730"; - compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3"; aliases { display0 = &dvi0; display1 = &tv0; }; }; &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = <&sb_t35_usb_hub_pins>; sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ >; }; }; &gpmc { ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ }; &dss { port { dpi_out: endpoint { remote-endpoint = <&tfp410_in>; data-lines = <24>; }; }; }; diff --git a/sys/gnu/dts/arm/omap3-sniper.dts b/sys/gnu/dts/arm/omap3-sniper.dts index b6879cdc5c13..40a87330e8c3 100644 --- a/sys/gnu/dts/arm/omap3-sniper.dts +++ b/sys/gnu/dts/arm/omap3-sniper.dts @@ -1,251 +1,251 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015-2016 Paul Kocialkowski */ /dts-v1/; #include "omap36xx.dtsi" #include / { model = "LG Optimus Black"; - compatible = "lg,omap3-sniper", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "lg,omap3-sniper", "ti,omap36xx", "ti,omap3"; cpus { cpu@0 { cpu0-supply = <&vcc>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; }; &omap3_pmx_core { pinctrl-names = "default"; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ >; }; dp3t_sel_pins: pinmux_dp3t_sel_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE4) /* gpio_161 */ OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* gpio_162 */ >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ >; }; i2c3_pins: pinmux_i2c3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ >; }; lp8720_en_pin: pinmux_lp8720_en_pin { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2080, PIN_OUTPUT | MUX_MODE4) /* gpio_37 */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT | MUX_MODE0) /* sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd */ OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0 */ OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1 */ OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2 */ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3 */ >; }; mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT | MUX_MODE0) /* sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT | MUX_MODE0) /* sdmmc2_cmd */ OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0 */ OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1 */ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2 */ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3 */ OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4 */ OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5 */ OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6 */ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7 */ >; }; usb_otg_hs_pins: pinmux_usb_otg_hs_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp */ OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir */ OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt */ OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0 */ OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1 */ OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2 */ OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3 */ OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4 */ OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5 */ OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6 */ OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7 */ >; }; }; &omap3_pmx_wkup { pinctrl-names = "default"; mmc1_cd_pin: pinmux_mmc1_cd_pin { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | MUX_MODE4) /* gpio_10 */ >; }; }; &gpio2 { ti,no-reset-on-init; }; &gpio5 { ti,no-reset-on-init; }; &gpio6 { ti,no-reset-on-init; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins &dp3t_sel_pins>; interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; }; &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; clock-frequency = <2600000>; twl: twl@48 { reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; power { compatible = "ti,twl4030-power"; ti,use_poweroff; }; }; }; &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; clock-frequency = <400000>; }; &i2c3 { pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; clock-frequency = <400000>; lp8720@7d { pinctrl-names = "default"; pinctrl-0 = <&lp8720_en_pin>; compatible = "ti,lp8720"; reg = <0x7d>; enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* gpio_37 */ lp8720_ldo1: ldo1 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; }; }; }; &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins &mmc1_cd_pin>; vmmc-supply = <&lp8720_ldo1>; cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* gpio 10 */ bus-width = <4>; }; &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; vmmc-supply = <&vmmc2>; ti,non-removable; bus-width = <8>; }; &mmc3 { status = "disabled"; }; &usb_otg_hs { pinctrl-names = "default"; pinctrl-0 = <&usb_otg_hs_pins>; interface-type = <0>; usb-phy = <&usb2_phy>; phys = <&usb2_phy>; phy-names = "usb2-phy"; mode = <3>; power = <50>; }; #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" &twl_keypad { linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_VOLUMEUP) MATRIX_KEY(0x01, 0x00, KEY_VOLUMEDOWN) MATRIX_KEY(0x02, 0x00, KEY_SELECT) >; }; /* * The TWL4030 VAUX2 and VDAC regulators power sensors that are slaves on I2C3. * When not powered, these sensors cause the I2C3 clock to stay low at all times, * making it impossible to reach other devices on I2C3. */ &vaux2 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; }; &vdac { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; diff --git a/sys/gnu/dts/arm/omap3-tao3530.dtsi b/sys/gnu/dts/arm/omap3-tao3530.dtsi index f24e2326cfa7..a7a04d78deeb 100644 --- a/sys/gnu/dts/arm/omap3-tao3530.dtsi +++ b/sys/gnu/dts/arm/omap3-tao3530.dtsi @@ -1,346 +1,346 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * Copyright (C) 2014 Stefan Roese */ /dts-v1/; #include "omap34xx.dtsi" /* Secure omaps have some devices inaccessible depending on the firmware */ &aes { status = "disabled"; }; &sham { status = "disabled"; }; / { cpus { cpu@0 { cpu0-supply = <&vcc>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; /* HS USB Port 2 Power */ hsusb2_power: hsusb2_power_reg { compatible = "regulator-fixed"; regulator-name = "hsusb2_vbus"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ startup-delay-us = <70000>; }; /* HS USB Host PHY on PORT 2 */ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */ vcc-supply = <&hsusb2_power>; #phy-cells = <0>; }; sound { compatible = "ti,omap-twl4030"; ti,model = "omap3beagle"; /* McBSP2 is used for onboard sound, same as on beagle */ ti,mcbsp = <&mcbsp2>; }; /* Regulator to enable/switch the vcc of the Wifi module */ mmc2_sdio_poweron: regulator-mmc2-sdio-poweron { compatible = "regulator-fixed"; regulator-name = "regulator-mmc2-sdio-poweron"; regulator-min-microvolt = <3150000>; regulator-max-microvolt = <3150000>; gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; /* gpio_157 */ startup-delay-us = <10000>; }; }; &omap3_pmx_core { hsusbb2_pins: pinmux_hsusbb2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3_CORE1_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ OMAP3_CORE1_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ OMAP3_CORE1_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ OMAP3_CORE1_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ OMAP3_CORE1_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ >; }; mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ >; }; /* wlan GPIO output for WLAN_EN */ wlan_gpio: pinmux_wlan_gpio { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr gpio_157 */ >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; i2c3_pins: pinmux_i2c3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl.i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.i2c3_sda */ >; }; mcspi1_pins: pinmux_mcspi1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ >; }; mcspi3_pins: pinmux_mcspi3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x25dc, PIN_OUTPUT | MUX_MODE1) /* etk_d0.mcspi3_simo gpio14 INPUT | MODE1 */ OMAP3_CORE1_IOPAD(0x25de, PIN_INPUT_PULLUP | MUX_MODE1) /* etk_d1.mcspi3_somi gpio15 INPUT | MODE1 */ OMAP3_CORE1_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE1) /* etk_d2.mcspi3_cs0 gpio16 INPUT | MODE1 */ OMAP3_CORE1_IOPAD(0x25e2, PIN_INPUT | MUX_MODE1) /* etk_d3.mcspi3_clk gpio17 INPUT | MODE1 */ >; }; mcbsp3_pins: pinmux_mcbsp3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.uart2_cts */ OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dr.uart2_rts */ OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clk.uart2_tx */ OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_fsx.uart2_rx */ >; }; }; /* McBSP1: mux'ed with GPIO158 as clock for HA-DSP */ &mcbsp1 { status = "disabled"; }; &mcbsp2 { status = "okay"; }; &i2c1 { clock-frequency = <2600000>; twl: twl@48 { reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; twl_audio: audio { compatible = "ti,twl4030-audio"; codec { }; }; }; }; &i2c3 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; }; &mcspi1 { pinctrl-names = "default"; pinctrl-0 = <&mcspi1_pins>; spidev@0 { compatible = "spidev"; spi-max-frequency = <48000000>; reg = <0>; spi-cpha; }; }; &mcspi3 { pinctrl-names = "default"; pinctrl-0 = <&mcspi3_pins>; spidev@0 { compatible = "spidev"; spi-max-frequency = <48000000>; reg = <0>; spi-cpha; }; }; #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; vmmc-supply = <&vmmc1>; vqmmc-supply = <&vsim>; - cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; + cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>; bus-width = <8>; }; // WiFi (Marvell 88W8686) on MMC2/SDIO &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; vmmc-supply = <&mmc2_sdio_poweron>; non-removable; bus-width = <4>; cap-power-off-card; }; &mmc3 { status = "disabled"; }; &usbhshost { port2-mode = "ehci-phy"; }; &usbhsehci { phys = <0 &hsusb2_phy>; }; &twl_gpio { ti,use-leds; /* pullups: BIT(1) */ ti,pullups = <0x000002>; /* * pulldowns: * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) * BIT(15), BIT(16), BIT(17) */ ti,pulldowns = <0x03a1c4>; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; &mcbsp3 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcbsp3_pins>; }; &gpmc { ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ nand-bus-width = <16>; gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ ti,nand-ecc-opt = "sw"; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <36>; gpmc,cs-wr-off-ns = <36>; gpmc,adv-on-ns = <6>; gpmc,adv-rd-off-ns = <24>; gpmc,adv-wr-off-ns = <36>; gpmc,oe-on-ns = <6>; gpmc,oe-off-ns = <48>; gpmc,we-on-ns = <6>; gpmc,we-off-ns = <30>; gpmc,rd-cycle-ns = <72>; gpmc,wr-cycle-ns = <72>; gpmc,access-ns = <54>; gpmc,wr-access-ns = <30>; #address-cells = <1>; #size-cells = <1>; x-loader@0 { label = "X-Loader"; reg = <0 0x80000>; }; bootloaders@80000 { label = "U-Boot"; reg = <0x80000 0x1e0000>; }; bootloaders_env@260000 { label = "U-Boot Env"; reg = <0x260000 0x20000>; }; kernel@280000 { label = "Kernel"; reg = <0x280000 0x400000>; }; filesystem@680000 { label = "File System"; reg = <0x680000 0xf980000>; }; }; }; &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; phys = <&usb2_phy>; phy-names = "usb2-phy"; mode = <3>; power = <50>; }; &vaux2 { regulator-name = "vdd_ehci"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; diff --git a/sys/gnu/dts/arm/omap3-thunder.dts b/sys/gnu/dts/arm/omap3-thunder.dts index 64221e3b3477..6276e7079b36 100644 --- a/sys/gnu/dts/arm/omap3-thunder.dts +++ b/sys/gnu/dts/arm/omap3-thunder.dts @@ -1,126 +1,126 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * Copyright (C) 2014 Stefan Roese */ #include "omap3-tao3530.dtsi" / { model = "TI OMAP3 Thunder baseboard with TAO3530 SOM"; - compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; + compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3"; }; &omap3_pmx_core { dss_dpi_pins: pinmux_dss_dpi_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ >; }; lte430_pins: pinmux_lte430_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ >; }; backlight_pins: pinmux_backlight_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ >; }; }; /* Needed to power the DPI pins */ &vpll2 { regulator-always-on; }; &dss { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; port { dpi_out: endpoint { remote-endpoint = <&lcd_in>; data-lines = <24>; }; }; }; / { aliases { display0 = &lcd0; }; lcd0: display { compatible = "samsung,lte430wq-f0c", "panel-dpi"; label = "lcd"; pinctrl-names = "default"; pinctrl-0 = <<e430_pins>; enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */ port { lcd_in: endpoint { remote-endpoint = <&dpi_out>; }; }; panel-timing { clock-frequency = <9000000>; hactive = <480>; vactive = <272>; hfront-porch = <3>; hback-porch = <2>; hsync-len = <42>; vback-porch = <2>; vfront-porch = <3>; vsync-len = <11>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <1>; }; }; backlight { compatible = "gpio-backlight"; pinctrl-names = "default"; pinctrl-0 = <&backlight_pins>; gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */ default-on; }; }; diff --git a/sys/gnu/dts/arm/omap3-zoom3.dts b/sys/gnu/dts/arm/omap3-zoom3.dts index d240e39f2151..db3a2fe84e99 100644 --- a/sys/gnu/dts/arm/omap3-zoom3.dts +++ b/sys/gnu/dts/arm/omap3-zoom3.dts @@ -1,231 +1,231 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; #include "omap36xx.dtsi" #include "omap-zoom-common.dtsi" / { model = "TI Zoom3"; - compatible = "ti,omap3-zoom3", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "ti,omap3-zoom3", "ti,omap36xx", "ti,omap3"; cpus { cpu@0 { cpu0-supply = <&vcc>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; vddvario: regulator-vddvario { compatible = "regulator-fixed"; regulator-name = "vddvario"; regulator-always-on; }; vdd33a: regulator-vdd33a { compatible = "regulator-fixed"; regulator-name = "vdd33a"; regulator-always-on; }; wl12xx_vmmc: wl12xx_vmmc { pinctrl-names = "default"; pinctrl-0 = <&wl12xx_gpio>; compatible = "regulator-fixed"; regulator-name = "vwl1271"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ startup-delay-us = <70000>; enable-active-high; }; }; &omap3_pmx_core { /* REVISIT: twl gpio0 is mmc0_cd */ mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ >; }; mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */ OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */ OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */ >; }; mmc3_pins: pinmux_mmc3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */ OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ OMAP3_CORE1_IOPAD(0x2182, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ >; }; uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; /* wl12xx GPIO output for WLAN_EN */ wl12xx_gpio: pinmux_wl12xx_gpio { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x211a, PIN_OUTPUT| MUX_MODE4) /* cam_d2.gpio_101 */ >; }; }; &omap3_pmx_core2 { mmc3_2_pins: pinmux_mmc3_2_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ >; }; }; &omap3_pmx_wkup { wlan_host_wkup: pinmux_wlan_host_wkup_pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_clkout1.gpio_10 WLAN_HOST_WKUP */ >; }; }; &i2c1 { clock-frequency = <2600000>; twl: twl@48 { reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; }; }; #include "twl4030.dtsi" &i2c2 { clock-frequency = <400000>; }; &i2c3 { clock-frequency = <400000>; /* * TVP5146 Video decoder-in for analog input support. */ tvp5146@5c { compatible = "ti,tvp5146m2"; reg = <0x5c>; }; }; &twl_gpio { ti,use-leds; }; &mmc1 { vmmc-supply = <&vmmc1>; vqmmc-supply = <&vsim>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; }; /* &mmc2 { vmmc-supply = <&vmmc2>; ti,non-removable; bus-width = <8>; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; }; */ &mmc3 { vmmc-supply = <&wl12xx_vmmc>; non-removable; bus-width = <4>; cap-power-off-card; pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins &mmc3_2_pins>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio6>; interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 162 */ ref-clock-frequency = <26000000>; }; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; &uart4 { status = "disabled"; }; &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; mode = <3>; power = <50>; }; diff --git a/sys/gnu/dts/arm/omap3.dtsi b/sys/gnu/dts/arm/omap3.dtsi index 634ea16a711e..4043ecb38016 100644 --- a/sys/gnu/dts/arm/omap3.dtsi +++ b/sys/gnu/dts/arm/omap3.dtsi @@ -1,889 +1,840 @@ /* * Device Tree Source for OMAP3 SoC * * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ -#include #include #include #include / { compatible = "ti,omap3430", "ti,omap3"; interrupt-parent = <&intc>; #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a8"; device_type = "cpu"; reg = <0x0>; clocks = <&dpll1_ck>; clock-names = "cpu"; clock-latency = <300000>; /* From omap-cpufreq driver */ }; }; pmu@54000000 { compatible = "arm,cortex-a8-pmu"; reg = <0x54000000 0x800000>; interrupts = <3>; ti,hwmods = "debugss"; }; /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself. */ soc { compatible = "ti,omap-infra"; mpu { compatible = "ti,omap3-mpu"; ti,hwmods = "mpu"; }; iva: iva { compatible = "ti,iva2.2"; ti,hwmods = "iva"; dsp { compatible = "ti,omap3-c64"; }; }; }; /* * XXX: Use a flat representation of the OMAP3 interconnect. * The real OMAP interconnect network is quite complex. * Since it will not bring real advantage to represent that in DT for * the moment, just use a fake OCP bus entry to represent the whole bus * hierarchy. */ ocp@68000000 { compatible = "ti,omap3-l3-smx", "simple-bus"; reg = <0x68000000 0x10000>; interrupts = <9 10>; #address-cells = <1>; #size-cells = <1>; ranges; ti,hwmods = "l3_main"; l4_core: l4@48000000 { compatible = "ti,omap3-l4-core", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x48000000 0x1000000>; scm: scm@2000 { compatible = "ti,omap3-scm", "simple-bus"; reg = <0x2000 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x2000 0x2000>; omap3_pmx_core: pinmux@30 { compatible = "ti,omap3-padconf", "pinctrl-single"; reg = <0x30 0x238>; #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xff1f>; }; scm_conf: scm_conf@270 { compatible = "syscon", "simple-bus"; reg = <0x270 0x330>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x270 0x330>; pbias_regulator: pbias_regulator@2b0 { compatible = "ti,pbias-omap3", "ti,pbias-omap"; reg = <0x2b0 0x4>; syscon = <&scm_conf>; pbias_mmc_reg: pbias_mmc_omap2430 { regulator-name = "pbias_mmc_omap2430"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; }; }; scm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; }; scm_clockdomains: clockdomains { }; omap3_pmx_wkup: pinmux@a00 { compatible = "ti,omap3-padconf", "pinctrl-single"; reg = <0xa00 0x5c>; #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xff1f>; }; }; }; aes: aes@480c5000 { compatible = "ti,omap3-aes"; ti,hwmods = "aes"; reg = <0x480c5000 0x50>; interrupts = <0>; dmas = <&sdma 65 &sdma 66>; dma-names = "tx", "rx"; }; prm: prm@48306000 { compatible = "ti,omap3-prm"; reg = <0x48306000 0x4000>; interrupts = <11>; prm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; prm_clockdomains: clockdomains { }; }; cm: cm@48004000 { compatible = "ti,omap3-cm"; reg = <0x48004000 0x4000>; cm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; cm_clockdomains: clockdomains { }; }; counter32k: counter@48320000 { compatible = "ti,omap-counter32k"; reg = <0x48320000 0x20>; ti,hwmods = "counter_32k"; }; intc: interrupt-controller@48200000 { compatible = "ti,omap3-intc"; interrupt-controller; #interrupt-cells = <1>; reg = <0x48200000 0x1000>; }; - target-module@48056000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x48056000 0x4>, - <0x4805602c 0x4>, - <0x48056028 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */ - clocks = <&core_l3_ick>; - clock-names = "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48056000 0x1000>; - - sdma: dma-controller@0 { - compatible = "ti,omap3430-sdma", "ti,omap-sdma"; - reg = <0x0 0x1000>; - interrupts = <12>, - <13>, - <14>, - <15>; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <96>; - }; + sdma: dma-controller@48056000 { + compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; + reg = <0x48056000 0x1000>; + interrupts = <12>, + <13>, + <14>, + <15>; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <96>; + ti,hwmods = "dma"; }; gpio1: gpio@48310000 { compatible = "ti,omap3-gpio"; reg = <0x48310000 0x200>; interrupts = <29>; ti,hwmods = "gpio1"; ti,gpio-always-on; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio2: gpio@49050000 { compatible = "ti,omap3-gpio"; reg = <0x49050000 0x200>; interrupts = <30>; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio3: gpio@49052000 { compatible = "ti,omap3-gpio"; reg = <0x49052000 0x200>; interrupts = <31>; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio4: gpio@49054000 { compatible = "ti,omap3-gpio"; reg = <0x49054000 0x200>; interrupts = <32>; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio5: gpio@49056000 { compatible = "ti,omap3-gpio"; reg = <0x49056000 0x200>; interrupts = <33>; ti,hwmods = "gpio5"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio6: gpio@49058000 { compatible = "ti,omap3-gpio"; reg = <0x49058000 0x200>; interrupts = <34>; ti,hwmods = "gpio6"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; uart1: serial@4806a000 { compatible = "ti,omap3-uart"; reg = <0x4806a000 0x2000>; interrupts-extended = <&intc 72>; dmas = <&sdma 49 &sdma 50>; dma-names = "tx", "rx"; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial@4806c000 { compatible = "ti,omap3-uart"; reg = <0x4806c000 0x400>; interrupts-extended = <&intc 73>; dmas = <&sdma 51 &sdma 52>; dma-names = "tx", "rx"; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial@49020000 { compatible = "ti,omap3-uart"; reg = <0x49020000 0x400>; interrupts-extended = <&intc 74>; dmas = <&sdma 53 &sdma 54>; dma-names = "tx", "rx"; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; i2c1: i2c@48070000 { compatible = "ti,omap3-i2c"; reg = <0x48070000 0x80>; interrupts = <56>; dmas = <&sdma 27 &sdma 28>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; }; i2c2: i2c@48072000 { compatible = "ti,omap3-i2c"; reg = <0x48072000 0x80>; interrupts = <57>; dmas = <&sdma 29 &sdma 30>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; }; i2c3: i2c@48060000 { compatible = "ti,omap3-i2c"; reg = <0x48060000 0x80>; interrupts = <61>; dmas = <&sdma 25 &sdma 26>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; }; mailbox: mailbox@48094000 { compatible = "ti,omap3-mailbox"; ti,hwmods = "mailbox"; reg = <0x48094000 0x200>; interrupts = <26>; #mbox-cells = <1>; ti,mbox-num-users = <2>; ti,mbox-num-fifos = <2>; mbox_dsp: dsp { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; }; mcspi1: spi@48098000 { compatible = "ti,omap2-mcspi"; reg = <0x48098000 0x100>; interrupts = <65>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi1"; ti,spi-num-cs = <4>; dmas = <&sdma 35>, <&sdma 36>, <&sdma 37>, <&sdma 38>, <&sdma 39>, <&sdma 40>, <&sdma 41>, <&sdma 42>; dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3"; }; mcspi2: spi@4809a000 { compatible = "ti,omap2-mcspi"; reg = <0x4809a000 0x100>; interrupts = <66>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi2"; ti,spi-num-cs = <2>; dmas = <&sdma 43>, <&sdma 44>, <&sdma 45>, <&sdma 46>; dma-names = "tx0", "rx0", "tx1", "rx1"; }; mcspi3: spi@480b8000 { compatible = "ti,omap2-mcspi"; reg = <0x480b8000 0x100>; interrupts = <91>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi3"; ti,spi-num-cs = <2>; dmas = <&sdma 15>, <&sdma 16>, <&sdma 23>, <&sdma 24>; dma-names = "tx0", "rx0", "tx1", "rx1"; }; mcspi4: spi@480ba000 { compatible = "ti,omap2-mcspi"; reg = <0x480ba000 0x100>; interrupts = <48>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi4"; ti,spi-num-cs = <1>; dmas = <&sdma 70>, <&sdma 71>; dma-names = "tx0", "rx0"; }; hdqw1w: 1w@480b2000 { compatible = "ti,omap3-1w"; reg = <0x480b2000 0x1000>; interrupts = <58>; ti,hwmods = "hdq1w"; }; mmc1: mmc@4809c000 { compatible = "ti,omap3-hsmmc"; reg = <0x4809c000 0x200>; interrupts = <83>; ti,hwmods = "mmc1"; ti,dual-volt; dmas = <&sdma 61>, <&sdma 62>; dma-names = "tx", "rx"; pbias-supply = <&pbias_mmc_reg>; }; mmc2: mmc@480b4000 { compatible = "ti,omap3-hsmmc"; reg = <0x480b4000 0x200>; interrupts = <86>; ti,hwmods = "mmc2"; dmas = <&sdma 47>, <&sdma 48>; dma-names = "tx", "rx"; }; mmc3: mmc@480ad000 { compatible = "ti,omap3-hsmmc"; reg = <0x480ad000 0x200>; interrupts = <94>; ti,hwmods = "mmc3"; dmas = <&sdma 77>, <&sdma 78>; dma-names = "tx", "rx"; }; mmu_isp: mmu@480bd400 { #iommu-cells = <0>; compatible = "ti,omap2-iommu"; reg = <0x480bd400 0x80>; interrupts = <24>; ti,hwmods = "mmu_isp"; ti,#tlb-entries = <8>; }; mmu_iva: mmu@5d000000 { #iommu-cells = <0>; compatible = "ti,omap2-iommu"; reg = <0x5d000000 0x80>; interrupts = <28>; ti,hwmods = "mmu_iva"; status = "disabled"; }; wdt2: wdt@48314000 { compatible = "ti,omap3-wdt"; reg = <0x48314000 0x80>; ti,hwmods = "wd_timer2"; }; mcbsp1: mcbsp@48074000 { compatible = "ti,omap3-mcbsp"; reg = <0x48074000 0xff>; reg-names = "mpu"; interrupts = <16>, /* OCP compliant interrupt */ <59>, /* TX interrupt */ <60>; /* RX interrupt */ interrupt-names = "common", "tx", "rx"; ti,buffer-size = <128>; ti,hwmods = "mcbsp1"; dmas = <&sdma 31>, <&sdma 32>; dma-names = "tx", "rx"; clocks = <&mcbsp1_fck>; clock-names = "fck"; status = "disabled"; }; - /* Likely needs to be tagged disabled on HS devices */ - rng_target: target-module@480a0000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x480a003c 0x4>, - <0x480a0040 0x4>, - <0x480a0044 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - ; - ti,syss-mask = <1>; - clocks = <&rng_ick>; - clock-names = "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x480a0000 0x2000>; - - rng: rng@0 { - compatible = "ti,omap2-rng"; - reg = <0x0 0x2000>; - interrupts = <52>; - }; - }; - mcbsp2: mcbsp@49022000 { compatible = "ti,omap3-mcbsp"; reg = <0x49022000 0xff>, <0x49028000 0xff>; reg-names = "mpu", "sidetone"; interrupts = <17>, /* OCP compliant interrupt */ <62>, /* TX interrupt */ <63>, /* RX interrupt */ <4>; /* Sidetone */ interrupt-names = "common", "tx", "rx", "sidetone"; ti,buffer-size = <1280>; ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; dmas = <&sdma 33>, <&sdma 34>; dma-names = "tx", "rx"; clocks = <&mcbsp2_fck>, <&mcbsp2_ick>; clock-names = "fck", "ick"; status = "disabled"; }; mcbsp3: mcbsp@49024000 { compatible = "ti,omap3-mcbsp"; reg = <0x49024000 0xff>, <0x4902a000 0xff>; reg-names = "mpu", "sidetone"; interrupts = <22>, /* OCP compliant interrupt */ <89>, /* TX interrupt */ <90>, /* RX interrupt */ <5>; /* Sidetone */ interrupt-names = "common", "tx", "rx", "sidetone"; ti,buffer-size = <128>; ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; dmas = <&sdma 17>, <&sdma 18>; dma-names = "tx", "rx"; clocks = <&mcbsp3_fck>, <&mcbsp3_ick>; clock-names = "fck", "ick"; status = "disabled"; }; mcbsp4: mcbsp@49026000 { compatible = "ti,omap3-mcbsp"; reg = <0x49026000 0xff>; reg-names = "mpu"; interrupts = <23>, /* OCP compliant interrupt */ <54>, /* TX interrupt */ <55>; /* RX interrupt */ interrupt-names = "common", "tx", "rx"; ti,buffer-size = <128>; ti,hwmods = "mcbsp4"; dmas = <&sdma 19>, <&sdma 20>; dma-names = "tx", "rx"; clocks = <&mcbsp4_fck>; clock-names = "fck"; #sound-dai-cells = <0>; status = "disabled"; }; mcbsp5: mcbsp@48096000 { compatible = "ti,omap3-mcbsp"; reg = <0x48096000 0xff>; reg-names = "mpu"; interrupts = <27>, /* OCP compliant interrupt */ <81>, /* TX interrupt */ <82>; /* RX interrupt */ interrupt-names = "common", "tx", "rx"; ti,buffer-size = <128>; ti,hwmods = "mcbsp5"; dmas = <&sdma 21>, <&sdma 22>; dma-names = "tx", "rx"; clocks = <&mcbsp5_fck>; clock-names = "fck"; status = "disabled"; }; sham: sham@480c3000 { compatible = "ti,omap3-sham"; ti,hwmods = "sham"; reg = <0x480c3000 0x64>; interrupts = <49>; dmas = <&sdma 69>; dma-names = "rx"; }; timer1: timer@48318000 { compatible = "ti,omap3430-timer"; reg = <0x48318000 0x400>; interrupts = <37>; ti,hwmods = "timer1"; ti,timer-alwon; }; timer2: timer@49032000 { compatible = "ti,omap3430-timer"; reg = <0x49032000 0x400>; interrupts = <38>; ti,hwmods = "timer2"; }; timer3: timer@49034000 { compatible = "ti,omap3430-timer"; reg = <0x49034000 0x400>; interrupts = <39>; ti,hwmods = "timer3"; }; timer4: timer@49036000 { compatible = "ti,omap3430-timer"; reg = <0x49036000 0x400>; interrupts = <40>; ti,hwmods = "timer4"; }; timer5: timer@49038000 { compatible = "ti,omap3430-timer"; reg = <0x49038000 0x400>; interrupts = <41>; ti,hwmods = "timer5"; ti,timer-dsp; }; timer6: timer@4903a000 { compatible = "ti,omap3430-timer"; reg = <0x4903a000 0x400>; interrupts = <42>; ti,hwmods = "timer6"; ti,timer-dsp; }; timer7: timer@4903c000 { compatible = "ti,omap3430-timer"; reg = <0x4903c000 0x400>; interrupts = <43>; ti,hwmods = "timer7"; ti,timer-dsp; }; timer8: timer@4903e000 { compatible = "ti,omap3430-timer"; reg = <0x4903e000 0x400>; interrupts = <44>; ti,hwmods = "timer8"; ti,timer-pwm; ti,timer-dsp; }; timer9: timer@49040000 { compatible = "ti,omap3430-timer"; reg = <0x49040000 0x400>; interrupts = <45>; ti,hwmods = "timer9"; ti,timer-pwm; }; timer10: timer@48086000 { compatible = "ti,omap3430-timer"; reg = <0x48086000 0x400>; interrupts = <46>; ti,hwmods = "timer10"; ti,timer-pwm; }; timer11: timer@48088000 { compatible = "ti,omap3430-timer"; reg = <0x48088000 0x400>; interrupts = <47>; ti,hwmods = "timer11"; ti,timer-pwm; }; timer12: timer@48304000 { compatible = "ti,omap3430-timer"; reg = <0x48304000 0x400>; interrupts = <95>; ti,hwmods = "timer12"; ti,timer-alwon; ti,timer-secure; }; usbhstll: usbhstll@48062000 { compatible = "ti,usbhs-tll"; reg = <0x48062000 0x1000>; interrupts = <78>; ti,hwmods = "usb_tll_hs"; }; usbhshost: usbhshost@48064000 { compatible = "ti,usbhs-host"; reg = <0x48064000 0x400>; ti,hwmods = "usb_host_hs"; #address-cells = <1>; #size-cells = <1>; ranges; usbhsohci: ohci@48064400 { compatible = "ti,ohci-omap3"; reg = <0x48064400 0x400>; interrupts = <76>; remote-wakeup-connected; }; usbhsehci: ehci@48064800 { compatible = "ti,ehci-omap"; reg = <0x48064800 0x400>; interrupts = <77>; }; }; gpmc: gpmc@6e000000 { compatible = "ti,omap3430-gpmc"; ti,hwmods = "gpmc"; reg = <0x6e000000 0x02d0>; interrupts = <20>; dmas = <&sdma 4>; dma-names = "rxtx"; gpmc,num-cs = <8>; gpmc,num-waitpins = <4>; #address-cells = <2>; #size-cells = <1>; interrupt-controller; #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; }; usb_otg_hs: usb_otg_hs@480ab000 { compatible = "ti,omap3-musb"; reg = <0x480ab000 0x1000>; interrupts = <92>, <93>; interrupt-names = "mc", "dma"; ti,hwmods = "usb_otg_hs"; multipoint = <1>; num-eps = <16>; ram-bits = <12>; }; dss: dss@48050000 { compatible = "ti,omap3-dss"; reg = <0x48050000 0x200>; status = "disabled"; ti,hwmods = "dss_core"; clocks = <&dss1_alwon_fck>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges; dispc@48050400 { compatible = "ti,omap3-dispc"; reg = <0x48050400 0x400>; interrupts = <25>; ti,hwmods = "dss_dispc"; clocks = <&dss1_alwon_fck>; clock-names = "fck"; }; dsi: encoder@4804fc00 { compatible = "ti,omap3-dsi"; reg = <0x4804fc00 0x200>, <0x4804fe00 0x40>, <0x4804ff00 0x20>; reg-names = "proto", "phy", "pll"; interrupts = <25>; status = "disabled"; ti,hwmods = "dss_dsi1"; clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; clock-names = "fck", "sys_clk"; }; rfbi: encoder@48050800 { compatible = "ti,omap3-rfbi"; reg = <0x48050800 0x100>; status = "disabled"; ti,hwmods = "dss_rfbi"; clocks = <&dss1_alwon_fck>, <&dss_ick>; clock-names = "fck", "ick"; }; venc: encoder@48050c00 { compatible = "ti,omap3-venc"; reg = <0x48050c00 0x100>; status = "disabled"; ti,hwmods = "dss_venc"; clocks = <&dss_tv_fck>; clock-names = "fck"; }; }; ssi: ssi-controller@48058000 { compatible = "ti,omap3-ssi"; ti,hwmods = "ssi"; status = "disabled"; reg = <0x48058000 0x1000>, <0x48059000 0x1000>; reg-names = "sys", "gdd"; interrupts = <71>; interrupt-names = "gdd_mpu"; #address-cells = <1>; #size-cells = <1>; ranges; ssi_port1: ssi-port@4805a000 { compatible = "ti,omap3-ssi-port"; reg = <0x4805a000 0x800>, <0x4805a800 0x800>; reg-names = "tx", "rx"; interrupts = <67>, <68>; }; ssi_port2: ssi-port@4805b000 { compatible = "ti,omap3-ssi-port"; reg = <0x4805b000 0x800>, <0x4805b800 0x800>; reg-names = "tx", "rx"; interrupts = <69>, <70>; }; }; }; }; /include/ "omap3xxx-clocks.dtsi" diff --git a/sys/gnu/dts/arm/omap3430-sdp.dts b/sys/gnu/dts/arm/omap3430-sdp.dts index 7bfde8aac7ae..0abd61108a53 100644 --- a/sys/gnu/dts/arm/omap3430-sdp.dts +++ b/sys/gnu/dts/arm/omap3430-sdp.dts @@ -1,195 +1,195 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; #include "omap34xx.dtsi" / { model = "TI OMAP3430 SDP"; - compatible = "ti,omap3430-sdp", "ti,omap3430", "ti,omap3"; + compatible = "ti,omap3430-sdp", "ti,omap3"; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; }; &i2c1 { clock-frequency = <2600000>; twl: twl@48 { reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ }; }; #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" &mmc1 { vmmc-supply = <&vmmc1>; vqmmc-supply = <&vsim>; /* * S6-3 must be in ON position for 8 bit mode to function * Else, use 4 bit mode */ bus-width = <8>; }; &mmc2 { status = "disabled"; }; &mmc3 { status = "disabled"; }; &gpmc { ranges = <0 0 0x10000000 0x08000000>, <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */ <2 0 0x20000000 0x1000000>; /* CS2: 16MB for OneNAND */ nor@0,0 { compatible = "cfi-flash"; linux,mtd-name= "intel,pf48f6000m0y1be"; #address-cells = <1>; #size-cells = <1>; reg = <0 0 0x08000000>; bank-width = <2>; gpmc,mux-add-data = <2>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <186>; gpmc,cs-wr-off-ns = <186>; gpmc,adv-on-ns = <12>; gpmc,adv-rd-off-ns = <48>; gpmc,adv-wr-off-ns = <48>; gpmc,oe-on-ns = <54>; gpmc,oe-off-ns = <168>; gpmc,we-on-ns = <54>; gpmc,we-off-ns = <168>; gpmc,rd-cycle-ns = <186>; gpmc,wr-cycle-ns = <186>; gpmc,access-ns = <114>; gpmc,page-burst-access-ns = <6>; gpmc,bus-turnaround-ns = <12>; gpmc,cycle2cycle-delay-ns = <18>; gpmc,wr-data-mux-bus-ns = <90>; gpmc,wr-access-ns = <186>; gpmc,cycle2cycle-samecsen; gpmc,cycle2cycle-diffcsen; partition@0 { label = "bootloader-nor"; reg = <0 0x40000>; }; partition@40000 { label = "params-nor"; reg = <0x40000 0x40000>; }; partition@80000 { label = "kernel-nor"; reg = <0x80000 0x200000>; }; partition@280000 { label = "filesystem-nor"; reg = <0x240000 0x7d80000>; }; }; nand@1,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ linux,mtd-name= "micron,mt29f1g08abb"; #address-cells = <1>; #size-cells = <1>; ti,nand-ecc-opt = "sw"; nand-bus-width = <8>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <36>; gpmc,cs-wr-off-ns = <36>; gpmc,adv-on-ns = <6>; gpmc,adv-rd-off-ns = <24>; gpmc,adv-wr-off-ns = <36>; gpmc,oe-on-ns = <6>; gpmc,oe-off-ns = <48>; gpmc,we-on-ns = <6>; gpmc,we-off-ns = <30>; gpmc,rd-cycle-ns = <72>; gpmc,wr-cycle-ns = <72>; gpmc,access-ns = <54>; gpmc,wr-access-ns = <30>; partition@0 { label = "xloader-nand"; reg = <0 0x80000>; }; partition@80000 { label = "bootloader-nand"; reg = <0x80000 0x140000>; }; partition@1c0000 { label = "params-nand"; reg = <0x1c0000 0xc0000>; }; partition@280000 { label = "kernel-nand"; reg = <0x280000 0x500000>; }; partition@780000 { label = "filesystem-nand"; reg = <0x780000 0x7880000>; }; }; onenand@2,0 { linux,mtd-name= "samsung,kfm2g16q2m-deb8"; #address-cells = <1>; #size-cells = <1>; compatible = "ti,omap2-onenand"; reg = <2 0 0x20000>; /* CS2, offset 0, IO size 4 */ gpmc,device-width = <2>; gpmc,mux-add-data = <2>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <84>; gpmc,cs-wr-off-ns = <72>; gpmc,adv-on-ns = <0>; gpmc,adv-rd-off-ns = <18>; gpmc,adv-wr-off-ns = <18>; gpmc,oe-on-ns = <30>; gpmc,oe-off-ns = <84>; gpmc,we-on-ns = <0>; gpmc,we-off-ns = <42>; gpmc,rd-cycle-ns = <108>; gpmc,wr-cycle-ns = <96>; gpmc,access-ns = <78>; gpmc,wr-data-mux-bus-ns = <30>; partition@0 { label = "xloader-onenand"; reg = <0 0x80000>; }; partition@80000 { label = "bootloader-onenand"; reg = <0x80000 0x40000>; }; partition@c0000 { label = "params-onenand"; reg = <0xc0000 0x20000>; }; partition@e0000 { label = "kernel-onenand"; reg = <0xe0000 0x200000>; }; partition@2e0000 { label = "filesystem-onenand"; reg = <0x2e0000 0xfd20000>; }; }; }; diff --git a/sys/gnu/dts/arm/omap34xx-omap36xx-clocks.dtsi b/sys/gnu/dts/arm/omap34xx-omap36xx-clocks.dtsi index 21079cdf2663..5e9d1afcd422 100644 --- a/sys/gnu/dts/arm/omap34xx-omap36xx-clocks.dtsi +++ b/sys/gnu/dts/arm/omap34xx-omap36xx-clocks.dtsi @@ -1,265 +1,265 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP34XX/OMAP36XX clock data * * Copyright (C) 2013 Texas Instruments, Inc. */ &cm_clocks { security_l4_ick2: security_l4_ick2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&l4_ick>; clock-mult = <1>; clock-div = <1>; }; aes1_ick: aes1_ick@a14 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&security_l4_ick2>; ti,bit-shift = <3>; reg = <0x0a14>; }; rng_ick: rng_ick@a14 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&security_l4_ick2>; reg = <0x0a14>; ti,bit-shift = <2>; }; sha11_ick: sha11_ick@a14 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&security_l4_ick2>; reg = <0x0a14>; ti,bit-shift = <1>; }; des1_ick: des1_ick@a14 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&security_l4_ick2>; reg = <0x0a14>; ti,bit-shift = <0>; }; cam_mclk: cam_mclk@f00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll4_m5x2_ck>; ti,bit-shift = <0>; reg = <0x0f00>; ti,set-rate-parent; }; cam_ick: cam_ick@f10 { #clock-cells = <0>; compatible = "ti,omap3-no-wait-interface-clock"; clocks = <&l4_ick>; reg = <0x0f10>; ti,bit-shift = <0>; }; csi2_96m_fck: csi2_96m_fck@f00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&core_96m_fck>; reg = <0x0f00>; ti,bit-shift = <1>; }; security_l3_ick: security_l3_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&l3_ick>; clock-mult = <1>; clock-div = <1>; }; pka_ick: pka_ick@a14 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&security_l3_ick>; reg = <0x0a14>; ti,bit-shift = <4>; }; icr_ick: icr_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <29>; }; des2_ick: des2_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <26>; }; mspro_ick: mspro_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <23>; }; mailboxes_ick: mailboxes_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <7>; }; ssi_l4_ick: ssi_l4_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&l4_ick>; clock-mult = <1>; clock-div = <1>; }; sr1_fck: sr1_fck@c00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&sys_ck>; reg = <0x0c00>; ti,bit-shift = <6>; }; sr2_fck: sr2_fck@c00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&sys_ck>; reg = <0x0c00>; ti,bit-shift = <7>; }; sr_l4_ick: sr_l4_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&l4_ick>; clock-mult = <1>; clock-div = <1>; }; dpll2_fck: dpll2_fck@40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&core_ck>; ti,bit-shift = <19>; ti,max-div = <7>; reg = <0x0040>; ti,index-starts-at-one; }; dpll2_ck: dpll2_ck@4 { #clock-cells = <0>; compatible = "ti,omap3-dpll-clock"; clocks = <&sys_ck>, <&dpll2_fck>; reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>; ti,low-power-stop; ti,lock; ti,low-power-bypass; }; dpll2_m2_ck: dpll2_m2_ck@44 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll2_ck>; ti,max-div = <31>; reg = <0x0044>; ti,index-starts-at-one; }; iva2_ck: iva2_ck@0 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&dpll2_m2_ck>; reg = <0x0000>; ti,bit-shift = <0>; }; modem_fck: modem_fck@a00 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&sys_ck>; reg = <0x0a00>; ti,bit-shift = <31>; }; sad2d_ick: sad2d_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l3_ick>; reg = <0x0a10>; ti,bit-shift = <3>; }; mad2d_ick: mad2d_ick@a18 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l3_ick>; reg = <0x0a18>; ti,bit-shift = <3>; }; mspro_fck: mspro_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_96m_fck>; reg = <0x0a00>; ti,bit-shift = <23>; }; }; &cm_clockdomains { cam_clkdm: cam_clkdm { compatible = "ti,clockdomain"; clocks = <&cam_ick>, <&csi2_96m_fck>; }; iva2_clkdm: iva2_clkdm { compatible = "ti,clockdomain"; clocks = <&iva2_ck>; }; dpll2_clkdm: dpll2_clkdm { compatible = "ti,clockdomain"; clocks = <&dpll2_ck>; }; wkup_clkdm: wkup_clkdm { compatible = "ti,clockdomain"; clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>; }; d2d_clkdm: d2d_clkdm { compatible = "ti,clockdomain"; clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>; }; core_l4_clkdm: core_l4_clkdm { compatible = "ti,clockdomain"; clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>, <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>, - <&rng_ick>, <&mspro_fck>; + <&mspro_fck>; }; }; diff --git a/sys/gnu/dts/arm/omap34xx.dtsi b/sys/gnu/dts/arm/omap34xx.dtsi index c4dd9801840d..7b09cbee8bb8 100644 --- a/sys/gnu/dts/arm/omap34xx.dtsi +++ b/sys/gnu/dts/arm/omap34xx.dtsi @@ -1,197 +1,149 @@ /* * Device Tree Source for OMAP34xx/OMAP35xx SoC * * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ #include #include #include "omap3.dtsi" / { cpus { cpu: cpu@0 { - /* OMAP343x/OMAP35xx variants OPP1-6 */ - operating-points-v2 = <&cpu0_opp_table>; - + /* OMAP343x/OMAP35xx variants OPP1-5 */ + operating-points = < + /* kHz uV */ + 125000 975000 + 250000 1075000 + 500000 1200000 + 550000 1270000 + 600000 1350000 + >; clock-latency = <300000>; /* From legacy driver */ }; }; - /* see Documentation/devicetree/bindings/opp/opp.txt */ - cpu0_opp_table: opp-table { - compatible = "operating-points-v2-ti-cpu"; - syscon = <&scm_conf>; - - opp1-125000000 { - opp-hz = /bits/ 64 <125000000>; - /* - * we currently only select the max voltage from table - * Table 3-3 of the omap3530 Data sheet (SPRS507F). - * Format is: - */ - opp-microvolt = <975000 975000 975000>; - /* - * first value is silicon revision bit mask - * second one 720MHz Device Identification bit mask - */ - opp-supported-hw = <0xffffffff 3>; - }; - - opp2-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <1075000 1075000 1075000>; - opp-supported-hw = <0xffffffff 3>; - opp-suspend; - }; - - opp3-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1200000 1200000 1200000>; - opp-supported-hw = <0xffffffff 3>; - }; - - opp4-550000000 { - opp-hz = /bits/ 64 <550000000>; - opp-microvolt = <1275000 1275000 1275000>; - opp-supported-hw = <0xffffffff 3>; - }; - - opp5-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1350000 1350000 1350000>; - opp-supported-hw = <0xffffffff 3>; - }; - - opp6-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1350000 1350000 1350000>; - /* only high-speed grade omap3530 devices */ - opp-supported-hw = <0xffffffff 2>; - turbo-mode; - }; - }; - ocp@68000000 { omap3_pmx_core2: pinmux@480025d8 { compatible = "ti,omap3-padconf", "pinctrl-single"; reg = <0x480025d8 0x24>; #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xff1f>; }; isp: isp@480bc000 { compatible = "ti,omap3-isp"; reg = <0x480bc000 0x12fc 0x480bd800 0x017c>; interrupts = <24>; iommus = <&mmu_isp>; syscon = <&scm_conf 0x6c>; ti,phy-type = ; #clock-cells = <1>; ports { #address-cells = <1>; #size-cells = <0>; }; }; bandgap: bandgap@48002524 { reg = <0x48002524 0x4>; compatible = "ti,omap34xx-bandgap"; #thermal-sensor-cells = <0>; }; target-module@480cb000 { compatible = "ti,sysc-omap3430-sr", "ti,sysc"; ti,hwmods = "smartreflex_core"; reg = <0x480cb024 0x4>; reg-names = "sysc"; ti,sysc-mask = ; clocks = <&sr2_fck>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x480cb000 0x001000>; smartreflex_core: smartreflex@0 { compatible = "ti,omap3-smartreflex-core"; reg = <0 0x400>; interrupts = <19>; }; }; target-module@480c9000 { compatible = "ti,sysc-omap3430-sr", "ti,sysc"; ti,hwmods = "smartreflex_mpu_iva"; reg = <0x480c9024 0x4>; reg-names = "sysc"; ti,sysc-mask = ; clocks = <&sr1_fck>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x480c9000 0x001000>; smartreflex_mpu_iva: smartreflex@480c9000 { compatible = "ti,omap3-smartreflex-mpu-iva"; reg = <0 0x400>; interrupts = <18>; }; }; /* * On omap34xx the OCP registers do not seem to be accessible * at all unlike on 36xx. Maybe SGX is permanently set to * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is * write-only at 0x50000e10. We detect SGX based on the SGX * revision register instead of the unreadable OCP revision * register. Also note that on early 34xx es1 revision there * are also different clocks, but we do not have any dts users * for it. */ sgx_module: target-module@50000000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x50000014 0x4>; reg-names = "rev"; clocks = <&sgx_fck>, <&sgx_ick>; clock-names = "fck", "ick"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x50000000 0x4000>; /* * Closed source PowerVR driver, no child device * binding or driver in mainline */ }; }; thermal_zones: thermal-zones { #include "omap3-cpu-thermal.dtsi" }; }; &ssi { status = "ok"; clocks = <&ssi_ssr_fck>, <&ssi_sst_fck>, <&ssi_ick>; clock-names = "ssi_ssr_fck", "ssi_sst_fck", "ssi_ick"; }; /include/ "omap34xx-omap36xx-clocks.dtsi" /include/ "omap36xx-omap3430es2plus-clocks.dtsi" /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/sys/gnu/dts/arm/omap36xx-clocks.dtsi b/sys/gnu/dts/arm/omap36xx-clocks.dtsi index 4e9cc9003594..e66fc57ec35d 100644 --- a/sys/gnu/dts/arm/omap36xx-clocks.dtsi +++ b/sys/gnu/dts/arm/omap36xx-clocks.dtsi @@ -1,111 +1,107 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP36xx clock data * * Copyright (C) 2013 Texas Instruments, Inc. */ &cm_clocks { dpll4_ck: dpll4_ck@d00 { #clock-cells = <0>; compatible = "ti,omap3-dpll-per-j-type-clock"; clocks = <&sys_ck>, <&sys_ck>; reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; }; dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { #clock-cells = <0>; compatible = "ti,hsdiv-gate-clock"; clocks = <&dpll4_m5x2_mul_ck>; ti,bit-shift = <0x1e>; reg = <0x0d00>; ti,set-rate-parent; ti,set-bit-to-disable; }; dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { #clock-cells = <0>; compatible = "ti,hsdiv-gate-clock"; clocks = <&dpll4_m2x2_mul_ck>; ti,bit-shift = <0x1b>; reg = <0x0d00>; ti,set-bit-to-disable; }; dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { #clock-cells = <0>; compatible = "ti,hsdiv-gate-clock"; clocks = <&dpll3_m3x2_mul_ck>; ti,bit-shift = <0xc>; reg = <0x0d00>; ti,set-bit-to-disable; }; dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { #clock-cells = <0>; compatible = "ti,hsdiv-gate-clock"; clocks = <&dpll4_m3x2_mul_ck>; ti,bit-shift = <0x1c>; reg = <0x0d00>; ti,set-bit-to-disable; }; dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { #clock-cells = <0>; compatible = "ti,hsdiv-gate-clock"; clocks = <&dpll4_m6x2_mul_ck>; ti,bit-shift = <0x1f>; reg = <0x0d00>; ti,set-bit-to-disable; }; uart4_fck: uart4_fck@1000 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&per_48m_fck>; reg = <0x1000>; ti,bit-shift = <18>; }; }; &dpll4_m2x2_mul_ck { clock-mult = <1>; }; &dpll4_m3x2_mul_ck { clock-mult = <1>; }; &dpll4_m4x2_mul_ck { ti,clock-mult = <1>; }; &dpll4_m5x2_mul_ck { ti,clock-mult = <1>; }; &dpll4_m6x2_mul_ck { clock-mult = <1>; }; &cm_clockdomains { dpll4_clkdm: dpll4_clkdm { compatible = "ti,clockdomain"; clocks = <&dpll4_ck>; }; per_clkdm: per_clkdm { compatible = "ti,clockdomain"; clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, <&mcbsp4_ick>, <&uart4_fck>; }; }; - -&dpll4_m4_ck { - ti,max-div = <31>; -}; diff --git a/sys/gnu/dts/arm/omap36xx.dtsi b/sys/gnu/dts/arm/omap36xx.dtsi index 71f3c8f1f924..1e552f08f120 100644 --- a/sys/gnu/dts/arm/omap36xx.dtsi +++ b/sys/gnu/dts/arm/omap36xx.dtsi @@ -1,250 +1,197 @@ /* * Device Tree Source for OMAP3 SoC * * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ #include #include #include "omap3.dtsi" / { aliases { serial3 = &uart4; }; cpus { - /* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */ + /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */ cpu: cpu@0 { - operating-points-v2 = <&cpu0_opp_table>; - - vbb-supply = <&abb_mpu_iva>; - clock-latency = <300000>; /* From omap-cpufreq driver */ - }; - }; - - /* see Documentation/devicetree/bindings/opp/opp.txt */ - cpu0_opp_table: opp-table { - compatible = "operating-points-v2-ti-cpu"; - syscon = <&scm_conf>; - - opp50-300000000 { - opp-hz = /bits/ 64 <300000000>; - /* - * we currently only select the max voltage from table - * Table 4-19 of the DM3730 Data sheet (SPRS685B) - * Format is: cpu0-supply: - * vbb-supply: - */ - opp-microvolt = <1012500 1012500 1012500>, - <1012500 1012500 1012500>; - /* - * first value is silicon revision bit mask - * second one is "speed binned" bit mask - */ - opp-supported-hw = <0xffffffff 3>; - opp-suspend; - }; - - opp100-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1200000 1200000 1200000>, - <1200000 1200000 1200000>; - opp-supported-hw = <0xffffffff 3>; - }; - - opp130-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1325000 1325000 1325000>, - <1325000 1325000 1325000>; - opp-supported-hw = <0xffffffff 3>; - }; - - opp1g-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1375000 1375000 1375000>, - <1375000 1375000 1375000>; - /* only on am/dm37x with speed-binned bit set */ - opp-supported-hw = <0xffffffff 2>; - turbo-mode; + operating-points = < + /* kHz uV */ + 300000 1012500 + 600000 1200000 + 800000 1325000 + >; + clock-latency = <300000>; /* From legacy driver */ }; }; - opp_supply_mpu_iva: opp_supply { - compatible = "ti,omap-opp-supply"; - ti,absolute-max-voltage-uv = <1375000>; - }; - ocp@68000000 { uart4: serial@49042000 { compatible = "ti,omap3-uart"; reg = <0x49042000 0x400>; interrupts = <80>; dmas = <&sdma 81 &sdma 82>; dma-names = "tx", "rx"; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; abb_mpu_iva: regulator-abb-mpu { compatible = "ti,abb-v1"; regulator-name = "abb_mpu_iva"; #address-cells = <0>; #size-cells = <0>; reg = <0x483072f0 0x8>, <0x48306818 0x4>; reg-names = "base-address", "int-address"; ti,tranxdone-status-mask = <0x4000000>; clocks = <&sys_ck>; ti,settling-time = <30>; ti,clock-cycles = <8>; ti,abb_info = < /*uV ABB efuse rbb_m fbb_m vset_m*/ 1012500 0 0 0 0 0 1200000 0 0 0 0 0 1325000 0 0 0 0 0 1375000 1 0 0 0 0 >; }; omap3_pmx_core2: pinmux@480025a0 { compatible = "ti,omap3-padconf", "pinctrl-single"; reg = <0x480025a0 0x5c>; #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xff1f>; }; isp: isp@480bc000 { compatible = "ti,omap3-isp"; reg = <0x480bc000 0x12fc 0x480bd800 0x0600>; interrupts = <24>; iommus = <&mmu_isp>; syscon = <&scm_conf 0x2f0>; ti,phy-type = ; #clock-cells = <1>; ports { #address-cells = <1>; #size-cells = <0>; }; }; bandgap: bandgap@48002524 { reg = <0x48002524 0x4>; compatible = "ti,omap36xx-bandgap"; #thermal-sensor-cells = <0>; }; target-module@480cb000 { compatible = "ti,sysc-omap3630-sr", "ti,sysc"; ti,hwmods = "smartreflex_core"; reg = <0x480cb038 0x4>; reg-names = "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; clocks = <&sr2_fck>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x480cb000 0x001000>; smartreflex_core: smartreflex@0 { compatible = "ti,omap3-smartreflex-core"; reg = <0 0x400>; interrupts = <19>; }; }; target-module@480c9000 { compatible = "ti,sysc-omap3630-sr", "ti,sysc"; ti,hwmods = "smartreflex_mpu_iva"; reg = <0x480c9038 0x4>; reg-names = "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; clocks = <&sr1_fck>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x480c9000 0x001000>; smartreflex_mpu_iva: smartreflex@480c9000 { compatible = "ti,omap3-smartreflex-mpu-iva"; reg = <0 0x400>; interrupts = <18>; }; }; /* * Note that the sysconfig register layout is a subset of the * "ti,sysc-omap4" type register with just sidle and midle bits * available while omap34xx has "ti,sysc-omap2" type sysconfig. */ sgx_module: target-module@50000000 { compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x5000fe00 0x4>, <0x5000fe10 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = , , ; ti,sysc-sidle = , , ; clocks = <&sgx_fck>, <&sgx_ick>; clock-names = "fck", "ick"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x50000000 0x2000000>; /* * Closed source PowerVR driver, no child device * binding or driver in mainline */ }; }; thermal_zones: thermal-zones { #include "omap3-cpu-thermal.dtsi" }; }; -&sdma { - compatible = "ti,omap3630-sdma", "ti,omap-sdma"; -}; - /* OMAP3630 needs dss_96m_fck for VENC */ &venc { clocks = <&dss_tv_fck>, <&dss_96m_fck>; clock-names = "fck", "tv_dac_clk"; }; &ssi { status = "ok"; clocks = <&ssi_ssr_fck>, <&ssi_sst_fck>, <&ssi_ick>; clock-names = "ssi_ssr_fck", "ssi_sst_fck", "ssi_ick"; }; /include/ "omap34xx-omap36xx-clocks.dtsi" /include/ "omap36xx-omap3430es2plus-clocks.dtsi" /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" /include/ "omap36xx-clocks.dtsi" diff --git a/sys/gnu/dts/arm/omap3xxx-clocks.dtsi b/sys/gnu/dts/arm/omap3xxx-clocks.dtsi index 0656c32439d2..685c82a9d03e 100644 --- a/sys/gnu/dts/arm/omap3xxx-clocks.dtsi +++ b/sys/gnu/dts/arm/omap3xxx-clocks.dtsi @@ -1,1662 +1,1662 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP3 clock data * * Copyright (C) 2013 Texas Instruments, Inc. */ &prm_clocks { virt_16_8m_ck: virt_16_8m_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <16800000>; }; osc_sys_ck: osc_sys_ck@d40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>; reg = <0x0d40>; }; sys_ck: sys_ck@1270 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&osc_sys_ck>; ti,bit-shift = <6>; ti,max-div = <3>; reg = <0x1270>; ti,index-starts-at-one; }; sys_clkout1: sys_clkout1@d70 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&osc_sys_ck>; reg = <0x0d70>; ti,bit-shift = <7>; }; dpll3_x2_ck: dpll3_x2_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll3_ck>; clock-mult = <2>; clock-div = <1>; }; dpll3_m2x2_ck: dpll3_m2x2_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll3_m2_ck>; clock-mult = <2>; clock-div = <1>; }; dpll4_x2_ck: dpll4_x2_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll4_ck>; clock-mult = <2>; clock-div = <1>; }; corex2_fck: corex2_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll3_m2x2_ck>; clock-mult = <1>; clock-div = <1>; }; wkup_l4_ick: wkup_l4_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_ck>; clock-mult = <1>; clock-div = <1>; }; }; &scm_clocks { mcbsp5_mux_fck: mcbsp5_mux_fck@68 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&core_96m_fck>, <&mcbsp_clks>; ti,bit-shift = <4>; reg = <0x68>; }; mcbsp5_fck: mcbsp5_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; }; mcbsp1_mux_fck: mcbsp1_mux_fck@4 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&core_96m_fck>, <&mcbsp_clks>; ti,bit-shift = <2>; reg = <0x04>; }; mcbsp1_fck: mcbsp1_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; }; mcbsp2_mux_fck: mcbsp2_mux_fck@4 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&per_96m_fck>, <&mcbsp_clks>; ti,bit-shift = <6>; reg = <0x04>; }; mcbsp2_fck: mcbsp2_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; }; mcbsp3_mux_fck: mcbsp3_mux_fck@68 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&per_96m_fck>, <&mcbsp_clks>; reg = <0x68>; }; mcbsp3_fck: mcbsp3_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; }; mcbsp4_mux_fck: mcbsp4_mux_fck@68 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&per_96m_fck>, <&mcbsp_clks>; ti,bit-shift = <2>; reg = <0x68>; }; mcbsp4_fck: mcbsp4_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; }; }; &cm_clocks { dummy_apb_pclk: dummy_apb_pclk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0x0>; }; omap_32k_fck: omap_32k_fck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; virt_12m_ck: virt_12m_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <12000000>; }; virt_13m_ck: virt_13m_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <13000000>; }; virt_19200000_ck: virt_19200000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <19200000>; }; virt_26000000_ck: virt_26000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <26000000>; }; virt_38_4m_ck: virt_38_4m_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <38400000>; }; dpll4_ck: dpll4_ck@d00 { #clock-cells = <0>; compatible = "ti,omap3-dpll-per-clock"; clocks = <&sys_ck>, <&sys_ck>; reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; }; dpll4_m2_ck: dpll4_m2_ck@d48 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll4_ck>; ti,max-div = <63>; reg = <0x0d48>; ti,index-starts-at-one; }; dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll4_m2_ck>; clock-mult = <2>; clock-div = <1>; }; dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll4_m2x2_mul_ck>; ti,bit-shift = <0x1b>; reg = <0x0d00>; ti,set-bit-to-disable; }; omap_96m_alwon_fck: omap_96m_alwon_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll4_m2x2_ck>; clock-mult = <1>; clock-div = <1>; }; dpll3_ck: dpll3_ck@d00 { #clock-cells = <0>; compatible = "ti,omap3-dpll-core-clock"; clocks = <&sys_ck>, <&sys_ck>; reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>; }; dpll3_m3_ck: dpll3_m3_ck@1140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll3_ck>; ti,bit-shift = <16>; ti,max-div = <31>; reg = <0x1140>; ti,index-starts-at-one; }; dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll3_m3_ck>; clock-mult = <2>; clock-div = <1>; }; dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll3_m3x2_mul_ck>; ti,bit-shift = <0xc>; reg = <0x0d00>; ti,set-bit-to-disable; }; emu_core_alwon_ck: emu_core_alwon_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll3_m3x2_ck>; clock-mult = <1>; clock-div = <1>; }; sys_altclk: sys_altclk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0x0>; }; mcbsp_clks: mcbsp_clks { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0x0>; }; dpll3_m2_ck: dpll3_m2_ck@d40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll3_ck>; ti,bit-shift = <27>; ti,max-div = <31>; reg = <0x0d40>; ti,index-starts-at-one; }; core_ck: core_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll3_m2_ck>; clock-mult = <1>; clock-div = <1>; }; dpll1_fck: dpll1_fck@940 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&core_ck>; ti,bit-shift = <19>; ti,max-div = <7>; reg = <0x0940>; ti,index-starts-at-one; }; dpll1_ck: dpll1_ck@904 { #clock-cells = <0>; compatible = "ti,omap3-dpll-clock"; clocks = <&sys_ck>, <&dpll1_fck>; reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>; }; dpll1_x2_ck: dpll1_x2_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll1_ck>; clock-mult = <2>; clock-div = <1>; }; dpll1_x2m2_ck: dpll1_x2m2_ck@944 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll1_x2_ck>; ti,max-div = <31>; reg = <0x0944>; ti,index-starts-at-one; }; cm_96m_fck: cm_96m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&omap_96m_alwon_fck>; clock-mult = <1>; clock-div = <1>; }; omap_96m_fck: omap_96m_fck@d40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&cm_96m_fck>, <&sys_ck>; ti,bit-shift = <6>; reg = <0x0d40>; }; dpll4_m3_ck: dpll4_m3_ck@e40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll4_ck>; ti,bit-shift = <8>; ti,max-div = <32>; reg = <0x0e40>; ti,index-starts-at-one; }; dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll4_m3_ck>; clock-mult = <2>; clock-div = <1>; }; dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll4_m3x2_mul_ck>; ti,bit-shift = <0x1c>; reg = <0x0d00>; ti,set-bit-to-disable; }; omap_54m_fck: omap_54m_fck@d40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; ti,bit-shift = <5>; reg = <0x0d40>; }; cm_96m_d2_fck: cm_96m_d2_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&cm_96m_fck>; clock-mult = <1>; clock-div = <2>; }; omap_48m_fck: omap_48m_fck@d40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&cm_96m_d2_fck>, <&sys_altclk>; ti,bit-shift = <3>; reg = <0x0d40>; }; omap_12m_fck: omap_12m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&omap_48m_fck>; clock-mult = <1>; clock-div = <4>; }; dpll4_m4_ck: dpll4_m4_ck@e40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll4_ck>; - ti,max-div = <16>; + ti,max-div = <32>; reg = <0x0e40>; ti,index-starts-at-one; }; dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; clocks = <&dpll4_m4_ck>; ti,clock-mult = <2>; ti,clock-div = <1>; ti,set-rate-parent; }; dpll4_m4x2_ck: dpll4_m4x2_ck@d00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll4_m4x2_mul_ck>; ti,bit-shift = <0x1d>; reg = <0x0d00>; ti,set-bit-to-disable; ti,set-rate-parent; }; dpll4_m5_ck: dpll4_m5_ck@f40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll4_ck>; ti,max-div = <63>; reg = <0x0f40>; ti,index-starts-at-one; }; dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; clocks = <&dpll4_m5_ck>; ti,clock-mult = <2>; ti,clock-div = <1>; ti,set-rate-parent; }; dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll4_m5x2_mul_ck>; ti,bit-shift = <0x1e>; reg = <0x0d00>; ti,set-bit-to-disable; ti,set-rate-parent; }; dpll4_m6_ck: dpll4_m6_ck@1140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll4_ck>; ti,bit-shift = <24>; ti,max-div = <63>; reg = <0x1140>; ti,index-starts-at-one; }; dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll4_m6_ck>; clock-mult = <2>; clock-div = <1>; }; dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll4_m6x2_mul_ck>; ti,bit-shift = <0x1f>; reg = <0x0d00>; ti,set-bit-to-disable; }; emu_per_alwon_ck: emu_per_alwon_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll4_m6x2_ck>; clock-mult = <1>; clock-div = <1>; }; clkout2_src_gate_ck: clkout2_src_gate_ck@d70 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&core_ck>; ti,bit-shift = <7>; reg = <0x0d70>; }; clkout2_src_mux_ck: clkout2_src_mux_ck@d70 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; reg = <0x0d70>; }; clkout2_src_ck: clkout2_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>; }; sys_clkout2: sys_clkout2@d70 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&clkout2_src_ck>; ti,bit-shift = <3>; ti,max-div = <64>; reg = <0x0d70>; ti,index-power-of-two; }; mpu_ck: mpu_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll1_x2m2_ck>; clock-mult = <1>; clock-div = <1>; }; arm_fck: arm_fck@924 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mpu_ck>; reg = <0x0924>; ti,max-div = <2>; }; emu_mpu_alwon_ck: emu_mpu_alwon_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&mpu_ck>; clock-mult = <1>; clock-div = <1>; }; l3_ick: l3_ick@a40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&core_ck>; ti,max-div = <3>; reg = <0x0a40>; ti,index-starts-at-one; }; l4_ick: l4_ick@a40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&l3_ick>; ti,bit-shift = <2>; ti,max-div = <3>; reg = <0x0a40>; ti,index-starts-at-one; }; rm_ick: rm_ick@c40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&l4_ick>; ti,bit-shift = <1>; ti,max-div = <3>; reg = <0x0c40>; ti,index-starts-at-one; }; gpt10_gate_fck: gpt10_gate_fck@a00 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; ti,bit-shift = <11>; reg = <0x0a00>; }; gpt10_mux_fck: gpt10_mux_fck@a40 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; ti,bit-shift = <6>; reg = <0x0a40>; }; gpt10_fck: gpt10_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; }; gpt11_gate_fck: gpt11_gate_fck@a00 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; ti,bit-shift = <12>; reg = <0x0a00>; }; gpt11_mux_fck: gpt11_mux_fck@a40 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; ti,bit-shift = <7>; reg = <0x0a40>; }; gpt11_fck: gpt11_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; }; core_96m_fck: core_96m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&omap_96m_fck>; clock-mult = <1>; clock-div = <1>; }; mmchs2_fck: mmchs2_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_96m_fck>; reg = <0x0a00>; ti,bit-shift = <25>; }; mmchs1_fck: mmchs1_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_96m_fck>; reg = <0x0a00>; ti,bit-shift = <24>; }; i2c3_fck: i2c3_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_96m_fck>; reg = <0x0a00>; ti,bit-shift = <17>; }; i2c2_fck: i2c2_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_96m_fck>; reg = <0x0a00>; ti,bit-shift = <16>; }; i2c1_fck: i2c1_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_96m_fck>; reg = <0x0a00>; ti,bit-shift = <15>; }; mcbsp5_gate_fck: mcbsp5_gate_fck@a00 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&mcbsp_clks>; ti,bit-shift = <10>; reg = <0x0a00>; }; mcbsp1_gate_fck: mcbsp1_gate_fck@a00 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&mcbsp_clks>; ti,bit-shift = <9>; reg = <0x0a00>; }; core_48m_fck: core_48m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&omap_48m_fck>; clock-mult = <1>; clock-div = <1>; }; mcspi4_fck: mcspi4_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_48m_fck>; reg = <0x0a00>; ti,bit-shift = <21>; }; mcspi3_fck: mcspi3_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_48m_fck>; reg = <0x0a00>; ti,bit-shift = <20>; }; mcspi2_fck: mcspi2_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_48m_fck>; reg = <0x0a00>; ti,bit-shift = <19>; }; mcspi1_fck: mcspi1_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_48m_fck>; reg = <0x0a00>; ti,bit-shift = <18>; }; uart2_fck: uart2_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_48m_fck>; reg = <0x0a00>; ti,bit-shift = <14>; }; uart1_fck: uart1_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_48m_fck>; reg = <0x0a00>; ti,bit-shift = <13>; }; core_12m_fck: core_12m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&omap_12m_fck>; clock-mult = <1>; clock-div = <1>; }; hdq_fck: hdq_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_12m_fck>; reg = <0x0a00>; ti,bit-shift = <22>; }; core_l3_ick: core_l3_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&l3_ick>; clock-mult = <1>; clock-div = <1>; }; sdrc_ick: sdrc_ick@a10 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_l3_ick>; reg = <0x0a10>; ti,bit-shift = <1>; }; gpmc_fck: gpmc_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&core_l3_ick>; clock-mult = <1>; clock-div = <1>; }; core_l4_ick: core_l4_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&l4_ick>; clock-mult = <1>; clock-div = <1>; }; mmchs2_ick: mmchs2_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <25>; }; mmchs1_ick: mmchs1_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <24>; }; hdq_ick: hdq_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <22>; }; mcspi4_ick: mcspi4_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <21>; }; mcspi3_ick: mcspi3_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <20>; }; mcspi2_ick: mcspi2_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <19>; }; mcspi1_ick: mcspi1_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <18>; }; i2c3_ick: i2c3_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <17>; }; i2c2_ick: i2c2_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <16>; }; i2c1_ick: i2c1_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <15>; }; uart2_ick: uart2_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <14>; }; uart1_ick: uart1_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <13>; }; gpt11_ick: gpt11_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <12>; }; gpt10_ick: gpt10_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <11>; }; mcbsp5_ick: mcbsp5_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <10>; }; mcbsp1_ick: mcbsp1_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <9>; }; omapctrl_ick: omapctrl_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <6>; }; dss_tv_fck: dss_tv_fck@e00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&omap_54m_fck>; reg = <0x0e00>; ti,bit-shift = <2>; }; dss_96m_fck: dss_96m_fck@e00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&omap_96m_fck>; reg = <0x0e00>; ti,bit-shift = <2>; }; dss2_alwon_fck: dss2_alwon_fck@e00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_ck>; reg = <0x0e00>; ti,bit-shift = <1>; }; dummy_ck: dummy_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; gpt1_gate_fck: gpt1_gate_fck@c00 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; ti,bit-shift = <0>; reg = <0x0c00>; }; gpt1_mux_fck: gpt1_mux_fck@c40 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; reg = <0x0c40>; }; gpt1_fck: gpt1_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; }; aes2_ick: aes2_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; ti,bit-shift = <28>; reg = <0x0a10>; }; wkup_32k_fck: wkup_32k_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&omap_32k_fck>; clock-mult = <1>; clock-div = <1>; }; gpio1_dbck: gpio1_dbck@c00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&wkup_32k_fck>; reg = <0x0c00>; ti,bit-shift = <3>; }; sha12_ick: sha12_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; reg = <0x0a10>; ti,bit-shift = <27>; }; wdt2_fck: wdt2_fck@c00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&wkup_32k_fck>; reg = <0x0c00>; ti,bit-shift = <5>; }; wdt2_ick: wdt2_ick@c10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&wkup_l4_ick>; reg = <0x0c10>; ti,bit-shift = <5>; }; wdt1_ick: wdt1_ick@c10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&wkup_l4_ick>; reg = <0x0c10>; ti,bit-shift = <4>; }; gpio1_ick: gpio1_ick@c10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&wkup_l4_ick>; reg = <0x0c10>; ti,bit-shift = <3>; }; omap_32ksync_ick: omap_32ksync_ick@c10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&wkup_l4_ick>; reg = <0x0c10>; ti,bit-shift = <2>; }; gpt12_ick: gpt12_ick@c10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&wkup_l4_ick>; reg = <0x0c10>; ti,bit-shift = <1>; }; gpt1_ick: gpt1_ick@c10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&wkup_l4_ick>; reg = <0x0c10>; ti,bit-shift = <0>; }; per_96m_fck: per_96m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&omap_96m_alwon_fck>; clock-mult = <1>; clock-div = <1>; }; per_48m_fck: per_48m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&omap_48m_fck>; clock-mult = <1>; clock-div = <1>; }; uart3_fck: uart3_fck@1000 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&per_48m_fck>; reg = <0x1000>; ti,bit-shift = <11>; }; gpt2_gate_fck: gpt2_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; ti,bit-shift = <3>; reg = <0x1000>; }; gpt2_mux_fck: gpt2_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; reg = <0x1040>; }; gpt2_fck: gpt2_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; }; gpt3_gate_fck: gpt3_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; ti,bit-shift = <4>; reg = <0x1000>; }; gpt3_mux_fck: gpt3_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; ti,bit-shift = <1>; reg = <0x1040>; }; gpt3_fck: gpt3_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; }; gpt4_gate_fck: gpt4_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; ti,bit-shift = <5>; reg = <0x1000>; }; gpt4_mux_fck: gpt4_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; ti,bit-shift = <2>; reg = <0x1040>; }; gpt4_fck: gpt4_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; }; gpt5_gate_fck: gpt5_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; ti,bit-shift = <6>; reg = <0x1000>; }; gpt5_mux_fck: gpt5_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; ti,bit-shift = <3>; reg = <0x1040>; }; gpt5_fck: gpt5_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; }; gpt6_gate_fck: gpt6_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; ti,bit-shift = <7>; reg = <0x1000>; }; gpt6_mux_fck: gpt6_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; ti,bit-shift = <4>; reg = <0x1040>; }; gpt6_fck: gpt6_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; }; gpt7_gate_fck: gpt7_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; ti,bit-shift = <8>; reg = <0x1000>; }; gpt7_mux_fck: gpt7_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; ti,bit-shift = <5>; reg = <0x1040>; }; gpt7_fck: gpt7_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; }; gpt8_gate_fck: gpt8_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; ti,bit-shift = <9>; reg = <0x1000>; }; gpt8_mux_fck: gpt8_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; ti,bit-shift = <6>; reg = <0x1040>; }; gpt8_fck: gpt8_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; }; gpt9_gate_fck: gpt9_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; ti,bit-shift = <10>; reg = <0x1000>; }; gpt9_mux_fck: gpt9_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; ti,bit-shift = <7>; reg = <0x1040>; }; gpt9_fck: gpt9_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; }; per_32k_alwon_fck: per_32k_alwon_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&omap_32k_fck>; clock-mult = <1>; clock-div = <1>; }; gpio6_dbck: gpio6_dbck@1000 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&per_32k_alwon_fck>; reg = <0x1000>; ti,bit-shift = <17>; }; gpio5_dbck: gpio5_dbck@1000 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&per_32k_alwon_fck>; reg = <0x1000>; ti,bit-shift = <16>; }; gpio4_dbck: gpio4_dbck@1000 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&per_32k_alwon_fck>; reg = <0x1000>; ti,bit-shift = <15>; }; gpio3_dbck: gpio3_dbck@1000 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&per_32k_alwon_fck>; reg = <0x1000>; ti,bit-shift = <14>; }; gpio2_dbck: gpio2_dbck@1000 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&per_32k_alwon_fck>; reg = <0x1000>; ti,bit-shift = <13>; }; wdt3_fck: wdt3_fck@1000 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&per_32k_alwon_fck>; reg = <0x1000>; ti,bit-shift = <12>; }; per_l4_ick: per_l4_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&l4_ick>; clock-mult = <1>; clock-div = <1>; }; gpio6_ick: gpio6_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <17>; }; gpio5_ick: gpio5_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <16>; }; gpio4_ick: gpio4_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <15>; }; gpio3_ick: gpio3_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <14>; }; gpio2_ick: gpio2_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <13>; }; wdt3_ick: wdt3_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <12>; }; uart3_ick: uart3_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <11>; }; uart4_ick: uart4_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <18>; }; gpt9_ick: gpt9_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <10>; }; gpt8_ick: gpt8_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <9>; }; gpt7_ick: gpt7_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <8>; }; gpt6_ick: gpt6_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <7>; }; gpt5_ick: gpt5_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <6>; }; gpt4_ick: gpt4_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <5>; }; gpt3_ick: gpt3_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <4>; }; gpt2_ick: gpt2_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <3>; }; mcbsp2_ick: mcbsp2_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <0>; }; mcbsp3_ick: mcbsp3_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <1>; }; mcbsp4_ick: mcbsp4_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; reg = <0x1010>; ti,bit-shift = <2>; }; mcbsp2_gate_fck: mcbsp2_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&mcbsp_clks>; ti,bit-shift = <0>; reg = <0x1000>; }; mcbsp3_gate_fck: mcbsp3_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&mcbsp_clks>; ti,bit-shift = <1>; reg = <0x1000>; }; mcbsp4_gate_fck: mcbsp4_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&mcbsp_clks>; ti,bit-shift = <2>; reg = <0x1000>; }; emu_src_mux_ck: emu_src_mux_ck@1140 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; reg = <0x1140>; }; emu_src_ck: emu_src_ck { #clock-cells = <0>; compatible = "ti,clkdm-gate-clock"; clocks = <&emu_src_mux_ck>; }; pclk_fck: pclk_fck@1140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&emu_src_ck>; ti,bit-shift = <8>; ti,max-div = <7>; reg = <0x1140>; ti,index-starts-at-one; }; pclkx2_fck: pclkx2_fck@1140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&emu_src_ck>; ti,bit-shift = <6>; ti,max-div = <3>; reg = <0x1140>; ti,index-starts-at-one; }; atclk_fck: atclk_fck@1140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&emu_src_ck>; ti,bit-shift = <4>; ti,max-div = <3>; reg = <0x1140>; ti,index-starts-at-one; }; traceclk_src_fck: traceclk_src_fck@1140 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; ti,bit-shift = <2>; reg = <0x1140>; }; traceclk_fck: traceclk_fck@1140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&traceclk_src_fck>; ti,bit-shift = <11>; ti,max-div = <7>; reg = <0x1140>; ti,index-starts-at-one; }; secure_32k_fck: secure_32k_fck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; gpt12_fck: gpt12_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&secure_32k_fck>; clock-mult = <1>; clock-div = <1>; }; wdt1_fck: wdt1_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&secure_32k_fck>; clock-mult = <1>; clock-div = <1>; }; }; &cm_clockdomains { core_l3_clkdm: core_l3_clkdm { compatible = "ti,clockdomain"; clocks = <&sdrc_ick>; }; dpll3_clkdm: dpll3_clkdm { compatible = "ti,clockdomain"; clocks = <&dpll3_ck>; }; dpll1_clkdm: dpll1_clkdm { compatible = "ti,clockdomain"; clocks = <&dpll1_ck>; }; per_clkdm: per_clkdm { compatible = "ti,clockdomain"; clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, <&mcbsp4_ick>; }; emu_clkdm: emu_clkdm { compatible = "ti,clockdomain"; clocks = <&emu_src_ck>; }; dpll4_clkdm: dpll4_clkdm { compatible = "ti,clockdomain"; clocks = <&dpll4_ck>; }; wkup_clkdm: wkup_clkdm { compatible = "ti,clockdomain"; clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, <&gpt1_ick>; }; dss_clkdm: dss_clkdm { compatible = "ti,clockdomain"; clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>; }; core_l4_clkdm: core_l4_clkdm { compatible = "ti,clockdomain"; clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>; }; }; diff --git a/sys/gnu/dts/arm/omap4-droid-bionic-xt875.dts b/sys/gnu/dts/arm/omap4-droid-bionic-xt875.dts index ba5c35b7027d..e69de29bb2d1 100644 --- a/sys/gnu/dts/arm/omap4-droid-bionic-xt875.dts +++ b/sys/gnu/dts/arm/omap4-droid-bionic-xt875.dts @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include "motorola-mapphone-common.dtsi" - -/ { - model = "Motorola Droid Bionic XT875"; - compatible = "motorola,droid-bionic", "ti,omap4430", "ti,omap4"; -}; diff --git a/sys/gnu/dts/arm/omap4-droid4-xt894.dts b/sys/gnu/dts/arm/omap4-droid4-xt894.dts index c0d2fd92aea3..a40fe8d49da6 100644 --- a/sys/gnu/dts/arm/omap4-droid4-xt894.dts +++ b/sys/gnu/dts/arm/omap4-droid4-xt894.dts @@ -1,9 +1,784 @@ // SPDX-License-Identifier: GPL-2.0-only /dts-v1/; -#include "motorola-mapphone-common.dtsi" +#include +#include "omap443x.dtsi" +#include "motorola-cpcap-mapphone.dtsi" / { model = "Motorola Droid 4 XT894"; compatible = "motorola,droid4", "ti,omap4430", "ti,omap4"; + + chosen { + stdout-path = &uart3; + }; + + aliases { + display0 = &lcd0; + display1 = &hdmi0; + }; + + /* + * We seem to have only 1021 MB accessible, 1021 - 1022 is locked, + * then 1023 - 1024 seems to contain mbm. + */ + memory { + device_type = "memory"; + reg = <0x80000000 0x3fd00000>; /* 1021 MB */ + }; + + /* Poweroff GPIO probably connected to CPCAP */ + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&poweroff_gpio>; + pinctrl-names = "default"; + gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; /* gpio50 */ + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + pinctrl-0 = <&hdmi_hpd_gpio>; + pinctrl-names = "default"; + label = "hdmi"; + type = "d"; + + hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio63 */ + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + }; + + /* + * HDMI 5V regulator probably sourced from battery. Let's keep + * keep this as always enabled for HDMI to work until we've + * figured what the encoder chip is. + */ + hdmi_regulator: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "hdmi"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio59 */ + enable-active-high; + regulator-always-on; + }; + + /* FS USB Host PHY on port 1 for mdm6600 */ + fsusb1_phy: usb-phy@1 { + compatible = "motorola,mapphone-mdm6600"; + pinctrl-0 = <&usb_mdm6600_pins>; + pinctrl-names = "default"; + enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; /* gpio_95 */ + power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54 */ + reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; /* gpio_49 */ + /* mode: gpio_148 gpio_149 */ + motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>, + <&gpio5 21 GPIO_ACTIVE_HIGH>; + /* cmd: gpio_103 gpio_104 gpio_142 */ + motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>, + <&gpio4 8 GPIO_ACTIVE_HIGH>, + <&gpio5 14 GPIO_ACTIVE_HIGH>; + /* status: gpio_52 gpio_53 gpio_55 */ + motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>, + <&gpio2 21 GPIO_ACTIVE_HIGH>, + <&gpio2 23 GPIO_ACTIVE_HIGH>; + #phy-cells = <0>; + }; + + /* HS USB host TLL nop-phy on port 2 for w3glte */ + hsusb2_phy: usb-phy@2 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + /* LCD regulator from sw5 source */ + lcd_regulator: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "lcd"; + regulator-min-microvolt = <5050000>; + regulator-max-microvolt = <5050000>; + gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; /* gpio96 */ + enable-active-high; + vin-supply = <&sw5>; + }; + + /* This is probably coming straight from the battery.. */ + wl12xx_vmmc: regulator-wl12xx { + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; /* gpio94 */ + startup-delay-us = <70000>; + enable-active-high; + }; + + gpio_keys { + compatible = "gpio-keys"; + + volume_down { + label = "Volume Down"; + gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */ + linux,code = ; + linux,can-disable; + /* Value above 7.95ms for no GPIO hardware debounce */ + debounce-interval = <10>; + }; + + slider { + label = "Keypad Slide"; + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio122 */ + linux,input-type = ; + linux,code = ; + linux,can-disable; + /* Value above 7.95ms for no GPIO hardware debounce */ + debounce-interval = <10>; + }; + }; + + soundcard { + compatible = "audio-graph-card"; + label = "Droid 4 Audio"; + + simple-graph-card,widgets = + "Speaker", "Earpiece", + "Speaker", "Loudspeaker", + "Headphone", "Headphone Jack", + "Microphone", "Internal Mic"; + + simple-graph-card,routing = + "Earpiece", "EP", + "Loudspeaker", "SPKR", + "Headphone Jack", "HSL", + "Headphone Jack", "HSR", + "MICR", "Internal Mic"; + + dais = <&mcbsp2_port>, <&mcbsp3_port>; + }; + + pwm8: dmtimer-pwm-8 { + pinctrl-names = "default"; + pinctrl-0 = <&vibrator_direction_pin>; + + compatible = "ti,omap-dmtimer-pwm"; + #pwm-cells = <3>; + ti,timers = <&timer8>; + ti,clock-source = <0x01>; + }; + + pwm9: dmtimer-pwm-9 { + pinctrl-names = "default"; + pinctrl-0 = <&vibrator_enable_pin>; + + compatible = "ti,omap-dmtimer-pwm"; + #pwm-cells = <3>; + ti,timers = <&timer9>; + ti,clock-source = <0x01>; + }; + + vibrator { + compatible = "pwm-vibrator"; + pwms = <&pwm9 0 10000000 0>, <&pwm8 0 10000000 0>; + pwm-names = "enable", "direction"; + direction-duty-cycle-ns = <10000000>; + }; +}; + +&dss { + status = "okay"; +}; + +&dsi1 { + status = "okay"; + vdd-supply = <&vcsi>; + + port { + dsi1_out_ep: endpoint { + remote-endpoint = <&lcd0_in>; + lanes = <0 1 2 3 4 5>; + }; + }; + + lcd0: display { + compatible = "panel-dsi-cm"; + label = "lcd0"; + vddi-supply = <&lcd_regulator>; + reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ + + width-mm = <50>; + height-mm = <89>; + + panel-timing { + clock-frequency = <0>; /* Calculated by dsi */ + + hback-porch = <2>; + hactive = <540>; + hfront-porch = <0>; + hsync-len = <2>; + + vback-porch = <1>; + vactive = <960>; + vfront-porch = <0>; + vsync-len = <1>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd0_in: endpoint { + remote-endpoint = <&dsi1_out_ep>; + }; + }; + }; +}; + +&hdmi { + status = "okay"; + pinctrl-0 = <&dss_hdmi_pins>; + pinctrl-names = "default"; + vdda-supply = <&vdac>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + lanes = <1 0 3 2 5 4 7 6>; + }; + }; +}; + +&i2c1 { + tmp105@48 { + compatible = "ti,tmp105"; + reg = <0x48>; + pinctrl-0 = <&tmp105_irq>; + pinctrl-names = "default"; + /* kpd_row0.gpio_178 */ + interrupts-extended = <&gpio6 18 IRQ_TYPE_EDGE_FALLING + &omap4_pmx_core 0x14e>; + interrupt-names = "irq", "wakeup"; + wakeup-source; + }; +}; + +&keypad { + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = < + + /* Row 1 */ + MATRIX_KEY(0, 2, KEY_1) + MATRIX_KEY(0, 6, KEY_2) + MATRIX_KEY(2, 3, KEY_3) + MATRIX_KEY(0, 7, KEY_4) + MATRIX_KEY(0, 4, KEY_5) + MATRIX_KEY(5, 5, KEY_6) + MATRIX_KEY(0, 1, KEY_7) + MATRIX_KEY(0, 5, KEY_8) + MATRIX_KEY(0, 0, KEY_9) + MATRIX_KEY(1, 6, KEY_0) + + /* Row 2 */ + MATRIX_KEY(3, 4, KEY_APOSTROPHE) + MATRIX_KEY(7, 6, KEY_Q) + MATRIX_KEY(7, 7, KEY_W) + MATRIX_KEY(7, 2, KEY_E) + MATRIX_KEY(1, 0, KEY_R) + MATRIX_KEY(4, 4, KEY_T) + MATRIX_KEY(1, 2, KEY_Y) + MATRIX_KEY(6, 7, KEY_U) + MATRIX_KEY(2, 2, KEY_I) + MATRIX_KEY(5, 6, KEY_O) + MATRIX_KEY(3, 7, KEY_P) + MATRIX_KEY(6, 5, KEY_BACKSPACE) + + /* Row 3 */ + MATRIX_KEY(5, 4, KEY_TAB) + MATRIX_KEY(5, 7, KEY_A) + MATRIX_KEY(2, 7, KEY_S) + MATRIX_KEY(7, 0, KEY_D) + MATRIX_KEY(2, 6, KEY_F) + MATRIX_KEY(6, 2, KEY_G) + MATRIX_KEY(6, 6, KEY_H) + MATRIX_KEY(1, 4, KEY_J) + MATRIX_KEY(3, 1, KEY_K) + MATRIX_KEY(2, 1, KEY_L) + MATRIX_KEY(4, 6, KEY_ENTER) + + /* Row 4 */ + MATRIX_KEY(3, 6, KEY_LEFTSHIFT) /* KEY_CAPSLOCK */ + MATRIX_KEY(6, 1, KEY_Z) + MATRIX_KEY(7, 4, KEY_X) + MATRIX_KEY(5, 1, KEY_C) + MATRIX_KEY(1, 7, KEY_V) + MATRIX_KEY(2, 4, KEY_B) + MATRIX_KEY(4, 1, KEY_N) + MATRIX_KEY(1, 1, KEY_M) + MATRIX_KEY(3, 5, KEY_COMMA) + MATRIX_KEY(5, 2, KEY_DOT) + MATRIX_KEY(6, 3, KEY_UP) + MATRIX_KEY(7, 3, KEY_OK) + + /* Row 5 */ + MATRIX_KEY(2, 5, KEY_LEFTCTRL) /* KEY_LEFTSHIFT */ + MATRIX_KEY(4, 5, KEY_LEFTALT) /* SYM */ + MATRIX_KEY(6, 0, KEY_MINUS) + MATRIX_KEY(4, 7, KEY_EQUAL) + MATRIX_KEY(1, 5, KEY_SPACE) + MATRIX_KEY(3, 2, KEY_SLASH) + MATRIX_KEY(4, 3, KEY_LEFT) + MATRIX_KEY(5, 3, KEY_DOWN) + MATRIX_KEY(3, 3, KEY_RIGHT) + + /* Side buttons, KEY_VOLUMEDOWN and KEY_PWER are on CPCAP? */ + MATRIX_KEY(5, 0, KEY_VOLUMEUP) + >; +}; + +&mmc1 { + vmmc-supply = <&vwlan2>; + bus-width = <4>; + cd-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* gpio176 */ +}; + +&mmc2 { + vmmc-supply = <&vsdio>; + bus-width = <8>; + ti,non-removable; +}; + +&mmc3 { + vmmc-supply = <&wl12xx_vmmc>; + /* uart2_tx.sdmmc3_dat1 pad as wakeirq */ + interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core 0xde>; + interrupt-names = "irq", "wakeup"; + non-removable; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1285", "ti,wl1283"; + reg = <2>; + /* gpio_100 with gpmc_wait2 pad as wakeirq */ + interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>, + <&omap4_pmx_core 0x4e>; + interrupt-names = "irq", "wakeup"; + ref-clock-frequency = <26000000>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&i2c1 { + led-controller@38 { + compatible = "ti,lm3532"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x38>; + + enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + + ramp-up-us = <1024>; + ramp-down-us = <8193>; + + led@0 { + reg = <0>; + led-sources = <2>; + ti,led-mode = <0>; + label = ":backlight"; + linux,default-trigger = "backlight"; + }; + + led@1 { + reg = <1>; + led-sources = <1>; + ti,led-mode = <0>; + label = ":kbd_backlight"; + }; + }; +}; + +&i2c2 { + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + + reset-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio173 */ + + /* gpio_183 with sys_nirq2 pad as wakeup */ + interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_FALLING>, + <&omap4_pmx_core 0x160>; + interrupt-names = "irq", "wakeup"; + wakeup-source; + }; + + isl29030@44 { + compatible = "isil,isl29030"; + reg = <0x44>; + + pinctrl-names = "default"; + pinctrl-0 = <&als_proximity_pins>; + + interrupt-parent = <&gpio6>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; /* gpio177 */ + }; +}; + +&omap4_pmx_core { + + /* hdmi_hpd.gpio_63 */ + hdmi_hpd_gpio: pinmux_hdmi_hpd_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) + >; + }; + + /* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */ + dss_hdmi_pins: pinmux_dss_hdmi_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) + OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) + OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) + >; + }; + + /* gpmc_ncs0.gpio_50 */ + poweroff_gpio: pinmux_poweroff_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x074, PIN_OUTPUT_PULLUP | MUX_MODE3) + >; + }; + + /* kpd_row0.gpio_178 */ + tmp105_irq: pinmux_tmp105_irq { + pinctrl-single,pins = < + OMAP4_IOPAD(0x18e, PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; + + usb_gpio_mux_sel1: pinmux_usb_gpio_mux_sel1_pins { + /* gpio_60 */ + pinctrl-single,pins = < + OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) + >; + }; + + touchscreen_pins: pinmux_touchscreen_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) + OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; + + als_proximity_pins: pinmux_als_proximity_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; + + usb_mdm6600_pins: pinmux_usb_mdm6600_pins { + pinctrl-single,pins = < + /* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */ + OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3) + + /* power 0x4a10007c gpmc_nwp.gpio_54 c25 */ + OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) + + /* reset 0x4a100072 gpmc_a25.gpio_49 d20 */ + OMAP4_IOPAD(0x072, PIN_OUTPUT | MUX_MODE3) + + /* mode0/bpwake 0x4a10014e sdmmc5_dat1.gpio_148 af4 */ + OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3) + + /* mode1/apwake 0x4a100150 sdmmc5_dat2.gpio_149 ag3 */ + OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3) + + /* status0 0x4a10007e gpmc_clk.gpio_55 b22 */ + OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3) + + /* status1 0x4a10007a gpmc_ncs3.gpio_53 c22 */ + OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) + + /* status2 0x4a100078 gpmc_ncs2.gpio_52 d21 */ + OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) + + /* cmd0 0x4a100094 gpmc_ncs6.gpio_103 c24 */ + OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3) + + /* cmd1 0x4a100096 gpmc_ncs7.gpio_104 d24 */ + OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3) + + /* cmd2 0x4a100142 uart3_rts_sd.gpio_142 f28 */ + OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3) + >; + }; + + usb_ulpi_pins: pinmux_usb_ulpi_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x196, MUX_MODE7) + OMAP4_IOPAD(0x198, MUX_MODE7) + OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE0) + >; + }; + + /* usb0_otg_dp and usb0_otg_dm */ + usb_utmi_pins: pinmux_usb_utmi_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) + OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) + OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) + >; + }; + + /* + * Note that the v3.0.8 stock userspace dynamically remuxes uart1 + * rts pin probably for PM purposes to PIN_INPUT_PULLUP | MUX_MODE7 + * when not used. If needed, we can add rts pin remux later based + * on power measurements. + */ + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + /* 0x4a10013c mcspi1_cs2.uart1_cts ag23 */ + OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) + + /* 0x4a10013e mcspi1_cs3.uart1_rts ah23 */ + OMAP4_IOPAD(0x13e, MUX_MODE1) + + /* 0x4a100140 uart3_cts_rctx.uart1_tx f27 */ + OMAP4_IOPAD(0x140, PIN_OUTPUT | MUX_MODE1) + + /* 0x4a1001ca dpm_emu14.uart1_rx aa3 */ + OMAP4_IOPAD(0x1ca, PIN_INPUT_PULLUP | MUX_MODE2) + >; + }; + + /* uart3_tx_irtx and uart3_rx_irrx */ + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x196, MUX_MODE7) + OMAP4_IOPAD(0x198, MUX_MODE7) + OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1ba, MUX_MODE2) + OMAP4_IOPAD(0x1bc, PIN_INPUT | MUX_MODE2) + OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) + >; + }; + + uart4_pins: pinmux_uart4_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx */ + OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx */ + OMAP4_IOPAD(0x110, PIN_INPUT_PULLUP | MUX_MODE5) /* uart4_cts */ + OMAP4_IOPAD(0x112, PIN_OUTPUT_PULLUP | MUX_MODE5) /* uart4_rts */ + >; + }; + + mcbsp2_pins: pinmux_mcbsp2_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx */ + OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_dr */ + OMAP4_IOPAD(0x0fa, PIN_OUTPUT | MUX_MODE0) /* abe_mcbsp2_dx */ + OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx */ + >; + }; + + mcbsp3_pins: pinmux_mcbsp3_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x106, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_dr */ + OMAP4_IOPAD(0x108, PIN_OUTPUT | MUX_MODE1) /* abe_mcbsp3_dx */ + OMAP4_IOPAD(0x10a, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_clkx */ + OMAP4_IOPAD(0x10c, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_fsx */ + >; + }; + + vibrator_direction_pin: pinmux_vibrator_direction_pin { + pinctrl-single,pins = < + OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */ + >; + }; + + vibrator_enable_pin: pinmux_vibrator_enable_pin { + pinctrl-single,pins = < + OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */ + >; + }; +}; + +&omap4_pmx_wkup { + usb_gpio_mux_sel2: pinmux_usb_gpio_mux_sel2_pins { + /* gpio_wk0 */ + pinctrl-single,pins = < + OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3) + >; + }; +}; + +/* Configure pwm clock source for timers 8 & 9 */ +&timer8 { + assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>; + assigned-clock-parents = <&sys_clkin_ck>; +}; + +&timer9 { + assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>; + assigned-clock-parents = <&sys_clkin_ck>; +}; + +/* + * As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for + * uart1 wakeirq. + */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core 0xfc>; +}; + +&uart3 { + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core 0x17c>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + + bluetooth { + compatible = "ti,wl1285-st"; + enable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; /* gpio 174 */ + max-speed = <3686400>; + }; +}; + +&usbhsohci { + phys = <&fsusb1_phy>; + phy-names = "usb"; +}; + +&usbhsehci { + phys = <&hsusb2_phy>; +}; + +&usbhshost { + port1-mode = "ohci-phy-4pin-dpdm"; + port2-mode = "ehci-tll"; +}; + +/* Internal UTMI+ PHY used for OTG, CPCAP ULPI PHY for detection and charger */ +&usb_otg_hs { + interface-type = <1>; + mode = <3>; + power = <50>; +}; + +&i2c4 { + ak8975: magnetometer@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + + vdd-supply = <&vhvio>; + + interrupt-parent = <&gpio6>; + interrupts = <15 IRQ_TYPE_EDGE_RISING>; /* gpio175 */ + + rotation-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + + }; + + lis3dh: accelerometer@18 { + compatible = "st,lis3dh-accel"; + reg = <0x18>; + + vdd-supply = <&vhvio>; + + interrupt-parent = <&gpio2>; + interrupts = <2 IRQ_TYPE_EDGE_BOTH>; /* gpio34 */ + + rotation-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "1"; + }; +}; + +&mcbsp2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; + status = "okay"; + + mcbsp2_port: port { + cpu_dai2: endpoint { + dai-format = "i2s"; + remote-endpoint = <&cpcap_audio_codec0>; + frame-master = <&cpcap_audio_codec0>; + bitclock-master = <&cpcap_audio_codec0>; + }; + }; +}; + +&mcbsp3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp3_pins>; + status = "okay"; + + mcbsp3_port: port { + cpu_dai3: endpoint { + dai-format = "dsp_a"; + frame-master = <&cpcap_audio_codec1>; + bitclock-master = <&cpcap_audio_codec1>; + remote-endpoint = <&cpcap_audio_codec1>; + }; + }; +}; + +&cpcap_audio_codec0 { + remote-endpoint = <&cpu_dai2>; +}; + +&cpcap_audio_codec1 { + remote-endpoint = <&cpu_dai3>; }; diff --git a/sys/gnu/dts/arm/omap4-l4-abe.dtsi b/sys/gnu/dts/arm/omap4-l4-abe.dtsi index a6feb201c569..8e6662bb9e83 100644 --- a/sys/gnu/dts/arm/omap4-l4-abe.dtsi +++ b/sys/gnu/dts/arm/omap4-l4-abe.dtsi @@ -1,489 +1,500 @@ &l4_abe { /* 0x40100000 */ compatible = "ti,omap4-l4-abe", "simple-bus"; reg = <0x40100000 0x400>, <0x40100400 0x400>; reg-names = "la", "ap"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ <0x49000000 0x49000000 0x100000>; segment@0 { /* 0x40100000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = /* CPU to L4 ABE mapping */ <0x00000000 0x00000000 0x000400>, /* ap 0 */ <0x00000400 0x00000400 0x000400>, /* ap 1 */ <0x00022000 0x00022000 0x001000>, /* ap 2 */ <0x00023000 0x00023000 0x001000>, /* ap 3 */ <0x00024000 0x00024000 0x001000>, /* ap 4 */ <0x00025000 0x00025000 0x001000>, /* ap 5 */ <0x00026000 0x00026000 0x001000>, /* ap 6 */ <0x00027000 0x00027000 0x001000>, /* ap 7 */ <0x00028000 0x00028000 0x001000>, /* ap 8 */ <0x00029000 0x00029000 0x001000>, /* ap 9 */ <0x0002a000 0x0002a000 0x001000>, /* ap 10 */ <0x0002b000 0x0002b000 0x001000>, /* ap 11 */ <0x0002e000 0x0002e000 0x001000>, /* ap 12 */ <0x0002f000 0x0002f000 0x001000>, /* ap 13 */ <0x00030000 0x00030000 0x001000>, /* ap 14 */ <0x00031000 0x00031000 0x001000>, /* ap 15 */ <0x00032000 0x00032000 0x001000>, /* ap 16 */ <0x00033000 0x00033000 0x001000>, /* ap 17 */ <0x00038000 0x00038000 0x001000>, /* ap 18 */ <0x00039000 0x00039000 0x001000>, /* ap 19 */ <0x0003a000 0x0003a000 0x001000>, /* ap 20 */ <0x0003b000 0x0003b000 0x001000>, /* ap 21 */ <0x0003c000 0x0003c000 0x001000>, /* ap 22 */ <0x0003d000 0x0003d000 0x001000>, /* ap 23 */ <0x0003e000 0x0003e000 0x001000>, /* ap 24 */ <0x0003f000 0x0003f000 0x001000>, /* ap 25 */ <0x00080000 0x00080000 0x010000>, /* ap 26 */ <0x00080000 0x00080000 0x001000>, /* ap 27 */ <0x000a0000 0x000a0000 0x010000>, /* ap 28 */ <0x000a0000 0x000a0000 0x001000>, /* ap 29 */ <0x000c0000 0x000c0000 0x010000>, /* ap 30 */ <0x000c0000 0x000c0000 0x001000>, /* ap 31 */ <0x000f1000 0x000f1000 0x001000>, /* ap 32 */ <0x000f2000 0x000f2000 0x001000>, /* ap 33 */ /* L3 to L4 ABE mapping */ <0x49000000 0x49000000 0x000400>, /* ap 0 */ <0x49000400 0x49000400 0x000400>, /* ap 1 */ <0x49022000 0x49022000 0x001000>, /* ap 2 */ <0x49023000 0x49023000 0x001000>, /* ap 3 */ <0x49024000 0x49024000 0x001000>, /* ap 4 */ <0x49025000 0x49025000 0x001000>, /* ap 5 */ <0x49026000 0x49026000 0x001000>, /* ap 6 */ <0x49027000 0x49027000 0x001000>, /* ap 7 */ <0x49028000 0x49028000 0x001000>, /* ap 8 */ <0x49029000 0x49029000 0x001000>, /* ap 9 */ <0x4902a000 0x4902a000 0x001000>, /* ap 10 */ <0x4902b000 0x4902b000 0x001000>, /* ap 11 */ <0x4902e000 0x4902e000 0x001000>, /* ap 12 */ <0x4902f000 0x4902f000 0x001000>, /* ap 13 */ <0x49030000 0x49030000 0x001000>, /* ap 14 */ <0x49031000 0x49031000 0x001000>, /* ap 15 */ <0x49032000 0x49032000 0x001000>, /* ap 16 */ <0x49033000 0x49033000 0x001000>, /* ap 17 */ <0x49038000 0x49038000 0x001000>, /* ap 18 */ <0x49039000 0x49039000 0x001000>, /* ap 19 */ <0x4903a000 0x4903a000 0x001000>, /* ap 20 */ <0x4903b000 0x4903b000 0x001000>, /* ap 21 */ <0x4903c000 0x4903c000 0x001000>, /* ap 22 */ <0x4903d000 0x4903d000 0x001000>, /* ap 23 */ <0x4903e000 0x4903e000 0x001000>, /* ap 24 */ <0x4903f000 0x4903f000 0x001000>, /* ap 25 */ <0x49080000 0x49080000 0x010000>, /* ap 26 */ <0x49080000 0x49080000 0x001000>, /* ap 27 */ <0x490a0000 0x490a0000 0x010000>, /* ap 28 */ <0x490a0000 0x490a0000 0x001000>, /* ap 29 */ <0x490c0000 0x490c0000 0x010000>, /* ap 30 */ <0x490c0000 0x490c0000 0x001000>, /* ap 31 */ <0x490f1000 0x490f1000 0x001000>, /* ap 32 */ <0x490f2000 0x490f2000 0x001000>; /* ap 33 */ target-module@22000 { /* 0x40122000, ap 2 02.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mcbsp1"; reg = <0x2208c 0x4>; reg-names = "sysc"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = , , ; /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x22000 0x1000>, <0x49022000 0x49022000 0x1000>; mcbsp1: mcbsp@0 { compatible = "ti,omap4-mcbsp"; reg = <0x0 0xff>, /* MPU private access */ <0x49022000 0xff>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = ; interrupt-names = "common"; ti,buffer-size = <128>; dmas = <&sdma 33>, <&sdma 34>; dma-names = "tx", "rx"; status = "disabled"; }; }; target-module@24000 { /* 0x40124000, ap 4 04.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mcbsp2"; reg = <0x2408c 0x4>; reg-names = "sysc"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = , , ; /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x24000 0x1000>, <0x49024000 0x49024000 0x1000>; mcbsp2: mcbsp@0 { compatible = "ti,omap4-mcbsp"; reg = <0x0 0xff>, /* MPU private access */ <0x49024000 0xff>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = ; interrupt-names = "common"; ti,buffer-size = <128>; dmas = <&sdma 17>, <&sdma 18>; dma-names = "tx", "rx"; status = "disabled"; }; }; target-module@26000 { /* 0x40126000, ap 6 06.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mcbsp3"; reg = <0x2608c 0x4>; reg-names = "sysc"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = , , ; /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x26000 0x1000>, <0x49026000 0x49026000 0x1000>; mcbsp3: mcbsp@0 { compatible = "ti,omap4-mcbsp"; reg = <0x0 0xff>, /* MPU private access */ <0x49026000 0xff>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = ; interrupt-names = "common"; ti,buffer-size = <128>; dmas = <&sdma 19>, <&sdma 20>; dma-names = "tx", "rx"; status = "disabled"; }; }; target-module@28000 { /* 0x40128000, ap 8 08.0 */ compatible = "ti,sysc-mcasp", "ti,sysc"; + ti,hwmods = "mcasp"; reg = <0x28000 0x4>, <0x28004 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , , ; /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x28000 0x1000>, <0x49028000 0x49028000 0x1000>; /* * Child device unsupported by davinci-mcasp. At least * RX path is disabled for omap4, and only DIT mode * works with no I2S. See also old Android kernel * omap-mcasp driver for more information. */ }; target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2a000 0x1000>, <0x4902a000 0x4902a000 0x1000>; }; target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "dmic"; reg = <0x2e000 0x4>, <0x2e010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2e000 0x1000>, <0x4902e000 0x4902e000 0x1000>; dmic: dmic@0 { compatible = "ti,omap4-dmic"; reg = <0x0 0x7f>, /* MPU private access */ <0x4902e000 0x7f>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = ; dmas = <&sdma 67>; dma-names = "up_link"; status = "disabled"; }; }; target-module@30000 { /* 0x40130000, ap 14 0e.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x30000 0x4>, <0x30010 0x4>, <0x30014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x30000 0x1000>, <0x49030000 0x49030000 0x1000>; wdt3: wdt@0 { compatible = "ti,omap4-wdt", "ti,omap3-wdt"; reg = <0x0 0x80>; interrupts = ; }; }; mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcpdm"; reg = <0x32000 0x4>, <0x32010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x32000 0x1000>, <0x49032000 0x49032000 0x1000>; /* Must be only enabled for boards with pdmclk wired */ status = "disabled"; mcpdm: mcpdm@0 { compatible = "ti,omap4-mcpdm"; reg = <0x0 0x7f>, /* MPU private access */ <0x49032000 0x7f>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = ; dmas = <&sdma 65>, <&sdma 66>; dma-names = "up_link", "dn_link"; }; }; target-module@38000 { /* 0x40138000, ap 18 12.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer5"; reg = <0x38000 0x4>, <0x38010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x38000 0x1000>, <0x49038000 0x49038000 0x1000>; timer5: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x00000000 0x80>, <0x49038000 0x80>; clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>; clock-names = "fck"; interrupts = ; ti,timer-dsp; }; }; target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer6"; reg = <0x3a000 0x4>, <0x3a010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3a000 0x1000>, <0x4903a000 0x4903a000 0x1000>; timer6: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x00000000 0x80>, <0x4903a000 0x80>; clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>; clock-names = "fck"; interrupts = ; ti,timer-dsp; }; }; target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer7"; reg = <0x3c000 0x4>, <0x3c010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3c000 0x1000>, <0x4903c000 0x4903c000 0x1000>; timer7: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x00000000 0x80>, <0x4903c000 0x80>; clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>; clock-names = "fck"; interrupts = ; ti,timer-dsp; }; }; target-module@3e000 { /* 0x4013e000, ap 24 18.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer8"; reg = <0x3e000 0x4>, <0x3e010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3e000 0x1000>, <0x4903e000 0x4903e000 0x1000>; timer8: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x00000000 0x80>, <0x4903e000 0x80>; clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>; clock-names = "fck"; interrupts = ; ti,timer-pwm; ti,timer-dsp; }; }; target-module@80000 { /* 0x40180000, ap 26 1a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000 0x10000>, <0x49080000 0x49080000 0x10000>; }; target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa0000 0x10000>, <0x490a0000 0x490a0000 0x10000>; }; target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc0000 0x10000>, <0x490c0000 0x490c0000 0x10000>; }; target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "aess"; reg = <0xf1000 0x4>, <0xf1010 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = , , , ; ti,sysc-sidle = , , ; /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xf1000 0x1000>, <0x490f1000 0x490f1000 0x1000>; /* * No child device binding or driver in mainline. * See Android tree and related upstreaming efforts * for the old driver. */ }; }; }; diff --git a/sys/gnu/dts/arm/omap4-l4.dtsi b/sys/gnu/dts/arm/omap4-l4.dtsi index 459fd7027591..d60d5e0ecc4c 100644 --- a/sys/gnu/dts/arm/omap4-l4.dtsi +++ b/sys/gnu/dts/arm/omap4-l4.dtsi @@ -1,2473 +1,2456 @@ // SPDX-License-Identifier: GPL-2.0 &l4_cfg { /* 0x4a000000 */ compatible = "ti,omap4-l4-cfg", "simple-bus"; reg = <0x4a000000 0x800>, <0x4a000800 0x800>, <0x4a001000 0x1000>; reg-names = "ap", "la", "ia0"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ <0x00080000 0x4a080000 0x080000>, /* segment 1 */ <0x00100000 0x4a100000 0x080000>, /* segment 2 */ <0x00180000 0x4a180000 0x080000>, /* segment 3 */ <0x00200000 0x4a200000 0x080000>, /* segment 4 */ <0x00280000 0x4a280000 0x080000>, /* segment 5 */ <0x00300000 0x4a300000 0x080000>; /* segment 6 */ segment@0 { /* 0x4a000000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00001000 0x00001000 0x001000>, /* ap 1 */ <0x00000800 0x00000800 0x000800>, /* ap 2 */ <0x00002000 0x00002000 0x001000>, /* ap 3 */ <0x00003000 0x00003000 0x001000>, /* ap 4 */ <0x00004000 0x00004000 0x001000>, /* ap 5 */ <0x00005000 0x00005000 0x001000>, /* ap 6 */ <0x00056000 0x00056000 0x001000>, /* ap 7 */ <0x00057000 0x00057000 0x001000>, /* ap 8 */ <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ <0x00058000 0x00058000 0x004000>, /* ap 10 */ <0x00062000 0x00062000 0x001000>, /* ap 11 */ <0x00063000 0x00063000 0x001000>, /* ap 12 */ <0x00008000 0x00008000 0x002000>, /* ap 23 */ <0x0000a000 0x0000a000 0x001000>, /* ap 24 */ <0x00066000 0x00066000 0x001000>, /* ap 25 */ <0x00067000 0x00067000 0x001000>, /* ap 26 */ <0x0005e000 0x0005e000 0x002000>, /* ap 80 */ <0x00060000 0x00060000 0x001000>, /* ap 81 */ <0x00064000 0x00064000 0x001000>, /* ap 86 */ <0x00065000 0x00065000 0x001000>; /* ap 87 */ target-module@2000 { /* 0x4a002000, ap 3 06.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "ctrl_module_core"; reg = <0x2000 0x4>, <0x2010 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x1000>; omap4_scm_core: scm@0 { compatible = "ti,omap4-scm-core", "simple-bus"; reg = <0x0 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x1000>; scm_conf: scm_conf@0 { compatible = "syscon"; reg = <0x0 0x800>; #address-cells = <1>; #size-cells = <1>; }; omap_control_usb2phy: control-phy@300 { compatible = "ti,control-phy-usb2"; reg = <0x300 0x4>; reg-names = "power"; }; omap_control_usbotg: control-phy@33c { compatible = "ti,control-phy-otghs"; reg = <0x33c 0x4>; reg-names = "otghs_control"; }; }; }; target-module@4000 { /* 0x4a004000, ap 5 02.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x4000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; cm1: cm1@0 { compatible = "ti,omap4-cm1", "simple-bus"; reg = <0x0 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x2000>; cm1_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; cm1_clockdomains: clockdomains { }; }; }; target-module@8000 { /* 0x4a008000, ap 23 32.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x8000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x2000>; cm2: cm2@0 { compatible = "ti,omap4-cm2", "simple-bus"; reg = <0x0 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x2000>; cm2_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; cm2_clockdomains: clockdomains { }; }; }; target-module@56000 { /* 0x4a056000, ap 7 0a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "dma_system"; reg = <0x56000 0x4>, <0x5602c 0x4>, <0x56028 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-midle = , , ; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */ clocks = <&l3_dma_clkctrl OMAP4_DMA_SYSTEM_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x56000 0x1000>; sdma: dma-controller@0 { - compatible = "ti,omap4430-sdma", "ti,omap-sdma"; + compatible = "ti,omap4430-sdma"; reg = <0x0 0x1000>; interrupts = , , , ; #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; }; }; target-module@58000 { /* 0x4a058000, ap 10 0e.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "hsi"; reg = <0x58000 0x4>, <0x58010 0x4>, <0x58014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x58000 0x5000>; hsi: hsi@0 { compatible = "ti,omap4-hsi"; reg = <0x0 0x4000>, <0x5000 0x1000>; reg-names = "sys", "gdd"; clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; clock-names = "hsi_fck"; interrupts = ; interrupt-names = "gdd_mpu"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x4000>; hsi_port1: hsi-port@2000 { compatible = "ti,omap4-hsi-port"; reg = <0x2000 0x800>, <0x2800 0x800>; reg-names = "tx", "rx"; interrupts = ; }; hsi_port2: hsi-port@3000 { compatible = "ti,omap4-hsi-port"; reg = <0x3000 0x800>, <0x3800 0x800>; reg-names = "tx", "rx"; interrupts = ; }; }; }; target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5e000 0x2000>; }; target-module@62000 { /* 0x4a062000, ap 11 16.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "usb_tll_hs"; reg = <0x62000 0x4>, <0x62010 0x4>, <0x62014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x62000 0x1000>; usbhstll: usbhstll@0 { compatible = "ti,usbhs-tll"; reg = <0x0 0x1000>; interrupts = ; }; }; target-module@64000 { /* 0x4a064000, ap 86 1e.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "usb_host_hs"; reg = <0x64000 0x4>, <0x64010 0x4>, <0x64014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = ; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ clocks = <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x64000 0x1000>; usbhshost: usbhshost@0 { compatible = "ti,usbhs-host"; reg = <0x0 0x800>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x1000>; clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>, <&xclk60mhsp2_ck>; clock-names = "refclk_60m_int", "refclk_60m_ext_p1", "refclk_60m_ext_p2"; usbhsohci: ohci@800 { compatible = "ti,ohci-omap3"; reg = <0x800 0x400>; interrupts = ; remote-wakeup-connected; }; usbhsehci: ehci@c00 { compatible = "ti,ehci-omap"; reg = <0xc00 0x400>; interrupts = ; }; }; }; target-module@66000 { /* 0x4a066000, ap 25 26.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mmu_dsp"; reg = <0x66000 0x4>, <0x66010 0x4>, <0x66014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */ clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; clock-names = "fck"; - resets = <&prm_tesla 1>; - reset-names = "rstctrl"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x66000 0x1000>; - mmu_dsp: mmu@0 { - compatible = "ti,omap4-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - }; + /* mmu_dsp cannot be moved before reset driver */ + status = "disabled"; }; }; segment@80000 { /* 0x4a080000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ <0x0005a000 0x000da000 0x001000>, /* ap 14 */ <0x0005b000 0x000db000 0x001000>, /* ap 15 */ <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ <0x0005e000 0x000de000 0x001000>, /* ap 18 */ <0x00060000 0x000e0000 0x001000>, /* ap 19 */ <0x00061000 0x000e1000 0x001000>, /* ap 20 */ <0x00074000 0x000f4000 0x001000>, /* ap 27 */ <0x00075000 0x000f5000 0x001000>, /* ap 28 */ <0x00076000 0x000f6000 0x001000>, /* ap 29 */ <0x00077000 0x000f7000 0x001000>, /* ap 30 */ <0x00036000 0x000b6000 0x001000>, /* ap 69 */ <0x00037000 0x000b7000 0x001000>, /* ap 70 */ <0x0004d000 0x000cd000 0x001000>, /* ap 78 */ <0x0004e000 0x000ce000 0x001000>, /* ap 79 */ <0x00029000 0x000a9000 0x001000>, /* ap 82 */ <0x0002a000 0x000aa000 0x001000>, /* ap 83 */ <0x0002b000 0x000ab000 0x001000>, /* ap 84 */ <0x0002c000 0x000ac000 0x001000>, /* ap 85 */ <0x0002d000 0x000ad000 0x001000>, /* ap 88 */ <0x0002e000 0x000ae000 0x001000>; /* ap 89 */ target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x29000 0x1000>; }; target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "usb_otg_hs"; reg = <0x2b400 0x4>, <0x2b404 0x4>, <0x2b408 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-midle = , , ; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2b000 0x1000>; usb_otg_hs: usb_otg_hs@0 { compatible = "ti,omap4-musb"; reg = <0x0 0x7ff>; interrupts = , ; interrupt-names = "mc", "dma"; usb-phy = <&usb2_phy>; phys = <&usb2_phy>; phy-names = "usb2-phy"; multipoint = <1>; num-eps = <16>; ram-bits = <12>; ctrl-module = <&omap_control_usbotg>; }; }; target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "ocp2scp_usb_phy"; reg = <0x2d000 0x4>, <0x2d010 0x4>, <0x2d014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2d000 0x1000>; ocp2scp@0 { compatible = "ti,omap-ocp2scp"; reg = <0x0 0x1f>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x1000>; usb2_phy: usb2phy@80 { compatible = "ti,omap-usb2"; reg = <0x80 0x58>; ctrl-module = <&omap_control_usb2phy>; clocks = <&usb_phy_cm_clk32k>; clock-names = "wkupclk"; #phy-cells = <0>; }; }; }; /* d2d mdm */ target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x36000 0x4>, <0x36010 0x4>, <0x36014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */ clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x36000 0x1000>; }; /* d2d mpu */ target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x4d000 0x4>, <0x4d010 0x4>, <0x4d014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */ clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4d000 0x1000>; }; target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */ compatible = "ti,sysc-omap4-sr", "ti,sysc"; + ti,hwmods = "smartreflex_mpu"; reg = <0x59038 0x4>; reg-names = "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x59000 0x1000>; smartreflex_mpu: smartreflex@0 { compatible = "ti,omap4-smartreflex-mpu"; reg = <0x0 0x80>; interrupts = ; }; }; target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */ compatible = "ti,sysc-omap4-sr", "ti,sysc"; + ti,hwmods = "smartreflex_iva"; reg = <0x5b038 0x4>; reg-names = "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5b000 0x1000>; smartreflex_iva: smartreflex@0 { compatible = "ti,omap4-smartreflex-iva"; reg = <0x0 0x80>; interrupts = ; }; }; target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */ compatible = "ti,sysc-omap4-sr", "ti,sysc"; + ti,hwmods = "smartreflex_core"; reg = <0x5d038 0x4>; reg-names = "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5d000 0x1000>; smartreflex_core: smartreflex@0 { compatible = "ti,omap4-smartreflex-core"; reg = <0x0 0x80>; interrupts = ; }; }; target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x60000 0x1000>; }; target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox"; reg = <0x74000 0x4>, <0x74010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x74000 0x1000>; mailbox: mailbox@0 { compatible = "ti,omap4-mailbox"; reg = <0x0 0x200>; interrupts = ; #mbox-cells = <1>; ti,mbox-num-users = <3>; ti,mbox-num-fifos = <8>; mbox_ipu: mbox_ipu { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; mbox_dsp: mbox_dsp { ti,mbox-tx = <3 0 0>; ti,mbox-rx = <2 0 0>; }; }; }; target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spinlock"; reg = <0x76000 0x4>, <0x76010 0x4>, <0x76014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x76000 0x1000>; hwspinlock: spinlock@0 { compatible = "ti,omap4-hwspinlock"; reg = <0x0 0x1000>; #hwlock-cells = <1>; }; }; }; segment@100000 { /* 0x4a100000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */ <0x00001000 0x00101000 0x001000>, /* ap 22 */ <0x00002000 0x00102000 0x001000>, /* ap 61 */ <0x00003000 0x00103000 0x001000>, /* ap 62 */ <0x00008000 0x00108000 0x001000>, /* ap 63 */ <0x00009000 0x00109000 0x001000>, /* ap 64 */ <0x0000a000 0x0010a000 0x001000>, /* ap 65 */ <0x0000b000 0x0010b000 0x001000>; /* ap 66 */ target-module@0 { /* 0x4a100000, ap 21 2a.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "ctrl_module_pad_core"; reg = <0x0 0x4>, <0x10 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x1000>; omap4_pmx_core: pinmux@40 { compatible = "ti,omap4-padconf", "pinctrl-single"; reg = <0x40 0x0196>; #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x7fff>; }; omap4_padconf_global: omap4_padconf_global@5a0 { compatible = "syscon", "simple-bus"; reg = <0x5a0 0x170>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x5a0 0x170>; pbias_regulator: pbias_regulator@60 { compatible = "ti,pbias-omap4", "ti,pbias-omap"; reg = <0x60 0x4>; syscon = <&omap4_padconf_global>; pbias_mmc_reg: pbias_mmc_omap4 { regulator-name = "pbias_mmc_omap4"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; }; }; }; }; target-module@2000 { /* 0x4a102000, ap 61 3c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x1000>; }; target-module@8000 { /* 0x4a108000, ap 63 62.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x1000>; }; target-module@a000 { /* 0x4a10a000, ap 65 50.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "fdif"; reg = <0xa000 0x4>, <0xa010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-midle = , , ; ti,sysc-sidle = , , ; ti,sysc-delay-us = <2>; /* Domains (V, P, C): core, cam_pwrdm, iss_clkdm */ clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa000 0x1000>; /* No child device binding or driver in mainline */ }; }; segment@180000 { /* 0x4a180000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; }; segment@200000 { /* 0x4a200000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */ <0x0001f000 0x0021f000 0x001000>, /* ap 32 */ <0x0000a000 0x0020a000 0x001000>, /* ap 33 */ <0x0000b000 0x0020b000 0x001000>, /* ap 34 */ <0x00004000 0x00204000 0x001000>, /* ap 35 */ <0x00005000 0x00205000 0x001000>, /* ap 36 */ <0x00006000 0x00206000 0x001000>, /* ap 37 */ <0x00007000 0x00207000 0x001000>, /* ap 38 */ <0x00012000 0x00212000 0x001000>, /* ap 39 */ <0x00013000 0x00213000 0x001000>, /* ap 40 */ <0x0000c000 0x0020c000 0x001000>, /* ap 41 */ <0x0000d000 0x0020d000 0x001000>, /* ap 42 */ <0x00010000 0x00210000 0x001000>, /* ap 43 */ <0x00011000 0x00211000 0x001000>, /* ap 44 */ <0x00016000 0x00216000 0x001000>, /* ap 45 */ <0x00017000 0x00217000 0x001000>, /* ap 46 */ <0x00014000 0x00214000 0x001000>, /* ap 47 */ <0x00015000 0x00215000 0x001000>, /* ap 48 */ <0x00018000 0x00218000 0x001000>, /* ap 49 */ <0x00019000 0x00219000 0x001000>, /* ap 50 */ <0x00020000 0x00220000 0x001000>, /* ap 51 */ <0x00021000 0x00221000 0x001000>, /* ap 52 */ <0x00026000 0x00226000 0x001000>, /* ap 53 */ <0x00027000 0x00227000 0x001000>, /* ap 54 */ <0x00028000 0x00228000 0x001000>, /* ap 55 */ <0x00029000 0x00229000 0x001000>, /* ap 56 */ <0x0002a000 0x0022a000 0x001000>, /* ap 57 */ <0x0002b000 0x0022b000 0x001000>, /* ap 58 */ <0x0001c000 0x0021c000 0x001000>, /* ap 59 */ <0x0001d000 0x0021d000 0x001000>; /* ap 60 */ target-module@4000 { /* 0x4a204000, ap 35 42.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; }; target-module@6000 { /* 0x4a206000, ap 37 4a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6000 0x1000>; }; target-module@a000 { /* 0x4a20a000, ap 33 2c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa000 0x1000>; }; target-module@c000 { /* 0x4a20c000, ap 41 20.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc000 0x1000>; }; target-module@10000 { /* 0x4a210000, ap 43 52.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x10000 0x1000>; }; target-module@12000 { /* 0x4a212000, ap 39 18.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x12000 0x1000>; }; target-module@14000 { /* 0x4a214000, ap 47 30.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x14000 0x1000>; }; target-module@16000 { /* 0x4a216000, ap 45 28.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x16000 0x1000>; }; target-module@18000 { /* 0x4a218000, ap 49 38.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x18000 0x1000>; }; target-module@1c000 { /* 0x4a21c000, ap 59 5a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1c000 0x1000>; }; target-module@1e000 { /* 0x4a21e000, ap 31 10.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1e000 0x1000>; }; target-module@20000 { /* 0x4a220000, ap 51 40.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x1000>; }; target-module@26000 { /* 0x4a226000, ap 53 34.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x26000 0x1000>; }; target-module@28000 { /* 0x4a228000, ap 55 2e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x28000 0x1000>; }; target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2a000 0x1000>; }; }; segment@280000 { /* 0x4a280000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; }; l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */ <0x00040000 0x00340000 0x001000>, /* ap 68 */ <0x00020000 0x00320000 0x004000>, /* ap 71 */ <0x00024000 0x00324000 0x002000>, /* ap 72 */ <0x00026000 0x00326000 0x001000>, /* ap 73 */ <0x00027000 0x00327000 0x001000>, /* ap 74 */ <0x00028000 0x00328000 0x001000>, /* ap 75 */ <0x00029000 0x00329000 0x001000>, /* ap 76 */ <0x00030000 0x00330000 0x010000>, /* ap 77 */ <0x0002a000 0x0032a000 0x002000>, /* ap 90 */ <0x0002c000 0x0032c000 0x004000>; /* ap 91 */ l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x00020000>, <0x00020000 0x00020000 0x00004000>, <0x00024000 0x00024000 0x00002000>, <0x00026000 0x00026000 0x00001000>, <0x00027000 0x00027000 0x00001000>, <0x00028000 0x00028000 0x00001000>, <0x00029000 0x00029000 0x00001000>, <0x0002a000 0x0002a000 0x00002000>, <0x0002c000 0x0002c000 0x00004000>, <0x00030000 0x00030000 0x00010000>; }; }; }; &l4_wkup { /* 0x4a300000 */ compatible = "ti,omap4-l4-wkup", "simple-bus"; reg = <0x4a300000 0x800>, <0x4a300800 0x800>, <0x4a301000 0x1000>; reg-names = "ap", "la", "ia0"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x4a300000 0x010000>, /* segment 0 */ <0x00010000 0x4a310000 0x010000>, /* segment 1 */ <0x00020000 0x4a320000 0x010000>; /* segment 2 */ segment@0 { /* 0x4a300000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00001000 0x00001000 0x001000>, /* ap 1 */ <0x00000800 0x00000800 0x000800>, /* ap 2 */ <0x00006000 0x00006000 0x002000>, /* ap 3 */ <0x00008000 0x00008000 0x001000>, /* ap 4 */ <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ <0x00004000 0x00004000 0x001000>, /* ap 17 */ <0x00005000 0x00005000 0x001000>, /* ap 18 */ <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ target-module@4000 { /* 0x4a304000, ap 17 24.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "counter_32k"; reg = <0x4000 0x4>, <0x4004 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , ; /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; counter32k: counter@0 { compatible = "ti,omap-counter32k"; reg = <0x0 0x20>; }; }; target-module@6000 { /* 0x4a306000, ap 3 08.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x6000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6000 0x2000>; prm: prm@0 { - compatible = "ti,omap4-prm", "simple-bus"; + compatible = "ti,omap4-prm"; reg = <0x0 0x2000>; interrupts = ; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x2000>; prm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; prm_clockdomains: clockdomains { }; }; }; target-module@a000 { /* 0x4a30a000, ap 15 34.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xa000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa000 0x1000>; scrm: scrm@0 { compatible = "ti,omap4-scrm"; reg = <0x0 0x2000>; scrm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; scrm_clockdomains: clockdomains { }; }; }; target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "ctrl_module_wkup"; reg = <0xc000 0x4>, <0xc010 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , , ; /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc000 0x1000>; omap4_scm_wkup: scm@c000 { compatible = "ti,omap4-scm-wkup"; reg = <0xc000 0x1000>; }; }; }; segment@10000 { /* 0x4a310000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ <0x00001000 0x00011000 0x001000>, /* ap 6 */ <0x00004000 0x00014000 0x001000>, /* ap 7 */ <0x00005000 0x00015000 0x001000>, /* ap 8 */ <0x00008000 0x00018000 0x001000>, /* ap 9 */ <0x00009000 0x00019000 0x001000>, /* ap 10 */ <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ <0x0000d000 0x0001d000 0x001000>, /* ap 12 */ <0x0000e000 0x0001e000 0x001000>, /* ap 21 */ <0x0000f000 0x0001f000 0x001000>; /* ap 22 */ gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio1"; reg = <0x0 0x4>, <0x10 0x4>, <0x114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>, <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x1000>; gpio1: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; ti,gpio-always-on; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@4000 { /* 0x4a314000, ap 7 18.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x4000 0x4>, <0x4010 0x4>, <0x4014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; wdt2: wdt@0 { compatible = "ti,omap4-wdt", "ti,omap3-wdt"; reg = <0x0 0x80>; interrupts = ; }; }; target-module@8000 { /* 0x4a318000, ap 9 1c.0 */ compatible = "ti,sysc-omap2-timer", "ti,sysc"; ti,hwmods = "timer1"; reg = <0x8000 0x4>, <0x8010 0x4>, <0x8014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x1000>; timer1: timer@0 { compatible = "ti,omap3430-timer"; reg = <0x0 0x80>; clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>; clock-names = "fck"; interrupts = ; ti,timer-alwon; }; }; target-module@c000 { /* 0x4a31c000, ap 11 20.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "kbd"; reg = <0xc000 0x4>, <0xc010 0x4>, <0xc014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc000 0x1000>; keypad: keypad@0 { compatible = "ti,omap4-keypad"; reg = <0x0 0x80>; interrupts = ; reg-names = "mpu"; }; }; target-module@e000 { /* 0x4a31e000, ap 21 30.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "ctrl_module_pad_wkup"; reg = <0xe000 0x4>, <0xe010 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , , , ; /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe000 0x1000>; omap4_pmx_wkup: pinmux@40 { compatible = "ti,omap4-padconf", "pinctrl-single"; reg = <0x40 0x0038>; #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x7fff>; }; }; }; segment@20000 { /* 0x4a320000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ <0x00000000 0x00020000 0x001000>, /* ap 23 */ <0x00001000 0x00021000 0x001000>, /* ap 24 */ <0x00002000 0x00022000 0x001000>, /* ap 25 */ <0x00003000 0x00023000 0x001000>, /* ap 26 */ <0x00004000 0x00024000 0x001000>, /* ap 27 */ <0x00005000 0x00025000 0x001000>, /* ap 28 */ <0x00007000 0x00027000 0x000400>, /* ap 29 */ <0x00008000 0x00028000 0x000800>, /* ap 30 */ <0x00009000 0x00029000 0x000400>; /* ap 31 */ target-module@0 { /* 0x4a320000, ap 23 04.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x1000>; }; target-module@2000 { /* 0x4a322000, ap 25 0c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x1000>; }; target-module@4000 { /* 0x4a324000, ap 27 10.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; }; target-module@6000 { /* 0x4a326000, ap 13 28.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00006000 0x00001000>, <0x00001000 0x00007000 0x00000400>, <0x00002000 0x00008000 0x00000800>, <0x00003000 0x00009000 0x00000400>; }; }; }; &l4_per { /* 0x48000000 */ compatible = "ti,omap4-l4-per", "simple-bus"; reg = <0x48000000 0x800>, <0x48000800 0x800>, <0x48001000 0x400>, <0x48001400 0x400>, <0x48001800 0x400>, <0x48001c00 0x400>; reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ <0x00200000 0x48200000 0x200000>; /* segment 1 */ segment@0 { /* 0x48000000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00001000 0x00001000 0x000400>, /* ap 1 */ <0x00000800 0x00000800 0x000800>, /* ap 2 */ <0x00020000 0x00020000 0x001000>, /* ap 3 */ <0x00021000 0x00021000 0x001000>, /* ap 4 */ <0x00032000 0x00032000 0x001000>, /* ap 5 */ <0x00033000 0x00033000 0x001000>, /* ap 6 */ <0x00034000 0x00034000 0x001000>, /* ap 7 */ <0x00035000 0x00035000 0x001000>, /* ap 8 */ <0x00036000 0x00036000 0x001000>, /* ap 9 */ <0x00037000 0x00037000 0x001000>, /* ap 10 */ <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ <0x00040000 0x00040000 0x010000>, /* ap 13 */ <0x00050000 0x00050000 0x001000>, /* ap 14 */ <0x00055000 0x00055000 0x001000>, /* ap 15 */ <0x00056000 0x00056000 0x001000>, /* ap 16 */ <0x00057000 0x00057000 0x001000>, /* ap 17 */ <0x00058000 0x00058000 0x001000>, /* ap 18 */ <0x00059000 0x00059000 0x001000>, /* ap 19 */ <0x0005a000 0x0005a000 0x001000>, /* ap 20 */ <0x0005b000 0x0005b000 0x001000>, /* ap 21 */ <0x0005c000 0x0005c000 0x001000>, /* ap 22 */ <0x0005d000 0x0005d000 0x001000>, /* ap 23 */ <0x0005e000 0x0005e000 0x001000>, /* ap 24 */ <0x00060000 0x00060000 0x001000>, /* ap 25 */ <0x0006a000 0x0006a000 0x001000>, /* ap 26 */ <0x0006b000 0x0006b000 0x001000>, /* ap 27 */ <0x0006c000 0x0006c000 0x001000>, /* ap 28 */ <0x0006d000 0x0006d000 0x001000>, /* ap 29 */ <0x0006e000 0x0006e000 0x001000>, /* ap 30 */ <0x0006f000 0x0006f000 0x001000>, /* ap 31 */ <0x00070000 0x00070000 0x001000>, /* ap 32 */ <0x00071000 0x00071000 0x001000>, /* ap 33 */ <0x00072000 0x00072000 0x001000>, /* ap 34 */ <0x00073000 0x00073000 0x001000>, /* ap 35 */ <0x00061000 0x00061000 0x001000>, /* ap 36 */ <0x00096000 0x00096000 0x001000>, /* ap 37 */ <0x00097000 0x00097000 0x001000>, /* ap 38 */ <0x00076000 0x00076000 0x001000>, /* ap 39 */ <0x00077000 0x00077000 0x001000>, /* ap 40 */ <0x00078000 0x00078000 0x001000>, /* ap 41 */ <0x00079000 0x00079000 0x001000>, /* ap 42 */ <0x00086000 0x00086000 0x001000>, /* ap 43 */ <0x00087000 0x00087000 0x001000>, /* ap 44 */ <0x00088000 0x00088000 0x001000>, /* ap 45 */ <0x00089000 0x00089000 0x001000>, /* ap 46 */ <0x000b0000 0x000b0000 0x001000>, /* ap 47 */ <0x000b1000 0x000b1000 0x001000>, /* ap 48 */ <0x00098000 0x00098000 0x001000>, /* ap 49 */ <0x00099000 0x00099000 0x001000>, /* ap 50 */ <0x0009a000 0x0009a000 0x001000>, /* ap 51 */ <0x0009b000 0x0009b000 0x001000>, /* ap 52 */ <0x0009c000 0x0009c000 0x001000>, /* ap 53 */ <0x0009d000 0x0009d000 0x001000>, /* ap 54 */ <0x0009e000 0x0009e000 0x001000>, /* ap 55 */ <0x0009f000 0x0009f000 0x001000>, /* ap 56 */ <0x00090000 0x00090000 0x002000>, /* ap 57 */ <0x00092000 0x00092000 0x001000>, /* ap 58 */ <0x000a4000 0x000a4000 0x001000>, /* ap 59 */ <0x000a6000 0x000a6000 0x001000>, /* ap 60 */ <0x000a8000 0x000a8000 0x004000>, /* ap 61 */ <0x000ac000 0x000ac000 0x001000>, /* ap 62 */ <0x000ad000 0x000ad000 0x001000>, /* ap 63 */ <0x000ae000 0x000ae000 0x001000>, /* ap 64 */ <0x000b2000 0x000b2000 0x001000>, /* ap 65 */ <0x000b3000 0x000b3000 0x001000>, /* ap 66 */ <0x000b4000 0x000b4000 0x001000>, /* ap 67 */ <0x000b5000 0x000b5000 0x001000>, /* ap 68 */ <0x000b8000 0x000b8000 0x001000>, /* ap 69 */ <0x000b9000 0x000b9000 0x001000>, /* ap 70 */ <0x000ba000 0x000ba000 0x001000>, /* ap 71 */ <0x000bb000 0x000bb000 0x001000>, /* ap 72 */ <0x000d1000 0x000d1000 0x001000>, /* ap 73 */ <0x000d2000 0x000d2000 0x001000>, /* ap 74 */ <0x000d5000 0x000d5000 0x001000>, /* ap 75 */ <0x000d6000 0x000d6000 0x001000>, /* ap 76 */ <0x000a2000 0x000a2000 0x001000>, /* ap 79 */ <0x000a3000 0x000a3000 0x001000>, /* ap 80 */ <0x00001400 0x00001400 0x000400>, /* ap 81 */ <0x00001800 0x00001800 0x000400>, /* ap 82 */ <0x00001c00 0x00001c00 0x000400>, /* ap 83 */ <0x000a5000 0x000a5000 0x001000>; /* ap 84 */ target-module@20000 { /* 0x48020000, ap 3 06.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x20050 0x4>, <0x20054 0x4>, <0x20058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x1000>; uart3: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; }; }; target-module@32000 { /* 0x48032000, ap 5 02.0 */ compatible = "ti,sysc-omap2-timer", "ti,sysc"; + ti,hwmods = "timer2"; reg = <0x32000 0x4>, <0x32010 0x4>, <0x32014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x32000 0x1000>; timer2: timer@0 { compatible = "ti,omap3430-timer"; reg = <0x0 0x80>; clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>; clock-names = "fck"; interrupts = ; }; }; target-module@34000 { /* 0x48034000, ap 7 04.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer3"; reg = <0x34000 0x4>, <0x34010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x34000 0x1000>; timer3: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x0 0x80>; clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>; clock-names = "fck"; interrupts = ; }; }; target-module@36000 { /* 0x48036000, ap 9 0e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer4"; reg = <0x36000 0x4>, <0x36010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x36000 0x1000>; timer4: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x0 0x80>; clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>; clock-names = "fck"; interrupts = ; }; }; target-module@3e000 { /* 0x4803e000, ap 11 08.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer9"; reg = <0x3e000 0x4>, <0x3e010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3e000 0x1000>; timer9: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x0 0x80>; clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>; clock-names = "fck"; interrupts = ; ti,timer-pwm; }; }; target-module@40000 { /* 0x48040000, ap 13 0a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x40000 0x10000>; }; target-module@55000 { /* 0x48055000, ap 15 0c.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio2"; reg = <0x55000 0x4>, <0x55010 0x4>, <0x55114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>, <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x55000 0x1000>; gpio2: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@57000 { /* 0x48057000, ap 17 16.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio3"; reg = <0x57000 0x4>, <0x57010 0x4>, <0x57114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>, <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x57000 0x1000>; gpio3: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@59000 { /* 0x48059000, ap 19 10.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio4"; reg = <0x59000 0x4>, <0x59010 0x4>, <0x59114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>, <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x59000 0x1000>; gpio4: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@5b000 { /* 0x4805b000, ap 21 12.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio5"; reg = <0x5b000 0x4>, <0x5b010 0x4>, <0x5b114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>, <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5b000 0x1000>; gpio5: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@5d000 { /* 0x4805d000, ap 23 14.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio6"; reg = <0x5d000 0x4>, <0x5d010 0x4>, <0x5d114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>, <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5d000 0x1000>; gpio6: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@60000 { /* 0x48060000, ap 25 1e.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x60000 0x8>, <0x60010 0x8>, <0x60090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x60000 0x1000>; i2c3: i2c@0 { compatible = "ti,omap4-i2c"; reg = <0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; }; }; target-module@6a000 { /* 0x4806a000, ap 26 18.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x6a050 0x4>, <0x6a054 0x4>, <0x6a058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6a000 0x1000>; uart1: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; }; }; target-module@6c000 { /* 0x4806c000, ap 28 20.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x6c050 0x4>, <0x6c054 0x4>, <0x6c058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6c000 0x1000>; uart2: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; }; }; target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x6e050 0x4>, <0x6e054 0x4>, <0x6e058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6e000 0x1000>; uart4: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; }; }; target-module@70000 { /* 0x48070000, ap 32 28.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x70000 0x8>, <0x70010 0x8>, <0x70090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x70000 0x1000>; i2c1: i2c@0 { compatible = "ti,omap4-i2c"; reg = <0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; }; }; target-module@72000 { /* 0x48072000, ap 34 30.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x72000 0x8>, <0x72010 0x8>, <0x72090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x72000 0x1000>; i2c2: i2c@0 { compatible = "ti,omap4-i2c"; reg = <0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; }; }; target-module@76000 { /* 0x48076000, ap 39 38.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "slimbus2"; reg = <0x76000 0x4>, <0x76010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x76000 0x1000>; /* No child device binding or driver in mainline */ }; target-module@78000 { /* 0x48078000, ap 41 1a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "elm"; reg = <0x78000 0x4>, <0x78010 0x4>, <0x78014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x78000 0x1000>; elm: elm@0 { compatible = "ti,am3352-elm"; reg = <0x0 0x2000>; interrupts = ; status = "disabled"; }; }; target-module@86000 { /* 0x48086000, ap 43 24.0 */ compatible = "ti,sysc-omap2-timer", "ti,sysc"; + ti,hwmods = "timer10"; reg = <0x86000 0x4>, <0x86010 0x4>, <0x86014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x86000 0x1000>; timer10: timer@0 { compatible = "ti,omap3430-timer"; reg = <0x0 0x80>; clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>; clock-names = "fck"; interrupts = ; ti,timer-pwm; }; }; target-module@88000 { /* 0x48088000, ap 45 2e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer11"; reg = <0x88000 0x4>, <0x88010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x88000 0x1000>; timer11: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x0 0x80>; clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>; clock-names = "fck"; interrupts = ; ti,timer-pwm; }; }; - rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x91fe0 0x4>, - <0x91fe4 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - ; - /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ - clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>; - clock-names = "fck"; + target-module@90000 { /* 0x48090000, ap 57 2a.0 */ + compatible = "ti,sysc"; + status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x90000 0x2000>; - - rng: rng@0 { - compatible = "ti,omap4-rng"; - reg = <0x0 0x2000>; - interrupts = ; - }; }; target-module@96000 { /* 0x48096000, ap 37 26.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mcbsp4"; reg = <0x9608c 0x4>; reg-names = "sysc"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = , , ; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x96000 0x1000>; mcbsp4: mcbsp@0 { compatible = "ti,omap4-mcbsp"; reg = <0x0 0xff>; /* L4 Interconnect */ reg-names = "mpu"; interrupts = ; interrupt-names = "common"; ti,buffer-size = <128>; dmas = <&sdma 31>, <&sdma 32>; dma-names = "tx", "rx"; status = "disabled"; }; }; target-module@98000 { /* 0x48098000, ap 49 22.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi1"; reg = <0x98000 0x4>, <0x98010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x98000 0x1000>; mcspi1: spi@0 { compatible = "ti,omap4-mcspi"; reg = <0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,spi-num-cs = <4>; dmas = <&sdma 35>, <&sdma 36>, <&sdma 37>, <&sdma 38>, <&sdma 39>, <&sdma 40>, <&sdma 41>, <&sdma 42>; dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3"; }; }; target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi2"; reg = <0x9a000 0x4>, <0x9a010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9a000 0x1000>; mcspi2: spi@0 { compatible = "ti,omap4-mcspi"; reg = <0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,spi-num-cs = <2>; dmas = <&sdma 43>, <&sdma 44>, <&sdma 45>, <&sdma 46>; dma-names = "tx0", "rx0", "tx1", "rx1"; }; }; target-module@9c000 { /* 0x4809c000, ap 53 36.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x9c000 0x4>, <0x9c010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9c000 0x1000>; mmc1: mmc@0 { compatible = "ti,omap4-hsmmc"; reg = <0x0 0x400>; interrupts = ; ti,dual-volt; ti,needs-special-reset; dmas = <&sdma 61>, <&sdma 62>; dma-names = "tx", "rx"; pbias-supply = <&pbias_mmc_reg>; }; }; target-module@9e000 { /* 0x4809e000, ap 55 48.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9e000 0x1000>; }; target-module@a2000 { /* 0x480a2000, ap 79 3a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa2000 0x1000>; }; target-module@a4000 { /* 0x480a4000, ap 59 34.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x000a4000 0x00001000>, <0x00001000 0x000a5000 0x00001000>; }; - des_target: target-module@a5000 { /* 0x480a5000 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xa5030 0x4>, - <0xa5034 0x4>, - <0xa5038 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ - clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xa5000 0x00001000>; - - des: des@0 { - compatible = "ti,omap4-des"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&sdma 117>, <&sdma 116>; - dma-names = "tx", "rx"; - }; - }; - target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa8000 0x4000>; }; target-module@ad000 { /* 0x480ad000, ap 63 50.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xad000 0x4>, <0xad010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xad000 0x1000>; mmc3: mmc@0 { compatible = "ti,omap4-hsmmc"; reg = <0x0 0x400>; interrupts = ; ti,needs-special-reset; dmas = <&sdma 77>, <&sdma 78>; dma-names = "tx", "rx"; }; }; target-module@b0000 { /* 0x480b0000, ap 47 40.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb0000 0x1000>; }; target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "hdq1w"; reg = <0xb2000 0x4>, <0xb2014 0x4>, <0xb2018 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,syss-mask = <1>; ti,no-reset-on-init; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_HDQ1W_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb2000 0x1000>; hdqw1w: 1w@0 { compatible = "ti,omap3-1w"; reg = <0x0 0x1000>; interrupts = ; }; }; target-module@b4000 { /* 0x480b4000, ap 67 46.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xb4000 0x4>, <0xb4010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb4000 0x1000>; mmc2: mmc@0 { compatible = "ti,omap4-hsmmc"; reg = <0x0 0x400>; interrupts = ; ti,needs-special-reset; dmas = <&sdma 47>, <&sdma 48>; dma-names = "tx", "rx"; }; }; target-module@b8000 { /* 0x480b8000, ap 69 58.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi3"; reg = <0xb8000 0x4>, <0xb8010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb8000 0x1000>; mcspi3: spi@0 { compatible = "ti,omap4-mcspi"; reg = <0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,spi-num-cs = <2>; dmas = <&sdma 15>, <&sdma 16>; dma-names = "tx0", "rx0"; }; }; target-module@ba000 { /* 0x480ba000, ap 71 32.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi4"; reg = <0xba000 0x4>, <0xba010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xba000 0x1000>; mcspi4: spi@0 { compatible = "ti,omap4-mcspi"; reg = <0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,spi-num-cs = <1>; dmas = <&sdma 70>, <&sdma 71>; dma-names = "tx0", "rx0"; }; }; target-module@d1000 { /* 0x480d1000, ap 73 44.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xd1000 0x4>, <0xd1010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd1000 0x1000>; mmc4: mmc@0 { compatible = "ti,omap4-hsmmc"; reg = <0x0 0x400>; interrupts = ; ti,needs-special-reset; dmas = <&sdma 57>, <&sdma 58>; dma-names = "tx", "rx"; }; }; target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xd5000 0x4>, <0xd5010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd5000 0x1000>; mmc5: mmc@0 { compatible = "ti,omap4-hsmmc"; reg = <0x0 0x400>; interrupts = ; ti,needs-special-reset; dmas = <&sdma 59>, <&sdma 60>; dma-names = "tx", "rx"; }; }; }; segment@200000 { /* 0x48200000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */ <0x00151000 0x00351000 0x001000>; /* ap 78 */ target-module@150000 { /* 0x48350000, ap 77 4c.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x150000 0x8>, <0x150010 0x8>, <0x150090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x150000 0x1000>; i2c4: i2c@0 { compatible = "ti,omap4-i2c"; reg = <0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; }; }; }; }; diff --git a/sys/gnu/dts/arm/omap4.dtsi b/sys/gnu/dts/arm/omap4.dtsi index 9a87440d0b9d..7cc95bc1598b 100644 --- a/sys/gnu/dts/arm/omap4.dtsi +++ b/sys/gnu/dts/arm/omap4.dtsi @@ -1,532 +1,444 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ */ #include #include #include #include #include #include / { compatible = "ti,omap4430", "ti,omap4"; interrupt-parent = <&wakeupgen>; #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; next-level-cache = <&L2>; reg = <0x0>; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; clock-latency = <300000>; /* From omap-cpufreq driver */ }; cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; next-level-cache = <&L2>; reg = <0x1>; }; }; /* * Note that 4430 needs cross trigger interface (CTI) supported * before we can configure the interrupts. This means sampling * events are not supported for pmu. Note that 4460 does not use * CTI, see also 4460.dtsi. */ pmu { compatible = "arm,cortex-a9-pmu"; ti,hwmods = "debugss"; }; gic: interrupt-controller@48241000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; #interrupt-cells = <3>; reg = <0x48241000 0x1000>, <0x48240100 0x0100>; interrupt-parent = <&gic>; }; L2: l2-cache-controller@48242000 { compatible = "arm,pl310-cache"; reg = <0x48242000 0x1000>; cache-unified; cache-level = <2>; }; local-timer@48240600 { compatible = "arm,cortex-a9-twd-timer"; clocks = <&mpu_periphclk>; reg = <0x48240600 0x20>; interrupts = ; interrupt-parent = <&gic>; }; wakeupgen: interrupt-controller@48281000 { compatible = "ti,omap4-wugen-mpu"; interrupt-controller; #interrupt-cells = <3>; reg = <0x48281000 0x1000>; interrupt-parent = <&gic>; }; /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself. */ soc { compatible = "ti,omap-infra"; mpu { compatible = "ti,omap4-mpu"; ti,hwmods = "mpu"; sram = <&ocmcram>; }; dsp { compatible = "ti,omap3-c64"; ti,hwmods = "dsp"; }; iva { compatible = "ti,ivahd"; ti,hwmods = "iva"; }; }; /* * XXX: Use a flat representation of the OMAP4 interconnect. * The real OMAP interconnect network is quite complex. * Since it will not bring real advantage to represent that in DT for * the moment, just use a fake OCP bus entry to represent the whole bus * hierarchy. */ ocp { compatible = "ti,omap4-l3-noc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; reg = <0x44000000 0x1000>, <0x44800000 0x2000>, <0x45000000 0x1000>; interrupts = , ; l4_wkup: interconnect@4a300000 { }; l4_cfg: interconnect@4a000000 { }; l4_per: interconnect@48000000 { }; l4_abe: interconnect@40100000 { }; - ocmcram: sram@40304000 { + ocmcram: ocmcram@40304000 { compatible = "mmio-sram"; reg = <0x40304000 0xa000>; /* 40k */ }; gpmc: gpmc@50000000 { compatible = "ti,omap4430-gpmc"; reg = <0x50000000 0x1000>; #address-cells = <2>; #size-cells = <1>; interrupts = ; dmas = <&sdma 4>; dma-names = "rxtx"; gpmc,num-cs = <8>; gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; ti,no-idle-on-init; clocks = <&l3_div_ck>; clock-names = "fck"; interrupt-controller; #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; }; + mmu_dsp: mmu@4a066000 { + compatible = "ti,omap4-iommu"; + reg = <0x4a066000 0x100>; + interrupts = ; + ti,hwmods = "mmu_dsp"; + #iommu-cells = <0>; + }; + target-module@52000000 { compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "iss"; reg = <0x52000000 0x4>, <0x52000010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; ti,sysc-delay-us = <2>; clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x52000000 0x1000000>; /* No child device binding, driver in staging */ }; - target-module@55082000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x55082000 0x4>, - <0x55082010 0x4>, - <0x55082014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_core 2>; - reset-names = "rstctrl"; - ranges = <0x0 0x55082000 0x100>; - #size-cells = <1>; - #address-cells = <1>; - - mmu_ipu: mmu@0 { - compatible = "ti,omap4-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - }; + mmu_ipu: mmu@55082000 { + compatible = "ti,omap4-iommu"; + reg = <0x55082000 0x100>; + interrupts = ; + ti,hwmods = "mmu_ipu"; + #iommu-cells = <0>; + ti,iommu-bus-err-back; }; - target-module@4012c000 { compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "slimbus1"; reg = <0x4012c000 0x4>, <0x4012c010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , , ; clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */ <0x4902c000 0x4902c000 0x1000>; /* L3 */ /* No child device binding or driver in mainline */ }; dmm@4e000000 { compatible = "ti,omap4-dmm"; reg = <0x4e000000 0x800>; interrupts = <0 113 0x4>; ti,hwmods = "dmm"; }; emif1: emif@4c000000 { compatible = "ti,emif-4d"; reg = <0x4c000000 0x100>; interrupts = ; ti,hwmods = "emif1"; ti,no-idle-on-init; phy-type = <1>; hw-caps-read-idle-ctrl; hw-caps-ll-interface; hw-caps-temp-alert; }; emif2: emif@4d000000 { compatible = "ti,emif-4d"; reg = <0x4d000000 0x100>; interrupts = ; ti,hwmods = "emif2"; ti,no-idle-on-init; phy-type = <1>; hw-caps-read-idle-ctrl; hw-caps-ll-interface; hw-caps-temp-alert; }; - aes1_target: target-module@4b501000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4b501080 0x4>, - <0x4b501084 0x4>, - <0x4b501088 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ - clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4b501000 0x1000>; - - aes1: aes@0 { - compatible = "ti,omap4-aes"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&sdma 111>, <&sdma 110>; - dma-names = "tx", "rx"; - }; + aes1: aes@4b501000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes1"; + reg = <0x4b501000 0xa0>; + interrupts = ; + dmas = <&sdma 111>, <&sdma 110>; + dma-names = "tx", "rx"; }; - aes2_target: target-module@4b701000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4b701080 0x4>, - <0x4b701084 0x4>, - <0x4b701088 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ - clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4b701000 0x1000>; - - aes2: aes@0 { - compatible = "ti,omap4-aes"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&sdma 114>, <&sdma 113>; - dma-names = "tx", "rx"; - }; + aes2: aes@4b701000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes2"; + reg = <0x4b701000 0xa0>; + interrupts = ; + dmas = <&sdma 114>, <&sdma 113>; + dma-names = "tx", "rx"; }; - sham_target: target-module@4b100000 { - compatible = "ti,sysc-omap3-sham", "ti,sysc"; - reg = <0x4b100100 0x4>, - <0x4b100110 0x4>, - <0x4b100114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ - clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4b100000 0x1000>; - - sham: sham@0 { - compatible = "ti,omap4-sham"; - reg = <0 0x300>; - interrupts = ; - dmas = <&sdma 119>; - dma-names = "rx"; - }; + des: des@480a5000 { + compatible = "ti,omap4-des"; + ti,hwmods = "des"; + reg = <0x480a5000 0xa0>; + interrupts = ; + dmas = <&sdma 117>, <&sdma 116>; + dma-names = "tx", "rx"; + }; + + sham: sham@4b100000 { + compatible = "ti,omap4-sham"; + ti,hwmods = "sham"; + reg = <0x4b100000 0x300>; + interrupts = ; + dmas = <&sdma 119>; + dma-names = "rx"; }; abb_mpu: regulator-abb-mpu { compatible = "ti,abb-v2"; regulator-name = "abb_mpu"; #address-cells = <0>; #size-cells = <0>; ti,tranxdone-status-mask = <0x80>; clocks = <&sys_clkin_ck>; ti,settling-time = <50>; ti,clock-cycles = <16>; status = "disabled"; }; abb_iva: regulator-abb-iva { compatible = "ti,abb-v2"; regulator-name = "abb_iva"; #address-cells = <0>; #size-cells = <0>; ti,tranxdone-status-mask = <0x80000000>; clocks = <&sys_clkin_ck>; ti,settling-time = <50>; ti,clock-cycles = <16>; status = "disabled"; }; target-module@56000000 { compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5600fe00 0x4>, - <0x5600fe10 0x4>; + reg = <0x5601fc00 0x4>, + <0x5601fc10 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; /* * Closed source PowerVR driver, no child device * binding or driver in mainline */ }; dss: dss@58000000 { compatible = "ti,omap4-dss"; reg = <0x58000000 0x80>; status = "disabled"; ti,hwmods = "dss_core"; clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges; dispc@58001000 { compatible = "ti,omap4-dispc"; reg = <0x58001000 0x1000>; interrupts = ; ti,hwmods = "dss_dispc"; clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; }; rfbi: encoder@58002000 { compatible = "ti,omap4-rfbi"; reg = <0x58002000 0x1000>; status = "disabled"; ti,hwmods = "dss_rfbi"; clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>; clock-names = "fck", "ick"; }; venc: encoder@58003000 { compatible = "ti,omap4-venc"; reg = <0x58003000 0x1000>; status = "disabled"; ti,hwmods = "dss_venc"; clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>; clock-names = "fck"; }; dsi1: encoder@58004000 { compatible = "ti,omap4-dsi"; reg = <0x58004000 0x200>, <0x58004200 0x40>, <0x58004300 0x20>; reg-names = "proto", "phy", "pll"; interrupts = ; status = "disabled"; ti,hwmods = "dss_dsi1"; clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; }; dsi2: encoder@58005000 { compatible = "ti,omap4-dsi"; reg = <0x58005000 0x200>, <0x58005200 0x40>, <0x58005300 0x20>; reg-names = "proto", "phy", "pll"; interrupts = ; status = "disabled"; ti,hwmods = "dss_dsi2"; clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; }; hdmi: encoder@58006000 { compatible = "ti,omap4-hdmi"; reg = <0x58006000 0x200>, <0x58006200 0x100>, <0x58006300 0x100>, <0x58006400 0x1000>; reg-names = "wp", "pll", "phy", "core"; interrupts = ; status = "disabled"; ti,hwmods = "dss_hdmi"; clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; dmas = <&sdma 76>; dma-names = "audio_tx"; }; }; }; }; #include "omap4-l4.dtsi" #include "omap4-l4-abe.dtsi" #include "omap44xx-clocks.dtsi" - -&prm { - prm_tesla: prm@400 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x400 0x100>; - #reset-cells = <1>; - }; - - prm_core: prm@700 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x700 0x100>; - #reset-cells = <1>; - }; - - prm_ivahd: prm@f00 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0xf00 0x100>; - #reset-cells = <1>; - }; - - prm_device: prm@1b00 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x1b00 0x40>; - #reset-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/omap44xx-clocks.dtsi b/sys/gnu/dts/arm/omap44xx-clocks.dtsi index 532868591107..e9d9c8460682 100644 --- a/sys/gnu/dts/arm/omap44xx-clocks.dtsi +++ b/sys/gnu/dts/arm/omap44xx-clocks.dtsi @@ -1,1324 +1,1319 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP4 clock data * * Copyright (C) 2013 Texas Instruments, Inc. */ &cm1_clocks { extalt_clkin_ck: extalt_clkin_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <59000000>; }; pad_clks_src_ck: pad_clks_src_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <12000000>; }; pad_clks_ck: pad_clks_ck@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&pad_clks_src_ck>; ti,bit-shift = <8>; reg = <0x0108>; }; pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <12000000>; }; secure_32k_clk_src_ck: secure_32k_clk_src_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; slimbus_src_clk: slimbus_src_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <12000000>; }; slimbus_clk: slimbus_clk@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&slimbus_src_clk>; ti,bit-shift = <10>; reg = <0x0108>; }; sys_32k_ck: sys_32k_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; virt_12000000_ck: virt_12000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <12000000>; }; virt_13000000_ck: virt_13000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <13000000>; }; virt_16800000_ck: virt_16800000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <16800000>; }; virt_19200000_ck: virt_19200000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <19200000>; }; virt_26000000_ck: virt_26000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <26000000>; }; virt_27000000_ck: virt_27000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <27000000>; }; virt_38400000_ck: virt_38400000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <38400000>; }; tie_low_clock_ck: tie_low_clock_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; utmi_phy_clkout_ck: utmi_phy_clkout_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <60000000>; }; xclk60mhsp1_ck: xclk60mhsp1_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <60000000>; }; xclk60mhsp2_ck: xclk60mhsp2_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <60000000>; }; xclk60motg_ck: xclk60motg_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <60000000>; }; dpll_abe_ck: dpll_abe_ck@1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>; reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; }; dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_abe_ck>; reg = <0x01f0>; }; dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x01f0>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; abe_24m_fclk: abe_24m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_abe_m2x2_ck>; clock-mult = <1>; clock-div = <8>; }; abe_clk: abe_clk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2x2_ck>; ti,max-div = <4>; reg = <0x0108>; ti,index-power-of-two; }; dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x01f4>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x012c>; }; dpll_core_ck: dpll_core_ck@120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>; reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; }; dpll_core_x2_ck: dpll_core_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_core_ck>; }; dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0140>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_core_m2_ck: dpll_core_m2_ck@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0130>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; ddrphy_ck: ddrphy_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m2_ck>; clock-mult = <1>; clock-div = <2>; }; dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x013c>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; div_core_ck: div_core_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_m5x2_ck>; reg = <0x0100>; ti,max-div = <2>; }; div_iva_hs_clk: div_iva_hs_clk@1dc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_m5x2_ck>; ti,max-div = <4>; reg = <0x01dc>; ti,index-power-of-two; }; div_mpu_hs_clk: div_mpu_hs_clk@19c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_m5x2_ck>; ti,max-div = <4>; reg = <0x019c>; ti,index-power-of-two; }; dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0138>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dll_clk_div_ck: dll_clk_div_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m4x2_ck>; clock-mult = <1>; clock-div = <2>; }; dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_ck>; ti,max-div = <31>; reg = <0x01f0>; ti,index-starts-at-one; }; dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_x2_ck>; ti,bit-shift = <8>; reg = <0x0134>; }; dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; reg = <0x0134>; ti,index-starts-at-one; }; dpll_core_m3x2_ck: dpll_core_m3x2_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>; }; dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0144>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>; ti,bit-shift = <23>; reg = <0x01ac>; }; dpll_iva_ck: dpll_iva_ck@1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; assigned-clocks = <&dpll_iva_ck>; assigned-clock-rates = <931200000>; }; dpll_iva_x2_ck: dpll_iva_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_iva_ck>; }; dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x01b8>; ti,index-starts-at-one; ti,invert-autoidle-bit; assigned-clocks = <&dpll_iva_m4x2_ck>; assigned-clock-rates = <465600000>; }; dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x01bc>; ti,index-starts-at-one; ti,invert-autoidle-bit; assigned-clocks = <&dpll_iva_m5x2_ck>; assigned-clock-rates = <266100000>; }; dpll_mpu_ck: dpll_mpu_ck@160 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0170>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; per_hs_clk_div_ck: per_hs_clk_div_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <2>; }; usb_hs_clk_div_ck: usb_hs_clk_div_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <3>; }; l3_div_ck: l3_div_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&div_core_ck>; ti,bit-shift = <4>; ti,max-div = <2>; reg = <0x0100>; }; l4_div_ck: l4_div_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&l3_div_ck>; ti,bit-shift = <8>; ti,max-div = <2>; reg = <0x0100>; }; lp_clk_div_ck: lp_clk_div_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_abe_m2x2_ck>; clock-mult = <1>; clock-div = <16>; }; mpu_periphclk: mpu_periphclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_mpu_ck>; clock-mult = <1>; clock-div = <2>; }; ocp_abe_iclk: ocp_abe_iclk@528 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>; ti,bit-shift = <24>; reg = <0x0528>; ti,dividers = <2>, <1>; }; per_abe_24m_fclk: per_abe_24m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_abe_m2_ck>; clock-mult = <1>; clock-div = <4>; }; dummy_ck: dummy_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; }; &prm_clocks { sys_clkin_ck: sys_clkin_ck@110 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; reg = <0x0110>; ti,index-starts-at-one; }; abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; ti,bit-shift = <24>; reg = <0x0108>; }; abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; reg = <0x010c>; }; dbgclk_mux_ck: dbgclk_mux_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>; reg = <0x0108>; }; syc_clk_div_ck: syc_clk_div_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin_ck>; reg = <0x0100>; ti,max-div = <2>; }; usim_ck: usim_ck@1858 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_m4x2_ck>; ti,bit-shift = <24>; reg = <0x1858>; ti,dividers = <14>, <18>; }; usim_fclk: usim_fclk@1858 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&usim_ck>; ti,bit-shift = <8>; reg = <0x1858>; }; trace_clk_div_ck: trace_clk_div_ck { #clock-cells = <0>; compatible = "ti,clkdm-gate-clock"; clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>; }; }; &prm_clockdomains { emu_sys_clkdm: emu_sys_clkdm { compatible = "ti,clockdomain"; clocks = <&trace_clk_div_ck>; }; }; &cm2_clocks { per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>; ti,bit-shift = <23>; reg = <0x014c>; }; dpll_per_ck: dpll_per_ck@140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>; reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; }; dpll_per_m2_ck: dpll_per_m2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_ck>; ti,max-div = <31>; reg = <0x0150>; ti,index-starts-at-one; }; dpll_per_x2_ck: dpll_per_x2_ck@150 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_per_ck>; reg = <0x0150>; }; dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0150>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_per_x2_ck>; ti,bit-shift = <8>; reg = <0x0154>; }; dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; reg = <0x0154>; ti,index-starts-at-one; }; dpll_per_m3x2_ck: dpll_per_m3x2_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>; }; dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0158>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x015c>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0160>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; reg = <0x0164>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_usb_ck: dpll_usb_ck@180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>; reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; }; dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; clocks = <&dpll_usb_ck>; ti,clock-div = <1>; ti,autoidle-shift = <8>; reg = <0x01b4>; ti,clock-mult = <1>; ti,invert-autoidle-bit; }; dpll_usb_m2_ck: dpll_usb_m2_ck@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; reg = <0x0190>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; ducati_clk_mux_ck: ducati_clk_mux_ck@100 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>; reg = <0x0100>; }; func_12m_fclk: func_12m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <16>; }; func_24m_clk: func_24m_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; func_24mc_fclk: func_24mc_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <8>; }; func_48m_fclk: func_48m_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_m2x2_ck>; reg = <0x0108>; ti,dividers = <4>, <8>; }; func_48mc_fclk: func_48mc_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <4>; }; func_64m_fclk: func_64m_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_m4x2_ck>; reg = <0x0108>; ti,dividers = <2>, <4>; }; func_96m_fclk: func_96m_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_m2x2_ck>; reg = <0x0108>; ti,dividers = <2>, <4>; }; init_60m_fclk: init_60m_fclk@104 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_m2_ck>; reg = <0x0104>; ti,dividers = <1>, <8>; }; per_abe_nc_fclk: per_abe_nc_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2_ck>; reg = <0x0108>; ti,max-div = <2>; }; sha2md5_fck: sha2md5_fck@15c8 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3_div_ck>; ti,bit-shift = <1>; reg = <0x15c8>; }; usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0640>; }; }; &cm2_clockdomains { l3_init_clkdm: l3_init_clkdm { compatible = "ti,clockdomain"; clocks = <&dpll_usb_ck>; }; }; &scrm_clocks { auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0310>; }; auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0310>; }; auxclk0_src_ck: auxclk0_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; }; auxclk0_ck: auxclk0_ck@310 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk0_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; reg = <0x0310>; }; auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0314>; }; auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0314>; }; auxclk1_src_ck: auxclk1_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; }; auxclk1_ck: auxclk1_ck@314 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk1_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; reg = <0x0314>; }; auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0318>; }; auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0318>; }; auxclk2_src_ck: auxclk2_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; }; auxclk2_ck: auxclk2_ck@318 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk2_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; reg = <0x0318>; }; auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x031c>; }; auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x031c>; }; auxclk3_src_ck: auxclk3_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; }; auxclk3_ck: auxclk3_ck@31c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk3_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; reg = <0x031c>; }; auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0320>; }; auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0320>; }; auxclk4_src_ck: auxclk4_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; }; auxclk4_ck: auxclk4_ck@320 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk4_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; reg = <0x0320>; }; auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0324>; }; auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0324>; }; auxclk5_src_ck: auxclk5_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>; }; auxclk5_ck: auxclk5_ck@324 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk5_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; reg = <0x0324>; }; auxclkreq0_ck: auxclkreq0_ck@210 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0210>; }; auxclkreq1_ck: auxclkreq1_ck@214 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0214>; }; auxclkreq2_ck: auxclkreq2_ck@218 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0218>; }; auxclkreq3_ck: auxclkreq3_ck@21c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x021c>; }; auxclkreq4_ck: auxclkreq4_ck@220 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0220>; }; auxclkreq5_ck: auxclkreq5_ck@224 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0224>; }; }; &cm1 { mpuss_cm: mpuss_cm@300 { compatible = "ti,omap4-cm"; reg = <0x300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x300 0x100>; mpuss_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; tesla_cm: tesla_cm@400 { compatible = "ti,omap4-cm"; reg = <0x400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x400 0x100>; tesla_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; abe_cm: abe_cm@500 { compatible = "ti,omap4-cm"; reg = <0x500 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x500 0x100>; abe_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x6c>; #clock-cells = <2>; }; }; }; &cm2 { l4_ao_cm: l4_ao_cm@600 { compatible = "ti,omap4-cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x600 0x100>; l4_ao_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x1c>; #clock-cells = <2>; }; }; l3_1_cm: l3_1_cm@700 { compatible = "ti,omap4-cm"; reg = <0x700 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x700 0x100>; l3_1_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; l3_2_cm: l3_2_cm@800 { compatible = "ti,omap4-cm"; reg = <0x800 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x800 0x100>; l3_2_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x14>; #clock-cells = <2>; }; }; ducati_cm: ducati_cm@900 { compatible = "ti,omap4-cm"; reg = <0x900 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x900 0x100>; ducati_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; l3_dma_cm: l3_dma_cm@a00 { compatible = "ti,omap4-cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xa00 0x100>; l3_dma_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; l3_emif_cm: l3_emif_cm@b00 { compatible = "ti,omap4-cm"; reg = <0xb00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xb00 0x100>; l3_emif_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x1c>; #clock-cells = <2>; }; }; d2d_cm: d2d_cm@c00 { compatible = "ti,omap4-cm"; reg = <0xc00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xc00 0x100>; d2d_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; l4_cfg_cm: l4_cfg_cm@d00 { compatible = "ti,omap4-cm"; reg = <0xd00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xd00 0x100>; l4_cfg_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x14>; #clock-cells = <2>; }; }; l3_instr_cm: l3_instr_cm@e00 { compatible = "ti,omap4-cm"; reg = <0xe00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xe00 0x100>; l3_instr_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x24>; #clock-cells = <2>; }; }; ivahd_cm: ivahd_cm@f00 { compatible = "ti,omap4-cm"; reg = <0xf00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xf00 0x100>; ivahd_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; }; iss_cm: iss_cm@1000 { compatible = "ti,omap4-cm"; reg = <0x1000 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1000 0x100>; iss_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; }; l3_dss_cm: l3_dss_cm@1100 { compatible = "ti,omap4-cm"; reg = <0x1100 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1100 0x100>; l3_dss_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; l3_gfx_cm: l3_gfx_cm@1200 { compatible = "ti,omap4-cm"; reg = <0x1200 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1200 0x100>; l3_gfx_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; l3_init_cm: l3_init_cm@1300 { compatible = "ti,omap4-cm"; reg = <0x1300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1300 0x100>; l3_init_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0xc4>; #clock-cells = <2>; }; }; l4_per_cm: l4_per_cm@1400 { compatible = "ti,omap4-cm"; reg = <0x1400 0x200>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1400 0x200>; - l4_per_clkctrl: clock@20 { - compatible = "ti,clkctrl-l4-per", "ti,clkctrl"; + l4_per_clkctrl: clk@20 { + compatible = "ti,clkctrl"; reg = <0x20 0x144>; #clock-cells = <2>; }; - - l4_secure_clkctrl: clock@1a0 { - compatible = "ti,clkctrl-l4-secure", "ti,clkctrl"; - reg = <0x1a0 0x3c>; - #clock-cells = <2>; - }; }; + }; &prm { l4_wkup_cm: l4_wkup_cm@1800 { compatible = "ti,omap4-cm"; reg = <0x1800 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1800 0x100>; l4_wkup_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x5c>; #clock-cells = <2>; }; }; emu_sys_cm: emu_sys_cm@1a00 { compatible = "ti,omap4-cm"; reg = <0x1a00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1a00 0x100>; emu_sys_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; }; diff --git a/sys/gnu/dts/arm/omap5-l4-abe.dtsi b/sys/gnu/dts/arm/omap5-l4-abe.dtsi index 4ec7909df78b..dc9d0532f4cf 100644 --- a/sys/gnu/dts/arm/omap5-l4-abe.dtsi +++ b/sys/gnu/dts/arm/omap5-l4-abe.dtsi @@ -1,438 +1,447 @@ &l4_abe { /* 0x40100000 */ compatible = "ti,omap5-l4-abe", "simple-bus"; reg = <0x40100000 0x400>, <0x40100400 0x400>; reg-names = "la", "ap"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ <0x49000000 0x49000000 0x100000>; segment@0 { /* 0x40100000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = /* CPU to L4 ABE mapping */ <0x00000000 0x00000000 0x000400>, /* ap 0 */ <0x00000400 0x00000400 0x000400>, /* ap 1 */ <0x00022000 0x00022000 0x001000>, /* ap 2 */ <0x00023000 0x00023000 0x001000>, /* ap 3 */ <0x00024000 0x00024000 0x001000>, /* ap 4 */ <0x00025000 0x00025000 0x001000>, /* ap 5 */ <0x00026000 0x00026000 0x001000>, /* ap 6 */ <0x00027000 0x00027000 0x001000>, /* ap 7 */ <0x00028000 0x00028000 0x001000>, /* ap 8 */ <0x00029000 0x00029000 0x001000>, /* ap 9 */ <0x0002a000 0x0002a000 0x001000>, /* ap 10 */ <0x0002b000 0x0002b000 0x001000>, /* ap 11 */ <0x0002e000 0x0002e000 0x001000>, /* ap 12 */ <0x0002f000 0x0002f000 0x001000>, /* ap 13 */ <0x00030000 0x00030000 0x001000>, /* ap 14 */ <0x00031000 0x00031000 0x001000>, /* ap 15 */ <0x00032000 0x00032000 0x001000>, /* ap 16 */ <0x00033000 0x00033000 0x001000>, /* ap 17 */ <0x00038000 0x00038000 0x001000>, /* ap 18 */ <0x00039000 0x00039000 0x001000>, /* ap 19 */ <0x0003a000 0x0003a000 0x001000>, /* ap 20 */ <0x0003b000 0x0003b000 0x001000>, /* ap 21 */ <0x0003c000 0x0003c000 0x001000>, /* ap 22 */ <0x0003d000 0x0003d000 0x001000>, /* ap 23 */ <0x0003e000 0x0003e000 0x001000>, /* ap 24 */ <0x0003f000 0x0003f000 0x001000>, /* ap 25 */ <0x00080000 0x00080000 0x010000>, /* ap 26 */ <0x00080000 0x00080000 0x001000>, /* ap 27 */ <0x000a0000 0x000a0000 0x010000>, /* ap 28 */ <0x000a0000 0x000a0000 0x001000>, /* ap 29 */ <0x000c0000 0x000c0000 0x010000>, /* ap 30 */ <0x000c0000 0x000c0000 0x001000>, /* ap 31 */ <0x000f1000 0x000f1000 0x001000>, /* ap 32 */ <0x000f2000 0x000f2000 0x001000>, /* ap 33 */ /* L3 to L4 ABE mapping */ <0x49000000 0x49000000 0x000400>, /* ap 0 */ <0x49000400 0x49000400 0x000400>, /* ap 1 */ <0x49022000 0x49022000 0x001000>, /* ap 2 */ <0x49023000 0x49023000 0x001000>, /* ap 3 */ <0x49024000 0x49024000 0x001000>, /* ap 4 */ <0x49025000 0x49025000 0x001000>, /* ap 5 */ <0x49026000 0x49026000 0x001000>, /* ap 6 */ <0x49027000 0x49027000 0x001000>, /* ap 7 */ <0x49028000 0x49028000 0x001000>, /* ap 8 */ <0x49029000 0x49029000 0x001000>, /* ap 9 */ <0x4902a000 0x4902a000 0x001000>, /* ap 10 */ <0x4902b000 0x4902b000 0x001000>, /* ap 11 */ <0x4902e000 0x4902e000 0x001000>, /* ap 12 */ <0x4902f000 0x4902f000 0x001000>, /* ap 13 */ <0x49030000 0x49030000 0x001000>, /* ap 14 */ <0x49031000 0x49031000 0x001000>, /* ap 15 */ <0x49032000 0x49032000 0x001000>, /* ap 16 */ <0x49033000 0x49033000 0x001000>, /* ap 17 */ <0x49038000 0x49038000 0x001000>, /* ap 18 */ <0x49039000 0x49039000 0x001000>, /* ap 19 */ <0x4903a000 0x4903a000 0x001000>, /* ap 20 */ <0x4903b000 0x4903b000 0x001000>, /* ap 21 */ <0x4903c000 0x4903c000 0x001000>, /* ap 22 */ <0x4903d000 0x4903d000 0x001000>, /* ap 23 */ <0x4903e000 0x4903e000 0x001000>, /* ap 24 */ <0x4903f000 0x4903f000 0x001000>, /* ap 25 */ <0x49080000 0x49080000 0x010000>, /* ap 26 */ <0x49080000 0x49080000 0x001000>, /* ap 27 */ <0x490a0000 0x490a0000 0x010000>, /* ap 28 */ <0x490a0000 0x490a0000 0x001000>, /* ap 29 */ <0x490c0000 0x490c0000 0x010000>, /* ap 30 */ <0x490c0000 0x490c0000 0x001000>, /* ap 31 */ <0x490f1000 0x490f1000 0x001000>, /* ap 32 */ <0x490f2000 0x490f2000 0x001000>; /* ap 33 */ target-module@22000 { /* 0x40122000, ap 2 02.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mcbsp1"; reg = <0x2208c 0x4>; reg-names = "sysc"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = , , ; /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x22000 0x1000>, <0x49022000 0x49022000 0x1000>; mcbsp1: mcbsp@0 { compatible = "ti,omap4-mcbsp"; reg = <0x0 0xff>, /* MPU private access */ <0x49022000 0xff>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = ; interrupt-names = "common"; ti,buffer-size = <128>; dmas = <&sdma 33>, <&sdma 34>; dma-names = "tx", "rx"; status = "disabled"; }; }; target-module@24000 { /* 0x40124000, ap 4 04.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mcbsp2"; reg = <0x2408c 0x4>; reg-names = "sysc"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = , , ; /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x24000 0x1000>, <0x49024000 0x49024000 0x1000>; mcbsp2: mcbsp@0 { compatible = "ti,omap4-mcbsp"; reg = <0x0 0xff>, /* MPU private access */ <0x49024000 0xff>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = ; interrupt-names = "common"; ti,buffer-size = <128>; dmas = <&sdma 17>, <&sdma 18>; dma-names = "tx", "rx"; status = "disabled"; }; }; target-module@26000 { /* 0x40126000, ap 6 06.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mcbsp3"; reg = <0x2608c 0x4>; reg-names = "sysc"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = , , ; /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x26000 0x1000>, <0x49026000 0x49026000 0x1000>; mcbsp3: mcbsp@0 { compatible = "ti,omap4-mcbsp"; reg = <0x0 0xff>, /* MPU private access */ <0x49026000 0xff>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = ; interrupt-names = "common"; ti,buffer-size = <128>; dmas = <&sdma 19>, <&sdma 20>; dma-names = "tx", "rx"; status = "disabled"; }; }; target-module@28000 { /* 0x40128000, ap 8 08.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x28000 0x1000>, <0x49028000 0x49028000 0x1000>; }; target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2a000 0x1000>, <0x4902a000 0x4902a000 0x1000>; }; target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "dmic"; reg = <0x2e000 0x4>, <0x2e010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2e000 0x1000>, <0x4902e000 0x4902e000 0x1000>; dmic: dmic@0 { compatible = "ti,omap4-dmic"; reg = <0x0 0x7f>, /* MPU private access */ <0x4902e000 0x7f>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = ; dmas = <&sdma 67>; dma-names = "up_link"; status = "disabled"; }; }; target-module@30000 { /* 0x40130000, ap 14 0e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x30000 0x1000>, <0x49030000 0x49030000 0x1000>; }; mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcpdm"; reg = <0x32000 0x4>, <0x32010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x32000 0x1000>, <0x49032000 0x49032000 0x1000>; /* Must be only enabled for boards with pdmclk wired */ status = "disabled"; mcpdm: mcpdm@0 { compatible = "ti,omap4-mcpdm"; reg = <0x0 0x7f>, /* MPU private access */ <0x49032000 0x7f>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = ; dmas = <&sdma 65>, <&sdma 66>; dma-names = "up_link", "dn_link"; }; }; target-module@38000 { /* 0x40138000, ap 18 12.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer5"; reg = <0x38000 0x4>, <0x38010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x38000 0x1000>, <0x49038000 0x49038000 0x1000>; timer5: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>, <0x49038000 0x80>; clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>; clock-names = "fck"; interrupts = ; ti,timer-dsp; ti,timer-pwm; }; }; target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer6"; reg = <0x3a000 0x4>, <0x3a010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3a000 0x1000>, <0x4903a000 0x4903a000 0x1000>; timer6: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>, <0x4903a000 0x80>; clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>; clock-names = "fck"; interrupts = ; ti,timer-dsp; ti,timer-pwm; }; }; target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer7"; reg = <0x3c000 0x4>, <0x3c010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3c000 0x1000>, <0x4903c000 0x4903c000 0x1000>; timer7: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>, <0x4903c000 0x80>; clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>; clock-names = "fck"; interrupts = ; ti,timer-dsp; }; }; target-module@3e000 { /* 0x4013e000, ap 24 18.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer8"; reg = <0x3e000 0x4>, <0x3e010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3e000 0x1000>, <0x4903e000 0x4903e000 0x1000>; timer8: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>, <0x4903e000 0x80>; clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>; clock-names = "fck"; interrupts = ; ti,timer-dsp; ti,timer-pwm; }; }; target-module@80000 { /* 0x40180000, ap 26 1a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000 0x10000>, <0x49080000 0x49080000 0x10000>; }; target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa0000 0x10000>, <0x490a0000 0x490a0000 0x10000>; }; target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc0000 0x10000>, <0x490c0000 0x490c0000 0x10000>; }; target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xf1000 0x1000>, <0x490f1000 0x490f1000 0x1000>; }; }; }; diff --git a/sys/gnu/dts/arm/omap5-l4.dtsi b/sys/gnu/dts/arm/omap5-l4.dtsi index f68740abb8aa..0960348002ad 100644 --- a/sys/gnu/dts/arm/omap5-l4.dtsi +++ b/sys/gnu/dts/arm/omap5-l4.dtsi @@ -1,2438 +1,2460 @@ &l4_cfg { /* 0x4a000000 */ compatible = "ti,omap5-l4-cfg", "simple-bus"; reg = <0x4a000000 0x800>, <0x4a000800 0x800>, <0x4a001000 0x1000>; reg-names = "ap", "la", "ia0"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ <0x00080000 0x4a080000 0x080000>, /* segment 1 */ <0x00100000 0x4a100000 0x080000>, /* segment 2 */ <0x00180000 0x4a180000 0x080000>, /* segment 3 */ <0x00200000 0x4a200000 0x080000>, /* segment 4 */ <0x00280000 0x4a280000 0x080000>, /* segment 5 */ <0x00300000 0x4a300000 0x080000>; /* segment 6 */ segment@0 { /* 0x4a000000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00001000 0x00001000 0x001000>, /* ap 1 */ <0x00000800 0x00000800 0x000800>, /* ap 2 */ <0x00002000 0x00002000 0x001000>, /* ap 3 */ <0x00003000 0x00003000 0x001000>, /* ap 4 */ <0x00004000 0x00004000 0x001000>, /* ap 5 */ <0x00005000 0x00005000 0x001000>, /* ap 6 */ <0x00056000 0x00056000 0x001000>, /* ap 7 */ <0x00057000 0x00057000 0x001000>, /* ap 8 */ <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ <0x00058000 0x00058000 0x001000>, /* ap 10 */ <0x00062000 0x00062000 0x001000>, /* ap 11 */ <0x00063000 0x00063000 0x001000>, /* ap 12 */ <0x00008000 0x00008000 0x002000>, /* ap 21 */ <0x0000a000 0x0000a000 0x001000>, /* ap 22 */ <0x00066000 0x00066000 0x001000>, /* ap 23 */ <0x00067000 0x00067000 0x001000>, /* ap 24 */ <0x0005e000 0x0005e000 0x002000>, /* ap 69 */ <0x00060000 0x00060000 0x001000>, /* ap 70 */ <0x00064000 0x00064000 0x001000>, /* ap 71 */ <0x00065000 0x00065000 0x001000>, /* ap 72 */ <0x0005a000 0x0005a000 0x001000>, /* ap 77 */ <0x0005b000 0x0005b000 0x001000>, /* ap 78 */ <0x00070000 0x00070000 0x004000>, /* ap 79 */ <0x00074000 0x00074000 0x001000>, /* ap 80 */ <0x00075000 0x00075000 0x001000>, /* ap 81 */ <0x00076000 0x00076000 0x001000>, /* ap 82 */ <0x00020000 0x00020000 0x020000>, /* ap 109 */ <0x00040000 0x00040000 0x001000>, /* ap 110 */ <0x00059000 0x00059000 0x001000>; /* ap 111 */ target-module@2000 { /* 0x4a002000, ap 3 44.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x2000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x1000>; scm_core: scm@0 { compatible = "ti,omap5-scm-core", "simple-bus"; reg = <0x0 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x800>; scm_conf: scm_conf@0 { compatible = "syscon"; reg = <0x0 0x800>; #address-cells = <1>; #size-cells = <1>; }; }; scm_padconf_core: scm@800 { compatible = "ti,omap5-scm-padconf-core", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x800 0x800>; omap5_pmx_core: pinmux@40 { compatible = "ti,omap5-padconf", "pinctrl-single"; reg = <0x40 0x01b6>; #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x7fff>; }; omap5_padconf_global: omap5_padconf_global@5a0 { compatible = "syscon", "simple-bus"; reg = <0x5a0 0xec>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x5a0 0xec>; pbias_regulator: pbias_regulator@60 { compatible = "ti,pbias-omap5", "ti,pbias-omap"; reg = <0x60 0x4>; syscon = <&omap5_padconf_global>; pbias_mmc_reg: pbias_mmc_omap5 { regulator-name = "pbias_mmc_omap5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; }; }; }; }; target-module@4000 { /* 0x4a004000, ap 5 5c.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x4000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; cm_core_aon: cm_core_aon@0 { compatible = "ti,omap5-cm-core-aon", "simple-bus"; reg = <0x0 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x1000>; cm_core_aon_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; cm_core_aon_clockdomains: clockdomains { }; }; }; target-module@8000 { /* 0x4a008000, ap 21 4c.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x8000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x2000>; cm_core: cm_core@0 { compatible = "ti,omap5-cm-core", "simple-bus"; reg = <0x0 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x2000>; cm_core_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; cm_core_clockdomains: clockdomains { }; }; }; target-module@20000 { /* 0x4a020000, ap 109 08.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "usb_otg_ss"; reg = <0x20000 0x4>, <0x20010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x20000>; usb3: omap_dwc3@0 { compatible = "ti,dwc3"; reg = <0x0 0x10000>; interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; ranges = <0 0 0x20000>; dwc3: dwc3@10000 { compatible = "snps,dwc3"; reg = <0x10000 0x10000>; interrupts = , , ; interrupt-names = "peripheral", "host", "otg"; phys = <&usb2_phy>, <&usb3_phy>; phy-names = "usb2-phy", "usb3-phy"; dr_mode = "peripheral"; }; }; }; target-module@56000 { /* 0x4a056000, ap 7 02.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "dma_system"; reg = <0x56000 0x4>, <0x5602c 0x4>, <0x56028 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-midle = , , ; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */ clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x56000 0x1000>; sdma: dma-controller@0 { - compatible = "ti,omap4430-sdma", "ti,omap-sdma"; + compatible = "ti,omap4430-sdma"; reg = <0x0 0x1000>; interrupts = , , , ; #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; }; }; target-module@58000 { /* 0x4a058000, ap 10 06.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00058000 0x00001000>, <0x00001000 0x00059000 0x00001000>, <0x00002000 0x0005a000 0x00001000>, <0x00003000 0x0005b000 0x00001000>; }; target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5e000 0x2000>; }; target-module@62000 { /* 0x4a062000, ap 11 0e.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "usb_tll_hs"; reg = <0x62000 0x4>, <0x62010 0x4>, <0x62014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x62000 0x1000>; usbhstll: usbhstll@0 { compatible = "ti,usbhs-tll"; reg = <0x0 0x1000>; interrupts = ; }; }; target-module@64000 { /* 0x4a064000, ap 71 1e.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "usb_host_hs"; reg = <0x64000 0x4>, <0x64010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x64000 0x1000>; usbhshost: usbhshost@0 { compatible = "ti,usbhs-host"; reg = <0x0 0x800>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x1000>; clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>, <&xclk60mhsp2_ck>; clock-names = "refclk_60m_int", "refclk_60m_ext_p1", "refclk_60m_ext_p2"; usbhsohci: ohci@800 { compatible = "ti,ohci-omap3"; reg = <0x800 0x400>; interrupts = ; remote-wakeup-connected; }; usbhsehci: ehci@c00 { compatible = "ti,ehci-omap"; reg = <0xc00 0x400>; interrupts = ; }; }; }; target-module@66000 { /* 0x4a066000, ap 23 0a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mmu_dsp"; reg = <0x66000 0x4>, <0x66010 0x4>, <0x66014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */ clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; clock-names = "fck"; - resets = <&prm_dsp 1>; - reset-names = "rstctrl"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x66000 0x1000>; - mmu_dsp: mmu@0 { - compatible = "ti,omap4-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - }; + /* mmu_dsp cannot be moved before reset driver */ + status = "disabled"; }; target-module@70000 { /* 0x4a070000, ap 79 2e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x70000 0x4000>; }; target-module@75000 { /* 0x4a075000, ap 81 32.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x75000 0x1000>; }; }; segment@80000 { /* 0x4a080000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ <0x0005a000 0x000da000 0x001000>, /* ap 14 */ <0x0005b000 0x000db000 0x001000>, /* ap 15 */ <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ <0x0005e000 0x000de000 0x001000>, /* ap 18 */ <0x00060000 0x000e0000 0x001000>, /* ap 19 */ <0x00061000 0x000e1000 0x001000>, /* ap 20 */ <0x00074000 0x000f4000 0x001000>, /* ap 25 */ <0x00075000 0x000f5000 0x001000>, /* ap 26 */ <0x00076000 0x000f6000 0x001000>, /* ap 27 */ <0x00077000 0x000f7000 0x001000>, /* ap 28 */ <0x00036000 0x000b6000 0x001000>, /* ap 65 */ <0x00037000 0x000b7000 0x001000>, /* ap 66 */ <0x0004d000 0x000cd000 0x001000>, /* ap 67 */ <0x0004e000 0x000ce000 0x001000>, /* ap 68 */ <0x00000000 0x00080000 0x004000>, /* ap 83 */ <0x00004000 0x00084000 0x001000>, /* ap 84 */ <0x00005000 0x00085000 0x001000>, /* ap 85 */ <0x00006000 0x00086000 0x001000>, /* ap 86 */ <0x00007000 0x00087000 0x001000>, /* ap 87 */ <0x00008000 0x00088000 0x001000>, /* ap 88 */ <0x00010000 0x00090000 0x004000>, /* ap 89 */ <0x00014000 0x00094000 0x001000>, /* ap 90 */ <0x00015000 0x00095000 0x001000>, /* ap 91 */ <0x00016000 0x00096000 0x001000>, /* ap 92 */ <0x00017000 0x00097000 0x001000>, /* ap 93 */ <0x00018000 0x00098000 0x001000>, /* ap 94 */ <0x00020000 0x000a0000 0x004000>, /* ap 95 */ <0x00024000 0x000a4000 0x001000>, /* ap 96 */ <0x00025000 0x000a5000 0x001000>, /* ap 97 */ <0x00026000 0x000a6000 0x001000>, /* ap 98 */ <0x00027000 0x000a7000 0x001000>, /* ap 99 */ <0x00028000 0x000a8000 0x001000>; /* ap 100 */ target-module@0 { /* 0x4a080000, ap 83 28.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "ocp2scp1"; reg = <0x0 0x4>, <0x10 0x4>, <0x14 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x00004000>, <0x00004000 0x00004000 0x00001000>, <0x00005000 0x00005000 0x00001000>, <0x00006000 0x00006000 0x00001000>, <0x00007000 0x00007000 0x00001000>; ocp2scp@0 { compatible = "ti,omap-ocp2scp"; #address-cells = <1>; #size-cells = <1>; reg = <0 0x20>; }; usb2_phy: usb2phy@4000 { compatible = "ti,omap-usb2"; reg = <0x4000 0x7c>; syscon-phy-power = <&scm_conf 0x300>; clocks = <&usb_phy_cm_clk32k>, <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; }; usb3_phy: usb3phy@4400 { compatible = "ti,omap-usb3"; reg = <0x4400 0x80>, <0x4800 0x64>, <0x4c00 0x40>; reg-names = "phy_rx", "phy_tx", "pll_ctrl"; syscon-phy-power = <&scm_conf 0x370>; clocks = <&usb_phy_cm_clk32k>, <&sys_clkin>, <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; clock-names = "wkupclk", "sysclk", "refclk"; #phy-cells = <0>; }; }; target-module@10000 { /* 0x4a090000, ap 89 36.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "ocp2scp3"; reg = <0x10000 0x4>, <0x10010 0x4>, <0x10014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00010000 0x00004000>, <0x00004000 0x00014000 0x00001000>, <0x00005000 0x00015000 0x00001000>, <0x00006000 0x00016000 0x00001000>, <0x00007000 0x00017000 0x00001000>; ocp2scp@0 { compatible = "ti,omap-ocp2scp"; #address-cells = <1>; #size-cells = <1>; reg = <0x0 0x20>; }; sata_phy: phy@6000 { compatible = "ti,phy-pipe3-sata"; reg = <0x6000 0x80>, /* phy_rx */ <0x6400 0x64>, /* phy_tx */ <0x6800 0x40>; /* pll_ctrl */ reg-names = "phy_rx", "phy_tx", "pll_ctrl"; syscon-phy-power = <&scm_conf 0x374>; clocks = <&sys_clkin>, <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; clock-names = "sysclk", "refclk"; #phy-cells = <0>; }; }; target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00020000 0x00004000>, <0x00004000 0x00024000 0x00001000>, <0x00005000 0x00025000 0x00001000>, <0x00006000 0x00026000 0x00001000>, <0x00007000 0x00027000 0x00001000>; }; target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x36000 0x1000>; }; target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4d000 0x1000>; }; target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x59000 0x1000>; }; target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5b000 0x1000>; }; target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5d000 0x1000>; }; target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x60000 0x1000>; }; target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox"; reg = <0x74000 0x4>, <0x74010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = ; ti,sysc-sidle = , , ; /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x74000 0x1000>; mailbox: mailbox@0 { compatible = "ti,omap4-mailbox"; reg = <0x0 0x200>; interrupts = ; #mbox-cells = <1>; ti,mbox-num-users = <3>; ti,mbox-num-fifos = <8>; mbox_ipu: mbox_ipu { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; mbox_dsp: mbox_dsp { ti,mbox-tx = <3 0 0>; ti,mbox-rx = <2 0 0>; }; }; }; target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spinlock"; reg = <0x76000 0x4>, <0x76010 0x4>, <0x76014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x76000 0x1000>; hwspinlock: spinlock@0 { compatible = "ti,omap4-hwspinlock"; reg = <0x0 0x1000>; #hwlock-cells = <1>; }; }; }; segment@100000 { /* 0x4a100000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */ <0x00003000 0x00103000 0x001000>, /* ap 60 */ <0x00008000 0x00108000 0x001000>, /* ap 61 */ <0x00009000 0x00109000 0x001000>, /* ap 62 */ <0x0000a000 0x0010a000 0x001000>, /* ap 63 */ <0x0000b000 0x0010b000 0x001000>, /* ap 64 */ <0x00040000 0x00140000 0x010000>, /* ap 101 */ <0x00050000 0x00150000 0x001000>; /* ap 102 */ target-module@2000 { /* 0x4a102000, ap 59 2c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x1000>; }; target-module@8000 { /* 0x4a108000, ap 61 26.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x1000>; }; target-module@a000 { /* 0x4a10a000, ap 63 22.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa000 0x1000>; }; target-module@40000 { /* 0x4a140000, ap 101 16.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x40000 0x10000>; }; }; segment@180000 { /* 0x4a180000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; }; segment@200000 { /* 0x4a200000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */ <0x0001f000 0x0021f000 0x001000>, /* ap 30 */ <0x0000a000 0x0020a000 0x001000>, /* ap 31 */ <0x0000b000 0x0020b000 0x001000>, /* ap 32 */ <0x00006000 0x00206000 0x001000>, /* ap 33 */ <0x00007000 0x00207000 0x001000>, /* ap 34 */ <0x00004000 0x00204000 0x001000>, /* ap 35 */ <0x00005000 0x00205000 0x001000>, /* ap 36 */ <0x00012000 0x00212000 0x001000>, /* ap 37 */ <0x00013000 0x00213000 0x001000>, /* ap 38 */ <0x0000c000 0x0020c000 0x001000>, /* ap 39 */ <0x0000d000 0x0020d000 0x001000>, /* ap 40 */ <0x00010000 0x00210000 0x001000>, /* ap 41 */ <0x00011000 0x00211000 0x001000>, /* ap 42 */ <0x00016000 0x00216000 0x001000>, /* ap 43 */ <0x00017000 0x00217000 0x001000>, /* ap 44 */ <0x00014000 0x00214000 0x001000>, /* ap 45 */ <0x00015000 0x00215000 0x001000>, /* ap 46 */ <0x00018000 0x00218000 0x001000>, /* ap 47 */ <0x00019000 0x00219000 0x001000>, /* ap 48 */ <0x00020000 0x00220000 0x001000>, /* ap 49 */ <0x00021000 0x00221000 0x001000>, /* ap 50 */ <0x00026000 0x00226000 0x001000>, /* ap 51 */ <0x00027000 0x00227000 0x001000>, /* ap 52 */ <0x00028000 0x00228000 0x001000>, /* ap 53 */ <0x00029000 0x00229000 0x001000>, /* ap 54 */ <0x0002a000 0x0022a000 0x001000>, /* ap 55 */ <0x0002b000 0x0022b000 0x001000>, /* ap 56 */ <0x0001c000 0x0021c000 0x001000>, /* ap 57 */ <0x0001d000 0x0021d000 0x001000>, /* ap 58 */ <0x0001a000 0x0021a000 0x001000>, /* ap 73 */ <0x0001b000 0x0021b000 0x001000>, /* ap 74 */ <0x00024000 0x00224000 0x001000>, /* ap 75 */ <0x00025000 0x00225000 0x001000>, /* ap 76 */ <0x00002000 0x00202000 0x001000>, /* ap 103 */ <0x00003000 0x00203000 0x001000>, /* ap 104 */ <0x00008000 0x00208000 0x001000>, /* ap 105 */ <0x00009000 0x00209000 0x001000>, /* ap 106 */ <0x00022000 0x00222000 0x001000>, /* ap 107 */ <0x00023000 0x00223000 0x001000>; /* ap 108 */ target-module@2000 { /* 0x4a202000, ap 103 3c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x1000>; }; target-module@4000 { /* 0x4a204000, ap 35 46.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; }; target-module@6000 { /* 0x4a206000, ap 33 4e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6000 0x1000>; }; target-module@8000 { /* 0x4a208000, ap 105 34.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x1000>; }; target-module@a000 { /* 0x4a20a000, ap 31 30.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa000 0x1000>; }; target-module@c000 { /* 0x4a20c000, ap 39 14.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc000 0x1000>; }; target-module@10000 { /* 0x4a210000, ap 41 56.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x10000 0x1000>; }; target-module@12000 { /* 0x4a212000, ap 37 52.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x12000 0x1000>; }; target-module@14000 { /* 0x4a214000, ap 45 1c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x14000 0x1000>; }; target-module@16000 { /* 0x4a216000, ap 43 42.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x16000 0x1000>; }; target-module@18000 { /* 0x4a218000, ap 47 1a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x18000 0x1000>; }; target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1a000 0x1000>; }; target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1c000 0x1000>; }; target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1e000 0x1000>; }; target-module@20000 { /* 0x4a220000, ap 49 4a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x1000>; }; target-module@22000 { /* 0x4a222000, ap 107 3a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x22000 0x1000>; }; target-module@24000 { /* 0x4a224000, ap 75 48.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x24000 0x1000>; }; target-module@26000 { /* 0x4a226000, ap 51 24.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x26000 0x1000>; }; target-module@28000 { /* 0x4a228000, ap 53 38.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x28000 0x1000>; }; target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2a000 0x1000>; }; }; segment@280000 { /* 0x4a280000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; }; segment@300000 { /* 0x4a300000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; }; }; &l4_per { /* 0x48000000 */ compatible = "ti,omap5-l4-per", "simple-bus"; reg = <0x48000000 0x800>, <0x48000800 0x800>, <0x48001000 0x400>, <0x48001400 0x400>, <0x48001800 0x400>, <0x48001c00 0x400>; reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ <0x00200000 0x48200000 0x200000>; /* segment 1 */ segment@0 { /* 0x48000000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00001000 0x00001000 0x000400>, /* ap 1 */ <0x00000800 0x00000800 0x000800>, /* ap 2 */ <0x00020000 0x00020000 0x001000>, /* ap 3 */ <0x00021000 0x00021000 0x001000>, /* ap 4 */ <0x00032000 0x00032000 0x001000>, /* ap 5 */ <0x00033000 0x00033000 0x001000>, /* ap 6 */ <0x00034000 0x00034000 0x001000>, /* ap 7 */ <0x00035000 0x00035000 0x001000>, /* ap 8 */ <0x00036000 0x00036000 0x001000>, /* ap 9 */ <0x00037000 0x00037000 0x001000>, /* ap 10 */ <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ <0x00055000 0x00055000 0x001000>, /* ap 13 */ <0x00056000 0x00056000 0x001000>, /* ap 14 */ <0x00057000 0x00057000 0x001000>, /* ap 15 */ <0x00058000 0x00058000 0x001000>, /* ap 16 */ <0x00059000 0x00059000 0x001000>, /* ap 17 */ <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ <0x00060000 0x00060000 0x001000>, /* ap 23 */ <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ <0x00070000 0x00070000 0x001000>, /* ap 30 */ <0x00071000 0x00071000 0x001000>, /* ap 31 */ <0x00072000 0x00072000 0x001000>, /* ap 32 */ <0x00073000 0x00073000 0x001000>, /* ap 33 */ <0x00061000 0x00061000 0x001000>, /* ap 34 */ <0x00053000 0x00053000 0x001000>, /* ap 35 */ <0x00054000 0x00054000 0x001000>, /* ap 36 */ <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ <0x00078000 0x00078000 0x001000>, /* ap 39 */ <0x00079000 0x00079000 0x001000>, /* ap 40 */ <0x00086000 0x00086000 0x001000>, /* ap 41 */ <0x00087000 0x00087000 0x001000>, /* ap 42 */ <0x00088000 0x00088000 0x001000>, /* ap 43 */ <0x00089000 0x00089000 0x001000>, /* ap 44 */ <0x00051000 0x00051000 0x001000>, /* ap 45 */ <0x00052000 0x00052000 0x001000>, /* ap 46 */ <0x00098000 0x00098000 0x001000>, /* ap 47 */ <0x00099000 0x00099000 0x001000>, /* ap 48 */ <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ <0x00068000 0x00068000 0x001000>, /* ap 53 */ <0x00069000 0x00069000 0x001000>, /* ap 54 */ <0x00090000 0x00090000 0x002000>, /* ap 55 */ <0x00092000 0x00092000 0x001000>, /* ap 56 */ <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ <0x00066000 0x00066000 0x001000>, /* ap 63 */ <0x00067000 0x00067000 0x001000>, /* ap 64 */ <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ <0x00001400 0x00001400 0x000400>, /* ap 77 */ <0x00001800 0x00001800 0x000400>, /* ap 78 */ <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ target-module@20000 { /* 0x48020000, ap 3 04.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart3"; reg = <0x20050 0x4>, <0x20054 0x4>, <0x20058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x1000>; uart3: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; }; }; target-module@32000 { /* 0x48032000, ap 5 3e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer2"; reg = <0x32000 0x4>, <0x32010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x32000 0x1000>; timer2: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>; clock-names = "fck"; interrupts = ; }; }; target-module@34000 { /* 0x48034000, ap 7 46.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer3"; reg = <0x34000 0x4>, <0x34010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x34000 0x1000>; timer3: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>; clock-names = "fck"; interrupts = ; }; }; target-module@36000 { /* 0x48036000, ap 9 4e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer4"; reg = <0x36000 0x4>, <0x36010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x36000 0x1000>; timer4: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>; clock-names = "fck"; interrupts = ; }; }; target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer9"; reg = <0x3e000 0x4>, <0x3e010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3e000 0x1000>; timer9: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>; clock-names = "fck"; interrupts = ; ti,timer-pwm; }; }; target-module@51000 { /* 0x48051000, ap 45 2e.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio7"; reg = <0x51000 0x4>, <0x51010 0x4>, <0x51114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>, <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x51000 0x1000>; gpio7: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@53000 { /* 0x48053000, ap 35 36.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio8"; reg = <0x53000 0x4>, <0x53010 0x4>, <0x53114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>, <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x53000 0x1000>; gpio8: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@55000 { /* 0x48055000, ap 13 0e.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio2"; reg = <0x55000 0x4>, <0x55010 0x4>, <0x55114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>, <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x55000 0x1000>; gpio2: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@57000 { /* 0x48057000, ap 15 06.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio3"; reg = <0x57000 0x4>, <0x57010 0x4>, <0x57114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>, <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x57000 0x1000>; gpio3: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@59000 { /* 0x48059000, ap 17 16.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio4"; reg = <0x59000 0x4>, <0x59010 0x4>, <0x59114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>, <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x59000 0x1000>; gpio4: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio5"; reg = <0x5b000 0x4>, <0x5b010 0x4>, <0x5b114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>, <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5b000 0x1000>; gpio5: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio6"; reg = <0x5d000 0x4>, <0x5d010 0x4>, <0x5d114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>, <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5d000 0x1000>; gpio6: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@60000 { /* 0x48060000, ap 23 24.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c3"; reg = <0x60000 0x8>, <0x60010 0x8>, <0x60090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x60000 0x1000>; i2c3: i2c@0 { compatible = "ti,omap4-i2c"; reg = <0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; }; }; target-module@66000 { /* 0x48066000, ap 63 4c.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart5"; reg = <0x66050 0x4>, <0x66054 0x4>, <0x66058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x66000 0x1000>; uart5: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; }; }; target-module@68000 { /* 0x48068000, ap 53 54.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart6"; reg = <0x68050 0x4>, <0x68054 0x4>, <0x68058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x68000 0x1000>; uart6: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; }; }; target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart1"; reg = <0x6a050 0x4>, <0x6a054 0x4>, <0x6a058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6a000 0x1000>; uart1: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; }; }; target-module@6c000 { /* 0x4806c000, ap 26 22.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart2"; reg = <0x6c050 0x4>, <0x6c054 0x4>, <0x6c058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6c000 0x1000>; uart2: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; }; }; target-module@6e000 { /* 0x4806e000, ap 28 44.1 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart4"; reg = <0x6e050 0x4>, <0x6e054 0x4>, <0x6e058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6e000 0x1000>; uart4: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; }; }; target-module@70000 { /* 0x48070000, ap 30 14.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c1"; reg = <0x70000 0x8>, <0x70010 0x8>, <0x70090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x70000 0x1000>; i2c1: i2c@0 { compatible = "ti,omap4-i2c"; reg = <0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; }; }; target-module@72000 { /* 0x48072000, ap 32 1c.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c2"; reg = <0x72000 0x8>, <0x72010 0x8>, <0x72090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x72000 0x1000>; i2c2: i2c@0 { compatible = "ti,omap4-i2c"; reg = <0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; }; }; target-module@78000 { /* 0x48078000, ap 39 12.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x78000 0x1000>; }; target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c4"; reg = <0x7a000 0x8>, <0x7a010 0x8>, <0x7a090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x7a000 0x1000>; i2c4: i2c@0 { compatible = "ti,omap4-i2c"; reg = <0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; }; }; target-module@7c000 { /* 0x4807c000, ap 83 34.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c5"; reg = <0x7c000 0x8>, <0x7c010 0x8>, <0x7c090 0x8>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x7c000 0x1000>; i2c5: i2c@0 { compatible = "ti,omap4-i2c"; reg = <0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; }; }; target-module@86000 { /* 0x48086000, ap 41 5e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer10"; reg = <0x86000 0x4>, <0x86010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x86000 0x1000>; timer10: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>; clock-names = "fck"; interrupts = ; ti,timer-pwm; }; }; target-module@88000 { /* 0x48088000, ap 43 66.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer11"; reg = <0x88000 0x4>, <0x88010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x88000 0x1000>; timer11: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>; clock-names = "fck"; interrupts = ; ti,timer-pwm; }; }; - rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x91fe0 0x4>, - <0x91fe4 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - ; - /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>; - clock-names = "fck"; + target-module@90000 { /* 0x48090000, ap 55 1a.0 */ + compatible = "ti,sysc"; + status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x90000 0x2000>; - - rng: rng@0 { - compatible = "ti,omap4-rng"; - reg = <0x0 0x2000>; - interrupts = ; - }; }; target-module@98000 { /* 0x48098000, ap 47 08.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi1"; reg = <0x98000 0x4>, <0x98010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x98000 0x1000>; mcspi1: spi@0 { compatible = "ti,omap4-mcspi"; reg = <0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,spi-num-cs = <4>; dmas = <&sdma 35>, <&sdma 36>, <&sdma 37>, <&sdma 38>, <&sdma 39>, <&sdma 40>, <&sdma 41>, <&sdma 42>; dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3"; }; }; target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi2"; reg = <0x9a000 0x4>, <0x9a010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9a000 0x1000>; mcspi2: spi@0 { compatible = "ti,omap4-mcspi"; reg = <0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,spi-num-cs = <2>; dmas = <&sdma 43>, <&sdma 44>, <&sdma 45>, <&sdma 46>; dma-names = "tx0", "rx0", "tx1", "rx1"; }; }; target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc1"; reg = <0x9c000 0x4>, <0x9c010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9c000 0x1000>; mmc1: mmc@0 { compatible = "ti,omap4-hsmmc"; reg = <0x0 0x400>; interrupts = ; ti,dual-volt; ti,needs-special-reset; dmas = <&sdma 61>, <&sdma 62>; dma-names = "tx", "rx"; pbias-supply = <&pbias_mmc_reg>; }; }; target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa2000 0x1000>; }; target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x000a4000 0x00001000>, <0x00001000 0x000a5000 0x00001000>; }; target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa8000 0x4000>; }; target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc3"; reg = <0xad000 0x4>, <0xad010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xad000 0x1000>; mmc3: mmc@0 { compatible = "ti,omap4-hsmmc"; reg = <0x0 0x400>; interrupts = ; ti,needs-special-reset; dmas = <&sdma 77>, <&sdma 78>; dma-names = "tx", "rx"; }; }; target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb2000 0x1000>; }; target-module@b4000 { /* 0x480b4000, ap 65 42.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc2"; reg = <0xb4000 0x4>, <0xb4010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb4000 0x1000>; mmc2: mmc@0 { compatible = "ti,omap4-hsmmc"; reg = <0x0 0x400>; interrupts = ; ti,needs-special-reset; dmas = <&sdma 47>, <&sdma 48>; dma-names = "tx", "rx"; }; }; target-module@b8000 { /* 0x480b8000, ap 67 32.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi3"; reg = <0xb8000 0x4>, <0xb8010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb8000 0x1000>; mcspi3: spi@0 { compatible = "ti,omap4-mcspi"; reg = <0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,spi-num-cs = <2>; dmas = <&sdma 15>, <&sdma 16>; dma-names = "tx0", "rx0"; }; }; target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi4"; reg = <0xba000 0x4>, <0xba010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xba000 0x1000>; mcspi4: spi@0 { compatible = "ti,omap4-mcspi"; reg = <0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,spi-num-cs = <1>; dmas = <&sdma 70>, <&sdma 71>; dma-names = "tx0", "rx0"; }; }; target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc4"; reg = <0xd1000 0x4>, <0xd1010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd1000 0x1000>; mmc4: mmc@0 { compatible = "ti,omap4-hsmmc"; reg = <0x0 0x400>; interrupts = ; ti,needs-special-reset; dmas = <&sdma 57>, <&sdma 58>; dma-names = "tx", "rx"; }; }; target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc5"; reg = <0xd5000 0x4>, <0xd5010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-midle = , , , ; ti,sysc-sidle = , , , ; /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd5000 0x1000>; mmc5: mmc@0 { compatible = "ti,omap4-hsmmc"; reg = <0x0 0x400>; interrupts = ; ti,needs-special-reset; dmas = <&sdma 59>, <&sdma 60>; dma-names = "tx", "rx"; }; }; }; segment@200000 { /* 0x48200000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; }; }; &l4_wkup { /* 0x4ae00000 */ compatible = "ti,omap5-l4-wkup", "simple-bus"; reg = <0x4ae00000 0x800>, <0x4ae00800 0x800>, <0x4ae01000 0x1000>; reg-names = "ap", "la", "ia0"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ <0x00020000 0x4ae20000 0x010000>; /* segment 2 */ segment@0 { /* 0x4ae00000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ <0x00001000 0x00001000 0x001000>, /* ap 1 */ <0x00000800 0x00000800 0x000800>, /* ap 2 */ <0x00006000 0x00006000 0x002000>, /* ap 3 */ <0x00008000 0x00008000 0x001000>, /* ap 4 */ <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ <0x00004000 0x00004000 0x001000>, /* ap 17 */ <0x00005000 0x00005000 0x001000>, /* ap 18 */ <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ target-module@4000 { /* 0x4ae04000, ap 17 20.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "counter_32k"; reg = <0x4000 0x4>, <0x4010 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = , ; /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; counter32k: counter@0 { compatible = "ti,omap-counter32k"; reg = <0x0 0x40>; }; }; target-module@6000 { /* 0x4ae06000, ap 3 08.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x6000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6000 0x2000>; prm: prm@0 { compatible = "ti,omap5-prm", "simple-bus"; reg = <0x0 0x2000>; interrupts = ; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x2000>; prm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; prm_clockdomains: clockdomains { }; }; }; target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xa000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa000 0x1000>; scrm: scrm@0 { compatible = "ti,omap5-scrm"; reg = <0x0 0x1000>; scrm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; scrm_clockdomains: clockdomains { }; }; }; target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xc000 0x4>; reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc000 0x1000>; omap5_pmx_wkup: pinmux@840 { compatible = "ti,omap5-padconf", "pinctrl-single"; reg = <0x840 0x003c>; #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x7fff>; }; omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 { compatible = "ti,omap5-scm-wkup-pad-conf", "simple-bus"; reg = <0xda0 0x60>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x60>; scm_wkup_pad_conf: scm_conf@0 { compatible = "syscon", "simple-bus"; reg = <0x0 0x60>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0x60>; scm_wkup_pad_conf_clocks: clocks@0 { #address-cells = <1>; #size-cells = <0>; }; }; }; }; }; segment@10000 { /* 0x4ae10000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ <0x00001000 0x00011000 0x001000>, /* ap 6 */ <0x00004000 0x00014000 0x001000>, /* ap 7 */ <0x00005000 0x00015000 0x001000>, /* ap 8 */ <0x00008000 0x00018000 0x001000>, /* ap 9 */ <0x00009000 0x00019000 0x001000>, /* ap 10 */ <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ target-module@0 { /* 0x4ae10000, ap 5 10.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio1"; reg = <0x0 0x4>, <0x10 0x4>, <0x114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>, <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 8>; clock-names = "fck", "dbclk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x1000>; gpio1: gpio@0 { compatible = "ti,omap4-gpio"; reg = <0x0 0x200>; interrupts = ; ti,gpio-always-on; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; target-module@4000 { /* 0x4ae14000, ap 7 14.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "wd_timer2"; reg = <0x4000 0x4>, <0x4010 0x4>, <0x4014 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = , , , ; ti,syss-mask = <1>; /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; wdt2: wdt@0 { compatible = "ti,omap5-wdt", "ti,omap3-wdt"; reg = <0x0 0x80>; interrupts = ; }; }; target-module@8000 { /* 0x4ae18000, ap 9 18.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; ti,hwmods = "timer1"; reg = <0x8000 0x4>, <0x8010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | SYSC_OMAP4_SOFTRESET)>; ti,sysc-sidle = , , , ; /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x1000>; timer1: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; clock-names = "fck"; interrupts = ; ti,timer-alwon; }; }; target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "kbd"; reg = <0xc000 0x4>, <0xc010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = , , ; /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc000 0x1000>; keypad: keypad@0 { compatible = "ti,omap4-keypad"; reg = <0x0 0x400>; }; }; }; segment@20000 { /* 0x4ae20000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ <0x00000000 0x00020000 0x001000>, /* ap 21 */ <0x00001000 0x00021000 0x001000>, /* ap 22 */ <0x00002000 0x00022000 0x001000>, /* ap 23 */ <0x00003000 0x00023000 0x001000>, /* ap 24 */ <0x00007000 0x00027000 0x000400>, /* ap 25 */ <0x00008000 0x00028000 0x000800>, /* ap 26 */ <0x00009000 0x00029000 0x000100>, /* ap 27 */ <0x00008800 0x00028800 0x000200>, /* ap 28 */ <0x00008a00 0x00028a00 0x000100>; /* ap 29 */ target-module@0 { /* 0x4ae20000, ap 21 04.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x1000>; }; target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x1000>; }; target-module@6000 { /* 0x4ae26000, ap 13 24.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00006000 0x00001000>, <0x00001000 0x00007000 0x00000400>, <0x00002000 0x00008000 0x00000800>, <0x00002800 0x00008800 0x00000200>, <0x00002a00 0x00008a00 0x00000100>, <0x00003000 0x00009000 0x00000100>; }; }; }; diff --git a/sys/gnu/dts/arm/omap5.dtsi b/sys/gnu/dts/arm/omap5.dtsi index a7562d3deb1a..1fb7937638f0 100644 --- a/sys/gnu/dts/arm/omap5.dtsi +++ b/sys/gnu/dts/arm/omap5.dtsi @@ -1,476 +1,437 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * * Based on "omap4.dtsi" */ #include #include #include #include #include / { #address-cells = <2>; #size-cells = <2>; compatible = "ti,omap5"; interrupt-parent = <&wakeupgen>; chosen { }; aliases { i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; i2c4 = &i2c5; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; serial5 = &uart6; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; operating-points = < /* kHz uV */ 1000000 1060000 1500000 1250000 >; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; clock-latency = <300000>; /* From omap-cpufreq driver */ /* cooling options */ #cooling-cells = <2>; /* min followed by max */ }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x1>; operating-points = < /* kHz uV */ 1000000 1060000 1500000 1250000 >; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; clock-latency = <300000>; /* From omap-cpufreq driver */ /* cooling options */ #cooling-cells = <2>; /* min followed by max */ }; }; thermal-zones { #include "omap4-cpu-thermal.dtsi" #include "omap5-gpu-thermal.dtsi" #include "omap5-core-thermal.dtsi" }; timer { compatible = "arm,armv7-timer"; /* PPI secure/nonsecure IRQ */ interrupts = , , , ; interrupt-parent = <&gic>; }; pmu { compatible = "arm,cortex-a15-pmu"; interrupts = , ; }; gic: interrupt-controller@48211000 { compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; reg = <0 0x48211000 0 0x1000>, <0 0x48212000 0 0x2000>, <0 0x48214000 0 0x2000>, <0 0x48216000 0 0x2000>; interrupt-parent = <&gic>; }; wakeupgen: interrupt-controller@48281000 { compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; interrupt-controller; #interrupt-cells = <3>; reg = <0 0x48281000 0 0x1000>; interrupt-parent = <&gic>; }; /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself. */ soc { compatible = "ti,omap-infra"; mpu { compatible = "ti,omap4-mpu"; ti,hwmods = "mpu"; sram = <&ocmcram>; }; }; /* * XXX: Use a flat representation of the OMAP3 interconnect. * The real OMAP interconnect network is quite complex. * Since it will not bring real advantage to represent that in DT for * the moment, just use a fake OCP bus entry to represent the whole bus * hierarchy. */ ocp { compatible = "ti,omap5-l3-noc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xc0000000>; - dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; reg = <0 0x44000000 0 0x2000>, <0 0x44800000 0 0x3000>, <0 0x45000000 0 0x4000>; interrupts = , ; l4_wkup: interconnect@4ae00000 { }; l4_cfg: interconnect@4a000000 { }; l4_per: interconnect@48000000 { }; l4_abe: interconnect@40100000 { }; - ocmcram: sram@40300000 { + ocmcram: ocmcram@40300000 { compatible = "mmio-sram"; reg = <0x40300000 0x20000>; /* 128k */ }; gpmc: gpmc@50000000 { compatible = "ti,omap4430-gpmc"; reg = <0x50000000 0x1000>; #address-cells = <2>; #size-cells = <1>; interrupts = ; dmas = <&sdma 4>; dma-names = "rxtx"; gpmc,num-cs = <8>; gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; clocks = <&l3_iclk_div>; clock-names = "fck"; interrupt-controller; #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; }; - target-module@55082000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x55082000 0x4>, - <0x55082010 0x4>, - <0x55082014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_core 2>; - reset-names = "rstctrl"; - ranges = <0x0 0x55082000 0x100>; - #size-cells = <1>; - #address-cells = <1>; + mmu_dsp: mmu@4a066000 { + compatible = "ti,omap4-iommu"; + reg = <0x4a066000 0x100>; + interrupts = ; + ti,hwmods = "mmu_dsp"; + #iommu-cells = <0>; + }; - mmu_ipu: mmu@0 { - compatible = "ti,omap4-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - }; + mmu_ipu: mmu@55082000 { + compatible = "ti,omap4-iommu"; + reg = <0x55082000 0x100>; + interrupts = ; + ti,hwmods = "mmu_ipu"; + #iommu-cells = <0>; + ti,iommu-bus-err-back; }; dmm@4e000000 { compatible = "ti,omap5-dmm"; reg = <0x4e000000 0x800>; interrupts = <0 113 0x4>; ti,hwmods = "dmm"; }; emif1: emif@4c000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif1"; ti,no-idle-on-init; phy-type = <2>; /* DDR PHY type: Intelli PHY */ reg = <0x4c000000 0x400>; interrupts = ; hw-caps-read-idle-ctrl; hw-caps-ll-interface; hw-caps-temp-alert; }; emif2: emif@4d000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif2"; ti,no-idle-on-init; phy-type = <2>; /* DDR PHY type: Intelli PHY */ reg = <0x4d000000 0x400>; interrupts = ; hw-caps-read-idle-ctrl; hw-caps-ll-interface; hw-caps-temp-alert; }; bandgap: bandgap@4a0021e0 { reg = <0x4a0021e0 0xc 0x4a00232c 0xc 0x4a002380 0x2c 0x4a0023C0 0x3c>; interrupts = ; compatible = "ti,omap5430-bandgap"; #thermal-sensor-cells = <1>; }; /* OCP2SCP3 */ sata: sata@4a141100 { compatible = "snps,dwc-ahci"; reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; interrupts = ; phys = <&sata_phy>; phy-names = "sata-phy"; clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; ti,hwmods = "sata"; ports-implemented = <0x1>; }; target-module@56000000 { compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x5600fe00 0x4>, <0x5600fe10 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = , , ; ti,sysc-sidle = , , ; clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; /* * Closed source PowerVR driver, no child device * binding or driver in mainline */ }; dss: dss@58000000 { compatible = "ti,omap5-dss"; reg = <0x58000000 0x80>; status = "disabled"; ti,hwmods = "dss_core"; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges; dispc@58001000 { compatible = "ti,omap5-dispc"; reg = <0x58001000 0x1000>; interrupts = ; ti,hwmods = "dss_dispc"; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; }; rfbi: encoder@58002000 { compatible = "ti,omap5-rfbi"; reg = <0x58002000 0x100>; status = "disabled"; ti,hwmods = "dss_rfbi"; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>; clock-names = "fck", "ick"; }; dsi1: encoder@58004000 { compatible = "ti,omap5-dsi"; reg = <0x58004000 0x200>, <0x58004200 0x40>, <0x58004300 0x40>; reg-names = "proto", "phy", "pll"; interrupts = ; status = "disabled"; ti,hwmods = "dss_dsi1"; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; }; dsi2: encoder@58005000 { compatible = "ti,omap5-dsi"; reg = <0x58009000 0x200>, <0x58009200 0x40>, <0x58009300 0x40>; reg-names = "proto", "phy", "pll"; interrupts = ; status = "disabled"; ti,hwmods = "dss_dsi2"; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; }; hdmi: encoder@58060000 { compatible = "ti,omap5-hdmi"; reg = <0x58040000 0x200>, <0x58040200 0x80>, <0x58040300 0x80>, <0x58060000 0x19000>; reg-names = "wp", "pll", "phy", "core"; interrupts = ; status = "disabled"; ti,hwmods = "dss_hdmi"; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; dmas = <&sdma 76>; dma-names = "audio_tx"; }; }; abb_mpu: regulator-abb-mpu { compatible = "ti,abb-v2"; regulator-name = "abb_mpu"; #address-cells = <0>; #size-cells = <0>; clocks = <&sys_clkin>; ti,settling-time = <50>; ti,clock-cycles = <16>; reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; reg-names = "base-address", "int-address", "efuse-address", "ldo-address"; ti,tranxdone-status-mask = <0x80>; /* LDOVBBMPU_MUX_CTRL */ ti,ldovbb-override-mask = <0x400>; /* LDOVBBMPU_VSET_OUT */ ti,ldovbb-vset-mask = <0x1F>; /* * NOTE: only FBB mode used but actual vset will * determine final biasing */ ti,abb_info = < /*uV ABB efuse rbb_m fbb_m vset_m*/ 1060000 0 0x0 0 0x02000000 0x01F00000 1250000 0 0x4 0 0x02000000 0x01F00000 >; }; abb_mm: regulator-abb-mm { compatible = "ti,abb-v2"; regulator-name = "abb_mm"; #address-cells = <0>; #size-cells = <0>; clocks = <&sys_clkin>; ti,settling-time = <50>; ti,clock-cycles = <16>; reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; reg-names = "base-address", "int-address", "efuse-address", "ldo-address"; ti,tranxdone-status-mask = <0x80000000>; /* LDOVBBMM_MUX_CTRL */ ti,ldovbb-override-mask = <0x400>; /* LDOVBBMM_VSET_OUT */ ti,ldovbb-vset-mask = <0x1F>; /* * NOTE: only FBB mode used but actual vset will * determine final biasing */ ti,abb_info = < /*uV ABB efuse rbb_m fbb_m vset_m*/ 1025000 0 0x0 0 0x02000000 0x01F00000 1120000 0 0x4 0 0x02000000 0x01F00000 >; }; }; }; &cpu_thermal { polling-delay = <500>; /* milliseconds */ coefficients = <65 (-1791)>; }; #include "omap5-l4.dtsi" #include "omap54xx-clocks.dtsi" &gpu_thermal { coefficients = <117 (-2992)>; }; &core_thermal { coefficients = <0 2000>; }; #include "omap5-l4-abe.dtsi" #include "omap54xx-clocks.dtsi" - -&prm { - prm_dsp: prm@400 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x400 0x100>; - #reset-cells = <1>; - }; - - prm_core: prm@700 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x700 0x100>; - #reset-cells = <1>; - }; - - prm_iva: prm@1200 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x1200 0x100>; - #reset-cells = <1>; - }; - - prm_device: prm@1c00 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x1c00 0x100>; - #reset-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/omap54xx-clocks.dtsi b/sys/gnu/dts/arm/omap54xx-clocks.dtsi index 42f2c447727d..4791834dacb2 100644 --- a/sys/gnu/dts/arm/omap54xx-clocks.dtsi +++ b/sys/gnu/dts/arm/omap54xx-clocks.dtsi @@ -1,1208 +1,1202 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP5 clock data * * Copyright (C) 2013 Texas Instruments, Inc. */ &cm_core_aon_clocks { pad_clks_src_ck: pad_clks_src_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <12000000>; }; pad_clks_ck: pad_clks_ck@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&pad_clks_src_ck>; ti,bit-shift = <8>; reg = <0x0108>; }; secure_32k_clk_src_ck: secure_32k_clk_src_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; slimbus_src_clk: slimbus_src_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <12000000>; }; slimbus_clk: slimbus_clk@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&slimbus_src_clk>; ti,bit-shift = <10>; reg = <0x0108>; }; sys_32k_ck: sys_32k_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; virt_12000000_ck: virt_12000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <12000000>; }; virt_13000000_ck: virt_13000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <13000000>; }; virt_16800000_ck: virt_16800000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <16800000>; }; virt_19200000_ck: virt_19200000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <19200000>; }; virt_26000000_ck: virt_26000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <26000000>; }; virt_27000000_ck: virt_27000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <27000000>; }; virt_38400000_ck: virt_38400000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <38400000>; }; xclk60mhsp1_ck: xclk60mhsp1_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <60000000>; }; xclk60mhsp2_ck: xclk60mhsp2_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <60000000>; }; dpll_abe_ck: dpll_abe_ck@1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; }; dpll_abe_x2_ck: dpll_abe_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_abe_ck>; }; dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; reg = <0x01f0>; ti,index-starts-at-one; }; abe_24m_fclk: abe_24m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_abe_m2x2_ck>; clock-mult = <1>; clock-div = <8>; }; abe_clk: abe_clk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2x2_ck>; ti,max-div = <4>; reg = <0x0108>; ti,index-power-of-two; }; abe_iclk: abe_iclk@528 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&aess_fclk>; ti,bit-shift = <24>; reg = <0x0528>; ti,dividers = <2>, <1>; }; abe_lp_clk_div: abe_lp_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_abe_m2x2_ck>; clock-mult = <1>; clock-div = <16>; }; dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; reg = <0x01f4>; ti,index-starts-at-one; }; dpll_core_byp_mux: dpll_core_byp_mux@12c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x012c>; }; dpll_core_ck: dpll_core_ck@120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; clocks = <&sys_clkin>, <&dpll_core_byp_mux>; reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; }; dpll_core_x2_ck: dpll_core_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_core_ck>; }; dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0150>; ti,index-starts-at-one; }; c2c_fclk: c2c_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_h21x2_ck>; clock-mult = <1>; clock-div = <1>; }; c2c_iclk: c2c_iclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&c2c_fclk>; clock-mult = <1>; clock-div = <2>; }; dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0138>; ti,index-starts-at-one; }; dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x013c>; ti,index-starts-at-one; }; dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0140>; ti,index-starts-at-one; }; dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0144>; ti,index-starts-at-one; }; dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0154>; ti,index-starts-at-one; }; dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0158>; ti,index-starts-at-one; }; dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x015c>; ti,index-starts-at-one; }; dpll_core_m2_ck: dpll_core_m2_ck@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_ck>; ti,max-div = <31>; reg = <0x0130>; ti,index-starts-at-one; }; dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; reg = <0x0134>; ti,index-starts-at-one; }; iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x01ac>; }; dpll_iva_ck: dpll_iva_ck@1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; assigned-clocks = <&dpll_iva_ck>; assigned-clock-rates = <1165000000>; }; dpll_iva_x2_ck: dpll_iva_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_iva_ck>; }; dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <63>; reg = <0x01b8>; ti,index-starts-at-one; assigned-clocks = <&dpll_iva_h11x2_ck>; assigned-clock-rates = <465920000>; }; dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <63>; reg = <0x01bc>; ti,index-starts-at-one; assigned-clocks = <&dpll_iva_h12x2_ck>; assigned-clock-rates = <388300000>; }; mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; dpll_mpu_ck: dpll_mpu_ck@160 { #clock-cells = <0>; compatible = "ti,omap5-mpu-dpll-clock"; clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; reg = <0x0170>; ti,index-starts-at-one; }; per_dpll_hs_clk_div: per_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <2>; }; usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <3>; }; l3_iclk_div: l3_iclk_div@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; ti,max-div = <2>; ti,bit-shift = <4>; reg = <0x100>; clocks = <&dpll_core_h12x2_ck>; ti,index-power-of-two; }; gpu_l3_iclk: gpu_l3_iclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&l3_iclk_div>; clock-mult = <1>; clock-div = <1>; }; l4_root_clk_div: l4_root_clk_div@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; ti,max-div = <2>; ti,bit-shift = <8>; reg = <0x100>; clocks = <&l3_iclk_div>; ti,index-power-of-two; }; slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&slimbus_clk>; ti,bit-shift = <11>; reg = <0x0560>; }; aess_fclk: aess_fclk@528 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&abe_clk>; ti,bit-shift = <24>; ti,max-div = <2>; reg = <0x0528>; }; mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; ti,bit-shift = <26>; reg = <0x0540>; }; mcasp_gfclk: mcasp_gfclk@540 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; ti,bit-shift = <24>; reg = <0x0540>; }; dummy_ck: dummy_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; }; &prm_clocks { sys_clkin: sys_clkin@110 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; reg = <0x0110>; ti,index-starts-at-one; }; abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>; reg = <0x0108>; }; abe_dpll_clk_mux: abe_dpll_clk_mux@10c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>; reg = <0x010c>; }; custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin>; clock-mult = <1>; clock-div = <2>; }; dss_syc_gfclk_div: dss_syc_gfclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin>; clock-mult = <1>; clock-div = <1>; }; wkupaon_iclk_mux: wkupaon_iclk_mux@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&abe_lp_clk_div>; reg = <0x0108>; }; l3instr_ts_gclk_div: l3instr_ts_gclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&wkupaon_iclk_mux>; clock-mult = <1>; clock-div = <1>; }; }; &cm_core_clocks { dpll_per_byp_mux: dpll_per_byp_mux@14c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x014c>; }; dpll_per_ck: dpll_per_ck@140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&dpll_per_byp_mux>; reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; }; dpll_per_x2_ck: dpll_per_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_per_ck>; }; dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; reg = <0x0158>; ti,index-starts-at-one; }; dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; reg = <0x015c>; ti,index-starts-at-one; }; dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; reg = <0x0164>; ti,index-starts-at-one; }; dpll_per_m2_ck: dpll_per_m2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_ck>; ti,max-div = <31>; reg = <0x0150>; ti,index-starts-at-one; }; dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; reg = <0x0150>; ti,index-starts-at-one; }; dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; reg = <0x0154>; ti,index-starts-at-one; }; dpll_unipro1_ck: dpll_unipro1_ck@200 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&sys_clkin>; reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; }; dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_unipro1_ck>; clock-mult = <1>; clock-div = <1>; }; dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_unipro1_ck>; ti,max-div = <127>; reg = <0x0210>; ti,index-starts-at-one; }; dpll_unipro2_ck: dpll_unipro2_ck@1c0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&sys_clkin>; reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; }; dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_unipro2_ck>; clock-mult = <1>; clock-div = <1>; }; dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_unipro2_ck>; ti,max-div = <127>; reg = <0x01d0>; ti,index-starts-at-one; }; dpll_usb_byp_mux: dpll_usb_byp_mux@18c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x018c>; }; dpll_usb_ck: dpll_usb_ck@180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; clocks = <&sys_clkin>, <&dpll_usb_byp_mux>; reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; }; dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_usb_ck>; clock-mult = <1>; clock-div = <1>; }; dpll_usb_m2_ck: dpll_usb_m2_ck@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_ck>; ti,max-div = <127>; reg = <0x0190>; ti,index-starts-at-one; }; func_128m_clk: func_128m_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_h11x2_ck>; clock-mult = <1>; clock-div = <2>; }; func_12m_fclk: func_12m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <16>; }; func_24m_clk: func_24m_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; func_48m_fclk: func_48m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <4>; }; func_96m_fclk: func_96m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <2>; }; l3init_60m_fclk: l3init_60m_fclk@104 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_m2_ck>; reg = <0x0104>; ti,dividers = <1>, <8>; }; iss_ctrlclk: iss_ctrlclk@1320 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&func_96m_fclk>; ti,bit-shift = <8>; reg = <0x1320>; }; lli_txphy_clk: lli_txphy_clk@f20 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_unipro1_clkdcoldo>; ti,bit-shift = <8>; reg = <0x0f20>; }; lli_txphy_ls_clk: lli_txphy_ls_clk@f20 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_unipro1_m2_ck>; ti,bit-shift = <9>; reg = <0x0f20>; }; usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0640>; }; fdif_fclk: fdif_fclk@1328 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_h11x2_ck>; ti,bit-shift = <24>; ti,max-div = <2>; reg = <0x1328>; }; gpu_core_gclk_mux: gpu_core_gclk_mux@1520 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; ti,bit-shift = <24>; reg = <0x1520>; }; gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; ti,bit-shift = <25>; reg = <0x1520>; }; hsi_fclk: hsi_fclk@1638 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_m2x2_ck>; ti,bit-shift = <24>; ti,max-div = <2>; reg = <0x1638>; }; }; &cm_core_clockdomains { l3init_clkdm: l3init_clkdm { compatible = "ti,clockdomain"; clocks = <&dpll_usb_ck>; }; }; &scrm_clocks { auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0310>; }; auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0310>; }; auxclk0_src_ck: auxclk0_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; }; auxclk0_ck: auxclk0_ck@310 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk0_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; reg = <0x0310>; }; auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0314>; }; auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0314>; }; auxclk1_src_ck: auxclk1_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; }; auxclk1_ck: auxclk1_ck@314 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk1_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; reg = <0x0314>; }; auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0318>; }; auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0318>; }; auxclk2_src_ck: auxclk2_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; }; auxclk2_ck: auxclk2_ck@318 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk2_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; reg = <0x0318>; }; auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x031c>; }; auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x031c>; }; auxclk3_src_ck: auxclk3_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; }; auxclk3_ck: auxclk3_ck@31c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk3_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; reg = <0x031c>; }; auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0320>; }; auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0320>; }; auxclk4_src_ck: auxclk4_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; }; auxclk4_ck: auxclk4_ck@320 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk4_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; reg = <0x0320>; }; auxclkreq0_ck: auxclkreq0_ck@210 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; ti,bit-shift = <2>; reg = <0x0210>; }; auxclkreq1_ck: auxclkreq1_ck@214 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; ti,bit-shift = <2>; reg = <0x0214>; }; auxclkreq2_ck: auxclkreq2_ck@218 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; ti,bit-shift = <2>; reg = <0x0218>; }; auxclkreq3_ck: auxclkreq3_ck@21c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; ti,bit-shift = <2>; reg = <0x021c>; }; }; &cm_core_aon { mpu_cm: mpu_cm@300 { compatible = "ti,omap4-cm"; reg = <0x300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x300 0x100>; mpu_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; dsp_cm: dsp_cm@400 { compatible = "ti,omap4-cm"; reg = <0x400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x400 0x100>; dsp_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; abe_cm: abe_cm@500 { compatible = "ti,omap4-cm"; reg = <0x500 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x500 0x100>; abe_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x64>; #clock-cells = <2>; }; }; }; &cm_core { l3main1_cm: l3main1_cm@700 { compatible = "ti,omap4-cm"; reg = <0x700 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x700 0x100>; l3main1_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; l3main2_cm: l3main2_cm@800 { compatible = "ti,omap4-cm"; reg = <0x800 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x800 0x100>; l3main2_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; ipu_cm: ipu_cm@900 { compatible = "ti,omap4-cm"; reg = <0x900 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x900 0x100>; ipu_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; dma_cm: dma_cm@a00 { compatible = "ti,omap4-cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xa00 0x100>; dma_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; emif_cm: emif_cm@b00 { compatible = "ti,omap4-cm"; reg = <0xb00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xb00 0x100>; emif_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x1c>; #clock-cells = <2>; }; }; l4cfg_cm: l4cfg_cm@d00 { compatible = "ti,omap4-cm"; reg = <0xd00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xd00 0x100>; l4cfg_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x14>; #clock-cells = <2>; }; }; l3instr_cm: l3instr_cm@e00 { compatible = "ti,omap4-cm"; reg = <0xe00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xe00 0x100>; l3instr_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; }; l4per_cm: l4per_cm@1000 { compatible = "ti,omap4-cm"; reg = <0x1000 0x200>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1000 0x200>; - l4per_clkctrl: clock@20 { - compatible = "ti,clkctrl-l4per", "ti,clkctrl"; + l4per_clkctrl: clk@20 { + compatible = "ti,clkctrl"; reg = <0x20 0x15c>; #clock-cells = <2>; }; - - l4sec_clkctrl: clock@1a0 { - compatible = "ti,clkctrl-l4sec", "ti,clkctrl"; - reg = <0x1a0 0x3c>; - #clock-cells = <2>; - }; }; dss_cm: dss_cm@1400 { compatible = "ti,omap4-cm"; reg = <0x1400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1400 0x100>; dss_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; gpu_cm: gpu_cm@1500 { compatible = "ti,omap4-cm"; reg = <0x1500 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1500 0x100>; gpu_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; l3init_cm: l3init_cm@1600 { compatible = "ti,omap4-cm"; reg = <0x1600 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1600 0x100>; l3init_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0xd4>; #clock-cells = <2>; }; }; }; &prm { wkupaon_cm: wkupaon_cm@1900 { compatible = "ti,omap4-cm"; reg = <0x1900 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1900 0x100>; wkupaon_clkctrl: clk@20 { compatible = "ti,clkctrl"; reg = <0x20 0x5c>; #clock-cells = <2>; }; }; }; &scm_wkup_pad_conf_clocks { fref_xtal_ck: fref_xtal_ck { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_clkin>; ti,bit-shift = <28>; reg = <0x14>; }; }; diff --git a/sys/gnu/dts/include/dt-bindings/clock/dra7.h b/sys/gnu/dts/include/dt-bindings/clock/dra7.h index 8cec5a1e1806..72f2e8411523 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/dra7.h +++ b/sys/gnu/dts/include/dt-bindings/clock/dra7.h @@ -1,378 +1,355 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright 2017 Texas Instruments, Inc. */ #ifndef __DT_BINDINGS_CLK_DRA7_H #define __DT_BINDINGS_CLK_DRA7_H #define DRA7_CLKCTRL_OFFSET 0x20 #define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET) /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ /* mpu clocks */ #define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) /* ipu clocks */ #define _DRA7_IPU_CLKCTRL_OFFSET 0x40 #define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET) #define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50) #define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58) #define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60) #define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68) #define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70) #define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78) #define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80) /* rtc clocks */ #define DRA7_RTC_CLKCTRL_OFFSET 0x40 #define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET) #define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44) -/* vip clocks */ -#define DRA7_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) - -/* vpe clocks */ -#define DRA7_VPE_CLKCTRL_OFFSET 0x60 -#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET) -#define DRA7_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64) - /* coreaon clocks */ #define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) /* l3main1 clocks */ #define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) #define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) #define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) #define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) #define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) /* dma clocks */ #define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) /* emif clocks */ #define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) /* atl clocks */ #define DRA7_ATL_CLKCTRL_OFFSET 0x0 #define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) #define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) /* l4cfg clocks */ #define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) #define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) #define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) #define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) #define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) #define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) #define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) #define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) #define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) #define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) #define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) #define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) #define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) /* l3instr clocks */ #define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) /* dss clocks */ #define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) -/* gpu clocks */ -#define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - /* l3init clocks */ #define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) #define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) #define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) #define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) #define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) #define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0) #define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8) #define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0) #define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) #define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) #define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) /* l4per clocks */ #define _DRA7_L4PER_CLKCTRL_OFFSET 0x0 #define _DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET) #define DRA7_L4_PER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc) #define DRA7_L4_PER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x14) #define DRA7_TIMER10_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x28) #define DRA7_TIMER11_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x30) #define DRA7_TIMER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x38) #define DRA7_TIMER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x40) #define DRA7_TIMER4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x48) #define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50) #define DRA7_ELM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x58) #define DRA7_GPIO2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x60) #define DRA7_GPIO3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x68) #define DRA7_GPIO4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x70) #define DRA7_GPIO5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x78) #define DRA7_GPIO6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x80) #define DRA7_HDQ1W_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x88) #define DRA7_EPWMSS1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x90) #define DRA7_EPWMSS2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x98) #define DRA7_I2C1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa0) #define DRA7_I2C2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa8) #define DRA7_I2C3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb0) #define DRA7_I2C4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb8) #define DRA7_L4_PER1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc0) #define DRA7_EPWMSS0_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc4) #define DRA7_TIMER13_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc8) #define DRA7_TIMER14_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd0) #define DRA7_TIMER15_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd8) #define DRA7_MCSPI1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf0) #define DRA7_MCSPI2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf8) #define DRA7_MCSPI3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x100) #define DRA7_MCSPI4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x108) #define DRA7_GPIO7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x110) #define DRA7_GPIO8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x118) #define DRA7_MMC3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x120) #define DRA7_MMC4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x128) #define DRA7_TIMER16_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x130) #define DRA7_QSPI_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x138) #define DRA7_UART1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x140) #define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148) #define DRA7_UART3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x150) #define DRA7_UART4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x158) #define DRA7_MCASP2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x160) #define DRA7_MCASP3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x168) #define DRA7_UART5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x170) #define DRA7_MCASP5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x178) #define DRA7_MCASP8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x190) #define DRA7_MCASP4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x198) #define DRA7_AES1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a0) #define DRA7_AES2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a8) #define DRA7_DES_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1b0) #define DRA7_RNG_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c0) #define DRA7_SHAM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c8) #define DRA7_UART7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1d0) #define DRA7_UART8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e0) #define DRA7_UART9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e8) #define DRA7_DCAN2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1f0) #define DRA7_MCASP6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x204) #define DRA7_MCASP7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x208) /* wkupaon clocks */ #define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) #define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) #define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) #define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) #define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) #define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) #define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) #define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) /* XXX: Compatibility part end. */ /* mpu clocks */ #define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) /* dsp1 clocks */ #define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) /* ipu1 clocks */ #define DRA7_IPU1_MMU_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) /* ipu clocks */ #define DRA7_IPU_CLKCTRL_OFFSET 0x50 #define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET) #define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50) #define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58) #define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60) #define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68) #define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70) #define DRA7_IPU_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78) #define DRA7_IPU_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80) /* dsp2 clocks */ #define DRA7_DSP2_MMU0_DSP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) /* rtc clocks */ #define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44) -/* vip clocks */ -#define DRA7_CAM_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_CAM_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_CAM_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) - -/* vpe clocks */ -#define DRA7_VPE_CLKCTRL_OFFSET 0x60 -#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET) -#define DRA7_VPE_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64) - /* coreaon clocks */ #define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) /* l3main1 clocks */ #define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_L3MAIN1_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_L3MAIN1_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) #define DRA7_L3MAIN1_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) #define DRA7_L3MAIN1_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) #define DRA7_L3MAIN1_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) #define DRA7_L3MAIN1_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) /* ipu2 clocks */ #define DRA7_IPU2_MMU_IPU2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) /* dma clocks */ #define DRA7_DMA_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) /* emif clocks */ #define DRA7_EMIF_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) /* atl clocks */ #define DRA7_ATL_CLKCTRL_OFFSET 0x0 #define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) #define DRA7_ATL_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) /* l4cfg clocks */ #define DRA7_L4CFG_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_L4CFG_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_L4CFG_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) #define DRA7_L4CFG_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) #define DRA7_L4CFG_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) #define DRA7_L4CFG_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) #define DRA7_L4CFG_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) #define DRA7_L4CFG_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) #define DRA7_L4CFG_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) #define DRA7_L4CFG_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) #define DRA7_L4CFG_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) #define DRA7_L4CFG_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) #define DRA7_L4CFG_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) #define DRA7_L4CFG_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) #define DRA7_L4CFG_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) /* l3instr clocks */ #define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) /* dss clocks */ #define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) /* l3init clocks */ #define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_L3INIT_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) #define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) #define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) #define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) #define DRA7_L3INIT_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) #define DRA7_L3INIT_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) #define DRA7_L3INIT_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) #define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) /* pcie clocks */ #define DRA7_PCIE_CLKCTRL_OFFSET 0xb0 #define DRA7_PCIE_CLKCTRL_INDEX(offset) ((offset) - DRA7_PCIE_CLKCTRL_OFFSET) #define DRA7_PCIE_PCIE1_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb0) #define DRA7_PCIE_PCIE2_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb8) /* gmac clocks */ #define DRA7_GMAC_CLKCTRL_OFFSET 0xd0 #define DRA7_GMAC_CLKCTRL_INDEX(offset) ((offset) - DRA7_GMAC_CLKCTRL_OFFSET) #define DRA7_GMAC_GMAC_CLKCTRL DRA7_GMAC_CLKCTRL_INDEX(0xd0) /* l4per clocks */ #define DRA7_L4PER_CLKCTRL_OFFSET 0x28 #define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET) #define DRA7_L4PER_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28) #define DRA7_L4PER_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30) #define DRA7_L4PER_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38) #define DRA7_L4PER_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40) #define DRA7_L4PER_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48) #define DRA7_L4PER_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50) #define DRA7_L4PER_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58) #define DRA7_L4PER_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60) #define DRA7_L4PER_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68) #define DRA7_L4PER_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70) #define DRA7_L4PER_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78) #define DRA7_L4PER_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80) #define DRA7_L4PER_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88) #define DRA7_L4PER_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0) #define DRA7_L4PER_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8) #define DRA7_L4PER_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0) #define DRA7_L4PER_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8) #define DRA7_L4PER_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0) #define DRA7_L4PER_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0) #define DRA7_L4PER_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8) #define DRA7_L4PER_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100) #define DRA7_L4PER_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108) #define DRA7_L4PER_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110) #define DRA7_L4PER_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118) #define DRA7_L4PER_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120) #define DRA7_L4PER_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128) #define DRA7_L4PER_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140) #define DRA7_L4PER_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148) #define DRA7_L4PER_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150) #define DRA7_L4PER_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158) #define DRA7_L4PER_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170) /* l4sec clocks */ #define DRA7_L4SEC_CLKCTRL_OFFSET 0x1a0 #define DRA7_L4SEC_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4SEC_CLKCTRL_OFFSET) #define DRA7_L4SEC_AES1_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a0) #define DRA7_L4SEC_AES2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a8) #define DRA7_L4SEC_DES_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1b0) #define DRA7_L4SEC_RNG_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c0) #define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8) /* l4per2 clocks */ #define DRA7_L4PER2_CLKCTRL_OFFSET 0xc #define DRA7_L4PER2_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER2_CLKCTRL_OFFSET) #define DRA7_L4PER2_L4_PER2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc) #define DRA7_L4PER2_PRUSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x18) #define DRA7_L4PER2_PRUSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x20) #define DRA7_L4PER2_EPWMSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x90) #define DRA7_L4PER2_EPWMSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x98) #define DRA7_L4PER2_EPWMSS0_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc4) #define DRA7_L4PER2_QSPI_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x138) #define DRA7_L4PER2_MCASP2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x160) #define DRA7_L4PER2_MCASP3_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x168) #define DRA7_L4PER2_MCASP5_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x178) #define DRA7_L4PER2_MCASP8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x190) #define DRA7_L4PER2_MCASP4_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x198) #define DRA7_L4PER2_UART7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1d0) #define DRA7_L4PER2_UART8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e0) #define DRA7_L4PER2_UART9_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e8) #define DRA7_L4PER2_DCAN2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1f0) #define DRA7_L4PER2_MCASP6_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x204) #define DRA7_L4PER2_MCASP7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x208) /* l4per3 clocks */ #define DRA7_L4PER3_CLKCTRL_OFFSET 0x14 #define DRA7_L4PER3_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER3_CLKCTRL_OFFSET) #define DRA7_L4PER3_L4_PER3_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x14) #define DRA7_L4PER3_TIMER13_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xc8) #define DRA7_L4PER3_TIMER14_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd0) #define DRA7_L4PER3_TIMER15_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd8) #define DRA7_L4PER3_TIMER16_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x130) /* wkupaon clocks */ #define DRA7_WKUPAON_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_WKUPAON_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) #define DRA7_WKUPAON_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) #define DRA7_WKUPAON_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) #define DRA7_WKUPAON_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) #define DRA7_WKUPAON_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) #define DRA7_WKUPAON_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) #define DRA7_WKUPAON_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) #define DRA7_WKUPAON_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) #endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/omap4.h b/sys/gnu/dts/include/dt-bindings/clock/omap4.h index 88d73be84b94..5167b2d93ac3 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/omap4.h +++ b/sys/gnu/dts/include/dt-bindings/clock/omap4.h @@ -1,149 +1,138 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright 2017 Texas Instruments, Inc. */ #ifndef __DT_BINDINGS_CLK_OMAP4_H #define __DT_BINDINGS_CLK_OMAP4_H #define OMAP4_CLKCTRL_OFFSET 0x20 #define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) /* mpuss clocks */ #define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) /* tesla clocks */ #define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) /* abe clocks */ #define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) #define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) #define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) #define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) #define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) #define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) #define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) #define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) #define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) #define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) #define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) #define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) #define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) #define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) /* l4_ao clocks */ #define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) #define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) #define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) /* l3_1 clocks */ #define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) /* l3_2 clocks */ #define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) #define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) #define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) /* ducati clocks */ #define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) /* l3_dma clocks */ #define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) /* l3_emif clocks */ #define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) #define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) #define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) /* d2d clocks */ #define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) /* l4_cfg clocks */ #define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) #define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) #define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) /* l3_instr clocks */ #define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) #define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) #define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) /* ivahd clocks */ #define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) #define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) /* iss clocks */ #define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) #define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) /* l3_dss clocks */ #define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) /* l3_gfx clocks */ #define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) /* l3_init clocks */ #define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) #define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) #define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) #define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) #define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) #define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) #define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0) #define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) /* l4_per clocks */ #define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) #define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) #define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) #define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) #define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) #define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) #define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) #define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) #define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) #define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) #define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) #define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) #define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) #define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0) #define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8) #define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0) #define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8) #define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0) #define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) #define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0) #define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8) #define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100) #define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108) #define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120) #define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128) #define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138) #define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140) #define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148) #define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150) #define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158) #define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160) -/* l4_secure clocks */ -#define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0 -#define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET) -#define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0) -#define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8) -#define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0) -#define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8) -#define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0) -#define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8) -#define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8) - /* l4_wkup clocks */ #define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) #define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) #define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) #define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) #define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) #define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) /* emu_sys clocks */ #define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) #endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/omap5.h b/sys/gnu/dts/include/dt-bindings/clock/omap5.h index 41775272fd27..e5411938983c 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/omap5.h +++ b/sys/gnu/dts/include/dt-bindings/clock/omap5.h @@ -1,129 +1,113 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright 2017 Texas Instruments, Inc. */ #ifndef __DT_BINDINGS_CLK_OMAP5_H #define __DT_BINDINGS_CLK_OMAP5_H #define OMAP5_CLKCTRL_OFFSET 0x20 #define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET) /* mpu clocks */ #define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) /* dsp clocks */ #define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) /* abe clocks */ #define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) #define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) #define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) #define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) #define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) #define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) #define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) #define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) #define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) #define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) /* l3main1 clocks */ #define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) /* l3main2 clocks */ #define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) /* ipu clocks */ #define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) /* dma clocks */ #define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) /* emif clocks */ #define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) #define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) #define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) /* l4cfg clocks */ #define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) #define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) #define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) /* l3instr clocks */ #define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) #define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) /* l4per clocks */ #define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) #define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) #define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) #define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) #define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) #define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) #define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60) #define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) #define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) #define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) #define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) #define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0) #define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8) #define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0) #define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8) #define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0) #define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) #define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8) #define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100) #define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108) #define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110) #define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118) #define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120) #define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128) #define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140) #define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148) #define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150) #define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158) #define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160) #define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168) #define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) #define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) -/* l4_secure clocks */ -#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0 -#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET) -#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0) -#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8) -#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0) -#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8) -#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0) -#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8) -#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8) - -/* iva clocks */ -#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) - /* dss clocks */ #define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) /* gpu clocks */ #define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) /* l3init clocks */ #define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) #define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) #define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) #define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) #define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88) #define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0) #define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8) #define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) /* wkupaon clocks */ #define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) #define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) #define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) #define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) #define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) #define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) #endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/ti-dra7-atl.h b/sys/gnu/dts/include/dt-bindings/clock/ti-dra7-atl.h index 42dd4164f6f4..e69de29bb2d1 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/ti-dra7-atl.h +++ b/sys/gnu/dts/include/dt-bindings/clock/ti-dra7-atl.h @@ -1,40 +0,0 @@ -/* - * This header provides constants for DRA7 ATL (Audio Tracking Logic) - * - * The constants defined in this header are used in dts files - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * Peter Ujfalusi - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H -#define _DT_BINDINGS_CLK_DRA7_ATL_H - -#define DRA7_ATL_WS_MCASP1_FSR 0 -#define DRA7_ATL_WS_MCASP1_FSX 1 -#define DRA7_ATL_WS_MCASP2_FSR 2 -#define DRA7_ATL_WS_MCASP2_FSX 3 -#define DRA7_ATL_WS_MCASP3_FSX 4 -#define DRA7_ATL_WS_MCASP4_FSX 5 -#define DRA7_ATL_WS_MCASP5_FSX 6 -#define DRA7_ATL_WS_MCASP6_FSX 7 -#define DRA7_ATL_WS_MCASP7_FSX 8 -#define DRA7_ATL_WS_MCASP8_FSX 9 -#define DRA7_ATL_WS_MCASP8_AHCLKX 10 -#define DRA7_ATL_WS_XREF_CLK3 11 -#define DRA7_ATL_WS_XREF_CLK0 12 -#define DRA7_ATL_WS_XREF_CLK1 13 -#define DRA7_ATL_WS_XREF_CLK2 14 -#define DRA7_ATL_WS_OSC1_X1 15 - -#endif