diff --git a/sys/pci/if_rl.c b/sys/pci/if_rl.c index d9ec5121d093..33d676a53f71 100644 --- a/sys/pci/if_rl.c +++ b/sys/pci/if_rl.c @@ -1,1989 +1,1988 @@ /* * Copyright (c) 1997, 1998 * Bill Paul . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * - * $Id: if_rl.c,v 1.13 1998/10/07 22:51:30 wpaul Exp $ + * $Id: if_rl.c,v 1.14 1998/11/18 20:27:28 wpaul Exp $ */ /* * RealTek 8129/8139 PCI NIC driver * * Supports several extremely cheap PCI 10/100 adapters based on * the RealTek chipset. Datasheets can be obtained from * www.realtek.com.tw. * * Written by Bill Paul * Electrical Engineering Department * Columbia University, New York City */ /* * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is * probably the worst PCI ethernet controller ever made, with the possible * exception of the FEAST chip made by SMC. The 8139 supports bus-master * DMA, but it has a terrible interface that nullifies any performance * gains that bus-master DMA usually offers. * * For transmission, the chip offers a series of four TX descriptor * registers. Each transmit frame must be in a contiguous buffer, aligned * on a doubleword (32-bit) boundary. This means we almost always have to * do mbuf copies in order to transmit a frame, except in the unlikely * case where a) the packet fits into a single mbuf, and b) the packet * is 32-bit aligned within the mbuf's data area. The presence of only * four descriptor registers means that we can never have more than four * packets queued for transmission at any one time. * * Reception is not much better. The driver has to allocate a single large * buffer area (up to 64K in size) into which the chip will DMA received * frames. Because we don't know where within this region received packets * will begin or end, we have no choice but to copy data from the buffer * area into mbufs in order to pass the packets up to the higher protocol * levels. * * It's impossible given this rotten design to really achieve decent * performance at 100Mbps, unless you happen to have a 400Mhz PII or * some equally overmuscled CPU to drive it. * * On the bright side, the 8139 does have a built-in PHY, although * rather than using an MDIO serial interface like most other NICs, the * PHY registers are directly accessible through the 8139's register * space. The 8139 supports autonegotiation, as well as a 64-bit multicast * filter. * * The 8129 chip is an older version of the 8139 that uses an external PHY * chip. The 8129 has a serial MDIO interface for accessing the MII where * the 8139 lets you directly access the on-board PHY registers. We need * to select which interface to use depending on the chip type. * * Note: beware of trying to use the Linux RealTek driver as a reference * for information about the RealTek chip. It contains several bogosities. * It contains definitions for several undocumented registers which it * claims are 'required for proper operation' yet it does not use these * registers anywhere in the code. It also refers to some undocumented * 'Twister tuning codes' which it doesn't use anywhere. It also contains * bit definitions for several registers which are totally ignored: magic * numbers are used instead, making the code hard to read. */ #include "bpfilter.h" #include #include #include #include #include #include #include #include #include #include #include #include #if NBPFILTER > 0 #include #endif #include /* for vtophys */ #include /* for vtophys */ #include /* for DELAY */ #include #include /* * Default to using PIO access for this driver. On SMP systems, * there appear to be problems with memory mapped mode: it looks like * doing too many memory mapped access back to back in rapid succession * can hang the bus. I'm inclined to blame this on crummy design/construction * on the part of RealTek. Memory mapped mode does appear to work on * uniprocessor systems though. */ #define RL_USEIOSPACE #include #ifndef lint static char rcsid[] = - "$Id: if_rl.c,v 1.13 1998/10/07 22:51:30 wpaul Exp $"; + "$Id: if_rl.c,v 1.14 1998/11/18 20:27:28 wpaul Exp $"; #endif /* * Various supported device vendors/types and their names. */ static struct rl_type rl_devs[] = { { RT_VENDORID, RT_DEVICEID_8129, "RealTek 8129 10/100BaseTX" }, { RT_VENDORID, RT_DEVICEID_8139, "RealTek 8139 10/100BaseTX" }, - { RT_VENDORID_ALT, RT_DEVICEID_8139_ALT, - "RealTek 8139 10/100BaseTX" }, + { ACCTON_VENDORID, ACCTON_DEVICEID_5030, + "Accton MPX 5030/5038 10/100BaseTX" }, { 0, 0, NULL } }; /* * Various supported PHY vendors/types and their names. Note that * this driver will work with pretty much any MII-compliant PHY, * so failure to positively identify the chip is not a fatal error. */ static struct rl_type rl_phys[] = { { TI_PHY_VENDORID, TI_PHY_10BT, "" }, { TI_PHY_VENDORID, TI_PHY_100VGPMI, "" }, { NS_PHY_VENDORID, NS_PHY_83840A, ""}, { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "" }, { INTEL_PHY_VENDORID, INTEL_PHY_82555, "" }, { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "" }, { 0, 0, "" } }; static unsigned long rl_count = 0; static char *rl_probe __P((pcici_t, pcidi_t)); static void rl_attach __P((pcici_t, int)); static int rl_encap __P((struct rl_softc *, struct rl_chain *, struct mbuf * )); static void rl_rxeof __P((struct rl_softc *)); static void rl_txeof __P((struct rl_softc *)); static void rl_txeoc __P((struct rl_softc *)); static void rl_intr __P((void *)); static void rl_start __P((struct ifnet *)); static int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); static void rl_init __P((void *)); static void rl_stop __P((struct rl_softc *)); static void rl_watchdog __P((struct ifnet *)); static void rl_shutdown __P((int, void *)); static int rl_ifmedia_upd __P((struct ifnet *)); static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); static void rl_eeprom_putbyte __P((struct rl_softc *, u_int8_t)); static void rl_eeprom_getword __P((struct rl_softc *, u_int8_t, u_int16_t *)); static void rl_read_eeprom __P((struct rl_softc *, caddr_t, int, int, int)); static void rl_mii_sync __P((struct rl_softc *)); static void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); static u_int16_t rl_phy_readreg __P((struct rl_softc *, int)); static void rl_phy_writereg __P((struct rl_softc *, u_int16_t, u_int16_t)); static void rl_autoneg_xmit __P((struct rl_softc *)); static void rl_autoneg_mii __P((struct rl_softc *, int, int)); static void rl_setmode_mii __P((struct rl_softc *, int)); static void rl_getmode_mii __P((struct rl_softc *)); static u_int8_t rl_calchash __P((u_int8_t *)); static void rl_setmulti __P((struct rl_softc *)); static void rl_reset __P((struct rl_softc *)); static int rl_list_tx_init __P((struct rl_softc *)); #define EE_SET(x) \ CSR_WRITE_1(sc, RL_EECMD, \ CSR_READ_1(sc, RL_EECMD) | x) #define EE_CLR(x) \ CSR_WRITE_1(sc, RL_EECMD, \ CSR_READ_1(sc, RL_EECMD) & ~x) /* * Send a read command and address to the EEPROM, check for ACK. */ static void rl_eeprom_putbyte(sc, addr) struct rl_softc *sc; u_int8_t addr; { register int d, i; d = addr | RL_EECMD_READ; /* * Feed in each bit and stobe the clock. */ for (i = 0x400; i; i >>= 1) { if (d & i) { EE_SET(RL_EE_DATAIN); } else { EE_CLR(RL_EE_DATAIN); } DELAY(100); EE_SET(RL_EE_CLK); DELAY(150); EE_CLR(RL_EE_CLK); DELAY(100); } return; } /* * Read a word of data stored in the EEPROM at address 'addr.' */ static void rl_eeprom_getword(sc, addr, dest) struct rl_softc *sc; u_int8_t addr; u_int16_t *dest; { register int i; u_int16_t word = 0; /* Enter EEPROM access mode. */ CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); /* * Send address of word we want to read. */ rl_eeprom_putbyte(sc, addr); CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); /* * Start reading bits from EEPROM. */ for (i = 0x8000; i; i >>= 1) { EE_SET(RL_EE_CLK); DELAY(100); if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) word |= i; EE_CLR(RL_EE_CLK); DELAY(100); } /* Turn off EEPROM access mode. */ CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); *dest = word; return; } /* * Read a sequence of words from the EEPROM. */ static void rl_read_eeprom(sc, dest, off, cnt, swap) struct rl_softc *sc; caddr_t dest; int off; int cnt; int swap; { int i; u_int16_t word = 0, *ptr; for (i = 0; i < cnt; i++) { rl_eeprom_getword(sc, off + i, &word); ptr = (u_int16_t *)(dest + (i * 2)); if (swap) *ptr = ntohs(word); else *ptr = word; } return; } /* * MII access routines are provided for the 8129, which * doesn't have a built-in PHY. For the 8139, we fake things * up by diverting rl_phy_readreg()/rl_phy_writereg() to the * direct access PHY registers. */ #define MII_SET(x) \ CSR_WRITE_1(sc, RL_MII, \ CSR_READ_1(sc, RL_MII) | x) #define MII_CLR(x) \ CSR_WRITE_1(sc, RL_MII, \ CSR_READ_1(sc, RL_MII) & ~x) /* * Sync the PHYs by setting data bit and strobing the clock 32 times. */ static void rl_mii_sync(sc) struct rl_softc *sc; { register int i; MII_SET(RL_MII_DIR|RL_MII_DATAOUT); for (i = 0; i < 32; i++) { MII_SET(RL_MII_CLK); DELAY(1); MII_CLR(RL_MII_CLK); DELAY(1); } return; } /* * Clock a series of bits through the MII. */ static void rl_mii_send(sc, bits, cnt) struct rl_softc *sc; u_int32_t bits; int cnt; { int i; MII_CLR(RL_MII_CLK); for (i = (0x1 << (cnt - 1)); i; i >>= 1) { if (bits & i) { MII_SET(RL_MII_DATAOUT); } else { MII_CLR(RL_MII_DATAOUT); } DELAY(1); MII_CLR(RL_MII_CLK); DELAY(1); MII_SET(RL_MII_CLK); } } /* * Read an PHY register through the MII. */ static int rl_mii_readreg(sc, frame) struct rl_softc *sc; struct rl_mii_frame *frame; { int i, ack, s; s = splimp(); /* * Set up frame for RX. */ frame->mii_stdelim = RL_MII_STARTDELIM; frame->mii_opcode = RL_MII_READOP; frame->mii_turnaround = 0; frame->mii_data = 0; CSR_WRITE_2(sc, RL_MII, 0); /* * Turn on data xmit. */ MII_SET(RL_MII_DIR); rl_mii_sync(sc); /* * Send command/address info. */ rl_mii_send(sc, frame->mii_stdelim, 2); rl_mii_send(sc, frame->mii_opcode, 2); rl_mii_send(sc, frame->mii_phyaddr, 5); rl_mii_send(sc, frame->mii_regaddr, 5); /* Idle bit */ MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); DELAY(1); MII_SET(RL_MII_CLK); DELAY(1); /* Turn off xmit. */ MII_CLR(RL_MII_DIR); /* Check for ack */ MII_CLR(RL_MII_CLK); DELAY(1); MII_SET(RL_MII_CLK); DELAY(1); ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; /* * Now try reading data bits. If the ack failed, we still * need to clock through 16 cycles to keep the PHY(s) in sync. */ if (ack) { for(i = 0; i < 16; i++) { MII_CLR(RL_MII_CLK); DELAY(1); MII_SET(RL_MII_CLK); DELAY(1); } goto fail; } for (i = 0x8000; i; i >>= 1) { MII_CLR(RL_MII_CLK); DELAY(1); if (!ack) { if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) frame->mii_data |= i; DELAY(1); } MII_SET(RL_MII_CLK); DELAY(1); } fail: MII_CLR(RL_MII_CLK); DELAY(1); MII_SET(RL_MII_CLK); DELAY(1); splx(s); if (ack) return(1); return(0); } /* * Write to a PHY register through the MII. */ static int rl_mii_writereg(sc, frame) struct rl_softc *sc; struct rl_mii_frame *frame; { int s; s = splimp(); /* * Set up frame for TX. */ frame->mii_stdelim = RL_MII_STARTDELIM; frame->mii_opcode = RL_MII_WRITEOP; frame->mii_turnaround = RL_MII_TURNAROUND; /* * Turn on data output. */ MII_SET(RL_MII_DIR); rl_mii_sync(sc); rl_mii_send(sc, frame->mii_stdelim, 2); rl_mii_send(sc, frame->mii_opcode, 2); rl_mii_send(sc, frame->mii_phyaddr, 5); rl_mii_send(sc, frame->mii_regaddr, 5); rl_mii_send(sc, frame->mii_turnaround, 2); rl_mii_send(sc, frame->mii_data, 16); /* Idle bit. */ MII_SET(RL_MII_CLK); DELAY(1); MII_CLR(RL_MII_CLK); DELAY(1); /* * Turn off xmit. */ MII_CLR(RL_MII_DIR); splx(s); return(0); } static u_int16_t rl_phy_readreg(sc, reg) struct rl_softc *sc; int reg; { struct rl_mii_frame frame; u_int16_t rval = 0; u_int16_t rl8139_reg = 0; if (sc->rl_type == RL_8139) { switch(reg) { case PHY_BMCR: rl8139_reg = RL_BMCR; break; case PHY_BMSR: rl8139_reg = RL_BMSR; break; case PHY_ANAR: rl8139_reg = RL_ANAR; break; case PHY_LPAR: rl8139_reg = RL_LPAR; break; default: printf("rl%d: bad phy register\n", sc->rl_unit); return(0); } rval = CSR_READ_2(sc, rl8139_reg); return(rval); } bzero((char *)&frame, sizeof(frame)); frame.mii_phyaddr = sc->rl_phy_addr; frame.mii_regaddr = reg; rl_mii_readreg(sc, &frame); return(frame.mii_data); } static void rl_phy_writereg(sc, reg, data) struct rl_softc *sc; u_int16_t reg; u_int16_t data; { struct rl_mii_frame frame; u_int16_t rl8139_reg = 0; if (sc->rl_type == RL_8139) { switch(reg) { case PHY_BMCR: rl8139_reg = RL_BMCR; break; case PHY_BMSR: rl8139_reg = RL_BMSR; break; case PHY_ANAR: rl8139_reg = RL_ANAR; break; case PHY_LPAR: rl8139_reg = RL_LPAR; break; default: printf("rl%d: bad phy register\n", sc->rl_unit); return; } CSR_WRITE_2(sc, rl8139_reg, data); } bzero((char *)&frame, sizeof(frame)); frame.mii_phyaddr = sc->rl_phy_addr; frame.mii_regaddr = reg; frame.mii_data = data; rl_mii_writereg(sc, &frame); return; } /* * Calculate CRC of a multicast group address, return the lower 6 bits. */ static u_int8_t rl_calchash(addr) u_int8_t *addr; { u_int32_t crc, carry; int i, j; u_int8_t c; /* Compute CRC for the address value. */ crc = 0xFFFFFFFF; /* initial value */ for (i = 0; i < 6; i++) { c = *(addr + i); for (j = 0; j < 8; j++) { carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); crc <<= 1; c >>= 1; if (carry) crc = (crc ^ 0x04c11db6) | carry; } } /* return the filter bit position */ return(crc & 0x0000003F); } /* * Program the 64-bit multicast hash filter. */ static void rl_setmulti(sc) struct rl_softc *sc; { struct ifnet *ifp; int h = 0; u_int32_t hashes[2] = { 0, 0 }; struct ifmultiaddr *ifma; u_int32_t rxfilt; int mcnt = 0; ifp = &sc->arpcom.ac_if; rxfilt = CSR_READ_4(sc, RL_RXCFG); if (ifp->if_flags & IFF_ALLMULTI) { rxfilt |= RL_RXCFG_RX_MULTI; CSR_WRITE_4(sc, RL_RXCFG, rxfilt); CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); return; } /* first, zot all the existing hash bits */ CSR_WRITE_4(sc, RL_MAR0, 0); CSR_WRITE_4(sc, RL_MAR4, 0); /* now program new ones */ for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; ifma = ifma->ifma_link.le_next) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); if (h < 32) hashes[0] |= (1 << h); else hashes[1] |= (1 << (h - 32)); mcnt++; } if (mcnt) rxfilt |= RL_RXCFG_RX_MULTI; else rxfilt &= ~RL_RXCFG_RX_MULTI; CSR_WRITE_4(sc, RL_RXCFG, rxfilt); CSR_WRITE_4(sc, RL_MAR0, hashes[0]); CSR_WRITE_4(sc, RL_MAR4, hashes[1]); return; } /* * Initiate an autonegotiation session. */ static void rl_autoneg_xmit(sc) struct rl_softc *sc; { u_int16_t phy_sts; rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); DELAY(500); while(rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); phy_sts = rl_phy_readreg(sc, PHY_BMCR); phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; rl_phy_writereg(sc, PHY_BMCR, phy_sts); return; } /* * Invoke autonegotiation on a PHY. Also used with the 8139 internal * transceiver. */ static void rl_autoneg_mii(sc, flag, verbose) struct rl_softc *sc; int flag; int verbose; { u_int16_t phy_sts = 0, media, advert, ability; struct ifnet *ifp; struct ifmedia *ifm; ifm = &sc->ifmedia; ifp = &sc->arpcom.ac_if; /* * The 100baseT4 PHY sometimes has the 'autoneg supported' * bit cleared in the status register, but has the 'autoneg enabled' * bit set in the control register. This is a contradiction, and * I'm not sure how to handle it. If you want to force an attempt * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR * and see what happens. */ #ifndef FORCE_AUTONEG_TFOUR /* * First, see if autoneg is supported. If not, there's * no point in continuing. */ phy_sts = rl_phy_readreg(sc, PHY_BMSR); if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { if (verbose) printf("rl%d: autonegotiation not supported\n", sc->rl_unit); return; } #endif switch (flag) { case RL_FLAG_FORCEDELAY: /* * XXX Never use this option anywhere but in the probe * routine: making the kernel stop dead in its tracks * for three whole seconds after we've gone multi-user * is really bad manners. */ rl_autoneg_xmit(sc); DELAY(5000000); break; case RL_FLAG_SCHEDDELAY: /* * Wait for the transmitter to go idle before starting * an autoneg session, otherwise rl_start() may clobber * our timeout, and we don't want to allow transmission * during an autoneg session since that can screw it up. */ if (sc->rl_cdata.rl_tx_cnt) { sc->rl_want_auto = 1; return; } rl_autoneg_xmit(sc); ifp->if_timer = 5; sc->rl_autoneg = 1; sc->rl_want_auto = 0; return; break; case RL_FLAG_DELAYTIMEO: ifp->if_timer = 0; sc->rl_autoneg = 0; break; default: printf("rl%d: invalid autoneg flag: %d\n", sc->rl_unit, flag); return; } if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { if (verbose) printf("rl%d: autoneg complete, ", sc->rl_unit); phy_sts = rl_phy_readreg(sc, PHY_BMSR); } else { if (verbose) printf("rl%d: autoneg not complete, ", sc->rl_unit); } media = rl_phy_readreg(sc, PHY_BMCR); /* Link is good. Report modes and set duplex mode. */ if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { if (verbose) printf("link status good "); advert = rl_phy_readreg(sc, PHY_ANAR); ability = rl_phy_readreg(sc, PHY_LPAR); if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { ifm->ifm_media = IFM_ETHER|IFM_100_T4; media |= PHY_BMCR_SPEEDSEL; media &= ~PHY_BMCR_DUPLEX; printf("(100baseT4)\n"); } else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) { ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; media |= PHY_BMCR_SPEEDSEL; media |= PHY_BMCR_DUPLEX; printf("(full-duplex, 100Mbps)\n"); } else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) { ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; media |= PHY_BMCR_SPEEDSEL; media &= ~PHY_BMCR_DUPLEX; printf("(half-duplex, 100Mbps)\n"); } else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) { ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; media &= ~PHY_BMCR_SPEEDSEL; media |= PHY_BMCR_DUPLEX; printf("(full-duplex, 10Mbps)\n"); } else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) { ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; media &= ~PHY_BMCR_SPEEDSEL; media &= ~PHY_BMCR_DUPLEX; printf("(half-duplex, 10Mbps)\n"); } else { ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; media &= ~PHY_BMCR_SPEEDSEL; media &= ~PHY_BMCR_DUPLEX; printf("(unknown mode! forcing half-duplex, 10Mbps)\n"); } /* Set ASIC's duplex mode to match the PHY. */ rl_phy_writereg(sc, PHY_BMCR, media); } else { if (verbose) printf("no carrier\n"); } rl_init(sc); if (sc->rl_tx_pend) { sc->rl_autoneg = 0; sc->rl_tx_pend = 0; rl_start(ifp); } return; } static void rl_getmode_mii(sc) struct rl_softc *sc; { u_int16_t bmsr; struct ifnet *ifp; ifp = &sc->arpcom.ac_if; bmsr = rl_phy_readreg(sc, PHY_BMSR); if (bootverbose) printf("rl%d: PHY status word: %x\n", sc->rl_unit, bmsr); /* fallback */ sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; if (bmsr & PHY_BMSR_10BTHALF) { if (bootverbose) printf("rl%d: 10Mbps half-duplex mode supported\n", sc->rl_unit); ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); } if (bmsr & PHY_BMSR_10BTFULL) { if (bootverbose) printf("rl%d: 10Mbps full-duplex mode supported\n", sc->rl_unit); ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; } if (bmsr & PHY_BMSR_100BTXHALF) { if (bootverbose) printf("rl%d: 100Mbps half-duplex mode supported\n", sc->rl_unit); ifp->if_baudrate = 100000000; ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; } if (bmsr & PHY_BMSR_100BTXFULL) { if (bootverbose) printf("rl%d: 100Mbps full-duplex mode supported\n", sc->rl_unit); ifp->if_baudrate = 100000000; ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; } /* Some also support 100BaseT4. */ if (bmsr & PHY_BMSR_100BT4) { if (bootverbose) printf("rl%d: 100baseT4 mode supported\n", sc->rl_unit); ifp->if_baudrate = 100000000; ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL); sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4; #ifdef FORCE_AUTONEG_TFOUR if (bootverbose) printf("rl%d: forcing on autoneg support for BT4\n", sc->rl_unit); ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL): sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; #endif } if (bmsr & PHY_BMSR_CANAUTONEG) { if (bootverbose) printf("rl%d: autoneg supported\n", sc->rl_unit); ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; } return; } /* * Set speed and duplex mode. */ static void rl_setmode_mii(sc, media) struct rl_softc *sc; int media; { u_int16_t bmcr; printf("rl%d: selecting MII, ", sc->rl_unit); bmcr = rl_phy_readreg(sc, PHY_BMCR); bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL| PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK); if (IFM_SUBTYPE(media) == IFM_100_T4) { printf("100Mbps/T4, half-duplex\n"); bmcr |= PHY_BMCR_SPEEDSEL; bmcr &= ~PHY_BMCR_DUPLEX; } if (IFM_SUBTYPE(media) == IFM_100_TX) { printf("100Mbps, "); bmcr |= PHY_BMCR_SPEEDSEL; } if (IFM_SUBTYPE(media) == IFM_10_T) { printf("10Mbps, "); bmcr &= ~PHY_BMCR_SPEEDSEL; } if ((media & IFM_GMASK) == IFM_FDX) { printf("full duplex\n"); bmcr |= PHY_BMCR_DUPLEX; } else { printf("half duplex\n"); bmcr &= ~PHY_BMCR_DUPLEX; } rl_phy_writereg(sc, PHY_BMCR, bmcr); return; } static void rl_reset(sc) struct rl_softc *sc; { register int i; CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); for (i = 0; i < RL_TIMEOUT; i++) { DELAY(10); if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) break; } if (i == RL_TIMEOUT) printf("rl%d: reset never completed!\n", sc->rl_unit); return; } /* * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device * IDs against our list and return a device name if we find a match. */ static char * rl_probe(config_id, device_id) pcici_t config_id; pcidi_t device_id; { struct rl_type *t; t = rl_devs; while(t->rl_name != NULL) { if ((device_id & 0xFFFF) == t->rl_vid && ((device_id >> 16) & 0xFFFF) == t->rl_did) { return(t->rl_name); } t++; } return(NULL); } /* * Attach the interface. Allocate softc structures, do ifmedia * setup and ethernet/BPF attach. */ static void rl_attach(config_id, unit) pcici_t config_id; int unit; { int s, i; #ifndef RL_USEIOSPACE vm_offset_t pbase, vbase; #endif u_char eaddr[ETHER_ADDR_LEN]; u_int32_t command; struct rl_softc *sc; struct ifnet *ifp; int media = IFM_ETHER|IFM_100_TX|IFM_FDX; struct rl_type *p; u_int16_t phy_vid, phy_did, phy_sts; u_int16_t rl_did = 0; s = splimp(); sc = malloc(sizeof(struct rl_softc), M_DEVBUF, M_NOWAIT); if (sc == NULL) { printf("rl%d: no memory for softc struct!\n", unit); return; } bzero(sc, sizeof(struct rl_softc)); /* * Handle power management nonsense. */ command = pci_conf_read(config_id, RL_PCI_CAPID) & 0x000000FF; if (command == 0x01) { command = pci_conf_read(config_id, RL_PCI_PWRMGMTCTRL); if (command & RL_PSTATE_MASK) { u_int32_t iobase, membase, irq; /* Save important PCI config data. */ iobase = pci_conf_read(config_id, RL_PCI_LOIO); membase = pci_conf_read(config_id, RL_PCI_LOMEM); irq = pci_conf_read(config_id, RL_PCI_INTLINE); /* Reset the power state. */ printf("rl%d: chip is is in D%d power mode " "-- setting to D0\n", unit, command & RL_PSTATE_MASK); command &= 0xFFFFFFFC; pci_conf_write(config_id, RL_PCI_PWRMGMTCTRL, command); /* Restore PCI config data. */ pci_conf_write(config_id, RL_PCI_LOIO, iobase); pci_conf_write(config_id, RL_PCI_LOMEM, membase); pci_conf_write(config_id, RL_PCI_INTLINE, irq); } } /* * Map control/status registers. */ command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command); command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); #ifdef RL_USEIOSPACE if (!(command & PCIM_CMD_PORTEN)) { printf("rl%d: failed to enable I/O ports!\n", unit); free(sc, M_DEVBUF); goto fail; } sc->iobase = pci_conf_read(config_id, RL_PCI_LOIO) & 0xFFFFFFFC; #else if (!(command & PCIM_CMD_MEMEN)) { printf("rl%d: failed to enable memory mapping!\n", unit); goto fail; } if (!pci_map_mem(config_id, RL_PCI_LOMEM, &vbase, &pbase)) { printf ("rl%d: couldn't map memory\n", unit); goto fail; } sc->csr = (volatile caddr_t)vbase; #endif /* Allocate interrupt */ if (!pci_map_int(config_id, rl_intr, sc, &net_imask)) { printf("rl%d: couldn't map interrupt\n", unit); goto fail; } /* Reset the adapter. */ rl_reset(sc); /* * Get station address from the EEPROM. */ rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); /* * A RealTek chip was detected. Inform the world. */ printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); sc->rl_unit = unit; bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); /* * Now read the exact device type from the EEPROM to find * out if it's an 8129 or 8139. */ rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); if (rl_did == RT_DEVICEID_8139) sc->rl_type = RL_8139; else if (rl_did == RT_DEVICEID_8129) sc->rl_type = RL_8129; else { printf("rl%d: unknown device ID: %x\n", unit, rl_did); free(sc, M_DEVBUF); goto fail; } sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 16, M_DEVBUF, M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); if (sc->rl_cdata.rl_rx_buf == NULL) { free(sc, M_DEVBUF); printf("rl%d: no memory for list buffers!\n", unit); goto fail; } ifp = &sc->arpcom.ac_if; ifp->if_softc = sc; ifp->if_unit = unit; ifp->if_name = "rl"; ifp->if_mtu = ETHERMTU; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_ioctl = rl_ioctl; ifp->if_output = ether_output; ifp->if_start = rl_start; ifp->if_watchdog = rl_watchdog; ifp->if_init = rl_init; ifp->if_baudrate = 10000000; if (sc->rl_type == RL_8129) { if (bootverbose) printf("rl%d: probing for a PHY\n", sc->rl_unit); for (i = RL_PHYADDR_MIN; i < RL_PHYADDR_MAX + 1; i++) { if (bootverbose) printf("rl%d: checking address: %d\n", sc->rl_unit, i); sc->rl_phy_addr = i; rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); DELAY(500); while(rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); if ((phy_sts = rl_phy_readreg(sc, PHY_BMSR))) break; } if (phy_sts) { phy_vid = rl_phy_readreg(sc, PHY_VENID); phy_did = rl_phy_readreg(sc, PHY_DEVID); if (bootverbose) printf("rl%d: found PHY at address %d, ", sc->rl_unit, sc->rl_phy_addr); if (bootverbose) printf("vendor id: %x device id: %x\n", phy_vid, phy_did); p = rl_phys; while(p->rl_vid) { if (phy_vid == p->rl_vid && (phy_did | 0x000F) == p->rl_did) { sc->rl_pinfo = p; break; } p++; } if (sc->rl_pinfo == NULL) sc->rl_pinfo = &rl_phys[PHY_UNKNOWN]; if (bootverbose) printf("rl%d: PHY type: %s\n", sc->rl_unit, sc->rl_pinfo->rl_name); } else { printf("rl%d: MII without any phy!\n", sc->rl_unit); } } /* * Do ifmedia setup. */ ifmedia_init(&sc->ifmedia, 0, rl_ifmedia_upd, rl_ifmedia_sts); rl_getmode_mii(sc); /* Choose a default media. */ media = IFM_ETHER|IFM_AUTO; ifmedia_set(&sc->ifmedia, media); rl_autoneg_mii(sc, RL_FLAG_FORCEDELAY, 1); /* * Call MI attach routines. */ if_attach(ifp); ether_ifattach(ifp); #if NBPFILTER > 0 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); #endif at_shutdown(rl_shutdown, sc, SHUTDOWN_POST_SYNC); fail: splx(s); return; } /* * Initialize the transmit descriptors. */ static int rl_list_tx_init(sc) struct rl_softc *sc; { struct rl_chain_data *cd; int i; cd = &sc->rl_cdata; for (i = 0; i < RL_TX_LIST_CNT; i++) { cd->rl_tx_chain[i].rl_desc = i * 4; CSR_WRITE_4(sc, RL_TXADDR0 + cd->rl_tx_chain[i].rl_desc, 0); CSR_WRITE_4(sc, RL_TXSTAT0 + cd->rl_tx_chain[i].rl_desc, 0); if (i == (RL_TX_LIST_CNT - 1)) cd->rl_tx_chain[i].rl_next = &cd->rl_tx_chain[0]; else cd->rl_tx_chain[i].rl_next = &cd->rl_tx_chain[i + 1]; } sc->rl_cdata.rl_tx_cnt = 0; cd->rl_tx_cur = cd->rl_tx_free = &cd->rl_tx_chain[0]; return(0); } /* * A frame has been uploaded: pass the resulting mbuf chain up to * the higher level protocols. * * You know there's something wrong with a PCI bus-master chip design * when you have to use m_devget(). * * The receive operation is badly documented in the datasheet, so I'll * attempt to document it here. The driver provides a buffer area and * places its base address in the RX buffer start address register. * The chip then begins copying frames into the RX buffer. Each frame * is preceeded by a 32-bit RX status word which specifies the length * of the frame and certain other status bits. Each frame (starting with * the status word) is also 32-bit aligned. The frame length is in the * first 16 bits of the status word; the lower 15 bits correspond with * the 'rx status register' mentioned in the datasheet. */ static void rl_rxeof(sc) struct rl_softc *sc; { struct ether_header *eh; struct mbuf *m; struct ifnet *ifp; int total_len = 0; u_int32_t rxstat; caddr_t rxbufpos; int wrap = 0; u_int16_t cur_rx; u_int16_t limit; u_int16_t rx_bytes = 0, max_bytes; ifp = &sc->arpcom.ac_if; cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; /* Do not try to read past this point. */ limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; if (limit < cur_rx) max_bytes = (RL_RXBUFLEN - cur_rx) + limit; else max_bytes = limit - cur_rx; while((CSR_READ_1(sc, RL_COMMAND) & 1) == 0) { rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; rxstat = *(u_int32_t *)rxbufpos; /* * Here's a totally undocumented fact for you. When the * RealTek chip is in the process of copying a packet into * RAM for you, the length will be 0xfff0. If you spot a * packet header with this value, you need to stop. The * datasheet makes absolutely no mention of this and * RealTek should be shot for this. */ if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) break; if (!(rxstat & RL_RXSTAT_RXOK)) { ifp->if_ierrors++; if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT| RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR| RL_RXSTAT_ALIGNERR)) { CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB); CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB| RL_CMD_RX_ENB); CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); cur_rx = 0; } break; } /* No errors; receive the packet. */ total_len = rxstat >> 16; rx_bytes += total_len + 4; /* * Avoid trying to read more bytes than we know * the chip has prepared for us. */ if (rx_bytes > max_bytes) break; rxbufpos = sc->rl_cdata.rl_rx_buf + ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) rxbufpos = sc->rl_cdata.rl_rx_buf; wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; if (total_len > wrap) { m = m_devget(rxbufpos, wrap, 0, ifp, NULL); if (m == NULL) { ifp->if_ierrors++; printf("rl%d: out of mbufs, tried to " "copy %d bytes\n", sc->rl_unit, wrap); } else m_copyback(m, wrap, total_len - wrap, sc->rl_cdata.rl_rx_buf); cur_rx = (total_len - wrap); } else { m = m_devget(rxbufpos, total_len, 0, ifp, NULL); if (m == NULL) { ifp->if_ierrors++; printf("rl%d: out of mbufs, tried to " "copy %d bytes\n", sc->rl_unit, total_len); } cur_rx += total_len + 4; } /* * Round up to 32-bit boundary. */ cur_rx = (cur_rx + 3) & ~3; CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); if (m == NULL) continue; eh = mtod(m, struct ether_header *); ifp->if_ipackets++; #if NBPFILTER > 0 /* * Handle BPF listeners. Let the BPF user see the packet, but * don't pass it up to the ether_input() layer unless it's * a broadcast packet, multicast packet, matches our ethernet * address or the interface is in promiscuous mode. */ if (ifp->if_bpf) { bpf_mtap(ifp, m); if (ifp->if_flags & IFF_PROMISC && (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, ETHER_ADDR_LEN) && (eh->ether_dhost[0] & 1) == 0)) { m_freem(m); continue; } } #endif /* Remove header from mbuf and pass it on. */ m_adj(m, sizeof(struct ether_header)); ether_input(ifp, eh, m); } return; } /* * A frame was downloaded to the chip. It's safe for us to clean up * the list buffers. */ static void rl_txeof(sc) struct rl_softc *sc; { struct rl_chain *cur_tx; struct ifnet *ifp; u_int32_t txstat; ifp = &sc->arpcom.ac_if; /* Clear the timeout timer. */ ifp->if_timer = 0; /* * Go through our tx list and free mbufs for those * frames that have been uploaded. */ if (sc->rl_cdata.rl_tx_free == NULL) return; while(sc->rl_cdata.rl_tx_free->rl_mbuf != NULL) { cur_tx = sc->rl_cdata.rl_tx_free; txstat = CSR_READ_4(sc, RL_TXSTAT0 + cur_tx->rl_desc); if (!(txstat & RL_TXSTAT_TX_OK)) break; if (txstat & RL_TXSTAT_COLLCNT) ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; sc->rl_cdata.rl_tx_free = cur_tx->rl_next; sc->rl_cdata.rl_tx_cnt--; m_freem(cur_tx->rl_mbuf); cur_tx->rl_mbuf = NULL; ifp->if_opackets++; } if (!sc->rl_cdata.rl_tx_cnt) { ifp->if_flags &= ~IFF_OACTIVE; if (sc->rl_want_auto) rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1); } else { if (ifp->if_snd.ifq_head != NULL) rl_start(ifp); } return; } /* * TX error handler. */ static void rl_txeoc(sc) struct rl_softc *sc; { u_int32_t txstat; struct rl_chain *cur_tx; struct ifnet *ifp; ifp = &sc->arpcom.ac_if; if (sc->rl_cdata.rl_tx_free == NULL) return; while(sc->rl_cdata.rl_tx_free->rl_mbuf != NULL) { cur_tx = sc->rl_cdata.rl_tx_free; txstat = CSR_READ_4(sc, RL_TXSTAT0 + cur_tx->rl_desc); if (!(txstat & RL_TXSTAT_OWN)) break; if (!(txstat & RL_TXSTAT_TX_OK)) { ifp->if_oerrors++; if (txstat & RL_TXSTAT_COLLCNT) ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; CSR_WRITE_4(sc, RL_TXADDR0 + cur_tx->rl_desc, vtophys(mtod(cur_tx->rl_mbuf, caddr_t))); CSR_WRITE_4(sc, RL_TXSTAT0 + cur_tx->rl_desc, RL_TX_EARLYTHRESH | cur_tx->rl_mbuf->m_pkthdr.len); break; } else { if (txstat & RL_TXSTAT_COLLCNT) ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; sc->rl_cdata.rl_tx_free = cur_tx->rl_next; sc->rl_cdata.rl_tx_cnt--; m_freem(cur_tx->rl_mbuf); cur_tx->rl_mbuf = NULL; ifp->if_opackets++; } } return; } static void rl_intr(arg) void *arg; { struct rl_softc *sc; struct ifnet *ifp; u_int16_t status; sc = arg; ifp = &sc->arpcom.ac_if; /* Disable interrupts. */ CSR_WRITE_2(sc, RL_IMR, 0x0000); for (;;) { status = CSR_READ_2(sc, RL_ISR); if (status) CSR_WRITE_2(sc, RL_ISR, status); if ((status & RL_INTRS) == 0) break; if (status & RL_ISR_RX_OK) rl_rxeof(sc); if (status & RL_ISR_RX_ERR) rl_rxeof(sc); if (status & RL_ISR_TX_OK) rl_txeof(sc); if (status & RL_ISR_TX_ERR) rl_txeoc(sc); if (status & RL_ISR_SYSTEM_ERR) { rl_reset(sc); rl_init(sc); } } /* Re-enable interrupts. */ CSR_WRITE_2(sc, RL_IMR, RL_INTRS); if (ifp->if_snd.ifq_head != NULL) { rl_start(ifp); } return; } /* * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data * pointers to the fragment pointers. */ static int rl_encap(sc, c, m_head) struct rl_softc *sc; struct rl_chain *c; struct mbuf *m_head; { struct mbuf *m; + struct mbuf *m_new = NULL; /* * There are two possible encapsulation mechanisms * that we can use: an efficient one, and a very lossy * one. The efficient one only happens very rarely, * whereas the lossy one can and most likely will happen * all the time. * The efficient case happens if: * - the packet fits in a single mbuf * - the packet is 32-bit aligned within the mbuf data area * In this case, we can DMA from the mbuf directly. * The lossy case covers everything else. Bah. */ m = m_head; - if (m->m_pkthdr.len > MHLEN || (mtod(m, u_int32_t) & 0x00000003)) { - struct mbuf *m_new = NULL; - - MGETHDR(m_new, M_DONTWAIT, MT_DATA); - if (m_new == NULL) { - printf("rl%d: no memory for tx list", sc->rl_unit); + MGETHDR(m_new, M_DONTWAIT, MT_DATA); + if (m_new == NULL) { + printf("rl%d: no memory for tx list", sc->rl_unit); + return(1); + } + if (m_head->m_pkthdr.len > MHLEN) { + MCLGET(m_new, M_DONTWAIT); + if (!(m_new->m_flags & M_EXT)) { + m_freem(m_new); + printf("rl%d: no memory for tx list", + sc->rl_unit); return(1); } - if (m_head->m_pkthdr.len > MHLEN) { - MCLGET(m_new, M_DONTWAIT); - if (!(m_new->m_flags & M_EXT)) { - m_freem(m_new); - printf("rl%d: no memory for tx list", - sc->rl_unit); - return(1); - } - } - m_copydata(m_head, 0, m_head->m_pkthdr.len, - mtod(m_new, caddr_t)); - m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; - m_freem(m_head); - m_head = m_new; } + m_copydata(m_head, 0, m_head->m_pkthdr.len, + mtod(m_new, caddr_t)); + m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; + m_freem(m_head); + m_head = m_new; /* Pad frames to at least 60 bytes. */ - if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) + if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { m_head->m_pkthdr.len += (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); + m_head->m_len = m_head->m_pkthdr.len; + } c->rl_mbuf = m_head; return(0); } /* * Main transmit routine. */ static void rl_start(ifp) struct ifnet *ifp; { struct rl_softc *sc; struct mbuf *m_head = NULL; struct rl_chain *cur_tx = NULL; sc = ifp->if_softc; if (sc->rl_autoneg) { sc->rl_tx_pend = 1; return; } /* * Check for an available queue slot. If there are none, * punt. */ if (sc->rl_cdata.rl_tx_cur->rl_mbuf != NULL) { ifp->if_flags |= IFF_OACTIVE; return; } while(sc->rl_cdata.rl_tx_cur->rl_mbuf == NULL) { IF_DEQUEUE(&ifp->if_snd, m_head); if (m_head == NULL) break; /* Pick a descriptor off the free list. */ cur_tx = sc->rl_cdata.rl_tx_cur; sc->rl_cdata.rl_tx_cur = cur_tx->rl_next; sc->rl_cdata.rl_tx_cnt++; /* Pack the data into the descriptor. */ rl_encap(sc, cur_tx, m_head); #if NBPFILTER > 0 /* * If there's a BPF listener, bounce a copy of this frame * to him. */ if (ifp->if_bpf) bpf_mtap(ifp, cur_tx->rl_mbuf); #endif /* * Transmit the frame. */ CSR_WRITE_4(sc, RL_TXADDR0 + cur_tx->rl_desc, vtophys(mtod(cur_tx->rl_mbuf, caddr_t))); CSR_WRITE_4(sc, RL_TXSTAT0 + cur_tx->rl_desc, RL_TX_EARLYTHRESH | cur_tx->rl_mbuf->m_pkthdr.len); } /* * Set a timeout in case the chip goes out to lunch. */ ifp->if_timer = 5; return; } static void rl_init(xsc) void *xsc; { struct rl_softc *sc = xsc; struct ifnet *ifp = &sc->arpcom.ac_if; int s, i; u_int32_t rxcfg = 0; u_int16_t phy_bmcr = 0; if (sc->rl_autoneg) return; s = splimp(); /* * XXX Hack for the 8139: the built-in autoneg logic's state * gets reset by rl_init() when we don't want it to. Try * to preserve it. (For 8129 cards with real external PHYs, * the BMCR register doesn't change, but this doesn't hurt.) */ if (sc->rl_type == RL_8139) phy_bmcr = rl_phy_readreg(sc, PHY_BMCR); /* * Cancel pending I/O and free all RX/TX buffers. */ rl_stop(sc); /* Init our MAC address */ for (i = 0; i < ETHER_ADDR_LEN; i++) { CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); } /* Init the RX buffer pointer register. */ CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); /* Init TX descriptors. */ rl_list_tx_init(sc); /* * Enable transmit and receive. */ CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); /* * Set the buffer size values. */ CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); /* Set the individual bit to receive frames for this host only. */ rxcfg = CSR_READ_4(sc, RL_RXCFG); rxcfg |= RL_RXCFG_RX_INDIV; /* If we want promiscuous mode, set the allframes bit. */ if (ifp->if_flags & IFF_PROMISC) { rxcfg |= RL_RXCFG_RX_ALLPHYS; CSR_WRITE_4(sc, RL_RXCFG, rxcfg); } else { rxcfg &= ~RL_RXCFG_RX_ALLPHYS; CSR_WRITE_4(sc, RL_RXCFG, rxcfg); } /* * Set capture broadcast bit to capture broadcast frames. */ if (ifp->if_flags & IFF_BROADCAST) { rxcfg |= RL_RXCFG_RX_BROAD; CSR_WRITE_4(sc, RL_RXCFG, rxcfg); } else { rxcfg &= ~RL_RXCFG_RX_BROAD; CSR_WRITE_4(sc, RL_RXCFG, rxcfg); } /* * Program the multicast filter, if necessary. */ rl_setmulti(sc); /* * Enable interrupts. */ CSR_WRITE_2(sc, RL_IMR, RL_INTRS); /* Start RX/TX process. */ CSR_WRITE_4(sc, RL_MISSEDPKT, 0); /* Enable receiver and transmitter. */ CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); /* Restore state of BMCR */ if (sc->rl_pinfo != NULL) rl_phy_writereg(sc, PHY_BMCR, phy_bmcr); CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); ifp->if_flags |= IFF_RUNNING; ifp->if_flags &= ~IFF_OACTIVE; (void)splx(s); return; } /* * Set media options. */ static int rl_ifmedia_upd(ifp) struct ifnet *ifp; { struct rl_softc *sc; struct ifmedia *ifm; sc = ifp->if_softc; ifm = &sc->ifmedia; if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) return(EINVAL); if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1); else rl_setmode_mii(sc, ifm->ifm_media); return(0); } /* * Report current media status. */ static void rl_ifmedia_sts(ifp, ifmr) struct ifnet *ifp; struct ifmediareq *ifmr; { struct rl_softc *sc; u_int16_t advert = 0, ability = 0; sc = ifp->if_softc; if (!(rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) ifmr->ifm_active = IFM_ETHER|IFM_100_TX; else ifmr->ifm_active = IFM_ETHER|IFM_10_T; if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) ifmr->ifm_active |= IFM_FDX; else ifmr->ifm_active |= IFM_HDX; return; } ability = rl_phy_readreg(sc, PHY_LPAR); advert = rl_phy_readreg(sc, PHY_ANAR); if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { ifmr->ifm_active = IFM_ETHER|IFM_100_T4; } else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) { ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX; } else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) { ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX; } else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) { ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX; } else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) { ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX; } return; } static int rl_ioctl(ifp, command, data) struct ifnet *ifp; u_long command; caddr_t data; { struct rl_softc *sc = ifp->if_softc; struct ifreq *ifr = (struct ifreq *) data; int s, error = 0; s = splimp(); switch(command) { case SIOCSIFADDR: case SIOCGIFADDR: case SIOCSIFMTU: error = ether_ioctl(ifp, command, data); break; case SIOCSIFFLAGS: if (ifp->if_flags & IFF_UP) { rl_init(sc); } else { if (ifp->if_flags & IFF_RUNNING) rl_stop(sc); } error = 0; break; case SIOCADDMULTI: case SIOCDELMULTI: rl_setmulti(sc); error = 0; break; case SIOCGIFMEDIA: case SIOCSIFMEDIA: error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); break; default: error = EINVAL; break; } (void)splx(s); return(error); } static void rl_watchdog(ifp) struct ifnet *ifp; { struct rl_softc *sc; sc = ifp->if_softc; if (sc->rl_autoneg) { rl_autoneg_mii(sc, RL_FLAG_DELAYTIMEO, 1); return; } printf("rl%d: watchdog timeout\n", sc->rl_unit); ifp->if_oerrors++; if (!(rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) printf("rl%d: no carrier - transceiver cable problem?\n", sc->rl_unit); rl_txeoc(sc); rl_txeof(sc); rl_rxeof(sc); rl_init(sc); return; } /* * Stop the adapter and free any mbufs allocated to the * RX and TX lists. */ static void rl_stop(sc) struct rl_softc *sc; { register int i; struct ifnet *ifp; ifp = &sc->arpcom.ac_if; ifp->if_timer = 0; CSR_WRITE_1(sc, RL_COMMAND, 0x00); CSR_WRITE_2(sc, RL_IMR, 0x0000); /* * Free the TX list buffers. */ for (i = 0; i < RL_TX_LIST_CNT; i++) { if (sc->rl_cdata.rl_tx_chain[i].rl_mbuf != NULL) { m_freem(sc->rl_cdata.rl_tx_chain[i].rl_mbuf); sc->rl_cdata.rl_tx_chain[i].rl_mbuf = NULL; CSR_WRITE_4(sc, RL_TXADDR0 + sc->rl_cdata.rl_tx_chain[i].rl_desc, 0x00000000); } } ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); return; } /* * Stop all chip I/O so that the kernel's probe routines don't * get confused by errant DMAs when rebooting. */ static void rl_shutdown(howto, arg) int howto; void *arg; { struct rl_softc *sc = (struct rl_softc *)arg; rl_stop(sc); return; } static struct pci_device rl_device = { "rl", rl_probe, rl_attach, &rl_count, NULL }; DATA_SET(pcidevice_set, rl_device); diff --git a/sys/pci/if_rlreg.h b/sys/pci/if_rlreg.h index 45956dd1ff3f..1825dbc400c6 100644 --- a/sys/pci/if_rlreg.h +++ b/sys/pci/if_rlreg.h @@ -1,564 +1,572 @@ /* * Copyright (c) 1997, 1998 * Bill Paul . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * - * $Id: if_rlreg.h,v 1.12 1998/10/07 22:52:34 wpaul Exp $ + * $Id: if_rlreg.h,v 1.13 1998/11/18 20:27:28 wpaul Exp $ */ /* * RealTek 8129/8139 register offsets */ #define RL_IDR0 0x0000 /* ID register 0 (station addr) */ #define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ #define RL_IDR2 0x0002 #define RL_IDR3 0x0003 #define RL_IDR4 0x0004 #define RL_IDR5 0x0005 /* 0006-0007 reserved */ #define RL_MAR0 0x0008 /* Multicast hash table */ #define RL_MAR1 0x0009 #define RL_MAR2 0x000A #define RL_MAR3 0x000B #define RL_MAR4 0x000C #define RL_MAR5 0x000D #define RL_MAR6 0x000E #define RL_MAR7 0x000F #define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ #define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ #define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ #define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ #define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ #define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ #define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ #define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ #define RL_RXADDR 0x0030 /* RX ring start address */ #define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ #define RL_RX_EARLY_STAT 0x0036 /* RX early status */ #define RL_COMMAND 0x0037 /* command register */ #define RL_CURRXADDR 0x0038 /* current address of packet read */ #define RL_CURRXBUF 0x003A /* current RX buffer address */ #define RL_IMR 0x003C /* interrupt mask register */ #define RL_ISR 0x003E /* interrupt status register */ #define RL_TXCFG 0x0040 /* transmit config */ #define RL_RXCFG 0x0044 /* receive config */ #define RL_TIMERCNT 0x0048 /* timer count register */ #define RL_MISSEDPKT 0x004C /* missed packet counter */ #define RL_EECMD 0x0050 /* EEPROM command register */ #define RL_CFG0 0x0051 /* config register #0 */ #define RL_CFG1 0x0052 /* config register #1 */ /* 0053-0057 reserved */ #define RL_MEDIASTAT 0x0058 /* media status register (8139) */ /* 0059-005A reserved */ #define RL_MII 0x005A /* 8129 chip only */ #define RL_HALTCLK 0x005B #define RL_MULTIINTR 0x005C /* multiple interrupt */ #define RL_PCIREV 0x005E /* PCI revision value */ /* 005F reserved */ #define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ /* Direct PHY access registers only available on 8139 */ #define RL_BMCR 0x0062 /* PHY basic mode control */ #define RL_BMSR 0x0064 /* PHY basic mode status */ #define RL_ANAR 0x0066 /* PHY autoneg advert */ #define RL_LPAR 0x0068 /* PHY link partner ability */ #define RL_ANER 0x006A /* PHY autoneg expansion */ #define RL_DISCCNT 0x006C /* disconnect counter */ #define RL_FALSECAR 0x006E /* false carrier counter */ #define RL_NWAYTST 0x0070 /* NWAY test register */ #define RL_RX_ER 0x0072 /* RX_ER counter */ #define RL_CSCFG 0x0074 /* CS configuration register */ /* * TX config register bits */ #define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ #define RL_TXCFG_MXDMA0 0x00000100 /* max DMA burst size */ #define RL_TXCFG_MXDMA1 0x00000200 #define RL_TXCFG_MXDMA2 0x00000400 #define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ #define RL_TXCFG_LOOPBKTST0 0x00020000 /* loopback test */ #define RL_TXCFG_LOOPBKTST1 0x00040000 /* loopback test */ #define RL_TXCFG_IFG0 0x01000000 /* interframe gap */ #define RL_TXCFG_IFG1 0x02000000 /* interframe gap */ /* * Transmit descriptor status register bits. */ #define RL_TXSTAT_LENMASK 0x00001FFF #define RL_TXSTAT_OWN 0x00002000 #define RL_TXSTAT_TX_UNDERRUN 0x00004000 #define RL_TXSTAT_TX_OK 0x00008000 #define RL_TXSTAT_EARLY_THRESH 0x003F0000 #define RL_TXSTAT_COLLCNT 0x0F000000 #define RL_TXSTAT_CARR_HBEAT 0x10000000 #define RL_TXSTAT_OUTOFWIN 0x20000000 #define RL_TXSTAT_TXABRT 0x40000000 #define RL_TXSTAT_CARRLOSS 0x80000000 /* * Interrupt status register bits. */ #define RL_ISR_RX_OK 0x0001 #define RL_ISR_RX_ERR 0x0002 #define RL_ISR_TX_OK 0x0004 #define RL_ISR_TX_ERR 0x0008 #define RL_ISR_RX_OVERRUN 0x0010 #define RL_ISR_PKT_UNDERRUN 0x0020 #define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ #define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ #define RL_ISR_SYSTEM_ERR 0x8000 #define RL_INTRS \ (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) /* * Media status register. (8139 only) */ #define RL_MEDIASTAT_RXPAUSE 0x01 #define RL_MEDIASTAT_TXPAUSE 0x02 #define RL_MEDIASTAT_LINK 0x04 #define RL_MEDIASTAT_SPEED10 0x08 #define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ #define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ /* * Receive config register. */ #define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ #define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ #define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ #define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ #define RL_RXCFG_RX_RUNT 0x00000010 #define RL_RXCFG_RX_ERRPKT 0x00000020 #define RL_RXCFG_WRAP 0x00000080 #define RL_RXCFG_MAXDMA (0x00000100|0x00000200|0x00000400) #define RL_RXCFG_BUFSZ (0x00000800|0x00001000) #define RL_RXCFG_FIFOTHRESH (0x00002000|0x00004000|0x00008000) #define RL_RXCFG_EARLYTHRESH (0x01000000|0x02000000|0x04000000) #define RL_RXBUF_8 0x00000000 #define RL_RXBUF_16 0x00000800 #define RL_RXBUF_32 0x00001000 #define RL_RXBUF_64 (0x00001000|0x00000800) /* * Bits in RX status header (included with RX'ed packet * in ring buffer). */ #define RL_RXSTAT_RXOK 0x00000001 #define RL_RXSTAT_ALIGNERR 0x00000002 #define RL_RXSTAT_CRCERR 0x00000004 #define RL_RXSTAT_GIANT 0x00000008 #define RL_RXSTAT_RUNT 0x00000010 #define RL_RXSTAT_BADSYM 0x00000020 #define RL_RXSTAT_BROAD 0x00002000 #define RL_RXSTAT_INDIV 0x00004000 #define RL_RXSTAT_MULTI 0x00008000 #define RL_RXSTAT_LENMASK 0xFFFF0000 #define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ /* * Command register. */ #define RL_CMD_EMPTY_RXBUF 0x0001 #define RL_CMD_TX_ENB 0x0004 #define RL_CMD_RX_ENB 0x0008 #define RL_CMD_RESET 0x0010 /* * EEPROM control register */ #define RL_EE_DATAOUT 0x01 /* Data out */ #define RL_EE_DATAIN 0x02 /* Data in */ #define RL_EE_CLK 0x04 /* clock */ #define RL_EE_SEL 0x08 /* chip select */ #define RL_EE_MODE (0x40|0x80) #define RL_EEMODE_OFF 0x00 #define RL_EEMODE_AUTOLOAD 0x40 #define RL_EEMODE_PROGRAM 0x80 #define RL_EEMODE_WRITECFG (0x80|0x40) /* 9346 EEPROM commands */ #define RL_EECMD_WRITE 0x140 #define RL_EECMD_READ 0x180 #define RL_EECMD_ERASE 0x1c0 #define RL_EE_ID 0x00 #define RL_EE_PCI_VID 0x01 #define RL_EE_PCI_DID 0x02 /* Location of station address inside EEPROM */ #define RL_EE_EADDR 0x07 /* * MII register (8129 only) */ #define RL_MII_CLK 0x01 #define RL_MII_DATAIN 0x02 #define RL_MII_DATAOUT 0x04 #define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ /* * Config 0 register */ #define RL_CFG0_ROM0 0x01 #define RL_CFG0_ROM1 0x02 #define RL_CFG0_ROM2 0x04 #define RL_CFG0_PL0 0x08 #define RL_CFG0_PL1 0x10 #define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ #define RL_CFG0_PCS 0x40 #define RL_CFG0_SCR 0x80 /* * Config 1 register */ #define RL_CFG1_PWRDWN 0x01 #define RL_CFG1_SLEEP 0x02 #define RL_CFG1_IOMAP 0x04 #define RL_CFG1_MEMMAP 0x08 #define RL_CFG1_RSVD 0x10 #define RL_CFG1_DRVLOAD 0x20 #define RL_CFG1_LED0 0x40 #define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ #define RL_CFG1_LED1 0x80 /* * The RealTek doesn't use a fragment-based descriptor mechanism. * Instead, there are only four register sets, each or which represents * one 'descriptor.' Basically, each TX descriptor is just a contiguous * packet buffer (32-bit aligned!) and we place the buffer addresses in * the registers so the chip knows where they are. * * We can sort of kludge together the same kind of buffer management * used in previous drivers, but we have to do buffer copies almost all * the time, so it doesn't really buy us much. * * For reception, there's just one large buffer where the chip stores * all received packets. */ #define RL_RX_BUF_SZ RL_RXBUF_64 #define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) #define RL_TX_LIST_CNT 4 #define RL_MIN_FRAMELEN 60 #define RL_TX_EARLYTHRESH 0x80000 /* 256 << 11 */ #define RL_RX_FIFOTHRESH 0x8000 /* 4 << 13 */ #define RL_RX_MAXDMA 0x00000400 #define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_BUF_SZ) struct rl_chain { char rl_desc; /* descriptor register idx */ struct mbuf *rl_mbuf; struct rl_chain *rl_next; }; struct rl_chain_data { u_int16_t cur_rx; caddr_t rl_rx_buf; struct rl_chain rl_tx_chain[RL_TX_LIST_CNT]; int rl_tx_cnt; struct rl_chain *rl_tx_cur; struct rl_chain *rl_tx_free; }; struct rl_type { u_int16_t rl_vid; u_int16_t rl_did; char *rl_name; }; struct rl_mii_frame { u_int8_t mii_stdelim; u_int8_t mii_opcode; u_int8_t mii_phyaddr; u_int8_t mii_regaddr; u_int8_t mii_turnaround; u_int16_t mii_data; }; /* * MII constants */ #define RL_MII_STARTDELIM 0x01 #define RL_MII_READOP 0x02 #define RL_MII_WRITEOP 0x01 #define RL_MII_TURNAROUND 0x02 #define RL_FLAG_FORCEDELAY 1 #define RL_FLAG_SCHEDDELAY 2 #define RL_FLAG_DELAYTIMEO 3 #define RL_8129 1 #define RL_8139 2 struct rl_softc { struct arpcom arpcom; /* interface info */ struct ifmedia ifmedia; /* media info */ u_int32_t iobase; /* pointer to PIO space */ #ifndef RL_USEIOSPACE volatile caddr_t csr; /* pointer to register map */ #endif struct rl_type *rl_pinfo; /* phy info */ u_int8_t rl_unit; /* interface number */ u_int8_t rl_type; u_int8_t rl_phy_addr; /* PHY address */ u_int8_t rl_tx_pend; /* TX pending */ u_int8_t rl_want_auto; u_int8_t rl_autoneg; u_int8_t rl_stats_no_timeout; struct rl_chain_data rl_cdata; }; /* * register space access macros */ #ifdef RL_USEIOSPACE #define CSR_WRITE_4(sc, reg, val) \ outl(sc->iobase + (u_int32_t)(reg), val) #define CSR_WRITE_2(sc, reg, val) \ outw(sc->iobase + (u_int32_t)(reg), val) #define CSR_WRITE_1(sc, reg, val) \ outb(sc->iobase + (u_int32_t)(reg), val) #define CSR_READ_4(sc, reg) \ inl(sc->iobase + (u_int32_t)(reg)) #define CSR_READ_2(sc, reg) \ inw(sc->iobase + (u_int32_t)(reg)) #define CSR_READ_1(sc, reg) \ inb(sc->iobase + (u_int32_t)(reg)) #else #define CSR_WRITE_4(sc, reg, val) \ ((*(u_int32_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int32_t)(val)) #define CSR_WRITE_2(sc, reg, val) \ ((*(u_int16_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int16_t)(val)) #define CSR_WRITE_1(sc, reg, val) \ ((*(u_int8_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int8_t)(val)) #define CSR_READ_4(sc, reg) \ (*(u_int32_t *)((sc)->csr + (u_int32_t)(reg))) #define CSR_READ_2(sc, reg) \ (*(u_int16_t *)((sc)->csr + (u_int32_t)(reg))) #define CSR_READ_1(sc, reg) \ (*(u_int8_t *)((sc)->csr + (u_int32_t)(reg))) #endif #define RL_TIMEOUT 1000 /* * General constants that are fun to know. * * RealTek PCI vendor ID */ #define RT_VENDORID 0x10EC -#define RT_VENDORID_ALT 0x1211 + +/* + * Accton PCI vendor ID + */ +#define ACCTON_VENDORID 0x1113 /* * RealTek chip device IDs. */ #define RT_DEVICEID_8129 0x8129 #define RT_DEVICEID_8139 0x8139 -#define RT_DEVICEID_8139_ALT 0x1211 + +/* + * Accton MPX 5030/5038 device ID. + */ +#define ACCTON_DEVICEID_5030 0x1211 /* * Texas Instruments PHY identifiers */ #define TI_PHY_VENDORID 0x4000 #define TI_PHY_10BT 0x501F #define TI_PHY_100VGPMI 0x502F /* * These ID values are for the NS DP83840A 10/100 PHY */ #define NS_PHY_VENDORID 0x2000 #define NS_PHY_83840A 0x5C0F /* * Level 1 10/100 PHY */ #define LEVEL1_PHY_VENDORID 0x7810 #define LEVEL1_PHY_LXT970 0x000F /* * Intel 82555 10/100 PHY */ #define INTEL_PHY_VENDORID 0x0A28 #define INTEL_PHY_82555 0x015F /* * SEEQ 80220 10/100 PHY */ #define SEEQ_PHY_VENDORID 0x0016 #define SEEQ_PHY_80220 0xF83F /* * PCI low memory base and low I/O base register, and * other PCI registers. Note: some are only available on * the 3c905B, in particular those that related to power management. */ #define RL_PCI_VENDOR_ID 0x00 #define RL_PCI_DEVICE_ID 0x02 #define RL_PCI_COMMAND 0x04 #define RL_PCI_STATUS 0x06 #define RL_PCI_CLASSCODE 0x09 #define RL_PCI_LATENCY_TIMER 0x0D #define RL_PCI_HEADER_TYPE 0x0E #define RL_PCI_LOIO 0x10 #define RL_PCI_LOMEM 0x14 #define RL_PCI_BIOSROM 0x30 #define RL_PCI_INTLINE 0x3C #define RL_PCI_INTPIN 0x3D #define RL_PCI_MINGNT 0x3E #define RL_PCI_MINLAT 0x0F #define RL_PCI_RESETOPT 0x48 #define RL_PCI_EEPROM_DATA 0x4C #define RL_PCI_CAPID 0xDC /* 8 bits */ #define RL_PCI_NEXTPTR 0xDD /* 8 bits */ #define RL_PCI_PWRMGMTCAP 0xDE /* 16 bits */ #define RL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ #define RL_PSTATE_MASK 0x0003 #define RL_PSTATE_D0 0x0000 #define RL_PSTATE_D1 0x0002 #define RL_PSTATE_D2 0x0002 #define RL_PSTATE_D3 0x0003 #define RL_PME_EN 0x0010 #define RL_PME_STATUS 0x8000 #define PHY_UNKNOWN 6 #define RL_PHYADDR_MIN 0x00 #define RL_PHYADDR_MAX 0x1F #define PHY_BMCR 0x00 #define PHY_BMSR 0x01 #define PHY_VENID 0x02 #define PHY_DEVID 0x03 #define PHY_ANAR 0x04 #define PHY_LPAR 0x05 #define PHY_ANEXP 0x06 #define PHY_ANAR_NEXTPAGE 0x8000 #define PHY_ANAR_RSVD0 0x4000 #define PHY_ANAR_TLRFLT 0x2000 #define PHY_ANAR_RSVD1 0x1000 #define PHY_ANAR_RSVD2 0x0800 #define PHY_ANAR_RSVD3 0x0400 #define PHY_ANAR_100BT4 0x0200 #define PHY_ANAR_100BTXFULL 0x0100 #define PHY_ANAR_100BTXHALF 0x0080 #define PHY_ANAR_10BTFULL 0x0040 #define PHY_ANAR_10BTHALF 0x0020 #define PHY_ANAR_PROTO4 0x0010 #define PHY_ANAR_PROTO3 0x0008 #define PHY_ANAR_PROTO2 0x0004 #define PHY_ANAR_PROTO1 0x0002 #define PHY_ANAR_PROTO0 0x0001 /* * These are the register definitions for the PHY (physical layer * interface chip). */ /* * PHY BMCR Basic Mode Control Register */ #define PHY_BMCR_RESET 0x8000 #define PHY_BMCR_LOOPBK 0x4000 #define PHY_BMCR_SPEEDSEL 0x2000 #define PHY_BMCR_AUTONEGENBL 0x1000 #define PHY_BMCR_RSVD0 0x0800 /* write as zero */ #define PHY_BMCR_ISOLATE 0x0400 #define PHY_BMCR_AUTONEGRSTR 0x0200 #define PHY_BMCR_DUPLEX 0x0100 #define PHY_BMCR_COLLTEST 0x0080 #define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ #define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ #define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ #define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ #define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ #define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ #define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ /* * RESET: 1 == software reset, 0 == normal operation * Resets status and control registers to default values. * Relatches all hardware config values. * * LOOPBK: 1 == loopback operation enabled, 0 == normal operation * * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s * Link speed is selected byt his bit or if auto-negotiation if bit * 12 (AUTONEGENBL) is set (in which case the value of this register * is ignored). * * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 * determine speed and mode. Should be cleared and then set if PHY configured * for no autoneg on startup. * * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation * * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation * * DUPLEX: 1 == full duplex mode, 0 == half duplex mode * * COLLTEST: 1 == collision test enabled, 0 == normal operation */ /* * PHY, BMSR Basic Mode Status Register */ #define PHY_BMSR_100BT4 0x8000 #define PHY_BMSR_100BTXFULL 0x4000 #define PHY_BMSR_100BTXHALF 0x2000 #define PHY_BMSR_10BTFULL 0x1000 #define PHY_BMSR_10BTHALF 0x0800 #define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ #define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ #define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ #define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ #define PHY_BMSR_MFPRESUP 0x0040 #define PHY_BMSR_AUTONEGCOMP 0x0020 #define PHY_BMSR_REMFAULT 0x0010 #define PHY_BMSR_CANAUTONEG 0x0008 #define PHY_BMSR_LINKSTAT 0x0004 #define PHY_BMSR_JABBER 0x0002 #define PHY_BMSR_EXTENDED 0x0001