diff --git a/sys/dev/age/if_age.c b/sys/dev/age/if_age.c index 75d0e5c80952..b712ff141e69 100644 --- a/sys/dev/age/if_age.c +++ b/sys/dev/age/if_age.c @@ -1,3339 +1,3338 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2008, Pyun YongHyeon * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* "device miibus" required. See GENERIC if you get errors here. */ #include "miibus_if.h" #define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) MODULE_DEPEND(age, pci, 1, 1, 1); MODULE_DEPEND(age, ether, 1, 1, 1); MODULE_DEPEND(age, miibus, 1, 1, 1); /* Tunables. */ static int msi_disable = 0; static int msix_disable = 0; TUNABLE_INT("hw.age.msi_disable", &msi_disable); TUNABLE_INT("hw.age.msix_disable", &msix_disable); /* * Devices supported by this driver. */ static struct age_dev { uint16_t age_vendorid; uint16_t age_deviceid; const char *age_name; } age_devs[] = { { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, "Attansic Technology Corp, L1 Gigabit Ethernet" }, }; static int age_miibus_readreg(device_t, int, int); static int age_miibus_writereg(device_t, int, int, int); static void age_miibus_statchg(device_t); -static void age_mediastatus(struct ifnet *, struct ifmediareq *); -static int age_mediachange(struct ifnet *); +static void age_mediastatus(if_t, struct ifmediareq *); +static int age_mediachange(if_t); static int age_probe(device_t); static void age_get_macaddr(struct age_softc *); static void age_phy_reset(struct age_softc *); static int age_attach(device_t); static int age_detach(device_t); static void age_sysctl_node(struct age_softc *); static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); static int age_check_boundary(struct age_softc *); static int age_dma_alloc(struct age_softc *); static void age_dma_free(struct age_softc *); static int age_shutdown(device_t); static void age_setwol(struct age_softc *); static int age_suspend(device_t); static int age_resume(device_t); static int age_encap(struct age_softc *, struct mbuf **); -static void age_start(struct ifnet *); -static void age_start_locked(struct ifnet *); +static void age_start(if_t); +static void age_start_locked(if_t); static void age_watchdog(struct age_softc *); -static int age_ioctl(struct ifnet *, u_long, caddr_t); +static int age_ioctl(if_t, u_long, caddr_t); static void age_mac_config(struct age_softc *); static void age_link_task(void *, int); static void age_stats_update(struct age_softc *); static int age_intr(void *); static void age_int_task(void *, int); static void age_txintr(struct age_softc *, int); static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); static int age_rxintr(struct age_softc *, int, int); static void age_tick(void *); static void age_reset(struct age_softc *); static void age_init(void *); static void age_init_locked(struct age_softc *); static void age_stop(struct age_softc *); static void age_stop_txmac(struct age_softc *); static void age_stop_rxmac(struct age_softc *); static void age_init_tx_ring(struct age_softc *); static int age_init_rx_ring(struct age_softc *); static void age_init_rr_ring(struct age_softc *); static void age_init_cmb_block(struct age_softc *); static void age_init_smb_block(struct age_softc *); #ifndef __NO_STRICT_ALIGNMENT -static struct mbuf *age_fixup_rx(struct ifnet *, struct mbuf *); +static struct mbuf *age_fixup_rx(if_t, struct mbuf *); #endif static int age_newbuf(struct age_softc *, struct age_rxdesc *); static void age_rxvlan(struct age_softc *); static void age_rxfilter(struct age_softc *); static int sysctl_age_stats(SYSCTL_HANDLER_ARGS); static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS); static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); static device_method_t age_methods[] = { /* Device interface. */ DEVMETHOD(device_probe, age_probe), DEVMETHOD(device_attach, age_attach), DEVMETHOD(device_detach, age_detach), DEVMETHOD(device_shutdown, age_shutdown), DEVMETHOD(device_suspend, age_suspend), DEVMETHOD(device_resume, age_resume), /* MII interface. */ DEVMETHOD(miibus_readreg, age_miibus_readreg), DEVMETHOD(miibus_writereg, age_miibus_writereg), DEVMETHOD(miibus_statchg, age_miibus_statchg), { NULL, NULL } }; static driver_t age_driver = { "age", age_methods, sizeof(struct age_softc) }; DRIVER_MODULE(age, pci, age_driver, 0, 0); MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, age, age_devs, nitems(age_devs)); DRIVER_MODULE(miibus, age, miibus_driver, 0, 0); static struct resource_spec age_res_spec_mem[] = { { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, { -1, 0, 0 } }; static struct resource_spec age_irq_spec_legacy[] = { { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, { -1, 0, 0 } }; static struct resource_spec age_irq_spec_msi[] = { { SYS_RES_IRQ, 1, RF_ACTIVE }, { -1, 0, 0 } }; static struct resource_spec age_irq_spec_msix[] = { { SYS_RES_IRQ, 1, RF_ACTIVE }, { -1, 0, 0 } }; /* * Read a PHY register on the MII of the L1. */ static int age_miibus_readreg(device_t dev, int phy, int reg) { struct age_softc *sc; uint32_t v; int i; sc = device_get_softc(dev); CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); for (i = AGE_PHY_TIMEOUT; i > 0; i--) { DELAY(1); v = CSR_READ_4(sc, AGE_MDIO); if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) break; } if (i == 0) { device_printf(sc->age_dev, "phy read timeout : %d\n", reg); return (0); } return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); } /* * Write a PHY register on the MII of the L1. */ static int age_miibus_writereg(device_t dev, int phy, int reg, int val) { struct age_softc *sc; uint32_t v; int i; sc = device_get_softc(dev); CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); for (i = AGE_PHY_TIMEOUT; i > 0; i--) { DELAY(1); v = CSR_READ_4(sc, AGE_MDIO); if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) break; } if (i == 0) device_printf(sc->age_dev, "phy write timeout : %d\n", reg); return (0); } /* * Callback from MII layer when media changes. */ static void age_miibus_statchg(device_t dev) { struct age_softc *sc; sc = device_get_softc(dev); taskqueue_enqueue(taskqueue_swi, &sc->age_link_task); } /* * Get the current interface media status. */ static void -age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) +age_mediastatus(if_t ifp, struct ifmediareq *ifmr) { struct age_softc *sc; struct mii_data *mii; - sc = ifp->if_softc; + sc = if_getsoftc(ifp); AGE_LOCK(sc); mii = device_get_softc(sc->age_miibus); mii_pollstat(mii); ifmr->ifm_status = mii->mii_media_status; ifmr->ifm_active = mii->mii_media_active; AGE_UNLOCK(sc); } /* * Set hardware to newly-selected media. */ static int -age_mediachange(struct ifnet *ifp) +age_mediachange(if_t ifp) { struct age_softc *sc; struct mii_data *mii; struct mii_softc *miisc; int error; - sc = ifp->if_softc; + sc = if_getsoftc(ifp); AGE_LOCK(sc); mii = device_get_softc(sc->age_miibus); LIST_FOREACH(miisc, &mii->mii_phys, mii_list) PHY_RESET(miisc); error = mii_mediachg(mii); AGE_UNLOCK(sc); return (error); } static int age_probe(device_t dev) { struct age_dev *sp; int i; uint16_t vendor, devid; vendor = pci_get_vendor(dev); devid = pci_get_device(dev); sp = age_devs; for (i = 0; i < nitems(age_devs); i++, sp++) { if (vendor == sp->age_vendorid && devid == sp->age_deviceid) { device_set_desc(dev, sp->age_name); return (BUS_PROBE_DEFAULT); } } return (ENXIO); } static void age_get_macaddr(struct age_softc *sc) { uint32_t ea[2], reg; int i, vpdc; reg = CSR_READ_4(sc, AGE_SPI_CTRL); if ((reg & SPI_VPD_ENB) != 0) { /* Get VPD stored in TWSI EEPROM. */ reg &= ~SPI_VPD_ENB; CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); } if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) { /* * PCI VPD capability found, let TWSI reload EEPROM. * This will set ethernet address of controller. */ CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | TWSI_CTRL_SW_LD_START); for (i = 100; i > 0; i--) { DELAY(1000); reg = CSR_READ_4(sc, AGE_TWSI_CTRL); if ((reg & TWSI_CTRL_SW_LD_START) == 0) break; } if (i == 0) device_printf(sc->age_dev, "reloading EEPROM timeout!\n"); } else { if (bootverbose) device_printf(sc->age_dev, "PCI VPD capability not found!\n"); } ea[0] = CSR_READ_4(sc, AGE_PAR0); ea[1] = CSR_READ_4(sc, AGE_PAR1); sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; } static void age_phy_reset(struct age_softc *sc) { uint16_t reg, pn; int i, linkup; /* Reset PHY. */ CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); DELAY(2000); CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); DELAY(2000); #define ATPHY_DBG_ADDR 0x1D #define ATPHY_DBG_DATA 0x1E #define ATPHY_CDTC 0x16 #define PHY_CDTC_ENB 0x0001 #define PHY_CDTC_POFF 8 #define ATPHY_CDTS 0x1C #define PHY_CDTS_STAT_OK 0x0000 #define PHY_CDTS_STAT_SHORT 0x0100 #define PHY_CDTS_STAT_OPEN 0x0200 #define PHY_CDTS_STAT_INVAL 0x0300 #define PHY_CDTS_STAT_MASK 0x0300 /* Check power saving mode. Magic from Linux. */ age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); for (linkup = 0, pn = 0; pn < 4; pn++) { age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC, (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); for (i = 200; i > 0; i--) { DELAY(1000); reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC); if ((reg & PHY_CDTC_ENB) == 0) break; } DELAY(1000); reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTS); if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { linkup++; break; } } age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); if (linkup == 0) { age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_DBG_ADDR, 0); age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_DBG_DATA, 0x124E); age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_DBG_ADDR, 1); reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, ATPHY_DBG_DATA); age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_DBG_DATA, reg | 0x03); /* XXX */ DELAY(1500 * 1000); age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_DBG_ADDR, 0); age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_DBG_DATA, 0x024E); } #undef ATPHY_DBG_ADDR #undef ATPHY_DBG_DATA #undef ATPHY_CDTC #undef PHY_CDTC_ENB #undef PHY_CDTC_POFF #undef ATPHY_CDTS #undef PHY_CDTS_STAT_OK #undef PHY_CDTS_STAT_SHORT #undef PHY_CDTS_STAT_OPEN #undef PHY_CDTS_STAT_INVAL #undef PHY_CDTS_STAT_MASK } static int age_attach(device_t dev) { struct age_softc *sc; - struct ifnet *ifp; + if_t ifp; uint16_t burst; int error, i, msic, msixc, pmc; error = 0; sc = device_get_softc(dev); sc->age_dev = dev; mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0); TASK_INIT(&sc->age_int_task, 0, age_int_task, sc); TASK_INIT(&sc->age_link_task, 0, age_link_task, sc); /* Map the device. */ pci_enable_busmaster(dev); sc->age_res_spec = age_res_spec_mem; sc->age_irq_spec = age_irq_spec_legacy; error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res); if (error != 0) { device_printf(dev, "cannot allocate memory resources.\n"); goto fail; } /* Set PHY address. */ sc->age_phyaddr = AGE_PHY_ADDR; /* Reset PHY. */ age_phy_reset(sc); /* Reset the ethernet controller. */ age_reset(sc); /* Get PCI and chip id/revision. */ sc->age_rev = pci_get_revid(dev); sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> MASTER_CHIP_REV_SHIFT; if (bootverbose) { device_printf(dev, "PCI device revision : 0x%04x\n", sc->age_rev); device_printf(dev, "Chip id/revision : 0x%04x\n", sc->age_chip_rev); } /* * XXX * Unintialized hardware returns an invalid chip id/revision * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that * unplugged cable results in putting hardware into automatic * power down mode which in turn returns invalld chip revision. */ if (sc->age_chip_rev == 0xFFFF) { device_printf(dev,"invalid chip revision : 0x%04x -- " "not initialized?\n", sc->age_chip_rev); error = ENXIO; goto fail; } device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); /* Allocate IRQ resources. */ msixc = pci_msix_count(dev); msic = pci_msi_count(dev); if (bootverbose) { device_printf(dev, "MSIX count : %d\n", msixc); device_printf(dev, "MSI count : %d\n", msic); } /* Prefer MSIX over MSI. */ if (msix_disable == 0 || msi_disable == 0) { if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES && pci_alloc_msix(dev, &msixc) == 0) { if (msic == AGE_MSIX_MESSAGES) { device_printf(dev, "Using %d MSIX messages.\n", msixc); sc->age_flags |= AGE_FLAG_MSIX; sc->age_irq_spec = age_irq_spec_msix; } else pci_release_msi(dev); } if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 && msic == AGE_MSI_MESSAGES && pci_alloc_msi(dev, &msic) == 0) { if (msic == AGE_MSI_MESSAGES) { device_printf(dev, "Using %d MSI messages.\n", msic); sc->age_flags |= AGE_FLAG_MSI; sc->age_irq_spec = age_irq_spec_msi; } else pci_release_msi(dev); } } error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq); if (error != 0) { device_printf(dev, "cannot allocate IRQ resources.\n"); goto fail; } /* Get DMA parameters from PCIe device control register. */ if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { sc->age_flags |= AGE_FLAG_PCIE; burst = pci_read_config(dev, i + 0x08, 2); /* Max read request size. */ sc->age_dma_rd_burst = ((burst >> 12) & 0x07) << DMA_CFG_RD_BURST_SHIFT; /* Max payload size. */ sc->age_dma_wr_burst = ((burst >> 5) & 0x07) << DMA_CFG_WR_BURST_SHIFT; if (bootverbose) { device_printf(dev, "Read request size : %d bytes.\n", 128 << ((burst >> 12) & 0x07)); device_printf(dev, "TLP payload size : %d bytes.\n", 128 << ((burst >> 5) & 0x07)); } } else { sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; } /* Create device sysctl node. */ age_sysctl_node(sc); if ((error = age_dma_alloc(sc)) != 0) goto fail; /* Load station address. */ age_get_macaddr(sc); ifp = sc->age_ifp = if_alloc(IFT_ETHER); if (ifp == NULL) { device_printf(dev, "cannot allocate ifnet structure.\n"); error = ENXIO; goto fail; } - ifp->if_softc = sc; + if_setsoftc(ifp, sc); if_initname(ifp, device_get_name(dev), device_get_unit(dev)); - ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; - ifp->if_ioctl = age_ioctl; - ifp->if_start = age_start; - ifp->if_init = age_init; - ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1; - IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); - IFQ_SET_READY(&ifp->if_snd); - ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; - ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO; + if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); + if_setioctlfn(ifp, age_ioctl); + if_setstartfn(ifp, age_start); + if_setinitfn(ifp, age_init); + if_setsendqlen(ifp, AGE_TX_RING_CNT - 1); + if_setsendqready(ifp); + if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_TSO4); + if_sethwassist(ifp, AGE_CSUM_FEATURES | CSUM_TSO); if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { sc->age_flags |= AGE_FLAG_PMCAP; - ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; + if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); } - ifp->if_capenable = ifp->if_capabilities; + if_setcapenable(ifp, if_getcapabilities(ifp)); /* Set up MII bus. */ error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange, age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY, 0); if (error != 0) { device_printf(dev, "attaching PHYs failed\n"); goto fail; } ether_ifattach(ifp, sc->age_eaddr); /* VLAN capability setup. */ - ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | - IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; - ifp->if_capenable = ifp->if_capabilities; + if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | + IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); + if_setcapenable(ifp, if_getcapabilities(ifp)); /* Tell the upper layer(s) we support long frames. */ - ifp->if_hdrlen = sizeof(struct ether_vlan_header); + if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); /* Create local taskq. */ sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK, taskqueue_thread_enqueue, &sc->age_tq); if (sc->age_tq == NULL) { device_printf(dev, "could not create taskqueue.\n"); ether_ifdetach(ifp); error = ENXIO; goto fail; } taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq", device_get_nameunit(sc->age_dev)); if ((sc->age_flags & AGE_FLAG_MSIX) != 0) msic = AGE_MSIX_MESSAGES; else if ((sc->age_flags & AGE_FLAG_MSI) != 0) msic = AGE_MSI_MESSAGES; else msic = 1; for (i = 0; i < msic; i++) { error = bus_setup_intr(dev, sc->age_irq[i], INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc, &sc->age_intrhand[i]); if (error != 0) break; } if (error != 0) { device_printf(dev, "could not set up interrupt handler.\n"); taskqueue_free(sc->age_tq); sc->age_tq = NULL; ether_ifdetach(ifp); goto fail; } fail: if (error != 0) age_detach(dev); return (error); } static int age_detach(device_t dev) { struct age_softc *sc; - struct ifnet *ifp; + if_t ifp; int i, msic; sc = device_get_softc(dev); ifp = sc->age_ifp; if (device_is_attached(dev)) { AGE_LOCK(sc); sc->age_flags |= AGE_FLAG_DETACH; age_stop(sc); AGE_UNLOCK(sc); callout_drain(&sc->age_tick_ch); taskqueue_drain(sc->age_tq, &sc->age_int_task); taskqueue_drain(taskqueue_swi, &sc->age_link_task); ether_ifdetach(ifp); } if (sc->age_tq != NULL) { taskqueue_drain(sc->age_tq, &sc->age_int_task); taskqueue_free(sc->age_tq); sc->age_tq = NULL; } if (sc->age_miibus != NULL) { device_delete_child(dev, sc->age_miibus); sc->age_miibus = NULL; } bus_generic_detach(dev); age_dma_free(sc); if (ifp != NULL) { if_free(ifp); sc->age_ifp = NULL; } if ((sc->age_flags & AGE_FLAG_MSIX) != 0) msic = AGE_MSIX_MESSAGES; else if ((sc->age_flags & AGE_FLAG_MSI) != 0) msic = AGE_MSI_MESSAGES; else msic = 1; for (i = 0; i < msic; i++) { if (sc->age_intrhand[i] != NULL) { bus_teardown_intr(dev, sc->age_irq[i], sc->age_intrhand[i]); sc->age_intrhand[i] = NULL; } } bus_release_resources(dev, sc->age_irq_spec, sc->age_irq); if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0) pci_release_msi(dev); bus_release_resources(dev, sc->age_res_spec, sc->age_res); mtx_destroy(&sc->age_mtx); return (0); } static void age_sysctl_node(struct age_softc *sc) { int error; SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, "stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, sysctl_age_stats, "I", "Statistics"); SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, "int_mod", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->age_int_mod, 0, sysctl_hw_age_int_mod, "I", "age interrupt moderation"); /* Pull in device tunables. */ sc->age_int_mod = AGE_IM_TIMER_DEFAULT; error = resource_int_value(device_get_name(sc->age_dev), device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); if (error == 0) { if (sc->age_int_mod < AGE_IM_TIMER_MIN || sc->age_int_mod > AGE_IM_TIMER_MAX) { device_printf(sc->age_dev, "int_mod value out of range; using default: %d\n", AGE_IM_TIMER_DEFAULT); sc->age_int_mod = AGE_IM_TIMER_DEFAULT; } } SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->age_process_limit, 0, sysctl_hw_age_proc_limit, "I", "max number of Rx events to process"); /* Pull in device tunables. */ sc->age_process_limit = AGE_PROC_DEFAULT; error = resource_int_value(device_get_name(sc->age_dev), device_get_unit(sc->age_dev), "process_limit", &sc->age_process_limit); if (error == 0) { if (sc->age_process_limit < AGE_PROC_MIN || sc->age_process_limit > AGE_PROC_MAX) { device_printf(sc->age_dev, "process_limit value out of range; " "using default: %d\n", AGE_PROC_DEFAULT); sc->age_process_limit = AGE_PROC_DEFAULT; } } } struct age_dmamap_arg { bus_addr_t age_busaddr; }; static void age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) { struct age_dmamap_arg *ctx; if (error != 0) return; KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); ctx = (struct age_dmamap_arg *)arg; ctx->age_busaddr = segs[0].ds_addr; } /* * Attansic L1 controller have single register to specify high * address part of DMA blocks. So all descriptor structures and * DMA memory blocks should have the same high address of given * 4GB address space(i.e. crossing 4GB boundary is not allowed). */ static int age_check_boundary(struct age_softc *sc) { bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; bus_addr_t cmb_block_end, smb_block_end; /* Tx/Rx descriptor queue should reside within 4GB boundary. */ tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || (AGE_ADDR_HI(rx_ring_end) != AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || (AGE_ADDR_HI(rr_ring_end) != AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || (AGE_ADDR_HI(cmb_block_end) != AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || (AGE_ADDR_HI(smb_block_end) != AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) return (EFBIG); if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) return (EFBIG); return (0); } static int age_dma_alloc(struct age_softc *sc) { struct age_txdesc *txd; struct age_rxdesc *rxd; bus_addr_t lowaddr; struct age_dmamap_arg ctx; int error, i; lowaddr = BUS_SPACE_MAXADDR; again: /* Create parent ring/DMA block tag. */ error = bus_dma_tag_create( bus_get_dma_tag(sc->age_dev), /* parent */ 1, 0, /* alignment, boundary */ lowaddr, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 0, /* nsegments */ BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->age_cdata.age_parent_tag); if (error != 0) { device_printf(sc->age_dev, "could not create parent DMA tag.\n"); goto fail; } /* Create tag for Tx ring. */ error = bus_dma_tag_create( sc->age_cdata.age_parent_tag, /* parent */ AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ AGE_TX_RING_SZ, /* maxsize */ 1, /* nsegments */ AGE_TX_RING_SZ, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->age_cdata.age_tx_ring_tag); if (error != 0) { device_printf(sc->age_dev, "could not create Tx ring DMA tag.\n"); goto fail; } /* Create tag for Rx ring. */ error = bus_dma_tag_create( sc->age_cdata.age_parent_tag, /* parent */ AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ AGE_RX_RING_SZ, /* maxsize */ 1, /* nsegments */ AGE_RX_RING_SZ, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->age_cdata.age_rx_ring_tag); if (error != 0) { device_printf(sc->age_dev, "could not create Rx ring DMA tag.\n"); goto fail; } /* Create tag for Rx return ring. */ error = bus_dma_tag_create( sc->age_cdata.age_parent_tag, /* parent */ AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ AGE_RR_RING_SZ, /* maxsize */ 1, /* nsegments */ AGE_RR_RING_SZ, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->age_cdata.age_rr_ring_tag); if (error != 0) { device_printf(sc->age_dev, "could not create Rx return ring DMA tag.\n"); goto fail; } /* Create tag for coalesing message block. */ error = bus_dma_tag_create( sc->age_cdata.age_parent_tag, /* parent */ AGE_CMB_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ AGE_CMB_BLOCK_SZ, /* maxsize */ 1, /* nsegments */ AGE_CMB_BLOCK_SZ, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->age_cdata.age_cmb_block_tag); if (error != 0) { device_printf(sc->age_dev, "could not create CMB DMA tag.\n"); goto fail; } /* Create tag for statistics message block. */ error = bus_dma_tag_create( sc->age_cdata.age_parent_tag, /* parent */ AGE_SMB_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ AGE_SMB_BLOCK_SZ, /* maxsize */ 1, /* nsegments */ AGE_SMB_BLOCK_SZ, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->age_cdata.age_smb_block_tag); if (error != 0) { device_printf(sc->age_dev, "could not create SMB DMA tag.\n"); goto fail; } /* Allocate DMA'able memory and load the DMA map. */ error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, (void **)&sc->age_rdata.age_tx_ring, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->age_cdata.age_tx_ring_map); if (error != 0) { device_printf(sc->age_dev, "could not allocate DMA'able memory for Tx ring.\n"); goto fail; } ctx.age_busaddr = 0; error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); if (error != 0 || ctx.age_busaddr == 0) { device_printf(sc->age_dev, "could not load DMA'able memory for Tx ring.\n"); goto fail; } sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; /* Rx ring */ error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, (void **)&sc->age_rdata.age_rx_ring, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->age_cdata.age_rx_ring_map); if (error != 0) { device_printf(sc->age_dev, "could not allocate DMA'able memory for Rx ring.\n"); goto fail; } ctx.age_busaddr = 0; error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); if (error != 0 || ctx.age_busaddr == 0) { device_printf(sc->age_dev, "could not load DMA'able memory for Rx ring.\n"); goto fail; } sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; /* Rx return ring */ error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, (void **)&sc->age_rdata.age_rr_ring, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->age_cdata.age_rr_ring_map); if (error != 0) { device_printf(sc->age_dev, "could not allocate DMA'able memory for Rx return ring.\n"); goto fail; } ctx.age_busaddr = 0; error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, age_dmamap_cb, &ctx, 0); if (error != 0 || ctx.age_busaddr == 0) { device_printf(sc->age_dev, "could not load DMA'able memory for Rx return ring.\n"); goto fail; } sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; /* CMB block */ error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, (void **)&sc->age_rdata.age_cmb_block, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->age_cdata.age_cmb_block_map); if (error != 0) { device_printf(sc->age_dev, "could not allocate DMA'able memory for CMB block.\n"); goto fail; } ctx.age_busaddr = 0; error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); if (error != 0 || ctx.age_busaddr == 0) { device_printf(sc->age_dev, "could not load DMA'able memory for CMB block.\n"); goto fail; } sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; /* SMB block */ error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, (void **)&sc->age_rdata.age_smb_block, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->age_cdata.age_smb_block_map); if (error != 0) { device_printf(sc->age_dev, "could not allocate DMA'able memory for SMB block.\n"); goto fail; } ctx.age_busaddr = 0; error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); if (error != 0 || ctx.age_busaddr == 0) { device_printf(sc->age_dev, "could not load DMA'able memory for SMB block.\n"); goto fail; } sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; /* * All ring buffer and DMA blocks should have the same * high address part of 64bit DMA address space. */ if (lowaddr != BUS_SPACE_MAXADDR_32BIT && (error = age_check_boundary(sc)) != 0) { device_printf(sc->age_dev, "4GB boundary crossed, " "switching to 32bit DMA addressing mode.\n"); age_dma_free(sc); /* Limit DMA address space to 32bit and try again. */ lowaddr = BUS_SPACE_MAXADDR_32BIT; goto again; } /* * Create Tx/Rx buffer parent tag. * L1 supports full 64bit DMA addressing in Tx/Rx buffers * so it needs separate parent DMA tag. * XXX * It seems enabling 64bit DMA causes data corruption. Limit * DMA address space to 32bit. */ error = bus_dma_tag_create( bus_get_dma_tag(sc->age_dev), /* parent */ 1, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 0, /* nsegments */ BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->age_cdata.age_buffer_tag); if (error != 0) { device_printf(sc->age_dev, "could not create parent buffer DMA tag.\n"); goto fail; } /* Create tag for Tx buffers. */ error = bus_dma_tag_create( sc->age_cdata.age_buffer_tag, /* parent */ 1, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ AGE_TSO_MAXSIZE, /* maxsize */ AGE_MAXTXSEGS, /* nsegments */ AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->age_cdata.age_tx_tag); if (error != 0) { device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); goto fail; } /* Create tag for Rx buffers. */ error = bus_dma_tag_create( sc->age_cdata.age_buffer_tag, /* parent */ AGE_RX_BUF_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ MCLBYTES, /* maxsize */ 1, /* nsegments */ MCLBYTES, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->age_cdata.age_rx_tag); if (error != 0) { device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); goto fail; } /* Create DMA maps for Tx buffers. */ for (i = 0; i < AGE_TX_RING_CNT; i++) { txd = &sc->age_cdata.age_txdesc[i]; txd->tx_m = NULL; txd->tx_dmamap = NULL; error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, &txd->tx_dmamap); if (error != 0) { device_printf(sc->age_dev, "could not create Tx dmamap.\n"); goto fail; } } /* Create DMA maps for Rx buffers. */ if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, &sc->age_cdata.age_rx_sparemap)) != 0) { device_printf(sc->age_dev, "could not create spare Rx dmamap.\n"); goto fail; } for (i = 0; i < AGE_RX_RING_CNT; i++) { rxd = &sc->age_cdata.age_rxdesc[i]; rxd->rx_m = NULL; rxd->rx_dmamap = NULL; error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, &rxd->rx_dmamap); if (error != 0) { device_printf(sc->age_dev, "could not create Rx dmamap.\n"); goto fail; } } fail: return (error); } static void age_dma_free(struct age_softc *sc) { struct age_txdesc *txd; struct age_rxdesc *rxd; int i; /* Tx buffers */ if (sc->age_cdata.age_tx_tag != NULL) { for (i = 0; i < AGE_TX_RING_CNT; i++) { txd = &sc->age_cdata.age_txdesc[i]; if (txd->tx_dmamap != NULL) { bus_dmamap_destroy(sc->age_cdata.age_tx_tag, txd->tx_dmamap); txd->tx_dmamap = NULL; } } bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); sc->age_cdata.age_tx_tag = NULL; } /* Rx buffers */ if (sc->age_cdata.age_rx_tag != NULL) { for (i = 0; i < AGE_RX_RING_CNT; i++) { rxd = &sc->age_cdata.age_rxdesc[i]; if (rxd->rx_dmamap != NULL) { bus_dmamap_destroy(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); rxd->rx_dmamap = NULL; } } if (sc->age_cdata.age_rx_sparemap != NULL) { bus_dmamap_destroy(sc->age_cdata.age_rx_tag, sc->age_cdata.age_rx_sparemap); sc->age_cdata.age_rx_sparemap = NULL; } bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); sc->age_cdata.age_rx_tag = NULL; } /* Tx ring. */ if (sc->age_cdata.age_tx_ring_tag != NULL) { if (sc->age_rdata.age_tx_ring_paddr != 0) bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, sc->age_cdata.age_tx_ring_map); if (sc->age_rdata.age_tx_ring != NULL) bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, sc->age_rdata.age_tx_ring, sc->age_cdata.age_tx_ring_map); sc->age_rdata.age_tx_ring_paddr = 0; sc->age_rdata.age_tx_ring = NULL; bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); sc->age_cdata.age_tx_ring_tag = NULL; } /* Rx ring. */ if (sc->age_cdata.age_rx_ring_tag != NULL) { if (sc->age_rdata.age_rx_ring_paddr != 0) bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, sc->age_cdata.age_rx_ring_map); if (sc->age_rdata.age_rx_ring != NULL) bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, sc->age_rdata.age_rx_ring, sc->age_cdata.age_rx_ring_map); sc->age_rdata.age_rx_ring_paddr = 0; sc->age_rdata.age_rx_ring = NULL; bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); sc->age_cdata.age_rx_ring_tag = NULL; } /* Rx return ring. */ if (sc->age_cdata.age_rr_ring_tag != NULL) { if (sc->age_rdata.age_rr_ring_paddr != 0) bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, sc->age_cdata.age_rr_ring_map); if (sc->age_rdata.age_rr_ring != NULL) bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, sc->age_rdata.age_rr_ring, sc->age_cdata.age_rr_ring_map); sc->age_rdata.age_rr_ring_paddr = 0; sc->age_rdata.age_rr_ring = NULL; bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); sc->age_cdata.age_rr_ring_tag = NULL; } /* CMB block */ if (sc->age_cdata.age_cmb_block_tag != NULL) { if (sc->age_rdata.age_cmb_block_paddr != 0) bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, sc->age_cdata.age_cmb_block_map); if (sc->age_rdata.age_cmb_block != NULL) bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, sc->age_rdata.age_cmb_block, sc->age_cdata.age_cmb_block_map); sc->age_rdata.age_cmb_block_paddr = 0; sc->age_rdata.age_cmb_block = NULL; bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); sc->age_cdata.age_cmb_block_tag = NULL; } /* SMB block */ if (sc->age_cdata.age_smb_block_tag != NULL) { if (sc->age_rdata.age_smb_block_paddr != 0) bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, sc->age_cdata.age_smb_block_map); if (sc->age_rdata.age_smb_block != NULL) bus_dmamem_free(sc->age_cdata.age_smb_block_tag, sc->age_rdata.age_smb_block, sc->age_cdata.age_smb_block_map); sc->age_rdata.age_smb_block_paddr = 0; sc->age_rdata.age_smb_block = NULL; bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); sc->age_cdata.age_smb_block_tag = NULL; } if (sc->age_cdata.age_buffer_tag != NULL) { bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); sc->age_cdata.age_buffer_tag = NULL; } if (sc->age_cdata.age_parent_tag != NULL) { bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); sc->age_cdata.age_parent_tag = NULL; } } /* * Make sure the interface is stopped at reboot time. */ static int age_shutdown(device_t dev) { return (age_suspend(dev)); } static void age_setwol(struct age_softc *sc) { - struct ifnet *ifp; + if_t ifp; struct mii_data *mii; uint32_t reg, pmcs; uint16_t pmstat; int aneg, i, pmc; AGE_LOCK_ASSERT(sc); if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) { CSR_WRITE_4(sc, AGE_WOL_CFG, 0); /* * No PME capability, PHY power down. * XXX * Due to an unknown reason powering down PHY resulted * in unexpected results such as inaccessbility of * hardware of freshly rebooted system. Disable * powering down PHY until I got more information for * Attansic/Atheros PHY hardwares. */ #ifdef notyet age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_PDOWN); #endif return; } ifp = sc->age_ifp; - if ((ifp->if_capenable & IFCAP_WOL) != 0) { + if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { /* * Note, this driver resets the link speed to 10/100Mbps with * auto-negotiation but we don't know whether that operation * would succeed or not as it have no control after powering * off. If the renegotiation fail WOL may not work. Running * at 1Gbps will draw more power than 375mA at 3.3V which is * specified in PCI specification and that would result in * complete shutdowning power to ethernet controller. * * TODO * Save current negotiated media speed/duplex/flow-control * to softc and restore the same link again after resuming. * PHY handling such as power down/resetting to 100Mbps * may be better handled in suspend method in phy driver. */ mii = device_get_softc(sc->age_miibus); mii_pollstat(mii); aneg = 0; if ((mii->mii_media_status & IFM_AVALID) != 0) { switch IFM_SUBTYPE(mii->mii_media_active) { case IFM_10_T: case IFM_100_TX: goto got_link; case IFM_1000_T: aneg++; default: break; } } age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_100T2CR, 0); age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); DELAY(1000); if (aneg != 0) { /* Poll link state until age(4) get a 10/100 link. */ for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { mii_pollstat(mii); if ((mii->mii_media_status & IFM_AVALID) != 0) { switch (IFM_SUBTYPE( mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: age_mac_config(sc); goto got_link; default: break; } } AGE_UNLOCK(sc); pause("agelnk", hz); AGE_LOCK(sc); } if (i == MII_ANEGTICKS_GIGE) device_printf(sc->age_dev, "establishing link failed, " "WOL may not work!"); } /* * No link, force MAC to have 100Mbps, full-duplex link. * This is the last resort and may/may not work. */ mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; age_mac_config(sc); } got_link: pmcs = 0; - if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) + if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); reg = CSR_READ_4(sc, AGE_MAC_CFG); reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); - if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) + if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; - if ((ifp->if_capenable & IFCAP_WOL) != 0) { + if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { reg |= MAC_CFG_RX_ENB; CSR_WRITE_4(sc, AGE_MAC_CFG, reg); } /* Request PME. */ pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); - if ((ifp->if_capenable & IFCAP_WOL) != 0) + if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); #ifdef notyet /* See above for powering down PHY issues. */ - if ((ifp->if_capenable & IFCAP_WOL) == 0) { + if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { /* No WOL, PHY power down. */ age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_PDOWN); } #endif } static int age_suspend(device_t dev) { struct age_softc *sc; sc = device_get_softc(dev); AGE_LOCK(sc); age_stop(sc); age_setwol(sc); AGE_UNLOCK(sc); return (0); } static int age_resume(device_t dev) { struct age_softc *sc; - struct ifnet *ifp; + if_t ifp; sc = device_get_softc(dev); AGE_LOCK(sc); age_phy_reset(sc); ifp = sc->age_ifp; - if ((ifp->if_flags & IFF_UP) != 0) + if ((if_getflags(ifp) & IFF_UP) != 0) age_init_locked(sc); AGE_UNLOCK(sc); return (0); } static int age_encap(struct age_softc *sc, struct mbuf **m_head) { struct age_txdesc *txd, *txd_last; struct tx_desc *desc; struct mbuf *m; struct ip *ip; struct tcphdr *tcp; bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; bus_dmamap_t map; uint32_t cflags, hdrlen, ip_off, poff, vtag; int error, i, nsegs, prod, si; AGE_LOCK_ASSERT(sc); M_ASSERTPKTHDR((*m_head)); m = *m_head; ip = NULL; tcp = NULL; cflags = vtag = 0; ip_off = poff = 0; if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) { /* * L1 requires offset of TCP/UDP payload in its Tx * descriptor to perform hardware Tx checksum offload. * Additionally, TSO requires IP/TCP header size and * modification of IP/TCP header in order to make TSO * engine work. This kind of operation takes many CPU * cycles on FreeBSD so fast host CPU is needed to get * smooth TSO performance. */ struct ether_header *eh; if (M_WRITABLE(m) == 0) { /* Get a writable copy. */ m = m_dup(*m_head, M_NOWAIT); /* Release original mbufs. */ m_freem(*m_head); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } *m_head = m; } ip_off = sizeof(struct ether_header); m = m_pullup(m, ip_off); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } eh = mtod(m, struct ether_header *); /* * Check if hardware VLAN insertion is off. * Additional check for LLC/SNAP frame? */ if (eh->ether_type == htons(ETHERTYPE_VLAN)) { ip_off = sizeof(struct ether_vlan_header); m = m_pullup(m, ip_off); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } } m = m_pullup(m, ip_off + sizeof(struct ip)); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } ip = (struct ip *)(mtod(m, char *) + ip_off); poff = ip_off + (ip->ip_hl << 2); if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { m = m_pullup(m, poff + sizeof(struct tcphdr)); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } tcp = (struct tcphdr *)(mtod(m, char *) + poff); m = m_pullup(m, poff + (tcp->th_off << 2)); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } /* * L1 requires IP/TCP header size and offset as * well as TCP pseudo checksum which complicates * TSO configuration. I guess this comes from the * adherence to Microsoft NDIS Large Send * specification which requires insertion of * pseudo checksum by upper stack. The pseudo * checksum that NDIS refers to doesn't include * TCP payload length so age(4) should recompute * the pseudo checksum here. Hopefully this wouldn't * be much burden on modern CPUs. * Reset IP checksum and recompute TCP pseudo * checksum as NDIS specification said. */ ip = (struct ip *)(mtod(m, char *) + ip_off); tcp = (struct tcphdr *)(mtod(m, char *) + poff); ip->ip_sum = 0; tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, htons(IPPROTO_TCP)); } *m_head = m; } si = prod = sc->age_cdata.age_tx_prod; txd = &sc->age_cdata.age_txdesc[prod]; txd_last = txd; map = txd->tx_dmamap; error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, *m_head, txsegs, &nsegs, 0); if (error == EFBIG) { m = m_collapse(*m_head, M_NOWAIT, AGE_MAXTXSEGS); if (m == NULL) { m_freem(*m_head); *m_head = NULL; return (ENOMEM); } *m_head = m; error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, *m_head, txsegs, &nsegs, 0); if (error != 0) { m_freem(*m_head); *m_head = NULL; return (error); } } else if (error != 0) return (error); if (nsegs == 0) { m_freem(*m_head); *m_head = NULL; return (EIO); } /* Check descriptor overrun. */ if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); return (ENOBUFS); } m = *m_head; /* Configure VLAN hardware tag insertion. */ if ((m->m_flags & M_VLANTAG) != 0) { vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); cflags |= AGE_TD_INSERT_VLAN_TAG; } desc = NULL; i = 0; if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { /* Request TSO and set MSS. */ cflags |= AGE_TD_TSO_IPV4; cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << AGE_TD_TSO_MSS_SHIFT); /* Set IP/TCP header size. */ cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; /* * L1 requires the first buffer should only hold IP/TCP * header data. TCP payload should be handled in other * descriptors. */ hdrlen = poff + (tcp->th_off << 2); desc = &sc->age_rdata.age_tx_ring[prod]; desc->addr = htole64(txsegs[0].ds_addr); desc->len = htole32(AGE_TX_BYTES(hdrlen) | vtag); desc->flags = htole32(cflags); sc->age_cdata.age_tx_cnt++; AGE_DESC_INC(prod, AGE_TX_RING_CNT); if (m->m_len - hdrlen > 0) { /* Handle remaining payload of the 1st fragment. */ desc = &sc->age_rdata.age_tx_ring[prod]; desc->addr = htole64(txsegs[0].ds_addr + hdrlen); desc->len = htole32(AGE_TX_BYTES(m->m_len - hdrlen) | vtag); desc->flags = htole32(cflags); sc->age_cdata.age_tx_cnt++; AGE_DESC_INC(prod, AGE_TX_RING_CNT); } /* Handle remaining fragments. */ i = 1; } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { /* Configure Tx IP/TCP/UDP checksum offload. */ cflags |= AGE_TD_CSUM; if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) cflags |= AGE_TD_TCPCSUM; if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) cflags |= AGE_TD_UDPCSUM; /* Set checksum start offset. */ cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); /* Set checksum insertion position of TCP/UDP. */ cflags |= ((poff + m->m_pkthdr.csum_data) << AGE_TD_CSUM_XSUMOFFSET_SHIFT); } for (; i < nsegs; i++) { desc = &sc->age_rdata.age_tx_ring[prod]; desc->addr = htole64(txsegs[i].ds_addr); desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); desc->flags = htole32(cflags); sc->age_cdata.age_tx_cnt++; AGE_DESC_INC(prod, AGE_TX_RING_CNT); } /* Update producer index. */ sc->age_cdata.age_tx_prod = prod; /* Set EOP on the last descriptor. */ prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; desc = &sc->age_rdata.age_tx_ring[prod]; desc->flags |= htole32(AGE_TD_EOP); /* Lastly set TSO header and modify IP/TCP header for TSO operation. */ if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { desc = &sc->age_rdata.age_tx_ring[si]; desc->flags |= htole32(AGE_TD_TSO_HDR); } /* Swap dmamap of the first and the last. */ txd = &sc->age_cdata.age_txdesc[prod]; map = txd_last->tx_dmamap; txd_last->tx_dmamap = txd->tx_dmamap; txd->tx_dmamap = map; txd->tx_m = m; /* Sync descriptors. */ bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, sc->age_cdata.age_tx_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); return (0); } static void -age_start(struct ifnet *ifp) +age_start(if_t ifp) { struct age_softc *sc; - sc = ifp->if_softc; + sc = if_getsoftc(ifp); AGE_LOCK(sc); age_start_locked(ifp); AGE_UNLOCK(sc); } static void -age_start_locked(struct ifnet *ifp) +age_start_locked(if_t ifp) { struct age_softc *sc; struct mbuf *m_head; int enq; - sc = ifp->if_softc; + sc = if_getsoftc(ifp); AGE_LOCK_ASSERT(sc); - if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != + if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) return; - for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { - IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); + for (enq = 0; !if_sendq_empty(ifp); ) { + m_head = if_dequeue(ifp); if (m_head == NULL) break; /* * Pack the data into the transmit ring. If we * don't have room, set the OACTIVE flag and wait * for the NIC to drain the ring. */ if (age_encap(sc, &m_head)) { if (m_head == NULL) break; - IFQ_DRV_PREPEND(&ifp->if_snd, m_head); - ifp->if_drv_flags |= IFF_DRV_OACTIVE; + if_sendq_prepend(ifp, m_head); + if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); break; } enq++; /* * If there's a BPF listener, bounce a copy of this frame * to him. */ ETHER_BPF_MTAP(ifp, m_head); } if (enq > 0) { /* Update mbox. */ AGE_COMMIT_MBOX(sc); /* Set a timeout in case the chip goes out to lunch. */ sc->age_watchdog_timer = AGE_TX_TIMEOUT; } } static void age_watchdog(struct age_softc *sc) { - struct ifnet *ifp; + if_t ifp; AGE_LOCK_ASSERT(sc); if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer) return; ifp = sc->age_ifp; if ((sc->age_flags & AGE_FLAG_LINK) == 0) { if_printf(sc->age_ifp, "watchdog timeout (missed link)\n"); if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); - ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); age_init_locked(sc); return; } if (sc->age_cdata.age_tx_cnt == 0) { if_printf(sc->age_ifp, "watchdog timeout (missed Tx interrupts) -- recovering\n"); - if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + if (!if_sendq_empty(ifp)) age_start_locked(ifp); return; } if_printf(sc->age_ifp, "watchdog timeout\n"); if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); - ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); age_init_locked(sc); - if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + if (!if_sendq_empty(ifp)) age_start_locked(ifp); } static int -age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) +age_ioctl(if_t ifp, u_long cmd, caddr_t data) { struct age_softc *sc; struct ifreq *ifr; struct mii_data *mii; uint32_t reg; int error, mask; - sc = ifp->if_softc; + sc = if_getsoftc(ifp); ifr = (struct ifreq *)data; error = 0; switch (cmd) { case SIOCSIFMTU: if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) error = EINVAL; - else if (ifp->if_mtu != ifr->ifr_mtu) { + else if (if_getmtu(ifp) != ifr->ifr_mtu) { AGE_LOCK(sc); - ifp->if_mtu = ifr->ifr_mtu; - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { - ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + if_setmtu(ifp, ifr->ifr_mtu); + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); age_init_locked(sc); } AGE_UNLOCK(sc); } break; case SIOCSIFFLAGS: AGE_LOCK(sc); - if ((ifp->if_flags & IFF_UP) != 0) { - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { - if (((ifp->if_flags ^ sc->age_if_flags) + if ((if_getflags(ifp) & IFF_UP) != 0) { + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { + if (((if_getflags(ifp) ^ sc->age_if_flags) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) age_rxfilter(sc); } else { if ((sc->age_flags & AGE_FLAG_DETACH) == 0) age_init_locked(sc); } } else { - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) age_stop(sc); } - sc->age_if_flags = ifp->if_flags; + sc->age_if_flags = if_getflags(ifp); AGE_UNLOCK(sc); break; case SIOCADDMULTI: case SIOCDELMULTI: AGE_LOCK(sc); - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) age_rxfilter(sc); AGE_UNLOCK(sc); break; case SIOCSIFMEDIA: case SIOCGIFMEDIA: mii = device_get_softc(sc->age_miibus); error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); break; case SIOCSIFCAP: AGE_LOCK(sc); - mask = ifr->ifr_reqcap ^ ifp->if_capenable; + mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); if ((mask & IFCAP_TXCSUM) != 0 && - (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { - ifp->if_capenable ^= IFCAP_TXCSUM; - if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) - ifp->if_hwassist |= AGE_CSUM_FEATURES; + (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { + if_togglecapenable(ifp, IFCAP_TXCSUM); + if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) + if_sethwassistbits(ifp, AGE_CSUM_FEATURES, 0); else - ifp->if_hwassist &= ~AGE_CSUM_FEATURES; + if_sethwassistbits(ifp, 0, AGE_CSUM_FEATURES); } if ((mask & IFCAP_RXCSUM) != 0 && - (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { - ifp->if_capenable ^= IFCAP_RXCSUM; + (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { + if_togglecapenable(ifp, IFCAP_RXCSUM); reg = CSR_READ_4(sc, AGE_MAC_CFG); reg &= ~MAC_CFG_RXCSUM_ENB; - if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) + if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) reg |= MAC_CFG_RXCSUM_ENB; CSR_WRITE_4(sc, AGE_MAC_CFG, reg); } if ((mask & IFCAP_TSO4) != 0 && - (ifp->if_capabilities & IFCAP_TSO4) != 0) { - ifp->if_capenable ^= IFCAP_TSO4; - if ((ifp->if_capenable & IFCAP_TSO4) != 0) - ifp->if_hwassist |= CSUM_TSO; + (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { + if_togglecapenable(ifp, IFCAP_TSO4); + if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) + if_sethwassistbits(ifp, CSUM_TSO, 0); else - ifp->if_hwassist &= ~CSUM_TSO; + if_sethwassistbits(ifp, 0, CSUM_TSO); } if ((mask & IFCAP_WOL_MCAST) != 0 && - (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) - ifp->if_capenable ^= IFCAP_WOL_MCAST; + (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) + if_togglecapenable(ifp, IFCAP_WOL_MCAST); if ((mask & IFCAP_WOL_MAGIC) != 0 && - (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) - ifp->if_capenable ^= IFCAP_WOL_MAGIC; + (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) + if_togglecapenable(ifp, IFCAP_WOL_MAGIC); if ((mask & IFCAP_VLAN_HWCSUM) != 0 && - (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) - ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; + (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) + if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); if ((mask & IFCAP_VLAN_HWTSO) != 0 && - (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) - ifp->if_capenable ^= IFCAP_VLAN_HWTSO; + (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) + if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && - (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { - ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; - if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) - ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; + (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { + if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); + if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) + if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); age_rxvlan(sc); } AGE_UNLOCK(sc); VLAN_CAPABILITIES(ifp); break; default: error = ether_ioctl(ifp, cmd, data); break; } return (error); } static void age_mac_config(struct age_softc *sc) { struct mii_data *mii; uint32_t reg; AGE_LOCK_ASSERT(sc); mii = device_get_softc(sc->age_miibus); reg = CSR_READ_4(sc, AGE_MAC_CFG); reg &= ~MAC_CFG_FULL_DUPLEX; reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); reg &= ~MAC_CFG_SPEED_MASK; /* Reprogram MAC with resolved speed/duplex. */ switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: reg |= MAC_CFG_SPEED_10_100; break; case IFM_1000_T: reg |= MAC_CFG_SPEED_1000; break; } if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { reg |= MAC_CFG_FULL_DUPLEX; #ifdef notyet if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) reg |= MAC_CFG_TX_FC; if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) reg |= MAC_CFG_RX_FC; #endif } CSR_WRITE_4(sc, AGE_MAC_CFG, reg); } static void age_link_task(void *arg, int pending) { struct age_softc *sc; struct mii_data *mii; - struct ifnet *ifp; + if_t ifp; uint32_t reg; sc = (struct age_softc *)arg; AGE_LOCK(sc); mii = device_get_softc(sc->age_miibus); ifp = sc->age_ifp; if (mii == NULL || ifp == NULL || - (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { + (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { AGE_UNLOCK(sc); return; } sc->age_flags &= ~AGE_FLAG_LINK; if ((mii->mii_media_status & IFM_AVALID) != 0) { switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: case IFM_1000_T: sc->age_flags |= AGE_FLAG_LINK; break; default: break; } } /* Stop Rx/Tx MACs. */ age_stop_rxmac(sc); age_stop_txmac(sc); /* Program MACs with resolved speed/duplex/flow-control. */ if ((sc->age_flags & AGE_FLAG_LINK) != 0) { age_mac_config(sc); reg = CSR_READ_4(sc, AGE_MAC_CFG); /* Restart DMA engine and Tx/Rx MAC. */ CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; CSR_WRITE_4(sc, AGE_MAC_CFG, reg); } AGE_UNLOCK(sc); } static void age_stats_update(struct age_softc *sc) { struct age_stats *stat; struct smb *smb; - struct ifnet *ifp; + if_t ifp; AGE_LOCK_ASSERT(sc); stat = &sc->age_stat; bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, sc->age_cdata.age_smb_block_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); smb = sc->age_rdata.age_smb_block; if (smb->updated == 0) return; ifp = sc->age_ifp; /* Rx stats. */ stat->rx_frames += smb->rx_frames; stat->rx_bcast_frames += smb->rx_bcast_frames; stat->rx_mcast_frames += smb->rx_mcast_frames; stat->rx_pause_frames += smb->rx_pause_frames; stat->rx_control_frames += smb->rx_control_frames; stat->rx_crcerrs += smb->rx_crcerrs; stat->rx_lenerrs += smb->rx_lenerrs; stat->rx_bytes += smb->rx_bytes; stat->rx_runts += smb->rx_runts; stat->rx_fragments += smb->rx_fragments; stat->rx_pkts_64 += smb->rx_pkts_64; stat->rx_pkts_65_127 += smb->rx_pkts_65_127; stat->rx_pkts_128_255 += smb->rx_pkts_128_255; stat->rx_pkts_256_511 += smb->rx_pkts_256_511; stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; stat->rx_pkts_truncated += smb->rx_pkts_truncated; stat->rx_fifo_oflows += smb->rx_fifo_oflows; stat->rx_desc_oflows += smb->rx_desc_oflows; stat->rx_alignerrs += smb->rx_alignerrs; stat->rx_bcast_bytes += smb->rx_bcast_bytes; stat->rx_mcast_bytes += smb->rx_mcast_bytes; stat->rx_pkts_filtered += smb->rx_pkts_filtered; /* Tx stats. */ stat->tx_frames += smb->tx_frames; stat->tx_bcast_frames += smb->tx_bcast_frames; stat->tx_mcast_frames += smb->tx_mcast_frames; stat->tx_pause_frames += smb->tx_pause_frames; stat->tx_excess_defer += smb->tx_excess_defer; stat->tx_control_frames += smb->tx_control_frames; stat->tx_deferred += smb->tx_deferred; stat->tx_bytes += smb->tx_bytes; stat->tx_pkts_64 += smb->tx_pkts_64; stat->tx_pkts_65_127 += smb->tx_pkts_65_127; stat->tx_pkts_128_255 += smb->tx_pkts_128_255; stat->tx_pkts_256_511 += smb->tx_pkts_256_511; stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; stat->tx_single_colls += smb->tx_single_colls; stat->tx_multi_colls += smb->tx_multi_colls; stat->tx_late_colls += smb->tx_late_colls; stat->tx_excess_colls += smb->tx_excess_colls; stat->tx_underrun += smb->tx_underrun; stat->tx_desc_underrun += smb->tx_desc_underrun; stat->tx_lenerrs += smb->tx_lenerrs; stat->tx_pkts_truncated += smb->tx_pkts_truncated; stat->tx_bcast_bytes += smb->tx_bcast_bytes; stat->tx_mcast_bytes += smb->tx_mcast_bytes; /* Update counters in ifnet. */ if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + smb->tx_multi_colls + smb->tx_late_colls + smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_excess_colls + smb->tx_late_colls + smb->tx_underrun + smb->tx_pkts_truncated); if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); if_inc_counter(ifp, IFCOUNTER_IERRORS, smb->rx_crcerrs + smb->rx_lenerrs + smb->rx_runts + smb->rx_pkts_truncated + smb->rx_fifo_oflows + smb->rx_desc_oflows + smb->rx_alignerrs); /* Update done, clear. */ smb->updated = 0; bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, sc->age_cdata.age_smb_block_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); } static int age_intr(void *arg) { struct age_softc *sc; uint32_t status; sc = (struct age_softc *)arg; status = CSR_READ_4(sc, AGE_INTR_STATUS); if (status == 0 || (status & AGE_INTRS) == 0) return (FILTER_STRAY); /* Disable interrupts. */ CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); taskqueue_enqueue(sc->age_tq, &sc->age_int_task); return (FILTER_HANDLED); } static void age_int_task(void *arg, int pending) { struct age_softc *sc; - struct ifnet *ifp; + if_t ifp; struct cmb *cmb; uint32_t status; sc = (struct age_softc *)arg; AGE_LOCK(sc); bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, sc->age_cdata.age_cmb_block_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); cmb = sc->age_rdata.age_cmb_block; status = le32toh(cmb->intr_status); if (sc->age_morework != 0) status |= INTR_CMB_RX; if ((status & AGE_INTRS) == 0) goto done; sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> TPD_CONS_SHIFT; sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> RRD_PROD_SHIFT; /* Let hardware know CMB was served. */ cmb->intr_status = 0; bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, sc->age_cdata.age_cmb_block_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ifp = sc->age_ifp; - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { if ((status & INTR_CMB_RX) != 0) sc->age_morework = age_rxintr(sc, sc->age_rr_prod, sc->age_process_limit); if ((status & INTR_CMB_TX) != 0) age_txintr(sc, sc->age_tpd_cons); if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { if ((status & INTR_DMA_RD_TO_RST) != 0) device_printf(sc->age_dev, "DMA read error! -- resetting\n"); if ((status & INTR_DMA_WR_TO_RST) != 0) device_printf(sc->age_dev, "DMA write error! -- resetting\n"); - ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); age_init_locked(sc); } - if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + if (!if_sendq_empty(ifp)) age_start_locked(ifp); if ((status & INTR_SMB) != 0) age_stats_update(sc); } /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, sc->age_cdata.age_cmb_block_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); status = le32toh(cmb->intr_status); if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) { taskqueue_enqueue(sc->age_tq, &sc->age_int_task); AGE_UNLOCK(sc); return; } done: /* Re-enable interrupts. */ CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); AGE_UNLOCK(sc); } static void age_txintr(struct age_softc *sc, int tpd_cons) { - struct ifnet *ifp; + if_t ifp; struct age_txdesc *txd; int cons, prog; AGE_LOCK_ASSERT(sc); ifp = sc->age_ifp; bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, sc->age_cdata.age_tx_ring_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); /* * Go through our Tx list and free mbufs for those * frames which have been transmitted. */ cons = sc->age_cdata.age_tx_cons; for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { if (sc->age_cdata.age_tx_cnt <= 0) break; prog++; - ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); sc->age_cdata.age_tx_cnt--; txd = &sc->age_cdata.age_txdesc[cons]; /* * Clear Tx descriptors, it's not required but would * help debugging in case of Tx issues. */ txd->tx_desc->addr = 0; txd->tx_desc->len = 0; txd->tx_desc->flags = 0; if (txd->tx_m == NULL) continue; /* Reclaim transmitted mbufs. */ bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); m_freem(txd->tx_m); txd->tx_m = NULL; } if (prog > 0) { sc->age_cdata.age_tx_cons = cons; /* * Unarm watchdog timer only when there are no pending * Tx descriptors in queue. */ if (sc->age_cdata.age_tx_cnt == 0) sc->age_watchdog_timer = 0; bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, sc->age_cdata.age_tx_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); } } #ifndef __NO_STRICT_ALIGNMENT static struct mbuf * -age_fixup_rx(struct ifnet *ifp, struct mbuf *m) +age_fixup_rx(if_t ifp, struct mbuf *m) { struct mbuf *n; int i; uint16_t *src, *dst; src = mtod(m, uint16_t *); dst = src - 3; if (m->m_next == NULL) { for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) *dst++ = *src++; m->m_data -= 6; return (m); } /* * Append a new mbuf to received mbuf chain and copy ethernet * header from the mbuf chain. This can save lots of CPU * cycles for jumbo frame. */ MGETHDR(n, M_NOWAIT, MT_DATA); if (n == NULL) { if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); m_freem(m); return (NULL); } bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); m->m_data += ETHER_HDR_LEN; m->m_len -= ETHER_HDR_LEN; n->m_len = ETHER_HDR_LEN; M_MOVE_PKTHDR(n, m); n->m_next = m; return (n); } #endif /* Receive a frame. */ static void age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) { struct age_rxdesc *rxd; - struct ifnet *ifp; + if_t ifp; struct mbuf *mp, *m; uint32_t status, index, vtag; int count, nsegs; int rx_cons; AGE_LOCK_ASSERT(sc); ifp = sc->age_ifp; status = le32toh(rxrd->flags); index = le32toh(rxrd->index); rx_cons = AGE_RX_CONS(index); nsegs = AGE_RX_NSEGS(index); sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); if ((status & (AGE_RRD_ERROR | AGE_RRD_LENGTH_NOK)) != 0) { /* * We want to pass the following frames to upper * layer regardless of error status of Rx return * ring. * * o IP/TCP/UDP checksum is bad. * o frame length and protocol specific length * does not match. */ status |= AGE_RRD_IPCSUM_NOK | AGE_RRD_TCP_UDPCSUM_NOK; if ((status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) return; } for (count = 0; count < nsegs; count++, AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { rxd = &sc->age_cdata.age_rxdesc[rx_cons]; mp = rxd->rx_m; /* Add a new receive buffer to the ring. */ if (age_newbuf(sc, rxd) != 0) { if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); /* Reuse Rx buffers. */ if (sc->age_cdata.age_rxhead != NULL) m_freem(sc->age_cdata.age_rxhead); break; } /* * Assume we've received a full sized frame. * Actual size is fixed when we encounter the end of * multi-segmented frame. */ mp->m_len = AGE_RX_BUF_SIZE; /* Chain received mbufs. */ if (sc->age_cdata.age_rxhead == NULL) { sc->age_cdata.age_rxhead = mp; sc->age_cdata.age_rxtail = mp; } else { mp->m_flags &= ~M_PKTHDR; sc->age_cdata.age_rxprev_tail = sc->age_cdata.age_rxtail; sc->age_cdata.age_rxtail->m_next = mp; sc->age_cdata.age_rxtail = mp; } if (count == nsegs - 1) { /* Last desc. for this frame. */ m = sc->age_cdata.age_rxhead; m->m_flags |= M_PKTHDR; /* * It seems that L1 controller has no way * to tell hardware to strip CRC bytes. */ m->m_pkthdr.len = sc->age_cdata.age_rxlen - ETHER_CRC_LEN; if (nsegs > 1) { /* Set last mbuf size. */ mp->m_len = sc->age_cdata.age_rxlen - ((nsegs - 1) * AGE_RX_BUF_SIZE); /* Remove the CRC bytes in chained mbufs. */ if (mp->m_len <= ETHER_CRC_LEN) { sc->age_cdata.age_rxtail = sc->age_cdata.age_rxprev_tail; sc->age_cdata.age_rxtail->m_len -= (ETHER_CRC_LEN - mp->m_len); sc->age_cdata.age_rxtail->m_next = NULL; m_freem(mp); } else { mp->m_len -= ETHER_CRC_LEN; } } else m->m_len = m->m_pkthdr.len; m->m_pkthdr.rcvif = ifp; /* * Set checksum information. * It seems that L1 controller can compute partial * checksum. The partial checksum value can be used * to accelerate checksum computation for fragmented * TCP/UDP packets. Upper network stack already * takes advantage of the partial checksum value in * IP reassembly stage. But I'm not sure the * correctness of the partial hardware checksum * assistance due to lack of data sheet. If it is * proven to work on L1 I'll enable it. */ - if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && + if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && (status & AGE_RRD_IPV4) != 0) { if ((status & AGE_RRD_IPCSUM_NOK) == 0) m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; m->m_pkthdr.csum_data = 0xffff; } /* * Don't mark bad checksum for TCP/UDP frames * as fragmented frames may always have set * bad checksummed bit of descriptor status. */ } /* Check for VLAN tagged frames. */ - if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && + if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && (status & AGE_RRD_VLAN) != 0) { vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); m->m_flags |= M_VLANTAG; } #ifndef __NO_STRICT_ALIGNMENT m = age_fixup_rx(ifp, m); if (m != NULL) #endif { /* Pass it on. */ AGE_UNLOCK(sc); - (*ifp->if_input)(ifp, m); + if_input(ifp, m); AGE_LOCK(sc); } } } /* Reset mbuf chains. */ AGE_RXCHAIN_RESET(sc); } static int age_rxintr(struct age_softc *sc, int rr_prod, int count) { struct rx_rdesc *rxrd; int rr_cons, nsegs, pktlen, prog; AGE_LOCK_ASSERT(sc); rr_cons = sc->age_cdata.age_rr_cons; if (rr_cons == rr_prod) return (0); bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, sc->age_cdata.age_rr_ring_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE); for (prog = 0; rr_cons != rr_prod; prog++) { if (count-- <= 0) break; rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); if (nsegs == 0) break; /* * Check number of segments against received bytes. * Non-matching value would indicate that hardware * is still trying to update Rx return descriptors. * I'm not sure whether this check is really needed. */ pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); if (nsegs != howmany(pktlen, AGE_RX_BUF_SIZE)) break; /* Received a frame. */ age_rxeof(sc, rxrd); /* Clear return ring. */ rxrd->index = 0; AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); sc->age_cdata.age_rx_cons += nsegs; sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; } if (prog > 0) { /* Update the consumer index. */ sc->age_cdata.age_rr_cons = rr_cons; bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); /* Sync descriptors. */ bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, sc->age_cdata.age_rr_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); /* Notify hardware availability of new Rx buffers. */ AGE_COMMIT_MBOX(sc); } return (count > 0 ? 0 : EAGAIN); } static void age_tick(void *arg) { struct age_softc *sc; struct mii_data *mii; sc = (struct age_softc *)arg; AGE_LOCK_ASSERT(sc); mii = device_get_softc(sc->age_miibus); mii_tick(mii); age_watchdog(sc); callout_reset(&sc->age_tick_ch, hz, age_tick, sc); } static void age_reset(struct age_softc *sc) { uint32_t reg; int i; CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); CSR_READ_4(sc, AGE_MASTER_CFG); DELAY(1000); for (i = AGE_RESET_TIMEOUT; i > 0; i--) { if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) break; DELAY(10); } if (i == 0) device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); /* Initialize PCIe module. From Linux. */ CSR_WRITE_4(sc, 0x12FC, 0x6500); CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); } static void age_init(void *xsc) { struct age_softc *sc; sc = (struct age_softc *)xsc; AGE_LOCK(sc); age_init_locked(sc); AGE_UNLOCK(sc); } static void age_init_locked(struct age_softc *sc) { - struct ifnet *ifp; + if_t ifp; struct mii_data *mii; uint8_t eaddr[ETHER_ADDR_LEN]; bus_addr_t paddr; uint32_t reg, fsize; uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; int error; AGE_LOCK_ASSERT(sc); ifp = sc->age_ifp; mii = device_get_softc(sc->age_miibus); - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) return; /* * Cancel any pending I/O. */ age_stop(sc); /* * Reset the chip to a known state. */ age_reset(sc); /* Initialize descriptors. */ error = age_init_rx_ring(sc); if (error != 0) { device_printf(sc->age_dev, "no memory for Rx buffers.\n"); age_stop(sc); return; } age_init_rr_ring(sc); age_init_tx_ring(sc); age_init_cmb_block(sc); age_init_smb_block(sc); /* Reprogram the station address. */ - bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); + bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); CSR_WRITE_4(sc, AGE_PAR0, eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); /* Set descriptor base addresses. */ paddr = sc->age_rdata.age_tx_ring_paddr; CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); paddr = sc->age_rdata.age_rx_ring_paddr; CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); paddr = sc->age_rdata.age_rr_ring_paddr; CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); paddr = sc->age_rdata.age_tx_ring_paddr; CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); paddr = sc->age_rdata.age_cmb_block_paddr; CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); paddr = sc->age_rdata.age_smb_block_paddr; CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); /* Set Rx/Rx return descriptor counter. */ CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & DESC_RRD_CNT_MASK) | ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); /* Set Tx descriptor counter. */ CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); /* Tell hardware that we're ready to load descriptors. */ CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); /* * Initialize mailbox register. * Updated producer/consumer index information is exchanged * through this mailbox register. However Tx producer and * Rx return consumer/Rx producer are all shared such that * it's hard to separate code path between Tx and Rx without * locking. If L1 hardware have a separate mail box register * for Tx and Rx consumer/producer management we could have * independent Tx/Rx handler which in turn Rx handler could have * been run without any locking. */ AGE_COMMIT_MBOX(sc); /* Configure IPG/IFG parameters. */ CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); /* Set parameters for half-duplex media. */ CSR_WRITE_4(sc, AGE_HDPX_CFG, ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & HDPX_CFG_LCOL_MASK) | ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & HDPX_CFG_ABEBT_MASK) | ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & HDPX_CFG_JAMIPG_MASK)); /* Configure interrupt moderation timer. */ CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); reg = CSR_READ_4(sc, AGE_MASTER_CFG); reg &= ~MASTER_MTIMER_ENB; if (AGE_USECS(sc->age_int_mod) == 0) reg &= ~MASTER_ITIMER_ENB; else reg |= MASTER_ITIMER_ENB; CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); if (bootverbose) device_printf(sc->age_dev, "interrupt moderation is %d us.\n", sc->age_int_mod); CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ - if (ifp->if_mtu < ETHERMTU) + if (if_getmtu(ifp) < ETHERMTU) sc->age_max_frame_size = ETHERMTU; else - sc->age_max_frame_size = ifp->if_mtu; + sc->age_max_frame_size = if_getmtu(ifp); sc->age_max_frame_size += ETHER_HDR_LEN + sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); /* Configure jumbo frame. */ fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, (((fsize / sizeof(uint64_t)) << RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | ((RXQ_JUMBO_CFG_LKAH_DEFAULT << RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & RXQ_JUMBO_CFG_RRD_TIMER_MASK)); /* Configure flow-control parameters. From Linux. */ if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { /* * Magic workaround for old-L1. * Don't know which hw revision requires this magic. */ CSR_WRITE_4(sc, 0x12FC, 0x6500); /* * Another magic workaround for flow-control mode * change. From Linux. */ CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); } /* * TODO * Should understand pause parameter relationships between FIFO * size and number of Rx descriptors and Rx return descriptors. * * Magic parameters came from Linux. */ switch (sc->age_chip_rev) { case 0x8001: case 0x9001: case 0x9002: case 0x9003: rxf_hi = AGE_RX_RING_CNT / 16; rxf_lo = (AGE_RX_RING_CNT * 7) / 8; rrd_hi = (AGE_RR_RING_CNT * 7) / 8; rrd_lo = AGE_RR_RING_CNT / 16; break; default: reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); rxf_lo = reg / 16; if (rxf_lo < 192) rxf_lo = 192; rxf_hi = (reg * 7) / 8; if (rxf_hi < rxf_lo) rxf_hi = rxf_lo + 16; reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); rrd_lo = reg / 8; rrd_hi = (reg * 7) / 8; if (rrd_lo < 2) rrd_lo = 2; if (rrd_hi < rrd_lo) rrd_hi = rrd_lo + 3; break; } CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & RXQ_FIFO_PAUSE_THRESH_LO_MASK) | ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & RXQ_FIFO_PAUSE_THRESH_HI_MASK)); CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & RXQ_RRD_PAUSE_THRESH_LO_MASK) | ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & RXQ_RRD_PAUSE_THRESH_HI_MASK)); /* Configure RxQ. */ CSR_WRITE_4(sc, AGE_RXQ_CFG, ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & RXQ_CFG_RD_BURST_MASK) | ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); /* Configure TxQ. */ CSR_WRITE_4(sc, AGE_TXQ_CFG, ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & TXQ_CFG_TPD_BURST_MASK) | ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK) | ((TXQ_CFG_TPD_FETCH_DEFAULT << TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | TXQ_CFG_ENB); CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & TX_JUMBO_TPD_TH_MASK) | ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & TX_JUMBO_TPD_IPG_MASK)); /* Configure DMA parameters. */ CSR_WRITE_4(sc, AGE_DMA_CFG, DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | sc->age_dma_rd_burst | DMA_CFG_RD_ENB | sc->age_dma_wr_burst | DMA_CFG_WR_ENB); /* Configure CMB DMA write threshold. */ CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & CMB_WR_THRESH_RRD_MASK) | ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & CMB_WR_THRESH_TPD_MASK)); /* Set CMB/SMB timer and enable them. */ CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); /* Request SMB updates for every seconds. */ CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); /* * Disable all WOL bits as WOL can interfere normal Rx * operation. */ CSR_WRITE_4(sc, AGE_WOL_CFG, 0); /* * Configure Tx/Rx MACs. * - Auto-padding for short frames. * - Enable CRC generation. * Start with full-duplex/1000Mbps media. Actual reconfiguration * of MAC is followed after link establishment. */ CSR_WRITE_4(sc, AGE_MAC_CFG, MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & MAC_CFG_PREAMBLE_MASK)); /* Set up the receive filter. */ age_rxfilter(sc); age_rxvlan(sc); reg = CSR_READ_4(sc, AGE_MAC_CFG); - if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) + if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) reg |= MAC_CFG_RXCSUM_ENB; /* Ack all pending interrupts and clear it. */ CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); /* Finally enable Tx/Rx MAC. */ CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); sc->age_flags &= ~AGE_FLAG_LINK; /* Switch to the current media. */ mii_mediachg(mii); callout_reset(&sc->age_tick_ch, hz, age_tick, sc); - ifp->if_drv_flags |= IFF_DRV_RUNNING; - ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); + if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); } static void age_stop(struct age_softc *sc) { - struct ifnet *ifp; + if_t ifp; struct age_txdesc *txd; struct age_rxdesc *rxd; uint32_t reg; int i; AGE_LOCK_ASSERT(sc); /* * Mark the interface down and cancel the watchdog timer. */ ifp = sc->age_ifp; - ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); + if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); sc->age_flags &= ~AGE_FLAG_LINK; callout_stop(&sc->age_tick_ch); sc->age_watchdog_timer = 0; /* * Disable interrupts. */ CSR_WRITE_4(sc, AGE_INTR_MASK, 0); CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); /* Stop CMB/SMB updates. */ CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); /* Stop Rx/Tx MAC. */ age_stop_rxmac(sc); age_stop_txmac(sc); /* Stop DMA. */ CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); /* Stop TxQ/RxQ. */ CSR_WRITE_4(sc, AGE_TXQ_CFG, CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); CSR_WRITE_4(sc, AGE_RXQ_CFG, CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); for (i = AGE_RESET_TIMEOUT; i > 0; i--) { if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) break; DELAY(10); } if (i == 0) device_printf(sc->age_dev, "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); /* Reclaim Rx buffers that have been processed. */ if (sc->age_cdata.age_rxhead != NULL) m_freem(sc->age_cdata.age_rxhead); AGE_RXCHAIN_RESET(sc); /* * Free RX and TX mbufs still in the queues. */ for (i = 0; i < AGE_RX_RING_CNT; i++) { rxd = &sc->age_cdata.age_rxdesc[i]; if (rxd->rx_m != NULL) { bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); m_freem(rxd->rx_m); rxd->rx_m = NULL; } } for (i = 0; i < AGE_TX_RING_CNT; i++) { txd = &sc->age_cdata.age_txdesc[i]; if (txd->tx_m != NULL) { bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); m_freem(txd->tx_m); txd->tx_m = NULL; } } } static void age_stop_txmac(struct age_softc *sc) { uint32_t reg; int i; AGE_LOCK_ASSERT(sc); reg = CSR_READ_4(sc, AGE_MAC_CFG); if ((reg & MAC_CFG_TX_ENB) != 0) { reg &= ~MAC_CFG_TX_ENB; CSR_WRITE_4(sc, AGE_MAC_CFG, reg); } /* Stop Tx DMA engine. */ reg = CSR_READ_4(sc, AGE_DMA_CFG); if ((reg & DMA_CFG_RD_ENB) != 0) { reg &= ~DMA_CFG_RD_ENB; CSR_WRITE_4(sc, AGE_DMA_CFG, reg); } for (i = AGE_RESET_TIMEOUT; i > 0; i--) { if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) break; DELAY(10); } if (i == 0) device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); } static void age_stop_rxmac(struct age_softc *sc) { uint32_t reg; int i; AGE_LOCK_ASSERT(sc); reg = CSR_READ_4(sc, AGE_MAC_CFG); if ((reg & MAC_CFG_RX_ENB) != 0) { reg &= ~MAC_CFG_RX_ENB; CSR_WRITE_4(sc, AGE_MAC_CFG, reg); } /* Stop Rx DMA engine. */ reg = CSR_READ_4(sc, AGE_DMA_CFG); if ((reg & DMA_CFG_WR_ENB) != 0) { reg &= ~DMA_CFG_WR_ENB; CSR_WRITE_4(sc, AGE_DMA_CFG, reg); } for (i = AGE_RESET_TIMEOUT; i > 0; i--) { if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) break; DELAY(10); } if (i == 0) device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); } static void age_init_tx_ring(struct age_softc *sc) { struct age_ring_data *rd; struct age_txdesc *txd; int i; AGE_LOCK_ASSERT(sc); sc->age_cdata.age_tx_prod = 0; sc->age_cdata.age_tx_cons = 0; sc->age_cdata.age_tx_cnt = 0; rd = &sc->age_rdata; bzero(rd->age_tx_ring, AGE_TX_RING_SZ); for (i = 0; i < AGE_TX_RING_CNT; i++) { txd = &sc->age_cdata.age_txdesc[i]; txd->tx_desc = &rd->age_tx_ring[i]; txd->tx_m = NULL; } bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, sc->age_cdata.age_tx_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); } static int age_init_rx_ring(struct age_softc *sc) { struct age_ring_data *rd; struct age_rxdesc *rxd; int i; AGE_LOCK_ASSERT(sc); sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; sc->age_morework = 0; rd = &sc->age_rdata; bzero(rd->age_rx_ring, AGE_RX_RING_SZ); for (i = 0; i < AGE_RX_RING_CNT; i++) { rxd = &sc->age_cdata.age_rxdesc[i]; rxd->rx_m = NULL; rxd->rx_desc = &rd->age_rx_ring[i]; if (age_newbuf(sc, rxd) != 0) return (ENOBUFS); } bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); return (0); } static void age_init_rr_ring(struct age_softc *sc) { struct age_ring_data *rd; AGE_LOCK_ASSERT(sc); sc->age_cdata.age_rr_cons = 0; AGE_RXCHAIN_RESET(sc); rd = &sc->age_rdata; bzero(rd->age_rr_ring, AGE_RR_RING_SZ); bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, sc->age_cdata.age_rr_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); } static void age_init_cmb_block(struct age_softc *sc) { struct age_ring_data *rd; AGE_LOCK_ASSERT(sc); rd = &sc->age_rdata; bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, sc->age_cdata.age_cmb_block_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); } static void age_init_smb_block(struct age_softc *sc) { struct age_ring_data *rd; AGE_LOCK_ASSERT(sc); rd = &sc->age_rdata; bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, sc->age_cdata.age_smb_block_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); } static int age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) { struct rx_desc *desc; struct mbuf *m; bus_dma_segment_t segs[1]; bus_dmamap_t map; int nsegs; AGE_LOCK_ASSERT(sc); m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); m->m_len = m->m_pkthdr.len = MCLBYTES; #ifndef __NO_STRICT_ALIGNMENT m_adj(m, AGE_RX_BUF_ALIGN); #endif if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { m_freem(m); return (ENOBUFS); } KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); if (rxd->rx_m != NULL) { bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); } map = rxd->rx_dmamap; rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; sc->age_cdata.age_rx_sparemap = map; bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD); rxd->rx_m = m; desc = rxd->rx_desc; desc->addr = htole64(segs[0].ds_addr); desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << AGE_RD_LEN_SHIFT); return (0); } static void age_rxvlan(struct age_softc *sc) { - struct ifnet *ifp; + if_t ifp; uint32_t reg; AGE_LOCK_ASSERT(sc); ifp = sc->age_ifp; reg = CSR_READ_4(sc, AGE_MAC_CFG); reg &= ~MAC_CFG_VLAN_TAG_STRIP; - if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) + if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) reg |= MAC_CFG_VLAN_TAG_STRIP; CSR_WRITE_4(sc, AGE_MAC_CFG, reg); } static u_int age_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) { uint32_t *mchash = arg; uint32_t crc; crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); return (1); } static void age_rxfilter(struct age_softc *sc) { - struct ifnet *ifp; + if_t ifp; uint32_t mchash[2]; uint32_t rxcfg; AGE_LOCK_ASSERT(sc); ifp = sc->age_ifp; rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); - if ((ifp->if_flags & IFF_BROADCAST) != 0) + if ((if_getflags(ifp) & IFF_BROADCAST) != 0) rxcfg |= MAC_CFG_BCAST; - if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { - if ((ifp->if_flags & IFF_PROMISC) != 0) + if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { + if ((if_getflags(ifp) & IFF_PROMISC) != 0) rxcfg |= MAC_CFG_PROMISC; - if ((ifp->if_flags & IFF_ALLMULTI) != 0) + if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) rxcfg |= MAC_CFG_ALLMULTI; CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); return; } /* Program new filter. */ bzero(mchash, sizeof(mchash)); if_foreach_llmaddr(ifp, age_hash_maddr, mchash); CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); } static int sysctl_age_stats(SYSCTL_HANDLER_ARGS) { struct age_softc *sc; struct age_stats *stats; int error, result; result = -1; error = sysctl_handle_int(oidp, &result, 0, req); if (error != 0 || req->newptr == NULL) return (error); if (result != 1) return (error); sc = (struct age_softc *)arg1; stats = &sc->age_stat; printf("%s statistics:\n", device_get_nameunit(sc->age_dev)); printf("Transmit good frames : %ju\n", (uintmax_t)stats->tx_frames); printf("Transmit good broadcast frames : %ju\n", (uintmax_t)stats->tx_bcast_frames); printf("Transmit good multicast frames : %ju\n", (uintmax_t)stats->tx_mcast_frames); printf("Transmit pause control frames : %u\n", stats->tx_pause_frames); printf("Transmit control frames : %u\n", stats->tx_control_frames); printf("Transmit frames with excessive deferrals : %u\n", stats->tx_excess_defer); printf("Transmit deferrals : %u\n", stats->tx_deferred); printf("Transmit good octets : %ju\n", (uintmax_t)stats->tx_bytes); printf("Transmit good broadcast octets : %ju\n", (uintmax_t)stats->tx_bcast_bytes); printf("Transmit good multicast octets : %ju\n", (uintmax_t)stats->tx_mcast_bytes); printf("Transmit frames 64 bytes : %ju\n", (uintmax_t)stats->tx_pkts_64); printf("Transmit frames 65 to 127 bytes : %ju\n", (uintmax_t)stats->tx_pkts_65_127); printf("Transmit frames 128 to 255 bytes : %ju\n", (uintmax_t)stats->tx_pkts_128_255); printf("Transmit frames 256 to 511 bytes : %ju\n", (uintmax_t)stats->tx_pkts_256_511); printf("Transmit frames 512 to 1024 bytes : %ju\n", (uintmax_t)stats->tx_pkts_512_1023); printf("Transmit frames 1024 to 1518 bytes : %ju\n", (uintmax_t)stats->tx_pkts_1024_1518); printf("Transmit frames 1519 to MTU bytes : %ju\n", (uintmax_t)stats->tx_pkts_1519_max); printf("Transmit single collisions : %u\n", stats->tx_single_colls); printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls); printf("Transmit late collisions : %u\n", stats->tx_late_colls); printf("Transmit abort due to excessive collisions : %u\n", stats->tx_excess_colls); printf("Transmit underruns due to FIFO underruns : %u\n", stats->tx_underrun); printf("Transmit descriptor write-back errors : %u\n", stats->tx_desc_underrun); printf("Transmit frames with length mismatched frame size : %u\n", stats->tx_lenerrs); printf("Transmit frames with truncated due to MTU size : %u\n", stats->tx_lenerrs); printf("Receive good frames : %ju\n", (uintmax_t)stats->rx_frames); printf("Receive good broadcast frames : %ju\n", (uintmax_t)stats->rx_bcast_frames); printf("Receive good multicast frames : %ju\n", (uintmax_t)stats->rx_mcast_frames); printf("Receive pause control frames : %u\n", stats->rx_pause_frames); printf("Receive control frames : %u\n", stats->rx_control_frames); printf("Receive CRC errors : %u\n", stats->rx_crcerrs); printf("Receive frames with length errors : %u\n", stats->rx_lenerrs); printf("Receive good octets : %ju\n", (uintmax_t)stats->rx_bytes); printf("Receive good broadcast octets : %ju\n", (uintmax_t)stats->rx_bcast_bytes); printf("Receive good multicast octets : %ju\n", (uintmax_t)stats->rx_mcast_bytes); printf("Receive frames too short : %u\n", stats->rx_runts); printf("Receive fragmented frames : %ju\n", (uintmax_t)stats->rx_fragments); printf("Receive frames 64 bytes : %ju\n", (uintmax_t)stats->rx_pkts_64); printf("Receive frames 65 to 127 bytes : %ju\n", (uintmax_t)stats->rx_pkts_65_127); printf("Receive frames 128 to 255 bytes : %ju\n", (uintmax_t)stats->rx_pkts_128_255); printf("Receive frames 256 to 511 bytes : %ju\n", (uintmax_t)stats->rx_pkts_256_511); printf("Receive frames 512 to 1024 bytes : %ju\n", (uintmax_t)stats->rx_pkts_512_1023); printf("Receive frames 1024 to 1518 bytes : %ju\n", (uintmax_t)stats->rx_pkts_1024_1518); printf("Receive frames 1519 to MTU bytes : %ju\n", (uintmax_t)stats->rx_pkts_1519_max); printf("Receive frames too long : %ju\n", (uint64_t)stats->rx_pkts_truncated); printf("Receive frames with FIFO overflow : %u\n", stats->rx_fifo_oflows); printf("Receive frames with return descriptor overflow : %u\n", stats->rx_desc_oflows); printf("Receive frames with alignment errors : %u\n", stats->rx_alignerrs); printf("Receive frames dropped due to address filtering : %ju\n", (uint64_t)stats->rx_pkts_filtered); return (error); } static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) { int error, value; if (arg1 == NULL) return (EINVAL); value = *(int *)arg1; error = sysctl_handle_int(oidp, &value, 0, req); if (error || req->newptr == NULL) return (error); if (value < low || value > high) return (EINVAL); *(int *)arg1 = value; return (0); } static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS) { return (sysctl_int_range(oidp, arg1, arg2, req, AGE_PROC_MIN, AGE_PROC_MAX)); } static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) { return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, AGE_IM_TIMER_MAX)); } diff --git a/sys/dev/age/if_agevar.h b/sys/dev/age/if_agevar.h index 800c33d8e619..82fc91b18723 100644 --- a/sys/dev/age/if_agevar.h +++ b/sys/dev/age/if_agevar.h @@ -1,276 +1,276 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2008, Pyun YongHyeon * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _IF_AGEVAR_H #define _IF_AGEVAR_H #define AGE_TX_RING_CNT 256 #define AGE_RX_RING_CNT 256 #define AGE_RR_RING_CNT (AGE_TX_RING_CNT + AGE_RX_RING_CNT) /* The following ring alignments are just guessing. */ #define AGE_TX_RING_ALIGN 16 #define AGE_RX_RING_ALIGN 16 #define AGE_RR_RING_ALIGN 16 #define AGE_CMB_ALIGN 16 #define AGE_SMB_ALIGN 16 #define AGE_TSO_MAXSEGSIZE 4096 #define AGE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) #define AGE_MAXTXSEGS 35 #define AGE_RX_BUF_ALIGN 8 #ifndef __NO_STRICT_ALIGNMENT #define AGE_RX_BUF_SIZE (MCLBYTES - AGE_RX_BUF_ALIGN) #else #define AGE_RX_BUF_SIZE (MCLBYTES) #endif #define AGE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) #define AGE_ADDR_HI(x) ((uint64_t) (x) >> 32) #define AGE_MSI_MESSAGES 1 #define AGE_MSIX_MESSAGES 1 /* TODO : Should get real jumbo MTU size. */ #define AGE_JUMBO_FRAMELEN 10240 #define AGE_JUMBO_MTU \ (AGE_JUMBO_FRAMELEN - ETHER_VLAN_ENCAP_LEN - \ ETHER_HDR_LEN - ETHER_CRC_LEN) #define AGE_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) #define AGE_PROC_MIN 30 #define AGE_PROC_MAX (AGE_RX_RING_CNT - 1) #define AGE_PROC_DEFAULT (AGE_RX_RING_CNT / 2) struct age_txdesc { struct mbuf *tx_m; bus_dmamap_t tx_dmamap; struct tx_desc *tx_desc; }; struct age_rxdesc { struct mbuf *rx_m; bus_dmamap_t rx_dmamap; struct rx_desc *rx_desc; }; struct age_chain_data{ bus_dma_tag_t age_parent_tag; bus_dma_tag_t age_buffer_tag; bus_dma_tag_t age_tx_tag; struct age_txdesc age_txdesc[AGE_TX_RING_CNT]; bus_dma_tag_t age_rx_tag; struct age_rxdesc age_rxdesc[AGE_RX_RING_CNT]; bus_dma_tag_t age_tx_ring_tag; bus_dmamap_t age_tx_ring_map; bus_dma_tag_t age_rx_ring_tag; bus_dmamap_t age_rx_ring_map; bus_dmamap_t age_rx_sparemap; bus_dma_tag_t age_rr_ring_tag; bus_dmamap_t age_rr_ring_map; bus_dma_tag_t age_cmb_block_tag; bus_dmamap_t age_cmb_block_map; bus_dma_tag_t age_smb_block_tag; bus_dmamap_t age_smb_block_map; int age_tx_prod; int age_tx_cons; int age_tx_cnt; int age_rx_cons; int age_rr_cons; int age_rxlen; struct mbuf *age_rxhead; struct mbuf *age_rxtail; struct mbuf *age_rxprev_tail; }; struct age_ring_data { struct tx_desc *age_tx_ring; bus_addr_t age_tx_ring_paddr; struct rx_desc *age_rx_ring; bus_addr_t age_rx_ring_paddr; struct rx_rdesc *age_rr_ring; bus_addr_t age_rr_ring_paddr; struct cmb *age_cmb_block; bus_addr_t age_cmb_block_paddr; struct smb *age_smb_block; bus_addr_t age_smb_block_paddr; }; #define AGE_TX_RING_SZ \ (sizeof(struct tx_desc) * AGE_TX_RING_CNT) #define AGE_RX_RING_SZ \ (sizeof(struct rx_desc) * AGE_RX_RING_CNT) #define AGE_RR_RING_SZ \ (sizeof(struct rx_rdesc) * AGE_RR_RING_CNT) #define AGE_CMB_BLOCK_SZ sizeof(struct cmb) #define AGE_SMB_BLOCK_SZ sizeof(struct smb) struct age_stats { /* Rx stats. */ uint64_t rx_frames; uint64_t rx_bcast_frames; uint64_t rx_mcast_frames; uint32_t rx_pause_frames; uint32_t rx_control_frames; uint32_t rx_crcerrs; uint32_t rx_lenerrs; uint64_t rx_bytes; uint32_t rx_runts; uint64_t rx_fragments; uint64_t rx_pkts_64; uint64_t rx_pkts_65_127; uint64_t rx_pkts_128_255; uint64_t rx_pkts_256_511; uint64_t rx_pkts_512_1023; uint64_t rx_pkts_1024_1518; uint64_t rx_pkts_1519_max; uint64_t rx_pkts_truncated; uint32_t rx_fifo_oflows; uint32_t rx_desc_oflows; uint32_t rx_alignerrs; uint64_t rx_bcast_bytes; uint64_t rx_mcast_bytes; uint64_t rx_pkts_filtered; /* Tx stats. */ uint64_t tx_frames; uint64_t tx_bcast_frames; uint64_t tx_mcast_frames; uint32_t tx_pause_frames; uint32_t tx_excess_defer; uint32_t tx_control_frames; uint32_t tx_deferred; uint64_t tx_bytes; uint64_t tx_pkts_64; uint64_t tx_pkts_65_127; uint64_t tx_pkts_128_255; uint64_t tx_pkts_256_511; uint64_t tx_pkts_512_1023; uint64_t tx_pkts_1024_1518; uint64_t tx_pkts_1519_max; uint32_t tx_single_colls; uint32_t tx_multi_colls; uint32_t tx_late_colls; uint32_t tx_excess_colls; uint32_t tx_underrun; uint32_t tx_desc_underrun; uint32_t tx_lenerrs; uint32_t tx_pkts_truncated; uint64_t tx_bcast_bytes; uint64_t tx_mcast_bytes; }; /* * Software state per device. */ struct age_softc { - struct ifnet *age_ifp; + if_t age_ifp; device_t age_dev; device_t age_miibus; struct resource *age_res[1]; struct resource_spec *age_res_spec; struct resource *age_irq[AGE_MSI_MESSAGES]; struct resource_spec *age_irq_spec; void *age_intrhand[AGE_MSI_MESSAGES]; int age_rev; int age_chip_rev; int age_phyaddr; uint8_t age_eaddr[ETHER_ADDR_LEN]; uint32_t age_dma_rd_burst; uint32_t age_dma_wr_burst; int age_flags; #define AGE_FLAG_PCIE 0x0001 #define AGE_FLAG_PCIX 0x0002 #define AGE_FLAG_MSI 0x0004 #define AGE_FLAG_MSIX 0x0008 #define AGE_FLAG_PMCAP 0x0010 #define AGE_FLAG_DETACH 0x4000 #define AGE_FLAG_LINK 0x8000 struct callout age_tick_ch; struct age_stats age_stat; struct age_chain_data age_cdata; struct age_ring_data age_rdata; int age_if_flags; int age_watchdog_timer; int age_process_limit; int age_int_mod; int age_max_frame_size; int age_morework; int age_rr_prod; int age_tpd_cons; struct task age_int_task; struct task age_link_task; struct taskqueue *age_tq; struct mtx age_mtx; }; /* Register access macros. */ #define CSR_WRITE_4(_sc, reg, val) \ bus_write_4((_sc)->age_res[0], (reg), (val)) #define CSR_WRITE_2(_sc, reg, val) \ bus_write_2((_sc)->age_res[0], (reg), (val)) #define CSR_READ_2(_sc, reg) \ bus_read_2((_sc)->age_res[0], (reg)) #define CSR_READ_4(_sc, reg) \ bus_read_4((_sc)->age_res[0], (reg)) #define AGE_LOCK(_sc) mtx_lock(&(_sc)->age_mtx) #define AGE_UNLOCK(_sc) mtx_unlock(&(_sc)->age_mtx) #define AGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->age_mtx, MA_OWNED) #define AGE_COMMIT_MBOX(_sc) \ do { \ CSR_WRITE_4(_sc, AGE_MBOX, \ (((_sc)->age_cdata.age_rx_cons << MBOX_RD_PROD_IDX_SHIFT) & \ MBOX_RD_PROD_IDX_MASK) | \ (((_sc)->age_cdata.age_rr_cons << \ MBOX_RRD_CONS_IDX_SHIFT) & MBOX_RRD_CONS_IDX_MASK) | \ (((_sc)->age_cdata.age_tx_prod << MBOX_TD_PROD_IDX_SHIFT) & \ MBOX_TD_PROD_IDX_MASK)); \ } while (0) #define AGE_RXCHAIN_RESET(_sc) \ do { \ (_sc)->age_cdata.age_rxhead = NULL; \ (_sc)->age_cdata.age_rxtail = NULL; \ (_sc)->age_cdata.age_rxprev_tail = NULL; \ (_sc)->age_cdata.age_rxlen = 0; \ } while (0) #define AGE_TX_TIMEOUT 5 #define AGE_RESET_TIMEOUT 100 #define AGE_TIMEOUT 1000 #define AGE_PHY_TIMEOUT 1000 #endif /* _IF_AGEVAR_H */ diff --git a/sys/dev/alc/if_alc.c b/sys/dev/alc/if_alc.c index dc1df6753811..6f6d95e266ea 100644 --- a/sys/dev/alc/if_alc.c +++ b/sys/dev/alc/if_alc.c @@ -1,4718 +1,4717 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2009, Pyun YongHyeon * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* "device miibus" required. See GENERIC if you get errors here. */ #include "miibus_if.h" #undef ALC_USE_CUSTOM_CSUM #ifdef ALC_USE_CUSTOM_CSUM #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) #else #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) #endif MODULE_DEPEND(alc, pci, 1, 1, 1); MODULE_DEPEND(alc, ether, 1, 1, 1); MODULE_DEPEND(alc, miibus, 1, 1, 1); /* Tunables. */ static int msi_disable = 0; static int msix_disable = 0; TUNABLE_INT("hw.alc.msi_disable", &msi_disable); TUNABLE_INT("hw.alc.msix_disable", &msix_disable); /* * Devices supported by this driver. */ static struct alc_ident alc_ident_table[] = { { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, "Atheros AR8131 PCIe Gigabit Ethernet" }, { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, "Atheros AR8132 PCIe Fast Ethernet" }, { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, "Atheros AR8161 PCIe Gigabit Ethernet" }, { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, "Atheros AR8162 PCIe Fast Ethernet" }, { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, "Atheros AR8171 PCIe Gigabit Ethernet" }, { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, "Atheros AR8172 PCIe Fast Ethernet" }, { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, "Killer E2200 Gigabit Ethernet" }, { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024, "Killer E2400 Gigabit Ethernet" }, { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024, "Killer E2500 Gigabit Ethernet" }, { 0, 0, 0, NULL} }; static void alc_aspm(struct alc_softc *, int, int); static void alc_aspm_813x(struct alc_softc *, int); static void alc_aspm_816x(struct alc_softc *, int); static int alc_attach(device_t); static int alc_check_boundary(struct alc_softc *); static void alc_config_msi(struct alc_softc *); static int alc_detach(device_t); static void alc_disable_l0s_l1(struct alc_softc *); static int alc_dma_alloc(struct alc_softc *); static void alc_dma_free(struct alc_softc *); static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); static void alc_dsp_fixup(struct alc_softc *, int); static int alc_encap(struct alc_softc *, struct mbuf **); static struct alc_ident * alc_find_ident(device_t); #ifndef __NO_STRICT_ALIGNMENT static struct mbuf * - alc_fixup_rx(struct ifnet *, struct mbuf *); + alc_fixup_rx(if_t, struct mbuf *); #endif static void alc_get_macaddr(struct alc_softc *); static void alc_get_macaddr_813x(struct alc_softc *); static void alc_get_macaddr_816x(struct alc_softc *); static void alc_get_macaddr_par(struct alc_softc *); static void alc_init(void *); static void alc_init_cmb(struct alc_softc *); static void alc_init_locked(struct alc_softc *); static void alc_init_rr_ring(struct alc_softc *); static int alc_init_rx_ring(struct alc_softc *); static void alc_init_smb(struct alc_softc *); static void alc_init_tx_ring(struct alc_softc *); static void alc_int_task(void *, int); static int alc_intr(void *); -static int alc_ioctl(struct ifnet *, u_long, caddr_t); +static int alc_ioctl(if_t, u_long, caddr_t); static void alc_mac_config(struct alc_softc *); static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); static int alc_miibus_readreg(device_t, int, int); static void alc_miibus_statchg(device_t); static int alc_miibus_writereg(device_t, int, int, int); static uint32_t alc_miidbg_readreg(struct alc_softc *, int); static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); -static int alc_mediachange(struct ifnet *); +static int alc_mediachange(if_t); static int alc_mediachange_locked(struct alc_softc *); -static void alc_mediastatus(struct ifnet *, struct ifmediareq *); +static void alc_mediastatus(if_t, struct ifmediareq *); static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); static void alc_osc_reset(struct alc_softc *); static void alc_phy_down(struct alc_softc *); static void alc_phy_reset(struct alc_softc *); static void alc_phy_reset_813x(struct alc_softc *); static void alc_phy_reset_816x(struct alc_softc *); static int alc_probe(device_t); static void alc_reset(struct alc_softc *); static int alc_resume(device_t); static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); static int alc_rxintr(struct alc_softc *, int); static void alc_rxfilter(struct alc_softc *); static void alc_rxvlan(struct alc_softc *); static void alc_setlinkspeed(struct alc_softc *); static void alc_setwol(struct alc_softc *); static void alc_setwol_813x(struct alc_softc *); static void alc_setwol_816x(struct alc_softc *); static int alc_shutdown(device_t); -static void alc_start(struct ifnet *); -static void alc_start_locked(struct ifnet *); +static void alc_start(if_t); +static void alc_start_locked(if_t); static void alc_start_queue(struct alc_softc *); static void alc_start_tx(struct alc_softc *); static void alc_stats_clear(struct alc_softc *); static void alc_stats_update(struct alc_softc *); static void alc_stop(struct alc_softc *); static void alc_stop_mac(struct alc_softc *); static void alc_stop_queue(struct alc_softc *); static int alc_suspend(device_t); static void alc_sysctl_node(struct alc_softc *); static void alc_tick(void *); static void alc_txeof(struct alc_softc *); static void alc_watchdog(struct alc_softc *); static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); DEBUGNET_DEFINE(alc); static device_method_t alc_methods[] = { /* Device interface. */ DEVMETHOD(device_probe, alc_probe), DEVMETHOD(device_attach, alc_attach), DEVMETHOD(device_detach, alc_detach), DEVMETHOD(device_shutdown, alc_shutdown), DEVMETHOD(device_suspend, alc_suspend), DEVMETHOD(device_resume, alc_resume), /* MII interface. */ DEVMETHOD(miibus_readreg, alc_miibus_readreg), DEVMETHOD(miibus_writereg, alc_miibus_writereg), DEVMETHOD(miibus_statchg, alc_miibus_statchg), DEVMETHOD_END }; static driver_t alc_driver = { "alc", alc_methods, sizeof(struct alc_softc) }; DRIVER_MODULE(alc, pci, alc_driver, 0, 0); MODULE_PNP_INFO("U16:vendor;U16:device", pci, alc, alc_ident_table, nitems(alc_ident_table) - 1); DRIVER_MODULE(miibus, alc, miibus_driver, 0, 0); static struct resource_spec alc_res_spec_mem[] = { { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, { -1, 0, 0 } }; static struct resource_spec alc_irq_spec_legacy[] = { { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, { -1, 0, 0 } }; static struct resource_spec alc_irq_spec_msi[] = { { SYS_RES_IRQ, 1, RF_ACTIVE }, { -1, 0, 0 } }; static struct resource_spec alc_irq_spec_msix[] = { { SYS_RES_IRQ, 1, RF_ACTIVE }, { -1, 0, 0 } }; static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; static int alc_miibus_readreg(device_t dev, int phy, int reg) { struct alc_softc *sc; int v; sc = device_get_softc(dev); if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) v = alc_mii_readreg_816x(sc, phy, reg); else v = alc_mii_readreg_813x(sc, phy, reg); return (v); } static uint32_t alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) { uint32_t v; int i; /* * For AR8132 fast ethernet controller, do not report 1000baseT * capability to mii(4). Even though AR8132 uses the same * model/revision number of F1 gigabit PHY, the PHY has no * ability to establish 1000baseT link. */ if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && reg == MII_EXTSR) return (0); CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); for (i = ALC_PHY_TIMEOUT; i > 0; i--) { DELAY(5); v = CSR_READ_4(sc, ALC_MDIO); if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) break; } if (i == 0) { device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); return (0); } return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); } static uint32_t alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) { uint32_t clk, v; int i; if ((sc->alc_flags & ALC_FLAG_LINK) != 0) clk = MDIO_CLK_25_128; else clk = MDIO_CLK_25_4; CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); for (i = ALC_PHY_TIMEOUT; i > 0; i--) { DELAY(5); v = CSR_READ_4(sc, ALC_MDIO); if ((v & MDIO_OP_BUSY) == 0) break; } if (i == 0) { device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); return (0); } return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); } static int alc_miibus_writereg(device_t dev, int phy, int reg, int val) { struct alc_softc *sc; int v; sc = device_get_softc(dev); if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) v = alc_mii_writereg_816x(sc, phy, reg, val); else v = alc_mii_writereg_813x(sc, phy, reg, val); return (v); } static uint32_t alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) { uint32_t v; int i; CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); for (i = ALC_PHY_TIMEOUT; i > 0; i--) { DELAY(5); v = CSR_READ_4(sc, ALC_MDIO); if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) break; } if (i == 0) device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); return (0); } static uint32_t alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) { uint32_t clk, v; int i; if ((sc->alc_flags & ALC_FLAG_LINK) != 0) clk = MDIO_CLK_25_128; else clk = MDIO_CLK_25_4; CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | MDIO_SUP_PREAMBLE | clk); for (i = ALC_PHY_TIMEOUT; i > 0; i--) { DELAY(5); v = CSR_READ_4(sc, ALC_MDIO); if ((v & MDIO_OP_BUSY) == 0) break; } if (i == 0) device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); return (0); } static void alc_miibus_statchg(device_t dev) { struct alc_softc *sc; struct mii_data *mii; - struct ifnet *ifp; + if_t ifp; uint32_t reg; sc = device_get_softc(dev); mii = device_get_softc(sc->alc_miibus); ifp = sc->alc_ifp; if (mii == NULL || ifp == NULL || - (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) + (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) return; sc->alc_flags &= ~ALC_FLAG_LINK; if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: sc->alc_flags |= ALC_FLAG_LINK; break; case IFM_1000_T: if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) sc->alc_flags |= ALC_FLAG_LINK; break; default: break; } } /* Stop Rx/Tx MACs. */ alc_stop_mac(sc); /* Program MACs with resolved speed/duplex/flow-control. */ if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { alc_start_queue(sc); alc_mac_config(sc); /* Re-enable Tx/Rx MACs. */ reg = CSR_READ_4(sc, ALC_MAC_CFG); reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; CSR_WRITE_4(sc, ALC_MAC_CFG, reg); } alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); } static uint32_t alc_miidbg_readreg(struct alc_softc *sc, int reg) { alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, reg); return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA)); } static uint32_t alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) { alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, reg); return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, val)); } static uint32_t alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) { uint32_t clk, v; int i; CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | EXT_MDIO_DEVADDR(devaddr)); if ((sc->alc_flags & ALC_FLAG_LINK) != 0) clk = MDIO_CLK_25_128; else clk = MDIO_CLK_25_4; CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); for (i = ALC_PHY_TIMEOUT; i > 0; i--) { DELAY(5); v = CSR_READ_4(sc, ALC_MDIO); if ((v & MDIO_OP_BUSY) == 0) break; } if (i == 0) { device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", devaddr, reg); return (0); } return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); } static uint32_t alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) { uint32_t clk, v; int i; CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | EXT_MDIO_DEVADDR(devaddr)); if ((sc->alc_flags & ALC_FLAG_LINK) != 0) clk = MDIO_CLK_25_128; else clk = MDIO_CLK_25_4; CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); for (i = ALC_PHY_TIMEOUT; i > 0; i--) { DELAY(5); v = CSR_READ_4(sc, ALC_MDIO); if ((v & MDIO_OP_BUSY) == 0) break; } if (i == 0) device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", devaddr, reg); return (0); } static void alc_dsp_fixup(struct alc_softc *sc, int media) { uint16_t agc, len, val; if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) return; if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) return; /* * Vendor PHY magic. * 1000BT/AZ, wrong cable length */ if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & EXT_CLDCTL6_CAB_LEN_MASK; agc = alc_miidbg_readreg(sc, MII_DBG_AGC); agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && agc > DBG_AGC_LONG1G_LIMT) || (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && agc > DBG_AGC_LONG1G_LIMT)) { alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, DBG_AZ_ANADECT_LONG); val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); val |= ANEG_AFEE_10BT_100M_TH; alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); } else { alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, DBG_AZ_ANADECT_DEFAULT); val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); val &= ~ANEG_AFEE_10BT_100M_TH; alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); } if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { if (media == IFM_1000_T) { /* * Giga link threshold, raise the tolerance of * noise 50%. */ val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); val &= ~DBG_MSE20DB_TH_MASK; val |= (DBG_MSE20DB_TH_HI << DBG_MSE20DB_TH_SHIFT); alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); } else if (media == IFM_100_TX) alc_miidbg_writereg(sc, MII_DBG_MSE16DB, DBG_MSE16DB_UP); } } else { val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); val &= ~ANEG_AFEE_10BT_100M_TH; alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { alc_miidbg_writereg(sc, MII_DBG_MSE16DB, DBG_MSE16DB_DOWN); val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); val &= ~DBG_MSE20DB_TH_MASK; val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); } } } static void -alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) +alc_mediastatus(if_t ifp, struct ifmediareq *ifmr) { struct alc_softc *sc; struct mii_data *mii; - sc = ifp->if_softc; + sc = if_getsoftc(ifp); ALC_LOCK(sc); - if ((ifp->if_flags & IFF_UP) == 0) { + if ((if_getflags(ifp) & IFF_UP) == 0) { ALC_UNLOCK(sc); return; } mii = device_get_softc(sc->alc_miibus); mii_pollstat(mii); ifmr->ifm_status = mii->mii_media_status; ifmr->ifm_active = mii->mii_media_active; ALC_UNLOCK(sc); } static int -alc_mediachange(struct ifnet *ifp) +alc_mediachange(if_t ifp) { struct alc_softc *sc; int error; - sc = ifp->if_softc; + sc = if_getsoftc(ifp); ALC_LOCK(sc); error = alc_mediachange_locked(sc); ALC_UNLOCK(sc); return (error); } static int alc_mediachange_locked(struct alc_softc *sc) { struct mii_data *mii; struct mii_softc *miisc; int error; ALC_LOCK_ASSERT(sc); mii = device_get_softc(sc->alc_miibus); LIST_FOREACH(miisc, &mii->mii_phys, mii_list) PHY_RESET(miisc); error = mii_mediachg(mii); return (error); } static struct alc_ident * alc_find_ident(device_t dev) { struct alc_ident *ident; uint16_t vendor, devid; vendor = pci_get_vendor(dev); devid = pci_get_device(dev); for (ident = alc_ident_table; ident->name != NULL; ident++) { if (vendor == ident->vendorid && devid == ident->deviceid) return (ident); } return (NULL); } static int alc_probe(device_t dev) { struct alc_ident *ident; ident = alc_find_ident(dev); if (ident != NULL) { device_set_desc(dev, ident->name); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static void alc_get_macaddr(struct alc_softc *sc) { if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) alc_get_macaddr_816x(sc); else alc_get_macaddr_813x(sc); } static void alc_get_macaddr_813x(struct alc_softc *sc) { uint32_t opt; uint16_t val; int eeprom, i; eeprom = 0; opt = CSR_READ_4(sc, ALC_OPT_CFG); if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { /* * EEPROM found, let TWSI reload EEPROM configuration. * This will set ethernet address of controller. */ eeprom++; switch (sc->alc_ident->deviceid) { case DEVICEID_ATHEROS_AR8131: case DEVICEID_ATHEROS_AR8132: if ((opt & OPT_CFG_CLK_ENB) == 0) { opt |= OPT_CFG_CLK_ENB; CSR_WRITE_4(sc, ALC_OPT_CFG, opt); CSR_READ_4(sc, ALC_OPT_CFG); DELAY(1000); } break; case DEVICEID_ATHEROS_AR8151: case DEVICEID_ATHEROS_AR8151_V2: case DEVICEID_ATHEROS_AR8152_B: case DEVICEID_ATHEROS_AR8152_B2: alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 0x00); val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, val & 0xFF7F); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 0x3B); val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, val | 0x0008); DELAY(20); break; } CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); CSR_WRITE_4(sc, ALC_WOL_CFG, 0); CSR_READ_4(sc, ALC_WOL_CFG); CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | TWSI_CFG_SW_LD_START); for (i = 100; i > 0; i--) { DELAY(1000); if ((CSR_READ_4(sc, ALC_TWSI_CFG) & TWSI_CFG_SW_LD_START) == 0) break; } if (i == 0) device_printf(sc->alc_dev, "reloading EEPROM timeout!\n"); } else { if (bootverbose) device_printf(sc->alc_dev, "EEPROM not found!\n"); } if (eeprom != 0) { switch (sc->alc_ident->deviceid) { case DEVICEID_ATHEROS_AR8131: case DEVICEID_ATHEROS_AR8132: if ((opt & OPT_CFG_CLK_ENB) != 0) { opt &= ~OPT_CFG_CLK_ENB; CSR_WRITE_4(sc, ALC_OPT_CFG, opt); CSR_READ_4(sc, ALC_OPT_CFG); DELAY(1000); } break; case DEVICEID_ATHEROS_AR8151: case DEVICEID_ATHEROS_AR8151_V2: case DEVICEID_ATHEROS_AR8152_B: case DEVICEID_ATHEROS_AR8152_B2: alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 0x00); val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, val | 0x0080); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 0x3B); val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, val & 0xFFF7); DELAY(20); break; } } alc_get_macaddr_par(sc); } static void alc_get_macaddr_816x(struct alc_softc *sc) { uint32_t reg; int i, reloaded; reloaded = 0; /* Try to reload station address via TWSI. */ for (i = 100; i > 0; i--) { reg = CSR_READ_4(sc, ALC_SLD); if ((reg & (SLD_PROGRESS | SLD_START)) == 0) break; DELAY(1000); } if (i != 0) { CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); for (i = 100; i > 0; i--) { DELAY(1000); reg = CSR_READ_4(sc, ALC_SLD); if ((reg & SLD_START) == 0) break; } if (i != 0) reloaded++; else if (bootverbose) device_printf(sc->alc_dev, "reloading station address via TWSI timed out!\n"); } /* Try to reload station address from EEPROM or FLASH. */ if (reloaded == 0) { reg = CSR_READ_4(sc, ALC_EEPROM_LD); if ((reg & (EEPROM_LD_EEPROM_EXIST | EEPROM_LD_FLASH_EXIST)) != 0) { for (i = 100; i > 0; i--) { reg = CSR_READ_4(sc, ALC_EEPROM_LD); if ((reg & (EEPROM_LD_PROGRESS | EEPROM_LD_START)) == 0) break; DELAY(1000); } if (i != 0) { CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | EEPROM_LD_START); for (i = 100; i > 0; i--) { DELAY(1000); reg = CSR_READ_4(sc, ALC_EEPROM_LD); if ((reg & EEPROM_LD_START) == 0) break; } } else if (bootverbose) device_printf(sc->alc_dev, "reloading EEPROM/FLASH timed out!\n"); } } alc_get_macaddr_par(sc); } static void alc_get_macaddr_par(struct alc_softc *sc) { uint32_t ea[2]; ea[0] = CSR_READ_4(sc, ALC_PAR0); ea[1] = CSR_READ_4(sc, ALC_PAR1); sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; } static void alc_disable_l0s_l1(struct alc_softc *sc) { uint32_t pmcfg; if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { /* Another magic from vendor. */ pmcfg = CSR_READ_4(sc, ALC_PM_CFG); pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); } } static void alc_phy_reset(struct alc_softc *sc) { if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) alc_phy_reset_816x(sc); else alc_phy_reset_813x(sc); } static void alc_phy_reset_813x(struct alc_softc *sc) { uint16_t data; /* Reset magic from Linux. */ CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); CSR_READ_2(sc, ALC_GPHY_CFG); DELAY(10 * 1000); CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | GPHY_CFG_SEL_ANA_RESET); CSR_READ_2(sc, ALC_GPHY_CFG); DELAY(10 * 1000); /* DSP fixup, Vendor magic. */ if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 0x000A); data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, data & 0xDFFF); } if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 0x003B); data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, data & 0xFFF7); DELAY(20 * 1000); } if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 0x0029); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 0x929D); } if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 0x0029); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 0xB6DD); } /* Load DSP codes, vendor magic. */ data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, MII_ANA_CFG18); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, data); data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | ANA_SERDES_EN_LCKDT; alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, MII_ANA_CFG5); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, data); data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & ANA_LONG_CABLE_TH_100_MASK) | ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & ANA_SHORT_CABLE_TH_100_SHIFT) | ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, MII_ANA_CFG54); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, data); data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, MII_ANA_CFG4); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, data); data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | ANA_OEN_125M; alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, MII_ANA_CFG0); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, data); DELAY(1000); /* Disable hibernation. */ alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 0x0029); data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA); data &= ~0x8000; alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, data); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 0x000B); data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA); data &= ~0x8000; alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, data); } static void alc_phy_reset_816x(struct alc_softc *sc) { uint32_t val; val = CSR_READ_4(sc, ALC_GPHY_CFG); val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); val |= GPHY_CFG_SEL_ANA_RESET; #ifdef notyet val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; #else /* Disable PHY hibernation. */ val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); #endif CSR_WRITE_4(sc, ALC_GPHY_CFG, val); DELAY(10); CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); DELAY(800); /* Vendor PHY magic. */ #ifdef notyet alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, EXT_VDRVBIAS_DEFAULT); #else /* Disable PHY hibernation. */ alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); alc_miidbg_writereg(sc, MII_DBG_HIBNEG, DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); #endif /* XXX Disable EEE. */ val = CSR_READ_4(sc, ALC_LPI_CTL); val &= ~LPI_CTL_ENB; CSR_WRITE_4(sc, ALC_LPI_CTL, val); alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); /* PHY power saving. */ alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); val &= ~DBG_GREENCFG2_GATE_DFSE_EN; alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); /* RTL8139C, 120m issue. */ alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, ANEG_NLP78_120M_DEFAULT); alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, ANEG_S3DIG10_DEFAULT); if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { /* Turn off half amplitude. */ val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); /* Turn off Green feature. */ val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); val |= DBG_GREENCFG2_BP_GREEN; alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); /* Turn off half bias. */ val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); val |= EXT_CLDCTL5_BP_VD_HLFBIAS; alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); } } static void alc_phy_down(struct alc_softc *sc) { uint32_t gphy; switch (sc->alc_ident->deviceid) { case DEVICEID_ATHEROS_AR8161: case DEVICEID_ATHEROS_E2200: case DEVICEID_ATHEROS_E2400: case DEVICEID_ATHEROS_E2500: case DEVICEID_ATHEROS_AR8162: case DEVICEID_ATHEROS_AR8171: case DEVICEID_ATHEROS_AR8172: gphy = CSR_READ_4(sc, ALC_GPHY_CFG); gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); break; case DEVICEID_ATHEROS_AR8151: case DEVICEID_ATHEROS_AR8151_V2: case DEVICEID_ATHEROS_AR8152_B: case DEVICEID_ATHEROS_AR8152_B2: /* * GPHY power down caused more problems on AR8151 v2.0. * When driver is reloaded after GPHY power down, * accesses to PHY/MAC registers hung the system. Only * cold boot recovered from it. I'm not sure whether * AR8151 v1.0 also requires this one though. I don't * have AR8151 v1.0 controller in hand. * The only option left is to isolate the PHY and * initiates power down the PHY which in turn saves * more power when driver is unloaded. */ alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_BMCR, BMCR_ISO | BMCR_PDOWN); break; default: /* Force PHY down. */ CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW); DELAY(1000); break; } } static void alc_aspm(struct alc_softc *sc, int init, int media) { if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) alc_aspm_816x(sc, init); else alc_aspm_813x(sc, media); } static void alc_aspm_813x(struct alc_softc *sc, int media) { uint32_t pmcfg; uint16_t linkcfg; if ((sc->alc_flags & ALC_FLAG_LINK) == 0) return; pmcfg = CSR_READ_4(sc, ALC_PM_CFG); if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == (ALC_FLAG_APS | ALC_FLAG_PCIE)) linkcfg = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); else linkcfg = 0; pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); pmcfg |= PM_CFG_MAC_ASPM_CHK; pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); if ((sc->alc_flags & ALC_FLAG_APS) != 0) { /* Disable extended sync except AR8152 B v1.0 */ linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && sc->alc_rev == ATHEROS_AR8152_B_V10) linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, linkcfg); pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | PM_CFG_HOTRST); pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << PM_CFG_L1_ENTRY_TIMER_SHIFT); pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << PM_CFG_PM_REQ_TIMER_SHIFT); pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; } if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { if ((sc->alc_flags & ALC_FLAG_L0S) != 0) pmcfg |= PM_CFG_ASPM_L0S_ENB; if ((sc->alc_flags & ALC_FLAG_L1S) != 0) pmcfg |= PM_CFG_ASPM_L1_ENB; if ((sc->alc_flags & ALC_FLAG_APS) != 0) { if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) pmcfg &= ~PM_CFG_ASPM_L0S_ENB; pmcfg &= ~(PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_BUDS_RX_L1_ENB); pmcfg |= PM_CFG_CLK_SWH_L1; if (media == IFM_100_TX || media == IFM_1000_T) { pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; switch (sc->alc_ident->deviceid) { case DEVICEID_ATHEROS_AR8152_B: pmcfg |= (7 << PM_CFG_L1_ENTRY_TIMER_SHIFT); break; case DEVICEID_ATHEROS_AR8152_B2: case DEVICEID_ATHEROS_AR8151_V2: pmcfg |= (4 << PM_CFG_L1_ENTRY_TIMER_SHIFT); break; default: pmcfg |= (15 << PM_CFG_L1_ENTRY_TIMER_SHIFT); break; } } } else { pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_BUDS_RX_L1_ENB; pmcfg &= ~(PM_CFG_CLK_SWH_L1 | PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); } } else { pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB); pmcfg |= PM_CFG_CLK_SWH_L1; if ((sc->alc_flags & ALC_FLAG_L1S) != 0) pmcfg |= PM_CFG_ASPM_L1_ENB; } CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); } static void alc_aspm_816x(struct alc_softc *sc, int init) { uint32_t pmcfg; pmcfg = CSR_READ_4(sc, ALC_PM_CFG); pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && (sc->alc_rev & 0x01) != 0) pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { /* Link up, enable both L0s, L1s. */ pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; } else { if (init != 0) pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; - else if ((sc->alc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + else if ((if_getdrvflags(sc->alc_ifp) & IFF_DRV_RUNNING) != 0) pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; } CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); } static void alc_init_pcie(struct alc_softc *sc) { const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; uint32_t cap, ctl, val; int state; /* Clear data link and flow-control protocol error. */ val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, CSR_READ_4(sc, ALC_PCIE_PHYMISC) | PCIE_PHYMISC_FORCE_RCV_DET); if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && sc->alc_rev == ATHEROS_AR8152_B_V10) { val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | PCIE_PHYMISC2_SERDES_TH_MASK); val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); } /* Disable ASPM L0S and L1. */ cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); if ((ctl & PCIEM_LINK_CTL_RCB) != 0) sc->alc_rcb = DMA_CFG_RCB_128; if (bootverbose) device_printf(sc->alc_dev, "RCB %u bytes\n", sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); state = ctl & PCIEM_LINK_CTL_ASPMC; if (state & PCIEM_LINK_CTL_ASPMC_L0S) sc->alc_flags |= ALC_FLAG_L0S; if (state & PCIEM_LINK_CTL_ASPMC_L1) sc->alc_flags |= ALC_FLAG_L1S; if (bootverbose) device_printf(sc->alc_dev, "ASPM %s %s\n", aspm_state[state], state == 0 ? "disabled" : "enabled"); alc_disable_l0s_l1(sc); } else { if (bootverbose) device_printf(sc->alc_dev, "no ASPM support\n"); } } else { val = CSR_READ_4(sc, ALC_PDLL_TRNS1); val &= ~PDLL_TRNS1_D3PLLOFF_ENB; CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); val = CSR_READ_4(sc, ALC_MASTER_CFG); if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && (sc->alc_rev & 0x01) != 0) { if ((val & MASTER_WAKEN_25M) == 0 || (val & MASTER_CLK_SEL_DIS) == 0) { val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; CSR_WRITE_4(sc, ALC_MASTER_CFG, val); } } else { if ((val & MASTER_WAKEN_25M) == 0 || (val & MASTER_CLK_SEL_DIS) != 0) { val |= MASTER_WAKEN_25M; val &= ~MASTER_CLK_SEL_DIS; CSR_WRITE_4(sc, ALC_MASTER_CFG, val); } } } alc_aspm(sc, 1, IFM_UNKNOWN); } static void alc_config_msi(struct alc_softc *sc) { uint32_t ctl, mod; if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { /* * It seems interrupt moderation is controlled by * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. * Driver uses RX interrupt moderation parameter to * program ALC_MSI_RETRANS_TIMER register. */ ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); ctl &= ~MSI_RETRANS_TIMER_MASK; ctl &= ~MSI_RETRANS_MASK_SEL_LINE; mod = ALC_USECS(sc->alc_int_rx_mod); if (mod == 0) mod = 1; ctl |= mod; if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | MSI_RETRANS_MASK_SEL_STD); else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | MSI_RETRANS_MASK_SEL_LINE); else CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); } } static int alc_attach(device_t dev) { struct alc_softc *sc; - struct ifnet *ifp; + if_t ifp; int base, error, i, msic, msixc; uint16_t burst; error = 0; sc = device_get_softc(dev); sc->alc_dev = dev; sc->alc_rev = pci_get_revid(dev); mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); NET_TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); sc->alc_ident = alc_find_ident(dev); /* Map the device. */ pci_enable_busmaster(dev); sc->alc_res_spec = alc_res_spec_mem; sc->alc_irq_spec = alc_irq_spec_legacy; error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); if (error != 0) { device_printf(dev, "cannot allocate memory resources.\n"); goto fail; } /* Set PHY address. */ sc->alc_phyaddr = ALC_PHY_ADDR; /* * One odd thing is AR8132 uses the same PHY hardware(F1 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports * the PHY supports 1000Mbps but that's not true. The PHY * used in AR8132 can't establish gigabit link even if it * shows the same PHY model/revision number of AR8131. */ switch (sc->alc_ident->deviceid) { case DEVICEID_ATHEROS_E2200: case DEVICEID_ATHEROS_E2400: case DEVICEID_ATHEROS_E2500: sc->alc_flags |= ALC_FLAG_E2X00; /* FALLTHROUGH */ case DEVICEID_ATHEROS_AR8161: if (pci_get_subvendor(dev) == VENDORID_ATHEROS && pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) sc->alc_flags |= ALC_FLAG_LINK_WAR; /* FALLTHROUGH */ case DEVICEID_ATHEROS_AR8171: sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; break; case DEVICEID_ATHEROS_AR8162: case DEVICEID_ATHEROS_AR8172: sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; break; case DEVICEID_ATHEROS_AR8152_B: case DEVICEID_ATHEROS_AR8152_B2: sc->alc_flags |= ALC_FLAG_APS; /* FALLTHROUGH */ case DEVICEID_ATHEROS_AR8132: sc->alc_flags |= ALC_FLAG_FASTETHER; break; case DEVICEID_ATHEROS_AR8151: case DEVICEID_ATHEROS_AR8151_V2: sc->alc_flags |= ALC_FLAG_APS; if (CSR_READ_4(sc, ALC_MT_MAGIC) == MT_MAGIC) sc->alc_flags |= ALC_FLAG_MT; /* FALLTHROUGH */ default: break; } sc->alc_flags |= ALC_FLAG_JUMBO; /* * It seems that AR813x/AR815x has silicon bug for SMB. In * addition, Atheros said that enabling SMB wouldn't improve * performance. However I think it's bad to access lots of * registers to extract MAC statistics. */ sc->alc_flags |= ALC_FLAG_SMB_BUG; /* * Don't use Tx CMB. It is known to have silicon bug. */ sc->alc_flags |= ALC_FLAG_CMB_BUG; sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> MASTER_CHIP_REV_SHIFT; if (bootverbose) { device_printf(dev, "PCI device revision : 0x%04x\n", sc->alc_rev); device_printf(dev, "Chip id/revision : 0x%04x\n", sc->alc_chip_rev); if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) device_printf(dev, "AR816x revision : 0x%x\n", AR816X_REV(sc->alc_rev)); } device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); /* Initialize DMA parameters. */ sc->alc_dma_rd_burst = 0; sc->alc_dma_wr_burst = 0; sc->alc_rcb = DMA_CFG_RCB_64; if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { sc->alc_flags |= ALC_FLAG_PCIE; sc->alc_expcap = base; burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); sc->alc_dma_rd_burst = (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; if (bootverbose) { device_printf(dev, "Read request size : %u bytes.\n", alc_dma_burst[sc->alc_dma_rd_burst]); device_printf(dev, "TLP payload size : %u bytes.\n", alc_dma_burst[sc->alc_dma_wr_burst]); } if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) sc->alc_dma_rd_burst = 3; if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) sc->alc_dma_wr_burst = 3; /* * Force maximum payload size to 128 bytes for * E2200/E2400/E2500/AR8162/AR8171/AR8172. * Otherwise it triggers DMA write error. */ if ((sc->alc_flags & (ALC_FLAG_E2X00 | ALC_FLAG_AR816X_FAMILY)) != 0) sc->alc_dma_wr_burst = 0; alc_init_pcie(sc); } /* Reset PHY. */ alc_phy_reset(sc); /* Reset the ethernet controller. */ alc_stop_mac(sc); alc_reset(sc); /* Allocate IRQ resources. */ msixc = pci_msix_count(dev); msic = pci_msi_count(dev); if (bootverbose) { device_printf(dev, "MSIX count : %d\n", msixc); device_printf(dev, "MSI count : %d\n", msic); } if (msixc > 1) msixc = 1; if (msic > 1) msic = 1; /* * Prefer MSIX over MSI. * AR816x controller has a silicon bug that MSI interrupt * does not assert if PCIM_CMD_INTxDIS bit of command * register is set. pci(4) was taught to handle that case. */ if (msix_disable == 0 || msi_disable == 0) { if (msix_disable == 0 && msixc > 0 && pci_alloc_msix(dev, &msixc) == 0) { if (msic == 1) { device_printf(dev, "Using %d MSIX message(s).\n", msixc); sc->alc_flags |= ALC_FLAG_MSIX; sc->alc_irq_spec = alc_irq_spec_msix; } else pci_release_msi(dev); } if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && msic > 0 && pci_alloc_msi(dev, &msic) == 0) { if (msic == 1) { device_printf(dev, "Using %d MSI message(s).\n", msic); sc->alc_flags |= ALC_FLAG_MSI; sc->alc_irq_spec = alc_irq_spec_msi; } else pci_release_msi(dev); } } error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); if (error != 0) { device_printf(dev, "cannot allocate IRQ resources.\n"); goto fail; } /* Create device sysctl node. */ alc_sysctl_node(sc); if ((error = alc_dma_alloc(sc)) != 0) goto fail; /* Load station address. */ alc_get_macaddr(sc); ifp = sc->alc_ifp = if_alloc(IFT_ETHER); if (ifp == NULL) { device_printf(dev, "cannot allocate ifnet structure.\n"); error = ENXIO; goto fail; } - ifp->if_softc = sc; + if_setsoftc(ifp, sc); if_initname(ifp, device_get_name(dev), device_get_unit(dev)); - ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; - ifp->if_ioctl = alc_ioctl; - ifp->if_start = alc_start; - ifp->if_init = alc_init; - ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; - IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); - IFQ_SET_READY(&ifp->if_snd); - ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; - ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; + if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); + if_setioctlfn(ifp, alc_ioctl); + if_setstartfn(ifp, alc_start); + if_setinitfn(ifp, alc_init); + if_setsendqlen(ifp, ALC_TX_RING_CNT - 1); + if_setsendqready(ifp); + if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_TSO4); + if_sethwassist(ifp, ALC_CSUM_FEATURES | CSUM_TSO); if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { - ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; + if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); sc->alc_flags |= ALC_FLAG_PM; sc->alc_pmcap = base; } - ifp->if_capenable = ifp->if_capabilities; + if_setcapenable(ifp, if_getcapabilities(ifp)); /* Set up MII bus. */ error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, MIIF_DOPAUSE); if (error != 0) { device_printf(dev, "attaching PHYs failed\n"); goto fail; } ether_ifattach(ifp, sc->alc_eaddr); /* VLAN capability setup. */ - ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | - IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; - ifp->if_capenable = ifp->if_capabilities; + if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | + IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); + if_setcapenable(ifp, if_getcapabilities(ifp)); /* * XXX * It seems enabling Tx checksum offloading makes more trouble. * Sometimes the controller does not receive any frames when * Tx checksum offloading is enabled. I'm not sure whether this * is a bug in Tx checksum offloading logic or I got broken * sample boards. To safety, don't enable Tx checksum offloading * by default but give chance to users to toggle it if they know * their controllers work without problems. * Fortunately, Tx checksum offloading for AR816x family * seems to work. */ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { - ifp->if_capenable &= ~IFCAP_TXCSUM; - ifp->if_hwassist &= ~ALC_CSUM_FEATURES; + if_setcapenablebit(ifp, 0, IFCAP_TXCSUM); + if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES); } /* Tell the upper layer(s) we support long frames. */ - ifp->if_hdrlen = sizeof(struct ether_vlan_header); + if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); /* Create local taskq. */ sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, taskqueue_thread_enqueue, &sc->alc_tq); if (sc->alc_tq == NULL) { device_printf(dev, "could not create taskqueue.\n"); ether_ifdetach(ifp); error = ENXIO; goto fail; } taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", device_get_nameunit(sc->alc_dev)); alc_config_msi(sc); if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) msic = ALC_MSIX_MESSAGES; else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) msic = ALC_MSI_MESSAGES; else msic = 1; for (i = 0; i < msic; i++) { error = bus_setup_intr(dev, sc->alc_irq[i], INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, &sc->alc_intrhand[i]); if (error != 0) break; } if (error != 0) { device_printf(dev, "could not set up interrupt handler.\n"); taskqueue_free(sc->alc_tq); sc->alc_tq = NULL; ether_ifdetach(ifp); goto fail; } /* Attach driver debugnet methods. */ DEBUGNET_SET(ifp, alc); fail: if (error != 0) alc_detach(dev); return (error); } static int alc_detach(device_t dev) { struct alc_softc *sc; - struct ifnet *ifp; + if_t ifp; int i, msic; sc = device_get_softc(dev); ifp = sc->alc_ifp; if (device_is_attached(dev)) { ether_ifdetach(ifp); ALC_LOCK(sc); alc_stop(sc); ALC_UNLOCK(sc); callout_drain(&sc->alc_tick_ch); taskqueue_drain(sc->alc_tq, &sc->alc_int_task); } if (sc->alc_tq != NULL) { taskqueue_drain(sc->alc_tq, &sc->alc_int_task); taskqueue_free(sc->alc_tq); sc->alc_tq = NULL; } if (sc->alc_miibus != NULL) { device_delete_child(dev, sc->alc_miibus); sc->alc_miibus = NULL; } bus_generic_detach(dev); alc_dma_free(sc); if (ifp != NULL) { if_free(ifp); sc->alc_ifp = NULL; } if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) msic = ALC_MSIX_MESSAGES; else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) msic = ALC_MSI_MESSAGES; else msic = 1; for (i = 0; i < msic; i++) { if (sc->alc_intrhand[i] != NULL) { bus_teardown_intr(dev, sc->alc_irq[i], sc->alc_intrhand[i]); sc->alc_intrhand[i] = NULL; } } if (sc->alc_res[0] != NULL) alc_phy_down(sc); bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) pci_release_msi(dev); bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); mtx_destroy(&sc->alc_mtx); return (0); } #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) static void alc_sysctl_node(struct alc_softc *sc) { struct sysctl_ctx_list *ctx; struct sysctl_oid_list *child, *parent; struct sysctl_oid *tree; struct alc_hw_stats *stats; int error; stats = &sc->alc_stats; ctx = device_get_sysctl_ctx(sc->alc_dev); child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_rx_mod, 0, sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_tx_mod, 0, sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); /* Pull in device tunables. */ sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; error = resource_int_value(device_get_name(sc->alc_dev), device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); if (error == 0) { if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { device_printf(sc->alc_dev, "int_rx_mod value out of " "range; using default: %d\n", ALC_IM_RX_TIMER_DEFAULT); sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; } } sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; error = resource_int_value(device_get_name(sc->alc_dev), device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); if (error == 0) { if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { device_printf(sc->alc_dev, "int_tx_mod value out of " "range; using default: %d\n", ALC_IM_TX_TIMER_DEFAULT); sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; } } SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_process_limit, 0, sysctl_hw_alc_proc_limit, "I", "max number of Rx events to process"); /* Pull in device tunables. */ sc->alc_process_limit = ALC_PROC_DEFAULT; error = resource_int_value(device_get_name(sc->alc_dev), device_get_unit(sc->alc_dev), "process_limit", &sc->alc_process_limit); if (error == 0) { if (sc->alc_process_limit < ALC_PROC_MIN || sc->alc_process_limit > ALC_PROC_MAX) { device_printf(sc->alc_dev, "process_limit value out of range; " "using default: %d\n", ALC_PROC_DEFAULT); sc->alc_process_limit = ALC_PROC_DEFAULT; } } tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ALC statistics"); parent = SYSCTL_CHILDREN(tree); /* Rx statistics. */ tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); child = SYSCTL_CHILDREN(tree); ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", &stats->rx_frames, "Good frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", &stats->rx_bcast_frames, "Good broadcast frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", &stats->rx_mcast_frames, "Good multicast frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", &stats->rx_pause_frames, "Pause control frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", &stats->rx_control_frames, "Control frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", &stats->rx_crcerrs, "CRC errors"); ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", &stats->rx_lenerrs, "Frames with length mismatched"); ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", &stats->rx_bytes, "Good octets"); ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", &stats->rx_bcast_bytes, "Good broadcast octets"); ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", &stats->rx_mcast_bytes, "Good multicast octets"); ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", &stats->rx_runts, "Too short frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", &stats->rx_fragments, "Fragmented frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", &stats->rx_pkts_64, "64 bytes frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", &stats->rx_pkts_65_127, "65 to 127 bytes frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", &stats->rx_pkts_128_255, "128 to 255 bytes frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", &stats->rx_pkts_256_511, "256 to 511 bytes frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", &stats->rx_pkts_1519_max, "1519 to max frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", &stats->rx_fifo_oflows, "FIFO overflows"); ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", &stats->rx_rrs_errs, "Return status write-back errors"); ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", &stats->rx_alignerrs, "Alignment errors"); ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", &stats->rx_pkts_filtered, "Frames dropped due to address filtering"); /* Tx statistics. */ tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); child = SYSCTL_CHILDREN(tree); ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", &stats->tx_frames, "Good frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", &stats->tx_bcast_frames, "Good broadcast frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", &stats->tx_mcast_frames, "Good multicast frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", &stats->tx_pause_frames, "Pause control frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", &stats->tx_control_frames, "Control frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", &stats->tx_excess_defer, "Frames with excessive derferrals"); ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", &stats->tx_excess_defer, "Frames with derferrals"); ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", &stats->tx_bytes, "Good octets"); ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", &stats->tx_bcast_bytes, "Good broadcast octets"); ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", &stats->tx_mcast_bytes, "Good multicast octets"); ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", &stats->tx_pkts_64, "64 bytes frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", &stats->tx_pkts_65_127, "65 to 127 bytes frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", &stats->tx_pkts_128_255, "128 to 255 bytes frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", &stats->tx_pkts_256_511, "256 to 511 bytes frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", &stats->tx_pkts_1519_max, "1519 to max frames"); ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", &stats->tx_single_colls, "Single collisions"); ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", &stats->tx_multi_colls, "Multiple collisions"); ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", &stats->tx_late_colls, "Late collisions"); ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", &stats->tx_excess_colls, "Excessive collisions"); ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", &stats->tx_underrun, "FIFO underruns"); ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", &stats->tx_desc_underrun, "Descriptor write-back errors"); ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", &stats->tx_lenerrs, "Frames with length mismatched"); ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); } #undef ALC_SYSCTL_STAT_ADD32 #undef ALC_SYSCTL_STAT_ADD64 struct alc_dmamap_arg { bus_addr_t alc_busaddr; }; static void alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) { struct alc_dmamap_arg *ctx; if (error != 0) return; KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); ctx = (struct alc_dmamap_arg *)arg; ctx->alc_busaddr = segs[0].ds_addr; } /* * Normal and high Tx descriptors shares single Tx high address. * Four Rx descriptor/return rings and CMB shares the same Rx * high address. */ static int alc_check_boundary(struct alc_softc *sc) { bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; /* 4GB boundary crossing is not allowed. */ if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || (ALC_ADDR_HI(rr_ring_end) != ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || (ALC_ADDR_HI(cmb_end) != ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || (ALC_ADDR_HI(tx_ring_end) != ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) return (EFBIG); /* * Make sure Rx return descriptor/Rx descriptor/CMB use * the same high address. */ if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) return (EFBIG); return (0); } static int alc_dma_alloc(struct alc_softc *sc) { struct alc_txdesc *txd; struct alc_rxdesc *rxd; bus_addr_t lowaddr; struct alc_dmamap_arg ctx; int error, i; lowaddr = BUS_SPACE_MAXADDR; if (sc->alc_flags & ALC_FLAG_MT) lowaddr = BUS_SPACE_MAXSIZE_32BIT; again: /* Create parent DMA tag. */ error = bus_dma_tag_create( bus_get_dma_tag(sc->alc_dev), /* parent */ 1, 0, /* alignment, boundary */ lowaddr, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 0, /* nsegments */ BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->alc_cdata.alc_parent_tag); if (error != 0) { device_printf(sc->alc_dev, "could not create parent DMA tag.\n"); goto fail; } /* Create DMA tag for Tx descriptor ring. */ error = bus_dma_tag_create( sc->alc_cdata.alc_parent_tag, /* parent */ ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ ALC_TX_RING_SZ, /* maxsize */ 1, /* nsegments */ ALC_TX_RING_SZ, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->alc_cdata.alc_tx_ring_tag); if (error != 0) { device_printf(sc->alc_dev, "could not create Tx ring DMA tag.\n"); goto fail; } /* Create DMA tag for Rx free descriptor ring. */ error = bus_dma_tag_create( sc->alc_cdata.alc_parent_tag, /* parent */ ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ ALC_RX_RING_SZ, /* maxsize */ 1, /* nsegments */ ALC_RX_RING_SZ, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->alc_cdata.alc_rx_ring_tag); if (error != 0) { device_printf(sc->alc_dev, "could not create Rx ring DMA tag.\n"); goto fail; } /* Create DMA tag for Rx return descriptor ring. */ error = bus_dma_tag_create( sc->alc_cdata.alc_parent_tag, /* parent */ ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ ALC_RR_RING_SZ, /* maxsize */ 1, /* nsegments */ ALC_RR_RING_SZ, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->alc_cdata.alc_rr_ring_tag); if (error != 0) { device_printf(sc->alc_dev, "could not create Rx return ring DMA tag.\n"); goto fail; } /* Create DMA tag for coalescing message block. */ error = bus_dma_tag_create( sc->alc_cdata.alc_parent_tag, /* parent */ ALC_CMB_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ ALC_CMB_SZ, /* maxsize */ 1, /* nsegments */ ALC_CMB_SZ, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->alc_cdata.alc_cmb_tag); if (error != 0) { device_printf(sc->alc_dev, "could not create CMB DMA tag.\n"); goto fail; } /* Create DMA tag for status message block. */ error = bus_dma_tag_create( sc->alc_cdata.alc_parent_tag, /* parent */ ALC_SMB_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ ALC_SMB_SZ, /* maxsize */ 1, /* nsegments */ ALC_SMB_SZ, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->alc_cdata.alc_smb_tag); if (error != 0) { device_printf(sc->alc_dev, "could not create SMB DMA tag.\n"); goto fail; } /* Allocate DMA'able memory and load the DMA map for Tx ring. */ error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, (void **)&sc->alc_rdata.alc_tx_ring, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->alc_cdata.alc_tx_ring_map); if (error != 0) { device_printf(sc->alc_dev, "could not allocate DMA'able memory for Tx ring.\n"); goto fail; } ctx.alc_busaddr = 0; error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); if (error != 0 || ctx.alc_busaddr == 0) { device_printf(sc->alc_dev, "could not load DMA'able memory for Tx ring.\n"); goto fail; } sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; /* Allocate DMA'able memory and load the DMA map for Rx ring. */ error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, (void **)&sc->alc_rdata.alc_rx_ring, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->alc_cdata.alc_rx_ring_map); if (error != 0) { device_printf(sc->alc_dev, "could not allocate DMA'able memory for Rx ring.\n"); goto fail; } ctx.alc_busaddr = 0; error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); if (error != 0 || ctx.alc_busaddr == 0) { device_printf(sc->alc_dev, "could not load DMA'able memory for Rx ring.\n"); goto fail; } sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, (void **)&sc->alc_rdata.alc_rr_ring, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->alc_cdata.alc_rr_ring_map); if (error != 0) { device_printf(sc->alc_dev, "could not allocate DMA'able memory for Rx return ring.\n"); goto fail; } ctx.alc_busaddr = 0; error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); if (error != 0 || ctx.alc_busaddr == 0) { device_printf(sc->alc_dev, "could not load DMA'able memory for Tx ring.\n"); goto fail; } sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; /* Allocate DMA'able memory and load the DMA map for CMB. */ error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, (void **)&sc->alc_rdata.alc_cmb, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->alc_cdata.alc_cmb_map); if (error != 0) { device_printf(sc->alc_dev, "could not allocate DMA'able memory for CMB.\n"); goto fail; } ctx.alc_busaddr = 0; error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); if (error != 0 || ctx.alc_busaddr == 0) { device_printf(sc->alc_dev, "could not load DMA'able memory for CMB.\n"); goto fail; } sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; /* Allocate DMA'able memory and load the DMA map for SMB. */ error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, (void **)&sc->alc_rdata.alc_smb, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->alc_cdata.alc_smb_map); if (error != 0) { device_printf(sc->alc_dev, "could not allocate DMA'able memory for SMB.\n"); goto fail; } ctx.alc_busaddr = 0; error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); if (error != 0 || ctx.alc_busaddr == 0) { device_printf(sc->alc_dev, "could not load DMA'able memory for CMB.\n"); goto fail; } sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; /* Make sure we've not crossed 4GB boundary. */ if (lowaddr != BUS_SPACE_MAXADDR_32BIT && (error = alc_check_boundary(sc)) != 0) { device_printf(sc->alc_dev, "4GB boundary crossed, " "switching to 32bit DMA addressing mode.\n"); alc_dma_free(sc); /* * Limit max allowable DMA address space to 32bit * and try again. */ lowaddr = BUS_SPACE_MAXADDR_32BIT; goto again; } /* * Create Tx buffer parent tag. * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers * so it needs separate parent DMA tag as parent DMA address * space could be restricted to be within 32bit address space * by 4GB boundary crossing. */ error = bus_dma_tag_create( bus_get_dma_tag(sc->alc_dev), /* parent */ 1, 0, /* alignment, boundary */ lowaddr, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 0, /* nsegments */ BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->alc_cdata.alc_buffer_tag); if (error != 0) { device_printf(sc->alc_dev, "could not create parent buffer DMA tag.\n"); goto fail; } /* Create DMA tag for Tx buffers. */ error = bus_dma_tag_create( sc->alc_cdata.alc_buffer_tag, /* parent */ 1, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ ALC_TSO_MAXSIZE, /* maxsize */ ALC_MAXTXSEGS, /* nsegments */ ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->alc_cdata.alc_tx_tag); if (error != 0) { device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); goto fail; } /* Create DMA tag for Rx buffers. */ error = bus_dma_tag_create( sc->alc_cdata.alc_buffer_tag, /* parent */ ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ MCLBYTES, /* maxsize */ 1, /* nsegments */ MCLBYTES, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->alc_cdata.alc_rx_tag); if (error != 0) { device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); goto fail; } /* Create DMA maps for Tx buffers. */ for (i = 0; i < ALC_TX_RING_CNT; i++) { txd = &sc->alc_cdata.alc_txdesc[i]; txd->tx_m = NULL; txd->tx_dmamap = NULL; error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, &txd->tx_dmamap); if (error != 0) { device_printf(sc->alc_dev, "could not create Tx dmamap.\n"); goto fail; } } /* Create DMA maps for Rx buffers. */ if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, &sc->alc_cdata.alc_rx_sparemap)) != 0) { device_printf(sc->alc_dev, "could not create spare Rx dmamap.\n"); goto fail; } for (i = 0; i < ALC_RX_RING_CNT; i++) { rxd = &sc->alc_cdata.alc_rxdesc[i]; rxd->rx_m = NULL; rxd->rx_dmamap = NULL; error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, &rxd->rx_dmamap); if (error != 0) { device_printf(sc->alc_dev, "could not create Rx dmamap.\n"); goto fail; } } fail: return (error); } static void alc_dma_free(struct alc_softc *sc) { struct alc_txdesc *txd; struct alc_rxdesc *rxd; int i; /* Tx buffers. */ if (sc->alc_cdata.alc_tx_tag != NULL) { for (i = 0; i < ALC_TX_RING_CNT; i++) { txd = &sc->alc_cdata.alc_txdesc[i]; if (txd->tx_dmamap != NULL) { bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, txd->tx_dmamap); txd->tx_dmamap = NULL; } } bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); sc->alc_cdata.alc_tx_tag = NULL; } /* Rx buffers */ if (sc->alc_cdata.alc_rx_tag != NULL) { for (i = 0; i < ALC_RX_RING_CNT; i++) { rxd = &sc->alc_cdata.alc_rxdesc[i]; if (rxd->rx_dmamap != NULL) { bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); rxd->rx_dmamap = NULL; } } if (sc->alc_cdata.alc_rx_sparemap != NULL) { bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, sc->alc_cdata.alc_rx_sparemap); sc->alc_cdata.alc_rx_sparemap = NULL; } bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); sc->alc_cdata.alc_rx_tag = NULL; } /* Tx descriptor ring. */ if (sc->alc_cdata.alc_tx_ring_tag != NULL) { if (sc->alc_rdata.alc_tx_ring_paddr != 0) bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, sc->alc_cdata.alc_tx_ring_map); if (sc->alc_rdata.alc_tx_ring != NULL) bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, sc->alc_rdata.alc_tx_ring, sc->alc_cdata.alc_tx_ring_map); sc->alc_rdata.alc_tx_ring_paddr = 0; sc->alc_rdata.alc_tx_ring = NULL; bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); sc->alc_cdata.alc_tx_ring_tag = NULL; } /* Rx ring. */ if (sc->alc_cdata.alc_rx_ring_tag != NULL) { if (sc->alc_rdata.alc_rx_ring_paddr != 0) bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, sc->alc_cdata.alc_rx_ring_map); if (sc->alc_rdata.alc_rx_ring != NULL) bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, sc->alc_rdata.alc_rx_ring, sc->alc_cdata.alc_rx_ring_map); sc->alc_rdata.alc_rx_ring_paddr = 0; sc->alc_rdata.alc_rx_ring = NULL; bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); sc->alc_cdata.alc_rx_ring_tag = NULL; } /* Rx return ring. */ if (sc->alc_cdata.alc_rr_ring_tag != NULL) { if (sc->alc_rdata.alc_rr_ring_paddr != 0) bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, sc->alc_cdata.alc_rr_ring_map); if (sc->alc_rdata.alc_rr_ring != NULL) bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, sc->alc_rdata.alc_rr_ring, sc->alc_cdata.alc_rr_ring_map); sc->alc_rdata.alc_rr_ring_paddr = 0; sc->alc_rdata.alc_rr_ring = NULL; bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); sc->alc_cdata.alc_rr_ring_tag = NULL; } /* CMB block */ if (sc->alc_cdata.alc_cmb_tag != NULL) { if (sc->alc_rdata.alc_cmb_paddr != 0) bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map); if (sc->alc_rdata.alc_cmb != NULL) bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, sc->alc_rdata.alc_cmb, sc->alc_cdata.alc_cmb_map); sc->alc_rdata.alc_cmb_paddr = 0; sc->alc_rdata.alc_cmb = NULL; bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); sc->alc_cdata.alc_cmb_tag = NULL; } /* SMB block */ if (sc->alc_cdata.alc_smb_tag != NULL) { if (sc->alc_rdata.alc_smb_paddr != 0) bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map); if (sc->alc_rdata.alc_smb != NULL) bus_dmamem_free(sc->alc_cdata.alc_smb_tag, sc->alc_rdata.alc_smb, sc->alc_cdata.alc_smb_map); sc->alc_rdata.alc_smb_paddr = 0; sc->alc_rdata.alc_smb = NULL; bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); sc->alc_cdata.alc_smb_tag = NULL; } if (sc->alc_cdata.alc_buffer_tag != NULL) { bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); sc->alc_cdata.alc_buffer_tag = NULL; } if (sc->alc_cdata.alc_parent_tag != NULL) { bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); sc->alc_cdata.alc_parent_tag = NULL; } } static int alc_shutdown(device_t dev) { return (alc_suspend(dev)); } /* * Note, this driver resets the link speed to 10/100Mbps by * restarting auto-negotiation in suspend/shutdown phase but we * don't know whether that auto-negotiation would succeed or not * as driver has no control after powering off/suspend operation. * If the renegotiation fail WOL may not work. Running at 1Gbps * will draw more power than 375mA at 3.3V which is specified in * PCI specification and that would result in complete * shutdowning power to ethernet controller. * * TODO * Save current negotiated media speed/duplex/flow-control to * softc and restore the same link again after resuming. PHY * handling such as power down/resetting to 100Mbps may be better * handled in suspend method in phy driver. */ static void alc_setlinkspeed(struct alc_softc *sc) { struct mii_data *mii; int aneg, i; mii = device_get_softc(sc->alc_miibus); mii_pollstat(mii); aneg = 0; if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { switch IFM_SUBTYPE(mii->mii_media_active) { case IFM_10_T: case IFM_100_TX: return; case IFM_1000_T: aneg++; break; default: break; } } alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); DELAY(1000); if (aneg != 0) { /* * Poll link state until alc(4) get a 10/100Mbps link. */ for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { mii_pollstat(mii); if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { switch (IFM_SUBTYPE( mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: alc_mac_config(sc); return; default: break; } } ALC_UNLOCK(sc); pause("alclnk", hz); ALC_LOCK(sc); } if (i == MII_ANEGTICKS_GIGE) device_printf(sc->alc_dev, "establishing a link failed, WOL may not work!"); } /* * No link, force MAC to have 100Mbps, full-duplex link. * This is the last resort and may/may not work. */ mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; alc_mac_config(sc); } static void alc_setwol(struct alc_softc *sc) { if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) alc_setwol_816x(sc); else alc_setwol_813x(sc); } static void alc_setwol_813x(struct alc_softc *sc) { - struct ifnet *ifp; + if_t ifp; uint32_t reg, pmcs; uint16_t pmstat; ALC_LOCK_ASSERT(sc); alc_disable_l0s_l1(sc); ifp = sc->alc_ifp; if ((sc->alc_flags & ALC_FLAG_PM) == 0) { /* Disable WOL. */ CSR_WRITE_4(sc, ALC_WOL_CFG, 0); reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); reg |= PCIE_PHYMISC_FORCE_RCV_DET; CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); /* Force PHY power down. */ alc_phy_down(sc); CSR_WRITE_4(sc, ALC_MASTER_CFG, CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); return; } - if ((ifp->if_capenable & IFCAP_WOL) != 0) { + if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) alc_setlinkspeed(sc); CSR_WRITE_4(sc, ALC_MASTER_CFG, CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); } pmcs = 0; - if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) + if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); reg = CSR_READ_4(sc, ALC_MAC_CFG); reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | MAC_CFG_BCAST); - if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) + if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; - if ((ifp->if_capenable & IFCAP_WOL) != 0) + if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) reg |= MAC_CFG_RX_ENB; CSR_WRITE_4(sc, ALC_MAC_CFG, reg); reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); reg |= PCIE_PHYMISC_FORCE_RCV_DET; CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); - if ((ifp->if_capenable & IFCAP_WOL) == 0) { + if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { /* WOL disabled, PHY power down. */ alc_phy_down(sc); CSR_WRITE_4(sc, ALC_MASTER_CFG, CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); } /* Request PME. */ pmstat = pci_read_config(sc->alc_dev, sc->alc_pmcap + PCIR_POWER_STATUS, 2); pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); - if ((ifp->if_capenable & IFCAP_WOL) != 0) + if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; pci_write_config(sc->alc_dev, sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); } static void alc_setwol_816x(struct alc_softc *sc) { - struct ifnet *ifp; + if_t ifp; uint32_t gphy, mac, master, pmcs, reg; uint16_t pmstat; ALC_LOCK_ASSERT(sc); ifp = sc->alc_ifp; master = CSR_READ_4(sc, ALC_MASTER_CFG); master &= ~MASTER_CLK_SEL_DIS; gphy = CSR_READ_4(sc, ALC_GPHY_CFG); gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; if ((sc->alc_flags & ALC_FLAG_PM) == 0) { CSR_WRITE_4(sc, ALC_WOL_CFG, 0); gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; mac = CSR_READ_4(sc, ALC_MAC_CFG); } else { - if ((ifp->if_capenable & IFCAP_WOL) != 0) { + if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { gphy |= GPHY_CFG_EXT_RESET; if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) alc_setlinkspeed(sc); } pmcs = 0; - if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) + if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); mac = CSR_READ_4(sc, ALC_MAC_CFG); mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | MAC_CFG_BCAST); - if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) + if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; - if ((ifp->if_capenable & IFCAP_WOL) != 0) + if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) mac |= MAC_CFG_RX_ENB; alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, ANEG_S3DIG10_SL); } /* Enable OSC. */ reg = CSR_READ_4(sc, ALC_MISC); reg &= ~MISC_INTNLOSC_OPEN; CSR_WRITE_4(sc, ALC_MISC, reg); reg |= MISC_INTNLOSC_OPEN; CSR_WRITE_4(sc, ALC_MISC, reg); CSR_WRITE_4(sc, ALC_MASTER_CFG, master); CSR_WRITE_4(sc, ALC_MAC_CFG, mac); CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); reg |= PDLL_TRNS1_D3PLLOFF_ENB; CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); if ((sc->alc_flags & ALC_FLAG_PM) != 0) { /* Request PME. */ pmstat = pci_read_config(sc->alc_dev, sc->alc_pmcap + PCIR_POWER_STATUS, 2); pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); - if ((ifp->if_capenable & IFCAP_WOL) != 0) + if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; pci_write_config(sc->alc_dev, sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); } } static int alc_suspend(device_t dev) { struct alc_softc *sc; sc = device_get_softc(dev); ALC_LOCK(sc); alc_stop(sc); alc_setwol(sc); ALC_UNLOCK(sc); return (0); } static int alc_resume(device_t dev) { struct alc_softc *sc; - struct ifnet *ifp; + if_t ifp; uint16_t pmstat; sc = device_get_softc(dev); ALC_LOCK(sc); if ((sc->alc_flags & ALC_FLAG_PM) != 0) { /* Disable PME and clear PME status. */ pmstat = pci_read_config(sc->alc_dev, sc->alc_pmcap + PCIR_POWER_STATUS, 2); if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { pmstat &= ~PCIM_PSTAT_PMEENABLE; pci_write_config(sc->alc_dev, sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); } } /* Reset PHY. */ alc_phy_reset(sc); ifp = sc->alc_ifp; - if ((ifp->if_flags & IFF_UP) != 0) { - ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + if ((if_getflags(ifp) & IFF_UP) != 0) { + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); alc_init_locked(sc); } ALC_UNLOCK(sc); return (0); } static int alc_encap(struct alc_softc *sc, struct mbuf **m_head) { struct alc_txdesc *txd, *txd_last; struct tx_desc *desc; struct mbuf *m; struct ip *ip; struct tcphdr *tcp; bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; bus_dmamap_t map; uint32_t cflags, hdrlen, ip_off, poff, vtag; int error, idx, nsegs, prod; ALC_LOCK_ASSERT(sc); M_ASSERTPKTHDR((*m_head)); m = *m_head; ip = NULL; tcp = NULL; ip_off = poff = 0; if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { /* * AR81[3567]x requires offset of TCP/UDP header in its * Tx descriptor to perform Tx checksum offloading. TSO * also requires TCP header offset and modification of * IP/TCP header. This kind of operation takes many CPU * cycles on FreeBSD so fast host CPU is required to get * smooth TSO performance. */ struct ether_header *eh; if (M_WRITABLE(m) == 0) { /* Get a writable copy. */ m = m_dup(*m_head, M_NOWAIT); /* Release original mbufs. */ m_freem(*m_head); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } *m_head = m; } ip_off = sizeof(struct ether_header); m = m_pullup(m, ip_off); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } eh = mtod(m, struct ether_header *); /* * Check if hardware VLAN insertion is off. * Additional check for LLC/SNAP frame? */ if (eh->ether_type == htons(ETHERTYPE_VLAN)) { ip_off = sizeof(struct ether_vlan_header); m = m_pullup(m, ip_off); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } } m = m_pullup(m, ip_off + sizeof(struct ip)); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } ip = (struct ip *)(mtod(m, char *) + ip_off); poff = ip_off + (ip->ip_hl << 2); if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { m = m_pullup(m, poff + sizeof(struct tcphdr)); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } tcp = (struct tcphdr *)(mtod(m, char *) + poff); m = m_pullup(m, poff + (tcp->th_off << 2)); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } /* * Due to strict adherence of Microsoft NDIS * Large Send specification, hardware expects * a pseudo TCP checksum inserted by upper * stack. Unfortunately the pseudo TCP * checksum that NDIS refers to does not include * TCP payload length so driver should recompute * the pseudo checksum here. Hopefully this * wouldn't be much burden on modern CPUs. * * Reset IP checksum and recompute TCP pseudo * checksum as NDIS specification said. */ ip = (struct ip *)(mtod(m, char *) + ip_off); tcp = (struct tcphdr *)(mtod(m, char *) + poff); ip->ip_sum = 0; tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, htons(IPPROTO_TCP)); } *m_head = m; } prod = sc->alc_cdata.alc_tx_prod; txd = &sc->alc_cdata.alc_txdesc[prod]; txd_last = txd; map = txd->tx_dmamap; error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, *m_head, txsegs, &nsegs, 0); if (error == EFBIG) { m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); if (m == NULL) { m_freem(*m_head); *m_head = NULL; return (ENOMEM); } *m_head = m; error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, *m_head, txsegs, &nsegs, 0); if (error != 0) { m_freem(*m_head); *m_head = NULL; return (error); } } else if (error != 0) return (error); if (nsegs == 0) { m_freem(*m_head); *m_head = NULL; return (EIO); } /* Check descriptor overrun. */ if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); return (ENOBUFS); } bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); m = *m_head; cflags = TD_ETHERNET; vtag = 0; desc = NULL; idx = 0; /* Configure VLAN hardware tag insertion. */ if ((m->m_flags & M_VLANTAG) != 0) { vtag = htons(m->m_pkthdr.ether_vtag); vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; cflags |= TD_INS_VLAN_TAG; } if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { /* Request TSO and set MSS. */ cflags |= TD_TSO | TD_TSO_DESCV1; cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & TD_MSS_MASK; /* Set TCP header offset. */ cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & TD_TCPHDR_OFFSET_MASK; /* * AR81[3567]x requires the first buffer should * only hold IP/TCP header data. Payload should * be handled in other descriptors. */ hdrlen = poff + (tcp->th_off << 2); desc = &sc->alc_rdata.alc_tx_ring[prod]; desc->len = htole32(TX_BYTES(hdrlen | vtag)); desc->flags = htole32(cflags); desc->addr = htole64(txsegs[0].ds_addr); sc->alc_cdata.alc_tx_cnt++; ALC_DESC_INC(prod, ALC_TX_RING_CNT); if (m->m_len - hdrlen > 0) { /* Handle remaining payload of the first fragment. */ desc = &sc->alc_rdata.alc_tx_ring[prod]; desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | vtag)); desc->flags = htole32(cflags); desc->addr = htole64(txsegs[0].ds_addr + hdrlen); sc->alc_cdata.alc_tx_cnt++; ALC_DESC_INC(prod, ALC_TX_RING_CNT); } /* Handle remaining fragments. */ idx = 1; } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { /* Configure Tx checksum offload. */ #ifdef ALC_USE_CUSTOM_CSUM cflags |= TD_CUSTOM_CSUM; /* Set checksum start offset. */ cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & TD_PLOAD_OFFSET_MASK; /* Set checksum insertion position of TCP/UDP. */ cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; #else if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) cflags |= TD_IPCSUM; if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) cflags |= TD_TCPCSUM; if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) cflags |= TD_UDPCSUM; /* Set TCP/UDP header offset. */ cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & TD_L4HDR_OFFSET_MASK; #endif } for (; idx < nsegs; idx++) { desc = &sc->alc_rdata.alc_tx_ring[prod]; desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); desc->flags = htole32(cflags); desc->addr = htole64(txsegs[idx].ds_addr); sc->alc_cdata.alc_tx_cnt++; ALC_DESC_INC(prod, ALC_TX_RING_CNT); } /* Update producer index. */ sc->alc_cdata.alc_tx_prod = prod; /* Finally set EOP on the last descriptor. */ prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; desc = &sc->alc_rdata.alc_tx_ring[prod]; desc->flags |= htole32(TD_EOP); /* Swap dmamap of the first and the last. */ txd = &sc->alc_cdata.alc_txdesc[prod]; map = txd_last->tx_dmamap; txd_last->tx_dmamap = txd->tx_dmamap; txd->tx_dmamap = map; txd->tx_m = m; return (0); } static void -alc_start(struct ifnet *ifp) +alc_start(if_t ifp) { struct alc_softc *sc; - sc = ifp->if_softc; + sc = if_getsoftc(ifp); ALC_LOCK(sc); alc_start_locked(ifp); ALC_UNLOCK(sc); } static void -alc_start_locked(struct ifnet *ifp) +alc_start_locked(if_t ifp) { struct alc_softc *sc; struct mbuf *m_head; int enq; - sc = ifp->if_softc; + sc = if_getsoftc(ifp); ALC_LOCK_ASSERT(sc); /* Reclaim transmitted frames. */ if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) alc_txeof(sc); - if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != + if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) return; - for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { - IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); + for (enq = 0; !if_sendq_empty(ifp); ) { + m_head = if_dequeue(ifp); if (m_head == NULL) break; /* * Pack the data into the transmit ring. If we * don't have room, set the OACTIVE flag and wait * for the NIC to drain the ring. */ if (alc_encap(sc, &m_head)) { if (m_head == NULL) break; - IFQ_DRV_PREPEND(&ifp->if_snd, m_head); - ifp->if_drv_flags |= IFF_DRV_OACTIVE; + if_sendq_prepend(ifp, m_head); + if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); break; } enq++; /* * If there's a BPF listener, bounce a copy of this frame * to him. */ ETHER_BPF_MTAP(ifp, m_head); } if (enq > 0) alc_start_tx(sc); } static void alc_start_tx(struct alc_softc *sc) { /* Sync descriptors. */ bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); /* Kick. Assume we're using normal Tx priority queue. */ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, (uint16_t)sc->alc_cdata.alc_tx_prod); else CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, (sc->alc_cdata.alc_tx_prod << MBOX_TD_PROD_LO_IDX_SHIFT) & MBOX_TD_PROD_LO_IDX_MASK); /* Set a timeout in case the chip goes out to lunch. */ sc->alc_watchdog_timer = ALC_TX_TIMEOUT; } static void alc_watchdog(struct alc_softc *sc) { - struct ifnet *ifp; + if_t ifp; ALC_LOCK_ASSERT(sc); if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) return; ifp = sc->alc_ifp; if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); - ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); alc_init_locked(sc); return; } if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); - ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); alc_init_locked(sc); - if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + if (!if_sendq_empty(ifp)) alc_start_locked(ifp); } static int -alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) +alc_ioctl(if_t ifp, u_long cmd, caddr_t data) { struct alc_softc *sc; struct ifreq *ifr; struct mii_data *mii; int error, mask; - sc = ifp->if_softc; + sc = if_getsoftc(ifp); ifr = (struct ifreq *)data; error = 0; switch (cmd) { case SIOCSIFMTU: if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > (sc->alc_ident->max_framelen - sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && ifr->ifr_mtu > ETHERMTU)) error = EINVAL; - else if (ifp->if_mtu != ifr->ifr_mtu) { + else if (if_getmtu(ifp) != ifr->ifr_mtu) { ALC_LOCK(sc); - ifp->if_mtu = ifr->ifr_mtu; + if_setmtu(ifp, ifr->ifr_mtu); /* AR81[3567]x has 13 bits MSS field. */ - if (ifp->if_mtu > ALC_TSO_MTU && - (ifp->if_capenable & IFCAP_TSO4) != 0) { - ifp->if_capenable &= ~IFCAP_TSO4; - ifp->if_hwassist &= ~CSUM_TSO; + if (if_getmtu(ifp) > ALC_TSO_MTU && + (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { + if_setcapenablebit(ifp, 0, IFCAP_TSO4); + if_sethwassistbits(ifp, 0, CSUM_TSO); VLAN_CAPABILITIES(ifp); } ALC_UNLOCK(sc); } break; case SIOCSIFFLAGS: ALC_LOCK(sc); - if ((ifp->if_flags & IFF_UP) != 0) { - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && - ((ifp->if_flags ^ sc->alc_if_flags) & + if ((if_getflags(ifp) & IFF_UP) != 0) { + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && + ((if_getflags(ifp) ^ sc->alc_if_flags) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) alc_rxfilter(sc); else alc_init_locked(sc); - } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) alc_stop(sc); - sc->alc_if_flags = ifp->if_flags; + sc->alc_if_flags = if_getflags(ifp); ALC_UNLOCK(sc); break; case SIOCADDMULTI: case SIOCDELMULTI: ALC_LOCK(sc); - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) alc_rxfilter(sc); ALC_UNLOCK(sc); break; case SIOCSIFMEDIA: case SIOCGIFMEDIA: mii = device_get_softc(sc->alc_miibus); error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); break; case SIOCSIFCAP: ALC_LOCK(sc); - mask = ifr->ifr_reqcap ^ ifp->if_capenable; + mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); if ((mask & IFCAP_TXCSUM) != 0 && - (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { - ifp->if_capenable ^= IFCAP_TXCSUM; - if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) - ifp->if_hwassist |= ALC_CSUM_FEATURES; + (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { + if_togglecapenable(ifp, IFCAP_TXCSUM); + if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) + if_sethwassistbits(ifp, ALC_CSUM_FEATURES, 0); else - ifp->if_hwassist &= ~ALC_CSUM_FEATURES; + if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES); } if ((mask & IFCAP_TSO4) != 0 && - (ifp->if_capabilities & IFCAP_TSO4) != 0) { - ifp->if_capenable ^= IFCAP_TSO4; - if ((ifp->if_capenable & IFCAP_TSO4) != 0) { + (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { + if_togglecapenable(ifp, IFCAP_TSO4); + if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) { /* AR81[3567]x has 13 bits MSS field. */ - if (ifp->if_mtu > ALC_TSO_MTU) { - ifp->if_capenable &= ~IFCAP_TSO4; - ifp->if_hwassist &= ~CSUM_TSO; + if (if_getmtu(ifp) > ALC_TSO_MTU) { + if_setcapenablebit(ifp, 0, IFCAP_TSO4); + if_sethwassistbits(ifp, 0, CSUM_TSO); } else - ifp->if_hwassist |= CSUM_TSO; + if_sethwassistbits(ifp, CSUM_TSO, 0); } else - ifp->if_hwassist &= ~CSUM_TSO; + if_sethwassistbits(ifp, 0, CSUM_TSO); } if ((mask & IFCAP_WOL_MCAST) != 0 && - (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) - ifp->if_capenable ^= IFCAP_WOL_MCAST; + (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) + if_togglecapenable(ifp, IFCAP_WOL_MCAST); if ((mask & IFCAP_WOL_MAGIC) != 0 && - (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) - ifp->if_capenable ^= IFCAP_WOL_MAGIC; + (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) + if_togglecapenable(ifp, IFCAP_WOL_MAGIC); if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && - (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { - ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; + (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { + if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); alc_rxvlan(sc); } if ((mask & IFCAP_VLAN_HWCSUM) != 0 && - (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) - ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; + (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) + if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); if ((mask & IFCAP_VLAN_HWTSO) != 0 && - (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) - ifp->if_capenable ^= IFCAP_VLAN_HWTSO; - if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) - ifp->if_capenable &= - ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); + (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) + if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); + if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) + if_setcapenablebit(ifp, 0, + IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); ALC_UNLOCK(sc); VLAN_CAPABILITIES(ifp); break; default: error = ether_ioctl(ifp, cmd, data); break; } return (error); } static void alc_mac_config(struct alc_softc *sc) { struct mii_data *mii; uint32_t reg; ALC_LOCK_ASSERT(sc); mii = device_get_softc(sc->alc_miibus); reg = CSR_READ_4(sc, ALC_MAC_CFG); reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | MAC_CFG_SPEED_MASK); if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; /* Reprogram MAC with resolved speed/duplex. */ switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: reg |= MAC_CFG_SPEED_10_100; break; case IFM_1000_T: reg |= MAC_CFG_SPEED_1000; break; } if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { reg |= MAC_CFG_FULL_DUPLEX; if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) reg |= MAC_CFG_TX_FC; if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) reg |= MAC_CFG_RX_FC; } CSR_WRITE_4(sc, ALC_MAC_CFG, reg); } static void alc_stats_clear(struct alc_softc *sc) { struct smb sb, *smb; uint32_t *reg; int i; if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); smb = sc->alc_rdata.alc_smb; /* Update done, clear. */ smb->updated = 0; bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); } else { for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { CSR_READ_4(sc, ALC_RX_MIB_BASE + i); i += sizeof(uint32_t); } /* Read Tx statistics. */ for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { CSR_READ_4(sc, ALC_TX_MIB_BASE + i); i += sizeof(uint32_t); } } } static void alc_stats_update(struct alc_softc *sc) { struct alc_hw_stats *stat; struct smb sb, *smb; - struct ifnet *ifp; + if_t ifp; uint32_t *reg; int i; ALC_LOCK_ASSERT(sc); ifp = sc->alc_ifp; stat = &sc->alc_stats; if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); smb = sc->alc_rdata.alc_smb; if (smb->updated == 0) return; } else { smb = &sb; /* Read Rx statistics. */ for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); i += sizeof(uint32_t); } /* Read Tx statistics. */ for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); i += sizeof(uint32_t); } } /* Rx stats. */ stat->rx_frames += smb->rx_frames; stat->rx_bcast_frames += smb->rx_bcast_frames; stat->rx_mcast_frames += smb->rx_mcast_frames; stat->rx_pause_frames += smb->rx_pause_frames; stat->rx_control_frames += smb->rx_control_frames; stat->rx_crcerrs += smb->rx_crcerrs; stat->rx_lenerrs += smb->rx_lenerrs; stat->rx_bytes += smb->rx_bytes; stat->rx_runts += smb->rx_runts; stat->rx_fragments += smb->rx_fragments; stat->rx_pkts_64 += smb->rx_pkts_64; stat->rx_pkts_65_127 += smb->rx_pkts_65_127; stat->rx_pkts_128_255 += smb->rx_pkts_128_255; stat->rx_pkts_256_511 += smb->rx_pkts_256_511; stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; stat->rx_pkts_truncated += smb->rx_pkts_truncated; stat->rx_fifo_oflows += smb->rx_fifo_oflows; stat->rx_rrs_errs += smb->rx_rrs_errs; stat->rx_alignerrs += smb->rx_alignerrs; stat->rx_bcast_bytes += smb->rx_bcast_bytes; stat->rx_mcast_bytes += smb->rx_mcast_bytes; stat->rx_pkts_filtered += smb->rx_pkts_filtered; /* Tx stats. */ stat->tx_frames += smb->tx_frames; stat->tx_bcast_frames += smb->tx_bcast_frames; stat->tx_mcast_frames += smb->tx_mcast_frames; stat->tx_pause_frames += smb->tx_pause_frames; stat->tx_excess_defer += smb->tx_excess_defer; stat->tx_control_frames += smb->tx_control_frames; stat->tx_deferred += smb->tx_deferred; stat->tx_bytes += smb->tx_bytes; stat->tx_pkts_64 += smb->tx_pkts_64; stat->tx_pkts_65_127 += smb->tx_pkts_65_127; stat->tx_pkts_128_255 += smb->tx_pkts_128_255; stat->tx_pkts_256_511 += smb->tx_pkts_256_511; stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; stat->tx_single_colls += smb->tx_single_colls; stat->tx_multi_colls += smb->tx_multi_colls; stat->tx_late_colls += smb->tx_late_colls; stat->tx_excess_colls += smb->tx_excess_colls; stat->tx_underrun += smb->tx_underrun; stat->tx_desc_underrun += smb->tx_desc_underrun; stat->tx_lenerrs += smb->tx_lenerrs; stat->tx_pkts_truncated += smb->tx_pkts_truncated; stat->tx_bcast_bytes += smb->tx_bcast_bytes; stat->tx_mcast_bytes += smb->tx_mcast_bytes; /* Update counters in ifnet. */ if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + smb->tx_multi_colls * 2 + smb->tx_late_colls + smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); if_inc_counter(ifp, IFCOUNTER_IERRORS, smb->rx_crcerrs + smb->rx_lenerrs + smb->rx_runts + smb->rx_pkts_truncated + smb->rx_fifo_oflows + smb->rx_rrs_errs + smb->rx_alignerrs); if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { /* Update done, clear. */ smb->updated = 0; bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); } } static int alc_intr(void *arg) { struct alc_softc *sc; uint32_t status; sc = (struct alc_softc *)arg; if (sc->alc_flags & ALC_FLAG_MT) { taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); return (FILTER_HANDLED); } status = CSR_READ_4(sc, ALC_INTR_STATUS); if ((status & ALC_INTRS) == 0) return (FILTER_STRAY); /* Disable interrupts. */ CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); return (FILTER_HANDLED); } static void alc_int_task(void *arg, int pending) { struct alc_softc *sc; - struct ifnet *ifp; + if_t ifp; uint32_t status; int more; sc = (struct alc_softc *)arg; ifp = sc->alc_ifp; status = CSR_READ_4(sc, ALC_INTR_STATUS); ALC_LOCK(sc); if (sc->alc_morework != 0) { sc->alc_morework = 0; status |= INTR_RX_PKT; } if ((status & ALC_INTRS) == 0) goto done; /* Acknowledge interrupts but still disable interrupts. */ CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); more = 0; - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { if ((status & INTR_RX_PKT) != 0) { more = alc_rxintr(sc, sc->alc_process_limit); if (more == EAGAIN) sc->alc_morework = 1; else if (more == EIO) { - ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); alc_init_locked(sc); ALC_UNLOCK(sc); return; } } if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | INTR_TXQ_TO_RST)) != 0) { if ((status & INTR_DMA_RD_TO_RST) != 0) device_printf(sc->alc_dev, "DMA read error! -- resetting\n"); if ((status & INTR_DMA_WR_TO_RST) != 0) device_printf(sc->alc_dev, "DMA write error! -- resetting\n"); if ((status & INTR_TXQ_TO_RST) != 0) device_printf(sc->alc_dev, "TxQ reset! -- resetting\n"); - ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); alc_init_locked(sc); ALC_UNLOCK(sc); return; } - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && - !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && + !if_sendq_empty(ifp)) alc_start_locked(ifp); } if (more == EAGAIN || (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { ALC_UNLOCK(sc); taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); return; } done: - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { /* Re-enable interrupts if we're running. */ if (sc->alc_flags & ALC_FLAG_MT) CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); else CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); } ALC_UNLOCK(sc); } static void alc_txeof(struct alc_softc *sc) { - struct ifnet *ifp; + if_t ifp; struct alc_txdesc *txd; uint32_t cons, prod; ALC_LOCK_ASSERT(sc); ifp = sc->alc_ifp; if (sc->alc_cdata.alc_tx_cnt == 0) return; bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); prod = sc->alc_rdata.alc_cmb->cons; } else { if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); else { prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); /* Assume we're using normal Tx priority queue. */ prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> MBOX_TD_CONS_LO_IDX_SHIFT; } } cons = sc->alc_cdata.alc_tx_cons; /* * Go through our Tx list and free mbufs for those * frames which have been transmitted. */ for (; cons != prod; ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { if (sc->alc_cdata.alc_tx_cnt <= 0) break; - ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); sc->alc_cdata.alc_tx_cnt--; txd = &sc->alc_cdata.alc_txdesc[cons]; if (txd->tx_m != NULL) { /* Reclaim transmitted mbufs. */ bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, txd->tx_dmamap); m_freem(txd->tx_m); txd->tx_m = NULL; } } if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); sc->alc_cdata.alc_tx_cons = cons; /* * Unarm watchdog timer only when there is no pending * frames in Tx queue. */ if (sc->alc_cdata.alc_tx_cnt == 0) sc->alc_watchdog_timer = 0; } static int alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) { struct mbuf *m; bus_dma_segment_t segs[1]; bus_dmamap_t map; int nsegs; m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; #ifndef __NO_STRICT_ALIGNMENT m_adj(m, sizeof(uint64_t)); #endif if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { m_freem(m); return (ENOBUFS); } KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); if (rxd->rx_m != NULL) { bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); } map = rxd->rx_dmamap; rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; sc->alc_cdata.alc_rx_sparemap = map; bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD); rxd->rx_m = m; rxd->rx_desc->addr = htole64(segs[0].ds_addr); return (0); } static int alc_rxintr(struct alc_softc *sc, int count) { - struct ifnet *ifp; + if_t ifp; struct rx_rdesc *rrd; uint32_t nsegs, status; int rr_cons, prog; bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, sc->alc_cdata.alc_rr_ring_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); rr_cons = sc->alc_cdata.alc_rr_cons; ifp = sc->alc_ifp; - for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { + for (prog = 0; (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0;) { if (count-- <= 0) break; rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; status = le32toh(rrd->status); if ((status & RRD_VALID) == 0) break; nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); if (nsegs == 0) { /* This should not happen! */ device_printf(sc->alc_dev, "unexpected segment count -- resetting\n"); return (EIO); } alc_rxeof(sc, rrd); /* Clear Rx return status. */ rrd->status = 0; ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); sc->alc_cdata.alc_rx_cons += nsegs; sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; prog += nsegs; } if (prog > 0) { /* Update the consumer index. */ sc->alc_cdata.alc_rr_cons = rr_cons; /* Sync Rx return descriptors. */ bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, sc->alc_cdata.alc_rr_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); /* * Sync updated Rx descriptors such that controller see * modified buffer addresses. */ bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); /* * Let controller know availability of new Rx buffers. * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors * it may be possible to update ALC_MBOX_RD0_PROD_IDX * only when Rx buffer pre-fetching is required. In * addition we already set ALC_RX_RD_FREE_THRESH to * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However * it still seems that pre-fetching needs more * experimentation. */ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, (uint16_t)sc->alc_cdata.alc_rx_cons); else CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); } return (count > 0 ? 0 : EAGAIN); } #ifndef __NO_STRICT_ALIGNMENT static struct mbuf * -alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) +alc_fixup_rx(if_t ifp, struct mbuf *m) { struct mbuf *n; int i; uint16_t *src, *dst; src = mtod(m, uint16_t *); dst = src - 3; if (m->m_next == NULL) { for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) *dst++ = *src++; m->m_data -= 6; return (m); } /* * Append a new mbuf to received mbuf chain and copy ethernet * header from the mbuf chain. This can save lots of CPU * cycles for jumbo frame. */ MGETHDR(n, M_NOWAIT, MT_DATA); if (n == NULL) { if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); m_freem(m); return (NULL); } bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); m->m_data += ETHER_HDR_LEN; m->m_len -= ETHER_HDR_LEN; n->m_len = ETHER_HDR_LEN; M_MOVE_PKTHDR(n, m); n->m_next = m; return (n); } #endif /* Receive a frame. */ static void alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) { struct alc_rxdesc *rxd; - struct ifnet *ifp; + if_t ifp; struct mbuf *mp, *m; uint32_t rdinfo, status, vtag; int count, nsegs, rx_cons; ifp = sc->alc_ifp; status = le32toh(rrd->status); rdinfo = le32toh(rrd->rdinfo); rx_cons = RRD_RD_IDX(rdinfo); nsegs = RRD_RD_CNT(rdinfo); sc->alc_cdata.alc_rxlen = RRD_BYTES(status); if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { /* * We want to pass the following frames to upper * layer regardless of error status of Rx return * ring. * * o IP/TCP/UDP checksum is bad. * o frame length and protocol specific length * does not match. * * Force network stack compute checksum for * errored frames. */ status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) return; } for (count = 0; count < nsegs; count++, ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; mp = rxd->rx_m; /* Add a new receive buffer to the ring. */ if (alc_newbuf(sc, rxd) != 0) { if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); /* Reuse Rx buffers. */ if (sc->alc_cdata.alc_rxhead != NULL) m_freem(sc->alc_cdata.alc_rxhead); break; } /* * Assume we've received a full sized frame. * Actual size is fixed when we encounter the end of * multi-segmented frame. */ mp->m_len = sc->alc_buf_size; /* Chain received mbufs. */ if (sc->alc_cdata.alc_rxhead == NULL) { sc->alc_cdata.alc_rxhead = mp; sc->alc_cdata.alc_rxtail = mp; } else { mp->m_flags &= ~M_PKTHDR; sc->alc_cdata.alc_rxprev_tail = sc->alc_cdata.alc_rxtail; sc->alc_cdata.alc_rxtail->m_next = mp; sc->alc_cdata.alc_rxtail = mp; } if (count == nsegs - 1) { /* Last desc. for this frame. */ m = sc->alc_cdata.alc_rxhead; m->m_flags |= M_PKTHDR; /* * It seems that L1C/L2C controller has no way * to tell hardware to strip CRC bytes. */ m->m_pkthdr.len = sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; if (nsegs > 1) { /* Set last mbuf size. */ mp->m_len = sc->alc_cdata.alc_rxlen - (nsegs - 1) * sc->alc_buf_size; /* Remove the CRC bytes in chained mbufs. */ if (mp->m_len <= ETHER_CRC_LEN) { sc->alc_cdata.alc_rxtail = sc->alc_cdata.alc_rxprev_tail; sc->alc_cdata.alc_rxtail->m_len -= (ETHER_CRC_LEN - mp->m_len); sc->alc_cdata.alc_rxtail->m_next = NULL; m_freem(mp); } else { mp->m_len -= ETHER_CRC_LEN; } } else m->m_len = m->m_pkthdr.len; m->m_pkthdr.rcvif = ifp; /* * Due to hardware bugs, Rx checksum offloading * was intentionally disabled. */ - if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && + if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && (status & RRD_VLAN_TAG) != 0) { vtag = RRD_VLAN(le32toh(rrd->vtag)); m->m_pkthdr.ether_vtag = ntohs(vtag); m->m_flags |= M_VLANTAG; } #ifndef __NO_STRICT_ALIGNMENT m = alc_fixup_rx(ifp, m); if (m != NULL) #endif { /* Pass it on. */ ALC_UNLOCK(sc); - (*ifp->if_input)(ifp, m); + if_input(ifp, m); ALC_LOCK(sc); } } } /* Reset mbuf chains. */ ALC_RXCHAIN_RESET(sc); } static void alc_tick(void *arg) { struct alc_softc *sc; struct mii_data *mii; sc = (struct alc_softc *)arg; ALC_LOCK_ASSERT(sc); mii = device_get_softc(sc->alc_miibus); mii_tick(mii); alc_stats_update(sc); /* * alc(4) does not rely on Tx completion interrupts to reclaim * transferred buffers. Instead Tx completion interrupts are * used to hint for scheduling Tx task. So it's necessary to * release transmitted buffers by kicking Tx completion * handler. This limits the maximum reclamation delay to a hz. */ alc_txeof(sc); alc_watchdog(sc); callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); } static void alc_osc_reset(struct alc_softc *sc) { uint32_t reg; reg = CSR_READ_4(sc, ALC_MISC3); reg &= ~MISC3_25M_BY_SW; reg |= MISC3_25M_NOTO_INTNL; CSR_WRITE_4(sc, ALC_MISC3, reg); reg = CSR_READ_4(sc, ALC_MISC); if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { /* * Restore over-current protection default value. * This value could be reset by MAC reset. */ reg &= ~MISC_PSW_OCP_MASK; reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); reg &= ~MISC_INTNLOSC_OPEN; CSR_WRITE_4(sc, ALC_MISC, reg); CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); reg = CSR_READ_4(sc, ALC_MISC2); reg &= ~MISC2_CALB_START; CSR_WRITE_4(sc, ALC_MISC2, reg); CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); } else { reg &= ~MISC_INTNLOSC_OPEN; /* Disable isolate for revision A devices. */ if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) reg &= ~MISC_ISO_ENB; CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); CSR_WRITE_4(sc, ALC_MISC, reg); } DELAY(20); } static void alc_reset(struct alc_softc *sc) { uint32_t pmcfg, reg; int i; pmcfg = 0; if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { /* Reset workaround. */ CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && (sc->alc_rev & 0x01) != 0) { /* Disable L0s/L1s before reset. */ pmcfg = CSR_READ_4(sc, ALC_PM_CFG); if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) != 0) { pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB); CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); } } } reg = CSR_READ_4(sc, ALC_MASTER_CFG); reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { for (i = ALC_RESET_TIMEOUT; i > 0; i--) { DELAY(10); if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) break; } if (i == 0) device_printf(sc->alc_dev, "MAC reset timeout!\n"); } for (i = ALC_RESET_TIMEOUT; i > 0; i--) { DELAY(10); if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) break; } if (i == 0) device_printf(sc->alc_dev, "master reset timeout!\n"); for (i = ALC_RESET_TIMEOUT; i > 0; i--) { reg = CSR_READ_4(sc, ALC_IDLE_STATUS); if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) break; DELAY(10); } if (i == 0) device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && (sc->alc_rev & 0x01) != 0) { reg = CSR_READ_4(sc, ALC_MASTER_CFG); reg |= MASTER_CLK_SEL_DIS; CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); /* Restore L0s/L1s config. */ if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) != 0) CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); } alc_osc_reset(sc); reg = CSR_READ_4(sc, ALC_MISC3); reg &= ~MISC3_25M_BY_SW; reg |= MISC3_25M_NOTO_INTNL; CSR_WRITE_4(sc, ALC_MISC3, reg); reg = CSR_READ_4(sc, ALC_MISC); reg &= ~MISC_INTNLOSC_OPEN; if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) reg &= ~MISC_ISO_ENB; CSR_WRITE_4(sc, ALC_MISC, reg); DELAY(20); } if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) CSR_WRITE_4(sc, ALC_SERDES_LOCK, CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | SERDES_PHY_CLK_SLOWDOWN); } static void alc_init(void *xsc) { struct alc_softc *sc; sc = (struct alc_softc *)xsc; ALC_LOCK(sc); alc_init_locked(sc); ALC_UNLOCK(sc); } static void alc_init_locked(struct alc_softc *sc) { - struct ifnet *ifp; + if_t ifp; uint8_t eaddr[ETHER_ADDR_LEN]; bus_addr_t paddr; uint32_t reg, rxf_hi, rxf_lo; ALC_LOCK_ASSERT(sc); ifp = sc->alc_ifp; - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) return; /* * Cancel any pending I/O. */ alc_stop(sc); /* * Reset the chip to a known state. */ alc_reset(sc); /* Initialize Rx descriptors. */ if (alc_init_rx_ring(sc) != 0) { device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); alc_stop(sc); return; } alc_init_rr_ring(sc); alc_init_tx_ring(sc); alc_init_cmb(sc); alc_init_smb(sc); /* Enable all clocks. */ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | CLK_GATING_RXMAC_ENB); if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, IDLE_DECISN_TIMER_DEFAULT_1MS); } else CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); /* Reprogram the station address. */ - bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); + bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); CSR_WRITE_4(sc, ALC_PAR0, eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); /* * Clear WOL status and disable all WOL feature as WOL * would interfere Rx operation under normal environments. */ CSR_READ_4(sc, ALC_WOL_CFG); CSR_WRITE_4(sc, ALC_WOL_CFG, 0); /* Set Tx descriptor base addresses. */ paddr = sc->alc_rdata.alc_tx_ring_paddr; CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); /* We don't use high priority ring. */ CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); /* Set Tx descriptor counter. */ CSR_WRITE_4(sc, ALC_TD_RING_CNT, (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); /* Set Rx descriptor base addresses. */ paddr = sc->alc_rdata.alc_rx_ring_paddr; CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { /* We use one Rx ring. */ CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); } /* Set Rx descriptor counter. */ CSR_WRITE_4(sc, ALC_RD_RING_CNT, (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); /* * Let hardware split jumbo frames into alc_max_buf_sized chunks. * if it do not fit the buffer size. Rx return descriptor holds * a counter that indicates how many fragments were made by the * hardware. The buffer size should be multiple of 8 bytes. * Since hardware has limit on the size of buffer size, always * use the maximum value. * For strict-alignment architectures make sure to reduce buffer * size by 8 bytes to make room for alignment fixup. */ #ifndef __NO_STRICT_ALIGNMENT sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); #else sc->alc_buf_size = RX_BUF_SIZE_MAX; #endif CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); paddr = sc->alc_rdata.alc_rr_ring_paddr; /* Set Rx return descriptor base addresses. */ CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { /* We use one Rx return ring. */ CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); } /* Set Rx return descriptor counter. */ CSR_WRITE_4(sc, ALC_RRD_RING_CNT, (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); paddr = sc->alc_rdata.alc_cmb_paddr; CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); paddr = sc->alc_rdata.alc_smb_paddr; CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { /* Reconfigure SRAM - Vendor magic. */ CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); } /* Tell hardware that we're ready to load DMA blocks. */ CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); /* Configure interrupt moderation timer. */ reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; CSR_WRITE_4(sc, ALC_IM_TIMER, reg); /* * We don't want to automatic interrupt clear as task queue * for the interrupt should know interrupt status. */ reg = CSR_READ_4(sc, ALC_MASTER_CFG); reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); reg |= MASTER_SA_TIMER_ENB; if (ALC_USECS(sc->alc_int_rx_mod) != 0) reg |= MASTER_IM_RX_TIMER_ENB; if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && ALC_USECS(sc->alc_int_tx_mod) != 0) reg |= MASTER_IM_TX_TIMER_ENB; CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); /* * Disable interrupt re-trigger timer. We don't want automatic * re-triggering of un-ACKed interrupts. */ CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); /* Configure CMB. */ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(sc->alc_int_tx_mod)); } else { if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); } else CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); } /* * Hardware can be configured to issue SMB interrupt based * on programmed interval. Since there is a callout that is * invoked for every hz in driver we use that instead of * relying on periodic SMB interrupt. */ CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); /* Clear MAC statistics. */ alc_stats_clear(sc); /* * Always use maximum frame size that controller can support. * Otherwise received frames that has larger frame length * than alc(4) MTU would be silently dropped in hardware. This * would make path-MTU discovery hard as sender wouldn't get * any responses from receiver. alc(4) supports * multi-fragmented frames on Rx path so it has no issue on * assembling fragmented frames. Using maximum frame size also * removes the need to reinitialize hardware when interface * MTU configuration was changed. * * Be conservative in what you do, be liberal in what you * accept from others - RFC 793. */ CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { /* Disable header split(?) */ CSR_WRITE_4(sc, ALC_HDS_CFG, 0); /* Configure IPG/IFG parameters. */ CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); /* Set parameters for half-duplex media. */ CSR_WRITE_4(sc, ALC_HDPX_CFG, ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & HDPX_CFG_LCOL_MASK) | ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & HDPX_CFG_ABEBT_MASK) | ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & HDPX_CFG_JAMIPG_MASK)); } /* * Set TSO/checksum offload threshold. For frames that is * larger than this threshold, hardware wouldn't do * TSO/checksum offloading. */ reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & TSO_OFFLOAD_THRESH_MASK; if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); /* Configure TxQ. */ reg = (alc_dma_burst[sc->alc_dma_rd_burst] << TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) reg >>= 1; reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & TXQ_CFG_TD_BURST_MASK; reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | HQTD_CFG_BURST_ENB); CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); reg = WRR_PRI_RESTRICT_NONE; reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); CSR_WRITE_4(sc, ALC_WRR, reg); } else { /* Configure Rx free descriptor pre-fetching. */ CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); } /* * Configure flow control parameters. * XON : 80% of Rx FIFO * XOFF : 30% of Rx FIFO */ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); reg &= SRAM_RX_FIFO_LEN_MASK; reg *= 8; if (reg > 8 * 1024) reg -= RX_FIFO_PAUSE_816X_RSVD; else reg -= RX_BUF_SIZE_MAX; reg /= 8; CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & RX_FIFO_PAUSE_THRESH_LO_MASK) | (((RX_FIFO_PAUSE_816X_RSVD / 8) << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & RX_FIFO_PAUSE_THRESH_HI_MASK)); } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); rxf_hi = (reg * 8) / 10; rxf_lo = (reg * 3) / 10; CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & RX_FIFO_PAUSE_THRESH_LO_MASK) | ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & RX_FIFO_PAUSE_THRESH_HI_MASK)); } if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { /* Disable RSS until I understand L1C/L2C's RSS logic. */ CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); CSR_WRITE_4(sc, ALC_RSS_CPU, 0); } /* Configure RxQ. */ reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & RXQ_CFG_RD_BURST_MASK; reg |= RXQ_CFG_RSS_MODE_DIS; if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & RXQ_CFG_816X_IDT_TBL_SIZE_MASK; if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; } else { if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; } CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); /* Configure DMA parameters. */ reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; reg |= sc->alc_rcb; if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) reg |= DMA_CFG_CMB_ENB; if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) reg |= DMA_CFG_SMB_ENB; else reg |= DMA_CFG_SMB_DIS; reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << DMA_CFG_RD_BURST_SHIFT; reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << DMA_CFG_WR_BURST_SHIFT; reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & DMA_CFG_RD_DELAY_CNT_MASK; reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & DMA_CFG_WR_DELAY_CNT_MASK; if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { switch (AR816X_REV(sc->alc_rev)) { case AR816X_REV_A0: case AR816X_REV_A1: reg |= DMA_CFG_RD_CHNL_SEL_2; break; case AR816X_REV_B0: /* FALLTHROUGH */ default: reg |= DMA_CFG_RD_CHNL_SEL_4; break; } } CSR_WRITE_4(sc, ALC_DMA_CFG, reg); /* * Configure Tx/Rx MACs. * - Auto-padding for short frames. * - Enable CRC generation. * Actual reconfiguration of MAC for resolved speed/duplex * is followed after detection of link establishment. * AR813x/AR815x always does checksum computation regardless * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to * have bug in protocol field in Rx return structure so * these controllers can't handle fragmented frames. Disable * Rx checksum offloading until there is a newer controller * that has sane implementation. */ reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & MAC_CFG_PREAMBLE_MASK); if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) reg |= MAC_CFG_SPEED_10_100; else reg |= MAC_CFG_SPEED_1000; CSR_WRITE_4(sc, ALC_MAC_CFG, reg); /* Set up the receive filter. */ alc_rxfilter(sc); alc_rxvlan(sc); /* Acknowledge all pending interrupts and clear it. */ CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); - ifp->if_drv_flags |= IFF_DRV_RUNNING; - ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); + if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); sc->alc_flags &= ~ALC_FLAG_LINK; /* Switch to the current media. */ alc_mediachange_locked(sc); callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); } static void alc_stop(struct alc_softc *sc) { - struct ifnet *ifp; + if_t ifp; struct alc_txdesc *txd; struct alc_rxdesc *rxd; uint32_t reg; int i; ALC_LOCK_ASSERT(sc); /* * Mark the interface down and cancel the watchdog timer. */ ifp = sc->alc_ifp; - ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); + if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); sc->alc_flags &= ~ALC_FLAG_LINK; callout_stop(&sc->alc_tick_ch); sc->alc_watchdog_timer = 0; alc_stats_update(sc); /* Disable interrupts. */ CSR_WRITE_4(sc, ALC_INTR_MASK, 0); CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); /* Disable DMA. */ reg = CSR_READ_4(sc, ALC_DMA_CFG); reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); reg |= DMA_CFG_SMB_DIS; CSR_WRITE_4(sc, ALC_DMA_CFG, reg); DELAY(1000); /* Stop Rx/Tx MACs. */ alc_stop_mac(sc); /* Disable interrupts which might be touched in taskq handler. */ CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); /* Disable L0s/L1s */ alc_aspm(sc, 0, IFM_UNKNOWN); /* Reclaim Rx buffers that have been processed. */ if (sc->alc_cdata.alc_rxhead != NULL) m_freem(sc->alc_cdata.alc_rxhead); ALC_RXCHAIN_RESET(sc); /* * Free Tx/Rx mbufs still in the queues. */ for (i = 0; i < ALC_RX_RING_CNT; i++) { rxd = &sc->alc_cdata.alc_rxdesc[i]; if (rxd->rx_m != NULL) { bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); m_freem(rxd->rx_m); rxd->rx_m = NULL; } } for (i = 0; i < ALC_TX_RING_CNT; i++) { txd = &sc->alc_cdata.alc_txdesc[i]; if (txd->tx_m != NULL) { bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, txd->tx_dmamap); m_freem(txd->tx_m); txd->tx_m = NULL; } } } static void alc_stop_mac(struct alc_softc *sc) { uint32_t reg; int i; alc_stop_queue(sc); /* Disable Rx/Tx MAC. */ reg = CSR_READ_4(sc, ALC_MAC_CFG); if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); CSR_WRITE_4(sc, ALC_MAC_CFG, reg); } for (i = ALC_TIMEOUT; i > 0; i--) { reg = CSR_READ_4(sc, ALC_IDLE_STATUS); if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) break; DELAY(10); } if (i == 0) device_printf(sc->alc_dev, "could not disable Rx/Tx MAC(0x%08x)!\n", reg); } static void alc_start_queue(struct alc_softc *sc) { uint32_t qcfg[] = { 0, RXQ_CFG_QUEUE0_ENB, RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, RXQ_CFG_ENB }; uint32_t cfg; ALC_LOCK_ASSERT(sc); /* Enable RxQ. */ cfg = CSR_READ_4(sc, ALC_RXQ_CFG); if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { cfg &= ~RXQ_CFG_ENB; cfg |= qcfg[1]; } else cfg |= RXQ_CFG_QUEUE0_ENB; CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); /* Enable TxQ. */ cfg = CSR_READ_4(sc, ALC_TXQ_CFG); cfg |= TXQ_CFG_ENB; CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); } static void alc_stop_queue(struct alc_softc *sc) { uint32_t reg; int i; /* Disable RxQ. */ reg = CSR_READ_4(sc, ALC_RXQ_CFG); if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { if ((reg & RXQ_CFG_ENB) != 0) { reg &= ~RXQ_CFG_ENB; CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); } } else { if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { reg &= ~RXQ_CFG_QUEUE0_ENB; CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); } } /* Disable TxQ. */ reg = CSR_READ_4(sc, ALC_TXQ_CFG); if ((reg & TXQ_CFG_ENB) != 0) { reg &= ~TXQ_CFG_ENB; CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); } DELAY(40); for (i = ALC_TIMEOUT; i > 0; i--) { reg = CSR_READ_4(sc, ALC_IDLE_STATUS); if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) break; DELAY(10); } if (i == 0) device_printf(sc->alc_dev, "could not disable RxQ/TxQ (0x%08x)!\n", reg); } static void alc_init_tx_ring(struct alc_softc *sc) { struct alc_ring_data *rd; struct alc_txdesc *txd; int i; ALC_LOCK_ASSERT(sc); sc->alc_cdata.alc_tx_prod = 0; sc->alc_cdata.alc_tx_cons = 0; sc->alc_cdata.alc_tx_cnt = 0; rd = &sc->alc_rdata; bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); for (i = 0; i < ALC_TX_RING_CNT; i++) { txd = &sc->alc_cdata.alc_txdesc[i]; txd->tx_m = NULL; } bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); } static int alc_init_rx_ring(struct alc_softc *sc) { struct alc_ring_data *rd; struct alc_rxdesc *rxd; int i; ALC_LOCK_ASSERT(sc); sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; sc->alc_morework = 0; rd = &sc->alc_rdata; bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); for (i = 0; i < ALC_RX_RING_CNT; i++) { rxd = &sc->alc_cdata.alc_rxdesc[i]; rxd->rx_m = NULL; rxd->rx_desc = &rd->alc_rx_ring[i]; if (alc_newbuf(sc, rxd) != 0) return (ENOBUFS); } /* * Since controller does not update Rx descriptors, driver * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE * is enough to ensure coherence. */ bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); /* Let controller know availability of new Rx buffers. */ CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); return (0); } static void alc_init_rr_ring(struct alc_softc *sc) { struct alc_ring_data *rd; ALC_LOCK_ASSERT(sc); sc->alc_cdata.alc_rr_cons = 0; ALC_RXCHAIN_RESET(sc); rd = &sc->alc_rdata; bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, sc->alc_cdata.alc_rr_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); } static void alc_init_cmb(struct alc_softc *sc) { struct alc_ring_data *rd; ALC_LOCK_ASSERT(sc); rd = &sc->alc_rdata; bzero(rd->alc_cmb, ALC_CMB_SZ); bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); } static void alc_init_smb(struct alc_softc *sc) { struct alc_ring_data *rd; ALC_LOCK_ASSERT(sc); rd = &sc->alc_rdata; bzero(rd->alc_smb, ALC_SMB_SZ); bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); } static void alc_rxvlan(struct alc_softc *sc) { - struct ifnet *ifp; + if_t ifp; uint32_t reg; ALC_LOCK_ASSERT(sc); ifp = sc->alc_ifp; reg = CSR_READ_4(sc, ALC_MAC_CFG); - if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) + if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) reg |= MAC_CFG_VLAN_TAG_STRIP; else reg &= ~MAC_CFG_VLAN_TAG_STRIP; CSR_WRITE_4(sc, ALC_MAC_CFG, reg); } static u_int alc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) { uint32_t *mchash = arg; uint32_t crc; crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); return (1); } static void alc_rxfilter(struct alc_softc *sc) { - struct ifnet *ifp; + if_t ifp; uint32_t mchash[2]; uint32_t rxcfg; ALC_LOCK_ASSERT(sc); ifp = sc->alc_ifp; bzero(mchash, sizeof(mchash)); rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); - if ((ifp->if_flags & IFF_BROADCAST) != 0) + if ((if_getflags(ifp) & IFF_BROADCAST) != 0) rxcfg |= MAC_CFG_BCAST; - if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { - if ((ifp->if_flags & IFF_PROMISC) != 0) + if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { + if ((if_getflags(ifp) & IFF_PROMISC) != 0) rxcfg |= MAC_CFG_PROMISC; - if ((ifp->if_flags & IFF_ALLMULTI) != 0) + if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) rxcfg |= MAC_CFG_ALLMULTI; mchash[0] = 0xFFFFFFFF; mchash[1] = 0xFFFFFFFF; goto chipit; } if_foreach_llmaddr(ifp, alc_hash_maddr, mchash); chipit: CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); } static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) { int error, value; if (arg1 == NULL) return (EINVAL); value = *(int *)arg1; error = sysctl_handle_int(oidp, &value, 0, req); if (error || req->newptr == NULL) return (error); if (value < low || value > high) return (EINVAL); *(int *)arg1 = value; return (0); } static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) { return (sysctl_int_range(oidp, arg1, arg2, req, ALC_PROC_MIN, ALC_PROC_MAX)); } static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) { return (sysctl_int_range(oidp, arg1, arg2, req, ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); } #ifdef DEBUGNET static void -alc_debugnet_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) +alc_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) { struct alc_softc *sc __diagused; sc = if_getsoftc(ifp); KASSERT(sc->alc_buf_size <= MCLBYTES, ("incorrect cluster size")); *nrxr = ALC_RX_RING_CNT; *ncl = DEBUGNET_MAX_IN_FLIGHT; *clsize = MCLBYTES; } static void -alc_debugnet_event(struct ifnet *ifp __unused, enum debugnet_ev event __unused) +alc_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused) { } static int -alc_debugnet_transmit(struct ifnet *ifp, struct mbuf *m) +alc_debugnet_transmit(if_t ifp, struct mbuf *m) { struct alc_softc *sc; int error; sc = if_getsoftc(ifp); if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING) return (EBUSY); error = alc_encap(sc, &m); if (error == 0) alc_start_tx(sc); return (error); } static int -alc_debugnet_poll(struct ifnet *ifp, int count) +alc_debugnet_poll(if_t ifp, int count) { struct alc_softc *sc; sc = if_getsoftc(ifp); if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING) return (EBUSY); alc_txeof(sc); return (alc_rxintr(sc, count)); } #endif /* DEBUGNET */ diff --git a/sys/dev/alc/if_alcvar.h b/sys/dev/alc/if_alcvar.h index 926c80021858..22e1db4fa8d1 100644 --- a/sys/dev/alc/if_alcvar.h +++ b/sys/dev/alc/if_alcvar.h @@ -1,290 +1,290 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2009, Pyun YongHyeon * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _IF_ALCVAR_H #define _IF_ALCVAR_H #define ALC_TX_RING_CNT 256 #define ALC_TX_RING_ALIGN sizeof(struct tx_desc) #define ALC_RX_RING_CNT 256 #define ALC_RX_RING_ALIGN sizeof(struct rx_desc) #define ALC_RX_BUF_ALIGN 4 #define ALC_RR_RING_CNT ALC_RX_RING_CNT #define ALC_RR_RING_ALIGN sizeof(struct rx_rdesc) #define ALC_CMB_ALIGN 8 #define ALC_SMB_ALIGN 8 #define ALC_TSO_MAXSEGSIZE 4096 #define ALC_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) #define ALC_MAXTXSEGS 35 #define ALC_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) #define ALC_ADDR_HI(x) ((uint64_t) (x) >> 32) #define ALC_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) /* Water mark to kick reclaiming Tx buffers. */ #define ALC_TX_DESC_HIWAT ((ALC_TX_RING_CNT * 6) / 10) /* * AR816x controllers support up to 16 messages but this driver * uses single message. */ #define ALC_MSI_MESSAGES 1 #define ALC_MSIX_MESSAGES 1 #define ALC_TX_RING_SZ \ (sizeof(struct tx_desc) * ALC_TX_RING_CNT) #define ALC_RX_RING_SZ \ (sizeof(struct rx_desc) * ALC_RX_RING_CNT) #define ALC_RR_RING_SZ \ (sizeof(struct rx_rdesc) * ALC_RR_RING_CNT) #define ALC_CMB_SZ (sizeof(struct cmb)) #define ALC_SMB_SZ (sizeof(struct smb)) #define ALC_PROC_MIN 16 #define ALC_PROC_MAX (ALC_RX_RING_CNT - 1) #define ALC_PROC_DEFAULT (ALC_RX_RING_CNT / 4) /* * The number of bits reserved for MSS in AR813x/AR815x controllers * are 13 bits. This limits the maximum interface MTU size in TSO * case(8191 + sizeof(struct ip) + sizeof(struct tcphdr)) as upper * stack should not generate TCP segments with MSS greater than the * limit. Also Atheros says that maximum MTU for TSO is 6KB. */ #define ALC_TSO_MTU (6 * 1024) struct alc_rxdesc { struct mbuf *rx_m; bus_dmamap_t rx_dmamap; struct rx_desc *rx_desc; }; struct alc_txdesc { struct mbuf *tx_m; bus_dmamap_t tx_dmamap; }; struct alc_ring_data { struct tx_desc *alc_tx_ring; bus_addr_t alc_tx_ring_paddr; struct rx_desc *alc_rx_ring; bus_addr_t alc_rx_ring_paddr; struct rx_rdesc *alc_rr_ring; bus_addr_t alc_rr_ring_paddr; struct cmb *alc_cmb; bus_addr_t alc_cmb_paddr; struct smb *alc_smb; bus_addr_t alc_smb_paddr; }; struct alc_chain_data { bus_dma_tag_t alc_parent_tag; bus_dma_tag_t alc_buffer_tag; bus_dma_tag_t alc_tx_tag; struct alc_txdesc alc_txdesc[ALC_TX_RING_CNT]; bus_dma_tag_t alc_rx_tag; struct alc_rxdesc alc_rxdesc[ALC_RX_RING_CNT]; bus_dma_tag_t alc_tx_ring_tag; bus_dmamap_t alc_tx_ring_map; bus_dma_tag_t alc_rx_ring_tag; bus_dmamap_t alc_rx_ring_map; bus_dma_tag_t alc_rr_ring_tag; bus_dmamap_t alc_rr_ring_map; bus_dmamap_t alc_rx_sparemap; bus_dma_tag_t alc_cmb_tag; bus_dmamap_t alc_cmb_map; bus_dma_tag_t alc_smb_tag; bus_dmamap_t alc_smb_map; int alc_tx_prod; int alc_tx_cons; int alc_tx_cnt; int alc_rx_cons; int alc_rr_cons; int alc_rxlen; struct mbuf *alc_rxhead; struct mbuf *alc_rxtail; struct mbuf *alc_rxprev_tail; }; struct alc_hw_stats { /* Rx stats. */ uint32_t rx_frames; uint32_t rx_bcast_frames; uint32_t rx_mcast_frames; uint32_t rx_pause_frames; uint32_t rx_control_frames; uint32_t rx_crcerrs; uint32_t rx_lenerrs; uint64_t rx_bytes; uint32_t rx_runts; uint32_t rx_fragments; uint32_t rx_pkts_64; uint32_t rx_pkts_65_127; uint32_t rx_pkts_128_255; uint32_t rx_pkts_256_511; uint32_t rx_pkts_512_1023; uint32_t rx_pkts_1024_1518; uint32_t rx_pkts_1519_max; uint32_t rx_pkts_truncated; uint32_t rx_fifo_oflows; uint32_t rx_rrs_errs; uint32_t rx_alignerrs; uint64_t rx_bcast_bytes; uint64_t rx_mcast_bytes; uint32_t rx_pkts_filtered; /* Tx stats. */ uint32_t tx_frames; uint32_t tx_bcast_frames; uint32_t tx_mcast_frames; uint32_t tx_pause_frames; uint32_t tx_excess_defer; uint32_t tx_control_frames; uint32_t tx_deferred; uint64_t tx_bytes; uint32_t tx_pkts_64; uint32_t tx_pkts_65_127; uint32_t tx_pkts_128_255; uint32_t tx_pkts_256_511; uint32_t tx_pkts_512_1023; uint32_t tx_pkts_1024_1518; uint32_t tx_pkts_1519_max; uint32_t tx_single_colls; uint32_t tx_multi_colls; uint32_t tx_late_colls; uint32_t tx_excess_colls; uint32_t tx_abort; uint32_t tx_underrun; uint32_t tx_desc_underrun; uint32_t tx_lenerrs; uint32_t tx_pkts_truncated; uint64_t tx_bcast_bytes; uint64_t tx_mcast_bytes; }; struct alc_ident { uint16_t vendorid; uint16_t deviceid; uint32_t max_framelen; const char *name; }; /* * Software state per device. */ struct alc_softc { - struct ifnet *alc_ifp; + if_t alc_ifp; device_t alc_dev; device_t alc_miibus; struct resource *alc_res[1]; struct resource_spec *alc_res_spec; struct resource *alc_irq[ALC_MSI_MESSAGES]; struct resource_spec *alc_irq_spec; void *alc_intrhand[ALC_MSI_MESSAGES]; struct alc_ident *alc_ident; int alc_rev; int alc_chip_rev; int alc_phyaddr; uint8_t alc_eaddr[ETHER_ADDR_LEN]; uint32_t alc_dma_rd_burst; uint32_t alc_dma_wr_burst; uint32_t alc_rcb; int alc_expcap; int alc_pmcap; int alc_flags; #define ALC_FLAG_PCIE 0x0001 #define ALC_FLAG_PCIX 0x0002 #define ALC_FLAG_MSI 0x0004 #define ALC_FLAG_MSIX 0x0008 #define ALC_FLAG_PM 0x0010 #define ALC_FLAG_FASTETHER 0x0020 #define ALC_FLAG_JUMBO 0x0040 #define ALC_FLAG_CMB_BUG 0x0100 #define ALC_FLAG_SMB_BUG 0x0200 #define ALC_FLAG_L0S 0x0400 #define ALC_FLAG_L1S 0x0800 #define ALC_FLAG_APS 0x1000 #define ALC_FLAG_AR816X_FAMILY 0x2000 #define ALC_FLAG_LINK_WAR 0x4000 #define ALC_FLAG_E2X00 0x8000 #define ALC_FLAG_LINK 0x10000 #define ALC_FLAG_MT 0x20000 struct callout alc_tick_ch; struct alc_hw_stats alc_stats; struct alc_chain_data alc_cdata; struct alc_ring_data alc_rdata; int alc_if_flags; int alc_watchdog_timer; int alc_process_limit; volatile int alc_morework; int alc_int_rx_mod; int alc_int_tx_mod; int alc_buf_size; struct task alc_int_task; struct taskqueue *alc_tq; struct mtx alc_mtx; }; /* Register access macros. */ #define CSR_WRITE_4(_sc, reg, val) \ bus_write_4((_sc)->alc_res[0], (reg), (val)) #define CSR_WRITE_2(_sc, reg, val) \ bus_write_2((_sc)->alc_res[0], (reg), (val)) #define CSR_WRITE_1(_sc, reg, val) \ bus_write_1((_sc)->alc_res[0], (reg), (val)) #define CSR_READ_2(_sc, reg) \ bus_read_2((_sc)->alc_res[0], (reg)) #define CSR_READ_4(_sc, reg) \ bus_read_4((_sc)->alc_res[0], (reg)) #define ALC_RXCHAIN_RESET(_sc) \ do { \ (_sc)->alc_cdata.alc_rxhead = NULL; \ (_sc)->alc_cdata.alc_rxtail = NULL; \ (_sc)->alc_cdata.alc_rxprev_tail = NULL; \ (_sc)->alc_cdata.alc_rxlen = 0; \ } while (0) #define ALC_LOCK(_sc) mtx_lock(&(_sc)->alc_mtx) #define ALC_UNLOCK(_sc) mtx_unlock(&(_sc)->alc_mtx) #define ALC_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->alc_mtx, MA_OWNED) #define ALC_TX_TIMEOUT 5 #define ALC_RESET_TIMEOUT 100 #define ALC_TIMEOUT 1000 #define ALC_PHY_TIMEOUT 10000 #endif /* _IF_ALCVAR_H */ diff --git a/sys/dev/ale/if_ale.c b/sys/dev/ale/if_ale.c index f91a5af44be0..df6b5dcb723d 100644 --- a/sys/dev/ale/if_ale.c +++ b/sys/dev/ale/if_ale.c @@ -1,3077 +1,3076 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2008, Pyun YongHyeon * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* "device miibus" required. See GENERIC if you get errors here. */ #include "miibus_if.h" /* For more information about Tx checksum offload issues see ale_encap(). */ #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) MODULE_DEPEND(ale, pci, 1, 1, 1); MODULE_DEPEND(ale, ether, 1, 1, 1); MODULE_DEPEND(ale, miibus, 1, 1, 1); /* Tunables. */ static int msi_disable = 0; static int msix_disable = 0; TUNABLE_INT("hw.ale.msi_disable", &msi_disable); TUNABLE_INT("hw.ale.msix_disable", &msix_disable); /* * Devices supported by this driver. */ static const struct ale_dev { uint16_t ale_vendorid; uint16_t ale_deviceid; const char *ale_name; } ale_devs[] = { { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, }; static int ale_attach(device_t); static int ale_check_boundary(struct ale_softc *); static int ale_detach(device_t); static int ale_dma_alloc(struct ale_softc *); static void ale_dma_free(struct ale_softc *); static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); static int ale_encap(struct ale_softc *, struct mbuf **); static void ale_get_macaddr(struct ale_softc *); static void ale_init(void *); static void ale_init_locked(struct ale_softc *); static void ale_init_rx_pages(struct ale_softc *); static void ale_init_tx_ring(struct ale_softc *); static void ale_int_task(void *, int); static int ale_intr(void *); -static int ale_ioctl(struct ifnet *, u_long, caddr_t); +static int ale_ioctl(if_t, u_long, caddr_t); static void ale_mac_config(struct ale_softc *); static int ale_miibus_readreg(device_t, int, int); static void ale_miibus_statchg(device_t); static int ale_miibus_writereg(device_t, int, int, int); -static int ale_mediachange(struct ifnet *); -static void ale_mediastatus(struct ifnet *, struct ifmediareq *); +static int ale_mediachange(if_t); +static void ale_mediastatus(if_t, struct ifmediareq *); static void ale_phy_reset(struct ale_softc *); static int ale_probe(device_t); static void ale_reset(struct ale_softc *); static int ale_resume(device_t); static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, uint32_t, uint32_t *); static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); static int ale_rxeof(struct ale_softc *sc, int); static void ale_rxfilter(struct ale_softc *); static void ale_rxvlan(struct ale_softc *); static void ale_setlinkspeed(struct ale_softc *); static void ale_setwol(struct ale_softc *); static int ale_shutdown(device_t); -static void ale_start(struct ifnet *); -static void ale_start_locked(struct ifnet *); +static void ale_start(if_t); +static void ale_start_locked(if_t); static void ale_stats_clear(struct ale_softc *); static void ale_stats_update(struct ale_softc *); static void ale_stop(struct ale_softc *); static void ale_stop_mac(struct ale_softc *); static int ale_suspend(device_t); static void ale_sysctl_node(struct ale_softc *); static void ale_tick(void *); static void ale_txeof(struct ale_softc *); static void ale_watchdog(struct ale_softc *); static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); static device_method_t ale_methods[] = { /* Device interface. */ DEVMETHOD(device_probe, ale_probe), DEVMETHOD(device_attach, ale_attach), DEVMETHOD(device_detach, ale_detach), DEVMETHOD(device_shutdown, ale_shutdown), DEVMETHOD(device_suspend, ale_suspend), DEVMETHOD(device_resume, ale_resume), /* MII interface. */ DEVMETHOD(miibus_readreg, ale_miibus_readreg), DEVMETHOD(miibus_writereg, ale_miibus_writereg), DEVMETHOD(miibus_statchg, ale_miibus_statchg), DEVMETHOD_END }; static driver_t ale_driver = { "ale", ale_methods, sizeof(struct ale_softc) }; DRIVER_MODULE(ale, pci, ale_driver, NULL, NULL); MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ale, ale_devs, nitems(ale_devs)); DRIVER_MODULE(miibus, ale, miibus_driver, NULL, NULL); static struct resource_spec ale_res_spec_mem[] = { { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, { -1, 0, 0 } }; static struct resource_spec ale_irq_spec_legacy[] = { { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, { -1, 0, 0 } }; static struct resource_spec ale_irq_spec_msi[] = { { SYS_RES_IRQ, 1, RF_ACTIVE }, { -1, 0, 0 } }; static struct resource_spec ale_irq_spec_msix[] = { { SYS_RES_IRQ, 1, RF_ACTIVE }, { -1, 0, 0 } }; static int ale_miibus_readreg(device_t dev, int phy, int reg) { struct ale_softc *sc; uint32_t v; int i; sc = device_get_softc(dev); CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); for (i = ALE_PHY_TIMEOUT; i > 0; i--) { DELAY(5); v = CSR_READ_4(sc, ALE_MDIO); if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) break; } if (i == 0) { device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); return (0); } return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); } static int ale_miibus_writereg(device_t dev, int phy, int reg, int val) { struct ale_softc *sc; uint32_t v; int i; sc = device_get_softc(dev); CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); for (i = ALE_PHY_TIMEOUT; i > 0; i--) { DELAY(5); v = CSR_READ_4(sc, ALE_MDIO); if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) break; } if (i == 0) device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); return (0); } static void ale_miibus_statchg(device_t dev) { struct ale_softc *sc; struct mii_data *mii; - struct ifnet *ifp; + if_t ifp; uint32_t reg; sc = device_get_softc(dev); mii = device_get_softc(sc->ale_miibus); ifp = sc->ale_ifp; if (mii == NULL || ifp == NULL || - (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) + (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) return; sc->ale_flags &= ~ALE_FLAG_LINK; if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: sc->ale_flags |= ALE_FLAG_LINK; break; case IFM_1000_T: if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) sc->ale_flags |= ALE_FLAG_LINK; break; default: break; } } /* Stop Rx/Tx MACs. */ ale_stop_mac(sc); /* Program MACs with resolved speed/duplex/flow-control. */ if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { ale_mac_config(sc); /* Reenable Tx/Rx MACs. */ reg = CSR_READ_4(sc, ALE_MAC_CFG); reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; CSR_WRITE_4(sc, ALE_MAC_CFG, reg); } } static void -ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) +ale_mediastatus(if_t ifp, struct ifmediareq *ifmr) { struct ale_softc *sc; struct mii_data *mii; - sc = ifp->if_softc; + sc = if_getsoftc(ifp); ALE_LOCK(sc); - if ((ifp->if_flags & IFF_UP) == 0) { + if ((if_getflags(ifp) & IFF_UP) == 0) { ALE_UNLOCK(sc); return; } mii = device_get_softc(sc->ale_miibus); mii_pollstat(mii); ifmr->ifm_status = mii->mii_media_status; ifmr->ifm_active = mii->mii_media_active; ALE_UNLOCK(sc); } static int -ale_mediachange(struct ifnet *ifp) +ale_mediachange(if_t ifp) { struct ale_softc *sc; struct mii_data *mii; struct mii_softc *miisc; int error; - sc = ifp->if_softc; + sc = if_getsoftc(ifp); ALE_LOCK(sc); mii = device_get_softc(sc->ale_miibus); LIST_FOREACH(miisc, &mii->mii_phys, mii_list) PHY_RESET(miisc); error = mii_mediachg(mii); ALE_UNLOCK(sc); return (error); } static int ale_probe(device_t dev) { const struct ale_dev *sp; int i; uint16_t vendor, devid; vendor = pci_get_vendor(dev); devid = pci_get_device(dev); sp = ale_devs; for (i = 0; i < nitems(ale_devs); i++) { if (vendor == sp->ale_vendorid && devid == sp->ale_deviceid) { device_set_desc(dev, sp->ale_name); return (BUS_PROBE_DEFAULT); } sp++; } return (ENXIO); } static void ale_get_macaddr(struct ale_softc *sc) { uint32_t ea[2], reg; int i, vpdc; reg = CSR_READ_4(sc, ALE_SPI_CTRL); if ((reg & SPI_VPD_ENB) != 0) { reg &= ~SPI_VPD_ENB; CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); } if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { /* * PCI VPD capability found, let TWSI reload EEPROM. * This will set ethernet address of controller. */ CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | TWSI_CTRL_SW_LD_START); for (i = 100; i > 0; i--) { DELAY(1000); reg = CSR_READ_4(sc, ALE_TWSI_CTRL); if ((reg & TWSI_CTRL_SW_LD_START) == 0) break; } if (i == 0) device_printf(sc->ale_dev, "reloading EEPROM timeout!\n"); } else { if (bootverbose) device_printf(sc->ale_dev, "PCI VPD capability not found!\n"); } ea[0] = CSR_READ_4(sc, ALE_PAR0); ea[1] = CSR_READ_4(sc, ALE_PAR1); sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; } static void ale_phy_reset(struct ale_softc *sc) { /* Reset magic from Linux. */ CSR_WRITE_2(sc, ALE_GPHY_CTRL, GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); DELAY(1000); CSR_WRITE_2(sc, ALE_GPHY_CTRL, GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); DELAY(1000); #define ATPHY_DBG_ADDR 0x1D #define ATPHY_DBG_DATA 0x1E /* Enable hibernation mode. */ ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, ATPHY_DBG_ADDR, 0x0B); ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, ATPHY_DBG_DATA, 0xBC00); /* Set Class A/B for all modes. */ ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, ATPHY_DBG_ADDR, 0x00); ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, ATPHY_DBG_DATA, 0x02EF); /* Enable 10BT power saving. */ ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, ATPHY_DBG_ADDR, 0x12); ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, ATPHY_DBG_DATA, 0x4C04); /* Adjust 1000T power. */ ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, ATPHY_DBG_ADDR, 0x04); ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, ATPHY_DBG_ADDR, 0x8BBB); /* 10BT center tap voltage. */ ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, ATPHY_DBG_ADDR, 0x05); ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, ATPHY_DBG_ADDR, 0x2C46); #undef ATPHY_DBG_ADDR #undef ATPHY_DBG_DATA DELAY(1000); } static int ale_attach(device_t dev) { struct ale_softc *sc; - struct ifnet *ifp; + if_t ifp; uint16_t burst; int error, i, msic, msixc, pmc; uint32_t rxf_len, txf_len; error = 0; sc = device_get_softc(dev); sc->ale_dev = dev; mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); NET_TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); /* Map the device. */ pci_enable_busmaster(dev); sc->ale_res_spec = ale_res_spec_mem; sc->ale_irq_spec = ale_irq_spec_legacy; error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); if (error != 0) { device_printf(dev, "cannot allocate memory resources.\n"); goto fail; } /* Set PHY address. */ sc->ale_phyaddr = ALE_PHY_ADDR; /* Reset PHY. */ ale_phy_reset(sc); /* Reset the ethernet controller. */ ale_reset(sc); /* Get PCI and chip id/revision. */ sc->ale_rev = pci_get_revid(dev); if (sc->ale_rev >= 0xF0) { /* L2E Rev. B. AR8114 */ sc->ale_flags |= ALE_FLAG_FASTETHER; } else { if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { /* L1E AR8121 */ sc->ale_flags |= ALE_FLAG_JUMBO; } else { /* L2E Rev. A. AR8113 */ sc->ale_flags |= ALE_FLAG_FASTETHER; } } /* * All known controllers seems to require 4 bytes alignment * of Tx buffers to make Tx checksum offload with custom * checksum generation method work. */ sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; /* * All known controllers seems to have issues on Rx checksum * offload for fragmented IP datagrams. */ sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; /* * Don't use Tx CMB. It is known to cause RRS update failure * under certain circumstances. Typical phenomenon of the * issue would be unexpected sequence number encountered in * Rx handler. */ sc->ale_flags |= ALE_FLAG_TXCMB_BUG; sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> MASTER_CHIP_REV_SHIFT; if (bootverbose) { device_printf(dev, "PCI device revision : 0x%04x\n", sc->ale_rev); device_printf(dev, "Chip id/revision : 0x%04x\n", sc->ale_chip_rev); } txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); /* * Uninitialized hardware returns an invalid chip id/revision * as well as 0xFFFFFFFF for Tx/Rx fifo length. */ if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || rxf_len == 0xFFFFFFF) { device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, txf_len, rxf_len); error = ENXIO; goto fail; } device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); /* Allocate IRQ resources. */ msixc = pci_msix_count(dev); msic = pci_msi_count(dev); if (bootverbose) { device_printf(dev, "MSIX count : %d\n", msixc); device_printf(dev, "MSI count : %d\n", msic); } /* Prefer MSIX over MSI. */ if (msix_disable == 0 || msi_disable == 0) { if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && pci_alloc_msix(dev, &msixc) == 0) { if (msixc == ALE_MSIX_MESSAGES) { device_printf(dev, "Using %d MSIX messages.\n", msixc); sc->ale_flags |= ALE_FLAG_MSIX; sc->ale_irq_spec = ale_irq_spec_msix; } else pci_release_msi(dev); } if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && msic == ALE_MSI_MESSAGES && pci_alloc_msi(dev, &msic) == 0) { if (msic == ALE_MSI_MESSAGES) { device_printf(dev, "Using %d MSI messages.\n", msic); sc->ale_flags |= ALE_FLAG_MSI; sc->ale_irq_spec = ale_irq_spec_msi; } else pci_release_msi(dev); } } error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); if (error != 0) { device_printf(dev, "cannot allocate IRQ resources.\n"); goto fail; } /* Get DMA parameters from PCIe device control register. */ if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { sc->ale_flags |= ALE_FLAG_PCIE; burst = pci_read_config(dev, i + 0x08, 2); /* Max read request size. */ sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << DMA_CFG_RD_BURST_SHIFT; /* Max payload size. */ sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << DMA_CFG_WR_BURST_SHIFT; if (bootverbose) { device_printf(dev, "Read request size : %d bytes.\n", 128 << ((burst >> 12) & 0x07)); device_printf(dev, "TLP payload size : %d bytes.\n", 128 << ((burst >> 5) & 0x07)); } } else { sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; } /* Create device sysctl node. */ ale_sysctl_node(sc); if ((error = ale_dma_alloc(sc)) != 0) goto fail; /* Load station address. */ ale_get_macaddr(sc); ifp = sc->ale_ifp = if_alloc(IFT_ETHER); if (ifp == NULL) { device_printf(dev, "cannot allocate ifnet structure.\n"); error = ENXIO; goto fail; } - ifp->if_softc = sc; + if_setsoftc(ifp, sc); if_initname(ifp, device_get_name(dev), device_get_unit(dev)); - ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; - ifp->if_ioctl = ale_ioctl; - ifp->if_start = ale_start; - ifp->if_init = ale_init; - ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1; - IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); - IFQ_SET_READY(&ifp->if_snd); - ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4; - ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO; + if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); + if_setioctlfn(ifp, ale_ioctl); + if_setstartfn(ifp, ale_start); + if_setinitfn(ifp, ale_init); + if_setsendqlen(ifp, ALE_TX_RING_CNT - 1); + if_setsendqready(ifp); + if_setcapabilities(ifp, IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4); + if_sethwassist(ifp, ALE_CSUM_FEATURES | CSUM_TSO); if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { sc->ale_flags |= ALE_FLAG_PMCAP; - ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; + if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); } - ifp->if_capenable = ifp->if_capabilities; + if_setcapenable(ifp, if_getcapabilities(ifp)); /* Set up MII bus. */ error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, MIIF_DOPAUSE); if (error != 0) { device_printf(dev, "attaching PHYs failed\n"); goto fail; } ether_ifattach(ifp, sc->ale_eaddr); /* VLAN capability setup. */ - ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | - IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; - ifp->if_capenable = ifp->if_capabilities; + if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | + IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); + if_setcapenable(ifp, if_getcapabilities(ifp)); /* * Even though controllers supported by ale(3) have Rx checksum * offload bug the workaround for fragmented frames seemed to * work so far. However it seems Rx checksum offload does not * work under certain conditions. So disable Rx checksum offload * until I find more clue about it but allow users to override it. */ - ifp->if_capenable &= ~IFCAP_RXCSUM; + if_setcapenablebit(ifp, 0, IFCAP_RXCSUM); /* Tell the upper layer(s) we support long frames. */ - ifp->if_hdrlen = sizeof(struct ether_vlan_header); + if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); /* Create local taskq. */ sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, taskqueue_thread_enqueue, &sc->ale_tq); if (sc->ale_tq == NULL) { device_printf(dev, "could not create taskqueue.\n"); ether_ifdetach(ifp); error = ENXIO; goto fail; } taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", device_get_nameunit(sc->ale_dev)); if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) msic = ALE_MSIX_MESSAGES; else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) msic = ALE_MSI_MESSAGES; else msic = 1; for (i = 0; i < msic; i++) { error = bus_setup_intr(dev, sc->ale_irq[i], INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, &sc->ale_intrhand[i]); if (error != 0) break; } if (error != 0) { device_printf(dev, "could not set up interrupt handler.\n"); taskqueue_free(sc->ale_tq); sc->ale_tq = NULL; ether_ifdetach(ifp); goto fail; } fail: if (error != 0) ale_detach(dev); return (error); } static int ale_detach(device_t dev) { struct ale_softc *sc; - struct ifnet *ifp; + if_t ifp; int i, msic; sc = device_get_softc(dev); ifp = sc->ale_ifp; if (device_is_attached(dev)) { ether_ifdetach(ifp); ALE_LOCK(sc); ale_stop(sc); ALE_UNLOCK(sc); callout_drain(&sc->ale_tick_ch); taskqueue_drain(sc->ale_tq, &sc->ale_int_task); } if (sc->ale_tq != NULL) { taskqueue_drain(sc->ale_tq, &sc->ale_int_task); taskqueue_free(sc->ale_tq); sc->ale_tq = NULL; } if (sc->ale_miibus != NULL) { device_delete_child(dev, sc->ale_miibus); sc->ale_miibus = NULL; } bus_generic_detach(dev); ale_dma_free(sc); if (ifp != NULL) { if_free(ifp); sc->ale_ifp = NULL; } if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) msic = ALE_MSIX_MESSAGES; else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) msic = ALE_MSI_MESSAGES; else msic = 1; for (i = 0; i < msic; i++) { if (sc->ale_intrhand[i] != NULL) { bus_teardown_intr(dev, sc->ale_irq[i], sc->ale_intrhand[i]); sc->ale_intrhand[i] = NULL; } } bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) pci_release_msi(dev); bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); mtx_destroy(&sc->ale_mtx); return (0); } #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) static void ale_sysctl_node(struct ale_softc *sc) { struct sysctl_ctx_list *ctx; struct sysctl_oid_list *child, *parent; struct sysctl_oid *tree; struct ale_hw_stats *stats; int error; stats = &sc->ale_stats; ctx = device_get_sysctl_ctx(sc->ale_dev); child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_rx_mod, 0, sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_tx_mod, 0, sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); /* Pull in device tunables. */ sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; error = resource_int_value(device_get_name(sc->ale_dev), device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); if (error == 0) { if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { device_printf(sc->ale_dev, "int_rx_mod value out of " "range; using default: %d\n", ALE_IM_RX_TIMER_DEFAULT); sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; } } sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; error = resource_int_value(device_get_name(sc->ale_dev), device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); if (error == 0) { if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { device_printf(sc->ale_dev, "int_tx_mod value out of " "range; using default: %d\n", ALE_IM_TX_TIMER_DEFAULT); sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; } } SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_process_limit, 0, sysctl_hw_ale_proc_limit, "I", "max number of Rx events to process"); /* Pull in device tunables. */ sc->ale_process_limit = ALE_PROC_DEFAULT; error = resource_int_value(device_get_name(sc->ale_dev), device_get_unit(sc->ale_dev), "process_limit", &sc->ale_process_limit); if (error == 0) { if (sc->ale_process_limit < ALE_PROC_MIN || sc->ale_process_limit > ALE_PROC_MAX) { device_printf(sc->ale_dev, "process_limit value out of range; " "using default: %d\n", ALE_PROC_DEFAULT); sc->ale_process_limit = ALE_PROC_DEFAULT; } } /* Misc statistics. */ ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", &stats->reset_brk_seq, "Controller resets due to broken Rx sequnce number"); tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ATE statistics"); parent = SYSCTL_CHILDREN(tree); /* Rx statistics. */ tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); child = SYSCTL_CHILDREN(tree); ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", &stats->rx_frames, "Good frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", &stats->rx_bcast_frames, "Good broadcast frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", &stats->rx_mcast_frames, "Good multicast frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", &stats->rx_pause_frames, "Pause control frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", &stats->rx_control_frames, "Control frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", &stats->rx_crcerrs, "CRC errors"); ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", &stats->rx_lenerrs, "Frames with length mismatched"); ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", &stats->rx_bytes, "Good octets"); ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", &stats->rx_bcast_bytes, "Good broadcast octets"); ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", &stats->rx_mcast_bytes, "Good multicast octets"); ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", &stats->rx_runts, "Too short frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", &stats->rx_fragments, "Fragmented frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", &stats->rx_pkts_64, "64 bytes frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", &stats->rx_pkts_65_127, "65 to 127 bytes frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", &stats->rx_pkts_128_255, "128 to 255 bytes frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", &stats->rx_pkts_256_511, "256 to 511 bytes frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", &stats->rx_pkts_1519_max, "1519 to max frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", &stats->rx_fifo_oflows, "FIFO overflows"); ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", &stats->rx_rrs_errs, "Return status write-back errors"); ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", &stats->rx_alignerrs, "Alignment errors"); ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", &stats->rx_pkts_filtered, "Frames dropped due to address filtering"); /* Tx statistics. */ tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); child = SYSCTL_CHILDREN(tree); ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", &stats->tx_frames, "Good frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", &stats->tx_bcast_frames, "Good broadcast frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", &stats->tx_mcast_frames, "Good multicast frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", &stats->tx_pause_frames, "Pause control frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", &stats->tx_control_frames, "Control frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", &stats->tx_excess_defer, "Frames with excessive derferrals"); ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", &stats->tx_excess_defer, "Frames with derferrals"); ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", &stats->tx_bytes, "Good octets"); ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", &stats->tx_bcast_bytes, "Good broadcast octets"); ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", &stats->tx_mcast_bytes, "Good multicast octets"); ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", &stats->tx_pkts_64, "64 bytes frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", &stats->tx_pkts_65_127, "65 to 127 bytes frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", &stats->tx_pkts_128_255, "128 to 255 bytes frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", &stats->tx_pkts_256_511, "256 to 511 bytes frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", &stats->tx_pkts_1519_max, "1519 to max frames"); ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", &stats->tx_single_colls, "Single collisions"); ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", &stats->tx_multi_colls, "Multiple collisions"); ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", &stats->tx_late_colls, "Late collisions"); ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", &stats->tx_excess_colls, "Excessive collisions"); ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", &stats->tx_underrun, "FIFO underruns"); ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", &stats->tx_desc_underrun, "Descriptor write-back errors"); ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", &stats->tx_lenerrs, "Frames with length mismatched"); ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); } #undef ALE_SYSCTL_STAT_ADD32 #undef ALE_SYSCTL_STAT_ADD64 struct ale_dmamap_arg { bus_addr_t ale_busaddr; }; static void ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) { struct ale_dmamap_arg *ctx; if (error != 0) return; KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); ctx = (struct ale_dmamap_arg *)arg; ctx->ale_busaddr = segs[0].ds_addr; } /* * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register * which specifies high address region of DMA blocks. Therefore these * blocks should have the same high address of given 4GB address * space(i.e. crossing 4GB boundary is not allowed). */ static int ale_check_boundary(struct ale_softc *sc) { bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + sc->ale_pagesize; rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + sc->ale_pagesize; tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || (ALE_ADDR_HI(rx_page_end[0]) != ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || (ALE_ADDR_HI(rx_page_end[1]) != ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || (ALE_ADDR_HI(tx_cmb_end) != ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || (ALE_ADDR_HI(rx_cmb_end[0]) != ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || (ALE_ADDR_HI(rx_cmb_end[1]) != ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) return (EFBIG); if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) return (EFBIG); return (0); } static int ale_dma_alloc(struct ale_softc *sc) { struct ale_txdesc *txd; bus_addr_t lowaddr; struct ale_dmamap_arg ctx; int error, guard_size, i; if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) guard_size = ALE_JUMBO_FRAMELEN; else guard_size = ALE_MAX_FRAMELEN; sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, ALE_RX_PAGE_ALIGN); lowaddr = BUS_SPACE_MAXADDR; again: /* Create parent DMA tag. */ error = bus_dma_tag_create( bus_get_dma_tag(sc->ale_dev), /* parent */ 1, 0, /* alignment, boundary */ lowaddr, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 0, /* nsegments */ BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->ale_cdata.ale_parent_tag); if (error != 0) { device_printf(sc->ale_dev, "could not create parent DMA tag.\n"); goto fail; } /* Create DMA tag for Tx descriptor ring. */ error = bus_dma_tag_create( sc->ale_cdata.ale_parent_tag, /* parent */ ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ ALE_TX_RING_SZ, /* maxsize */ 1, /* nsegments */ ALE_TX_RING_SZ, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->ale_cdata.ale_tx_ring_tag); if (error != 0) { device_printf(sc->ale_dev, "could not create Tx ring DMA tag.\n"); goto fail; } /* Create DMA tag for Rx pages. */ for (i = 0; i < ALE_RX_PAGES; i++) { error = bus_dma_tag_create( sc->ale_cdata.ale_parent_tag, /* parent */ ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ sc->ale_pagesize, /* maxsize */ 1, /* nsegments */ sc->ale_pagesize, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->ale_cdata.ale_rx_page[i].page_tag); if (error != 0) { device_printf(sc->ale_dev, "could not create Rx page %d DMA tag.\n", i); goto fail; } } /* Create DMA tag for Tx coalescing message block. */ error = bus_dma_tag_create( sc->ale_cdata.ale_parent_tag, /* parent */ ALE_CMB_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ ALE_TX_CMB_SZ, /* maxsize */ 1, /* nsegments */ ALE_TX_CMB_SZ, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->ale_cdata.ale_tx_cmb_tag); if (error != 0) { device_printf(sc->ale_dev, "could not create Tx CMB DMA tag.\n"); goto fail; } /* Create DMA tag for Rx coalescing message block. */ for (i = 0; i < ALE_RX_PAGES; i++) { error = bus_dma_tag_create( sc->ale_cdata.ale_parent_tag, /* parent */ ALE_CMB_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ ALE_RX_CMB_SZ, /* maxsize */ 1, /* nsegments */ ALE_RX_CMB_SZ, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->ale_cdata.ale_rx_page[i].cmb_tag); if (error != 0) { device_printf(sc->ale_dev, "could not create Rx page %d CMB DMA tag.\n", i); goto fail; } } /* Allocate DMA'able memory and load the DMA map for Tx ring. */ error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, (void **)&sc->ale_cdata.ale_tx_ring, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->ale_cdata.ale_tx_ring_map); if (error != 0) { device_printf(sc->ale_dev, "could not allocate DMA'able memory for Tx ring.\n"); goto fail; } ctx.ale_busaddr = 0; error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); if (error != 0 || ctx.ale_busaddr == 0) { device_printf(sc->ale_dev, "could not load DMA'able memory for Tx ring.\n"); goto fail; } sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; /* Rx pages. */ for (i = 0; i < ALE_RX_PAGES; i++) { error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->ale_cdata.ale_rx_page[i].page_map); if (error != 0) { device_printf(sc->ale_dev, "could not allocate DMA'able memory for " "Rx page %d.\n", i); goto fail; } ctx.ale_busaddr = 0; error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, sc->ale_cdata.ale_rx_page[i].page_map, sc->ale_cdata.ale_rx_page[i].page_addr, sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); if (error != 0 || ctx.ale_busaddr == 0) { device_printf(sc->ale_dev, "could not load DMA'able memory for " "Rx page %d.\n", i); goto fail; } sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; } /* Tx CMB. */ error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, (void **)&sc->ale_cdata.ale_tx_cmb, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->ale_cdata.ale_tx_cmb_map); if (error != 0) { device_printf(sc->ale_dev, "could not allocate DMA'able memory for Tx CMB.\n"); goto fail; } ctx.ale_busaddr = 0; error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); if (error != 0 || ctx.ale_busaddr == 0) { device_printf(sc->ale_dev, "could not load DMA'able memory for Tx CMB.\n"); goto fail; } sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; /* Rx CMB. */ for (i = 0; i < ALE_RX_PAGES; i++) { error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->ale_cdata.ale_rx_page[i].cmb_map); if (error != 0) { device_printf(sc->ale_dev, "could not allocate " "DMA'able memory for Rx page %d CMB.\n", i); goto fail; } ctx.ale_busaddr = 0; error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, sc->ale_cdata.ale_rx_page[i].cmb_map, sc->ale_cdata.ale_rx_page[i].cmb_addr, ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); if (error != 0 || ctx.ale_busaddr == 0) { device_printf(sc->ale_dev, "could not load DMA'able " "memory for Rx page %d CMB.\n", i); goto fail; } sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; } /* * Tx descriptors/RXF0/CMB DMA blocks share the same * high address region of 64bit DMA address space. */ if (lowaddr != BUS_SPACE_MAXADDR_32BIT && (error = ale_check_boundary(sc)) != 0) { device_printf(sc->ale_dev, "4GB boundary crossed, " "switching to 32bit DMA addressing mode.\n"); ale_dma_free(sc); /* * Limit max allowable DMA address space to 32bit * and try again. */ lowaddr = BUS_SPACE_MAXADDR_32BIT; goto again; } /* * Create Tx buffer parent tag. * AR81xx allows 64bit DMA addressing of Tx buffers so it * needs separate parent DMA tag as parent DMA address space * could be restricted to be within 32bit address space by * 4GB boundary crossing. */ error = bus_dma_tag_create( bus_get_dma_tag(sc->ale_dev), /* parent */ 1, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 0, /* nsegments */ BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->ale_cdata.ale_buffer_tag); if (error != 0) { device_printf(sc->ale_dev, "could not create parent buffer DMA tag.\n"); goto fail; } /* Create DMA tag for Tx buffers. */ error = bus_dma_tag_create( sc->ale_cdata.ale_buffer_tag, /* parent */ 1, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ ALE_TSO_MAXSIZE, /* maxsize */ ALE_MAXTXSEGS, /* nsegments */ ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->ale_cdata.ale_tx_tag); if (error != 0) { device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); goto fail; } /* Create DMA maps for Tx buffers. */ for (i = 0; i < ALE_TX_RING_CNT; i++) { txd = &sc->ale_cdata.ale_txdesc[i]; txd->tx_m = NULL; txd->tx_dmamap = NULL; error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, &txd->tx_dmamap); if (error != 0) { device_printf(sc->ale_dev, "could not create Tx dmamap.\n"); goto fail; } } fail: return (error); } static void ale_dma_free(struct ale_softc *sc) { struct ale_txdesc *txd; int i; /* Tx buffers. */ if (sc->ale_cdata.ale_tx_tag != NULL) { for (i = 0; i < ALE_TX_RING_CNT; i++) { txd = &sc->ale_cdata.ale_txdesc[i]; if (txd->tx_dmamap != NULL) { bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, txd->tx_dmamap); txd->tx_dmamap = NULL; } } bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); sc->ale_cdata.ale_tx_tag = NULL; } /* Tx descriptor ring. */ if (sc->ale_cdata.ale_tx_ring_tag != NULL) { if (sc->ale_cdata.ale_tx_ring_paddr != 0) bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, sc->ale_cdata.ale_tx_ring_map); if (sc->ale_cdata.ale_tx_ring != NULL) bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, sc->ale_cdata.ale_tx_ring, sc->ale_cdata.ale_tx_ring_map); sc->ale_cdata.ale_tx_ring_paddr = 0; sc->ale_cdata.ale_tx_ring = NULL; bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); sc->ale_cdata.ale_tx_ring_tag = NULL; } /* Rx page block. */ for (i = 0; i < ALE_RX_PAGES; i++) { if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { if (sc->ale_cdata.ale_rx_page[i].page_paddr != 0) bus_dmamap_unload( sc->ale_cdata.ale_rx_page[i].page_tag, sc->ale_cdata.ale_rx_page[i].page_map); if (sc->ale_cdata.ale_rx_page[i].page_addr != NULL) bus_dmamem_free( sc->ale_cdata.ale_rx_page[i].page_tag, sc->ale_cdata.ale_rx_page[i].page_addr, sc->ale_cdata.ale_rx_page[i].page_map); sc->ale_cdata.ale_rx_page[i].page_paddr = 0; sc->ale_cdata.ale_rx_page[i].page_addr = NULL; bus_dma_tag_destroy( sc->ale_cdata.ale_rx_page[i].page_tag); sc->ale_cdata.ale_rx_page[i].page_tag = NULL; } } /* Rx CMB. */ for (i = 0; i < ALE_RX_PAGES; i++) { if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { if (sc->ale_cdata.ale_rx_page[i].cmb_paddr != 0) bus_dmamap_unload( sc->ale_cdata.ale_rx_page[i].cmb_tag, sc->ale_cdata.ale_rx_page[i].cmb_map); if (sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) bus_dmamem_free( sc->ale_cdata.ale_rx_page[i].cmb_tag, sc->ale_cdata.ale_rx_page[i].cmb_addr, sc->ale_cdata.ale_rx_page[i].cmb_map); sc->ale_cdata.ale_rx_page[i].cmb_paddr = 0; sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; bus_dma_tag_destroy( sc->ale_cdata.ale_rx_page[i].cmb_tag); sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; } } /* Tx CMB. */ if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { if (sc->ale_cdata.ale_tx_cmb_paddr != 0) bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, sc->ale_cdata.ale_tx_cmb_map); if (sc->ale_cdata.ale_tx_cmb != NULL) bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, sc->ale_cdata.ale_tx_cmb, sc->ale_cdata.ale_tx_cmb_map); sc->ale_cdata.ale_tx_cmb_paddr = 0; sc->ale_cdata.ale_tx_cmb = NULL; bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); sc->ale_cdata.ale_tx_cmb_tag = NULL; } if (sc->ale_cdata.ale_buffer_tag != NULL) { bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); sc->ale_cdata.ale_buffer_tag = NULL; } if (sc->ale_cdata.ale_parent_tag != NULL) { bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); sc->ale_cdata.ale_parent_tag = NULL; } } static int ale_shutdown(device_t dev) { return (ale_suspend(dev)); } /* * Note, this driver resets the link speed to 10/100Mbps by * restarting auto-negotiation in suspend/shutdown phase but we * don't know whether that auto-negotiation would succeed or not * as driver has no control after powering off/suspend operation. * If the renegotiation fail WOL may not work. Running at 1Gbps * will draw more power than 375mA at 3.3V which is specified in * PCI specification and that would result in complete * shutdowning power to ethernet controller. * * TODO * Save current negotiated media speed/duplex/flow-control to * softc and restore the same link again after resuming. PHY * handling such as power down/resetting to 100Mbps may be better * handled in suspend method in phy driver. */ static void ale_setlinkspeed(struct ale_softc *sc) { struct mii_data *mii; int aneg, i; mii = device_get_softc(sc->ale_miibus); mii_pollstat(mii); aneg = 0; if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { switch IFM_SUBTYPE(mii->mii_media_active) { case IFM_10_T: case IFM_100_TX: return; case IFM_1000_T: aneg++; break; default: break; } } ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); DELAY(1000); if (aneg != 0) { /* * Poll link state until ale(4) get a 10/100Mbps link. */ for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { mii_pollstat(mii); if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { switch (IFM_SUBTYPE( mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: ale_mac_config(sc); return; default: break; } } ALE_UNLOCK(sc); pause("alelnk", hz); ALE_LOCK(sc); } if (i == MII_ANEGTICKS_GIGE) device_printf(sc->ale_dev, "establishing a link failed, WOL may not work!"); } /* * No link, force MAC to have 100Mbps, full-duplex link. * This is the last resort and may/may not work. */ mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; ale_mac_config(sc); } static void ale_setwol(struct ale_softc *sc) { - struct ifnet *ifp; + if_t ifp; uint32_t reg, pmcs; uint16_t pmstat; int pmc; ALE_LOCK_ASSERT(sc); if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { /* Disable WOL. */ CSR_WRITE_4(sc, ALE_WOL_CFG, 0); reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); reg |= PCIE_PHYMISC_FORCE_RCV_DET; CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); /* Force PHY power down. */ CSR_WRITE_2(sc, ALE_GPHY_CTRL, GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); return; } ifp = sc->ale_ifp; - if ((ifp->if_capenable & IFCAP_WOL) != 0) { + if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) ale_setlinkspeed(sc); } pmcs = 0; - if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) + if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); reg = CSR_READ_4(sc, ALE_MAC_CFG); reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | MAC_CFG_BCAST); - if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) + if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; - if ((ifp->if_capenable & IFCAP_WOL) != 0) + if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) reg |= MAC_CFG_RX_ENB; CSR_WRITE_4(sc, ALE_MAC_CFG, reg); - if ((ifp->if_capenable & IFCAP_WOL) == 0) { + if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { /* WOL disabled, PHY power down. */ reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); reg |= PCIE_PHYMISC_FORCE_RCV_DET; CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); CSR_WRITE_2(sc, ALE_GPHY_CTRL, GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); } /* Request PME. */ pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); - if ((ifp->if_capenable & IFCAP_WOL) != 0) + if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); } static int ale_suspend(device_t dev) { struct ale_softc *sc; sc = device_get_softc(dev); ALE_LOCK(sc); ale_stop(sc); ale_setwol(sc); ALE_UNLOCK(sc); return (0); } static int ale_resume(device_t dev) { struct ale_softc *sc; - struct ifnet *ifp; + if_t ifp; int pmc; uint16_t pmstat; sc = device_get_softc(dev); ALE_LOCK(sc); if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { /* Disable PME and clear PME status. */ pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { pmstat &= ~PCIM_PSTAT_PMEENABLE; pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); } } /* Reset PHY. */ ale_phy_reset(sc); ifp = sc->ale_ifp; - if ((ifp->if_flags & IFF_UP) != 0) { - ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + if ((if_getflags(ifp) & IFF_UP) != 0) { + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); ale_init_locked(sc); } ALE_UNLOCK(sc); return (0); } static int ale_encap(struct ale_softc *sc, struct mbuf **m_head) { struct ale_txdesc *txd, *txd_last; struct tx_desc *desc; struct mbuf *m; struct ip *ip; struct tcphdr *tcp; bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; bus_dmamap_t map; uint32_t cflags, hdrlen, ip_off, poff, vtag; int error, i, nsegs, prod, si; ALE_LOCK_ASSERT(sc); M_ASSERTPKTHDR((*m_head)); m = *m_head; ip = NULL; tcp = NULL; cflags = vtag = 0; ip_off = poff = 0; if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { /* * AR81xx requires offset of TCP/UDP payload in its Tx * descriptor to perform hardware Tx checksum offload. * Additionally, TSO requires IP/TCP header size and * modification of IP/TCP header in order to make TSO * engine work. This kind of operation takes many CPU * cycles on FreeBSD so fast host CPU is required to * get smooth TSO performance. */ struct ether_header *eh; if (M_WRITABLE(m) == 0) { /* Get a writable copy. */ m = m_dup(*m_head, M_NOWAIT); /* Release original mbufs. */ m_freem(*m_head); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } *m_head = m; } /* * Buggy-controller requires 4 byte aligned Tx buffer * to make custom checksum offload work. */ if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && (mtod(m, intptr_t) & 3) != 0) { m = m_defrag(*m_head, M_NOWAIT); if (m == NULL) { m_freem(*m_head); *m_head = NULL; return (ENOBUFS); } *m_head = m; } ip_off = sizeof(struct ether_header); m = m_pullup(m, ip_off); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } eh = mtod(m, struct ether_header *); /* * Check if hardware VLAN insertion is off. * Additional check for LLC/SNAP frame? */ if (eh->ether_type == htons(ETHERTYPE_VLAN)) { ip_off = sizeof(struct ether_vlan_header); m = m_pullup(m, ip_off); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } } m = m_pullup(m, ip_off + sizeof(struct ip)); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } ip = (struct ip *)(mtod(m, char *) + ip_off); poff = ip_off + (ip->ip_hl << 2); if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { /* * XXX * AR81xx requires the first descriptor should * not include any TCP playload for TSO case. * (i.e. ethernet header + IP + TCP header only) * m_pullup(9) above will ensure this too. * However it's not correct if the first mbuf * of the chain does not use cluster. */ m = m_pullup(m, poff + sizeof(struct tcphdr)); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } ip = (struct ip *)(mtod(m, char *) + ip_off); tcp = (struct tcphdr *)(mtod(m, char *) + poff); m = m_pullup(m, poff + (tcp->th_off << 2)); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } /* * AR81xx requires IP/TCP header size and offset as * well as TCP pseudo checksum which complicates * TSO configuration. I guess this comes from the * adherence to Microsoft NDIS Large Send * specification which requires insertion of * pseudo checksum by upper stack. The pseudo * checksum that NDIS refers to doesn't include * TCP payload length so ale(4) should recompute * the pseudo checksum here. Hopefully this wouldn't * be much burden on modern CPUs. * Reset IP checksum and recompute TCP pseudo * checksum as NDIS specification said. */ ip->ip_sum = 0; tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, htons(IPPROTO_TCP)); } *m_head = m; } si = prod = sc->ale_cdata.ale_tx_prod; txd = &sc->ale_cdata.ale_txdesc[prod]; txd_last = txd; map = txd->tx_dmamap; error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, *m_head, txsegs, &nsegs, 0); if (error == EFBIG) { m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS); if (m == NULL) { m_freem(*m_head); *m_head = NULL; return (ENOMEM); } *m_head = m; error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, *m_head, txsegs, &nsegs, 0); if (error != 0) { m_freem(*m_head); *m_head = NULL; return (error); } } else if (error != 0) return (error); if (nsegs == 0) { m_freem(*m_head); *m_head = NULL; return (EIO); } /* Check descriptor overrun. */ if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); return (ENOBUFS); } bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); m = *m_head; if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { /* Request TSO and set MSS. */ cflags |= ALE_TD_TSO; cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); /* Set IP/TCP header size. */ cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { /* * AR81xx supports Tx custom checksum offload feature * that offloads single 16bit checksum computation. * So you can choose one among IP, TCP and UDP. * Normally driver sets checksum start/insertion * position from the information of TCP/UDP frame as * TCP/UDP checksum takes more time than that of IP. * However it seems that custom checksum offload * requires 4 bytes aligned Tx buffers due to hardware * bug. * AR81xx also supports explicit Tx checksum computation * if it is told that the size of IP header and TCP * header(for UDP, the header size does not matter * because it's fixed length). However with this scheme * TSO does not work so you have to choose one either * TSO or explicit Tx checksum offload. I chosen TSO * plus custom checksum offload with work-around which * will cover most common usage for this consumer * ethernet controller. The work-around takes a lot of * CPU cycles if Tx buffer is not aligned on 4 bytes * boundary, though. */ cflags |= ALE_TD_CXSUM; /* Set checksum start offset. */ cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); /* Set checksum insertion position of TCP/UDP. */ cflags |= ((poff + m->m_pkthdr.csum_data) << ALE_TD_CSUM_XSUMOFFSET_SHIFT); } /* Configure VLAN hardware tag insertion. */ if ((m->m_flags & M_VLANTAG) != 0) { vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); cflags |= ALE_TD_INSERT_VLAN_TAG; } i = 0; if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { /* * Make sure the first fragment contains * only ethernet and IP/TCP header with options. */ hdrlen = poff + (tcp->th_off << 2); desc = &sc->ale_cdata.ale_tx_ring[prod]; desc->addr = htole64(txsegs[i].ds_addr); desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); desc->flags = htole32(cflags); sc->ale_cdata.ale_tx_cnt++; ALE_DESC_INC(prod, ALE_TX_RING_CNT); if (m->m_len - hdrlen > 0) { /* Handle remaining payload of the first fragment. */ desc = &sc->ale_cdata.ale_tx_ring[prod]; desc->addr = htole64(txsegs[i].ds_addr + hdrlen); desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | vtag); desc->flags = htole32(cflags); sc->ale_cdata.ale_tx_cnt++; ALE_DESC_INC(prod, ALE_TX_RING_CNT); } i = 1; } for (; i < nsegs; i++) { desc = &sc->ale_cdata.ale_tx_ring[prod]; desc->addr = htole64(txsegs[i].ds_addr); desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); desc->flags = htole32(cflags); sc->ale_cdata.ale_tx_cnt++; ALE_DESC_INC(prod, ALE_TX_RING_CNT); } /* Update producer index. */ sc->ale_cdata.ale_tx_prod = prod; /* Set TSO header on the first descriptor. */ if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { desc = &sc->ale_cdata.ale_tx_ring[si]; desc->flags |= htole32(ALE_TD_TSO_HDR); } /* Finally set EOP on the last descriptor. */ prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; desc = &sc->ale_cdata.ale_tx_ring[prod]; desc->flags |= htole32(ALE_TD_EOP); /* Swap dmamap of the first and the last. */ txd = &sc->ale_cdata.ale_txdesc[prod]; map = txd_last->tx_dmamap; txd_last->tx_dmamap = txd->tx_dmamap; txd->tx_dmamap = map; txd->tx_m = m; /* Sync descriptors. */ bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, sc->ale_cdata.ale_tx_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); return (0); } static void -ale_start(struct ifnet *ifp) +ale_start(if_t ifp) { struct ale_softc *sc; - sc = ifp->if_softc; + sc = if_getsoftc(ifp); ALE_LOCK(sc); ale_start_locked(ifp); ALE_UNLOCK(sc); } static void -ale_start_locked(struct ifnet *ifp) +ale_start_locked(if_t ifp) { struct ale_softc *sc; struct mbuf *m_head; int enq; - sc = ifp->if_softc; + sc = if_getsoftc(ifp); ALE_LOCK_ASSERT(sc); /* Reclaim transmitted frames. */ if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) ale_txeof(sc); - if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != + if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) return; - for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { - IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); + for (enq = 0; !if_sendq_empty(ifp); ) { + m_head = if_dequeue(ifp); if (m_head == NULL) break; /* * Pack the data into the transmit ring. If we * don't have room, set the OACTIVE flag and wait * for the NIC to drain the ring. */ if (ale_encap(sc, &m_head)) { if (m_head == NULL) break; - IFQ_DRV_PREPEND(&ifp->if_snd, m_head); - ifp->if_drv_flags |= IFF_DRV_OACTIVE; + if_sendq_prepend(ifp, m_head); + if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); break; } enq++; /* * If there's a BPF listener, bounce a copy of this frame * to him. */ ETHER_BPF_MTAP(ifp, m_head); } if (enq > 0) { /* Kick. */ CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, sc->ale_cdata.ale_tx_prod); /* Set a timeout in case the chip goes out to lunch. */ sc->ale_watchdog_timer = ALE_TX_TIMEOUT; } } static void ale_watchdog(struct ale_softc *sc) { - struct ifnet *ifp; + if_t ifp; ALE_LOCK_ASSERT(sc); if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) return; ifp = sc->ale_ifp; if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); - ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); ale_init_locked(sc); return; } if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); - ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); ale_init_locked(sc); - if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + if (!if_sendq_empty(ifp)) ale_start_locked(ifp); } static int -ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) +ale_ioctl(if_t ifp, u_long cmd, caddr_t data) { struct ale_softc *sc; struct ifreq *ifr; struct mii_data *mii; int error, mask; - sc = ifp->if_softc; + sc = if_getsoftc(ifp); ifr = (struct ifreq *)data; error = 0; switch (cmd) { case SIOCSIFMTU: if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && ifr->ifr_mtu > ETHERMTU)) error = EINVAL; - else if (ifp->if_mtu != ifr->ifr_mtu) { + else if (if_getmtu(ifp) != ifr->ifr_mtu) { ALE_LOCK(sc); - ifp->if_mtu = ifr->ifr_mtu; - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { - ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + if_setmtu(ifp, ifr->ifr_mtu); + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); ale_init_locked(sc); } ALE_UNLOCK(sc); } break; case SIOCSIFFLAGS: ALE_LOCK(sc); - if ((ifp->if_flags & IFF_UP) != 0) { - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { - if (((ifp->if_flags ^ sc->ale_if_flags) + if ((if_getflags(ifp) & IFF_UP) != 0) { + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { + if (((if_getflags(ifp) ^ sc->ale_if_flags) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) ale_rxfilter(sc); } else { ale_init_locked(sc); } } else { - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) ale_stop(sc); } - sc->ale_if_flags = ifp->if_flags; + sc->ale_if_flags = if_getflags(ifp); ALE_UNLOCK(sc); break; case SIOCADDMULTI: case SIOCDELMULTI: ALE_LOCK(sc); - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) ale_rxfilter(sc); ALE_UNLOCK(sc); break; case SIOCSIFMEDIA: case SIOCGIFMEDIA: mii = device_get_softc(sc->ale_miibus); error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); break; case SIOCSIFCAP: ALE_LOCK(sc); - mask = ifr->ifr_reqcap ^ ifp->if_capenable; + mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); if ((mask & IFCAP_TXCSUM) != 0 && - (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { - ifp->if_capenable ^= IFCAP_TXCSUM; - if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) - ifp->if_hwassist |= ALE_CSUM_FEATURES; + (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { + if_togglecapenable(ifp, IFCAP_TXCSUM); + if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) + if_sethwassistbits(ifp, ALE_CSUM_FEATURES, 0); else - ifp->if_hwassist &= ~ALE_CSUM_FEATURES; + if_sethwassistbits(ifp, 0, ALE_CSUM_FEATURES); } if ((mask & IFCAP_RXCSUM) != 0 && - (ifp->if_capabilities & IFCAP_RXCSUM) != 0) - ifp->if_capenable ^= IFCAP_RXCSUM; + (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) + if_togglecapenable(ifp, IFCAP_RXCSUM); if ((mask & IFCAP_TSO4) != 0 && - (ifp->if_capabilities & IFCAP_TSO4) != 0) { - ifp->if_capenable ^= IFCAP_TSO4; - if ((ifp->if_capenable & IFCAP_TSO4) != 0) - ifp->if_hwassist |= CSUM_TSO; + (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { + if_togglecapenable(ifp, IFCAP_TSO4); + if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) + if_sethwassistbits(ifp, CSUM_TSO, 0); else - ifp->if_hwassist &= ~CSUM_TSO; + if_sethwassistbits(ifp, 0, CSUM_TSO); } if ((mask & IFCAP_WOL_MCAST) != 0 && - (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) - ifp->if_capenable ^= IFCAP_WOL_MCAST; + (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) + if_togglecapenable(ifp, IFCAP_WOL_MCAST); if ((mask & IFCAP_WOL_MAGIC) != 0 && - (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) - ifp->if_capenable ^= IFCAP_WOL_MAGIC; + (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) + if_togglecapenable(ifp, IFCAP_WOL_MAGIC); if ((mask & IFCAP_VLAN_HWCSUM) != 0 && - (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) - ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; + (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) + if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); if ((mask & IFCAP_VLAN_HWTSO) != 0 && - (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) - ifp->if_capenable ^= IFCAP_VLAN_HWTSO; + (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) + if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && - (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { - ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; - if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) - ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; + (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { + if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); + if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) + if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); ale_rxvlan(sc); } ALE_UNLOCK(sc); VLAN_CAPABILITIES(ifp); break; default: error = ether_ioctl(ifp, cmd, data); break; } return (error); } static void ale_mac_config(struct ale_softc *sc) { struct mii_data *mii; uint32_t reg; ALE_LOCK_ASSERT(sc); mii = device_get_softc(sc->ale_miibus); reg = CSR_READ_4(sc, ALE_MAC_CFG); reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | MAC_CFG_SPEED_MASK); /* Reprogram MAC with resolved speed/duplex. */ switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: reg |= MAC_CFG_SPEED_10_100; break; case IFM_1000_T: reg |= MAC_CFG_SPEED_1000; break; } if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { reg |= MAC_CFG_FULL_DUPLEX; if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) reg |= MAC_CFG_TX_FC; if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) reg |= MAC_CFG_RX_FC; } CSR_WRITE_4(sc, ALE_MAC_CFG, reg); } static void ale_stats_clear(struct ale_softc *sc) { struct smb sb; uint32_t *reg; int i; for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { CSR_READ_4(sc, ALE_RX_MIB_BASE + i); i += sizeof(uint32_t); } /* Read Tx statistics. */ for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { CSR_READ_4(sc, ALE_TX_MIB_BASE + i); i += sizeof(uint32_t); } } static void ale_stats_update(struct ale_softc *sc) { struct ale_hw_stats *stat; struct smb sb, *smb; - struct ifnet *ifp; + if_t ifp; uint32_t *reg; int i; ALE_LOCK_ASSERT(sc); ifp = sc->ale_ifp; stat = &sc->ale_stats; smb = &sb; /* Read Rx statistics. */ for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); i += sizeof(uint32_t); } /* Read Tx statistics. */ for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); i += sizeof(uint32_t); } /* Rx stats. */ stat->rx_frames += smb->rx_frames; stat->rx_bcast_frames += smb->rx_bcast_frames; stat->rx_mcast_frames += smb->rx_mcast_frames; stat->rx_pause_frames += smb->rx_pause_frames; stat->rx_control_frames += smb->rx_control_frames; stat->rx_crcerrs += smb->rx_crcerrs; stat->rx_lenerrs += smb->rx_lenerrs; stat->rx_bytes += smb->rx_bytes; stat->rx_runts += smb->rx_runts; stat->rx_fragments += smb->rx_fragments; stat->rx_pkts_64 += smb->rx_pkts_64; stat->rx_pkts_65_127 += smb->rx_pkts_65_127; stat->rx_pkts_128_255 += smb->rx_pkts_128_255; stat->rx_pkts_256_511 += smb->rx_pkts_256_511; stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; stat->rx_pkts_truncated += smb->rx_pkts_truncated; stat->rx_fifo_oflows += smb->rx_fifo_oflows; stat->rx_rrs_errs += smb->rx_rrs_errs; stat->rx_alignerrs += smb->rx_alignerrs; stat->rx_bcast_bytes += smb->rx_bcast_bytes; stat->rx_mcast_bytes += smb->rx_mcast_bytes; stat->rx_pkts_filtered += smb->rx_pkts_filtered; /* Tx stats. */ stat->tx_frames += smb->tx_frames; stat->tx_bcast_frames += smb->tx_bcast_frames; stat->tx_mcast_frames += smb->tx_mcast_frames; stat->tx_pause_frames += smb->tx_pause_frames; stat->tx_excess_defer += smb->tx_excess_defer; stat->tx_control_frames += smb->tx_control_frames; stat->tx_deferred += smb->tx_deferred; stat->tx_bytes += smb->tx_bytes; stat->tx_pkts_64 += smb->tx_pkts_64; stat->tx_pkts_65_127 += smb->tx_pkts_65_127; stat->tx_pkts_128_255 += smb->tx_pkts_128_255; stat->tx_pkts_256_511 += smb->tx_pkts_256_511; stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; stat->tx_single_colls += smb->tx_single_colls; stat->tx_multi_colls += smb->tx_multi_colls; stat->tx_late_colls += smb->tx_late_colls; stat->tx_excess_colls += smb->tx_excess_colls; stat->tx_underrun += smb->tx_underrun; stat->tx_desc_underrun += smb->tx_desc_underrun; stat->tx_lenerrs += smb->tx_lenerrs; stat->tx_pkts_truncated += smb->tx_pkts_truncated; stat->tx_bcast_bytes += smb->tx_bcast_bytes; stat->tx_mcast_bytes += smb->tx_mcast_bytes; /* Update counters in ifnet. */ if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + smb->tx_multi_colls * 2 + smb->tx_late_colls + smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); if_inc_counter(ifp, IFCOUNTER_IERRORS, smb->rx_crcerrs + smb->rx_lenerrs + smb->rx_runts + smb->rx_pkts_truncated + smb->rx_fifo_oflows + smb->rx_rrs_errs + smb->rx_alignerrs); } static int ale_intr(void *arg) { struct ale_softc *sc; uint32_t status; sc = (struct ale_softc *)arg; status = CSR_READ_4(sc, ALE_INTR_STATUS); if ((status & ALE_INTRS) == 0) return (FILTER_STRAY); /* Disable interrupts. */ CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); return (FILTER_HANDLED); } static void ale_int_task(void *arg, int pending) { struct ale_softc *sc; - struct ifnet *ifp; + if_t ifp; uint32_t status; int more; sc = (struct ale_softc *)arg; status = CSR_READ_4(sc, ALE_INTR_STATUS); ALE_LOCK(sc); if (sc->ale_morework != 0) status |= INTR_RX_PKT; if ((status & ALE_INTRS) == 0) goto done; /* Acknowledge interrupts but still disable interrupts. */ CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); ifp = sc->ale_ifp; more = 0; - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { more = ale_rxeof(sc, sc->ale_process_limit); if (more == EAGAIN) sc->ale_morework = 1; else if (more == EIO) { sc->ale_stats.reset_brk_seq++; - ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); ale_init_locked(sc); ALE_UNLOCK(sc); return; } if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { if ((status & INTR_DMA_RD_TO_RST) != 0) device_printf(sc->ale_dev, "DMA read error! -- resetting\n"); if ((status & INTR_DMA_WR_TO_RST) != 0) device_printf(sc->ale_dev, "DMA write error! -- resetting\n"); - ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); ale_init_locked(sc); ALE_UNLOCK(sc); return; } - if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + if (!if_sendq_empty(ifp)) ale_start_locked(ifp); } if (more == EAGAIN || (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { ALE_UNLOCK(sc); taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); return; } done: ALE_UNLOCK(sc); /* Re-enable interrupts. */ CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); } static void ale_txeof(struct ale_softc *sc) { - struct ifnet *ifp; + if_t ifp; struct ale_txdesc *txd; uint32_t cons, prod; int prog; ALE_LOCK_ASSERT(sc); ifp = sc->ale_ifp; if (sc->ale_cdata.ale_tx_cnt == 0) return; bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, sc->ale_cdata.ale_tx_ring_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, sc->ale_cdata.ale_tx_cmb_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; } else prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); cons = sc->ale_cdata.ale_tx_cons; /* * Go through our Tx list and free mbufs for those * frames which have been transmitted. */ for (prog = 0; cons != prod; prog++, ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { if (sc->ale_cdata.ale_tx_cnt <= 0) break; prog++; - ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); sc->ale_cdata.ale_tx_cnt--; txd = &sc->ale_cdata.ale_txdesc[cons]; if (txd->tx_m != NULL) { /* Reclaim transmitted mbufs. */ bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, txd->tx_dmamap); m_freem(txd->tx_m); txd->tx_m = NULL; } } if (prog > 0) { sc->ale_cdata.ale_tx_cons = cons; /* * Unarm watchdog timer only when there is no pending * Tx descriptors in queue. */ if (sc->ale_cdata.ale_tx_cnt == 0) sc->ale_watchdog_timer = 0; } } static void ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, uint32_t length, uint32_t *prod) { struct ale_rx_page *rx_page; rx_page = *page; /* Update consumer position. */ rx_page->cons += roundup(length + sizeof(struct rx_rs), ALE_RX_PAGE_ALIGN); if (rx_page->cons >= ALE_RX_PAGE_SZ) { /* * End of Rx page reached, let hardware reuse * this page. */ rx_page->cons = 0; *rx_page->cmb_addr = 0; bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, RXF_VALID); /* Switch to alternate Rx page. */ sc->ale_cdata.ale_rx_curp ^= 1; rx_page = *page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; /* Page flipped, sync CMB and Rx page. */ bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); /* Sync completed, cache updated producer index. */ *prod = *rx_page->cmb_addr; } } /* * It seems that AR81xx controller can compute partial checksum. * The partial checksum value can be used to accelerate checksum * computation for fragmented TCP/UDP packets. Upper network stack * already takes advantage of the partial checksum value in IP * reassembly stage. But I'm not sure the correctness of the * partial hardware checksum assistance due to lack of data sheet. * In addition, the Rx feature of controller that requires copying * for every frames effectively nullifies one of most nice offload * capability of controller. */ static void ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) { - struct ifnet *ifp; + if_t ifp; struct ip *ip; char *p; ifp = sc->ale_ifp; m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; if ((status & ALE_RD_IPCSUM_NOK) == 0) m->m_pkthdr.csum_flags |= CSUM_IP_VALID; if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { if (((status & ALE_RD_IPV4_FRAG) == 0) && ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; m->m_pkthdr.csum_data = 0xffff; } } else { if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { p = mtod(m, char *); p += ETHER_HDR_LEN; if ((status & ALE_RD_802_3) != 0) p += LLC_SNAPFRAMELEN; - if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && + if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0 && (status & ALE_RD_VLAN) != 0) p += ETHER_VLAN_ENCAP_LEN; ip = (struct ip *)p; if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) return; m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; m->m_pkthdr.csum_data = 0xffff; } } /* * Don't mark bad checksum for TCP/UDP frames * as fragmented frames may always have set * bad checksummed bit of frame status. */ } /* Process received frames. */ static int ale_rxeof(struct ale_softc *sc, int count) { struct ale_rx_page *rx_page; struct rx_rs *rs; - struct ifnet *ifp; + if_t ifp; struct mbuf *m; uint32_t length, prod, seqno, status, vtags; int prog; ifp = sc->ale_ifp; rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); /* * Don't directly access producer index as hardware may * update it while Rx handler is in progress. It would * be even better if there is a way to let hardware * know how far driver processed its received frames. * Alternatively, hardware could provide a way to disable * CMB updates until driver acknowledges the end of CMB * access. */ prod = *rx_page->cmb_addr; for (prog = 0; prog < count; prog++) { if (rx_page->cons >= prod) break; rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); if (sc->ale_cdata.ale_rx_seqno != seqno) { /* * Normally I believe this should not happen unless * severe driver bug or corrupted memory. However * it seems to happen under certain conditions which * is triggered by abrupt Rx events such as initiation * of bulk transfer of remote host. It's not easy to * reproduce this and I doubt it could be related * with FIFO overflow of hardware or activity of Tx * CMB updates. I also remember similar behaviour * seen on RealTek 8139 which uses resembling Rx * scheme. */ if (bootverbose) device_printf(sc->ale_dev, "garbled seq: %u, expected: %u -- " "resetting!\n", seqno, sc->ale_cdata.ale_rx_seqno); return (EIO); } /* Frame received. */ sc->ale_cdata.ale_rx_seqno++; length = ALE_RX_BYTES(le32toh(rs->length)); status = le32toh(rs->flags); if ((status & ALE_RD_ERROR) != 0) { /* * We want to pass the following frames to upper * layer regardless of error status of Rx return * status. * * o IP/TCP/UDP checksum is bad. * o frame length and protocol specific length * does not match. */ if ((status & (ALE_RD_CRC | ALE_RD_CODE | ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | ALE_RD_TRUNC)) != 0) { ale_rx_update_page(sc, &rx_page, length, &prod); continue; } } /* * m_devget(9) is major bottle-neck of ale(4)(It comes * from hardware limitation). For jumbo frames we could * get a slightly better performance if driver use * m_getjcl(9) with proper buffer size argument. However * that would make code more complicated and I don't * think users would expect good Rx performance numbers * on these low-end consumer ethernet controller. */ m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, ETHER_ALIGN, ifp, NULL); if (m == NULL) { if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); ale_rx_update_page(sc, &rx_page, length, &prod); continue; } - if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && + if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && (status & ALE_RD_IPV4) != 0) ale_rxcsum(sc, m, status); - if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && + if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && (status & ALE_RD_VLAN) != 0) { vtags = ALE_RX_VLAN(le32toh(rs->vtags)); m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); m->m_flags |= M_VLANTAG; } /* Pass it to upper layer. */ ALE_UNLOCK(sc); - (*ifp->if_input)(ifp, m); + if_input(ifp, m); ALE_LOCK(sc); ale_rx_update_page(sc, &rx_page, length, &prod); } return (count > 0 ? 0 : EAGAIN); } static void ale_tick(void *arg) { struct ale_softc *sc; struct mii_data *mii; sc = (struct ale_softc *)arg; ALE_LOCK_ASSERT(sc); mii = device_get_softc(sc->ale_miibus); mii_tick(mii); ale_stats_update(sc); /* * Reclaim Tx buffers that have been transferred. It's not * needed here but it would release allocated mbuf chains * faster and limit the maximum delay to a hz. */ ale_txeof(sc); ale_watchdog(sc); callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); } static void ale_reset(struct ale_softc *sc) { uint32_t reg; int i; /* Initialize PCIe module. From Linux. */ CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); for (i = ALE_RESET_TIMEOUT; i > 0; i--) { DELAY(10); if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) break; } if (i == 0) device_printf(sc->ale_dev, "master reset timeout!\n"); for (i = ALE_RESET_TIMEOUT; i > 0; i--) { if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) break; DELAY(10); } if (i == 0) device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); } static void ale_init(void *xsc) { struct ale_softc *sc; sc = (struct ale_softc *)xsc; ALE_LOCK(sc); ale_init_locked(sc); ALE_UNLOCK(sc); } static void ale_init_locked(struct ale_softc *sc) { - struct ifnet *ifp; + if_t ifp; struct mii_data *mii; uint8_t eaddr[ETHER_ADDR_LEN]; bus_addr_t paddr; uint32_t reg, rxf_hi, rxf_lo; ALE_LOCK_ASSERT(sc); ifp = sc->ale_ifp; mii = device_get_softc(sc->ale_miibus); - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) return; /* * Cancel any pending I/O. */ ale_stop(sc); /* * Reset the chip to a known state. */ ale_reset(sc); /* Initialize Tx descriptors, DMA memory blocks. */ ale_init_rx_pages(sc); ale_init_tx_ring(sc); /* Reprogram the station address. */ - bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); + bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); CSR_WRITE_4(sc, ALE_PAR0, eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); /* * Clear WOL status and disable all WOL feature as WOL * would interfere Rx operation under normal environments. */ CSR_READ_4(sc, ALE_WOL_CFG); CSR_WRITE_4(sc, ALE_WOL_CFG, 0); /* * Set Tx descriptor/RXF0/CMB base addresses. They share * the same high address part of DMAable region. */ paddr = sc->ale_cdata.ale_tx_ring_paddr; CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); CSR_WRITE_4(sc, ALE_TPD_CNT, (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); /* Set Rx page base address, note we use single queue. */ paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); /* Set Tx/Rx CMB addresses. */ paddr = sc->ale_cdata.ale_tx_cmb_paddr; CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); /* Mark RXF0 is valid. */ CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); /* * No need to initialize RFX1/RXF2/RXF3. We don't use * multi-queue yet. */ /* Set Rx page size, excluding guard frame size. */ CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); /* Tell hardware that we're ready to load DMA blocks. */ CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); /* Set Rx/Tx interrupt trigger threshold. */ CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | (4 << INT_TRIG_TX_THRESH_SHIFT)); /* * XXX * Set interrupt trigger timer, its purpose and relation * with interrupt moderation mechanism is not clear yet. */ CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); /* Configure interrupt moderation timer. */ reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; CSR_WRITE_4(sc, ALE_IM_TIMER, reg); reg = CSR_READ_4(sc, ALE_MASTER_CFG); reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); if (ALE_USECS(sc->ale_int_rx_mod) != 0) reg |= MASTER_IM_RX_TIMER_ENB; if (ALE_USECS(sc->ale_int_tx_mod) != 0) reg |= MASTER_IM_TX_TIMER_ENB; CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); /* Set Maximum frame size of controller. */ - if (ifp->if_mtu < ETHERMTU) + if (if_getmtu(ifp) < ETHERMTU) sc->ale_max_frame_size = ETHERMTU; else - sc->ale_max_frame_size = ifp->if_mtu; + sc->ale_max_frame_size = if_getmtu(ifp); sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); /* Configure IPG/IFG parameters. */ CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); /* Set parameters for half-duplex media. */ CSR_WRITE_4(sc, ALE_HDPX_CFG, ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & HDPX_CFG_LCOL_MASK) | ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & HDPX_CFG_ABEBT_MASK) | ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & HDPX_CFG_JAMIPG_MASK)); /* Configure Tx jumbo frame parameters. */ if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { - if (ifp->if_mtu < ETHERMTU) + if (if_getmtu(ifp) < ETHERMTU) reg = sc->ale_max_frame_size; - else if (ifp->if_mtu < 6 * 1024) + else if (if_getmtu(ifp) < 6 * 1024) reg = (sc->ale_max_frame_size * 2) / 3; else reg = sc->ale_max_frame_size / 2; CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, roundup(reg, TX_JUMBO_THRESH_UNIT) >> TX_JUMBO_THRESH_UNIT_SHIFT); } /* Configure TxQ. */ reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) << TXQ_CFG_TX_FIFO_BURST_SHIFT; reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & TXQ_CFG_TPD_BURST_MASK; CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); /* Configure Rx jumbo frame & flow control parameters. */ if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & RX_JUMBO_LKAH_MASK)); reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); rxf_hi = (reg * 7) / 10; rxf_lo = (reg * 3)/ 10; CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & RX_FIFO_PAUSE_THRESH_LO_MASK) | ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & RX_FIFO_PAUSE_THRESH_HI_MASK)); } /* Disable RSS. */ CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); CSR_WRITE_4(sc, ALE_RSS_CPU, 0); /* Configure RxQ. */ CSR_WRITE_4(sc, ALE_RXQ_CFG, RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); /* Configure DMA parameters. */ reg = 0; if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) reg |= DMA_CFG_TXCMB_ENB; CSR_WRITE_4(sc, ALE_DMA_CFG, DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | sc->ale_dma_rd_burst | reg | sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & DMA_CFG_RD_DELAY_CNT_MASK) | ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & DMA_CFG_WR_DELAY_CNT_MASK)); /* * Hardware can be configured to issue SMB interrupt based * on programmed interval. Since there is a callout that is * invoked for every hz in driver we use that instead of * relying on periodic SMB interrupt. */ CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); /* Clear MAC statistics. */ ale_stats_clear(sc); /* * Configure Tx/Rx MACs. * - Auto-padding for short frames. * - Enable CRC generation. * Actual reconfiguration of MAC for resolved speed/duplex * is followed after detection of link establishment. * AR81xx always does checksum computation regardless of * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will * cause Rx handling issue for fragmented IP datagrams due * to silicon bug. */ reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & MAC_CFG_PREAMBLE_MASK); if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) reg |= MAC_CFG_SPEED_10_100; else reg |= MAC_CFG_SPEED_1000; CSR_WRITE_4(sc, ALE_MAC_CFG, reg); /* Set up the receive filter. */ ale_rxfilter(sc); ale_rxvlan(sc); /* Acknowledge all pending interrupts and clear it. */ CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); - ifp->if_drv_flags |= IFF_DRV_RUNNING; - ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); + if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); sc->ale_flags &= ~ALE_FLAG_LINK; /* Switch to the current media. */ mii_mediachg(mii); callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); } static void ale_stop(struct ale_softc *sc) { - struct ifnet *ifp; + if_t ifp; struct ale_txdesc *txd; uint32_t reg; int i; ALE_LOCK_ASSERT(sc); /* * Mark the interface down and cancel the watchdog timer. */ ifp = sc->ale_ifp; - ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); + if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); sc->ale_flags &= ~ALE_FLAG_LINK; callout_stop(&sc->ale_tick_ch); sc->ale_watchdog_timer = 0; ale_stats_update(sc); /* Disable interrupts. */ CSR_WRITE_4(sc, ALE_INTR_MASK, 0); CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); /* Disable queue processing and DMA. */ reg = CSR_READ_4(sc, ALE_TXQ_CFG); reg &= ~TXQ_CFG_ENB; CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); reg = CSR_READ_4(sc, ALE_RXQ_CFG); reg &= ~RXQ_CFG_ENB; CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); reg = CSR_READ_4(sc, ALE_DMA_CFG); reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); CSR_WRITE_4(sc, ALE_DMA_CFG, reg); DELAY(1000); /* Stop Rx/Tx MACs. */ ale_stop_mac(sc); /* Disable interrupts which might be touched in taskq handler. */ CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); /* * Free TX mbufs still in the queues. */ for (i = 0; i < ALE_TX_RING_CNT; i++) { txd = &sc->ale_cdata.ale_txdesc[i]; if (txd->tx_m != NULL) { bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, txd->tx_dmamap); m_freem(txd->tx_m); txd->tx_m = NULL; } } } static void ale_stop_mac(struct ale_softc *sc) { uint32_t reg; int i; ALE_LOCK_ASSERT(sc); reg = CSR_READ_4(sc, ALE_MAC_CFG); if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); CSR_WRITE_4(sc, ALE_MAC_CFG, reg); } for (i = ALE_TIMEOUT; i > 0; i--) { reg = CSR_READ_4(sc, ALE_IDLE_STATUS); if (reg == 0) break; DELAY(10); } if (i == 0) device_printf(sc->ale_dev, "could not disable Tx/Rx MAC(0x%08x)!\n", reg); } static void ale_init_tx_ring(struct ale_softc *sc) { struct ale_txdesc *txd; int i; ALE_LOCK_ASSERT(sc); sc->ale_cdata.ale_tx_prod = 0; sc->ale_cdata.ale_tx_cons = 0; sc->ale_cdata.ale_tx_cnt = 0; bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); for (i = 0; i < ALE_TX_RING_CNT; i++) { txd = &sc->ale_cdata.ale_txdesc[i]; txd->tx_m = NULL; } *sc->ale_cdata.ale_tx_cmb = 0; bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, sc->ale_cdata.ale_tx_cmb_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, sc->ale_cdata.ale_tx_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); } static void ale_init_rx_pages(struct ale_softc *sc) { struct ale_rx_page *rx_page; int i; ALE_LOCK_ASSERT(sc); sc->ale_morework = 0; sc->ale_cdata.ale_rx_seqno = 0; sc->ale_cdata.ale_rx_curp = 0; for (i = 0; i < ALE_RX_PAGES; i++) { rx_page = &sc->ale_cdata.ale_rx_page[i]; bzero(rx_page->page_addr, sc->ale_pagesize); bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); rx_page->cons = 0; *rx_page->cmb_addr = 0; bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); } } static void ale_rxvlan(struct ale_softc *sc) { - struct ifnet *ifp; + if_t ifp; uint32_t reg; ALE_LOCK_ASSERT(sc); ifp = sc->ale_ifp; reg = CSR_READ_4(sc, ALE_MAC_CFG); reg &= ~MAC_CFG_VLAN_TAG_STRIP; - if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) + if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) reg |= MAC_CFG_VLAN_TAG_STRIP; CSR_WRITE_4(sc, ALE_MAC_CFG, reg); } static u_int ale_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) { uint32_t crc, *mchash = arg; crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); return (1); } static void ale_rxfilter(struct ale_softc *sc) { - struct ifnet *ifp; + if_t ifp; uint32_t mchash[2]; uint32_t rxcfg; ALE_LOCK_ASSERT(sc); ifp = sc->ale_ifp; rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); - if ((ifp->if_flags & IFF_BROADCAST) != 0) + if ((if_getflags(ifp) & IFF_BROADCAST) != 0) rxcfg |= MAC_CFG_BCAST; - if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { - if ((ifp->if_flags & IFF_PROMISC) != 0) + if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { + if ((if_getflags(ifp) & IFF_PROMISC) != 0) rxcfg |= MAC_CFG_PROMISC; - if ((ifp->if_flags & IFF_ALLMULTI) != 0) + if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) rxcfg |= MAC_CFG_ALLMULTI; CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); return; } /* Program new filter. */ bzero(mchash, sizeof(mchash)); if_foreach_llmaddr(ifp, ale_hash_maddr, &mchash); CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); } static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) { int error, value; if (arg1 == NULL) return (EINVAL); value = *(int *)arg1; error = sysctl_handle_int(oidp, &value, 0, req); if (error || req->newptr == NULL) return (error); if (value < low || value > high) return (EINVAL); *(int *)arg1 = value; return (0); } static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) { return (sysctl_int_range(oidp, arg1, arg2, req, ALE_PROC_MIN, ALE_PROC_MAX)); } static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) { return (sysctl_int_range(oidp, arg1, arg2, req, ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); } diff --git a/sys/dev/ale/if_alevar.h b/sys/dev/ale/if_alevar.h index 628a67b5623a..a2921498d096 100644 --- a/sys/dev/ale/if_alevar.h +++ b/sys/dev/ale/if_alevar.h @@ -1,251 +1,251 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2008, Pyun YongHyeon * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _IF_ALEVAR_H #define _IF_ALEVAR_H #define ALE_TX_RING_CNT 256 /* Should be multiple of 4. */ #define ALE_TX_RING_CNT_MIN 32 #define ALE_TX_RING_CNT_MAX 1020 #define ALE_TX_RING_ALIGN 8 #define ALE_RX_PAGE_ALIGN 32 #define ALE_RX_PAGES 2 #define ALE_CMB_ALIGN 32 #define ALE_TSO_MAXSEGSIZE 4096 #define ALE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) #define ALE_MAXTXSEGS 35 #define ALE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) #define ALE_ADDR_HI(x) ((uint64_t) (x) >> 32) /* Water mark to kick reclaiming Tx buffers. */ #define ALE_TX_DESC_HIWAT (ALE_TX_RING_CNT - ((ALE_TX_RING_CNT * 4) / 10)) #define ALE_MSI_MESSAGES 1 #define ALE_MSIX_MESSAGES 1 /* * TODO : Should get real jumbo MTU size. * The hardware seems to have trouble in dealing with large * frame length. If you encounter unstability issue, use * lower MTU size. */ #define ALE_JUMBO_FRAMELEN 8132 #define ALE_JUMBO_MTU \ (ALE_JUMBO_FRAMELEN - sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) #define ALE_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) #define ALE_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) struct ale_txdesc { struct mbuf *tx_m; bus_dmamap_t tx_dmamap; }; struct ale_rx_page { bus_dma_tag_t page_tag; bus_dmamap_t page_map; uint8_t *page_addr; bus_addr_t page_paddr; bus_dma_tag_t cmb_tag; bus_dmamap_t cmb_map; uint32_t *cmb_addr; bus_addr_t cmb_paddr; uint32_t cons; }; struct ale_chain_data{ bus_dma_tag_t ale_parent_tag; bus_dma_tag_t ale_buffer_tag; bus_dma_tag_t ale_tx_tag; struct ale_txdesc ale_txdesc[ALE_TX_RING_CNT]; bus_dma_tag_t ale_tx_ring_tag; bus_dmamap_t ale_tx_ring_map; bus_dma_tag_t ale_rx_mblock_tag[ALE_RX_PAGES]; bus_dmamap_t ale_rx_mblock_map[ALE_RX_PAGES]; struct tx_desc *ale_tx_ring; bus_addr_t ale_tx_ring_paddr; uint32_t *ale_tx_cmb; bus_addr_t ale_tx_cmb_paddr; bus_dma_tag_t ale_tx_cmb_tag; bus_dmamap_t ale_tx_cmb_map; uint32_t ale_tx_prod; uint32_t ale_tx_cons; int ale_tx_cnt; struct ale_rx_page ale_rx_page[ALE_RX_PAGES]; int ale_rx_curp; uint16_t ale_rx_seqno; }; #define ALE_TX_RING_SZ \ (sizeof(struct tx_desc) * ALE_TX_RING_CNT) #define ALE_RX_PAGE_SZ_MIN (8 * 1024) #define ALE_RX_PAGE_SZ_MAX (1024 * 1024) #define ALE_RX_FRAMES_PAGE 128 #define ALE_RX_PAGE_SZ \ (roundup(ALE_MAX_FRAMELEN, ALE_RX_PAGE_ALIGN) * ALE_RX_FRAMES_PAGE) #define ALE_TX_CMB_SZ (sizeof(uint32_t)) #define ALE_RX_CMB_SZ (sizeof(uint32_t)) #define ALE_PROC_MIN (ALE_RX_FRAMES_PAGE / 4) #define ALE_PROC_MAX \ ((ALE_RX_PAGE_SZ * ALE_RX_PAGES) / ETHER_MAX_LEN) #define ALE_PROC_DEFAULT (ALE_PROC_MAX / 4) struct ale_hw_stats { /* Rx stats. */ uint32_t rx_frames; uint32_t rx_bcast_frames; uint32_t rx_mcast_frames; uint32_t rx_pause_frames; uint32_t rx_control_frames; uint32_t rx_crcerrs; uint32_t rx_lenerrs; uint64_t rx_bytes; uint32_t rx_runts; uint32_t rx_fragments; uint32_t rx_pkts_64; uint32_t rx_pkts_65_127; uint32_t rx_pkts_128_255; uint32_t rx_pkts_256_511; uint32_t rx_pkts_512_1023; uint32_t rx_pkts_1024_1518; uint32_t rx_pkts_1519_max; uint32_t rx_pkts_truncated; uint32_t rx_fifo_oflows; uint32_t rx_rrs_errs; uint32_t rx_alignerrs; uint64_t rx_bcast_bytes; uint64_t rx_mcast_bytes; uint32_t rx_pkts_filtered; /* Tx stats. */ uint32_t tx_frames; uint32_t tx_bcast_frames; uint32_t tx_mcast_frames; uint32_t tx_pause_frames; uint32_t tx_excess_defer; uint32_t tx_control_frames; uint32_t tx_deferred; uint64_t tx_bytes; uint32_t tx_pkts_64; uint32_t tx_pkts_65_127; uint32_t tx_pkts_128_255; uint32_t tx_pkts_256_511; uint32_t tx_pkts_512_1023; uint32_t tx_pkts_1024_1518; uint32_t tx_pkts_1519_max; uint32_t tx_single_colls; uint32_t tx_multi_colls; uint32_t tx_late_colls; uint32_t tx_excess_colls; uint32_t tx_abort; uint32_t tx_underrun; uint32_t tx_desc_underrun; uint32_t tx_lenerrs; uint32_t tx_pkts_truncated; uint64_t tx_bcast_bytes; uint64_t tx_mcast_bytes; /* Misc. */ uint32_t reset_brk_seq; }; /* * Software state per device. */ struct ale_softc { - struct ifnet *ale_ifp; + if_t ale_ifp; device_t ale_dev; device_t ale_miibus; struct resource *ale_res[1]; struct resource_spec *ale_res_spec; struct resource *ale_irq[ALE_MSI_MESSAGES]; struct resource_spec *ale_irq_spec; void *ale_intrhand[ALE_MSI_MESSAGES]; int ale_rev; int ale_chip_rev; int ale_phyaddr; uint8_t ale_eaddr[ETHER_ADDR_LEN]; uint32_t ale_dma_rd_burst; uint32_t ale_dma_wr_burst; int ale_flags; #define ALE_FLAG_PCIE 0x0001 #define ALE_FLAG_PCIX 0x0002 #define ALE_FLAG_MSI 0x0004 #define ALE_FLAG_MSIX 0x0008 #define ALE_FLAG_PMCAP 0x0010 #define ALE_FLAG_FASTETHER 0x0020 #define ALE_FLAG_JUMBO 0x0040 #define ALE_FLAG_RXCSUM_BUG 0x0080 #define ALE_FLAG_TXCSUM_BUG 0x0100 #define ALE_FLAG_TXCMB_BUG 0x0200 #define ALE_FLAG_LINK 0x8000 struct callout ale_tick_ch; struct ale_hw_stats ale_stats; struct ale_chain_data ale_cdata; int ale_if_flags; int ale_watchdog_timer; int ale_process_limit; volatile int ale_morework; int ale_int_rx_mod; int ale_int_tx_mod; int ale_max_frame_size; int ale_pagesize; struct task ale_int_task; struct taskqueue *ale_tq; struct mtx ale_mtx; }; /* Register access macros. */ #define CSR_WRITE_4(_sc, reg, val) \ bus_write_4((_sc)->ale_res[0], (reg), (val)) #define CSR_WRITE_2(_sc, reg, val) \ bus_write_2((_sc)->ale_res[0], (reg), (val)) #define CSR_WRITE_1(_sc, reg, val) \ bus_write_1((_sc)->ale_res[0], (reg), (val)) #define CSR_READ_2(_sc, reg) \ bus_read_2((_sc)->ale_res[0], (reg)) #define CSR_READ_4(_sc, reg) \ bus_read_4((_sc)->ale_res[0], (reg)) #define ALE_LOCK(_sc) mtx_lock(&(_sc)->ale_mtx) #define ALE_UNLOCK(_sc) mtx_unlock(&(_sc)->ale_mtx) #define ALE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ale_mtx, MA_OWNED) #define ALE_TX_TIMEOUT 5 #define ALE_RESET_TIMEOUT 100 #define ALE_TIMEOUT 1000 #define ALE_PHY_TIMEOUT 1000 #endif /* _IF_ATEVAR_H */