diff --git a/lib/msun/aarch64/fenv.h b/lib/msun/aarch64/fenv.h index 2148a68b053b..a435a9de5223 100644 --- a/lib/msun/aarch64/fenv.h +++ b/lib/msun/aarch64/fenv.h @@ -1,250 +1,251 @@ /*- * Copyright (c) 2004-2005 David Schultz * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #ifdef __arm__ #include #else /* __arm__ */ #ifndef _FENV_H_ #define _FENV_H_ +#include #include #ifndef __fenv_static #define __fenv_static static #endif /* The high 32 bits contain fpcr, low 32 contain fpsr. */ typedef __uint64_t fenv_t; typedef __uint64_t fexcept_t; /* Exception flags */ #define FE_INVALID 0x00000001 #define FE_DIVBYZERO 0x00000002 #define FE_OVERFLOW 0x00000004 #define FE_UNDERFLOW 0x00000008 #define FE_INEXACT 0x00000010 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW) /* * Rounding modes * * We can't just use the hardware bit values here, because that would * make FE_UPWARD and FE_DOWNWARD negative, which is not allowed. */ #define FE_TONEAREST 0x0 #define FE_UPWARD 0x1 #define FE_DOWNWARD 0x2 #define FE_TOWARDZERO 0x3 #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ FE_UPWARD | FE_TOWARDZERO) #define _ROUND_SHIFT 22 __BEGIN_DECLS /* Default floating-point environment */ extern const fenv_t __fe_dfl_env; #define FE_DFL_ENV (&__fe_dfl_env) /* We need to be able to map status flag positions to mask flag positions */ #define _FPUSW_SHIFT 8 #define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT) #define __mrs_fpcr(__r) __asm __volatile("mrs %0, fpcr" : "=r" (__r)) #define __msr_fpcr(__r) __asm __volatile("msr fpcr, %0" : : "r" (__r)) #define __mrs_fpsr(__r) __asm __volatile("mrs %0, fpsr" : "=r" (__r)) #define __msr_fpsr(__r) __asm __volatile("msr fpsr, %0" : : "r" (__r)) __fenv_static __inline int feclearexcept(int __excepts) { fexcept_t __r; __mrs_fpsr(__r); __r &= ~__excepts; __msr_fpsr(__r); return (0); } __fenv_static inline int fegetexceptflag(fexcept_t *__flagp, int __excepts) { fexcept_t __r; __mrs_fpsr(__r); *__flagp = __r & __excepts; return (0); } __fenv_static inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts) { fexcept_t __r; __mrs_fpsr(__r); __r &= ~__excepts; __r |= *__flagp & __excepts; __msr_fpsr(__r); return (0); } __fenv_static inline int feraiseexcept(int __excepts) { fexcept_t __r; __mrs_fpsr(__r); __r |= __excepts; __msr_fpsr(__r); return (0); } __fenv_static inline int fetestexcept(int __excepts) { fexcept_t __r; __mrs_fpsr(__r); return (__r & __excepts); } __fenv_static inline int fegetround(void) { fenv_t __r; __mrs_fpcr(__r); return ((__r >> _ROUND_SHIFT) & _ROUND_MASK); } __fenv_static inline int fesetround(int __round) { fenv_t __r; if (__round & ~_ROUND_MASK) return (-1); __mrs_fpcr(__r); __r &= ~(_ROUND_MASK << _ROUND_SHIFT); __r |= __round << _ROUND_SHIFT; __msr_fpcr(__r); return (0); } __fenv_static inline int fegetenv(fenv_t *__envp) { __uint64_t fpcr; __uint64_t fpsr; __mrs_fpcr(fpcr); __mrs_fpsr(fpsr); *__envp = fpsr | (fpcr << 32); return (0); } __fenv_static inline int feholdexcept(fenv_t *__envp) { fenv_t __r; __mrs_fpcr(__r); *__envp = __r << 32; __r &= ~(_ENABLE_MASK); __msr_fpcr(__r); __mrs_fpsr(__r); *__envp |= (__uint32_t)__r; __r &= ~(_ENABLE_MASK); __msr_fpsr(__r); return (0); } __fenv_static inline int fesetenv(const fenv_t *__envp) { __msr_fpcr((*__envp) >> 32); __msr_fpsr((fenv_t)(__uint32_t)*__envp); return (0); } __fenv_static inline int feupdateenv(const fenv_t *__envp) { fexcept_t __r; __mrs_fpsr(__r); fesetenv(__envp); feraiseexcept(__r & FE_ALL_EXCEPT); return (0); } #if __BSD_VISIBLE /* We currently provide no external definitions of the functions below. */ static inline int feenableexcept(int __mask) { fenv_t __old_r, __new_r; __mrs_fpcr(__old_r); __new_r = __old_r | ((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT); __msr_fpcr(__new_r); return ((__old_r >> _FPUSW_SHIFT) & FE_ALL_EXCEPT); } static inline int fedisableexcept(int __mask) { fenv_t __old_r, __new_r; __mrs_fpcr(__old_r); __new_r = __old_r & ~((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT); __msr_fpcr(__new_r); return ((__old_r >> _FPUSW_SHIFT) & FE_ALL_EXCEPT); } static inline int fegetexcept(void) { fenv_t __r; __mrs_fpcr(__r); return ((__r & _ENABLE_MASK) >> _FPUSW_SHIFT); } #endif /* __BSD_VISIBLE */ __END_DECLS #endif /* !_FENV_H_ */ #endif /* __arm__ */ diff --git a/lib/msun/arm/fenv.h b/lib/msun/arm/fenv.h index 5dded5d744fd..e8a30fcf496f 100644 --- a/lib/msun/arm/fenv.h +++ b/lib/msun/arm/fenv.h @@ -1,267 +1,268 @@ /*- * SPDX-License-Identifier: BSD-2-Clause * * Copyright (c) 2004-2005 David Schultz * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #ifndef _FENV_H_ #define _FENV_H_ +#include #include #ifndef __fenv_static #define __fenv_static static #endif typedef __uint32_t fenv_t; typedef __uint32_t fexcept_t; /* Exception flags */ #define FE_INVALID 0x0001 #define FE_DIVBYZERO 0x0002 #define FE_OVERFLOW 0x0004 #define FE_UNDERFLOW 0x0008 #define FE_INEXACT 0x0010 #ifdef __ARM_PCS_VFP #define FE_DENORMAL 0x0080 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW | FE_DENORMAL) #else #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW) #endif /* Rounding modes */ #define VFP_FE_TONEAREST 0x00000000 #define VFP_FE_UPWARD 0x00400000 #define VFP_FE_DOWNWARD 0x00800000 #define VFP_FE_TOWARDZERO 0x00c00000 #ifdef __ARM_PCS_VFP #define FE_TONEAREST VFP_FE_TONEAREST #define FE_UPWARD VFP_FE_UPWARD #define FE_DOWNWARD VFP_FE_DOWNWARD #define FE_TOWARDZERO VFP_FE_TOWARDZERO #else #define FE_TONEAREST 0x0000 #define FE_TOWARDZERO 0x0001 #define FE_UPWARD 0x0002 #define FE_DOWNWARD 0x0003 #endif #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ FE_UPWARD | FE_TOWARDZERO) __BEGIN_DECLS /* Default floating-point environment */ extern const fenv_t __fe_dfl_env; #define FE_DFL_ENV (&__fe_dfl_env) /* We need to be able to map status flag positions to mask flag positions */ #ifndef __ARM_PCS_VFP #define _FPUSW_SHIFT 16 #define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT) #endif #ifndef __ARM_PCS_VFP int feclearexcept(int __excepts); int fegetexceptflag(fexcept_t *__flagp, int __excepts); int fesetexceptflag(const fexcept_t *__flagp, int __excepts); int feraiseexcept(int __excepts); int fetestexcept(int __excepts); int fegetround(void); int fesetround(int __round); int fegetenv(fenv_t *__envp); int feholdexcept(fenv_t *__envp); int fesetenv(const fenv_t *__envp); int feupdateenv(const fenv_t *__envp); #if __BSD_VISIBLE int feenableexcept(int __mask); int fedisableexcept(int __mask); int fegetexcept(void); #endif #else /* __ARM_PCS_VFP */ #define vmrs_fpscr(__r) __asm __volatile("vmrs %0, fpscr" : "=&r"(__r)) #define vmsr_fpscr(__r) __asm __volatile("vmsr fpscr, %0" : : "r"(__r)) #define _FPU_MASK_SHIFT 8 __fenv_static inline int feclearexcept(int __excepts) { fexcept_t __fpsr; vmrs_fpscr(__fpsr); __fpsr &= ~__excepts; vmsr_fpscr(__fpsr); return (0); } __fenv_static inline int fegetexceptflag(fexcept_t *__flagp, int __excepts) { fexcept_t __fpsr; vmrs_fpscr(__fpsr); *__flagp = __fpsr & __excepts; return (0); } __fenv_static inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts) { fexcept_t __fpsr; vmrs_fpscr(__fpsr); __fpsr &= ~__excepts; __fpsr |= *__flagp & __excepts; vmsr_fpscr(__fpsr); return (0); } __fenv_static inline int feraiseexcept(int __excepts) { fexcept_t __ex = __excepts; fesetexceptflag(&__ex, __excepts); /* XXX */ return (0); } __fenv_static inline int fetestexcept(int __excepts) { fexcept_t __fpsr; vmrs_fpscr(__fpsr); return (__fpsr & __excepts); } __fenv_static inline int fegetround(void) { fenv_t __fpsr; vmrs_fpscr(__fpsr); return (__fpsr & _ROUND_MASK); } __fenv_static inline int fesetround(int __round) { fenv_t __fpsr; vmrs_fpscr(__fpsr); __fpsr &= ~(_ROUND_MASK); __fpsr |= __round; vmsr_fpscr(__fpsr); return (0); } __fenv_static inline int fegetenv(fenv_t *__envp) { vmrs_fpscr(*__envp); return (0); } __fenv_static inline int feholdexcept(fenv_t *__envp) { fenv_t __env; vmrs_fpscr(__env); *__envp = __env; __env &= ~(FE_ALL_EXCEPT); vmsr_fpscr(__env); return (0); } __fenv_static inline int fesetenv(const fenv_t *__envp) { vmsr_fpscr(*__envp); return (0); } __fenv_static inline int feupdateenv(const fenv_t *__envp) { fexcept_t __fpsr; vmrs_fpscr(__fpsr); vmsr_fpscr(*__envp); feraiseexcept(__fpsr & FE_ALL_EXCEPT); return (0); } #if __BSD_VISIBLE /* We currently provide no external definitions of the functions below. */ __fenv_static inline int feenableexcept(int __mask) { fenv_t __old_fpsr, __new_fpsr; vmrs_fpscr(__old_fpsr); __new_fpsr = __old_fpsr | ((__mask & FE_ALL_EXCEPT) << _FPU_MASK_SHIFT); vmsr_fpscr(__new_fpsr); return ((__old_fpsr >> _FPU_MASK_SHIFT) & FE_ALL_EXCEPT); } __fenv_static inline int fedisableexcept(int __mask) { fenv_t __old_fpsr, __new_fpsr; vmrs_fpscr(__old_fpsr); __new_fpsr = __old_fpsr & ~((__mask & FE_ALL_EXCEPT) << _FPU_MASK_SHIFT); vmsr_fpscr(__new_fpsr); return ((__old_fpsr >> _FPU_MASK_SHIFT) & FE_ALL_EXCEPT); } __fenv_static inline int fegetexcept(void) { fenv_t __fpsr; vmrs_fpscr(__fpsr); return (__fpsr & FE_ALL_EXCEPT); } #endif /* __BSD_VISIBLE */ #endif /* __ARM_PCS_VFP */ __END_DECLS #endif /* !_FENV_H_ */ diff --git a/sys/arm/include/sysarch.h b/sys/arm/include/sysarch.h index 907a84f39e58..e0a8e0039b99 100644 --- a/sys/arm/include/sysarch.h +++ b/sys/arm/include/sysarch.h @@ -1,82 +1,84 @@ /* $NetBSD: sysarch.h,v 1.5 2003/09/11 09:40:12 kleink Exp $ */ /*- * SPDX-License-Identifier: BSD-4-Clause * * Copyright (c) 1996-1997 Mark Brinicombe. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Mark Brinicombe. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #ifndef _ARM_SYSARCH_H_ #define _ARM_SYSARCH_H_ +#include + #include #ifndef LOCORE #ifndef __ASSEMBLER__ /* * Pickup definition of various __types. */ #include /* * Architecture specific syscalls (arm) */ #define ARM_SYNC_ICACHE 0 #define ARM_DRAIN_WRITEBUF 1 #define ARM_SET_TP 2 #define ARM_GET_TP 3 #define ARM_GET_VFPSTATE 4 struct arm_sync_icache_args { __uintptr_t addr; /* Virtual start address */ __size_t len; /* Region size */ }; struct arm_get_vfpstate_args { __size_t mc_vfp_size; void *mc_vfp; }; #ifndef _KERNEL __BEGIN_DECLS int arm_sync_icache(unsigned int, int); int arm_drain_writebuf(void); int sysarch(int, void *); __END_DECLS #endif #endif /* __ASSEMBLER__ */ #endif /* LOCORE */ #endif /* !_ARM_SYSARCH_H_ */ diff --git a/sys/arm64/include/sysarch.h b/sys/arm64/include/sysarch.h index b7846651c031..498e26f6d47e 100644 --- a/sys/arm64/include/sysarch.h +++ b/sys/arm64/include/sysarch.h @@ -1,62 +1,64 @@ /*- * Copyright (c) 1993 The Regents of the University of California. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: FreeBSD: src/sys/i386/include/sysarch.h,v 1.14 2000/09/21 */ #ifdef __arm__ #include #else /* !__arm__ */ /* * Architecture specific syscalls (arm64) */ #ifndef _MACHINE_SYSARCH_H_ #define _MACHINE_SYSARCH_H_ +#include + #define ARM64_GUARD_PAGE 0x100 struct arm64_guard_page_args { __uintptr_t addr; __size_t len; }; #define ARM64_GET_SVE_VL 0x200 /* Reserved ARM64_SET_SVE_VL 0x201 */ #ifndef _KERNEL __BEGIN_DECLS int sysarch(int _number, void *_args); __END_DECLS #endif #endif /* !_MACHINE_SYSARCH_H_ */ #endif /* !__arm__ */