diff --git a/sys/amd64/amd64/amd64_mem.c b/sys/amd64/amd64/amd64_mem.c index 9264a2b2a81c..2627e1564853 100644 --- a/sys/amd64/amd64/amd64_mem.c +++ b/sys/amd64/amd64/amd64_mem.c @@ -1,630 +1,631 @@ /*- * Copyright (c) 1999 Michael Smith * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include /* * amd64 memory range operations * * This code will probably be impenetrable without reference to the * Intel Pentium Pro documentation or x86-64 programmers manual vol 2. */ static char *mem_owner_bios = "BIOS"; #define MR686_FIXMTRR (1<<0) #define mrwithin(mr, a) \ (((a) >= (mr)->mr_base) && ((a) < ((mr)->mr_base + (mr)->mr_len))) #define mroverlap(mra, mrb) \ (mrwithin(mra, mrb->mr_base) || mrwithin(mrb, mra->mr_base)) #define mrvalid(base, len) \ ((!(base & ((1 << 12) - 1))) && /* base is multiple of 4k */ \ ((len) >= (1 << 12)) && /* length is >= 4k */ \ powerof2((len)) && /* ... and power of two */ \ !((base) & ((len) - 1))) /* range is not discontiuous */ #define mrcopyflags(curr, new) (((curr) & ~MDF_ATTRMASK) | ((new) & MDF_ATTRMASK)) static int mtrrs_disabled; TUNABLE_INT("machdep.disable_mtrrs", &mtrrs_disabled); SYSCTL_INT(_machdep, OID_AUTO, disable_mtrrs, CTLFLAG_RDTUN, &mtrrs_disabled, 0, "Disable amd64 MTRRs."); static void amd64_mrinit(struct mem_range_softc *sc); static int amd64_mrset(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg); static void amd64_mrAPinit(struct mem_range_softc *sc); static struct mem_range_ops amd64_mrops = { amd64_mrinit, amd64_mrset, amd64_mrAPinit }; /* XXX for AP startup hook */ static u_int64_t mtrrcap, mtrrdef; static struct mem_range_desc *mem_range_match(struct mem_range_softc *sc, struct mem_range_desc *mrd); static void amd64_mrfetch(struct mem_range_softc *sc); static int amd64_mtrrtype(int flags); static int amd64_mrt2mtrr(int flags, int oldval); static int amd64_mtrrconflict(int flag1, int flag2); static void amd64_mrstore(struct mem_range_softc *sc); static void amd64_mrstoreone(void *arg); static struct mem_range_desc *amd64_mtrrfixsearch(struct mem_range_softc *sc, u_int64_t addr); static int amd64_mrsetlow(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg); static int amd64_mrsetvariable(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg); /* amd64 MTRR type to memory range type conversion */ static int amd64_mtrrtomrt[] = { MDF_UNCACHEABLE, MDF_WRITECOMBINE, MDF_UNKNOWN, MDF_UNKNOWN, MDF_WRITETHROUGH, MDF_WRITEPROTECT, MDF_WRITEBACK }; #define MTRRTOMRTLEN (sizeof(amd64_mtrrtomrt) / sizeof(amd64_mtrrtomrt[0])) /* * Used in /dev/mem drivers and elsewhere */ MALLOC_DEFINE(M_MEMDESC, "memdesc", "memory range descriptors"); static int amd64_mtrr2mrt(int val) { if (val < 0 || val >= MTRRTOMRTLEN) return MDF_UNKNOWN; return amd64_mtrrtomrt[val]; } /* * amd64 MTRR conflicts. Writeback and uncachable may overlap. */ static int amd64_mtrrconflict(int flag1, int flag2) { flag1 &= MDF_ATTRMASK; flag2 &= MDF_ATTRMASK; if ((flag1 & MDF_UNKNOWN) || (flag2 & MDF_UNKNOWN)) return 1; if (flag1 == flag2 || (flag1 == MDF_WRITEBACK && flag2 == MDF_UNCACHEABLE) || (flag2 == MDF_WRITEBACK && flag1 == MDF_UNCACHEABLE)) return 0; return 1; } /* * Look for an exactly-matching range. */ static struct mem_range_desc * mem_range_match(struct mem_range_softc *sc, struct mem_range_desc *mrd) { struct mem_range_desc *cand; int i; for (i = 0, cand = sc->mr_desc; i < sc->mr_ndesc; i++, cand++) if ((cand->mr_base == mrd->mr_base) && (cand->mr_len == mrd->mr_len)) return(cand); return(NULL); } /* * Fetch the current mtrr settings from the current CPU (assumed to all * be in sync in the SMP case). Note that if we are here, we assume * that MTRRs are enabled, and we may or may not have fixed MTRRs. */ static void amd64_mrfetch(struct mem_range_softc *sc) { struct mem_range_desc *mrd; u_int64_t msrv; int i, j, msr; mrd = sc->mr_desc; /* Get fixed-range MTRRs */ if (sc->mr_cap & MR686_FIXMTRR) { msr = MSR_MTRR64kBase; for (i = 0; i < (MTRR_N64K / 8); i++, msr++) { msrv = rdmsr(msr); for (j = 0; j < 8; j++, mrd++) { mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) | amd64_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE; if (mrd->mr_owner[0] == 0) strcpy(mrd->mr_owner, mem_owner_bios); msrv = msrv >> 8; } } msr = MSR_MTRR16kBase; for (i = 0; i < (MTRR_N16K / 8); i++, msr++) { msrv = rdmsr(msr); for (j = 0; j < 8; j++, mrd++) { mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) | amd64_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE; if (mrd->mr_owner[0] == 0) strcpy(mrd->mr_owner, mem_owner_bios); msrv = msrv >> 8; } } msr = MSR_MTRR4kBase; for (i = 0; i < (MTRR_N4K / 8); i++, msr++) { msrv = rdmsr(msr); for (j = 0; j < 8; j++, mrd++) { mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) | amd64_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE; if (mrd->mr_owner[0] == 0) strcpy(mrd->mr_owner, mem_owner_bios); msrv = msrv >> 8; } } } /* Get remainder which must be variable MTRRs */ msr = MSR_MTRRVarBase; for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) { msrv = rdmsr(msr); mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) | - amd64_mtrr2mrt(msrv & 0xff); - mrd->mr_base = msrv & 0x000000fffffff000L; + amd64_mtrr2mrt(msrv & MTRR_PHYSBASE_TYPE); + mrd->mr_base = msrv & MTRR_PHYSBASE_PHYSBASE; msrv = rdmsr(msr + 1); - mrd->mr_flags = (msrv & 0x800) ? + mrd->mr_flags = (msrv & MTRR_PHYSMASK_VALID) ? (mrd->mr_flags | MDF_ACTIVE) : (mrd->mr_flags & ~MDF_ACTIVE); /* Compute the range from the mask. Ick. */ - mrd->mr_len = (~(msrv & 0x000000fffffff000L) & 0x000000ffffffffffL) + 1; + mrd->mr_len = (~(msrv & MTRR_PHYSMASK_PHYSMASK) + & (MTRR_PHYSMASK_PHYSMASK | 0xfffL)) + 1; if (!mrvalid(mrd->mr_base, mrd->mr_len)) mrd->mr_flags |= MDF_BOGUS; /* If unclaimed and active, must be the BIOS */ if ((mrd->mr_flags & MDF_ACTIVE) && (mrd->mr_owner[0] == 0)) strcpy(mrd->mr_owner, mem_owner_bios); } } /* * Return the MTRR memory type matching a region's flags */ static int amd64_mtrrtype(int flags) { int i; flags &= MDF_ATTRMASK; for (i = 0; i < MTRRTOMRTLEN; i++) { if (amd64_mtrrtomrt[i] == MDF_UNKNOWN) continue; if (flags == amd64_mtrrtomrt[i]) return(i); } return(-1); } static int amd64_mrt2mtrr(int flags, int oldval) { int val; if ((val = amd64_mtrrtype(flags)) == -1) return oldval & 0xff; return val & 0xff; } /* * Update running CPU(s) MTRRs to match the ranges in the descriptor * list. * * XXX Must be called with interrupts enabled. */ static void amd64_mrstore(struct mem_range_softc *sc) { #ifdef SMP /* * We should use ipi_all_but_self() to call other CPUs into a * locking gate, then call a target function to do this work. * The "proper" solution involves a generalised locking gate * implementation, not ready yet. */ smp_rendezvous(NULL, amd64_mrstoreone, NULL, (void *)sc); #else disable_intr(); /* disable interrupts */ amd64_mrstoreone((void *)sc); enable_intr(); #endif } /* * Update the current CPU's MTRRs with those represented in the * descriptor list. Note that we do this wholesale rather than * just stuffing one entry; this is simpler (but slower, of course). */ static void amd64_mrstoreone(void *arg) { struct mem_range_softc *sc = (struct mem_range_softc *)arg; struct mem_range_desc *mrd; u_int64_t omsrv, msrv; int i, j, msr; u_int cr4save; mrd = sc->mr_desc; cr4save = rcr4(); /* save cr4 */ if (cr4save & CR4_PGE) load_cr4(cr4save & ~CR4_PGE); load_cr0((rcr0() & ~CR0_NW) | CR0_CD); /* disable caches (CD = 1, NW = 0) */ wbinvd(); /* flush caches, TLBs */ - wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~0x800); /* disable MTRRs (E = 0) */ + wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE); /* disable MTRRs (E = 0) */ /* Set fixed-range MTRRs */ if (sc->mr_cap & MR686_FIXMTRR) { msr = MSR_MTRR64kBase; for (i = 0; i < (MTRR_N64K / 8); i++, msr++) { msrv = 0; omsrv = rdmsr(msr); for (j = 7; j >= 0; j--) { msrv = msrv << 8; msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8)); } wrmsr(msr, msrv); mrd += 8; } msr = MSR_MTRR16kBase; for (i = 0; i < (MTRR_N16K / 8); i++, msr++) { msrv = 0; omsrv = rdmsr(msr); for (j = 7; j >= 0; j--) { msrv = msrv << 8; msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8)); } wrmsr(msr, msrv); mrd += 8; } msr = MSR_MTRR4kBase; for (i = 0; i < (MTRR_N4K / 8); i++, msr++) { msrv = 0; omsrv = rdmsr(msr); for (j = 7; j >= 0; j--) { msrv = msrv << 8; msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8)); } wrmsr(msr, msrv); mrd += 8; } } /* Set remainder which must be variable MTRRs */ msr = MSR_MTRRVarBase; for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) { /* base/type register */ omsrv = rdmsr(msr); if (mrd->mr_flags & MDF_ACTIVE) { - msrv = mrd->mr_base & 0x000000fffffff000L; + msrv = mrd->mr_base & MTRR_PHYSBASE_PHYSBASE; msrv |= amd64_mrt2mtrr(mrd->mr_flags, omsrv); } else { msrv = 0; } wrmsr(msr, msrv); /* mask/active register */ if (mrd->mr_flags & MDF_ACTIVE) { - msrv = 0x800 | (~(mrd->mr_len - 1) & 0x000000fffffff000L); + msrv = MTRR_PHYSMASK_VALID | (~(mrd->mr_len - 1) & MTRR_PHYSMASK_PHYSMASK); } else { msrv = 0; } wrmsr(msr + 1, msrv); } wbinvd(); /* flush caches, TLBs */ - wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | 0x800); /* restore MTRR state */ + wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE); /* restore MTRR state */ load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* enable caches CD = 0 and NW = 0 */ load_cr4(cr4save); /* restore cr4 */ } /* * Hunt for the fixed MTRR referencing (addr) */ static struct mem_range_desc * amd64_mtrrfixsearch(struct mem_range_softc *sc, u_int64_t addr) { struct mem_range_desc *mrd; int i; for (i = 0, mrd = sc->mr_desc; i < (MTRR_N64K + MTRR_N16K + MTRR_N4K); i++, mrd++) if ((addr >= mrd->mr_base) && (addr < (mrd->mr_base + mrd->mr_len))) return(mrd); return(NULL); } /* * Try to satisfy the given range request by manipulating the fixed MTRRs that * cover low memory. * * Note that we try to be generous here; we'll bloat the range out to the * next higher/lower boundary to avoid the consumer having to know too much * about the mechanisms here. * * XXX note that this will have to be updated when we start supporting "busy" ranges. */ static int amd64_mrsetlow(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg) { struct mem_range_desc *first_md, *last_md, *curr_md; /* range check */ if (((first_md = amd64_mtrrfixsearch(sc, mrd->mr_base)) == NULL) || ((last_md = amd64_mtrrfixsearch(sc, mrd->mr_base + mrd->mr_len - 1)) == NULL)) return(EINVAL); /* check we aren't doing something risky */ if (!(mrd->mr_flags & MDF_FORCE)) for (curr_md = first_md; curr_md <= last_md; curr_md++) { if ((curr_md->mr_flags & MDF_ATTRMASK) == MDF_UNKNOWN) return (EACCES); } /* set flags, clear set-by-firmware flag */ for (curr_md = first_md; curr_md <= last_md; curr_md++) { curr_md->mr_flags = mrcopyflags(curr_md->mr_flags & ~MDF_FIRMWARE, mrd->mr_flags); bcopy(mrd->mr_owner, curr_md->mr_owner, sizeof(mrd->mr_owner)); } return(0); } /* * Modify/add a variable MTRR to satisfy the request. * * XXX needs to be updated to properly support "busy" ranges. */ static int amd64_mrsetvariable(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg) { struct mem_range_desc *curr_md, *free_md; int i; /* * Scan the currently active variable descriptors, look for * one we exactly match (straight takeover) and for possible * accidental overlaps. * Keep track of the first empty variable descriptor in case we * can't perform a takeover. */ i = (sc->mr_cap & MR686_FIXMTRR) ? MTRR_N64K + MTRR_N16K + MTRR_N4K : 0; curr_md = sc->mr_desc + i; free_md = NULL; for (; i < sc->mr_ndesc; i++, curr_md++) { if (curr_md->mr_flags & MDF_ACTIVE) { /* exact match? */ if ((curr_md->mr_base == mrd->mr_base) && (curr_md->mr_len == mrd->mr_len)) { /* whoops, owned by someone */ if (curr_md->mr_flags & MDF_BUSY) return(EBUSY); /* check we aren't doing something risky */ if (!(mrd->mr_flags & MDF_FORCE) && ((curr_md->mr_flags & MDF_ATTRMASK) == MDF_UNKNOWN)) return (EACCES); /* Ok, just hijack this entry */ free_md = curr_md; break; } /* non-exact overlap ? */ if (mroverlap(curr_md, mrd)) { /* between conflicting region types? */ if (amd64_mtrrconflict(curr_md->mr_flags, mrd->mr_flags)) return(EINVAL); } } else if (free_md == NULL) { free_md = curr_md; } } /* got somewhere to put it? */ if (free_md == NULL) return(ENOSPC); /* Set up new descriptor */ free_md->mr_base = mrd->mr_base; free_md->mr_len = mrd->mr_len; free_md->mr_flags = mrcopyflags(MDF_ACTIVE, mrd->mr_flags); bcopy(mrd->mr_owner, free_md->mr_owner, sizeof(mrd->mr_owner)); return(0); } /* * Handle requests to set memory range attributes by manipulating MTRRs. * */ static int amd64_mrset(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg) { struct mem_range_desc *targ; int error = 0; switch(*arg) { case MEMRANGE_SET_UPDATE: /* make sure that what's being asked for is even possible at all */ if (!mrvalid(mrd->mr_base, mrd->mr_len) || amd64_mtrrtype(mrd->mr_flags) == -1) return(EINVAL); #define FIXTOP ((MTRR_N64K * 0x10000) + (MTRR_N16K * 0x4000) + (MTRR_N4K * 0x1000)) /* are the "low memory" conditions applicable? */ if ((sc->mr_cap & MR686_FIXMTRR) && ((mrd->mr_base + mrd->mr_len) <= FIXTOP)) { if ((error = amd64_mrsetlow(sc, mrd, arg)) != 0) return(error); } else { /* it's time to play with variable MTRRs */ if ((error = amd64_mrsetvariable(sc, mrd, arg)) != 0) return(error); } break; case MEMRANGE_SET_REMOVE: if ((targ = mem_range_match(sc, mrd)) == NULL) return(ENOENT); if (targ->mr_flags & MDF_FIXACTIVE) return(EPERM); if (targ->mr_flags & MDF_BUSY) return(EBUSY); targ->mr_flags &= ~MDF_ACTIVE; targ->mr_owner[0] = 0; break; default: return(EOPNOTSUPP); } /* update the hardware */ amd64_mrstore(sc); amd64_mrfetch(sc); /* refetch to see where we're at */ return(0); } /* * Work out how many ranges we support, initialise storage for them, * fetch the initial settings. */ static void amd64_mrinit(struct mem_range_softc *sc) { struct mem_range_desc *mrd; int nmdesc = 0; int i; mtrrcap = rdmsr(MSR_MTRRcap); mtrrdef = rdmsr(MSR_MTRRdefType); /* For now, bail out if MTRRs are not enabled */ - if (!(mtrrdef & 0x800)) { + if (!(mtrrdef & MTRR_DEF_ENABLE)) { if (bootverbose) printf("CPU supports MTRRs but not enabled\n"); return; } - nmdesc = mtrrcap & 0xff; + nmdesc = mtrrcap & MTRR_CAP_VCNT; /* If fixed MTRRs supported and enabled */ - if ((mtrrcap & 0x100) && (mtrrdef & 0x400)) { + if ((mtrrcap & MTRR_CAP_FIXED) && (mtrrdef & MTRR_DEF_FIXED_ENABLE)) { sc->mr_cap = MR686_FIXMTRR; nmdesc += MTRR_N64K + MTRR_N16K + MTRR_N4K; } sc->mr_desc = (struct mem_range_desc *)malloc(nmdesc * sizeof(struct mem_range_desc), M_MEMDESC, M_WAITOK | M_ZERO); sc->mr_ndesc = nmdesc; mrd = sc->mr_desc; /* Populate the fixed MTRR entries' base/length */ if (sc->mr_cap & MR686_FIXMTRR) { for (i = 0; i < MTRR_N64K; i++, mrd++) { mrd->mr_base = i * 0x10000; mrd->mr_len = 0x10000; mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN | MDF_FIXACTIVE; } for (i = 0; i < MTRR_N16K; i++, mrd++) { mrd->mr_base = i * 0x4000 + 0x80000; mrd->mr_len = 0x4000; mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN | MDF_FIXACTIVE; } for (i = 0; i < MTRR_N4K; i++, mrd++) { mrd->mr_base = i * 0x1000 + 0xc0000; mrd->mr_len = 0x1000; mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN | MDF_FIXACTIVE; } } /* * Get current settings, anything set now is considered to have * been set by the firmware. (XXX has something already played here?) */ amd64_mrfetch(sc); mrd = sc->mr_desc; for (i = 0; i < sc->mr_ndesc; i++, mrd++) { if (mrd->mr_flags & MDF_ACTIVE) mrd->mr_flags |= MDF_FIRMWARE; } } /* * Initialise MTRRs on an AP after the BSP has run the init code. */ static void amd64_mrAPinit(struct mem_range_softc *sc) { amd64_mrstoreone((void *)sc); /* set MTRRs to match BSP */ wrmsr(MSR_MTRRdefType, mtrrdef); /* set MTRR behaviour to match BSP */ } static void amd64_mem_drvinit(void *unused) { if (mtrrs_disabled) return; if (!(cpu_feature & CPUID_MTRR)) return; if ((cpu_id & 0xf00) != 0x600 && (cpu_id & 0xf00) != 0xf00) return; if ((strcmp(cpu_vendor, "GenuineIntel") != 0) && (strcmp(cpu_vendor, "AuthenticAMD") != 0)) return; mem_range_softc.mr_op = &amd64_mrops; } SYSINIT(amd64memdev,SI_SUB_DRIVERS,SI_ORDER_FIRST,amd64_mem_drvinit,NULL) diff --git a/sys/amd64/include/specialreg.h b/sys/amd64/include/specialreg.h index 5771796af100..94d70adfb7ed 100644 --- a/sys/amd64/include/specialreg.h +++ b/sys/amd64/include/specialreg.h @@ -1,403 +1,418 @@ /*- * Copyright (c) 1991 The Regents of the University of California. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 * $FreeBSD$ */ #ifndef _MACHINE_SPECIALREG_H_ #define _MACHINE_SPECIALREG_H_ /* * Bits in 386 special registers: */ #define CR0_PE 0x00000001 /* Protected mode Enable */ #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ #define CR0_PG 0x80000000 /* PaGing enable */ /* * Bits in 486 special registers: */ #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ #define CR0_WP 0x00010000 /* Write Protect (honor page protect in all modes) */ #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ #define CR0_NW 0x20000000 /* Not Write-through */ #define CR0_CD 0x40000000 /* Cache Disable */ /* * Bits in PPro special registers */ #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ #define CR4_TSD 0x00000004 /* Time stamp disable */ #define CR4_DE 0x00000008 /* Debugging extensions */ #define CR4_PSE 0x00000010 /* Page size extensions */ #define CR4_PAE 0x00000020 /* Physical address extension */ #define CR4_MCE 0x00000040 /* Machine check enable */ #define CR4_PGE 0x00000080 /* Page global enable */ #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ /* * Bits in AMD64 special registers. EFER is 64 bits wide. */ #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ #define EFER_LMA 0x000000400 /* Long mode active (R) */ #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ /* * CPUID instruction features register */ #define CPUID_FPU 0x00000001 #define CPUID_VME 0x00000002 #define CPUID_DE 0x00000004 #define CPUID_PSE 0x00000008 #define CPUID_TSC 0x00000010 #define CPUID_MSR 0x00000020 #define CPUID_PAE 0x00000040 #define CPUID_MCE 0x00000080 #define CPUID_CX8 0x00000100 #define CPUID_APIC 0x00000200 #define CPUID_B10 0x00000400 #define CPUID_SEP 0x00000800 #define CPUID_MTRR 0x00001000 #define CPUID_PGE 0x00002000 #define CPUID_MCA 0x00004000 #define CPUID_CMOV 0x00008000 #define CPUID_PAT 0x00010000 #define CPUID_PSE36 0x00020000 #define CPUID_PSN 0x00040000 #define CPUID_CLFSH 0x00080000 #define CPUID_B20 0x00100000 #define CPUID_DS 0x00200000 #define CPUID_ACPI 0x00400000 #define CPUID_MMX 0x00800000 #define CPUID_FXSR 0x01000000 #define CPUID_SSE 0x02000000 #define CPUID_XMM 0x02000000 #define CPUID_SSE2 0x04000000 #define CPUID_SS 0x08000000 #define CPUID_HTT 0x10000000 #define CPUID_TM 0x20000000 #define CPUID_IA64 0x40000000 #define CPUID_PBE 0x80000000 #define CPUID2_SSE3 0x00000001 #define CPUID2_DTES64 0x00000004 #define CPUID2_MON 0x00000008 #define CPUID2_DS_CPL 0x00000010 #define CPUID2_VMX 0x00000020 #define CPUID2_SMX 0x00000040 #define CPUID2_EST 0x00000080 #define CPUID2_TM2 0x00000100 #define CPUID2_SSSE3 0x00000200 #define CPUID2_CNXTID 0x00000400 #define CPUID2_CX16 0x00002000 #define CPUID2_XTPR 0x00004000 #define CPUID2_PDCM 0x00008000 #define CPUID2_DCA 0x00040000 #define CPUID2_SSE41 0x00080000 #define CPUID2_SSE42 0x00100000 #define CPUID2_X2APIC 0x00200000 #define CPUID2_POPCNT 0x00800000 /* * Important bits in the AMD extended cpuid flags */ #define AMDID_SYSCALL 0x00000800 #define AMDID_MP 0x00080000 #define AMDID_NX 0x00100000 #define AMDID_EXT_MMX 0x00400000 #define AMDID_FFXSR 0x01000000 #define AMDID_PAGE1GB 0x04000000 #define AMDID_RDTSCP 0x08000000 #define AMDID_LM 0x20000000 #define AMDID_EXT_3DNOW 0x40000000 #define AMDID_3DNOW 0x80000000 #define AMDID2_LAHF 0x00000001 #define AMDID2_CMP 0x00000002 #define AMDID2_SVM 0x00000004 #define AMDID2_EXT_APIC 0x00000008 #define AMDID2_CR8 0x00000010 #define AMDID2_PREFETCH 0x00000100 /* * CPUID instruction 1 ebx info */ #define CPUID_BRAND_INDEX 0x000000ff #define CPUID_CLFUSH_SIZE 0x0000ff00 #define CPUID_HTT_CORES 0x00ff0000 #define CPUID_LOCAL_APIC_ID 0xff000000 /* * AMD extended function 8000_0008h ecx info */ #define AMDID_CMP_CORES 0x000000ff /* * Model-specific registers for the i386 family */ #define MSR_P5_MC_ADDR 0x000 #define MSR_P5_MC_TYPE 0x001 #define MSR_TSC 0x010 #define MSR_P5_CESR 0x011 #define MSR_P5_CTR0 0x012 #define MSR_P5_CTR1 0x013 #define MSR_IA32_PLATFORM_ID 0x017 #define MSR_APICBASE 0x01b #define MSR_EBL_CR_POWERON 0x02a #define MSR_TEST_CTL 0x033 #define MSR_BIOS_UPDT_TRIG 0x079 #define MSR_BBL_CR_D0 0x088 #define MSR_BBL_CR_D1 0x089 #define MSR_BBL_CR_D2 0x08a #define MSR_BIOS_SIGN 0x08b #define MSR_PERFCTR0 0x0c1 #define MSR_PERFCTR1 0x0c2 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ #define MSR_MTRRcap 0x0fe #define MSR_BBL_CR_ADDR 0x116 #define MSR_BBL_CR_DECC 0x118 #define MSR_BBL_CR_CTL 0x119 #define MSR_BBL_CR_TRIG 0x11a #define MSR_BBL_CR_BUSY 0x11b #define MSR_BBL_CR_CTL3 0x11e #define MSR_SYSENTER_CS_MSR 0x174 #define MSR_SYSENTER_ESP_MSR 0x175 #define MSR_SYSENTER_EIP_MSR 0x176 #define MSR_MCG_CAP 0x179 #define MSR_MCG_STATUS 0x17a #define MSR_MCG_CTL 0x17b #define MSR_EVNTSEL0 0x186 #define MSR_EVNTSEL1 0x187 #define MSR_THERM_CONTROL 0x19a #define MSR_THERM_INTERRUPT 0x19b #define MSR_THERM_STATUS 0x19c #define MSR_IA32_MISC_ENABLE 0x1a0 #define MSR_DEBUGCTLMSR 0x1d9 #define MSR_LASTBRANCHFROMIP 0x1db #define MSR_LASTBRANCHTOIP 0x1dc #define MSR_LASTINTFROMIP 0x1dd #define MSR_LASTINTTOIP 0x1de #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 #define MSR_MTRRVarBase 0x200 #define MSR_MTRR64kBase 0x250 #define MSR_MTRR16kBase 0x258 #define MSR_MTRR4kBase 0x268 #define MSR_PAT 0x277 #define MSR_MTRRdefType 0x2ff #define MSR_MC0_CTL 0x400 #define MSR_MC0_STATUS 0x401 #define MSR_MC0_ADDR 0x402 #define MSR_MC0_MISC 0x403 #define MSR_MC1_CTL 0x404 #define MSR_MC1_STATUS 0x405 #define MSR_MC1_ADDR 0x406 #define MSR_MC1_MISC 0x407 #define MSR_MC2_CTL 0x408 #define MSR_MC2_STATUS 0x409 #define MSR_MC2_ADDR 0x40a #define MSR_MC2_MISC 0x40b #define MSR_MC3_CTL 0x40c #define MSR_MC3_STATUS 0x40d #define MSR_MC3_ADDR 0x40e #define MSR_MC3_MISC 0x40f #define MSR_MC4_CTL 0x410 #define MSR_MC4_STATUS 0x411 #define MSR_MC4_ADDR 0x412 #define MSR_MC4_MISC 0x413 /* * Constants related to MSR's. */ #define APICBASE_RESERVED 0x000006ff #define APICBASE_BSP 0x00000100 #define APICBASE_ENABLED 0x00000800 #define APICBASE_ADDRESS 0xfffff000 /* * PAT modes. */ #define PAT_UNCACHEABLE 0x00 #define PAT_WRITE_COMBINING 0x01 #define PAT_WRITE_THROUGH 0x04 #define PAT_WRITE_PROTECTED 0x05 #define PAT_WRITE_BACK 0x06 #define PAT_UNCACHED 0x07 #define PAT_VALUE(i, m) ((long)(m) << (8 * (i))) #define PAT_MASK(i) PAT_VALUE(i, 0xff) /* * Constants related to MTRRs */ +#define MTRR_UNCACHEABLE 0x00 +#define MTRR_WRITE_COMBINING 0x01 +#define MTRR_WRITE_THROUGH 0x04 +#define MTRR_WRITE_PROTECTED 0x05 +#define MTRR_WRITE_BACK 0x06 #define MTRR_N64K 8 /* numbers of fixed-size entries */ #define MTRR_N16K 16 #define MTRR_N4K 64 +#define MTRR_CAP_WC 0x0000000000000400UL +#define MTRR_CAP_FIXED 0x0000000000000100UL +#define MTRR_CAP_VCNT 0x00000000000000ffUL +#define MTRR_DEF_ENABLE 0x0000000000000800UL +#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400UL +#define MTRR_DEF_TYPE 0x00000000000000ffUL +#define MTRR_PHYSBASE_PHYSBASE 0x000000fffffff000UL +#define MTRR_PHYSBASE_TYPE 0x00000000000000ffUL +#define MTRR_PHYSMASK_PHYSMASK 0x000000fffffff000UL +#define MTRR_PHYSMASK_VALID 0x0000000000000800UL /* Performance Control Register (5x86 only). */ #define PCR0 0x20 #define PCR0_RSTK 0x01 /* Enables return stack */ #define PCR0_BTB 0x02 /* Enables branch target buffer */ #define PCR0_LOOP 0x04 /* Enables loop */ #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to serialize pipe. */ #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ #define PCR0_LSSER 0x80 /* Disable reorder */ /* Device Identification Registers */ #define DIR0 0xfe #define DIR1 0xff /* * The following four 3-byte registers control the non-cacheable regions. * These registers must be written as three separate bytes. * * NCRx+0: A31-A24 of starting address * NCRx+1: A23-A16 of starting address * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. * * The non-cacheable region's starting address must be aligned to the * size indicated by the NCR_SIZE_xx field. */ #define NCR1 0xc4 #define NCR2 0xc7 #define NCR3 0xca #define NCR4 0xcd #define NCR_SIZE_0K 0 #define NCR_SIZE_4K 1 #define NCR_SIZE_8K 2 #define NCR_SIZE_16K 3 #define NCR_SIZE_32K 4 #define NCR_SIZE_64K 5 #define NCR_SIZE_128K 6 #define NCR_SIZE_256K 7 #define NCR_SIZE_512K 8 #define NCR_SIZE_1M 9 #define NCR_SIZE_2M 10 #define NCR_SIZE_4M 11 #define NCR_SIZE_8M 12 #define NCR_SIZE_16M 13 #define NCR_SIZE_32M 14 #define NCR_SIZE_4G 15 /* * The address region registers are used to specify the location and * size for the eight address regions. * * ARRx + 0: A31-A24 of start address * ARRx + 1: A23-A16 of start address * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx */ #define ARR0 0xc4 #define ARR1 0xc7 #define ARR2 0xca #define ARR3 0xcd #define ARR4 0xd0 #define ARR5 0xd3 #define ARR6 0xd6 #define ARR7 0xd9 #define ARR_SIZE_0K 0 #define ARR_SIZE_4K 1 #define ARR_SIZE_8K 2 #define ARR_SIZE_16K 3 #define ARR_SIZE_32K 4 #define ARR_SIZE_64K 5 #define ARR_SIZE_128K 6 #define ARR_SIZE_256K 7 #define ARR_SIZE_512K 8 #define ARR_SIZE_1M 9 #define ARR_SIZE_2M 10 #define ARR_SIZE_4M 11 #define ARR_SIZE_8M 12 #define ARR_SIZE_16M 13 #define ARR_SIZE_32M 14 #define ARR_SIZE_4G 15 /* * The region control registers specify the attributes associated with * the ARRx addres regions. */ #define RCR0 0xdc #define RCR1 0xdd #define RCR2 0xde #define RCR3 0xdf #define RCR4 0xe0 #define RCR5 0xe1 #define RCR6 0xe2 #define RCR7 0xe3 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ #define RCR_RCE 0x01 /* Enables caching for ARR7. */ #define RCR_WWO 0x02 /* Weak write ordering. */ #define RCR_WL 0x04 /* Weak locking. */ #define RCR_WG 0x08 /* Write gathering. */ #define RCR_WT 0x10 /* Write-through. */ #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ /* AMD Write Allocate Top-Of-Memory and Control Register */ #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ /* AMD64 MSR's */ #define MSR_EFER 0xc0000080 /* extended features */ #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ #define MSR_PERFEVSEL0 0xc0010000 #define MSR_PERFEVSEL1 0xc0010001 #define MSR_PERFEVSEL2 0xc0010002 #define MSR_PERFEVSEL3 0xc0010003 #undef MSR_PERFCTR0 #undef MSR_PERFCTR1 #define MSR_PERFCTR0 0xc0010004 #define MSR_PERFCTR1 0xc0010005 #define MSR_PERFCTR2 0xc0010006 #define MSR_PERFCTR3 0xc0010007 #define MSR_SYSCFG 0xc0010010 #define MSR_IORRBASE0 0xc0010016 #define MSR_IORRMASK0 0xc0010017 #define MSR_IORRBASE1 0xc0010018 #define MSR_IORRMASK1 0xc0010019 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ #endif /* !_MACHINE_SPECIALREG_H_ */ diff --git a/sys/i386/i386/i686_mem.c b/sys/i386/i386/i686_mem.c index 453932969e06..26f35425bf6b 100644 --- a/sys/i386/i386/i686_mem.c +++ b/sys/i386/i386/i686_mem.c @@ -1,620 +1,621 @@ /*- * Copyright (c) 1999 Michael Smith * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include /* * i686 memory range operations * * This code will probably be impenetrable without reference to the * Intel Pentium Pro documentation. */ static char *mem_owner_bios = "BIOS"; #define MR686_FIXMTRR (1<<0) #define mrwithin(mr, a) \ (((a) >= (mr)->mr_base) && ((a) < ((mr)->mr_base + (mr)->mr_len))) #define mroverlap(mra, mrb) \ (mrwithin(mra, mrb->mr_base) || mrwithin(mrb, mra->mr_base)) #define mrvalid(base, len) \ ((!(base & ((1 << 12) - 1))) && /* base is multiple of 4k */ \ ((len) >= (1 << 12)) && /* length is >= 4k */ \ powerof2((len)) && /* ... and power of two */ \ !((base) & ((len) - 1))) /* range is not discontiuous */ #define mrcopyflags(curr, new) (((curr) & ~MDF_ATTRMASK) | ((new) & MDF_ATTRMASK)) static int mtrrs_disabled; TUNABLE_INT("machdep.disable_mtrrs", &mtrrs_disabled); SYSCTL_INT(_machdep, OID_AUTO, disable_mtrrs, CTLFLAG_RDTUN, &mtrrs_disabled, 0, "Disable i686 MTRRs."); static void i686_mrinit(struct mem_range_softc *sc); static int i686_mrset(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg); static void i686_mrAPinit(struct mem_range_softc *sc); static struct mem_range_ops i686_mrops = { i686_mrinit, i686_mrset, i686_mrAPinit }; /* XXX for AP startup hook */ static u_int64_t mtrrcap, mtrrdef; static struct mem_range_desc *mem_range_match(struct mem_range_softc *sc, struct mem_range_desc *mrd); static void i686_mrfetch(struct mem_range_softc *sc); static int i686_mtrrtype(int flags); static int i686_mrt2mtrr(int flags, int oldval); static int i686_mtrrconflict(int flag1, int flag2); static void i686_mrstore(struct mem_range_softc *sc); static void i686_mrstoreone(void *arg); static struct mem_range_desc *i686_mtrrfixsearch(struct mem_range_softc *sc, u_int64_t addr); static int i686_mrsetlow(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg); static int i686_mrsetvariable(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg); /* i686 MTRR type to memory range type conversion */ static int i686_mtrrtomrt[] = { MDF_UNCACHEABLE, MDF_WRITECOMBINE, MDF_UNKNOWN, MDF_UNKNOWN, MDF_WRITETHROUGH, MDF_WRITEPROTECT, MDF_WRITEBACK }; #define MTRRTOMRTLEN (sizeof(i686_mtrrtomrt) / sizeof(i686_mtrrtomrt[0])) static int i686_mtrr2mrt(int val) { if (val < 0 || val >= MTRRTOMRTLEN) return MDF_UNKNOWN; return i686_mtrrtomrt[val]; } /* * i686 MTRR conflicts. Writeback and uncachable may overlap. */ static int i686_mtrrconflict(int flag1, int flag2) { flag1 &= MDF_ATTRMASK; flag2 &= MDF_ATTRMASK; if (flag1 == flag2 || (flag1 == MDF_WRITEBACK && flag2 == MDF_UNCACHEABLE) || (flag2 == MDF_WRITEBACK && flag1 == MDF_UNCACHEABLE)) return 0; return 1; } /* * Look for an exactly-matching range. */ static struct mem_range_desc * mem_range_match(struct mem_range_softc *sc, struct mem_range_desc *mrd) { struct mem_range_desc *cand; int i; for (i = 0, cand = sc->mr_desc; i < sc->mr_ndesc; i++, cand++) if ((cand->mr_base == mrd->mr_base) && (cand->mr_len == mrd->mr_len)) return(cand); return(NULL); } /* * Fetch the current mtrr settings from the current CPU (assumed to all * be in sync in the SMP case). Note that if we are here, we assume * that MTRRs are enabled, and we may or may not have fixed MTRRs. */ static void i686_mrfetch(struct mem_range_softc *sc) { struct mem_range_desc *mrd; u_int64_t msrv; int i, j, msr; mrd = sc->mr_desc; /* Get fixed-range MTRRs */ if (sc->mr_cap & MR686_FIXMTRR) { msr = MSR_MTRR64kBase; for (i = 0; i < (MTRR_N64K / 8); i++, msr++) { msrv = rdmsr(msr); for (j = 0; j < 8; j++, mrd++) { mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) | i686_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE; if (mrd->mr_owner[0] == 0) strcpy(mrd->mr_owner, mem_owner_bios); msrv = msrv >> 8; } } msr = MSR_MTRR16kBase; for (i = 0; i < (MTRR_N16K / 8); i++, msr++) { msrv = rdmsr(msr); for (j = 0; j < 8; j++, mrd++) { mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) | i686_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE; if (mrd->mr_owner[0] == 0) strcpy(mrd->mr_owner, mem_owner_bios); msrv = msrv >> 8; } } msr = MSR_MTRR4kBase; for (i = 0; i < (MTRR_N4K / 8); i++, msr++) { msrv = rdmsr(msr); for (j = 0; j < 8; j++, mrd++) { mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) | i686_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE; if (mrd->mr_owner[0] == 0) strcpy(mrd->mr_owner, mem_owner_bios); msrv = msrv >> 8; } } } /* Get remainder which must be variable MTRRs */ msr = MSR_MTRRVarBase; for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) { msrv = rdmsr(msr); mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) | - i686_mtrr2mrt(msrv & 0xff); - mrd->mr_base = msrv & 0x0000000ffffff000LL; + i686_mtrr2mrt(msrv & MTRR_PHYSBASE_TYPE); + mrd->mr_base = msrv & MTRR_PHYSBASE_PHYSBASE; msrv = rdmsr(msr + 1); - mrd->mr_flags = (msrv & 0x800) ? + mrd->mr_flags = (msrv & MTRR_PHYSMASK_VALID) ? (mrd->mr_flags | MDF_ACTIVE) : (mrd->mr_flags & ~MDF_ACTIVE); /* Compute the range from the mask. Ick. */ - mrd->mr_len = (~(msrv & 0x0000000ffffff000LL) & 0x0000000fffffffffLL) + 1; + mrd->mr_len = (~(msrv & MTRR_PHYSMASK_PHYSMASK) & + (MTRR_PHYSMASK_PHYSMASK | 0xfffLL)) + 1; if (!mrvalid(mrd->mr_base, mrd->mr_len)) mrd->mr_flags |= MDF_BOGUS; /* If unclaimed and active, must be the BIOS */ if ((mrd->mr_flags & MDF_ACTIVE) && (mrd->mr_owner[0] == 0)) strcpy(mrd->mr_owner, mem_owner_bios); } } /* * Return the MTRR memory type matching a region's flags */ static int i686_mtrrtype(int flags) { int i; flags &= MDF_ATTRMASK; for (i = 0; i < MTRRTOMRTLEN; i++) { if (i686_mtrrtomrt[i] == MDF_UNKNOWN) continue; if (flags == i686_mtrrtomrt[i]) return(i); } return(-1); } static int i686_mrt2mtrr(int flags, int oldval) { int val; if ((val = i686_mtrrtype(flags)) == -1) return oldval & 0xff; return val & 0xff; } /* * Update running CPU(s) MTRRs to match the ranges in the descriptor * list. * * XXX Must be called with interrupts enabled. */ static void i686_mrstore(struct mem_range_softc *sc) { #ifdef SMP /* * We should use ipi_all_but_self() to call other CPUs into a * locking gate, then call a target function to do this work. * The "proper" solution involves a generalised locking gate * implementation, not ready yet. */ smp_rendezvous(NULL, i686_mrstoreone, NULL, (void *)sc); #else disable_intr(); /* disable interrupts */ i686_mrstoreone((void *)sc); enable_intr(); #endif } /* * Update the current CPU's MTRRs with those represented in the * descriptor list. Note that we do this wholesale rather than * just stuffing one entry; this is simpler (but slower, of course). */ static void i686_mrstoreone(void *arg) { struct mem_range_softc *sc = (struct mem_range_softc *)arg; struct mem_range_desc *mrd; u_int64_t omsrv, msrv; int i, j, msr; u_int cr4save; mrd = sc->mr_desc; cr4save = rcr4(); /* save cr4 */ if (cr4save & CR4_PGE) load_cr4(cr4save & ~CR4_PGE); load_cr0((rcr0() & ~CR0_NW) | CR0_CD); /* disable caches (CD = 1, NW = 0) */ wbinvd(); /* flush caches, TLBs */ - wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~0x800); /* disable MTRRs (E = 0) */ + wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE); /* disable MTRRs (E = 0) */ /* Set fixed-range MTRRs */ if (sc->mr_cap & MR686_FIXMTRR) { msr = MSR_MTRR64kBase; for (i = 0; i < (MTRR_N64K / 8); i++, msr++) { msrv = 0; omsrv = rdmsr(msr); for (j = 7; j >= 0; j--) { msrv = msrv << 8; msrv |= i686_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8)); } wrmsr(msr, msrv); mrd += 8; } msr = MSR_MTRR16kBase; for (i = 0; i < (MTRR_N16K / 8); i++, msr++) { msrv = 0; omsrv = rdmsr(msr); for (j = 7; j >= 0; j--) { msrv = msrv << 8; msrv |= i686_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8)); } wrmsr(msr, msrv); mrd += 8; } msr = MSR_MTRR4kBase; for (i = 0; i < (MTRR_N4K / 8); i++, msr++) { msrv = 0; omsrv = rdmsr(msr); for (j = 7; j >= 0; j--) { msrv = msrv << 8; msrv |= i686_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8)); } wrmsr(msr, msrv); mrd += 8; } } /* Set remainder which must be variable MTRRs */ msr = MSR_MTRRVarBase; for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) { /* base/type register */ omsrv = rdmsr(msr); if (mrd->mr_flags & MDF_ACTIVE) { - msrv = mrd->mr_base & 0x0000000ffffff000LL; + msrv = mrd->mr_base & MTRR_PHYSBASE_PHYSBASE; msrv |= i686_mrt2mtrr(mrd->mr_flags, omsrv); } else { msrv = 0; } wrmsr(msr, msrv); /* mask/active register */ if (mrd->mr_flags & MDF_ACTIVE) { - msrv = 0x800 | (~(mrd->mr_len - 1) & 0x0000000ffffff000LL); + msrv = MTRR_PHYSMASK_VALID | (~(mrd->mr_len - 1) & MTRR_PHYSMASK_PHYSMASK); } else { msrv = 0; } wrmsr(msr + 1, msrv); } wbinvd(); /* flush caches, TLBs */ - wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | 0x800); /* restore MTRR state */ + wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE); /* restore MTRR state */ load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* enable caches CD = 0 and NW = 0 */ load_cr4(cr4save); /* restore cr4 */ } /* * Hunt for the fixed MTRR referencing (addr) */ static struct mem_range_desc * i686_mtrrfixsearch(struct mem_range_softc *sc, u_int64_t addr) { struct mem_range_desc *mrd; int i; for (i = 0, mrd = sc->mr_desc; i < (MTRR_N64K + MTRR_N16K + MTRR_N4K); i++, mrd++) if ((addr >= mrd->mr_base) && (addr < (mrd->mr_base + mrd->mr_len))) return(mrd); return(NULL); } /* * Try to satisfy the given range request by manipulating the fixed MTRRs that * cover low memory. * * Note that we try to be generous here; we'll bloat the range out to the * next higher/lower boundary to avoid the consumer having to know too much * about the mechanisms here. * * XXX note that this will have to be updated when we start supporting "busy" ranges. */ static int i686_mrsetlow(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg) { struct mem_range_desc *first_md, *last_md, *curr_md; /* range check */ if (((first_md = i686_mtrrfixsearch(sc, mrd->mr_base)) == NULL) || ((last_md = i686_mtrrfixsearch(sc, mrd->mr_base + mrd->mr_len - 1)) == NULL)) return(EINVAL); /* check we aren't doing something risky */ if (!(mrd->mr_flags & MDF_FORCE)) for (curr_md = first_md; curr_md <= last_md; curr_md++) { if ((curr_md->mr_flags & MDF_ATTRMASK) == MDF_UNKNOWN) return (EACCES); } /* set flags, clear set-by-firmware flag */ for (curr_md = first_md; curr_md <= last_md; curr_md++) { curr_md->mr_flags = mrcopyflags(curr_md->mr_flags & ~MDF_FIRMWARE, mrd->mr_flags); bcopy(mrd->mr_owner, curr_md->mr_owner, sizeof(mrd->mr_owner)); } return(0); } /* * Modify/add a variable MTRR to satisfy the request. * * XXX needs to be updated to properly support "busy" ranges. */ static int i686_mrsetvariable(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg) { struct mem_range_desc *curr_md, *free_md; int i; /* * Scan the currently active variable descriptors, look for * one we exactly match (straight takeover) and for possible * accidental overlaps. * Keep track of the first empty variable descriptor in case we * can't perform a takeover. */ i = (sc->mr_cap & MR686_FIXMTRR) ? MTRR_N64K + MTRR_N16K + MTRR_N4K : 0; curr_md = sc->mr_desc + i; free_md = NULL; for (; i < sc->mr_ndesc; i++, curr_md++) { if (curr_md->mr_flags & MDF_ACTIVE) { /* exact match? */ if ((curr_md->mr_base == mrd->mr_base) && (curr_md->mr_len == mrd->mr_len)) { /* whoops, owned by someone */ if (curr_md->mr_flags & MDF_BUSY) return(EBUSY); /* check we aren't doing something risky */ if (!(mrd->mr_flags & MDF_FORCE) && ((curr_md->mr_flags & MDF_ATTRMASK) == MDF_UNKNOWN)) return (EACCES); /* Ok, just hijack this entry */ free_md = curr_md; break; } /* non-exact overlap ? */ if (mroverlap(curr_md, mrd)) { /* between conflicting region types? */ if (i686_mtrrconflict(curr_md->mr_flags, mrd->mr_flags)) return(EINVAL); } } else if (free_md == NULL) { free_md = curr_md; } } /* got somewhere to put it? */ if (free_md == NULL) return(ENOSPC); /* Set up new descriptor */ free_md->mr_base = mrd->mr_base; free_md->mr_len = mrd->mr_len; free_md->mr_flags = mrcopyflags(MDF_ACTIVE, mrd->mr_flags); bcopy(mrd->mr_owner, free_md->mr_owner, sizeof(mrd->mr_owner)); return(0); } /* * Handle requests to set memory range attributes by manipulating MTRRs. * */ static int i686_mrset(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg) { struct mem_range_desc *targ; int error = 0; switch(*arg) { case MEMRANGE_SET_UPDATE: /* make sure that what's being asked for is even possible at all */ if (!mrvalid(mrd->mr_base, mrd->mr_len) || i686_mtrrtype(mrd->mr_flags) == -1) return(EINVAL); #define FIXTOP ((MTRR_N64K * 0x10000) + (MTRR_N16K * 0x4000) + (MTRR_N4K * 0x1000)) /* are the "low memory" conditions applicable? */ if ((sc->mr_cap & MR686_FIXMTRR) && ((mrd->mr_base + mrd->mr_len) <= FIXTOP)) { if ((error = i686_mrsetlow(sc, mrd, arg)) != 0) return(error); } else { /* it's time to play with variable MTRRs */ if ((error = i686_mrsetvariable(sc, mrd, arg)) != 0) return(error); } break; case MEMRANGE_SET_REMOVE: if ((targ = mem_range_match(sc, mrd)) == NULL) return(ENOENT); if (targ->mr_flags & MDF_FIXACTIVE) return(EPERM); if (targ->mr_flags & MDF_BUSY) return(EBUSY); targ->mr_flags &= ~MDF_ACTIVE; targ->mr_owner[0] = 0; break; default: return(EOPNOTSUPP); } /* update the hardware */ i686_mrstore(sc); i686_mrfetch(sc); /* refetch to see where we're at */ return(0); } /* * Work out how many ranges we support, initialise storage for them, * fetch the initial settings. */ static void i686_mrinit(struct mem_range_softc *sc) { struct mem_range_desc *mrd; int nmdesc = 0; int i; mtrrcap = rdmsr(MSR_MTRRcap); mtrrdef = rdmsr(MSR_MTRRdefType); /* For now, bail out if MTRRs are not enabled */ - if (!(mtrrdef & 0x800)) { + if (!(mtrrdef & MTRR_DEF_ENABLE)) { if (bootverbose) printf("CPU supports MTRRs but not enabled\n"); return; } - nmdesc = mtrrcap & 0xff; + nmdesc = mtrrcap & MTRR_CAP_VCNT; if (bootverbose) printf("Pentium Pro MTRR support enabled\n"); /* If fixed MTRRs supported and enabled */ - if ((mtrrcap & 0x100) && (mtrrdef & 0x400)) { + if ((mtrrcap & MTRR_CAP_FIXED) && (mtrrdef & MTRR_DEF_FIXED_ENABLE)) { sc->mr_cap = MR686_FIXMTRR; nmdesc += MTRR_N64K + MTRR_N16K + MTRR_N4K; } sc->mr_desc = (struct mem_range_desc *)malloc(nmdesc * sizeof(struct mem_range_desc), M_MEMDESC, M_WAITOK | M_ZERO); sc->mr_ndesc = nmdesc; mrd = sc->mr_desc; /* Populate the fixed MTRR entries' base/length */ if (sc->mr_cap & MR686_FIXMTRR) { for (i = 0; i < MTRR_N64K; i++, mrd++) { mrd->mr_base = i * 0x10000; mrd->mr_len = 0x10000; mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN | MDF_FIXACTIVE; } for (i = 0; i < MTRR_N16K; i++, mrd++) { mrd->mr_base = i * 0x4000 + 0x80000; mrd->mr_len = 0x4000; mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN | MDF_FIXACTIVE; } for (i = 0; i < MTRR_N4K; i++, mrd++) { mrd->mr_base = i * 0x1000 + 0xc0000; mrd->mr_len = 0x1000; mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN | MDF_FIXACTIVE; } } /* * Get current settings, anything set now is considered to have * been set by the firmware. (XXX has something already played here?) */ i686_mrfetch(sc); mrd = sc->mr_desc; for (i = 0; i < sc->mr_ndesc; i++, mrd++) { if (mrd->mr_flags & MDF_ACTIVE) mrd->mr_flags |= MDF_FIRMWARE; } } /* * Initialise MTRRs on an AP after the BSP has run the init code. */ static void i686_mrAPinit(struct mem_range_softc *sc) { i686_mrstoreone((void *)sc); /* set MTRRs to match BSP */ wrmsr(MSR_MTRRdefType, mtrrdef); /* set MTRR behaviour to match BSP */ } static void i686_mem_drvinit(void *unused) { /* Try for i686 MTRRs */ if (!mtrrs_disabled && (cpu_feature & CPUID_MTRR) && ((cpu_id & 0xf00) == 0x600 || (cpu_id & 0xf00) == 0xf00) && ((strcmp(cpu_vendor, "GenuineIntel") == 0) || (strcmp(cpu_vendor, "AuthenticAMD") == 0))) { mem_range_softc.mr_op = &i686_mrops; } } SYSINIT(i686memdev,SI_SUB_DRIVERS,SI_ORDER_FIRST,i686_mem_drvinit,NULL) diff --git a/sys/i386/include/specialreg.h b/sys/i386/include/specialreg.h index 24b686b17a8f..4e1f5e3b2edb 100644 --- a/sys/i386/include/specialreg.h +++ b/sys/i386/include/specialreg.h @@ -1,485 +1,500 @@ /*- * Copyright (c) 1991 The Regents of the University of California. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 * $FreeBSD$ */ #ifndef _MACHINE_SPECIALREG_H_ #define _MACHINE_SPECIALREG_H_ /* * Bits in 386 special registers: */ #define CR0_PE 0x00000001 /* Protected mode Enable */ #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ #define CR0_PG 0x80000000 /* PaGing enable */ /* * Bits in 486 special registers: */ #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ #define CR0_WP 0x00010000 /* Write Protect (honor page protect in all modes) */ #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ #define CR0_NW 0x20000000 /* Not Write-through */ #define CR0_CD 0x40000000 /* Cache Disable */ /* * Bits in PPro special registers */ #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ #define CR4_TSD 0x00000004 /* Time stamp disable */ #define CR4_DE 0x00000008 /* Debugging extensions */ #define CR4_PSE 0x00000010 /* Page size extensions */ #define CR4_PAE 0x00000020 /* Physical address extension */ #define CR4_MCE 0x00000040 /* Machine check enable */ #define CR4_PGE 0x00000080 /* Page global enable */ #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ /* * Bits in AMD64 special registers. EFER is 64 bits wide. */ #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ /* * CPUID instruction features register */ #define CPUID_FPU 0x00000001 #define CPUID_VME 0x00000002 #define CPUID_DE 0x00000004 #define CPUID_PSE 0x00000008 #define CPUID_TSC 0x00000010 #define CPUID_MSR 0x00000020 #define CPUID_PAE 0x00000040 #define CPUID_MCE 0x00000080 #define CPUID_CX8 0x00000100 #define CPUID_APIC 0x00000200 #define CPUID_B10 0x00000400 #define CPUID_SEP 0x00000800 #define CPUID_MTRR 0x00001000 #define CPUID_PGE 0x00002000 #define CPUID_MCA 0x00004000 #define CPUID_CMOV 0x00008000 #define CPUID_PAT 0x00010000 #define CPUID_PSE36 0x00020000 #define CPUID_PSN 0x00040000 #define CPUID_CLFSH 0x00080000 #define CPUID_B20 0x00100000 #define CPUID_DS 0x00200000 #define CPUID_ACPI 0x00400000 #define CPUID_MMX 0x00800000 #define CPUID_FXSR 0x01000000 #define CPUID_SSE 0x02000000 #define CPUID_XMM 0x02000000 #define CPUID_SSE2 0x04000000 #define CPUID_SS 0x08000000 #define CPUID_HTT 0x10000000 #define CPUID_TM 0x20000000 #define CPUID_IA64 0x40000000 #define CPUID_PBE 0x80000000 #define CPUID2_SSE3 0x00000001 #define CPUID2_MON 0x00000008 #define CPUID2_DS_CPL 0x00000010 #define CPUID2_VMX 0x00000020 #define CPUID2_SMX 0x00000040 #define CPUID2_EST 0x00000080 #define CPUID2_TM2 0x00000100 #define CPUID2_SSSE3 0x00000200 #define CPUID2_CNXTID 0x00000400 #define CPUID2_CX16 0x00002000 #define CPUID2_XTPR 0x00004000 #define CPUID2_PDCM 0x00008000 #define CPUID2_DCA 0x00040000 /* * Important bits in the AMD extended cpuid flags */ #define AMDID_SYSCALL 0x00000800 #define AMDID_MP 0x00080000 #define AMDID_NX 0x00100000 #define AMDID_EXT_MMX 0x00400000 #define AMDID_FFXSR 0x01000000 #define AMDID_RDTSCP 0x08000000 #define AMDID_LM 0x20000000 #define AMDID_EXT_3DNOW 0x40000000 #define AMDID_3DNOW 0x80000000 #define AMDID2_LAHF 0x00000001 #define AMDID2_CMP 0x00000002 #define AMDID2_SVM 0x00000004 #define AMDID2_EXT_APIC 0x00000008 #define AMDID2_CR8 0x00000010 #define AMDID2_PREFETCH 0x00000100 /* * CPUID instruction 1 ebx info */ #define CPUID_BRAND_INDEX 0x000000ff #define CPUID_CLFUSH_SIZE 0x0000ff00 #define CPUID_HTT_CORES 0x00ff0000 #define CPUID_LOCAL_APIC_ID 0xff000000 /* * AMD extended function 8000_0008h ecx info */ #define AMDID_CMP_CORES 0x000000ff /* * Model-specific registers for the i386 family */ #define MSR_P5_MC_ADDR 0x000 #define MSR_P5_MC_TYPE 0x001 #define MSR_TSC 0x010 #define MSR_P5_CESR 0x011 #define MSR_P5_CTR0 0x012 #define MSR_P5_CTR1 0x013 #define MSR_IA32_PLATFORM_ID 0x017 #define MSR_APICBASE 0x01b #define MSR_EBL_CR_POWERON 0x02a #define MSR_TEST_CTL 0x033 #define MSR_BIOS_UPDT_TRIG 0x079 #define MSR_BBL_CR_D0 0x088 #define MSR_BBL_CR_D1 0x089 #define MSR_BBL_CR_D2 0x08a #define MSR_BIOS_SIGN 0x08b #define MSR_PERFCTR0 0x0c1 #define MSR_PERFCTR1 0x0c2 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ #define MSR_MTRRcap 0x0fe #define MSR_BBL_CR_ADDR 0x116 #define MSR_BBL_CR_DECC 0x118 #define MSR_BBL_CR_CTL 0x119 #define MSR_BBL_CR_TRIG 0x11a #define MSR_BBL_CR_BUSY 0x11b #define MSR_BBL_CR_CTL3 0x11e #define MSR_SYSENTER_CS_MSR 0x174 #define MSR_SYSENTER_ESP_MSR 0x175 #define MSR_SYSENTER_EIP_MSR 0x176 #define MSR_MCG_CAP 0x179 #define MSR_MCG_STATUS 0x17a #define MSR_MCG_CTL 0x17b #define MSR_EVNTSEL0 0x186 #define MSR_EVNTSEL1 0x187 #define MSR_THERM_CONTROL 0x19a #define MSR_THERM_INTERRUPT 0x19b #define MSR_THERM_STATUS 0x19c #define MSR_IA32_MISC_ENABLE 0x1a0 #define MSR_DEBUGCTLMSR 0x1d9 #define MSR_LASTBRANCHFROMIP 0x1db #define MSR_LASTBRANCHTOIP 0x1dc #define MSR_LASTINTFROMIP 0x1dd #define MSR_LASTINTTOIP 0x1de #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 #define MSR_MTRRVarBase 0x200 #define MSR_MTRR64kBase 0x250 #define MSR_MTRR16kBase 0x258 #define MSR_MTRR4kBase 0x268 #define MSR_PAT 0x277 #define MSR_MTRRdefType 0x2ff #define MSR_MC0_CTL 0x400 #define MSR_MC0_STATUS 0x401 #define MSR_MC0_ADDR 0x402 #define MSR_MC0_MISC 0x403 #define MSR_MC1_CTL 0x404 #define MSR_MC1_STATUS 0x405 #define MSR_MC1_ADDR 0x406 #define MSR_MC1_MISC 0x407 #define MSR_MC2_CTL 0x408 #define MSR_MC2_STATUS 0x409 #define MSR_MC2_ADDR 0x40a #define MSR_MC2_MISC 0x40b #define MSR_MC3_CTL 0x40c #define MSR_MC3_STATUS 0x40d #define MSR_MC3_ADDR 0x40e #define MSR_MC3_MISC 0x40f #define MSR_MC4_CTL 0x410 #define MSR_MC4_STATUS 0x411 #define MSR_MC4_ADDR 0x412 #define MSR_MC4_MISC 0x413 /* * Constants related to MSR's. */ #define APICBASE_RESERVED 0x000006ff #define APICBASE_BSP 0x00000100 #define APICBASE_ENABLED 0x00000800 #define APICBASE_ADDRESS 0xfffff000 /* * PAT modes. */ #define PAT_UNCACHEABLE 0x00 #define PAT_WRITE_COMBINING 0x01 #define PAT_WRITE_THROUGH 0x04 #define PAT_WRITE_PROTECTED 0x05 #define PAT_WRITE_BACK 0x06 #define PAT_UNCACHED 0x07 #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) #define PAT_MASK(i) PAT_VALUE(i, 0xff) /* * Constants related to MTRRs */ +#define MTRR_UNCACHEABLE 0x00 +#define MTRR_WRITE_COMBINING 0x01 +#define MTRR_WRITE_THROUGH 0x04 +#define MTRR_WRITE_PROTECTED 0x05 +#define MTRR_WRITE_BACK 0x06 #define MTRR_N64K 8 /* numbers of fixed-size entries */ #define MTRR_N16K 16 #define MTRR_N4K 64 +#define MTRR_CAP_WC 0x0000000000000400ULL +#define MTRR_CAP_FIXED 0x0000000000000100ULL +#define MTRR_CAP_VCNT 0x00000000000000ffULL +#define MTRR_DEF_ENABLE 0x0000000000000800ULL +#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400ULL +#define MTRR_DEF_TYPE 0x00000000000000ffULL +#define MTRR_PHYSBASE_PHYSBASE 0x0000000ffffff000ULL +#define MTRR_PHYSBASE_TYPE 0x00000000000000ffULL +#define MTRR_PHYSMASK_PHYSMASK 0x0000000ffffff000ULL +#define MTRR_PHYSMASK_VALID 0x0000000000000800ULL /* * Cyrix configuration registers, accessible as IO ports. */ #define CCR0 0xc0 /* Configuration control register 0 */ #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is non-cacheable */ #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ #define CCR0_A20M 0x04 /* Enables A20M# input pin */ #define CCR0_KEN 0x08 /* Enables KEN# input pin */ #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold state */ #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set assoc */ #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ #define CCR1 0xc1 /* Configuration control register 1 */ #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ #define CCR1_SMI 0x02 /* Enables SMM pins */ #define CCR1_SMAC 0x04 /* System management memory access */ #define CCR1_MMAC 0x08 /* Main memory access */ #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ #define CCR1_SM3 0x80 /* SMM address space address region 3 */ #define CCR2 0xc2 #define CCR2_WB 0x02 /* Enables WB cache interface pins */ #define CCR2_SADS 0x02 /* Slow ADS */ #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ #define CCR2_WT1 0x10 /* WT region 1 */ #define CCR2_WPR1 0x10 /* Write-protect region 1 */ #define CCR2_BARB 0x20 /* Flushes write-back cache when entering hold state. */ #define CCR2_BWRT 0x40 /* Enables burst write cycles */ #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ #define CCR3 0xc3 #define CCR3_SMILOCK 0x01 /* SMM register lock */ #define CCR3_NMI 0x02 /* Enables NMI during SMM */ #define CCR3_LINBRST 0x04 /* Linear address burst cycles */ #define CCR3_SMMMODE 0x08 /* SMM Mode */ #define CCR3_MAPEN0 0x10 /* Enables Map0 */ #define CCR3_MAPEN1 0x20 /* Enables Map1 */ #define CCR3_MAPEN2 0x40 /* Enables Map2 */ #define CCR3_MAPEN3 0x80 /* Enables Map3 */ #define CCR4 0xe8 #define CCR4_IOMASK 0x07 #define CCR4_MEM 0x08 /* Enables momory bypassing */ #define CCR4_DTE 0x10 /* Enables directory table entry cache */ #define CCR4_FASTFPE 0x20 /* Fast FPU exception */ #define CCR4_CPUID 0x80 /* Enables CPUID instruction */ #define CCR5 0xe9 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ #define CCR5_LBR1 0x10 /* Local bus region 1 */ #define CCR5_ARREN 0x20 /* Enables ARR region */ #define CCR6 0xea #define CCR7 0xeb /* Performance Control Register (5x86 only). */ #define PCR0 0x20 #define PCR0_RSTK 0x01 /* Enables return stack */ #define PCR0_BTB 0x02 /* Enables branch target buffer */ #define PCR0_LOOP 0x04 /* Enables loop */ #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to serialize pipe. */ #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ #define PCR0_LSSER 0x80 /* Disable reorder */ /* Device Identification Registers */ #define DIR0 0xfe #define DIR1 0xff /* * The following four 3-byte registers control the non-cacheable regions. * These registers must be written as three separate bytes. * * NCRx+0: A31-A24 of starting address * NCRx+1: A23-A16 of starting address * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. * * The non-cacheable region's starting address must be aligned to the * size indicated by the NCR_SIZE_xx field. */ #define NCR1 0xc4 #define NCR2 0xc7 #define NCR3 0xca #define NCR4 0xcd #define NCR_SIZE_0K 0 #define NCR_SIZE_4K 1 #define NCR_SIZE_8K 2 #define NCR_SIZE_16K 3 #define NCR_SIZE_32K 4 #define NCR_SIZE_64K 5 #define NCR_SIZE_128K 6 #define NCR_SIZE_256K 7 #define NCR_SIZE_512K 8 #define NCR_SIZE_1M 9 #define NCR_SIZE_2M 10 #define NCR_SIZE_4M 11 #define NCR_SIZE_8M 12 #define NCR_SIZE_16M 13 #define NCR_SIZE_32M 14 #define NCR_SIZE_4G 15 /* * The address region registers are used to specify the location and * size for the eight address regions. * * ARRx + 0: A31-A24 of start address * ARRx + 1: A23-A16 of start address * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx */ #define ARR0 0xc4 #define ARR1 0xc7 #define ARR2 0xca #define ARR3 0xcd #define ARR4 0xd0 #define ARR5 0xd3 #define ARR6 0xd6 #define ARR7 0xd9 #define ARR_SIZE_0K 0 #define ARR_SIZE_4K 1 #define ARR_SIZE_8K 2 #define ARR_SIZE_16K 3 #define ARR_SIZE_32K 4 #define ARR_SIZE_64K 5 #define ARR_SIZE_128K 6 #define ARR_SIZE_256K 7 #define ARR_SIZE_512K 8 #define ARR_SIZE_1M 9 #define ARR_SIZE_2M 10 #define ARR_SIZE_4M 11 #define ARR_SIZE_8M 12 #define ARR_SIZE_16M 13 #define ARR_SIZE_32M 14 #define ARR_SIZE_4G 15 /* * The region control registers specify the attributes associated with * the ARRx addres regions. */ #define RCR0 0xdc #define RCR1 0xdd #define RCR2 0xde #define RCR3 0xdf #define RCR4 0xe0 #define RCR5 0xe1 #define RCR6 0xe2 #define RCR7 0xe3 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ #define RCR_RCE 0x01 /* Enables caching for ARR7. */ #define RCR_WWO 0x02 /* Weak write ordering. */ #define RCR_WL 0x04 /* Weak locking. */ #define RCR_WG 0x08 /* Write gathering. */ #define RCR_WT 0x10 /* Write-through. */ #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ /* AMD Write Allocate Top-Of-Memory and Control Register */ #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ /* AMD64 MSR's */ #define MSR_EFER 0xc0000080 /* extended features */ /* VIA ACE crypto featureset: for via_feature_rng */ #define VIA_HAS_RNG 1 /* cpu has RNG */ /* VIA ACE crypto featureset: for via_feature_xcrypt */ #define VIA_HAS_AES 1 /* cpu has AES */ #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ #define VIA_HAS_MM 4 /* cpu has RSA instructions */ #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ /* Centaur Extended Feature flags */ #define VIA_CPUID_HAS_RNG 0x000004 #define VIA_CPUID_DO_RNG 0x000008 #define VIA_CPUID_HAS_ACE 0x000040 #define VIA_CPUID_DO_ACE 0x000080 #define VIA_CPUID_HAS_ACE2 0x000100 #define VIA_CPUID_DO_ACE2 0x000200 #define VIA_CPUID_HAS_PHE 0x000400 #define VIA_CPUID_DO_PHE 0x000800 #define VIA_CPUID_HAS_PMM 0x001000 #define VIA_CPUID_DO_PMM 0x002000 /* VIA ACE xcrypt-* instruction context control options */ #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f #define VIA_CRYPT_CWLO_ALG_M 0x00000070 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 #define VIA_CRYPT_CWLO_NORMAL 0x00000000 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ #ifndef LOCORE static __inline u_char read_cyrix_reg(u_char reg) { outb(0x22, reg); return inb(0x23); } static __inline void write_cyrix_reg(u_char reg, u_char data) { outb(0x22, reg); outb(0x23, data); } #endif #endif /* !_MACHINE_SPECIALREG_H_ */