diff --git a/sys/dev/pci/pci_host_generic.c b/sys/dev/pci/pci_host_generic.c index 0c45f5d316ed..22b3ccdc17b1 100644 --- a/sys/dev/pci/pci_host_generic.c +++ b/sys/dev/pci/pci_host_generic.c @@ -1,544 +1,546 @@ /*- * Copyright (c) 2015, 2020 Ruslan Bukin * Copyright (c) 2014 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* Generic ECAM PCIe driver */ #include __FBSDID("$FreeBSD$"); #include "opt_platform.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "pcib_if.h" /* Forward prototypes */ static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes); static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, uint32_t val, int bytes); static int generic_pcie_maxslots(device_t dev); static int generic_pcie_read_ivar(device_t dev, device_t child, int index, uintptr_t *result); static int generic_pcie_write_ivar(device_t dev, device_t child, int index, uintptr_t value); int pci_host_generic_core_attach(device_t dev) { struct generic_pcie_core_softc *sc; uint64_t phys_base; uint64_t pci_base; uint64_t size; int error; int rid, tuple; sc = device_get_softc(dev); sc->dev = dev; /* Create the parent DMA tag to pass down the coherent flag */ error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1, 0, /* alignment, bounds */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ BUS_SPACE_MAXSIZE, /* maxsize */ BUS_SPACE_UNRESTRICTED, /* nsegments */ BUS_SPACE_MAXSIZE, /* maxsegsize */ sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->dmat); if (error != 0) return (error); rid = 0; sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->res == NULL) { device_printf(dev, "could not map memory.\n"); return (ENXIO); } sc->bst = rman_get_bustag(sc->res); sc->bsh = rman_get_bushandle(sc->res); sc->has_pmem = false; sc->pmem_rman.rm_type = RMAN_ARRAY; sc->pmem_rman.rm_descr = "PCIe Prefetch Memory"; sc->mem_rman.rm_type = RMAN_ARRAY; sc->mem_rman.rm_descr = "PCIe Memory"; sc->io_rman.rm_type = RMAN_ARRAY; sc->io_rman.rm_descr = "PCIe IO window"; /* Initialize rman and allocate memory regions */ error = rman_init(&sc->pmem_rman); if (error) { device_printf(dev, "rman_init() failed. error = %d\n", error); return (error); } error = rman_init(&sc->mem_rman); if (error) { device_printf(dev, "rman_init() failed. error = %d\n", error); return (error); } error = rman_init(&sc->io_rman); if (error) { device_printf(dev, "rman_init() failed. error = %d\n", error); return (error); } for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { phys_base = sc->ranges[tuple].phys_base; pci_base = sc->ranges[tuple].pci_base; size = sc->ranges[tuple].size; if (phys_base == 0 || size == 0) continue; /* empty range element */ switch (FLAG_TYPE(sc->ranges[tuple].flags)) { case FLAG_TYPE_PMEM: sc->has_pmem = true; error = rman_manage_region(&sc->pmem_rman, pci_base, pci_base + size - 1); break; case FLAG_TYPE_MEM: error = rman_manage_region(&sc->mem_rman, pci_base, pci_base + size - 1); break; case FLAG_TYPE_IO: error = rman_manage_region(&sc->io_rman, pci_base, pci_base + size - 1); break; default: continue; } if (error) { device_printf(dev, "rman_manage_region() failed." "error = %d\n", error); rman_fini(&sc->pmem_rman); rman_fini(&sc->mem_rman); rman_fini(&sc->io_rman); return (error); } } return (0); } static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes) { struct generic_pcie_core_softc *sc; bus_space_handle_t h; bus_space_tag_t t; uint64_t offset; uint32_t data; sc = device_get_softc(dev); if ((bus < sc->bus_start) || (bus > sc->bus_end)) return (~0U); if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) return (~0U); + if ((sc->quirks & PCIE_ECAM_DESIGNWARE_QUIRK) && bus == 0 && slot > 0) + return (~0U); offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg); t = sc->bst; h = sc->bsh; switch (bytes) { case 1: data = bus_space_read_1(t, h, offset); break; case 2: data = le16toh(bus_space_read_2(t, h, offset)); break; case 4: data = le32toh(bus_space_read_4(t, h, offset)); break; default: return (~0U); } return (data); } static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, uint32_t val, int bytes) { struct generic_pcie_core_softc *sc; bus_space_handle_t h; bus_space_tag_t t; uint64_t offset; sc = device_get_softc(dev); if ((bus < sc->bus_start) || (bus > sc->bus_end)) return; if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) return; offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg); t = sc->bst; h = sc->bsh; switch (bytes) { case 1: bus_space_write_1(t, h, offset, val); break; case 2: bus_space_write_2(t, h, offset, htole16(val)); break; case 4: bus_space_write_4(t, h, offset, htole32(val)); break; default: return; } } static int generic_pcie_maxslots(device_t dev) { return (31); /* max slots per bus acc. to standard */ } static int generic_pcie_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) { struct generic_pcie_core_softc *sc; sc = device_get_softc(dev); if (index == PCIB_IVAR_BUS) { *result = sc->bus_start; return (0); } if (index == PCIB_IVAR_DOMAIN) { *result = sc->ecam; return (0); } if (bootverbose) device_printf(dev, "ERROR: Unknown index %d.\n", index); return (ENOENT); } static int generic_pcie_write_ivar(device_t dev, device_t child, int index, uintptr_t value) { return (ENOENT); } static struct rman * generic_pcie_rman(struct generic_pcie_core_softc *sc, int type, int flags) { switch (type) { case SYS_RES_IOPORT: return (&sc->io_rman); case SYS_RES_MEMORY: if (sc->has_pmem && (flags & RF_PREFETCHABLE) != 0) return (&sc->pmem_rman); return (&sc->mem_rman); default: break; } return (NULL); } int pci_host_generic_core_release_resource(device_t dev, device_t child, int type, int rid, struct resource *res) { struct generic_pcie_core_softc *sc; struct rman *rm; sc = device_get_softc(dev); #if defined(NEW_PCIB) && defined(PCI_RES_BUS) if (type == PCI_RES_BUS) { return (pci_domain_release_bus(sc->ecam, child, rid, res)); } #endif rm = generic_pcie_rman(sc, type, rman_get_flags(res)); if (rm != NULL) { KASSERT(rman_is_region_manager(res, rm), ("rman mismatch")); rman_release_resource(res); } return (bus_generic_release_resource(dev, child, type, rid, res)); } static bool generic_pcie_translate_resource(device_t dev, int type, rman_res_t start, rman_res_t end, rman_res_t *new_start, rman_res_t *new_end) { struct generic_pcie_core_softc *sc; uint64_t phys_base; uint64_t pci_base; uint64_t size; int i, space; bool found; sc = device_get_softc(dev); /* Translate the address from a PCI address to a physical address */ switch (type) { case SYS_RES_IOPORT: case SYS_RES_MEMORY: found = false; for (i = 0; i < MAX_RANGES_TUPLES; i++) { pci_base = sc->ranges[i].pci_base; phys_base = sc->ranges[i].phys_base; size = sc->ranges[i].size; if (start < pci_base || start >= pci_base + size) continue; switch (FLAG_TYPE(sc->ranges[i].flags)) { case FLAG_TYPE_MEM: case FLAG_TYPE_PMEM: space = SYS_RES_MEMORY; break; case FLAG_TYPE_IO: space = SYS_RES_IOPORT; break; default: space = -1; continue; } if (type == space) { *new_start = start - pci_base + phys_base; *new_end = end - pci_base + phys_base; found = true; break; } } break; default: /* No translation for non-memory types */ *new_start = start; *new_end = end; found = true; break; } return (found); } struct resource * pci_host_generic_core_alloc_resource(device_t dev, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { struct generic_pcie_core_softc *sc; struct resource *res; struct rman *rm; rman_res_t phys_start, phys_end; sc = device_get_softc(dev); #if defined(NEW_PCIB) && defined(PCI_RES_BUS) if (type == PCI_RES_BUS) { return (pci_domain_alloc_bus(sc->ecam, child, rid, start, end, count, flags)); } #endif rm = generic_pcie_rman(sc, type, flags); if (rm == NULL) return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, start, end, count, flags)); /* Translate the address from a PCI address to a physical address */ if (!generic_pcie_translate_resource(dev, type, start, end, &phys_start, &phys_end)) { device_printf(dev, "Failed to translate resource %jx-%jx type %x for %s\n", (uintmax_t)start, (uintmax_t)end, type, device_get_nameunit(child)); return (NULL); } if (bootverbose) { device_printf(dev, "rman_reserve_resource: start=%#jx, end=%#jx, count=%#jx\n", start, end, count); } res = rman_reserve_resource(rm, start, end, count, flags, child); if (res == NULL) goto fail; rman_set_rid(res, *rid); if (flags & RF_ACTIVE) if (bus_activate_resource(child, type, *rid, res)) { rman_release_resource(res); goto fail; } return (res); fail: device_printf(dev, "%s FAIL: type=%d, rid=%d, " "start=%016jx, end=%016jx, count=%016jx, flags=%x\n", __func__, type, *rid, start, end, count, flags); return (NULL); } static int generic_pcie_activate_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct generic_pcie_core_softc *sc; rman_res_t start, end; int res; sc = device_get_softc(dev); if ((res = rman_activate_resource(r)) != 0) return (res); start = rman_get_start(r); end = rman_get_end(r); if (!generic_pcie_translate_resource(dev, type, start, end, &start, &end)) return (EINVAL); rman_set_start(r, start); rman_set_end(r, end); return (BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child, type, rid, r)); } static int generic_pcie_deactivate_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { int res; if ((res = rman_deactivate_resource(r)) != 0) return (res); switch (type) { case SYS_RES_IOPORT: case SYS_RES_MEMORY: case SYS_RES_IRQ: res = BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child, type, rid, r); break; default: break; } return (res); } static int generic_pcie_adjust_resource(device_t dev, device_t child, int type, struct resource *res, rman_res_t start, rman_res_t end) { struct generic_pcie_core_softc *sc; struct rman *rm; sc = device_get_softc(dev); #if defined(NEW_PCIB) && defined(PCI_RES_BUS) if (type == PCI_RES_BUS) return (pci_domain_adjust_bus(sc->ecam, child, res, start, end)); #endif rm = generic_pcie_rman(sc, type, rman_get_flags(res)); if (rm != NULL) return (rman_adjust_resource(res, start, end)); return (bus_generic_adjust_resource(dev, child, type, res, start, end)); } static bus_dma_tag_t generic_pcie_get_dma_tag(device_t dev, device_t child) { struct generic_pcie_core_softc *sc; sc = device_get_softc(dev); return (sc->dmat); } static device_method_t generic_pcie_methods[] = { DEVMETHOD(device_attach, pci_host_generic_core_attach), DEVMETHOD(bus_read_ivar, generic_pcie_read_ivar), DEVMETHOD(bus_write_ivar, generic_pcie_write_ivar), DEVMETHOD(bus_alloc_resource, pci_host_generic_core_alloc_resource), DEVMETHOD(bus_adjust_resource, generic_pcie_adjust_resource), DEVMETHOD(bus_activate_resource, generic_pcie_activate_resource), DEVMETHOD(bus_deactivate_resource, generic_pcie_deactivate_resource), DEVMETHOD(bus_release_resource, pci_host_generic_core_release_resource), DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), DEVMETHOD(bus_get_dma_tag, generic_pcie_get_dma_tag), /* pcib interface */ DEVMETHOD(pcib_maxslots, generic_pcie_maxslots), DEVMETHOD(pcib_read_config, generic_pcie_read_config), DEVMETHOD(pcib_write_config, generic_pcie_write_config), DEVMETHOD_END }; DEFINE_CLASS_0(pcib, generic_pcie_core_driver, generic_pcie_methods, sizeof(struct generic_pcie_core_softc)); diff --git a/sys/dev/pci/pci_host_generic.h b/sys/dev/pci/pci_host_generic.h index 36a12b9559ba..20117cbe32e3 100644 --- a/sys/dev/pci/pci_host_generic.h +++ b/sys/dev/pci/pci_host_generic.h @@ -1,98 +1,102 @@ /* * Copyright (c) 2015, 2020 Ruslan Bukin * Copyright (c) 2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * * $FreeBSD$ * */ #ifndef __PCI_HOST_GENERIC_H_ #define __PCI_HOST_GENERIC_H_ #include "pci_if.h" /* Assembling ECAM Configuration Address */ #define PCIE_BUS_SHIFT 20 #define PCIE_SLOT_SHIFT 15 #define PCIE_FUNC_SHIFT 12 #define PCIE_BUS_MASK 0xFF #define PCIE_SLOT_MASK 0x1F #define PCIE_FUNC_MASK 0x07 #define PCIE_REG_MASK 0xFFF #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ ((reg) & PCIE_REG_MASK)) #define MAX_RANGES_TUPLES 16 #define MIN_RANGES_TUPLES 2 struct pcie_range { uint64_t pci_base; uint64_t phys_base; uint64_t size; uint64_t flags; #define FLAG_TYPE(x) ((x) & FLAG_TYPE_MASK) #define FLAG_TYPE_MASK 0x3 #define FLAG_TYPE_INVALID 0x0 #define FLAG_TYPE_IO 0x1 #define FLAG_TYPE_MEM 0x2 #define FLAG_TYPE_PMEM 0x3 }; struct generic_pcie_core_softc { struct pcie_range ranges[MAX_RANGES_TUPLES]; int nranges; int coherent; bool has_pmem; struct rman pmem_rman; struct rman mem_rman; struct rman io_rman; struct resource *res; struct resource *res1; int bus_start; int bus_end; int ecam; bus_space_tag_t bst; bus_space_handle_t bsh; device_t dev; bus_space_handle_t ioh; bus_dma_tag_t dmat; + uint32_t quirks; }; +/* Quirks */ +#define PCIE_ECAM_DESIGNWARE_QUIRK (1 << 0) + DECLARE_CLASS(generic_pcie_core_driver); int pci_host_generic_core_attach(device_t); struct resource *pci_host_generic_core_alloc_resource(device_t, device_t, int, int *, rman_res_t, rman_res_t, rman_res_t, u_int); int pci_host_generic_core_release_resource(device_t, device_t, int, int, struct resource *); #endif /* __PCI_HOST_GENERIC_H_ */ diff --git a/sys/dev/pci/pci_host_generic_acpi.c b/sys/dev/pci/pci_host_generic_acpi.c index 763a84d2fd53..3c32abc5007a 100644 --- a/sys/dev/pci/pci_host_generic_acpi.c +++ b/sys/dev/pci/pci_host_generic_acpi.c @@ -1,462 +1,495 @@ /*- * Copyright (C) 2018 Cavium Inc. * Copyright (c) 2015 Ruslan Bukin * Copyright (c) 2014 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* Generic ECAM PCIe driver */ #include __FBSDID("$FreeBSD$"); #include "opt_platform.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "pcib_if.h" #include "acpi_bus_if.h" /* Assembling ECAM Configuration Address */ #define PCIE_BUS_SHIFT 20 #define PCIE_SLOT_SHIFT 15 #define PCIE_FUNC_SHIFT 12 #define PCIE_BUS_MASK 0xFF #define PCIE_SLOT_MASK 0x1F #define PCIE_FUNC_MASK 0x07 #define PCIE_REG_MASK 0xFFF #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ ((reg) & PCIE_REG_MASK)) #define PCI_IO_WINDOW_OFFSET 0x1000 #define SPACE_CODE_SHIFT 24 #define SPACE_CODE_MASK 0x3 #define SPACE_CODE_IO_SPACE 0x1 #define PROPS_CELL_SIZE 1 #define PCI_ADDR_CELL_SIZE 2 +static struct { + char oem_id[ACPI_OEM_ID_SIZE + 1]; + char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; + uint32_t quirks; +} pci_acpi_quirks[] = { + { "MRVL ", "CN9130 ", PCIE_ECAM_DESIGNWARE_QUIRK }, + { "MRVL ", "CN913X ", PCIE_ECAM_DESIGNWARE_QUIRK }, + { "MVEBU ", "ARMADA7K", PCIE_ECAM_DESIGNWARE_QUIRK }, + { "MVEBU ", "ARMADA8K", PCIE_ECAM_DESIGNWARE_QUIRK }, + { "MVEBU ", "CN9130 ", PCIE_ECAM_DESIGNWARE_QUIRK }, + { "MVEBU ", "CN9131 ", PCIE_ECAM_DESIGNWARE_QUIRK }, + { "MVEBU ", "CN9132 ", PCIE_ECAM_DESIGNWARE_QUIRK }, + { 0 }, +}; + /* Forward prototypes */ static int generic_pcie_acpi_probe(device_t dev); static ACPI_STATUS pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *, void *); static int generic_pcie_acpi_read_ivar(device_t, device_t, int, uintptr_t *); /* * generic_pcie_acpi_probe - look for root bridge flag */ static int generic_pcie_acpi_probe(device_t dev) { ACPI_DEVICE_INFO *devinfo; ACPI_HANDLE h; int root; if (acpi_disabled("pcib") || (h = acpi_get_handle(dev)) == NULL || ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo))) return (ENXIO); root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0; AcpiOsFree(devinfo); if (!root) return (ENXIO); device_set_desc(dev, "Generic PCI host controller"); return (BUS_PROBE_GENERIC); } /* * pci_host_generic_acpi_parse_resource - parse PCI memory, IO and bus spaces * 'produced' by this bridge */ static ACPI_STATUS pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *res, void *arg) { device_t dev = (device_t)arg; struct generic_pcie_acpi_softc *sc; struct rman *rm; rman_res_t min, max, off; int r; rm = NULL; sc = device_get_softc(dev); r = sc->base.nranges; switch (res->Type) { case ACPI_RESOURCE_TYPE_ADDRESS16: min = res->Data.Address16.Address.Minimum; max = res->Data.Address16.Address.Maximum; break; case ACPI_RESOURCE_TYPE_ADDRESS32: min = res->Data.Address32.Address.Minimum; max = res->Data.Address32.Address.Maximum; off = res->Data.Address32.Address.TranslationOffset; break; case ACPI_RESOURCE_TYPE_ADDRESS64: min = res->Data.Address64.Address.Minimum; max = res->Data.Address64.Address.Maximum; off = res->Data.Address64.Address.TranslationOffset; break; default: return (AE_OK); } /* Save detected ranges */ if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE || res->Data.Address.ResourceType == ACPI_IO_RANGE) { sc->base.ranges[r].pci_base = min; sc->base.ranges[r].phys_base = min + off; sc->base.ranges[r].size = max - min + 1; if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE) sc->base.ranges[r].flags |= FLAG_TYPE_MEM; else if (res->Data.Address.ResourceType == ACPI_IO_RANGE) sc->base.ranges[r].flags |= FLAG_TYPE_IO; sc->base.nranges++; } else if (res->Data.Address.ResourceType == ACPI_BUS_NUMBER_RANGE) { sc->base.bus_start = min; sc->base.bus_end = max; } return (AE_OK); } +static void +pci_host_acpi_get_oem_quirks(struct generic_pcie_acpi_softc *sc, + ACPI_TABLE_HEADER *hdr) +{ + int i; + + for (i = 0; pci_acpi_quirks[i].quirks; i++) { + if (memcmp(hdr->OemId, pci_acpi_quirks[i].oem_id, + ACPI_OEM_ID_SIZE) != 0) + continue; + if (memcmp(hdr->OemTableId, pci_acpi_quirks[i].oem_table_id, + ACPI_OEM_TABLE_ID_SIZE) != 0) + continue; + sc->base.quirks |= pci_acpi_quirks[i].quirks; + } +} + static int pci_host_acpi_get_ecam_resource(device_t dev) { struct generic_pcie_acpi_softc *sc; struct acpi_device *ad; struct resource_list *rl; ACPI_TABLE_HEADER *hdr; ACPI_MCFG_ALLOCATION *mcfg_entry, *mcfg_end; ACPI_HANDLE handle; ACPI_STATUS status; rman_res_t base, start, end; int found, val; sc = device_get_softc(dev); handle = acpi_get_handle(dev); /* Try MCFG first */ status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr); if (ACPI_SUCCESS(status)) { found = FALSE; mcfg_end = (ACPI_MCFG_ALLOCATION *)((char *)hdr + hdr->Length); mcfg_entry = (ACPI_MCFG_ALLOCATION *)((ACPI_TABLE_MCFG *)hdr + 1); while (mcfg_entry < mcfg_end && !found) { if (mcfg_entry->PciSegment == sc->base.ecam && mcfg_entry->StartBusNumber <= sc->base.bus_start && mcfg_entry->EndBusNumber >= sc->base.bus_start) found = TRUE; else mcfg_entry++; } if (found) { if (mcfg_entry->EndBusNumber < sc->base.bus_end) sc->base.bus_end = mcfg_entry->EndBusNumber; base = mcfg_entry->Address; } else { device_printf(dev, "MCFG exists, but does not have bus %d-%d\n", sc->base.bus_start, sc->base.bus_end); return (ENXIO); } + pci_host_acpi_get_oem_quirks(sc, hdr); } else { status = acpi_GetInteger(handle, "_CBA", &val); if (ACPI_SUCCESS(status)) base = val; else return (ENXIO); } /* add as MEM rid 0 */ ad = device_get_ivars(dev); rl = &ad->ad_rl; start = base + (sc->base.bus_start << PCIE_BUS_SHIFT); end = base + ((sc->base.bus_end + 1) << PCIE_BUS_SHIFT) - 1; resource_list_add(rl, SYS_RES_MEMORY, 0, start, end, end - start + 1); if (bootverbose) device_printf(dev, "ECAM for bus %d-%d at mem %jx-%jx\n", sc->base.bus_start, sc->base.bus_end, start, end); return (0); } int pci_host_generic_acpi_init(device_t dev) { struct generic_pcie_acpi_softc *sc; ACPI_HANDLE handle; ACPI_STATUS status; int error; sc = device_get_softc(dev); handle = acpi_get_handle(dev); /* Get Start bus number for the PCI host bus is from _BBN method */ status = acpi_GetInteger(handle, "_BBN", &sc->base.bus_start); if (ACPI_FAILURE(status)) { device_printf(dev, "No _BBN, using start bus 0\n"); sc->base.bus_start = 0; } sc->base.bus_end = 255; /* Get PCI Segment (domain) needed for MCFG lookup */ status = acpi_GetInteger(handle, "_SEG", &sc->base.ecam); if (ACPI_FAILURE(status)) { device_printf(dev, "No _SEG for PCI Bus, using segment 0\n"); sc->base.ecam = 0; } /* Bus decode ranges */ status = AcpiWalkResources(handle, "_CRS", pci_host_generic_acpi_parse_resource, (void *)dev); if (ACPI_FAILURE(status)) return (ENXIO); /* Coherency attribute */ if (ACPI_FAILURE(acpi_GetInteger(handle, "_CCA", &sc->base.coherent))) sc->base.coherent = 0; if (bootverbose) device_printf(dev, "Bus is%s cache-coherent\n", sc->base.coherent ? "" : " not"); /* add config space resource */ pci_host_acpi_get_ecam_resource(dev); acpi_pcib_fetch_prt(dev, &sc->ap_prt); error = pci_host_generic_core_attach(dev); if (error != 0) return (error); return (0); } static int pci_host_generic_acpi_attach(device_t dev) { int error; error = pci_host_generic_acpi_init(dev); if (error != 0) return (error); device_add_child(dev, "pci", -1); return (bus_generic_attach(dev)); } static int generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) { struct generic_pcie_acpi_softc *sc; sc = device_get_softc(dev); if (index == PCIB_IVAR_BUS) { *result = sc->base.bus_start; return (0); } if (index == PCIB_IVAR_DOMAIN) { *result = sc->base.ecam; return (0); } if (bootverbose) device_printf(dev, "ERROR: Unknown index %d.\n", index); return (ENOENT); } static int generic_pcie_acpi_route_interrupt(device_t bus, device_t dev, int pin) { struct generic_pcie_acpi_softc *sc; sc = device_get_softc(bus); return (acpi_pcib_route_interrupt(bus, dev, pin, &sc->ap_prt)); } static u_int generic_pcie_get_xref(device_t pci, device_t child) { struct generic_pcie_acpi_softc *sc; uintptr_t rid; u_int xref, devid; int err; sc = device_get_softc(pci); err = pcib_get_id(pci, child, PCI_ID_RID, &rid); if (err != 0) return (ACPI_MSI_XREF); err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid); if (err != 0) return (ACPI_MSI_XREF); return (xref); } static u_int generic_pcie_map_id(device_t pci, device_t child, uintptr_t *id) { struct generic_pcie_acpi_softc *sc; uintptr_t rid; u_int xref, devid; int err; sc = device_get_softc(pci); err = pcib_get_id(pci, child, PCI_ID_RID, &rid); if (err != 0) return (err); err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid); if (err == 0) *id = devid; else *id = rid; /* RID not in IORT, likely FW bug, ignore */ return (0); } static int generic_pcie_acpi_alloc_msi(device_t pci, device_t child, int count, int maxcount, int *irqs) { #if defined(INTRNG) return (intr_alloc_msi(pci, child, generic_pcie_get_xref(pci, child), count, maxcount, irqs)); #else return (ENXIO); #endif } static int generic_pcie_acpi_release_msi(device_t pci, device_t child, int count, int *irqs) { #if defined(INTRNG) return (intr_release_msi(pci, child, generic_pcie_get_xref(pci, child), count, irqs)); #else return (ENXIO); #endif } static int generic_pcie_acpi_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, uint32_t *data) { #if defined(INTRNG) return (intr_map_msi(pci, child, generic_pcie_get_xref(pci, child), irq, addr, data)); #else return (ENXIO); #endif } static int generic_pcie_acpi_alloc_msix(device_t pci, device_t child, int *irq) { #if defined(INTRNG) return (intr_alloc_msix(pci, child, generic_pcie_get_xref(pci, child), irq)); #else return (ENXIO); #endif } static int generic_pcie_acpi_release_msix(device_t pci, device_t child, int irq) { #if defined(INTRNG) return (intr_release_msix(pci, child, generic_pcie_get_xref(pci, child), irq)); #else return (ENXIO); #endif } static int generic_pcie_acpi_get_id(device_t pci, device_t child, enum pci_id_type type, uintptr_t *id) { if (type == PCI_ID_MSI) return (generic_pcie_map_id(pci, child, id)); else return (pcib_get_id(pci, child, type, id)); } static device_method_t generic_pcie_acpi_methods[] = { DEVMETHOD(device_probe, generic_pcie_acpi_probe), DEVMETHOD(device_attach, pci_host_generic_acpi_attach), DEVMETHOD(bus_read_ivar, generic_pcie_acpi_read_ivar), /* pcib interface */ DEVMETHOD(pcib_route_interrupt, generic_pcie_acpi_route_interrupt), DEVMETHOD(pcib_alloc_msi, generic_pcie_acpi_alloc_msi), DEVMETHOD(pcib_release_msi, generic_pcie_acpi_release_msi), DEVMETHOD(pcib_alloc_msix, generic_pcie_acpi_alloc_msix), DEVMETHOD(pcib_release_msix, generic_pcie_acpi_release_msix), DEVMETHOD(pcib_map_msi, generic_pcie_acpi_map_msi), DEVMETHOD(pcib_get_id, generic_pcie_acpi_get_id), DEVMETHOD_END }; DEFINE_CLASS_1(pcib, generic_pcie_acpi_driver, generic_pcie_acpi_methods, sizeof(struct generic_pcie_acpi_softc), generic_pcie_core_driver); static devclass_t generic_pcie_acpi_devclass; DRIVER_MODULE(pcib, acpi, generic_pcie_acpi_driver, generic_pcie_acpi_devclass, 0, 0); diff --git a/sys/dev/pci/pci_host_generic_fdt.c b/sys/dev/pci/pci_host_generic_fdt.c index 91ffaf7357b9..249637019137 100644 --- a/sys/dev/pci/pci_host_generic_fdt.c +++ b/sys/dev/pci/pci_host_generic_fdt.c @@ -1,485 +1,492 @@ /*- * Copyright (c) 2015 Ruslan Bukin * Copyright (c) 2014,2016 The FreeBSD Foundation * All rights reserved. * * This software was developed by Andrew Turner under * the sponsorship of the FreeBSD Foundation. * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* Generic ECAM PCIe driver FDT attachment */ #include __FBSDID("$FreeBSD$"); #include "opt_platform.h" #include #include #include #include #include #include #include #if defined(INTRNG) #include #endif #include #include #include #include #include #include #include #include #include #include #include "pcib_if.h" #define SPACE_CODE_SHIFT 24 #define SPACE_CODE_MASK 0x3 #define SPACE_CODE_IO_SPACE 0x1 #define PROPS_CELL_SIZE 1 #define PCI_ADDR_CELL_SIZE 2 struct pci_ofw_devinfo { STAILQ_ENTRY(pci_ofw_devinfo) pci_ofw_link; struct ofw_bus_devinfo di_dinfo; uint8_t slot; uint8_t func; uint8_t bus; }; /* Forward prototypes */ static int generic_pcie_fdt_probe(device_t dev); static int parse_pci_mem_ranges(device_t, struct generic_pcie_core_softc *); static int generic_pcie_ofw_bus_attach(device_t); static const struct ofw_bus_devinfo *generic_pcie_ofw_get_devinfo(device_t, device_t); static int generic_pcie_fdt_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) { device_set_desc(dev, "Generic PCI host controller"); return (BUS_PROBE_GENERIC); } if (ofw_bus_is_compatible(dev, "arm,gem5_pcie")) { device_set_desc(dev, "GEM5 PCIe host controller"); return (BUS_PROBE_DEFAULT); } return (ENXIO); } int pci_host_generic_setup_fdt(device_t dev) { struct generic_pcie_fdt_softc *sc; phandle_t node; int error; sc = device_get_softc(dev); STAILQ_INIT(&sc->pci_ofw_devlist); /* Retrieve 'ranges' property from FDT */ if (bootverbose) device_printf(dev, "parsing FDT for ECAM%d:\n", sc->base.ecam); if (parse_pci_mem_ranges(dev, &sc->base)) return (ENXIO); /* Attach OFW bus */ if (generic_pcie_ofw_bus_attach(dev) != 0) return (ENXIO); node = ofw_bus_get_node(dev); if (sc->base.coherent == 0) { sc->base.coherent = OF_hasprop(node, "dma-coherent"); } if (bootverbose) device_printf(dev, "Bus is%s cache-coherent\n", sc->base.coherent ? "" : " not"); /* TODO parse FDT bus ranges */ sc->base.bus_start = 0; sc->base.bus_end = 0xFF; /* * ofw_pcib uses device unit as PCI domain number. * Do the same. Some boards have multiple RCs handled * by different drivers, this ensures that there are * no collisions. */ sc->base.ecam = device_get_unit(dev); error = pci_host_generic_core_attach(dev); if (error != 0) return (error); + if (ofw_bus_is_compatible(dev, "marvell,armada8k-pcie-ecam") || + ofw_bus_is_compatible(dev, "socionext,synquacer-pcie-ecam") || + ofw_bus_is_compatible(dev, "snps,dw-pcie-ecam")) { + device_set_desc(dev, "Synopsys DesignWare PCIe Controller"); + sc->base.quirks |= PCIE_ECAM_DESIGNWARE_QUIRK; + } + ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t)); return (0); } int pci_host_generic_attach(device_t dev) { struct generic_pcie_fdt_softc *sc; int error; sc = device_get_softc(dev); error = pci_host_generic_setup_fdt(dev); if (error != 0) return (error); device_add_child(dev, "pci", -1); return (bus_generic_attach(dev)); } static int parse_pci_mem_ranges(device_t dev, struct generic_pcie_core_softc *sc) { pcell_t pci_addr_cells, parent_addr_cells; pcell_t attributes, size_cells; cell_t *base_ranges; int nbase_ranges; phandle_t node; int i, j, k; int tuple; node = ofw_bus_get_node(dev); OF_getencprop(node, "#address-cells", &pci_addr_cells, sizeof(pci_addr_cells)); OF_getencprop(node, "#size-cells", &size_cells, sizeof(size_cells)); OF_getencprop(OF_parent(node), "#address-cells", &parent_addr_cells, sizeof(parent_addr_cells)); if (parent_addr_cells > 2 || pci_addr_cells != 3 || size_cells > 2) { device_printf(dev, "Unexpected number of address or size cells in FDT\n"); return (ENXIO); } nbase_ranges = OF_getproplen(node, "ranges"); sc->nranges = nbase_ranges / sizeof(cell_t) / (parent_addr_cells + pci_addr_cells + size_cells); base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK); OF_getencprop(node, "ranges", base_ranges, nbase_ranges); for (i = 0, j = 0; i < sc->nranges; i++) { attributes = (base_ranges[j++] >> SPACE_CODE_SHIFT) & \ SPACE_CODE_MASK; if (attributes == SPACE_CODE_IO_SPACE) { sc->ranges[i].flags |= FLAG_TYPE_IO; } else { sc->ranges[i].flags |= FLAG_TYPE_MEM; } sc->ranges[i].pci_base = 0; for (k = 0; k < (pci_addr_cells - 1); k++) { sc->ranges[i].pci_base <<= 32; sc->ranges[i].pci_base |= base_ranges[j++]; } sc->ranges[i].phys_base = 0; for (k = 0; k < parent_addr_cells; k++) { sc->ranges[i].phys_base <<= 32; sc->ranges[i].phys_base |= base_ranges[j++]; } sc->ranges[i].size = 0; for (k = 0; k < size_cells; k++) { sc->ranges[i].size <<= 32; sc->ranges[i].size |= base_ranges[j++]; } } for (; i < MAX_RANGES_TUPLES; i++) { /* zero-fill remaining tuples to mark empty elements in array */ sc->ranges[i].pci_base = 0; sc->ranges[i].phys_base = 0; sc->ranges[i].size = 0; } if (bootverbose) { for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { device_printf(dev, "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n", sc->ranges[tuple].pci_base, sc->ranges[tuple].phys_base, sc->ranges[tuple].size); } } free(base_ranges, M_DEVBUF); return (0); } static int generic_pcie_fdt_route_interrupt(device_t bus, device_t dev, int pin) { struct generic_pcie_fdt_softc *sc; struct ofw_pci_register reg; uint32_t pintr, mintr[4]; phandle_t iparent; int intrcells; sc = device_get_softc(bus); pintr = pin; bzero(®, sizeof(reg)); reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr), &iparent); if (intrcells) { pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr); return (pintr); } device_printf(bus, "could not route pin %d for device %d.%d\n", pin, pci_get_slot(dev), pci_get_function(dev)); return (PCI_INVALID_IRQ); } static int generic_pcie_fdt_alloc_msi(device_t pci, device_t child, int count, int maxcount, int *irqs) { #if defined(INTRNG) phandle_t msi_parent; int err; err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, NULL); if (err != 0) return (err); return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, irqs)); #else return (ENXIO); #endif } static int generic_pcie_fdt_release_msi(device_t pci, device_t child, int count, int *irqs) { #if defined(INTRNG) phandle_t msi_parent; int err; err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, NULL); if (err != 0) return (err); return (intr_release_msi(pci, child, msi_parent, count, irqs)); #else return (ENXIO); #endif } static int generic_pcie_fdt_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, uint32_t *data) { #if defined(INTRNG) phandle_t msi_parent; int err; err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, NULL); if (err != 0) return (err); return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); #else return (ENXIO); #endif } static int generic_pcie_fdt_alloc_msix(device_t pci, device_t child, int *irq) { #if defined(INTRNG) phandle_t msi_parent; int err; err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, NULL); if (err != 0) return (err); return (intr_alloc_msix(pci, child, msi_parent, irq)); #else return (ENXIO); #endif } static int generic_pcie_fdt_release_msix(device_t pci, device_t child, int irq) { #if defined(INTRNG) phandle_t msi_parent; int err; err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, NULL); if (err != 0) return (err); return (intr_release_msix(pci, child, msi_parent, irq)); #else return (ENXIO); #endif } int generic_pcie_get_id(device_t pci, device_t child, enum pci_id_type type, uintptr_t *id) { phandle_t node; int err; uint32_t rid; uint16_t pci_rid; if (type != PCI_ID_MSI) return (pcib_get_id(pci, child, type, id)); node = ofw_bus_get_node(pci); pci_rid = pci_get_rid(child); err = ofw_bus_msimap(node, pci_rid, NULL, &rid); if (err != 0) return (err); *id = rid; return (0); } static const struct ofw_bus_devinfo * generic_pcie_ofw_get_devinfo(device_t bus, device_t child) { struct generic_pcie_fdt_softc *sc; struct pci_ofw_devinfo *di; uint8_t slot, func, busno; sc = device_get_softc(bus); slot = pci_get_slot(child); func = pci_get_function(child); busno = pci_get_bus(child); STAILQ_FOREACH(di, &sc->pci_ofw_devlist, pci_ofw_link) if (slot == di->slot && func == di->func && busno == di->bus) return (&di->di_dinfo); return (NULL); } /* Helper functions */ static int generic_pcie_ofw_bus_attach(device_t dev) { struct generic_pcie_fdt_softc *sc; struct pci_ofw_devinfo *di; phandle_t parent, node; pcell_t reg[5]; ssize_t len; sc = device_get_softc(dev); parent = ofw_bus_get_node(dev); if (parent == 0) return (0); /* Iterate through all bus subordinates */ for (node = OF_child(parent); node > 0; node = OF_peer(node)) { len = OF_getencprop(node, "reg", reg, sizeof(reg)); if (len != 5 * sizeof(pcell_t)) continue; /* Allocate and populate devinfo. */ di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO); if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { free(di, M_DEVBUF); continue; } di->func = OFW_PCI_PHYS_HI_FUNCTION(reg[0]); di->slot = OFW_PCI_PHYS_HI_DEVICE(reg[0]); di->bus = OFW_PCI_PHYS_HI_BUS(reg[0]); STAILQ_INSERT_TAIL(&sc->pci_ofw_devlist, di, pci_ofw_link); } return (0); } static device_method_t generic_pcie_fdt_methods[] = { DEVMETHOD(device_probe, generic_pcie_fdt_probe), DEVMETHOD(device_attach, pci_host_generic_attach), DEVMETHOD(bus_alloc_resource, pci_host_generic_core_alloc_resource), DEVMETHOD(bus_release_resource, pci_host_generic_core_release_resource), /* pcib interface */ DEVMETHOD(pcib_route_interrupt, generic_pcie_fdt_route_interrupt), DEVMETHOD(pcib_alloc_msi, generic_pcie_fdt_alloc_msi), DEVMETHOD(pcib_release_msi, generic_pcie_fdt_release_msi), DEVMETHOD(pcib_alloc_msix, generic_pcie_fdt_alloc_msix), DEVMETHOD(pcib_release_msix, generic_pcie_fdt_release_msix), DEVMETHOD(pcib_map_msi, generic_pcie_fdt_map_msi), DEVMETHOD(pcib_get_id, generic_pcie_get_id), DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), DEVMETHOD(ofw_bus_get_devinfo, generic_pcie_ofw_get_devinfo), DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), DEVMETHOD_END }; DEFINE_CLASS_1(pcib, generic_pcie_fdt_driver, generic_pcie_fdt_methods, sizeof(struct generic_pcie_fdt_softc), generic_pcie_core_driver); static devclass_t generic_pcie_fdt_devclass; DRIVER_MODULE(pcib, simplebus, generic_pcie_fdt_driver, generic_pcie_fdt_devclass, 0, 0); DRIVER_MODULE(pcib, ofwbus, generic_pcie_fdt_driver, generic_pcie_fdt_devclass, 0, 0);