diff --git a/sys/dev/igc/igc_api.c b/sys/dev/igc/igc_api.c
index cad116c2395d..6aafc9898df8 100644
--- a/sys/dev/igc/igc_api.c
+++ b/sys/dev/igc/igc_api.c
@@ -1,735 +1,720 @@
/*-
* Copyright 2021 Intel Corp
* Copyright 2021 Rubicon Communications, LLC (Netgate)
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "igc_api.h"
/**
* igc_init_mac_params - Initialize MAC function pointers
* @hw: pointer to the HW structure
*
* This function initializes the function pointers for the MAC
* set of functions. Called by drivers or by igc_setup_init_funcs.
**/
s32 igc_init_mac_params(struct igc_hw *hw)
{
s32 ret_val = IGC_SUCCESS;
if (hw->mac.ops.init_params) {
ret_val = hw->mac.ops.init_params(hw);
if (ret_val) {
DEBUGOUT("MAC Initialization Error\n");
goto out;
}
} else {
DEBUGOUT("mac.init_mac_params was NULL\n");
ret_val = -IGC_ERR_CONFIG;
}
out:
return ret_val;
}
/**
* igc_init_nvm_params - Initialize NVM function pointers
* @hw: pointer to the HW structure
*
* This function initializes the function pointers for the NVM
* set of functions. Called by drivers or by igc_setup_init_funcs.
**/
s32 igc_init_nvm_params(struct igc_hw *hw)
{
s32 ret_val = IGC_SUCCESS;
if (hw->nvm.ops.init_params) {
ret_val = hw->nvm.ops.init_params(hw);
if (ret_val) {
DEBUGOUT("NVM Initialization Error\n");
goto out;
}
} else {
DEBUGOUT("nvm.init_nvm_params was NULL\n");
ret_val = -IGC_ERR_CONFIG;
}
out:
return ret_val;
}
/**
* igc_init_phy_params - Initialize PHY function pointers
* @hw: pointer to the HW structure
*
* This function initializes the function pointers for the PHY
* set of functions. Called by drivers or by igc_setup_init_funcs.
**/
s32 igc_init_phy_params(struct igc_hw *hw)
{
s32 ret_val = IGC_SUCCESS;
if (hw->phy.ops.init_params) {
ret_val = hw->phy.ops.init_params(hw);
if (ret_val) {
DEBUGOUT("PHY Initialization Error\n");
goto out;
}
} else {
DEBUGOUT("phy.init_phy_params was NULL\n");
ret_val = -IGC_ERR_CONFIG;
}
out:
return ret_val;
}
/**
* igc_set_mac_type - Sets MAC type
* @hw: pointer to the HW structure
*
* This function sets the mac type of the adapter based on the
* device ID stored in the hw structure.
* MUST BE FIRST FUNCTION CALLED (explicitly or through
* igc_setup_init_funcs()).
**/
s32 igc_set_mac_type(struct igc_hw *hw)
{
struct igc_mac_info *mac = &hw->mac;
s32 ret_val = IGC_SUCCESS;
DEBUGFUNC("igc_set_mac_type");
switch (hw->device_id) {
case IGC_DEV_ID_I225_LM:
case IGC_DEV_ID_I225_V:
case IGC_DEV_ID_I225_K:
case IGC_DEV_ID_I225_I:
case IGC_DEV_ID_I220_V:
case IGC_DEV_ID_I225_K2:
case IGC_DEV_ID_I225_LMVP:
case IGC_DEV_ID_I225_IT:
case IGC_DEV_ID_I226_LM:
case IGC_DEV_ID_I226_V:
case IGC_DEV_ID_I226_IT:
case IGC_DEV_ID_I221_V:
case IGC_DEV_ID_I226_BLANK_NVM:
case IGC_DEV_ID_I225_BLANK_NVM:
mac->type = igc_i225;
break;
default:
/* Should never have loaded on this device */
ret_val = -IGC_ERR_MAC_INIT;
break;
}
return ret_val;
}
/**
* igc_setup_init_funcs - Initializes function pointers
* @hw: pointer to the HW structure
* @init_device: true will initialize the rest of the function pointers
* getting the device ready for use. FALSE will only set
* MAC type and the function pointers for the other init
* functions. Passing FALSE will not generate any hardware
* reads or writes.
*
* This function must be called by a driver in order to use the rest
* of the 'shared' code files. Called by drivers only.
**/
s32 igc_setup_init_funcs(struct igc_hw *hw, bool init_device)
{
s32 ret_val;
/* Can't do much good without knowing the MAC type. */
ret_val = igc_set_mac_type(hw);
if (ret_val) {
DEBUGOUT("ERROR: MAC type could not be set properly.\n");
goto out;
}
if (!hw->hw_addr) {
DEBUGOUT("ERROR: Registers not mapped\n");
ret_val = -IGC_ERR_CONFIG;
goto out;
}
/*
* Init function pointers to generic implementations. We do this first
* allowing a driver module to override it afterward.
*/
igc_init_mac_ops_generic(hw);
igc_init_phy_ops_generic(hw);
igc_init_nvm_ops_generic(hw);
/*
* Set up the init function pointers. These are functions within the
* adapter family file that sets up function pointers for the rest of
* the functions in that family.
*/
switch (hw->mac.type) {
case igc_i225:
igc_init_function_pointers_i225(hw);
break;
default:
DEBUGOUT("Hardware not supported\n");
ret_val = -IGC_ERR_CONFIG;
break;
}
/*
* Initialize the rest of the function pointers. These require some
* register reads/writes in some cases.
*/
if (!(ret_val) && init_device) {
ret_val = igc_init_mac_params(hw);
if (ret_val)
goto out;
ret_val = igc_init_nvm_params(hw);
if (ret_val)
goto out;
ret_val = igc_init_phy_params(hw);
if (ret_val)
goto out;
}
out:
return ret_val;
}
/**
* igc_get_bus_info - Obtain bus information for adapter
* @hw: pointer to the HW structure
*
* This will obtain information about the HW bus for which the
* adapter is attached and stores it in the hw structure. This is a
* function pointer entry point called by drivers.
**/
s32 igc_get_bus_info(struct igc_hw *hw)
{
if (hw->mac.ops.get_bus_info)
return hw->mac.ops.get_bus_info(hw);
return IGC_SUCCESS;
}
/**
* igc_clear_vfta - Clear VLAN filter table
* @hw: pointer to the HW structure
*
* This clears the VLAN filter table on the adapter. This is a function
* pointer entry point called by drivers.
**/
void igc_clear_vfta(struct igc_hw *hw)
{
if (hw->mac.ops.clear_vfta)
hw->mac.ops.clear_vfta(hw);
}
/**
* igc_write_vfta - Write value to VLAN filter table
* @hw: pointer to the HW structure
* @offset: the 32-bit offset in which to write the value to.
* @value: the 32-bit value to write at location offset.
*
* This writes a 32-bit value to a 32-bit offset in the VLAN filter
* table. This is a function pointer entry point called by drivers.
**/
void igc_write_vfta(struct igc_hw *hw, u32 offset, u32 value)
{
if (hw->mac.ops.write_vfta)
hw->mac.ops.write_vfta(hw, offset, value);
}
/**
* igc_update_mc_addr_list - Update Multicast addresses
* @hw: pointer to the HW structure
* @mc_addr_list: array of multicast addresses to program
* @mc_addr_count: number of multicast addresses to program
*
* Updates the Multicast Table Array.
* The caller must have a packed mc_addr_list of multicast addresses.
**/
void igc_update_mc_addr_list(struct igc_hw *hw, u8 *mc_addr_list,
u32 mc_addr_count)
{
if (hw->mac.ops.update_mc_addr_list)
hw->mac.ops.update_mc_addr_list(hw, mc_addr_list,
mc_addr_count);
}
/**
* igc_force_mac_fc - Force MAC flow control
* @hw: pointer to the HW structure
*
* Force the MAC's flow control settings. Currently no func pointer exists
* and all implementations are handled in the generic version of this
* function.
**/
s32 igc_force_mac_fc(struct igc_hw *hw)
{
return igc_force_mac_fc_generic(hw);
}
/**
* igc_check_for_link - Check/Store link connection
* @hw: pointer to the HW structure
*
* This checks the link condition of the adapter and stores the
* results in the hw->mac structure. This is a function pointer entry
* point called by drivers.
**/
s32 igc_check_for_link(struct igc_hw *hw)
{
if (hw->mac.ops.check_for_link)
return hw->mac.ops.check_for_link(hw);
return -IGC_ERR_CONFIG;
}
/**
* igc_reset_hw - Reset hardware
* @hw: pointer to the HW structure
*
* This resets the hardware into a known state. This is a function pointer
* entry point called by drivers.
**/
s32 igc_reset_hw(struct igc_hw *hw)
{
if (hw->mac.ops.reset_hw)
return hw->mac.ops.reset_hw(hw);
return -IGC_ERR_CONFIG;
}
/**
* igc_init_hw - Initialize hardware
* @hw: pointer to the HW structure
*
* This inits the hardware readying it for operation. This is a function
* pointer entry point called by drivers.
**/
s32 igc_init_hw(struct igc_hw *hw)
{
if (hw->mac.ops.init_hw)
return hw->mac.ops.init_hw(hw);
return -IGC_ERR_CONFIG;
}
/**
* igc_setup_link - Configures link and flow control
* @hw: pointer to the HW structure
*
* This configures link and flow control settings for the adapter. This
* is a function pointer entry point called by drivers. While modules can
* also call this, they probably call their own version of this function.
**/
s32 igc_setup_link(struct igc_hw *hw)
{
if (hw->mac.ops.setup_link)
return hw->mac.ops.setup_link(hw);
return -IGC_ERR_CONFIG;
}
/**
* igc_get_speed_and_duplex - Returns current speed and duplex
* @hw: pointer to the HW structure
* @speed: pointer to a 16-bit value to store the speed
* @duplex: pointer to a 16-bit value to store the duplex.
*
* This returns the speed and duplex of the adapter in the two 'out'
* variables passed in. This is a function pointer entry point called
* by drivers.
**/
s32 igc_get_speed_and_duplex(struct igc_hw *hw, u16 *speed, u16 *duplex)
{
if (hw->mac.ops.get_link_up_info)
return hw->mac.ops.get_link_up_info(hw, speed, duplex);
return -IGC_ERR_CONFIG;
}
/**
* igc_disable_pcie_master - Disable PCI-Express master access
* @hw: pointer to the HW structure
*
* Disables PCI-Express master access and verifies there are no pending
* requests. Currently no func pointer exists and all implementations are
* handled in the generic version of this function.
**/
s32 igc_disable_pcie_master(struct igc_hw *hw)
{
return igc_disable_pcie_master_generic(hw);
}
/**
* igc_config_collision_dist - Configure collision distance
* @hw: pointer to the HW structure
*
* Configures the collision distance to the default value and is used
* during link setup.
**/
void igc_config_collision_dist(struct igc_hw *hw)
{
if (hw->mac.ops.config_collision_dist)
hw->mac.ops.config_collision_dist(hw);
}
/**
* igc_rar_set - Sets a receive address register
* @hw: pointer to the HW structure
* @addr: address to set the RAR to
* @index: the RAR to set
*
* Sets a Receive Address Register (RAR) to the specified address.
**/
int igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index)
{
if (hw->mac.ops.rar_set)
return hw->mac.ops.rar_set(hw, addr, index);
return IGC_SUCCESS;
}
/**
* igc_validate_mdi_setting - Ensures valid MDI/MDIX SW state
* @hw: pointer to the HW structure
*
* Ensures that the MDI/MDIX SW state is valid.
**/
s32 igc_validate_mdi_setting(struct igc_hw *hw)
{
if (hw->mac.ops.validate_mdi_setting)
return hw->mac.ops.validate_mdi_setting(hw);
return IGC_SUCCESS;
}
/**
* igc_hash_mc_addr - Determines address location in multicast table
* @hw: pointer to the HW structure
* @mc_addr: Multicast address to hash.
*
* This hashes an address to determine its location in the multicast
* table. Currently no func pointer exists and all implementations
* are handled in the generic version of this function.
**/
u32 igc_hash_mc_addr(struct igc_hw *hw, u8 *mc_addr)
{
return igc_hash_mc_addr_generic(hw, mc_addr);
}
/**
* igc_check_reset_block - Verifies PHY can be reset
* @hw: pointer to the HW structure
*
* Checks if the PHY is in a state that can be reset or if manageability
* has it tied up. This is a function pointer entry point called by drivers.
**/
s32 igc_check_reset_block(struct igc_hw *hw)
{
if (hw->phy.ops.check_reset_block)
return hw->phy.ops.check_reset_block(hw);
return IGC_SUCCESS;
}
/**
* igc_read_phy_reg - Reads PHY register
* @hw: pointer to the HW structure
* @offset: the register to read
* @data: the buffer to store the 16-bit read.
*
* Reads the PHY register and returns the value in data.
* This is a function pointer entry point called by drivers.
**/
s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
{
if (hw->phy.ops.read_reg)
return hw->phy.ops.read_reg(hw, offset, data);
return IGC_SUCCESS;
}
/**
* igc_write_phy_reg - Writes PHY register
* @hw: pointer to the HW structure
* @offset: the register to write
* @data: the value to write.
*
* Writes the PHY register at offset with the value in data.
* This is a function pointer entry point called by drivers.
**/
s32 igc_write_phy_reg(struct igc_hw *hw, u32 offset, u16 data)
{
if (hw->phy.ops.write_reg)
return hw->phy.ops.write_reg(hw, offset, data);
return IGC_SUCCESS;
}
/**
* igc_release_phy - Generic release PHY
* @hw: pointer to the HW structure
*
* Return if silicon family does not require a semaphore when accessing the
* PHY.
**/
void igc_release_phy(struct igc_hw *hw)
{
if (hw->phy.ops.release)
hw->phy.ops.release(hw);
}
/**
* igc_acquire_phy - Generic acquire PHY
* @hw: pointer to the HW structure
*
* Return success if silicon family does not require a semaphore when
* accessing the PHY.
**/
s32 igc_acquire_phy(struct igc_hw *hw)
{
if (hw->phy.ops.acquire)
return hw->phy.ops.acquire(hw);
return IGC_SUCCESS;
}
/**
* igc_get_phy_info - Retrieves PHY information from registers
* @hw: pointer to the HW structure
*
* This function gets some information from various PHY registers and
* populates hw->phy values with it. This is a function pointer entry
* point called by drivers.
**/
s32 igc_get_phy_info(struct igc_hw *hw)
{
if (hw->phy.ops.get_info)
return hw->phy.ops.get_info(hw);
return IGC_SUCCESS;
}
/**
* igc_phy_hw_reset - Hard PHY reset
* @hw: pointer to the HW structure
*
* Performs a hard PHY reset. This is a function pointer entry point called
* by drivers.
**/
s32 igc_phy_hw_reset(struct igc_hw *hw)
{
if (hw->phy.ops.reset)
return hw->phy.ops.reset(hw);
return IGC_SUCCESS;
}
-/**
- * igc_phy_commit - Soft PHY reset
- * @hw: pointer to the HW structure
- *
- * Performs a soft PHY reset on those that apply. This is a function pointer
- * entry point called by drivers.
- **/
-s32 igc_phy_commit(struct igc_hw *hw)
-{
- if (hw->phy.ops.commit)
- return hw->phy.ops.commit(hw);
-
- return IGC_SUCCESS;
-}
-
/**
* igc_set_d0_lplu_state - Sets low power link up state for D0
* @hw: pointer to the HW structure
* @active: boolean used to enable/disable lplu
*
* Success returns 0, Failure returns 1
*
* The low power link up (lplu) state is set to the power management level D0
* and SmartSpeed is disabled when active is true, else clear lplu for D0
* and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
* is used during Dx states where the power conservation is most important.
* During driver activity, SmartSpeed should be enabled so performance is
* maintained. This is a function pointer entry point called by drivers.
**/
s32 igc_set_d0_lplu_state(struct igc_hw *hw, bool active)
{
if (hw->phy.ops.set_d0_lplu_state)
return hw->phy.ops.set_d0_lplu_state(hw, active);
return IGC_SUCCESS;
}
/**
* igc_set_d3_lplu_state - Sets low power link up state for D3
* @hw: pointer to the HW structure
* @active: boolean used to enable/disable lplu
*
* Success returns 0, Failure returns 1
*
* The low power link up (lplu) state is set to the power management level D3
* and SmartSpeed is disabled when active is true, else clear lplu for D3
* and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
* is used during Dx states where the power conservation is most important.
* During driver activity, SmartSpeed should be enabled so performance is
* maintained. This is a function pointer entry point called by drivers.
**/
s32 igc_set_d3_lplu_state(struct igc_hw *hw, bool active)
{
if (hw->phy.ops.set_d3_lplu_state)
return hw->phy.ops.set_d3_lplu_state(hw, active);
return IGC_SUCCESS;
}
/**
* igc_read_mac_addr - Reads MAC address
* @hw: pointer to the HW structure
*
* Reads the MAC address out of the adapter and stores it in the HW structure.
* Currently no func pointer exists and all implementations are handled in the
* generic version of this function.
**/
s32 igc_read_mac_addr(struct igc_hw *hw)
{
if (hw->mac.ops.read_mac_addr)
return hw->mac.ops.read_mac_addr(hw);
return igc_read_mac_addr_generic(hw);
}
/**
* igc_read_pba_string - Read device part number string
* @hw: pointer to the HW structure
* @pba_num: pointer to device part number
* @pba_num_size: size of part number buffer
*
* Reads the product board assembly (PBA) number from the EEPROM and stores
* the value in pba_num.
* Currently no func pointer exists and all implementations are handled in the
* generic version of this function.
**/
s32 igc_read_pba_string(struct igc_hw *hw, u8 *pba_num, u32 pba_num_size)
{
return igc_read_pba_string_generic(hw, pba_num, pba_num_size);
}
/**
* igc_validate_nvm_checksum - Verifies NVM (EEPROM) checksum
* @hw: pointer to the HW structure
*
* Validates the NVM checksum is correct. This is a function pointer entry
* point called by drivers.
**/
s32 igc_validate_nvm_checksum(struct igc_hw *hw)
{
if (hw->nvm.ops.validate)
return hw->nvm.ops.validate(hw);
return -IGC_ERR_CONFIG;
}
/**
* igc_update_nvm_checksum - Updates NVM (EEPROM) checksum
* @hw: pointer to the HW structure
*
* Updates the NVM checksum. Currently no func pointer exists and all
* implementations are handled in the generic version of this function.
**/
s32 igc_update_nvm_checksum(struct igc_hw *hw)
{
if (hw->nvm.ops.update)
return hw->nvm.ops.update(hw);
return -IGC_ERR_CONFIG;
}
/**
* igc_reload_nvm - Reloads EEPROM
* @hw: pointer to the HW structure
*
* Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
* extended control register.
**/
void igc_reload_nvm(struct igc_hw *hw)
{
if (hw->nvm.ops.reload)
hw->nvm.ops.reload(hw);
}
/**
* igc_read_nvm - Reads NVM (EEPROM)
* @hw: pointer to the HW structure
* @offset: the word offset to read
* @words: number of 16-bit words to read
* @data: pointer to the properly sized buffer for the data.
*
* Reads 16-bit chunks of data from the NVM (EEPROM). This is a function
* pointer entry point called by drivers.
**/
s32 igc_read_nvm(struct igc_hw *hw, u16 offset, u16 words, u16 *data)
{
if (hw->nvm.ops.read)
return hw->nvm.ops.read(hw, offset, words, data);
return -IGC_ERR_CONFIG;
}
/**
* igc_write_nvm - Writes to NVM (EEPROM)
* @hw: pointer to the HW structure
* @offset: the word offset to read
* @words: number of 16-bit words to write
* @data: pointer to the properly sized buffer for the data.
*
* Writes 16-bit chunks of data to the NVM (EEPROM). This is a function
* pointer entry point called by drivers.
**/
s32 igc_write_nvm(struct igc_hw *hw, u16 offset, u16 words, u16 *data)
{
if (hw->nvm.ops.write)
return hw->nvm.ops.write(hw, offset, words, data);
return IGC_SUCCESS;
}
/**
* igc_power_up_phy - Restores link in case of PHY power down
* @hw: pointer to the HW structure
*
* The phy may be powered down to save power, to turn off link when the
* driver is unloaded, or wake on lan is not enabled (among others).
**/
void igc_power_up_phy(struct igc_hw *hw)
{
if (hw->phy.ops.power_up)
hw->phy.ops.power_up(hw);
igc_setup_link(hw);
}
/**
* igc_power_down_phy - Power down PHY
* @hw: pointer to the HW structure
*
* The phy may be powered down to save power, to turn off link when the
* driver is unloaded, or wake on lan is not enabled (among others).
**/
void igc_power_down_phy(struct igc_hw *hw)
{
if (hw->phy.ops.power_down)
hw->phy.ops.power_down(hw);
}
diff --git a/sys/dev/igc/igc_api.h b/sys/dev/igc/igc_api.h
index a0fc9ff21166..f9064b540c7c 100644
--- a/sys/dev/igc/igc_api.h
+++ b/sys/dev/igc/igc_api.h
@@ -1,58 +1,57 @@
/*-
* Copyright 2021 Intel Corp
* Copyright 2021 Rubicon Communications, LLC (Netgate)
* SPDX-License-Identifier: BSD-3-Clause
*
* $FreeBSD$
*/
#ifndef _IGC_API_H_
#define _IGC_API_H_
#include "igc_hw.h"
extern void igc_init_function_pointers_i225(struct igc_hw *hw);
s32 igc_set_mac_type(struct igc_hw *hw);
s32 igc_setup_init_funcs(struct igc_hw *hw, bool init_device);
s32 igc_init_mac_params(struct igc_hw *hw);
s32 igc_init_nvm_params(struct igc_hw *hw);
s32 igc_init_phy_params(struct igc_hw *hw);
s32 igc_get_bus_info(struct igc_hw *hw);
void igc_clear_vfta(struct igc_hw *hw);
void igc_write_vfta(struct igc_hw *hw, u32 offset, u32 value);
s32 igc_force_mac_fc(struct igc_hw *hw);
s32 igc_check_for_link(struct igc_hw *hw);
s32 igc_reset_hw(struct igc_hw *hw);
s32 igc_init_hw(struct igc_hw *hw);
s32 igc_setup_link(struct igc_hw *hw);
s32 igc_get_speed_and_duplex(struct igc_hw *hw, u16 *speed, u16 *duplex);
s32 igc_disable_pcie_master(struct igc_hw *hw);
void igc_config_collision_dist(struct igc_hw *hw);
int igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index);
u32 igc_hash_mc_addr(struct igc_hw *hw, u8 *mc_addr);
void igc_update_mc_addr_list(struct igc_hw *hw, u8 *mc_addr_list,
u32 mc_addr_count);
s32 igc_check_reset_block(struct igc_hw *hw);
s32 igc_get_cable_length(struct igc_hw *hw);
s32 igc_validate_mdi_setting(struct igc_hw *hw);
s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data);
s32 igc_write_phy_reg(struct igc_hw *hw, u32 offset, u16 data);
s32 igc_get_phy_info(struct igc_hw *hw);
void igc_release_phy(struct igc_hw *hw);
s32 igc_acquire_phy(struct igc_hw *hw);
s32 igc_phy_hw_reset(struct igc_hw *hw);
-s32 igc_phy_commit(struct igc_hw *hw);
void igc_power_up_phy(struct igc_hw *hw);
void igc_power_down_phy(struct igc_hw *hw);
s32 igc_read_mac_addr(struct igc_hw *hw);
s32 igc_read_pba_string(struct igc_hw *hw, u8 *pba_num, u32 pba_num_size);
void igc_reload_nvm(struct igc_hw *hw);
s32 igc_update_nvm_checksum(struct igc_hw *hw);
s32 igc_validate_nvm_checksum(struct igc_hw *hw);
s32 igc_read_nvm(struct igc_hw *hw, u16 offset, u16 words, u16 *data);
s32 igc_write_nvm(struct igc_hw *hw, u16 offset, u16 words, u16 *data);
s32 igc_set_d3_lplu_state(struct igc_hw *hw, bool active);
s32 igc_set_d0_lplu_state(struct igc_hw *hw, bool active);
#endif /* _IGC_API_H_ */
diff --git a/sys/dev/igc/igc_hw.h b/sys/dev/igc/igc_hw.h
index a07d2894f97a..a8323a8578a9 100644
--- a/sys/dev/igc/igc_hw.h
+++ b/sys/dev/igc/igc_hw.h
@@ -1,548 +1,547 @@
/*-
* Copyright 2021 Intel Corp
* Copyright 2021 Rubicon Communications, LLC (Netgate)
* SPDX-License-Identifier: BSD-3-Clause
*
* $FreeBSD$
*/
#ifndef _IGC_HW_H_
#define _IGC_HW_H_
#include "igc_osdep.h"
#include "igc_regs.h"
#include "igc_defines.h"
struct igc_hw;
#define IGC_DEV_ID_I225_LM 0x15F2
#define IGC_DEV_ID_I225_V 0x15F3
#define IGC_DEV_ID_I225_K 0x3100
#define IGC_DEV_ID_I225_I 0x15F8
#define IGC_DEV_ID_I220_V 0x15F7
#define IGC_DEV_ID_I225_K2 0x3101
#define IGC_DEV_ID_I225_LMVP 0x5502
#define IGC_DEV_ID_I226_K 0x5504
#define IGC_DEV_ID_I225_IT 0x0D9F
#define IGC_DEV_ID_I226_LM 0x125B
#define IGC_DEV_ID_I226_V 0x125C
#define IGC_DEV_ID_I226_IT 0x125D
#define IGC_DEV_ID_I221_V 0x125E
#define IGC_DEV_ID_I226_BLANK_NVM 0x125F
#define IGC_DEV_ID_I225_BLANK_NVM 0x15FD
#define IGC_REVISION_0 0
#define IGC_REVISION_1 1
#define IGC_REVISION_2 2
#define IGC_REVISION_3 3
#define IGC_REVISION_4 4
#define IGC_FUNC_1 1
#define IGC_ALT_MAC_ADDRESS_OFFSET_LAN0 0
#define IGC_ALT_MAC_ADDRESS_OFFSET_LAN1 3
enum igc_mac_type {
igc_undefined = 0,
igc_i225,
igc_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
};
enum igc_media_type {
igc_media_type_unknown = 0,
igc_media_type_copper = 1,
igc_num_media_types
};
enum igc_nvm_type {
igc_nvm_unknown = 0,
igc_nvm_eeprom_spi,
igc_nvm_flash_hw,
igc_nvm_invm,
};
enum igc_phy_type {
igc_phy_unknown = 0,
igc_phy_none,
igc_phy_i225,
};
enum igc_bus_type {
igc_bus_type_unknown = 0,
igc_bus_type_pci,
igc_bus_type_pcix,
igc_bus_type_pci_express,
igc_bus_type_reserved
};
enum igc_bus_speed {
igc_bus_speed_unknown = 0,
igc_bus_speed_33,
igc_bus_speed_66,
igc_bus_speed_100,
igc_bus_speed_120,
igc_bus_speed_133,
igc_bus_speed_2500,
igc_bus_speed_5000,
igc_bus_speed_reserved
};
enum igc_bus_width {
igc_bus_width_unknown = 0,
igc_bus_width_pcie_x1,
igc_bus_width_pcie_x2,
igc_bus_width_pcie_x4 = 4,
igc_bus_width_pcie_x8 = 8,
igc_bus_width_32,
igc_bus_width_64,
igc_bus_width_reserved
};
enum igc_fc_mode {
igc_fc_none = 0,
igc_fc_rx_pause,
igc_fc_tx_pause,
igc_fc_full,
igc_fc_default = 0xFF
};
enum igc_ms_type {
igc_ms_hw_default = 0,
igc_ms_force_master,
igc_ms_force_slave,
igc_ms_auto
};
enum igc_smart_speed {
igc_smart_speed_default = 0,
igc_smart_speed_on,
igc_smart_speed_off
};
#define __le16 u16
#define __le32 u32
#define __le64 u64
/* Receive Descriptor */
struct igc_rx_desc {
__le64 buffer_addr; /* Address of the descriptor's data buffer */
__le16 length; /* Length of data DMAed into data buffer */
__le16 csum; /* Packet checksum */
u8 status; /* Descriptor status */
u8 errors; /* Descriptor Errors */
__le16 special;
};
/* Receive Descriptor - Extended */
union igc_rx_desc_extended {
struct {
__le64 buffer_addr;
__le64 reserved;
} read;
struct {
struct {
__le32 mrq; /* Multiple Rx Queues */
union {
__le32 rss; /* RSS Hash */
struct {
__le16 ip_id; /* IP id */
__le16 csum; /* Packet Checksum */
} csum_ip;
} hi_dword;
} lower;
struct {
__le32 status_error; /* ext status/error */
__le16 length;
__le16 vlan; /* VLAN tag */
} upper;
} wb; /* writeback */
};
#define MAX_PS_BUFFERS 4
/* Number of packet split data buffers (not including the header buffer) */
#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
/* Receive Descriptor - Packet Split */
union igc_rx_desc_packet_split {
struct {
/* one buffer for protocol header(s), three data buffers */
__le64 buffer_addr[MAX_PS_BUFFERS];
} read;
struct {
struct {
__le32 mrq; /* Multiple Rx Queues */
union {
__le32 rss; /* RSS Hash */
struct {
__le16 ip_id; /* IP id */
__le16 csum; /* Packet Checksum */
} csum_ip;
} hi_dword;
} lower;
struct {
__le32 status_error; /* ext status/error */
__le16 length0; /* length of buffer 0 */
__le16 vlan; /* VLAN tag */
} middle;
struct {
__le16 header_status;
/* length of buffers 1-3 */
__le16 length[PS_PAGE_BUFFERS];
} upper;
__le64 reserved;
} wb; /* writeback */
};
/* Transmit Descriptor */
struct igc_tx_desc {
__le64 buffer_addr; /* Address of the descriptor's data buffer */
union {
__le32 data;
struct {
__le16 length; /* Data buffer length */
u8 cso; /* Checksum offset */
u8 cmd; /* Descriptor control */
} flags;
} lower;
union {
__le32 data;
struct {
u8 status; /* Descriptor status */
u8 css; /* Checksum start */
__le16 special;
} fields;
} upper;
};
/* Offload Context Descriptor */
struct igc_context_desc {
union {
__le32 ip_config;
struct {
u8 ipcss; /* IP checksum start */
u8 ipcso; /* IP checksum offset */
__le16 ipcse; /* IP checksum end */
} ip_fields;
} lower_setup;
union {
__le32 tcp_config;
struct {
u8 tucss; /* TCP checksum start */
u8 tucso; /* TCP checksum offset */
__le16 tucse; /* TCP checksum end */
} tcp_fields;
} upper_setup;
__le32 cmd_and_length;
union {
__le32 data;
struct {
u8 status; /* Descriptor status */
u8 hdr_len; /* Header length */
__le16 mss; /* Maximum segment size */
} fields;
} tcp_seg_setup;
};
/* Offload data descriptor */
struct igc_data_desc {
__le64 buffer_addr; /* Address of the descriptor's buffer address */
union {
__le32 data;
struct {
__le16 length; /* Data buffer length */
u8 typ_len_ext;
u8 cmd;
} flags;
} lower;
union {
__le32 data;
struct {
u8 status; /* Descriptor status */
u8 popts; /* Packet Options */
__le16 special;
} fields;
} upper;
};
/* Statistics counters collected by the MAC */
struct igc_hw_stats {
u64 crcerrs;
u64 algnerrc;
u64 symerrs;
u64 rxerrc;
u64 mpc;
u64 scc;
u64 ecol;
u64 mcc;
u64 latecol;
u64 colc;
u64 dc;
u64 tncrs;
u64 sec;
u64 rlec;
u64 xonrxc;
u64 xontxc;
u64 xoffrxc;
u64 xofftxc;
u64 fcruc;
u64 prc64;
u64 prc127;
u64 prc255;
u64 prc511;
u64 prc1023;
u64 prc1522;
u64 tlpic;
u64 rlpic;
u64 gprc;
u64 bprc;
u64 mprc;
u64 gptc;
u64 gorc;
u64 gotc;
u64 rnbc;
u64 ruc;
u64 rfc;
u64 roc;
u64 rjc;
u64 mgprc;
u64 mgpdc;
u64 mgptc;
u64 tor;
u64 tot;
u64 tpr;
u64 tpt;
u64 ptc64;
u64 ptc127;
u64 ptc255;
u64 ptc511;
u64 ptc1023;
u64 ptc1522;
u64 mptc;
u64 bptc;
u64 tsctc;
u64 iac;
u64 rxdmtc;
u64 htdpmc;
u64 rpthc;
u64 hgptc;
u64 hgorc;
u64 hgotc;
u64 lenerrs;
u64 scvpc;
u64 hrmpc;
u64 doosync;
u64 o2bgptc;
u64 o2bspc;
u64 b2ospc;
u64 b2ogprc;
};
#include "igc_mac.h"
#include "igc_phy.h"
#include "igc_nvm.h"
/* Function pointers for the MAC. */
struct igc_mac_operations {
s32 (*init_params)(struct igc_hw *);
s32 (*check_for_link)(struct igc_hw *);
void (*clear_hw_cntrs)(struct igc_hw *);
void (*clear_vfta)(struct igc_hw *);
s32 (*get_bus_info)(struct igc_hw *);
void (*set_lan_id)(struct igc_hw *);
s32 (*get_link_up_info)(struct igc_hw *, u16 *, u16 *);
void (*update_mc_addr_list)(struct igc_hw *, u8 *, u32);
s32 (*reset_hw)(struct igc_hw *);
s32 (*init_hw)(struct igc_hw *);
s32 (*setup_link)(struct igc_hw *);
s32 (*setup_physical_interface)(struct igc_hw *);
void (*write_vfta)(struct igc_hw *, u32, u32);
void (*config_collision_dist)(struct igc_hw *);
int (*rar_set)(struct igc_hw *, u8*, u32);
s32 (*read_mac_addr)(struct igc_hw *);
s32 (*validate_mdi_setting)(struct igc_hw *);
s32 (*acquire_swfw_sync)(struct igc_hw *, u16);
void (*release_swfw_sync)(struct igc_hw *, u16);
};
/* When to use various PHY register access functions:
*
* Func Caller
* Function Does Does When to use
* ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* X_reg L,P,A n/a for simple PHY reg accesses
* X_reg_locked P,A L for multiple accesses of different regs
* on different pages
* X_reg_page A L,P for multiple accesses of different regs
* on the same page
*
* Where X=[read|write], L=locking, P=sets page, A=register access
*
*/
struct igc_phy_operations {
s32 (*init_params)(struct igc_hw *);
s32 (*acquire)(struct igc_hw *);
s32 (*check_reset_block)(struct igc_hw *);
- s32 (*commit)(struct igc_hw *);
s32 (*force_speed_duplex)(struct igc_hw *);
s32 (*get_info)(struct igc_hw *);
s32 (*set_page)(struct igc_hw *, u16);
s32 (*read_reg)(struct igc_hw *, u32, u16 *);
s32 (*read_reg_locked)(struct igc_hw *, u32, u16 *);
s32 (*read_reg_page)(struct igc_hw *, u32, u16 *);
void (*release)(struct igc_hw *);
s32 (*reset)(struct igc_hw *);
s32 (*set_d0_lplu_state)(struct igc_hw *, bool);
s32 (*set_d3_lplu_state)(struct igc_hw *, bool);
s32 (*write_reg)(struct igc_hw *, u32, u16);
s32 (*write_reg_locked)(struct igc_hw *, u32, u16);
s32 (*write_reg_page)(struct igc_hw *, u32, u16);
void (*power_up)(struct igc_hw *);
void (*power_down)(struct igc_hw *);
};
/* Function pointers for the NVM. */
struct igc_nvm_operations {
s32 (*init_params)(struct igc_hw *);
s32 (*acquire)(struct igc_hw *);
s32 (*read)(struct igc_hw *, u16, u16, u16 *);
void (*release)(struct igc_hw *);
void (*reload)(struct igc_hw *);
s32 (*update)(struct igc_hw *);
s32 (*validate)(struct igc_hw *);
s32 (*write)(struct igc_hw *, u16, u16, u16 *);
};
struct igc_info {
s32 (*get_invariants)(struct igc_hw *hw);
struct igc_mac_operations *mac_ops;
const struct igc_phy_operations *phy_ops;
struct igc_nvm_operations *nvm_ops;
};
extern const struct igc_info igc_i225_info;
struct igc_mac_info {
struct igc_mac_operations ops;
u8 addr[ETH_ADDR_LEN];
u8 perm_addr[ETH_ADDR_LEN];
enum igc_mac_type type;
u32 mc_filter_type;
u16 current_ifs_val;
u16 ifs_max_val;
u16 ifs_min_val;
u16 ifs_ratio;
u16 ifs_step_size;
u16 mta_reg_count;
u16 uta_reg_count;
/* Maximum size of the MTA register table in all supported adapters */
#define MAX_MTA_REG 128
u32 mta_shadow[MAX_MTA_REG];
u16 rar_entry_count;
u8 forced_speed_duplex;
bool asf_firmware_present;
bool autoneg;
bool get_link_status;
u32 max_frame_size;
};
struct igc_phy_info {
struct igc_phy_operations ops;
enum igc_phy_type type;
enum igc_smart_speed smart_speed;
u32 addr;
u32 id;
u32 reset_delay_us; /* in usec */
u32 revision;
enum igc_media_type media_type;
u16 autoneg_advertised;
u16 autoneg_mask;
u8 mdix;
bool polarity_correction;
bool speed_downgraded;
bool autoneg_wait_to_complete;
};
struct igc_nvm_info {
struct igc_nvm_operations ops;
enum igc_nvm_type type;
u16 word_size;
u16 delay_usec;
u16 address_bits;
u16 opcode_bits;
u16 page_size;
};
struct igc_bus_info {
enum igc_bus_type type;
enum igc_bus_speed speed;
enum igc_bus_width width;
u16 func;
u16 pci_cmd_word;
};
struct igc_fc_info {
u32 high_water; /* Flow control high-water mark */
u32 low_water; /* Flow control low-water mark */
u16 pause_time; /* Flow control pause timer */
u16 refresh_time; /* Flow control refresh timer */
bool send_xon; /* Flow control send XON */
bool strict_ieee; /* Strict IEEE mode */
enum igc_fc_mode current_mode; /* FC mode in effect */
enum igc_fc_mode requested_mode; /* FC mode requested by caller */
};
struct igc_dev_spec_i225 {
bool eee_disable;
bool clear_semaphore_once;
u32 mtu;
};
struct igc_hw {
void *back;
u8 *hw_addr;
u8 *flash_address;
unsigned long io_base;
struct igc_mac_info mac;
struct igc_fc_info fc;
struct igc_phy_info phy;
struct igc_nvm_info nvm;
struct igc_bus_info bus;
union {
struct igc_dev_spec_i225 _i225;
} dev_spec;
u16 device_id;
u16 subsystem_vendor_id;
u16 subsystem_device_id;
u16 vendor_id;
u8 revision_id;
};
#include "igc_i225.h"
#include "igc_base.h"
/* These functions must be implemented by drivers */
s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
#endif
diff --git a/sys/dev/igc/igc_i225.c b/sys/dev/igc/igc_i225.c
index 75c4b5125a97..4c50daa16b79 100644
--- a/sys/dev/igc/igc_i225.c
+++ b/sys/dev/igc/igc_i225.c
@@ -1,1232 +1,1227 @@
/*-
* Copyright 2021 Intel Corp
* Copyright 2021 Rubicon Communications, LLC (Netgate)
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "igc_api.h"
static s32 igc_init_nvm_params_i225(struct igc_hw *hw);
static s32 igc_init_mac_params_i225(struct igc_hw *hw);
static s32 igc_init_phy_params_i225(struct igc_hw *hw);
static s32 igc_reset_hw_i225(struct igc_hw *hw);
static s32 igc_acquire_nvm_i225(struct igc_hw *hw);
static void igc_release_nvm_i225(struct igc_hw *hw);
static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw);
static s32 __igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words,
u16 *data);
static s32 igc_pool_flash_update_done_i225(struct igc_hw *hw);
/**
* igc_init_nvm_params_i225 - Init NVM func ptrs.
* @hw: pointer to the HW structure
**/
static s32 igc_init_nvm_params_i225(struct igc_hw *hw)
{
struct igc_nvm_info *nvm = &hw->nvm;
u32 eecd = IGC_READ_REG(hw, IGC_EECD);
u16 size;
DEBUGFUNC("igc_init_nvm_params_i225");
size = (u16)((eecd & IGC_EECD_SIZE_EX_MASK) >>
IGC_EECD_SIZE_EX_SHIFT);
/*
* Added to a constant, "size" becomes the left-shift value
* for setting word_size.
*/
size += NVM_WORD_SIZE_BASE_SHIFT;
/* Just in case size is out of range, cap it to the largest
* EEPROM size supported
*/
if (size > 15)
size = 15;
nvm->word_size = 1 << size;
nvm->opcode_bits = 8;
nvm->delay_usec = 1;
nvm->type = igc_nvm_eeprom_spi;
nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8;
nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ?
16 : 8;
if (nvm->word_size == (1 << 15))
nvm->page_size = 128;
nvm->ops.acquire = igc_acquire_nvm_i225;
nvm->ops.release = igc_release_nvm_i225;
if (igc_get_flash_presence_i225(hw)) {
hw->nvm.type = igc_nvm_flash_hw;
nvm->ops.read = igc_read_nvm_srrd_i225;
nvm->ops.write = igc_write_nvm_srwr_i225;
nvm->ops.validate = igc_validate_nvm_checksum_i225;
nvm->ops.update = igc_update_nvm_checksum_i225;
} else {
hw->nvm.type = igc_nvm_invm;
nvm->ops.write = igc_null_write_nvm;
nvm->ops.validate = igc_null_ops_generic;
nvm->ops.update = igc_null_ops_generic;
}
return IGC_SUCCESS;
}
/**
* igc_init_mac_params_i225 - Init MAC func ptrs.
* @hw: pointer to the HW structure
**/
static s32 igc_init_mac_params_i225(struct igc_hw *hw)
{
struct igc_mac_info *mac = &hw->mac;
struct igc_dev_spec_i225 *dev_spec = &hw->dev_spec._i225;
DEBUGFUNC("igc_init_mac_params_i225");
/* Initialize function pointer */
igc_init_mac_ops_generic(hw);
/* Set media type */
hw->phy.media_type = igc_media_type_copper;
/* Set mta register count */
mac->mta_reg_count = 128;
/* Set rar entry count */
mac->rar_entry_count = IGC_RAR_ENTRIES_BASE;
/* reset */
mac->ops.reset_hw = igc_reset_hw_i225;
/* hw initialization */
mac->ops.init_hw = igc_init_hw_i225;
/* link setup */
mac->ops.setup_link = igc_setup_link_generic;
/* check for link */
mac->ops.check_for_link = igc_check_for_link_i225;
/* link info */
mac->ops.get_link_up_info = igc_get_speed_and_duplex_copper_generic;
/* acquire SW_FW sync */
mac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225;
/* release SW_FW sync */
mac->ops.release_swfw_sync = igc_release_swfw_sync_i225;
/* Allow a single clear of the SW semaphore on I225 */
dev_spec->clear_semaphore_once = true;
mac->ops.setup_physical_interface = igc_setup_copper_link_i225;
/* Set if part includes ASF firmware */
mac->asf_firmware_present = true;
/* multicast address update */
mac->ops.update_mc_addr_list = igc_update_mc_addr_list_generic;
mac->ops.write_vfta = igc_write_vfta_generic;
return IGC_SUCCESS;
}
/**
* igc_init_phy_params_i225 - Init PHY func ptrs.
* @hw: pointer to the HW structure
**/
static s32 igc_init_phy_params_i225(struct igc_hw *hw)
{
struct igc_phy_info *phy = &hw->phy;
s32 ret_val = IGC_SUCCESS;
- u32 ctrl_ext;
DEBUGFUNC("igc_init_phy_params_i225");
if (hw->phy.media_type != igc_media_type_copper) {
phy->type = igc_phy_none;
goto out;
}
phy->ops.power_up = igc_power_up_phy_copper;
phy->ops.power_down = igc_power_down_phy_copper_base;
phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT_2500;
phy->reset_delay_us = 100;
phy->ops.acquire = igc_acquire_phy_base;
phy->ops.check_reset_block = igc_check_reset_block_generic;
- phy->ops.commit = igc_phy_sw_reset_generic;
phy->ops.release = igc_release_phy_base;
-
- ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);
+ phy->ops.reset = igc_phy_hw_reset_generic;
+ phy->ops.read_reg = igc_read_phy_reg_gpy;
+ phy->ops.write_reg = igc_write_phy_reg_gpy;
/* Make sure the PHY is in a good state. Several people have reported
* firmware leaving the PHY's page select register set to something
* other than the default of zero, which causes the PHY ID read to
* access something other than the intended register.
*/
ret_val = hw->phy.ops.reset(hw);
if (ret_val)
goto out;
- IGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext);
- phy->ops.read_reg = igc_read_phy_reg_gpy;
- phy->ops.write_reg = igc_write_phy_reg_gpy;
-
ret_val = igc_get_phy_id(hw);
/* Verify phy id and set remaining function pointers */
switch (phy->id) {
case I225_I_PHY_ID:
phy->type = igc_phy_i225;
phy->ops.set_d0_lplu_state = igc_set_d0_lplu_state_i225;
phy->ops.set_d3_lplu_state = igc_set_d3_lplu_state_i225;
/* TODO - complete with GPY PHY information */
break;
default:
ret_val = -IGC_ERR_PHY;
goto out;
}
out:
return ret_val;
}
/**
* igc_reset_hw_i225 - Reset hardware
* @hw: pointer to the HW structure
*
* This resets the hardware into a known state.
**/
static s32 igc_reset_hw_i225(struct igc_hw *hw)
{
u32 ctrl;
s32 ret_val;
DEBUGFUNC("igc_reset_hw_i225");
/*
* Prevent the PCI-E bus from sticking if there is no TLP connection
* on the last TLP read/write transaction when MAC is reset.
*/
ret_val = igc_disable_pcie_master_generic(hw);
if (ret_val)
DEBUGOUT("PCI-E Master disable polling has failed.\n");
DEBUGOUT("Masking off all interrupts\n");
IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff);
IGC_WRITE_REG(hw, IGC_RCTL, 0);
IGC_WRITE_REG(hw, IGC_TCTL, IGC_TCTL_PSP);
IGC_WRITE_FLUSH(hw);
msec_delay(10);
ctrl = IGC_READ_REG(hw, IGC_CTRL);
DEBUGOUT("Issuing a global reset to MAC\n");
IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_DEV_RST);
ret_val = igc_get_auto_rd_done_generic(hw);
if (ret_val) {
/*
* When auto config read does not complete, do not
* return with an error. This can happen in situations
* where there is no eeprom and prevents getting link.
*/
DEBUGOUT("Auto Read Done did not complete\n");
}
/* Clear any pending interrupt events. */
IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff);
IGC_READ_REG(hw, IGC_ICR);
/* Install any alternate MAC address into RAR0 */
ret_val = igc_check_alt_mac_addr_generic(hw);
return ret_val;
}
/* igc_acquire_nvm_i225 - Request for access to EEPROM
* @hw: pointer to the HW structure
*
* Acquire the necessary semaphores for exclusive access to the EEPROM.
* Set the EEPROM access request bit and wait for EEPROM access grant bit.
* Return successful if access grant bit set, else clear the request for
* EEPROM access and return -IGC_ERR_NVM (-1).
*/
static s32 igc_acquire_nvm_i225(struct igc_hw *hw)
{
s32 ret_val;
DEBUGFUNC("igc_acquire_nvm_i225");
ret_val = igc_acquire_swfw_sync_i225(hw, IGC_SWFW_EEP_SM);
return ret_val;
}
/* igc_release_nvm_i225 - Release exclusive access to EEPROM
* @hw: pointer to the HW structure
*
* Stop any current commands to the EEPROM and clear the EEPROM request bit,
* then release the semaphores acquired.
*/
static void igc_release_nvm_i225(struct igc_hw *hw)
{
DEBUGFUNC("igc_release_nvm_i225");
igc_release_swfw_sync_i225(hw, IGC_SWFW_EEP_SM);
}
/* igc_acquire_swfw_sync_i225 - Acquire SW/FW semaphore
* @hw: pointer to the HW structure
* @mask: specifies which semaphore to acquire
*
* Acquire the SW/FW semaphore to access the PHY or NVM. The mask
* will also specify which port we're acquiring the lock for.
*/
s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask)
{
u32 swfw_sync;
u32 swmask = mask;
u32 fwmask = mask << 16;
s32 ret_val = IGC_SUCCESS;
s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
DEBUGFUNC("igc_acquire_swfw_sync_i225");
while (i < timeout) {
if (igc_get_hw_semaphore_i225(hw)) {
ret_val = -IGC_ERR_SWFW_SYNC;
goto out;
}
swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC);
if (!(swfw_sync & (fwmask | swmask)))
break;
/* Firmware currently using resource (fwmask)
* or other software thread using resource (swmask)
*/
igc_put_hw_semaphore_generic(hw);
msec_delay_irq(5);
i++;
}
if (i == timeout) {
DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
ret_val = -IGC_ERR_SWFW_SYNC;
goto out;
}
swfw_sync |= swmask;
IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync);
igc_put_hw_semaphore_generic(hw);
out:
return ret_val;
}
/* igc_release_swfw_sync_i225 - Release SW/FW semaphore
* @hw: pointer to the HW structure
* @mask: specifies which semaphore to acquire
*
* Release the SW/FW semaphore used to access the PHY or NVM. The mask
* will also specify which port we're releasing the lock for.
*/
void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask)
{
u32 swfw_sync;
DEBUGFUNC("igc_release_swfw_sync_i225");
while (igc_get_hw_semaphore_i225(hw) != IGC_SUCCESS)
; /* Empty */
swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC);
swfw_sync &= ~mask;
IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync);
igc_put_hw_semaphore_generic(hw);
}
/*
* igc_setup_copper_link_i225 - Configure copper link settings
* @hw: pointer to the HW structure
*
* Configures the link for auto-neg or forced speed and duplex. Then we check
* for link, once link is established calls to configure collision distance
* and flow control are called.
*/
s32 igc_setup_copper_link_i225(struct igc_hw *hw)
{
u32 phpm_reg;
s32 ret_val;
u32 ctrl;
DEBUGFUNC("igc_setup_copper_link_i225");
ctrl = IGC_READ_REG(hw, IGC_CTRL);
ctrl |= IGC_CTRL_SLU;
ctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);
IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
phpm_reg = IGC_READ_REG(hw, IGC_I225_PHPM);
phpm_reg &= ~IGC_I225_PHPM_GO_LINKD;
IGC_WRITE_REG(hw, IGC_I225_PHPM, phpm_reg);
ret_val = igc_setup_copper_link_generic(hw);
return ret_val;
}
/* igc_get_hw_semaphore_i225 - Acquire hardware semaphore
* @hw: pointer to the HW structure
*
* Acquire the HW semaphore to access the PHY or NVM
*/
static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw)
{
u32 swsm;
s32 timeout = hw->nvm.word_size + 1;
s32 i = 0;
DEBUGFUNC("igc_get_hw_semaphore_i225");
/* Get the SW semaphore */
while (i < timeout) {
swsm = IGC_READ_REG(hw, IGC_SWSM);
if (!(swsm & IGC_SWSM_SMBI))
break;
usec_delay(50);
i++;
}
if (i == timeout) {
/* In rare circumstances, the SW semaphore may already be held
* unintentionally. Clear the semaphore once before giving up.
*/
if (hw->dev_spec._i225.clear_semaphore_once) {
hw->dev_spec._i225.clear_semaphore_once = false;
igc_put_hw_semaphore_generic(hw);
for (i = 0; i < timeout; i++) {
swsm = IGC_READ_REG(hw, IGC_SWSM);
if (!(swsm & IGC_SWSM_SMBI))
break;
usec_delay(50);
}
}
/* If we do not have the semaphore here, we have to give up. */
if (i == timeout) {
DEBUGOUT("Driver can't access device -\n");
DEBUGOUT("SMBI bit is set.\n");
return -IGC_ERR_NVM;
}
}
/* Get the FW semaphore. */
for (i = 0; i < timeout; i++) {
swsm = IGC_READ_REG(hw, IGC_SWSM);
IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI);
/* Semaphore acquired if bit latched */
if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI)
break;
usec_delay(50);
}
if (i == timeout) {
/* Release semaphores */
igc_put_hw_semaphore_generic(hw);
DEBUGOUT("Driver can't access the NVM\n");
return -IGC_ERR_NVM;
}
return IGC_SUCCESS;
}
/* igc_read_nvm_srrd_i225 - Reads Shadow Ram using EERD register
* @hw: pointer to the HW structure
* @offset: offset of word in the Shadow Ram to read
* @words: number of words to read
* @data: word read from the Shadow Ram
*
* Reads a 16 bit word from the Shadow Ram using the EERD register.
* Uses necessary synchronization semaphores.
*/
s32 igc_read_nvm_srrd_i225(struct igc_hw *hw, u16 offset, u16 words,
u16 *data)
{
s32 status = IGC_SUCCESS;
u16 i, count;
DEBUGFUNC("igc_read_nvm_srrd_i225");
/* We cannot hold synchronization semaphores for too long,
* because of forceful takeover procedure. However it is more efficient
* to read in bursts than synchronizing access for each word.
*/
for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) {
count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ?
IGC_EERD_EEWR_MAX_COUNT : (words - i);
if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
status = igc_read_nvm_eerd(hw, offset, count,
data + i);
hw->nvm.ops.release(hw);
} else {
status = IGC_ERR_SWFW_SYNC;
}
if (status != IGC_SUCCESS)
break;
}
return status;
}
/* igc_write_nvm_srwr_i225 - Write to Shadow RAM using EEWR
* @hw: pointer to the HW structure
* @offset: offset within the Shadow RAM to be written to
* @words: number of words to write
* @data: 16 bit word(s) to be written to the Shadow RAM
*
* Writes data to Shadow RAM at offset using EEWR register.
*
* If igc_update_nvm_checksum is not called after this function , the
* data will not be committed to FLASH and also Shadow RAM will most likely
* contain an invalid checksum.
*
* If error code is returned, data and Shadow RAM may be inconsistent - buffer
* partially written.
*/
s32 igc_write_nvm_srwr_i225(struct igc_hw *hw, u16 offset, u16 words,
u16 *data)
{
s32 status = IGC_SUCCESS;
u16 i, count;
DEBUGFUNC("igc_write_nvm_srwr_i225");
/* We cannot hold synchronization semaphores for too long,
* because of forceful takeover procedure. However it is more efficient
* to write in bursts than synchronizing access for each word.
*/
for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) {
count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ?
IGC_EERD_EEWR_MAX_COUNT : (words - i);
if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
status = __igc_write_nvm_srwr(hw, offset, count,
data + i);
hw->nvm.ops.release(hw);
} else {
status = IGC_ERR_SWFW_SYNC;
}
if (status != IGC_SUCCESS)
break;
}
return status;
}
/* __igc_write_nvm_srwr - Write to Shadow Ram using EEWR
* @hw: pointer to the HW structure
* @offset: offset within the Shadow Ram to be written to
* @words: number of words to write
* @data: 16 bit word(s) to be written to the Shadow Ram
*
* Writes data to Shadow Ram at offset using EEWR register.
*
* If igc_update_nvm_checksum is not called after this function , the
* Shadow Ram will most likely contain an invalid checksum.
*/
static s32 __igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words,
u16 *data)
{
struct igc_nvm_info *nvm = &hw->nvm;
u32 i, k, eewr = 0;
u32 attempts = 100000;
s32 ret_val = IGC_SUCCESS;
DEBUGFUNC("__igc_write_nvm_srwr");
/* A check for invalid values: offset too large, too many words,
* too many words for the offset, and not enough words.
*/
if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
(words == 0)) {
DEBUGOUT("nvm parameter(s) out of bounds\n");
ret_val = -IGC_ERR_NVM;
goto out;
}
for (i = 0; i < words; i++) {
eewr = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT) |
(data[i] << IGC_NVM_RW_REG_DATA) |
IGC_NVM_RW_REG_START;
IGC_WRITE_REG(hw, IGC_SRWR, eewr);
for (k = 0; k < attempts; k++) {
if (IGC_NVM_RW_REG_DONE &
IGC_READ_REG(hw, IGC_SRWR)) {
ret_val = IGC_SUCCESS;
break;
}
usec_delay(5);
}
if (ret_val != IGC_SUCCESS) {
DEBUGOUT("Shadow RAM write EEWR timed out\n");
break;
}
}
out:
return ret_val;
}
/* igc_validate_nvm_checksum_i225 - Validate EEPROM checksum
* @hw: pointer to the HW structure
*
* Calculates the EEPROM checksum by reading/adding each word of the EEPROM
* and then verifies that the sum of the EEPROM is equal to 0xBABA.
*/
s32 igc_validate_nvm_checksum_i225(struct igc_hw *hw)
{
s32 status = IGC_SUCCESS;
s32 (*read_op_ptr)(struct igc_hw *, u16, u16, u16 *);
DEBUGFUNC("igc_validate_nvm_checksum_i225");
if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
/* Replace the read function with semaphore grabbing with
* the one that skips this for a while.
* We have semaphore taken already here.
*/
read_op_ptr = hw->nvm.ops.read;
hw->nvm.ops.read = igc_read_nvm_eerd;
status = igc_validate_nvm_checksum_generic(hw);
/* Revert original read operation. */
hw->nvm.ops.read = read_op_ptr;
hw->nvm.ops.release(hw);
} else {
status = IGC_ERR_SWFW_SYNC;
}
return status;
}
/* igc_update_nvm_checksum_i225 - Update EEPROM checksum
* @hw: pointer to the HW structure
*
* Updates the EEPROM checksum by reading/adding each word of the EEPROM
* up to the checksum. Then calculates the EEPROM checksum and writes the
* value to the EEPROM. Next commit EEPROM data onto the Flash.
*/
s32 igc_update_nvm_checksum_i225(struct igc_hw *hw)
{
s32 ret_val;
u16 checksum = 0;
u16 i, nvm_data;
DEBUGFUNC("igc_update_nvm_checksum_i225");
/* Read the first word from the EEPROM. If this times out or fails, do
* not continue or we could be in for a very long wait while every
* EEPROM read fails
*/
ret_val = igc_read_nvm_eerd(hw, 0, 1, &nvm_data);
if (ret_val != IGC_SUCCESS) {
DEBUGOUT("EEPROM read failed\n");
goto out;
}
if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
/* Do not use hw->nvm.ops.write, hw->nvm.ops.read
* because we do not want to take the synchronization
* semaphores twice here.
*/
for (i = 0; i < NVM_CHECKSUM_REG; i++) {
ret_val = igc_read_nvm_eerd(hw, i, 1, &nvm_data);
if (ret_val) {
hw->nvm.ops.release(hw);
DEBUGOUT("NVM Read Error while updating\n");
DEBUGOUT("checksum.\n");
goto out;
}
checksum += nvm_data;
}
checksum = (u16)NVM_SUM - checksum;
ret_val = __igc_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,
&checksum);
if (ret_val != IGC_SUCCESS) {
hw->nvm.ops.release(hw);
DEBUGOUT("NVM Write Error while updating checksum.\n");
goto out;
}
hw->nvm.ops.release(hw);
ret_val = igc_update_flash_i225(hw);
} else {
ret_val = IGC_ERR_SWFW_SYNC;
}
out:
return ret_val;
}
/* igc_get_flash_presence_i225 - Check if flash device is detected.
* @hw: pointer to the HW structure
*/
bool igc_get_flash_presence_i225(struct igc_hw *hw)
{
u32 eec = 0;
bool ret_val = false;
DEBUGFUNC("igc_get_flash_presence_i225");
eec = IGC_READ_REG(hw, IGC_EECD);
if (eec & IGC_EECD_FLASH_DETECTED_I225)
ret_val = true;
return ret_val;
}
/* igc_set_flsw_flash_burst_counter_i225 - sets FLSW NVM Burst
* Counter in FLSWCNT register.
*
* @hw: pointer to the HW structure
* @burst_counter: size in bytes of the Flash burst to read or write
*/
s32 igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw,
u32 burst_counter)
{
s32 ret_val = IGC_SUCCESS;
DEBUGFUNC("igc_set_flsw_flash_burst_counter_i225");
/* Validate input data */
if (burst_counter < IGC_I225_SHADOW_RAM_SIZE) {
/* Write FLSWCNT - burst counter */
IGC_WRITE_REG(hw, IGC_I225_FLSWCNT, burst_counter);
} else {
ret_val = IGC_ERR_INVALID_ARGUMENT;
}
return ret_val;
}
/* igc_write_erase_flash_command_i225 - write/erase to a sector
* region on a given address.
*
* @hw: pointer to the HW structure
* @opcode: opcode to be used for the write command
* @address: the offset to write into the FLASH image
*/
s32 igc_write_erase_flash_command_i225(struct igc_hw *hw, u32 opcode,
u32 address)
{
u32 flswctl = 0;
s32 timeout = IGC_NVM_GRANT_ATTEMPTS;
s32 ret_val = IGC_SUCCESS;
DEBUGFUNC("igc_write_erase_flash_command_i225");
flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL);
/* Polling done bit on FLSWCTL register */
while (timeout) {
if (flswctl & IGC_FLSWCTL_DONE)
break;
usec_delay(5);
flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL);
timeout--;
}
if (!timeout) {
DEBUGOUT("Flash transaction was not done\n");
return -IGC_ERR_NVM;
}
/* Build and issue command on FLSWCTL register */
flswctl = address | opcode;
IGC_WRITE_REG(hw, IGC_I225_FLSWCTL, flswctl);
/* Check if issued command is valid on FLSWCTL register */
flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL);
if (!(flswctl & IGC_FLSWCTL_CMDV)) {
DEBUGOUT("Write flash command failed\n");
ret_val = IGC_ERR_INVALID_ARGUMENT;
}
return ret_val;
}
/* igc_update_flash_i225 - Commit EEPROM to the flash
* if fw_valid_bit is set, FW is active. setting FLUPD bit in EEC
* register makes the FW load the internal shadow RAM into the flash.
* Otherwise, fw_valid_bit is 0. if FL_SECU.block_prtotected_sw = 0
* then FW is not active so the SW is responsible shadow RAM dump.
*
* @hw: pointer to the HW structure
*/
s32 igc_update_flash_i225(struct igc_hw *hw)
{
u16 current_offset_data = 0;
u32 block_sw_protect = 1;
u16 base_address = 0x0;
u32 i, fw_valid_bit;
u16 current_offset;
s32 ret_val = 0;
u32 flup;
DEBUGFUNC("igc_update_flash_i225");
block_sw_protect = IGC_READ_REG(hw, IGC_I225_FLSECU) &
IGC_FLSECU_BLK_SW_ACCESS_I225;
fw_valid_bit = IGC_READ_REG(hw, IGC_FWSM) &
IGC_FWSM_FW_VALID_I225;
if (fw_valid_bit) {
ret_val = igc_pool_flash_update_done_i225(hw);
if (ret_val == -IGC_ERR_NVM) {
DEBUGOUT("Flash update time out\n");
goto out;
}
flup = IGC_READ_REG(hw, IGC_EECD) | IGC_EECD_FLUPD_I225;
IGC_WRITE_REG(hw, IGC_EECD, flup);
ret_val = igc_pool_flash_update_done_i225(hw);
if (ret_val == IGC_SUCCESS)
DEBUGOUT("Flash update complete\n");
else
DEBUGOUT("Flash update time out\n");
} else if (!block_sw_protect) {
/* FW is not active and security protection is disabled.
* therefore, SW is in charge of shadow RAM dump.
* Check which sector is valid. if sector 0 is valid,
* base address remains 0x0. otherwise, sector 1 is
* valid and it's base address is 0x1000
*/
if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_SEC1VAL_I225)
base_address = 0x1000;
/* Valid sector erase */
ret_val = igc_write_erase_flash_command_i225(hw,
IGC_I225_ERASE_CMD_OPCODE,
base_address);
if (!ret_val) {
DEBUGOUT("Sector erase failed\n");
goto out;
}
current_offset = base_address;
/* Write */
for (i = 0; i < IGC_I225_SHADOW_RAM_SIZE / 2; i++) {
/* Set burst write length */
ret_val = igc_set_flsw_flash_burst_counter_i225(hw,
0x2);
if (ret_val != IGC_SUCCESS)
break;
/* Set address and opcode */
ret_val = igc_write_erase_flash_command_i225(hw,
IGC_I225_WRITE_CMD_OPCODE,
2 * current_offset);
if (ret_val != IGC_SUCCESS)
break;
ret_val = igc_read_nvm_eerd(hw, current_offset,
1, ¤t_offset_data);
if (ret_val) {
DEBUGOUT("Failed to read from EEPROM\n");
goto out;
}
/* Write CurrentOffseData to FLSWDATA register */
IGC_WRITE_REG(hw, IGC_I225_FLSWDATA,
current_offset_data);
current_offset++;
/* Wait till operation has finished */
ret_val = igc_poll_eerd_eewr_done(hw,
IGC_NVM_POLL_READ);
if (ret_val)
break;
usec_delay(1000);
}
}
out:
return ret_val;
}
/* igc_pool_flash_update_done_i225 - Pool FLUDONE status.
* @hw: pointer to the HW structure
*/
s32 igc_pool_flash_update_done_i225(struct igc_hw *hw)
{
s32 ret_val = -IGC_ERR_NVM;
u32 i, reg;
DEBUGFUNC("igc_pool_flash_update_done_i225");
for (i = 0; i < IGC_FLUDONE_ATTEMPTS; i++) {
reg = IGC_READ_REG(hw, IGC_EECD);
if (reg & IGC_EECD_FLUDONE_I225) {
ret_val = IGC_SUCCESS;
break;
}
usec_delay(5);
}
return ret_val;
}
/* igc_set_ltr_i225 - Set Latency Tolerance Reporting thresholds.
* @hw: pointer to the HW structure
* @link: bool indicating link status
*
* Set the LTR thresholds based on the link speed (Mbps), EEE, and DMAC
* settings, otherwise specify that there is no LTR requirement.
*/
static s32 igc_set_ltr_i225(struct igc_hw *hw, bool link)
{
u16 speed, duplex;
u32 tw_system, ltrc, ltrv, ltr_min, ltr_max, scale_min, scale_max;
s32 size;
DEBUGFUNC("igc_set_ltr_i225");
/* If we do not have link, LTR thresholds are zero. */
if (link) {
hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
/* Check if using copper interface with EEE enabled or if the
* link speed is 10 Mbps.
*/
if ((hw->phy.media_type == igc_media_type_copper) &&
!(hw->dev_spec._i225.eee_disable) &&
(speed != SPEED_10)) {
/* EEE enabled, so send LTRMAX threshold. */
ltrc = IGC_READ_REG(hw, IGC_LTRC) |
IGC_LTRC_EEEMS_EN;
IGC_WRITE_REG(hw, IGC_LTRC, ltrc);
/* Calculate tw_system (nsec). */
if (speed == SPEED_100) {
tw_system = ((IGC_READ_REG(hw, IGC_EEE_SU) &
IGC_TW_SYSTEM_100_MASK) >>
IGC_TW_SYSTEM_100_SHIFT) * 500;
} else {
tw_system = (IGC_READ_REG(hw, IGC_EEE_SU) &
IGC_TW_SYSTEM_1000_MASK) * 500;
}
} else {
tw_system = 0;
}
/* Get the Rx packet buffer size. */
size = IGC_READ_REG(hw, IGC_RXPBS) &
IGC_RXPBS_SIZE_I225_MASK;
/* Calculations vary based on DMAC settings. */
if (IGC_READ_REG(hw, IGC_DMACR) & IGC_DMACR_DMAC_EN) {
size -= (IGC_READ_REG(hw, IGC_DMACR) &
IGC_DMACR_DMACTHR_MASK) >>
IGC_DMACR_DMACTHR_SHIFT;
/* Convert size to bits. */
size *= 1024 * 8;
} else {
/* Convert size to bytes, subtract the MTU, and then
* convert the size to bits.
*/
size *= 1024;
size -= hw->dev_spec._i225.mtu;
size *= 8;
}
if (size < 0) {
DEBUGOUT1("Invalid effective Rx buffer size %d\n",
size);
return -IGC_ERR_CONFIG;
}
/* Calculate the thresholds. Since speed is in Mbps, simplify
* the calculation by multiplying size/speed by 1000 for result
* to be in nsec before dividing by the scale in nsec. Set the
* scale such that the LTR threshold fits in the register.
*/
ltr_min = (1000 * size) / speed;
ltr_max = ltr_min + tw_system;
scale_min = (ltr_min / 1024) < 1024 ? IGC_LTRMINV_SCALE_1024 :
IGC_LTRMINV_SCALE_32768;
scale_max = (ltr_max / 1024) < 1024 ? IGC_LTRMAXV_SCALE_1024 :
IGC_LTRMAXV_SCALE_32768;
ltr_min /= scale_min == IGC_LTRMINV_SCALE_1024 ? 1024 : 32768;
ltr_max /= scale_max == IGC_LTRMAXV_SCALE_1024 ? 1024 : 32768;
/* Only write the LTR thresholds if they differ from before. */
ltrv = IGC_READ_REG(hw, IGC_LTRMINV);
if (ltr_min != (ltrv & IGC_LTRMINV_LTRV_MASK)) {
ltrv = IGC_LTRMINV_LSNP_REQ | ltr_min |
(scale_min << IGC_LTRMINV_SCALE_SHIFT);
IGC_WRITE_REG(hw, IGC_LTRMINV, ltrv);
}
ltrv = IGC_READ_REG(hw, IGC_LTRMAXV);
if (ltr_max != (ltrv & IGC_LTRMAXV_LTRV_MASK)) {
ltrv = IGC_LTRMAXV_LSNP_REQ | ltr_max |
(scale_min << IGC_LTRMAXV_SCALE_SHIFT);
IGC_WRITE_REG(hw, IGC_LTRMAXV, ltrv);
}
}
return IGC_SUCCESS;
}
/* igc_check_for_link_i225 - Check for link
* @hw: pointer to the HW structure
*
* Checks to see of the link status of the hardware has changed. If a
* change in link status has been detected, then we read the PHY registers
* to get the current speed/duplex if link exists.
*/
s32 igc_check_for_link_i225(struct igc_hw *hw)
{
struct igc_mac_info *mac = &hw->mac;
s32 ret_val;
bool link = false;
DEBUGFUNC("igc_check_for_link_i225");
/* We only want to go out to the PHY registers to see if
* Auto-Neg has completed and/or if our link status has
* changed. The get_link_status flag is set upon receiving
* a Link Status Change or Rx Sequence Error interrupt.
*/
if (!mac->get_link_status) {
ret_val = IGC_SUCCESS;
goto out;
}
/* First we want to see if the MII Status Register reports
* link. If so, then we want to get the current speed/duplex
* of the PHY.
*/
ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
if (ret_val)
goto out;
if (!link)
goto out; /* No link detected */
/* First we want to see if the MII Status Register reports
* link. If so, then we want to get the current speed/duplex
* of the PHY.
*/
ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
if (ret_val)
goto out;
if (!link)
goto out; /* No link detected */
mac->get_link_status = false;
/* Check if there was DownShift, must be checked
* immediately after link-up
*/
igc_check_downshift_generic(hw);
/* If we are forcing speed/duplex, then we simply return since
* we have already determined whether we have link or not.
*/
if (!mac->autoneg)
goto out;
/* Auto-Neg is enabled. Auto Speed Detection takes care
* of MAC speed/duplex configuration. So we only need to
* configure Collision Distance in the MAC.
*/
mac->ops.config_collision_dist(hw);
/* Configure Flow Control now that Auto-Neg has completed.
* First, we need to restore the desired flow control
* settings because we may have had to re-autoneg with a
* different link partner.
*/
ret_val = igc_config_fc_after_link_up_generic(hw);
if (ret_val)
DEBUGOUT("Error configuring flow control\n");
out:
/* Now that we are aware of our link settings, we can set the LTR
* thresholds.
*/
ret_val = igc_set_ltr_i225(hw, link);
return ret_val;
}
/* igc_init_function_pointers_i225 - Init func ptrs.
* @hw: pointer to the HW structure
*
* Called to initialize all function pointers and parameters.
*/
void igc_init_function_pointers_i225(struct igc_hw *hw)
{
igc_init_mac_ops_generic(hw);
igc_init_phy_ops_generic(hw);
igc_init_nvm_ops_generic(hw);
hw->mac.ops.init_params = igc_init_mac_params_i225;
hw->nvm.ops.init_params = igc_init_nvm_params_i225;
hw->phy.ops.init_params = igc_init_phy_params_i225;
}
/* igc_init_hw_i225 - Init hw for I225
* @hw: pointer to the HW structure
*
* Called to initialize hw for i225 hw family.
*/
s32 igc_init_hw_i225(struct igc_hw *hw)
{
s32 ret_val;
DEBUGFUNC("igc_init_hw_i225");
ret_val = igc_init_hw_base(hw);
return ret_val;
}
/*
* igc_set_d0_lplu_state_i225 - Set Low-Power-Link-Up (LPLU) D0 state
* @hw: pointer to the HW structure
* @active: true to enable LPLU, false to disable
*
* Note: since I225 does not actually support LPLU, this function
* simply enables/disables 1G and 2.5G speeds in D0.
*/
s32 igc_set_d0_lplu_state_i225(struct igc_hw *hw, bool active)
{
u32 data;
DEBUGFUNC("igc_set_d0_lplu_state_i225");
data = IGC_READ_REG(hw, IGC_I225_PHPM);
if (active) {
data |= IGC_I225_PHPM_DIS_1000;
data |= IGC_I225_PHPM_DIS_2500;
} else {
data &= ~IGC_I225_PHPM_DIS_1000;
data &= ~IGC_I225_PHPM_DIS_2500;
}
IGC_WRITE_REG(hw, IGC_I225_PHPM, data);
return IGC_SUCCESS;
}
/*
* igc_set_d3_lplu_state_i225 - Set Low-Power-Link-Up (LPLU) D3 state
* @hw: pointer to the HW structure
* @active: true to enable LPLU, false to disable
*
* Note: since I225 does not actually support LPLU, this function
* simply enables/disables 100M, 1G and 2.5G speeds in D3.
*/
s32 igc_set_d3_lplu_state_i225(struct igc_hw *hw, bool active)
{
u32 data;
DEBUGFUNC("igc_set_d3_lplu_state_i225");
data = IGC_READ_REG(hw, IGC_I225_PHPM);
if (active) {
data |= IGC_I225_PHPM_DIS_100_D3;
data |= IGC_I225_PHPM_DIS_1000_D3;
data |= IGC_I225_PHPM_DIS_2500_D3;
} else {
data &= ~IGC_I225_PHPM_DIS_100_D3;
data &= ~IGC_I225_PHPM_DIS_1000_D3;
data &= ~IGC_I225_PHPM_DIS_2500_D3;
}
IGC_WRITE_REG(hw, IGC_I225_PHPM, data);
return IGC_SUCCESS;
}
/**
* igc_set_eee_i225 - Enable/disable EEE support
* @hw: pointer to the HW structure
* @adv2p5G: boolean flag enabling 2.5G EEE advertisement
* @adv1G: boolean flag enabling 1G EEE advertisement
* @adv100M: boolean flag enabling 100M EEE advertisement
*
* Enable/disable EEE based on setting in dev_spec structure.
*
**/
s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G,
bool adv100M)
{
u32 ipcnfg, eeer;
DEBUGFUNC("igc_set_eee_i225");
if (hw->mac.type != igc_i225 ||
hw->phy.media_type != igc_media_type_copper)
goto out;
ipcnfg = IGC_READ_REG(hw, IGC_IPCNFG);
eeer = IGC_READ_REG(hw, IGC_EEER);
/* enable or disable per user setting */
if (!(hw->dev_spec._i225.eee_disable)) {
u32 eee_su = IGC_READ_REG(hw, IGC_EEE_SU);
if (adv100M)
ipcnfg |= IGC_IPCNFG_EEE_100M_AN;
else
ipcnfg &= ~IGC_IPCNFG_EEE_100M_AN;
if (adv1G)
ipcnfg |= IGC_IPCNFG_EEE_1G_AN;
else
ipcnfg &= ~IGC_IPCNFG_EEE_1G_AN;
if (adv2p5G)
ipcnfg |= IGC_IPCNFG_EEE_2_5G_AN;
else
ipcnfg &= ~IGC_IPCNFG_EEE_2_5G_AN;
eeer |= (IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN |
IGC_EEER_LPI_FC);
/* This bit should not be set in normal operation. */
if (eee_su & IGC_EEE_SU_LPI_CLK_STP)
DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
} else {
ipcnfg &= ~(IGC_IPCNFG_EEE_2_5G_AN | IGC_IPCNFG_EEE_1G_AN |
IGC_IPCNFG_EEE_100M_AN);
eeer &= ~(IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN |
IGC_EEER_LPI_FC);
}
IGC_WRITE_REG(hw, IGC_IPCNFG, ipcnfg);
IGC_WRITE_REG(hw, IGC_EEER, eeer);
IGC_READ_REG(hw, IGC_IPCNFG);
IGC_READ_REG(hw, IGC_EEER);
out:
return IGC_SUCCESS;
}
diff --git a/sys/dev/igc/igc_phy.c b/sys/dev/igc/igc_phy.c
index a1d71ab15829..a6823ddf7bac 100644
--- a/sys/dev/igc/igc_phy.c
+++ b/sys/dev/igc/igc_phy.c
@@ -1,1109 +1,1076 @@
/*-
* Copyright 2021 Intel Corp
* Copyright 2021 Rubicon Communications, LLC (Netgate)
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "igc_api.h"
static s32 igc_wait_autoneg(struct igc_hw *hw);
/**
* igc_init_phy_ops_generic - Initialize PHY function pointers
* @hw: pointer to the HW structure
*
* Setups up the function pointers to no-op functions
**/
void igc_init_phy_ops_generic(struct igc_hw *hw)
{
struct igc_phy_info *phy = &hw->phy;
DEBUGFUNC("igc_init_phy_ops_generic");
/* Initialize function pointers */
phy->ops.init_params = igc_null_ops_generic;
phy->ops.acquire = igc_null_ops_generic;
phy->ops.check_reset_block = igc_null_ops_generic;
- phy->ops.commit = igc_null_ops_generic;
phy->ops.force_speed_duplex = igc_null_ops_generic;
phy->ops.get_info = igc_null_ops_generic;
phy->ops.set_page = igc_null_set_page;
phy->ops.read_reg = igc_null_read_reg;
phy->ops.read_reg_locked = igc_null_read_reg;
phy->ops.read_reg_page = igc_null_read_reg;
phy->ops.release = igc_null_phy_generic;
phy->ops.reset = igc_null_ops_generic;
phy->ops.set_d0_lplu_state = igc_null_lplu_state;
phy->ops.set_d3_lplu_state = igc_null_lplu_state;
phy->ops.write_reg = igc_null_write_reg;
phy->ops.write_reg_locked = igc_null_write_reg;
phy->ops.write_reg_page = igc_null_write_reg;
phy->ops.power_up = igc_null_phy_generic;
phy->ops.power_down = igc_null_phy_generic;
}
/**
* igc_null_set_page - No-op function, return 0
* @hw: pointer to the HW structure
* @data: dummy variable
**/
s32 igc_null_set_page(struct igc_hw IGC_UNUSEDARG *hw,
u16 IGC_UNUSEDARG data)
{
DEBUGFUNC("igc_null_set_page");
return IGC_SUCCESS;
}
/**
* igc_null_read_reg - No-op function, return 0
* @hw: pointer to the HW structure
* @offset: dummy variable
* @data: dummy variable
**/
s32 igc_null_read_reg(struct igc_hw IGC_UNUSEDARG *hw,
u32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG *data)
{
DEBUGFUNC("igc_null_read_reg");
return IGC_SUCCESS;
}
/**
* igc_null_phy_generic - No-op function, return void
* @hw: pointer to the HW structure
**/
void igc_null_phy_generic(struct igc_hw IGC_UNUSEDARG *hw)
{
DEBUGFUNC("igc_null_phy_generic");
return;
}
/**
* igc_null_lplu_state - No-op function, return 0
* @hw: pointer to the HW structure
* @active: dummy variable
**/
s32 igc_null_lplu_state(struct igc_hw IGC_UNUSEDARG *hw,
bool IGC_UNUSEDARG active)
{
DEBUGFUNC("igc_null_lplu_state");
return IGC_SUCCESS;
}
/**
* igc_null_write_reg - No-op function, return 0
* @hw: pointer to the HW structure
* @offset: dummy variable
* @data: dummy variable
**/
s32 igc_null_write_reg(struct igc_hw IGC_UNUSEDARG *hw,
u32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG data)
{
DEBUGFUNC("igc_null_write_reg");
return IGC_SUCCESS;
}
/**
* igc_check_reset_block_generic - Check if PHY reset is blocked
* @hw: pointer to the HW structure
*
* Read the PHY management control register and check whether a PHY reset
* is blocked. If a reset is not blocked return IGC_SUCCESS, otherwise
* return IGC_BLK_PHY_RESET (12).
**/
s32 igc_check_reset_block_generic(struct igc_hw *hw)
{
u32 manc;
DEBUGFUNC("igc_check_reset_block");
manc = IGC_READ_REG(hw, IGC_MANC);
return (manc & IGC_MANC_BLK_PHY_RST_ON_IDE) ?
IGC_BLK_PHY_RESET : IGC_SUCCESS;
}
/**
* igc_get_phy_id - Retrieve the PHY ID and revision
* @hw: pointer to the HW structure
*
* Reads the PHY registers and stores the PHY ID and possibly the PHY
* revision in the hardware structure.
**/
s32 igc_get_phy_id(struct igc_hw *hw)
{
struct igc_phy_info *phy = &hw->phy;
s32 ret_val = IGC_SUCCESS;
u16 phy_id;
DEBUGFUNC("igc_get_phy_id");
if (!phy->ops.read_reg)
return IGC_SUCCESS;
ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
if (ret_val)
return ret_val;
phy->id = (u32)(phy_id << 16);
- usec_delay(20);
+ usec_delay(200);
ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
if (ret_val)
return ret_val;
phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
-
return IGC_SUCCESS;
}
/**
* igc_read_phy_reg_mdic - Read MDI control register
* @hw: pointer to the HW structure
* @offset: register offset to be read
* @data: pointer to the read data
*
* Reads the MDI control register in the PHY at offset and stores the
* information read to data.
**/
s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data)
{
struct igc_phy_info *phy = &hw->phy;
u32 i, mdic = 0;
DEBUGFUNC("igc_read_phy_reg_mdic");
if (offset > MAX_PHY_REG_ADDRESS) {
DEBUGOUT1("PHY Address %d is out of range\n", offset);
return -IGC_ERR_PARAM;
}
/* Set up Op-code, Phy Address, and register offset in the MDI
* Control register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
mdic = ((offset << IGC_MDIC_REG_SHIFT) |
(phy->addr << IGC_MDIC_PHY_SHIFT) |
(IGC_MDIC_OP_READ));
IGC_WRITE_REG(hw, IGC_MDIC, mdic);
/* Poll the ready bit to see if the MDI read completed
* Increasing the time out as testing showed failures with
* the lower time out
*/
for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) {
usec_delay_irq(50);
mdic = IGC_READ_REG(hw, IGC_MDIC);
if (mdic & IGC_MDIC_READY)
break;
}
if (!(mdic & IGC_MDIC_READY)) {
DEBUGOUT("MDI Read did not complete\n");
return -IGC_ERR_PHY;
}
if (mdic & IGC_MDIC_ERROR) {
DEBUGOUT("MDI Error\n");
return -IGC_ERR_PHY;
}
if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) {
DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
offset,
(mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT);
return -IGC_ERR_PHY;
}
*data = (u16) mdic;
return IGC_SUCCESS;
}
/**
* igc_write_phy_reg_mdic - Write MDI control register
* @hw: pointer to the HW structure
* @offset: register offset to write to
* @data: data to write to register at offset
*
* Writes data to MDI control register in the PHY at offset.
**/
s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data)
{
struct igc_phy_info *phy = &hw->phy;
u32 i, mdic = 0;
DEBUGFUNC("igc_write_phy_reg_mdic");
if (offset > MAX_PHY_REG_ADDRESS) {
DEBUGOUT1("PHY Address %d is out of range\n", offset);
return -IGC_ERR_PARAM;
}
/* Set up Op-code, Phy Address, and register offset in the MDI
* Control register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
mdic = (((u32)data) |
(offset << IGC_MDIC_REG_SHIFT) |
(phy->addr << IGC_MDIC_PHY_SHIFT) |
(IGC_MDIC_OP_WRITE));
IGC_WRITE_REG(hw, IGC_MDIC, mdic);
/* Poll the ready bit to see if the MDI read completed
* Increasing the time out as testing showed failures with
* the lower time out
*/
for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) {
usec_delay_irq(50);
mdic = IGC_READ_REG(hw, IGC_MDIC);
if (mdic & IGC_MDIC_READY)
break;
}
if (!(mdic & IGC_MDIC_READY)) {
DEBUGOUT("MDI Write did not complete\n");
return -IGC_ERR_PHY;
}
if (mdic & IGC_MDIC_ERROR) {
DEBUGOUT("MDI Error\n");
return -IGC_ERR_PHY;
}
if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) {
DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
offset,
(mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT);
return -IGC_ERR_PHY;
}
return IGC_SUCCESS;
}
/**
* igc_phy_setup_autoneg - Configure PHY for auto-negotiation
* @hw: pointer to the HW structure
*
* Reads the MII auto-neg advertisement register and/or the 1000T control
* register and if the PHY is already setup for auto-negotiation, then
* return successful. Otherwise, setup advertisement and flow control to
* the appropriate values for the wanted auto-negotiation.
**/
static s32 igc_phy_setup_autoneg(struct igc_hw *hw)
{
struct igc_phy_info *phy = &hw->phy;
s32 ret_val;
u16 mii_autoneg_adv_reg;
u16 mii_1000t_ctrl_reg = 0;
u16 aneg_multigbt_an_ctrl = 0;
DEBUGFUNC("igc_phy_setup_autoneg");
phy->autoneg_advertised &= phy->autoneg_mask;
/* Read the MII Auto-Neg Advertisement Register (Address 4). */
ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
if (ret_val)
return ret_val;
if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
/* Read the MII 1000Base-T Control Register (Address 9). */
ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
&mii_1000t_ctrl_reg);
if (ret_val)
return ret_val;
}
if ((phy->autoneg_mask & ADVERTISE_2500_FULL) &&
hw->phy.id == I225_I_PHY_ID) {
- /* Read the MULTI GBT AN Control Register - reg 7.32 */
+ /* Read the MULTI GBT AN Control Register - reg 7.32 */
ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<
MMD_DEVADDR_SHIFT) |
ANEG_MULTIGBT_AN_CTRL,
&aneg_multigbt_an_ctrl);
if (ret_val)
return ret_val;
}
/* Need to parse both autoneg_advertised and fc and set up
* the appropriate PHY registers. First we will parse for
* autoneg_advertised software override. Since we can advertise
* a plethora of combinations, we need to check each bit
* individually.
*/
/* First we clear all the 10/100 mb speed bits in the Auto-Neg
* Advertisement Register (Address 4) and the 1000 mb speed bits in
* the 1000Base-T Control Register (Address 9).
*/
mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
NWAY_AR_100TX_HD_CAPS |
NWAY_AR_10T_FD_CAPS |
NWAY_AR_10T_HD_CAPS);
mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
/* Do we want to advertise 10 Mb Half Duplex? */
if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
DEBUGOUT("Advertise 10mb Half duplex\n");
mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
}
/* Do we want to advertise 10 Mb Full Duplex? */
if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
DEBUGOUT("Advertise 10mb Full duplex\n");
mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
}
/* Do we want to advertise 100 Mb Half Duplex? */
if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
DEBUGOUT("Advertise 100mb Half duplex\n");
mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
}
/* Do we want to advertise 100 Mb Full Duplex? */
if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
DEBUGOUT("Advertise 100mb Full duplex\n");
mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
}
/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
/* Do we want to advertise 1000 Mb Full Duplex? */
if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
DEBUGOUT("Advertise 1000mb Full duplex\n");
mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
}
/* We do not allow the Phy to advertise 2500 Mb Half Duplex */
if (phy->autoneg_advertised & ADVERTISE_2500_HALF)
DEBUGOUT("Advertise 2500mb Half duplex request denied!\n");
/* Do we want to advertise 2500 Mb Full Duplex? */
if (phy->autoneg_advertised & ADVERTISE_2500_FULL) {
DEBUGOUT("Advertise 2500mb Full duplex\n");
aneg_multigbt_an_ctrl |= CR_2500T_FD_CAPS;
} else {
aneg_multigbt_an_ctrl &= ~CR_2500T_FD_CAPS;
}
/* Check for a software override of the flow control settings, and
* setup the PHY advertisement registers accordingly. If
* auto-negotiation is enabled, then software will have to set the
* "PAUSE" bits to the correct value in the Auto-Negotiation
* Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
* negotiation.
*
* The possible values of the "fc" parameter are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames
* but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames
* but we do not support receiving pause frames).
* 3: Both Rx and Tx flow control (symmetric) are enabled.
* other: No software override. The flow control configuration
* in the EEPROM is used.
*/
switch (hw->fc.current_mode) {
case igc_fc_none:
/* Flow control (Rx & Tx) is completely disabled by a
* software over-ride.
*/
mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
break;
case igc_fc_rx_pause:
/* Rx Flow control is enabled, and Tx Flow control is
* disabled, by a software over-ride.
*
* Since there really isn't a way to advertise that we are
* capable of Rx Pause ONLY, we will advertise that we
* support both symmetric and asymmetric Rx PAUSE. Later
* (in igc_config_fc_after_link_up) we will disable the
* hw's ability to send PAUSE frames.
*/
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
break;
case igc_fc_tx_pause:
/* Tx Flow control is enabled, and Rx Flow control is
* disabled, by a software over-ride.
*/
mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
break;
case igc_fc_full:
/* Flow control (both Rx and Tx) is enabled by a software
* over-ride.
*/
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
break;
default:
DEBUGOUT("Flow control param set incorrectly\n");
return -IGC_ERR_CONFIG;
}
ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
if (ret_val)
return ret_val;
DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
if (phy->autoneg_mask & ADVERTISE_1000_FULL)
ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
mii_1000t_ctrl_reg);
if ((phy->autoneg_mask & ADVERTISE_2500_FULL) &&
hw->phy.id == I225_I_PHY_ID)
ret_val = phy->ops.write_reg(hw,
(STANDARD_AN_REG_MASK <<
MMD_DEVADDR_SHIFT) |
ANEG_MULTIGBT_AN_CTRL,
aneg_multigbt_an_ctrl);
return ret_val;
}
/**
* igc_copper_link_autoneg - Setup/Enable autoneg for copper link
* @hw: pointer to the HW structure
*
* Performs initial bounds checking on autoneg advertisement parameter, then
* configure to advertise the full capability. Setup the PHY to autoneg
* and restart the negotiation process between the link partner. If
* autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
**/
static s32 igc_copper_link_autoneg(struct igc_hw *hw)
{
struct igc_phy_info *phy = &hw->phy;
s32 ret_val;
u16 phy_ctrl;
DEBUGFUNC("igc_copper_link_autoneg");
/* Perform some bounds checking on the autoneg advertisement
* parameter.
*/
phy->autoneg_advertised &= phy->autoneg_mask;
/* If autoneg_advertised is zero, we assume it was not defaulted
* by the calling code so we set to advertise full capability.
*/
if (!phy->autoneg_advertised)
phy->autoneg_advertised = phy->autoneg_mask;
DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
ret_val = igc_phy_setup_autoneg(hw);
if (ret_val) {
DEBUGOUT("Error Setting up Auto-Negotiation\n");
return ret_val;
}
DEBUGOUT("Restarting Auto-Neg\n");
/* Restart auto-negotiation by setting the Auto Neg Enable bit and
* the Auto Neg Restart bit in the PHY control register.
*/
ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
if (ret_val)
return ret_val;
phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
if (ret_val)
return ret_val;
/* Does the user want to wait for Auto-Neg to complete here, or
* check at a later time (for example, callback routine).
*/
if (phy->autoneg_wait_to_complete) {
ret_val = igc_wait_autoneg(hw);
if (ret_val) {
DEBUGOUT("Error while waiting for autoneg to complete\n");
return ret_val;
}
}
hw->mac.get_link_status = true;
return ret_val;
}
/**
* igc_setup_copper_link_generic - Configure copper link settings
* @hw: pointer to the HW structure
*
* Calls the appropriate function to configure the link for auto-neg or forced
* speed and duplex. Then we check for link, once link is established calls
* to configure collision distance and flow control are called. If link is
* not established, we return -IGC_ERR_PHY (-2).
**/
s32 igc_setup_copper_link_generic(struct igc_hw *hw)
{
s32 ret_val;
bool link;
DEBUGFUNC("igc_setup_copper_link_generic");
if (hw->mac.autoneg) {
/* Setup autoneg and flow control advertisement and perform
* autonegotiation.
*/
ret_val = igc_copper_link_autoneg(hw);
if (ret_val)
return ret_val;
} else {
/* PHY will be set to 10H, 10F, 100H or 100F
* depending on user settings.
*/
DEBUGOUT("Forcing Speed and Duplex\n");
ret_val = hw->phy.ops.force_speed_duplex(hw);
if (ret_val) {
DEBUGOUT("Error Forcing Speed and Duplex\n");
return ret_val;
}
}
/* Check link status. Wait up to 100 microseconds for link to become
* valid.
*/
ret_val = igc_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
&link);
if (ret_val)
return ret_val;
if (link) {
DEBUGOUT("Valid link established!!!\n");
hw->mac.ops.config_collision_dist(hw);
ret_val = igc_config_fc_after_link_up_generic(hw);
} else {
DEBUGOUT("Unable to establish link!!!\n");
}
return ret_val;
}
/**
* igc_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
* @hw: pointer to the HW structure
* @phy_ctrl: pointer to current value of PHY_CONTROL
*
* Forces speed and duplex on the PHY by doing the following: disable flow
* control, force speed/duplex on the MAC, disable auto speed detection,
* disable auto-negotiation, configure duplex, configure speed, configure
* the collision distance, write configuration to CTRL register. The
* caller must write to the PHY_CONTROL register for these settings to
* take affect.
**/
void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl)
{
struct igc_mac_info *mac = &hw->mac;
u32 ctrl;
DEBUGFUNC("igc_phy_force_speed_duplex_setup");
/* Turn off flow control when forcing speed/duplex */
hw->fc.current_mode = igc_fc_none;
/* Force speed/duplex on the mac */
ctrl = IGC_READ_REG(hw, IGC_CTRL);
ctrl |= (IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);
ctrl &= ~IGC_CTRL_SPD_SEL;
/* Disable Auto Speed Detection */
ctrl &= ~IGC_CTRL_ASDE;
/* Disable autoneg on the phy */
*phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
/* Forcing Full or Half Duplex? */
if (mac->forced_speed_duplex & IGC_ALL_HALF_DUPLEX) {
ctrl &= ~IGC_CTRL_FD;
*phy_ctrl &= ~MII_CR_FULL_DUPLEX;
DEBUGOUT("Half Duplex\n");
} else {
ctrl |= IGC_CTRL_FD;
*phy_ctrl |= MII_CR_FULL_DUPLEX;
DEBUGOUT("Full Duplex\n");
}
/* Forcing 10mb or 100mb? */
if (mac->forced_speed_duplex & IGC_ALL_100_SPEED) {
ctrl |= IGC_CTRL_SPD_100;
*phy_ctrl |= MII_CR_SPEED_100;
*phy_ctrl &= ~MII_CR_SPEED_1000;
DEBUGOUT("Forcing 100mb\n");
} else {
ctrl &= ~(IGC_CTRL_SPD_1000 | IGC_CTRL_SPD_100);
*phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
DEBUGOUT("Forcing 10mb\n");
}
hw->mac.ops.config_collision_dist(hw);
IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
}
/**
* igc_set_d3_lplu_state_generic - Sets low power link up state for D3
* @hw: pointer to the HW structure
* @active: boolean used to enable/disable lplu
*
* Success returns 0, Failure returns 1
*
* The low power link up (lplu) state is set to the power management level D3
* and SmartSpeed is disabled when active is true, else clear lplu for D3
* and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
* is used during Dx states where the power conservation is most important.
* During driver activity, SmartSpeed should be enabled so performance is
* maintained.
**/
s32 igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active)
{
struct igc_phy_info *phy = &hw->phy;
s32 ret_val;
u16 data;
DEBUGFUNC("igc_set_d3_lplu_state_generic");
if (!hw->phy.ops.read_reg)
return IGC_SUCCESS;
ret_val = phy->ops.read_reg(hw, IGP02IGC_PHY_POWER_MGMT, &data);
if (ret_val)
return ret_val;
if (!active) {
data &= ~IGP02IGC_PM_D3_LPLU;
ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
data);
if (ret_val)
return ret_val;
/* LPLU and SmartSpeed are mutually exclusive. LPLU is used
* during Dx states where the power conservation is most
* important. During driver activity we should enable
* SmartSpeed, so performance is maintained.
*/
if (phy->smart_speed == igc_smart_speed_on) {
ret_val = phy->ops.read_reg(hw,
IGP01IGC_PHY_PORT_CONFIG,
&data);
if (ret_val)
return ret_val;
data |= IGP01IGC_PSCFR_SMART_SPEED;
ret_val = phy->ops.write_reg(hw,
IGP01IGC_PHY_PORT_CONFIG,
data);
if (ret_val)
return ret_val;
} else if (phy->smart_speed == igc_smart_speed_off) {
ret_val = phy->ops.read_reg(hw,
IGP01IGC_PHY_PORT_CONFIG,
&data);
if (ret_val)
return ret_val;
data &= ~IGP01IGC_PSCFR_SMART_SPEED;
ret_val = phy->ops.write_reg(hw,
IGP01IGC_PHY_PORT_CONFIG,
data);
if (ret_val)
return ret_val;
}
} else if ((phy->autoneg_advertised == IGC_ALL_SPEED_DUPLEX) ||
(phy->autoneg_advertised == IGC_ALL_NOT_GIG) ||
(phy->autoneg_advertised == IGC_ALL_10_SPEED)) {
data |= IGP02IGC_PM_D3_LPLU;
ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
data);
if (ret_val)
return ret_val;
/* When LPLU is enabled, we should disable SmartSpeed */
ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
&data);
if (ret_val)
return ret_val;
data &= ~IGP01IGC_PSCFR_SMART_SPEED;
ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
data);
}
return ret_val;
}
/**
* igc_check_downshift_generic - Checks whether a downshift in speed occurred
* @hw: pointer to the HW structure
*
* Success returns 0, Failure returns 1
*
* A downshift is detected by querying the PHY link health.
**/
s32 igc_check_downshift_generic(struct igc_hw *hw)
{
struct igc_phy_info *phy = &hw->phy;
s32 ret_val;
DEBUGFUNC("igc_check_downshift_generic");
switch (phy->type) {
case igc_phy_i225:
default:
/* speed downshift not supported */
phy->speed_downgraded = false;
return IGC_SUCCESS;
}
return ret_val;
}
/**
* igc_wait_autoneg - Wait for auto-neg completion
* @hw: pointer to the HW structure
*
* Waits for auto-negotiation to complete or for the auto-negotiation time
* limit to expire, which ever happens first.
**/
static s32 igc_wait_autoneg(struct igc_hw *hw)
{
s32 ret_val = IGC_SUCCESS;
u16 i, phy_status;
DEBUGFUNC("igc_wait_autoneg");
if (!hw->phy.ops.read_reg)
return IGC_SUCCESS;
/* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
if (ret_val)
break;
ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
if (ret_val)
break;
if (phy_status & MII_SR_AUTONEG_COMPLETE)
break;
msec_delay(100);
}
/* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
* has completed.
*/
return ret_val;
}
/**
* igc_phy_has_link_generic - Polls PHY for link
* @hw: pointer to the HW structure
* @iterations: number of times to poll for link
* @usec_interval: delay between polling attempts
* @success: pointer to whether polling was successful or not
*
* Polls the PHY status register for link, 'iterations' number of times.
**/
s32 igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations,
u32 usec_interval, bool *success)
{
s32 ret_val = IGC_SUCCESS;
u16 i, phy_status;
DEBUGFUNC("igc_phy_has_link_generic");
if (!hw->phy.ops.read_reg)
return IGC_SUCCESS;
for (i = 0; i < iterations; i++) {
/* Some PHYs require the PHY_STATUS register to be read
* twice due to the link bit being sticky. No harm doing
* it across the board.
*/
ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
if (ret_val) {
/* If the first read fails, another entity may have
* ownership of the resources, wait and try again to
* see if they have relinquished the resources yet.
*/
if (usec_interval >= 1000)
msec_delay(usec_interval/1000);
else
usec_delay(usec_interval);
}
ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
if (ret_val)
break;
if (phy_status & MII_SR_LINK_STATUS)
break;
if (usec_interval >= 1000)
msec_delay(usec_interval/1000);
else
usec_delay(usec_interval);
}
*success = (i < iterations);
return ret_val;
}
-/**
- * igc_phy_sw_reset_generic - PHY software reset
- * @hw: pointer to the HW structure
- *
- * Does a software reset of the PHY by reading the PHY control register and
- * setting/write the control register reset bit to the PHY.
- **/
-s32 igc_phy_sw_reset_generic(struct igc_hw *hw)
-{
- s32 ret_val;
- u16 phy_ctrl;
-
- DEBUGFUNC("igc_phy_sw_reset_generic");
-
- if (!hw->phy.ops.read_reg)
- return IGC_SUCCESS;
-
- ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
- if (ret_val)
- return ret_val;
-
- phy_ctrl |= MII_CR_RESET;
- ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
- if (ret_val)
- return ret_val;
-
- usec_delay(1);
-
- return ret_val;
-}
-
/**
* igc_phy_hw_reset_generic - PHY hardware reset
* @hw: pointer to the HW structure
*
* Verify the reset block is not blocking us from resetting. Acquire
* semaphore (if necessary) and read/set/write the device control reset
* bit in the PHY. Wait the appropriate delay time for the device to
* reset and release the semaphore (if necessary).
**/
s32 igc_phy_hw_reset_generic(struct igc_hw *hw)
{
struct igc_phy_info *phy = &hw->phy;
s32 ret_val;
u32 ctrl, timeout = 10000, phpm = 0;
DEBUGFUNC("igc_phy_hw_reset_generic");
if (phy->ops.check_reset_block) {
ret_val = phy->ops.check_reset_block(hw);
if (ret_val)
return IGC_SUCCESS;
}
ret_val = phy->ops.acquire(hw);
if (ret_val)
return ret_val;
phpm = IGC_READ_REG(hw, IGC_I225_PHPM);
ctrl = IGC_READ_REG(hw, IGC_CTRL);
IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_PHY_RST);
IGC_WRITE_FLUSH(hw);
usec_delay(phy->reset_delay_us);
IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
IGC_WRITE_FLUSH(hw);
usec_delay(150);
do {
phpm = IGC_READ_REG(hw, IGC_I225_PHPM);
timeout--;
usec_delay(1);
} while (!(phpm & IGC_I225_PHPM_RST_COMPL) && timeout);
if (!timeout)
DEBUGOUT("Timeout expired after a phy reset\n");
phy->ops.release(hw);
return ret_val;
}
/**
* igc_power_up_phy_copper - Restore copper link in case of PHY power down
* @hw: pointer to the HW structure
*
* In the case of a PHY power down to save power, or to turn off link during a
* driver unload, or wake on lan is not enabled, restore the link to previous
* settings.
**/
void igc_power_up_phy_copper(struct igc_hw *hw)
{
u16 mii_reg = 0;
/* The PHY will retain its settings across a power down/up cycle */
hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
mii_reg &= ~MII_CR_POWER_DOWN;
hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
usec_delay(300);
}
/**
* igc_power_down_phy_copper - Restore copper link in case of PHY power down
* @hw: pointer to the HW structure
*
* In the case of a PHY power down to save power, or to turn off link during a
* driver unload, or wake on lan is not enabled, restore the link to previous
* settings.
**/
void igc_power_down_phy_copper(struct igc_hw *hw)
{
u16 mii_reg = 0;
/* The PHY will retain its settings across a power down/up cycle */
hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
mii_reg |= MII_CR_POWER_DOWN;
hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
msec_delay(1);
}
/**
* igc_write_phy_reg_gpy - Write GPY PHY register
* @hw: pointer to the HW structure
* @offset: register offset to write to
* @data: data to write at register offset
*
* Acquires semaphore, if necessary, then writes the data to PHY register
* at the offset. Release any acquired semaphores before exiting.
**/
s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data)
{
s32 ret_val;
u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT;
DEBUGFUNC("igc_write_phy_reg_gpy");
offset = offset & GPY_REG_MASK;
if (!dev_addr) {
ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
return ret_val;
ret_val = igc_write_phy_reg_mdic(hw, offset, data);
if (ret_val)
return ret_val;
hw->phy.ops.release(hw);
} else {
ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr,
data);
}
return ret_val;
}
/**
* igc_read_phy_reg_gpy - Read GPY PHY register
* @hw: pointer to the HW structure
* @offset: lower half is register offset to read to
* upper half is MMD to use.
* @data: data to read at register offset
*
* Acquires semaphore, if necessary, then reads the data in the PHY register
* at the offset. Release any acquired semaphores before exiting.
**/
s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data)
{
s32 ret_val;
u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT;
DEBUGFUNC("igc_read_phy_reg_gpy");
offset = offset & GPY_REG_MASK;
if (!dev_addr) {
ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
return ret_val;
ret_val = igc_read_phy_reg_mdic(hw, offset, data);
if (ret_val)
return ret_val;
hw->phy.ops.release(hw);
} else {
ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr,
data);
}
return ret_val;
}
/**
* __igc_access_xmdio_reg - Read/write XMDIO register
* @hw: pointer to the HW structure
* @address: XMDIO address to program
* @dev_addr: device address to program
* @data: pointer to value to read/write from/to the XMDIO address
* @read: boolean flag to indicate read or write
**/
static s32 __igc_access_xmdio_reg(struct igc_hw *hw, u16 address,
u8 dev_addr, u16 *data, bool read)
{
s32 ret_val;
DEBUGFUNC("__igc_access_xmdio_reg");
ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);
if (ret_val)
return ret_val;
ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);
if (ret_val)
return ret_val;
ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |
dev_addr);
if (ret_val)
return ret_val;
if (read)
ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);
else
ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);
if (ret_val)
return ret_val;
/* Recalibrate the device back to 0 */
ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);
if (ret_val)
return ret_val;
return ret_val;
}
/**
* igc_read_xmdio_reg - Read XMDIO register
* @hw: pointer to the HW structure
* @addr: XMDIO address to program
* @dev_addr: device address to program
* @data: value to be read from the EMI address
**/
s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 *data)
{
DEBUGFUNC("igc_read_xmdio_reg");
return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true);
}
/**
* igc_write_xmdio_reg - Write XMDIO register
* @hw: pointer to the HW structure
* @addr: XMDIO address to program
* @dev_addr: device address to program
* @data: value to be written to the XMDIO address
**/
s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 data)
{
DEBUGFUNC("igc_write_xmdio_reg");
return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false);
}
diff --git a/sys/dev/igc/igc_phy.h b/sys/dev/igc/igc_phy.h
index 61cc46cdc583..36fa0677c3e6 100644
--- a/sys/dev/igc/igc_phy.h
+++ b/sys/dev/igc/igc_phy.h
@@ -1,134 +1,133 @@
/*-
* Copyright 2021 Intel Corp
* Copyright 2021 Rubicon Communications, LLC (Netgate)
* SPDX-License-Identifier: BSD-3-Clause
*
* $FreeBSD$
*/
#ifndef _IGC_PHY_H_
#define _IGC_PHY_H_
void igc_init_phy_ops_generic(struct igc_hw *hw);
s32 igc_null_read_reg(struct igc_hw *hw, u32 offset, u16 *data);
void igc_null_phy_generic(struct igc_hw *hw);
s32 igc_null_lplu_state(struct igc_hw *hw, bool active);
s32 igc_null_write_reg(struct igc_hw *hw, u32 offset, u16 data);
s32 igc_null_set_page(struct igc_hw *hw, u16 data);
s32 igc_check_downshift_generic(struct igc_hw *hw);
s32 igc_check_reset_block_generic(struct igc_hw *hw);
s32 igc_get_phy_id(struct igc_hw *hw);
-s32 igc_phy_sw_reset_generic(struct igc_hw *hw);
void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl);
s32 igc_phy_hw_reset_generic(struct igc_hw *hw);
s32 igc_phy_reset_dsp_generic(struct igc_hw *hw);
s32 igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active);
s32 igc_setup_copper_link_generic(struct igc_hw *hw);
s32 igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations,
u32 usec_interval, bool *success);
enum igc_phy_type igc_get_phy_type_from_id(u32 phy_id);
s32 igc_determine_phy_address(struct igc_hw *hw);
s32 igc_enable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg);
s32 igc_disable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg);
void igc_power_up_phy_copper(struct igc_hw *hw);
void igc_power_down_phy_copper(struct igc_hw *hw);
s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data);
s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data);
s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr,
u16 *data);
s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr,
u16 data);
s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data);
s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data);
#define IGC_MAX_PHY_ADDR 8
/* IGP01IGC Specific Registers */
#define IGP01IGC_PHY_PORT_CONFIG 0x10 /* Port Config */
#define IGP01IGC_PHY_PORT_STATUS 0x11 /* Status */
#define IGP01IGC_PHY_PORT_CTRL 0x12 /* Control */
#define IGP01IGC_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
#define IGP02IGC_PHY_POWER_MGMT 0x19 /* Power Management */
#define IGP01IGC_PHY_PAGE_SELECT 0x1F /* Page Select */
#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
#define IGP_PAGE_SHIFT 5
#define PHY_REG_MASK 0x1F
#define IGC_I225_PHPM 0x0E14 /* I225 PHY Power Management */
#define IGC_I225_PHPM_DIS_1000_D3 0x0008 /* Disable 1G in D3 */
#define IGC_I225_PHPM_LINK_ENERGY 0x0010 /* Link Energy Detect */
#define IGC_I225_PHPM_GO_LINKD 0x0020 /* Go Link Disconnect */
#define IGC_I225_PHPM_DIS_1000 0x0040 /* Disable 1G globally */
#define IGC_I225_PHPM_SPD_B2B_EN 0x0080 /* Smart Power Down Back2Back */
#define IGC_I225_PHPM_RST_COMPL 0x0100 /* PHY Reset Completed */
#define IGC_I225_PHPM_DIS_100_D3 0x0200 /* Disable 100M in D3 */
#define IGC_I225_PHPM_ULP 0x0400 /* Ultra Low-Power Mode */
#define IGC_I225_PHPM_DIS_2500 0x0800 /* Disable 2.5G globally */
#define IGC_I225_PHPM_DIS_2500_D3 0x1000 /* Disable 2.5G in D3 */
/* GPY211 - I225 defines */
#define GPY_MMD_MASK 0xFFFF0000
#define GPY_MMD_SHIFT 16
#define GPY_REG_MASK 0x0000FFFF
#define IGP01IGC_PHY_PCS_INIT_REG 0x00B4
#define IGP01IGC_PHY_POLARITY_MASK 0x0078
#define IGP01IGC_PSCR_AUTO_MDIX 0x1000
#define IGP01IGC_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
#define IGP01IGC_PSCFR_SMART_SPEED 0x0080
#define IGP02IGC_PM_SPD 0x0001 /* Smart Power Down */
#define IGP02IGC_PM_D0_LPLU 0x0002 /* For D0a states */
#define IGP02IGC_PM_D3_LPLU 0x0004 /* For all other states */
#define IGP01IGC_PLHR_SS_DOWNGRADE 0x8000
#define IGP01IGC_PSSR_POLARITY_REVERSED 0x0002
#define IGP01IGC_PSSR_MDIX 0x0800
#define IGP01IGC_PSSR_SPEED_MASK 0xC000
#define IGP01IGC_PSSR_SPEED_1000MBPS 0xC000
#define IGP02IGC_PHY_CHANNEL_NUM 4
#define IGP02IGC_PHY_AGC_A 0x11B1
#define IGP02IGC_PHY_AGC_B 0x12B1
#define IGP02IGC_PHY_AGC_C 0x14B1
#define IGP02IGC_PHY_AGC_D 0x18B1
#define IGP02IGC_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */
#define IGP02IGC_AGC_LENGTH_MASK 0x7F
#define IGP02IGC_AGC_RANGE 15
#define IGC_CABLE_LENGTH_UNDEFINED 0xFF
#define IGC_KMRNCTRLSTA_OFFSET 0x001F0000
#define IGC_KMRNCTRLSTA_OFFSET_SHIFT 16
#define IGC_KMRNCTRLSTA_REN 0x00200000
#define IGC_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
#define IGC_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
#define IGC_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
#define IGC_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
#define IGC_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */
#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */
#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
/* IFE PHY Extended Status Control */
#define IFE_PESC_POLARITY_REVERSED 0x0100
/* IFE PHY Special Control */
#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
#define IFE_PSC_FORCE_POLARITY 0x0020
/* IFE PHY Special Control and LED Control */
#define IFE_PSCL_PROBE_MODE 0x0020
#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
/* IFE PHY MDIX Control */
#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */
#endif