diff --git a/sys/dev/ice/ice_bitops.h b/sys/dev/ice/ice_bitops.h index c480900596f4..a623f810c101 100644 --- a/sys/dev/ice/ice_bitops.h +++ b/sys/dev/ice/ice_bitops.h @@ -1,539 +1,539 @@ /* SPDX-License-Identifier: BSD-3-Clause */ /* Copyright (c) 2024, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * 3. Neither the name of the Intel Corporation nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _ICE_BITOPS_H_ #define _ICE_BITOPS_H_ #include "ice_defs.h" #include "ice_osdep.h" /* Define the size of the bitmap chunk */ typedef u32 ice_bitmap_t; /* NOTE! * Do not use any of the functions declared in this file * on memory that was not declared with ice_declare_bitmap. * Not following this rule might cause issues like split * locks. */ /* Number of bits per bitmap chunk */ #define BITS_PER_CHUNK (BITS_PER_BYTE * sizeof(ice_bitmap_t)) /* Determine which chunk a bit belongs in */ #define BIT_CHUNK(nr) ((nr) / BITS_PER_CHUNK) /* How many chunks are required to store this many bits */ #define BITS_TO_CHUNKS(sz) (((sz) + BITS_PER_CHUNK - 1) / BITS_PER_CHUNK) /* Which bit inside a chunk this bit corresponds to */ #define BIT_IN_CHUNK(nr) ((nr) % BITS_PER_CHUNK) /* How many bits are valid in the last chunk, assumes nr > 0 */ #define LAST_CHUNK_BITS(nr) ((((nr) - 1) % BITS_PER_CHUNK) + 1) /* Generate a bitmask of valid bits in the last chunk, assumes nr > 0 */ #define LAST_CHUNK_MASK(nr) (((ice_bitmap_t)~0) >> \ (BITS_PER_CHUNK - LAST_CHUNK_BITS(nr))) #define ice_declare_bitmap(A, sz) \ ice_bitmap_t A[BITS_TO_CHUNKS(sz)] static inline bool ice_is_bit_set_internal(u16 nr, const ice_bitmap_t *bitmap) { return !!(*bitmap & BIT(nr)); } /* * If atomic version of the bitops are required, each specific OS * implementation will need to implement OS/platform specific atomic * version of the functions below: * * ice_clear_bit_internal * ice_set_bit_internal * ice_test_and_clear_bit_internal * ice_test_and_set_bit_internal * * and define macro ICE_ATOMIC_BITOPS to overwrite the default non-atomic * implementation. */ static inline void ice_clear_bit_internal(u16 nr, ice_bitmap_t *bitmap) { *bitmap &= ~BIT(nr); } static inline void ice_set_bit_internal(u16 nr, ice_bitmap_t *bitmap) { *bitmap |= BIT(nr); } static inline bool ice_test_and_clear_bit_internal(u16 nr, ice_bitmap_t *bitmap) { if (ice_is_bit_set_internal(nr, bitmap)) { ice_clear_bit_internal(nr, bitmap); return true; } return false; } static inline bool ice_test_and_set_bit_internal(u16 nr, ice_bitmap_t *bitmap) { if (ice_is_bit_set_internal(nr, bitmap)) return true; ice_set_bit_internal(nr, bitmap); return false; } /** * ice_is_bit_set - Check state of a bit in a bitmap * @bitmap: the bitmap to check * @nr: the bit to check * * Returns true if bit nr of bitmap is set. False otherwise. Assumes that nr * is less than the size of the bitmap. */ static inline bool ice_is_bit_set(const ice_bitmap_t *bitmap, u16 nr) { return ice_is_bit_set_internal(BIT_IN_CHUNK(nr), &bitmap[BIT_CHUNK(nr)]); } /** * ice_clear_bit - Clear a bit in a bitmap * @bitmap: the bitmap to change * @nr: the bit to change * * Clears the bit nr in bitmap. Assumes that nr is less than the size of the * bitmap. */ static inline void ice_clear_bit(u16 nr, ice_bitmap_t *bitmap) { ice_clear_bit_internal(BIT_IN_CHUNK(nr), &bitmap[BIT_CHUNK(nr)]); } /** * ice_set_bit - Set a bit in a bitmap * @bitmap: the bitmap to change * @nr: the bit to change * * Sets the bit nr in bitmap. Assumes that nr is less than the size of the * bitmap. */ static inline void ice_set_bit(u16 nr, ice_bitmap_t *bitmap) { ice_set_bit_internal(BIT_IN_CHUNK(nr), &bitmap[BIT_CHUNK(nr)]); } /** * ice_test_and_clear_bit - Atomically clear a bit and return the old bit value * @nr: the bit to change * @bitmap: the bitmap to change * * Check and clear the bit nr in bitmap. Assumes that nr is less than the size * of the bitmap. */ static inline bool ice_test_and_clear_bit(u16 nr, ice_bitmap_t *bitmap) { return ice_test_and_clear_bit_internal(BIT_IN_CHUNK(nr), &bitmap[BIT_CHUNK(nr)]); } /** * ice_test_and_set_bit - Atomically set a bit and return the old bit value * @nr: the bit to change * @bitmap: the bitmap to change * * Check and set the bit nr in bitmap. Assumes that nr is less than the size of * the bitmap. */ static inline bool ice_test_and_set_bit(u16 nr, ice_bitmap_t *bitmap) { return ice_test_and_set_bit_internal(BIT_IN_CHUNK(nr), &bitmap[BIT_CHUNK(nr)]); } /* ice_zero_bitmap - set bits of bitmap to zero. * @bmp: bitmap to set zeros * @size: Size of the bitmaps in bits * * Set all of the bits in a bitmap to zero. Note that this function assumes it * operates on an ice_bitmap_t which was declared using ice_declare_bitmap. It * will zero every bit in the last chunk, even if those bits are beyond the * size. */ static inline void ice_zero_bitmap(ice_bitmap_t *bmp, u16 size) { ice_memset(bmp, 0, BITS_TO_CHUNKS(size) * sizeof(ice_bitmap_t), ICE_NONDMA_MEM); } /** * ice_and_bitmap - bitwise AND 2 bitmaps and store result in dst bitmap * @dst: Destination bitmap that receive the result of the operation * @bmp1: The first bitmap to intersect - * @bmp2: The second bitmap to intersect wit the first + * @bmp2: The second bitmap to intersect with the first * @size: Size of the bitmaps in bits * * This function performs a bitwise AND on two "source" bitmaps of the same size * and stores the result to "dst" bitmap. The "dst" bitmap must be of the same * size as the "source" bitmaps to avoid buffer overflows. This function returns * a non-zero value if at least one bit location from both "source" bitmaps is * non-zero. */ static inline int ice_and_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1, const ice_bitmap_t *bmp2, u16 size) { ice_bitmap_t res = 0, mask; u16 i; /* Handle all but the last chunk */ for (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++) { dst[i] = bmp1[i] & bmp2[i]; res |= dst[i]; } /* We want to take care not to modify any bits outside of the bitmap * size, even in the destination bitmap. Thus, we won't directly * assign the last bitmap, but instead use a bitmask to ensure we only * modify bits which are within the size, and leave any bits above the * size value alone. */ mask = LAST_CHUNK_MASK(size); dst[i] = (dst[i] & ~mask) | ((bmp1[i] & bmp2[i]) & mask); res |= dst[i] & mask; return res != 0; } /** * ice_or_bitmap - bitwise OR 2 bitmaps and store result in dst bitmap * @dst: Destination bitmap that receive the result of the operation * @bmp1: The first bitmap to intersect - * @bmp2: The second bitmap to intersect wit the first + * @bmp2: The second bitmap to intersect with the first * @size: Size of the bitmaps in bits * * This function performs a bitwise OR on two "source" bitmaps of the same size * and stores the result to "dst" bitmap. The "dst" bitmap must be of the same * size as the "source" bitmaps to avoid buffer overflows. */ static inline void ice_or_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1, const ice_bitmap_t *bmp2, u16 size) { ice_bitmap_t mask; u16 i; /* Handle all but last chunk */ for (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++) dst[i] = bmp1[i] | bmp2[i]; /* We want to only OR bits within the size. Furthermore, we also do * not want to modify destination bits which are beyond the specified * size. Use a bitmask to ensure that we only modify the bits that are * within the specified size. */ mask = LAST_CHUNK_MASK(size); dst[i] = (dst[i] & ~mask) | ((bmp1[i] | bmp2[i]) & mask); } /** * ice_xor_bitmap - bitwise XOR 2 bitmaps and store result in dst bitmap * @dst: Destination bitmap that receive the result of the operation * @bmp1: The first bitmap of XOR operation * @bmp2: The second bitmap to XOR with the first * @size: Size of the bitmaps in bits * * This function performs a bitwise XOR on two "source" bitmaps of the same size * and stores the result to "dst" bitmap. The "dst" bitmap must be of the same * size as the "source" bitmaps to avoid buffer overflows. */ static inline void ice_xor_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1, const ice_bitmap_t *bmp2, u16 size) { ice_bitmap_t mask; u16 i; /* Handle all but last chunk */ for (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++) dst[i] = bmp1[i] ^ bmp2[i]; /* We want to only XOR bits within the size. Furthermore, we also do * not want to modify destination bits which are beyond the specified * size. Use a bitmask to ensure that we only modify the bits that are * within the specified size. */ mask = LAST_CHUNK_MASK(size); dst[i] = (dst[i] & ~mask) | ((bmp1[i] ^ bmp2[i]) & mask); } /** * ice_andnot_bitmap - bitwise ANDNOT 2 bitmaps and result in dst bitmap * @dst: Destination bitmap that receive the result of the operation * @bmp1: The first bitmap of ANDNOT operation * @bmp2: The second bitmap to ANDNOT operation * @size: Size of the bitmaps in bits * * This function performs a bitwise ANDNOT on two "source" bitmaps of the same * size, and stores the result to "dst" bitmap. The "dst" bitmap must be of the * same size as the "source" bitmaps to avoid buffer overflows. */ static inline void ice_andnot_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1, const ice_bitmap_t *bmp2, u16 size) { ice_bitmap_t mask; u16 i; /* Handle all but last chunk */ for (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++) dst[i] = bmp1[i] & ~bmp2[i]; /* We want to only clear bits within the size. Furthermore, we also do * not want to modify destination bits which are beyond the specified * size. Use a bitmask to ensure that we only modify the bits that are * within the specified size. */ mask = LAST_CHUNK_MASK(size); dst[i] = (dst[i] & ~mask) | ((bmp1[i] & ~bmp2[i]) & mask); } /** * ice_find_next_bit - Find the index of the next set bit of a bitmap * @bitmap: the bitmap to scan * @size: the size in bits of the bitmap * @offset: the offset to start at * * Scans the bitmap and returns the index of the first set bit which is equal * to or after the specified offset. Will return size if no bits are set. */ static inline u16 ice_find_next_bit(const ice_bitmap_t *bitmap, u16 size, u16 offset) { u16 i, j; if (offset >= size) return size; /* Since the starting position may not be directly on a chunk * boundary, we need to be careful to handle the first chunk specially */ i = BIT_CHUNK(offset); if (bitmap[i] != 0) { u16 off = i * BITS_PER_CHUNK; for (j = offset % BITS_PER_CHUNK; j < BITS_PER_CHUNK; j++) { if (ice_is_bit_set(bitmap, off + j)) return min(size, (u16)(off + j)); } } /* Now we handle the remaining chunks, if any */ for (i++; i < BITS_TO_CHUNKS(size); i++) { if (bitmap[i] != 0) { u16 off = i * BITS_PER_CHUNK; for (j = 0; j < BITS_PER_CHUNK; j++) { if (ice_is_bit_set(bitmap, off + j)) return min(size, (u16)(off + j)); } } } return size; } /** * ice_find_first_bit - Find the index of the first set bit of a bitmap * @bitmap: the bitmap to scan * @size: the size in bits of the bitmap * * Scans the bitmap and returns the index of the first set bit. Will return * size if no bits are set. */ static inline u16 ice_find_first_bit(const ice_bitmap_t *bitmap, u16 size) { return ice_find_next_bit(bitmap, size, 0); } #define ice_for_each_set_bit(_bitpos, _addr, _maxlen) \ for ((_bitpos) = ice_find_first_bit((_addr), (_maxlen)); \ (_bitpos) < (_maxlen); \ (_bitpos) = ice_find_next_bit((_addr), (_maxlen), (_bitpos) + 1)) /** * ice_is_any_bit_set - Return true of any bit in the bitmap is set * @bitmap: the bitmap to check * @size: the size of the bitmap * * Equivalent to checking if ice_find_first_bit returns a value less than the * bitmap size. */ static inline bool ice_is_any_bit_set(ice_bitmap_t *bitmap, u16 size) { return ice_find_first_bit(bitmap, size) < size; } /** * ice_cp_bitmap - copy bitmaps * @dst: bitmap destination * @src: bitmap to copy from * @size: Size of the bitmaps in bits * * This function copy bitmap from src to dst. Note that this function assumes * it is operating on a bitmap declared using ice_declare_bitmap. It will copy * the entire last chunk even if this contains bits beyond the size. */ static inline void ice_cp_bitmap(ice_bitmap_t *dst, ice_bitmap_t *src, u16 size) { ice_memcpy(dst, src, BITS_TO_CHUNKS(size) * sizeof(ice_bitmap_t), ICE_NONDMA_TO_NONDMA); } /** * ice_bitmap_set - set a number of bits in bitmap from a starting position * @dst: bitmap destination * @pos: first bit position to set * @num_bits: number of bits to set * * This function sets bits in a bitmap from pos to (pos + num_bits) - 1. * Note that this function assumes it is operating on a bitmap declared using * ice_declare_bitmap. */ static inline void ice_bitmap_set(ice_bitmap_t *dst, u16 pos, u16 num_bits) { u16 i; for (i = pos; i < pos + num_bits; i++) ice_set_bit(i, dst); } /** * ice_bitmap_hweight - hamming weight of bitmap * @bm: bitmap pointer * @size: size of bitmap (in bits) * * This function determines the number of set bits in a bitmap. * Note that this function assumes it is operating on a bitmap declared using * ice_declare_bitmap. */ static inline u16 ice_bitmap_hweight(ice_bitmap_t *bm, u16 size) { u16 count = 0; u16 bit = 0; while (size > (bit = ice_find_next_bit(bm, size, bit))) { count++; bit++; } return count; } /** * ice_cmp_bitmap - compares two bitmaps * @bmp1: the bitmap to compare * @bmp2: the bitmap to compare with bmp1 * @size: Size of the bitmaps in bits * * This function compares two bitmaps, and returns result as true or false. */ static inline bool ice_cmp_bitmap(ice_bitmap_t *bmp1, ice_bitmap_t *bmp2, u16 size) { ice_bitmap_t mask; u16 i; /* Handle all but last chunk */ for (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++) if (bmp1[i] != bmp2[i]) return false; /* We want to only compare bits within the size */ mask = LAST_CHUNK_MASK(size); if ((bmp1[i] & mask) != (bmp2[i] & mask)) return false; return true; } /** * ice_bitmap_from_array32 - copies u32 array source into bitmap destination * @dst: the destination bitmap * @src: the source u32 array * @size: size of the bitmap (in bits) * * This function copies the src bitmap stored in an u32 array into the dst * bitmap stored as an ice_bitmap_t. */ static inline void ice_bitmap_from_array32(ice_bitmap_t *dst, u32 *src, u16 size) { u32 remaining_bits, i; #define BITS_PER_U32 (sizeof(u32) * BITS_PER_BYTE) /* clear bitmap so we only have to set when iterating */ ice_zero_bitmap(dst, size); for (i = 0; i < (u32)(size / BITS_PER_U32); i++) { u32 bit_offset = i * BITS_PER_U32; u32 entry = src[i]; u32 j; for (j = 0; j < BITS_PER_U32; j++) { if (entry & BIT(j)) ice_set_bit((u16)(j + bit_offset), dst); } } /* still need to check the leftover bits (i.e. if size isn't evenly * divisible by BITS_PER_U32 **/ remaining_bits = size % BITS_PER_U32; if (remaining_bits) { u32 bit_offset = i * BITS_PER_U32; u32 entry = src[i]; u32 j; for (j = 0; j < remaining_bits; j++) { if (entry & BIT(j)) ice_set_bit((u16)(j + bit_offset), dst); } } } #undef BIT_CHUNK #undef BIT_IN_CHUNK #undef LAST_CHUNK_BITS #undef LAST_CHUNK_MASK #endif /* _ICE_BITOPS_H_ */ diff --git a/sys/dev/ice/ice_lan_tx_rx.h b/sys/dev/ice/ice_lan_tx_rx.h index 693e0ca5efc6..eedacdab0216 100644 --- a/sys/dev/ice/ice_lan_tx_rx.h +++ b/sys/dev/ice/ice_lan_tx_rx.h @@ -1,2378 +1,2378 @@ /* SPDX-License-Identifier: BSD-3-Clause */ /* Copyright (c) 2024, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * 3. Neither the name of the Intel Corporation nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _ICE_LAN_TX_RX_H_ #define _ICE_LAN_TX_RX_H_ #include "ice_osdep.h" /* Rx Descriptors */ union ice_16byte_rx_desc { struct { __le64 pkt_addr; /* Packet buffer address */ __le64 hdr_addr; /* Header buffer address */ } read; struct { struct { struct { __le16 mirroring_status; __le16 l2tag1; } lo_dword; union { __le32 rss; /* RSS Hash */ __le32 fd_id; /* Flow Director filter ID */ } hi_dword; } qword0; struct { /* ext status/error/PTYPE/length */ __le64 status_error_len; } qword1; } wb; /* writeback */ }; union ice_32byte_rx_desc { struct { __le64 pkt_addr; /* Packet buffer address */ __le64 hdr_addr; /* Header buffer address */ /* bit 0 of hdr_addr is DD bit */ __le64 rsvd1; __le64 rsvd2; } read; struct { struct { struct { __le16 mirroring_status; __le16 l2tag1; } lo_dword; union { __le32 rss; /* RSS Hash */ __le32 fd_id; /* Flow Director filter ID */ } hi_dword; } qword0; struct { /* status/error/PTYPE/length */ __le64 status_error_len; } qword1; struct { __le16 ext_status; /* extended status */ __le16 rsvd; __le16 l2tag2_1; __le16 l2tag2_2; } qword2; struct { __le32 reserved; __le32 fd_id; } qword3; } wb; /* writeback */ }; struct ice_fltr_desc { __le64 qidx_compq_space_stat; __le64 dtype_cmd_vsi_fdid; }; #define ICE_FXD_FLTR_QW0_QINDEX_S 0 #define ICE_FXD_FLTR_QW0_QINDEX_M (0x7FFULL << ICE_FXD_FLTR_QW0_QINDEX_S) #define ICE_FXD_FLTR_QW0_COMP_Q_S 11 #define ICE_FXD_FLTR_QW0_COMP_Q_M BIT_ULL(ICE_FXD_FLTR_QW0_COMP_Q_S) #define ICE_FXD_FLTR_QW0_COMP_Q_ZERO 0x0ULL #define ICE_FXD_FLTR_QW0_COMP_Q_QINDX 0x1ULL #define ICE_FXD_FLTR_QW0_COMP_REPORT_S 12 #define ICE_FXD_FLTR_QW0_COMP_REPORT_M \ (0x3ULL << ICE_FXD_FLTR_QW0_COMP_REPORT_S) #define ICE_FXD_FLTR_QW0_COMP_REPORT_NONE 0x0ULL #define ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL 0x1ULL #define ICE_FXD_FLTR_QW0_COMP_REPORT_SW 0x2ULL #define ICE_FXD_FLTR_QW0_FD_SPACE_S 14 #define ICE_FXD_FLTR_QW0_FD_SPACE_M (0x3ULL << ICE_FXD_FLTR_QW0_FD_SPACE_S) #define ICE_FXD_FLTR_QW0_FD_SPACE_GUAR 0x0ULL #define ICE_FXD_FLTR_QW0_FD_SPACE_BEST_EFFORT 0x1ULL #define ICE_FXD_FLTR_QW0_FD_SPACE_GUAR_BEST 0x2ULL #define ICE_FXD_FLTR_QW0_FD_SPACE_BEST_GUAR 0x3ULL #define ICE_FXD_FLTR_QW0_STAT_CNT_S 16 #define ICE_FXD_FLTR_QW0_STAT_CNT_M \ (0x1FFFULL << ICE_FXD_FLTR_QW0_STAT_CNT_S) #define ICE_FXD_FLTR_QW0_STAT_ENA_S 29 #define ICE_FXD_FLTR_QW0_STAT_ENA_M (0x3ULL << ICE_FXD_FLTR_QW0_STAT_ENA_S) #define ICE_FXD_FLTR_QW0_STAT_ENA_NONE 0x0ULL #define ICE_FXD_FLTR_QW0_STAT_ENA_PKTS 0x1ULL #define ICE_FXD_FLTR_QW0_STAT_ENA_BYTES 0x2ULL #define ICE_FXD_FLTR_QW0_STAT_ENA_PKTS_BYTES 0x3ULL #define ICE_FXD_FLTR_QW0_EVICT_ENA_S 31 #define ICE_FXD_FLTR_QW0_EVICT_ENA_M BIT_ULL(ICE_FXD_FLTR_QW0_EVICT_ENA_S) #define ICE_FXD_FLTR_QW0_EVICT_ENA_FALSE 0x0ULL #define ICE_FXD_FLTR_QW0_EVICT_ENA_TRUE 0x1ULL #define ICE_FXD_FLTR_QW0_TO_Q_S 32 #define ICE_FXD_FLTR_QW0_TO_Q_M (0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_S) #define ICE_FXD_FLTR_QW0_TO_Q_EQUALS_QINDEX 0x0ULL #define ICE_FXD_FLTR_QW0_TO_Q_PRI_S 35 #define ICE_FXD_FLTR_QW0_TO_Q_PRI_M (0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_PRI_S) #define ICE_FXD_FLTR_QW0_TO_Q_PRIO1 0x1ULL #define ICE_FXD_FLTR_QW0_DPU_RECIPE_S 38 #define ICE_FXD_FLTR_QW0_DPU_RECIPE_M \ (0x3ULL << ICE_FXD_FLTR_QW0_DPU_RECIPE_S) #define ICE_FXD_FLTR_QW0_DPU_RECIPE_DFLT 0x0ULL #define ICE_FXD_FLTR_QW0_DROP_S 40 #define ICE_FXD_FLTR_QW0_DROP_M BIT_ULL(ICE_FXD_FLTR_QW0_DROP_S) #define ICE_FXD_FLTR_QW0_DROP_NO 0x0ULL #define ICE_FXD_FLTR_QW0_DROP_YES 0x1ULL #define ICE_FXD_FLTR_QW0_FLEX_PRI_S 41 #define ICE_FXD_FLTR_QW0_FLEX_PRI_M (0x7ULL << ICE_FXD_FLTR_QW0_FLEX_PRI_S) #define ICE_FXD_FLTR_QW0_FLEX_PRI_NONE 0x0ULL #define ICE_FXD_FLTR_QW0_FLEX_MDID_S 44 #define ICE_FXD_FLTR_QW0_FLEX_MDID_M (0xFULL << ICE_FXD_FLTR_QW0_FLEX_MDID_S) #define ICE_FXD_FLTR_QW0_FLEX_MDID0 0x0ULL #define ICE_FXD_FLTR_QW0_FLEX_VAL_S 48 #define ICE_FXD_FLTR_QW0_FLEX_VAL_M \ (0xFFFFULL << ICE_FXD_FLTR_QW0_FLEX_VAL_S) #define ICE_FXD_FLTR_QW0_FLEX_VAL0 0x0ULL #define ICE_FXD_FLTR_QW1_DTYPE_S 0 #define ICE_FXD_FLTR_QW1_DTYPE_M (0xFULL << ICE_FXD_FLTR_QW1_DTYPE_S) #define ICE_FXD_FLTR_QW1_PCMD_S 4 #define ICE_FXD_FLTR_QW1_PCMD_M BIT_ULL(ICE_FXD_FLTR_QW1_PCMD_S) #define ICE_FXD_FLTR_QW1_PCMD_ADD 0x0ULL #define ICE_FXD_FLTR_QW1_PCMD_REMOVE 0x1ULL #define ICE_FXD_FLTR_QW1_PROF_PRI_S 5 #define ICE_FXD_FLTR_QW1_PROF_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_PROF_PRI_S) #define ICE_FXD_FLTR_QW1_PROF_PRIO_ZERO 0x0ULL #define ICE_FXD_FLTR_QW1_PROF_S 8 #define ICE_FXD_FLTR_QW1_PROF_M (0x3FULL << ICE_FXD_FLTR_QW1_PROF_S) #define ICE_FXD_FLTR_QW1_PROF_ZERO 0x0ULL #define ICE_FXD_FLTR_QW1_FD_VSI_S 14 #define ICE_FXD_FLTR_QW1_FD_VSI_M (0x3FFULL << ICE_FXD_FLTR_QW1_FD_VSI_S) #define ICE_FXD_FLTR_QW1_SWAP_S 24 #define ICE_FXD_FLTR_QW1_SWAP_M BIT_ULL(ICE_FXD_FLTR_QW1_SWAP_S) #define ICE_FXD_FLTR_QW1_SWAP_NOT_SET 0x0ULL #define ICE_FXD_FLTR_QW1_SWAP_SET 0x1ULL #define ICE_FXD_FLTR_QW1_FDID_PRI_S 25 #define ICE_FXD_FLTR_QW1_FDID_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S) #define ICE_FXD_FLTR_QW1_FDID_PRI_ONE 0x1ULL #define ICE_FXD_FLTR_QW1_FDID_PRI_THREE 0x3ULL #define ICE_FXD_FLTR_QW1_FDID_MDID_S 28 #define ICE_FXD_FLTR_QW1_FDID_MDID_M (0xFULL << ICE_FXD_FLTR_QW1_FDID_MDID_S) #define ICE_FXD_FLTR_QW1_FDID_MDID_FD 0x05ULL #define ICE_FXD_FLTR_QW1_FDID_S 32 #define ICE_FXD_FLTR_QW1_FDID_M \ (0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S) #define ICE_FXD_FLTR_QW1_FDID_ZERO 0x0ULL enum ice_rx_desc_status_bits { /* Note: These are predefined bit offsets */ ICE_RX_DESC_STATUS_DD_S = 0, ICE_RX_DESC_STATUS_EOF_S = 1, ICE_RX_DESC_STATUS_L2TAG1P_S = 2, ICE_RX_DESC_STATUS_L3L4P_S = 3, ICE_RX_DESC_STATUS_CRCP_S = 4, ICE_RX_DESC_STATUS_TSYNINDX_S = 5, ICE_RX_DESC_STATUS_TSYNVALID_S = 7, ICE_RX_DESC_STATUS_EXT_UDP_0_S = 8, ICE_RX_DESC_STATUS_UMBCAST_S = 9, ICE_RX_DESC_STATUS_FLM_S = 11, ICE_RX_DESC_STATUS_FLTSTAT_S = 12, ICE_RX_DESC_STATUS_LPBK_S = 14, ICE_RX_DESC_STATUS_IPV6EXADD_S = 15, ICE_RX_DESC_STATUS_RESERVED2_S = 16, ICE_RX_DESC_STATUS_INT_UDP_0_S = 18, ICE_RX_DESC_STATUS_LAST /* this entry must be last!!! */ }; #define ICE_RXD_QW1_STATUS_S 0 #define ICE_RXD_QW1_STATUS_M ((BIT(ICE_RX_DESC_STATUS_LAST) - 1) << \ ICE_RXD_QW1_STATUS_S) #define ICE_RXD_QW1_STATUS_TSYNINDX_S ICE_RX_DESC_STATUS_TSYNINDX_S #define ICE_RXD_QW1_STATUS_TSYNINDX_M (0x3UL << ICE_RXD_QW1_STATUS_TSYNINDX_S) #define ICE_RXD_QW1_STATUS_TSYNVALID_S ICE_RX_DESC_STATUS_TSYNVALID_S #define ICE_RXD_QW1_STATUS_TSYNVALID_M BIT_ULL(ICE_RXD_QW1_STATUS_TSYNVALID_S) enum ice_rx_desc_fltstat_values { ICE_RX_DESC_FLTSTAT_NO_DATA = 0, ICE_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ ICE_RX_DESC_FLTSTAT_RSV = 2, ICE_RX_DESC_FLTSTAT_RSS_HASH = 3, }; #define ICE_RXD_QW1_ERROR_S 19 #define ICE_RXD_QW1_ERROR_M (0xFFUL << ICE_RXD_QW1_ERROR_S) enum ice_rx_desc_error_bits { /* Note: These are predefined bit offsets */ ICE_RX_DESC_ERROR_RXE_S = 0, ICE_RX_DESC_ERROR_RECIPE_S = 1, ICE_RX_DESC_ERROR_HBO_S = 2, ICE_RX_DESC_ERROR_L3L4E_S = 3, /* 3 BITS */ ICE_RX_DESC_ERROR_IPE_S = 3, ICE_RX_DESC_ERROR_L4E_S = 4, ICE_RX_DESC_ERROR_EIPE_S = 5, ICE_RX_DESC_ERROR_OVERSIZE_S = 6, ICE_RX_DESC_ERROR_PPRS_S = 7 }; enum ice_rx_desc_error_l3l4e_masks { ICE_RX_DESC_ERROR_L3L4E_NONE = 0, ICE_RX_DESC_ERROR_L3L4E_PROT = 1, }; #define ICE_RXD_QW1_PTYPE_S 30 #define ICE_RXD_QW1_PTYPE_M (0xFFULL << ICE_RXD_QW1_PTYPE_S) /* Packet type non-ip values */ enum ice_rx_l2_ptype { ICE_RX_PTYPE_L2_RESERVED = 0, ICE_RX_PTYPE_L2_MAC_PAY2 = 1, ICE_RX_PTYPE_L2_FIP_PAY2 = 3, ICE_RX_PTYPE_L2_OUI_PAY2 = 4, ICE_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, ICE_RX_PTYPE_L2_LLDP_PAY2 = 6, ICE_RX_PTYPE_L2_ECP_PAY2 = 7, ICE_RX_PTYPE_L2_EVB_PAY2 = 8, ICE_RX_PTYPE_L2_QCN_PAY2 = 9, ICE_RX_PTYPE_L2_EAPOL_PAY2 = 10, ICE_RX_PTYPE_L2_ARP = 11, }; struct ice_rx_ptype_decoded { u32 known:1; u32 outer_ip:1; u32 outer_ip_ver:2; u32 outer_frag:1; u32 tunnel_type:3; u32 tunnel_end_prot:2; u32 tunnel_end_frag:1; u32 inner_prot:4; u32 payload_layer:3; }; enum ice_rx_ptype_outer_ip { ICE_RX_PTYPE_OUTER_L2 = 0, ICE_RX_PTYPE_OUTER_IP = 1, }; enum ice_rx_ptype_outer_ip_ver { ICE_RX_PTYPE_OUTER_NONE = 0, ICE_RX_PTYPE_OUTER_IPV4 = 1, ICE_RX_PTYPE_OUTER_IPV6 = 2, }; enum ice_rx_ptype_outer_fragmented { ICE_RX_PTYPE_NOT_FRAG = 0, ICE_RX_PTYPE_FRAG = 1, }; enum ice_rx_ptype_tunnel_type { ICE_RX_PTYPE_TUNNEL_NONE = 0, ICE_RX_PTYPE_TUNNEL_IP_IP = 1, ICE_RX_PTYPE_TUNNEL_IP_GRENAT = 2, ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, }; enum ice_rx_ptype_tunnel_end_prot { ICE_RX_PTYPE_TUNNEL_END_NONE = 0, ICE_RX_PTYPE_TUNNEL_END_IPV4 = 1, ICE_RX_PTYPE_TUNNEL_END_IPV6 = 2, }; enum ice_rx_ptype_inner_prot { ICE_RX_PTYPE_INNER_PROT_NONE = 0, ICE_RX_PTYPE_INNER_PROT_UDP = 1, ICE_RX_PTYPE_INNER_PROT_TCP = 2, ICE_RX_PTYPE_INNER_PROT_SCTP = 3, ICE_RX_PTYPE_INNER_PROT_ICMP = 4, }; enum ice_rx_ptype_payload_layer { ICE_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, ICE_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, ICE_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, }; #define ICE_RXD_QW1_LEN_PBUF_S 38 #define ICE_RXD_QW1_LEN_PBUF_M (0x3FFFULL << ICE_RXD_QW1_LEN_PBUF_S) #define ICE_RXD_QW1_LEN_HBUF_S 52 #define ICE_RXD_QW1_LEN_HBUF_M (0x7FFULL << ICE_RXD_QW1_LEN_HBUF_S) #define ICE_RXD_QW1_LEN_SPH_S 63 #define ICE_RXD_QW1_LEN_SPH_M BIT_ULL(ICE_RXD_QW1_LEN_SPH_S) enum ice_rx_desc_ext_status_bits { /* Note: These are predefined bit offsets */ ICE_RX_DESC_EXT_STATUS_L2TAG2P_S = 0, ICE_RX_DESC_EXT_STATUS_L2TAG3P_S = 1, ICE_RX_DESC_EXT_STATUS_FLEXBL_S = 2, ICE_RX_DESC_EXT_STATUS_FLEXBH_S = 4, ICE_RX_DESC_EXT_STATUS_FDLONGB_S = 9, ICE_RX_DESC_EXT_STATUS_PELONGB_S = 11, }; enum ice_rx_desc_pe_status_bits { /* Note: These are predefined bit offsets */ ICE_RX_DESC_PE_STATUS_QPID_S = 0, /* 18 BITS */ ICE_RX_DESC_PE_STATUS_L4PORT_S = 0, /* 16 BITS */ ICE_RX_DESC_PE_STATUS_IPINDEX_S = 16, /* 8 BITS */ ICE_RX_DESC_PE_STATUS_QPIDHIT_S = 24, ICE_RX_DESC_PE_STATUS_APBVTHIT_S = 25, ICE_RX_DESC_PE_STATUS_PORTV_S = 26, ICE_RX_DESC_PE_STATUS_URG_S = 27, ICE_RX_DESC_PE_STATUS_IPFRAG_S = 28, ICE_RX_DESC_PE_STATUS_IPOPT_S = 29 }; #define ICE_RX_PROG_STATUS_DESC_LEN_S 38 #define ICE_RX_PROG_STATUS_DESC_LEN 0x2000000 #define ICE_RX_PROG_STATUS_DESC_QW1_PROGID_S 2 #define ICE_RX_PROG_STATUS_DESC_QW1_PROGID_M \ (0x7UL << ICE_RX_PROG_STATUS_DESC_QW1_PROGID_S) #define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S 19 #define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_M \ (0x3FUL << ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S) enum ice_rx_prog_status_desc_status_bits { /* Note: These are predefined bit offsets */ ICE_RX_PROG_STATUS_DESC_DD_S = 0, ICE_RX_PROG_STATUS_DESC_PROG_ID_S = 2 /* 3 BITS */ }; enum ice_rx_prog_status_desc_prog_id_masks { ICE_RX_PROG_STATUS_DESC_FD_FLTR_STATUS = 1, }; enum ice_rx_prog_status_desc_error_bits { /* Note: These are predefined bit offsets */ ICE_RX_PROG_STATUS_DESC_FD_TBL_FULL_S = 0, ICE_RX_PROG_STATUS_DESC_NO_FD_ENTRY_S = 1, }; /* Rx Flex Descriptors * These descriptors are used instead of the legacy version descriptors when * ice_rlan_ctx.adv_desc is set */ union ice_32b_rx_flex_desc { struct { __le64 pkt_addr; /* Packet buffer address */ __le64 hdr_addr; /* Header buffer address */ /* bit 0 of hdr_addr is DD bit */ __le64 rsvd1; __le64 rsvd2; } read; struct { /* Qword 0 */ u8 rxdid; /* descriptor builder profile ID */ u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */ __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */ __le16 pkt_len; /* [15:14] are reserved */ __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */ /* sph=[11:11] */ /* ff1/ext=[15:12] */ /* Qword 1 */ __le16 status_error0; __le16 l2tag1; __le16 flex_meta0; __le16 flex_meta1; /* Qword 2 */ __le16 status_error1; u8 flex_flags2; u8 time_stamp_low; __le16 l2tag2_1st; __le16 l2tag2_2nd; /* Qword 3 */ __le16 flex_meta2; __le16 flex_meta3; union { struct { __le16 flex_meta4; __le16 flex_meta5; } flex; __le32 ts_high; } flex_ts; } wb; /* writeback */ }; /* Rx Flex Descriptor NIC Profile * RxDID Profile ID 2 * Flex-field 0: RSS hash lower 16-bits * Flex-field 1: RSS hash upper 16-bits * Flex-field 2: Flow ID lower 16-bits * Flex-field 3: Flow ID higher 16-bits * Flex-field 4: reserved, VLAN ID taken from L2Tag */ struct ice_32b_rx_flex_desc_nic { /* Qword 0 */ u8 rxdid; u8 mir_id_umb_cast; __le16 ptype_flexi_flags0; __le16 pkt_len; __le16 hdr_len_sph_flex_flags1; /* Qword 1 */ __le16 status_error0; __le16 l2tag1; __le32 rss_hash; /* Qword 2 */ __le16 status_error1; u8 flexi_flags2; u8 ts_low; __le16 l2tag2_1st; __le16 l2tag2_2nd; /* Qword 3 */ __le32 flow_id; union { struct { __le16 rsvd; __le16 flow_id_ipv6; } flex; __le32 ts_high; } flex_ts; }; /* Rx Flex Descriptor Switch Profile * RxDID Profile ID 3 * Flex-field 0: Source VSI */ struct ice_32b_rx_flex_desc_sw { /* Qword 0 */ u8 rxdid; u8 mir_id_umb_cast; __le16 ptype_flexi_flags0; __le16 pkt_len; __le16 hdr_len_sph_flex_flags1; /* Qword 1 */ __le16 status_error0; __le16 l2tag1; __le16 src_vsi; /* [10:15] are reserved */ __le16 flex_md1_rsvd; /* Qword 2 */ __le16 status_error1; u8 flex_flags2; u8 ts_low; __le16 l2tag2_1st; __le16 l2tag2_2nd; /* Qword 3 */ __le32 rsvd; /* flex words 2-3 are reserved */ __le32 ts_high; }; /* Rx Flex Descriptor NIC VEB Profile * RxDID Profile ID 4 * Flex-field 0: Destination VSI */ struct ice_32b_rx_flex_desc_nic_veb_dbg { /* Qword 0 */ u8 rxdid; u8 mir_id_umb_cast; __le16 ptype_flexi_flags0; __le16 pkt_len; __le16 hdr_len_sph_flex_flags1; /* Qword 1 */ __le16 status_error0; __le16 l2tag1; __le16 dst_vsi; /* [0:12]: destination VSI */ /* 13: VSI valid bit */ /* [14:15] are reserved */ __le16 flex_field_1; /* Qword 2 */ __le16 status_error1; u8 flex_flags2; u8 ts_low; __le16 l2tag2_1st; __le16 l2tag2_2nd; /* Qword 3 */ __le32 rsvd; /* flex words 2-3 are reserved */ __le32 ts_high; }; /* Rx Flex Descriptor NIC ACL Profile * RxDID Profile ID 5 * Flex-field 0: ACL Counter 0 * Flex-field 1: ACL Counter 1 * Flex-field 2: ACL Counter 2 */ struct ice_32b_rx_flex_desc_nic_acl_dbg { /* Qword 0 */ u8 rxdid; u8 mir_id_umb_cast; __le16 ptype_flexi_flags0; __le16 pkt_len; __le16 hdr_len_sph_flex_flags1; /* Qword 1 */ __le16 status_error0; __le16 l2tag1; __le16 acl_ctr0; __le16 acl_ctr1; /* Qword 2 */ __le16 status_error1; u8 flex_flags2; u8 ts_low; __le16 l2tag2_1st; __le16 l2tag2_2nd; /* Qword 3 */ __le16 acl_ctr2; __le16 rsvd; /* flex words 2-3 are reserved */ __le32 ts_high; }; /* Rx Flex Descriptor NIC Profile * RxDID Profile ID 6 * Flex-field 0: RSS hash lower 16-bits * Flex-field 1: RSS hash upper 16-bits * Flex-field 2: Flow ID lower 16-bits * Flex-field 3: Source VSI * Flex-field 4: reserved, VLAN ID taken from L2Tag */ struct ice_32b_rx_flex_desc_nic_2 { /* Qword 0 */ u8 rxdid; u8 mir_id_umb_cast; __le16 ptype_flexi_flags0; __le16 pkt_len; __le16 hdr_len_sph_flex_flags1; /* Qword 1 */ __le16 status_error0; __le16 l2tag1; __le32 rss_hash; /* Qword 2 */ __le16 status_error1; u8 flexi_flags2; u8 ts_low; __le16 l2tag2_1st; __le16 l2tag2_2nd; /* Qword 3 */ __le16 flow_id; __le16 src_vsi; union { struct { __le16 rsvd; __le16 flow_id_ipv6; } flex; __le32 ts_high; } flex_ts; }; /* Receive Flex Descriptor profile IDs: There are a total * of 64 profiles where profile IDs 0/1 are for legacy; and * profiles 2-63 are flex profiles that can be programmed * with a specific metadata (profile 7 reserved for HW) */ enum ice_rxdid { ICE_RXDID_LEGACY_0 = 0, ICE_RXDID_LEGACY_1 = 1, ICE_RXDID_FLEX_NIC = 2, ICE_RXDID_FLEX_NIC_2 = 6, ICE_RXDID_HW = 7, ICE_RXDID_LAST = 63, }; -/* Recceive Flex descriptor Dword Index */ +/* Receive Flex descriptor Dword Index */ enum ice_flex_word { ICE_RX_FLEX_DWORD_0 = 0, ICE_RX_FLEX_DWORD_1, ICE_RX_FLEX_DWORD_2, ICE_RX_FLEX_DWORD_3, ICE_RX_FLEX_DWORD_4, ICE_RX_FLEX_DWORD_5 }; /* Receive Flex Descriptor Rx opcode values */ enum ice_flex_opcode { ICE_RX_OPC_DEBUG = 0, ICE_RX_OPC_MDID, ICE_RX_OPC_EXTRACT, ICE_RX_OPC_PROTID }; /* Receive Descriptor MDID values that access packet flags */ enum ice_flex_mdid_pkt_flags { ICE_RX_MDID_PKT_FLAGS_15_0 = 20, ICE_RX_MDID_PKT_FLAGS_31_16, ICE_RX_MDID_PKT_FLAGS_47_32, ICE_RX_MDID_PKT_FLAGS_63_48, }; /* Generic descriptor MDID values */ enum ice_flex_mdid { ICE_MDID_GENERIC_WORD_0, ICE_MDID_GENERIC_WORD_1, ICE_MDID_GENERIC_WORD_2, ICE_MDID_GENERIC_WORD_3, ICE_MDID_GENERIC_WORD_4, ICE_MDID_FLOW_ID_LOWER, ICE_MDID_FLOW_ID_HIGH, ICE_MDID_RX_DESCR_PROF_IDX, ICE_MDID_RX_PKT_DROP, ICE_MDID_RX_DST_Q = 12, ICE_MDID_RX_DST_VSI, ICE_MDID_SRC_VSI = 19, ICE_MDID_ACL_NOP = 55, /* Entry 56 */ ICE_MDID_RX_HASH_LOW, ICE_MDID_ACL_CNTR_PKT = ICE_MDID_RX_HASH_LOW, /* Entry 57 */ ICE_MDID_RX_HASH_HIGH, ICE_MDID_ACL_CNTR_BYTES = ICE_MDID_RX_HASH_HIGH, ICE_MDID_ACL_CNTR_PKT_BYTES }; /* for ice_32byte_rx_flex_desc.mir_id_umb_cast member */ #define ICE_RX_FLEX_DESC_MIRROR_M (0x3F) /* 6-bits */ /* Rx/Tx Flag64 packet flag bits */ enum ice_flg64_bits { ICE_FLG_PKT_DSI = 0, /* If there is a 1 in this bit position then that means Rx packet */ ICE_FLG_PKT_DIR = 4, ICE_FLG_EVLAN_x8100 = 14, ICE_FLG_EVLAN_x9100, ICE_FLG_VLAN_x8100, ICE_FLG_TNL_MAC = 22, ICE_FLG_TNL_VLAN, ICE_FLG_PKT_FRG, ICE_FLG_FIN = 32, ICE_FLG_SYN, ICE_FLG_RST, ICE_FLG_TNL0 = 38, ICE_FLG_TNL1, ICE_FLG_TNL2, ICE_FLG_UDP_GRE, ICE_FLG_RSVD = 63 }; enum ice_rx_flex_desc_umb_cast_bits { /* field is 2 bits long */ ICE_RX_FLEX_DESC_UMB_CAST_S = 6, ICE_RX_FLEX_DESC_UMB_CAST_LAST /* this entry must be last!!! */ }; enum ice_umbcast_dest_addr_types { ICE_DEST_UNICAST = 0, ICE_DEST_MULTICAST, ICE_DEST_BROADCAST, ICE_DEST_MIRRORED, }; /* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */ #define ICE_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */ enum ice_rx_flex_desc_flexi_flags0_bits { /* field is 6 bits long */ ICE_RX_FLEX_DESC_FLEXI_FLAGS0_S = 10, ICE_RX_FLEX_DESC_FLEXI_FLAGS0_LAST /* this entry must be last!!! */ }; /* for ice_32byte_rx_flex_desc.pkt_length member */ #define ICE_RX_FLX_DESC_PKT_LEN_M (0x3FFF) /* 14-bits */ /* for ice_32byte_rx_flex_desc.header_length_sph_flexi_flags1 member */ #define ICE_RX_FLEX_DESC_HEADER_LEN_M (0x7FF) /* 11-bits */ enum ice_rx_flex_desc_sph_bits { /* field is 1 bit long */ ICE_RX_FLEX_DESC_SPH_S = 11, ICE_RX_FLEX_DESC_SPH_LAST /* this entry must be last!!! */ }; enum ice_rx_flex_desc_flexi_flags1_bits { /* field is 4 bits long */ ICE_RX_FLEX_DESC_FLEXI_FLAGS1_S = 12, ICE_RX_FLEX_DESC_FLEXI_FLAGS1_LAST /* this entry must be last!!! */ }; enum ice_rx_flex_desc_ext_status_bits { /* field is 4 bits long */ ICE_RX_FLEX_DESC_EXT_STATUS_EXT_UDP_S = 12, ICE_RX_FLEX_DESC_EXT_STATUS_INT_UDP_S = 13, ICE_RX_FLEX_DESC_EXT_STATUS_RECIPE_S = 14, ICE_RX_FLEX_DESC_EXT_STATUS_OVERSIZE_S = 15, ICE_RX_FLEX_DESC_EXT_STATUS_LAST /* entry must be last!!! */ }; enum ice_rx_flex_desc_status_error_0_bits { /* Note: These are predefined bit offsets */ ICE_RX_FLEX_DESC_STATUS0_DD_S = 0, ICE_RX_FLEX_DESC_STATUS0_EOF_S, ICE_RX_FLEX_DESC_STATUS0_HBO_S, ICE_RX_FLEX_DESC_STATUS0_L3L4P_S, ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S, ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S, ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S, ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S, ICE_RX_FLEX_DESC_STATUS0_LPBK_S, ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S, ICE_RX_FLEX_DESC_STATUS0_RXE_S, ICE_RX_FLEX_DESC_STATUS0_CRCP_S, ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S, ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S, ICE_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S, ICE_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S, ICE_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */ }; enum ice_rx_flex_desc_status_error_1_bits { /* Note: These are predefined bit offsets */ ICE_RX_FLEX_DESC_STATUS1_CPM_S = 0, /* 4 bits */ ICE_RX_FLEX_DESC_STATUS1_NAT_S = 4, ICE_RX_FLEX_DESC_STATUS1_CRYPTO_S = 5, /* [10:6] reserved */ ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S = 11, ICE_RX_FLEX_DESC_STATUS1_XTRMD2_VALID_S = 12, ICE_RX_FLEX_DESC_STATUS1_XTRMD3_VALID_S = 13, ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S = 14, ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S = 15, ICE_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */ }; enum ice_rx_flex_desc_exstat_bits { /* Note: These are predefined bit offsets */ ICE_RX_FLEX_DESC_EXSTAT_EXTUDP_S = 0, ICE_RX_FLEX_DESC_EXSTAT_INTUDP_S = 1, ICE_RX_FLEX_DESC_EXSTAT_RECIPE_S = 2, ICE_RX_FLEX_DESC_EXSTAT_OVERSIZE_S = 3, }; /* * For ice_32b_rx_flex_desc.ts_low: * [0]: Timestamp-low validity bit * [1:7]: Timestamp-low value */ #define ICE_RX_FLEX_DESC_TS_L_VALID_S 0x01 #define ICE_RX_FLEX_DESC_TS_L_VALID_M ICE_RX_FLEX_DESC_TS_L_VALID_S #define ICE_RX_FLEX_DESC_TS_L_M 0xFE #define ICE_RXQ_CTX_SIZE_DWORDS 8 #define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32)) #define ICE_TXQ_CTX_SIZE_DWORDS 10 #define ICE_TXQ_CTX_SZ (ICE_TXQ_CTX_SIZE_DWORDS * sizeof(u32)) #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS 22 #define ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS 5 #define GLTCLAN_CQ_CNTX(i, CQ) (GLTCLAN_CQ_CNTX0(CQ) + ((i) * 0x0800)) /* RLAN Rx queue context data * * The sizes of the variables may be larger than needed due to crossing byte * boundaries. If we do not have the width of the variable set to the correct * size then we could end up shifting bits off the top of the variable when the * variable is at the top of a byte and crosses over into the next byte. */ struct ice_rlan_ctx { u16 head; u16 cpuid; /* bigger than needed, see above for reason */ #define ICE_RLAN_BASE_S 7 u64 base; u16 qlen; #define ICE_RLAN_CTX_DBUF_S 7 u16 dbuf; /* bigger than needed, see above for reason */ #define ICE_RLAN_CTX_HBUF_S 6 u16 hbuf; /* bigger than needed, see above for reason */ u8 dtype; u8 dsize; u8 crcstrip; u8 l2tsel; u8 hsplit_0; u8 hsplit_1; u8 showiv; u32 rxmax; /* bigger than needed, see above for reason */ u8 tphrdesc_ena; u8 tphwdesc_ena; u8 tphdata_ena; u8 tphhead_ena; u16 lrxqthresh; /* bigger than needed, see above for reason */ u8 prefena; /* NOTE: normally must be set to 1 at init */ }; struct ice_ctx_ele { u16 offset; u16 size_of; u16 width; u16 lsb; }; #define ICE_CTX_STORE(_struct, _ele, _width, _lsb) { \ .offset = offsetof(struct _struct, _ele), \ .size_of = FIELD_SIZEOF(struct _struct, _ele), \ .width = _width, \ .lsb = _lsb, \ } /* for hsplit_0 field of Rx RLAN context */ enum ice_rlan_ctx_rx_hsplit_0 { ICE_RLAN_RX_HSPLIT_0_NO_SPLIT = 0, ICE_RLAN_RX_HSPLIT_0_SPLIT_L2 = 1, ICE_RLAN_RX_HSPLIT_0_SPLIT_IP = 2, ICE_RLAN_RX_HSPLIT_0_SPLIT_TCP_UDP = 4, ICE_RLAN_RX_HSPLIT_0_SPLIT_SCTP = 8, }; /* for hsplit_1 field of Rx RLAN context */ enum ice_rlan_ctx_rx_hsplit_1 { ICE_RLAN_RX_HSPLIT_1_NO_SPLIT = 0, ICE_RLAN_RX_HSPLIT_1_SPLIT_L2 = 1, ICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS = 2, }; /* Tx Descriptor */ struct ice_tx_desc { __le64 buf_addr; /* Address of descriptor's data buf */ __le64 cmd_type_offset_bsz; }; #define ICE_TXD_QW1_DTYPE_S 0 #define ICE_TXD_QW1_DTYPE_M (0xFUL << ICE_TXD_QW1_DTYPE_S) enum ice_tx_desc_dtype_value { ICE_TX_DESC_DTYPE_DATA = 0x0, ICE_TX_DESC_DTYPE_CTX = 0x1, ICE_TX_DESC_DTYPE_IPSEC = 0x3, ICE_TX_DESC_DTYPE_FLTR_PROG = 0x8, ICE_TX_DESC_DTYPE_HLP_META = 0x9, /* DESC_DONE - HW has completed write-back of descriptor */ ICE_TX_DESC_DTYPE_DESC_DONE = 0xF, }; #define ICE_TXD_QW1_CMD_S 4 #define ICE_TXD_QW1_CMD_M (0xFFFUL << ICE_TXD_QW1_CMD_S) enum ice_tx_desc_cmd_bits { ICE_TX_DESC_CMD_EOP = 0x0001, ICE_TX_DESC_CMD_RS = 0x0002, ICE_TX_DESC_CMD_RSVD = 0x0004, ICE_TX_DESC_CMD_IL2TAG1 = 0x0008, ICE_TX_DESC_CMD_DUMMY = 0x0010, ICE_TX_DESC_CMD_IIPT_NONIP = 0x0000, ICE_TX_DESC_CMD_IIPT_IPV6 = 0x0020, ICE_TX_DESC_CMD_IIPT_IPV4 = 0x0040, ICE_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, ICE_TX_DESC_CMD_RSVD2 = 0x0080, ICE_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, ICE_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, ICE_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, ICE_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, ICE_TX_DESC_CMD_RE = 0x0400, ICE_TX_DESC_CMD_RSVD3 = 0x0800, }; #define ICE_TXD_QW1_OFFSET_S 16 #define ICE_TXD_QW1_OFFSET_M (0x3FFFFULL << ICE_TXD_QW1_OFFSET_S) enum ice_tx_desc_len_fields { /* Note: These are predefined bit offsets */ ICE_TX_DESC_LEN_MACLEN_S = 0, /* 7 BITS */ ICE_TX_DESC_LEN_IPLEN_S = 7, /* 7 BITS */ ICE_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */ }; #define ICE_TXD_QW1_MACLEN_M (0x7FUL << ICE_TX_DESC_LEN_MACLEN_S) #define ICE_TXD_QW1_IPLEN_M (0x7FUL << ICE_TX_DESC_LEN_IPLEN_S) #define ICE_TXD_QW1_L4LEN_M (0xFUL << ICE_TX_DESC_LEN_L4_LEN_S) /* Tx descriptor field limits in bytes */ #define ICE_TXD_MACLEN_MAX ((ICE_TXD_QW1_MACLEN_M >> \ ICE_TX_DESC_LEN_MACLEN_S) * ICE_BYTES_PER_WORD) #define ICE_TXD_IPLEN_MAX ((ICE_TXD_QW1_IPLEN_M >> \ ICE_TX_DESC_LEN_IPLEN_S) * ICE_BYTES_PER_DWORD) #define ICE_TXD_L4LEN_MAX ((ICE_TXD_QW1_L4LEN_M >> \ ICE_TX_DESC_LEN_L4_LEN_S) * ICE_BYTES_PER_DWORD) #define ICE_TXD_QW1_TX_BUF_SZ_S 34 #define ICE_TXD_QW1_TX_BUF_SZ_M (0x3FFFULL << ICE_TXD_QW1_TX_BUF_SZ_S) #define ICE_TXD_QW1_L2TAG1_S 48 #define ICE_TXD_QW1_L2TAG1_M (0xFFFFULL << ICE_TXD_QW1_L2TAG1_S) /* Context descriptors */ struct ice_tx_ctx_desc { __le32 tunneling_params; __le16 l2tag2; __le16 rsvd; __le64 qw1; }; #define ICE_TX_GCS_DESC_START 0 /* 8 BITS */ #define ICE_TX_GCS_DESC_OFFSET 8 /* 4 BITS */ #define ICE_TX_GCS_DESC_TYPE 12 /* 3 BITS */ #define ICE_TXD_CTX_QW1_DTYPE_S 0 #define ICE_TXD_CTX_QW1_DTYPE_M (0xFUL << ICE_TXD_CTX_QW1_DTYPE_S) #define ICE_TXD_CTX_QW1_CMD_S 4 #define ICE_TXD_CTX_QW1_CMD_M (0x7FUL << ICE_TXD_CTX_QW1_CMD_S) #define ICE_TXD_CTX_QW1_IPSEC_S 11 #define ICE_TXD_CTX_QW1_IPSEC_M (0x7FUL << ICE_TXD_CTX_QW1_IPSEC_S) #define ICE_TXD_CTX_QW1_TSO_LEN_S 30 #define ICE_TXD_CTX_QW1_TSO_LEN_M \ (0x3FFFFULL << ICE_TXD_CTX_QW1_TSO_LEN_S) #define ICE_TXD_CTX_QW1_TSYN_S ICE_TXD_CTX_QW1_TSO_LEN_S #define ICE_TXD_CTX_QW1_TSYN_M ICE_TXD_CTX_QW1_TSO_LEN_M #define ICE_TXD_CTX_QW1_MSS_S 50 #define ICE_TXD_CTX_QW1_MSS_M (0x3FFFULL << ICE_TXD_CTX_QW1_MSS_S) #define ICE_TXD_CTX_MIN_MSS 64 #define ICE_TXD_CTX_MAX_MSS 9668 #define ICE_TXD_CTX_QW1_VSI_S 50 #define ICE_TXD_CTX_QW1_VSI_M (0x3FFULL << ICE_TXD_CTX_QW1_VSI_S) enum ice_tx_ctx_desc_cmd_bits { ICE_TX_CTX_DESC_TSO = 0x01, ICE_TX_CTX_DESC_TSYN = 0x02, ICE_TX_CTX_DESC_IL2TAG2 = 0x04, ICE_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, ICE_TX_CTX_DESC_SWTCH_NOTAG = 0x00, ICE_TX_CTX_DESC_SWTCH_UPLINK = 0x10, ICE_TX_CTX_DESC_SWTCH_LOCAL = 0x20, ICE_TX_CTX_DESC_SWTCH_VSI = 0x30, ICE_TX_CTX_DESC_RESERVED = 0x40 }; enum ice_tx_ctx_desc_eipt_offload { ICE_TX_CTX_EIPT_NONE = 0x0, ICE_TX_CTX_EIPT_IPV6 = 0x1, ICE_TX_CTX_EIPT_IPV4_NO_CSUM = 0x2, ICE_TX_CTX_EIPT_IPV4 = 0x3 }; #define ICE_TXD_CTX_QW0_EIPT_S 0 #define ICE_TXD_CTX_QW0_EIPT_M (0x3ULL << ICE_TXD_CTX_QW0_EIPT_S) #define ICE_TXD_CTX_QW0_EIPLEN_S 2 #define ICE_TXD_CTX_QW0_EIPLEN_M (0x7FUL << ICE_TXD_CTX_QW0_EIPLEN_S) #define ICE_TXD_CTX_QW0_L4TUNT_S 9 #define ICE_TXD_CTX_QW0_L4TUNT_M (0x3ULL << ICE_TXD_CTX_QW0_L4TUNT_S) #define ICE_TXD_CTX_UDP_TUNNELING BIT_ULL(ICE_TXD_CTX_QW0_L4TUNT_S) #define ICE_TXD_CTX_GRE_TUNNELING (0x2ULL << ICE_TXD_CTX_QW0_L4TUNT_S) #define ICE_TXD_CTX_QW0_EIP_NOINC_S 11 #define ICE_TXD_CTX_QW0_EIP_NOINC_M BIT_ULL(ICE_TXD_CTX_QW0_EIP_NOINC_S) #define ICE_TXD_CTX_EIP_NOINC_IPID_CONST ICE_TXD_CTX_QW0_EIP_NOINC_M #define ICE_TXD_CTX_QW0_NATLEN_S 12 #define ICE_TXD_CTX_QW0_NATLEN_M (0X7FULL << ICE_TXD_CTX_QW0_NATLEN_S) #define ICE_TXD_CTX_QW0_DECTTL_S 19 #define ICE_TXD_CTX_QW0_DECTTL_M (0xFULL << ICE_TXD_CTX_QW0_DECTTL_S) #define ICE_TXD_CTX_QW0_L4T_CS_S 23 #define ICE_TXD_CTX_QW0_L4T_CS_M BIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S) #define ICE_LAN_TXQ_MAX_QGRPS 127 #define ICE_LAN_TXQ_MAX_QDIS 1023 /* Tx queue context data * * The sizes of the variables may be larger than needed due to crossing byte * boundaries. If we do not have the width of the variable set to the correct * size then we could end up shifting bits off the top of the variable when the * variable is at the top of a byte and crosses over into the next byte. */ struct ice_tlan_ctx { #define ICE_TLAN_CTX_BASE_S 7 u64 base; /* base is defined in 128-byte units */ u8 port_num; u16 cgd_num; /* bigger than needed, see above for reason */ u8 pf_num; u16 vmvf_num; u8 vmvf_type; #define ICE_TLAN_CTX_VMVF_TYPE_VF 0 #define ICE_TLAN_CTX_VMVF_TYPE_VMQ 1 #define ICE_TLAN_CTX_VMVF_TYPE_PF 2 u16 src_vsi; u8 tsyn_ena; u8 internal_usage_flag; u8 alt_vlan; u16 cpuid; /* bigger than needed, see above for reason */ u8 wb_mode; u8 tphrd_desc; u8 tphrd; u8 tphwr_desc; u16 cmpq_id; u16 qnum_in_func; u8 itr_notification_mode; u8 adjust_prof_id; u32 qlen; /* bigger than needed, see above for reason */ u8 quanta_prof_idx; u8 tso_ena; u16 tso_qnum; u8 legacy_int; u8 drop_ena; u8 cache_prof_idx; u8 pkt_shaper_prof_idx; u8 int_q_state; /* width not needed - internal - DO NOT WRITE!!! */ u16 tail; }; /* LAN Tx Completion Queue data */ #pragma pack(1) struct ice_tx_cmpltnq { u16 txq_id; u8 generation; u16 tx_head; u8 cmpl_type; }; #pragma pack() /* FIXME: move to a .c file that references this variable */ /* LAN Tx Completion Queue data info */ static const struct ice_ctx_ele ice_tx_cmpltnq_info[] = { /* Field Width LSB */ ICE_CTX_STORE(ice_tx_cmpltnq, txq_id, 14, 0), ICE_CTX_STORE(ice_tx_cmpltnq, generation, 1, 15), ICE_CTX_STORE(ice_tx_cmpltnq, tx_head, 13, 16), ICE_CTX_STORE(ice_tx_cmpltnq, cmpl_type, 3, 29), { 0 } }; /* LAN Tx Completion Queue Context */ #pragma pack(1) struct ice_tx_cmpltnq_ctx { u64 base; #define ICE_TX_CMPLTNQ_CTX_BASE_S 7 u32 q_len; #define ICE_TX_CMPLTNQ_CTX_Q_LEN_S 4 u8 generation; u32 wrt_ptr; u8 pf_num; u16 vmvf_num; u8 vmvf_type; #define ICE_TX_CMPLTNQ_CTX_VMVF_TYPE_VF 0 #define ICE_TX_CMPLTNQ_CTX_VMVF_TYPE_VMQ 1 #define ICE_TX_CMPLTNQ_CTX_VMVF_TYPE_PF 2 u8 tph_desc_wr; u8 cpuid; u32 cmpltn_cache[16]; }; #pragma pack() /* LAN Tx Doorbell Descriptor Format */ struct ice_tx_drbell_fmt { u16 txq_id; u8 dd; u8 rs; u32 db; }; /* FIXME: move to a .c file that references this variable */ /* LAN Tx Doorbell Descriptor format info */ static const struct ice_ctx_ele ice_tx_drbell_fmt_info[] = { /* Field Width LSB */ ICE_CTX_STORE(ice_tx_drbell_fmt, txq_id, 14, 0), ICE_CTX_STORE(ice_tx_drbell_fmt, dd, 1, 14), ICE_CTX_STORE(ice_tx_drbell_fmt, rs, 1, 15), ICE_CTX_STORE(ice_tx_drbell_fmt, db, 32, 32), { 0 } }; /* LAN Tx Doorbell Queue Context */ #pragma pack(1) struct ice_tx_drbell_q_ctx { u64 base; #define ICE_TX_DRBELL_Q_CTX_BASE_S 7 u16 ring_len; #define ICE_TX_DRBELL_Q_CTX_RING_LEN_S 4 u8 pf_num; u16 vf_num; u8 vmvf_type; #define ICE_TX_DRBELL_Q_CTX_VMVF_TYPE_VF 0 #define ICE_TX_DRBELL_Q_CTX_VMVF_TYPE_VMQ 1 #define ICE_TX_DRBELL_Q_CTX_VMVF_TYPE_PF 2 u8 cpuid; u8 tph_desc_rd; u8 tph_desc_wr; u8 db_q_en; u16 rd_head; u16 rd_tail; }; #pragma pack() /* The ice_ptype_lkup table is used to convert from the 10-bit ptype in the * hardware to a bit-field that can be used by SW to more easily determine the * packet type. * * Macros are used to shorten the table lines and make this table human * readable. * * We store the PTYPE in the top byte of the bit field - this is just so that * we can check that the table doesn't have a row missing, as the index into * the table should be the PTYPE. * * Typical work flow: * * IF NOT ice_ptype_lkup[ptype].known * THEN * Packet is unknown * ELSE IF ice_ptype_lkup[ptype].outer_ip == ICE_RX_PTYPE_OUTER_IP * Use the rest of the fields to look at the tunnels, inner protocols, etc * ELSE * Use the enum ice_rx_l2_ptype to decode the packet type * ENDIF */ /* macro to make the table lines short */ #define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ { 1, \ ICE_RX_PTYPE_OUTER_##OUTER_IP, \ ICE_RX_PTYPE_OUTER_##OUTER_IP_VER, \ ICE_RX_PTYPE_##OUTER_FRAG, \ ICE_RX_PTYPE_TUNNEL_##T, \ ICE_RX_PTYPE_TUNNEL_END_##TE, \ ICE_RX_PTYPE_##TEF, \ ICE_RX_PTYPE_INNER_PROT_##I, \ ICE_RX_PTYPE_PAYLOAD_LAYER_##PL } #define ICE_PTT_UNUSED_ENTRY(PTYPE) { 0, 0, 0, 0, 0, 0, 0, 0, 0 } /* shorter macros makes the table fit but are terse */ #define ICE_RX_PTYPE_NOF ICE_RX_PTYPE_NOT_FRAG #define ICE_RX_PTYPE_FRG ICE_RX_PTYPE_FRAG /* Lookup table mapping the 10-bit HW PTYPE to the bit field for decoding */ static const struct ice_rx_ptype_decoded ice_ptype_lkup[1024] = { /* L2 Packet types */ ICE_PTT_UNUSED_ENTRY(0), ICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), ICE_PTT_UNUSED_ENTRY(2), ICE_PTT_UNUSED_ENTRY(3), ICE_PTT_UNUSED_ENTRY(4), ICE_PTT_UNUSED_ENTRY(5), ICE_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), ICE_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), ICE_PTT_UNUSED_ENTRY(8), ICE_PTT_UNUSED_ENTRY(9), ICE_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), ICE_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), ICE_PTT_UNUSED_ENTRY(12), ICE_PTT_UNUSED_ENTRY(13), ICE_PTT_UNUSED_ENTRY(14), ICE_PTT_UNUSED_ENTRY(15), ICE_PTT_UNUSED_ENTRY(16), ICE_PTT_UNUSED_ENTRY(17), ICE_PTT_UNUSED_ENTRY(18), ICE_PTT_UNUSED_ENTRY(19), ICE_PTT_UNUSED_ENTRY(20), ICE_PTT_UNUSED_ENTRY(21), /* Non Tunneled IPv4 */ ICE_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), ICE_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), ICE_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(25), ICE_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), ICE_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), ICE_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), /* IPv4 --> IPv4 */ ICE_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), ICE_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), ICE_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(32), ICE_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), ICE_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), ICE_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), /* IPv4 --> IPv6 */ ICE_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), ICE_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), ICE_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(39), ICE_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), ICE_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), ICE_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), /* IPv4 --> GRE/NAT */ ICE_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), /* IPv4 --> GRE/NAT --> IPv4 */ ICE_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), ICE_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), ICE_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(47), ICE_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), ICE_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), ICE_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), /* IPv4 --> GRE/NAT --> IPv6 */ ICE_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), ICE_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), ICE_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(54), ICE_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), ICE_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), ICE_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), /* IPv4 --> GRE/NAT --> MAC */ ICE_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ ICE_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), ICE_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), ICE_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(62), ICE_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), ICE_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), ICE_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ ICE_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), ICE_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), ICE_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(69), ICE_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), ICE_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), ICE_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), /* IPv4 --> GRE/NAT --> MAC/VLAN */ ICE_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ ICE_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), ICE_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), ICE_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(77), ICE_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), ICE_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), ICE_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ ICE_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), ICE_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), ICE_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(84), ICE_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), ICE_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), ICE_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), /* Non Tunneled IPv6 */ ICE_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), ICE_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), ICE_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(91), ICE_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), ICE_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), ICE_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), /* IPv6 --> IPv4 */ ICE_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), ICE_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), ICE_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(98), ICE_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), ICE_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), ICE_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), /* IPv6 --> IPv6 */ ICE_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), ICE_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), ICE_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(105), ICE_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), ICE_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), ICE_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), /* IPv6 --> GRE/NAT */ ICE_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), /* IPv6 --> GRE/NAT -> IPv4 */ ICE_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), ICE_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), ICE_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(113), ICE_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), ICE_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), ICE_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), /* IPv6 --> GRE/NAT -> IPv6 */ ICE_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), ICE_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), ICE_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(120), ICE_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), ICE_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), ICE_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), /* IPv6 --> GRE/NAT -> MAC */ ICE_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ ICE_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), ICE_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), ICE_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(128), ICE_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), ICE_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), ICE_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ ICE_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), ICE_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), ICE_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(135), ICE_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), ICE_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), ICE_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), /* IPv6 --> GRE/NAT -> MAC/VLAN */ ICE_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ ICE_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), ICE_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), ICE_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(143), ICE_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), ICE_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), ICE_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ ICE_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), ICE_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), ICE_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(150), ICE_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), ICE_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), ICE_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), /* unused entries */ ICE_PTT_UNUSED_ENTRY(154), ICE_PTT_UNUSED_ENTRY(155), ICE_PTT_UNUSED_ENTRY(156), ICE_PTT_UNUSED_ENTRY(157), ICE_PTT_UNUSED_ENTRY(158), ICE_PTT_UNUSED_ENTRY(159), ICE_PTT_UNUSED_ENTRY(160), ICE_PTT_UNUSED_ENTRY(161), ICE_PTT_UNUSED_ENTRY(162), ICE_PTT_UNUSED_ENTRY(163), ICE_PTT_UNUSED_ENTRY(164), ICE_PTT_UNUSED_ENTRY(165), ICE_PTT_UNUSED_ENTRY(166), ICE_PTT_UNUSED_ENTRY(167), ICE_PTT_UNUSED_ENTRY(168), ICE_PTT_UNUSED_ENTRY(169), ICE_PTT_UNUSED_ENTRY(170), ICE_PTT_UNUSED_ENTRY(171), ICE_PTT_UNUSED_ENTRY(172), ICE_PTT_UNUSED_ENTRY(173), ICE_PTT_UNUSED_ENTRY(174), ICE_PTT_UNUSED_ENTRY(175), ICE_PTT_UNUSED_ENTRY(176), ICE_PTT_UNUSED_ENTRY(177), ICE_PTT_UNUSED_ENTRY(178), ICE_PTT_UNUSED_ENTRY(179), ICE_PTT_UNUSED_ENTRY(180), ICE_PTT_UNUSED_ENTRY(181), ICE_PTT_UNUSED_ENTRY(182), ICE_PTT_UNUSED_ENTRY(183), ICE_PTT_UNUSED_ENTRY(184), ICE_PTT_UNUSED_ENTRY(185), ICE_PTT_UNUSED_ENTRY(186), ICE_PTT_UNUSED_ENTRY(187), ICE_PTT_UNUSED_ENTRY(188), ICE_PTT_UNUSED_ENTRY(189), ICE_PTT_UNUSED_ENTRY(190), ICE_PTT_UNUSED_ENTRY(191), ICE_PTT_UNUSED_ENTRY(192), ICE_PTT_UNUSED_ENTRY(193), ICE_PTT_UNUSED_ENTRY(194), ICE_PTT_UNUSED_ENTRY(195), ICE_PTT_UNUSED_ENTRY(196), ICE_PTT_UNUSED_ENTRY(197), ICE_PTT_UNUSED_ENTRY(198), ICE_PTT_UNUSED_ENTRY(199), ICE_PTT_UNUSED_ENTRY(200), ICE_PTT_UNUSED_ENTRY(201), ICE_PTT_UNUSED_ENTRY(202), ICE_PTT_UNUSED_ENTRY(203), ICE_PTT_UNUSED_ENTRY(204), ICE_PTT_UNUSED_ENTRY(205), ICE_PTT_UNUSED_ENTRY(206), ICE_PTT_UNUSED_ENTRY(207), ICE_PTT_UNUSED_ENTRY(208), ICE_PTT_UNUSED_ENTRY(209), ICE_PTT_UNUSED_ENTRY(210), ICE_PTT_UNUSED_ENTRY(211), ICE_PTT_UNUSED_ENTRY(212), ICE_PTT_UNUSED_ENTRY(213), ICE_PTT_UNUSED_ENTRY(214), ICE_PTT_UNUSED_ENTRY(215), ICE_PTT_UNUSED_ENTRY(216), ICE_PTT_UNUSED_ENTRY(217), ICE_PTT_UNUSED_ENTRY(218), ICE_PTT_UNUSED_ENTRY(219), ICE_PTT_UNUSED_ENTRY(220), ICE_PTT_UNUSED_ENTRY(221), ICE_PTT_UNUSED_ENTRY(222), ICE_PTT_UNUSED_ENTRY(223), ICE_PTT_UNUSED_ENTRY(224), ICE_PTT_UNUSED_ENTRY(225), ICE_PTT_UNUSED_ENTRY(226), ICE_PTT_UNUSED_ENTRY(227), ICE_PTT_UNUSED_ENTRY(228), ICE_PTT_UNUSED_ENTRY(229), ICE_PTT_UNUSED_ENTRY(230), ICE_PTT_UNUSED_ENTRY(231), ICE_PTT_UNUSED_ENTRY(232), ICE_PTT_UNUSED_ENTRY(233), ICE_PTT_UNUSED_ENTRY(234), ICE_PTT_UNUSED_ENTRY(235), ICE_PTT_UNUSED_ENTRY(236), ICE_PTT_UNUSED_ENTRY(237), ICE_PTT_UNUSED_ENTRY(238), ICE_PTT_UNUSED_ENTRY(239), ICE_PTT_UNUSED_ENTRY(240), ICE_PTT_UNUSED_ENTRY(241), ICE_PTT_UNUSED_ENTRY(242), ICE_PTT_UNUSED_ENTRY(243), ICE_PTT_UNUSED_ENTRY(244), ICE_PTT_UNUSED_ENTRY(245), ICE_PTT_UNUSED_ENTRY(246), ICE_PTT_UNUSED_ENTRY(247), ICE_PTT_UNUSED_ENTRY(248), ICE_PTT_UNUSED_ENTRY(249), ICE_PTT_UNUSED_ENTRY(250), ICE_PTT_UNUSED_ENTRY(251), ICE_PTT_UNUSED_ENTRY(252), ICE_PTT_UNUSED_ENTRY(253), ICE_PTT_UNUSED_ENTRY(254), ICE_PTT_UNUSED_ENTRY(255), ICE_PTT_UNUSED_ENTRY(256), ICE_PTT_UNUSED_ENTRY(257), ICE_PTT_UNUSED_ENTRY(258), ICE_PTT_UNUSED_ENTRY(259), ICE_PTT_UNUSED_ENTRY(260), ICE_PTT_UNUSED_ENTRY(261), ICE_PTT_UNUSED_ENTRY(262), ICE_PTT_UNUSED_ENTRY(263), ICE_PTT_UNUSED_ENTRY(264), ICE_PTT_UNUSED_ENTRY(265), ICE_PTT_UNUSED_ENTRY(266), ICE_PTT_UNUSED_ENTRY(267), ICE_PTT_UNUSED_ENTRY(268), ICE_PTT_UNUSED_ENTRY(269), ICE_PTT_UNUSED_ENTRY(270), ICE_PTT_UNUSED_ENTRY(271), ICE_PTT_UNUSED_ENTRY(272), ICE_PTT_UNUSED_ENTRY(273), ICE_PTT_UNUSED_ENTRY(274), ICE_PTT_UNUSED_ENTRY(275), ICE_PTT_UNUSED_ENTRY(276), ICE_PTT_UNUSED_ENTRY(277), ICE_PTT_UNUSED_ENTRY(278), ICE_PTT_UNUSED_ENTRY(279), ICE_PTT_UNUSED_ENTRY(280), ICE_PTT_UNUSED_ENTRY(281), ICE_PTT_UNUSED_ENTRY(282), ICE_PTT_UNUSED_ENTRY(283), ICE_PTT_UNUSED_ENTRY(284), ICE_PTT_UNUSED_ENTRY(285), ICE_PTT_UNUSED_ENTRY(286), ICE_PTT_UNUSED_ENTRY(287), ICE_PTT_UNUSED_ENTRY(288), ICE_PTT_UNUSED_ENTRY(289), ICE_PTT_UNUSED_ENTRY(290), ICE_PTT_UNUSED_ENTRY(291), ICE_PTT_UNUSED_ENTRY(292), ICE_PTT_UNUSED_ENTRY(293), ICE_PTT_UNUSED_ENTRY(294), ICE_PTT_UNUSED_ENTRY(295), ICE_PTT_UNUSED_ENTRY(296), ICE_PTT_UNUSED_ENTRY(297), ICE_PTT_UNUSED_ENTRY(298), ICE_PTT_UNUSED_ENTRY(299), ICE_PTT_UNUSED_ENTRY(300), ICE_PTT_UNUSED_ENTRY(301), ICE_PTT_UNUSED_ENTRY(302), ICE_PTT_UNUSED_ENTRY(303), ICE_PTT_UNUSED_ENTRY(304), ICE_PTT_UNUSED_ENTRY(305), ICE_PTT_UNUSED_ENTRY(306), ICE_PTT_UNUSED_ENTRY(307), ICE_PTT_UNUSED_ENTRY(308), ICE_PTT_UNUSED_ENTRY(309), ICE_PTT_UNUSED_ENTRY(310), ICE_PTT_UNUSED_ENTRY(311), ICE_PTT_UNUSED_ENTRY(312), ICE_PTT_UNUSED_ENTRY(313), ICE_PTT_UNUSED_ENTRY(314), ICE_PTT_UNUSED_ENTRY(315), ICE_PTT_UNUSED_ENTRY(316), ICE_PTT_UNUSED_ENTRY(317), ICE_PTT_UNUSED_ENTRY(318), ICE_PTT_UNUSED_ENTRY(319), ICE_PTT_UNUSED_ENTRY(320), ICE_PTT_UNUSED_ENTRY(321), ICE_PTT_UNUSED_ENTRY(322), ICE_PTT_UNUSED_ENTRY(323), ICE_PTT_UNUSED_ENTRY(324), ICE_PTT_UNUSED_ENTRY(325), ICE_PTT_UNUSED_ENTRY(326), ICE_PTT_UNUSED_ENTRY(327), ICE_PTT_UNUSED_ENTRY(328), ICE_PTT_UNUSED_ENTRY(329), ICE_PTT_UNUSED_ENTRY(330), ICE_PTT_UNUSED_ENTRY(331), ICE_PTT_UNUSED_ENTRY(332), ICE_PTT_UNUSED_ENTRY(333), ICE_PTT_UNUSED_ENTRY(334), ICE_PTT_UNUSED_ENTRY(335), ICE_PTT_UNUSED_ENTRY(336), ICE_PTT_UNUSED_ENTRY(337), ICE_PTT_UNUSED_ENTRY(338), ICE_PTT_UNUSED_ENTRY(339), ICE_PTT_UNUSED_ENTRY(340), ICE_PTT_UNUSED_ENTRY(341), ICE_PTT_UNUSED_ENTRY(342), ICE_PTT_UNUSED_ENTRY(343), ICE_PTT_UNUSED_ENTRY(344), ICE_PTT_UNUSED_ENTRY(345), ICE_PTT_UNUSED_ENTRY(346), ICE_PTT_UNUSED_ENTRY(347), ICE_PTT_UNUSED_ENTRY(348), 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ICE_PTT_UNUSED_ENTRY(978), ICE_PTT_UNUSED_ENTRY(979), ICE_PTT_UNUSED_ENTRY(980), ICE_PTT_UNUSED_ENTRY(981), ICE_PTT_UNUSED_ENTRY(982), ICE_PTT_UNUSED_ENTRY(983), ICE_PTT_UNUSED_ENTRY(984), ICE_PTT_UNUSED_ENTRY(985), ICE_PTT_UNUSED_ENTRY(986), ICE_PTT_UNUSED_ENTRY(987), ICE_PTT_UNUSED_ENTRY(988), ICE_PTT_UNUSED_ENTRY(989), ICE_PTT_UNUSED_ENTRY(990), ICE_PTT_UNUSED_ENTRY(991), ICE_PTT_UNUSED_ENTRY(992), ICE_PTT_UNUSED_ENTRY(993), ICE_PTT_UNUSED_ENTRY(994), ICE_PTT_UNUSED_ENTRY(995), ICE_PTT_UNUSED_ENTRY(996), ICE_PTT_UNUSED_ENTRY(997), ICE_PTT_UNUSED_ENTRY(998), ICE_PTT_UNUSED_ENTRY(999), ICE_PTT_UNUSED_ENTRY(1000), ICE_PTT_UNUSED_ENTRY(1001), ICE_PTT_UNUSED_ENTRY(1002), ICE_PTT_UNUSED_ENTRY(1003), ICE_PTT_UNUSED_ENTRY(1004), ICE_PTT_UNUSED_ENTRY(1005), ICE_PTT_UNUSED_ENTRY(1006), ICE_PTT_UNUSED_ENTRY(1007), ICE_PTT_UNUSED_ENTRY(1008), ICE_PTT_UNUSED_ENTRY(1009), ICE_PTT_UNUSED_ENTRY(1010), ICE_PTT_UNUSED_ENTRY(1011), ICE_PTT_UNUSED_ENTRY(1012), ICE_PTT_UNUSED_ENTRY(1013), ICE_PTT_UNUSED_ENTRY(1014), ICE_PTT_UNUSED_ENTRY(1015), ICE_PTT_UNUSED_ENTRY(1016), ICE_PTT_UNUSED_ENTRY(1017), ICE_PTT_UNUSED_ENTRY(1018), ICE_PTT_UNUSED_ENTRY(1019), ICE_PTT_UNUSED_ENTRY(1020), ICE_PTT_UNUSED_ENTRY(1021), ICE_PTT_UNUSED_ENTRY(1022), ICE_PTT_UNUSED_ENTRY(1023) }; static inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(u16 ptype) { return ice_ptype_lkup[ptype]; } #define ICE_LINK_SPEED_UNKNOWN 0 #define ICE_LINK_SPEED_10MBPS 10 #define ICE_LINK_SPEED_100MBPS 100 #define ICE_LINK_SPEED_1000MBPS 1000 #define ICE_LINK_SPEED_2500MBPS 2500 #define ICE_LINK_SPEED_5000MBPS 5000 #define ICE_LINK_SPEED_10000MBPS 10000 #define ICE_LINK_SPEED_20000MBPS 20000 #define ICE_LINK_SPEED_25000MBPS 25000 #define ICE_LINK_SPEED_40000MBPS 40000 #define ICE_LINK_SPEED_50000MBPS 50000 #define ICE_LINK_SPEED_100000MBPS 100000 #define ICE_LINK_SPEED_200000MBPS 200000 #endif /* _ICE_LAN_TX_RX_H_ */ diff --git a/sys/dev/ice/ice_lib.h b/sys/dev/ice/ice_lib.h index b6b23ec82161..28c4f668292c 100644 --- a/sys/dev/ice/ice_lib.h +++ b/sys/dev/ice/ice_lib.h @@ -1,1030 +1,1030 @@ /* SPDX-License-Identifier: BSD-3-Clause */ /* Copyright (c) 2024, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * 3. Neither the name of the Intel Corporation nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /** * @file ice_lib.h * @brief header for generic device and sysctl functions * * Contains definitions and function declarations for the ice_lib.c file. It * does not depend on the iflib networking stack. */ #ifndef _ICE_LIB_H_ #define _ICE_LIB_H_ /* include kernel options first */ #include "ice_opts.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "ice_dcb.h" #include "ice_type.h" #include "ice_common.h" #include "ice_flow.h" #include "ice_sched.h" #include "ice_resmgr.h" #include "ice_rdma_internal.h" #include "ice_rss.h" /* Hide debug sysctls unless INVARIANTS is enabled */ #ifdef INVARIANTS #define ICE_CTLFLAG_DEBUG 0 #else #define ICE_CTLFLAG_DEBUG CTLFLAG_SKIP #endif /** * for_each_set_bit - For loop over each set bit in a bit string * @bit: storage for the bit index * @data: address of data block to loop over * @nbits: maximum number of bits to loop over * * macro to create a for loop over a bit string, which runs the body once for * each bit that is set in the string. The bit variable will be set to the * index of each set bit in the string, with zero representing the first bit. */ #define for_each_set_bit(bit, data, nbits) \ for (bit_ffs((bitstr_t *)(data), (nbits), &(bit)); \ (bit) != -1; \ bit_ffs_at((bitstr_t *)(data), (bit) + 1, (nbits), &(bit))) /** * @var broadcastaddr * @brief broadcast MAC address * * constant defining the broadcast MAC address, used for programming the * broadcast address as a MAC filter for the PF VSI. */ static const u8 broadcastaddr[ETHER_ADDR_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; MALLOC_DECLARE(M_ICE); extern const char ice_driver_version[]; extern const uint8_t ice_major_version; extern const uint8_t ice_minor_version; extern const uint8_t ice_patch_version; extern const uint8_t ice_rc_version; /* global sysctl indicating whether the Tx FC filter should be enabled */ extern bool ice_enable_tx_fc_filter; /* global sysctl indicating whether the Tx LLDP filter should be enabled */ extern bool ice_enable_tx_lldp_filter; /* global sysctl indicating whether FW health status events should be enabled */ extern bool ice_enable_health_events; /* global sysctl indicating whether to enable 5-layer scheduler topology */ extern bool ice_tx_balance_en; /** * @struct ice_bar_info * @brief PCI BAR mapping information * * Contains data about a PCI BAR that the driver has mapped for use. */ struct ice_bar_info { struct resource *res; bus_space_tag_t tag; bus_space_handle_t handle; bus_size_t size; int rid; }; /* Alignment for queues */ #define DBA_ALIGN 128 /* Maximum TSO size is (256K)-1 */ #define ICE_TSO_SIZE ((256*1024) - 1) /* Minimum size for TSO MSS */ #define ICE_MIN_TSO_MSS 64 #define ICE_MAX_TX_SEGS 8 #define ICE_MAX_TSO_SEGS 128 #define ICE_MAX_DMA_SEG_SIZE ((16*1024) - 1) #define ICE_MAX_RX_SEGS 5 #define ICE_MAX_TSO_HDR_SEGS 3 #define ICE_MSIX_BAR 3 #define ICE_MAX_MSIX_VECTORS (GLINT_DYN_CTL_MAX_INDEX + 1) #define ICE_DEFAULT_DESC_COUNT 1024 #define ICE_MAX_DESC_COUNT 8160 #define ICE_MIN_DESC_COUNT 64 #define ICE_DESC_COUNT_INCR 32 /* List of hardware offloads we support */ #define ICE_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP | CSUM_IP_SCTP | \ CSUM_IP6_TCP| CSUM_IP6_UDP | CSUM_IP6_SCTP | \ CSUM_IP_TSO | CSUM_IP6_TSO) /* Macros to decide what kind of hardware offload to enable */ #define ICE_CSUM_TCP (CSUM_IP_TCP|CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP6_TCP) #define ICE_CSUM_UDP (CSUM_IP_UDP|CSUM_IP6_UDP) #define ICE_CSUM_SCTP (CSUM_IP_SCTP|CSUM_IP6_SCTP) #define ICE_CSUM_IP (CSUM_IP|CSUM_IP_TSO) /* List of known RX CSUM offload flags */ #define ICE_RX_CSUM_FLAGS (CSUM_L3_CALC | CSUM_L3_VALID | CSUM_L4_CALC | \ CSUM_L4_VALID | CSUM_L5_CALC | CSUM_L5_VALID | \ CSUM_COALESCED) /* List of interface capabilities supported by ice hardware */ #define ICE_FULL_CAPS \ (IFCAP_TSO4 | IFCAP_TSO6 | \ IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6 | \ IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6 | \ IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO | \ IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | \ IFCAP_VLAN_MTU | IFCAP_JUMBO_MTU | IFCAP_LRO) /* Safe mode disables support for hardware checksums and TSO */ #define ICE_SAFE_CAPS \ (ICE_FULL_CAPS & ~(IFCAP_HWCSUM | IFCAP_TSO | \ IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM)) #define ICE_CAPS(sc) \ (ice_is_bit_set(sc->feat_en, ICE_FEATURE_SAFE_MODE) ? ICE_SAFE_CAPS : ICE_FULL_CAPS) /** * ICE_NVM_ACCESS * @brief Private ioctl command number for NVM access ioctls * * The ioctl command number used by NVM update for accessing the driver for * NVM access commands. */ #define ICE_NVM_ACCESS \ (((((((('E' << 4) + '1') << 4) + 'K') << 4) + 'G') << 4) | 5) /** * ICE_DEBUG_DUMP * @brief Private ioctl command number for retrieving debug dump data * * The ioctl command number used by a userspace tool for accessing the driver for * getting debug dump data from the firmware. */ #define ICE_DEBUG_DUMP \ (((((((('E' << 4) + '1') << 4) + 'K') << 4) + 'G') << 4) | 6) #define ICE_AQ_LEN 1023 #define ICE_MBXQ_LEN 512 #define ICE_SBQ_LEN 512 #define ICE_CTRLQ_WORK_LIMIT 256 #define ICE_DFLT_TRAFFIC_CLASS BIT(0) /* wait up to 50 microseconds for queue state change */ #define ICE_Q_WAIT_RETRY_LIMIT 5 #define ICE_UP_TABLE_TRANSLATE(val, i) \ (((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \ ICE_AQ_VSI_UP_TABLE_UP##i##_M) /* * For now, set this to the hardware maximum. Each function gets a smaller * number assigned to it in hw->func_caps.guar_num_vsi, though there * appears to be no guarantee that is the maximum number that a function * can use. */ #define ICE_MAX_VSI_AVAILABLE 768 /* Maximum size of a single frame (for Tx and Rx) */ #define ICE_MAX_FRAME_SIZE ICE_AQ_SET_MAC_FRAME_SIZE_MAX /* Maximum MTU size */ #define ICE_MAX_MTU (ICE_MAX_FRAME_SIZE - \ ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) /* * Hardware requires that TSO packets have an segment size of at least 64 * bytes. To avoid sending bad frames to the hardware, the driver forces the * MSS for all TSO packets to have a segment size of at least 64 bytes. * * However, if the MTU is reduced below a certain size, then the resulting * larger MSS can result in transmitting segmented frames with a packet size * larger than the MTU. * * Avoid this by preventing the MTU from being lowered below this limit. * Alternative solutions require changing the TCP stack to disable offloading * the segmentation when the requested segment size goes below 64 bytes. */ #define ICE_MIN_MTU 112 /* * The default number of queues reserved for a VF is 4, according to the * AVF Base Mode specification. */ #define ICE_DEFAULT_VF_QUEUES 4 /* * An invalid VSI number to indicate that mirroring should be disabled. */ #define ICE_INVALID_MIRROR_VSI ((u16)-1) /* * The maximum number of RX queues allowed per TC in a VSI. */ #define ICE_MAX_RXQS_PER_TC 256 /* * There are three settings that can be updated independently or * altogether: Link speed, FEC, and Flow Control. These macros allow * the caller to specify which setting(s) to update. */ #define ICE_APPLY_LS BIT(0) #define ICE_APPLY_FEC BIT(1) #define ICE_APPLY_FC BIT(2) #define ICE_APPLY_LS_FEC (ICE_APPLY_LS | ICE_APPLY_FEC) #define ICE_APPLY_LS_FC (ICE_APPLY_LS | ICE_APPLY_FC) #define ICE_APPLY_FEC_FC (ICE_APPLY_FEC | ICE_APPLY_FC) #define ICE_APPLY_LS_FEC_FC (ICE_APPLY_LS_FEC | ICE_APPLY_FC) /* * Mask of valid flags that can be used as an input for the * advertise_speed sysctl. */ #define ICE_SYSCTL_SPEEDS_VALID_RANGE 0xFFF /** * @enum ice_dyn_idx_t * @brief Dynamic Control ITR indexes * * This enum matches hardware bits and is meant to be used by DYN_CTLN * registers and QINT registers or more generally anywhere in the manual * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any * register but instead is a special value meaning "don't update" ITR0/1/2. */ enum ice_dyn_idx_t { ICE_IDX_ITR0 = 0, ICE_IDX_ITR1 = 1, ICE_IDX_ITR2 = 2, ICE_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ }; -/* By convenction ITR0 is used for RX, and ITR1 is used for TX */ +/* By convention ITR0 is used for RX, and ITR1 is used for TX */ #define ICE_RX_ITR ICE_IDX_ITR0 #define ICE_TX_ITR ICE_IDX_ITR1 #define ICE_ITR_MAX 8160 /* Define the default Tx and Rx ITR as 50us (translates to ~20k int/sec max) */ #define ICE_DFLT_TX_ITR 50 #define ICE_DFLT_RX_ITR 50 /* RS FEC register values */ #define ICE_RS_FEC_REG_SHIFT 2 #define ICE_RS_FEC_RECV_ID_SHIFT 4 #define ICE_RS_FEC_CORR_LOW_REG_PORT0 (0x02 << ICE_RS_FEC_REG_SHIFT) #define ICE_RS_FEC_CORR_HIGH_REG_PORT0 (0x03 << ICE_RS_FEC_REG_SHIFT) #define ICE_RS_FEC_UNCORR_LOW_REG_PORT0 (0x04 << ICE_RS_FEC_REG_SHIFT) #define ICE_RS_FEC_UNCORR_HIGH_REG_PORT0 (0x05 << ICE_RS_FEC_REG_SHIFT) #define ICE_RS_FEC_CORR_LOW_REG_PORT1 (0x42 << ICE_RS_FEC_REG_SHIFT) #define ICE_RS_FEC_CORR_HIGH_REG_PORT1 (0x43 << ICE_RS_FEC_REG_SHIFT) #define ICE_RS_FEC_UNCORR_LOW_REG_PORT1 (0x44 << ICE_RS_FEC_REG_SHIFT) #define ICE_RS_FEC_UNCORR_HIGH_REG_PORT1 (0x45 << ICE_RS_FEC_REG_SHIFT) #define ICE_RS_FEC_CORR_LOW_REG_PORT2 (0x4A << ICE_RS_FEC_REG_SHIFT) #define ICE_RS_FEC_CORR_HIGH_REG_PORT2 (0x4B << ICE_RS_FEC_REG_SHIFT) #define ICE_RS_FEC_UNCORR_LOW_REG_PORT2 (0x4C << ICE_RS_FEC_REG_SHIFT) #define ICE_RS_FEC_UNCORR_HIGH_REG_PORT2 (0x4D << ICE_RS_FEC_REG_SHIFT) #define ICE_RS_FEC_CORR_LOW_REG_PORT3 (0x52 << ICE_RS_FEC_REG_SHIFT) #define ICE_RS_FEC_CORR_HIGH_REG_PORT3 (0x53 << ICE_RS_FEC_REG_SHIFT) #define ICE_RS_FEC_UNCORR_LOW_REG_PORT3 (0x54 << ICE_RS_FEC_REG_SHIFT) #define ICE_RS_FEC_UNCORR_HIGH_REG_PORT3 (0x55 << ICE_RS_FEC_REG_SHIFT) #define ICE_RS_FEC_RECEIVER_ID_PCS0 (0x33 << ICE_RS_FEC_RECV_ID_SHIFT) #define ICE_RS_FEC_RECEIVER_ID_PCS1 (0x34 << ICE_RS_FEC_RECV_ID_SHIFT) /** * ice_itr_to_reg - Convert an ITR setting into its register equivalent * @hw: The device HW structure * @itr_setting: the ITR setting to convert * * Based on the hardware ITR granularity, convert an ITR setting into the * correct value to prepare programming to the HW. */ static inline u16 ice_itr_to_reg(struct ice_hw *hw, u16 itr_setting) { return itr_setting / hw->itr_gran; } /** * @enum ice_rx_dtype * @brief DTYPE header split options * * This enum matches the Rx context bits to define whether header split is * enabled or not. */ enum ice_rx_dtype { ICE_RX_DTYPE_NO_SPLIT = 0, ICE_RX_DTYPE_HEADER_SPLIT = 1, ICE_RX_DTYPE_SPLIT_ALWAYS = 2, }; /* Strings used for displaying FEC mode * * Use ice_fec_str() to get these unless these need to be embedded in a * string constant. */ #define ICE_FEC_STRING_AUTO "Auto" #define ICE_FEC_STRING_RS "RS-FEC" #define ICE_FEC_STRING_BASER "FC-FEC/BASE-R" #define ICE_FEC_STRING_NONE "None" #define ICE_FEC_STRING_DIS_AUTO "Auto (w/ No-FEC)" /* Strings used for displaying Flow Control mode * * Use ice_fc_str() to get these unless these need to be embedded in a * string constant. */ #define ICE_FC_STRING_FULL "Full" #define ICE_FC_STRING_TX "Tx" #define ICE_FC_STRING_RX "Rx" #define ICE_FC_STRING_NONE "None" /* * The number of times the ice_handle_i2c_req function will retry reading * I2C data via the Admin Queue before returning EBUSY. */ #define ICE_I2C_MAX_RETRIES 10 /* * The Get Link Status AQ command and other link commands can return * EAGAIN, indicating that the FW Link Management engine is busy. * Define the number of times that the driver should retry sending these * commands and the amount of time it should wait between those retries * (in milliseconds) here. */ #define ICE_LINK_AQ_MAX_RETRIES 10 #define ICE_LINK_RETRY_DELAY 17 /* * The Start LLDP Agent AQ command will fail if it's sent too soon after * the LLDP agent is stopped. The period between the stop and start * commands must currently be at least 2 seconds. */ #define ICE_START_LLDP_RETRY_WAIT (2 * hz) /* * Only certain clusters are valid for certain devices for the FW debug dump * functionality, so define masks of those here. */ #define ICE_FW_DEBUG_DUMP_VALID_CLUSTER_MASK_E810 0x4001AF #define ICE_FW_DEBUG_DUMP_VALID_CLUSTER_MASK_E830 0x1AF struct ice_softc; /** * @enum ice_rx_cso_stat * @brief software checksum offload statistics * * Enumeration of possible checksum offload statistics captured by software * during the Rx path. */ enum ice_rx_cso_stat { ICE_CSO_STAT_RX_IP4_ERR, ICE_CSO_STAT_RX_IP6_ERR, ICE_CSO_STAT_RX_L3_ERR, ICE_CSO_STAT_RX_TCP_ERR, ICE_CSO_STAT_RX_UDP_ERR, ICE_CSO_STAT_RX_SCTP_ERR, ICE_CSO_STAT_RX_L4_ERR, ICE_CSO_STAT_RX_COUNT }; /** * @enum ice_tx_cso_stat * @brief software checksum offload statistics * * Enumeration of possible checksum offload statistics captured by software * during the Tx path. */ enum ice_tx_cso_stat { ICE_CSO_STAT_TX_TCP, ICE_CSO_STAT_TX_UDP, ICE_CSO_STAT_TX_SCTP, ICE_CSO_STAT_TX_IP4, ICE_CSO_STAT_TX_IP6, ICE_CSO_STAT_TX_L3_ERR, ICE_CSO_STAT_TX_L4_ERR, ICE_CSO_STAT_TX_COUNT }; /** * @struct tx_stats * @brief software Tx statistics * * Contains software counted Tx statistics for a single queue */ struct tx_stats { /* Soft Stats */ u64 tx_bytes; u64 tx_packets; u64 mss_too_small; u64 tso; u64 cso[ICE_CSO_STAT_TX_COUNT]; }; /** * @struct rx_stats * @brief software Rx statistics * * Contains software counted Rx statistics for a single queue */ struct rx_stats { /* Soft Stats */ u64 rx_packets; u64 rx_bytes; u64 desc_errs; u64 cso[ICE_CSO_STAT_RX_COUNT]; }; /** * @struct ice_vsi_hw_stats * @brief hardware statistics for a VSI * * Stores statistics that are generated by hardware for a VSI. */ struct ice_vsi_hw_stats { struct ice_eth_stats prev; struct ice_eth_stats cur; bool offsets_loaded; }; /** * @struct ice_pf_hw_stats * @brief hardware statistics for a PF * * Stores statistics that are generated by hardware for each PF. */ struct ice_pf_hw_stats { struct ice_hw_port_stats prev; struct ice_hw_port_stats cur; bool offsets_loaded; }; /** * @struct ice_pf_sw_stats * @brief software statistics for a PF * * Contains software generated statistics relevant to a PF. */ struct ice_pf_sw_stats { /* # of reset events handled, by type */ u32 corer_count; u32 globr_count; u32 empr_count; u32 pfr_count; /* # of detected MDD events for Tx and Rx */ u32 tx_mdd_count; u32 rx_mdd_count; u64 rx_roc_error; /* port oversize packet stats, error_cnt \ from GLV_REPC VSI register + RxOversize */ }; /** * @struct ice_tc_info * @brief Traffic class information for a VSI * * Stores traffic class information used in configuring * a VSI. */ struct ice_tc_info { u16 qoffset; /* Offset in VSI queue space */ u16 qcount_tx; /* TX queues for this Traffic Class */ u16 qcount_rx; /* RX queues */ }; /** * @struct ice_vsi * @brief VSI structure * * Contains data relevant to a single VSI */ struct ice_vsi { /* back pointer to the softc */ struct ice_softc *sc; bool dynamic; /* if true, dynamically allocated */ enum ice_vsi_type type; /* type of this VSI */ u16 idx; /* software index to sc->all_vsi[] */ u16 *tx_qmap; /* Tx VSI to PF queue mapping */ u16 *rx_qmap; /* Rx VSI to PF queue mapping */ enum ice_resmgr_alloc_type qmap_type; struct ice_tx_queue *tx_queues; /* Tx queue array */ struct ice_rx_queue *rx_queues; /* Rx queue array */ int num_tx_queues; int num_rx_queues; int num_vectors; int16_t rx_itr; int16_t tx_itr; /* RSS configuration */ u16 rss_table_size; /* HW RSS table size */ u8 rss_lut_type; /* Used to configure Get/Set RSS LUT AQ call */ int max_frame_size; u16 mbuf_sz; struct ice_aqc_vsi_props info; /* DCB configuration */ u8 num_tcs; /* Total number of enabled TCs */ u16 tc_map; /* bitmap of enabled Traffic Classes */ /* Information for each traffic class */ struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS]; /* context for per-VSI sysctls */ struct sysctl_ctx_list ctx; struct sysctl_oid *vsi_node; /* context for per-txq sysctls */ struct sysctl_ctx_list txqs_ctx; struct sysctl_oid *txqs_node; /* context for per-rxq sysctls */ struct sysctl_ctx_list rxqs_ctx; struct sysctl_oid *rxqs_node; /* VSI-level stats */ struct ice_vsi_hw_stats hw_stats; /* VSI mirroring details */ u16 mirror_src_vsi; u16 rule_mir_ingress; u16 rule_mir_egress; }; /** * @struct ice_debug_dump_cmd * @brief arguments/return value for debug dump ioctl */ struct ice_debug_dump_cmd { u32 offset; /* offset to read/write from table, in bytes */ u16 cluster_id; /* also used to get next cluster id */ u16 table_id; u16 data_size; /* size of data field, in bytes */ u16 reserved1; u32 reserved2; u8 data[]; }; /** * @struct ice_serdes_equalization * @brief serdes equalization info */ struct ice_serdes_equalization { int rx_equalization_pre1; int rx_equalization_pre2; int rx_equalization_post1; int rx_equalization_bflf; int rx_equalization_bfhf; int rx_equalization_drate; int tx_equalization_pre1; int tx_equalization_pre2; int tx_equalization_pre3; int tx_equalization_atten; int tx_equalization_post1; }; /** * @struct ice_fec_stats_to_sysctl * @brief FEC stats register value of port */ struct ice_fec_stats_to_sysctl { u16 fec_corr_cnt_low; u16 fec_corr_cnt_high; u16 fec_uncorr_cnt_low; u16 fec_uncorr_cnt_high; }; #define ICE_MAX_SERDES_LANE_COUNT 4 /** * @struct ice_regdump_to_sysctl * @brief PHY stats of port */ struct ice_regdump_to_sysctl { /* A multilane port can have max 4 serdes */ struct ice_serdes_equalization equalization[ICE_MAX_SERDES_LANE_COUNT]; struct ice_fec_stats_to_sysctl stats; }; /** * @struct ice_port_topology * @brief Port topology from lport i.e. serdes mapping, pcsquad, macport, cage */ struct ice_port_topology { u16 pcs_port; u16 primary_serdes_lane; u16 serdes_lane_count; u16 pcs_quad_select; }; /** * @enum ice_state * @brief Driver state flags * * Used to indicate the status of various driver events. Intended to be * modified only using atomic operations, so that we can use it even in places * which aren't locked. */ enum ice_state { ICE_STATE_CONTROLQ_EVENT_PENDING, ICE_STATE_VFLR_PENDING, ICE_STATE_MDD_PENDING, ICE_STATE_RESET_OICR_RECV, ICE_STATE_RESET_PFR_REQ, ICE_STATE_PREPARED_FOR_RESET, ICE_STATE_SUBIF_NEEDS_REINIT, ICE_STATE_RESET_FAILED, ICE_STATE_DRIVER_INITIALIZED, ICE_STATE_NO_MEDIA, ICE_STATE_RECOVERY_MODE, ICE_STATE_ROLLBACK_MODE, ICE_STATE_LINK_STATUS_REPORTED, ICE_STATE_ATTACHING, ICE_STATE_DETACHING, ICE_STATE_LINK_DEFAULT_OVERRIDE_PENDING, ICE_STATE_LLDP_RX_FLTR_FROM_DRIVER, ICE_STATE_MULTIPLE_TCS, ICE_STATE_DO_FW_DEBUG_DUMP, ICE_STATE_LINK_ACTIVE_ON_DOWN, ICE_STATE_FIRST_INIT_LINK, ICE_STATE_DO_CREATE_MIRR_INTFC, ICE_STATE_DO_DESTROY_MIRR_INTFC, ICE_STATE_PHY_FW_INIT_PENDING, /* This entry must be last */ ICE_STATE_LAST, }; /* Functions for setting and checking driver state. Note the functions take * bit positions, not bitmasks. The atomic_testandset_32 and * atomic_testandclear_32 operations require bit positions, while the * atomic_set_32 and atomic_clear_32 require bitmasks. This can easily lead to * programming error, so we provide wrapper functions to avoid this. */ /** * ice_set_state - Set the specified state * @s: the state bitmap * @bit: the state to set * * Atomically update the state bitmap with the specified bit set. */ static inline void ice_set_state(volatile u32 *s, enum ice_state bit) { /* atomic_set_32 expects a bitmask */ atomic_set_32(s, BIT(bit)); } /** * ice_clear_state - Clear the specified state * @s: the state bitmap * @bit: the state to clear * * Atomically update the state bitmap with the specified bit cleared. */ static inline void ice_clear_state(volatile u32 *s, enum ice_state bit) { /* atomic_clear_32 expects a bitmask */ atomic_clear_32(s, BIT(bit)); } /** * ice_testandset_state - Test and set the specified state * @s: the state bitmap * @bit: the bit to test * * Atomically update the state bitmap, setting the specified bit. Returns the * previous value of the bit. */ static inline u32 ice_testandset_state(volatile u32 *s, enum ice_state bit) { /* atomic_testandset_32 expects a bit position */ return atomic_testandset_32(s, bit); } /** * ice_testandclear_state - Test and clear the specified state * @s: the state bitmap * @bit: the bit to test * * Atomically update the state bitmap, clearing the specified bit. Returns the * previous value of the bit. */ static inline u32 ice_testandclear_state(volatile u32 *s, enum ice_state bit) { /* atomic_testandclear_32 expects a bit position */ return atomic_testandclear_32(s, bit); } /** * ice_test_state - Test the specified state * @s: the state bitmap * @bit: the bit to test * * Return true if the state is set, false otherwise. Use this only if the flow * does not need to update the state. If you must update the state as well, * prefer ice_testandset_state or ice_testandclear_state. */ static inline u32 ice_test_state(volatile u32 *s, enum ice_state bit) { return (*s & BIT(bit)) ? true : false; } /** * @struct ice_str_buf * @brief static length buffer for string returning * * Structure containing a fixed size string buffer, used to implement * numeric->string conversion functions that may want to return non-constant * strings. * * This allows returning a fixed size string that is generated by a conversion * function, and then copied to the used location without needing to use an * explicit local variable passed by reference. */ struct ice_str_buf { char str[ICE_STR_BUF_LEN]; }; struct ice_str_buf _ice_aq_str(enum ice_aq_err aq_err); struct ice_str_buf _ice_status_str(int status); struct ice_str_buf _ice_err_str(int err); struct ice_str_buf _ice_fltr_flag_str(u16 flag); struct ice_str_buf _ice_log_sev_str(u8 log_level); struct ice_str_buf _ice_mdd_tx_tclan_str(u8 event); struct ice_str_buf _ice_mdd_tx_pqm_str(u8 event); struct ice_str_buf _ice_mdd_rx_str(u8 event); struct ice_str_buf _ice_fw_lldp_status(u32 lldp_status); #define ice_aq_str(err) _ice_aq_str(err).str #define ice_status_str(err) _ice_status_str(err).str #define ice_err_str(err) _ice_err_str(err).str #define ice_fltr_flag_str(flag) _ice_fltr_flag_str(flag).str #define ice_mdd_tx_tclan_str(event) _ice_mdd_tx_tclan_str(event).str #define ice_mdd_tx_pqm_str(event) _ice_mdd_tx_pqm_str(event).str #define ice_mdd_rx_str(event) _ice_mdd_rx_str(event).str #define ice_log_sev_str(log_level) _ice_log_sev_str(log_level).str #define ice_fw_lldp_status(lldp_status) _ice_fw_lldp_status(lldp_status).str /** * ice_enable_intr - Enable interrupts for given vector * @hw: the device private HW structure * @vector: the interrupt index in PF space * * In MSI or Legacy interrupt mode, interrupt 0 is the only valid index. */ static inline void ice_enable_intr(struct ice_hw *hw, int vector) { u32 dyn_ctl; /* Use ITR_NONE so that ITR configuration is not changed. */ dyn_ctl = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | (ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S); wr32(hw, GLINT_DYN_CTL(vector), dyn_ctl); } /** * ice_disable_intr - Disable interrupts for given vector * @hw: the device private HW structure * @vector: the interrupt index in PF space * * In MSI or Legacy interrupt mode, interrupt 0 is the only valid index. */ static inline void ice_disable_intr(struct ice_hw *hw, int vector) { u32 dyn_ctl; /* Use ITR_NONE so that ITR configuration is not changed. */ dyn_ctl = ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S; wr32(hw, GLINT_DYN_CTL(vector), dyn_ctl); } /** * ice_is_tx_desc_done - determine if a Tx descriptor is done * @txd: the Tx descriptor to check * * Returns true if hardware is done with a Tx descriptor and software is * capable of re-using it. */ static inline bool ice_is_tx_desc_done(struct ice_tx_desc *txd) { return (((txd->cmd_type_offset_bsz & ICE_TXD_QW1_DTYPE_M) >> ICE_TXD_QW1_DTYPE_S) == ICE_TX_DESC_DTYPE_DESC_DONE); } /** * ice_get_pf_id - Get the PF id from the hardware registers * @hw: the ice hardware structure * * Reads the PF_FUNC_RID register and extracts the function number from it. * Intended to be used in cases where hw->pf_id hasn't yet been assigned by * ice_init_hw. * * @pre this function should be called only after PCI register access has been * setup, and prior to ice_init_hw. After hardware has been initialized, the * cached hw->pf_id value can be used. */ static inline u8 ice_get_pf_id(struct ice_hw *hw) { return (u8)((rd32(hw, PF_FUNC_RID) & PF_FUNC_RID_FUNCTION_NUMBER_M) >> PF_FUNC_RID_FUNCTION_NUMBER_S); } /* Details of how to re-initialize depend on the networking stack */ void ice_request_stack_reinit(struct ice_softc *sc); /* Details of how to check if the network stack is detaching us */ bool ice_driver_is_detaching(struct ice_softc *sc); /* Details of how to setup/teardown a mirror interface */ /** * @brief Create an interface for mirroring */ int ice_create_mirror_interface(struct ice_softc *sc); /** * @brief Destroy created mirroring interface */ void ice_destroy_mirror_interface(struct ice_softc *sc); const char * ice_fw_module_str(enum ice_aqc_fw_logging_mod module); void ice_add_fw_logging_tunables(struct ice_softc *sc, struct sysctl_oid *parent); void ice_handle_fw_log_event(struct ice_softc *sc, struct ice_aq_desc *desc, void *buf); int ice_process_ctrlq(struct ice_softc *sc, enum ice_ctl_q q_type, u16 *pending); int ice_map_bar(device_t dev, struct ice_bar_info *bar, int bar_num); void ice_free_bar(device_t dev, struct ice_bar_info *bar); void ice_set_ctrlq_len(struct ice_hw *hw); void ice_release_vsi(struct ice_vsi *vsi); struct ice_vsi *ice_alloc_vsi(struct ice_softc *sc, enum ice_vsi_type type); void ice_alloc_vsi_qmap(struct ice_vsi *vsi, const int max_tx_queues, const int max_rx_queues); void ice_free_vsi_qmaps(struct ice_vsi *vsi); int ice_initialize_vsi(struct ice_vsi *vsi); void ice_deinit_vsi(struct ice_vsi *vsi); uint64_t ice_aq_speed_to_rate(struct ice_port_info *pi); int ice_get_phy_type_low(uint64_t phy_type_low); int ice_get_phy_type_high(uint64_t phy_type_high); int ice_add_media_types(struct ice_softc *sc, struct ifmedia *media); void ice_configure_rxq_interrupt(struct ice_hw *hw, u16 rxqid, u16 vector, u8 itr_idx); void ice_configure_all_rxq_interrupts(struct ice_vsi *vsi); void ice_configure_txq_interrupt(struct ice_hw *hw, u16 txqid, u16 vector, u8 itr_idx); void ice_configure_all_txq_interrupts(struct ice_vsi *vsi); void ice_flush_rxq_interrupts(struct ice_vsi *vsi); void ice_flush_txq_interrupts(struct ice_vsi *vsi); int ice_cfg_vsi_for_tx(struct ice_vsi *vsi); int ice_cfg_vsi_for_rx(struct ice_vsi *vsi); int ice_control_rx_queue(struct ice_vsi *vsi, u16 qidx, bool enable); int ice_control_all_rx_queues(struct ice_vsi *vsi, bool enable); int ice_cfg_pf_default_mac_filters(struct ice_softc *sc); int ice_rm_pf_default_mac_filters(struct ice_softc *sc); void ice_print_nvm_version(struct ice_softc *sc); void ice_update_vsi_hw_stats(struct ice_vsi *vsi); void ice_reset_vsi_stats(struct ice_vsi *vsi); void ice_update_pf_stats(struct ice_softc *sc); void ice_reset_pf_stats(struct ice_softc *sc); void ice_add_device_sysctls(struct ice_softc *sc); void ice_log_hmc_error(struct ice_hw *hw, device_t dev); void ice_add_sysctls_eth_stats(struct sysctl_ctx_list *ctx, struct sysctl_oid *parent, struct ice_eth_stats *stats); void ice_add_vsi_sysctls(struct ice_vsi *vsi); void ice_add_sysctls_mac_stats(struct sysctl_ctx_list *ctx, struct sysctl_oid *parent, struct ice_softc *sc); void ice_configure_misc_interrupts(struct ice_softc *sc); int ice_sync_multicast_filters(struct ice_softc *sc); int ice_add_vlan_hw_filters(struct ice_vsi *vsi, u16 *vid, u16 length); int ice_add_vlan_hw_filter(struct ice_vsi *vsi, u16 vid); int ice_remove_vlan_hw_filters(struct ice_vsi *vsi, u16 *vid, u16 length); int ice_remove_vlan_hw_filter(struct ice_vsi *vsi, u16 vid); void ice_add_vsi_tunables(struct ice_vsi *vsi, struct sysctl_oid *parent); void ice_del_vsi_sysctl_ctx(struct ice_vsi *vsi); void ice_add_device_tunables(struct ice_softc *sc); int ice_add_vsi_mac_filter(struct ice_vsi *vsi, const u8 *addr); int ice_remove_vsi_mac_filter(struct ice_vsi *vsi, const u8 *addr); int ice_vsi_disable_tx(struct ice_vsi *vsi); void ice_vsi_add_txqs_ctx(struct ice_vsi *vsi); void ice_vsi_add_rxqs_ctx(struct ice_vsi *vsi); void ice_vsi_del_txqs_ctx(struct ice_vsi *vsi); void ice_vsi_del_rxqs_ctx(struct ice_vsi *vsi); void ice_add_txq_sysctls(struct ice_tx_queue *txq); void ice_add_rxq_sysctls(struct ice_rx_queue *rxq); int ice_config_rss(struct ice_vsi *vsi); void ice_clean_all_vsi_rss_cfg(struct ice_softc *sc); int ice_load_pkg_file(struct ice_softc *sc); void ice_log_pkg_init(struct ice_softc *sc, enum ice_ddp_state pkg_status); uint64_t ice_get_ifnet_counter(struct ice_vsi *vsi, ift_counter counter); void ice_save_pci_info(struct ice_hw *hw, device_t dev); int ice_replay_all_vsi_cfg(struct ice_softc *sc); void ice_link_up_msg(struct ice_softc *sc); int ice_update_laa_mac(struct ice_softc *sc); void ice_get_and_print_bus_info(struct ice_softc *sc); const char *ice_fec_str(enum ice_fec_mode mode); const char *ice_fc_str(enum ice_fc_mode mode); const char *ice_fwd_act_str(enum ice_sw_fwd_act_type action); const char *ice_state_to_str(enum ice_state state); int ice_init_link_events(struct ice_softc *sc); void ice_configure_rx_itr(struct ice_vsi *vsi); void ice_configure_tx_itr(struct ice_vsi *vsi); void ice_setup_pf_vsi(struct ice_softc *sc); void ice_handle_mdd_event(struct ice_softc *sc); void ice_init_dcb_setup(struct ice_softc *sc); int ice_send_version(struct ice_softc *sc); int ice_cfg_pf_ethertype_filters(struct ice_softc *sc); void ice_init_link_configuration(struct ice_softc *sc); void ice_init_saved_phy_cfg(struct ice_softc *sc); int ice_apply_saved_phy_cfg(struct ice_softc *sc, u8 settings); void ice_set_link_management_mode(struct ice_softc *sc); int ice_module_event_handler(module_t mod, int what, void *arg); int ice_handle_nvm_access_ioctl(struct ice_softc *sc, struct ifdrv *ifd); int ice_handle_i2c_req(struct ice_softc *sc, struct ifi2creq *req); int ice_read_sff_eeprom(struct ice_softc *sc, u16 dev_addr, u16 offset, u8* data, u16 length); int ice_alloc_intr_tracking(struct ice_softc *sc); void ice_free_intr_tracking(struct ice_softc *sc); void ice_set_default_local_lldp_mib(struct ice_softc *sc); void ice_set_link(struct ice_softc *sc, bool enabled); void ice_add_rx_lldp_filter(struct ice_softc *sc); void ice_init_health_events(struct ice_softc *sc); void ice_cfg_pba_num(struct ice_softc *sc); int ice_handle_debug_dump_ioctl(struct ice_softc *sc, struct ifdrv *ifd); u8 ice_dcb_get_tc_map(const struct ice_dcbx_cfg *dcbcfg); void ice_do_dcb_reconfig(struct ice_softc *sc, bool pending_mib); int ice_setup_vsi_mirroring(struct ice_vsi *vsi); #endif /* _ICE_LIB_H_ */ diff --git a/sys/dev/ice/ice_protocol_type.h b/sys/dev/ice/ice_protocol_type.h index 300d61bfb5d9..b90c25e6c427 100644 --- a/sys/dev/ice/ice_protocol_type.h +++ b/sys/dev/ice/ice_protocol_type.h @@ -1,362 +1,362 @@ /* SPDX-License-Identifier: BSD-3-Clause */ /* Copyright (c) 2024, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * 3. Neither the name of the Intel Corporation nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _ICE_PROTOCOL_TYPE_H_ #define _ICE_PROTOCOL_TYPE_H_ #include "ice_flex_type.h" #define ICE_IPV6_ADDR_LENGTH 16 /* Each recipe can match up to 5 different fields. Fields to match can be meta- * data, values extracted from packet headers, or results from other recipes. * One of the 5 fields is reserved for matching the switch ID. So, up to 4 * recipes can provide intermediate results to another one through chaining, * e.g. recipes 0, 1, 2, and 3 can provide intermediate results to recipe 4. */ #define ICE_NUM_WORDS_RECIPE 4 /* Max recipes that can be chained */ #define ICE_MAX_CHAIN_RECIPE 5 /* 1 word reserved for switch ID from allowed 5 words. * So a recipe can have max 4 words. And you can chain 5 such recipes * together. So maximum words that can be programmed for look up is 5 * 4. */ #define ICE_MAX_CHAIN_WORDS (ICE_NUM_WORDS_RECIPE * ICE_MAX_CHAIN_RECIPE) /* Field vector index corresponding to chaining */ #define ICE_CHAIN_FV_INDEX_START 47 enum ice_protocol_type { ICE_MAC_OFOS = 0, ICE_MAC_IL, ICE_ETYPE_OL, ICE_ETYPE_IL, ICE_VLAN_OFOS, ICE_IPV4_OFOS, ICE_IPV4_IL, ICE_IPV6_OFOS, ICE_IPV6_IL, ICE_TCP_IL, ICE_UDP_OF, ICE_UDP_ILOS, ICE_SCTP_IL, ICE_VXLAN, ICE_GENEVE, ICE_VXLAN_GPE, ICE_NVGRE, ICE_GTP, ICE_GTP_NO_PAY, ICE_PPPOE, ICE_L2TPV3, ICE_PROTOCOL_LAST }; enum ice_sw_tunnel_type { ICE_NON_TUN = 0, ICE_SW_TUN_AND_NON_TUN, ICE_SW_TUN_VXLAN_GPE, ICE_SW_TUN_GENEVE, /* GENEVE matches only non-VLAN pkts */ ICE_SW_TUN_GENEVE_VLAN, /* GENEVE matches both VLAN and non-VLAN pkts */ ICE_SW_TUN_VXLAN, /* VXLAN matches only non-VLAN pkts */ ICE_SW_TUN_VXLAN_VLAN, /* VXLAN matches both VLAN and non-VLAN pkts */ ICE_SW_TUN_NVGRE, ICE_SW_TUN_UDP, /* This means all "UDP" tunnel types: VXLAN-GPE, VXLAN * and GENEVE */ ICE_SW_TUN_GTPU, ICE_SW_TUN_GTPC, ICE_ALL_TUNNELS /* All tunnel types including NVGRE */ }; /* Decoders for ice_prot_id: * - F: First * - I: Inner * - L: Last * - O: Outer * - S: Single */ enum ice_prot_id { ICE_PROT_ID_INVAL = 0, ICE_PROT_MAC_OF_OR_S = 1, ICE_PROT_MAC_O2 = 2, ICE_PROT_MAC_IL = 4, ICE_PROT_MAC_IN_MAC = 7, ICE_PROT_ETYPE_OL = 9, ICE_PROT_ETYPE_IL = 10, ICE_PROT_PAY = 15, ICE_PROT_EVLAN_O = 16, ICE_PROT_VLAN_O = 17, ICE_PROT_VLAN_IF = 18, ICE_PROT_MPLS_OL_MINUS_1 = 27, ICE_PROT_MPLS_OL_OR_OS = 28, ICE_PROT_MPLS_IL = 29, ICE_PROT_IPV4_OF_OR_S = 32, ICE_PROT_IPV4_IL = 33, ICE_PROT_IPV4_IL_IL = 34, ICE_PROT_IPV6_OF_OR_S = 40, ICE_PROT_IPV6_IL = 41, ICE_PROT_IPV6_IL_IL = 42, ICE_PROT_IPV6_NEXT_PROTO = 43, ICE_PROT_IPV6_FRAG = 47, ICE_PROT_TCP_IL = 49, ICE_PROT_UDP_OF = 52, ICE_PROT_UDP_IL_OR_S = 53, ICE_PROT_GRE_OF = 64, ICE_PROT_NSH_F = 84, ICE_PROT_ESP_F = 88, ICE_PROT_ESP_2 = 89, ICE_PROT_SCTP_IL = 96, ICE_PROT_ICMP_IL = 98, ICE_PROT_ICMPV6_IL = 100, ICE_PROT_VRRP_F = 101, ICE_PROT_OSPF = 102, ICE_PROT_ATAOE_OF = 114, ICE_PROT_CTRL_OF = 116, ICE_PROT_LLDP_OF = 117, ICE_PROT_ARP_OF = 118, ICE_PROT_EAPOL_OF = 120, - ICE_PROT_META_ID = 255, /* when offset == metaddata */ + ICE_PROT_META_ID = 255, /* when offset == metadata */ ICE_PROT_INVALID = 255 /* when offset == ICE_FV_OFFSET_INVAL */ }; #define ICE_VNI_OFFSET 12 /* offset of VNI from ICE_PROT_UDP_OF */ #define ICE_NAN_OFFSET 511 #define ICE_MAC_OFOS_HW 1 #define ICE_MAC_IL_HW 4 #define ICE_ETYPE_OL_HW 9 #define ICE_ETYPE_IL_HW 10 #define ICE_VLAN_OF_HW 16 #define ICE_VLAN_OL_HW 17 #define ICE_IPV4_OFOS_HW 32 #define ICE_IPV4_IL_HW 33 #define ICE_IPV6_OFOS_HW 40 #define ICE_IPV6_IL_HW 41 #define ICE_TCP_IL_HW 49 #define ICE_UDP_ILOS_HW 53 #define ICE_SCTP_IL_HW 96 #define ICE_PPPOE_HW 103 #define ICE_L2TPV3_HW 104 /* ICE_UDP_OF is used to identify all 3 tunnel types * VXLAN, GENEVE and VXLAN_GPE. To differentiate further * need to use flags from the field vector */ #define ICE_UDP_OF_HW 52 /* UDP Tunnels */ #define ICE_GRE_OF_HW 64 /* NVGRE */ #define ICE_META_DATA_ID_HW 255 /* this is used for tunnel and VLAN type */ #define ICE_MDID_SIZE 2 #define ICE_TUN_FLAG_MDID 20 #define ICE_TUN_FLAG_MDID_OFF(word) \ (ICE_MDID_SIZE * (ICE_TUN_FLAG_MDID + (word))) #define ICE_TUN_FLAG_MASK 0xFF #define ICE_FROM_NETWORK_FLAG_MASK 0x8 #define ICE_DIR_FLAG_MASK 0x10 #define ICE_TUN_FLAG_IN_VLAN_MASK 0x80 /* VLAN inside tunneled header */ #define ICE_TUN_FLAG_VLAN_MASK 0x01 #define ICE_TUN_FLAG_FV_IND 2 #define ICE_VLAN_FLAG_MDID 20 #define ICE_VLAN_FLAG_MDID_OFF (ICE_MDID_SIZE * ICE_VLAN_FLAG_MDID) #define ICE_PKT_FLAGS_0_TO_15_VLAN_FLAGS_MASK 0xD000 #define ICE_PROTOCOL_MAX_ENTRIES 16 /* Mapping of software defined protocol ID to hardware defined protocol ID */ struct ice_protocol_entry { enum ice_protocol_type type; u8 protocol_id; }; struct ice_ether_hdr { u8 dst_addr[ETH_ALEN]; u8 src_addr[ETH_ALEN]; }; struct ice_ethtype_hdr { __be16 ethtype_id; }; struct ice_ether_vlan_hdr { u8 dst_addr[ETH_ALEN]; u8 src_addr[ETH_ALEN]; __be32 vlan_id; }; struct ice_vlan_hdr { __be16 type; __be16 vlan; }; struct ice_ipv4_hdr { u8 version; u8 tos; __be16 total_length; __be16 id; __be16 frag_off; u8 time_to_live; u8 protocol; __be16 check; __be32 src_addr; __be32 dst_addr; }; struct ice_le_ver_tc_flow { union { struct { u32 flow_label : 20; u32 tc : 8; u32 version : 4; } fld; u32 val; } u; }; struct ice_ipv6_hdr { __be32 be_ver_tc_flow; __be16 payload_len; u8 next_hdr; u8 hop_limit; u8 src_addr[ICE_IPV6_ADDR_LENGTH]; u8 dst_addr[ICE_IPV6_ADDR_LENGTH]; }; struct ice_sctp_hdr { __be16 src_port; __be16 dst_port; __be32 verification_tag; __be32 check; }; struct ice_l4_hdr { __be16 src_port; __be16 dst_port; __be16 len; __be16 check; }; struct ice_udp_tnl_hdr { __be16 field; __be16 proto_type; __be32 vni; /* only use lower 24-bits */ }; struct ice_udp_gtp_hdr { u8 flags; u8 msg_type; __be16 rsrvd_len; __be32 teid; __be16 rsrvd_seq_nbr; u8 rsrvd_n_pdu_nbr; u8 rsrvd_next_ext; u8 rsvrd_ext_len; u8 pdu_type; u8 qfi; u8 rsvrd; }; struct ice_pppoe_hdr { u8 rsrvd_ver_type; u8 rsrvd_code; __be16 session_id; __be16 length; __be16 ppp_prot_id; /* control and data only */ }; struct ice_l2tpv3_sess_hdr { __be32 session_id; __be64 cookie; }; struct ice_nvgre { __be16 flags; __be16 protocol; __be32 tni_flow; }; union ice_prot_hdr { struct ice_ether_hdr eth_hdr; struct ice_ethtype_hdr ethertype; struct ice_vlan_hdr vlan_hdr; struct ice_ipv4_hdr ipv4_hdr; struct ice_ipv6_hdr ipv6_hdr; struct ice_l4_hdr l4_hdr; struct ice_sctp_hdr sctp_hdr; struct ice_udp_tnl_hdr tnl_hdr; struct ice_nvgre nvgre_hdr; struct ice_udp_gtp_hdr gtp_hdr; struct ice_pppoe_hdr pppoe_hdr; struct ice_l2tpv3_sess_hdr l2tpv3_sess_hdr; }; /* This is mapping table entry that maps every word within a given protocol * structure to the real byte offset as per the specification of that * protocol header. * for e.g. dst address is 3 words in ethertype header and corresponding bytes * are 0, 2, 3 in the actual packet header and src address is at 4, 6, 8 */ struct ice_prot_ext_tbl_entry { enum ice_protocol_type prot_type; /* Byte offset into header of given protocol type */ u8 offs[sizeof(union ice_prot_hdr)]; }; /* Extractions to be looked up for a given recipe */ struct ice_prot_lkup_ext { u16 prot_type; u8 n_val_words; /* create a buffer to hold max words per recipe */ u16 field_off[ICE_MAX_CHAIN_WORDS]; u16 field_mask[ICE_MAX_CHAIN_WORDS]; struct ice_fv_word fv_words[ICE_MAX_CHAIN_WORDS]; /* Indicate field offsets that have field vector indices assigned */ ice_declare_bitmap(done, ICE_MAX_CHAIN_WORDS); }; struct ice_pref_recipe_group { u8 n_val_pairs; /* Number of valid pairs */ struct ice_fv_word pairs[ICE_NUM_WORDS_RECIPE]; u16 mask[ICE_NUM_WORDS_RECIPE]; }; struct ice_recp_grp_entry { struct LIST_ENTRY_TYPE l_entry; #define ICE_INVAL_CHAIN_IND 0xFF u16 rid; u8 chain_idx; u16 fv_idx[ICE_NUM_WORDS_RECIPE]; u16 fv_mask[ICE_NUM_WORDS_RECIPE]; struct ice_pref_recipe_group r_group; }; #endif /* _ICE_PROTOCOL_TYPE_H_ */