diff --git a/sys/arm/conf/GENERIC b/sys/arm/conf/GENERIC index 74958061be46..815fd2a1881e 100644 --- a/sys/arm/conf/GENERIC +++ b/sys/arm/conf/GENERIC @@ -1,309 +1,308 @@ # # GENERIC -- Generic(ish) kernel config. # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # https://docs.freebsd.org/en/books/handbook/kernelconfig/#kernelconfig-config # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ ident GENERIC cpu CPU_CORTEXA cpu CPU_MV_PJ4B options SMP_ON_UP machine arm armv7 makeoptions CONF_CFLAGS="-march=armv7a" include "std.armv7" files "../allwinner/files.allwinner" files "../allwinner/files.allwinner_up" files "../allwinner/a10/files.a10" files "../allwinner/a13/files.a13" files "../allwinner/a20/files.a20" files "../allwinner/a31/files.a31" files "../allwinner/a33/files.a33" files "../allwinner/a83t/files.a83t" files "../allwinner/h3/files.h3" files "../broadcom/bcm2835/files.bcm2836" files "../broadcom/bcm2835/files.bcm283x" files "../freescale/imx/files.imx6" files "../mv/files.arm7" files "../nvidia/tegra124/files.tegra124" files "../qemu/files.qemu" files "../rockchip/files.rk32xx" files "../ti/files.ti" files "../ti/am335x/files.am335x" files "../ti/omap4/files.omap4" files "../xilinx/files.zynq7" options SOC_ALLWINNER_A10 options SOC_ALLWINNER_A13 options SOC_ALLWINNER_A20 options SOC_ALLWINNER_A31 options SOC_ALLWINNER_A31S options SOC_ALLWINNER_A33 options SOC_ALLWINNER_A83T options SOC_ALLWINNER_H2PLUS options SOC_ALLWINNER_H3 options SOC_BCM2836 options SOC_BRCM_BCM2837 options SOC_MV_ARMADA38X options SOC_MV_ARMADAXP options SOC_TI_AM335X options SOC_OMAP4 options SCHED_ULE # ULE scheduler options SMP # Enable multiple cores options PLATFORM options LINUX_BOOT_ABI # pseudo devices device clk device phy device hwreset device nvmem device regulator device syscon # CPU frequency control device cpufreq # Interrupt controller device gic device aw_r_intc # PMU support (for CCNT). device pmu # ARM Generic Timer device generic_timer device mpcore_timer # MMC/SD/SDIO Card slot support device dwmmc device sdhci # SD controller device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards # ATA controllers device ahci # AHCI-compatible SATA controllers #device ata # Legacy ATA/SATA controllers # PCI options NEW_PCIB device pci device pci_host_generic # PCI NICs device re # RealTek 8139C+/8169/8169S/8110S # VirtIO device virtio device virtio_mmio device virtio_pci device virtio_blk device vtnet # Console and misc device uart device uart_ns8250 device uart_snps device pl011 device pty device snp device md # Memory "disks" device firmware # firmware assist module device pl310 # PL310 L2 cache controller device psci # I2C support device iicbus device iic device twsi device rsb # Allwinner Reduced Serial Bus device p2wi # Allwinner Push-Pull Two Wire device axp209 # AXP209 Power Management Unit device axp81x # AXP813/818 Power Management Unit device bcm2835_bsc device fsliic # Freescale i2c/iic device icee # AT24Cxxx and compatible EEPROMs device sy8106a # SY8106A Buck Regulator device ti_i2c device am335x_pmic # AM335x Power Management IC (TPC65217) device am335x_rtc # RTC support (power management only) device twl # TI TWLX0X0/TPS659x0 Power Management device twl_vreg # twl voltage regulation device twl_clks # twl external clocks # i2c RTCs device ds1307 # Dallas DS1307 RTC and compatible device ds13rtc # All Dallas/Maxim DS13xx RTCs device ds1672 # Dallas DS1672 RTC device ds3231 # Dallas DS3231 RTC + temperature device nxprtc # NXP RTCs: PCA/PFC212x PCA/PCF85xx device s35390a # Seiko s3539x RTCs # GPIO device dwgpio # Synopsys DesignWare APB GPIO Controller device gpio device gpiobacklight device gpioled device gpioregulator # EVDEV support device evdev # input event device support options EVDEV_SUPPORT # evdev support in legacy drivers device uinput # install /dev/uinput cdev device aw_cir # SPI device spibus device spigen device bcm2835_spi device mv_spi device ti_spi device zy7_qspi # Xilinx Zynq QSPI controller # ADC support device ti_adc # PWM device pwm # Watchdog support # If we don't enable the watchdog driver, the BeagleBone could potentially # reboot automatically because the boot loader might have enabled the # watchdog. device ti_wdt device imxwdt # Watchdog. WARNING: can't be disabled!!! device aw_wdog # Allwinner Watchdog device scbus # SCSI bus (required for ATA/SCSI) device da # Direct Access (disks) device cd # CD device pass # Passthrough device (direct ATA/SCSI access) # USB support options USB_HOST_ALIGN=64 # Align usb buffers to cache line size. device usb device uhci device ohci device ehci device xhci device dwcotg # DWC OTG controller device musb device axe # USB-Ethernet device umass # Disks/Mass storage - Requires scbus and da device uhid # "Human Interface Devices" device ukbd # Allow keyboard like HIDs to control console # Device mode support device usb_template # Control of the gadget # Ethernet device loop device ether device vlan # 802.1Q VLAN support device bpf device mii device mdio device etherswitch device e6000sw # Ethernet NICs that use the common MII bus controller code. # NOTE: Be sure to keep the 'device miibus' line in order to use these NICs! device miibus device awg # 10/100/1000 integrated EMAC controller device cgem # Cadence GEM Gigabit Ethernet device device cpsw # TI Common Platform Ethernet Switch (CPSW) device dwc # 10/100/1000 integrated GMAC controller device emac # 10/100 integrated EMAC controller device ffec # Freescale Fast Ethernet Controller device neta # Marvell 10/100/1000 Network controller device smsc # SMSC LAN91C111 # Sound support device sound # Framebuffer support device vt device kbdmux device ums device videomode -device hdmi device vchiq # IMX6 HDMI Controller device dwc_hdmi device imx6_hdmi device imx6_ipu # TDA19988 HDMI Encoder device tda19988 # Pinmux device fdt_pinctrl # TI Programmable Realtime Unit support device ti_pruss # Mailbox support device ti_mbox # DMA controller device fslsdma device ti_sdma device a10_dmac device a31_dmac # Extensible Firmware Interface options EFI # Marvell Cryptographic Engine and Security Accelerator device cesa device crypto device cryptodev # RTC device imx6_snvs # IMX6 On-chip RTC device aw_rtc # Allwinner On-chip RTC # EFUSE device aw_sid # Allwinner Secure ID EFUSE # Thermal sensors device aw_thermal # Allwinner Thermal Sensor Controller # HID support device hid # Generic HID support # Flattened Device Tree options FDT # Configure using FDT/DTB data makeoptions MODULES_EXTRA+="dtb/allwinner" makeoptions MODULES_EXTRA+="dtb/am335x" makeoptions MODULES_EXTRA+="dtb/imx6" makeoptions MODULES_EXTRA+="dtb/nvidia" makeoptions MODULES_EXTRA+="dtb/omap4" makeoptions MODULES_EXTRA+="dtb/rockchip" makeoptions MODULES_EXTRA+="dtb/rpi" makeoptions MODULES_EXTRA+="dtb/zynq" # SOC-specific modules makeoptions MODULES_EXTRA+="allwinner" makeoptions MODULES_EXTRA+="arm_ti" makeoptions MODULES_EXTRA+="imx" diff --git a/sys/arm/freescale/imx/imx6_hdmi.c b/sys/arm/freescale/imx/imx6_hdmi.c index 28a62a66fd01..f5b4a2ab0ac5 100644 --- a/sys/arm/freescale/imx/imx6_hdmi.c +++ b/sys/arm/freescale/imx/imx6_hdmi.c @@ -1,216 +1,216 @@ /*- * Copyright (c) 2015 Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * HDMI core module */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include "hdmi_if.h" +#include "crtc_if.h" struct imx_hdmi_softc { struct dwc_hdmi_softc base; phandle_t i2c_xref; eventhandler_tag eh_tag; }; static struct ofw_compat_data compat_data[] = { {"fsl,imx6dl-hdmi", 1}, {"fsl,imx6q-hdmi", 1}, {NULL, 0} }; static device_t imx_hdmi_get_i2c_dev(device_t dev) { struct imx_hdmi_softc *sc; sc = device_get_softc(dev); if (sc->i2c_xref == 0) return (NULL); return (OF_device_from_xref(sc->i2c_xref)); } /* * Deferred HDMI init. dwc_hdmi_init() does i2c transfers for DDC/EDID. The imx * i2c devices also use a config_intrhook function to finish their init, because * they require interrupts to perform transfers. There is no way to control * whether the i2c or our hdmi intrhook function runs first. If we go first we * have to continue waiting until after the i2c driver is ready to do transfers * and has registered its phandle. * * This function is used as both a config_intrhook function and after that as an * eventhandler callback function (if necessary), to see if our i2c device is * ready yet. When it is, continue with hdmi init. When first called as an * intrhook function the i2c devices might be ready, in which case we never * register as an eventhandler at all. Otherwise we register to see newbus * attach events, and as each device attaches we check to see whether it was the * i2c device we care about. Once we have our i2c device we unregister from * seeing further attach events. */ static void imx_hdmi_init(void *dev) { struct imx_hdmi_softc *sc; sc = device_get_softc((device_t)dev); if (OF_device_from_xref(sc->i2c_xref) != NULL) { if (sc->eh_tag != NULL) { EVENTHANDLER_DEREGISTER_NOWAIT(device_attach, sc->eh_tag); } dwc_hdmi_init(dev); return; } if (bootverbose) device_printf((device_t)dev, "Waiting for DDC i2c device\n"); if (sc->eh_tag == NULL) { sc->eh_tag = EVENTHANDLER_REGISTER(device_attach, imx_hdmi_init, dev, EVENTHANDLER_PRI_ANY); } } static int imx_hdmi_detach(device_t dev) { struct imx_hdmi_softc *sc; sc = device_get_softc(dev); if (sc->base.sc_mem_res != NULL) bus_release_resource(dev, SYS_RES_MEMORY, sc->base.sc_mem_rid, sc->base.sc_mem_res); return (0); } static int imx_hdmi_attach(device_t dev) { struct imx_hdmi_softc *sc; int err; uint32_t gpr3; phandle_t node, i2c_xref; sc = device_get_softc(dev); sc->base.sc_dev = dev; sc->base.sc_get_i2c_dev = imx_hdmi_get_i2c_dev; err = 0; /* Allocate memory resources. */ sc->base.sc_mem_rid = 0; sc->base.sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->base.sc_mem_rid, RF_ACTIVE); if (sc->base.sc_mem_res == NULL) { device_printf(dev, "Cannot allocate memory resources\n"); err = ENXIO; goto out; } node = ofw_bus_get_node(dev); if (OF_getencprop(node, "ddc-i2c-bus", &i2c_xref, sizeof(i2c_xref)) == -1) sc->i2c_xref = 0; else sc->i2c_xref = i2c_xref; imx_ccm_hdmi_enable(); gpr3 = imx_iomux_gpr_get(IOMUXC_GPR3); gpr3 &= ~(IOMUXC_GPR3_HDMI_MASK); gpr3 |= IOMUXC_GPR3_HDMI_IPU1_DI0; imx_iomux_gpr_set(IOMUXC_GPR3, gpr3); /* Further HDMI init requires interrupts for i2c transfers. */ config_intrhook_oneshot(imx_hdmi_init, dev); return (0); out: imx_hdmi_detach(dev); return (err); } static int imx_hdmi_probe(device_t dev) { if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Freescale i.MX6 HDMI core"); return (BUS_PROBE_DEFAULT); } static device_method_t imx_hdmi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, imx_hdmi_probe), DEVMETHOD(device_attach, imx_hdmi_attach), DEVMETHOD(device_detach, imx_hdmi_detach), - /* HDMI methods */ - DEVMETHOD(hdmi_get_edid, dwc_hdmi_get_edid), - DEVMETHOD(hdmi_set_videomode, dwc_hdmi_set_videomode), + /* CRTC methods */ + DEVMETHOD(crtc_get_edid, dwc_hdmi_get_edid), + DEVMETHOD(crtc_set_videomode, dwc_hdmi_set_videomode), DEVMETHOD_END }; static driver_t imx_hdmi_driver = { "hdmi", imx_hdmi_methods, sizeof(struct imx_hdmi_softc) }; DRIVER_MODULE(hdmi, simplebus, imx_hdmi_driver, 0, 0); diff --git a/sys/arm/freescale/imx/imx6_ipu.c b/sys/arm/freescale/imx/imx6_ipu.c index be9487620a06..02bfbe8e0049 100644 --- a/sys/arm/freescale/imx/imx6_ipu.c +++ b/sys/arm/freescale/imx/imx6_ipu.c @@ -1,1270 +1,1270 @@ /*- * Copyright 2015 Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "fb_if.h" -#include "hdmi_if.h" +#include "crtc_if.h" static int have_ipu = 0; #define MODE_HBP(mode) ((mode)->htotal - (mode)->hsync_end) #define MODE_HFP(mode) ((mode)->hsync_start - (mode)->hdisplay) #define MODE_HSW(mode) ((mode)->hsync_end - (mode)->hsync_start) #define MODE_VBP(mode) ((mode)->vtotal - (mode)->vsync_end) #define MODE_VFP(mode) ((mode)->vsync_start - (mode)->vdisplay) #define MODE_VSW(mode) ((mode)->vsync_end - (mode)->vsync_start) #define MODE_BPP 16 #define MODE_PIXEL_CLOCK_INVERT 1 #define DMA_CHANNEL 23 #define DC_CHAN5 5 #define DI_PORT 0 #define IPU_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) #define IPU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) #define IPU_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ device_get_nameunit(_sc->sc_dev), "ipu", MTX_DEF) #define IPU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) #define IPU_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, (reg)) #define IPU_WRITE4(_sc, reg, value) \ bus_write_4((_sc)->sc_mem_res, (reg), (value)) #define CPMEM_BASE 0x300000 #define DC_TEMPL_BASE 0x380000 /* Microcode */ /* Word 1 */ #define TEMPLATE_SYNC(v) ((v) << 0) #define TEMPLATE_GLUELOGIC(v) ((v) << 4) #define TEMPLATE_MAPPING(v) ((v) << 15) #define TEMPLATE_WAVEFORM(v) ((v) << 11) #define GLUELOGIC_KEEP_ASSERTED (1 << 3) #define GLUELOGIC_KEEP_NEGATED (1 << 2) /* Word 2 */ #define TEMPLATE_OPCODE(v) ((v) << 4) #define OPCODE_WROD 0x18 #define TEMPLATE_STOP (1 << 9) #define IPU_CONF 0x200000 #define IPU_CONF_DMFC_EN (1 << 10) #define IPU_CONF_DC_EN (1 << 9) #define IPU_CONF_DI1_EN (1 << 7) #define IPU_CONF_DI0_EN (1 << 6) #define IPU_CONF_DP_EN (1 << 5) #define IPU_DISP_GEN 0x2000C4 #define DISP_GEN_DI1_CNTR_RELEASE (1 << 25) #define DISP_GEN_DI0_CNTR_RELEASE (1 << 24) #define DISP_GEN_MCU_MAX_BURST_STOP (1 << 22) #define DISP_GEN_MCU_T_SHIFT 18 #define IPU_MEM_RST 0x2000DC #define IPU_MEM_RST_START (1 << 31) #define IPU_MEM_RST_ALL 0x807FFFFF #define IPU_CH_DB_MODE_SEL_0 0x200150 #define IPU_CH_DB_MODE_SEL_1 0x200154 #define IPU_CUR_BUF_0 0x20023C #define IPU_CUR_BUF_1 0x200240 #define IPU_IDMAC_CH_EN_1 0x208004 #define IPU_IDMAC_CH_EN_2 0x208008 #define IPU_IDMAC_CH_PRI_1 0x208014 #define IPU_IDMAC_CH_PRI_2 0x208018 #define IPU_DI0_GENERAL 0x240000 #define DI_CLOCK_EXTERNAL (1 << 20) #define DI_GENERAL_POL_CLK (1 << 17) #define DI_GENERAL_POLARITY_3 (1 << 2) #define DI_GENERAL_POLARITY_2 (1 << 1) #define IPU_DI0_BS_CLKGEN0 0x240004 #define DI_BS_CLKGEN0(_int, _frac) (((_int) << 4) | (_frac)) #define IPU_DI0_BS_CLKGEN1 0x240008 #define DI_BS_CLKGEN1_DOWN(_int, _frac) ((((_int) << 1) | (_frac)) << 16) #define IPU_DI0_SW_GEN0_1 0x24000C #define DI_RUN_VALUE_M1(v) ((v) << 19) #define DI_RUN_RESOLUTION(v) ((v) << 16) #define DI_OFFSET_VALUE(v) ((v) << 3) #define IPU_DI0_SW_GEN1_1 0x240030 #define DI_CNT_POLARITY_GEN_EN(v) ((v) << 29) #define DI_CNT_AUTO_RELOAD (1 << 28) #define DI_CNT_CLR_SEL(v) ((v) << 25) #define DI_CNT_DOWN(v) ((v) << 16) #define DI_CNT_POLARITY_TRIGGER_SEL(v) ((v) << 12) #define DI_CNT_POLARITY_CLR_SEL(v) ((v) << 9) #define IPU_DI0_SYNC_AS_GEN 0x240054 #define SYNC_AS_GEN_VSYNC_SEL(v) ((v) << 13) #define SYNC_AS_GEN_SYNC_START(v) ((v) << 0) #define IPU_DI0_DW_GEN_0 0x240058 #define DW_GEN_DI_ACCESS_SIZE(v) ((v) << 24) #define DW_GEN_DI_COMPONENT_SIZE(v) ((v) << 16) #define DW_GEN_DI_SET_MASK 3 #define DW_GEN_DI_PIN_15_SET(v) ((v) << 8) #define IPU_DI0_DW_SET3_0 0x240118 #define DW_SET_DATA_CNT_DOWN(v) ((v) << 16) #define DW_SET_DATA_CNT_UP(v) ((v) << 0) #define IPU_DI0_STP_REP 0x240148 #define IPU_DI0_POL 0x240164 #define DI_POL_DRDY_POLARITY_15 (1 << 4) #define IPU_DI0_SCR_CONF 0x240170 #define IPU_DI1_GENERAL 0x248000 #define IPU_DI1_BS_CLKGEN0 0x248004 #define IPU_DI1_BS_CLKGEN1 0x248008 #define IPU_DI1_SW_GEN0_1 0x24800C #define IPU_DI1_SW_GEN1_1 0x248030 #define IPU_DI1_SYNC_AS_GEN 0x248054 #define IPU_DI1_DW_GEN_0 0x248058 #define IPU_DI1_POL 0x248164 #define IPU_DI1_DW_SET3_0 0x248118 #define IPU_DI1_STP_REP 0x248148 #define IPU_DI1_SCR_CONF 0x248170 #define DMFC_RD_CHAN 0x260000 #define DMFC_WR_CHAN 0x260004 #define DMFC_WR_CHAN_BURST_SIZE_32 (0 << 6) #define DMFC_WR_CHAN_BURST_SIZE_16 (1 << 6) #define DMFC_WR_CHAN_BURST_SIZE_8 (2 << 6) #define DMFC_WR_CHAN_BURST_SIZE_4 (3 << 6) #define DMFC_WR_CHAN_BURST_SIZE_4 (3 << 6) #define DMFC_WR_CHAN_FIFO_SIZE_128 (2 << 3) #define DMFC_WR_CHAN_DEF 0x260008 #define DMFC_WR_CHAN_DEF_WM_CLR_2C(v) ((v) << 29) #define DMFC_WR_CHAN_DEF_WM_CLR_1C(v) ((v) << 21) #define DMFC_WR_CHAN_DEF_WM_CLR_2(v) ((v) << 13) #define DMFC_WR_CHAN_DEF_WM_CLR_1(v) ((v) << 5) #define DMFC_WR_CHAN_DEF_WM_SET_1(v) ((v) << 2) #define DMFC_WR_CHAN_DEF_WM_EN_1 (1 << 1) #define DMFC_DP_CHAN 0x26000C #define DMFC_DP_CHAN_BURST_SIZE_8 2 #define DMFC_DP_CHAN_FIFO_SIZE_256 1 #define DMFC_DP_CHAN_FIFO_SIZE_128 2 #define DMFC_DP_CHAN_BURST_SIZE_5F(v) ((v) << 14) #define DMFC_DP_CHAN_FIFO_SIZE_5F(v) ((v) << 11) #define DMFC_DP_CHAN_ST_ADDR_SIZE_5F(v) ((v) << 8) #define DMFC_DP_CHAN_BURST_SIZE_5B(v) ((v) << 6) #define DMFC_DP_CHAN_FIFO_SIZE_5B(v) ((v) << 3) #define DMFC_DP_CHAN_ST_ADDR_SIZE_5B(v) ((v) << 0) #define DMFC_DP_CHAN_DEF 0x260010 #define DMFC_DP_CHAN_DEF_WM_CLR_6F(v) ((v) << 29) #define DMFC_DP_CHAN_DEF_WM_CLR_6B(v) ((v) << 21) #define DMFC_DP_CHAN_DEF_WM_CLR_5F(v) ((v) << 13) #define DMFC_DP_CHAN_DEF_WM_SET_5F(v) ((v) << 10) #define DMFC_DP_CHAN_DEF_WM_EN_5F (1 << 9) #define DMFC_DP_CHAN_DEF_WM_CLR_5B(v) ((v) << 5) #define DMFC_DP_CHAN_DEF_WM_SET_5B(v) ((v) << 2) #define DMFC_DP_CHAN_DEF_WM_EN_5B (1 << 1) #define DMFC_GENERAL_1 0x260014 #define DMFC_GENERAL_1_WAIT4EOT_5B (1 << 20) #define DMFC_IC_CTRL 0x26001C #define DMFC_IC_CTRL_DISABLED 0x2 #define DC_WRITE_CH_CONF_1 0x0025801C #define WRITE_CH_CONF_PROG_CHAN_TYP_MASK (7 << 5) #define WRITE_CH_CONF_PROG_CHAN_NORMAL (4 << 5) #define DC_WRITE_CH_ADDR_1 0x00258020 #define DC_WRITE_CH_CONF_5 0x0025805C #define WRITE_CH_CONF_PROG_DISP_ID(v) ((v) << 3) #define WRITE_CH_CONF_PROG_DI_ID(v) ((v) << 2) #define WRITE_CH_CONF_PROG_W_SIZE(v) (v) #define DC_WRITE_CH_ADDR_5 0x00258060 #define DC_RL0_CH_5 0x00258064 #define DC_GEN 0x002580D4 #define DC_GEN_SYNC_PRIORITY (1 << 7) #define DC_GEN_ASYNC (0 << 1) #define DC_GEN_SYNC (2 << 1) #define DC_DISP_CONF2(di) (0x002580E8 + (di) * 4) #define DC_MAP_CONF_0 0x00258108 #define DC_MAP_CONF_15 0x00258144 #define DC_MAP_CONF_VAL(map) (DC_MAP_CONF_15 + ((map) / 2) * sizeof(uint32_t)) #define MAP_CONF_VAL_MASK 0xffff #define DC_MAP_CONF_PTR(ptr) (DC_MAP_CONF_0 + ((ptr) / 2) * sizeof(uint32_t)) #define MAP_CONF_PTR_MASK 0x1f #define DI_COUNTER_INT_HSYNC 1 #define DI_COUNTER_HSYNC 2 #define DI_COUNTER_VSYNC 3 #define DI_COUNTER_AD_0 4 #define DI_COUNTER_AD_1 5 #define DI_SYNC_NONE 0 #define DI_SYNC_CLK 1 #define DI_SYNC_COUNTER(c) ((c) + 1) struct ipu_cpmem_word { uint32_t data[5]; uint32_t padding[3]; }; struct ipu_cpmem_ch_param { struct ipu_cpmem_word word[2]; }; #define CH_PARAM_RESET(param) memset(param, 0, sizeof(*param)) #define IPU_READ_CH_PARAM(_sc, ch, param) bus_read_region_4( \ (_sc)->sc_mem_res, CPMEM_BASE + ch * (sizeof(*param)),\ (uint32_t*)param, sizeof(*param) / 4) #define IPU_WRITE_CH_PARAM(_sc, ch, param) bus_write_region_4( \ (_sc)->sc_mem_res, CPMEM_BASE + ch * (sizeof(*param)),\ (uint32_t*)param, sizeof(*param) / 4) #define CH_PARAM_SET_FW(param, v) ipu_ch_param_set_value((param), \ 0, 125, 13, (v)) #define CH_PARAM_SET_FH(param, v) ipu_ch_param_set_value((param), \ 0, 138, 12, (v)) #define CH_PARAM_SET_SLY(param, v) ipu_ch_param_set_value((param), \ 1, 102, 14, (v)) #define CH_PARAM_SET_EBA0(param, v) ipu_ch_param_set_value((param), \ 1, 0, 29, (v)) #define CH_PARAM_SET_EBA1(param, v) ipu_ch_param_set_value((param), \ 1, 29, 29, (v)) #define CH_PARAM_SET_BPP(param, v) ipu_ch_param_set_value((param), \ 0, 107, 3, (v)) #define CH_PARAM_SET_PFS(param, v) ipu_ch_param_set_value((param), \ 1, 85, 4, (v)) #define CH_PARAM_SET_NPB(param, v) ipu_ch_param_set_value((param), \ 1, 78, 7, (v)) #define CH_PARAM_SET_UBO(param, v) ipu_ch_param_set_value((param), \ 0, 46, 22, (v)) #define CH_PARAM_SET_VBO(param, v) ipu_ch_param_set_value((param), \ 0, 68, 22, (v)) #define CH_PARAM_SET_RED_WIDTH(param, v) ipu_ch_param_set_value((param), \ 1, 116, 3, (v)) #define CH_PARAM_SET_RED_OFFSET(param, v) ipu_ch_param_set_value((param), \ 1, 128, 5, (v)) #define CH_PARAM_SET_GREEN_WIDTH(param, v) ipu_ch_param_set_value((param), \ 1, 119, 3, (v)) #define CH_PARAM_SET_GREEN_OFFSET(param, v) ipu_ch_param_set_value((param), \ 1, 133, 5, (v)) #define CH_PARAM_SET_BLUE_WIDTH(param, v) ipu_ch_param_set_value((param), \ 1, 122, 3, (v)) #define CH_PARAM_SET_BLUE_OFFSET(param, v) ipu_ch_param_set_value((param), \ 1, 138, 5, (v)) #define CH_PARAM_SET_ALPHA_WIDTH(param, v) ipu_ch_param_set_value((param), \ 1, 125, 3, (v)) #define CH_PARAM_SET_ALPHA_OFFSET(param, v) ipu_ch_param_set_value((param), \ 1, 143, 5, (v)) #define CH_PARAM_GET_FW(param) ipu_ch_param_get_value((param), \ 0, 125, 13) #define CH_PARAM_GET_FH(param) ipu_ch_param_get_value((param), \ 0, 138, 12) #define CH_PARAM_GET_SLY(param) ipu_ch_param_get_value((param), \ 1, 102, 14) #define CH_PARAM_GET_EBA0(param) ipu_ch_param_get_value((param), \ 1, 0, 29) #define CH_PARAM_GET_EBA1(param) ipu_ch_param_get_value((param), \ 1, 29, 29) #define CH_PARAM_GET_BPP(param) ipu_ch_param_get_value((param), \ 0, 107, 3) #define CH_PARAM_GET_PFS(param) ipu_ch_param_get_value((param), \ 1, 85, 4) #define CH_PARAM_GET_NPB(param) ipu_ch_param_get_value((param), \ 1, 78, 7) #define CH_PARAM_GET_UBO(param) ipu_ch_param_get_value((param), \ 0, 46, 22) #define CH_PARAM_GET_VBO(param) ipu_ch_param_get_value((param), \ 0, 68, 22) #define CH_PARAM_GET_RED_WIDTH(param) ipu_ch_param_get_value((param), \ 1, 116, 3) #define CH_PARAM_GET_RED_OFFSET(param) ipu_ch_param_get_value((param), \ 1, 128, 5) #define CH_PARAM_GET_GREEN_WIDTH(param) ipu_ch_param_get_value((param), \ 1, 119, 3) #define CH_PARAM_GET_GREEN_OFFSET(param) ipu_ch_param_get_value((param), \ 1, 133, 5) #define CH_PARAM_GET_BLUE_WIDTH(param) ipu_ch_param_get_value((param), \ 1, 122, 3) #define CH_PARAM_GET_BLUE_OFFSET(param) ipu_ch_param_get_value((param), \ 1, 138, 5) #define CH_PARAM_GET_ALPHA_WIDTH(param) ipu_ch_param_get_value((param), \ 1, 125, 3) #define CH_PARAM_GET_ALPHA_OFFSET(param) ipu_ch_param_get_value((param), \ 1, 143, 5) #define IPU_PIX_FORMAT_BPP_32 0 #define IPU_PIX_FORMAT_BPP_24 1 #define IPU_PIX_FORMAT_BPP_18 2 #define IPU_PIX_FORMAT_BPP_16 3 #define IPU_PIX_FORMAT_BPP_12 4 #define IPU_PIX_FORMAT_BPP_8 5 #define IPU_PIX_FORMAT_BPP_ #define IPU_PIX_FORMAT_RGB 7 enum dc_event_t { DC_EVENT_NF = 0, DC_EVENT_NL, DC_EVENT_EOF, DC_EVENT_NFIELD, DC_EVENT_EOL, DC_EVENT_EOFIELD, DC_EVENT_NEW_ADDR, DC_EVENT_NEW_CHAN, DC_EVENT_NEW_DATA }; struct ipu_softc { device_t sc_dev; struct resource *sc_mem_res; int sc_mem_rid; struct resource *sc_irq_res; int sc_irq_rid; void *sc_intr_hl; struct mtx sc_mtx; struct fb_info sc_fb_info; const struct videomode *sc_mode; /* Framebuffer */ bus_dma_tag_t sc_dma_tag; bus_dmamap_t sc_dma_map; size_t sc_fb_size; bus_addr_t sc_fb_phys; uint8_t *sc_fb_base; /* HDMI */ eventhandler_tag sc_hdmi_evh; }; static void ipu_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) { bus_addr_t *addr; if (err) return; addr = (bus_addr_t*)arg; *addr = segs[0].ds_addr; } static void ipu_ch_param_set_value(struct ipu_cpmem_ch_param *param, int word, unsigned int offset, int len, uint32_t value) { uint32_t datapos, bitpos, mask; uint32_t data, data2; KASSERT((len <= 32), ("%s: field len is more than 32", __func__)); datapos = offset / 32; bitpos = offset % 32; mask = (1 << len) - 1; data = param->word[word].data[datapos]; data &= ~(mask << bitpos); data |= (value << bitpos); param->word[word].data[datapos] = data; if ((bitpos + len) > 32) { len = bitpos + len - 32; mask = (1UL << len) - 1; data2 = param->word[word].data[datapos + 1]; data2 &= mask; data2 |= (value >> (32 - bitpos)); param->word[word].data[datapos + 1] = data2; } } #ifdef DEBUG static uint32_t ipu_ch_param_get_value(struct ipu_cpmem_ch_param *param, int word, unsigned int offset, int len) { uint32_t datapos, bitpos, mask; uint32_t data, data2; KASSERT((len <= 32), ("%s: field len is more than 32", __func__)); datapos = offset / 32; bitpos = offset % 32; mask = (1UL << len) - 1; data = param->word[word].data[datapos]; data = data >> bitpos; data &= mask; if ((bitpos + len) > 32) { len = bitpos + len - 32; mask = (1UL << len) - 1; data2 = param->word[word].data[datapos + 1]; data2 &= mask; data |= (data2 << (32 - bitpos)); } return (data); } static void ipu_print_channel(struct ipu_cpmem_ch_param *param) { int offset0[] = {0, 10, 19, 32, 44, 45, 46, 68, 90, 94, 95, 113, 114, 117, 119, 120, 121, 122, 123, 124, 125, 138, 150, 151, -1}; int offset1[] = {0, 29, 58, 78, 85, 89, 90, 93, 95, 102, 116, 119, 122, 125, 128, 133, 138, 143, 148, 149, 150, -1}; printf("WORD0: %08x %08x %08x %08x %08x\n", param->word[0].data[0], param->word[0].data[1], param->word[0].data[2], param->word[0].data[3], param->word[0].data[4]); printf("WORD1: %08x %08x %08x %08x %08x\n", param->word[1].data[0], param->word[1].data[1], param->word[1].data[2], param->word[1].data[3], param->word[1].data[4]); for (int i = 0; offset0[i + 1] != -1; i++) { int len = offset0[i + 1] - offset0[i]; printf("W0[%d:%d] = %d\n", offset0[i], offset0[i] + len - 1, ipu_ch_param_get_value(param, 0, offset0[i], len) ); } for (int i = 0; offset1[i + 1] != -1; i++) { int len = offset1[i + 1] - offset1[i]; printf("W1[%d:%d] = %d\n", offset1[i], offset1[i] + len - 1, ipu_ch_param_get_value(param, 1, offset1[i], len) ); } printf("FW: %d\n", CH_PARAM_GET_FW(param)); printf("FH: %d\n", CH_PARAM_GET_FH(param)); printf("SLY: %d\n", CH_PARAM_GET_SLY(param)); printf("EBA0: 0x%08x\n", CH_PARAM_GET_EBA0(param)); printf("EBA1: 0x%08x\n", CH_PARAM_GET_EBA1(param)); printf("BPP: %d\n", CH_PARAM_GET_BPP(param)); printf("PFS: %d\n", CH_PARAM_GET_PFS(param)); printf("NPB: %d\n", CH_PARAM_GET_NPB(param)); printf("UBO: %d\n", CH_PARAM_GET_UBO(param)); printf("VBO: %d\n", CH_PARAM_GET_VBO(param)); printf("RED: %d bits @%d\n", CH_PARAM_GET_RED_WIDTH(param) + 1, CH_PARAM_GET_RED_OFFSET(param)); printf("GREEN: %d bits @%d\n", CH_PARAM_GET_GREEN_WIDTH(param) + 1, CH_PARAM_GET_GREEN_OFFSET(param)); printf("BLUE: %d bits @%d\n", CH_PARAM_GET_BLUE_WIDTH(param) + 1, CH_PARAM_GET_BLUE_OFFSET(param)); printf("ALPHA: %d bits @%d\n", CH_PARAM_GET_ALPHA_WIDTH(param) + 1, CH_PARAM_GET_ALPHA_OFFSET(param)); } #endif static void ipu_di_enable(struct ipu_softc *sc, int di) { uint32_t flag, reg; flag = di ? DISP_GEN_DI1_CNTR_RELEASE : DISP_GEN_DI0_CNTR_RELEASE; reg = IPU_READ4(sc, IPU_DISP_GEN); reg |= flag; IPU_WRITE4(sc, IPU_DISP_GEN, reg); } static void ipu_config_wave_gen_0(struct ipu_softc *sc, int di, int wave_gen, int run_value, int run_res, int offset_value, int offset_res) { uint32_t addr, reg; addr = (di ? IPU_DI1_SW_GEN0_1 : IPU_DI0_SW_GEN0_1) + (wave_gen - 1) * sizeof(uint32_t); reg = DI_RUN_VALUE_M1(run_value) | DI_RUN_RESOLUTION(run_res) | DI_OFFSET_VALUE(offset_value) | offset_res; IPU_WRITE4(sc, addr, reg); } static void ipu_config_wave_gen_1(struct ipu_softc *sc, int di, int wave_gen, int repeat_count, int cnt_clr_src, int cnt_polarity_gen_en, int cnt_polarity_clr_src, int cnt_polarity_trigger_src, int cnt_up, int cnt_down) { uint32_t addr, reg; addr = (di ? IPU_DI1_SW_GEN1_1 : IPU_DI0_SW_GEN1_1) + (wave_gen - 1) * sizeof(uint32_t); reg = DI_CNT_POLARITY_GEN_EN(cnt_polarity_gen_en) | DI_CNT_CLR_SEL(cnt_clr_src) | DI_CNT_POLARITY_TRIGGER_SEL(cnt_polarity_trigger_src) | DI_CNT_POLARITY_CLR_SEL(cnt_polarity_clr_src); reg |= DI_CNT_DOWN(cnt_down) | cnt_up; if (repeat_count == 0) reg |= DI_CNT_AUTO_RELOAD; IPU_WRITE4(sc, addr, reg); addr = (di ? IPU_DI1_STP_REP : IPU_DI0_STP_REP) + (wave_gen - 1) / 2 * sizeof(uint32_t); reg = IPU_READ4(sc, addr); if (wave_gen % 2) { reg &= ~(0xffff); reg |= repeat_count; } else { reg &= ~(0xffff << 16); reg |= (repeat_count << 16); } IPU_WRITE4(sc, addr, reg); } static void ipu_reset_wave_gen(struct ipu_softc *sc, int di, int wave_gen) { uint32_t addr, reg; addr = (di ? IPU_DI1_SW_GEN0_1 : IPU_DI0_SW_GEN0_1) + (wave_gen - 1) * sizeof(uint32_t); IPU_WRITE4(sc, addr, 0); addr = (di ? IPU_DI1_SW_GEN1_1 : IPU_DI0_SW_GEN1_1) + (wave_gen - 1) * sizeof(uint32_t); IPU_WRITE4(sc, addr, 0); addr = (di ? IPU_DI1_STP_REP : IPU_DI0_STP_REP) + (wave_gen - 1) / 2 * sizeof(uint32_t); reg = IPU_READ4(sc, addr); if (wave_gen % 2) reg &= ~(0xffff); else reg &= ~(0xffff << 16); IPU_WRITE4(sc, addr, reg); } static void ipu_init_microcode_template(struct ipu_softc *sc, int di, int map) { uint32_t addr; uint32_t w1, w2; int i, word; int glue; word = di ? 2 : 5; for (i = 0; i < 3; i++) { if (i == 0) glue = GLUELOGIC_KEEP_ASSERTED; else if (i == 1) glue = GLUELOGIC_KEEP_NEGATED; else if (i == 2) glue = 0; w1 = TEMPLATE_SYNC(5) | TEMPLATE_GLUELOGIC(glue) | TEMPLATE_WAVEFORM(1) | /* wave unit 0 */ TEMPLATE_MAPPING(map + 1); /* operand is zero */ /* Write data to DI and Hold data in register */ w2 = TEMPLATE_OPCODE(OPCODE_WROD) | TEMPLATE_STOP; addr = DC_TEMPL_BASE + (word + i) * 2 * sizeof(uint32_t); IPU_WRITE4(sc, addr, w1); IPU_WRITE4(sc, addr + sizeof(uint32_t), w2); } } static uint32_t ipu_calc_divisor(uint32_t reference, uint32_t freq) { uint32_t div, i; uint32_t delta, min_delta; min_delta = freq; div = 255; for (i = 1; i < 255; i++) { delta = abs(reference/i - freq); if (delta < min_delta) { div = i; min_delta = delta; } } return (div); } static void ipu_config_timing(struct ipu_softc *sc, int di) { uint32_t div; uint32_t di_scr_conf; uint32_t gen_offset, gen; uint32_t as_gen_offset, as_gen; uint32_t dw_gen_offset, dw_gen; uint32_t dw_set_offset, dw_set; uint32_t bs_clkgen_offset; int map; uint32_t freq; freq = sc->sc_mode->dot_clock * 1000; div = ipu_calc_divisor(imx_ccm_ipu_hz(), freq); map = 0; bs_clkgen_offset = di ? IPU_DI1_BS_CLKGEN0 : IPU_DI0_BS_CLKGEN0; IPU_WRITE4(sc, bs_clkgen_offset, DI_BS_CLKGEN0(div, 0)); /* half of the divider */ IPU_WRITE4(sc, bs_clkgen_offset + 4, DI_BS_CLKGEN1_DOWN(div / 2, div % 2)); /* Setup wave generator */ dw_gen_offset = di ? IPU_DI1_DW_GEN_0 : IPU_DI0_DW_GEN_0; dw_gen = DW_GEN_DI_ACCESS_SIZE(div - 1) | DW_GEN_DI_COMPONENT_SIZE(div - 1); dw_gen &= ~DW_GEN_DI_PIN_15_SET(DW_GEN_DI_SET_MASK); dw_gen |= DW_GEN_DI_PIN_15_SET(3); /* set 3*/ IPU_WRITE4(sc, dw_gen_offset, dw_gen); dw_set_offset = di ? IPU_DI1_DW_SET3_0 : IPU_DI0_DW_SET3_0; dw_set = DW_SET_DATA_CNT_DOWN(div * 2) | DW_SET_DATA_CNT_UP(0); IPU_WRITE4(sc, dw_set_offset, dw_set); /* DI_COUNTER_INT_HSYNC */ ipu_config_wave_gen_0(sc, di, DI_COUNTER_INT_HSYNC, sc->sc_mode->htotal - 1, DI_SYNC_CLK, 0, DI_SYNC_NONE); ipu_config_wave_gen_1(sc, di, DI_COUNTER_INT_HSYNC, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); /* DI_COUNTER_HSYNC */ ipu_config_wave_gen_0(sc, di, DI_COUNTER_HSYNC, sc->sc_mode->htotal - 1, DI_SYNC_CLK, 0, DI_SYNC_CLK); ipu_config_wave_gen_1(sc, di, DI_COUNTER_HSYNC, 0, DI_SYNC_NONE, 1, DI_SYNC_NONE, DI_SYNC_CLK, 0, MODE_HSW(sc->sc_mode) * 2); /* DI_COUNTER_VSYNC */ ipu_config_wave_gen_0(sc, di, DI_COUNTER_VSYNC, sc->sc_mode->vtotal - 1, DI_SYNC_COUNTER(DI_COUNTER_INT_HSYNC), 0, DI_SYNC_NONE); ipu_config_wave_gen_1(sc, di, DI_COUNTER_VSYNC, 0, DI_SYNC_NONE, 1, DI_SYNC_NONE, DI_SYNC_COUNTER(DI_COUNTER_INT_HSYNC), 0, MODE_VSW(sc->sc_mode) * 2); di_scr_conf = di ? IPU_DI1_SCR_CONF : IPU_DI0_SCR_CONF; IPU_WRITE4(sc, di_scr_conf, sc->sc_mode->vtotal - 1); /* TODO: update DI_SCR_CONF */ /* Active Data 0 */ ipu_config_wave_gen_0(sc, di, DI_COUNTER_AD_0, 0, DI_SYNC_COUNTER(DI_COUNTER_HSYNC), MODE_VSW(sc->sc_mode) + MODE_VFP(sc->sc_mode), DI_SYNC_COUNTER(DI_COUNTER_HSYNC)); ipu_config_wave_gen_1(sc, di, DI_COUNTER_AD_0, sc->sc_mode->vdisplay, DI_SYNC_COUNTER(DI_COUNTER_VSYNC), 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); ipu_config_wave_gen_0(sc, di, DI_COUNTER_AD_1, 0, DI_SYNC_CLK, MODE_HSW(sc->sc_mode) + MODE_HFP(sc->sc_mode), DI_SYNC_CLK); ipu_config_wave_gen_1(sc, di, DI_COUNTER_AD_1, sc->sc_mode->hdisplay, DI_SYNC_COUNTER(DI_COUNTER_AD_0), 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); ipu_reset_wave_gen(sc, di, 6); ipu_reset_wave_gen(sc, di, 7); ipu_reset_wave_gen(sc, di, 8); ipu_reset_wave_gen(sc, di, 9); ipu_init_microcode_template(sc, di, map); gen_offset = di ? IPU_DI1_GENERAL : IPU_DI0_GENERAL; gen = IPU_READ4(sc, gen_offset); if (sc->sc_mode->flags & VID_NHSYNC) gen &= ~DI_GENERAL_POLARITY_2; else /* active high */ gen |= DI_GENERAL_POLARITY_2; if (sc->sc_mode->flags & VID_NVSYNC) gen &= ~DI_GENERAL_POLARITY_3; else /* active high */ gen |= DI_GENERAL_POLARITY_3; if (MODE_PIXEL_CLOCK_INVERT) gen &= ~DI_GENERAL_POL_CLK; else gen |= DI_GENERAL_POL_CLK; /* Use LDB clock to drive pixel clock */ gen |= DI_CLOCK_EXTERNAL; IPU_WRITE4(sc, gen_offset, gen); as_gen_offset = di ? IPU_DI1_SYNC_AS_GEN : IPU_DI0_SYNC_AS_GEN; as_gen = SYNC_AS_GEN_VSYNC_SEL(DI_COUNTER_VSYNC - 1) | SYNC_AS_GEN_SYNC_START(2); IPU_WRITE4(sc, as_gen_offset, as_gen); IPU_WRITE4(sc, (di ? IPU_DI1_POL : IPU_DI0_POL), DI_POL_DRDY_POLARITY_15); IPU_WRITE4(sc, DC_DISP_CONF2(di), sc->sc_mode->hdisplay); } static void ipu_dc_enable(struct ipu_softc *sc) { uint32_t conf; /* channel 1 uses DI1 */ IPU_WRITE4(sc, DC_WRITE_CH_CONF_1, WRITE_CH_CONF_PROG_DI_ID(1)); conf = IPU_READ4(sc, DC_WRITE_CH_CONF_5); conf &= ~WRITE_CH_CONF_PROG_CHAN_TYP_MASK; conf |= WRITE_CH_CONF_PROG_CHAN_NORMAL; IPU_WRITE4(sc, DC_WRITE_CH_CONF_5, conf); } static void ipu_dc_link_event(struct ipu_softc *sc, int event, int addr, int priority) { uint32_t reg; int offset; int shift; if (event % 2) shift = 16; else shift = 0; offset = DC_RL0_CH_5 + (event / 2) * sizeof(uint32_t); reg = IPU_READ4(sc, offset); reg &= ~(0xFFFF << shift); reg |= ((addr << 8) | priority) << shift; IPU_WRITE4(sc, offset, reg); } static void ipu_dc_setup_map(struct ipu_softc *sc, int map, int byte, int offset, int mask) { uint32_t reg, shift, ptr; ptr = map * 3 + byte; reg = IPU_READ4(sc, DC_MAP_CONF_VAL(ptr)); if (ptr & 1) shift = 16; else shift = 0; reg &= ~(0xffff << shift); reg |= ((offset << 8) | mask) << shift; IPU_WRITE4(sc, DC_MAP_CONF_VAL(ptr), reg); reg = IPU_READ4(sc, DC_MAP_CONF_PTR(map)); if (map & 1) shift = 16 + 5 * byte; else shift = 5 * byte; reg &= ~(MAP_CONF_PTR_MASK << shift); reg |= (ptr) << shift; IPU_WRITE4(sc, DC_MAP_CONF_PTR(map), reg); } static void ipu_dc_reset_map(struct ipu_softc *sc, int map) { uint32_t reg, shift; reg = IPU_READ4(sc, DC_MAP_CONF_VAL(map)); if (map & 1) shift = 16; else shift = 0; reg &= ~(MAP_CONF_VAL_MASK << shift); IPU_WRITE4(sc, DC_MAP_CONF_VAL(map), reg); } static void ipu_dc_init(struct ipu_softc *sc, int di_port) { int addr; uint32_t conf; if (di_port) addr = 2; else addr = 5; ipu_dc_link_event(sc, DC_EVENT_NL, addr, 3); ipu_dc_link_event(sc, DC_EVENT_EOL, addr + 1, 2); ipu_dc_link_event(sc, DC_EVENT_NEW_DATA, addr + 2, 1); ipu_dc_link_event(sc, DC_EVENT_NF, 0, 0); ipu_dc_link_event(sc, DC_EVENT_NFIELD, 0, 0); ipu_dc_link_event(sc, DC_EVENT_EOF, 0, 0); ipu_dc_link_event(sc, DC_EVENT_EOFIELD, 0, 0); ipu_dc_link_event(sc, DC_EVENT_NEW_CHAN, 0, 0); ipu_dc_link_event(sc, DC_EVENT_NEW_ADDR, 0, 0); conf = WRITE_CH_CONF_PROG_W_SIZE(0x02) | WRITE_CH_CONF_PROG_DISP_ID(DI_PORT) | WRITE_CH_CONF_PROG_DI_ID(DI_PORT); IPU_WRITE4(sc, DC_WRITE_CH_CONF_5, conf); IPU_WRITE4(sc, DC_WRITE_CH_ADDR_5, 0x00000000); IPU_WRITE4(sc, DC_GEN, DC_GEN_SYNC_PRIORITY | DC_GEN_SYNC); /* High priority, sync */ } static void ipu_init_buffer(struct ipu_softc *sc) { struct ipu_cpmem_ch_param param; uint32_t stride; uint32_t reg, db_mode_sel, cur_buf; stride = sc->sc_mode->hdisplay * MODE_BPP / 8; /* init channel parameters */ CH_PARAM_RESET(¶m); /* XXX: interlaced modes are not supported yet */ CH_PARAM_SET_FW(¶m, sc->sc_mode->hdisplay - 1); CH_PARAM_SET_FH(¶m, sc->sc_mode->vdisplay - 1); CH_PARAM_SET_SLY(¶m, stride - 1); CH_PARAM_SET_EBA0(¶m, (sc->sc_fb_phys >> 3)); CH_PARAM_SET_EBA1(¶m, (sc->sc_fb_phys >> 3)); CH_PARAM_SET_BPP(¶m, IPU_PIX_FORMAT_BPP_16); CH_PARAM_SET_PFS(¶m, IPU_PIX_FORMAT_RGB); /* 16 pixels per burst access */ CH_PARAM_SET_NPB(¶m, 16 - 1); CH_PARAM_SET_RED_OFFSET(¶m, 0); CH_PARAM_SET_RED_WIDTH(¶m, 5 - 1); CH_PARAM_SET_GREEN_OFFSET(¶m, 5); CH_PARAM_SET_GREEN_WIDTH(¶m, 6 - 1); CH_PARAM_SET_BLUE_OFFSET(¶m, 11); CH_PARAM_SET_BLUE_WIDTH(¶m, 5 - 1); CH_PARAM_SET_ALPHA_OFFSET(¶m, 16); CH_PARAM_SET_ALPHA_WIDTH(¶m, 8 - 1); CH_PARAM_SET_UBO(¶m, 0); CH_PARAM_SET_VBO(¶m, 0); IPU_WRITE_CH_PARAM(sc, DMA_CHANNEL, ¶m); #ifdef DEBUG ipu_print_channel(¶m); #endif /* init DMFC */ IPU_WRITE4(sc, DMFC_IC_CTRL, DMFC_IC_CTRL_DISABLED); /* High resolution DP */ IPU_WRITE4(sc, DMFC_WR_CHAN, DMFC_WR_CHAN_BURST_SIZE_8 | DMFC_WR_CHAN_FIFO_SIZE_128); IPU_WRITE4(sc, DMFC_WR_CHAN_DEF, DMFC_WR_CHAN_DEF_WM_CLR_2C(1) | DMFC_WR_CHAN_DEF_WM_CLR_1C(1) | DMFC_WR_CHAN_DEF_WM_CLR_2(1) | DMFC_WR_CHAN_DEF_WM_CLR_1(7) | DMFC_WR_CHAN_DEF_WM_SET_1(5) | DMFC_WR_CHAN_DEF_WM_EN_1); IPU_WRITE4(sc, DMFC_DP_CHAN, DMFC_DP_CHAN_BURST_SIZE_5F(DMFC_DP_CHAN_BURST_SIZE_8) | DMFC_DP_CHAN_FIFO_SIZE_5F(DMFC_DP_CHAN_FIFO_SIZE_128) | DMFC_DP_CHAN_ST_ADDR_SIZE_5F(6) /* segment 6 */ | DMFC_DP_CHAN_BURST_SIZE_5B(DMFC_DP_CHAN_BURST_SIZE_8) | DMFC_DP_CHAN_FIFO_SIZE_5B(DMFC_DP_CHAN_FIFO_SIZE_256) | DMFC_DP_CHAN_ST_ADDR_SIZE_5B(2) /* segment 2 */); IPU_WRITE4(sc, DMFC_DP_CHAN_DEF, DMFC_DP_CHAN_DEF_WM_CLR_6F(1) | DMFC_DP_CHAN_DEF_WM_CLR_6B(1) | DMFC_DP_CHAN_DEF_WM_CLR_5F(7) | DMFC_DP_CHAN_DEF_WM_SET_5F(5) | DMFC_DP_CHAN_DEF_WM_EN_5F | DMFC_DP_CHAN_DEF_WM_CLR_5B(7) | DMFC_DP_CHAN_DEF_WM_SET_5B(5) | DMFC_DP_CHAN_DEF_WM_EN_5B); reg = IPU_READ4(sc, DMFC_GENERAL_1); reg &= ~(DMFC_GENERAL_1_WAIT4EOT_5B); IPU_WRITE4(sc, DMFC_GENERAL_1, reg); /* XXX: set priority? */ /* Set single buffer mode */ if (DMA_CHANNEL < 32) { db_mode_sel = IPU_CH_DB_MODE_SEL_0; cur_buf = IPU_CUR_BUF_0; } else { db_mode_sel = IPU_CH_DB_MODE_SEL_1; cur_buf = IPU_CUR_BUF_1; } reg = IPU_READ4(sc, db_mode_sel); reg |= (1UL << (DMA_CHANNEL & 0x1f)); IPU_WRITE4(sc, db_mode_sel, reg); IPU_WRITE4(sc, cur_buf, (1UL << (DMA_CHANNEL & 0x1f))); } static int ipu_init(struct ipu_softc *sc) { uint32_t reg, off; int i, err; size_t dma_size; IPU_WRITE4(sc, IPU_CONF, DI_PORT ? IPU_CONF_DI1_EN : IPU_CONF_DI0_EN); IPU_WRITE4(sc, IPU_MEM_RST, IPU_MEM_RST_ALL); i = 1000; while (i-- > 0) { if (!(IPU_READ4(sc, IPU_MEM_RST) & IPU_MEM_RST_START)) break; DELAY(1); } if (i <= 0) { err = ETIMEDOUT; device_printf(sc->sc_dev, "timeout while resetting memory\n"); goto fail; } ipu_dc_reset_map(sc, 0); ipu_dc_setup_map(sc, 0, 0, 7, 0xff); ipu_dc_setup_map(sc, 0, 1, 15, 0xff); ipu_dc_setup_map(sc, 0, 2, 23, 0xff); dma_size = round_page(sc->sc_mode->hdisplay * sc->sc_mode->vdisplay * (MODE_BPP / 8)); /* * Now allocate framebuffer memory */ err = bus_dma_tag_create( bus_get_dma_tag(sc->sc_dev), 4, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ dma_size, 1, /* maxsize, nsegments */ dma_size, 0, /* maxsegsize, flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->sc_dma_tag); if (err) goto fail; err = bus_dmamem_alloc(sc->sc_dma_tag, (void **)&sc->sc_fb_base, BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_dma_map); if (err) { device_printf(sc->sc_dev, "cannot allocate framebuffer\n"); goto fail; } err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, sc->sc_fb_base, dma_size, ipu_dmamap_cb, &sc->sc_fb_phys, BUS_DMA_NOWAIT); if (err) { device_printf(sc->sc_dev, "cannot load DMA map\n"); goto fail; } /* Calculate actual FB Size */ sc->sc_fb_size = sc->sc_mode->hdisplay * sc->sc_mode->vdisplay * MODE_BPP / 8; ipu_dc_init(sc, DI_PORT); reg = IPU_READ4(sc, IPU_CONF); reg |= IPU_CONF_DMFC_EN | IPU_CONF_DC_EN | IPU_CONF_DP_EN; IPU_WRITE4(sc, IPU_CONF, reg); ipu_config_timing(sc, DI_PORT); ipu_init_buffer(sc); ipu_di_enable(sc, DI_PORT); /* Enable DMA channel */ off = (DMA_CHANNEL > 31) ? IPU_IDMAC_CH_EN_2 : IPU_IDMAC_CH_EN_1; reg = IPU_READ4(sc, off); reg |= (1 << (DMA_CHANNEL & 0x1f)); IPU_WRITE4(sc, off, reg); ipu_dc_enable(sc); sc->sc_fb_info.fb_name = device_get_nameunit(sc->sc_dev); sc->sc_fb_info.fb_vbase = (intptr_t)sc->sc_fb_base; sc->sc_fb_info.fb_pbase = sc->sc_fb_phys; sc->sc_fb_info.fb_size = sc->sc_fb_size; sc->sc_fb_info.fb_bpp = sc->sc_fb_info.fb_depth = MODE_BPP; sc->sc_fb_info.fb_stride = sc->sc_mode->hdisplay * MODE_BPP / 8; sc->sc_fb_info.fb_width = sc->sc_mode->hdisplay; sc->sc_fb_info.fb_height = sc->sc_mode->vdisplay; device_t fbd = device_add_child(sc->sc_dev, "fbd", device_get_unit(sc->sc_dev)); if (fbd == NULL) { device_printf(sc->sc_dev, "Failed to add fbd child\n"); goto fail; } if (device_probe_and_attach(fbd) != 0) { device_printf(sc->sc_dev, "Failed to attach fbd device\n"); goto fail; } return (0); fail: return (err); } static int ipu_mode_is_valid(const struct videomode *mode) { if ((mode->dot_clock < 13500) || (mode->dot_clock > 216000)) return (0); return (1); } static const struct videomode * ipu_pick_mode(struct edid_info *ei) { const struct videomode *videomode; const struct videomode *m; int n; videomode = NULL; /* * Pick a mode. */ if (ei->edid_preferred_mode != NULL) { if (ipu_mode_is_valid(ei->edid_preferred_mode)) videomode = ei->edid_preferred_mode; } if (videomode == NULL) { m = ei->edid_modes; sort_modes(ei->edid_modes, &ei->edid_preferred_mode, ei->edid_nmodes); for (n = 0; n < ei->edid_nmodes; n++) if (ipu_mode_is_valid(&m[n])) { videomode = &m[n]; break; } } return videomode; } static void ipu_hdmi_event(void *arg, device_t hdmi_dev) { struct ipu_softc *sc; uint8_t *edid; uint32_t edid_len; struct edid_info ei; const struct videomode *videomode; sc = arg; edid = NULL; edid_len = 0; - if (HDMI_GET_EDID(hdmi_dev, &edid, &edid_len) != 0) { + if (CRTC_GET_EDID(hdmi_dev, &edid, &edid_len) != 0) { device_printf(sc->sc_dev, "failed to get EDID info from HDMI framer\n"); } videomode = NULL; if ( edid && (edid_parse(edid, &ei) == 0)) { if (bootverbose) edid_print(&ei); videomode = ipu_pick_mode(&ei); } else device_printf(sc->sc_dev, "failed to parse EDID\n"); /* Use standard VGA as fallback */ if (videomode == NULL) videomode = pick_mode_by_ref(640, 480, 60); if (videomode == NULL) { device_printf(sc->sc_dev, "failed to find usable videomode\n"); return; } sc->sc_mode = videomode; if (bootverbose) device_printf(sc->sc_dev, "detected videomode: %dx%d\n", videomode->hdisplay, videomode->vdisplay); ipu_init(sc); - HDMI_SET_VIDEOMODE(hdmi_dev, sc->sc_mode); + CRTC_SET_VIDEOMODE(hdmi_dev, sc->sc_mode); } static int ipu_probe(device_t dev) { if (have_ipu) return (ENXIO); if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ipu")) return (ENXIO); device_set_desc(dev, "Freescale IPU"); return (BUS_PROBE_DEFAULT); } static int ipu_attach(device_t dev) { struct ipu_softc *sc; if (have_ipu) return (ENXIO); sc = device_get_softc(dev); sc->sc_dev = dev; sc->sc_mem_rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_mem_rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "cannot allocate memory window\n"); return (ENXIO); } sc->sc_irq_rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irq_rid, RF_ACTIVE); if (!sc->sc_irq_res) { bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, sc->sc_mem_res); device_printf(dev, "cannot allocate interrupt\n"); return (ENXIO); } /* Enable IPU1 */ if (imx_ccm_pll_video_enable() != 0) { bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, sc->sc_mem_res); bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, sc->sc_irq_res); device_printf(dev, "failed to set up video PLL\n"); return (ENXIO); } imx_ccm_ipu_enable(1); if (src_reset_ipu() != 0) { bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, sc->sc_mem_res); bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, sc->sc_irq_res); device_printf(dev, "failed to reset IPU\n"); return (ENXIO); } IPU_LOCK_INIT(sc); sc->sc_hdmi_evh = EVENTHANDLER_REGISTER(hdmi_event, ipu_hdmi_event, sc, 0); have_ipu = 1; return (0); } static int ipu_detach(device_t dev) { /* Do not let unload driver */ return (EBUSY); } static struct fb_info * ipu_fb_getinfo(device_t dev) { struct ipu_softc *sc; sc = device_get_softc(dev); return (&sc->sc_fb_info); } static device_method_t ipu_methods[] = { DEVMETHOD(device_probe, ipu_probe), DEVMETHOD(device_attach, ipu_attach), DEVMETHOD(device_detach, ipu_detach), /* Framebuffer service methods */ DEVMETHOD(fb_getinfo, ipu_fb_getinfo), DEVMETHOD_END }; static driver_t ipu_driver = { "fb", ipu_methods, sizeof(struct ipu_softc), }; DRIVER_MODULE(ipu, simplebus, ipu_driver, 0, 0); MODULE_VERSION(ipu, 1); MODULE_DEPEND(ipu, simplebus, 1, 1, 1); diff --git a/sys/arm/ti/am335x/am335x_lcd.c b/sys/arm/ti/am335x/am335x_lcd.c index 06563a476a3c..34f46613afac 100644 --- a/sys/arm/ti/am335x/am335x_lcd.c +++ b/sys/arm/ti/am335x/am335x_lcd.c @@ -1,1102 +1,1102 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright 2013 Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_syscons.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef DEV_SC #include #else /* VT */ #include #endif #include #include #include "am335x_lcd.h" #include "am335x_pwm.h" #include "fb_if.h" -#include "hdmi_if.h" +#include "crtc_if.h" #define LCD_PID 0x00 #define LCD_CTRL 0x04 #define CTRL_DIV_MASK 0xff #define CTRL_DIV_SHIFT 8 #define CTRL_AUTO_UFLOW_RESTART (1 << 1) #define CTRL_RASTER_MODE 1 #define CTRL_LIDD_MODE 0 #define LCD_LIDD_CTRL 0x0C #define LCD_LIDD_CS0_CONF 0x10 #define LCD_LIDD_CS0_ADDR 0x14 #define LCD_LIDD_CS0_DATA 0x18 #define LCD_LIDD_CS1_CONF 0x1C #define LCD_LIDD_CS1_ADDR 0x20 #define LCD_LIDD_CS1_DATA 0x24 #define LCD_RASTER_CTRL 0x28 #define RASTER_CTRL_TFT24_UNPACKED (1 << 26) #define RASTER_CTRL_TFT24 (1 << 25) #define RASTER_CTRL_STN565 (1 << 24) #define RASTER_CTRL_TFTPMAP (1 << 23) #define RASTER_CTRL_NIBMODE (1 << 22) #define RASTER_CTRL_PALMODE_SHIFT 20 #define PALETTE_PALETTE_AND_DATA 0x00 #define PALETTE_PALETTE_ONLY 0x01 #define PALETTE_DATA_ONLY 0x02 #define RASTER_CTRL_REQDLY_SHIFT 12 #define RASTER_CTRL_MONO8B (1 << 9) #define RASTER_CTRL_RBORDER (1 << 8) #define RASTER_CTRL_LCDTFT (1 << 7) #define RASTER_CTRL_LCDBW (1 << 1) #define RASTER_CTRL_LCDEN (1 << 0) #define LCD_RASTER_TIMING_0 0x2C #define RASTER_TIMING_0_HBP_SHIFT 24 #define RASTER_TIMING_0_HFP_SHIFT 16 #define RASTER_TIMING_0_HSW_SHIFT 10 #define RASTER_TIMING_0_PPLLSB_SHIFT 4 #define RASTER_TIMING_0_PPLMSB_SHIFT 3 #define LCD_RASTER_TIMING_1 0x30 #define RASTER_TIMING_1_VBP_SHIFT 24 #define RASTER_TIMING_1_VFP_SHIFT 16 #define RASTER_TIMING_1_VSW_SHIFT 10 #define RASTER_TIMING_1_LPP_SHIFT 0 #define LCD_RASTER_TIMING_2 0x34 #define RASTER_TIMING_2_HSWHI_SHIFT 27 #define RASTER_TIMING_2_LPP_B10_SHIFT 26 #define RASTER_TIMING_2_PHSVS (1 << 25) #define RASTER_TIMING_2_PHSVS_RISE (1 << 24) #define RASTER_TIMING_2_PHSVS_FALL (0 << 24) #define RASTER_TIMING_2_IOE (1 << 23) #define RASTER_TIMING_2_IPC (1 << 22) #define RASTER_TIMING_2_IHS (1 << 21) #define RASTER_TIMING_2_IVS (1 << 20) #define RASTER_TIMING_2_ACBI_SHIFT 16 #define RASTER_TIMING_2_ACB_SHIFT 8 #define RASTER_TIMING_2_HBPHI_SHIFT 4 #define RASTER_TIMING_2_HFPHI_SHIFT 0 #define LCD_RASTER_SUBPANEL 0x38 #define LCD_RASTER_SUBPANEL2 0x3C #define LCD_LCDDMA_CTRL 0x40 #define LCDDMA_CTRL_DMA_MASTER_PRIO_SHIFT 16 #define LCDDMA_CTRL_TH_FIFO_RDY_SHIFT 8 #define LCDDMA_CTRL_BURST_SIZE_SHIFT 4 #define LCDDMA_CTRL_BYTES_SWAP (1 << 3) #define LCDDMA_CTRL_BE (1 << 1) #define LCDDMA_CTRL_FB0_ONLY 0 #define LCDDMA_CTRL_FB0_FB1 (1 << 0) #define LCD_LCDDMA_FB0_BASE 0x44 #define LCD_LCDDMA_FB0_CEILING 0x48 #define LCD_LCDDMA_FB1_BASE 0x4C #define LCD_LCDDMA_FB1_CEILING 0x50 #define LCD_SYSCONFIG 0x54 #define SYSCONFIG_STANDBY_FORCE (0 << 4) #define SYSCONFIG_STANDBY_NONE (1 << 4) #define SYSCONFIG_STANDBY_SMART (2 << 4) #define SYSCONFIG_IDLE_FORCE (0 << 2) #define SYSCONFIG_IDLE_NONE (1 << 2) #define SYSCONFIG_IDLE_SMART (2 << 2) #define LCD_IRQSTATUS_RAW 0x58 #define LCD_IRQSTATUS 0x5C #define LCD_IRQENABLE_SET 0x60 #define LCD_IRQENABLE_CLEAR 0x64 #define IRQ_EOF1 (1 << 9) #define IRQ_EOF0 (1 << 8) #define IRQ_PL (1 << 6) #define IRQ_FUF (1 << 5) #define IRQ_ACB (1 << 3) #define IRQ_SYNC_LOST (1 << 2) #define IRQ_RASTER_DONE (1 << 1) #define IRQ_FRAME_DONE (1 << 0) #define LCD_END_OF_INT_IND 0x68 #define LCD_CLKC_ENABLE 0x6C #define CLKC_ENABLE_DMA (1 << 2) #define CLKC_ENABLE_LDID (1 << 1) #define CLKC_ENABLE_CORE (1 << 0) #define LCD_CLKC_RESET 0x70 #define CLKC_RESET_MAIN (1 << 3) #define CLKC_RESET_DMA (1 << 2) #define CLKC_RESET_LDID (1 << 1) #define CLKC_RESET_CORE (1 << 0) #define LCD_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) #define LCD_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) #define LCD_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ device_get_nameunit(_sc->sc_dev), "am335x_lcd", MTX_DEF) #define LCD_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx); #define LCD_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg); #define LCD_WRITE4(_sc, reg, value) \ bus_write_4((_sc)->sc_mem_res, reg, value); /* Backlight is controlled by eCAS interface on PWM unit 0 */ #define PWM_UNIT 0 #define PWM_PERIOD 100 #define MODE_HBP(mode) ((mode)->htotal - (mode)->hsync_end) #define MODE_HFP(mode) ((mode)->hsync_start - (mode)->hdisplay) #define MODE_HSW(mode) ((mode)->hsync_end - (mode)->hsync_start) #define MODE_VBP(mode) ((mode)->vtotal - (mode)->vsync_end) #define MODE_VFP(mode) ((mode)->vsync_start - (mode)->vdisplay) #define MODE_VSW(mode) ((mode)->vsync_end - (mode)->vsync_start) #define MAX_PIXEL_CLOCK 126000 #define MAX_BANDWIDTH (1280*1024*60) struct am335x_lcd_softc { device_t sc_dev; struct fb_info sc_fb_info; struct resource *sc_mem_res; struct resource *sc_irq_res; void *sc_intr_hl; struct mtx sc_mtx; int sc_backlight; struct sysctl_oid *sc_oid; struct panel_info sc_panel; /* Framebuffer */ bus_dma_tag_t sc_dma_tag; bus_dmamap_t sc_dma_map; size_t sc_fb_size; bus_addr_t sc_fb_phys; uint8_t *sc_fb_base; /* HDMI framer */ phandle_t sc_hdmi_framer; eventhandler_tag sc_hdmi_evh; /* Clock */ clk_t sc_clk_dpll_disp_ck; }; static void am335x_fb_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) { bus_addr_t *addr; if (err) return; addr = (bus_addr_t*)arg; *addr = segs[0].ds_addr; } static uint32_t am335x_lcd_calc_divisor(uint32_t reference, uint32_t freq) { uint32_t div, i; uint32_t delta, min_delta; min_delta = freq; div = 255; /* Raster mode case: divisors are in range from 2 to 255 */ for (i = 2; i < 255; i++) { delta = abs(reference/i - freq); if (delta < min_delta) { div = i; min_delta = delta; } } return (div); } static int am335x_lcd_sysctl_backlight(SYSCTL_HANDLER_ARGS) { struct am335x_lcd_softc *sc = (struct am335x_lcd_softc*)arg1; int error; int backlight; backlight = sc->sc_backlight; error = sysctl_handle_int(oidp, &backlight, 0, req); if (error != 0 || req->newptr == NULL) return (error); if (backlight < 0) backlight = 0; if (backlight > 100) backlight = 100; LCD_LOCK(sc); error = am335x_pwm_config_ecap(PWM_UNIT, PWM_PERIOD, backlight*PWM_PERIOD/100); if (error == 0) sc->sc_backlight = backlight; LCD_UNLOCK(sc); return (error); } static uint32_t am335x_mode_vrefresh(const struct videomode *mode) { uint32_t refresh; /* Calculate vertical refresh rate */ refresh = (mode->dot_clock * 1000 / mode->htotal); refresh = (refresh + mode->vtotal / 2) / mode->vtotal; if (mode->flags & VID_INTERLACE) refresh *= 2; if (mode->flags & VID_DBLSCAN) refresh /= 2; return refresh; } static int am335x_mode_is_valid(const struct videomode *mode) { uint32_t hbp, hfp, hsw; uint32_t vbp, vfp, vsw; if (mode->dot_clock > MAX_PIXEL_CLOCK) return (0); if (mode->hdisplay & 0xf) return (0); if (mode->vdisplay > 2048) return (0); /* Check ranges for timing parameters */ hbp = MODE_HBP(mode) - 1; hfp = MODE_HFP(mode) - 1; hsw = MODE_HSW(mode) - 1; vbp = MODE_VBP(mode); vfp = MODE_VFP(mode); vsw = MODE_VSW(mode) - 1; if (hbp > 0x3ff) return (0); if (hfp > 0x3ff) return (0); if (hsw > 0x3ff) return (0); if (vbp > 0xff) return (0); if (vfp > 0xff) return (0); if (vsw > 0x3f) return (0); if (mode->vdisplay*mode->hdisplay*am335x_mode_vrefresh(mode) > MAX_BANDWIDTH) return (0); return (1); } static void am335x_read_hdmi_property(device_t dev) { phandle_t node, xref; phandle_t endpoint; phandle_t hdmi_xref; struct am335x_lcd_softc *sc; sc = device_get_softc(dev); node = ofw_bus_get_node(dev); sc->sc_hdmi_framer = 0; /* * Old FreeBSD way of referencing to HDMI framer */ if (OF_getencprop(node, "hdmi", &hdmi_xref, sizeof(hdmi_xref)) != -1) { sc->sc_hdmi_framer = hdmi_xref; return; } /* * Use bindings described in Linux docs: * bindings/media/video-interfaces.txt * We assume that the only endpoint in LCDC node * is HDMI framer. */ node = ofw_bus_find_child(node, "port"); /* No media bindings */ if (node == 0) return; for (endpoint = OF_child(node); endpoint != 0; endpoint = OF_peer(endpoint)) { if (OF_getencprop(endpoint, "remote-endpoint", &xref, sizeof(xref)) != -1) { /* port/port@0/endpoint@0 */ node = OF_node_from_xref(xref); /* port/port@0 */ node = OF_parent(node); /* port */ node = OF_parent(node); /* actual owner of port, in our case HDMI framer */ sc->sc_hdmi_framer = OF_xref_from_node(OF_parent(node)); if (sc->sc_hdmi_framer != 0) return; } } } static int am335x_read_property(device_t dev, phandle_t node, const char *name, uint32_t *val) { pcell_t cell; if ((OF_getencprop(node, name, &cell, sizeof(cell))) <= 0) { device_printf(dev, "missing '%s' attribute in LCD panel info\n", name); return (ENXIO); } *val = cell; return (0); } static int am335x_read_timing(device_t dev, phandle_t node, struct panel_info *panel) { int error; phandle_t timings_node, timing_node, native; timings_node = ofw_bus_find_child(node, "display-timings"); if (timings_node == 0) { device_printf(dev, "no \"display-timings\" node\n"); return (-1); } if (OF_searchencprop(timings_node, "native-mode", &native, sizeof(native)) == -1) { device_printf(dev, "no \"native-mode\" reference in \"timings\" node\n"); return (-1); } timing_node = OF_node_from_xref(native); error = 0; if ((error = am335x_read_property(dev, timing_node, "hactive", &panel->panel_width))) goto out; if ((error = am335x_read_property(dev, timing_node, "vactive", &panel->panel_height))) goto out; if ((error = am335x_read_property(dev, timing_node, "hfront-porch", &panel->panel_hfp))) goto out; if ((error = am335x_read_property(dev, timing_node, "hback-porch", &panel->panel_hbp))) goto out; if ((error = am335x_read_property(dev, timing_node, "hsync-len", &panel->panel_hsw))) goto out; if ((error = am335x_read_property(dev, timing_node, "vfront-porch", &panel->panel_vfp))) goto out; if ((error = am335x_read_property(dev, timing_node, "vback-porch", &panel->panel_vbp))) goto out; if ((error = am335x_read_property(dev, timing_node, "vsync-len", &panel->panel_vsw))) goto out; if ((error = am335x_read_property(dev, timing_node, "clock-frequency", &panel->panel_pxl_clk))) goto out; if ((error = am335x_read_property(dev, timing_node, "pixelclk-active", &panel->pixelclk_active))) goto out; if ((error = am335x_read_property(dev, timing_node, "hsync-active", &panel->hsync_active))) goto out; if ((error = am335x_read_property(dev, timing_node, "vsync-active", &panel->vsync_active))) goto out; out: return (error); } static int am335x_read_panel_info(device_t dev, phandle_t node, struct panel_info *panel) { phandle_t panel_info_node; panel_info_node = ofw_bus_find_child(node, "panel-info"); if (panel_info_node == 0) return (-1); am335x_read_property(dev, panel_info_node, "ac-bias", &panel->ac_bias); am335x_read_property(dev, panel_info_node, "ac-bias-intrpt", &panel->ac_bias_intrpt); am335x_read_property(dev, panel_info_node, "dma-burst-sz", &panel->dma_burst_sz); am335x_read_property(dev, panel_info_node, "bpp", &panel->bpp); am335x_read_property(dev, panel_info_node, "fdd", &panel->fdd); am335x_read_property(dev, panel_info_node, "sync-edge", &panel->sync_edge); am335x_read_property(dev, panel_info_node, "sync-ctrl", &panel->sync_ctrl); return (0); } static void am335x_lcd_intr(void *arg) { struct am335x_lcd_softc *sc = arg; uint32_t reg; reg = LCD_READ4(sc, LCD_IRQSTATUS); LCD_WRITE4(sc, LCD_IRQSTATUS, reg); /* Read value back to make sure it reached the hardware */ reg = LCD_READ4(sc, LCD_IRQSTATUS); if (reg & IRQ_SYNC_LOST) { reg = LCD_READ4(sc, LCD_RASTER_CTRL); reg &= ~RASTER_CTRL_LCDEN; LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); reg = LCD_READ4(sc, LCD_RASTER_CTRL); reg |= RASTER_CTRL_LCDEN; LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); goto done; } if (reg & IRQ_PL) { reg = LCD_READ4(sc, LCD_RASTER_CTRL); reg &= ~RASTER_CTRL_LCDEN; LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); reg = LCD_READ4(sc, LCD_RASTER_CTRL); reg |= RASTER_CTRL_LCDEN; LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); goto done; } if (reg & IRQ_EOF0) { LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); reg &= ~IRQ_EOF0; } if (reg & IRQ_EOF1) { LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); reg &= ~IRQ_EOF1; } if (reg & IRQ_FUF) { /* TODO: Handle FUF */ } if (reg & IRQ_ACB) { /* TODO: Handle ACB */ } done: LCD_WRITE4(sc, LCD_END_OF_INT_IND, 0); /* Read value back to make sure it reached the hardware */ reg = LCD_READ4(sc, LCD_END_OF_INT_IND); } static const struct videomode * am335x_lcd_pick_mode(struct edid_info *ei) { const struct videomode *videomode; const struct videomode *m; int n; /* Get standard VGA as default */ videomode = NULL; /* * Pick a mode. */ if (ei->edid_preferred_mode != NULL) { if (am335x_mode_is_valid(ei->edid_preferred_mode)) videomode = ei->edid_preferred_mode; } if (videomode == NULL) { m = ei->edid_modes; sort_modes(ei->edid_modes, &ei->edid_preferred_mode, ei->edid_nmodes); for (n = 0; n < ei->edid_nmodes; n++) if (am335x_mode_is_valid(&m[n])) { videomode = &m[n]; break; } } return videomode; } static int am335x_lcd_configure(struct am335x_lcd_softc *sc) { int div; uint32_t reg, timing0, timing1, timing2; uint32_t burst_log; size_t dma_size; uint32_t hbp, hfp, hsw; uint32_t vbp, vfp, vsw; uint32_t width, height; uint64_t ref_freq; int err; /* * try to adjust clock to get double of requested frequency * HDMI/DVI displays are very sensitive to error in frequncy value */ err = clk_set_freq(sc->sc_clk_dpll_disp_ck, sc->sc_panel.panel_pxl_clk*2, CLK_SET_ROUND_ANY); if (err != 0) { device_printf(sc->sc_dev, "can't set source frequency\n"); return (ENXIO); } err = clk_get_freq(sc->sc_clk_dpll_disp_ck, &ref_freq); if (err != 0) { device_printf(sc->sc_dev, "can't get reference frequency\n"); return (ENXIO); } /* Panel initialization */ dma_size = round_page(sc->sc_panel.panel_width*sc->sc_panel.panel_height*sc->sc_panel.bpp/8); /* * Now allocate framebuffer memory */ err = bus_dma_tag_create( bus_get_dma_tag(sc->sc_dev), 4, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ dma_size, 1, /* maxsize, nsegments */ dma_size, 0, /* maxsegsize, flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->sc_dma_tag); if (err) goto done; err = bus_dmamem_alloc(sc->sc_dma_tag, (void **)&sc->sc_fb_base, BUS_DMA_COHERENT, &sc->sc_dma_map); if (err) { device_printf(sc->sc_dev, "cannot allocate framebuffer\n"); goto done; } err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, sc->sc_fb_base, dma_size, am335x_fb_dmamap_cb, &sc->sc_fb_phys, BUS_DMA_NOWAIT); if (err) { device_printf(sc->sc_dev, "cannot load DMA map\n"); goto done; } /* Make sure it's blank */ memset(sc->sc_fb_base, 0x0, dma_size); /* Calculate actual FB Size */ sc->sc_fb_size = sc->sc_panel.panel_width*sc->sc_panel.panel_height*sc->sc_panel.bpp/8; /* Only raster mode is supported */ reg = CTRL_RASTER_MODE; div = am335x_lcd_calc_divisor(ref_freq, sc->sc_panel.panel_pxl_clk); reg |= (div << CTRL_DIV_SHIFT); LCD_WRITE4(sc, LCD_CTRL, reg); /* Set timing */ timing0 = timing1 = timing2 = 0; hbp = sc->sc_panel.panel_hbp - 1; hfp = sc->sc_panel.panel_hfp - 1; hsw = sc->sc_panel.panel_hsw - 1; vbp = sc->sc_panel.panel_vbp; vfp = sc->sc_panel.panel_vfp; vsw = sc->sc_panel.panel_vsw - 1; height = sc->sc_panel.panel_height - 1; width = sc->sc_panel.panel_width - 1; /* Horizontal back porch */ timing0 |= (hbp & 0xff) << RASTER_TIMING_0_HBP_SHIFT; timing2 |= ((hbp >> 8) & 3) << RASTER_TIMING_2_HBPHI_SHIFT; /* Horizontal front porch */ timing0 |= (hfp & 0xff) << RASTER_TIMING_0_HFP_SHIFT; timing2 |= ((hfp >> 8) & 3) << RASTER_TIMING_2_HFPHI_SHIFT; /* Horizontal sync width */ timing0 |= (hsw & 0x3f) << RASTER_TIMING_0_HSW_SHIFT; timing2 |= ((hsw >> 6) & 0xf) << RASTER_TIMING_2_HSWHI_SHIFT; /* Vertical back porch, front porch, sync width */ timing1 |= (vbp & 0xff) << RASTER_TIMING_1_VBP_SHIFT; timing1 |= (vfp & 0xff) << RASTER_TIMING_1_VFP_SHIFT; timing1 |= (vsw & 0x3f) << RASTER_TIMING_1_VSW_SHIFT; /* Pixels per line */ timing0 |= ((width >> 10) & 1) << RASTER_TIMING_0_PPLMSB_SHIFT; timing0 |= ((width >> 4) & 0x3f) << RASTER_TIMING_0_PPLLSB_SHIFT; /* Lines per panel */ timing1 |= (height & 0x3ff) << RASTER_TIMING_1_LPP_SHIFT; timing2 |= ((height >> 10 ) & 1) << RASTER_TIMING_2_LPP_B10_SHIFT; /* clock signal settings */ if (sc->sc_panel.sync_ctrl) timing2 |= RASTER_TIMING_2_PHSVS; if (sc->sc_panel.sync_edge) timing2 |= RASTER_TIMING_2_PHSVS_RISE; else timing2 |= RASTER_TIMING_2_PHSVS_FALL; if (sc->sc_panel.hsync_active == 0) timing2 |= RASTER_TIMING_2_IHS; if (sc->sc_panel.vsync_active == 0) timing2 |= RASTER_TIMING_2_IVS; if (sc->sc_panel.pixelclk_active == 0) timing2 |= RASTER_TIMING_2_IPC; /* AC bias */ timing2 |= (sc->sc_panel.ac_bias << RASTER_TIMING_2_ACB_SHIFT); timing2 |= (sc->sc_panel.ac_bias_intrpt << RASTER_TIMING_2_ACBI_SHIFT); LCD_WRITE4(sc, LCD_RASTER_TIMING_0, timing0); LCD_WRITE4(sc, LCD_RASTER_TIMING_1, timing1); LCD_WRITE4(sc, LCD_RASTER_TIMING_2, timing2); /* DMA settings */ reg = LCDDMA_CTRL_FB0_FB1; /* Find power of 2 for current burst size */ switch (sc->sc_panel.dma_burst_sz) { case 1: burst_log = 0; break; case 2: burst_log = 1; break; case 4: burst_log = 2; break; case 8: burst_log = 3; break; case 16: default: burst_log = 4; break; } reg |= (burst_log << LCDDMA_CTRL_BURST_SIZE_SHIFT); /* XXX: FIFO TH */ reg |= (0 << LCDDMA_CTRL_TH_FIFO_RDY_SHIFT); LCD_WRITE4(sc, LCD_LCDDMA_CTRL, reg); LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); /* Enable LCD */ reg = RASTER_CTRL_LCDTFT; reg |= (sc->sc_panel.fdd << RASTER_CTRL_REQDLY_SHIFT); reg |= (PALETTE_DATA_ONLY << RASTER_CTRL_PALMODE_SHIFT); if (sc->sc_panel.bpp >= 24) reg |= RASTER_CTRL_TFT24; if (sc->sc_panel.bpp == 32) reg |= RASTER_CTRL_TFT24_UNPACKED; LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); LCD_WRITE4(sc, LCD_CLKC_ENABLE, CLKC_ENABLE_DMA | CLKC_ENABLE_LDID | CLKC_ENABLE_CORE); LCD_WRITE4(sc, LCD_CLKC_RESET, CLKC_RESET_MAIN); DELAY(100); LCD_WRITE4(sc, LCD_CLKC_RESET, 0); reg = IRQ_EOF1 | IRQ_EOF0 | IRQ_FUF | IRQ_PL | IRQ_ACB | IRQ_SYNC_LOST | IRQ_RASTER_DONE | IRQ_FRAME_DONE; LCD_WRITE4(sc, LCD_IRQENABLE_SET, reg); reg = LCD_READ4(sc, LCD_RASTER_CTRL); reg |= RASTER_CTRL_LCDEN; LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); LCD_WRITE4(sc, LCD_SYSCONFIG, SYSCONFIG_STANDBY_SMART | SYSCONFIG_IDLE_SMART); sc->sc_fb_info.fb_name = device_get_nameunit(sc->sc_dev); sc->sc_fb_info.fb_vbase = (intptr_t)sc->sc_fb_base; sc->sc_fb_info.fb_pbase = sc->sc_fb_phys; sc->sc_fb_info.fb_size = sc->sc_fb_size; sc->sc_fb_info.fb_bpp = sc->sc_fb_info.fb_depth = sc->sc_panel.bpp; sc->sc_fb_info.fb_stride = sc->sc_panel.panel_width*sc->sc_panel.bpp / 8; sc->sc_fb_info.fb_width = sc->sc_panel.panel_width; sc->sc_fb_info.fb_height = sc->sc_panel.panel_height; #ifdef DEV_SC err = (sc_attach_unit(device_get_unit(sc->sc_dev), device_get_flags(sc->sc_dev) | SC_AUTODETECT_KBD)); if (err) { device_printf(sc->sc_dev, "failed to attach syscons\n"); goto fail; } am335x_lcd_syscons_setup((vm_offset_t)sc->sc_fb_base, sc->sc_fb_phys, &panel); #else /* VT */ device_t fbd = device_add_child(sc->sc_dev, "fbd", device_get_unit(sc->sc_dev)); if (fbd != NULL) { if (device_probe_and_attach(fbd) != 0) device_printf(sc->sc_dev, "failed to attach fbd device\n"); } else device_printf(sc->sc_dev, "failed to add fbd child\n"); #endif done: return (err); } static void am335x_lcd_hdmi_event(void *arg, device_t hdmi, int event) { struct am335x_lcd_softc *sc; const struct videomode *videomode; struct videomode hdmi_mode; device_t hdmi_dev; uint8_t *edid; uint32_t edid_len; struct edid_info ei; sc = arg; /* Nothing to work with */ if (!sc->sc_hdmi_framer) { device_printf(sc->sc_dev, "HDMI event without HDMI framer set\n"); return; } hdmi_dev = OF_device_from_xref(sc->sc_hdmi_framer); if (!hdmi_dev) { device_printf(sc->sc_dev, "no actual device for \"hdmi\" property\n"); return; } edid = NULL; edid_len = 0; - if (HDMI_GET_EDID(hdmi_dev, &edid, &edid_len) != 0) { + if (CRTC_GET_EDID(hdmi_dev, &edid, &edid_len) != 0) { device_printf(sc->sc_dev, "failed to get EDID info from HDMI framer\n"); return; } videomode = NULL; if (edid_parse(edid, &ei) == 0) { edid_print(&ei); videomode = am335x_lcd_pick_mode(&ei); } else device_printf(sc->sc_dev, "failed to parse EDID\n"); /* Use standard VGA as fallback */ if (videomode == NULL) videomode = pick_mode_by_ref(640, 480, 60); if (videomode == NULL) { device_printf(sc->sc_dev, "failed to find usable videomode"); return; } device_printf(sc->sc_dev, "detected videomode: %dx%d @ %dKHz\n", videomode->hdisplay, videomode->vdisplay, am335x_mode_vrefresh(videomode)); sc->sc_panel.panel_width = videomode->hdisplay; sc->sc_panel.panel_height = videomode->vdisplay; sc->sc_panel.panel_hfp = videomode->hsync_start - videomode->hdisplay; sc->sc_panel.panel_hbp = videomode->htotal - videomode->hsync_end; sc->sc_panel.panel_hsw = videomode->hsync_end - videomode->hsync_start; sc->sc_panel.panel_vfp = videomode->vsync_start - videomode->vdisplay; sc->sc_panel.panel_vbp = videomode->vtotal - videomode->vsync_end; sc->sc_panel.panel_vsw = videomode->vsync_end - videomode->vsync_start; sc->sc_panel.pixelclk_active = 1; /* logic for HSYNC should be reversed */ if (videomode->flags & VID_NHSYNC) sc->sc_panel.hsync_active = 1; else sc->sc_panel.hsync_active = 0; if (videomode->flags & VID_NVSYNC) sc->sc_panel.vsync_active = 0; else sc->sc_panel.vsync_active = 1; sc->sc_panel.panel_pxl_clk = videomode->dot_clock * 1000; am335x_lcd_configure(sc); memcpy(&hdmi_mode, videomode, sizeof(hdmi_mode)); hdmi_mode.hskew = videomode->hsync_end - videomode->hsync_start; hdmi_mode.flags |= VID_HSKEW; - HDMI_SET_VIDEOMODE(hdmi_dev, &hdmi_mode); + CRTC_SET_VIDEOMODE(hdmi_dev, &hdmi_mode); } static int am335x_lcd_probe(device_t dev) { #ifdef DEV_SC int err; #endif if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "ti,am33xx-tilcdc")) return (ENXIO); device_set_desc(dev, "AM335x LCD controller"); #ifdef DEV_SC err = sc_probe_unit(device_get_unit(dev), device_get_flags(dev) | SC_AUTODETECT_KBD); if (err != 0) return (err); #endif return (BUS_PROBE_DEFAULT); } static int am335x_lcd_attach(device_t dev) { struct am335x_lcd_softc *sc; int err; int rid; struct sysctl_ctx_list *ctx; struct sysctl_oid *tree; phandle_t root, panel_node; err = 0; sc = device_get_softc(dev); sc->sc_dev = dev; am335x_read_hdmi_property(dev); root = OF_finddevice("/"); if (root == -1) { device_printf(dev, "failed to get FDT root node\n"); return (ENXIO); } /* Fixme: Cant find any reference in DTS for dpll_disp_ck@498 for now. */ err = clk_get_by_name(dev, "dpll_disp_ck@498", &sc->sc_clk_dpll_disp_ck); if (err != 0) { device_printf(dev, "Cant get dpll_disp_ck@49\n"); return (ENXIO); } sc->sc_panel.ac_bias = 255; sc->sc_panel.ac_bias_intrpt = 0; sc->sc_panel.dma_burst_sz = 16; sc->sc_panel.bpp = 16; sc->sc_panel.fdd = 128; sc->sc_panel.sync_edge = 0; sc->sc_panel.sync_ctrl = 1; panel_node = fdt_find_compatible(root, "ti,tilcdc,panel", 1); if (panel_node != 0) { device_printf(dev, "using static panel info\n"); if (am335x_read_panel_info(dev, panel_node, &sc->sc_panel)) { device_printf(dev, "failed to read panel info\n"); return (ENXIO); } if (am335x_read_timing(dev, panel_node, &sc->sc_panel)) { device_printf(dev, "failed to read timings\n"); return (ENXIO); } } err = ti_sysc_clock_enable(device_get_parent(dev)); if (err != 0) { device_printf(dev, "Failed to enable sysc clkctrl, err %d\n", err); return (ENXIO); } rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "cannot allocate memory window\n"); return (ENXIO); } rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!sc->sc_irq_res) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot allocate interrupt\n"); return (ENXIO); } if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, am335x_lcd_intr, sc, &sc->sc_intr_hl) != 0) { bus_release_resource(dev, SYS_RES_IRQ, rid, sc->sc_irq_res); bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->sc_mem_res); device_printf(dev, "Unable to setup the irq handler.\n"); return (ENXIO); } LCD_LOCK_INIT(sc); /* Init backlight interface */ ctx = device_get_sysctl_ctx(sc->sc_dev); tree = device_get_sysctl_tree(sc->sc_dev); sc->sc_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "backlight", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, am335x_lcd_sysctl_backlight, "I", "LCD backlight"); sc->sc_backlight = 0; /* Check if eCAS interface is available at this point */ if (am335x_pwm_config_ecap(PWM_UNIT, PWM_PERIOD, PWM_PERIOD) == 0) sc->sc_backlight = 100; if (panel_node != 0) am335x_lcd_configure(sc); else sc->sc_hdmi_evh = EVENTHANDLER_REGISTER(hdmi_event, am335x_lcd_hdmi_event, sc, EVENTHANDLER_PRI_ANY); return (0); } static int am335x_lcd_detach(device_t dev) { /* Do not let unload driver */ return (EBUSY); } static struct fb_info * am335x_lcd_fb_getinfo(device_t dev) { struct am335x_lcd_softc *sc; sc = device_get_softc(dev); return (&sc->sc_fb_info); } static device_method_t am335x_lcd_methods[] = { DEVMETHOD(device_probe, am335x_lcd_probe), DEVMETHOD(device_attach, am335x_lcd_attach), DEVMETHOD(device_detach, am335x_lcd_detach), /* Framebuffer service methods */ DEVMETHOD(fb_getinfo, am335x_lcd_fb_getinfo), DEVMETHOD_END }; static driver_t am335x_lcd_driver = { "fb", am335x_lcd_methods, sizeof(struct am335x_lcd_softc), }; DRIVER_MODULE(am335x_lcd, simplebus, am335x_lcd_driver, 0, 0); MODULE_VERSION(am335x_lcd, 1); MODULE_DEPEND(am335x_lcd, simplebus, 1, 1, 1); MODULE_DEPEND(am335x_lcd, ti_sysc, 1, 1, 1); diff --git a/sys/arm/ti/am335x/tda19988.c b/sys/arm/ti/am335x/tda19988.c index 8f3a626b7c42..ff3f374a9bcd 100644 --- a/sys/arm/ti/am335x/tda19988.c +++ b/sys/arm/ti/am335x/tda19988.c @@ -1,799 +1,799 @@ /*- * Copyright (c) 2015 Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * NXP TDA19988 HDMI encoder */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "iicbus_if.h" -#include "hdmi_if.h" +#include "crtc_if.h" #define MKREG(page, addr) (((page) << 8) | (addr)) #define REGPAGE(reg) (((reg) >> 8) & 0xff) #define REGADDR(reg) ((reg) & 0xff) #define TDA_VERSION MKREG(0x00, 0x00) #define TDA_MAIN_CNTRL0 MKREG(0x00, 0x01) #define MAIN_CNTRL0_SR (1 << 0) #define TDA_VERSION_MSB MKREG(0x00, 0x02) #define TDA_SOFTRESET MKREG(0x00, 0x0a) #define SOFTRESET_I2C (1 << 1) #define SOFTRESET_AUDIO (1 << 0) #define TDA_DDC_CTRL MKREG(0x00, 0x0b) #define DDC_ENABLE 0 #define TDA_CCLK MKREG(0x00, 0x0c) #define CCLK_ENABLE 1 #define TDA_INT_FLAGS_2 MKREG(0x00, 0x11) #define INT_FLAGS_2_EDID_BLK_RD (1 << 1) #define TDA_VIP_CNTRL_0 MKREG(0x00, 0x20) #define TDA_VIP_CNTRL_1 MKREG(0x00, 0x21) #define TDA_VIP_CNTRL_2 MKREG(0x00, 0x22) #define TDA_VIP_CNTRL_3 MKREG(0x00, 0x23) #define VIP_CNTRL_3_SYNC_HS (2 << 4) #define VIP_CNTRL_3_V_TGL (1 << 2) #define VIP_CNTRL_3_H_TGL (1 << 1) #define TDA_VIP_CNTRL_4 MKREG(0x00, 0x24) #define VIP_CNTRL_4_BLANKIT_NDE (0 << 2) #define VIP_CNTRL_4_BLANKIT_HS_VS (1 << 2) #define VIP_CNTRL_4_BLANKIT_NHS_VS (2 << 2) #define VIP_CNTRL_4_BLANKIT_HE_VE (3 << 2) #define VIP_CNTRL_4_BLC_NONE (0 << 0) #define VIP_CNTRL_4_BLC_RGB444 (1 << 0) #define VIP_CNTRL_4_BLC_YUV444 (2 << 0) #define VIP_CNTRL_4_BLC_YUV422 (3 << 0) #define TDA_VIP_CNTRL_5 MKREG(0x00, 0x25) #define VIP_CNTRL_5_SP_CNT(n) (((n) & 3) << 1) #define TDA_MUX_VP_VIP_OUT MKREG(0x00, 0x27) #define TDA_MAT_CONTRL MKREG(0x00, 0x80) #define MAT_CONTRL_MAT_BP (1 << 2) #define TDA_VIDFORMAT MKREG(0x00, 0xa0) #define TDA_REFPIX_MSB MKREG(0x00, 0xa1) #define TDA_REFPIX_LSB MKREG(0x00, 0xa2) #define TDA_REFLINE_MSB MKREG(0x00, 0xa3) #define TDA_REFLINE_LSB MKREG(0x00, 0xa4) #define TDA_NPIX_MSB MKREG(0x00, 0xa5) #define TDA_NPIX_LSB MKREG(0x00, 0xa6) #define TDA_NLINE_MSB MKREG(0x00, 0xa7) #define TDA_NLINE_LSB MKREG(0x00, 0xa8) #define TDA_VS_LINE_STRT_1_MSB MKREG(0x00, 0xa9) #define TDA_VS_LINE_STRT_1_LSB MKREG(0x00, 0xaa) #define TDA_VS_PIX_STRT_1_MSB MKREG(0x00, 0xab) #define TDA_VS_PIX_STRT_1_LSB MKREG(0x00, 0xac) #define TDA_VS_LINE_END_1_MSB MKREG(0x00, 0xad) #define TDA_VS_LINE_END_1_LSB MKREG(0x00, 0xae) #define TDA_VS_PIX_END_1_MSB MKREG(0x00, 0xaf) #define TDA_VS_PIX_END_1_LSB MKREG(0x00, 0xb0) #define TDA_VS_LINE_STRT_2_MSB MKREG(0x00, 0xb1) #define TDA_VS_LINE_STRT_2_LSB MKREG(0x00, 0xb2) #define TDA_VS_PIX_STRT_2_MSB MKREG(0x00, 0xb3) #define TDA_VS_PIX_STRT_2_LSB MKREG(0x00, 0xb4) #define TDA_VS_LINE_END_2_MSB MKREG(0x00, 0xb5) #define TDA_VS_LINE_END_2_LSB MKREG(0x00, 0xb6) #define TDA_VS_PIX_END_2_MSB MKREG(0x00, 0xb7) #define TDA_VS_PIX_END_2_LSB MKREG(0x00, 0xb8) #define TDA_HS_PIX_START_MSB MKREG(0x00, 0xb9) #define TDA_HS_PIX_START_LSB MKREG(0x00, 0xba) #define TDA_HS_PIX_STOP_MSB MKREG(0x00, 0xbb) #define TDA_HS_PIX_STOP_LSB MKREG(0x00, 0xbc) #define TDA_VWIN_START_1_MSB MKREG(0x00, 0xbd) #define TDA_VWIN_START_1_LSB MKREG(0x00, 0xbe) #define TDA_VWIN_END_1_MSB MKREG(0x00, 0xbf) #define TDA_VWIN_END_1_LSB MKREG(0x00, 0xc0) #define TDA_VWIN_START_2_MSB MKREG(0x00, 0xc1) #define TDA_VWIN_START_2_LSB MKREG(0x00, 0xc2) #define TDA_VWIN_END_2_MSB MKREG(0x00, 0xc3) #define TDA_VWIN_END_2_LSB MKREG(0x00, 0xc4) #define TDA_DE_START_MSB MKREG(0x00, 0xc5) #define TDA_DE_START_LSB MKREG(0x00, 0xc6) #define TDA_DE_STOP_MSB MKREG(0x00, 0xc7) #define TDA_DE_STOP_LSB MKREG(0x00, 0xc8) #define TDA_TBG_CNTRL_0 MKREG(0x00, 0xca) #define TBG_CNTRL_0_SYNC_ONCE (1 << 7) #define TBG_CNTRL_0_SYNC_MTHD (1 << 6) #define TDA_TBG_CNTRL_1 MKREG(0x00, 0xcb) #define TBG_CNTRL_1_DWIN_DIS (1 << 6) #define TBG_CNTRL_1_TGL_EN (1 << 2) #define TBG_CNTRL_1_V_TGL (1 << 1) #define TBG_CNTRL_1_H_TGL (1 << 0) #define TDA_HVF_CNTRL_0 MKREG(0x00, 0xe4) #define HVF_CNTRL_0_PREFIL_NONE (0 << 2) #define HVF_CNTRL_0_INTPOL_BYPASS (0 << 0) #define TDA_HVF_CNTRL_1 MKREG(0x00, 0xe5) #define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) #define HVF_CNTRL_1_VQR_FULL HVF_CNTRL_1_VQR(0) #define TDA_ENABLE_SPACE MKREG(0x00, 0xd6) #define TDA_RPT_CNTRL MKREG(0x00, 0xf0) #define TDA_PLL_SERIAL_1 MKREG(0x02, 0x00) #define PLL_SERIAL_1_SRL_MAN_IP (1 << 6) #define TDA_PLL_SERIAL_2 MKREG(0x02, 0x01) #define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) #define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 0x3) << 0) #define TDA_PLL_SERIAL_3 MKREG(0x02, 0x02) #define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) #define PLL_SERIAL_3_SRL_DE (1 << 2) #define PLL_SERIAL_3_SRL_CCIR (1 << 0) #define TDA_SERIALIZER MKREG(0x02, 0x03) #define TDA_BUFFER_OUT MKREG(0x02, 0x04) #define TDA_PLL_SCG1 MKREG(0x02, 0x05) #define TDA_PLL_SCG2 MKREG(0x02, 0x06) #define TDA_PLL_SCGN1 MKREG(0x02, 0x07) #define TDA_PLL_SCGN2 MKREG(0x02, 0x08) #define TDA_PLL_SCGR1 MKREG(0x02, 0x09) #define TDA_PLL_SCGR2 MKREG(0x02, 0x0a) #define TDA_SEL_CLK MKREG(0x02, 0x11) #define SEL_CLK_ENA_SC_CLK (1 << 3) #define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) #define SEL_CLK_SEL_CLK1 (1 << 0) #define TDA_ANA_GENERAL MKREG(0x02, 0x12) #define TDA_EDID_DATA0 MKREG(0x09, 0x00) #define TDA_EDID_CTRL MKREG(0x09, 0xfa) #define TDA_DDC_ADDR MKREG(0x09, 0xfb) #define TDA_DDC_OFFS MKREG(0x09, 0xfc) #define TDA_DDC_SEGM_ADDR MKREG(0x09, 0xfd) #define TDA_DDC_SEGM MKREG(0x09, 0xfe) #define TDA_IF_VSP MKREG(0x10, 0x20) #define TDA_IF_AVI MKREG(0x10, 0x40) #define TDA_IF_SPD MKREG(0x10, 0x60) #define TDA_IF_AUD MKREG(0x10, 0x80) #define TDA_IF_MPS MKREG(0x10, 0xa0) #define TDA_ENC_CNTRL MKREG(0x11, 0x0d) #define ENC_CNTRL_DVI_MODE (0 << 2) #define ENC_CNTRL_HDMI_MODE (1 << 2) #define TDA_DIP_IF_FLAGS MKREG(0x11, 0x0f) #define DIP_IF_FLAGS_IF5 (1 << 5) #define DIP_IF_FLAGS_IF4 (1 << 4) #define DIP_IF_FLAGS_IF3 (1 << 3) #define DIP_IF_FLAGS_IF2 (1 << 2) /* AVI IF on page 10h */ #define DIP_IF_FLAGS_IF1 (1 << 1) #define TDA_TX3 MKREG(0x12, 0x9a) #define TDA_TX4 MKREG(0x12, 0x9b) #define TX4_PD_RAM (1 << 1) #define TDA_HDCP_TX33 MKREG(0x12, 0xb8) #define HDCP_TX33_HDMI (1 << 1) #define TDA_CURPAGE_ADDR 0xff #define TDA_CEC_ENAMODS 0xff #define ENAMODS_RXSENS (1 << 2) #define ENAMODS_HDMI (1 << 1) #define TDA_CEC_FRO_IM_CLK_CTRL 0xfb #define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) #define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) /* EDID reading */ #define EDID_LENGTH 0x80 #define MAX_READ_ATTEMPTS 100 /* EDID fields */ #define EDID_MODES0 35 #define EDID_MODES1 36 #define EDID_TIMING_START 38 #define EDID_TIMING_END 54 #define EDID_TIMING_X(v) (((v) + 31) * 8) #define EDID_FREQ(v) (((v) & 0x3f) + 60) #define EDID_RATIO(v) (((v) >> 6) & 0x3) #define EDID_RATIO_10x16 0 #define EDID_RATIO_3x4 1 #define EDID_RATIO_4x5 2 #define EDID_RATIO_9x16 3 #define TDA19988 0x0301 struct tda19988_softc { device_t sc_dev; uint32_t sc_addr; uint32_t sc_cec_addr; uint16_t sc_version; int sc_current_page; uint8_t *sc_edid; uint32_t sc_edid_len; }; static int tda19988_set_page(struct tda19988_softc *sc, uint8_t page) { uint8_t addr = TDA_CURPAGE_ADDR; uint8_t cmd[2]; int result; struct iic_msg msg[] = { { sc->sc_addr, IIC_M_WR, 2, cmd }, }; cmd[0] = addr; cmd[1] = page; result = (iicbus_transfer(sc->sc_dev, msg, 1)); if (result) printf("tda19988_set_page failed: %d\n", result); else sc->sc_current_page = page; return (result); } static int tda19988_cec_read(struct tda19988_softc *sc, uint8_t addr, uint8_t *data) { int result; struct iic_msg msg[] = { { sc->sc_cec_addr, IIC_M_WR, 1, &addr }, { sc->sc_cec_addr, IIC_M_RD, 1, data }, }; result = iicbus_transfer(sc->sc_dev, msg, 2); if (result) printf("tda19988_cec_read failed: %d\n", result); return (result); } static int tda19988_cec_write(struct tda19988_softc *sc, uint8_t address, uint8_t data) { uint8_t cmd[2]; int result; struct iic_msg msg[] = { { sc->sc_cec_addr, IIC_M_WR, 2, cmd }, }; cmd[0] = address; cmd[1] = data; result = iicbus_transfer(sc->sc_dev, msg, 1); if (result) printf("tda19988_cec_write failed: %d\n", result); return (result); } static int tda19988_block_read(struct tda19988_softc *sc, uint16_t addr, uint8_t *data, int len) { uint8_t reg; int result; struct iic_msg msg[] = { { sc->sc_addr, IIC_M_WR, 1, ® }, { sc->sc_addr, IIC_M_RD, len, data }, }; reg = REGADDR(addr); if (sc->sc_current_page != REGPAGE(addr)) tda19988_set_page(sc, REGPAGE(addr)); result = (iicbus_transfer(sc->sc_dev, msg, 2)); if (result) device_printf(sc->sc_dev, "tda19988_block_read failed: %d\n", result); return (result); } static int tda19988_reg_read(struct tda19988_softc *sc, uint16_t addr, uint8_t *data) { uint8_t reg; int result; struct iic_msg msg[] = { { sc->sc_addr, IIC_M_WR, 1, ® }, { sc->sc_addr, IIC_M_RD, 1, data }, }; reg = REGADDR(addr); if (sc->sc_current_page != REGPAGE(addr)) tda19988_set_page(sc, REGPAGE(addr)); result = (iicbus_transfer(sc->sc_dev, msg, 2)); if (result) device_printf(sc->sc_dev, "tda19988_reg_read failed: %d\n", result); return (result); } static int tda19988_reg_write(struct tda19988_softc *sc, uint16_t address, uint8_t data) { uint8_t cmd[2]; int result; struct iic_msg msg[] = { { sc->sc_addr, IIC_M_WR, 2, cmd }, }; cmd[0] = REGADDR(address); cmd[1] = data; if (sc->sc_current_page != REGPAGE(address)) tda19988_set_page(sc, REGPAGE(address)); result = iicbus_transfer(sc->sc_dev, msg, 1); if (result) device_printf(sc->sc_dev, "tda19988_reg_write failed: %d\n", result); return (result); } static int tda19988_reg_write2(struct tda19988_softc *sc, uint16_t address, uint16_t data) { uint8_t cmd[3]; int result; struct iic_msg msg[] = { { sc->sc_addr, IIC_M_WR, 3, cmd }, }; cmd[0] = REGADDR(address); cmd[1] = (data >> 8); cmd[2] = (data & 0xff); if (sc->sc_current_page != REGPAGE(address)) tda19988_set_page(sc, REGPAGE(address)); result = iicbus_transfer(sc->sc_dev, msg, 1); if (result) device_printf(sc->sc_dev, "tda19988_reg_write2 failed: %d\n", result); return (result); } static void tda19988_reg_set(struct tda19988_softc *sc, uint16_t addr, uint8_t flags) { uint8_t data; tda19988_reg_read(sc, addr, &data); data |= flags; tda19988_reg_write(sc, addr, data); } static void tda19988_reg_clear(struct tda19988_softc *sc, uint16_t addr, uint8_t flags) { uint8_t data; tda19988_reg_read(sc, addr, &data); data &= ~flags; tda19988_reg_write(sc, addr, data); } static int tda19988_probe(device_t dev) { if (!ofw_bus_is_compatible(dev, "nxp,tda998x")) return (ENXIO); return (BUS_PROBE_DEFAULT); } static void tda19988_init_encoder(struct tda19988_softc *sc, const struct videomode *mode) { uint16_t ref_pix, ref_line, n_pix, n_line; uint16_t hs_pix_start, hs_pix_stop; uint16_t vs1_pix_start, vs1_pix_stop; uint16_t vs1_line_start, vs1_line_end; uint16_t vs2_pix_start, vs2_pix_stop; uint16_t vs2_line_start, vs2_line_end; uint16_t vwin1_line_start, vwin1_line_end; uint16_t vwin2_line_start, vwin2_line_end; uint16_t de_start, de_stop; uint8_t reg, div; n_pix = mode->htotal; n_line = mode->vtotal; hs_pix_stop = mode->hsync_end - mode->hdisplay; hs_pix_start = mode->hsync_start - mode->hdisplay; de_stop = mode->htotal; de_start = mode->htotal - mode->hdisplay; ref_pix = hs_pix_start + 3; if (mode->flags & VID_HSKEW) ref_pix += mode->hskew; if ((mode->flags & VID_INTERLACE) == 0) { ref_line = 1 + mode->vsync_start - mode->vdisplay; vwin1_line_start = mode->vtotal - mode->vdisplay - 1; vwin1_line_end = vwin1_line_start + mode->vdisplay; vs1_pix_start = vs1_pix_stop = hs_pix_start; vs1_line_start = mode->vsync_start - mode->vdisplay; vs1_line_end = vs1_line_start + mode->vsync_end - mode->vsync_start; vwin2_line_start = vwin2_line_end = 0; vs2_pix_start = vs2_pix_stop = 0; vs2_line_start = vs2_line_end = 0; } else { ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; vwin1_line_start = (mode->vtotal - mode->vdisplay)/2; vwin1_line_end = vwin1_line_start + mode->vdisplay/2; vs1_pix_start = vs1_pix_stop = hs_pix_start; vs1_line_start = (mode->vsync_start - mode->vdisplay)/2; vs1_line_end = vs1_line_start + (mode->vsync_end - mode->vsync_start)/2; vwin2_line_start = vwin1_line_start + mode->vtotal/2; vwin2_line_end = vwin2_line_start + mode->vdisplay/2; vs2_pix_start = vs2_pix_stop = hs_pix_start + mode->htotal/2; vs2_line_start = vs1_line_start + mode->vtotal/2 ; vs2_line_end = vs2_line_start + (mode->vsync_end - mode->vsync_start)/2; } div = 148500 / mode->dot_clock; if (div != 0) { div--; if (div > 3) div = 3; } /* set HDMI HDCP mode off */ tda19988_reg_set(sc, TDA_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); tda19988_reg_clear(sc, TDA_HDCP_TX33, HDCP_TX33_HDMI); tda19988_reg_write(sc, TDA_ENC_CNTRL, ENC_CNTRL_DVI_MODE); /* no pre-filter or interpolator */ tda19988_reg_write(sc, TDA_HVF_CNTRL_0, HVF_CNTRL_0_INTPOL_BYPASS | HVF_CNTRL_0_PREFIL_NONE); tda19988_reg_write(sc, TDA_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); tda19988_reg_write(sc, TDA_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT_NDE | VIP_CNTRL_4_BLC_NONE); tda19988_reg_clear(sc, TDA_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR); tda19988_reg_clear(sc, TDA_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IP); tda19988_reg_clear(sc, TDA_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE); tda19988_reg_write(sc, TDA_SERIALIZER, 0); tda19988_reg_write(sc, TDA_HVF_CNTRL_1, HVF_CNTRL_1_VQR_FULL); tda19988_reg_write(sc, TDA_RPT_CNTRL, 0); tda19988_reg_write(sc, TDA_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); tda19988_reg_write(sc, TDA_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | PLL_SERIAL_2_SRL_PR(0)); tda19988_reg_set(sc, TDA_MAT_CONTRL, MAT_CONTRL_MAT_BP); tda19988_reg_write(sc, TDA_ANA_GENERAL, 0x09); tda19988_reg_clear(sc, TDA_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD); /* * Sync on rising HSYNC/VSYNC */ reg = VIP_CNTRL_3_SYNC_HS; if (mode->flags & VID_NHSYNC) reg |= VIP_CNTRL_3_H_TGL; if (mode->flags & VID_NVSYNC) reg |= VIP_CNTRL_3_V_TGL; tda19988_reg_write(sc, TDA_VIP_CNTRL_3, reg); reg = TBG_CNTRL_1_TGL_EN; if (mode->flags & VID_NHSYNC) reg |= TBG_CNTRL_1_H_TGL; if (mode->flags & VID_NVSYNC) reg |= TBG_CNTRL_1_V_TGL; tda19988_reg_write(sc, TDA_TBG_CNTRL_1, reg); /* Program timing */ tda19988_reg_write(sc, TDA_VIDFORMAT, 0x00); tda19988_reg_write2(sc, TDA_REFPIX_MSB, ref_pix); tda19988_reg_write2(sc, TDA_REFLINE_MSB, ref_line); tda19988_reg_write2(sc, TDA_NPIX_MSB, n_pix); tda19988_reg_write2(sc, TDA_NLINE_MSB, n_line); tda19988_reg_write2(sc, TDA_VS_LINE_STRT_1_MSB, vs1_line_start); tda19988_reg_write2(sc, TDA_VS_PIX_STRT_1_MSB, vs1_pix_start); tda19988_reg_write2(sc, TDA_VS_LINE_END_1_MSB, vs1_line_end); tda19988_reg_write2(sc, TDA_VS_PIX_END_1_MSB, vs1_pix_stop); tda19988_reg_write2(sc, TDA_VS_LINE_STRT_2_MSB, vs2_line_start); tda19988_reg_write2(sc, TDA_VS_PIX_STRT_2_MSB, vs2_pix_start); tda19988_reg_write2(sc, TDA_VS_LINE_END_2_MSB, vs2_line_end); tda19988_reg_write2(sc, TDA_VS_PIX_END_2_MSB, vs2_pix_stop); tda19988_reg_write2(sc, TDA_HS_PIX_START_MSB, hs_pix_start); tda19988_reg_write2(sc, TDA_HS_PIX_STOP_MSB, hs_pix_stop); tda19988_reg_write2(sc, TDA_VWIN_START_1_MSB, vwin1_line_start); tda19988_reg_write2(sc, TDA_VWIN_END_1_MSB, vwin1_line_end); tda19988_reg_write2(sc, TDA_VWIN_START_2_MSB, vwin2_line_start); tda19988_reg_write2(sc, TDA_VWIN_END_2_MSB, vwin2_line_end); tda19988_reg_write2(sc, TDA_DE_START_MSB, de_start); tda19988_reg_write2(sc, TDA_DE_STOP_MSB, de_stop); if (sc->sc_version == TDA19988) tda19988_reg_write(sc, TDA_ENABLE_SPACE, 0x00); /* must be last register set */ tda19988_reg_clear(sc, TDA_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); } static int tda19988_read_edid_block(struct tda19988_softc *sc, uint8_t *buf, int block) { int attempt, err; uint8_t data; err = 0; tda19988_reg_set(sc, TDA_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); /* Block 0 */ tda19988_reg_write(sc, TDA_DDC_ADDR, 0xa0); tda19988_reg_write(sc, TDA_DDC_OFFS, (block % 2) ? 128 : 0); tda19988_reg_write(sc, TDA_DDC_SEGM_ADDR, 0x60); tda19988_reg_write(sc, TDA_DDC_SEGM, block / 2); tda19988_reg_write(sc, TDA_EDID_CTRL, 1); tda19988_reg_write(sc, TDA_EDID_CTRL, 0); data = 0; for (attempt = 0; attempt < MAX_READ_ATTEMPTS; attempt++) { tda19988_reg_read(sc, TDA_INT_FLAGS_2, &data); if (data & INT_FLAGS_2_EDID_BLK_RD) break; pause("EDID", 1); } if (attempt == MAX_READ_ATTEMPTS) { err = -1; goto done; } if (tda19988_block_read(sc, TDA_EDID_DATA0, buf, EDID_LENGTH) != 0) { err = -1; goto done; } done: tda19988_reg_clear(sc, TDA_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); return (err); } static int tda19988_read_edid(struct tda19988_softc *sc) { int err; int blocks, i; uint8_t *buf; err = 0; if (sc->sc_version == TDA19988) tda19988_reg_clear(sc, TDA_TX4, TX4_PD_RAM); err = tda19988_read_edid_block(sc, sc->sc_edid, 0); if (err) goto done; blocks = sc->sc_edid[0x7e]; if (blocks > 0) { sc->sc_edid = realloc(sc->sc_edid, EDID_LENGTH*(blocks+1), M_DEVBUF, M_WAITOK); sc->sc_edid_len = EDID_LENGTH*(blocks+1); for (i = 0; i < blocks; i++) { /* TODO: check validity */ buf = sc->sc_edid + EDID_LENGTH*(i+1); err = tda19988_read_edid_block(sc, buf, i); if (err) goto done; } } EVENTHANDLER_INVOKE(hdmi_event, sc->sc_dev, HDMI_EVENT_CONNECTED); done: if (sc->sc_version == TDA19988) tda19988_reg_set(sc, TDA_TX4, TX4_PD_RAM); return (err); } static void tda19988_start(struct tda19988_softc *sc) { device_t dev; uint8_t data; uint16_t version; dev = sc->sc_dev; tda19988_cec_write(sc, TDA_CEC_ENAMODS, ENAMODS_RXSENS | ENAMODS_HDMI); DELAY(1000); tda19988_cec_read(sc, 0xfe, &data); /* Reset core */ tda19988_reg_set(sc, TDA_SOFTRESET, 3); DELAY(100); tda19988_reg_clear(sc, TDA_SOFTRESET, 3); DELAY(100); /* reset transmitter: */ tda19988_reg_set(sc, TDA_MAIN_CNTRL0, MAIN_CNTRL0_SR); tda19988_reg_clear(sc, TDA_MAIN_CNTRL0, MAIN_CNTRL0_SR); /* PLL registers common configuration */ tda19988_reg_write(sc, TDA_PLL_SERIAL_1, 0x00); tda19988_reg_write(sc, TDA_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); tda19988_reg_write(sc, TDA_PLL_SERIAL_3, 0x00); tda19988_reg_write(sc, TDA_SERIALIZER, 0x00); tda19988_reg_write(sc, TDA_BUFFER_OUT, 0x00); tda19988_reg_write(sc, TDA_PLL_SCG1, 0x00); tda19988_reg_write(sc, TDA_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); tda19988_reg_write(sc, TDA_PLL_SCGN1, 0xfa); tda19988_reg_write(sc, TDA_PLL_SCGN2, 0x00); tda19988_reg_write(sc, TDA_PLL_SCGR1, 0x5b); tda19988_reg_write(sc, TDA_PLL_SCGR2, 0x00); tda19988_reg_write(sc, TDA_PLL_SCG2, 0x10); /* Write the default value MUX register */ tda19988_reg_write(sc, TDA_MUX_VP_VIP_OUT, 0x24); version = 0; tda19988_reg_read(sc, TDA_VERSION, &data); version |= data; tda19988_reg_read(sc, TDA_VERSION_MSB, &data); version |= (data << 8); /* Clear feature bits */ sc->sc_version = version & ~0x30; switch (sc->sc_version) { case TDA19988: device_printf(dev, "TDA19988\n"); break; default: device_printf(dev, "Unknown device: %04x\n", sc->sc_version); return; } tda19988_reg_write(sc, TDA_DDC_CTRL, DDC_ENABLE); tda19988_reg_write(sc, TDA_TX3, 39); tda19988_cec_write(sc, TDA_CEC_FRO_IM_CLK_CTRL, CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); if (tda19988_read_edid(sc) < 0) { device_printf(dev, "failed to read EDID\n"); return; } /* Default values for RGB 4:4:4 mapping */ tda19988_reg_write(sc, TDA_VIP_CNTRL_0, 0x23); tda19988_reg_write(sc, TDA_VIP_CNTRL_1, 0x01); tda19988_reg_write(sc, TDA_VIP_CNTRL_2, 0x45); } static int tda19988_attach(device_t dev) { struct tda19988_softc *sc; phandle_t node; sc = device_get_softc(dev); sc->sc_dev = dev; sc->sc_addr = iicbus_get_addr(dev); sc->sc_cec_addr = (0x34 << 1); /* hardcoded */ sc->sc_edid = malloc(EDID_LENGTH, M_DEVBUF, M_WAITOK | M_ZERO); sc->sc_edid_len = EDID_LENGTH; device_set_desc(dev, "NXP TDA19988 HDMI transmitter"); node = ofw_bus_get_node(dev); OF_device_register_xref(OF_xref_from_node(node), dev); tda19988_start(sc); return (0); } static int tda19988_detach(device_t dev) { /* XXX: Do not let unload drive */ return (EBUSY); } static int tda19988_get_edid(device_t dev, uint8_t **edid, uint32_t *edid_len) { struct tda19988_softc *sc; sc = device_get_softc(dev); if (sc->sc_edid) { *edid = sc->sc_edid; *edid_len = sc->sc_edid_len; } else return (ENXIO); return (0); } static int tda19988_set_videomode(device_t dev, const struct videomode *mode) { struct tda19988_softc *sc; sc = device_get_softc(dev); tda19988_init_encoder(sc, mode); return (0); } static device_method_t tda_methods[] = { DEVMETHOD(device_probe, tda19988_probe), DEVMETHOD(device_attach, tda19988_attach), DEVMETHOD(device_detach, tda19988_detach), - /* HDMI methods */ - DEVMETHOD(hdmi_get_edid, tda19988_get_edid), - DEVMETHOD(hdmi_set_videomode, tda19988_set_videomode), + /* CRTC methods */ + DEVMETHOD(crtc_get_edid, tda19988_get_edid), + DEVMETHOD(crtc_set_videomode, tda19988_set_videomode), {0, 0}, }; static driver_t tda_driver = { "tda", tda_methods, sizeof(struct tda19988_softc), }; DRIVER_MODULE(tda, iicbus, tda_driver, 0, 0); MODULE_VERSION(tda, 1); MODULE_DEPEND(tda, iicbus, 1, 1, 1); diff --git a/sys/conf/files.arm b/sys/conf/files.arm index de7dfdffa591..d236c083cc43 100644 --- a/sys/conf/files.arm +++ b/sys/conf/files.arm @@ -1,139 +1,139 @@ # $FreeBSD$ arm/arm/autoconf.c standard arm/arm/bcopy_page.S standard arm/arm/bcopyinout.S standard arm/arm/blockio.S standard arm/arm/bus_space_asm_generic.S standard arm/arm/bus_space_base.c optional fdt arm/arm/bus_space_generic.c standard arm/arm/busdma_machdep.c standard arm/arm/copystr.S standard arm/arm/cpufunc.c standard arm/arm/cpufunc_asm.S standard arm/arm/cpufunc_asm_arm11x6.S optional cpu_arm1176 arm/arm/cpufunc_asm_armv7.S optional cpu_cortexa | cpu_krait | cpu_mv_pj4b arm/arm/cpufunc_asm_pj4b.S optional cpu_mv_pj4b arm/arm/cpuinfo.c standard arm/arm/cpu_asm-v6.S standard arm/arm/db_disasm.c optional ddb arm/arm/db_interface.c optional ddb arm/arm/db_trace.c optional ddb arm/arm/debug_monitor.c optional ddb | gdb arm/arm/disassem.c optional ddb arm/arm/dump_machdep.c standard arm/arm/elf_machdep.c standard arm/arm/elf_note.S standard arm/arm/exception.S standard arm/arm/exec_machdep.c standard arm/arm/fiq.c standard arm/arm/fiq_subr.S standard arm/arm/fusu.S standard arm/arm/gdb_machdep.c optional gdb arm/arm/generic_timer.c optional generic_timer arm/arm/gic.c optional gic arm/arm/gic_fdt.c optional gic fdt arm/arm/gic_if.m optional gic arm/arm/identcpu-v6.c standard arm/arm/in_cksum_arm.S optional inet | inet6 arm/arm/in_cksum_machdep.c optional inet | inet6 kern/subr_intr.c standard arm/arm/locore.S standard no-obj arm/arm/hypervisor-stub.S standard arm/arm/machdep.c standard arm/arm/machdep_boot.c standard arm/arm/machdep_kdb.c standard arm/arm/machdep_intr.c standard arm/arm/machdep_ptrace.c standard arm/arm/mem.c optional mem arm/arm/minidump_machdep.c standard arm/arm/mp_machdep.c optional smp arm/arm/mpcore_timer.c optional mpcore_timer arm/arm/nexus.c standard arm/arm/ofw_machdep.c optional fdt arm/arm/pl190.c optional pl190 arm/arm/pl310.c optional pl310 arm/arm/platform.c optional platform arm/arm/platform_if.m optional platform arm/arm/platform_pl310_if.m optional platform pl310 arm/arm/pmap-v6.c standard arm/arm/pmu.c optional pmu | hwpmc arm/arm/pmu_fdt.c optional fdt pmu | fdt hwpmc arm/arm/ptrace_machdep.c standard arm/arm/sc_machdep.c optional sc arm/arm/setcpsr.S standard arm/arm/setstack.S standard arm/arm/stack_machdep.c optional ddb | stack arm/arm/stdatomic.c standard \ compile-with "${NORMAL_C:N-Wmissing-prototypes}" arm/arm/support.S standard arm/arm/swtch.S standard arm/arm/swtch-v6.S standard arm/arm/sys_machdep.c standard arm/arm/syscall.c standard arm/arm/trap-v6.c standard arm/arm/uio_machdep.c standard arm/arm/undefined.c standard arm/arm/unwind.c optional ddb | kdtrace_hooks | stack arm/arm/vm_machdep.c standard arm/arm/vfp.c standard cddl/dev/dtrace/arm/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/arm/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/arm/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" crypto/des/des_enc.c optional netsmb dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/dwc/if_dwc.c optional dwc dev/dwc/if_dwc_if.m optional dwc dev/fb/fb.c optional sc dev/fdt/fdt_arm_platform.c optional platform fdt -dev/hdmi/hdmi_if.m optional hdmi +dev/video/crtc_if.m optional vt dev/hwpmc/hwpmc_arm.c optional hwpmc dev/hwpmc/hwpmc_armv7.c optional hwpmc dev/iicbus/twsi/twsi.c optional twsi dev/ofw/ofw_pcib.c optional fdt pci dev/pci/pci_host_generic.c optional pci_host_generic pci dev/pci/pci_host_generic_fdt.c optional pci_host_generic pci fdt dev/psci/psci.c optional psci dev/psci/smccc_arm.S optional psci dev/syscons/scgfbrndr.c optional sc dev/uart/uart_cpu_fdt.c optional uart fdt dev/usb/controller/dwc3.c optional fdt dwc3 dev/usb/controller/generic_xhci.c optional xhci dev/usb/controller/generic_xhci_fdt.c optional xhci fdt kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_busdma_bufalloc.c standard kern/subr_devmap.c standard kern/subr_physmem.c standard kern/subr_sfbuf.c standard libkern/arm/aeabi_unwind.c standard libkern/arm/divsi3.S standard libkern/arm/ldivmod.S standard libkern/arm/ldivmod_helper.c standard libkern/arm/memclr.S standard libkern/arm/memcpy.S standard libkern/arm/memset.S standard libkern/arm/muldi3.c standard libkern/ashldi3.c standard libkern/ashrdi3.c standard libkern/divdi3.c standard libkern/lshrdi3.c standard libkern/moddi3.c standard libkern/qdivrem.c standard libkern/strcmp.c standard libkern/strlen.c standard libkern/strncmp.c standard libkern/ucmpdi2.c standard libkern/udivdi3.c standard libkern/umoddi3.c standard # Annapurna support arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${.IMPSRC}" diff --git a/sys/dev/hdmi/dwc_hdmi.c b/sys/dev/hdmi/dwc_hdmi.c index 0f1388874292..52b0045a00ee 100644 --- a/sys/dev/hdmi/dwc_hdmi.c +++ b/sys/dev/hdmi/dwc_hdmi.c @@ -1,856 +1,856 @@ /*- * Copyright (c) 2015 Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * HDMI core module */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include "hdmi_if.h" +#include "crtc_if.h" #define I2C_DDC_ADDR (0x50 << 1) #define I2C_DDC_SEGADDR (0x30 << 1) #define EDID_LENGTH 0x80 #define EXT_TAG 0x00 #define CEA_TAG_ID 0x02 #define CEA_DTD 0x03 #define DTD_BASIC_AUDIO (1 << 6) #define CEA_REV 0x02 #define CEA_DATA_OFF 0x03 #define CEA_DATA_START 4 #define BLOCK_TAG(x) (((x) >> 5) & 0x7) #define BLOCK_TAG_VSDB 3 #define BLOCK_LEN(x) ((x) & 0x1f) #define HDMI_VSDB_MINLEN 5 #define HDMI_OUI "\x03\x0c\x00" #define HDMI_OUI_LEN 3 static void dwc_hdmi_phy_wait_i2c_done(struct dwc_hdmi_softc *sc, int msec) { uint8_t val; val = RD1(sc, HDMI_IH_I2CMPHY_STAT0) & (HDMI_IH_I2CMPHY_STAT0_DONE | HDMI_IH_I2CMPHY_STAT0_ERROR); while (val == 0) { pause("HDMI_PHY", hz/100); msec -= 10; if (msec <= 0) return; val = RD1(sc, HDMI_IH_I2CMPHY_STAT0) & (HDMI_IH_I2CMPHY_STAT0_DONE | HDMI_IH_I2CMPHY_STAT0_ERROR); } } static void dwc_hdmi_phy_i2c_write(struct dwc_hdmi_softc *sc, unsigned short data, unsigned char addr) { /* clear DONE and ERROR flags */ WR1(sc, HDMI_IH_I2CMPHY_STAT0, HDMI_IH_I2CMPHY_STAT0_DONE | HDMI_IH_I2CMPHY_STAT0_ERROR); WR1(sc, HDMI_PHY_I2CM_ADDRESS_ADDR, addr); WR1(sc, HDMI_PHY_I2CM_DATAO_1_ADDR, ((data >> 8) & 0xff)); WR1(sc, HDMI_PHY_I2CM_DATAO_0_ADDR, ((data >> 0) & 0xff)); WR1(sc, HDMI_PHY_I2CM_OPERATION_ADDR, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE); dwc_hdmi_phy_wait_i2c_done(sc, 1000); } static void dwc_hdmi_disable_overflow_interrupts(struct dwc_hdmi_softc *sc) { WR1(sc, HDMI_IH_MUTE_FC_STAT2, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK); WR1(sc, HDMI_FC_MASK2, HDMI_FC_MASK2_LOW_PRI | HDMI_FC_MASK2_HIGH_PRI); } static void dwc_hdmi_av_composer(struct dwc_hdmi_softc *sc) { uint8_t inv_val; int is_dvi; int hblank, vblank, hsync_len, hfp, vfp; /* Set up HDMI_FC_INVIDCONF */ inv_val = ((sc->sc_mode.flags & VID_PVSYNC) ? HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW); inv_val |= ((sc->sc_mode.flags & VID_PHSYNC) ? HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW); inv_val |= HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH; inv_val |= ((sc->sc_mode.flags & VID_INTERLACE) ? HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW); inv_val |= ((sc->sc_mode.flags & VID_INTERLACE) ? HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE); /* TODO: implement HDMI part */ is_dvi = sc->sc_has_audio == 0; inv_val |= (is_dvi ? HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE : HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE); WR1(sc, HDMI_FC_INVIDCONF, inv_val); /* Set up horizontal active pixel region width */ WR1(sc, HDMI_FC_INHACTV1, sc->sc_mode.hdisplay >> 8); WR1(sc, HDMI_FC_INHACTV0, sc->sc_mode.hdisplay); /* Set up vertical blanking pixel region width */ WR1(sc, HDMI_FC_INVACTV1, sc->sc_mode.vdisplay >> 8); WR1(sc, HDMI_FC_INVACTV0, sc->sc_mode.vdisplay); /* Set up horizontal blanking pixel region width */ hblank = sc->sc_mode.htotal - sc->sc_mode.hdisplay; WR1(sc, HDMI_FC_INHBLANK1, hblank >> 8); WR1(sc, HDMI_FC_INHBLANK0, hblank); /* Set up vertical blanking pixel region width */ vblank = sc->sc_mode.vtotal - sc->sc_mode.vdisplay; WR1(sc, HDMI_FC_INVBLANK, vblank); /* Set up HSYNC active edge delay width (in pixel clks) */ hfp = sc->sc_mode.hsync_start - sc->sc_mode.hdisplay; WR1(sc, HDMI_FC_HSYNCINDELAY1, hfp >> 8); WR1(sc, HDMI_FC_HSYNCINDELAY0, hfp); /* Set up VSYNC active edge delay (in pixel clks) */ vfp = sc->sc_mode.vsync_start - sc->sc_mode.vdisplay; WR1(sc, HDMI_FC_VSYNCINDELAY, vfp); hsync_len = (sc->sc_mode.hsync_end - sc->sc_mode.hsync_start); /* Set up HSYNC active pulse width (in pixel clks) */ WR1(sc, HDMI_FC_HSYNCINWIDTH1, hsync_len >> 8); WR1(sc, HDMI_FC_HSYNCINWIDTH0, hsync_len); /* Set up VSYNC active edge delay (in pixel clks) */ WR1(sc, HDMI_FC_VSYNCINWIDTH, (sc->sc_mode.vsync_end - sc->sc_mode.vsync_start)); } static void dwc_hdmi_phy_enable_power(struct dwc_hdmi_softc *sc, uint8_t enable) { uint8_t reg; reg = RD1(sc, HDMI_PHY_CONF0); reg &= ~HDMI_PHY_CONF0_PDZ_MASK; reg |= (enable << HDMI_PHY_CONF0_PDZ_OFFSET); WR1(sc, HDMI_PHY_CONF0, reg); } static void dwc_hdmi_phy_enable_tmds(struct dwc_hdmi_softc *sc, uint8_t enable) { uint8_t reg; reg = RD1(sc, HDMI_PHY_CONF0); reg &= ~HDMI_PHY_CONF0_ENTMDS_MASK; reg |= (enable << HDMI_PHY_CONF0_ENTMDS_OFFSET); WR1(sc, HDMI_PHY_CONF0, reg); } static void dwc_hdmi_phy_gen2_pddq(struct dwc_hdmi_softc *sc, uint8_t enable) { uint8_t reg; reg = RD1(sc, HDMI_PHY_CONF0); reg &= ~HDMI_PHY_CONF0_GEN2_PDDQ_MASK; reg |= (enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET); WR1(sc, HDMI_PHY_CONF0, reg); } static void dwc_hdmi_phy_gen2_txpwron(struct dwc_hdmi_softc *sc, uint8_t enable) { uint8_t reg; reg = RD1(sc, HDMI_PHY_CONF0); reg &= ~HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; reg |= (enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET); WR1(sc, HDMI_PHY_CONF0, reg); } static void dwc_hdmi_phy_sel_data_en_pol(struct dwc_hdmi_softc *sc, uint8_t enable) { uint8_t reg; reg = RD1(sc, HDMI_PHY_CONF0); reg &= ~HDMI_PHY_CONF0_SELDATAENPOL_MASK; reg |= (enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET); WR1(sc, HDMI_PHY_CONF0, reg); } static void dwc_hdmi_phy_sel_interface_control(struct dwc_hdmi_softc *sc, uint8_t enable) { uint8_t reg; reg = RD1(sc, HDMI_PHY_CONF0); reg &= ~HDMI_PHY_CONF0_SELDIPIF_MASK; reg |= (enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET); WR1(sc, HDMI_PHY_CONF0, reg); } static inline void dwc_hdmi_phy_test_clear(struct dwc_hdmi_softc *sc, unsigned char bit) { uint8_t val; val = RD1(sc, HDMI_PHY_TST0); val &= ~HDMI_PHY_TST0_TSTCLR_MASK; val |= (bit << HDMI_PHY_TST0_TSTCLR_OFFSET) & HDMI_PHY_TST0_TSTCLR_MASK; WR1(sc, HDMI_PHY_TST0, val); } static void dwc_hdmi_clear_overflow(struct dwc_hdmi_softc *sc) { int count; uint8_t val; /* TMDS software reset */ WR1(sc, HDMI_MC_SWRSTZ, (uint8_t)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ); val = RD1(sc, HDMI_FC_INVIDCONF); for (count = 0 ; count < 4 ; count++) WR1(sc, HDMI_FC_INVIDCONF, val); } static int dwc_hdmi_phy_configure(struct dwc_hdmi_softc *sc) { uint8_t val; uint8_t msec; WR1(sc, HDMI_MC_FLOWCTRL, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS); /* gen2 tx power off */ dwc_hdmi_phy_gen2_txpwron(sc, 0); /* gen2 pddq */ dwc_hdmi_phy_gen2_pddq(sc, 1); /* PHY reset */ WR1(sc, HDMI_MC_PHYRSTZ, HDMI_MC_PHYRSTZ_DEASSERT); WR1(sc, HDMI_MC_PHYRSTZ, HDMI_MC_PHYRSTZ_ASSERT); WR1(sc, HDMI_MC_HEACPHY_RST, HDMI_MC_HEACPHY_RST_ASSERT); dwc_hdmi_phy_test_clear(sc, 1); WR1(sc, HDMI_PHY_I2CM_SLAVE_ADDR, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); dwc_hdmi_phy_test_clear(sc, 0); /* * Following initialization are for 8bit per color case */ /* * PLL/MPLL config, see section 24.7.22 in TRM * config, see section 24.7.22 */ if (sc->sc_mode.dot_clock*1000 <= 45250000) { dwc_hdmi_phy_i2c_write(sc, CPCE_CTRL_45_25, HDMI_PHY_I2C_CPCE_CTRL); dwc_hdmi_phy_i2c_write(sc, GMPCTRL_45_25, HDMI_PHY_I2C_GMPCTRL); } else if (sc->sc_mode.dot_clock*1000 <= 92500000) { dwc_hdmi_phy_i2c_write(sc, CPCE_CTRL_92_50, HDMI_PHY_I2C_CPCE_CTRL); dwc_hdmi_phy_i2c_write(sc, GMPCTRL_92_50, HDMI_PHY_I2C_GMPCTRL); } else if (sc->sc_mode.dot_clock*1000 <= 185000000) { dwc_hdmi_phy_i2c_write(sc, CPCE_CTRL_185, HDMI_PHY_I2C_CPCE_CTRL); dwc_hdmi_phy_i2c_write(sc, GMPCTRL_185, HDMI_PHY_I2C_GMPCTRL); } else { dwc_hdmi_phy_i2c_write(sc, CPCE_CTRL_370, HDMI_PHY_I2C_CPCE_CTRL); dwc_hdmi_phy_i2c_write(sc, GMPCTRL_370, HDMI_PHY_I2C_GMPCTRL); } /* * Values described in TRM section 34.9.2 PLL/MPLL Generic * Configuration Settings. Table 34-23. */ if (sc->sc_mode.dot_clock*1000 <= 54000000) { dwc_hdmi_phy_i2c_write(sc, 0x091c, HDMI_PHY_I2C_CURRCTRL); } else if (sc->sc_mode.dot_clock*1000 <= 58400000) { dwc_hdmi_phy_i2c_write(sc, 0x091c, HDMI_PHY_I2C_CURRCTRL); } else if (sc->sc_mode.dot_clock*1000 <= 72000000) { dwc_hdmi_phy_i2c_write(sc, 0x06dc, HDMI_PHY_I2C_CURRCTRL); } else if (sc->sc_mode.dot_clock*1000 <= 74250000) { dwc_hdmi_phy_i2c_write(sc, 0x06dc, HDMI_PHY_I2C_CURRCTRL); } else if (sc->sc_mode.dot_clock*1000 <= 118800000) { dwc_hdmi_phy_i2c_write(sc, 0x091c, HDMI_PHY_I2C_CURRCTRL); } else if (sc->sc_mode.dot_clock*1000 <= 216000000) { dwc_hdmi_phy_i2c_write(sc, 0x06dc, HDMI_PHY_I2C_CURRCTRL); } else { panic("Unsupported mode\n"); } dwc_hdmi_phy_i2c_write(sc, 0x0000, HDMI_PHY_I2C_PLLPHBYCTRL); dwc_hdmi_phy_i2c_write(sc, MSM_CTRL_FB_CLK, HDMI_PHY_I2C_MSM_CTRL); /* RESISTANCE TERM 133 Ohm */ dwc_hdmi_phy_i2c_write(sc, TXTERM_133, HDMI_PHY_I2C_TXTERM); /* REMOVE CLK TERM */ dwc_hdmi_phy_i2c_write(sc, CKCALCTRL_OVERRIDE, HDMI_PHY_I2C_CKCALCTRL); if (sc->sc_mode.dot_clock*1000 > 148500000) { dwc_hdmi_phy_i2c_write(sc,CKSYMTXCTRL_OVERRIDE | CKSYMTXCTRL_TX_SYMON | CKSYMTXCTRL_TX_TRBON | CKSYMTXCTRL_TX_CK_SYMON, HDMI_PHY_I2C_CKSYMTXCTRL); dwc_hdmi_phy_i2c_write(sc, VLEVCTRL_TX_LVL(9) | VLEVCTRL_CK_LVL(9), HDMI_PHY_I2C_VLEVCTRL); } else { dwc_hdmi_phy_i2c_write(sc,CKSYMTXCTRL_OVERRIDE | CKSYMTXCTRL_TX_SYMON | CKSYMTXCTRL_TX_TRAON | CKSYMTXCTRL_TX_CK_SYMON, HDMI_PHY_I2C_CKSYMTXCTRL); dwc_hdmi_phy_i2c_write(sc, VLEVCTRL_TX_LVL(13) | VLEVCTRL_CK_LVL(13), HDMI_PHY_I2C_VLEVCTRL); } dwc_hdmi_phy_enable_power(sc, 1); /* toggle TMDS enable */ dwc_hdmi_phy_enable_tmds(sc, 0); dwc_hdmi_phy_enable_tmds(sc, 1); /* gen2 tx power on */ dwc_hdmi_phy_gen2_txpwron(sc, 1); dwc_hdmi_phy_gen2_pddq(sc, 0); /*Wait for PHY PLL lock */ msec = 4; val = RD1(sc, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; while (val == 0) { DELAY(1000); if (msec-- == 0) { device_printf(sc->sc_dev, "PHY PLL not locked\n"); return (-1); } val = RD1(sc, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; } return true; } static void dwc_hdmi_phy_init(struct dwc_hdmi_softc *sc) { int i; /* HDMI Phy spec says to do the phy initialization sequence twice */ for (i = 0 ; i < 2 ; i++) { dwc_hdmi_phy_sel_data_en_pol(sc, 1); dwc_hdmi_phy_sel_interface_control(sc, 0); dwc_hdmi_phy_enable_tmds(sc, 0); dwc_hdmi_phy_enable_power(sc, 0); /* Enable CSC */ dwc_hdmi_phy_configure(sc); } } static void dwc_hdmi_enable_video_path(struct dwc_hdmi_softc *sc) { uint8_t clkdis; /* * Control period timing * Values are minimal according to HDMI spec 1.4a */ WR1(sc, HDMI_FC_CTRLDUR, 12); WR1(sc, HDMI_FC_EXCTRLDUR, 32); WR1(sc, HDMI_FC_EXCTRLSPAC, 1); /* * Bits to fill data lines not used to transmit preamble * for channels 0, 1, and 2 respectively */ WR1(sc, HDMI_FC_CH0PREAM, 0x0B); WR1(sc, HDMI_FC_CH1PREAM, 0x16); WR1(sc, HDMI_FC_CH2PREAM, 0x21); /* Save CEC clock */ clkdis = RD1(sc, HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_CECCLK_DISABLE; clkdis |= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; /* Enable pixel clock and tmds data path */ clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; WR1(sc, HDMI_MC_CLKDIS, clkdis); clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; WR1(sc, HDMI_MC_CLKDIS, clkdis); } static void dwc_hdmi_configure_audio(struct dwc_hdmi_softc *sc) { unsigned int n; uint8_t val; if (sc->sc_has_audio == 0) return; /* The following values are for 48 kHz */ switch (sc->sc_mode.dot_clock) { case 25170: n = 6864; break; case 27020: n = 6144; break; case 74170: n = 11648; break; case 148350: n = 5824; break; default: n = 6144; break; } WR1(sc, HDMI_AUD_N1, (n >> 0) & 0xff); WR1(sc, HDMI_AUD_N2, (n >> 8) & 0xff); WR1(sc, HDMI_AUD_N3, (n >> 16) & 0xff); val = RD1(sc, HDMI_AUD_CTS3); val &= ~(HDMI_AUD_CTS3_N_SHIFT_MASK | HDMI_AUD_CTS3_CTS_MANUAL); WR1(sc, HDMI_AUD_CTS3, val); val = RD1(sc, HDMI_AUD_CONF0); val &= ~HDMI_AUD_CONF0_INTERFACE_MASK; val |= HDMI_AUD_CONF0_INTERFACE_IIS; val &= ~HDMI_AUD_CONF0_I2SINEN_MASK; val |= HDMI_AUD_CONF0_I2SINEN_CH2; WR1(sc, HDMI_AUD_CONF0, val); val = RD1(sc, HDMI_AUD_CONF1); val &= ~HDMI_AUD_CONF1_DATAMODE_MASK; val |= HDMI_AUD_CONF1_DATAMODE_IIS; val &= ~HDMI_AUD_CONF1_DATWIDTH_MASK; val |= HDMI_AUD_CONF1_DATWIDTH_16BIT; WR1(sc, HDMI_AUD_CONF1, val); WR1(sc, HDMI_AUD_INPUTCLKFS, HDMI_AUD_INPUTCLKFS_64); WR1(sc, HDMI_FC_AUDICONF0, 1 << 4); /* CC=1 */ WR1(sc, HDMI_FC_AUDICONF1, 0); WR1(sc, HDMI_FC_AUDICONF2, 0); /* CA=0 */ WR1(sc, HDMI_FC_AUDICONF3, 0); WR1(sc, HDMI_FC_AUDSV, 0xee); /* channels valid */ /* Enable audio clock */ val = RD1(sc, HDMI_MC_CLKDIS); val &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; WR1(sc, HDMI_MC_CLKDIS, val); } static void dwc_hdmi_video_packetize(struct dwc_hdmi_softc *sc) { unsigned int color_depth = 0; unsigned int remap_size = HDMI_VP_REMAP_YCC422_16BIT; unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; uint8_t val; output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; color_depth = 4; /* set the packetizer registers */ val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & HDMI_VP_PR_CD_COLOR_DEPTH_MASK); WR1(sc, HDMI_VP_PR_CD, val); val = RD1(sc, HDMI_VP_STUFF); val &= ~HDMI_VP_STUFF_PR_STUFFING_MASK; val |= HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE; WR1(sc, HDMI_VP_STUFF, val); val = RD1(sc, HDMI_VP_CONF); val &= ~(HDMI_VP_CONF_PR_EN_MASK | HDMI_VP_CONF_BYPASS_SELECT_MASK); val |= HDMI_VP_CONF_PR_EN_DISABLE | HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; WR1(sc, HDMI_VP_CONF, val); val = RD1(sc, HDMI_VP_STUFF); val &= ~HDMI_VP_STUFF_IDEFAULT_PHASE_MASK; val |= 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET; WR1(sc, HDMI_VP_STUFF, val); WR1(sc, HDMI_VP_REMAP, remap_size); if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { val = RD1(sc, HDMI_VP_CONF); val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK); val |= HDMI_VP_CONF_BYPASS_EN_DISABLE | HDMI_VP_CONF_PP_EN_ENABLE | HDMI_VP_CONF_YCC422_EN_DISABLE; WR1(sc, HDMI_VP_CONF, val); } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { val = RD1(sc, HDMI_VP_CONF); val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK); val |= HDMI_VP_CONF_BYPASS_EN_DISABLE | HDMI_VP_CONF_PP_EN_DISABLE | HDMI_VP_CONF_YCC422_EN_ENABLE; WR1(sc, HDMI_VP_CONF, val); } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { val = RD1(sc, HDMI_VP_CONF); val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK); val |= HDMI_VP_CONF_BYPASS_EN_ENABLE | HDMI_VP_CONF_PP_EN_DISABLE | HDMI_VP_CONF_YCC422_EN_DISABLE; WR1(sc, HDMI_VP_CONF, val); } else { return; } val = RD1(sc, HDMI_VP_STUFF); val &= ~(HDMI_VP_STUFF_PP_STUFFING_MASK | HDMI_VP_STUFF_YCC422_STUFFING_MASK); val |= HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE; WR1(sc, HDMI_VP_STUFF, val); val = RD1(sc, HDMI_VP_CONF); val &= ~HDMI_VP_CONF_OUTPUT_SELECTOR_MASK; val |= output_select; WR1(sc, HDMI_VP_CONF, val); } static void dwc_hdmi_video_sample(struct dwc_hdmi_softc *sc) { int color_format; uint8_t val; color_format = 0x01; val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & HDMI_TX_INVID0_VIDEO_MAPPING_MASK); WR1(sc, HDMI_TX_INVID0, val); /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; WR1(sc, HDMI_TX_INSTUFFING, val); WR1(sc, HDMI_TX_GYDATA0, 0x0); WR1(sc, HDMI_TX_GYDATA1, 0x0); WR1(sc, HDMI_TX_RCRDATA0, 0x0); WR1(sc, HDMI_TX_RCRDATA1, 0x0); WR1(sc, HDMI_TX_BCBDATA0, 0x0); WR1(sc, HDMI_TX_BCBDATA1, 0x0); } static void dwc_hdmi_tx_hdcp_config(struct dwc_hdmi_softc *sc) { uint8_t de, val; de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; /* Disable RX detect */ val = RD1(sc, HDMI_A_HDCPCFG0); val &= ~HDMI_A_HDCPCFG0_RXDETECT_MASK; val |= HDMI_A_HDCPCFG0_RXDETECT_DISABLE; WR1(sc, HDMI_A_HDCPCFG0, val); /* Set polarity */ val = RD1(sc, HDMI_A_VIDPOLCFG); val &= ~HDMI_A_VIDPOLCFG_DATAENPOL_MASK; val |= de; WR1(sc, HDMI_A_VIDPOLCFG, val); /* Disable encryption */ val = RD1(sc, HDMI_A_HDCPCFG1); val &= ~HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK; val |= HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE; WR1(sc, HDMI_A_HDCPCFG1, val); } static int dwc_hdmi_set_mode(struct dwc_hdmi_softc *sc) { /* XXX */ sc->sc_has_audio = 1; dwc_hdmi_disable_overflow_interrupts(sc); dwc_hdmi_av_composer(sc); dwc_hdmi_phy_init(sc); dwc_hdmi_enable_video_path(sc); dwc_hdmi_configure_audio(sc); /* TODO: dwc_hdmi_config_avi(sc); */ dwc_hdmi_video_packetize(sc); /* TODO: dwc_hdmi_video_csc(sc); */ dwc_hdmi_video_sample(sc); dwc_hdmi_tx_hdcp_config(sc); dwc_hdmi_clear_overflow(sc); return (0); } static int hdmi_edid_read(struct dwc_hdmi_softc *sc, int block, uint8_t **edid, uint32_t *edid_len) { device_t i2c_dev; int result; uint8_t addr = block & 1 ? EDID_LENGTH : 0; uint8_t segment = block >> 1; /* * Some devices do not support E-DDC so attempt * writing segment address only if it's neccessary */ unsigned char xfers = segment ? 3 : 2; struct iic_msg msg[] = { { I2C_DDC_SEGADDR, IIC_M_WR, 1, &segment }, { I2C_DDC_ADDR, IIC_M_WR, 1, &addr }, { I2C_DDC_ADDR, IIC_M_RD, EDID_LENGTH, sc->sc_edid } }; *edid = NULL; *edid_len = 0; i2c_dev = NULL; if (sc->sc_get_i2c_dev != NULL) i2c_dev = sc->sc_get_i2c_dev(sc->sc_dev); if (!i2c_dev) { device_printf(sc->sc_dev, "no DDC device found\n"); return (ENXIO); } if (bootverbose) device_printf(sc->sc_dev, "reading EDID from %s, block %d, addr %02x\n", device_get_nameunit(i2c_dev), block, I2C_DDC_ADDR/2); result = iicbus_request_bus(i2c_dev, sc->sc_dev, IIC_INTRWAIT); if (result) { device_printf(sc->sc_dev, "failed to request i2c bus: %d\n", result); return (result); } result = iicbus_transfer(i2c_dev, &msg[3 - xfers], xfers); iicbus_release_bus(i2c_dev, sc->sc_dev); if (result) { device_printf(sc->sc_dev, "i2c transfer failed: %d\n", result); return (result); } else { *edid_len = sc->sc_edid_len; *edid = sc->sc_edid; } return (result); } static void dwc_hdmi_detect_cable(void *arg) { struct dwc_hdmi_softc *sc; uint32_t stat; sc = arg; stat = RD1(sc, HDMI_IH_PHY_STAT0); if ((stat & HDMI_IH_PHY_STAT0_HPD) != 0) { EVENTHANDLER_INVOKE(hdmi_event, sc->sc_dev, HDMI_EVENT_CONNECTED); } /* Finished with the interrupt hook */ config_intrhook_disestablish(&sc->sc_mode_hook); } int dwc_hdmi_init(device_t dev) { struct dwc_hdmi_softc *sc; int err; sc = device_get_softc(dev); err = 0; sc->sc_edid = malloc(EDID_LENGTH, M_DEVBUF, M_WAITOK | M_ZERO); sc->sc_edid_len = EDID_LENGTH; device_printf(sc->sc_dev, "HDMI controller %02x:%02x:%02x:%02x\n", RD1(sc, HDMI_DESIGN_ID), RD1(sc, HDMI_REVISION_ID), RD1(sc, HDMI_PRODUCT_ID0), RD1(sc, HDMI_PRODUCT_ID1)); WR1(sc, HDMI_PHY_POL0, HDMI_PHY_POL0_HPD); WR1(sc, HDMI_IH_PHY_STAT0, HDMI_IH_PHY_STAT0_HPD); sc->sc_mode_hook.ich_func = dwc_hdmi_detect_cable; sc->sc_mode_hook.ich_arg = sc; if (config_intrhook_establish(&sc->sc_mode_hook) != 0) { err = ENOMEM; goto out; } out: if (err != 0) { free(sc->sc_edid, M_DEVBUF); sc->sc_edid = NULL; } return (err); } static int dwc_hdmi_detect_hdmi_vsdb(uint8_t *edid) { int off, p, btag, blen; if (edid[EXT_TAG] != CEA_TAG_ID) return (0); off = edid[CEA_DATA_OFF]; /* CEA data block collection starts at byte 4 */ if (off <= CEA_DATA_START) return (0); /* Parse the CEA data blocks */ for (p = CEA_DATA_START; p < off;) { btag = BLOCK_TAG(edid[p]); blen = BLOCK_LEN(edid[p]); /* Make sure the length is sane */ if (p + blen + 1 > off) break; /* Look for a VSDB with the HDMI 24-bit IEEE registration ID */ if (btag == BLOCK_TAG_VSDB && blen >= HDMI_VSDB_MINLEN && memcmp(&edid[p + 1], HDMI_OUI, HDMI_OUI_LEN) == 0) return (1); /* Next data block */ p += (1 + blen); } /* Not found */ return (0); } static void dwc_hdmi_detect_hdmi(struct dwc_hdmi_softc *sc) { uint8_t *edid; uint32_t edid_len; int block; sc->sc_has_audio = 0; /* Scan through extension blocks, looking for a CEA-861 block */ for (block = 1; block <= sc->sc_edid_info.edid_ext_block_count; block++) { if (hdmi_edid_read(sc, block, &edid, &edid_len) != 0) return; if (dwc_hdmi_detect_hdmi_vsdb(edid) != 0) { if (bootverbose) device_printf(sc->sc_dev, "enabling audio support\n"); sc->sc_has_audio = (edid[CEA_DTD] & DTD_BASIC_AUDIO) != 0; return; } } } int dwc_hdmi_get_edid(device_t dev, uint8_t **edid, uint32_t *edid_len) { struct dwc_hdmi_softc *sc; int error; sc = device_get_softc(dev); memset(&sc->sc_edid_info, 0, sizeof(sc->sc_edid_info)); error = hdmi_edid_read(sc, 0, edid, edid_len); if (error != 0) return (error); edid_parse(*edid, &sc->sc_edid_info); return (0); } int dwc_hdmi_set_videomode(device_t dev, const struct videomode *mode) { struct dwc_hdmi_softc *sc; sc = device_get_softc(dev); memcpy(&sc->sc_mode, mode, sizeof(*mode)); dwc_hdmi_detect_hdmi(sc); dwc_hdmi_set_mode(sc); return (0); } diff --git a/sys/dev/hdmi/dwc_hdmi_fdt.c b/sys/dev/hdmi/dwc_hdmi_fdt.c index 4486e83f1a73..810a1f53e2dc 100644 --- a/sys/dev/hdmi/dwc_hdmi_fdt.c +++ b/sys/dev/hdmi/dwc_hdmi_fdt.c @@ -1,199 +1,199 @@ /*- * Copyright (c) 2015 Oleksandr Tymoshenko * Copyright (c) 2016 Jared McNeill * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * HDMI core module */ #include #include #include #include #include #include #include #include #include #include #include #include #include -#include "hdmi_if.h" +#include "crtc_if.h" struct dwc_hdmi_fdt_softc { struct dwc_hdmi_softc base; clk_t clk_hdmi; clk_t clk_ahb; phandle_t i2c_xref; }; static struct ofw_compat_data compat_data[] = { { "synopsys,dwc-hdmi", 1 }, { NULL, 0 } }; static device_t dwc_hdmi_fdt_get_i2c_dev(device_t dev) { struct dwc_hdmi_fdt_softc *sc; sc = device_get_softc(dev); if (sc->i2c_xref == 0) return (NULL); return (OF_device_from_xref(sc->i2c_xref)); } static int dwc_hdmi_fdt_detach(device_t dev) { struct dwc_hdmi_fdt_softc *sc; sc = device_get_softc(dev); if (sc->clk_ahb != NULL) clk_release(sc->clk_ahb); if (sc->clk_hdmi != NULL) clk_release(sc->clk_hdmi); if (sc->base.sc_mem_res != NULL) bus_release_resource(dev, SYS_RES_MEMORY, sc->base.sc_mem_rid, sc->base.sc_mem_res); return (0); } static int dwc_hdmi_fdt_attach(device_t dev) { struct dwc_hdmi_fdt_softc *sc; phandle_t node, i2c_xref; uint32_t freq; int err; sc = device_get_softc(dev); sc->base.sc_dev = dev; sc->base.sc_get_i2c_dev = dwc_hdmi_fdt_get_i2c_dev; err = 0; /* Allocate memory resources. */ sc->base.sc_mem_rid = 0; sc->base.sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->base.sc_mem_rid, RF_ACTIVE); if (sc->base.sc_mem_res == NULL) { device_printf(dev, "Cannot allocate memory resources\n"); err = ENXIO; goto out; } node = ofw_bus_get_node(dev); if (OF_getencprop(node, "ddc", &i2c_xref, sizeof(i2c_xref)) == -1) sc->i2c_xref = 0; else sc->i2c_xref = i2c_xref; if (OF_getencprop(node, "reg-shift", &sc->base.sc_reg_shift, sizeof(sc->base.sc_reg_shift)) <= 0) sc->base.sc_reg_shift = 0; if (clk_get_by_ofw_name(dev, 0, "hdmi", &sc->clk_hdmi) != 0 || clk_get_by_ofw_name(dev, 0, "ahb", &sc->clk_ahb) != 0) { device_printf(dev, "Cannot get clocks\n"); err = ENXIO; goto out; } if (OF_getencprop(node, "clock-frequency", &freq, sizeof(freq)) > 0) { err = clk_set_freq(sc->clk_hdmi, freq, CLK_SET_ROUND_DOWN); if (err != 0) { device_printf(dev, "Cannot set HDMI clock frequency to %u Hz\n", freq); goto out; } } else device_printf(dev, "HDMI clock frequency not specified\n"); if (clk_enable(sc->clk_hdmi) != 0) { device_printf(dev, "Cannot enable HDMI clock\n"); err = ENXIO; goto out; } if (clk_enable(sc->clk_ahb) != 0) { device_printf(dev, "Cannot enable AHB clock\n"); err = ENXIO; goto out; } return (dwc_hdmi_init(dev)); out: dwc_hdmi_fdt_detach(dev); return (err); } static int dwc_hdmi_fdt_probe(device_t dev) { if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Synopsys DesignWare HDMI Controller"); return (BUS_PROBE_DEFAULT); } static device_method_t dwc_hdmi_fdt_methods[] = { /* Device interface */ DEVMETHOD(device_probe, dwc_hdmi_fdt_probe), DEVMETHOD(device_attach, dwc_hdmi_fdt_attach), DEVMETHOD(device_detach, dwc_hdmi_fdt_detach), /* HDMI methods */ DEVMETHOD(hdmi_get_edid, dwc_hdmi_get_edid), DEVMETHOD(hdmi_set_videomode, dwc_hdmi_set_videomode), DEVMETHOD_END }; static driver_t dwc_hdmi_fdt_driver = { "dwc_hdmi", dwc_hdmi_fdt_methods, sizeof(struct dwc_hdmi_fdt_softc) }; DRIVER_MODULE(dwc_hdmi_fdt, simplebus, dwc_hdmi_fdt_driver, 0, 0); diff --git a/sys/dev/hdmi/hdmi_if.m b/sys/dev/video/crtc_if.m similarity index 99% rename from sys/dev/hdmi/hdmi_if.m rename to sys/dev/video/crtc_if.m index 81dbfa2009bb..8cf81bccccf9 100644 --- a/sys/dev/hdmi/hdmi_if.m +++ b/sys/dev/video/crtc_if.m @@ -1,67 +1,67 @@ #- # Copyright (c) 2015 Oleksandr Tymoshenko # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS # OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) # HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT # LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY # OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF # SUCH DAMAGE. # # $FreeBSD$ # #include #include #include -INTERFACE hdmi; +INTERFACE crtc; HEADER { #include typedef void (*hdmi_event_hook)(void *, device_t, int); EVENTHANDLER_DECLARE(hdmi_event, hdmi_event_hook); #define HDMI_EVENT_CONNECTED 0 } # # Get EDID info # METHOD int get_edid { device_t dev; uint8_t **edid; uint32_t *edid_length; }; # # Set videomode # METHOD int set_videomode { device_t dev; const struct videomode *videomode; }; # # Enable/disable output # METHOD int enable { device_t dev; int onoff; };