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- User Since
- Jun 29 2025, 4:40 PM (32 w, 3 d)
Yesterday
Mon, Feb 9
For reference, this is the Petitboot commit that added the feature in originally:
Fri, Feb 6
Use system defined MAXPHYS value
Thu, Feb 5
Update manpage and fix tunable registration
Updated to move this to a tunable. From what I can see MAXPHYS is only 128k, and is not available to drivers as a constant. As a result, we actually end up only allocating 8MB by default; if I missed something just let me know and I'll update the MAXPHYS to match...
Understood. What would a sane value be here? 4GB is way too large (as an example, the allocation we actually get on a server that doesn't have a ton of other cards installed is "only" ~1.8GB), would 128MB or 512MB be workable?
Example boot, hotplug, and hot remove of disk device with this patch applied. Note that without this patch the driver won't load, since ~2GB of bounce buffers are allocated and the DMA template tag request fails.
Committed in 1364e7d0921b
Wed, Feb 4
After overnight stress testing, a combination of D55095 and using the correct DMA tag seems to have completely resolved the AHCI instability I was seeing with this patchset applied.
Thanks for that!
Digging further, at least some of the problem here seems to be from our rather unique memory allocation on POWER9:
OK, thanks for testing. I spent most of the day already going over the codebase trying to figure out what might be going wrong, and all I've come up with thus far is that the 32-bit MMIO window setup and DMA configuration both make no sense. It shouldn't even be working at all on POWER9 using the stock code (without this patch).
Tue, Feb 3
! In D54745#1259084, @adrian wrote:
my POWER8 box does, but that may not be good enough?
@adrian Could you give this patch set a thorough test as well? It is not dependent on D54745, I mainly want some additional testing without this on top of D54745 and a merge before going to the next phase of IOMMU enablement. D54745 has some issues with DMA and the AHCI controller that I don't currently understand and will need further investigation.
When testing, does anyone else have access to a SATA controller that does DMA? I'm sporadically seeing the Blackbird's AHCI controller lock up but I don't know if this is a PE freeze, bad DMA, or something completely unrelated (flaky cabling?):
Sat, Jan 24
Fri, Jan 23
Fri, Jan 16
Dec 15 2025
I'm leaning toward @jrtc27's side of things here, but I would like to know more about the issues that were seen that prompted adding this code in the first place. Worst case is that the code being reverted "fixed" the original issue by simply modifying timing / avoiding a race condition, especially given that a.) we tend to have a lot more cores than the other two weak memory ordering architectures and b.) they don't have this kind of flushing behavior yet apparently function normally.
Dec 3 2025
Merged as 201af1a14
Nov 19 2025
On second read through, caught a couple of code issues that don't affect functionality. Once those are fixed this looks good.
Looks good to me on a POWER9 Blackbird / powerpc64le.
Sep 11 2025
Sep 10 2025
Added aesni and armv8crypto alongside ossl
Sep 5 2025
Rebase for 15.0
Jun 29 2025
@jhibbits I'm wondering the same thing. On my side this seems good, any chance we can get it merged? Raptor is still carrying this as a downstream patch in its OPNsense builds. Thanks!
