meloun-miracle-cz (Michal Meloun)
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Feb 3 2015, 4:54 AM (176 w, 5 d)

Recent Activity

Sat, Jun 16

meloun-miracle-cz updated the diff for D13861: Add support for booting FreeBSD kernel directly from U_Boot using booti command..

Rebased to current, renamed UBOOT_BOOT_API to LINUX_BOOT_API

Sat, Jun 16, 9:32 AM

Mar 9 2018

meloun-miracle-cz accepted D14541: Make Raspberry Pi RNG compatible with upstream DTBs.
Mar 9 2018, 5:18 AM

Mar 2 2018

meloun-miracle-cz accepted D14541: Make Raspberry Pi RNG compatible with upstream DTBs.

Tested also on RPi-B (armv6) without problem.
Please, also remove rng related lines from sys/dts/arm/rpi[2].dts stubs.

Mar 2 2018, 11:35 AM

Feb 10 2018

meloun-miracle-cz added a comment to D14299: sysutils/rpi-firware Include dtb and overlays.

+100 for overlays.
But I'm not sure if it's right time to publish base .dtb files in this way. We cannot use it for now (because interrupts for uart and spi are routed throw "bcm2835-aux") and it's unclear if binding headers (dts/include/dt-bindings/*) are same (or compatible) as linux mainstream ones.

Feb 10 2018, 5:07 PM

Jan 19 2018

meloun-miracle-cz updated the diff for D13931: Implement mitigation for Spectre Version 2 attacks on ARMv7..
  • print actual mitigation variant if bootversode
  • slightly restructure code to make additional vendors or CPUs addition easier
Jan 19 2018, 5:07 PM

Jan 18 2018

meloun-miracle-cz added inline comments to D13931: Implement mitigation for Spectre Version 2 attacks on ARMv7..
Jan 18 2018, 2:47 PM
meloun-miracle-cz updated the diff for D13931: Implement mitigation for Spectre Version 2 attacks on ARMv7..

Addressed all objections.

Jan 18 2018, 2:18 PM

Jan 17 2018

meloun-miracle-cz added inline comments to D13931: Implement mitigation for Spectre Version 2 attacks on ARMv7..
Jan 17 2018, 7:00 AM

Jan 16 2018

meloun-miracle-cz retitled D13931: Implement mitigation for Spectre Version 2 attacks on ARMv7. from Implement BP hardening as mitigation for Spectre Version 2 attacks on ARMv7 platforms. to Implement mitigation for Spectre Version 2 attacks on ARMv7..
Jan 16 2018, 7:51 AM
meloun-miracle-cz created D13931: Implement mitigation for Spectre Version 2 attacks on ARMv7..
Jan 16 2018, 6:16 AM

Jan 12 2018

meloun-miracle-cz updated the diff for D13863: Simplify and cleanup startup code for secondary cores..
Jan 12 2018, 8:42 AM
meloun-miracle-cz added a comment to D13861: Add support for booting FreeBSD kernel directly from U_Boot using booti command..

You didn't describe any reason it wouldn't work. Rather than the kernel as the first argument to booti, it would be the second, after either passing it through mkimage, or loading it as a raw file with a size.

mkimage, imho, is not supported(or not preferred - it have bundled load address inside) on arm64, but this is not important yet.

Jan 12 2018, 8:01 AM
meloun-miracle-cz added a comment to D13864: Add workaround for broken PSCI implementation..

I agree but, unfortunately, yes. The context_id is used for selecting right stack. See line 270 in new file.

Jan 12 2018, 7:14 AM
meloun-miracle-cz added a comment to D13863: Simplify and cleanup startup code for secondary cores..

Boot CPU have always cpuid 0 so yes, it boots (i hope). I have disordered cpus nodes in my DTS and all looks OK.

Jan 12 2018, 7:09 AM

Jan 11 2018

meloun-miracle-cz added a comment to D13861: Add support for booting FreeBSD kernel directly from U_Boot using booti command..

Yep, I known. But my actual situation with Jetson TX1 board is more complicated.

  • the TX1 firmware can only load U-Boot for eMMC.
  • shipped U-Boot doesn't support EFI
  • on OS start, U-Boot modifies DTB (it excludes memory used by secure monitor and PSCI,, it modifies the pinmux table so that it matches the current setting), it stored trained settings for DDR4 controller for various memory frequencies...)
Jan 11 2018, 4:12 PM
meloun-miracle-cz added a dependency for D13864: Add workaround for broken PSCI implementation.: D13863: Simplify and cleanup startup code for secondary cores..
Jan 11 2018, 3:46 PM
meloun-miracle-cz added a dependent revision for D13863: Simplify and cleanup startup code for secondary cores.: D13864: Add workaround for broken PSCI implementation..
Jan 11 2018, 3:46 PM
meloun-miracle-cz created D13864: Add workaround for broken PSCI implementation..
Jan 11 2018, 3:46 PM
meloun-miracle-cz created D13863: Simplify and cleanup startup code for secondary cores..
Jan 11 2018, 3:44 PM
meloun-miracle-cz created D13861: Add support for booting FreeBSD kernel directly from U_Boot using booti command..
Jan 11 2018, 2:57 PM

Dec 26 2017

meloun-miracle-cz added a comment to D13619: axp209: move driver to sys/dev/pmic.

imho, we should put platform specialized drivers to dev subtree only if given driver can be reused on multiple platforms. I personally vote for not moving it.

Dec 26 2017, 12:04 PM

Dec 23 2017

meloun-miracle-cz accepted D13521: syscon: Introduce kobj and split out fdt bits.

Perfect, thanks.

Dec 23 2017, 9:20 AM

Dec 21 2017

meloun-miracle-cz added a comment to D13521: syscon: Introduce kobj and split out fdt bits.

Everything else looks OK for me.

Dec 21 2017, 4:30 AM
meloun-miracle-cz added a comment to D13536: Set the address of translation table for thread0..

Nice, this looks OK for me
But,it seems that there are some related problems:

  • the PCB for proc0/thread0 is allocated on top of stack, from dirty memory, but not all fields are not initialized - this is probably a root cause why this bug is not visible on all boards.
  • we leaks initial low memory mappings in kernel_pmap. This can results to double mappings with different attributes which is undefined behavior. Imho, we should clear all mappings in low memory region.
Dec 21 2017, 4:07 AM

Dec 19 2017

meloun-miracle-cz added a comment to D13536: Set the address of translation table for thread0..

yes, but the fix looks incorrect for me.
I think that we can have same problem with secondary cores(idle threads). Imho, cpu_startup() is more appropriate place for this and we should derive TTBR0 value from kernel_pmap[1]. See arm version of cpu_startup() and call to pmap_set_pcb_pagedir(kernel_pmap, pcb); .

Dec 19 2017, 3:41 PM
meloun-miracle-cz accepted D8720: Add ACPI support to the GICv2 and GICv3 drivers..

No objection from arm or intrng side.

Dec 19 2017, 3:04 PM
meloun-miracle-cz added a comment to D13536: Set the address of translation table for thread0..

I can confirm same issue on Cortex-A72. Loading zero to TTBR0_EL1 causes immediate exception (in sched_switch+0x3a0).

Dec 19 2017, 2:58 PM

Dec 12 2017

meloun-miracle-cz added inline comments to D13455: u-boot-tools: Add new ports u-boot-tools.
Dec 12 2017, 4:54 AM
meloun-miracle-cz accepted D13455: u-boot-tools: Add new ports u-boot-tools.

Thanks !!!

Dec 12 2017, 4:51 AM

Dec 8 2017

meloun-miracle-cz added a comment to D13378: Rework alignment handling in __libc_allocate_tls() for Variant I of TLS layout..

Kib,
thanks. I will incorporate all your comments into final commit.

Dec 8 2017, 10:04 AM

Dec 5 2017

meloun-miracle-cz created D13378: Rework alignment handling in __libc_allocate_tls() for Variant I of TLS layout..
Dec 5 2017, 4:46 PM

Nov 29 2017

meloun-miracle-cz added a comment to D13152: math/R: Fix build on armv6 and armv7 (RE: Bug 223476).

Sorry for delay. We don't support arm for FreeBSD 10 and arm packages are built only for FreeBSD11 and higher.
See http://pkg.freebsd.org/

Nov 29 2017, 1:22 PM

Nov 25 2017

meloun-miracle-cz added a comment to D13134: [mips32/tls] change TCB size from 8 to 16 to be aligned with r324938 & r325364.

Generally speaking, I think that implementing more and more knowledge about TLS ABI into kernel is direct way to hell and it simply leads to hard to solve compatibility issues.
The ideal kernel should take TP pointer as opaque value, without any attempt to interpret it.

Nov 25 2017, 8:58 AM

Nov 20 2017

meloun-miracle-cz added a comment to D13134: [mips32/tls] change TCB size from 8 to 16 to be aligned with r324938 & r325364.

with full respect, I don’t think that this is right way. Moreover, I think that you papering over real problem there.
With this patch, what’s happen if someone requests any higher alignment (that actual 16) for TLS data? Or, can patched kernel run the old init (pre r324938)?

Nov 20 2017, 3:19 PM

Nov 19 2017

meloun-miracle-cz accepted D13152: math/R: Fix build on armv6 and armv7 (RE: Bug 223476).

I can confirm that R cad be built on native ARMv7 system with this.

Nov 19 2017, 7:52 AM

Nov 3 2017

meloun-miracle-cz added a comment to D12816: Fix qt5 builds on some arm architectures.

Seems that exp-run passed without problems. Can you, please, commit this ?

Nov 3 2017, 6:20 AM
meloun-miracle-cz added inline comments to D12907: Add alignment support to __libc_allocate_tls()..
Nov 3 2017, 6:06 AM

Nov 2 2017

meloun-miracle-cz added inline comments to D12907: Add alignment support to __libc_allocate_tls()..
Nov 2 2017, 4:21 PM
meloun-miracle-cz updated the diff for D12907: Add alignment support to __libc_allocate_tls()..
  • malloc_aligned() modified to rtld version
  • added alignment fix also for Variant I
  • check malloc() return values
  • use custom version of assert()
Nov 2 2017, 4:19 PM
meloun-miracle-cz added inline comments to D12907: Add alignment support to __libc_allocate_tls()..
Nov 2 2017, 1:22 PM
meloun-miracle-cz created D12907: Add alignment support to __libc_allocate_tls()..
Nov 2 2017, 6:41 AM

Oct 30 2017

meloun-miracle-cz accepted D12816: Fix qt5 builds on some arm architectures.
Oct 30 2017, 1:16 PM

Oct 20 2017

meloun-miracle-cz added a comment to D12743: Make elf_aux_info() as public libc function..
In D12743#264414, @kib wrote:

Does it make sense to include machine/elf.h from auxv.h ? Why not make it a user duty ?

Imho yes, AT_ values are defined in machine/elf.h so user should include it in (almost) all cases.

Would be nice to provide some kind of man page.

I will ask Ian for man page, this kind of job is significantly out of my skill (even in my native language). My bad I known.

Oct 20 2017, 2:39 PM
meloun-miracle-cz created D12743: Make elf_aux_info() as public libc function..
Oct 20 2017, 1:48 PM
meloun-miracle-cz updated the diff for D12699: Add AT_HWCAP2 ELF auxiliary vector. .

Split out libc changes

Oct 20 2017, 1:46 PM

Oct 18 2017

meloun-miracle-cz updated the diff for D12699: Add AT_HWCAP2 ELF auxiliary vector. .

Drop getauxval(), make _elf_aux_info() public.

Oct 18 2017, 3:48 PM
meloun-miracle-cz added a comment to D12699: Add AT_HWCAP2 ELF auxiliary vector. .

My exp-run for selected ports just ended and It found unexpected problem.
Some ports detect getauxval() presence and if is present then expect that all (linux specific) AT_ flags are defined and implemented (e.g. security/p11-kit ).

Oct 18 2017, 11:15 AM

Oct 17 2017

meloun-miracle-cz added inline comments to D12699: Add AT_HWCAP2 ELF auxiliary vector. .
Oct 17 2017, 3:39 PM
meloun-miracle-cz created D12699: Add AT_HWCAP2 ELF auxiliary vector. .
Oct 17 2017, 1:31 PM

Sep 10 2017

meloun-miracle-cz accepted D12294: Add ptrace operations to fetch and store VFP registers..
Sep 10 2017, 5:36 AM
meloun-miracle-cz accepted D12293: Add a NT_ARM_VFP ELF core note to hold VFP registers for each thread..
Sep 10 2017, 5:34 AM
meloun-miracle-cz accepted D12292: Only mess with VFP state on the CPU for curthread for get/set_vfpcontext..
Sep 10 2017, 5:32 AM
meloun-miracle-cz accepted D12291: Add AT_HWCAP flags for VFP settings for FreeBSD/arm..
Sep 10 2017, 5:21 AM

Sep 9 2017

meloun-miracle-cz added inline comments to D12010: Support armv7 builds for userland.
Sep 9 2017, 6:00 AM

Sep 8 2017

meloun-miracle-cz accepted D12274: End softfp->hardfp transition period for arm.

Can be this MFCed to stable? In other words, do we support in place upgrade from 10 (soft FP ABI) to 11 (hard FP ABI)?
From my point of view, this is OK for FBSD 12.

Sep 8 2017, 3:27 PM

Sep 6 2017

meloun-miracle-cz added inline comments to D8616: Rework the logic for finding the pic object..
Sep 6 2017, 10:11 AM

Aug 11 2017

meloun-miracle-cz accepted D11957: Only return the current cpu if it's in the cpumask.
Aug 11 2017, 11:24 AM
meloun-miracle-cz accepted D11846: Add to sysreg definition for coproc regs required for virtualization.
Aug 11 2017, 11:23 AM

Aug 4 2017

meloun-miracle-cz added inline comments to D11846: Add to sysreg definition for coproc regs required for virtualization.
Aug 4 2017, 5:21 AM

Jun 28 2017

meloun-miracle-cz accepted D11393: Start to remove _libc_arm_fpu_present checks.
Jun 28 2017, 3:54 PM

Jun 21 2017

meloun-miracle-cz accepted D11204: Enable arm,io-coherent property of PL310 L2 cache on Armada 38x platforms.
Jun 21 2017, 1:57 PM · ARM

Jun 18 2017

meloun-miracle-cz accepted D11245: Disable PL310 outer cache sync for IO coherent platforms.
Jun 18 2017, 3:44 AM · ARM

Jun 17 2017

meloun-miracle-cz added a comment to D11238: Allow to fetch tunable variable introduced in r319896 from getenv().

Oups, my bad, sorry.
We cannot use standard way for tunable sysctl initialization here. SYSINIT machinery is executed far after cpuinfo_init() so boot CPU doesn't get right quirks.
Anyway, I submitted fix for this in r320054.
So again, sorry for troubles...

Jun 17 2017, 3:52 PM
meloun-miracle-cz added a comment to D11245: Disable PL310 outer cache sync for IO coherent platforms.

I'm fine with rest.

Jun 17 2017, 3:45 PM · ARM
meloun-miracle-cz accepted D10218: Implement workaround for Armada 38X family HW issue between CPU and devices.
Jun 17 2017, 4:11 AM

Jun 15 2017

meloun-miracle-cz added a comment to D11203: Create root DMA tag and fix MBUS windows on DMA coherent platforms.

I do not think this patch was accepted in mainline Linux -> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-August/363953.html

But this one is -> https://github.com/torvalds/linux/commit/98ea2dba65932ffc456b6d7b11b8a0624e2f7b95
Please note that commit log uses "the outer cache sync operation is useless: and not a " the entire outer cache operations are useless".
Also note that this behavior is driven by "arm,io-coherent" property.

Event better. We were thinking how to replace the callbacks in the pl310 in a nice way. Are you ok with using "arm,io-coherent" property in pl310 in a similar way?

I'm fine with both solutions, with preference to "arm,io-coherent". Using standardized, documented way is always better :)

Jun 15 2017, 2:54 PM · ARM
meloun-miracle-cz added a comment to D11203: Create root DMA tag and fix MBUS windows on DMA coherent platforms.

I do not think this patch was accepted in mainline Linux -> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-August/363953.html

Jun 15 2017, 12:41 PM · ARM
meloun-miracle-cz added a comment to D11203: Create root DMA tag and fix MBUS windows on DMA coherent platforms.

When a PL310 cache is used in a system that provides hardware
coherency, the entire outer cache operations are useless, and can be
skipped.

This is significantly incorrect/misleading/false sentence. All these outer cache operations are necessary for standard mapping operations, irrespective of coherency status.
Please, reword this part in commit.

Jun 15 2017, 11:04 AM · ARM

Jun 14 2017

meloun-miracle-cz added a comment to D10909: Add detection of CPU class for ARMv6/v7.

Too late but still...
What exactly is "cpu_class" and why we need at all? I understand why it's useful for ARMv4, but it's near useless for ARMv7 (there is too much variants)

Jun 14 2017, 4:31 PM · ARM
meloun-miracle-cz added a comment to D10682: Introduce platform CPU init for ARM.
In D10682#231591, @zbb wrote:

BTW. As for the unsolvable problem with the memory attributes change from DEVICE to SO we could use the same method as you used for ACTLR modification, means we could create another sysctl quirk and so on...
In platform code for Armada38X we could then check whether memory attributes are set as expected and if not we could fire an assertion. What do you think?

Imho, this problem is already solved by pmap_remap_vm_attr() (r318021) - or I didn't notice something important?

OK. I though that using this function so late was discussed to be not allowed. But if it is OK to use in platform_late_init than this concludes this issue. So I understand that will get a green light after putting pmap_remap_vm_attr() to platform_late_init() ?

Jun 14 2017, 1:15 PM
meloun-miracle-cz added a comment to D10682: Introduce platform CPU init for ARM.
In D10682#231259, @zbb wrote:

@meloun-miracle-cz if I understand correctly, in your commit you simply create a environment variable to modify ACTLR from the loader.conf or etc.
We can use that solution directly for our purposes without any further modifications, platform_late_init() complications and etc. Until ARMADA38X will be compatible with the GENERIC kernel we could potentially add environment configuration file to be compiled-into the kernel. The latter would need testing whether it works with the loader.conf file as well or not (I expect problems with that).
Regardless of the settings for Armada38X we can drop this revision completely and start using environment variables. Agree?

Yep, exactly, I agree.

Jun 14 2017, 12:27 PM

Jun 13 2017

meloun-miracle-cz updated subscribers of D10682: Introduce platform CPU init for ARM.

Hmm, allow me a short summary:

  • This patch simply cannot work. On boot core, the platform_cpu_init() is called before platform is recognized. On secondary cores, platform_cpu_init() is called before given core enters to coherency domain, so each single memory write (outside of stack) causes disaster..
  • I don't see any way how we can do any platform specific operation before reinit_mmu() is called.
  • The goal can be reached by different, much more consistent way.
Jun 13 2017, 1:41 PM

May 28 2017

meloun-miracle-cz added a comment to D10765: Implement sincos, sincosf, and sincosl..
In D10765#225464, @dim wrote:

It would be nice to have some tests, even if they are rudimentary... :)

May 28 2017, 5:46 AM

May 22 2017

meloun-miracle-cz updated the diff for D10765: Implement sincos, sincosf, and sincosl..

The one should really save all edited files before updating review :(

May 22 2017, 12:02 PM
meloun-miracle-cz updated the diff for D10765: Implement sincos, sincosf, and sincosl..
  • fix style(9) for copyright blocks
  • pair RETURNV() with ENTERV()
May 22 2017, 11:53 AM

May 17 2017

meloun-miracle-cz added a comment to D10765: Implement sincos, sincosf, and sincosl..

Oups, the 'lib/msun/src/math.h.orig' will not be included in the final commit, of course.

May 17 2017, 3:56 AM
meloun-miracle-cz created D10765: Implement sincos, sincosf, and sincosl..
May 17 2017, 3:48 AM

May 15 2017

meloun-miracle-cz added a comment to D10733: Run platform_late_init on all cpus..

Nothing strong, but I would probably prefer a new method for late init on secondary cores, instead of reusing of platform_late_init() - something like platform_mp_late_init.
Code sharing between BP / AP will be very rare, i think.

May 15 2017, 1:13 PM

May 14 2017

meloun-miracle-cz added a comment to D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.

I would prefer to move this code to platform_late_init().
The only drawback is that you must use cp15_actlr_set() + cp15_actlr_get() for boot CPU...

May 14 2017, 7:55 AM
meloun-miracle-cz added a comment to D10682: Introduce platform CPU init for ARM.

I think that this patch is not longer needed?
Both issues (device memory class remap, ACTRL modification) can be processed in platform_late_init().
I'm right?

May 14 2017, 7:12 AM
meloun-miracle-cz added a comment to D10683: Introduce platform CPU info container for ARM. Use it for ACTLR..

Otherwise, I'm fine with this.

May 14 2017, 6:47 AM

May 9 2017

meloun-miracle-cz added a comment to D10218: Implement workaround for Armada 38X family HW issue between CPU and devices.

Committed as r318021. Sorry for huge delay...

May 9 2017, 11:07 AM

Apr 16 2017

meloun-miracle-cz accepted D10217: Increase number of L2 tables required for kernel bootstrap.

Thanks for clarification, I see it now.

Apr 16 2017, 1:24 PM
meloun-miracle-cz accepted D10221: Execute PL310_ERRATA_727915 only for related revisions.

Thanks.

Apr 16 2017, 1:21 PM

Apr 11 2017

D8616: Rework the logic for finding the pic object. now requires changes to proceed.
In D8616#210013, @skra wrote:

(1) The staff around PIC and xref was implemented with concrete idea. You are trying to change it. So, it's not cleanup, it's an implementation of new idea. And I don't see why this change would be better.

It might be ok for FDT, however we need to also consider ACPI where zero is a valid xref.

(2) You are forcing devices which do not know (or have) their XREFs to generate some instead of using one and only XREF_UNKNOWN for these cases, which is zero.

But zero may be a valid xref. I would prefer we create a new value for XREF_UNKNOWN separate from XREF_INVALID, e.g. -2. This will be used by devices that don't naturally have an xref, e.g. a PCI GPIO controller, but would allow the error checking in the patch to be kept. I didn't do this in this patch as I'm not aware of any drivers in the tree that would use this so am unable to test it.

In short:

  • in current code takes 0 (or NULL) xref as unknown xref not as error indicator.
  • we cannot expect that all "information sources" *FDT/ACPI/HINTS" can share same value for unknown xref natively

I don't see why, both ACPI and FDT will use positive values close or equal to zero.

  • natural value for unknown xref is 0 for FDT , NULL for HINTS

-1 is a natural value for unknown, it's too large for an FDT xref to work, and memory around the top of the virtual address space is unusable by HINTS. It also has the property where

  • if you want change value of unknown xref correctly, then you must also remap FDT no such property to INTRNG unknown xref for all FDT users

As best as I can tell the OFW code uses -1 for unknown values. This patch will help find bugs where these values are unchecked.

  • the "#define XREF_INVALID (-1)" is nonsense, it's hidden "#define XREF_INVALID ACPI_INVALID_HANDLE" as these values are coupled

The exact value doesn't matter, e.g. -2 would also work, however by using -1 we will catch bugs in drivers that fail to check the return value of ofw_bus_get_node before passing them to OF_xref_from_node.

(3) XREF_INVALID used the way you are suggesting is a nonsense. I would see XREF_INVALID only as an error code.

We already use errno values in this code so the error code would be EINVAL.

Where we pass any error code to xref parameter? Ore where we return error code from function returning xref?

They shouldn't be passing in error values as if it was a valid xref.

(4) This part of INTRNG was implemented strictly according to Michal, so I hope that you do not commit this before Michal agrees with it.

As far as I know I've answered all questions, and haven't seen any further feedback in a month.

Sorry for delay, I'm overloaded these days (or weeks)
And no, I don't think that you answered my questions:

  • newly added kasserts limits already working cases. But why?

Because drivers passing the invalid value in are broken, they should only get this from failing to check return values.

  • you want to change already working pic_lookup() behavior. But why?

Because it won't work with ACPI. As such I tried to make the minimal changes needed to support this.

Apr 11 2017, 2:43 PM

Apr 2 2017

meloun-miracle-cz added a comment to D10217: Increase number of L2 tables required for kernel bootstrap.

Can you be, please, little more verbose? I'm unable to detect where exactly the problem is.

Apr 2 2017, 7:12 AM
meloun-miracle-cz added a comment to D10218: Implement workaround for Armada 38X family HW issue between CPU and devices.

Please tell me, do you really think that hellish "#ifdef SOC_xxx" style used in Marvell subdirectory is the right one?
For me, using "#ifdef SOC_xxx" is unacceptable in common code, and is deprecated in vendor subdirs.

The SOC_XXX checks are correct when it's to enable code that will only be run on a single SoC, e.g. the platform code. Unfortunately the Marvell code uses it to change definitions and I would like to move away from that style.

Yep, I agree. Thanks for clarification.

Apr 2 2017, 6:47 AM

Apr 1 2017

meloun-miracle-cz accepted D10223: Fix bit assignment in PL310_POWER_CTRL.
Apr 1 2017, 7:48 AM
meloun-miracle-cz added a comment to D10221: Execute PL310_ERRATA_727915 only for related revisions.

Armada38x have Marvell specific (or modified) PL310 ? If not then all errata fixes (but two at line 274 and 295) are checked online. Why do you want to disable them? Do you have measured impact caused by these tests?

Apr 1 2017, 7:48 AM
meloun-miracle-cz added a comment to D10218: Implement workaround for Armada 38X family HW issue between CPU and devices.

Please tell me, do you really think that hellish "#ifdef SOC_xxx" style used in Marvell subdirectory is the right one?
For me, using "#ifdef SOC_xxx" is unacceptable in common code, and is deprecated in vendor subdirs.

Apr 1 2017, 7:29 AM

Mar 29 2017

meloun-miracle-cz added a comment to D8616: Rework the logic for finding the pic object..

Alternatively, we can use global variable for unknown xref value , initialized at early system startup.

Mar 29 2017, 6:46 AM
meloun-miracle-cz added a comment to D8616: Rework the logic for finding the pic object..
In D8616#210013, @skra wrote:

(1) The staff around PIC and xref was implemented with concrete idea. You are trying to change it. So, it's not cleanup, it's an implementation of new idea. And I don't see why this change would be better.

It might be ok for FDT, however we need to also consider ACPI where zero is a valid xref.

(2) You are forcing devices which do not know (or have) their XREFs to generate some instead of using one and only XREF_UNKNOWN for these cases, which is zero.

But zero may be a valid xref. I would prefer we create a new value for XREF_UNKNOWN separate from XREF_INVALID, e.g. -2. This will be used by devices that don't naturally have an xref, e.g. a PCI GPIO controller, but would allow the error checking in the patch to be kept. I didn't do this in this patch as I'm not aware of any drivers in the tree that would use this so am unable to test it.

In short:

  • in current code takes 0 (or NULL) xref as unknown xref not as error indicator.
  • we cannot expect that all "information sources" *FDT/ACPI/HINTS" can share same value for unknown xref natively
  • natural value for unknown xref is 0 for FDT , NULL for HINTS
  • if you want change value of unknown xref correctly, then you must also remap FDT no such property to INTRNG unknown xref for all FDT users
  • the "#define XREF_INVALID (-1)" is nonsense, it's hidden "#define XREF_INVALID ACPI_INVALID_HANDLE" as these values are coupled
Mar 29 2017, 5:43 AM

Mar 13 2017

meloun-miracle-cz added a comment to D8076: Capsicum-ize lam(1).

It seems that this breaks lam (and thus portsnap) on systems without capsicum. Many tier2 systems are affected by this.

root@tegra124:/usr/ports # portsnap fetch
Looking up portsnap.FreeBSD.org mirrors... 6 mirrors found.
Fetching snapshot tag from ec2-eu-west-1.portsnap.freebsd.org... done.
Fetching snapshot metadata... done.
Updating from Sat Jan 28 07:27:13 UTC 2017 to Mon Mar 13 16:02:31 UTC 2017.
Fetching 5 metadata patches.lam: unable to limit rights on: -: Function not implemented
done.
Applying metadata patches... done.
Fetching 5 metadata files... lam: unable to limit rights on: -: Function not implemented
/usr/sbin/portsnap: cannot open a5dec4addaeb7dfd733a5eb227f3cdbb7f1f4ab2bd63426d5fd6e5d4e5be2277.gz: No such file or directory

metadata is corrupt.

Mar 13 2017, 5:03 PM

Mar 8 2017

meloun-miracle-cz added a comment to D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.
In D9864#205185, @zbb wrote:

Armada stuff provides platform_late_init, etc.

platform_late_init() is only transitional hack, full platform model needs FDT_PLATFORM_DEF() macro.

Mar 8 2017, 11:29 AM
meloun-miracle-cz added a comment to D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.

Ahh, I see now, Marvell subtree is not fully converted to platform model :) . But trust me, conversion its not that hard and makes your life much easier.
Also, there is global effort to make single generic kernel for all supported armv6 boards, and #ifdef SoC only technique is in direct direct contradiction with this goal.
See allwinner subtree, mainly aw_machdep.c. This platform supports numerous board with single kernel in 'right' way, without #ifdef hell.

Mar 8 2017, 5:56 AM

Mar 7 2017

meloun-miracle-cz added a comment to D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.

In D9864#204948, @zbb wrote:
In general, I don't insist on adding this change to all Cortex-A9 CPUs and I acknowledge your arguments.
Another platform-dependent method is OK for us. We need something that will be executed on both primary and secondary CPUs. It would be best if this stays in a common place for both primary and secondary CPUs (such as cpu_setup() is common for CPU0 and CPUx).
What do you think?

Mar 7 2017, 4:07 PM
meloun-miracle-cz added a comment to D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.

I'm sorry about my platform_mp_start_ap() mistake.
I understand that cpuinfo_get_actlr_modifier() looks like most direct (and most easier) way how to make this. But again, this setting must be platform dependent.
Assume that you have 2 different boards (with different bootloaders) but with exactly same CPU. One board start OS in secure world, one in non-secure. . Then, write to ACTRL is OK for first one, but may cause exception on second.

Mar 7 2017, 3:22 PM

Mar 4 2017

meloun-miracle-cz added a comment to D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.

Yep, fully agree. From my point of view, platform_late_init() (for BP) is best place for performance tweaks. At this point, printf() works and cpuinfo is initialized, so you can check proper CPU revision, print some warning about potentially dangerous action, etc...
For AP, you can use standard platform_mp_start_ap(), but many ACTRL bits are shared between CPU's. So, typically, it's sufficient to set up only BP.

Mar 4 2017, 6:51 AM

Mar 2 2017

meloun-miracle-cz accepted D9833: extres: clk: Export clkdom and clocks under sysctl..

Perfect :)

Mar 2 2017, 5:18 PM · ARM
meloun-miracle-cz requested changes to D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.

See Erratum 571620, 719331, 719332, 751473 and probably more others.

Mar 2 2017, 5:15 PM