diff --git a/sys/arm/xilinx/zy7_qspi.c b/sys/arm/xilinx/zy7_qspi.c index 81ceb79e2bf6..c033fd29a7db 100644 --- a/sys/arm/xilinx/zy7_qspi.c +++ b/sys/arm/xilinx/zy7_qspi.c @@ -1,751 +1,751 @@ /*- * SPDX-License-Identifier: BSD-2-Clause * * Copyright (c) 2018 Thomas Skibo * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include /* * This is a driver for the Quad-SPI Flash Controller in the Xilinx * Zynq-7000 SoC. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" static struct ofw_compat_data compat_data[] = { {"xlnx,zy7_qspi", 1}, {"xlnx,zynq-qspi-1.0", 1}, {NULL, 0} }; struct zy7_qspi_softc { device_t dev; device_t child; struct mtx sc_mtx; struct resource *mem_res; struct resource *irq_res; void *intrhandle; uint32_t cfg_reg_shadow; uint32_t lqspi_cfg_shadow; uint32_t spi_clock; uint32_t ref_clock; unsigned int spi_clk_real_freq; unsigned int rx_overflows; unsigned int tx_underflows; unsigned int interrupts; unsigned int stray_ints; struct spi_command *cmd; int tx_bytes; /* tx_cmd_sz + tx_data_sz */ int tx_bytes_sent; int rx_bytes; /* rx_cmd_sz + rx_data_sz */ int rx_bytes_rcvd; int busy; int is_dual; int is_stacked; int is_dio; }; #define ZY7_QSPI_DEFAULT_SPI_CLOCK 50000000 #define QSPI_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx) #define QSPI_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) #define QSPI_SC_LOCK_INIT(sc) \ mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), NULL, MTX_DEF) #define QSPI_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx) #define QSPI_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) /* * QSPI device registers. * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. * (v1.12.2) July 1, 2018. Xilinx doc UG585. */ #define ZY7_QSPI_CONFIG_REG 0x0000 #define ZY7_QSPI_CONFIG_IFMODE (1U << 31) #define ZY7_QSPI_CONFIG_ENDIAN (1 << 26) #define ZY7_QSPI_CONFIG_HOLDB_DR (1 << 19) #define ZY7_QSPI_CONFIG_RSVD1 (1 << 17) /* must be 1 */ #define ZY7_QSPI_CONFIG_MANSTRT (1 << 16) #define ZY7_QSPI_CONFIG_MANSTRTEN (1 << 15) #define ZY7_QSPI_CONFIG_SSFORCE (1 << 14) #define ZY7_QSPI_CONFIG_PCS (1 << 10) #define ZY7_QSPI_CONFIG_REF_CLK (1 << 8) #define ZY7_QSPI_CONFIG_FIFO_WIDTH_MASK (3 << 6) #define ZY7_QSPI_CONFIG_FIFO_WIDTH32 (3 << 6) #define ZY7_QSPI_CONFIG_BAUD_RATE_DIV_MASK (7 << 3) #define ZY7_QSPI_CONFIG_BAUD_RATE_DIV_SHIFT 3 #define ZY7_QSPI_CONFIG_BAUD_RATE_DIV(x) ((x) << 3) /* divide by 2< 0) { nvalid = MIN(4, nbytes); data = 0xffffffff; /* * A hardware bug forces us to wait until the tx fifo is * empty before writing partial words. We'll come back * next tx interrupt. */ if (nvalid < 4 && (RD4(sc, ZY7_QSPI_INTR_STAT_REG) & ZY7_QSPI_INTR_TX_FIFO_NOT_FULL) == 0) return; if (sc->tx_bytes_sent < sc->cmd->tx_cmd_sz) { /* Writing command. */ n = MIN(nvalid, sc->cmd->tx_cmd_sz - sc->tx_bytes_sent); memcpy(&data, (uint8_t *)sc->cmd->tx_cmd + sc->tx_bytes_sent, n); if (nvalid > n) { /* Writing start of data. */ memcpy((uint8_t *)&data + n, sc->cmd->tx_data, nvalid - n); } } else /* Writing data. */ memcpy(&data, (uint8_t *)sc->cmd->tx_data + (sc->tx_bytes_sent - sc->cmd->tx_cmd_sz), nvalid); switch (nvalid) { case 1: WR4(sc, ZY7_QSPI_TXD1_REG, data); break; case 2: WR4(sc, ZY7_QSPI_TXD2_REG, data); break; case 3: WR4(sc, ZY7_QSPI_TXD3_REG, data); break; case 4: WR4(sc, ZY7_QSPI_TXD0_REG, data); break; } sc->tx_bytes_sent += nvalid; nbytes -= nvalid; } } /* Read hardware fifo data into command response and data buffers. */ static void zy7_qspi_read_fifo(struct zy7_qspi_softc *sc) { int n, nbytes; uint32_t data; do { data = RD4(sc, ZY7_QSPI_RX_DATA_REG); nbytes = MIN(4, sc->rx_bytes - sc->rx_bytes_rcvd); /* * Last word in non-word-multiple transfer is packed * non-intuitively. */ if (nbytes < 4) data >>= 8 * (4 - nbytes); if (sc->rx_bytes_rcvd < sc->cmd->rx_cmd_sz) { /* Reading command. */ n = MIN(nbytes, sc->cmd->rx_cmd_sz - sc->rx_bytes_rcvd); memcpy((uint8_t *)sc->cmd->rx_cmd + sc->rx_bytes_rcvd, &data, n); sc->rx_bytes_rcvd += n; nbytes -= n; data >>= 8 * n; } if (nbytes > 0) { /* Reading data. */ memcpy((uint8_t *)sc->cmd->rx_data + (sc->rx_bytes_rcvd - sc->cmd->rx_cmd_sz), &data, nbytes); sc->rx_bytes_rcvd += nbytes; } } while (sc->rx_bytes_rcvd < sc->rx_bytes && (RD4(sc, ZY7_QSPI_INTR_STAT_REG) & ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY) != 0); } /* End a transfer early by draining rx fifo and disabling interrupts. */ static void zy7_qspi_abort_transfer(struct zy7_qspi_softc *sc) { /* Drain receive fifo. */ while ((RD4(sc, ZY7_QSPI_INTR_STAT_REG) & ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY) != 0) (void)RD4(sc, ZY7_QSPI_RX_DATA_REG); /* Shut down interrupts. */ WR4(sc, ZY7_QSPI_INTR_DIS_REG, ZY7_QSPI_INTR_RX_OVERFLOW | ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY | ZY7_QSPI_INTR_TX_FIFO_NOT_FULL); } static void zy7_qspi_intr(void *arg) { struct zy7_qspi_softc *sc = (struct zy7_qspi_softc *)arg; uint32_t istatus; QSPI_SC_LOCK(sc); sc->interrupts++; istatus = RD4(sc, ZY7_QSPI_INTR_STAT_REG); /* Stray interrupts can happen if a transfer gets interrupted. */ if (!sc->busy) { sc->stray_ints++; QSPI_SC_UNLOCK(sc); return; } if ((istatus & ZY7_QSPI_INTR_RX_OVERFLOW) != 0) { device_printf(sc->dev, "rx fifo overflow!\n"); sc->rx_overflows++; /* Clear status bit. */ WR4(sc, ZY7_QSPI_INTR_STAT_REG, ZY7_QSPI_INTR_RX_OVERFLOW); } /* Empty receive fifo before any more transmit data is sent. */ if (sc->rx_bytes_rcvd < sc->rx_bytes && (istatus & ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY) != 0) { zy7_qspi_read_fifo(sc); if (sc->rx_bytes_rcvd == sc->rx_bytes) /* Disable receive interrupts. */ WR4(sc, ZY7_QSPI_INTR_DIS_REG, ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY | ZY7_QSPI_INTR_RX_OVERFLOW); } /* * Transmit underflows aren't really a bug because a hardware * bug forces us to allow the tx fifo to go empty between full * and partial fifo writes. Why bother counting? */ if ((istatus & ZY7_QSPI_INTR_TX_FIFO_UNDERFLOW) != 0) { sc->tx_underflows++; /* Clear status bit. */ WR4(sc, ZY7_QSPI_INTR_STAT_REG, ZY7_QSPI_INTR_TX_FIFO_UNDERFLOW); } /* Fill transmit fifo. */ if (sc->tx_bytes_sent < sc->tx_bytes && (istatus & ZY7_QSPI_INTR_TX_FIFO_NOT_FULL) != 0) { zy7_qspi_write_fifo(sc, MIN(240, sc->tx_bytes - sc->tx_bytes_sent)); if (sc->tx_bytes_sent == sc->tx_bytes) { /* * Disable transmit FIFO interrupt, enable receive * FIFO interrupt. */ WR4(sc, ZY7_QSPI_INTR_DIS_REG, ZY7_QSPI_INTR_TX_FIFO_NOT_FULL); WR4(sc, ZY7_QSPI_INTR_EN_REG, ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY); } } /* Finished with transfer? */ if (sc->tx_bytes_sent == sc->tx_bytes && sc->rx_bytes_rcvd == sc->rx_bytes) { /* De-assert CS. */ sc->cfg_reg_shadow |= ZY7_QSPI_CONFIG_PCS; WR4(sc, ZY7_QSPI_CONFIG_REG, sc->cfg_reg_shadow); wakeup(sc->dev); } QSPI_SC_UNLOCK(sc); } /* Initialize hardware. */ static int zy7_qspi_init_hw(struct zy7_qspi_softc *sc) { uint32_t baud_div; /* Configure LQSPI Config register. Disable linear mode. */ sc->lqspi_cfg_shadow = RD4(sc, ZY7_QSPI_LQSPI_CFG_REG); sc->lqspi_cfg_shadow &= ~(ZY7_QSPI_LQSPI_CFG_LINEAR | ZY7_QSPI_LQSPI_CFG_TWO_MEM | ZY7_QSPI_LQSPI_CFG_SEP_BUS); if (sc->is_dual) { sc->lqspi_cfg_shadow |= ZY7_QSPI_LQSPI_CFG_TWO_MEM; if (sc->is_stacked) { sc->lqspi_cfg_shadow &= ~ZY7_QSPI_LQSPI_CFG_INST_CODE_MASK; sc->lqspi_cfg_shadow |= ZY7_QSPI_LQSPI_CFG_INST_CODE(sc->is_dio ? CMD_READ_DUAL_IO : CMD_READ_QUAD_OUTPUT); } else sc->lqspi_cfg_shadow |= ZY7_QSPI_LQSPI_CFG_SEP_BUS; } WR4(sc, ZY7_QSPI_LQSPI_CFG_REG, sc->lqspi_cfg_shadow); /* Find best clock divider. */ baud_div = 0; while ((sc->ref_clock >> (baud_div + 1)) > sc->spi_clock && baud_div < 8) baud_div++; if (baud_div >= 8) { device_printf(sc->dev, "cannot configure clock divider: ref=%d" " spi=%d.\n", sc->ref_clock, sc->spi_clock); return (EINVAL); } sc->spi_clk_real_freq = sc->ref_clock >> (baud_div + 1); /* * If divider is 2 (the max speed), use internal loopback master * clock for read data. (See section 12.3.1 in ref man.) */ if (baud_div == 0) WR4(sc, ZY7_QSPI_LPBK_DLY_ADJ_REG, ZY7_QSPI_LPBK_DLY_ADJ_USE_LPBK | ZY7_QSPI_LPBK_DLY_ADJ_DLY1(0) | ZY7_QSPI_LPBK_DLY_ADJ_DLY0(0)); else WR4(sc, ZY7_QSPI_LPBK_DLY_ADJ_REG, 0); /* Set up configuration register. */ sc->cfg_reg_shadow = ZY7_QSPI_CONFIG_IFMODE | ZY7_QSPI_CONFIG_HOLDB_DR | ZY7_QSPI_CONFIG_RSVD1 | ZY7_QSPI_CONFIG_SSFORCE | ZY7_QSPI_CONFIG_PCS | ZY7_QSPI_CONFIG_FIFO_WIDTH32 | ZY7_QSPI_CONFIG_BAUD_RATE_DIV(baud_div) | ZY7_QSPI_CONFIG_MODE_SEL; WR4(sc, ZY7_QSPI_CONFIG_REG, sc->cfg_reg_shadow); /* * Set thresholds. We must use 1 for tx threshold because there * is no fifo empty flag and we need one to implement a bug * workaround. */ WR4(sc, ZY7_QSPI_TX_THRESH_REG, 1); WR4(sc, ZY7_QSPI_RX_THRESH_REG, 1); /* Clear and disable all interrupts. */ WR4(sc, ZY7_QSPI_INTR_STAT_REG, ~0); WR4(sc, ZY7_QSPI_INTR_DIS_REG, ~0); /* Enable SPI. */ WR4(sc, ZY7_QSPI_EN_REG, ZY7_SPI_ENABLE); return (0); } static void zy7_qspi_add_sysctls(device_t dev) { struct zy7_qspi_softc *sc = device_get_softc(dev); struct sysctl_ctx_list *ctx; struct sysctl_oid_list *child; ctx = device_get_sysctl_ctx(dev); child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "spi_clk_real_freq", CTLFLAG_RD, &sc->spi_clk_real_freq, 0, "SPI clock real frequency"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_overflows", CTLFLAG_RD, &sc->rx_overflows, 0, "RX FIFO overflow events"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_underflows", CTLFLAG_RD, &sc->tx_underflows, 0, "TX FIFO underflow events"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "interrupts", CTLFLAG_RD, &sc->interrupts, 0, "interrupt calls"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stray_ints", CTLFLAG_RD, &sc->stray_ints, 0, "stray interrupts"); } static int zy7_qspi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Zynq Quad-SPI Flash Controller"); return (BUS_PROBE_DEFAULT); } static int zy7_qspi_attach(device_t dev) { struct zy7_qspi_softc *sc; int rid, err; phandle_t node; pcell_t cell; sc = device_get_softc(dev); sc->dev = dev; QSPI_SC_LOCK_INIT(sc); /* Get ref-clock, spi-clock, and other properties. */ node = ofw_bus_get_node(dev); if (OF_getprop(node, "ref-clock", &cell, sizeof(cell)) > 0) sc->ref_clock = fdt32_to_cpu(cell); else { device_printf(dev, "must have ref-clock property\n"); return (ENXIO); } if (OF_getprop(node, "spi-clock", &cell, sizeof(cell)) > 0) sc->spi_clock = fdt32_to_cpu(cell); else sc->spi_clock = ZY7_QSPI_DEFAULT_SPI_CLOCK; if (OF_getprop(node, "is-stacked", &cell, sizeof(cell)) > 0 && fdt32_to_cpu(cell) != 0) { sc->is_dual = 1; sc->is_stacked = 1; } else if (OF_getprop(node, "is-dual", &cell, sizeof(cell)) > 0 && fdt32_to_cpu(cell) != 0) sc->is_dual = 1; if (OF_getprop(node, "is-dio", &cell, sizeof(cell)) > 0 && fdt32_to_cpu(cell) != 0) sc->is_dio = 1; /* Get memory resource. */ rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res == NULL) { device_printf(dev, "could not allocate memory resources.\n"); zy7_qspi_detach(dev); return (ENOMEM); } /* Allocate IRQ. */ rid = 0; sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (sc->irq_res == NULL) { device_printf(dev, "could not allocate IRQ resource.\n"); zy7_qspi_detach(dev); return (ENOMEM); } /* Activate the interrupt. */ err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, zy7_qspi_intr, sc, &sc->intrhandle); if (err) { device_printf(dev, "could not setup IRQ.\n"); zy7_qspi_detach(dev); return (err); } /* Configure the device. */ err = zy7_qspi_init_hw(sc); if (err) { zy7_qspi_detach(dev); return (err); } sc->child = device_add_child(dev, "spibus", DEVICE_UNIT_ANY); zy7_qspi_add_sysctls(dev); /* Attach spibus driver as a child later when interrupts work. */ - config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); + bus_delayed_attach_children(dev); return (0); } static int zy7_qspi_detach(device_t dev) { struct zy7_qspi_softc *sc = device_get_softc(dev); if (device_is_attached(dev)) bus_generic_detach(dev); /* Delete child bus. */ if (sc->child) device_delete_child(dev, sc->child); /* Disable hardware. */ if (sc->mem_res != NULL) { /* Disable SPI. */ WR4(sc, ZY7_QSPI_EN_REG, 0); /* Clear and disable all interrupts. */ WR4(sc, ZY7_QSPI_INTR_STAT_REG, ~0); WR4(sc, ZY7_QSPI_INTR_DIS_REG, ~0); } /* Teardown and release interrupt. */ if (sc->irq_res != NULL) { if (sc->intrhandle) bus_teardown_intr(dev, sc->irq_res, sc->intrhandle); bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), sc->irq_res); } /* Release memory resource. */ if (sc->mem_res != NULL) bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res), sc->mem_res); QSPI_SC_LOCK_DESTROY(sc); return (0); } static phandle_t zy7_qspi_get_node(device_t bus, device_t dev) { return (ofw_bus_get_node(bus)); } static int zy7_qspi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct zy7_qspi_softc *sc = device_get_softc(dev); int err = 0; KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("TX/RX command sizes should be equal")); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("TX/RX data sizes should be equal")); if (sc->is_dual && cmd->tx_data_sz % 2 != 0) { device_printf(dev, "driver does not support odd byte data " "transfers in dual mode. (sz=%d)\n", cmd->tx_data_sz); return (EINVAL); } QSPI_SC_LOCK(sc); /* Wait for controller available. */ while (sc->busy != 0) { err = mtx_sleep(dev, &sc->sc_mtx, 0, "zqspi0", 0); if (err) { QSPI_SC_UNLOCK(sc); return (err); } } /* Start transfer. */ sc->busy = 1; sc->cmd = cmd; sc->tx_bytes = sc->cmd->tx_cmd_sz + sc->cmd->tx_data_sz; sc->tx_bytes_sent = 0; sc->rx_bytes = sc->cmd->rx_cmd_sz + sc->cmd->rx_data_sz; sc->rx_bytes_rcvd = 0; /* Enable interrupts. zy7_qspi_intr() will handle transfer. */ WR4(sc, ZY7_QSPI_INTR_EN_REG, ZY7_QSPI_INTR_TX_FIFO_NOT_FULL | ZY7_QSPI_INTR_RX_OVERFLOW); #ifdef SPI_XFER_U_PAGE /* XXX: future support for stacked memories. */ if (sc->is_stacked) { if ((cmd->flags & SPI_XFER_U_PAGE) != 0) sc->lqspi_cfg_shadow |= ZY7_QSPI_LQSPI_CFG_U_PAGE; else sc->lqspi_cfg_shadow &= ~ZY7_QSPI_LQSPI_CFG_U_PAGE; WR4(sc, ZY7_QSPI_LQSPI_CFG_REG, sc->lqspi_cfg_shadow); } #endif /* Assert CS. */ sc->cfg_reg_shadow &= ~ZY7_QSPI_CONFIG_PCS; WR4(sc, ZY7_QSPI_CONFIG_REG, sc->cfg_reg_shadow); /* Wait for completion. */ err = mtx_sleep(dev, &sc->sc_mtx, 0, "zqspi1", hz * 2); if (err) zy7_qspi_abort_transfer(sc); /* Release controller. */ sc->busy = 0; wakeup_one(dev); QSPI_SC_UNLOCK(sc); return (err); } static device_method_t zy7_qspi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, zy7_qspi_probe), DEVMETHOD(device_attach, zy7_qspi_attach), DEVMETHOD(device_detach, zy7_qspi_detach), /* SPI interface */ DEVMETHOD(spibus_transfer, zy7_qspi_transfer), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, zy7_qspi_get_node), DEVMETHOD_END }; static driver_t zy7_qspi_driver = { "zy7_qspi", zy7_qspi_methods, sizeof(struct zy7_qspi_softc), }; DRIVER_MODULE(zy7_qspi, simplebus, zy7_qspi_driver, 0, 0); DRIVER_MODULE(ofw_spibus, zy7_qspi, ofw_spibus_driver, 0, 0); SIMPLEBUS_PNP_INFO(compat_data); MODULE_DEPEND(zy7_qspi, ofw_spibus, 1, 1, 1); diff --git a/sys/arm/xilinx/zy7_spi.c b/sys/arm/xilinx/zy7_spi.c index bb21ca6eec43..a24ce542a860 100644 --- a/sys/arm/xilinx/zy7_spi.c +++ b/sys/arm/xilinx/zy7_spi.c @@ -1,590 +1,590 @@ /*- * Copyright (c) 2018 Thomas Skibo * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" static struct ofw_compat_data compat_data[] = { {"xlnx,zy7_spi", 1}, {"xlnx,zynq-spi-1.0", 1}, {"cdns,spi-r1p6", 1}, {NULL, 0} }; struct zy7_spi_softc { device_t dev; device_t child; struct mtx sc_mtx; struct resource *mem_res; struct resource *irq_res; void *intrhandle; uint32_t cfg_reg_shadow; uint32_t spi_clock; uint32_t ref_clock; unsigned int spi_clk_real_freq; unsigned int rx_overflows; unsigned int tx_underflows; unsigned int interrupts; unsigned int stray_ints; struct spi_command *cmd; int tx_bytes; /* tx_cmd_sz + tx_data_sz */ int tx_bytes_sent; int rx_bytes; /* rx_cmd_sz + rx_data_sz */ int rx_bytes_rcvd; int busy; }; #define ZY7_SPI_DEFAULT_SPI_CLOCK 50000000 #define SPI_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx) #define SPI_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) #define SPI_SC_LOCK_INIT(sc) \ mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), NULL, MTX_DEF) #define SPI_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx) #define SPI_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) /* * SPI device registers. * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. * (v1.12.1) December 6, 2017. Xilinx doc UG585. */ #define ZY7_SPI_CONFIG_REG 0x0000 #define ZY7_SPI_CONFIG_MODEFAIL_GEN_EN (1 << 17) #define ZY7_SPI_CONFIG_MAN_STRT (1 << 16) #define ZY7_SPI_CONFIG_MAN_STRT_EN (1 << 15) #define ZY7_SPI_CONFIG_MAN_CS (1 << 14) #define ZY7_SPI_CONFIG_CS_MASK (0xf << 10) #define ZY7_SPI_CONFIG_CS(x) ((0xf ^ (1 << (x))) << 10) #define ZY7_SPI_CONFIG_PERI_SEL (1 << 9) #define ZY7_SPI_CONFIG_REF_CLK (1 << 8) #define ZY7_SPI_CONFIG_BAUD_RATE_DIV_MASK (7 << 3) #define ZY7_SPI_CONFIG_BAUD_RATE_DIV_SHIFT 3 #define ZY7_SPI_CONFIG_BAUD_RATE_DIV(x) ((x) << 3) /* divide by 2< 0) { if (sc->tx_bytes_sent < sc->cmd->tx_cmd_sz) /* Writing command. */ byte = *((uint8_t *)sc->cmd->tx_cmd + sc->tx_bytes_sent); else /* Writing data. */ byte = *((uint8_t *)sc->cmd->tx_data + (sc->tx_bytes_sent - sc->cmd->tx_cmd_sz)); WR4(sc, ZY7_SPI_TX_DATA_REG, (uint32_t)byte); sc->tx_bytes_sent++; nbytes--; } } /* Read hardware fifo data into command response and data buffers. */ static void zy7_spi_read_fifo(struct zy7_spi_softc *sc) { uint8_t byte; do { byte = RD4(sc, ZY7_SPI_RX_DATA_REG) & 0xff; if (sc->rx_bytes_rcvd < sc->cmd->rx_cmd_sz) /* Reading command. */ *((uint8_t *)sc->cmd->rx_cmd + sc->rx_bytes_rcvd) = byte; else /* Reading data. */ *((uint8_t *)sc->cmd->rx_data + (sc->rx_bytes_rcvd - sc->cmd->rx_cmd_sz)) = byte; sc->rx_bytes_rcvd++; } while (sc->rx_bytes_rcvd < sc->rx_bytes && (RD4(sc, ZY7_SPI_INTR_STAT_REG) & ZY7_SPI_INTR_RX_FIFO_NOT_EMPTY) != 0); } /* End a transfer early by draining rx fifo and disabling interrupts. */ static void zy7_spi_abort_transfer(struct zy7_spi_softc *sc) { /* Drain receive fifo. */ while ((RD4(sc, ZY7_SPI_INTR_STAT_REG) & ZY7_SPI_INTR_RX_FIFO_NOT_EMPTY) != 0) (void)RD4(sc, ZY7_SPI_RX_DATA_REG); /* Shut down interrupts. */ WR4(sc, ZY7_SPI_INTR_DIS_REG, ZY7_SPI_INTR_RX_OVERFLOW | ZY7_SPI_INTR_RX_FIFO_NOT_EMPTY | ZY7_SPI_INTR_TX_FIFO_NOT_FULL); } static void zy7_spi_intr(void *arg) { struct zy7_spi_softc *sc = (struct zy7_spi_softc *)arg; uint32_t istatus; SPI_SC_LOCK(sc); sc->interrupts++; istatus = RD4(sc, ZY7_SPI_INTR_STAT_REG); /* Stray interrupts can happen if a transfer gets interrupted. */ if (!sc->busy) { sc->stray_ints++; SPI_SC_UNLOCK(sc); return; } if ((istatus & ZY7_SPI_INTR_RX_OVERFLOW) != 0) { device_printf(sc->dev, "rx fifo overflow!\n"); sc->rx_overflows++; /* Clear status bit. */ WR4(sc, ZY7_SPI_INTR_STAT_REG, ZY7_SPI_INTR_RX_OVERFLOW); } /* Empty receive fifo before any more transmit data is sent. */ if (sc->rx_bytes_rcvd < sc->rx_bytes && (istatus & ZY7_SPI_INTR_RX_FIFO_NOT_EMPTY) != 0) { zy7_spi_read_fifo(sc); if (sc->rx_bytes_rcvd == sc->rx_bytes) /* Disable receive interrupts. */ WR4(sc, ZY7_SPI_INTR_DIS_REG, ZY7_SPI_INTR_RX_FIFO_NOT_EMPTY | ZY7_SPI_INTR_RX_OVERFLOW); } /* Count tx underflows. They probably shouldn't happen. */ if ((istatus & ZY7_SPI_INTR_TX_FIFO_UNDERFLOW) != 0) { sc->tx_underflows++; /* Clear status bit. */ WR4(sc, ZY7_SPI_INTR_STAT_REG, ZY7_SPI_INTR_TX_FIFO_UNDERFLOW); } /* Fill transmit fifo. */ if (sc->tx_bytes_sent < sc->tx_bytes && (istatus & ZY7_SPI_INTR_TX_FIFO_NOT_FULL) != 0) { zy7_spi_write_fifo(sc, MIN(96, sc->tx_bytes - sc->tx_bytes_sent)); if (sc->tx_bytes_sent == sc->tx_bytes) { /* Disable transmit FIFO interrupt, enable receive * FIFO interrupt. */ WR4(sc, ZY7_SPI_INTR_DIS_REG, ZY7_SPI_INTR_TX_FIFO_NOT_FULL); WR4(sc, ZY7_SPI_INTR_EN_REG, ZY7_SPI_INTR_RX_FIFO_NOT_EMPTY); } } /* Finished with transfer? */ if (sc->tx_bytes_sent == sc->tx_bytes && sc->rx_bytes_rcvd == sc->rx_bytes) { /* De-assert CS. */ sc->cfg_reg_shadow &= ~(ZY7_SPI_CONFIG_CLK_PH | ZY7_SPI_CONFIG_CLK_POL); sc->cfg_reg_shadow |= ZY7_SPI_CONFIG_CS_MASK; WR4(sc, ZY7_SPI_CONFIG_REG, sc->cfg_reg_shadow); wakeup(sc->dev); } SPI_SC_UNLOCK(sc); } /* Initialize hardware. */ static int zy7_spi_init_hw(struct zy7_spi_softc *sc) { uint32_t baud_div; /* Find best clock divider. Divide by 2 not supported. */ baud_div = 1; while ((sc->ref_clock >> (baud_div + 1)) > sc->spi_clock && baud_div < 8) baud_div++; if (baud_div >= 8) { device_printf(sc->dev, "cannot configure clock divider: ref=%d" " spi=%d.\n", sc->ref_clock, sc->spi_clock); return (EINVAL); } sc->spi_clk_real_freq = sc->ref_clock >> (baud_div + 1); /* Set up configuration register. */ sc->cfg_reg_shadow = ZY7_SPI_CONFIG_MAN_CS | ZY7_SPI_CONFIG_CS_MASK | ZY7_SPI_CONFIG_BAUD_RATE_DIV(baud_div) | ZY7_SPI_CONFIG_MODE_SEL; WR4(sc, ZY7_SPI_CONFIG_REG, sc->cfg_reg_shadow); /* Set thresholds. */ WR4(sc, ZY7_SPI_TX_THRESH_REG, 32); WR4(sc, ZY7_SPI_RX_THRESH_REG, 1); /* Clear and disable all interrupts. */ WR4(sc, ZY7_SPI_INTR_STAT_REG, ~0); WR4(sc, ZY7_SPI_INTR_DIS_REG, ~0); /* Enable SPI. */ WR4(sc, ZY7_SPI_EN_REG, ZY7_SPI_ENABLE); return (0); } static void zy7_spi_add_sysctls(device_t dev) { struct zy7_spi_softc *sc = device_get_softc(dev); struct sysctl_ctx_list *ctx; struct sysctl_oid_list *child; ctx = device_get_sysctl_ctx(dev); child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "spi_clk_real_freq", CTLFLAG_RD, &sc->spi_clk_real_freq, 0, "SPI clock real frequency"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_overflows", CTLFLAG_RD, &sc->rx_overflows, 0, "RX FIFO overflow events"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_underflows", CTLFLAG_RD, &sc->tx_underflows, 0, "TX FIFO underflow events"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "interrupts", CTLFLAG_RD, &sc->interrupts, 0, "interrupt calls"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stray_ints", CTLFLAG_RD, &sc->stray_ints, 0, "stray interrupts"); } static int zy7_spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Zynq SPI Controller"); return (BUS_PROBE_DEFAULT); } static int zy7_spi_detach(device_t); static int zy7_spi_attach(device_t dev) { struct zy7_spi_softc *sc; int rid, err; phandle_t node; pcell_t cell; sc = device_get_softc(dev); sc->dev = dev; SPI_SC_LOCK_INIT(sc); /* Get ref-clock and spi-clock properties. */ node = ofw_bus_get_node(dev); if (OF_getprop(node, "ref-clock", &cell, sizeof(cell)) > 0) sc->ref_clock = fdt32_to_cpu(cell); else { device_printf(dev, "must have ref-clock property\n"); return (ENXIO); } if (OF_getprop(node, "spi-clock", &cell, sizeof(cell)) > 0) sc->spi_clock = fdt32_to_cpu(cell); else sc->spi_clock = ZY7_SPI_DEFAULT_SPI_CLOCK; /* Get memory resource. */ rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res == NULL) { device_printf(dev, "could not allocate memory resources.\n"); zy7_spi_detach(dev); return (ENOMEM); } /* Allocate IRQ. */ rid = 0; sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (sc->irq_res == NULL) { device_printf(dev, "could not allocate IRQ resource.\n"); zy7_spi_detach(dev); return (ENOMEM); } /* Activate the interrupt. */ err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, zy7_spi_intr, sc, &sc->intrhandle); if (err) { device_printf(dev, "could not setup IRQ.\n"); zy7_spi_detach(dev); return (err); } /* Configure the device. */ err = zy7_spi_init_hw(sc); if (err) { zy7_spi_detach(dev); return (err); } sc->child = device_add_child(dev, "spibus", DEVICE_UNIT_ANY); zy7_spi_add_sysctls(dev); /* Attach spibus driver as a child later when interrupts work. */ - config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); + bus_delayed_attach_children(dev); return (0); } static int zy7_spi_detach(device_t dev) { struct zy7_spi_softc *sc = device_get_softc(dev); if (device_is_attached(dev)) bus_generic_detach(dev); /* Delete child bus. */ if (sc->child) device_delete_child(dev, sc->child); /* Disable hardware. */ if (sc->mem_res != NULL) { /* Disable SPI. */ WR4(sc, ZY7_SPI_EN_REG, 0); /* Clear and disable all interrupts. */ WR4(sc, ZY7_SPI_INTR_STAT_REG, ~0); WR4(sc, ZY7_SPI_INTR_DIS_REG, ~0); } /* Teardown and release interrupt. */ if (sc->irq_res != NULL) { if (sc->intrhandle) bus_teardown_intr(dev, sc->irq_res, sc->intrhandle); bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), sc->irq_res); } /* Release memory resource. */ if (sc->mem_res != NULL) bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res), sc->mem_res); SPI_SC_LOCK_DESTROY(sc); return (0); } static phandle_t zy7_spi_get_node(device_t bus, device_t dev) { return (ofw_bus_get_node(bus)); } static int zy7_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct zy7_spi_softc *sc = device_get_softc(dev); uint32_t cs; uint32_t mode; int err = 0; KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("TX/RX command sizes should be equal")); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("TX/RX data sizes should be equal")); /* Get chip select and mode for this child. */ spibus_get_cs(child, &cs); cs &= ~SPIBUS_CS_HIGH; if (cs > 2) { device_printf(dev, "Invalid chip select %d requested by %s", cs, device_get_nameunit(child)); return (EINVAL); } spibus_get_mode(child, &mode); SPI_SC_LOCK(sc); /* Wait for controller available. */ while (sc->busy != 0) { err = mtx_sleep(dev, &sc->sc_mtx, 0, "zspi0", 0); if (err) { SPI_SC_UNLOCK(sc); return (err); } } /* Start transfer. */ sc->busy = 1; sc->cmd = cmd; sc->tx_bytes = sc->cmd->tx_cmd_sz + sc->cmd->tx_data_sz; sc->tx_bytes_sent = 0; sc->rx_bytes = sc->cmd->rx_cmd_sz + sc->cmd->rx_data_sz; sc->rx_bytes_rcvd = 0; /* Enable interrupts. zy7_spi_intr() will handle transfer. */ WR4(sc, ZY7_SPI_INTR_EN_REG, ZY7_SPI_INTR_TX_FIFO_NOT_FULL | ZY7_SPI_INTR_RX_OVERFLOW); /* Handle polarity and phase. */ if (mode == SPIBUS_MODE_CPHA || mode == SPIBUS_MODE_CPOL_CPHA) sc->cfg_reg_shadow |= ZY7_SPI_CONFIG_CLK_PH; if (mode == SPIBUS_MODE_CPOL || mode == SPIBUS_MODE_CPOL_CPHA) sc->cfg_reg_shadow |= ZY7_SPI_CONFIG_CLK_POL; /* Assert CS. */ sc->cfg_reg_shadow &= ~ZY7_SPI_CONFIG_CS_MASK; sc->cfg_reg_shadow |= ZY7_SPI_CONFIG_CS(cs); WR4(sc, ZY7_SPI_CONFIG_REG, sc->cfg_reg_shadow); /* Wait for completion. */ err = mtx_sleep(dev, &sc->sc_mtx, 0, "zspi1", hz * 2); if (err) zy7_spi_abort_transfer(sc); /* Release controller. */ sc->busy = 0; wakeup_one(dev); SPI_SC_UNLOCK(sc); return (err); } static device_method_t zy7_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, zy7_spi_probe), DEVMETHOD(device_attach, zy7_spi_attach), DEVMETHOD(device_detach, zy7_spi_detach), /* SPI interface */ DEVMETHOD(spibus_transfer, zy7_spi_transfer), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, zy7_spi_get_node), DEVMETHOD_END }; static driver_t zy7_spi_driver = { "zy7_spi", zy7_spi_methods, sizeof(struct zy7_spi_softc), }; DRIVER_MODULE(zy7_spi, simplebus, zy7_spi_driver, 0, 0); DRIVER_MODULE(ofw_spibus, zy7_spi, ofw_spibus_driver, 0, 0); SIMPLEBUS_PNP_INFO(compat_data); MODULE_DEPEND(zy7_spi, ofw_spibus, 1, 1, 1); diff --git a/sys/dev/iicbus/controller/opencores/iicoc_fdt.c b/sys/dev/iicbus/controller/opencores/iicoc_fdt.c index 4220b0798398..2423d2b87272 100644 --- a/sys/dev/iicbus/controller/opencores/iicoc_fdt.c +++ b/sys/dev/iicbus/controller/opencores/iicoc_fdt.c @@ -1,189 +1,189 @@ /*- * SPDX-License-Identifier: BSD-2-Clause * * Copyright (c) 2019 Axiado Corporation. * All rights reserved. * * This software was developed in part by Philip Paeps under contract for * Axiado Corporation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "iicbus_if.h" #include "iicoc.h" static struct ofw_compat_data compat_data[] = { { "opencores,i2c-ocores", 1 }, { "sifive,fu740-c000-i2c", 1 }, { "sifive,fu540-c000-i2c", 1 }, { "sifive,i2c0", 1 }, { NULL, 0 } }; static struct resource_spec iicoc_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, RESOURCE_SPEC_END }; static phandle_t iicoc_get_node(device_t bus, device_t dev) { /* Share controller node with iicbus device. */ return (ofw_bus_get_node(bus)); } static int iicoc_attach(device_t dev) { struct iicoc_softc *sc; phandle_t node; clk_t clock; uint64_t clockfreq; int error; sc = device_get_softc(dev); sc->dev = dev; mtx_init(&sc->sc_mtx, "iicoc", "iicoc", MTX_DEF); error = bus_alloc_resources(dev, iicoc_spec, &sc->mem_res); if (error) { device_printf(dev, "Could not allocate bus resource.\n"); goto fail; } node = ofw_bus_get_node(dev); sc->reg_shift = 0; OF_getencprop(node, "reg-shift", &sc->reg_shift, sizeof(sc->reg_shift)); error = clk_get_by_ofw_index(dev, 0, 0, &clock); if (error) { device_printf(dev, "Couldn't get clock\n"); goto fail; } error = clk_enable(clock); if (error) { device_printf(dev, "Couldn't enable clock\n"); goto fail1; } error = clk_get_freq(clock, &clockfreq); if (error) { device_printf(dev, "Couldn't get clock frequency\n"); goto fail1; } if (clockfreq > UINT_MAX) { device_printf(dev, "Unsupported clock frequency\n"); goto fail1; } sc->clockfreq = (u_int)clockfreq; sc->i2cfreq = XLP_I2C_FREQ; iicoc_init(dev); sc->iicbus = device_add_child(dev, "iicbus", DEVICE_UNIT_ANY); if (sc->iicbus == NULL) { device_printf(dev, "Could not allocate iicbus instance.\n"); error = ENXIO; goto fail1; } /* Probe and attach the iicbus when interrupts are available. */ - config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); + bus_delayed_attach_children(dev); return (0); fail1: clk_disable(clock); fail: bus_release_resources(dev, iicoc_spec, &sc->mem_res); mtx_destroy(&sc->sc_mtx); return (error); } static int iicoc_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "OpenCores I2C master controller"); return (BUS_PROBE_DEFAULT); } static device_method_t iicoc_methods[] = { /* device interface */ DEVMETHOD(device_probe, iicoc_probe), DEVMETHOD(device_attach, iicoc_attach), /* ofw interface */ DEVMETHOD(ofw_bus_get_node, iicoc_get_node), /* iicbus interface */ DEVMETHOD(iicbus_callback, iicbus_null_callback), DEVMETHOD(iicbus_repeated_start, iicoc_iicbus_repeated_start), DEVMETHOD(iicbus_start, iicoc_iicbus_start), DEVMETHOD(iicbus_stop, iicoc_iicbus_stop), DEVMETHOD(iicbus_reset, iicoc_iicbus_reset), DEVMETHOD(iicbus_write, iicoc_iicbus_write), DEVMETHOD(iicbus_read, iicoc_iicbus_read), DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), DEVMETHOD_END }; static driver_t iicoc_driver = { "iicoc", iicoc_methods, sizeof(struct iicoc_softc), }; SIMPLEBUS_PNP_INFO(compat_data); DRIVER_MODULE(iicoc, simplebus, iicoc_driver, 0, 0); DRIVER_MODULE(ofw_iicbus, iicoc, ofw_iicbus_driver, 0, 0); MODULE_DEPEND(iicoc, iicbus, 1, 1, 1); MODULE_DEPEND(iicoc, ofw_iicbus, 1, 1, 1); diff --git a/sys/riscv/sifive/sifive_spi.c b/sys/riscv/sifive/sifive_spi.c index e5e1e60223e9..486cf4209c10 100644 --- a/sys/riscv/sifive/sifive_spi.c +++ b/sys/riscv/sifive/sifive_spi.c @@ -1,400 +1,400 @@ /*- * SPDX-License-Identifier: BSD-2-Clause * * Copyright (c) 2019 Axiado Corporation * All rights reserved. * * This software was developed in part by Philip Paeps and Kristof Provost * under contract for Axiado Corporation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" #if 1 #define DBGPRINT(dev, fmt, args...) \ device_printf(dev, "%s: " fmt "\n", __func__, ## args) #else #define DBGPRINT(dev, fmt, args...) #endif static struct resource_spec sfspi_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, RESOURCE_SPEC_END }; struct sfspi_softc { device_t dev; device_t parent; struct mtx mtx; struct resource *res; bus_space_tag_t bst; bus_space_handle_t bsh; void *ih; clk_t clk; uint64_t freq; uint32_t cs_max; }; #define SFSPI_LOCK(sc) mtx_lock(&(sc)->mtx) #define SFSPI_UNLOCK(sc) mtx_unlock(&(sc)->mtx) #define SFSPI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); #define SFSPI_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); /* * Register offsets. * From Sifive-Unleashed-FU540-C000-v1.0.pdf page 101. */ #define SFSPI_REG_SCKDIV 0x00 /* Serial clock divisor */ #define SFSPI_REG_SCKMODE 0x04 /* Serial clock mode */ #define SFSPI_REG_CSID 0x10 /* Chip select ID */ #define SFSPI_REG_CSDEF 0x14 /* Chip select default */ #define SFSPI_REG_CSMODE 0x18 /* Chip select mode */ #define SFSPI_REG_DELAY0 0x28 /* Delay control 0 */ #define SFSPI_REG_DELAY1 0x2C /* Delay control 1 */ #define SFSPI_REG_FMT 0x40 /* Frame format */ #define SFSPI_REG_TXDATA 0x48 /* Tx FIFO data */ #define SFSPI_REG_RXDATA 0x4C /* Rx FIFO data */ #define SFSPI_REG_TXMARK 0x50 /* Tx FIFO watermark */ #define SFSPI_REG_RXMARK 0x54 /* Rx FIFO watermark */ #define SFSPI_REG_FCTRL 0x60 /* SPI flash interface control* */ #define SFSPI_REG_FFMT 0x64 /* SPI flash instruction format* */ #define SFSPI_REG_IE 0x70 /* SPI interrupt enable */ #define SFSPI_REG_IP 0x74 /* SPI interrupt pending */ #define SFSPI_SCKDIV_MASK 0xfff #define SFSPI_CSDEF_ALL ((1 << sc->cs_max)-1) #define SFSPI_CSMODE_AUTO 0x0U #define SFSPI_CSMODE_HOLD 0x2U #define SFSPI_CSMODE_OFF 0x3U #define SFSPI_TXDATA_DATA_MASK 0xff #define SFSPI_TXDATA_FULL (1 << 31) #define SFSPI_RXDATA_DATA_MASK 0xff #define SFSPI_RXDATA_EMPTY (1 << 31) #define SFSPI_SCKMODE_PHA (1 << 0) #define SFSPI_SCKMODE_POL (1 << 1) #define SFSPI_FMT_PROTO_SINGLE 0x0U #define SFSPI_FMT_PROTO_DUAL 0x1U #define SFSPI_FMT_PROTO_QUAD 0x2U #define SFSPI_FMT_PROTO_MASK 0x3U #define SFSPI_FMT_ENDIAN (1 << 2) #define SFSPI_FMT_DIR (1 << 3) #define SFSPI_FMT_LEN(x) ((uint32_t)(x) << 16) #define SFSPI_FMT_LEN_MASK (0xfU << 16) #define SFSPI_FIFO_DEPTH 8 #define SFSPI_READ(_sc, _reg) \ bus_space_read_4((_sc)->bst, (_sc)->bsh, (_reg)) #define SFSPI_WRITE(_sc, _reg, _val) \ bus_space_write_4((_sc)->bst, (_sc)->bsh, (_reg), (_val)) static void sfspi_tx(struct sfspi_softc *sc, uint8_t *buf, uint32_t bufsiz) { uint32_t val; uint8_t *p, *end; KASSERT(buf != NULL, ("TX buffer cannot be NULL")); end = buf + bufsiz; for (p = buf; p < end; p++) { do { val = SFSPI_READ(sc, SFSPI_REG_TXDATA); } while (val & SFSPI_TXDATA_FULL); val = *p; SFSPI_WRITE(sc, SFSPI_REG_TXDATA, val); } } static void sfspi_rx(struct sfspi_softc *sc, uint8_t *buf, uint32_t bufsiz) { uint32_t val; uint8_t *p, *end; KASSERT(buf != NULL, ("RX buffer cannot be NULL")); KASSERT(bufsiz <= SFSPI_FIFO_DEPTH, ("Cannot receive more than %d bytes at a time\n", SFSPI_FIFO_DEPTH)); end = buf + bufsiz; for (p = buf; p < end; p++) { do { val = SFSPI_READ(sc, SFSPI_REG_RXDATA); } while (val & SFSPI_RXDATA_EMPTY); *p = val & SFSPI_RXDATA_DATA_MASK; }; } static int sfspi_xfer_buf(struct sfspi_softc *sc, uint8_t *rxbuf, uint8_t *txbuf, uint32_t txlen, uint32_t rxlen) { uint32_t bytes; KASSERT(txlen == rxlen, ("TX and RX lengths must be equal")); KASSERT(rxbuf != NULL, ("RX buffer cannot be NULL")); KASSERT(txbuf != NULL, ("TX buffer cannot be NULL")); while (txlen) { bytes = (txlen > SFSPI_FIFO_DEPTH) ? SFSPI_FIFO_DEPTH : txlen; sfspi_tx(sc, txbuf, bytes); txbuf += bytes; sfspi_rx(sc, rxbuf, bytes); rxbuf += bytes; txlen -= bytes; } return (0); } static int sfspi_setup(struct sfspi_softc *sc, uint32_t cs, uint32_t mode, uint32_t freq) { uint32_t csmode, fmt, sckdiv, sckmode; SFSPI_ASSERT_LOCKED(sc); /* * Fsck = Fin / 2 * (div + 1) * -> div = Fin / (2 * Fsck) - 1 */ sckdiv = (howmany(sc->freq >> 1, freq) - 1) & SFSPI_SCKDIV_MASK; SFSPI_WRITE(sc, SFSPI_REG_SCKDIV, sckdiv); switch (mode) { case SPIBUS_MODE_NONE: sckmode = 0; break; case SPIBUS_MODE_CPHA: sckmode = SFSPI_SCKMODE_PHA; break; case SPIBUS_MODE_CPOL: sckmode = SFSPI_SCKMODE_POL; break; case SPIBUS_MODE_CPOL_CPHA: sckmode = SFSPI_SCKMODE_PHA | SFSPI_SCKMODE_POL; break; default: return (EINVAL); } SFSPI_WRITE(sc, SFSPI_REG_SCKMODE, sckmode); csmode = SFSPI_CSMODE_HOLD; if (cs & SPIBUS_CS_HIGH) csmode = SFSPI_CSMODE_AUTO; SFSPI_WRITE(sc, SFSPI_REG_CSMODE, csmode); SFSPI_WRITE(sc, SFSPI_REG_CSID, cs & ~SPIBUS_CS_HIGH); fmt = SFSPI_FMT_PROTO_SINGLE | SFSPI_FMT_LEN(8); SFSPI_WRITE(sc, SFSPI_REG_FMT, fmt); return (0); } static int sfspi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct sfspi_softc *sc; uint32_t clock, cs, csdef, mode; int err; KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("TX and RX command sizes must be equal")); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("TX and RX data sizes must be equal")); sc = device_get_softc(dev); spibus_get_cs(child, &cs); spibus_get_clock(child, &clock); spibus_get_mode(child, &mode); if (cs > sc->cs_max) { device_printf(sc->dev, "Invalid chip select %u\n", cs); return (EINVAL); } SFSPI_LOCK(sc); device_busy(sc->dev); err = sfspi_setup(sc, cs, mode, clock); if (err != 0) { SFSPI_UNLOCK(sc); return (err); } err = 0; if (cmd->tx_cmd_sz > 0) err = sfspi_xfer_buf(sc, cmd->rx_cmd, cmd->tx_cmd, cmd->tx_cmd_sz, cmd->rx_cmd_sz); if (cmd->tx_data_sz > 0 && err == 0) err = sfspi_xfer_buf(sc, cmd->rx_data, cmd->tx_data, cmd->tx_data_sz, cmd->rx_data_sz); /* Deassert chip select. */ csdef = SFSPI_CSDEF_ALL & ~(1 << cs); SFSPI_WRITE(sc, SFSPI_REG_CSDEF, csdef); SFSPI_WRITE(sc, SFSPI_REG_CSDEF, SFSPI_CSDEF_ALL); device_unbusy(sc->dev); SFSPI_UNLOCK(sc); return (err); } static int sfspi_attach(device_t dev) { struct sfspi_softc *sc; int error; sc = device_get_softc(dev); sc->dev = dev; mtx_init(&sc->mtx, device_get_nameunit(sc->dev), NULL, MTX_DEF); error = bus_alloc_resources(dev, sfspi_spec, &sc->res); if (error) { device_printf(dev, "Couldn't allocate resources\n"); goto fail; } sc->bst = rman_get_bustag(sc->res); sc->bsh = rman_get_bushandle(sc->res); error = clk_get_by_ofw_index(dev, 0, 0, &sc->clk); if (error) { device_printf(dev, "Couldn't allocate clock: %d\n", error); goto fail; } error = clk_enable(sc->clk); if (error) { device_printf(dev, "Couldn't enable clock: %d\n", error); goto fail; } error = clk_get_freq(sc->clk, &sc->freq); if (error) { device_printf(sc->dev, "Couldn't get frequency: %d\n", error); goto fail; } /* * From Sifive-Unleashed-FU540-C000-v1.0.pdf page 103: * csdef is cs_width bits wide and all ones on reset. */ sc->cs_max = SFSPI_READ(sc, SFSPI_REG_CSDEF); /* * We don't support the direct-mapped flash interface. * Disable it. */ SFSPI_WRITE(sc, SFSPI_REG_FCTRL, 0x0); /* Probe and attach the spibus when interrupts are available. */ sc->parent = device_add_child(dev, "spibus", DEVICE_UNIT_ANY); - config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); + bus_delayed_attach_children(dev); return (0); fail: bus_release_resources(dev, sfspi_spec, &sc->res); mtx_destroy(&sc->mtx); return (error); } static int sfspi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "sifive,spi0")) return (ENXIO); device_set_desc(dev, "SiFive SPI controller"); return (BUS_PROBE_DEFAULT); } static phandle_t sfspi_get_node(device_t bus, device_t dev) { return (ofw_bus_get_node(bus)); } static device_method_t sfspi_methods[] = { DEVMETHOD(device_probe, sfspi_probe), DEVMETHOD(device_attach, sfspi_attach), DEVMETHOD(spibus_transfer, sfspi_transfer), DEVMETHOD(ofw_bus_get_node, sfspi_get_node), DEVMETHOD_END }; static driver_t sfspi_driver = { "sifive_spi", sfspi_methods, sizeof(struct sfspi_softc) }; DRIVER_MODULE(sifive_spi, simplebus, sfspi_driver, 0, 0); DRIVER_MODULE(ofw_spibus, sifive_spi, ofw_spibus_driver, 0, 0); MODULE_DEPEND(sifive_spi, ofw_spibus, 1, 1, 1);