diff --git a/sys/riscv/conf/GENERIC b/sys/riscv/conf/GENERIC
--- a/sys/riscv/conf/GENERIC
+++ b/sys/riscv/conf/GENERIC
@@ -201,6 +201,7 @@
 
 # Include SoC specific configuration
 include		"std.allwinner"
+include		"std.cvitek"
 include		"std.eswin"
 include		"std.sifive"
 include		"std.starfive"
diff --git a/sys/riscv/conf/std.cvitek b/sys/riscv/conf/std.cvitek
new file mode 100644
--- /dev/null
+++ b/sys/riscv/conf/std.cvitek
@@ -0,0 +1,14 @@
+#
+# CVITEK SoC support
+#
+
+device	fdt
+device	dwc
+device	dwgpio
+device	uart_snps
+device	dwc_cvitek
+device	sdhci_cvitek
+device	cvitek_reset
+device	cvitek_restart
+
+files	"../cvitek/files.cvitek"
diff --git a/sys/riscv/cvitek/files.cvitek b/sys/riscv/cvitek/files.cvitek
new file mode 100644
--- /dev/null
+++ b/sys/riscv/cvitek/files.cvitek
@@ -0,0 +1,4 @@
+riscv/cvitek/cvitek_restart.c		optional fdt cvitek_restart
+riscv/cvitek/cvitek_reset.c		optional fdt cvitek_reset
+dev/dwc/if_dwc_cvitek.c			optional fdt dwc_cvitek
+dev/sdhci/sdhci_fdt_cvitek.c		optional fdt sdhci sdhci_cvitek regulator