diff --git a/sys/arm/qualcomm/std.ipq4018 b/sys/arm/qualcomm/std.ipq4018 index 89d2cb546bf3..1c70ecc448bd 100644 --- a/sys/arm/qualcomm/std.ipq4018 +++ b/sys/arm/qualcomm/std.ipq4018 @@ -1,66 +1,68 @@ arm/qualcomm/ipq4018_machdep.c standard arm/qualcomm/ipq4018_mp.c optional smp arm/qualcomm/qcom_scm_legacy.c standard arm/qualcomm/qcom_cpu_kpssv2.c optional smp arm/qualcomm/ipq4018_usb_hs_phy.c optional qcom_ipq4018_hs_usbphy arm/qualcomm/ipq4018_usb_ss_phy.c optional qcom_ipq4018_ss_usbphy dev/etherswitch/ar40xx/ar40xx_main.c \ optional mdio etherswitch ar40xx_switch dev/etherswitch/ar40xx/ar40xx_phy.c \ optional mdio etherswitch ar40xx_switch dev/etherswitch/ar40xx/ar40xx_hw.c \ optional mdio etherswitch ar40xx_switch dev/etherswitch/ar40xx/ar40xx_hw_atu.c \ optional mdio etherswitch ar40xx_switch dev/etherswitch/ar40xx/ar40xx_hw_port.c \ optional mdio etherswitch ar40xx_switch dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c \ optional mdio etherswitch ar40xx_switch dev/etherswitch/ar40xx/ar40xx_hw_mib.c \ optional mdio etherswitch ar40xx_switch dev/etherswitch/ar40xx/ar40xx_hw_mirror.c \ optional mdio etherswitch ar40xx_switch dev/etherswitch/ar40xx/ar40xx_hw_vtu.c \ optional mdio etherswitch ar40xx_switch dev/etherswitch/ar40xx/ar40xx_hw_mdio.c \ optional mdio etherswitch ar40xx_switch dev/qcom_dwc3/qcom_dwc3.c optional qcom_dwc3 dev/qcom_rnd/qcom_rnd.c optional qcom_rnd dev/qcom_qup/qcom_spi.c optional qcom_qup_spi dev/qcom_qup/qcom_spi_hw.c optional qcom_qup_spi dev/qcom_gcc/qcom_gcc_main.c optional qcom_gcc dev/qcom_gcc/qcom_gcc_clock.c optional qcom_gcc dev/qcom_gcc/qcom_gcc_reset.c optional qcom_gcc dev/qcom_gcc/qcom_gcc_ipq4018_reset.c optional qcom_gcc dev/qcom_gcc/qcom_gcc_ipq4018_clock.c optional qcom_gcc +dev/qcom_gcc/qcom_gcc_msm8916_reset.c optional qcom_gcc +dev/qcom_gcc/qcom_gcc_msm8916_clock.c optional qcom_gcc dev/qcom_clk/qcom_clk_fepll.c optional qcom_gcc dev/qcom_clk/qcom_clk_fdiv.c optional qcom_gcc dev/qcom_clk/qcom_clk_apssdiv.c optional qcom_gcc dev/qcom_clk/qcom_clk_freqtbl.c optional qcom_gcc dev/qcom_clk/qcom_clk_rcg2.c optional qcom_gcc dev/qcom_clk/qcom_clk_branch2.c optional qcom_gcc dev/qcom_clk/qcom_clk_ro_div.c optional qcom_gcc dev/qcom_tlmm/qcom_tlmm_debug.c optional qcom_tlmm_ipq4018 dev/qcom_tlmm/qcom_tlmm_ipq4018.c optional qcom_tlmm_ipq4018 dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c optional qcom_tlmm_ipq4018 dev/qcom_tlmm/qcom_tlmm_pin.c optional qcom_tlmm_ipq4018 dev/qcom_tlmm/qcom_tlmm_pinmux.c optional qcom_tlmm_ipq4018 dev/qcom_tcsr/qcom_tcsr.c optional qcom_tcsr dev/qcom_mdio/qcom_mdio_ipq4018.c optional qcom_mdio_ipq4018 dev/qcom_ess_edma/qcom_ess_edma.c optional qcom_ess_edma dev/qcom_ess_edma/qcom_ess_edma_desc.c optional qcom_ess_edma dev/qcom_ess_edma/qcom_ess_edma_gmac.c optional qcom_ess_edma dev/qcom_ess_edma/qcom_ess_edma_hw.c optional qcom_ess_edma dev/qcom_ess_edma/qcom_ess_edma_rx.c optional qcom_ess_edma dev/qcom_ess_edma/qcom_ess_edma_tx.c optional qcom_ess_edma diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64 index 59a65a8251ca..c36a391d75a2 100644 --- a/sys/conf/files.arm64 +++ b/sys/conf/files.arm64 @@ -1,829 +1,842 @@ ## ## Kernel ## kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_efi_map.c standard kern/subr_intr.c optional intrng kern/subr_physmem.c standard libkern/strlen.c standard libkern/arm64/crc32c_armv8.S standard arm/arm/generic_timer.c standard arm/arm/gic.c standard arm/arm/gic_acpi.c optional acpi arm/arm/gic_fdt.c optional fdt arm/arm/gic_if.m standard arm/arm/pmu.c standard arm/arm/pmu_acpi.c optional acpi arm/arm/pmu_fdt.c optional fdt arm64/acpica/acpi_iort.c optional acpi arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/spe/arm_spe_backend.c optional hwt spe arm64/spe/arm_spe_dev.c optional hwt spe arm64/spe/arm_spe_acpi.c optional hwt spe acpi arm64/spe/arm_spe_fdt.c optional hwt spe fdt arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/copyinout_ifunc.c standard arm64/arm64/cpu_errata.c standard arm64/arm64/cpu_feat.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c standard arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/efirt_machdep.c optional efirt arm64/arm64/efirt_support.S optional efirt arm64/arm64/elf32_machdep.c optional compat_freebsd32 arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/exec_machdep.c standard arm64/arm64/freebsd32_machdep.c optional compat_freebsd32 arm64/arm64/gdb_machdep.c optional gdb arm64/arm64/gicv3_its.c optional intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_acpi.c optional acpi arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/hyp_stub.S standard arm64/arm64/identcpu.c standard arm64/arm64/kexec_support.c standard arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/machdep_boot.c standard arm64/arm64/mem.c standard arm64/arm64/memcmp.S standard arm64/arm64/memcpy.S standard arm64/arm64/memset.S standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pl031_rtc.c optional fdt pl031 arm64/arm64/ptrauth.c standard \ compile-with "${NORMAL_C:N-mbranch-protection*} -mbranch-protection=bti" arm64/arm64/pmap.c standard arm64/arm64/ptrace_machdep.c standard arm64/arm64/sdt_machdep.c optional kdtrace_hooks arm64/arm64/sigtramp.S standard arm64/arm64/spec_workaround.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/strcmp.S standard arm64/arm64/strncmp.S standard arm64/arm64/support_ifunc.c standard arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/undefined.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack \ compile-with "${NOSAN_C}" arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard arm64/coresight/coresight.c standard arm64/coresight/coresight_acpi.c optional acpi arm64/coresight/coresight_fdt.c optional fdt arm64/coresight/coresight_if.m standard arm64/coresight/coresight_cmd.c standard arm64/coresight/coresight_cpu_debug.c optional fdt arm64/coresight/coresight_etm4x.c standard arm64/coresight/coresight_etm4x_acpi.c optional acpi arm64/coresight/coresight_etm4x_fdt.c optional fdt arm64/coresight/coresight_funnel.c standard arm64/coresight/coresight_funnel_acpi.c optional acpi arm64/coresight/coresight_funnel_fdt.c optional fdt arm64/coresight/coresight_replicator.c standard arm64/coresight/coresight_replicator_acpi.c optional acpi arm64/coresight/coresight_replicator_fdt.c optional fdt arm64/coresight/coresight_tmc.c standard arm64/coresight/coresight_tmc_acpi.c optional acpi arm64/coresight/coresight_tmc_fdt.c optional fdt dev/smbios/smbios_subr.c standard arm64/iommu/iommu.c optional iommu arm64/iommu/iommu_if.m optional iommu arm64/iommu/iommu_pmap.c optional iommu arm64/iommu/smmu.c optional iommu arm64/iommu/smmu_acpi.c optional iommu acpi arm64/iommu/smmu_fdt.c optional iommu fdt arm64/iommu/smmu_quirks.c optional iommu dev/iommu/busdma_iommu.c optional iommu dev/iommu/iommu_gas.c optional iommu arm64/vmm/vmm.c optional vmm arm64/vmm/vmm_dev_machdep.c optional vmm arm64/vmm/vmm_instruction_emul.c optional vmm arm64/vmm/vmm_arm64.c optional vmm arm64/vmm/vmm_reset.c optional vmm arm64/vmm/vmm_handlers.c optional vmm arm64/vmm/vmm_call.S optional vmm arm64/vmm/vmm_nvhe_exception.S optional vmm \ dependency "$S/arm64/vmm/vmm_hyp_exception.S" \ compile-with "${NOSAN_C} -fpie" \ no-obj arm64/vmm/vmm_nvhe.c optional vmm \ dependency "$S/arm64/vmm/vmm_hyp.c" \ compile-with "${NOSAN_C} -fpie" \ no-obj vmm_hyp_blob.elf.full optional vmm \ dependency "vmm_nvhe.o vmm_nvhe_exception.o" \ compile-with "${SYSTEM_LD_BASECMD} -o ${.TARGET} ${.ALLSRC} --defsym=_start='0x0' --defsym=text_start='0x0'" \ no-obj no-implicit-rule vmm_hyp_blob.elf optional vmm \ dependency "vmm_hyp_blob.elf.full" \ compile-with "${OBJCOPY} --strip-debug ${.ALLSRC} ${.TARGET}" \ no-obj no-implicit-rule vmm_hyp_blob.bin optional vmm \ dependency vmm_hyp_blob.elf \ compile-with "${OBJCOPY} --output-target=binary ${.ALLSRC} ${.TARGET}" \ no-obj no-implicit-rule arm64/vmm/vmm_hyp_el2.S optional vmm \ dependency vmm_hyp_blob.bin arm64/vmm/vmm_mmu.c optional vmm arm64/vmm/vmm_vhe.c optional vmm arm64/vmm/vmm_vhe_exception.S optional vmm arm64/vmm/io/vgic.c optional vmm arm64/vmm/io/vgic_v3.c optional vmm arm64/vmm/io/vgic_if.m optional vmm arm64/vmm/io/vtimer.c optional vmm dev/vmm/vmm_dev.c optional vmm dev/vmm/vmm_mem.c optional vmm dev/vmm/vmm_stat.c optional vmm crypto/armv8/armv8_crypto.c optional armv8crypto armv8_crypto_wrap.o optional armv8crypto \ dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8 ${WERROR} ${NO_WCAST_QUAL} ${CFLAGS:M-march=*:S/^$/-march=armv8-a/}+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "armv8_crypto_wrap.o" aesv8-armx.o optional armv8crypto | ossl \ dependency "$S/crypto/openssl/aarch64/aesv8-armx.S" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8 -I$S/crypto/openssl ${WERROR} ${NO_WCAST_QUAL} ${CFLAGS:M-march=*:S/^$/-march=armv8-a/}+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "aesv8-armx.o" ghashv8-armx.o optional armv8crypto \ dependency "$S/crypto/openssl/aarch64/ghashv8-armx.S" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8 -I$S/crypto/openssl ${WERROR} ${NO_WCAST_QUAL} ${CFLAGS:M-march=*:S/^$/-march=armv8-a/}+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "ghashv8-armx.o" crypto/des/des_enc.c optional netsmb crypto/openssl/ossl_aarch64.c optional ossl crypto/openssl/aarch64/chacha-armv8.S optional ossl \ compile-with "${CC} -c ${CFLAGS:N-mgeneral-regs-only} -I$S/crypto/openssl ${WERROR} ${.IMPSRC}" crypto/openssl/aarch64/chacha-armv8-sve.S optional ossl \ compile-with "${CC} -c ${CFLAGS:N-mgeneral-regs-only} -I$S/crypto/openssl ${WERROR} ${.IMPSRC}" crypto/openssl/aarch64/poly1305-armv8.S optional ossl \ compile-with "${CC} -c ${CFLAGS:N-mgeneral-regs-only} -I$S/crypto/openssl ${WERROR} ${.IMPSRC}" crypto/openssl/aarch64/sha1-armv8.S optional ossl \ compile-with "${CC} -c ${CFLAGS:N-mgeneral-regs-only} -I$S/crypto/openssl ${WERROR} ${.IMPSRC}" crypto/openssl/aarch64/sha256-armv8.S optional ossl \ compile-with "${CC} -c ${CFLAGS:N-mgeneral-regs-only} -I$S/crypto/openssl ${WERROR} ${.IMPSRC}" crypto/openssl/aarch64/sha512-armv8.S optional ossl \ compile-with "${CC} -c ${CFLAGS:N-mgeneral-regs-only} -I$S/crypto/openssl ${WERROR} ${.IMPSRC}" crypto/openssl/aarch64/vpaes-armv8.S optional ossl \ compile-with "${CC} -c ${CFLAGS:N-mgeneral-regs-only} -I$S/crypto/openssl ${WERROR} ${.IMPSRC}" dev/acpica/acpi_bus_if.m optional acpi dev/acpica/acpi_if.m optional acpi dev/acpica/acpi_pci.c optional acpi pci dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/acpica/acpi_pxm.c optional acpi dev/acpi_support/acpi_wmi_if.m optional acpi acpi_wmi dev/ahci/ahci_generic.c optional ahci cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_isa.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" # zfs blake3 hash support contrib/openzfs/module/icp/asm-aarch64/blake3/b3_aarch64_sse2.S optional zfs compile-with "${ZFS_S:N-mgeneral-regs-only}" contrib/openzfs/module/icp/asm-aarch64/blake3/b3_aarch64_sse41.S optional zfs compile-with "${ZFS_S:N-mgeneral-regs-only}" # zfs sha2 hash support zfs-sha256-armv8.o optional zfs \ dependency "$S/contrib/openzfs/module/icp/asm-aarch64/sha2/sha256-armv8.S" \ compile-with "${CC} -c ${ZFS_ASM_CFLAGS:N-mgeneral-regs-only} -o ${.TARGET} ${WERROR} $S/contrib/openzfs/module/icp/asm-aarch64/sha2/sha256-armv8.S" \ no-implicit-rule \ clean "zfs-sha256-armv8.o" zfs-sha512-armv8.o optional zfs \ dependency "$S/contrib/openzfs/module/icp/asm-aarch64/sha2/sha512-armv8.S" \ compile-with "${CC} -c ${ZFS_ASM_CFLAGS:N-mgeneral-regs-only} -o ${.TARGET} ${WERROR} $S/contrib/openzfs/module/icp/asm-aarch64/sha2/sha512-armv8.S" \ no-implicit-rule \ clean "zfs-sha512-armv8.o" ## ## ASoC support ## dev/sound/fdt/audio_dai_if.m optional sound fdt dev/sound/fdt/audio_soc.c optional sound fdt dev/sound/fdt/dummy_codec.c optional sound fdt dev/sound/fdt/simple_amplifier.c optional sound fdt ## ## Device drivers ## dev/axgbe/if_axgbe.c optional axa fdt dev/axgbe/xgbe-desc.c optional axa fdt dev/axgbe/xgbe-dev.c optional axa fdt dev/axgbe/xgbe-drv.c optional axa fdt dev/axgbe/xgbe-mdio.c optional axa fdt dev/axgbe/xgbe-sysctl.c optional axa fdt dev/axgbe/xgbe-txrx.c optional axa fdt dev/axgbe/xgbe_osdep.c optional axa fdt dev/axgbe/xgbe-phy-v1.c optional axa fdt dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/dpaa2/dpaa2_bp.c optional soc_nxp_ls dpaa2 dev/dpaa2/dpaa2_buf.c optional soc_nxp_ls dpaa2 dev/dpaa2/dpaa2_channel.c optional soc_nxp_ls dpaa2 dev/dpaa2/dpaa2_cmd_if.m optional soc_nxp_ls dpaa2 dev/dpaa2/dpaa2_con.c optional soc_nxp_ls dpaa2 dev/dpaa2/dpaa2_console.c optional soc_nxp_ls dpaa2 fdt dev/dpaa2/dpaa2_frame.c optional soc_nxp_ls dpaa2 dev/dpaa2/dpaa2_io.c optional soc_nxp_ls dpaa2 dev/dpaa2/dpaa2_mac.c optional soc_nxp_ls dpaa2 dev/dpaa2/dpaa2_mc.c optional soc_nxp_ls dpaa2 dev/dpaa2/dpaa2_mc_acpi.c optional soc_nxp_ls dpaa2 acpi dev/dpaa2/dpaa2_mc_fdt.c optional soc_nxp_ls dpaa2 fdt dev/dpaa2/dpaa2_mc_if.m optional soc_nxp_ls dpaa2 dev/dpaa2/dpaa2_mcp.c optional soc_nxp_ls dpaa2 dev/dpaa2/dpaa2_ni.c optional soc_nxp_ls dpaa2 dev/dpaa2/dpaa2_rc.c optional soc_nxp_ls dpaa2 dev/dpaa2/dpaa2_swp.c optional soc_nxp_ls dpaa2 dev/dpaa2/dpaa2_swp_if.m optional soc_nxp_ls dpaa2 dev/dpaa2/dpaa2_types.c optional soc_nxp_ls dpaa2 dev/dpaa2/memac_mdio_acpi.c optional soc_nxp_ls dpaa2 acpi dev/dpaa2/memac_mdio_common.c optional soc_nxp_ls dpaa2 acpi | soc_nxp_ls dpaa2 fdt dev/dpaa2/memac_mdio_fdt.c optional soc_nxp_ls dpaa2 fdt dev/dpaa2/memac_mdio_if.m optional soc_nxp_ls dpaa2 acpi | soc_nxp_ls dpaa2 fdt # Synopsys DesignWare Ethernet Controller dev/dwc/if_dwc_rk.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 dev/dwc/if_dwc_socfpga.c optional fdt dwc_socfpga dev/enetc/enetc_mdio.c optional enetc soc_nxp_ls dev/enetc/if_enetc.c optional enetc iflib pci fdt soc_nxp_ls dev/eqos/if_eqos.c optional eqos dev/eqos/if_eqos_if.m optional eqos dev/eqos/if_eqos_fdt.c optional eqos fdt dev/etherswitch/felix/felix.c optional enetc etherswitch fdt felix pci soc_nxp_ls dev/firmware/arm/scmi.c optional fdt scmi dev/firmware/arm/scmi_clk.c optional fdt scmi dev/firmware/arm/scmi_if.m optional fdt scmi dev/firmware/arm/scmi_mailbox.c optional fdt scmi dev/firmware/arm/scmi_smc.c optional fdt scmi dev/firmware/arm/scmi_virtio.c optional fdt scmi virtio dev/firmware/arm/scmi_shmem.c optional fdt scmi dev/gpio/pl061.c optional pl061 gpio dev/gpio/pl061_acpi.c optional pl061 gpio acpi dev/gpio/pl061_fdt.c optional pl061 gpio fdt dev/gpio/qoriq_gpio.c optional soc_nxp_ls gpio fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/hwpmc/hwpmc_cmn600.c optional hwpmc acpi arm64/arm64/cmn600.c optional hwpmc acpi dev/hwpmc/hwpmc_dmc620.c optional hwpmc acpi dev/hwpmc/pmu_dmc620.c optional hwpmc acpi # Microsoft Hyper-V dev/hyperv/vmbus/hyperv.c optional hyperv acpi dev/hyperv/vmbus/aarch64/hyperv_aarch64.c optional hyperv acpi dev/hyperv/vmbus/vmbus.c optional hyperv acpi pci dev/hyperv/vmbus/aarch64/vmbus_aarch64.c optional hyperv acpi dev/hyperv/vmbus/vmbus_if.m optional hyperv acpi dev/hyperv/vmbus/vmbus_res.c optional hyperv acpi dev/hyperv/vmbus/vmbus_xact.c optional hyperv acpi dev/hyperv/vmbus/aarch64/hyperv_machdep.c optional hyperv acpi dev/hyperv/vmbus/vmbus_chan.c optional hyperv acpi dev/hyperv/vmbus/hyperv_busdma.c optional hyperv acpi dev/hyperv/vmbus/vmbus_br.c optional hyperv acpi dev/hyperv/storvsc/hv_storvsc_drv_freebsd.c optional hyperv acpi dev/hyperv/utilities/vmbus_timesync.c optional hyperv acpi dev/hyperv/utilities/vmbus_heartbeat.c optional hyperv acpi dev/hyperv/utilities/vmbus_ic.c optional hyperv acpi dev/hyperv/utilities/vmbus_shutdown.c optional hyperv acpi dev/hyperv/utilities/hv_kvp.c optional hyperv acpi dev/hyperv/input/hv_kbd.c optional hyperv acpi dev/hyperv/input/hv_kbdc.c optional hyperv acpi dev/hyperv/netvsc/hn_nvs.c optional hyperv acpi dev/hyperv/netvsc/hn_rndis.c optional hyperv acpi dev/hyperv/netvsc/if_hn.c optional hyperv acpi dev/hyperv/pcib/vmbus_pcib.c optional hyperv pci acpi dev/ice/if_ice_iflib.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_lib.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_osdep.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_resmgr.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_strings.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_iflib_recovery_txrx.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_iflib_txrx.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_common.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_controlq.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_dcb.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_flex_pipe.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_flow.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_nvm.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_sched.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_switch.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_vlan_mode.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_fw_logging.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_fwlog.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_rdma.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/irdma_if.m optional ice pci \ compile-with "${NORMAL_M} -I$S/dev/ice" dev/ice/irdma_di_if.m optional ice pci \ compile-with "${NORMAL_M} -I$S/dev/ice" dev/ice/ice_ddp_common.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_iov.c optional ice pci pci_iov \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_vf_mbx.c optional ice pci pci_iov \ compile-with "${NORMAL_C} -I$S/dev/ice" ice_ddp.c optional ice_ddp \ compile-with "${AWK} -f $S/tools/fw_stub.awk ice_ddp.fw:ice_ddp:0x01032900 -mice_ddp -c${.TARGET}" \ no-ctfconvert no-implicit-rule before-depend local \ clean "ice_ddp.c" ice_ddp.fwo optional ice_ddp \ dependency "ice_ddp.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "ice_ddp.fwo" ice_ddp.fw optional ice_ddp \ dependency "$S/contrib/dev/ice/ice-1.3.41.0.pkg" \ compile-with "${CP} $S/contrib/dev/ice/ice-1.3.41.0.pkg ice_ddp.fw" \ no-obj no-implicit-rule \ clean "ice_ddp.fw" dev/iicbus/controller/twsi/mv_twsi.c optional twsi fdt dev/iicbus/controller/twsi/a10_twsi.c optional twsi fdt dev/iicbus/controller/twsi/twsi.c optional twsi fdt dev/iicbus/controller/rockchip/rk_i2c.c optional rk_i2c fdt dev/ipmi/ipmi.c optional ipmi dev/ipmi/ipmi_acpi.c optional ipmi acpi dev/ipmi/ipmi_bt.c optional ipmi dev/ipmi/ipmi_kcs.c optional ipmi dev/ipmi/ipmi_pci.c optional ipmi pci dev/ipmi/ipmi_smbios.c optional ipmi dev/ipmi/ipmi_smbus.c optional ipmi smbus dev/ipmi/ipmi_smic.c optional ipmi dev/ipmi/ipmi_ssif.c optional ipmi smbus dev/ixl/if_ixl.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/ixl_pf_main.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/ixl_pf_iflib.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/ixl_pf_qmgr.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/ixl_pf_iov.c optional ixl pci pci_iov \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/ixl_pf_i2c.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/ixl_txrx.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_osdep.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_lan_hmc.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_hmc.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_common.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_nvm.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_adminq.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_dcb.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/mailbox/arm/arm_doorbell.c optional fdt arm_doorbell dev/mbox/mbox_if.m optional soc_brcm_bcm2837 dev/mmc/host/dwmmc_altera.c optional dwmmc dwmmc_altera fdt dev/mmc/host/dwmmc_hisi.c optional dwmmc dwmmc_hisi fdt dev/mmc/host/dwmmc_rockchip.c optional dwmmc rk_dwmmc fdt dev/neta/if_mvneta_fdt.c optional neta fdt dev/neta/if_mvneta.c optional neta mdio mii fdt dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofw_pci.c optional fdt pci dev/ofw/ofw_pcib.c optional fdt pci dev/pci/controller/pci_n1sdp.c optional pci_n1sdp acpi dev/pci/pci_host_generic.c optional pci dev/pci/pci_host_generic_acpi.c optional pci acpi dev/pci/pci_host_generic_den0115.c optional pci acpi dev/pci/pci_host_generic_fdt.c optional pci fdt dev/pci/pci_dw_mv.c optional pci fdt dev/pci/pci_dw.c optional pci fdt dev/pci/pci_dw_if.m optional pci fdt dev/psci/psci.c standard dev/psci/smccc_arm64.S standard dev/psci/smccc_errata.c standard dev/psci/smccc_trng.c standard dev/psci/smccc.c standard dev/pwm/controller/allwinner/aw_pwm.c optional fdt aw_pwm dev/pwm/controller//rockchip/rk_pwm.c optional fdt rk_pwm dev/random/armv8rng.c optional armv8_rng !random_loadable dev/safexcel/safexcel.c optional safexcel fdt dev/sdhci/sdhci_xenon.c optional sdhci_xenon sdhci dev/sdhci/sdhci_xenon_acpi.c optional sdhci_xenon sdhci acpi dev/sdhci/sdhci_xenon_fdt.c optional sdhci_xenon sdhci fdt dev/sdhci/sdhci_fdt_xilinx.c optional sdhci_xilinx sdhci fdt dev/sdhci/sdhci_fdt_rockchip.c optional sdhci fdt soc_rockchip dev/sram/mmio_sram.c optional fdt mmio_sram dev/sram/mmio_sram_if.m optional fdt mmio_sram dev/spibus/controller/allwinner/aw_spi.c optional fdt aw_spi dev/spibus/controller/rockchip/rk_spi.c optional fdt rk_spi dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_mu.c optional uart uart_mu fdt dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 dev/usb/controller/ehci_mv.c optional ehci_mv fdt dev/usb/controller/generic_ehci.c optional ehci dev/usb/controller/generic_ehci_acpi.c optional ehci acpi dev/usb/controller/generic_ehci_fdt.c optional ehci fdt dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt dev/usb/controller/musb_otg_allwinner.c optional musb fdt soc_allwinner_a64 dev/usb/controller/usb_nop_xceiv.c optional fdt dev/usb/controller/generic_xhci.c optional xhci dev/usb/controller/generic_xhci_acpi.c optional xhci acpi dev/usb/controller/generic_xhci_fdt.c optional xhci fdt dev/usb/controller/dwc3/dwc3.c optional xhci acpi dwc3 | xhci fdt dwc3 dev/usb/controller/dwc3/aw_dwc3.c optional xhci fdt dwc3 aw_dwc3 dev/usb/controller/dwc3/rk_dwc3.c optional xhci fdt dwc3 rk_dwc3 dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional soc_cavm_thunderx pci vnic fdt dev/vnic/thunder_bgx.c optional soc_cavm_thunderx pci vnic pci dev/vnic/thunder_mdio_fdt.c optional soc_cavm_thunderx pci vnic fdt dev/vnic/thunder_mdio.c optional soc_cavm_thunderx pci vnic dev/vnic/lmac_if.m optional inet | inet6 | vnic ## ## SoC Support ## # Allwinner common files arm/allwinner/a10_codec.c optional sound a10_codec fdt arm/allwinner/a31_dmac.c optional a31_dmac fdt arm/allwinner/a33_codec.c optional fdt sound a33_codec arm/allwinner/a64/sun50i_a64_acodec.c optional fdt sound a64_codec arm/allwinner/sunxi_dma_if.m optional a31_dmac arm/allwinner/aw_cir.c optional evdev aw_cir fdt arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt arm/allwinner/aw_i2s.c optional fdt sound aw_i2s arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt arm/allwinner/aw_nmi.c optional aw_nmi fdt \ compile-with "${NORMAL_C} -I$S/contrib/device-tree/include" arm/allwinner/aw_r_intc.c optional aw_r_intc fdt arm/allwinner/aw_rsb.c optional aw_rsb fdt arm/allwinner/aw_rtc.c optional aw_rtc fdt arm/allwinner/aw_sid.c optional aw_sid nvmem fdt arm/allwinner/aw_syscon.c optional aw_syscon syscon fdt arm/allwinner/aw_timer.c optional aw_timer fdt arm/allwinner/aw_thermal.c optional aw_thermal nvmem fdt arm/allwinner/aw_usbphy.c optional ehci aw_usbphy fdt arm/allwinner/aw_usb3phy.c optional xhci aw_usbphy fdt arm/allwinner/aw_wdog.c optional aw_wdog fdt arm/allwinner/axp81x.c optional axp81x fdt arm/allwinner/if_awg.c optional awg syscon aw_sid nvmem fdt # Allwinner clock driver dev/clk/allwinner/aw_ccung.c optional aw_ccu fdt dev/clk/allwinner/aw_clk_frac.c optional aw_ccu fdt dev/clk/allwinner/aw_clk_m.c optional aw_ccu fdt dev/clk/allwinner/aw_clk_mipi.c optional aw_ccu fdt dev/clk/allwinner/aw_clk_nkmp.c optional aw_ccu fdt dev/clk/allwinner/aw_clk_nm.c optional aw_ccu fdt dev/clk/allwinner/aw_clk_nmm.c optional aw_ccu fdt dev/clk/allwinner/aw_clk_np.c optional aw_ccu fdt dev/clk/allwinner/aw_clk_prediv_mux.c optional aw_ccu fdt dev/clk/allwinner/ccu_a64.c optional soc_allwinner_a64 aw_ccu fdt dev/clk/allwinner/ccu_h3.c optional soc_allwinner_h5 aw_ccu fdt dev/clk/allwinner/ccu_h6.c optional soc_allwinner_h6 aw_ccu fdt dev/clk/allwinner/ccu_h6_r.c optional soc_allwinner_h6 aw_ccu fdt dev/clk/allwinner/ccu_h616.c optional soc_allwinner_h616 aw_ccu fdt dev/clk/allwinner/ccu_sun8i_r.c optional aw_ccu fdt dev/clk/allwinner/ccu_de2.c optional aw_ccu fdt # Allwinner padconf files arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/h3/h3_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h3/h3_r_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h6/h6_padconf.c optional soc_allwinner_h6 fdt arm/allwinner/h6/h6_r_padconf.c optional soc_allwinner_h6 fdt arm/allwinner/h616/h616_padconf.c optional soc_allwinner_h616 fdt arm/allwinner/h616/h616_r_padconf.c optional soc_allwinner_h616 fdt # Altera/Intel arm64/intel/stratix10-soc-fpga-mgr.c optional soc_intel_stratix10 fdt arm64/intel/stratix10-svc.c optional soc_intel_stratix10 fdt # Annapurna arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${.IMPSRC}" # Apple arm64/apple/apple_aic.c optional soc_apple_t8103 fdt arm64/apple/apple_pinctrl.c optional soc_apple_t8103 fdt arm64/apple/apple_wdog.c optional soc_apple_t8103 fdt arm64/apple/exynos_uart.c optional soc_apple_t8103 fdt # Broadcom arm64/broadcom/brcmmdio/mdio_mux_iproc.c optional soc_brcm_ns2 fdt arm64/broadcom/brcmmdio/mdio_nexus_iproc.c optional soc_brcm_ns2 fdt arm64/broadcom/brcmmdio/mdio_ns2_pcie_phy.c optional soc_brcm_ns2 fdt pci arm64/broadcom/genet/if_genet.c optional soc_brcm_bcm2838 fdt genet arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc fdt arm/broadcom/bcm2835/bcm2835_clkman.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 fdt | vt soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_firmware.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 fdt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 fdt | gpio soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_rng.c optional !random_loadable soc_brcm_bcm2837 fdt | !random_loadable soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhost.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi fdt arm/broadcom/bcm2835/bcm2835_vcbus.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 | dwcotg fdt soc_brcm_bcm2838 arm/broadcom/bcm2835/bcm2838_pci.c optional soc_brcm_bcm2838 fdt pci arm/broadcom/bcm2835/bcm2838_xhci.c optional soc_brcm_bcm2838 fdt pci xhci arm/broadcom/bcm2835/raspberrypi_gpio.c optional soc_brcm_bcm2837 gpio fdt | soc_brcm_bcm2838 gpio fdt arm/broadcom/bcm2835/raspberrypi_virtgpio.c optional soc_brcm_bcm2837 gpio fdt | soc_brcm_bcm2838 gpio fdt contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 fdt \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 fdt \ compile-with "${NORMAL_C} -Wno-unused ${NO_WDEFAULT_CONST_INIT_FIELD_UNSAFE} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" # Cavium arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci # i.MX8 Clock support arm64/freescale/imx/imx_ccm.c optional fdt soc_freescale_imx8 arm64/freescale/imx/imx8mp_ccm.c optional fdt soc_freescale_imx8 arm64/freescale/imx/imx8mq_ccm.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_gate.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_mux.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_composite.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_sscg_pll.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_frac_pll.c optional fdt soc_freescale_imx8 # iMX drivers arm/freescale/imx/imx_gpio.c optional gpio soc_freescale_imx8 fdt arm/freescale/imx/imx_i2c.c optional fdt fsliic arm/freescale/imx/imx_machdep.c optional fdt soc_freescale_imx8 arm64/freescale/imx/imx7gpc.c optional fdt soc_freescale_imx8 dev/ffec/if_ffec.c optional fdt ffec # Marvell arm/mv/a37x0_gpio.c optional a37x0_gpio gpio fdt arm/mv/a37x0_iic.c optional a37x0_iic iicbus fdt arm/mv/a37x0_spi.c optional a37x0_spi spibus fdt arm/mv/clk/a37x0_tbg.c optional a37x0_tbg clk fdt syscon arm/mv/clk/a37x0_xtal.c optional a37x0_xtal clk fdt syscon arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/mv/gpio.c optional mv_gpio fdt arm/mv/mvebu_gpio.c optional mv_gpio fdt arm/mv/mvebu_pinctrl.c optional mvebu_pinctrl fdt arm/mv/mv_ap806_clock.c optional soc_marvell_8k fdt arm/mv/mv_ap806_gicp.c optional mv_ap806_gicp fdt arm/mv/mv_ap806_sei.c optional mv_ap806_sei fdt arm/mv/mv_cp110_clock.c optional soc_marvell_8k fdt arm/mv/mv_cp110_icu.c optional mv_cp110_icu fdt arm/mv/mv_cp110_icu_bus.c optional mv_cp110_icu fdt arm/mv/mv_thermal.c optional soc_marvell_8k mv_thermal fdt arm/mv/clk/a37x0_tbg_pll.c optional a37x0_tbg clk fdt syscon arm/mv/clk/a37x0_periph_clk_driver.c optional a37x0_nb_periph a37x0_sb_periph clk fdt syscon arm/mv/clk/a37x0_nb_periph_clk_driver.c optional a37x0_nb_periph clk fdt syscon arm/mv/clk/a37x0_sb_periph_clk_driver.c optional a37x0_sb_periph clk fdt syscon arm/mv/clk/periph.c optional a37x0_nb_periph a37x0_sb_periph clk fdt syscon arm/mv/clk/periph_clk_d.c optional a37x0_nb_periph a37x0_sb_periph clk fdt syscon arm/mv/clk/periph_clk_fixed.c optional a37x0_nb_periph a37x0_sb_periph clk fdt syscon arm/mv/clk/periph_clk_gate.c optional a37x0_nb_periph a37x0_sb_periph clk fdt syscon arm/mv/clk/periph_clk_mux_gate.c optional a37x0_nb_periph a37x0_sb_periph clk fdt syscon # NVidia arm/nvidia/tegra_abpmisc.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_ahci.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_efuse.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_ehci.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_gpio.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_i2c.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_lic.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_mc.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_pcie.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_sdhci.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_soctherm_if.m optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_soctherm.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_uart.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_usbphy.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_xhci.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/max77620.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/max77620_gpio.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/max77620_regulators.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/max77620_rtc.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_car.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_clk_per.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_clk_pll.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_clk_super.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_coretemp.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_cpufreq.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_pinmux.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_pmc.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_xusbpadctl.c optional fdt soc_nvidia_tegra210 # Nvidia firmware for Tegra tegra210_xusb_fw.c optional tegra210_xusb_fw \ dependency "$S/conf/files.arm64" \ compile-with "${AWK} -f $S/tools/fw_stub.awk tegra210_xusb.fw:tegra210_xusb_fw -mtegra210_xusb_fw -c${.TARGET}" \ no-ctfconvert no-implicit-rule before-depend local \ clean "tegra210_xusb_fw.c" tegra210_xusb.fwo optional tegra210_xusb_fw \ dependency "tegra210_xusb.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "tegra210_xusb.fwo" tegra210_xusb.fw optional tegra210_xusb_fw \ dependency "$S/contrib/dev/nvidia/tegra210_xusb.bin.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "tegra210_xusb.fw" # NXP dev/iicbus/controller/vybrid/vf_i2c.c optional vf_i2c iicbus soc_nxp_ls dev/iicbus/controller/vybrid/vf_i2c_acpi.c optional vf_i2c iicbus acpi soc_nxp_ls dev/iicbus/controller/vybrid/vf_i2c_fdt.c optional vf_i2c iicbus fdt soc_nxp_ls arm64/qoriq/qoriq_dw_pci.c optional pci fdt soc_nxp_ls arm64/qoriq/qoriq_gpio_pic.c optional gpio fdt soc_nxp_ls arm64/qoriq/qoriq_therm.c optional pci fdt soc_nxp_ls arm64/qoriq/qoriq_therm_if.m optional pci fdt soc_nxp_ls arm64/qoriq/clk/ls1028a_clkgen.c optional clk soc_nxp_ls fdt arm64/qoriq/clk/ls1028a_flexspi_clk.c optional clk soc_nxp_ls fdt arm64/qoriq/clk/ls1046a_clkgen.c optional clk soc_nxp_ls fdt arm64/qoriq/clk/ls1088a_clkgen.c optional clk soc_nxp_ls fdt arm64/qoriq/clk/lx2160a_clkgen.c optional clk soc_nxp_ls fdt arm64/qoriq/clk/qoriq_clk_pll.c optional clk soc_nxp_ls arm64/qoriq/clk/qoriq_clkgen.c optional clk soc_nxp_ls fdt dev/ahci/ahci_fsl_fdt.c optional soc_nxp_ls ahci fdt dev/flash/flexspi/flex_spi.c optional clk flex_spi soc_nxp_ls fdt # Qualcomm -arm64/qualcomm/qcom_gcc.c optional qcom_gcc fdt +dev/qcom_gcc/qcom_gcc_main.c optional qcom_gcc +dev/qcom_gcc/qcom_gcc_clock.c optional qcom_gcc +dev/qcom_gcc/qcom_gcc_reset.c optional qcom_gcc +dev/qcom_gcc/qcom_gcc_ipq4018_reset.c optional qcom_gcc +dev/qcom_gcc/qcom_gcc_ipq4018_clock.c optional qcom_gcc +dev/qcom_gcc/qcom_gcc_msm8916_reset.c optional qcom_gcc +dev/qcom_gcc/qcom_gcc_msm8916_clock.c optional qcom_gcc +dev/qcom_clk/qcom_clk_fepll.c optional qcom_gcc +dev/qcom_clk/qcom_clk_fdiv.c optional qcom_gcc +dev/qcom_clk/qcom_clk_apssdiv.c optional qcom_gcc +dev/qcom_clk/qcom_clk_freqtbl.c optional qcom_gcc +dev/qcom_clk/qcom_clk_rcg2.c optional qcom_gcc +dev/qcom_clk/qcom_clk_branch2.c optional qcom_gcc +dev/qcom_clk/qcom_clk_ro_div.c optional qcom_gcc dev/qcom_mdio/qcom_mdio_ipq4018.c optional qcom_mdio fdt mdio mii # RockChip Drivers arm64/rockchip/rk3328_codec.c optional fdt rk3328codec soc_rockchip_rk3328 arm64/rockchip/rk3399_emmcphy.c optional fdt rk_emmcphy soc_rockchip_rk3399 arm64/rockchip/rk3568_combphy.c optional fdt rk_combphy soc_rockchip_rk3568 arm64/rockchip/rk3568_pcie.c optional fdt pci soc_rockchip_rk3568 arm64/rockchip/rk3568_pciephy.c optional fdt pci soc_rockchip_rk3568 arm64/rockchip/rk_i2s.c optional fdt sound soc_rockchip_rk3328 | fdt sound soc_rockchip_rk3399 arm64/rockchip/rk_otp.c optional fdt soc_rockchip_rk3568 arm64/rockchip/rk_otp_if.m optional fdt soc_rockchip_rk3568 dev/iicbus/pmic/rockchip/rk8xx.c optional fdt rk8xx soc_rockchip dev/iicbus/pmic/rockchip/rk8xx_clocks.c optional fdt rk8xx soc_rockchip dev/iicbus/pmic/rockchip/rk8xx_regulators.c optional fdt rk8xx soc_rockchip dev/iicbus/pmic/rockchip/rk8xx_rtc.c optional fdt rk8xx soc_rockchip dev/iicbus/pmic/rockchip/rk805.c optional fdt rk805 soc_rockchip_rk3328 dev/iicbus/pmic/rockchip/rk808.c optional fdt rk808 soc_rockchip_rk3399 dev/iicbus/pmic/rockchip/rk817.c optional fdt rk817 soc_rockchip_rk3568 arm64/rockchip/rk_grf.c optional fdt soc_rockchip arm64/rockchip/rk_grf_gpio.c optional fdt soc_rockchip arm64/rockchip/rk_pinctrl.c optional fdt rk_pinctrl soc_rockchip arm64/rockchip/rk_gpio.c optional fdt rk_gpio soc_rockchip arm64/rockchip/rk_iodomain.c optional fdt rk_iodomain arm64/rockchip/rk_usb2phy.c optional fdt rk_usb2phy soc_rockchip arm64/rockchip/rk_typec_phy.c optional fdt rk_typec_phy soc_rockchip_rk3399 arm64/rockchip/rk_tsadc_if.m optional fdt soc_rockchip_rk3399 | fdt soc_rockchip_rk3568 arm64/rockchip/rk_tsadc.c optional fdt soc_rockchip_rk3399 | fdt soc_rockchip_rk3568 arm64/rockchip/rk_pcie.c optional fdt pci soc_rockchip_rk3399 arm64/rockchip/rk_pcie_phy.c optional fdt pci soc_rockchip_rk3399 # RockChip Clock support dev/clk/rockchip/rk_cru.c optional fdt soc_rockchip dev/clk/rockchip/rk_clk_armclk.c optional fdt soc_rockchip dev/clk/rockchip/rk_clk_composite.c optional fdt soc_rockchip dev/clk/rockchip/rk_clk_fract.c optional fdt soc_rockchip dev/clk/rockchip/rk_clk_gate.c optional fdt soc_rockchip dev/clk/rockchip/rk_clk_mux.c optional fdt soc_rockchip dev/clk/rockchip/rk_clk_pll.c optional fdt soc_rockchip dev/clk/rockchip/rk3328_cru.c optional fdt soc_rockchip_rk3328 dev/clk/rockchip/rk3399_cru.c optional fdt soc_rockchip_rk3399 dev/clk/rockchip/rk3399_pmucru.c optional fdt soc_rockchip_rk3399 dev/clk/rockchip/rk3568_cru.c optional fdt soc_rockchip_rk3568 dev/clk/rockchip/rk3568_pmucru.c optional fdt soc_rockchip_rk3568 # Xilinx arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq fdt arm/xilinx/zy7_gpio.c optional gpio soc_xilinx_zynq fdt dev/iicbus/controller/cadence/cdnc_i2c.c optional cdnc_i2c iicbus soc_xilinx_zynq fdt dev/usb/controller/xlnx_dwc3.c optional xhci soc_xilinx_zynq fdt dev/firmware/xilinx/zynqmp_firmware.c optional fdt soc_xilinx_zynq dev/firmware/xilinx/zynqmp_firmware_if.m optional fdt soc_xilinx_zynq dev/clk/xilinx/zynqmp_clock.c optional fdt soc_xilinx_zynq dev/clk/xilinx/zynqmp_clk_div.c optional fdt soc_xilinx_zynq dev/clk/xilinx/zynqmp_clk_fixed.c optional fdt soc_xilinx_zynq dev/clk/xilinx/zynqmp_clk_gate.c optional fdt soc_xilinx_zynq dev/clk/xilinx/zynqmp_clk_mux.c optional fdt soc_xilinx_zynq dev/clk/xilinx/zynqmp_clk_pll.c optional fdt soc_xilinx_zynq dev/clk/xilinx/zynqmp_reset.c optional fdt soc_xilinx_zynq diff --git a/sys/dev/qcom_clk/qcom_clk_rcg2.c b/sys/dev/qcom_clk/qcom_clk_rcg2.c index 0407706dd138..6a1962982184 100644 --- a/sys/dev/qcom_clk/qcom_clk_rcg2.c +++ b/sys/dev/qcom_clk/qcom_clk_rcg2.c @@ -1,659 +1,659 @@ /*- * Copyright (c) 2021 Adrian Chadd . * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include "qcom_clk_freqtbl.h" #include "qcom_clk_rcg2.h" #include "qcom_clk_rcg2_reg.h" #include "clkdev_if.h" #if 0 #define DPRINTF(dev, msg...) device_printf(dev, msg); #else #define DPRINTF(dev, msg...) #endif #define QCOM_CLK_RCG2_CFG_OFFSET(sc) \ ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_CFG_REG) #define QCOM_CLK_RCG2_CMD_REGISTER(sc) \ ((sc)->cmd_rcgr + QCOM_CLK_RCG2_CMD_REG) #define QCOM_CLK_RCG2_M_OFFSET(sc) \ ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_M_REG) #define QCOM_CLK_RCG2_N_OFFSET(sc) \ ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_N_REG) #define QCOM_CLK_RCG2_D_OFFSET(sc) \ ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_D_REG) struct qcom_clk_rcg2_sc { struct clknode *clknode; uint32_t cmd_rcgr; uint32_t hid_width; uint32_t mnd_width; int32_t safe_src_idx; uint32_t cfg_offset; int safe_pre_parent_idx; uint32_t flags; const struct qcom_clk_freq_tbl *freq_tbl; }; /* * Finish a clock update. * * This instructs the configuration to take effect. */ static bool qcom_clk_rcg2_update_config_locked(struct qcom_clk_rcg2_sc *sc) { uint32_t reg, count; /* * Send "update" to the controller. */ CLKDEV_READ_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_CMD_REGISTER(sc), ®); reg |= QCOM_CLK_RCG2_CMD_UPDATE; CLKDEV_WRITE_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_CMD_REGISTER(sc), reg); wmb(); /* * Poll for completion of update. */ for (count = 0; count < 1000; count++) { CLKDEV_READ_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_CMD_REGISTER(sc), ®); if ((reg & QCOM_CLK_RCG2_CMD_UPDATE) == 0) { return (true); } DELAY(10); rmb(); } CLKDEV_READ_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_CMD_REGISTER(sc), ®); DPRINTF(clknode_get_device(sc->clknode), "%s: failed; reg=0x%08x\n", __func__, reg); return (false); } /* * Calculate the output frequency given an input frequency and the m/n:d * configuration. */ static uint64_t qcom_clk_rcg2_calc_rate(uint64_t rate, uint32_t mode, uint32_t m, uint32_t n, uint32_t hid_div) { if (hid_div != 0) { rate = rate * 2; rate = rate / (hid_div + 1); } /* Note: assume n is not 0 here; bad things happen if it is */ if (mode != 0) { rate = (rate * m) / n; } return (rate); } /* * The inverse of calc_rate() - calculate the required input frequency * given the desired output freqency and m/n:d configuration. */ static uint64_t qcom_clk_rcg2_calc_input_freq(uint64_t freq, uint32_t m, uint32_t n, uint32_t hid_div) { if (hid_div != 0) { freq = freq / 2; freq = freq * (hid_div + 1); } if (n != 0) { freq = (freq * n) / m; } return (freq); } static int qcom_clk_rcg2_recalc(struct clknode *clk, uint64_t *freq) { struct qcom_clk_rcg2_sc *sc; uint32_t cfg, m = 0, n = 0, hid_div = 0; uint32_t mode = 0, mask; sc = clknode_get_softc(clk); /* Read the MODE, CFG, M and N parameters */ CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode)); CLKDEV_READ_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_CFG_OFFSET(sc), &cfg); if (sc->mnd_width != 0) { mask = (1U << sc->mnd_width) - 1; CLKDEV_READ_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_M_OFFSET(sc), &m); CLKDEV_READ_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_N_OFFSET(sc), &n); m = m & mask; n = ~ n; n = n & mask; n = n + m; mode = (cfg & QCOM_CLK_RCG2_CFG_MODE_MASK) >> QCOM_CLK_RCG2_CFG_MODE_SHIFT; } CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); /* Fetch the divisor */ mask = (1U << sc->hid_width) - 1; hid_div = (cfg >> QCOM_CLK_RCG2_CFG_SRC_DIV_SHIFT) & mask; /* Calculate the rate based on the parent rate and config */ *freq = qcom_clk_rcg2_calc_rate(*freq, mode, m, n, hid_div); return (0); } /* * configure the mn:d divisor, pre-divisor, and parent. */ static void qcom_clk_rcg2_set_config_locked(struct qcom_clk_rcg2_sc *sc, const struct qcom_clk_freq_tbl *f, int parent_idx) { uint32_t mask, reg; /* If we have MN:D, then update it */ if (sc->mnd_width != 0 && f->n != 0) { mask = (1U << sc->mnd_width) - 1; CLKDEV_READ_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_M_OFFSET(sc), ®); reg &= ~mask; reg |= (f->m & mask); CLKDEV_WRITE_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_M_OFFSET(sc), reg); CLKDEV_READ_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_N_OFFSET(sc), ®); reg &= ~mask; reg |= ((~(f->n - f->m)) & mask); CLKDEV_WRITE_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_N_OFFSET(sc), reg); CLKDEV_READ_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_D_OFFSET(sc), ®); reg &= ~mask; reg |= ((~f->n) & mask); CLKDEV_WRITE_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_D_OFFSET(sc), reg); } mask = (1U << sc->hid_width) - 1; /* * Mask out register fields we're going to modify along with * the pre-divisor. */ mask |= QCOM_CLK_RCG2_CFG_SRC_SEL_MASK | QCOM_CLK_RCG2_CFG_MODE_MASK | QCOM_CLK_RCG2_CFG_HW_CLK_CTRL_MASK; CLKDEV_READ_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_CFG_OFFSET(sc), ®); reg &= ~mask; /* Configure pre-divisor */ reg = reg | ((f->pre_div) << QCOM_CLK_RCG2_CFG_SRC_DIV_SHIFT); /* Configure parent clock */ reg = reg | (((parent_idx << QCOM_CLK_RCG2_CFG_SRC_SEL_SHIFT) & QCOM_CLK_RCG2_CFG_SRC_SEL_MASK)); /* Configure dual-edge if needed */ if (sc->mnd_width != 0 && f->n != 0 && (f->m != f->n)) reg |= QCOM_CLK_RCG2_CFG_MODE_DUAL_EDGE; CLKDEV_WRITE_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_CFG_OFFSET(sc), reg); } static int qcom_clk_rcg2_init(struct clknode *clk, device_t dev) { struct qcom_clk_rcg2_sc *sc; uint32_t reg; uint32_t idx; bool enabled __unused; sc = clknode_get_softc(clk); /* * Read the mux setting to set the right parent. * Whilst here, read the config to get whether we're enabled * or not. */ CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode)); /* check if rcg2 root clock is enabled */ CLKDEV_READ_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_CMD_REGISTER(sc), ®); if (reg & QCOM_CLK_RCG2_CMD_ROOT_OFF) enabled = false; else enabled = true; /* mux settings */ CLKDEV_READ_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_CFG_OFFSET(sc), ®); CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); idx = (reg & QCOM_CLK_RCG2_CFG_SRC_SEL_MASK) >> QCOM_CLK_RCG2_CFG_SRC_SEL_SHIFT; DPRINTF(clknode_get_device(sc->clknode), "%s: mux index %u, enabled=%d\n", __func__, idx, enabled); clknode_init_parent_idx(clk, idx); /* * If we could be sure our parent clocks existed here in the tree, * we could calculate our current frequency by fetching the parent * frequency and then do our divider math. Unfortunately that * currently isn't the case. */ return(0); } static int qcom_clk_rcg2_set_gate(struct clknode *clk, bool enable) { /* * For now this isn't supported; there's some support for * "shared" rcg2 nodes in the Qualcomm/upstream Linux trees but * it's not currently needed for the supported platforms. */ return (0); } /* * Program the parent index. * * This doesn't do the update. It also must be called with the device * lock held. */ static void qcom_clk_rcg2_set_parent_index_locked(struct qcom_clk_rcg2_sc *sc, uint32_t index) { uint32_t reg; CLKDEV_READ_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_CFG_OFFSET(sc), ®); reg = reg & ~QCOM_CLK_RCG2_CFG_SRC_SEL_MASK; reg = reg | (((index << QCOM_CLK_RCG2_CFG_SRC_SEL_SHIFT) & QCOM_CLK_RCG2_CFG_SRC_SEL_MASK)); CLKDEV_WRITE_4(clknode_get_device(sc->clknode), QCOM_CLK_RCG2_CFG_OFFSET(sc), reg); } /* * Set frequency * * fin - the parent frequency, if exists * fout - starts as the requested frequency, ends with the configured * or dry-run frequency * Flags - CLK_SET_DRYRUN, CLK_SET_ROUND_UP, CLK_SET_ROUND_DOWN * retval - 0, ERANGE */ static int qcom_clk_rcg2_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, int flags, int *stop) { struct qcom_clk_rcg2_sc *sc; const struct qcom_clk_freq_tbl *f; const char **parent_names; uint64_t p_freq, p_clk_freq; int parent_cnt; struct clknode *p_clk; int i; sc = clknode_get_softc(clk); /* * Find a suitable frequency in the frequency table. * * TODO: should pay attention to ROUND_UP / ROUND_DOWN and add * a freqtbl method to handle both accordingly. */ f = qcom_clk_freq_tbl_lookup(sc->freq_tbl, *fout); if (f == NULL) { device_printf(clknode_get_device(sc->clknode), "%s: no suitable freqtbl entry found for freq %llu\n", __func__, - *fout); + (unsigned long long) *fout); return (ERANGE); } /* * Find the parent index for the given parent clock. * Abort if we can't actually find it. * * XXX TODO: this should be a clk API call! */ parent_cnt = clknode_get_parents_num(clk); parent_names = clknode_get_parent_names(clk); for (i = 0; i < parent_cnt; i++) { if (parent_names[i] == NULL) continue; if (strcmp(parent_names[i], f->parent) == 0) break; } if (i >= parent_cnt) { device_printf(clknode_get_device(sc->clknode), "%s: couldn't find suitable parent?\n", __func__); return (ENXIO); } /* * If we aren't setting the parent clock, then we need * to just program the new parent clock in and update. * (or for DRYRUN just skip that and return the new * frequency.) */ if ((sc->flags & QCOM_CLK_RCG2_FLAGS_SET_RATE_PARENT) == 0) { if (flags & CLK_SET_DRYRUN) { *fout = f->freq; return (0); } if (sc->safe_pre_parent_idx > -1) { DPRINTF(clknode_get_device(sc->clknode), "%s: setting to safe parent idx %d\n", __func__, sc->safe_pre_parent_idx); CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode)); qcom_clk_rcg2_set_parent_index_locked(sc, sc->safe_pre_parent_idx); DPRINTF(clknode_get_device(sc->clknode), "%s: safe parent: updating config\n", __func__); if (! qcom_clk_rcg2_update_config_locked(sc)) { CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); DPRINTF(clknode_get_device(sc->clknode), "%s: error updating config\n", __func__); return (ENXIO); } CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); DPRINTF(clknode_get_device(sc->clknode), "%s: safe parent: done\n", __func__); clknode_set_parent_by_idx(sc->clknode, sc->safe_pre_parent_idx); } /* Program parent index, then schedule update */ CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode)); qcom_clk_rcg2_set_parent_index_locked(sc, i); if (! qcom_clk_rcg2_update_config_locked(sc)) { CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); device_printf(clknode_get_device(sc->clknode), "%s: couldn't program in parent idx %u!\n", __func__, i); return (ENXIO); } CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); clknode_set_parent_by_idx(sc->clknode, i); *fout = f->freq; return (0); } /* * If we /are/ setting the parent clock, then we need * to determine what frequency we need the parent to * be, and then reconfigure the parent to the new * frequency, and then change our parent. * * (Again, if we're doing DRYRUN, just skip that * and return the new frequency.) */ p_clk = clknode_find_by_name(f->parent); if (p_clk == NULL) { device_printf(clknode_get_device(sc->clknode), "%s: couldn't find parent clk (%s)\n", __func__, f->parent); return (ENXIO); } /* * Calculate required frequency from said parent clock to * meet the needs of our target clock. */ p_freq = qcom_clk_rcg2_calc_input_freq(f->freq, f->m, f->n, f->pre_div); DPRINTF(clknode_get_device(sc->clknode), "%s: request %llu, parent %s freq %llu, parent freq %llu\n", __func__, *fout, f->parent, f->freq, - p_freq); + (unsigned long long) p_freq); /* * To ensure glitch-free operation on some clocks, set it to * a safe parent before programming our divisor and the parent * clock configuration. Then once it's done, flip the parent * to the new parent. * * If we're doing a dry-run then we don't need to re-parent the * clock just yet! */ if (((flags & CLK_SET_DRYRUN) == 0) && (sc->safe_pre_parent_idx > -1)) { DPRINTF(clknode_get_device(sc->clknode), "%s: setting to safe parent idx %d\n", __func__, sc->safe_pre_parent_idx); CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode)); qcom_clk_rcg2_set_parent_index_locked(sc, sc->safe_pre_parent_idx); DPRINTF(clknode_get_device(sc->clknode), "%s: safe parent: updating config\n", __func__); if (! qcom_clk_rcg2_update_config_locked(sc)) { CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); DPRINTF(clknode_get_device(sc->clknode), "%s: error updating config\n", __func__); return (ENXIO); } CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); DPRINTF(clknode_get_device(sc->clknode), "%s: safe parent: done\n", __func__); clknode_set_parent_by_idx(sc->clknode, sc->safe_pre_parent_idx); } /* * Set the parent frequency before we change our mux and divisor * configuration. */ if (clknode_get_freq(p_clk, &p_clk_freq) != 0) { device_printf(clknode_get_device(sc->clknode), "%s: couldn't get freq for parent clock %s\n", __func__, f->parent); return (ENXIO); } if (p_clk_freq != p_freq) { uint64_t n_freq; int rv; /* * If we're doing a dryrun then call test_freq() not set_freq(). * That way we get the frequency back that we would be set to. * * If we're not doing a dry run then set the frequency, then * call get_freq to get what it was set to. */ if (flags & CLK_SET_DRYRUN) { n_freq = p_freq; rv = clknode_test_freq(p_clk, n_freq, flags, 0, &p_freq); } else { rv = clknode_set_freq(p_clk, p_freq, flags, 0); } if (rv != 0) { device_printf(clknode_get_device(sc->clknode), "%s: couldn't set parent clock %s frequency to " "%llu\n", __func__, f->parent, - p_freq); + (unsigned long long) p_freq); return (ENXIO); } /* Frequency was set, fetch what it was set to */ if ((flags & CLK_SET_DRYRUN) == 0) { rv = clknode_get_freq(p_clk, &p_freq); if (rv != 0) { device_printf(clknode_get_device(sc->clknode), "%s: couldn't get parent frequency", __func__); return (ENXIO); } } } DPRINTF(clknode_get_device(sc->clknode), "%s: requested freq=%llu, target freq=%llu," " parent choice=%s, parent_freq=%llu\n", __func__, *fout, f->freq, f->parent, - p_freq); + (unsigned long long) p_freq); /* * Set the parent node, the parent programming and the divisor * config. Because they're done together, we don't go via * a mux method on this node. */ /* * Program the divisor and parent. */ if ((flags & CLK_SET_DRYRUN) == 0) { CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode)); qcom_clk_rcg2_set_config_locked(sc, f, i); if (! qcom_clk_rcg2_update_config_locked(sc)) { CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); device_printf(clknode_get_device(sc->clknode), "%s: couldn't program in divisor, help!\n", __func__); return (ENXIO); } CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); clknode_set_parent_by_idx(sc->clknode, i); } /* * p_freq is now the frequency that the parent /is/ set to. * (Or would be set to for a dry run.) * * Calculate what the eventual frequency would be, we'll want * this to return when we're done - and again, if it's a dryrun, * don't set anything up. This doesn't rely on the register * contents. */ *fout = qcom_clk_rcg2_calc_rate(p_freq, (f->n == 0 ? 0 : 1), f->m, f->n, f->pre_div); return (0); } static clknode_method_t qcom_clk_rcg2_methods[] = { /* Device interface */ CLKNODEMETHOD(clknode_init, qcom_clk_rcg2_init), CLKNODEMETHOD(clknode_recalc_freq, qcom_clk_rcg2_recalc), CLKNODEMETHOD(clknode_set_gate, qcom_clk_rcg2_set_gate), CLKNODEMETHOD(clknode_set_freq, qcom_clk_rcg2_set_freq), CLKNODEMETHOD_END }; DEFINE_CLASS_1(qcom_clk_fepll, qcom_clk_rcg2_class, qcom_clk_rcg2_methods, sizeof(struct qcom_clk_rcg2_sc), clknode_class); int qcom_clk_rcg2_register(struct clkdom *clkdom, struct qcom_clk_rcg2_def *clkdef) { struct clknode *clk; struct qcom_clk_rcg2_sc *sc; /* * Right now the rcg2 code isn't supporting turning off the clock * or limiting it to the lowest parent clock. But, do set the * flags appropriately. */ if (clkdef->flags & QCOM_CLK_RCG2_FLAGS_CRITICAL) clkdef->clkdef.flags |= CLK_NODE_CANNOT_STOP; clk = clknode_create(clkdom, &qcom_clk_rcg2_class, &clkdef->clkdef); if (clk == NULL) return (1); sc = clknode_get_softc(clk); sc->clknode = clk; sc->cmd_rcgr = clkdef->cmd_rcgr; sc->hid_width = clkdef->hid_width; sc->mnd_width = clkdef->mnd_width; sc->safe_src_idx = clkdef->safe_src_idx; sc->safe_pre_parent_idx = clkdef->safe_pre_parent_idx; sc->cfg_offset = clkdef->cfg_offset; sc->flags = clkdef->flags; sc->freq_tbl = clkdef->freq_tbl; clknode_register(clkdom, clk); return (0); } diff --git a/sys/dev/qcom_gcc/qcom_gcc_clock.c b/sys/dev/qcom_gcc/qcom_gcc_clock.c index c8c10b0c5172..f51b4021a821 100644 --- a/sys/dev/qcom_gcc/qcom_gcc_clock.c +++ b/sys/dev/qcom_gcc/qcom_gcc_clock.c @@ -1,98 +1,99 @@ /*- * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (c) 2025, Adrian Chadd + * Copyright (c) 2026 Adrian Chadd * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include +#include #include #include #include #include "qcom_gcc_var.h" int qcom_gcc_clock_read(device_t dev, bus_addr_t addr, uint32_t *val) { struct qcom_gcc_softc *sc; sc = device_get_softc(dev); *val = bus_read_4(sc->reg, addr); return (0); } int qcom_gcc_clock_write(device_t dev, bus_addr_t addr, uint32_t val) { struct qcom_gcc_softc *sc; sc = device_get_softc(dev); bus_write_4(sc->reg, addr, val); return (0); } int qcom_gcc_clock_modify(device_t dev, bus_addr_t addr, uint32_t clear_mask, uint32_t set_mask) { struct qcom_gcc_softc *sc; uint32_t reg; sc = device_get_softc(dev); reg = bus_read_4(sc->reg, addr); reg &= clear_mask; reg |= set_mask; bus_write_4(sc->reg, addr, reg); return (0); } void qcom_gcc_clock_lock(device_t dev) { struct qcom_gcc_softc *sc; sc = device_get_softc(dev); mtx_lock(&sc->mtx); } void qcom_gcc_clock_unlock(device_t dev) { struct qcom_gcc_softc *sc; sc = device_get_softc(dev); mtx_unlock(&sc->mtx); } diff --git a/sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c b/sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c index f99d1d9ad9f1..127ca944c77e 100644 --- a/sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c +++ b/sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c @@ -1,183 +1,186 @@ /*- * SPDX-License-Identifier: BSD-2-Clause * * Copyright (c) 2021, Adrian Chadd * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Driver for Qualcomm IPQ4018 clock and reset device */ #include #include #include #include #include #include #include #include #include #include +#include #include #include #include #include #include #include "hwreset_if.h" #include #include "qcom_gcc_var.h" #include "qcom_gcc_ipq4018.h" static const struct qcom_gcc_reset_entry gcc_ipq4019_reset_list[] = { [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 }, [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 }, [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 }, [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 }, [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 }, [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 }, [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 }, [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 }, [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 }, [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 }, [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 }, [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 }, [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 }, [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 }, [USB3_HSPHY_S_ARES] = { 0x1e038, 2 }, [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 }, [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 }, [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 }, [PCIE_AHB_ARES] = { 0x1d010, 10 }, [PCIE_PWR_ARES] = { 0x1d010, 9 }, [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 }, [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 }, [PCIE_PHY_ARES] = { 0x1d010, 6 }, [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 }, [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 }, [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 }, [PCIE_PIPE_ARES] = { 0x1d010, 2 }, [PCIE_AXI_S_ARES] = { 0x1d010, 1 }, [PCIE_AXI_M_ARES] = { 0x1d010, 0 }, [ESS_RESET] = { 0x12008, 0}, [GCC_BLSP1_BCR] = {0x01000, 0}, [GCC_BLSP1_QUP1_BCR] = {0x02000, 0}, [GCC_BLSP1_UART1_BCR] = {0x02038, 0}, [GCC_BLSP1_QUP2_BCR] = {0x03008, 0}, [GCC_BLSP1_UART2_BCR] = {0x03028, 0}, [GCC_BIMC_BCR] = {0x04000, 0}, [GCC_TLMM_BCR] = {0x05000, 0}, [GCC_IMEM_BCR] = {0x0E000, 0}, [GCC_ESS_BCR] = {0x12008, 0}, [GCC_PRNG_BCR] = {0x13000, 0}, [GCC_BOOT_ROM_BCR] = {0x13008, 0}, [GCC_CRYPTO_BCR] = {0x16000, 0}, [GCC_SDCC1_BCR] = {0x18000, 0}, [GCC_SEC_CTRL_BCR] = {0x1A000, 0}, [GCC_AUDIO_BCR] = {0x1B008, 0}, [GCC_QPIC_BCR] = {0x1C000, 0}, [GCC_PCIE_BCR] = {0x1D000, 0}, [GCC_USB2_BCR] = {0x1E008, 0}, [GCC_USB2_PHY_BCR] = {0x1E018, 0}, [GCC_USB3_BCR] = {0x1E024, 0}, [GCC_USB3_PHY_BCR] = {0x1E034, 0}, [GCC_SYSTEM_NOC_BCR] = {0x21000, 0}, [GCC_PCNOC_BCR] = {0x2102C, 0}, [GCC_DCD_BCR] = {0x21038, 0}, [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0}, [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0}, [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0}, [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0}, [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0}, [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0}, [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0}, [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0}, [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0}, [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0}, [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0}, [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0}, [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0}, [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0}, [GCC_TCSR_BCR] = {0x22000, 0}, [GCC_MPM_BCR] = {0x24000, 0}, [GCC_SPDM_BCR] = {0x25000, 0}, }; static int qcom_gcc_ipq4018_hwreset_assert(device_t dev, intptr_t id, bool reset) { struct qcom_gcc_softc *sc; uint32_t reg; sc = device_get_softc(dev); if (id > nitems(gcc_ipq4019_reset_list)) { - device_printf(dev, "%s: invalid id (%d)\n", __func__, id); + device_printf(dev, "%s: invalid id (%d)\n", __func__, + (uint32_t) id); return (EINVAL); } mtx_lock(&sc->mtx); reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg); if (reset) reg |= (1U << gcc_ipq4019_reset_list[id].bit); else reg &= ~(1U << gcc_ipq4019_reset_list[id].bit); bus_write_4(sc->reg, gcc_ipq4019_reset_list[id].reg, reg); mtx_unlock(&sc->mtx); return (0); } static int qcom_gcc_ipq4018_hwreset_is_asserted(device_t dev, intptr_t id, bool *reset) { struct qcom_gcc_softc *sc; uint32_t reg; sc = device_get_softc(dev); if (id > nitems(gcc_ipq4019_reset_list)) { - device_printf(dev, "%s: invalid id (%d)\n", __func__, id); + device_printf(dev, "%s: invalid id (%d)\n", __func__, + (uint32_t) id); return (EINVAL); } mtx_lock(&sc->mtx); reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg); if (reg & ((1U << gcc_ipq4019_reset_list[id].bit))) *reset = true; else *reset = false; mtx_unlock(&sc->mtx); - device_printf(dev, "called; id=%d\n", id); + device_printf(dev, "called; id=%d\n", (uint32_t) id); return (0); } void qcom_gcc_ipq4018_hwreset_init(struct qcom_gcc_softc *sc) { sc->sc_cb.hw_reset_assert = qcom_gcc_ipq4018_hwreset_assert; sc->sc_cb.hw_reset_is_asserted = qcom_gcc_ipq4018_hwreset_is_asserted; } diff --git a/sys/dev/qcom_gcc/qcom_gcc_main.c b/sys/dev/qcom_gcc/qcom_gcc_main.c index 3950bd985feb..38f409827541 100644 --- a/sys/dev/qcom_gcc/qcom_gcc_main.c +++ b/sys/dev/qcom_gcc/qcom_gcc_main.c @@ -1,222 +1,238 @@ /*- * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (c) 2025, Adrian Chadd + * Copyright (c) 2026 Adrian Chadd * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Driver for Qualcomm clock/reset trees */ #include #include #include #include #include #include #include #include #include #include #include +#include #include #include #include #include #include "clkdev_if.h" #include "hwreset_if.h" #include "qcom_gcc_var.h" #include "qcom_gcc_ipq4018.h" +#include "qcom_gcc_msm8916.h" static int qcom_gcc_modevent(module_t, int, void *); static int qcom_gcc_probe(device_t); static int qcom_gcc_attach(device_t); static int qcom_gcc_detach(device_t); struct qcom_gcc_chipset_list_entry { const char *ofw; const char *desc; qcom_gcc_chipset_t chipset; }; static struct qcom_gcc_chipset_list_entry qcom_gcc_chipset_list[] = { { "qcom,gcc-ipq4019", "Qualcomm IPQ4018 Clock/Reset Controller", QCOM_GCC_CHIPSET_IPQ4018 }, + { "qcom,gcc-msm8916", "Qualcomm MSM8916 Clock/Reset Controller", + QCOM_GCC_CHIPSET_MSM8916 }, { NULL, NULL, 0 }, }; static int qcom_gcc_modevent(module_t mod, int type, void *unused) { int error; switch (type) { case MOD_LOAD: case MOD_QUIESCE: case MOD_UNLOAD: case MOD_SHUTDOWN: error = 0; break; default: error = EOPNOTSUPP; break; } return (error); } static int qcom_gcc_probe(device_t dev) { struct qcom_gcc_softc *sc; int i; sc = device_get_softc(dev); if (! ofw_bus_status_okay(dev)) return (ENXIO); for (i = 0; qcom_gcc_chipset_list[i].ofw != NULL; i++) { const struct qcom_gcc_chipset_list_entry *ce; ce = &qcom_gcc_chipset_list[i]; if (ofw_bus_is_compatible(dev, ce->ofw) == 0) continue; device_set_desc(dev, ce->desc); sc->sc_chipset = ce->chipset; return (0); } return (ENXIO); } static int qcom_gcc_attach(device_t dev) { struct qcom_gcc_softc *sc; size_t mem_sz; sc = device_get_softc(dev); /* Found a compatible device! */ sc->dev = dev; /* * Setup the hardware callbacks, before any further initialisation * is performed. */ switch (sc->sc_chipset) { case QCOM_GCC_CHIPSET_IPQ4018: qcom_gcc_ipq4018_hwreset_init(sc); mem_sz = 0x60000; break; + case QCOM_GCC_CHIPSET_MSM8916: + qcom_gcc_msm8916_hwreset_init(sc); + mem_sz = 0x0; + break; case QCOM_GCC_CHIPSET_NONE: device_printf(dev, "Invalid chipset (%d)\n", sc->sc_chipset); return (ENXIO); } sc->reg_rid = 0; - sc->reg = bus_alloc_resource_anywhere(dev, SYS_RES_MEMORY, - &sc->reg_rid, mem_sz, RF_ACTIVE); + if (mem_sz != 0) + sc->reg = bus_alloc_resource_anywhere(dev, SYS_RES_MEMORY, + &sc->reg_rid, mem_sz, RF_ACTIVE); + else + sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, + &sc->reg_rid, RF_ACTIVE); + if (sc->reg == NULL) { device_printf(dev, "Couldn't allocate memory resource!\n"); return (ENXIO); } mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); /* * Register as a reset provider. */ hwreset_register_ofw_provider(dev); /* * Setup and register as a clock provider. */ switch (sc->sc_chipset) { case QCOM_GCC_CHIPSET_IPQ4018: qcom_gcc_ipq4018_clock_setup(sc); break; + case QCOM_GCC_CHIPSET_MSM8916: + qcom_gcc_msm8916_clock_setup(sc); + break; case QCOM_GCC_CHIPSET_NONE: device_printf(dev, "Invalid chipset (%d)\n", sc->sc_chipset); return (ENXIO); } return (0); } static int qcom_gcc_detach(device_t dev) { struct qcom_gcc_softc *sc; sc = device_get_softc(dev); /* * TBD - deregistering reset/clock resources. */ if (sc->reg != NULL) { bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->reg_rid, sc->reg); } return (0); } static device_method_t qcom_gcc_methods[] = { /* Device methods. */ DEVMETHOD(device_probe, qcom_gcc_probe), DEVMETHOD(device_attach, qcom_gcc_attach), DEVMETHOD(device_detach, qcom_gcc_detach), /* Reset interface */ DEVMETHOD(hwreset_assert, qcom_gcc_hwreset_assert), DEVMETHOD(hwreset_is_asserted, qcom_gcc_hwreset_is_asserted), /* Clock interface */ DEVMETHOD(clkdev_read_4, qcom_gcc_clock_read), DEVMETHOD(clkdev_write_4, qcom_gcc_clock_write), DEVMETHOD(clkdev_modify_4, qcom_gcc_clock_modify), DEVMETHOD(clkdev_device_lock, qcom_gcc_clock_lock), DEVMETHOD(clkdev_device_unlock, qcom_gcc_clock_unlock), DEVMETHOD_END }; static driver_t qcom_gcc_driver = { "qcom_gcc", qcom_gcc_methods, sizeof(struct qcom_gcc_softc) }; EARLY_DRIVER_MODULE(qcom_gcc, simplebus, qcom_gcc_driver, qcom_gcc_modevent, NULL, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY); EARLY_DRIVER_MODULE(qcom_gcc, ofwbus, qcom_gcc_driver, qcom_gcc_modevent, NULL, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY); MODULE_VERSION(qcom_gcc, 1); diff --git a/sys/dev/qcom_gcc/qcom_gcc_var.h b/sys/dev/qcom_gcc/qcom_gcc_msm8916.h similarity index 51% copy from sys/dev/qcom_gcc/qcom_gcc_var.h copy to sys/dev/qcom_gcc/qcom_gcc_msm8916.h index 2d4e969e1134..10758b0744a4 100644 --- a/sys/dev/qcom_gcc/qcom_gcc_var.h +++ b/sys/dev/qcom_gcc/qcom_gcc_msm8916.h @@ -1,80 +1,41 @@ /*- * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (c) 2021 Adrian Chadd + * Copyright (c) 2026 Adrian Chadd * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ -#ifndef __QCOM_GCC_VAR_H__ -#define __QCOM_GCC_VAR_H__ - -typedef enum { - QCOM_GCC_CHIPSET_NONE = 0, - QCOM_GCC_CHIPSET_IPQ4018 = 1, -} qcom_gcc_chipset_t; - -struct qcom_gcc_reset_entry { - uint32_t reg; - uint32_t bit; -}; - -struct qcom_gcc_hw_callbacks { - /* Reset block */ - int (*hw_reset_assert)(device_t, intptr_t, bool); - int (*hw_reset_is_asserted)(device_t, intptr_t, bool *); - - /* Clock block */ -}; - -struct qcom_gcc_softc { - device_t dev; - int reg_rid; - struct resource *reg; - struct mtx mtx; - struct clkdom *clkdom; - qcom_gcc_chipset_t sc_chipset; - struct qcom_gcc_hw_callbacks sc_cb; -}; +#ifndef __QCOM_GCC_MSM8916_H__ +#define __QCOM_GCC_MSM8916_H__ /* * reset block */ -extern int qcom_gcc_hwreset_assert(device_t dev, intptr_t id, - bool reset); -extern int qcom_gcc_hwreset_is_asserted(device_t dev, intptr_t id, - bool *reset); +extern void qcom_gcc_msm8916_hwreset_init(struct qcom_gcc_softc *); /* * clock block */ -extern int qcom_gcc_clock_read(device_t dev, bus_addr_t addr, - uint32_t *val); -extern int qcom_gcc_clock_write(device_t dev, bus_addr_t addr, - uint32_t val); -extern int qcom_gcc_clock_modify(device_t dev, bus_addr_t addr, - uint32_t clear_mask, uint32_t set_mask); -extern void qcom_gcc_clock_setup(struct qcom_gcc_softc *sc); -extern void qcom_gcc_clock_lock(device_t dev); -extern void qcom_gcc_clock_unlock(device_t dev); +extern void qcom_gcc_msm8916_clock_setup(struct qcom_gcc_softc *); -#endif /* __QCOM_GCC_VAR_H__ */ +#endif /* __QCOM_GCC_MSM8916_H__ */ diff --git a/sys/arm64/qualcomm/qcom_gcc.c b/sys/dev/qcom_gcc/qcom_gcc_msm8916_clock.c similarity index 60% rename from sys/arm64/qualcomm/qcom_gcc.c rename to sys/dev/qcom_gcc/qcom_gcc_msm8916_clock.c index 3f08577f4d3c..5c0e4afcc17f 100644 --- a/sys/arm64/qualcomm/qcom_gcc.c +++ b/sys/dev/qcom_gcc/qcom_gcc_msm8916_clock.c @@ -1,143 +1,84 @@ /*- * Copyright (c) 2018 Ruslan Bukin * All rights reserved. * * This software was developed by BAE Systems, the University of Cambridge * Computer Laboratory, and Memorial University under DARPA/AFRL contract * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing * (TC) research program. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include +#include "qcom_gcc_var.h" +#include "qcom_gcc_msm8916.h" + #define GCC_QDSS_BCR 0x29000 #define GCC_QDSS_BCR_BLK_ARES (1 << 0) /* Async software reset. */ #define GCC_QDSS_CFG_AHB_CBCR 0x29008 #define AHB_CBCR_CLK_ENABLE (1 << 0) /* AHB clk branch ctrl */ #define GCC_QDSS_ETR_USB_CBCR 0x29028 #define ETR_USB_CBCR_CLK_ENABLE (1 << 0) /* ETR USB clk branch ctrl */ #define GCC_QDSS_DAP_CBCR 0x29084 #define DAP_CBCR_CLK_ENABLE (1 << 0) /* DAP clk branch ctrl */ -static struct ofw_compat_data compat_data[] = { - { "qcom,gcc-msm8916", 1 }, - { NULL, 0 } -}; - -struct qcom_gcc_softc { - struct resource *res; -}; - -static struct resource_spec qcom_gcc_spec[] = { - { SYS_RES_MEMORY, 0, RF_ACTIVE }, - { -1, 0 } -}; - /* * Qualcomm Debug Subsystem (QDSS) * block enabling routine. */ static void -qcom_qdss_enable(struct qcom_gcc_softc *sc) +qcom_msm8916_qdss_enable(struct qcom_gcc_softc *sc) { /* Put QDSS block to reset */ - bus_write_4(sc->res, GCC_QDSS_BCR, GCC_QDSS_BCR_BLK_ARES); + bus_write_4(sc->reg, GCC_QDSS_BCR, GCC_QDSS_BCR_BLK_ARES); /* Enable AHB clock branch */ - bus_write_4(sc->res, GCC_QDSS_CFG_AHB_CBCR, AHB_CBCR_CLK_ENABLE); + bus_write_4(sc->reg, GCC_QDSS_CFG_AHB_CBCR, AHB_CBCR_CLK_ENABLE); /* Enable DAP clock branch */ - bus_write_4(sc->res, GCC_QDSS_DAP_CBCR, DAP_CBCR_CLK_ENABLE); + bus_write_4(sc->reg, GCC_QDSS_DAP_CBCR, DAP_CBCR_CLK_ENABLE); /* Enable ETR USB clock branch */ - bus_write_4(sc->res, GCC_QDSS_ETR_USB_CBCR, ETR_USB_CBCR_CLK_ENABLE); + bus_write_4(sc->reg, GCC_QDSS_ETR_USB_CBCR, ETR_USB_CBCR_CLK_ENABLE); /* Out of reset */ - bus_write_4(sc->res, GCC_QDSS_BCR, 0); -} - -static int -qcom_gcc_probe(device_t dev) -{ - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) - return (ENXIO); - - device_set_desc(dev, "Qualcomm Global Clock Controller"); - - return (BUS_PROBE_DEFAULT); + bus_write_4(sc->reg, GCC_QDSS_BCR, 0); } -static int -qcom_gcc_attach(device_t dev) +void +qcom_gcc_msm8916_clock_setup(struct qcom_gcc_softc *sc) { - struct qcom_gcc_softc *sc; - - sc = device_get_softc(dev); - - if (bus_alloc_resources(dev, qcom_gcc_spec, &sc->res) != 0) { - device_printf(dev, "cannot allocate resources for device\n"); - return (ENXIO); - } - - /* - * Enable debug unit. - * This is required for Coresight operation. - * This also enables USB clock branch. - */ - qcom_qdss_enable(sc); - - return (0); + qcom_msm8916_qdss_enable(sc); } - -static device_method_t qcom_gcc_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, qcom_gcc_probe), - DEVMETHOD(device_attach, qcom_gcc_attach), - - DEVMETHOD_END -}; - -static driver_t qcom_gcc_driver = { - "qcom_gcc", - qcom_gcc_methods, - sizeof(struct qcom_gcc_softc), -}; - -EARLY_DRIVER_MODULE(qcom_gcc, simplebus, qcom_gcc_driver, 0, 0, - BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); -MODULE_VERSION(qcom_gcc, 1); diff --git a/sys/dev/qcom_gcc/qcom_gcc_clock.c b/sys/dev/qcom_gcc/qcom_gcc_msm8916_reset.c similarity index 64% copy from sys/dev/qcom_gcc/qcom_gcc_clock.c copy to sys/dev/qcom_gcc/qcom_gcc_msm8916_reset.c index c8c10b0c5172..c83fd3e981ab 100644 --- a/sys/dev/qcom_gcc/qcom_gcc_clock.c +++ b/sys/dev/qcom_gcc/qcom_gcc_msm8916_reset.c @@ -1,98 +1,71 @@ /*- * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (c) 2025, Adrian Chadd + * Copyright (c) 2026 Adrian Chadd * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include "qcom_gcc_var.h" - -int -qcom_gcc_clock_read(device_t dev, bus_addr_t addr, uint32_t *val) -{ - struct qcom_gcc_softc *sc; +#include - sc = device_get_softc(dev); - *val = bus_read_4(sc->reg, addr); - return (0); -} - -int -qcom_gcc_clock_write(device_t dev, bus_addr_t addr, uint32_t val) -{ - struct qcom_gcc_softc *sc; +#include "hwreset_if.h" - sc = device_get_softc(dev); - bus_write_4(sc->reg, addr, val); - return (0); -} +#include "qcom_gcc_var.h" +#include "qcom_gcc_msm8916.h" -int -qcom_gcc_clock_modify(device_t dev, bus_addr_t addr, - uint32_t clear_mask, uint32_t set_mask) +static int +qcom_gcc_msm8916_hwreset_assert(device_t dev, intptr_t id, bool reset) { - struct qcom_gcc_softc *sc; - uint32_t reg; - - sc = device_get_softc(dev); - reg = bus_read_4(sc->reg, addr); - reg &= clear_mask; - reg |= set_mask; - bus_write_4(sc->reg, addr, reg); - return (0); + device_printf(dev, "%s: invalid id (%d)\n", __func__, (uint32_t) id); + return (EINVAL); } -void -qcom_gcc_clock_lock(device_t dev) +static int +qcom_gcc_msm8916_hwreset_is_asserted(device_t dev, intptr_t id, bool *reset) { - struct qcom_gcc_softc *sc; - - sc = device_get_softc(dev); - mtx_lock(&sc->mtx); + device_printf(dev, "%s: invalid id (%d)\n", __func__, (uint32_t) id); + return (EINVAL); } void -qcom_gcc_clock_unlock(device_t dev) +qcom_gcc_msm8916_hwreset_init(struct qcom_gcc_softc *sc) { - struct qcom_gcc_softc *sc; - - sc = device_get_softc(dev); - mtx_unlock(&sc->mtx); + sc->sc_cb.hw_reset_assert = qcom_gcc_msm8916_hwreset_assert; + sc->sc_cb.hw_reset_is_asserted = qcom_gcc_msm8916_hwreset_is_asserted; } diff --git a/sys/dev/qcom_gcc/qcom_gcc_var.h b/sys/dev/qcom_gcc/qcom_gcc_var.h index 2d4e969e1134..e3796f0d5f0f 100644 --- a/sys/dev/qcom_gcc/qcom_gcc_var.h +++ b/sys/dev/qcom_gcc/qcom_gcc_var.h @@ -1,80 +1,81 @@ /*- * SPDX-License-Identifier: BSD-2-Clause * * Copyright (c) 2021 Adrian Chadd * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #ifndef __QCOM_GCC_VAR_H__ #define __QCOM_GCC_VAR_H__ typedef enum { QCOM_GCC_CHIPSET_NONE = 0, QCOM_GCC_CHIPSET_IPQ4018 = 1, + QCOM_GCC_CHIPSET_MSM8916 = 2, } qcom_gcc_chipset_t; struct qcom_gcc_reset_entry { uint32_t reg; uint32_t bit; }; struct qcom_gcc_hw_callbacks { /* Reset block */ int (*hw_reset_assert)(device_t, intptr_t, bool); int (*hw_reset_is_asserted)(device_t, intptr_t, bool *); /* Clock block */ }; struct qcom_gcc_softc { device_t dev; int reg_rid; struct resource *reg; struct mtx mtx; struct clkdom *clkdom; qcom_gcc_chipset_t sc_chipset; struct qcom_gcc_hw_callbacks sc_cb; }; /* * reset block */ extern int qcom_gcc_hwreset_assert(device_t dev, intptr_t id, bool reset); extern int qcom_gcc_hwreset_is_asserted(device_t dev, intptr_t id, bool *reset); /* * clock block */ extern int qcom_gcc_clock_read(device_t dev, bus_addr_t addr, uint32_t *val); extern int qcom_gcc_clock_write(device_t dev, bus_addr_t addr, uint32_t val); extern int qcom_gcc_clock_modify(device_t dev, bus_addr_t addr, uint32_t clear_mask, uint32_t set_mask); extern void qcom_gcc_clock_setup(struct qcom_gcc_softc *sc); extern void qcom_gcc_clock_lock(device_t dev); extern void qcom_gcc_clock_unlock(device_t dev); #endif /* __QCOM_GCC_VAR_H__ */