Index: sys/arm/allwinner/a20/files.a20 =================================================================== --- sys/arm/allwinner/a20/files.a20 +++ sys/arm/allwinner/a20/files.a20 @@ -1,5 +1,5 @@ # $FreeBSD$ arm/allwinner/a20/a20_padconf.c standard -arm/allwinner/a20/a20_mp.c optional smp +arm/allwinner/aw_mp.c optional smp arm/allwinner/a20/a20_if_dwc.c optional dwc Index: sys/arm/allwinner/aw_mp.c =================================================================== --- sys/arm/allwinner/aw_mp.c +++ sys/arm/allwinner/aw_mp.c @@ -1,5 +1,6 @@ /*- * Copyright (c) 2014 Ganbold Tsagaankhuu + * Copyright (c) 2016 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -38,23 +39,39 @@ #include #include +#include #include #include #include -#define CPUCFG_BASE 0x01c25c00 +#include + +/* Register for all dual-core SoC */ +#define A20_CPUCFG_BASE 0x01c25c00 +/* Register for all quad-core SoC */ +#define A31_CPUCFG_BASE 0x01f01c00 #define CPUCFG_SIZE 0x400 +#define A31_PRCM_BASE 0x01f01400 +#define PRCM_SIZE 0x800 + +#define CPU_OFFSET 0x40 +#define CPU_OFFSET_CTL 0x04 +#define CPU_OFFSET_STATUS 0x08 +#define CPU_RST_CTL(cpuid) ((cpuid + 1) * CPU_OFFSET) +#define CPU_CTL(cpuid) (((cpuid + 1) * CPU_OFFSET) + CPU_OFFSET_CTL) +#define CPU_STATUS(cpuid) (((cpuid + 1) * CPU_OFFSET) + CPU_OFFSET_STATUS) -#define CPU0_RST_CTL 0x40 -#define CPU0_CTL 0x44 -#define CPU0_STATUS 0x48 -#define CPU1_RST_CTL 0x80 -#define CPU1_CTL 0x84 -#define CPU1_STATUS 0x88 #define CPUCFG_GENCTL 0x184 #define CPUCFG_P_REG0 0x1a4 -#define CPU1_PWR_CLAMP 0x1b0 -#define CPU1_PWROFF_REG 0x1b4 + +#define A20_CPU1_PWR_CLAMP 0x1b0 +#define A31_CPU_PWR_CLAMP_REG 0x140 +#define A31_CPU_PWR_CLAMP(cpu) ((cpu * 4) + A31_CPU_PWR_CLAMP_REG) +#define CPU_PWR_CLAMP_STEPS 8 + +#define A20_CPU1_PWROFF_REG 0x1b4 +#define A31_CPU_PWROFF 0x100 + #define CPUCFG_DBGCTL0 0x1e0 #define CPUCFG_DBGCTL1 0x1e4 @@ -69,13 +86,13 @@ platform_mp_setmaxid(void) { int ncpu; + uint32_t reg; if (mp_ncpus != 0) return; - /* Read the number of cores from the CP15 L2 Control Register. */ - __asm __volatile("mrc p15, 1, %0, c9, c0, 2" : "=r" (ncpu)); - ncpu = ((ncpu >> 24) & 0x3) + 1; + reg = cp15_l2ctlr_get(); + ncpu = CPUV7_L2CTLR_NPROC(reg); mp_ncpus = ncpu; mp_maxid = ncpu - 1; @@ -95,63 +112,106 @@ platform_mp_start_ap(void) { bus_space_handle_t cpucfg; - - uint32_t val; - - if (bus_space_map(fdtbus_bs_tag, CPUCFG_BASE, CPUCFG_SIZE, 0, - &cpucfg) != 0) + bus_space_handle_t prcm; + int i, j; + uint32_t val, soc_type; + + soc_type = allwinner_soc_type(); + switch (soc_type) { + case ALLWINNERSOC_A20: + if (bus_space_map(fdtbus_bs_tag, A20_CPUCFG_BASE, CPUCFG_SIZE, 0, + &cpucfg) != 0) + panic("Couldn't map the CPUCFG\n"); + break; + case ALLWINNERSOC_A31: + case ALLWINNERSOC_A31S: + if (bus_space_map(fdtbus_bs_tag, A31_CPUCFG_BASE, CPUCFG_SIZE, 0, + &cpucfg) != 0) panic("Couldn't map the CPUCFG\n"); + if (bus_space_map(fdtbus_bs_tag, A31_PRCM_BASE, PRCM_SIZE, 0, + &prcm) != 0) + panic("Couldn't map the PRCM\n"); + break; + } dcache_wbinv_poc_all(); bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_P_REG0, - pmap_kextract((vm_offset_t)mpentry)); + pmap_kextract((vm_offset_t)mpentry)); /* * Assert nCOREPORESET low and set L1RSTDISABLE low. * Ensure DBGPWRDUP is set to LOW to prevent any external * debug access to the processor. */ - bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_RST_CTL, 0); + for (i = 1; i < mp_ncpus; i++) + bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU_RST_CTL(i), 0); /* Set L1RSTDISABLE low */ val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPUCFG_GENCTL); - val &= ~(1 << 1); + for (i = 1; i < mp_ncpus; i++) + val &= ~(1 << i); bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_GENCTL, val); /* Set DBGPWRDUP low */ val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1); - val &= ~(1 << 1); + for (i = 1; i < mp_ncpus; i++) + val &= ~(1 << i); bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1, val); /* Release power clamp */ - bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0xff); - bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0x7f); - bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0x3f); - bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0x1f); - bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0x0f); - bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0x07); - bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0x03); - bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0x01); - bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWR_CLAMP, 0x00); + for (i = 1; i < mp_ncpus; i++) + for (j = 0; j <= CPU_PWR_CLAMP_STEPS; j++) { + switch (soc_type) { + case ALLWINNERSOC_A20: + bus_space_write_4(fdtbus_bs_tag, cpucfg, + A20_CPU1_PWR_CLAMP, + 0xff >> j); + break; + case ALLWINNERSOC_A31: + case ALLWINNERSOC_A31S: + bus_space_write_4(fdtbus_bs_tag, + prcm, + A31_CPU_PWR_CLAMP(i), + 0xff >> j); + } + } DELAY(10000); /* Clear power-off gating */ - val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPU1_PWROFF_REG); - val &= ~(1 << 0); - bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_PWROFF_REG, val); + switch (soc_type) { + case ALLWINNERSOC_A20: + val = bus_space_read_4(fdtbus_bs_tag, + cpucfg, A20_CPU1_PWROFF_REG); + val &= ~(1 << 0); + bus_space_write_4(fdtbus_bs_tag, cpucfg, + A20_CPU1_PWROFF_REG, val); + break; + case ALLWINNERSOC_A31: + case ALLWINNERSOC_A31S: + val = bus_space_read_4(fdtbus_bs_tag, prcm, A31_CPU_PWROFF); + for (i = 0; i < mp_ncpus; i++) + val &= ~(1 << i); + bus_space_write_4(fdtbus_bs_tag, prcm, A31_CPU_PWROFF, val); + break; + } DELAY(1000); /* De-assert cpu core reset */ - bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU1_RST_CTL, 3); + for (i = 1; i < mp_ncpus; i++) + bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU_RST_CTL(i), 3); /* Assert DBGPWRDUP signal */ val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1); - val |= (1 << 1); + for (i = 1; i < mp_ncpus; i++) + val |= (1 << i); bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1, val); armv7_sev(); bus_space_unmap(fdtbus_bs_tag, cpucfg, CPUCFG_SIZE); + if (soc_type == ALLWINNERSOC_A31 || + soc_type == ALLWINNERSOC_A31S) + bus_space_unmap(fdtbus_bs_tag, prcm, PRCM_SIZE); } void