LGTM. The code is also easier to read now, without those hw_direct_map conditionals.

Address jhibbits' comments

LGTM

LGTM.

Rebased.

Your changes look good to me overall.

It looks great now! Since this changes core libc functions, can you perform a buildworld on a system with the modified libc installed to confirm everything works fine?

@bruno.larsen_eldorado.org.br, overall your changes look good to me.
I have only one more suggestion and some nitpicks.

In D28776#646046, @alfredo wrote:

In D28776#645964, @bruno.larsen_eldorado.org.br wrote:

• improved formatting
• solution to the problem outlined by luporl

The alignment problem is solved, but this patch makes bcopy performance go down by a factor of 10. I think a third version of the code should be considered, restricting this patch only to POWER7 CPUs.

Does it produce any gain over original non-optimized code on Power7? If there's no gain I'd suggest restrict optimizations to ISA >= v.2.07 (POWER8). And in this case, remove unaligned access handling since newer CPUs can handle it transparently.

If there's still a gain I agree with having two optimized versions one handling VSX & ISA <=2.06 and the other for VSX & ISA >=2.07 (probably removing unaligned handling to make code simpler if no negative performance impact)

Worked fine on PPC64LE, both on Talos and QEMU, with D27475 to fix boot with ofwfb on LE.

Looks good. I have been using a slightly modified version of this on Talos II and it is working well.

Using only htole64() won't work in all cases.

The changes look good to me overall.

Leave superpages disabled by default

Wow, that's really a lot of endianness fixes, nice job!

Restore comment about tlbie instruction forms

• improve performance
  • force inline in new moea64_pte_* functions to avoid extra overhead with clang -O now defaulting -O1
  • look for superpage PVO in moea64_enter only when superpages are enabled
  • use multiple PV locks for superpage ops, instead of making a single PV lock cover a superpage

Rename ppcpnv/powernv to power8.

This diff has several changes on top of the previous one. The main ones are:

Fix ERAT multi-hit issue

Looks good to me.

• address (part of) markj's comments

Address jhibbits' comments

Address bdragon's comments

In D26114#580412, @bdragon wrote:

Makes sense to me. Is there a good way to test this?

Additionally, I believe this would also be relevant to ppc32, perhaps use the __powerpc__ ifdef instead.

In D26113#579628, @kbowling wrote:

One thing we do have is the full power8/9 pmcs in src/lib/libpmc/pmu-events/arch. I think these just need to be hooked up

Looks good to me.