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May 17 2017

zbb committed rS318410: Fix broken malloc in e6000sw.
Fix broken malloc in e6000sw
May 17 2017, 3:58 PM
zbb closed D10711: Fix broken malloc in e6000sw by committing rS318410: Fix broken malloc in e6000sw.
May 17 2017, 3:58 PM · ARM
zbb committed rS318409: Fix registration of MPIC driver.
Fix registration of MPIC driver
May 17 2017, 3:57 PM
zbb closed D10717: Fix registration of MPIC driver by committing rS318409: Fix registration of MPIC driver.
May 17 2017, 3:57 PM · ARM
zbb committed rS318408: Correct MPIC order of attachment.
Correct MPIC order of attachment
May 17 2017, 3:56 PM
zbb closed D10715: Correct MPIC order of attachment by committing rS318408: Correct MPIC order of attachment.
May 17 2017, 3:56 PM · ARM
zbb committed rS318407: Enable proper parsing of nested simlpe-buses on Marvell platforms.
Enable proper parsing of nested simlpe-buses on Marvell platforms
May 17 2017, 3:54 PM
zbb closed D10719: Enable proper parsing of nested simlpe-buses on Marvell platforms by committing rS318407: Enable proper parsing of nested simlpe-buses on Marvell platforms.
May 17 2017, 3:54 PM · ARM
zbb committed rS318406: Parse EHCI windows on Marvell platforms.
Parse EHCI windows on Marvell platforms
May 17 2017, 3:53 PM
zbb closed D10722: Parse EHCI windows on Marvell platforms by committing rS318406: Parse EHCI windows on Marvell platforms.
May 17 2017, 3:53 PM · ARM
zbb committed rS318405: Fix USB3.0 decoding windows on Armada38x.
Fix USB3.0 decoding windows on Armada38x
May 17 2017, 3:52 PM
zbb closed D10721: Fix USB3.0 decoding windows on Armada38x by committing rS318405: Fix USB3.0 decoding windows on Armada38x.
May 17 2017, 3:52 PM · ARM

May 15 2017

zbb added a comment to D10682: Introduce platform CPU init for ARM.
In D10682#222298, @zbb wrote:

Also if we use platform_late_init there would be a need to rework all late_init implementations so that they could be used in the init_secondary.

It's not very difficult to rework platform_late_init, see D10733.

May 15 2017, 1:03 PM
zbb added a comment to D10682: Introduce platform CPU init for ARM.
In D10682#222184, @meloun-miracle-cz wrote:

I think that this patch is not longer needed?
Both issues (device memory class remap, ACTRL modification) can be processed in platform_late_init().
I'm right?

May 15 2017, 11:54 AM
zbb added a comment to D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.
In D9864#222185, @meloun-miracle-cz wrote:

I would prefer to move this code to platform_late_init().
The only drawback is that you must use cp15_actlr_set() + cp15_actlr_get() for boot CPU...

May 15 2017, 11:44 AM
zbb added a comment to D10218: Implement workaround for Armada 38X family HW issue between CPU and devices.
In D10218#221808, @skra wrote:
In D10218#221730, @zbb wrote:

@skra Why are we not able to pmap_set_tex() while caches are enabled? We are merely modifying two registers. TLB invalidation should be the only thing that is required to be done. Could you elaborate this constraint a little? It seems that this is the only thing that is holding us back from the acceptable solution so I would like to understand the issue.
Thanks in advance for your help.

My note was about two aspects of pmap_remap_vm_attr().
(1) Generally, when cache is enabled, changing cache mode of memory in active use (i.e. any memory which is mapped (keep in mind speculative reads)) is a tricky thing if possible at all. It's a problem of atomicity of such action. It's also a thing of how cache itself and cache maintainance functions work. Imagine that a page is remapped from cached mode to uncached one. All cachelines associated with this page must be removed from cache. To do this while the page is mapped as cached is not enough because of speculative reads. To do this after the page is remapped will not work as the mapping is uncached and cache maintainance function may do nothing for uncached memory. Note that access to uncached memory may still go thru cache.
Some cache modes may be change to others without problem, but it's not true for every combination of cache modes. Maybe, under very strict circumstances, it could be possible to change cache mode in some memory region.
However, pmap_remap_vm_attr() works globally for every TEX class combination. It touches all memory mapped with TEXs being changed. So, my concern was to comment such function properly to specify when it's safe to use it.
(2) Code consistency. Either some explanation should have been done why pmap_set_tex() can be used in pmap_remap_vm_attr() or comment in pmap_set_tex() should have been changed.
Well, it looks that r318251 answered my note.

May 15 2017, 11:38 AM

May 12 2017

zbb added a comment to D10218: Implement workaround for Armada 38X family HW issue between CPU and devices.

@skra Why are we not able to pmap_set_tex() while caches are enabled? We are merely modifying two registers. TLB invalidation should be the only thing that is required to be done. Could you elaborate this constraint a little? It seems that this is the only thing that is holding us back from the acceptable solution so I would like to understand the issue.
Thanks in advance for your help.

May 12 2017, 6:55 PM
zbb added a comment to D10218: Implement workaround for Armada 38X family HW issue between CPU and devices.
In D10218#221634, @skra wrote:
In D10218#221615, @zbb wrote:
In D10218#221537, @skra wrote:

Note that pmap_remap_vm_attr() calls pmap_set_tex() which assumes that all caches are disabled (see last two lines in this function). Caches are enabled in reinit_mmu() which is called from pmap_bootstrap_prepare() and init_secondary(). It's unfortunate that Michal did not add some comment about this to pmap_remap_vm_attr(). However, it's just a note for now as use of platform_cpu_init() is not clear so far.

Yes. This must be called where it is being called now. Unfortunately platform_ code seems to be unusable for our case.
BTW. What is unclear for you regarding the use of platform_cpu_init()? There was a need to modify the default, hard-coded settings of the mappings as well as CPUs auxiliary control register. Use of another platform callback was suggested instead of ugly ifdef or another hard-coded setting of ACTLR (that was undesirable on some Cortex revisions). That is why we created this function and we use it in the related patches (please see dependencies) to modify default CPU/MMU settings.

Just wanted to say that pmap_remap_vm_attr() must be called before pmap_bootstrap_prepare(). And even if platform cpu_init() method is introduced in another place (D10682) where platform_cpu_init() is called before pmap_bootstrap_prepare(), it's used before platform code is initialized and it's wrong. So, it's unclear for now if this patch will satisfy what was noted by me.

May 12 2017, 1:20 PM
zbb added inline comments to D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.
May 12 2017, 11:48 AM
zbb added a comment to D10682: Introduce platform CPU init for ARM.

Let us summarize what we deal with.

May 12 2017, 10:32 AM
zbb added inline comments to D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.
May 12 2017, 10:29 AM
zbb added inline comments to D10682: Introduce platform CPU init for ARM.
May 12 2017, 10:22 AM
zbb added a comment to D10218: Implement workaround for Armada 38X family HW issue between CPU and devices.
In D10218#221537, @skra wrote:

Note that pmap_remap_vm_attr() calls pmap_set_tex() which assumes that all caches are disabled (see last two lines in this function). Caches are enabled in reinit_mmu() which is called from pmap_bootstrap_prepare() and init_secondary(). It's unfortunate that Michal did not add some comment about this to pmap_remap_vm_attr(). However, it's just a note for now as use of platform_cpu_init() is not clear so far.

May 12 2017, 10:20 AM

May 11 2017

zbb updated the diff for D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.

Reworked to use platform call.

May 11 2017, 4:01 PM
zbb added a comment to D10218: Implement workaround for Armada 38X family HW issue between CPU and devices.
In D10218#220936, @meloun-miracle-cz wrote:

Committed as r318021. Sorry for huge delay...

May 11 2017, 4:00 PM
zbb updated the diff for D10218: Implement workaround for Armada 38X family HW issue between CPU and devices.

Reworked to use a platform call instead of a hard-coded value.

May 11 2017, 3:59 PM
zbb commandeered D10218: Implement workaround for Armada 38X family HW issue between CPU and devices.
May 11 2017, 3:58 PM
zbb created D10683: Introduce platform CPU info container for ARM. Use it for ACTLR..
May 11 2017, 3:57 PM
zbb created D10682: Introduce platform CPU init for ARM.
May 11 2017, 3:55 PM

Apr 27 2017

zbb committed rS317518: Import Amazon Elastic Network Adapter (ENA) HAL to sys/contrib/.
Import Amazon Elastic Network Adapter (ENA) HAL to sys/contrib/
Apr 27 2017, 7:57 PM
zbb committed rS317516: Introduce HAL for Amazon Elastic Network Adapter (ENA).
Introduce HAL for Amazon Elastic Network Adapter (ENA)
Apr 27 2017, 7:41 PM

Apr 18 2017

zbb closed D10219: Optimize Armada38x low-level MBUS settings by committing rS317090: Optimize Armada38x low-level MBUS settings.
Apr 18 2017, 10:39 AM
zbb committed rS317090: Optimize Armada38x low-level MBUS settings.
Optimize Armada38x low-level MBUS settings
Apr 18 2017, 10:39 AM
zbb closed D10223: Fix bit assignment in PL310_POWER_CTRL by committing rS317089: Fix bit assignment in PL310_POWER_CTRL.
Apr 18 2017, 10:37 AM
zbb committed rS317089: Fix bit assignment in PL310_POWER_CTRL.
Fix bit assignment in PL310_POWER_CTRL
Apr 18 2017, 10:37 AM
zbb committed rS317088: Add PL310 device in ARMADA38X config.
Add PL310 device in ARMADA38X config
Apr 18 2017, 10:35 AM
zbb closed D10222: Add PL310 device in ARMADA38X config by committing rS317088: Add PL310 device in ARMADA38X config.
Apr 18 2017, 10:35 AM
zbb closed D10221: Execute PL310_ERRATA_727915 only for related revisions by committing rS317087: Execute PL310_ERRATA_727915 only for related revisions.
Apr 18 2017, 10:34 AM
zbb committed rS317087: Execute PL310_ERRATA_727915 only for related revisions.
Execute PL310_ERRATA_727915 only for related revisions
Apr 18 2017, 10:34 AM
zbb committed rS317086: Add PL310 platform initialization for Armada 38x.
Add PL310 platform initialization for Armada 38x
Apr 18 2017, 10:32 AM
zbb closed D10220: Add PL310 platform initialization for Armada 38x by committing rS317086: Add PL310 platform initialization for Armada 38x.
Apr 18 2017, 10:32 AM
zbb closed D10217: Increase number of L2 tables required for kernel bootstrap by committing rS317085: Increase number of L2 tables required for kernel bootstrap.
Apr 18 2017, 10:26 AM
zbb committed rS317085: Increase number of L2 tables required for kernel bootstrap.
Increase number of L2 tables required for kernel bootstrap
Apr 18 2017, 10:26 AM
zbb committed rS317084: Reduce kmem_arena maximum size for Armada38x.
Reduce kmem_arena maximum size for Armada38x
Apr 18 2017, 10:20 AM
zbb closed D10216: Reduce kmem_arena maximum size by committing rS317084: Reduce kmem_arena maximum size for Armada38x.
Apr 18 2017, 10:20 AM

Apr 5 2017

zbb added a comment to D10218: Implement workaround for Armada 38X family HW issue between CPU and devices.

@meloun-miracle-cz your solution presented here https://github.com/strejda/tegra/commit/3b5138751ee5643992b20fcb21b280fab433bb20 looks very good.
It would be nice if you could commit this to the HEAD.

Apr 5 2017, 10:54 AM

Mar 31 2017

zbb committed rS316336: Rework BGX detection to support both new and old firmware.
Rework BGX detection to support both new and old firmware
Mar 31 2017, 6:05 PM
zbb closed D9863: Rework BGX detection to support both new and old firmware by committing rS316336: Rework BGX detection to support both new and old firmware.
Mar 31 2017, 6:05 PM
zbb added a comment to D9863: Rework BGX detection to support both new and old firmware.

@andrew Do you have any objections to committing this patch? If not, I would like to push it to head. It was marinated long enough here :)

Mar 31 2017, 10:09 AM

Mar 8 2017

zbb added a comment to D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.
In D9864#205105, @meloun-miracle-cz wrote:

Ahh, I see now, Marvell subtree is not fully converted to platform model :) . But trust me, conversion its not that hard and makes your life much easier.
Also, there is global effort to make single generic kernel for all supported armv6 boards, and #ifdef SoC only technique is in direct direct contradiction with this goal.
See allwinner subtree, mainly aw_machdep.c. This platform supports numerous board with single kernel in 'right' way, without #ifdef hell.
But anyway, because SYSINIT() based proposal doesn't 'collide' with other boards/platforms, I have no objections. Now platform method seems more flexible, but that's just my personal opinion.

Mar 8 2017, 10:21 AM

Mar 7 2017

zbb added a comment to D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.
In D9864#204949, @meloun-miracle-cz wrote:

In D9864#204948, @zbb wrote:
In general, I don't insist on adding this change to all Cortex-A9 CPUs and I acknowledge your arguments.
Another platform-dependent method is OK for us. We need something that will be executed on both primary and secondary CPUs. It would be best if this stays in a common place for both primary and secondary CPUs (such as cpu_setup() is common for CPU0 and CPUx).
What do you think?

Yep, I have no problem with this {if cpu_setup() is new platform method). I prefer to call this new function in the place where cpuinfo is initialized and printf is working.

Mar 7 2017, 6:04 PM
zbb added a comment to D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.
In D9864#204946, @meloun-miracle-cz wrote:

I'm sorry about my platform_mp_start_ap() mistake.
I understand that cpuinfo_get_actlr_modifier() looks like most direct (and most easier) way how to make this. But again, this setting must be platform dependent.
Assume that you have 2 different boards (with different bootloaders) but with exactly same CPU. One board start OS in secure world, one in non-secure. . Then, write to ACTRL is OK for first one, but may cause exception on second.
IMO, we can add another platform method, say platform_late_init_ap(), called from here https://svnweb.freebsd.org/base/head/sys/arm/arm/mp_machdep.c?view=markup#l182.
Is this sufficient for you ?

Mar 7 2017, 3:44 PM
zbb added a comment to D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.

BTW. How do you expect u-boot to turn this bit on if it always works in UP?

Mar 7 2017, 2:28 PM

Mar 6 2017

zbb added a comment to D9863: Rework BGX detection to support both new and old firmware.

The BGX interface is unconnected in the ThunderX units in the netperf cluster

Mar 6 2017, 1:55 PM
zbb added a comment to D9863: Rework BGX detection to support both new and old firmware.

Any comments or test results?

Mar 6 2017, 12:01 PM
zbb reclaimed D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.
Mar 6 2017, 10:55 AM
zbb added a comment to D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.
In D9864#204162, @meloun-miracle-cz wrote:

Yep, fully agree. From my point of view, platform_late_init() (for BP) is best place for performance tweaks. At this point, printf() works and cpuinfo is initialized, so you can check proper CPU revision, print some warning about potentially dangerous action, etc...
For AP, you can use standard platform_mp_start_ap(), but many ACTRL bits are shared between CPU's. So, typically, it's sufficient to set up only BP.
Unfortunately, platform_late_init() is called to late for majority of errata fixups - in this case, i think that only real safe solution is bootloader fix.

Mar 6 2017, 10:54 AM

Mar 3 2017

zbb added a comment to D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.

@meloun-miracle-cz just to consider all possibillities. Do you have any idea whatsoever how this change could be inserted into the OS (in case there is no possibility to modify firmware), even in form of an option or platform-specific stuff?

Mar 3 2017, 6:57 PM
zbb abandoned D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.
In D9864#203677, @meloun-miracle-cz wrote:

See Erratum 571620, 719331, 719332, 751473 and probably more others.
Right place for proper CPU setup (including recommended errata fixes) is bootloader, not a boot stage of OS.
Please take in account:

  • on many boards, OS starts in in non-secure mode with disabled access to ACTRL (Pandaboard is one example).
  • effect of NS write to protected ACTRL is not consistent across for Cortex family, some CPU's ignore writes, some generates exception (A8, and probably some older A9).
  • the current code writes to ACTRL only if bits absolutely necessary for FreeBSD run are not set. In this case, it's irrelevant if we crashes here, or few instruction later.
Mar 3 2017, 2:17 PM

Mar 2 2017

zbb updated subscribers of D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs.
Mar 2 2017, 2:40 PM
zbb retitled D9864: Enable L1 Dcache prefetch for Cortex A9 CPUs from to Enable L1 Dcache prefetch for Cortex A9 CPUs.
Mar 2 2017, 2:30 PM
zbb retitled D9863: Rework BGX detection to support both new and old firmware from to Rework BGX detection to support both new and old firmware.
Mar 2 2017, 2:28 PM

Jan 23 2017

zbb accepted D9222: Add support for AHCI on ARMADA38X.
Jan 23 2017, 11:21 AM

Jan 19 2017

zbb accepted D9247: Use SoC ID - based detection in CESA.
Jan 19 2017, 6:09 PM
zbb accepted D9248: Add misssing Armada38x ID's in CESA attach.
Jan 19 2017, 6:00 PM

Jan 17 2017

zbb requested changes to D9222: Add support for AHCI on ARMADA38X.
Jan 17 2017, 7:03 PM
zbb requested changes to D9221: Enable optional soft reset in AHCI.

I think we should change this commit after all. I would prefer not to see soft_reset_del uninitialized for other drivers than Armada AHCI even though it is a part of ahci_controller structure. The better solution would be to create another quirk and activate it in the Armada AHCI wrapper according to the FDT property. We can then hard code the delay value in the generic AHCI driver and call it when the quirk is active.

Jan 17 2017, 6:52 PM
zbb accepted D9220: Setup decoding windows for ARMADA38X AHCI.
Jan 17 2017, 6:34 PM
zbb accepted D9219: Fix node detection for MBUS windows configuration.
Jan 17 2017, 6:32 PM
zbb accepted D9218: Expand OpenFirmware API with ofw_bus_node_status_okay method.

This is a useful change. +1

Jan 17 2017, 6:31 PM
zbb accepted D9215: Fix SHA256 usage on older CESA versions.
Jan 17 2017, 6:30 PM

Jan 5 2017

zbb committed rS311455: Add DTS file for Armada 385 DB-AP board.
Add DTS file for Armada 385 DB-AP board
Jan 5 2017, 5:28 PM
zbb closed D7327: Add DTS file for Armada 385 DB-AP board by committing rS311455: Add DTS file for Armada 385 DB-AP board.
Jan 5 2017, 5:28 PM
zbb committed rS311454: Add DTS file for Solidrun ClearFog board.
Add DTS file for Solidrun ClearFog board
Jan 5 2017, 5:25 PM
zbb closed D7326: Add DTS file for Solidrun ClearFog board by committing rS311454: Add DTS file for Solidrun ClearFog board.
Jan 5 2017, 5:25 PM
zbb committed rS311451: Correct CESA node in armada-38x.dtsi.
Correct CESA node in armada-38x.dtsi
Jan 5 2017, 5:15 PM
zbb closed D8180: Correct CESA node in armada-38x.dtsi by committing rS311451: Correct CESA node in armada-38x.dtsi.
Jan 5 2017, 5:15 PM
zbb committed rS311450: Add buffer management entries to armada-38x.dtsi.
Add buffer management entries to armada-38x.dtsi
Jan 5 2017, 5:13 PM
zbb closed D8179: Add bm entries to armada-38x.dtsi by committing rS311450: Add buffer management entries to armada-38x.dtsi.
Jan 5 2017, 5:13 PM
zbb closed D8178: Include e6000sw driver in compilation by committing rS311449: Include e6000sw driver in ARMADA38X configuration.
Jan 5 2017, 5:11 PM
zbb committed rS311449: Include e6000sw driver in ARMADA38X configuration.
Include e6000sw driver in ARMADA38X configuration
Jan 5 2017, 5:11 PM
zbb committed rS311448: Improve ports handling in e6000sw driver.
Improve ports handling in e6000sw driver
Jan 5 2017, 5:08 PM
zbb closed D7328: Improve ports handling in e6000sw driver by committing rS311448: Improve ports handling in e6000sw driver.
Jan 5 2017, 5:08 PM

Sep 6 2016

zbb accepted D7568: Register GICv3 xref.
Sep 6 2016, 3:32 PM
zbb added a reviewer for D7568: Register GICv3 xref: wma.
Sep 6 2016, 3:15 PM
zbb added a reviewer for D7565: Introduce support for Annapurna Alpine CCU and NB devices: wma.
Sep 6 2016, 3:15 PM

Jun 29 2016

zbb accepted D7023: ARM64: fix DMAP calculation.
Jun 29 2016, 12:16 PM

Jun 3 2016

zbb committed rS301282: Use proper interface for FDT parsing and memory mapping in CESA.
Use proper interface for FDT parsing and memory mapping in CESA
Jun 3 2016, 6:54 PM
zbb committed rS301281: Use nitems() macro instead of re-inventing it.
Use nitems() macro instead of re-inventing it
Jun 3 2016, 6:53 PM

Jun 2 2016

zbb committed rS301225: Add support for CESA on Armada38x.
Add support for CESA on Armada38x
Jun 2 2016, 6:41 PM
zbb closed D6220: Add support for CESA on Armada38x by committing rS301225: Add support for CESA on Armada38x.
Jun 2 2016, 6:41 PM
zbb committed rS301224: Add HMAC-SHA256 support in CESA.
Add HMAC-SHA256 support in CESA
Jun 2 2016, 6:39 PM
zbb closed D6219: Add HMAC-SHA256 support in CESA by committing rS301224: Add HMAC-SHA256 support in CESA.
Jun 2 2016, 6:39 PM
zbb committed rS301223: Truncate HMAC output only if requested by the client.
Truncate HMAC output only if requested by the client
Jun 2 2016, 6:38 PM
zbb closed D6218: Truncate HMAC output only if requested by the client by committing rS301223: Truncate HMAC output only if requested by the client.
Jun 2 2016, 6:38 PM
zbb committed rS301222: Split CESA memory resource into TDMA and CESA regs.
Split CESA memory resource into TDMA and CESA regs
Jun 2 2016, 6:35 PM
zbb closed D6217: Split CESA memory resource into TDMA and CESA regs by committing rS301222: Split CESA memory resource into TDMA and CESA regs.
Jun 2 2016, 6:35 PM
zbb committed rS301221: Configure CPU window to second CESA SRAM.
Configure CPU window to second CESA SRAM
Jun 2 2016, 6:33 PM
zbb closed D6216: Configure CPU window to second CESA SRAM by committing rS301221: Configure CPU window to second CESA SRAM.
Jun 2 2016, 6:33 PM
zbb committed rS301220: Map CESA SRAM memory in driver attach for Armada38x.
Map CESA SRAM memory in driver attach for Armada38x
Jun 2 2016, 6:31 PM