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May 5 2023

christos updated the diff for D39884: kinst: port to riscv.

Add some spaces.

May 5 2023, 12:20 PM · riscv, DTrace
christos updated the diff for D39884: kinst: port to riscv.

Remove dtrace_cddl.h ifdefs as they'll also be needed by the aarch64 port.

May 5 2023, 12:19 PM · riscv, DTrace

May 4 2023

christos added inline comments to D39884: kinst: port to riscv.
May 4 2023, 4:56 PM · riscv, DTrace
christos added a comment to D39884: kinst: port to riscv.

I agree, they provide some of the tools/definitions we need, but not all. I won't block this work on that, but we should work together to plan how it can be improved. FYI encoding.h is a generated file, so we should not stick custom definitions in there. I'll take a bit of time to consider how this can be organized so it is reusable elsewhere.

May 4 2023, 4:51 PM · riscv, DTrace
mhorne added a comment to D39884: kinst: port to riscv.

My main hesitation with the change is the magic numbers in the instruction parsing... named constants are preferable in general. I guess you looked a bit at what is provided by encoding.h and riscvreg.h?

I have, but it's quite limited, which is why I decided to go with no constants from encoding.h and riscvreg.h for now. I am however thinking of patching those 2 header files to include more constants which can be used in kinst.

May 4 2023, 4:50 PM · riscv, DTrace
christos added inline comments to D39884: kinst: port to riscv.
May 4 2023, 4:12 PM · riscv, DTrace
christos added a comment to D39884: kinst: port to riscv.

My main hesitation with the change is the magic numbers in the instruction parsing... named constants are preferable in general. I guess you looked a bit at what is provided by encoding.h and riscvreg.h?

May 4 2023, 4:09 PM · riscv, DTrace
mhorne added a comment to D39884: kinst: port to riscv.

Thanks for working on this, it's a great tool to have. I'll trust most of the functional parts to your testing and Mark's review.

May 4 2023, 3:46 PM · riscv, DTrace
christos updated the diff for D39884: kinst: port to riscv.

Add riscv to dtraceall

May 4 2023, 12:14 PM · riscv, DTrace

May 1 2023

jhb accepted D39894: riscv: do not duplicate sd of tp.
May 1 2023, 6:49 PM · riscv
christos added inline comments to D39582: riscv/exception.S: save the thread pointer in both modes.
May 1 2023, 3:47 PM · riscv
christos requested review of D39894: riscv: do not duplicate sd of tp.
May 1 2023, 3:44 PM · riscv
christos updated the diff for D39884: kinst: port to riscv.

Address Mark's comments.

May 1 2023, 3:24 PM · riscv, DTrace
markj added inline comments to D39884: kinst: port to riscv.
May 1 2023, 2:12 PM · riscv, DTrace
christos updated the diff for D39884: kinst: port to riscv.

Ignore LL/SC blocks.

May 1 2023, 12:49 PM · riscv, DTrace

Apr 30 2023

christos requested review of D39884: kinst: port to riscv.
Apr 30 2023, 2:17 PM · riscv, DTrace

Apr 20 2023

markj closed D39611: dtrace: add register bindings for RISC-V.
Apr 20 2023, 5:38 PM · riscv, DTrace
markj closed D39652: riscv/dtrace_subr.c: use dtrace_instr_size().
Apr 20 2023, 5:38 PM · riscv, DTrace

Apr 18 2023

markj accepted D39611: dtrace: add register bindings for RISC-V.
Apr 18 2023, 3:53 PM · riscv, DTrace
markj accepted D39652: riscv/dtrace_subr.c: use dtrace_instr_size().
Apr 18 2023, 3:52 PM · riscv, DTrace
mhorne accepted D39652: riscv/dtrace_subr.c: use dtrace_instr_size().

Much better, thanks.

Apr 18 2023, 3:01 PM · riscv, DTrace
christos requested review of D39652: riscv/dtrace_subr.c: use dtrace_instr_size().
Apr 18 2023, 12:47 PM · riscv, DTrace

Apr 17 2023

mhorne accepted D39611: dtrace: add register bindings for RISC-V.
Apr 17 2023, 8:52 PM · riscv, DTrace
christos updated the diff for D39611: dtrace: add register bindings for RISC-V.

Add /* NOTREACHED */ at the end of dtrace_getreg().

Apr 17 2023, 7:59 PM · riscv, DTrace
jhb added inline comments to D39582: riscv/exception.S: save the thread pointer in both modes.
Apr 17 2023, 5:13 PM · riscv
christos added inline comments to D39611: dtrace: add register bindings for RISC-V.
Apr 17 2023, 5:05 PM · riscv, DTrace
mhorne accepted D39611: dtrace: add register bindings for RISC-V.
Apr 17 2023, 4:51 PM · riscv, DTrace
christos updated the diff for D39611: dtrace: add register bindings for RISC-V.

Bump version to 1.13.

Apr 17 2023, 4:09 PM · riscv, DTrace
christos added inline comments to D39611: dtrace: add register bindings for RISC-V.
Apr 17 2023, 3:33 PM · riscv, DTrace
christos added inline comments to D39611: dtrace: add register bindings for RISC-V.
Apr 17 2023, 3:32 PM · riscv, DTrace
markj added inline comments to D39611: dtrace: add register bindings for RISC-V.
Apr 17 2023, 3:19 PM · riscv, DTrace
christos updated the diff for D39611: dtrace: add register bindings for RISC-V.

Add FP.

Apr 17 2023, 3:15 PM · riscv, DTrace
christos added inline comments to D39611: dtrace: add register bindings for RISC-V.
Apr 17 2023, 3:12 PM · riscv, DTrace
markj closed D39582: riscv/exception.S: save the thread pointer in both modes.
Apr 17 2023, 1:50 PM · riscv
mhorne added inline comments to D39611: dtrace: add register bindings for RISC-V.
Apr 17 2023, 1:35 PM · riscv, DTrace
christos updated the diff for D39611: dtrace: add register bindings for RISC-V.
Apr 17 2023, 2:13 AM · riscv, DTrace
christos removed a member for riscv: christos.
Apr 17 2023, 2:09 AM
christos updated the diff for D39611: dtrace: add register bindings for RISC-V.

Forgot riscv_regs.d

Apr 17 2023, 2:05 AM · riscv, DTrace
christos requested review of D39611: dtrace: add register bindings for RISC-V.
Apr 17 2023, 2:01 AM · riscv, DTrace

Apr 16 2023

christos added a member for riscv: christos.
Apr 16 2023, 10:41 PM

Apr 15 2023

markj accepted D39582: riscv/exception.S: save the thread pointer in both modes.
Apr 15 2023, 10:27 PM · riscv
mhorne accepted D39582: riscv/exception.S: save the thread pointer in both modes.

Nice!

Apr 15 2023, 8:56 PM · riscv
christos requested review of D39582: riscv/exception.S: save the thread pointer in both modes.
Apr 15 2023, 4:30 PM · riscv

Nov 30 2022

gehaowu_bitmoe.com added a watcher for riscv: gehaowu_bitmoe.com.
Nov 30 2022, 1:52 AM

Jun 21 2022

kfv_kfv.io removed a member for riscv: kfv_kfv.io.
Jun 21 2022, 11:18 AM

Dec 19 2021

pkubaj closed D30862: Add OPENMP for riscv64*.
Dec 19 2021, 10:43 PM · riscv
mhorne added a comment to D30862: Add OPENMP for riscv64*.

@mhorne
OK to MFC it to stable/13?

Dec 19 2021, 9:57 PM · riscv
pkubaj reopened D30862: Add OPENMP for riscv64*.

@mhorne
OK to MFC it to stable/13?

Dec 19 2021, 9:18 PM · riscv

Nov 18 2021

kfv_kfv.io added a member for riscv: kfv_kfv.io.
Nov 18 2021, 5:11 PM

Jul 24 2021

oskar.holmlund_ohdata.se added a member for riscv: oskar.holmlund_ohdata.se.
Jul 24 2021, 10:37 PM

Jul 10 2021

freebsdphab-AX9_cmx.ietfng.org added a comment to D31118: riscv pmap_fault: SFENCE.VMA more selectively.

Oof, that erratum; thanks for the heads up. I guess that means there should be some mechanism to replace (other uses of) sfence_vma_page with sfence_vma on effected chips? I think specifically for this case, though, it's fine: the ITLB may still fill with the old entry before this sfence.vma, but pmap_fault only changes A/D here. I suppose there could be an extra fault delivered from caching an A-clear PTE (if the load is done now by some very prognosticative speculation, say) despite that pmap_fault just set it, and I imagine the ITLB doesn't care about D at all. This extra fault will land us here again and cause another sfence.vma and even if the ITLB simultaneously refills the PTE about to be sfence.vma-ed, it will definitely see the A-set PTE from the last go around. That is, I don't think this makes anything worse.

Jul 10 2021, 3:20 PM · riscv

Jul 9 2021

jrtc27 added a reviewer for D31118: riscv pmap_fault: SFENCE.VMA more selectively: jrtc27.
Jul 9 2021, 8:33 PM · riscv
jrtc27 added a comment to D31118: riscv pmap_fault: SFENCE.VMA more selectively.

And how does this interact with the fact that we don't invalidate on promotion? I believe sfence.vma with an address is only required to invalidate leaves, but TLBs can cache non-leaves, so we could still return, have the processor use the stale cached non-superpage L2 entry, find the old leaves that are still around (because we keep them around) and reuse those?

Jul 9 2021, 8:31 PM · riscv
jrtc27 added a comment to D31118: riscv pmap_fault: SFENCE.VMA more selectively.

Although perhaps that's fine if this is in the _fault_ path?

Jul 9 2021, 8:21 PM · riscv
jrtc27 added a comment to D31118: riscv pmap_fault: SFENCE.VMA more selectively.

This will hit SiFive FU740 erratum CIP-1200 (https://sifive.cdn.prismic.io/sifive/167a1a56-03f4-4615-a79e-b2a86153148f_FU740_errata_20210205.pdf).

Jul 9 2021, 8:20 PM · riscv
mhorne accepted D31118: riscv pmap_fault: SFENCE.VMA more selectively.
Jul 9 2021, 2:12 PM · riscv
markj accepted D31118: riscv pmap_fault: SFENCE.VMA more selectively.
Jul 9 2021, 1:47 PM · riscv
freebsdphab-AX9_cmx.ietfng.org requested review of D31118: riscv pmap_fault: SFENCE.VMA more selectively.
Jul 9 2021, 1:30 PM · riscv

Jun 25 2021

pkubaj closed D30862: Add OPENMP for riscv64*.
Jun 25 2021, 2:24 PM · riscv
mhorne accepted D30862: Add OPENMP for riscv64*.
Jun 25 2021, 1:35 PM · riscv
pkubaj updated the diff for D30862: Add OPENMP for riscv64*.

Adding riscv64sf.

Jun 25 2021, 1:33 PM · riscv

Jun 24 2021

mhorne added inline comments to D30862: Add OPENMP for riscv64*.
Jun 24 2021, 7:08 PM · riscv
mhorne accepted D30862: Add OPENMP for riscv64*.

Thanks, this fell off my radar.

Jun 24 2021, 7:07 PM · riscv

Jun 22 2021

pkubaj requested review of D30862: Add OPENMP for riscv64*.
Jun 22 2021, 9:09 AM · riscv

Jun 4 2021

markj added a comment to D30550: RISC-V pmap: remove incorrect assertions in pmap_demote_l2_locked.

Thanks to @markj for the explanation; this is an incorrect fix.

Jun 4 2021, 6:25 PM · riscv

Jun 2 2021

freebsdphab-AX9_cmx.ietfng.org abandoned D30550: RISC-V pmap: remove incorrect assertions in pmap_demote_l2_locked.

Thanks to @markj for the explanation; this is an incorrect fix.

Jun 2 2021, 6:21 PM · riscv

May 30 2021

jrtc27 added a comment to D30550: RISC-V pmap: remove incorrect assertions in pmap_demote_l2_locked.

Yes, there is no way to detect what hardware does short of trying and seeing (the spec mandates all harts must always do dirty tracking, or all harts must never, so it's an easy test if you really want to). QEMU currently implements hardware dirty tracking, with no knob to turn it off. Depending on how it's configured, an FPGA implementation we use also does.

May 30 2021, 10:55 PM · riscv
markj added a comment to D30550: RISC-V pmap: remove incorrect assertions in pmap_demote_l2_locked.

So after a successful promotion, the 2MB mapping must either be writable and dirty, or read-only. That is what the removed assertion is checking, and it is wrong on riscv since pmap_promote_l2() doesn't handle this problem.

May 30 2021, 9:51 PM · riscv
markj added a comment to D30550: RISC-V pmap: remove incorrect assertions in pmap_demote_l2_locked.

The essential difference here is that riscv's pmap_promote_l2() assumes that PTE_D is always set by software, i.e., no hardware management of the dirty bit. We should possibly fix that instead.

May 30 2021, 9:49 PM · riscv
freebsdphab-AX9_cmx.ietfng.org added a comment to D30550: RISC-V pmap: remove incorrect assertions in pmap_demote_l2_locked.

Well, for whatever it's worth, the reproducer seems not to panic on amd64, which is a little surprising as I don't see any special handling for setting PG_M on !VPO_UNMANAGED, PG_RW, psind=1 pages in pmap_enter(), and I'd have thought the MI layers were doing the same thing on both.

May 30 2021, 4:00 PM · riscv
rwatson updated subscribers of D30550: RISC-V pmap: remove incorrect assertions in pmap_demote_l2_locked.
May 30 2021, 2:47 PM · riscv
jrtc27 added a comment to D30550: RISC-V pmap: remove incorrect assertions in pmap_demote_l2_locked.

Have you tried running this on arm64? Its pmap_demote_l2_locked has a similar:

KASSERT((oldl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) !=
    (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM),
    ("pmap_demote_l2: L2 entry is writeable but not dirty"));
May 30 2021, 2:20 PM · riscv
arichardson added a comment to D30550: RISC-V pmap: remove incorrect assertions in pmap_demote_l2_locked.

Can we include the test program as a regression test in tests/sys? No need to rewrite it in ATF, keeping it as a plain C executable seems fine to me.

May 30 2021, 2:17 PM · riscv
freebsdphab-AX9_cmx.ietfng.org requested review of D30550: RISC-V pmap: remove incorrect assertions in pmap_demote_l2_locked.
May 30 2021, 2:12 PM · riscv

Apr 27 2021

bdragon closed D30011: riscv: Remove old qemu compatibility code.
Apr 27 2021, 9:26 PM · riscv
mhorne accepted D30011: riscv: Remove old qemu compatibility code.
Apr 27 2021, 5:44 PM · riscv
jrtc27 accepted D30011: riscv: Remove old qemu compatibility code.

Seems fine to me

Apr 27 2021, 4:49 PM · riscv
bdragon updated the summary of D30011: riscv: Remove old qemu compatibility code.
Apr 27 2021, 4:23 PM · riscv
bdragon requested review of D30011: riscv: Remove old qemu compatibility code.
Apr 27 2021, 4:22 PM · riscv

Mar 25 2021

markj removed a member for riscv: markj.
Mar 25 2021, 2:10 PM

Mar 3 2021

herbert_mailbox.org added a watcher for riscv: herbert_mailbox.org.
Mar 3 2021, 2:31 PM

Jan 19 2021

danq1222_gmail.com added a watcher for riscv: danq1222_gmail.com.
Jan 19 2021, 12:08 AM

Oct 17 2020

mhorne closed D26607: riscv pmap: zero reserved pte bits in ppn for l2 leaf entries, too.
Oct 17 2020, 5:31 PM · riscv

Oct 13 2020

nick abandoned D23878: RISCV: SiFive specific platform.
Oct 13 2020, 5:37 AM · riscv
nick closed D23877: RISCV Platform Specific Code.
Oct 13 2020, 5:37 AM · riscv
nick closed D23879: RISCV: PLATFORM_DEFAULT implementation.
Oct 13 2020, 5:36 AM · riscv

Oct 9 2020

mhorne accepted D26607: riscv pmap: zero reserved pte bits in ppn for l2 leaf entries, too.
Oct 9 2020, 1:06 PM · riscv
kp accepted D26607: riscv pmap: zero reserved pte bits in ppn for l2 leaf entries, too.
Oct 9 2020, 9:46 AM · riscv

Oct 8 2020

freebsdphab-AX9_cmx.ietfng.org updated the diff for D26607: riscv pmap: zero reserved pte bits in ppn for l2 leaf entries, too.

Renamed macro as per mhorne's feedback

Oct 8 2020, 11:37 PM · riscv

Sep 30 2020

mhorne added inline comments to D26607: riscv pmap: zero reserved pte bits in ppn for l2 leaf entries, too.
Sep 30 2020, 1:11 PM · riscv
freebsdphab-AX9_cmx.ietfng.org requested review of D26607: riscv pmap: zero reserved pte bits in ppn for l2 leaf entries, too.
Sep 30 2020, 12:35 PM · riscv

Aug 18 2020

nick closed D26092: riscv: Use global mimpid in identify_cpu().
Aug 18 2020, 4:51 PM · riscv
kp added a comment to D26092: riscv: Use global mimpid in identify_cpu().

Approved by: philip, kp (mentors)

Aug 18 2020, 8:47 AM · riscv
kp accepted D26092: riscv: Use global mimpid in identify_cpu().
Aug 18 2020, 8:46 AM · riscv
philip accepted D26092: riscv: Use global mimpid in identify_cpu().

Looks good to me.

Aug 18 2020, 1:49 AM · riscv

Aug 17 2020

nick requested review of D26092: riscv: Use global mimpid in identify_cpu().
Aug 17 2020, 9:20 PM · riscv

Jul 29 2020

jrtc27 removed a watcher for riscv: jrtc27.
Jul 29 2020, 3:24 AM
jrtc27 added a member for riscv: jrtc27.
Jul 29 2020, 3:23 AM

Jul 19 2020

mhorne closed D25544: riscv: look for bootargs in FDT.
Jul 19 2020, 11:35 PM · riscv

Jul 17 2020

mhorne accepted D25544: riscv: look for bootargs in FDT.

Thanks, looks good to me, and will be quite useful! I gave it a quick test as well.

Jul 17 2020, 2:06 PM · riscv