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sys/arm64/arm64/exec_machdep.c
Show First 20 Lines • Show All 235 Lines • ▼ Show 20 Lines | for (i = 0; i < DBG_BRP_MAX; i++) { | ||||
/* | /* | ||||
* Some control fields are ignored, and other bits reserved. | * Some control fields are ignored, and other bits reserved. | ||||
* Only unlinked, address-matching breakpoints are supported. | * Only unlinked, address-matching breakpoints are supported. | ||||
* | * | ||||
* XXX: fields that appear unvalidated, such as BAS, have | * XXX: fields that appear unvalidated, such as BAS, have | ||||
* constrained undefined behaviour. If the user mis-programs | * constrained undefined behaviour. If the user mis-programs | ||||
* these, there is no risk to the system. | * these, there is no risk to the system. | ||||
*/ | */ | ||||
ctrl &= DBG_BCR_EN | DBG_BCR_PMC | DBG_BCR_BAS; | ctrl &= DBGBCR_EN | DBGBCR_PMC | DBGBCR_BAS; | ||||
if ((ctrl & DBG_BCR_EN) != 0) { | if ((ctrl & DBGBCR_EN) != 0) { | ||||
/* Only target EL0. */ | /* Only target EL0. */ | ||||
if ((ctrl & DBG_BCR_PMC) != DBG_BCR_PMC_EL0) | if ((ctrl & DBGBCR_PMC) != DBGBCR_PMC_EL0) | ||||
return (EINVAL); | return (EINVAL); | ||||
monitor->dbg_enable_count++; | monitor->dbg_enable_count++; | ||||
} | } | ||||
monitor->dbg_bvr[i] = addr; | monitor->dbg_bvr[i] = addr; | ||||
monitor->dbg_bcr[i] = ctrl; | monitor->dbg_bcr[i] = ctrl; | ||||
} | } | ||||
for (i = 0; i < DBG_WRP_MAX; i++) { | for (i = 0; i < DBG_WRP_MAX; i++) { | ||||
addr = regs->db_watchregs[i].dbw_addr; | addr = regs->db_watchregs[i].dbw_addr; | ||||
ctrl = regs->db_watchregs[i].dbw_ctrl; | ctrl = regs->db_watchregs[i].dbw_ctrl; | ||||
/* | /* | ||||
* Don't let the user set a watchpoint on a kernel or | * Don't let the user set a watchpoint on a kernel or | ||||
* non-canonical user address. | * non-canonical user address. | ||||
*/ | */ | ||||
if (addr >= VM_MAXUSER_ADDRESS) | if (addr >= VM_MAXUSER_ADDRESS) | ||||
return (EINVAL); | return (EINVAL); | ||||
/* | /* | ||||
* Some control fields are ignored, and other bits reserved. | * Some control fields are ignored, and other bits reserved. | ||||
* Only unlinked watchpoints are supported. | * Only unlinked watchpoints are supported. | ||||
*/ | */ | ||||
ctrl &= DBG_WCR_EN | DBG_WCR_PAC | DBG_WCR_LSC | DBG_WCR_BAS | | ctrl &= DBGWCR_EN | DBGWCR_PAC | DBGWCR_LSC | DBGWCR_BAS | | ||||
DBG_WCR_MASK; | DBGWCR_MASK; | ||||
if ((ctrl & DBG_WCR_EN) != 0) { | if ((ctrl & DBGWCR_EN) != 0) { | ||||
/* Only target EL0. */ | /* Only target EL0. */ | ||||
if ((ctrl & DBG_WCR_PAC) != DBG_WCR_PAC_EL0) | if ((ctrl & DBGWCR_PAC) != DBGWCR_PAC_EL0) | ||||
return (EINVAL); | return (EINVAL); | ||||
/* Must set at least one of the load/store bits. */ | /* Must set at least one of the load/store bits. */ | ||||
if ((ctrl & DBG_WCR_LSC) == 0) | if ((ctrl & DBGWCR_LSC) == 0) | ||||
return (EINVAL); | return (EINVAL); | ||||
/* | /* | ||||
* When specifying the address range with BAS, the MASK | * When specifying the address range with BAS, the MASK | ||||
* field must be zero. | * field must be zero. | ||||
*/ | */ | ||||
if ((ctrl & DBG_WCR_BAS) != DBG_WCR_BAS_MASK && | if ((ctrl & DBGWCR_BAS) != DBGWCR_BAS && | ||||
(ctrl & DBG_WCR_MASK) != 0) | (ctrl & DBGWCR_MASK) != 0) | ||||
return (EINVAL); | return (EINVAL); | ||||
monitor->dbg_enable_count++; | monitor->dbg_enable_count++; | ||||
} | } | ||||
monitor->dbg_wvr[i] = addr; | monitor->dbg_wvr[i] = addr; | ||||
monitor->dbg_wcr[i] = ctrl; | monitor->dbg_wcr[i] = ctrl; | ||||
} | } | ||||
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