Differential D26209 Diff 100964 sys/dev/pci/pcireg.h

Changeset View

Standalone View

sys/dev/pci/pcireg.h

	Show First 20 Lines • Show All 1,092 Lines • ▼ Show 20 Lines
	#define PCIM_OSC_SUPPORT_SEG_GROUP 0x08 /* PCI Segment Groups supported */			#define PCIM_OSC_SUPPORT_SEG_GROUP 0x08 /* PCI Segment Groups supported */
	#define PCIM_OSC_SUPPORT_MSI 0x10 /* MSI signalling supported */			#define PCIM_OSC_SUPPORT_MSI 0x10 /* MSI signalling supported */
	#define PCI_OSC_CTL 2			#define PCI_OSC_CTL 2
	#define PCIM_OSC_CTL_PCIE_HP 0x01 /* PCIe Native Hot Plug */			#define PCIM_OSC_CTL_PCIE_HP 0x01 /* PCIe Native Hot Plug */
	#define PCIM_OSC_CTL_SHPC_HP 0x02 /* SHPC Native Hot Plug */			#define PCIM_OSC_CTL_SHPC_HP 0x02 /* SHPC Native Hot Plug */
	#define PCIM_OSC_CTL_PCIE_PME 0x04 /* PCIe Native Power Mgt Events */			#define PCIM_OSC_CTL_PCIE_PME 0x04 /* PCIe Native Power Mgt Events */
	#define PCIM_OSC_CTL_PCIE_AER 0x08 /* PCIe Advanced Error Reporting */			#define PCIM_OSC_CTL_PCIE_AER 0x08 /* PCIe Advanced Error Reporting */
	#define PCIM_OSC_CTL_PCIE_CAP_STRUCT 0x10 /* Various Capability Structures */			#define PCIM_OSC_CTL_PCIE_CAP_STRUCT 0x10 /* Various Capability Structures */

				/*
				* Intel graphics device definitions
				*/
				#define PCIR_BDSM 0x5C /* Base of Data Stolen Memory register */
				#define PCIR_ASLS_CTL 0xFC /* Opregion start address register */

				/*
				* PCI Vendors
				grehanUnsubmitted Done Inline Actions Is this the same as the value configured through BIOS ("DVMT Pre-Allocated" from the intro) ? Any value in having this configurable ? grehan: Is this the same as the value configured through BIOS ("DVMT Pre-Allocated" from the intro) ?
				corvinkAuthorUnsubmitted Done Inline Actions Yes, that's the "DVMT Pre-Allocated" setting. My updated revision detects this value. corvink: Yes, that's the "DVMT Pre-Allocated" setting. My updated revision detects this value.
				*/
				grehanUnsubmitted Done Inline Actions Does this value have to be fixed ? (ie.. for a 1:1 guest/host mapping) grehan: Does this value have to be fixed ? (ie.. for a 1:1 guest/host mapping)
				corvinkAuthorUnsubmitted Done Inline Actions Normally this value is set to TOLUD - GSM_SIZE by BIOS. (TOLUD == Top of Low Usable DRAM) So, I think for bhyve it should be lowmem_limit - GSM_SIZE. This address is no MMIO-Space, which means that vm_map_pptdev_mmio fails. I don't know how to create such a mapping. The current implementation maps GPU_GSM_GPA into the PCI-Space (0xC0000000 - 0xE0000000) and works fine. Don't know if it's neccessary to set it to lowmem_limit - GSM_SIZE. corvink: Normally this value is set to //TOLUD - GSM_SIZE// by BIOS. (TOLUD == Top of Low Usable DRAM)…
				#define PCI_VENDOR_INTEL 0x8086