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Differential D33390 Diff 99861 sys/amd64/amd64/fpu.c

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sys/amd64/amd64/fpu.c

Show First 20 Lines • Show All 478 Lines • ▼ Show 20 Lines xstate_bv = (uint64_t *)((char *)(fpu_initialstate + 1) +
offsetof(struct xstate_hdr, xstate_bv)); offsetof(struct xstate_hdr, xstate_bv));
*xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; *xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
/* x87 state */ /* x87 state */
xsave_area_desc[0].offset = 0; xsave_area_desc[0].offset = 0;
xsave_area_desc[0].size = 160; xsave_area_desc[0].size = 160;
/* XMM */ /* XMM */
xsave_area_desc[1].offset = 160; xsave_area_desc[1].offset = 160;
xsave_area_desc[1].size = 288 - 160; xsave_area_desc[1].size = 416 - 160;
emasteUnsubmitted
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Indeed, 16 128-bit XMM registers occupy 256 bytes.

I wonder if xsave_area_desc[1].size = 256 would be more clear here.

emaste: Indeed, 16 128-bit XMM registers occupy 256 bytes. I wonder if `xsave_area_desc[1].size = 256`…
mpratt_google.comUnsubmitted
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Alternatively/additionally, a reference to the documentation source for these values would be helpful. e.g., Intel SDM Vol 1, Ch. 13.4.1 "Legacy Region of an XSAVE Area", Table 13-1 "Format of the Legacy Region of an XSAVE Area" shows these sizes and offsets.

mpratt_google.com: Alternatively/additionally, a reference to the documentation source for these values would be…
emasteUnsubmitted
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Thanks, a comment like that is in the tree now.

emaste: Thanks, a comment like that is in the tree now.
for (i = 2; i < max_ext_n; i++) { for (i = 2; i < max_ext_n; i++) {
cpuid_count(0xd, i, cp); cpuid_count(0xd, i, cp);
xsave_area_desc[i].offset = cp[1]; xsave_area_desc[i].offset = cp[1];
xsave_area_desc[i].size = cp[0]; xsave_area_desc[i].size = cp[0];
} }
} }
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