Differential D33118 Diff 99010 usr.sbin/bhyve/pci_emul.c

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usr.sbin/bhyve/pci_emul.c

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uint64_t		uint64_t
pci_ecfg_base(void)		pci_ecfg_base(void)
{		{

return (PCI_EMUL_ECFG_BASE);		return (PCI_EMUL_ECFG_BASE);
}		}

#define BUSIO_ROUNDUP 32		#define BUSIO_ROUNDUP 32
#define BUSMEM_ROUNDUP (1024 * 1024)		#define BUSMEM32_ROUNDUP (1024 * 1024)
		#define BUSMEM64_ROUNDUP (512 * 1024 * 1024)

int		int
init_pci(struct vmctx *ctx)		init_pci(struct vmctx *ctx)
{		{
char node_name[sizeof("pci.XXX.XX.X")];		char node_name[sizeof("pci.XXX.XX.X")];
struct mem_range mr;		struct mem_range mr;
struct pci_devemu *pde;		struct pci_devemu *pde;
struct businfo *bi;		struct businfo *bi;
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines	for (bus = 0; bus < MAXBUSES; bus++) {
* Add some slop to the I/O and memory resources decoded by		* Add some slop to the I/O and memory resources decoded by
* this bus to give a guest some flexibility if it wants to		* this bus to give a guest some flexibility if it wants to
* reprogram the BARs.		* reprogram the BARs.
*/		*/
pci_emul_iobase += BUSIO_ROUNDUP;		pci_emul_iobase += BUSIO_ROUNDUP;
pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP);		pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP);
bi->iolimit = pci_emul_iobase;		bi->iolimit = pci_emul_iobase;

pci_emul_membase32 += BUSMEM_ROUNDUP;		pci_emul_membase32 += BUSMEM32_ROUNDUP;
pci_emul_membase32 = roundup2(pci_emul_membase32,		pci_emul_membase32 = roundup2(pci_emul_membase32,
BUSMEM_ROUNDUP);		BUSMEM32_ROUNDUP);
bi->memlimit32 = pci_emul_membase32;		bi->memlimit32 = pci_emul_membase32;

pci_emul_membase64 += BUSMEM_ROUNDUP;		pci_emul_membase64 += BUSMEM64_ROUNDUP;
pci_emul_membase64 = roundup2(pci_emul_membase64,		pci_emul_membase64 = roundup2(pci_emul_membase64,
BUSMEM_ROUNDUP);		BUSMEM64_ROUNDUP);
bi->memlimit64 = pci_emul_membase64;		bi->memlimit64 = pci_emul_membase64;
}		}

/*		/*
* PCI backends are initialized before routing INTx interrupts		* PCI backends are initialized before routing INTx interrupts
* so that LPC devices are able to reserve ISA IRQs before		* so that LPC devices are able to reserve ISA IRQs before
* routing PIRQ pins.		* routing PIRQ pins.
*/		*/
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