Differential D30888 Diff 98893 sys/dev/ice/ice_controlq.c

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sys/dev/ice/ice_controlq.c

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sq_send_command_error:		sq_send_command_error:
return status;		return status;
}		}

/**		/**
* ice_sq_send_cmd - send command to Control Queue (ATQ)		* ice_sq_send_cmd - send command to Control Queue (ATQ)
* @hw: pointer to the HW struct		* @hw: pointer to the HW struct
* @cq: pointer to the specific Control queue		* @cq: pointer to the specific Control queue
* @desc: prefilled descriptor describing the command (non DMA mem)		* @desc: prefilled descriptor describing the command
* @buf: buffer to use for indirect commands (or NULL for direct commands)		* @buf: buffer to use for indirect commands (or NULL for direct commands)
* @buf_size: size of buffer for indirect commands (or 0 for direct commands)		* @buf_size: size of buffer for indirect commands (or 0 for direct commands)
* @cd: pointer to command details structure		* @cd: pointer to command details structure
*		*
* This is the main send command routine for the ATQ. It runs the queue,		* This is the main send command routine for the ATQ. It runs the queue,
* cleans the queue, etc.		* cleans the queue, etc.
*/		*/
enum ice_status		enum ice_status
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* the contents through e. It can also return how many events are		* the contents through e. It can also return how many events are
* left to process through 'pending'.		* left to process through 'pending'.
*/		*/
enum ice_status		enum ice_status
ice_clean_rq_elem(struct ice_hw hw, struct ice_ctl_q_info cq,		ice_clean_rq_elem(struct ice_hw hw, struct ice_ctl_q_info cq,
struct ice_rq_event_info e, u16 pending)		struct ice_rq_event_info e, u16 pending)
{		{
u16 ntc = cq->rq.next_to_clean;		u16 ntc = cq->rq.next_to_clean;
		enum ice_aq_err rq_last_status;
enum ice_status ret_code = ICE_SUCCESS;		enum ice_status ret_code = ICE_SUCCESS;
struct ice_aq_desc *desc;		struct ice_aq_desc *desc;
struct ice_dma_mem *bi;		struct ice_dma_mem *bi;
u16 desc_idx;		u16 desc_idx;
u16 datalen;		u16 datalen;
u16 flags;		u16 flags;
u16 ntu;		u16 ntu;

Show All 17 Lines	if (ntu == ntc) {
ret_code = ICE_ERR_AQ_NO_WORK;		ret_code = ICE_ERR_AQ_NO_WORK;
goto clean_rq_elem_out;		goto clean_rq_elem_out;
}		}

/* now clean the next descriptor */		/* now clean the next descriptor */
desc = ICE_CTL_Q_DESC(cq->rq, ntc);		desc = ICE_CTL_Q_DESC(cq->rq, ntc);
desc_idx = ntc;		desc_idx = ntc;

cq->rq_last_status = (enum ice_aq_err)LE16_TO_CPU(desc->retval);		rq_last_status = (enum ice_aq_err)LE16_TO_CPU(desc->retval);
flags = LE16_TO_CPU(desc->flags);		flags = LE16_TO_CPU(desc->flags);
if (flags & ICE_AQ_FLAG_ERR) {		if (flags & ICE_AQ_FLAG_ERR) {
ret_code = ICE_ERR_AQ_ERROR;		ret_code = ICE_ERR_AQ_ERROR;
ice_debug(hw, ICE_DBG_AQ_MSG, "Control Receive Queue Event 0x%04X received with error 0x%X\n",		ice_debug(hw, ICE_DBG_AQ_MSG, "Control Receive Queue Event 0x%04X received with error 0x%X\n",
LE16_TO_CPU(desc->opcode),		LE16_TO_CPU(desc->opcode), rq_last_status);
cq->rq_last_status);
}		}
ice_memcpy(&e->desc, desc, sizeof(e->desc), ICE_DMA_TO_NONDMA);		ice_memcpy(&e->desc, desc, sizeof(e->desc), ICE_DMA_TO_NONDMA);
datalen = LE16_TO_CPU(desc->datalen);		datalen = LE16_TO_CPU(desc->datalen);
e->msg_len = MIN_T(u16, datalen, e->buf_len);		e->msg_len = MIN_T(u16, datalen, e->buf_len);
if (e->msg_buf && e->msg_len)		if (e->msg_buf && e->msg_len)
ice_memcpy(e->msg_buf, cq->rq.r.rq_bi[desc_idx].va,		ice_memcpy(e->msg_buf, cq->rq.r.rq_bi[desc_idx].va,
e->msg_len, ICE_DMA_TO_NONDMA);		e->msg_len, ICE_DMA_TO_NONDMA);

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