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usr.sbin/bhyve/pci_emul.c
Show First 20 Lines • Show All 701 Lines • ▼ Show 20 Lines | if (baseptr != NULL) { | ||||
error = pci_emul_alloc_resource(baseptr, limit, size, &addr); | error = pci_emul_alloc_resource(baseptr, limit, size, &addr); | ||||
if (error != 0) | if (error != 0) | ||||
return (error); | return (error); | ||||
} | } | ||||
pdi->pi_bar[idx].type = type; | pdi->pi_bar[idx].type = type; | ||||
pdi->pi_bar[idx].addr = addr; | pdi->pi_bar[idx].addr = addr; | ||||
pdi->pi_bar[idx].size = size; | pdi->pi_bar[idx].size = size; | ||||
/* | |||||
* passthru devices are using same lobits as physical device they set | |||||
* this property | |||||
*/ | |||||
if (pdi->pi_bar[idx].lobits != 0) { | |||||
lobits = pdi->pi_bar[idx].lobits; | |||||
} else { | |||||
pdi->pi_bar[idx].lobits = lobits; | |||||
} | |||||
/* Initialize the BAR register in config space */ | /* Initialize the BAR register in config space */ | ||||
bar = (addr & mask) | lobits; | bar = (addr & mask) | lobits; | ||||
pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); | pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); | ||||
if (type == PCIBAR_MEM64) { | if (type == PCIBAR_MEM64) { | ||||
assert(idx + 1 <= PCI_BARMAX); | assert(idx + 1 <= PCI_BARMAX); | ||||
pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; | pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; | ||||
▲ Show 20 Lines • Show All 1,223 Lines • ▼ Show 20 Lines | if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) { | ||||
mask = ~(pi->pi_bar[idx].size - 1); | mask = ~(pi->pi_bar[idx].size - 1); | ||||
switch (pi->pi_bar[idx].type) { | switch (pi->pi_bar[idx].type) { | ||||
case PCIBAR_NONE: | case PCIBAR_NONE: | ||||
pi->pi_bar[idx].addr = bar = 0; | pi->pi_bar[idx].addr = bar = 0; | ||||
break; | break; | ||||
case PCIBAR_IO: | case PCIBAR_IO: | ||||
addr = *eax & mask; | addr = *eax & mask; | ||||
addr &= 0xffff; | addr &= 0xffff; | ||||
bar = addr | PCIM_BAR_IO_SPACE; | bar = addr | pi->pi_bar[idx].lobits; | ||||
/* | /* | ||||
* Register the new BAR value for interception | * Register the new BAR value for interception | ||||
*/ | */ | ||||
if (addr != pi->pi_bar[idx].addr) { | if (addr != pi->pi_bar[idx].addr) { | ||||
update_bar_address(pi, addr, idx, | update_bar_address(pi, addr, idx, | ||||
PCIBAR_IO); | PCIBAR_IO); | ||||
} | } | ||||
break; | break; | ||||
case PCIBAR_MEM32: | case PCIBAR_MEM32: | ||||
addr = bar = *eax & mask; | addr = bar = *eax & mask; | ||||
bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; | bar |= pi->pi_bar[idx].lobits; | ||||
if (addr != pi->pi_bar[idx].addr) { | if (addr != pi->pi_bar[idx].addr) { | ||||
update_bar_address(pi, addr, idx, | update_bar_address(pi, addr, idx, | ||||
PCIBAR_MEM32); | PCIBAR_MEM32); | ||||
} | } | ||||
break; | break; | ||||
case PCIBAR_MEM64: | case PCIBAR_MEM64: | ||||
addr = bar = *eax & mask; | addr = bar = *eax & mask; | ||||
bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | | bar |= pi->pi_bar[idx].lobits; | ||||
PCIM_BAR_MEM_PREFETCH; | |||||
if (addr != (uint32_t)pi->pi_bar[idx].addr) { | if (addr != (uint32_t)pi->pi_bar[idx].addr) { | ||||
update_bar_address(pi, addr, idx, | update_bar_address(pi, addr, idx, | ||||
PCIBAR_MEM64); | PCIBAR_MEM64); | ||||
} | } | ||||
break; | break; | ||||
case PCIBAR_MEMHI64: | case PCIBAR_MEMHI64: | ||||
mask = ~(pi->pi_bar[idx - 1].size - 1); | mask = ~(pi->pi_bar[idx - 1].size - 1); | ||||
addr = ((uint64_t)*eax << 32) & mask; | addr = ((uint64_t)*eax << 32) & mask; | ||||
▲ Show 20 Lines • Show All 450 Lines • Show Last 20 Lines |