Changeset View
Changeset View
Standalone View
Standalone View
sys/dev/pccbb/pccbb_pci.c
Show First 20 Lines • Show All 273 Lines • ▼ Show 20 Lines | for (i = 0; i < 256; i += 4) { | ||||
printf("0x%08x ", pci_read_config(dev, i, 4)); | printf("0x%08x ", pci_read_config(dev, i, 4)); | ||||
} | } | ||||
printf("\n"); | printf("\n"); | ||||
} | } | ||||
static int | static int | ||||
cbb_pci_attach(device_t brdev) | cbb_pci_attach(device_t brdev) | ||||
{ | { | ||||
#if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) | #if !defined(PCI_RES_BUS) | ||||
static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */ | static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */ | ||||
uint32_t pribus; | uint32_t pribus; | ||||
#endif | #endif | ||||
struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); | struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); | ||||
struct sysctl_ctx_list *sctx; | struct sysctl_ctx_list *sctx; | ||||
struct sysctl_oid *soid; | struct sysctl_oid *soid; | ||||
int rid; | int rid; | ||||
device_t parent; | device_t parent; | ||||
parent = device_get_parent(brdev); | parent = device_get_parent(brdev); | ||||
mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); | mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); | ||||
sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); | sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); | ||||
sc->dev = brdev; | sc->dev = brdev; | ||||
sc->cbdev = NULL; | sc->cbdev = NULL; | ||||
sc->domain = pci_get_domain(brdev); | sc->domain = pci_get_domain(brdev); | ||||
sc->pribus = pcib_get_bus(parent); | sc->pribus = pcib_get_bus(parent); | ||||
#if defined(NEW_PCIB) && defined(PCI_RES_BUS) | #if defined(PCI_RES_BUS) | ||||
pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); | pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); | ||||
pcib_setup_secbus(brdev, &sc->bus, 1); | pcib_setup_secbus(brdev, &sc->bus, 1); | ||||
#else | #else | ||||
sc->bus.sec = pci_read_config(brdev, PCIR_SECBUS_2, 1); | sc->bus.sec = pci_read_config(brdev, PCIR_SECBUS_2, 1); | ||||
sc->bus.sub = pci_read_config(brdev, PCIR_SUBBUS_2, 1); | sc->bus.sub = pci_read_config(brdev, PCIR_SUBBUS_2, 1); | ||||
#endif | #endif | ||||
SLIST_INIT(&sc->rl); | SLIST_INIT(&sc->rl); | ||||
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines | #if 0 | ||||
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "premem", | SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "premem", | ||||
CTLFLAG_RD, &sc->subbus, 0, "Prefetch memory window open"); | CTLFLAG_RD, &sc->subbus, 0, "Prefetch memory window open"); | ||||
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io1", | SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io1", | ||||
CTLFLAG_RD, &sc->subbus, 0, "io range 1 open"); | CTLFLAG_RD, &sc->subbus, 0, "io range 1 open"); | ||||
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io2", | SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io2", | ||||
CTLFLAG_RD, &sc->subbus, 0, "io range 2 open"); | CTLFLAG_RD, &sc->subbus, 0, "io range 2 open"); | ||||
#endif | #endif | ||||
#if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) | #if !defined(PCI_RES_BUS) | ||||
/* | /* | ||||
* This is a gross hack. We should be scanning the entire pci | * This is a gross hack. We should be scanning the entire pci | ||||
* tree, assigning bus numbers in a way such that we (1) can | * tree, assigning bus numbers in a way such that we (1) can | ||||
* reserve 1 extra bus just in case and (2) all sub buses | * reserve 1 extra bus just in case and (2) all sub buses | ||||
* are in an appropriate range. | * are in an appropriate range. | ||||
*/ | */ | ||||
DEVPRINTF((brdev, "Secondary bus is %d\n", sc->bus.sec)); | DEVPRINTF((brdev, "Secondary bus is %d\n", sc->bus.sec)); | ||||
pribus = pci_read_config(brdev, PCIR_PRIBUS_2, 1); | pribus = pci_read_config(brdev, PCIR_PRIBUS_2, 1); | ||||
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines | err: | ||||
} | } | ||||
mtx_destroy(&sc->mtx); | mtx_destroy(&sc->mtx); | ||||
return (ENOMEM); | return (ENOMEM); | ||||
} | } | ||||
static int | static int | ||||
cbb_pci_detach(device_t brdev) | cbb_pci_detach(device_t brdev) | ||||
{ | { | ||||
#if defined(NEW_PCIB) && defined(PCI_RES_BUS) | #if defined(PCI_RES_BUS) | ||||
struct cbb_softc *sc = device_get_softc(brdev); | struct cbb_softc *sc = device_get_softc(brdev); | ||||
#endif | #endif | ||||
int error; | int error; | ||||
error = cbb_detach(brdev); | error = cbb_detach(brdev); | ||||
#if defined(NEW_PCIB) && defined(PCI_RES_BUS) | #if defined(PCI_RES_BUS) | ||||
if (error == 0) | if (error == 0) | ||||
pcib_free_secbus(brdev, &sc->bus); | pcib_free_secbus(brdev, &sc->bus); | ||||
#endif | #endif | ||||
return (error); | return (error); | ||||
} | } | ||||
static void | static void | ||||
cbb_chipinit(struct cbb_softc *sc) | cbb_chipinit(struct cbb_softc *sc) | ||||
▲ Show 20 Lines • Show All 335 Lines • ▼ Show 20 Lines | #undef DELTA | ||||
*/ | */ | ||||
if (sockevent & CBB_SOCKET_EVENT_CSTS) | if (sockevent & CBB_SOCKET_EVENT_CSTS) | ||||
cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_CSTS); | cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_CSTS); | ||||
retval = FILTER_HANDLED; | retval = FILTER_HANDLED; | ||||
} | } | ||||
return retval; | return retval; | ||||
} | } | ||||
#if defined(NEW_PCIB) && defined(PCI_RES_BUS) | #if defined(PCI_RES_BUS) | ||||
static struct resource * | static struct resource * | ||||
cbb_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, | cbb_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, | ||||
rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) | rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) | ||||
{ | { | ||||
struct cbb_softc *sc; | struct cbb_softc *sc; | ||||
sc = device_get_softc(bus); | sc = device_get_softc(bus); | ||||
if (type == PCI_RES_BUS) | if (type == PCI_RES_BUS) | ||||
▲ Show 20 Lines • Show All 128 Lines • ▼ Show 20 Lines | static device_method_t cbb_methods[] = { | ||||
DEVMETHOD(device_detach, cbb_pci_detach), | DEVMETHOD(device_detach, cbb_pci_detach), | ||||
DEVMETHOD(device_shutdown, cbb_pci_shutdown), | DEVMETHOD(device_shutdown, cbb_pci_shutdown), | ||||
DEVMETHOD(device_suspend, cbb_pci_suspend), | DEVMETHOD(device_suspend, cbb_pci_suspend), | ||||
DEVMETHOD(device_resume, cbb_pci_resume), | DEVMETHOD(device_resume, cbb_pci_resume), | ||||
/* bus methods */ | /* bus methods */ | ||||
DEVMETHOD(bus_read_ivar, cbb_read_ivar), | DEVMETHOD(bus_read_ivar, cbb_read_ivar), | ||||
DEVMETHOD(bus_write_ivar, cbb_write_ivar), | DEVMETHOD(bus_write_ivar, cbb_write_ivar), | ||||
#if defined(NEW_PCIB) && defined(PCI_RES_BUS) | #if defined(PCI_RES_BUS) | ||||
DEVMETHOD(bus_alloc_resource, cbb_pci_alloc_resource), | DEVMETHOD(bus_alloc_resource, cbb_pci_alloc_resource), | ||||
DEVMETHOD(bus_adjust_resource, cbb_pci_adjust_resource), | DEVMETHOD(bus_adjust_resource, cbb_pci_adjust_resource), | ||||
DEVMETHOD(bus_release_resource, cbb_pci_release_resource), | DEVMETHOD(bus_release_resource, cbb_pci_release_resource), | ||||
#else | #else | ||||
DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), | DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), | ||||
DEVMETHOD(bus_release_resource, cbb_release_resource), | DEVMETHOD(bus_release_resource, cbb_release_resource), | ||||
#endif | #endif | ||||
DEVMETHOD(bus_activate_resource, cbb_activate_resource), | DEVMETHOD(bus_activate_resource, cbb_activate_resource), | ||||
Show All 34 Lines |