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sys/dev/igc/igc_phy.c
Show All 20 Lines | |||||
{ | { | ||||
struct igc_phy_info *phy = &hw->phy; | struct igc_phy_info *phy = &hw->phy; | ||||
DEBUGFUNC("igc_init_phy_ops_generic"); | DEBUGFUNC("igc_init_phy_ops_generic"); | ||||
/* Initialize function pointers */ | /* Initialize function pointers */ | ||||
phy->ops.init_params = igc_null_ops_generic; | phy->ops.init_params = igc_null_ops_generic; | ||||
phy->ops.acquire = igc_null_ops_generic; | phy->ops.acquire = igc_null_ops_generic; | ||||
phy->ops.check_reset_block = igc_null_ops_generic; | phy->ops.check_reset_block = igc_null_ops_generic; | ||||
phy->ops.commit = igc_null_ops_generic; | |||||
phy->ops.force_speed_duplex = igc_null_ops_generic; | phy->ops.force_speed_duplex = igc_null_ops_generic; | ||||
phy->ops.get_info = igc_null_ops_generic; | phy->ops.get_info = igc_null_ops_generic; | ||||
phy->ops.set_page = igc_null_set_page; | phy->ops.set_page = igc_null_set_page; | ||||
phy->ops.read_reg = igc_null_read_reg; | phy->ops.read_reg = igc_null_read_reg; | ||||
phy->ops.read_reg_locked = igc_null_read_reg; | phy->ops.read_reg_locked = igc_null_read_reg; | ||||
phy->ops.read_reg_page = igc_null_read_reg; | phy->ops.read_reg_page = igc_null_read_reg; | ||||
phy->ops.release = igc_null_phy_generic; | phy->ops.release = igc_null_phy_generic; | ||||
phy->ops.reset = igc_null_ops_generic; | phy->ops.reset = igc_null_ops_generic; | ||||
▲ Show 20 Lines • Show All 104 Lines • ▼ Show 20 Lines | s32 igc_get_phy_id(struct igc_hw *hw) | ||||
if (!phy->ops.read_reg) | if (!phy->ops.read_reg) | ||||
return IGC_SUCCESS; | return IGC_SUCCESS; | ||||
ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); | ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); | ||||
if (ret_val) | if (ret_val) | ||||
return ret_val; | return ret_val; | ||||
phy->id = (u32)(phy_id << 16); | phy->id = (u32)(phy_id << 16); | ||||
usec_delay(20); | usec_delay(200); | ||||
ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); | ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); | ||||
if (ret_val) | if (ret_val) | ||||
return ret_val; | return ret_val; | ||||
phy->id |= (u32)(phy_id & PHY_REVISION_MASK); | phy->id |= (u32)(phy_id & PHY_REVISION_MASK); | ||||
phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | ||||
return IGC_SUCCESS; | return IGC_SUCCESS; | ||||
} | } | ||||
/** | /** | ||||
* igc_read_phy_reg_mdic - Read MDI control register | * igc_read_phy_reg_mdic - Read MDI control register | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @offset: register offset to be read | * @offset: register offset to be read | ||||
* @data: pointer to the read data | * @data: pointer to the read data | ||||
▲ Show 20 Lines • Show All 142 Lines • ▼ Show 20 Lines | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { | ||||
ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, | ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, | ||||
&mii_1000t_ctrl_reg); | &mii_1000t_ctrl_reg); | ||||
if (ret_val) | if (ret_val) | ||||
return ret_val; | return ret_val; | ||||
} | } | ||||
if ((phy->autoneg_mask & ADVERTISE_2500_FULL) && | if ((phy->autoneg_mask & ADVERTISE_2500_FULL) && | ||||
hw->phy.id == I225_I_PHY_ID) { | hw->phy.id == I225_I_PHY_ID) { | ||||
/* Read the MULTI GBT AN Control Register - reg 7.32 */ | /* Read the MULTI GBT AN Control Register - reg 7.32 */ | ||||
ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK << | ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK << | ||||
MMD_DEVADDR_SHIFT) | | MMD_DEVADDR_SHIFT) | | ||||
ANEG_MULTIGBT_AN_CTRL, | ANEG_MULTIGBT_AN_CTRL, | ||||
&aneg_multigbt_an_ctrl); | &aneg_multigbt_an_ctrl); | ||||
if (ret_val) | if (ret_val) | ||||
return ret_val; | return ret_val; | ||||
} | } | ||||
▲ Show 20 Lines • Show All 512 Lines • ▼ Show 20 Lines | if (phy_status & MII_SR_LINK_STATUS) | ||||
break; | break; | ||||
if (usec_interval >= 1000) | if (usec_interval >= 1000) | ||||
msec_delay(usec_interval/1000); | msec_delay(usec_interval/1000); | ||||
else | else | ||||
usec_delay(usec_interval); | usec_delay(usec_interval); | ||||
} | } | ||||
*success = (i < iterations); | *success = (i < iterations); | ||||
return ret_val; | |||||
} | |||||
/** | |||||
* igc_phy_sw_reset_generic - PHY software reset | |||||
* @hw: pointer to the HW structure | |||||
* | |||||
* Does a software reset of the PHY by reading the PHY control register and | |||||
* setting/write the control register reset bit to the PHY. | |||||
**/ | |||||
s32 igc_phy_sw_reset_generic(struct igc_hw *hw) | |||||
{ | |||||
s32 ret_val; | |||||
u16 phy_ctrl; | |||||
DEBUGFUNC("igc_phy_sw_reset_generic"); | |||||
if (!hw->phy.ops.read_reg) | |||||
return IGC_SUCCESS; | |||||
ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); | |||||
if (ret_val) | |||||
return ret_val; | |||||
phy_ctrl |= MII_CR_RESET; | |||||
ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); | |||||
if (ret_val) | |||||
return ret_val; | |||||
usec_delay(1); | |||||
return ret_val; | return ret_val; | ||||
} | } | ||||
/** | /** | ||||
* igc_phy_hw_reset_generic - PHY hardware reset | * igc_phy_hw_reset_generic - PHY hardware reset | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* | * | ||||
▲ Show 20 Lines • Show All 225 Lines • Show Last 20 Lines |