Differential D4168 Diff 11403 sys/arm/freescale/imx/imx6_ccm.c

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	return (132000000);	return (132000000);
	}	}

		void
		imx_ccm_ipu_enable(int ipu)
		{
		struct ccm_softc *sc;
		uint32_t reg;

		sc = ccm_sc;
		reg = RD4(sc, CCM_CCGR3);
		if (ipu == 1)
		reg \|= CCGR3_IPU1_IPU \| CCGR3_IPU1_DI0;
		else
		reg \|= CCGR3_IPU2_IPU \| CCGR3_IPU2_DI0;
		WR4(sc, CCM_CCGR3, reg);
		}

		void
		imx_ccm_hdmi_enable(void)
		andrewUnsubmitted Not Done Inline Actions void imx_ccm_hdmi_enable(void) andrew: ``` void imx_ccm_hdmi_enable(void) ```
		{
		struct ccm_softc *sc;
		uint32_t reg;

		sc = ccm_sc;
		reg = RD4(sc, CCM_CCGR2);
		reg \|= CCGR2_HDMI_TX \| CCGR2_HDMI_TX_ISFR;
		WR4(sc, CCM_CCGR2, reg);

		/* Set HDMI clock to 280MHz */
		reg = RD4(sc, CCM_CHSCCDR);
		reg &= ~(CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK \|
		CHSCCDR_IPU1_DI0_PODF_MASK \| CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
		reg \|= (CHSCCDR_PODF_DIVIDE_BY_3 << CHSCCDR_IPU1_DI0_PODF_SHIFT);
		reg \|= (CHSCCDR_IPU_PRE_CLK_540M_PFD << CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT);
		WR4(sc, CCM_CHSCCDR, reg);
		reg \|= (CHSCCDR_CLK_SEL_LDB_DI0 << CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT);
		WR4(sc, CCM_CHSCCDR, reg);
		}

	uint32_t	uint32_t
	imx_ccm_get_cacrr(void)	imx_ccm_get_cacrr(void)
	{	{
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