Changeset View
Changeset View
Standalone View
Standalone View
sys/dev/e1000/if_em.c
Show First 20 Lines • Show All 1,728 Lines • ▼ Show 20 Lines | if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) | ||||
e1000_pci_clear_mwi(&sc->hw); | e1000_pci_clear_mwi(&sc->hw); | ||||
reg_rctl |= E1000_RCTL_RST; | reg_rctl |= E1000_RCTL_RST; | ||||
E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); | E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); | ||||
msec_delay(5); | msec_delay(5); | ||||
} | } | ||||
mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); | mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); | ||||
if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) | |||||
e1000_update_mc_addr_list(&sc->hw, mta, mcnt); | |||||
reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); | reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); | ||||
if (if_getflags(ifp) & IFF_PROMISC) | if (if_getflags(ifp) & IFF_PROMISC) | ||||
reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); | reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); | ||||
else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || | else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || | ||||
if_getflags(ifp) & IFF_ALLMULTI) { | if_getflags(ifp) & IFF_ALLMULTI) { | ||||
reg_rctl |= E1000_RCTL_MPE; | reg_rctl |= E1000_RCTL_MPE; | ||||
reg_rctl &= ~E1000_RCTL_UPE; | reg_rctl &= ~E1000_RCTL_UPE; | ||||
} else | } else | ||||
reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); | reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); | ||||
E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); | E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); | ||||
if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) | |||||
e1000_update_mc_addr_list(&sc->hw, mta, mcnt); | |||||
if (sc->hw.mac.type == e1000_82542 && | if (sc->hw.mac.type == e1000_82542 && | ||||
sc->hw.revision_id == E1000_REVISION_2) { | sc->hw.revision_id == E1000_REVISION_2) { | ||||
reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); | reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); | ||||
reg_rctl &= ~E1000_RCTL_RST; | reg_rctl &= ~E1000_RCTL_RST; | ||||
E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); | E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); | ||||
msec_delay(5); | msec_delay(5); | ||||
if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) | if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) | ||||
▲ Show 20 Lines • Show All 3,126 Lines • Show Last 20 Lines |