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sys/xen/interface/arch-x86/xen.h
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* Terminate the array with a sentinel entry, with traps[].address==0. | * Terminate the array with a sentinel entry, with traps[].address==0. | ||||
* The privilege level specifies which modes may enter a trap via a software | * The privilege level specifies which modes may enter a trap via a software | ||||
* interrupt. On x86/64, since rings 1 and 2 are unavailable, we allocate | * interrupt. On x86/64, since rings 1 and 2 are unavailable, we allocate | ||||
* privilege levels as follows: | * privilege levels as follows: | ||||
* Level == 0: Noone may enter | * Level == 0: Noone may enter | ||||
* Level == 1: Kernel may enter | * Level == 1: Kernel may enter | ||||
* Level == 2: Kernel may enter | * Level == 2: Kernel may enter | ||||
* Level == 3: Everyone may enter | * Level == 3: Everyone may enter | ||||
* | |||||
* Note: For compatibility with kernels not setting up exception handlers | |||||
* early enough, Xen will avoid trying to inject #GP (and hence crash | |||||
* the domain) when an RDMSR would require this, but no handler was | |||||
* set yet. The precise conditions are implementation specific, and | |||||
* new code may not rely on such behavior anyway. | |||||
*/ | */ | ||||
#define TI_GET_DPL(_ti) ((_ti)->flags & 3) | #define TI_GET_DPL(_ti) ((_ti)->flags & 3) | ||||
#define TI_GET_IF(_ti) ((_ti)->flags & 4) | #define TI_GET_IF(_ti) ((_ti)->flags & 4) | ||||
#define TI_SET_DPL(_ti,_dpl) ((_ti)->flags |= (_dpl)) | #define TI_SET_DPL(_ti,_dpl) ((_ti)->flags |= (_dpl)) | ||||
#define TI_SET_IF(_ti,_if) ((_ti)->flags |= ((!!(_if))<<2)) | #define TI_SET_IF(_ti,_if) ((_ti)->flags |= ((!!(_if))<<2)) | ||||
struct trap_info { | struct trap_info { | ||||
uint8_t vector; /* exception vector */ | uint8_t vector; /* exception vector */ | ||||
uint8_t flags; /* 0-3: privilege level; 4: clear event enable? */ | uint8_t flags; /* 0-3: privilege level; 4: clear event enable? */ | ||||
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#define XEN_X86_EMU_ALL (XEN_X86_EMU_LAPIC | XEN_X86_EMU_HPET | \ | #define XEN_X86_EMU_ALL (XEN_X86_EMU_LAPIC | XEN_X86_EMU_HPET | \ | ||||
XEN_X86_EMU_PM | XEN_X86_EMU_RTC | \ | XEN_X86_EMU_PM | XEN_X86_EMU_RTC | \ | ||||
XEN_X86_EMU_IOAPIC | XEN_X86_EMU_PIC | \ | XEN_X86_EMU_IOAPIC | XEN_X86_EMU_PIC | \ | ||||
XEN_X86_EMU_VGA | XEN_X86_EMU_IOMMU | \ | XEN_X86_EMU_VGA | XEN_X86_EMU_IOMMU | \ | ||||
XEN_X86_EMU_PIT | XEN_X86_EMU_USE_PIRQ |\ | XEN_X86_EMU_PIT | XEN_X86_EMU_USE_PIRQ |\ | ||||
XEN_X86_EMU_VPCI) | XEN_X86_EMU_VPCI) | ||||
uint32_t emulation_flags; | uint32_t emulation_flags; | ||||
/* | |||||
* Select whether to use a relaxed behavior for accesses to MSRs not explicitly | |||||
* handled by Xen instead of injecting a #GP to the guest. Note this option | |||||
* doesn't allow the guest to read or write to the underlying MSR. | |||||
*/ | |||||
#define XEN_X86_MSR_RELAXED (1u << 0) | |||||
uint32_t misc_flags; | |||||
}; | }; | ||||
/* Location of online VCPU bitmap. */ | /* Location of online VCPU bitmap. */ | ||||
#define XEN_ACPI_CPU_MAP 0xaf00 | #define XEN_ACPI_CPU_MAP 0xaf00 | ||||
#define XEN_ACPI_CPU_MAP_LEN ((HVM_MAX_VCPUS + 7) / 8) | #define XEN_ACPI_CPU_MAP_LEN ((HVM_MAX_VCPUS + 7) / 8) | ||||
/* GPE0 bit set during CPU hotplug */ | /* GPE0 bit set during CPU hotplug */ | ||||
#define XEN_ACPI_GPE0_CPUHP_BIT 2 | #define XEN_ACPI_GPE0_CPUHP_BIT 2 | ||||
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