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sys/riscv/riscv/pmap.c
Show First 20 Lines • Show All 4,440 Lines • ▼ Show 20 Lines | #ifdef SMP | ||||
CPU_SET_ATOMIC(hart, &pmap->pm_active); | CPU_SET_ATOMIC(hart, &pmap->pm_active); | ||||
#else | #else | ||||
CPU_SET(hart, &pmap->pm_active); | CPU_SET(hart, &pmap->pm_active); | ||||
#endif | #endif | ||||
PCPU_SET(curpmap, pmap); | PCPU_SET(curpmap, pmap); | ||||
} | } | ||||
void | void | ||||
pmap_active_cpus(pmap_t pmap, cpuset_t *res) | |||||
{ | |||||
*res = pmap->pm_active; | |||||
} | |||||
void | |||||
pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz) | pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz) | ||||
{ | { | ||||
cpuset_t mask; | cpuset_t mask; | ||||
/* | /* | ||||
* From the RISC-V User-Level ISA V2.2: | * From the RISC-V User-Level ISA V2.2: | ||||
* | * | ||||
* "To make a store to instruction memory visible to all | * "To make a store to instruction memory visible to all | ||||
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