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sys/mips/mips/mips_pic.c
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#include <dev/ofw/ofw_bus.h> | #include <dev/ofw/ofw_bus.h> | ||||
#include <dev/ofw/ofw_bus_subr.h> | #include <dev/ofw/ofw_bus_subr.h> | ||||
#endif | #endif | ||||
#include "pic_if.h" | #include "pic_if.h" | ||||
struct mips_pic_softc; | struct mips_pic_softc; | ||||
static int mips_pic_intr(void *); | static intr_irq_filter_t mips_pic_intr; | ||||
static struct mips_pic_intr *mips_pic_find_intr(struct resource *r); | static struct mips_pic_intr *mips_pic_find_intr(struct resource *r); | ||||
static int mips_pic_map_fixed_intr(u_int irq, | static int mips_pic_map_fixed_intr(u_int irq, | ||||
struct mips_pic_intr **mapping); | struct mips_pic_intr **mapping); | ||||
static void cpu_establish_intr(struct mips_pic_softc *sc, | static void cpu_establish_intr(struct mips_pic_softc *sc, | ||||
const char *name, driver_filter_t *filt, | const char *name, driver_filter_t *filt, | ||||
void (*handler)(void*), void *arg, int irq, | void (*handler)(void*), void *arg, int irq, | ||||
int flags, void **cookiep); | int flags, void **cookiep); | ||||
▲ Show 20 Lines • Show All 172 Lines • ▼ Show 20 Lines | mips_pic_attach(device_t dev) | ||||
return (0); | return (0); | ||||
cleanup: | cleanup: | ||||
return(ENXIO); | return(ENXIO); | ||||
} | } | ||||
int | int | ||||
mips_pic_intr(void *arg) | mips_pic_intr(INTR_IRQ_FILTER_ARGS(arg, tf)) | ||||
{ | { | ||||
INTR_IRQ_FILTER_TRAPFRAME(tf) | |||||
struct mips_pic_softc *sc = arg; | struct mips_pic_softc *sc = arg; | ||||
register_t cause, status; | register_t cause, status; | ||||
int i, intr; | int i, intr; | ||||
cause = mips_rd_cause(); | cause = mips_rd_cause(); | ||||
status = mips_rd_status(); | status = mips_rd_status(); | ||||
intr = (cause & MIPS_INT_MASK) >> 8; | intr = (cause & MIPS_INT_MASK) >> 8; | ||||
/* | /* | ||||
* Do not handle masked interrupts. They were masked by | * Do not handle masked interrupts. They were masked by | ||||
* pre_ithread function (mips_mask_XXX_intr) and will be | * pre_ithread function (mips_mask_XXX_intr) and will be | ||||
* unmasked once ithread is through with handler | * unmasked once ithread is through with handler | ||||
*/ | */ | ||||
intr &= (status & MIPS_INT_MASK) >> 8; | intr &= (status & MIPS_INT_MASK) >> 8; | ||||
while ((i = fls(intr)) != 0) { | while ((i = fls(intr)) != 0) { | ||||
i--; /* Get a 0-offset interrupt. */ | i--; /* Get a 0-offset interrupt. */ | ||||
intr &= ~(1 << i); | intr &= ~(1 << i); | ||||
if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, i), | if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, i), tf) != 0) { | ||||
curthread->td_intr_frame) != 0) { | |||||
device_printf(sc->pic_dev, | device_printf(sc->pic_dev, | ||||
"Stray interrupt %u detected\n", i); | "Stray interrupt %u detected\n", i); | ||||
pic_irq_mask(sc, i); | pic_irq_mask(sc, i); | ||||
continue; | continue; | ||||
} | } | ||||
} | } | ||||
KASSERT(i == 0, ("all interrupts handled")); | KASSERT(i == 0, ("all interrupts handled")); | ||||
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