Differential D31986 Diff 96117 sys/arm64/iommu/iommu_pmap.c

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sys/arm64/iommu/iommu_pmap.c

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	static int			static int
	iommu_pmap_pinit_levels(pmap_t pmap, int levels)			iommu_pmap_pinit_levels(pmap_t pmap, int levels)
	{			{
	vm_page_t m;			vm_page_t m;

	/*			/*
	* allocate the l0 page			* allocate the l0 page
	*/			*/
	while ((m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL \|			m = vm_page_alloc_noobj(VM_ALLOC_NORMAL \| VM_ALLOC_WAITOK \|
	VM_ALLOC_NOOBJ \| VM_ALLOC_WIRED \| VM_ALLOC_ZERO)) == NULL)			VM_ALLOC_WIRED \| VM_ALLOC_ZERO);
	vm_wait(NULL);

	pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(m);			pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(m);
	pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);			pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);

	if ((m->flags & PG_ZERO) == 0)
	pagezero(pmap->pm_l0);

	pmap->pm_root.rt_root = 0;			pmap->pm_root.rt_root = 0;
	bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));			bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));

	MPASS(levels == 3 \|\| levels == 4);			MPASS(levels == 3 \|\| levels == 4);
	pmap->pm_levels = levels;			pmap->pm_levels = levels;

	/*			/*
	* Allocate the level 1 entry to use as the root. This will increase			* Allocate the level 1 entry to use as the root. This will increase
	Show All 33 Lines
	{			{
	vm_page_t m, l1pg, l2pg;			vm_page_t m, l1pg, l2pg;

	PMAP_LOCK_ASSERT(pmap, MA_OWNED);			PMAP_LOCK_ASSERT(pmap, MA_OWNED);

	/*			/*
	* Allocate a page table page.			* Allocate a page table page.
	*/			*/
	if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ \|			if ((m = vm_page_alloc_noobj(VM_ALLOC_WIRED \| VM_ALLOC_ZERO)) == NULL) {
	VM_ALLOC_WIRED \| VM_ALLOC_ZERO)) == NULL) {
	/*			/*
	* Indicate the need to retry. While waiting, the page table			* Indicate the need to retry. While waiting, the page table
	* page may have been allocated.			* page may have been allocated.
	*/			*/
	return (NULL);			return (NULL);
	}			}
	if ((m->flags & PG_ZERO) == 0)			m->pindex = ptepindex;
	pmap_zero_page(m);

	/*			/*
	* Because of AArch64's weak memory consistency model, we must have a			* Because of AArch64's weak memory consistency model, we must have a
	* barrier here to ensure that the stores for zeroing "m", whether by			* barrier here to ensure that the stores for zeroing "m", whether by
	* pmap_zero_page() or an earlier function, are visible before adding			* pmap_zero_page() or an earlier function, are visible before adding
	* "m" to the page table. Otherwise, a page table walk by another			* "m" to the page table. Otherwise, a page table walk by another
	* processor's MMU could see the mapping to "m" and a stale, non-zero			* processor's MMU could see the mapping to "m" and a stale, non-zero
	* PTE within "m".			* PTE within "m".
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