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Differential D32247 Diff 96080 sys/dev/nvme/nvme_ctrlr.c

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sys/dev/nvme/nvme_ctrlr.c

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#include "nvme_private.h" #include "nvme_private.h"
#define B4_CHK_RDY_DELAY_MS 2300 /* work around controller bug */ #define B4_CHK_RDY_DELAY_MS 2300 /* work around controller bug */
static void nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr, static void nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr,
struct nvme_async_event_request *aer); struct nvme_async_event_request *aer);
static void static void
nvme_ctrlr_barrier(struct nvme_controller *ctrlr, int flags)
{
bus_barrier(ctrlr->resource, 0, rman_get_size(ctrlr->resource), flags);
cpercivaUnsubmitted
Done
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--- nvme_ctrlr.o ---
/usr/src/sys/dev/nvme/nvme_ctrlr.c:60:11: error: too few arguments to function call, expected 5, have 4
            flags);
                 ^
./x86/bus.h:1002:1: note: 'bus_space_barrier' declared here
bus_space_barrier(bus_space_tag_t tag __unused, bus_space_handle_t bsh __unused,
^
cperciva: ``` --- nvme_ctrlr.o --- /usr/src/sys/dev/nvme/nvme_ctrlr.c:60:11: error: too few arguments to…
impAuthorUnsubmitted
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I'm an idiot... I got this too, fix it, but somehow uploaded the wrong one :(

imp: I'm an idiot... I got this too, fix it, but somehow uploaded the wrong one :(
}
static void
nvme_ctrlr_devctl_log(struct nvme_controller *ctrlr, const char *type, const char *msg, ...) nvme_ctrlr_devctl_log(struct nvme_controller *ctrlr, const char *type, const char *msg, ...)
{ {
struct sbuf sb; struct sbuf sb;
va_list ap; va_list ap;
int error; int error;
if (sbuf_new(&sb, NULL, 0, SBUF_AUTOEXTEND | SBUF_NOWAIT) == NULL) if (sbuf_new(&sb, NULL, 0, SBUF_AUTOEXTEND | SBUF_NOWAIT) == NULL)
return; return;
▲ Show 20 Lines • Show All 287 Lines • ▼ Show 20 Linesnvme_ctrlr_enable(struct nvme_controller *ctrlr)
} else { } else {
/* EN == 0 already wait for RDY == 0 or fail */ /* EN == 0 already wait for RDY == 0 or fail */
err = nvme_ctrlr_wait_for_ready(ctrlr, 0); err = nvme_ctrlr_wait_for_ready(ctrlr, 0);
if (err != 0) if (err != 0)
return (err); return (err);
} }
nvme_mmio_write_8(ctrlr, asq, ctrlr->adminq.cmd_bus_addr); nvme_mmio_write_8(ctrlr, asq, ctrlr->adminq.cmd_bus_addr);
DELAY(5000);
nvme_mmio_write_8(ctrlr, acq, ctrlr->adminq.cpl_bus_addr); nvme_mmio_write_8(ctrlr, acq, ctrlr->adminq.cpl_bus_addr);
DELAY(5000);
/* acqs and asqs are 0-based. */ /* acqs and asqs are 0-based. */
qsize = ctrlr->adminq.num_entries - 1; qsize = ctrlr->adminq.num_entries - 1;
aqa = 0; aqa = 0;
aqa = (qsize & NVME_AQA_REG_ACQS_MASK) << NVME_AQA_REG_ACQS_SHIFT; aqa = (qsize & NVME_AQA_REG_ACQS_MASK) << NVME_AQA_REG_ACQS_SHIFT;
aqa |= (qsize & NVME_AQA_REG_ASQS_MASK) << NVME_AQA_REG_ASQS_SHIFT; aqa |= (qsize & NVME_AQA_REG_ASQS_MASK) << NVME_AQA_REG_ASQS_SHIFT;
nvme_mmio_write_4(ctrlr, aqa, aqa); nvme_mmio_write_4(ctrlr, aqa, aqa);
DELAY(5000);
/* Initialization values for CC */ /* Initialization values for CC */
cc = 0; cc = 0;
cc |= 1 << NVME_CC_REG_EN_SHIFT; cc |= 1 << NVME_CC_REG_EN_SHIFT;
cc |= 0 << NVME_CC_REG_CSS_SHIFT; cc |= 0 << NVME_CC_REG_CSS_SHIFT;
cc |= 0 << NVME_CC_REG_AMS_SHIFT; cc |= 0 << NVME_CC_REG_AMS_SHIFT;
cc |= 0 << NVME_CC_REG_SHN_SHIFT; cc |= 0 << NVME_CC_REG_SHN_SHIFT;
cc |= 6 << NVME_CC_REG_IOSQES_SHIFT; /* SQ entry size == 64 == 2^6 */ cc |= 6 << NVME_CC_REG_IOSQES_SHIFT; /* SQ entry size == 64 == 2^6 */
cc |= 4 << NVME_CC_REG_IOCQES_SHIFT; /* CQ entry size == 16 == 2^4 */ cc |= 4 << NVME_CC_REG_IOCQES_SHIFT; /* CQ entry size == 16 == 2^4 */
/* This evaluates to 0, which is according to spec. */ /* This evaluates to 0, which is according to spec. */
cc |= (PAGE_SIZE >> 13) << NVME_CC_REG_MPS_SHIFT; cc |= (PAGE_SIZE >> 13) << NVME_CC_REG_MPS_SHIFT;
nvme_ctrlr_barrier(ctrlr, BUS_SPACE_BARRIER_WRITE);
nvme_mmio_write_4(ctrlr, cc, cc); nvme_mmio_write_4(ctrlr, cc, cc);
return (nvme_ctrlr_wait_for_ready(ctrlr, 1)); return (nvme_ctrlr_wait_for_ready(ctrlr, 1));
} }
static void static void
nvme_ctrlr_disable_qpairs(struct nvme_controller *ctrlr) nvme_ctrlr_disable_qpairs(struct nvme_controller *ctrlr)
{ {
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