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sys/dev/usb/controller/dwc3.h
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#define DWC3_GUSB2PHYCFG0_ENBLSLPM (1 << 8) | #define DWC3_GUSB2PHYCFG0_ENBLSLPM (1 << 8) | ||||
#define DWC3_GUSB2PHYCFG0_PHYSEL(x) ((x >> 7) & 0x1) /* 0 = USB2.0, 1 = USB1.1 */ | #define DWC3_GUSB2PHYCFG0_PHYSEL(x) ((x >> 7) & 0x1) /* 0 = USB2.0, 1 = USB1.1 */ | ||||
#define DWC3_GUSB2PHYCFG0_SUSPENDUSB20 (1 << 6) | #define DWC3_GUSB2PHYCFG0_SUSPENDUSB20 (1 << 6) | ||||
#define DWC3_GUSB2PHYCFG0_ULPI_UTMI_SEL (1 << 4) | #define DWC3_GUSB2PHYCFG0_ULPI_UTMI_SEL (1 << 4) | ||||
#define DWC3_GUSB2PHYCFG0_PHYIF (1 << 3) | #define DWC3_GUSB2PHYCFG0_PHYIF (1 << 3) | ||||
#define DWC3_GUSB3PIPECTL0 0xc2c0 | #define DWC3_GUSB3PIPECTL0 0xc2c0 | ||||
#define DWC3_GUSB3PIPECTL0_PHYSOFTRST (1 << 31) | #define DWC3_GUSB3PIPECTL0_PHYSOFTRST (1 << 31) | ||||
#define DWC3_GUSB3PIPECTL0_DISRXDETINP3 (1 << 28) | |||||
#define DWC3_GUSB3PIPECTL0_DELAYP1TRANS (1 << 18) | #define DWC3_GUSB3PIPECTL0_DELAYP1TRANS (1 << 18) | ||||
#define DWC3_GTXFIFOSIZ(x) (0xc300 + 0x4 * (x)) | #define DWC3_GTXFIFOSIZ(x) (0xc300 + 0x4 * (x)) | ||||
#define DWC3_GRXFIFOSIZ(x) (0xc380 + 0x4 * (x)) | #define DWC3_GRXFIFOSIZ(x) (0xc380 + 0x4 * (x)) | ||||
#define DWC3_GEVNTADRLO0 0xc400 | #define DWC3_GEVNTADRLO0 0xc400 | ||||
#define DWC3_GEVNTADRHI0 0xc404 | #define DWC3_GEVNTADRHI0 0xc404 | ||||
#define DWC3_GEVNTSIZ0 0xc408 | #define DWC3_GEVNTSIZ0 0xc408 | ||||
#define DWC3_GEVNTCOUNT0 0xc40C | #define DWC3_GEVNTCOUNT0 0xc40C | ||||
#define DWC3_GHWPARAMS8 0xc600 | #define DWC3_GHWPARAMS8 0xc600 | ||||
#define DWC3_GTXFIFOPRIDEV 0xc610 | #define DWC3_GTXFIFOPRIDEV 0xc610 | ||||
#define DWC3_GTXFIFOPRIHST 0xc618 | #define DWC3_GTXFIFOPRIHST 0xc618 | ||||
#define DWC3_GRXFIFOPRIHST 0xc61c | #define DWC3_GRXFIFOPRIHST 0xc61c | ||||
#define DWC3_GFIFOPRIDBC 0xc620 | #define DWC3_GFIFOPRIDBC 0xc620 | ||||
#define DWC3_GDMAHLRATIO 0xc624 | #define DWC3_GDMAHLRATIO 0xc624 | ||||
#define DWC3_GFLADJ 0xc630 | #define DWC3_GFLADJ 0xc630 | ||||
#define DWC3_DCFG 0xc700 | #define DWC3_DCFG 0xc700 | ||||
#define DWC3_DCTL 0xc704 | #define DWC3_DCTL 0xc704 | ||||
#define DWC3_DEVTEN 0xc708 | #define DWC3_DEVTEN 0xc708 | ||||
#define DWC3_DSTS 0xc70C | #define DWC3_DSTS 0xc70C | ||||
#define DWC3_DGCMDPAR 0xc710 | #define DWC3_DGCMDPAR 0xc710 | ||||
#define DWC3_DGCMD 0xc714 | #define DWC3_DGCMD 0xc714 | ||||
#define DWC3_DALEPENA 0xc720 | #define DWC3_DALEPENA 0xc720 | ||||
struct snps_dwc3_common_softc { | |||||
struct xhci_softc xsc; | |||||
device_t dev; | |||||
struct resource * mem_res; | |||||
bus_space_tag_t bst; | |||||
bus_space_handle_t bsh; | |||||
}; | |||||
#define DWC3_WRITE(_csc, _off, _val) \ | |||||
bus_space_write_4((_csc)->bst, (_csc)->bsh, _off, _val) | |||||
#define DWC3_READ(_csc, _off) \ | |||||
bus_space_read_4((_csc)->bst, (_csc)->bsh, _off) | |||||
int snps_dwc3_attach_xhci(struct snps_dwc3_common_softc *); | |||||
#if 0 | |||||
void snsp_dwc3_dump_regs(struct snps_dwc3_common_softc *); | |||||
#endif | |||||
void snps_dwc3_reset(struct snps_dwc3_common_softc *); | |||||
void snps_dwc3_configure_host(struct snps_dwc3_common_softc *); | |||||
void snps_dwc3_do_quirks(struct snps_dwc3_common_softc *); | |||||
int snps_dwc3_probe_common(device_t); | |||||
#endif /* _DWC3_H_ */ | #endif /* _DWC3_H_ */ |