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sys/dev/e1000/if_em.h
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* Default Value: 1024 | * Default Value: 1024 | ||||
* This value is the number of transmit descriptors allocated by the driver. | * This value is the number of transmit descriptors allocated by the driver. | ||||
* Increasing this value allows the driver to queue more transmits. Each | * Increasing this value allows the driver to queue more transmits. Each | ||||
* descriptor is 16 bytes. | * descriptor is 16 bytes. | ||||
* Since TDLEN should be multiple of 128bytes, the number of transmit | * Since TDLEN should be multiple of 128bytes, the number of transmit | ||||
* desscriptors should meet the following condition. | * desscriptors should meet the following condition. | ||||
* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 | * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 | ||||
*/ | */ | ||||
#define EM_MIN_TXD 128 | #define EM_MIN_TXD 128 | ||||
#define EM_MAX_TXD 4096 | #define EM_MAX_TXD 4096 | ||||
#define EM_DEFAULT_TXD 1024 | #define EM_DEFAULT_TXD 1024 | ||||
#define EM_DEFAULT_MULTI_TXD 4096 | #define EM_DEFAULT_MULTI_TXD 4096 | ||||
#define IGB_MAX_TXD 4096 | #define IGB_MAX_TXD 4096 | ||||
/* | /* | ||||
* EM_MAX_RXD - Maximum number of receive Descriptors | * EM_MAX_RXD - Maximum number of receive Descriptors | ||||
* Valid Range: 80-256 for 82542 and 82543-based adapters | * Valid Range: 80-256 for 82542 and 82543-based adapters | ||||
* 80-4096 for others | * 80-4096 for others | ||||
* Default Value: 1024 | * Default Value: 1024 | ||||
* This value is the number of receive descriptors allocated by the driver. | * This value is the number of receive descriptors allocated by the driver. | ||||
* Increasing this value allows the driver to buffer more incoming packets. | * Increasing this value allows the driver to buffer more incoming packets. | ||||
* Each descriptor is 16 bytes. A receive buffer is also allocated for each | * Each descriptor is 16 bytes. A receive buffer is also allocated for each | ||||
* descriptor. The maximum MTU size is 16110. | * descriptor. The maximum MTU size is 16110. | ||||
* Since TDLEN should be multiple of 128bytes, the number of transmit | * Since TDLEN should be multiple of 128bytes, the number of transmit | ||||
* desscriptors should meet the following condition. | * desscriptors should meet the following condition. | ||||
* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 | * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 | ||||
*/ | */ | ||||
#define EM_MIN_RXD 128 | #define EM_MIN_RXD 128 | ||||
#define EM_MAX_RXD 4096 | #define EM_MAX_RXD 4096 | ||||
#define EM_DEFAULT_RXD 1024 | #define EM_DEFAULT_RXD 1024 | ||||
#define EM_DEFAULT_MULTI_RXD 4096 | #define EM_DEFAULT_MULTI_RXD 4096 | ||||
#define IGB_MAX_RXD 4096 | #define IGB_MAX_RXD 4096 | ||||
/* | /* | ||||
* EM_TIDV - Transmit Interrupt Delay Value | * EM_TIDV - Transmit Interrupt Delay Value | ||||
* Valid Range: 0-65535 (0=off) | * Valid Range: 0-65535 (0=off) | ||||
* Default Value: 64 | * Default Value: 64 | ||||
* This value delays the generation of transmit interrupts in units of | * This value delays the generation of transmit interrupts in units of | ||||
* 1.024 microseconds. Transmit interrupt reduction can improve CPU | * 1.024 microseconds. Transmit interrupt reduction can improve CPU | ||||
* efficiency if properly tuned for specific network traffic. If the | * efficiency if properly tuned for specific network traffic. If the | ||||
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines | |||||
*/ | */ | ||||
#define EM_RADV 64 | #define EM_RADV 64 | ||||
/* | /* | ||||
* This parameter controls whether or not autonegotation is enabled. | * This parameter controls whether or not autonegotation is enabled. | ||||
* 0 - Disable autonegotiation | * 0 - Disable autonegotiation | ||||
* 1 - Enable autonegotiation | * 1 - Enable autonegotiation | ||||
*/ | */ | ||||
#define DO_AUTO_NEG 1 | #define DO_AUTO_NEG 1 | ||||
/* | /* | ||||
* This parameter control whether or not the driver will wait for | * This parameter control whether or not the driver will wait for | ||||
* autonegotiation to complete. | * autonegotiation to complete. | ||||
* 1 - Wait for autonegotiation to complete | * 1 - Wait for autonegotiation to complete | ||||
* 0 - Don't wait for autonegotiation to complete | * 0 - Don't wait for autonegotiation to complete | ||||
*/ | */ | ||||
#define WAIT_FOR_AUTO_NEG_DEFAULT 0 | #define WAIT_FOR_AUTO_NEG_DEFAULT 0 | ||||
/* Tunables -- End */ | /* Tunables -- End */ | ||||
#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ | #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ | ||||
ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ | ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ | ||||
ADVERTISE_1000_FULL) | ADVERTISE_1000_FULL) | ||||
#define AUTO_ALL_MODES 0 | #define AUTO_ALL_MODES 0 | ||||
/* PHY master/slave setting */ | /* PHY master/slave setting */ | ||||
#define EM_MASTER_SLAVE e1000_ms_hw_default | #define EM_MASTER_SLAVE e1000_ms_hw_default | ||||
/* | /* | ||||
* Miscellaneous constants | * Miscellaneous constants | ||||
*/ | */ | ||||
#define EM_VENDOR_ID 0x8086 | #define EM_VENDOR_ID 0x8086 | ||||
#define EM_FLASH 0x0014 | #define EM_FLASH 0x0014 | ||||
#define EM_JUMBO_PBA 0x00000028 | #define EM_JUMBO_PBA 0x00000028 | ||||
#define EM_DEFAULT_PBA 0x00000030 | #define EM_DEFAULT_PBA 0x00000030 | ||||
#define EM_SMARTSPEED_DOWNSHIFT 3 | #define EM_SMARTSPEED_DOWNSHIFT 3 | ||||
#define EM_SMARTSPEED_MAX 15 | #define EM_SMARTSPEED_MAX 15 | ||||
#define EM_MAX_LOOP 10 | #define EM_MAX_LOOP 10 | ||||
#define MAX_NUM_MULTICAST_ADDRESSES 128 | #define MAX_NUM_MULTICAST_ADDRESSES 128 | ||||
#define PCI_ANY_ID (~0U) | #define PCI_ANY_ID (~0U) | ||||
#define ETHER_ALIGN 2 | #define ETHER_ALIGN 2 | ||||
#define EM_FC_PAUSE_TIME 0x0680 | #define EM_FC_PAUSE_TIME 0x0680 | ||||
#define EM_EEPROM_APME 0x400; | #define EM_EEPROM_APME 0x400; | ||||
#define EM_82544_APME 0x0004; | #define EM_82544_APME 0x0004; | ||||
/* Support AutoMediaDetect for Marvell M88 PHY in i354 */ | /* Support AutoMediaDetect for Marvell M88 PHY in i354 */ | ||||
#define IGB_MEDIA_RESET (1 << 0) | #define IGB_MEDIA_RESET (1 << 0) | ||||
/* Define the starting Interrupt rate per Queue */ | /* Define the starting Interrupt rate per Queue */ | ||||
#define IGB_INTS_PER_SEC 8000 | #define IGB_INTS_PER_SEC 8000 | ||||
#define IGB_DEFAULT_ITR ((1000000/IGB_INTS_PER_SEC) << 2) | #define IGB_DEFAULT_ITR ((1000000/IGB_INTS_PER_SEC) << 2) | ||||
#define IGB_LINK_ITR 2000 | #define IGB_LINK_ITR 2000 | ||||
#define I210_LINK_DELAY 1000 | #define I210_LINK_DELAY 1000 | ||||
#define IGB_TXPBSIZE 20408 | #define IGB_TXPBSIZE 20408 | ||||
#define IGB_HDR_BUF 128 | #define IGB_HDR_BUF 128 | ||||
#define IGB_PKTTYPE_MASK 0x0000FFF0 | #define IGB_PKTTYPE_MASK 0x0000FFF0 | ||||
#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ | #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ | ||||
/* | /* | ||||
* Driver state logic for the detection of a hung state | * Driver state logic for the detection of a hung state | ||||
* in hardware. Set TX_HUNG whenever a TX packet is used | * in hardware. Set TX_HUNG whenever a TX packet is used | ||||
* (data is sent) and clear it when txeof() is invoked if | * (data is sent) and clear it when txeof() is invoked if | ||||
* any descriptors from the ring are cleaned/reclaimed. | * any descriptors from the ring are cleaned/reclaimed. | ||||
* Increment internal counter if no descriptors are cleaned | * Increment internal counter if no descriptors are cleaned | ||||
* and compare to TX_MAXTRIES. When counter > TX_MAXTRIES, | * and compare to TX_MAXTRIES. When counter > TX_MAXTRIES, | ||||
* reset adapter. | * reset adapter. | ||||
*/ | */ | ||||
#define EM_TX_IDLE 0x00000000 | #define EM_TX_IDLE 0x00000000 | ||||
#define EM_TX_BUSY 0x00000001 | #define EM_TX_BUSY 0x00000001 | ||||
#define EM_TX_HUNG 0x80000000 | #define EM_TX_HUNG 0x80000000 | ||||
#define EM_TX_MAXTRIES 10 | #define EM_TX_MAXTRIES 10 | ||||
#define PCICFG_DESC_RING_STATUS 0xe4 | #define PCICFG_DESC_RING_STATUS 0xe4 | ||||
#define FLUSH_DESC_REQUIRED 0x100 | #define FLUSH_DESC_REQUIRED 0x100 | ||||
#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \ | #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \ | ||||
((hw->mac.type <= e1000_82576) ? 16 : 8)) | ((hw->mac.type <= e1000_82576) ? 16 : 8)) | ||||
#define IGB_RX_HTHRESH 8 | #define IGB_RX_HTHRESH 8 | ||||
#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ | #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ | ||||
(sc->intr_type == IFLIB_INTR_MSIX)) ? 1 : 4) | (sc->intr_type == IFLIB_INTR_MSIX)) ? 1 : 4) | ||||
#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) | #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) | ||||
#define IGB_TX_HTHRESH 1 | #define IGB_TX_HTHRESH 1 | ||||
#define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ | #define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ | ||||
sc->intr_type == IFLIB_INTR_MSIX) ? 1 : 16) | sc->intr_type == IFLIB_INTR_MSIX) ? 1 : 16) | ||||
/* | /* | ||||
* TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be | * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be | ||||
* multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will | * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will | ||||
* also optimize cache line size effect. H/W supports up to cache line size 128. | * also optimize cache line size effect. H/W supports up to cache line size 128. | ||||
*/ | */ | ||||
#define EM_DBA_ALIGN 128 | #define EM_DBA_ALIGN 128 | ||||
/* | /* | ||||
* See Intel 82574 Driver Programming Interface Manual, Section 10.2.6.9 | * See Intel 82574 Driver Programming Interface Manual, Section 10.2.6.9 | ||||
*/ | */ | ||||
#define TARC_COMPENSATION_MODE (1 << 7) /* Compensation Mode */ | #define TARC_COMPENSATION_MODE (1 << 7) /* Compensation Mode */ | ||||
#define TARC_SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */ | #define TARC_SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */ | ||||
#define TARC_MQ_FIX (1 << 23) | \ | #define TARC_MQ_FIX (1 << 23) | \ | ||||
(1 << 24) | \ | (1 << 24) | \ | ||||
(1 << 25) /* Handle errata in MQ mode */ | (1 << 25) /* Handle errata in MQ mode */ | ||||
#define TARC_ERRATA_BIT (1 << 26) /* Note from errata on 82574 */ | #define TARC_ERRATA_BIT (1 << 26) /* Note from errata on 82574 */ | ||||
/* PCI Config defines */ | /* PCI Config defines */ | ||||
#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) | #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) | ||||
#define EM_BAR_TYPE_MASK 0x00000001 | #define EM_BAR_TYPE_MASK 0x00000001 | ||||
#define EM_BAR_TYPE_MMEM 0x00000000 | #define EM_BAR_TYPE_MMEM 0x00000000 | ||||
#define EM_BAR_TYPE_IO 0x00000001 | #define EM_BAR_TYPE_IO 0x00000001 | ||||
#define EM_BAR_TYPE_FLASH 0x0014 | #define EM_BAR_TYPE_FLASH 0x0014 | ||||
#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) | #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) | ||||
#define EM_BAR_MEM_TYPE_MASK 0x00000006 | #define EM_BAR_MEM_TYPE_MASK 0x00000006 | ||||
#define EM_BAR_MEM_TYPE_32BIT 0x00000000 | #define EM_BAR_MEM_TYPE_32BIT 0x00000000 | ||||
#define EM_BAR_MEM_TYPE_64BIT 0x00000004 | #define EM_BAR_MEM_TYPE_64BIT 0x00000004 | ||||
/* Defines for printing debug information */ | /* Defines for printing debug information */ | ||||
#define DEBUG_INIT 0 | #define DEBUG_INIT 0 | ||||
#define DEBUG_IOCTL 0 | #define DEBUG_IOCTL 0 | ||||
#define DEBUG_HW 0 | #define DEBUG_HW 0 | ||||
#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") | #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") | ||||
#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) | #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) | ||||
#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) | #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) | ||||
#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") | #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") | ||||
#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) | #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) | ||||
#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) | #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) | ||||
#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") | #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") | ||||
#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) | #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) | ||||
#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) | #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) | ||||
#define EM_MAX_SCATTER 40 | #define EM_MAX_SCATTER 40 | ||||
#define EM_VFTA_SIZE 128 | #define EM_VFTA_SIZE 128 | ||||
#define EM_TSO_SIZE 65535 | #define EM_TSO_SIZE 65535 | ||||
#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ | #define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ | ||||
#define ETH_ZLEN 60 | #define ETH_ZLEN 60 | ||||
#define EM_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP) /* Offload bits in mbuf flag */ | #define EM_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP) /* Offload bits in mbuf flag */ | ||||
#define IGB_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | \ | #define IGB_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | \ | ||||
CSUM_IP_SCTP | CSUM_IP6_UDP | CSUM_IP6_TCP | \ | CSUM_IP_SCTP | CSUM_IP6_UDP | CSUM_IP6_TCP | \ | ||||
CSUM_IP6_SCTP) /* Offload bits in mbuf flag */ | CSUM_IP6_SCTP) /* Offload bits in mbuf flag */ | ||||
#define IGB_PKTTYPE_MASK 0x0000FFF0 | #define IGB_PKTTYPE_MASK 0x0000FFF0 | ||||
#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ | #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ | ||||
/* | /* | ||||
* 82574 has a nonstandard address for EIAC | * 82574 has a nonstandard address for EIAC | ||||
* and since its only used in MSI-X, and in | * and since its only used in MSI-X, and in | ||||
* the em driver only 82574 uses MSI-X we can | * the em driver only 82574 uses MSI-X we can | ||||
* solve it just using this define. | * solve it just using this define. | ||||
*/ | */ | ||||
#define EM_EIAC 0x000DC | #define EM_EIAC 0x000DC | ||||
/* | /* | ||||
* 82574 only reports 3 MSI-X vectors by default; | * 82574 only reports 3 MSI-X vectors by default; | ||||
* defines assisting with making it report 5 are | * defines assisting with making it report 5 are | ||||
* located here. | * located here. | ||||
*/ | */ | ||||
#define EM_NVM_PCIE_CTRL 0x1B | #define EM_NVM_PCIE_CTRL 0x1B | ||||
#define EM_NVM_MSIX_N_MASK (0x7 << EM_NVM_MSIX_N_SHIFT) | #define EM_NVM_MSIX_N_MASK (0x7 << EM_NVM_MSIX_N_SHIFT) | ||||
#define EM_NVM_MSIX_N_SHIFT 7 | #define EM_NVM_MSIX_N_SHIFT 7 | ||||
struct e1000_softc; | struct e1000_softc; | ||||
struct em_int_delay_info { | struct em_int_delay_info { | ||||
struct e1000_softc *sc; /* Back-pointer to the sc struct */ | struct e1000_softc *sc; /* Back-pointer to the sc struct */ | ||||
int offset; /* Register offset to read/write */ | int offset; /* Register offset to read/write */ | ||||
int value; /* Current value in usecs */ | int value; /* Current value in usecs */ | ||||
}; | }; | ||||
/* | /* | ||||
* The transmit ring, one per tx queue | * The transmit ring, one per tx queue | ||||
*/ | */ | ||||
struct tx_ring { | struct tx_ring { | ||||
struct e1000_softc *sc; | struct e1000_softc *sc; | ||||
struct e1000_tx_desc *tx_base; | struct e1000_tx_desc *tx_base; | ||||
uint64_t tx_paddr; | uint64_t tx_paddr; | ||||
qidx_t *tx_rsq; | qidx_t *tx_rsq; | ||||
bool tx_tso; /* last tx was tso */ | bool tx_tso; /* last tx was tso */ | ||||
uint8_t me; | uint8_t me; | ||||
qidx_t tx_rs_cidx; | qidx_t tx_rs_cidx; | ||||
qidx_t tx_rs_pidx; | qidx_t tx_rs_pidx; | ||||
qidx_t tx_cidx_processed; | qidx_t tx_cidx_processed; | ||||
/* Interrupt resources */ | /* Interrupt resources */ | ||||
void *tag; | void *tag; | ||||
struct resource *res; | struct resource *res; | ||||
unsigned long tx_irq; | unsigned long tx_irq; | ||||
/* Saved csum offloading context information */ | /* Saved csum offloading context information */ | ||||
int csum_flags; | int csum_flags; | ||||
int csum_lhlen; | int csum_lhlen; | ||||
int csum_iphlen; | int csum_iphlen; | ||||
int csum_thlen; | int csum_thlen; | ||||
int csum_mss; | int csum_mss; | ||||
int csum_pktlen; | int csum_pktlen; | ||||
uint32_t csum_txd_upper; | uint32_t csum_txd_upper; | ||||
uint32_t csum_txd_lower; /* last field */ | uint32_t csum_txd_lower; /* last field */ | ||||
}; | }; | ||||
/* | /* | ||||
* The Receive ring, one per rx queue | * The Receive ring, one per rx queue | ||||
*/ | */ | ||||
struct rx_ring { | struct rx_ring { | ||||
struct e1000_softc *sc; | struct e1000_softc *sc; | ||||
struct em_rx_queue *que; | struct em_rx_queue *que; | ||||
u32 me; | u32 me; | ||||
u32 payload; | u32 payload; | ||||
union e1000_rx_desc_extended *rx_base; | union e1000_rx_desc_extended *rx_base; | ||||
uint64_t rx_paddr; | uint64_t rx_paddr; | ||||
/* Interrupt resources */ | /* Interrupt resources */ | ||||
void *tag; | void *tag; | ||||
struct resource *res; | struct resource *res; | ||||
bool discard; | bool discard; | ||||
/* Soft stats */ | /* Soft stats */ | ||||
unsigned long rx_irq; | unsigned long rx_irq; | ||||
unsigned long rx_discarded; | unsigned long rx_discarded; | ||||
unsigned long rx_packets; | unsigned long rx_packets; | ||||
unsigned long rx_bytes; | unsigned long rx_bytes; | ||||
}; | }; | ||||
struct em_tx_queue { | struct em_tx_queue { | ||||
struct e1000_softc *sc; | struct e1000_softc *sc; | ||||
u32 msix; | u32 msix; | ||||
u32 eims; /* This queue's EIMS bit */ | u32 eims; /* This queue's EIMS bit */ | ||||
u32 me; | u32 me; | ||||
struct tx_ring txr; | struct tx_ring txr; | ||||
}; | }; | ||||
struct em_rx_queue { | struct em_rx_queue { | ||||
struct e1000_softc *sc; | struct e1000_softc *sc; | ||||
u32 me; | u32 me; | ||||
u32 msix; | u32 msix; | ||||
u32 eims; | u32 eims; | ||||
struct rx_ring rxr; | struct rx_ring rxr; | ||||
u64 irqs; | u64 irqs; | ||||
struct if_irq que_irq; | struct if_irq que_irq; | ||||
}; | }; | ||||
/* Our softc structure */ | /* Our softc structure */ | ||||
struct e1000_softc { | struct e1000_softc { | ||||
struct ifnet *ifp; | struct ifnet *ifp; | ||||
struct e1000_hw hw; | struct e1000_hw hw; | ||||
if_softc_ctx_t shared; | if_softc_ctx_t shared; | ||||
if_ctx_t ctx; | if_ctx_t ctx; | ||||
#define tx_num_queues shared->isc_ntxqsets | #define tx_num_queues shared->isc_ntxqsets | ||||
#define rx_num_queues shared->isc_nrxqsets | #define rx_num_queues shared->isc_nrxqsets | ||||
#define intr_type shared->isc_intr | #define intr_type shared->isc_intr | ||||
/* FreeBSD operating-system-specific structures. */ | /* FreeBSD operating-system-specific structures. */ | ||||
struct e1000_osdep osdep; | struct e1000_osdep osdep; | ||||
device_t dev; | device_t dev; | ||||
struct cdev *led_dev; | struct cdev *led_dev; | ||||
struct em_tx_queue *tx_queues; | struct em_tx_queue *tx_queues; | ||||
struct em_rx_queue *rx_queues; | struct em_rx_queue *rx_queues; | ||||
struct if_irq irq; | struct if_irq irq; | ||||
struct resource *memory; | struct resource *memory; | ||||
struct resource *flash; | struct resource *flash; | ||||
struct resource *ioport; | struct resource *ioport; | ||||
struct resource *res; | struct resource *res; | ||||
void *tag; | void *tag; | ||||
u32 linkvec; | u32 linkvec; | ||||
u32 ivars; | u32 ivars; | ||||
struct ifmedia *media; | struct ifmedia *media; | ||||
int msix; | int msix; | ||||
int if_flags; | int if_flags; | ||||
int em_insert_vlan_header; | int em_insert_vlan_header; | ||||
u32 ims; | u32 ims; | ||||
bool in_detach; | bool in_detach; | ||||
u32 flags; | u32 flags; | ||||
/* Task for FAST handling */ | /* Task for FAST handling */ | ||||
struct grouptask link_task; | struct grouptask link_task; | ||||
u16 num_vlans; | u16 num_vlans; | ||||
u32 txd_cmd; | u32 txd_cmd; | ||||
u32 tx_process_limit; | u32 tx_process_limit; | ||||
u32 rx_process_limit; | u32 rx_process_limit; | ||||
u32 rx_mbuf_sz; | u32 rx_mbuf_sz; | ||||
/* Management and WOL features */ | /* Management and WOL features */ | ||||
u32 wol; | u32 wol; | ||||
bool has_manage; | bool has_manage; | ||||
bool has_amt; | bool has_amt; | ||||
/* Multicast array memory */ | /* Multicast array memory */ | ||||
u8 *mta; | u8 *mta; | ||||
/* | /* | ||||
** Shadow VFTA table, this is needed because | ** Shadow VFTA table, this is needed because | ||||
** the real vlan filter table gets cleared during | ** the real vlan filter table gets cleared during | ||||
** a soft reset and the driver needs to be able | ** a soft reset and the driver needs to be able | ||||
** to repopulate it. | ** to repopulate it. | ||||
*/ | */ | ||||
u32 shadow_vfta[EM_VFTA_SIZE]; | u32 shadow_vfta[EM_VFTA_SIZE]; | ||||
/* Info about the interface */ | /* Info about the interface */ | ||||
u16 link_active; | u16 link_active; | ||||
u16 fc; | u16 fc; | ||||
u16 link_speed; | u16 link_speed; | ||||
u16 link_duplex; | u16 link_duplex; | ||||
u32 smartspeed; | u32 smartspeed; | ||||
u32 dmac; | u32 dmac; | ||||
int link_mask; | int link_mask; | ||||
u64 que_mask; | u64 que_mask; | ||||
struct em_int_delay_info tx_int_delay; | struct em_int_delay_info tx_int_delay; | ||||
struct em_int_delay_info tx_abs_int_delay; | struct em_int_delay_info tx_abs_int_delay; | ||||
struct em_int_delay_info rx_int_delay; | struct em_int_delay_info rx_int_delay; | ||||
struct em_int_delay_info rx_abs_int_delay; | struct em_int_delay_info rx_abs_int_delay; | ||||
struct em_int_delay_info tx_itr; | struct em_int_delay_info tx_itr; | ||||
/* Misc stats maintained by the driver */ | /* Misc stats maintained by the driver */ | ||||
unsigned long dropped_pkts; | unsigned long dropped_pkts; | ||||
unsigned long link_irq; | unsigned long link_irq; | ||||
unsigned long rx_overruns; | unsigned long rx_overruns; | ||||
unsigned long watchdog_events; | unsigned long watchdog_events; | ||||
struct e1000_hw_stats stats; | struct e1000_hw_stats stats; | ||||
u16 vf_ifp; | u16 vf_ifp; | ||||
}; | }; | ||||
/******************************************************************************** | /******************************************************************************** | ||||
* vendor_info_array | * vendor_info_array | ||||
* | * | ||||
* This array contains the list of Subvendor/Subdevice IDs on which the driver | * This array contains the list of Subvendor/Subdevice IDs on which the driver | ||||
* should load. | * should load. | ||||
* | * | ||||
********************************************************************************/ | ********************************************************************************/ | ||||
typedef struct _em_vendor_info_t { | typedef struct _em_vendor_info_t { | ||||
unsigned int vendor_id; | unsigned int vendor_id; | ||||
unsigned int device_id; | unsigned int device_id; | ||||
unsigned int subvendor_id; | unsigned int subvendor_id; | ||||
unsigned int subdevice_id; | unsigned int subdevice_id; | ||||
unsigned int index; | unsigned int index; | ||||
} em_vendor_info_t; | } em_vendor_info_t; | ||||
void em_dump_rs(struct e1000_softc *); | void em_dump_rs(struct e1000_softc *); | ||||
#define EM_RSSRK_SIZE 4 | #define EM_RSSRK_SIZE 4 | ||||
#define EM_RSSRK_VAL(key, i) (key[(i) * EM_RSSRK_SIZE] | \ | #define EM_RSSRK_VAL(key, i) (key[(i) * EM_RSSRK_SIZE] | \ | ||||
key[(i) * EM_RSSRK_SIZE + 1] << 8 | \ | key[(i) * EM_RSSRK_SIZE + 1] << 8 | \ | ||||
key[(i) * EM_RSSRK_SIZE + 2] << 16 | \ | key[(i) * EM_RSSRK_SIZE + 2] << 16 | \ | ||||
key[(i) * EM_RSSRK_SIZE + 3] << 24) | key[(i) * EM_RSSRK_SIZE + 3] << 24) | ||||
#endif /* _EM_H_DEFINED_ */ | #endif /* _EM_H_DEFINED_ */ |