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sys/dev/mlx5/mlx5_ifc.h
/*- | /*- | ||||
* Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. | * Copyright (c) 2013-2020, Mellanox Technologies. All rights reserved. | ||||
* | * | ||||
* Redistribution and use in source and binary forms, with or without | * Redistribution and use in source and binary forms, with or without | ||||
* modification, are permitted provided that the following conditions | * modification, are permitted provided that the following conditions | ||||
* are met: | * are met: | ||||
* 1. Redistributions of source code must retain the above copyright | * 1. Redistributions of source code must retain the above copyright | ||||
* notice, this list of conditions and the following disclaimer. | * notice, this list of conditions and the following disclaimer. | ||||
* 2. Redistributions in binary form must reproduce the above copyright | * 2. Redistributions in binary form must reproduce the above copyright | ||||
* notice, this list of conditions and the following disclaimer in the | * notice, this list of conditions and the following disclaimer in the | ||||
Show All 15 Lines | |||||
*/ | */ | ||||
#ifndef MLX5_IFC_H | #ifndef MLX5_IFC_H | ||||
#define MLX5_IFC_H | #define MLX5_IFC_H | ||||
#include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h> | #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h> | ||||
enum { | enum { | ||||
MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0, | |||||
MLX5_EVENT_TYPE_COMP = 0x0, | MLX5_EVENT_TYPE_COMP = 0x0, | ||||
MLX5_EVENT_TYPE_PATH_MIG = 0x1, | MLX5_EVENT_TYPE_PATH_MIG = 0x1, | ||||
MLX5_EVENT_TYPE_COMM_EST = 0x2, | MLX5_EVENT_TYPE_COMM_EST = 0x2, | ||||
MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, | MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, | ||||
MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, | MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, | ||||
MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, | MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, | ||||
MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, | MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, | ||||
MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, | MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, | ||||
MLX5_EVENT_TYPE_CQ_ERROR = 0x4, | MLX5_EVENT_TYPE_CQ_ERROR = 0x4, | ||||
MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, | MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, | ||||
MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, | MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, | ||||
MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, | MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, | ||||
MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | ||||
MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | ||||
MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | ||||
MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, | MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, | ||||
MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, | MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, | ||||
MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, | MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, | ||||
MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, | MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, | ||||
MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, | MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, | ||||
MLX5_EVENT_TYPE_XRQ_ERROR = 0x18, | |||||
MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, | MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, | ||||
MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, | MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, | ||||
MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, | MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, | ||||
MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, | MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, | ||||
MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, | MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, | ||||
MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, | MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, | ||||
MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, | MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, | ||||
MLX5_EVENT_TYPE_CMD = 0xa, | MLX5_EVENT_TYPE_CMD = 0xa, | ||||
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}; | }; | ||||
enum { | enum { | ||||
MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, | MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, | ||||
MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, | MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, | ||||
}; | }; | ||||
enum { | enum { | ||||
MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, | |||||
MLX5_OBJ_TYPE_MKEY = 0xff01, | |||||
MLX5_OBJ_TYPE_QP = 0xff02, | |||||
MLX5_OBJ_TYPE_PSV = 0xff03, | |||||
MLX5_OBJ_TYPE_RMP = 0xff04, | |||||
MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, | |||||
MLX5_OBJ_TYPE_RQ = 0xff06, | |||||
MLX5_OBJ_TYPE_SQ = 0xff07, | |||||
MLX5_OBJ_TYPE_TIR = 0xff08, | |||||
MLX5_OBJ_TYPE_TIS = 0xff09, | |||||
MLX5_OBJ_TYPE_DCT = 0xff0a, | |||||
MLX5_OBJ_TYPE_XRQ = 0xff0b, | |||||
MLX5_OBJ_TYPE_RQT = 0xff0e, | |||||
MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, | |||||
MLX5_OBJ_TYPE_CQ = 0xff10, | |||||
}; | |||||
enum { | |||||
MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, | MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, | ||||
MLX5_CMD_OP_QUERY_ADAPTER = 0x101, | MLX5_CMD_OP_QUERY_ADAPTER = 0x101, | ||||
MLX5_CMD_OP_INIT_HCA = 0x102, | MLX5_CMD_OP_INIT_HCA = 0x102, | ||||
MLX5_CMD_OP_TEARDOWN_HCA = 0x103, | MLX5_CMD_OP_TEARDOWN_HCA = 0x103, | ||||
MLX5_CMD_OP_ENABLE_HCA = 0x104, | MLX5_CMD_OP_ENABLE_HCA = 0x104, | ||||
MLX5_CMD_OP_DISABLE_HCA = 0x105, | MLX5_CMD_OP_DISABLE_HCA = 0x105, | ||||
MLX5_CMD_OP_QUERY_PAGES = 0x107, | MLX5_CMD_OP_QUERY_PAGES = 0x107, | ||||
MLX5_CMD_OP_MANAGE_PAGES = 0x108, | MLX5_CMD_OP_MANAGE_PAGES = 0x108, | ||||
Show All 40 Lines | enum { | ||||
MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, | MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, | ||||
MLX5_CMD_OP_CREATE_DCT = 0x710, | MLX5_CMD_OP_CREATE_DCT = 0x710, | ||||
MLX5_CMD_OP_DESTROY_DCT = 0x711, | MLX5_CMD_OP_DESTROY_DCT = 0x711, | ||||
MLX5_CMD_OP_DRAIN_DCT = 0x712, | MLX5_CMD_OP_DRAIN_DCT = 0x712, | ||||
MLX5_CMD_OP_QUERY_DCT = 0x713, | MLX5_CMD_OP_QUERY_DCT = 0x713, | ||||
MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, | MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, | ||||
MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, | MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, | ||||
MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, | MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, | ||||
MLX5_CMD_OP_CREATE_XRQ = 0x717, | |||||
MLX5_CMD_OP_DESTROY_XRQ = 0x718, | |||||
MLX5_CMD_OP_QUERY_XRQ = 0x719, | |||||
MLX5_CMD_OP_ARM_XRQ = 0x71a, | |||||
MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, | |||||
MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, | |||||
MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, | |||||
MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, | |||||
MLX5_CMD_OP_MODIFY_XRQ = 0x72a, | |||||
MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, | MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, | ||||
MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, | MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, | ||||
MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, | MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, | ||||
MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, | MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, | ||||
MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, | MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, | ||||
MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, | MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, | ||||
MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, | MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, | ||||
MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, | MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, | ||||
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines | enum { | ||||
MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, | MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, | ||||
MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, | MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, | ||||
MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, | MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, | ||||
MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, | MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, | ||||
MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, | MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, | ||||
MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, | MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, | ||||
MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, | MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, | ||||
MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, | MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, | ||||
MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, | MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, | ||||
MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, | MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, | ||||
MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, | |||||
MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, | |||||
MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, | |||||
MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, | |||||
MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, | MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, | ||||
MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, | MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, | ||||
MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, | MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, | ||||
MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, | MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, | ||||
MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, | MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, | ||||
MLX5_CMD_OP_CREATE_GENERAL_OBJ = 0xa00, | MLX5_CMD_OP_CREATE_GENERAL_OBJ = 0xa00, | ||||
MLX5_CMD_OP_MODIFY_GENERAL_OBJ = 0xa01, | MLX5_CMD_OP_MODIFY_GENERAL_OBJ = 0xa01, | ||||
MLX5_CMD_OP_QUERY_GENERAL_OBJ = 0xa02, | MLX5_CMD_OP_QUERY_GENERAL_OBJ = 0xa02, | ||||
MLX5_CMD_OP_DESTROY_GENERAL_OBJ = 0xa03, | MLX5_CMD_OP_DESTROY_GENERAL_OBJ = 0xa03, | ||||
MLX5_CMD_OP_CREATE_UCTX = 0xa04, | |||||
MLX5_CMD_OP_DESTROY_UCTX = 0xa06, | |||||
MLX5_CMD_OP_CREATE_UMEM = 0xa08, | |||||
MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, | |||||
}; | |||||
/* Valid range for general commands that don't work over an object */ | |||||
enum { | |||||
MLX5_CMD_OP_GENERAL_START = 0xb00, | |||||
MLX5_CMD_OP_GENERAL_END = 0xd00, | |||||
}; | }; | ||||
enum { | enum { | ||||
MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, | MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, | ||||
MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, | MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, | ||||
MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, | MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, | ||||
MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, | MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, | ||||
MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, | MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, | ||||
▲ Show 20 Lines • Show All 673 Lines • ▼ Show 20 Lines | struct mlx5_ifc_roce_cap_bits { | ||||
u8 r_roce_min_src_udp_port[0x10]; | u8 r_roce_min_src_udp_port[0x10]; | ||||
u8 reserved_5[0x10]; | u8 reserved_5[0x10]; | ||||
u8 roce_address_table_size[0x10]; | u8 roce_address_table_size[0x10]; | ||||
u8 reserved_6[0x700]; | u8 reserved_6[0x700]; | ||||
}; | }; | ||||
struct mlx5_ifc_device_event_cap_bits { | |||||
u8 user_affiliated_events[4][0x40]; | |||||
u8 user_unaffiliated_events[4][0x40]; | |||||
}; | |||||
enum { | enum { | ||||
MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, | ||||
MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, | ||||
MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, | ||||
MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, | ||||
MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, | ||||
MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, | ||||
MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, | ||||
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines | |||||
enum { | enum { | ||||
MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, | MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, | ||||
MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, | MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, | ||||
MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, | MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, | ||||
}; | }; | ||||
enum { | enum { | ||||
MLX5_UCTX_CAP_RAW_TX = 1UL << 0, | |||||
MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, | |||||
}; | |||||
enum { | |||||
MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, | MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, | ||||
MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, | MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, | ||||
MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, | MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, | ||||
}; | }; | ||||
enum { | enum { | ||||
MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, | MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, | ||||
MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, | MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, | ||||
MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, | MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, | ||||
}; | }; | ||||
struct mlx5_ifc_cmd_hca_cap_bits { | struct mlx5_ifc_cmd_hca_cap_bits { | ||||
u8 reserved_0[0x80]; | u8 reserved_0[0x80]; | ||||
u8 log_max_srq_sz[0x8]; | u8 log_max_srq_sz[0x8]; | ||||
u8 log_max_qp_sz[0x8]; | u8 log_max_qp_sz[0x8]; | ||||
u8 reserved_1[0xb]; | u8 event_cap[0x1]; | ||||
u8 reserved_1[0xa]; | |||||
u8 log_max_qp[0x5]; | u8 log_max_qp[0x5]; | ||||
u8 reserved_2[0xb]; | u8 reserved_2[0xb]; | ||||
u8 log_max_srq[0x5]; | u8 log_max_srq[0x5]; | ||||
u8 reserved_3[0x10]; | u8 reserved_3[0x10]; | ||||
u8 reserved_4[0x8]; | u8 reserved_4[0x8]; | ||||
u8 log_max_cq_sz[0x8]; | u8 log_max_cq_sz[0x8]; | ||||
▲ Show 20 Lines • Show All 261 Lines • ▼ Show 20 Lines | struct mlx5_ifc_cmd_hca_cap_bits { | ||||
u8 cqe_128_always[0x1]; | u8 cqe_128_always[0x1]; | ||||
u8 cqe_compression_128b[0x1]; | u8 cqe_compression_128b[0x1]; | ||||
u8 cqe_compression[0x1]; | u8 cqe_compression[0x1]; | ||||
u8 cqe_compression_timeout[0x10]; | u8 cqe_compression_timeout[0x10]; | ||||
u8 cqe_compression_max_num[0x10]; | u8 cqe_compression_max_num[0x10]; | ||||
u8 reserved_69[0x220]; | u8 reserved_5e0[0xc0]; | ||||
u8 uctx_cap[0x20]; | |||||
u8 reserved_6c0[0xc0]; | |||||
u8 vhca_tunnel_commands[0x40]; | |||||
u8 reserved_at_7c0[0x40]; | |||||
}; | }; | ||||
enum mlx5_flow_destination_type { | enum mlx5_flow_destination_type { | ||||
MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, | MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, | ||||
MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, | MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, | ||||
MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, | MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, | ||||
}; | }; | ||||
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines | struct mlx5_ifc_wq_bits { | ||||
u8 reserved_4[0xc]; | u8 reserved_4[0xc]; | ||||
u8 log_wq_stride[0x4]; | u8 log_wq_stride[0x4]; | ||||
u8 reserved_5[0x3]; | u8 reserved_5[0x3]; | ||||
u8 log_wq_pg_sz[0x5]; | u8 log_wq_pg_sz[0x5]; | ||||
u8 reserved_6[0x3]; | u8 reserved_6[0x3]; | ||||
u8 log_wq_sz[0x5]; | u8 log_wq_sz[0x5]; | ||||
u8 reserved_7[0x15]; | u8 dbr_umem_valid[0x1]; | ||||
u8 wq_umem_valid[0x1]; | |||||
u8 reserved_7[0x13]; | |||||
u8 single_wqe_log_num_of_strides[0x3]; | u8 single_wqe_log_num_of_strides[0x3]; | ||||
u8 two_byte_shift_en[0x1]; | u8 two_byte_shift_en[0x1]; | ||||
u8 reserved_8[0x4]; | u8 reserved_8[0x4]; | ||||
u8 single_stride_log_num_of_bytes[0x3]; | u8 single_stride_log_num_of_bytes[0x3]; | ||||
u8 reserved_9[0x4c0]; | u8 reserved_9[0x4c0]; | ||||
struct mlx5_ifc_cmd_pas_bits pas[0]; | struct mlx5_ifc_cmd_pas_bits pas[0]; | ||||
▲ Show 20 Lines • Show All 664 Lines • ▼ Show 20 Lines | struct mlx5_ifc_qpc_bits { | ||||
u8 reserved_30[0xf]; | u8 reserved_30[0xf]; | ||||
u8 cgs[0x1]; | u8 cgs[0x1]; | ||||
u8 cs_req[0x8]; | u8 cs_req[0x8]; | ||||
u8 cs_res[0x8]; | u8 cs_res[0x8]; | ||||
u8 dc_access_key[0x40]; | u8 dc_access_key[0x40]; | ||||
u8 rdma_active[0x1]; | u8 reserved_at_680[0x3]; | ||||
u8 comm_est[0x1]; | u8 dbr_umem_valid[0x1]; | ||||
u8 suspended[0x1]; | |||||
u8 reserved_31[0x5]; | |||||
u8 send_msg_psn[0x18]; | |||||
u8 reserved_32[0x8]; | u8 reserved_at_684[0xbc]; | ||||
u8 rcv_msg_psn[0x18]; | |||||
u8 rdma_va[0x40]; | |||||
u8 rdma_key[0x20]; | |||||
u8 reserved_33[0x20]; | |||||
}; | }; | ||||
struct mlx5_ifc_roce_addr_layout_bits { | struct mlx5_ifc_roce_addr_layout_bits { | ||||
u8 source_l3_address[16][0x8]; | u8 source_l3_address[16][0x8]; | ||||
u8 reserved_0[0x3]; | u8 reserved_0[0x3]; | ||||
u8 vlan_valid[0x1]; | u8 vlan_valid[0x1]; | ||||
u8 vlan_id[0xc]; | u8 vlan_id[0xc]; | ||||
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines | struct mlx5_ifc_xrc_srqc_bits { | ||||
u8 cont_srq[0x1]; | u8 cont_srq[0x1]; | ||||
u8 reserved_1[0x1]; | u8 reserved_1[0x1]; | ||||
u8 rlky[0x1]; | u8 rlky[0x1]; | ||||
u8 basic_cyclic_rcv_wqe[0x1]; | u8 basic_cyclic_rcv_wqe[0x1]; | ||||
u8 log_rq_stride[0x3]; | u8 log_rq_stride[0x3]; | ||||
u8 xrcd[0x18]; | u8 xrcd[0x18]; | ||||
u8 page_offset[0x6]; | u8 page_offset[0x6]; | ||||
u8 reserved_2[0x2]; | u8 reserved_at_46[0x1]; | ||||
u8 dbr_umem_valid[0x1]; | |||||
u8 cqn[0x18]; | u8 cqn[0x18]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
u8 reserved_4[0x2]; | u8 reserved_4[0x2]; | ||||
u8 log_page_size[0x6]; | u8 log_page_size[0x6]; | ||||
u8 user_index[0x18]; | u8 user_index[0x18]; | ||||
▲ Show 20 Lines • Show All 404 Lines • ▼ Show 20 Lines | struct mlx5_ifc_nic_vport_context_bits { | ||||
u8 current_uc_mac_address[0][0x40]; | u8 current_uc_mac_address[0][0x40]; | ||||
}; | }; | ||||
enum { | enum { | ||||
MLX5_ACCESS_MODE_PA = 0x0, | MLX5_ACCESS_MODE_PA = 0x0, | ||||
MLX5_ACCESS_MODE_MTT = 0x1, | MLX5_ACCESS_MODE_MTT = 0x1, | ||||
MLX5_ACCESS_MODE_KLM = 0x2, | MLX5_ACCESS_MODE_KLM = 0x2, | ||||
MLX5_ACCESS_MODE_KSM = 0x3, | |||||
MLX5_ACCESS_MODE_SW_ICM = 0x4, | |||||
MLX5_ACCESS_MODE_MEMIC = 0x5, | |||||
}; | }; | ||||
struct mlx5_ifc_mkc_bits { | struct mlx5_ifc_mkc_bits { | ||||
u8 reserved_at_0[0x1]; | u8 reserved_at_0[0x1]; | ||||
u8 free[0x1]; | u8 free[0x1]; | ||||
u8 reserved_at_2[0x1]; | u8 reserved_at_2[0x1]; | ||||
u8 access_mode_4_2[0x3]; | u8 access_mode_4_2[0x3]; | ||||
u8 reserved_at_6[0x7]; | u8 reserved_at_6[0x7]; | ||||
▲ Show 20 Lines • Show All 344 Lines • ▼ Show 20 Lines | |||||
enum { | enum { | ||||
MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, | MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, | ||||
MLX5_CQ_STATE_ARMED = 0x9, | MLX5_CQ_STATE_ARMED = 0x9, | ||||
MLX5_CQ_STATE_FIRED = 0xa, | MLX5_CQ_STATE_FIRED = 0xa, | ||||
}; | }; | ||||
struct mlx5_ifc_cqc_bits { | struct mlx5_ifc_cqc_bits { | ||||
u8 status[0x4]; | u8 status[0x4]; | ||||
u8 reserved_0[0x4]; | u8 reserved_at_4[0x2]; | ||||
u8 dbr_umem_valid[0x1]; | |||||
u8 reserved_at_7[0x1]; | |||||
u8 cqe_sz[0x3]; | u8 cqe_sz[0x3]; | ||||
u8 cc[0x1]; | u8 cc[0x1]; | ||||
u8 reserved_1[0x1]; | u8 reserved_1[0x1]; | ||||
u8 scqe_break_moderation_en[0x1]; | u8 scqe_break_moderation_en[0x1]; | ||||
u8 oi[0x1]; | u8 oi[0x1]; | ||||
u8 cq_period_mode[0x2]; | u8 cq_period_mode[0x2]; | ||||
u8 cqe_compression_en[0x1]; | u8 cqe_compression_en[0x1]; | ||||
u8 mini_cqe_res_format[0x2]; | u8 mini_cqe_res_format[0x2]; | ||||
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines | struct mlx5_ifc_config_item_bits { | ||||
u8 length[0x9]; | u8 length[0x9]; | ||||
u8 type[0x20]; | u8 type[0x20]; | ||||
u8 reserved_4[0x10]; | u8 reserved_4[0x10]; | ||||
u8 crc16[0x10]; | u8 crc16[0x10]; | ||||
}; | }; | ||||
enum { | |||||
MLX5_XRQC_STATE_GOOD = 0x0, | |||||
MLX5_XRQC_STATE_ERROR = 0x1, | |||||
}; | |||||
enum { | |||||
MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, | |||||
MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, | |||||
}; | |||||
enum { | |||||
MLX5_XRQC_OFFLOAD_RNDV = 0x1, | |||||
}; | |||||
struct mlx5_ifc_tag_matching_topology_context_bits { | |||||
u8 log_matching_list_sz[0x4]; | |||||
u8 reserved_at_4[0xc]; | |||||
u8 append_next_index[0x10]; | |||||
u8 sw_phase_cnt[0x10]; | |||||
u8 hw_phase_cnt[0x10]; | |||||
u8 reserved_at_40[0x40]; | |||||
}; | |||||
struct mlx5_ifc_xrqc_bits { | |||||
u8 state[0x4]; | |||||
u8 rlkey[0x1]; | |||||
u8 reserved_at_5[0xf]; | |||||
u8 topology[0x4]; | |||||
u8 reserved_at_18[0x4]; | |||||
u8 offload[0x4]; | |||||
u8 reserved_at_20[0x8]; | |||||
u8 user_index[0x18]; | |||||
u8 reserved_at_40[0x8]; | |||||
u8 cqn[0x18]; | |||||
u8 reserved_at_60[0xa0]; | |||||
struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; | |||||
u8 reserved_at_180[0x280]; | |||||
struct mlx5_ifc_wq_bits wq; | |||||
}; | |||||
struct mlx5_ifc_nodnic_port_config_reg_bits { | struct mlx5_ifc_nodnic_port_config_reg_bits { | ||||
struct mlx5_ifc_nodnic_event_word_bits event; | struct mlx5_ifc_nodnic_event_word_bits event; | ||||
u8 network_en[0x1]; | u8 network_en[0x1]; | ||||
u8 dma_en[0x1]; | u8 dma_en[0x1]; | ||||
u8 promisc_en[0x1]; | u8 promisc_en[0x1]; | ||||
u8 promisc_multicast_en[0x1]; | u8 promisc_multicast_en[0x1]; | ||||
u8 reserved_0[0x17]; | u8 reserved_0[0x17]; | ||||
▲ Show 20 Lines • Show All 389 Lines • ▼ Show 20 Lines | struct mlx5_ifc_sqd2rts_qp_out_bits { | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_sqd2rts_qp_in_bits { | struct mlx5_ifc_sqd2rts_qp_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 qpn[0x18]; | u8 qpn[0x18]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
▲ Show 20 Lines • Show All 417 Lines • ▼ Show 20 Lines | struct mlx5_ifc_rst2init_qp_in_bits { | ||||
u8 reserved_4[0x20]; | u8 reserved_4[0x20]; | ||||
struct mlx5_ifc_qpc_bits qpc; | struct mlx5_ifc_qpc_bits qpc; | ||||
u8 reserved_5[0x80]; | u8 reserved_5[0x80]; | ||||
}; | }; | ||||
struct mlx5_ifc_query_xrq_out_bits { | |||||
u8 status[0x8]; | |||||
u8 reserved_at_8[0x18]; | |||||
u8 syndrome[0x20]; | |||||
u8 reserved_at_40[0x40]; | |||||
struct mlx5_ifc_xrqc_bits xrq_context; | |||||
}; | |||||
struct mlx5_ifc_query_xrq_in_bits { | |||||
u8 opcode[0x10]; | |||||
u8 reserved_at_10[0x10]; | |||||
u8 reserved_at_20[0x10]; | |||||
u8 op_mod[0x10]; | |||||
u8 reserved_at_40[0x8]; | |||||
u8 xrqn[0x18]; | |||||
u8 reserved_at_60[0x20]; | |||||
}; | |||||
struct mlx5_ifc_resume_qp_out_bits { | struct mlx5_ifc_resume_qp_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_0[0x18]; | u8 reserved_0[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
}; | }; | ||||
Show All 23 Lines | struct mlx5_ifc_query_xrc_srq_out_bits { | ||||
u8 reserved_2[0x600]; | u8 reserved_2[0x600]; | ||||
u8 pas[0][0x40]; | u8 pas[0][0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_query_xrc_srq_in_bits { | struct mlx5_ifc_query_xrc_srq_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 xrc_srqn[0x18]; | u8 xrc_srqn[0x18]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
▲ Show 20 Lines • Show All 1,058 Lines • ▼ Show 20 Lines | struct mlx5_ifc_query_dc_cnak_trace_in_bits { | ||||
u8 reserved_0[0x10]; | u8 reserved_0[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x40]; | u8 reserved_2[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_packet_reformat_context_in_bits { | |||||
u8 reserved_at_0[0x5]; | |||||
u8 reformat_type[0x3]; | |||||
u8 reserved_at_8[0xe]; | |||||
u8 reformat_data_size[0xa]; | |||||
u8 reserved_at_20[0x10]; | |||||
u8 reformat_data[2][0x8]; | |||||
u8 more_reformat_data[0][0x8]; | |||||
}; | |||||
struct mlx5_ifc_query_packet_reformat_context_out_bits { | |||||
u8 status[0x8]; | |||||
u8 reserved_at_8[0x18]; | |||||
u8 syndrome[0x20]; | |||||
u8 reserved_at_40[0xa0]; | |||||
struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; | |||||
}; | |||||
struct mlx5_ifc_query_packet_reformat_context_in_bits { | |||||
u8 opcode[0x10]; | |||||
u8 reserved_at_10[0x10]; | |||||
u8 reserved_at_20[0x10]; | |||||
u8 op_mod[0x10]; | |||||
u8 packet_reformat_id[0x20]; | |||||
u8 reserved_at_60[0xa0]; | |||||
}; | |||||
struct mlx5_ifc_alloc_packet_reformat_context_out_bits { | |||||
u8 status[0x8]; | |||||
u8 reserved_at_8[0x18]; | |||||
u8 syndrome[0x20]; | |||||
u8 packet_reformat_id[0x20]; | |||||
u8 reserved_at_60[0x20]; | |||||
}; | |||||
enum mlx5_reformat_ctx_type { | |||||
MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, | |||||
MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, | |||||
MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, | |||||
MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, | |||||
MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, | |||||
}; | |||||
struct mlx5_ifc_alloc_packet_reformat_context_in_bits { | |||||
u8 opcode[0x10]; | |||||
u8 reserved_at_10[0x10]; | |||||
u8 reserved_at_20[0x10]; | |||||
u8 op_mod[0x10]; | |||||
u8 reserved_at_40[0xa0]; | |||||
struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; | |||||
}; | |||||
struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { | |||||
u8 status[0x8]; | |||||
u8 reserved_at_8[0x18]; | |||||
u8 syndrome[0x20]; | |||||
u8 reserved_at_40[0x40]; | |||||
}; | |||||
struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { | |||||
u8 opcode[0x10]; | |||||
u8 reserved_at_10[0x10]; | |||||
u8 reserved_20[0x10]; | |||||
u8 op_mod[0x10]; | |||||
u8 packet_reformat_id[0x20]; | |||||
u8 reserved_60[0x20]; | |||||
}; | |||||
struct mlx5_ifc_query_cq_out_bits { | struct mlx5_ifc_query_cq_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_0[0x18]; | u8 reserved_0[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
▲ Show 20 Lines • Show All 310 Lines • ▼ Show 20 Lines | struct mlx5_ifc_modify_tis_bitmask_bits { | ||||
u8 reserved_at_20[0x1d]; | u8 reserved_at_20[0x1d]; | ||||
u8 lag_tx_port_affinity[0x1]; | u8 lag_tx_port_affinity[0x1]; | ||||
u8 strict_lag_tx_port_affinity[0x1]; | u8 strict_lag_tx_port_affinity[0x1]; | ||||
u8 prio[0x1]; | u8 prio[0x1]; | ||||
}; | }; | ||||
struct mlx5_ifc_modify_tis_in_bits { | struct mlx5_ifc_modify_tis_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 tisn[0x18]; | u8 tisn[0x18]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
Show All 17 Lines | |||||
enum | enum | ||||
{ | { | ||||
MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, | MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, | ||||
MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 | MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 | ||||
}; | }; | ||||
struct mlx5_ifc_modify_tir_in_bits { | struct mlx5_ifc_modify_tir_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 tirn[0x18]; | u8 tirn[0x18]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
Show All 11 Lines | struct mlx5_ifc_modify_sq_out_bits { | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_modify_sq_in_bits { | struct mlx5_ifc_modify_sq_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 sq_state[0x4]; | u8 sq_state[0x4]; | ||||
u8 reserved_2[0x4]; | u8 reserved_2[0x4]; | ||||
u8 sqn[0x18]; | u8 sqn[0x18]; | ||||
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines | struct mlx5_ifc_modify_rqt_out_bits { | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_modify_rqt_in_bits { | struct mlx5_ifc_modify_rqt_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 rqtn[0x18]; | u8 rqtn[0x18]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
Show All 16 Lines | |||||
enum { | enum { | ||||
MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, | ||||
MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, | ||||
}; | }; | ||||
struct mlx5_ifc_modify_rq_in_bits { | struct mlx5_ifc_modify_rq_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 rq_state[0x4]; | u8 rq_state[0x4]; | ||||
u8 reserved_2[0x4]; | u8 reserved_2[0x4]; | ||||
u8 rqn[0x18]; | u8 rqn[0x18]; | ||||
Show All 19 Lines | struct mlx5_ifc_rmp_bitmask_bits { | ||||
u8 reserved[0x20]; | u8 reserved[0x20]; | ||||
u8 reserved1[0x1f]; | u8 reserved1[0x1f]; | ||||
u8 lwm[0x1]; | u8 lwm[0x1]; | ||||
}; | }; | ||||
struct mlx5_ifc_modify_rmp_in_bits { | struct mlx5_ifc_modify_rmp_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 rmp_state[0x4]; | u8 rmp_state[0x4]; | ||||
u8 reserved_2[0x4]; | u8 reserved_2[0x4]; | ||||
u8 rmpn[0x18]; | u8 rmpn[0x18]; | ||||
▲ Show 20 Lines • Show All 193 Lines • ▼ Show 20 Lines | |||||
enum { | enum { | ||||
MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, | MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, | ||||
MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, | MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, | ||||
}; | }; | ||||
struct mlx5_ifc_modify_cq_in_bits { | struct mlx5_ifc_modify_cq_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 cqn[0x18]; | u8 cqn[0x18]; | ||||
union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; | union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; | ||||
struct mlx5_ifc_cqc_bits cq_context; | struct mlx5_ifc_cqc_bits cq_context; | ||||
u8 reserved_3[0x600]; | u8 reserved_at_280[0x60]; | ||||
u8 cq_umem_valid[0x1]; | |||||
u8 reserved_at_2e1[0x1f]; | |||||
u8 reserved_at_300[0x580]; | |||||
u8 pas[0][0x40]; | u8 pas[0][0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_modify_cong_status_out_bits { | struct mlx5_ifc_modify_cong_status_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_0[0x18]; | u8 reserved_0[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
▲ Show 20 Lines • Show All 325 Lines • ▼ Show 20 Lines | struct mlx5_ifc_detach_from_mcg_out_bits { | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_detach_from_mcg_in_bits { | struct mlx5_ifc_detach_from_mcg_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 qpn[0x18]; | u8 qpn[0x18]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
u8 multicast_gid[16][0x8]; | u8 multicast_gid[16][0x8]; | ||||
}; | }; | ||||
struct mlx5_ifc_destroy_xrc_srq_out_bits { | struct mlx5_ifc_destroy_xrc_srq_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_0[0x18]; | u8 reserved_0[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_destroy_xrc_srq_in_bits { | struct mlx5_ifc_destroy_xrc_srq_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 xrc_srqn[0x18]; | u8 xrc_srqn[0x18]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
}; | }; | ||||
struct mlx5_ifc_destroy_tis_out_bits { | struct mlx5_ifc_destroy_tis_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_0[0x18]; | u8 reserved_0[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_destroy_tis_in_bits { | struct mlx5_ifc_destroy_tis_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 tisn[0x18]; | u8 tisn[0x18]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
}; | }; | ||||
struct mlx5_ifc_destroy_tir_out_bits { | struct mlx5_ifc_destroy_tir_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_0[0x18]; | u8 reserved_0[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_destroy_tir_in_bits { | struct mlx5_ifc_destroy_tir_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 tirn[0x18]; | u8 tirn[0x18]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
}; | }; | ||||
struct mlx5_ifc_destroy_srq_out_bits { | struct mlx5_ifc_destroy_srq_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_0[0x18]; | u8 reserved_0[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_destroy_srq_in_bits { | struct mlx5_ifc_destroy_srq_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 srqn[0x18]; | u8 srqn[0x18]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines | struct mlx5_ifc_destroy_rqt_out_bits { | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_destroy_rqt_in_bits { | struct mlx5_ifc_destroy_rqt_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 rqtn[0x18]; | u8 rqtn[0x18]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
▲ Show 20 Lines • Show All 268 Lines • ▼ Show 20 Lines | struct mlx5_ifc_destroy_cq_out_bits { | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_destroy_cq_in_bits { | struct mlx5_ifc_destroy_cq_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 cqn[0x18]; | u8 cqn[0x18]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines | struct mlx5_ifc_dealloc_xrcd_out_bits { | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_dealloc_xrcd_in_bits { | struct mlx5_ifc_dealloc_xrcd_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 xrcd[0x18]; | u8 xrcd[0x18]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
Show All 27 Lines | struct mlx5_ifc_dealloc_transport_domain_out_bits { | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_dealloc_transport_domain_in_bits { | struct mlx5_ifc_dealloc_transport_domain_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 transport_domain[0x18]; | u8 transport_domain[0x18]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines | struct mlx5_ifc_dealloc_pd_out_bits { | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_dealloc_pd_in_bits { | struct mlx5_ifc_dealloc_pd_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 pd[0x18]; | u8 pd[0x18]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
Show All 16 Lines | struct mlx5_ifc_dealloc_flow_counter_in_bits { | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x10]; | u8 reserved_2[0x10]; | ||||
u8 flow_counter_id[0x10]; | u8 flow_counter_id[0x10]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
}; | }; | ||||
struct mlx5_ifc_create_xrq_out_bits { | |||||
u8 status[0x8]; | |||||
u8 reserved_at_8[0x18]; | |||||
u8 syndrome[0x20]; | |||||
u8 reserved_at_40[0x8]; | |||||
u8 xrqn[0x18]; | |||||
u8 reserved_at_60[0x20]; | |||||
}; | |||||
struct mlx5_ifc_create_xrq_in_bits { | |||||
u8 opcode[0x10]; | |||||
u8 uid[0x10]; | |||||
u8 reserved_at_20[0x10]; | |||||
u8 op_mod[0x10]; | |||||
u8 reserved_at_40[0x40]; | |||||
struct mlx5_ifc_xrqc_bits xrq_context; | |||||
}; | |||||
struct mlx5_ifc_deactivate_tracer_out_bits { | struct mlx5_ifc_deactivate_tracer_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_0[0x18]; | u8 reserved_0[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
}; | }; | ||||
Show All 19 Lines | struct mlx5_ifc_create_xrc_srq_out_bits { | ||||
u8 reserved_1[0x8]; | u8 reserved_1[0x8]; | ||||
u8 xrc_srqn[0x18]; | u8 xrc_srqn[0x18]; | ||||
u8 reserved_2[0x20]; | u8 reserved_2[0x20]; | ||||
}; | }; | ||||
struct mlx5_ifc_create_xrc_srq_in_bits { | struct mlx5_ifc_create_xrc_srq_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x40]; | u8 reserved_2[0x40]; | ||||
struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; | struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; | ||||
u8 reserved_3[0x600]; | u8 reserved_at_280[0x60]; | ||||
u8 xrc_srq_umem_valid[0x1]; | |||||
u8 reserved_at_2e1[0x1f]; | |||||
u8 reserved_at_300[0x580]; | |||||
u8 pas[0][0x40]; | u8 pas[0][0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_create_tis_out_bits { | struct mlx5_ifc_create_tis_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_0[0x18]; | u8 reserved_0[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x8]; | u8 reserved_1[0x8]; | ||||
u8 tisn[0x18]; | u8 tisn[0x18]; | ||||
u8 reserved_2[0x20]; | u8 reserved_2[0x20]; | ||||
}; | }; | ||||
struct mlx5_ifc_create_tis_in_bits { | struct mlx5_ifc_create_tis_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0xc0]; | u8 reserved_2[0xc0]; | ||||
struct mlx5_ifc_tisc_bits ctx; | struct mlx5_ifc_tisc_bits ctx; | ||||
}; | }; | ||||
struct mlx5_ifc_create_tir_out_bits { | struct mlx5_ifc_create_tir_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_0[0x18]; | u8 reserved_0[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x8]; | u8 reserved_1[0x8]; | ||||
u8 tirn[0x18]; | u8 tirn[0x18]; | ||||
u8 reserved_2[0x20]; | u8 reserved_2[0x20]; | ||||
}; | }; | ||||
struct mlx5_ifc_create_tir_in_bits { | struct mlx5_ifc_create_tir_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0xc0]; | u8 reserved_2[0xc0]; | ||||
struct mlx5_ifc_tirc_bits tir_context; | struct mlx5_ifc_tirc_bits tir_context; | ||||
}; | }; | ||||
struct mlx5_ifc_create_srq_out_bits { | struct mlx5_ifc_create_srq_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_0[0x18]; | u8 reserved_0[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x8]; | u8 reserved_1[0x8]; | ||||
u8 srqn[0x18]; | u8 srqn[0x18]; | ||||
u8 reserved_2[0x20]; | u8 reserved_2[0x20]; | ||||
}; | }; | ||||
struct mlx5_ifc_create_srq_in_bits { | struct mlx5_ifc_create_srq_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x40]; | u8 reserved_2[0x40]; | ||||
struct mlx5_ifc_srqc_bits srq_context_entry; | struct mlx5_ifc_srqc_bits srq_context_entry; | ||||
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines | struct mlx5_ifc_create_rqt_out_bits { | ||||
u8 reserved_1[0x8]; | u8 reserved_1[0x8]; | ||||
u8 rqtn[0x18]; | u8 rqtn[0x18]; | ||||
u8 reserved_2[0x20]; | u8 reserved_2[0x20]; | ||||
}; | }; | ||||
struct mlx5_ifc_create_rqt_in_bits { | struct mlx5_ifc_create_rqt_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0xc0]; | u8 reserved_2[0xc0]; | ||||
struct mlx5_ifc_rqtc_bits rqt_context; | struct mlx5_ifc_rqtc_bits rqt_context; | ||||
}; | }; | ||||
Show All 31 Lines | struct mlx5_ifc_create_rmp_out_bits { | ||||
u8 reserved_1[0x8]; | u8 reserved_1[0x8]; | ||||
u8 rmpn[0x18]; | u8 rmpn[0x18]; | ||||
u8 reserved_2[0x20]; | u8 reserved_2[0x20]; | ||||
}; | }; | ||||
struct mlx5_ifc_create_rmp_in_bits { | struct mlx5_ifc_create_rmp_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0xc0]; | u8 reserved_2[0xc0]; | ||||
struct mlx5_ifc_rmpc_bits ctx; | struct mlx5_ifc_rmpc_bits ctx; | ||||
}; | }; | ||||
Show All 23 Lines | struct mlx5_ifc_create_qp_in_bits { | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
u8 opt_param_mask[0x20]; | u8 opt_param_mask[0x20]; | ||||
u8 reserved_4[0x20]; | u8 reserved_4[0x20]; | ||||
struct mlx5_ifc_qpc_bits qpc; | struct mlx5_ifc_qpc_bits qpc; | ||||
u8 reserved_5[0x80]; | u8 reserved_at_800[0x60]; | ||||
u8 wq_umem_valid[0x1]; | |||||
u8 reserved_at_861[0x1f]; | |||||
u8 pas[0][0x40]; | u8 pas[0][0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_create_qos_para_vport_out_bits { | struct mlx5_ifc_create_qos_para_vport_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_at_8[0x18]; | u8 reserved_at_8[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines | struct mlx5_ifc_create_mkey_in_bits { | ||||
u8 reserved_0[0x10]; | u8 reserved_0[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x20]; | u8 reserved_2[0x20]; | ||||
u8 pg_access[0x1]; | u8 pg_access[0x1]; | ||||
u8 reserved_3[0x1f]; | u8 mkey_umem_valid[0x1]; | ||||
u8 reserved_at_62[0x1e]; | |||||
struct mlx5_ifc_mkc_bits memory_key_mkey_entry; | struct mlx5_ifc_mkc_bits memory_key_mkey_entry; | ||||
u8 reserved_4[0x80]; | u8 reserved_4[0x80]; | ||||
u8 translations_octword_actual_size[0x20]; | u8 translations_octword_actual_size[0x20]; | ||||
u8 reserved_5[0x560]; | u8 reserved_5[0x560]; | ||||
▲ Show 20 Lines • Show All 179 Lines • ▼ Show 20 Lines | struct mlx5_ifc_create_cq_out_bits { | ||||
u8 reserved_1[0x8]; | u8 reserved_1[0x8]; | ||||
u8 cqn[0x18]; | u8 cqn[0x18]; | ||||
u8 reserved_2[0x20]; | u8 reserved_2[0x20]; | ||||
}; | }; | ||||
struct mlx5_ifc_create_cq_in_bits { | struct mlx5_ifc_create_cq_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x40]; | u8 reserved_2[0x40]; | ||||
struct mlx5_ifc_cqc_bits cq_context; | struct mlx5_ifc_cqc_bits cq_context; | ||||
u8 reserved_3[0x600]; | u8 reserved_at_280[0x60]; | ||||
u8 cq_umem_valid[0x1]; | |||||
u8 reserved_at_2e1[0x59f]; | |||||
u8 pas[0][0x40]; | u8 pas[0][0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_config_int_moderation_out_bits { | struct mlx5_ifc_config_int_moderation_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_0[0x18]; | u8 reserved_0[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
Show All 30 Lines | struct mlx5_ifc_attach_to_mcg_out_bits { | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_attach_to_mcg_in_bits { | struct mlx5_ifc_attach_to_mcg_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 qpn[0x18]; | u8 qpn[0x18]; | ||||
u8 reserved_3[0x20]; | u8 reserved_3[0x20]; | ||||
u8 multicast_gid[16][0x8]; | u8 multicast_gid[16][0x8]; | ||||
}; | }; | ||||
struct mlx5_ifc_arm_xrq_out_bits { | |||||
u8 status[0x8]; | |||||
u8 reserved_at_8[0x18]; | |||||
u8 syndrome[0x20]; | |||||
u8 reserved_at_40[0x40]; | |||||
}; | |||||
struct mlx5_ifc_arm_xrq_in_bits { | |||||
u8 opcode[0x10]; | |||||
u8 reserved_at_10[0x10]; | |||||
u8 reserved_at_20[0x10]; | |||||
u8 op_mod[0x10]; | |||||
u8 reserved_at_40[0x8]; | |||||
u8 xrqn[0x18]; | |||||
u8 reserved_at_60[0x10]; | |||||
u8 lwm[0x10]; | |||||
}; | |||||
struct mlx5_ifc_arm_xrc_srq_out_bits { | struct mlx5_ifc_arm_xrc_srq_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_0[0x18]; | u8 reserved_0[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x40]; | u8 reserved_1[0x40]; | ||||
}; | }; | ||||
enum { | enum { | ||||
MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, | MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, | ||||
}; | }; | ||||
struct mlx5_ifc_arm_xrc_srq_in_bits { | struct mlx5_ifc_arm_xrc_srq_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 xrc_srqn[0x18]; | u8 xrc_srqn[0x18]; | ||||
u8 reserved_3[0x10]; | u8 reserved_3[0x10]; | ||||
Show All 10 Lines | |||||
}; | }; | ||||
enum { | enum { | ||||
MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, | MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, | ||||
}; | }; | ||||
struct mlx5_ifc_arm_rq_in_bits { | struct mlx5_ifc_arm_rq_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x8]; | u8 reserved_2[0x8]; | ||||
u8 srq_number[0x18]; | u8 srq_number[0x18]; | ||||
u8 reserved_3[0x10]; | u8 reserved_3[0x10]; | ||||
Show All 31 Lines | struct mlx5_ifc_alloc_xrcd_out_bits { | ||||
u8 reserved_1[0x8]; | u8 reserved_1[0x8]; | ||||
u8 xrcd[0x18]; | u8 xrcd[0x18]; | ||||
u8 reserved_2[0x20]; | u8 reserved_2[0x20]; | ||||
}; | }; | ||||
struct mlx5_ifc_alloc_xrcd_in_bits { | struct mlx5_ifc_alloc_xrcd_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x40]; | u8 reserved_2[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_alloc_uar_out_bits { | struct mlx5_ifc_alloc_uar_out_bits { | ||||
Show All 27 Lines | struct mlx5_ifc_alloc_transport_domain_out_bits { | ||||
u8 reserved_1[0x8]; | u8 reserved_1[0x8]; | ||||
u8 transport_domain[0x18]; | u8 transport_domain[0x18]; | ||||
u8 reserved_2[0x20]; | u8 reserved_2[0x20]; | ||||
}; | }; | ||||
struct mlx5_ifc_alloc_transport_domain_in_bits { | struct mlx5_ifc_alloc_transport_domain_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x40]; | u8 reserved_2[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_alloc_q_counter_out_bits { | struct mlx5_ifc_alloc_q_counter_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_0[0x18]; | u8 reserved_0[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x18]; | u8 reserved_1[0x18]; | ||||
u8 counter_set_id[0x8]; | u8 counter_set_id[0x8]; | ||||
u8 reserved_2[0x20]; | u8 reserved_2[0x20]; | ||||
}; | }; | ||||
struct mlx5_ifc_alloc_q_counter_in_bits { | struct mlx5_ifc_alloc_q_counter_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x40]; | u8 reserved_2[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_alloc_pd_out_bits { | struct mlx5_ifc_alloc_pd_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_0[0x18]; | u8 reserved_0[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x8]; | u8 reserved_1[0x8]; | ||||
u8 pd[0x18]; | u8 pd[0x18]; | ||||
u8 reserved_2[0x20]; | u8 reserved_2[0x20]; | ||||
}; | }; | ||||
struct mlx5_ifc_alloc_pd_in_bits { | struct mlx5_ifc_alloc_pd_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_1[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x40]; | u8 reserved_2[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_alloc_flow_counter_out_bits { | struct mlx5_ifc_alloc_flow_counter_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_0[0x18]; | u8 reserved_at_8[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_1[0x10]; | u8 flow_counter_id[0x20]; | ||||
u8 flow_counter_id[0x10]; | |||||
u8 reserved_2[0x20]; | u8 reserved_at_60[0x20]; | ||||
}; | }; | ||||
struct mlx5_ifc_alloc_flow_counter_in_bits { | struct mlx5_ifc_alloc_flow_counter_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_0[0x10]; | u8 reserved_at_10[0x10]; | ||||
u8 reserved_1[0x10]; | u8 reserved_at_20[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_2[0x40]; | u8 reserved_at_40[0x38]; | ||||
u8 flow_counter_bulk[0x8]; | |||||
}; | }; | ||||
struct mlx5_ifc_add_vxlan_udp_dport_out_bits { | struct mlx5_ifc_add_vxlan_udp_dport_out_bits { | ||||
u8 status[0x8]; | u8 status[0x8]; | ||||
u8 reserved_0[0x18]; | u8 reserved_0[0x18]; | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
Show All 40 Lines | struct mlx5_ifc_set_rate_limit_out_bits { | ||||
u8 syndrome[0x20]; | u8 syndrome[0x20]; | ||||
u8 reserved_at_40[0x40]; | u8 reserved_at_40[0x40]; | ||||
}; | }; | ||||
struct mlx5_ifc_set_rate_limit_in_bits { | struct mlx5_ifc_set_rate_limit_in_bits { | ||||
u8 opcode[0x10]; | u8 opcode[0x10]; | ||||
u8 reserved_at_10[0x10]; | u8 uid[0x10]; | ||||
u8 reserved_at_20[0x10]; | u8 reserved_at_20[0x10]; | ||||
u8 op_mod[0x10]; | u8 op_mod[0x10]; | ||||
u8 reserved_at_40[0x10]; | u8 reserved_at_40[0x10]; | ||||
u8 rate_limit_index[0x10]; | u8 rate_limit_index[0x10]; | ||||
u8 reserved_at_60[0x20]; | u8 reserved_at_60[0x20]; | ||||
▲ Show 20 Lines • Show All 3,018 Lines • ▼ Show 20 Lines | struct mlx5_ifc_mtmp_ext_bits { | ||||
u8 reserved_at_80[0x10]; | u8 reserved_at_80[0x10]; | ||||
u8 temperature_threshold_lo[0x10]; | u8 temperature_threshold_lo[0x10]; | ||||
u8 reserved_at_a0[0x20]; | u8 reserved_at_a0[0x20]; | ||||
u8 sensor_name_hi[0x20]; | u8 sensor_name_hi[0x20]; | ||||
u8 sensor_name_lo[0x20]; | u8 sensor_name_lo[0x20]; | ||||
}; | |||||
struct mlx5_ifc_general_obj_in_cmd_hdr_bits { | |||||
u8 opcode[0x10]; | |||||
u8 uid[0x10]; | |||||
u8 vhca_tunnel_id[0x10]; | |||||
u8 obj_type[0x10]; | |||||
u8 obj_id[0x20]; | |||||
u8 reserved_at_60[0x20]; | |||||
}; | |||||
struct mlx5_ifc_general_obj_out_cmd_hdr_bits { | |||||
u8 status[0x8]; | |||||
u8 reserved_at_8[0x18]; | |||||
u8 syndrome[0x20]; | |||||
u8 obj_id[0x20]; | |||||
u8 reserved_at_60[0x20]; | |||||
}; | |||||
struct mlx5_ifc_umem_bits { | |||||
u8 reserved_at_0[0x80]; | |||||
u8 reserved_at_80[0x1b]; | |||||
u8 log_page_size[0x5]; | |||||
u8 page_offset[0x20]; | |||||
u8 num_of_mtt[0x40]; | |||||
struct mlx5_ifc_mtt_bits mtt[0]; | |||||
}; | |||||
struct mlx5_ifc_uctx_bits { | |||||
u8 cap[0x20]; | |||||
u8 reserved_at_20[0x160]; | |||||
}; | |||||
struct mlx5_ifc_create_umem_in_bits { | |||||
u8 opcode[0x10]; | |||||
u8 uid[0x10]; | |||||
u8 reserved_at_20[0x10]; | |||||
u8 op_mod[0x10]; | |||||
u8 reserved_at_40[0x40]; | |||||
struct mlx5_ifc_umem_bits umem; | |||||
}; | |||||
struct mlx5_ifc_create_uctx_in_bits { | |||||
u8 opcode[0x10]; | |||||
u8 reserved_at_10[0x10]; | |||||
u8 reserved_at_20[0x10]; | |||||
u8 op_mod[0x10]; | |||||
u8 reserved_at_40[0x40]; | |||||
struct mlx5_ifc_uctx_bits uctx; | |||||
}; | |||||
struct mlx5_ifc_destroy_uctx_in_bits { | |||||
u8 opcode[0x10]; | |||||
u8 reserved_at_10[0x10]; | |||||
u8 reserved_at_20[0x10]; | |||||
u8 op_mod[0x10]; | |||||
u8 reserved_at_40[0x10]; | |||||
u8 uid[0x10]; | |||||
u8 reserved_at_60[0x20]; | |||||
}; | |||||
struct mlx5_ifc_mtrc_string_db_param_bits { | |||||
u8 string_db_base_address[0x20]; | |||||
u8 reserved_at_20[0x8]; | |||||
u8 string_db_size[0x18]; | |||||
}; | |||||
struct mlx5_ifc_mtrc_cap_bits { | |||||
u8 trace_owner[0x1]; | |||||
u8 trace_to_memory[0x1]; | |||||
u8 reserved_at_2[0x4]; | |||||
u8 trc_ver[0x2]; | |||||
u8 reserved_at_8[0x14]; | |||||
u8 num_string_db[0x4]; | |||||
u8 first_string_trace[0x8]; | |||||
u8 num_string_trace[0x8]; | |||||
u8 reserved_at_30[0x28]; | |||||
u8 log_max_trace_buffer_size[0x8]; | |||||
u8 reserved_at_60[0x20]; | |||||
struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; | |||||
u8 reserved_at_280[0x180]; | |||||
}; | |||||
struct mlx5_ifc_mtrc_conf_bits { | |||||
u8 reserved_at_0[0x1c]; | |||||
u8 trace_mode[0x4]; | |||||
u8 reserved_at_20[0x18]; | |||||
u8 log_trace_buffer_size[0x8]; | |||||
u8 trace_mkey[0x20]; | |||||
u8 reserved_at_60[0x3a0]; | |||||
}; | |||||
struct mlx5_ifc_mtrc_stdb_bits { | |||||
u8 string_db_index[0x4]; | |||||
u8 reserved_at_4[0x4]; | |||||
u8 read_size[0x18]; | |||||
u8 start_offset[0x20]; | |||||
u8 string_db_data[0]; | |||||
}; | |||||
struct mlx5_ifc_mtrc_ctrl_bits { | |||||
u8 trace_status[0x2]; | |||||
u8 reserved_at_2[0x2]; | |||||
u8 arm_event[0x1]; | |||||
u8 reserved_at_5[0xb]; | |||||
u8 modify_field_select[0x10]; | |||||
u8 reserved_at_20[0x2b]; | |||||
u8 current_timestamp52_32[0x15]; | |||||
u8 current_timestamp31_0[0x20]; | |||||
u8 reserved_at_80[0x180]; | |||||
}; | |||||
struct mlx5_ifc_affiliated_event_header_bits { | |||||
u8 reserved_at_0[0x10]; | |||||
u8 obj_type[0x10]; | |||||
u8 obj_id[0x20]; | |||||
}; | }; | ||||
#endif /* MLX5_IFC_H */ | #endif /* MLX5_IFC_H */ |