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sys/dev/mlx5/mlx5_core/mlx5_eq.c
| /*- | /*- | ||||
| * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. | * Copyright (c) 2013-2021, Mellanox Technologies, Ltd. All rights reserved. | ||||
| * | * | ||||
| * Redistribution and use in source and binary forms, with or without | * Redistribution and use in source and binary forms, with or without | ||||
| * modification, are permitted provided that the following conditions | * modification, are permitted provided that the following conditions | ||||
| * are met: | * are met: | ||||
| * 1. Redistributions of source code must retain the above copyright | * 1. Redistributions of source code must retain the above copyright | ||||
| * notice, this list of conditions and the following disclaimer. | * notice, this list of conditions and the following disclaimer. | ||||
| * 2. Redistributions in binary form must reproduce the above copyright | * 2. Redistributions in binary form must reproduce the above copyright | ||||
| * notice, this list of conditions and the following disclaimer in the | * notice, this list of conditions and the following disclaimer in the | ||||
| ▲ Show 20 Lines • Show All 228 Lines • ▼ Show 20 Lines | while ((eqe = next_eqe_sw(eq))) { | ||||
| /* | /* | ||||
| * Make sure we read EQ entry contents after we've | * Make sure we read EQ entry contents after we've | ||||
| * checked the ownership bit. | * checked the ownership bit. | ||||
| */ | */ | ||||
| atomic_thread_fence_acq(); | atomic_thread_fence_acq(); | ||||
| mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n", | mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n", | ||||
| eq->eqn, eqe_type_str(eqe->type)); | eq->eqn, eqe_type_str(eqe->type)); | ||||
| switch (eqe->type) { | |||||
| if (dev->priv.eq_table.cb != NULL && | |||||
| dev->priv.eq_table.cb(dev, eqe->type, &eqe->data)) { | |||||
| /* FALLTHROUGH */ | |||||
| } else switch (eqe->type) { | |||||
| case MLX5_EVENT_TYPE_COMP: | case MLX5_EVENT_TYPE_COMP: | ||||
| mlx5_cq_completion(dev, eqe); | mlx5_cq_completion(dev, eqe); | ||||
| break; | break; | ||||
| case MLX5_EVENT_TYPE_PATH_MIG: | case MLX5_EVENT_TYPE_PATH_MIG: | ||||
| case MLX5_EVENT_TYPE_COMM_EST: | case MLX5_EVENT_TYPE_COMM_EST: | ||||
| case MLX5_EVENT_TYPE_SQ_DRAINED: | case MLX5_EVENT_TYPE_SQ_DRAINED: | ||||
| case MLX5_EVENT_TYPE_SRQ_LAST_WQE: | case MLX5_EVENT_TYPE_SRQ_LAST_WQE: | ||||
| ▲ Show 20 Lines • Show All 526 Lines • Show Last 20 Lines | |||||