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sys/dev/ixl/i40e_common.c
Show First 20 Lines • Show All 1,245 Lines • ▼ Show 20 Lines | static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) | ||||
case I40E_PHY_TYPE_10GBASE_SR: | case I40E_PHY_TYPE_10GBASE_SR: | ||||
case I40E_PHY_TYPE_10GBASE_LR: | case I40E_PHY_TYPE_10GBASE_LR: | ||||
case I40E_PHY_TYPE_1000BASE_SX: | case I40E_PHY_TYPE_1000BASE_SX: | ||||
case I40E_PHY_TYPE_1000BASE_LX: | case I40E_PHY_TYPE_1000BASE_LX: | ||||
case I40E_PHY_TYPE_40GBASE_SR4: | case I40E_PHY_TYPE_40GBASE_SR4: | ||||
case I40E_PHY_TYPE_40GBASE_LR4: | case I40E_PHY_TYPE_40GBASE_LR4: | ||||
case I40E_PHY_TYPE_25GBASE_LR: | case I40E_PHY_TYPE_25GBASE_LR: | ||||
case I40E_PHY_TYPE_25GBASE_SR: | case I40E_PHY_TYPE_25GBASE_SR: | ||||
case I40E_PHY_TYPE_10GBASE_AOC: | |||||
case I40E_PHY_TYPE_25GBASE_AOC: | |||||
case I40E_PHY_TYPE_40GBASE_AOC: | |||||
media = I40E_MEDIA_TYPE_FIBER; | media = I40E_MEDIA_TYPE_FIBER; | ||||
break; | break; | ||||
case I40E_PHY_TYPE_100BASE_TX: | case I40E_PHY_TYPE_100BASE_TX: | ||||
case I40E_PHY_TYPE_1000BASE_T: | case I40E_PHY_TYPE_1000BASE_T: | ||||
case I40E_PHY_TYPE_2_5GBASE_T: | case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS: | ||||
case I40E_PHY_TYPE_5GBASE_T: | case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS: | ||||
case I40E_PHY_TYPE_10GBASE_T: | case I40E_PHY_TYPE_10GBASE_T: | ||||
media = I40E_MEDIA_TYPE_BASET; | media = I40E_MEDIA_TYPE_BASET; | ||||
break; | break; | ||||
case I40E_PHY_TYPE_10GBASE_CR1_CU: | case I40E_PHY_TYPE_10GBASE_CR1_CU: | ||||
case I40E_PHY_TYPE_40GBASE_CR4_CU: | case I40E_PHY_TYPE_40GBASE_CR4_CU: | ||||
case I40E_PHY_TYPE_10GBASE_CR1: | case I40E_PHY_TYPE_10GBASE_CR1: | ||||
case I40E_PHY_TYPE_40GBASE_CR4: | case I40E_PHY_TYPE_40GBASE_CR4: | ||||
case I40E_PHY_TYPE_10GBASE_SFPP_CU: | case I40E_PHY_TYPE_10GBASE_SFPP_CU: | ||||
case I40E_PHY_TYPE_40GBASE_AOC: | |||||
case I40E_PHY_TYPE_10GBASE_AOC: | |||||
case I40E_PHY_TYPE_25GBASE_CR: | case I40E_PHY_TYPE_25GBASE_CR: | ||||
case I40E_PHY_TYPE_25GBASE_AOC: | |||||
case I40E_PHY_TYPE_25GBASE_ACC: | case I40E_PHY_TYPE_25GBASE_ACC: | ||||
media = I40E_MEDIA_TYPE_DA; | media = I40E_MEDIA_TYPE_DA; | ||||
break; | break; | ||||
case I40E_PHY_TYPE_1000BASE_KX: | case I40E_PHY_TYPE_1000BASE_KX: | ||||
case I40E_PHY_TYPE_10GBASE_KX4: | case I40E_PHY_TYPE_10GBASE_KX4: | ||||
case I40E_PHY_TYPE_10GBASE_KR: | case I40E_PHY_TYPE_10GBASE_KR: | ||||
case I40E_PHY_TYPE_40GBASE_KR4: | case I40E_PHY_TYPE_40GBASE_KR4: | ||||
case I40E_PHY_TYPE_20GBASE_KR2: | case I40E_PHY_TYPE_20GBASE_KR2: | ||||
Show All 31 Lines | static enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw, | ||||
} | } | ||||
DEBUGOUT("Global reset failed.\n"); | DEBUGOUT("Global reset failed.\n"); | ||||
DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg); | DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg); | ||||
return I40E_ERR_RESET_FAILED; | return I40E_ERR_RESET_FAILED; | ||||
} | } | ||||
#define I40E_PF_RESET_WAIT_COUNT 200 | #define I40E_PF_RESET_WAIT_COUNT 1000 | ||||
/** | /** | ||||
* i40e_pf_reset - Reset the PF | * i40e_pf_reset - Reset the PF | ||||
* @hw: pointer to the hardware structure | * @hw: pointer to the hardware structure | ||||
* | * | ||||
* Assuming someone else has triggered a global reset, | * Assuming someone else has triggered a global reset, | ||||
* assure the global reset is complete and then reset the PF | * assure the global reset is complete and then reset the PF | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) | enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) | ||||
▲ Show 20 Lines • Show All 230 Lines • ▼ Show 20 Lines | |||||
* | * | ||||
* The value returned is the 'mode' field as defined in the | * The value returned is the 'mode' field as defined in the | ||||
* GPIO register definitions: 0x0 = off, 0xf = on, and other | * GPIO register definitions: 0x0 = off, 0xf = on, and other | ||||
* values are variations of possible behaviors relating to | * values are variations of possible behaviors relating to | ||||
* blink, link, and wire. | * blink, link, and wire. | ||||
**/ | **/ | ||||
u32 i40e_led_get(struct i40e_hw *hw) | u32 i40e_led_get(struct i40e_hw *hw) | ||||
{ | { | ||||
u32 current_mode = 0; | |||||
u32 mode = 0; | u32 mode = 0; | ||||
int i; | int i; | ||||
/* as per the documentation GPIO 22-29 are the LED | /* as per the documentation GPIO 22-29 are the LED | ||||
* GPIO pins named LED0..LED7 | * GPIO pins named LED0..LED7 | ||||
*/ | */ | ||||
for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { | for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { | ||||
u32 gpio_val = i40e_led_is_mine(hw, i); | u32 gpio_val = i40e_led_is_mine(hw, i); | ||||
if (!gpio_val) | if (!gpio_val) | ||||
continue; | continue; | ||||
/* ignore gpio LED src mode entries related to the activity | |||||
* LEDs | |||||
*/ | |||||
current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) | |||||
>> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); | |||||
switch (current_mode) { | |||||
case I40E_COMBINED_ACTIVITY: | |||||
case I40E_FILTER_ACTIVITY: | |||||
case I40E_MAC_ACTIVITY: | |||||
case I40E_LINK_ACTIVITY: | |||||
continue; | |||||
default: | |||||
break; | |||||
} | |||||
mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> | mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> | ||||
I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; | I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; | ||||
break; | break; | ||||
} | } | ||||
return mode; | return mode; | ||||
} | } | ||||
/** | /** | ||||
* i40e_led_set - set new on/off mode | * i40e_led_set - set new on/off mode | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @mode: 0=off, 0xf=on (else see manual for mode details) | * @mode: 0=off, 0xf=on (else see manual for mode details) | ||||
* @blink: TRUE if the LED should blink when on, FALSE if steady | * @blink: TRUE if the LED should blink when on, FALSE if steady | ||||
* | * | ||||
* if this function is used to turn on the blink it should | * if this function is used to turn on the blink it should | ||||
* be used to disable the blink when restoring the original state. | * be used to disable the blink when restoring the original state. | ||||
**/ | **/ | ||||
void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) | void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) | ||||
{ | { | ||||
u32 current_mode = 0; | |||||
int i; | int i; | ||||
if (mode & ~I40E_LED_MODE_VALID) { | if (mode & ~I40E_LED_MODE_VALID) { | ||||
DEBUGOUT1("invalid mode passed in %X\n", mode); | DEBUGOUT1("invalid mode passed in %X\n", mode); | ||||
return; | return; | ||||
} | } | ||||
/* as per the documentation GPIO 22-29 are the LED | /* as per the documentation GPIO 22-29 are the LED | ||||
* GPIO pins named LED0..LED7 | * GPIO pins named LED0..LED7 | ||||
*/ | */ | ||||
for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { | for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { | ||||
u32 gpio_val = i40e_led_is_mine(hw, i); | u32 gpio_val = i40e_led_is_mine(hw, i); | ||||
if (!gpio_val) | if (!gpio_val) | ||||
continue; | continue; | ||||
/* ignore gpio LED src mode entries related to the activity | |||||
* LEDs | |||||
*/ | |||||
current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) | |||||
>> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); | |||||
switch (current_mode) { | |||||
case I40E_COMBINED_ACTIVITY: | |||||
case I40E_FILTER_ACTIVITY: | |||||
case I40E_MAC_ACTIVITY: | |||||
case I40E_LINK_ACTIVITY: | |||||
continue; | |||||
default: | |||||
break; | |||||
} | |||||
if (I40E_IS_X710TL_DEVICE(hw->device_id)) { | if (I40E_IS_X710TL_DEVICE(hw->device_id)) { | ||||
u32 pin_func = 0; | u32 pin_func = 0; | ||||
if (mode & I40E_FW_LED) | if (mode & I40E_FW_LED) | ||||
pin_func = I40E_PIN_FUNC_SDP; | pin_func = I40E_PIN_FUNC_SDP; | ||||
else | else | ||||
pin_func = I40E_PIN_FUNC_LED; | pin_func = I40E_PIN_FUNC_LED; | ||||
▲ Show 20 Lines • Show All 396 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, | ||||
else | else | ||||
hw_link_info->lse_enable = FALSE; | hw_link_info->lse_enable = FALSE; | ||||
if ((hw->mac.type == I40E_MAC_XL710) && | if ((hw->mac.type == I40E_MAC_XL710) && | ||||
(hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && | (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && | ||||
hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) | hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) | ||||
hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; | hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; | ||||
/* 'Get Link Status' response data structure from X722 FW has | |||||
* different format and does not contain this information | |||||
*/ | |||||
if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE && | if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE && | ||||
hw->mac.type != I40E_MAC_X722) { | hw->mac.type != I40E_MAC_X722) { | ||||
__le32 tmp; | __le32 tmp; | ||||
i40e_memcpy(&tmp, resp->link_type, sizeof(tmp), | i40e_memcpy(&tmp, resp->link_type, sizeof(tmp), | ||||
I40E_NONDMA_TO_NONDMA); | I40E_NONDMA_TO_NONDMA); | ||||
hw->phy.phy_types = LE32_TO_CPU(tmp); | hw->phy.phy_types = LE32_TO_CPU(tmp); | ||||
hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); | hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); | ||||
▲ Show 20 Lines • Show All 183 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, | ||||
cmd->command_flags = cmd_flags; | cmd->command_flags = cmd_flags; | ||||
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_hw_ver_ge | |||||
* @hw: pointer to the hw struct | |||||
* @maj: api major value | |||||
* @min: api minor value | |||||
* | |||||
* Assert whether current HW api version is greater/equal than provided. | |||||
**/ | |||||
static bool i40e_hw_ver_ge(struct i40e_hw *hw, u16 maj, u16 min) | |||||
{ | |||||
if (hw->aq.api_maj_ver > maj || | |||||
(hw->aq.api_maj_ver == maj && hw->aq.api_min_ver >= min)) | |||||
return TRUE; | |||||
return FALSE; | |||||
} | |||||
/** | |||||
* i40e_aq_add_vsi | * i40e_aq_add_vsi | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @vsi_ctx: pointer to a vsi context struct | * @vsi_ctx: pointer to a vsi context struct | ||||
* @cmd_details: pointer to command details structure or NULL | * @cmd_details: pointer to command details structure or NULL | ||||
* | * | ||||
* Add a VSI context to the hardware. | * Add a VSI context to the hardware. | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, | enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, | ||||
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, | ||||
enum i40e_status_code status; | enum i40e_status_code status; | ||||
u16 flags = 0; | u16 flags = 0; | ||||
i40e_fill_default_direct_cmd_desc(&desc, | i40e_fill_default_direct_cmd_desc(&desc, | ||||
i40e_aqc_opc_set_vsi_promiscuous_modes); | i40e_aqc_opc_set_vsi_promiscuous_modes); | ||||
if (set) { | if (set) { | ||||
flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; | flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; | ||||
if (rx_only_promisc && | if (rx_only_promisc && i40e_hw_ver_ge(hw, 1, 5)) | ||||
(((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || | flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; | ||||
(hw->aq.api_maj_ver > 1))) | |||||
flags |= I40E_AQC_SET_VSI_PROMISC_TX; | |||||
} | } | ||||
cmd->promiscuous_flags = CPU_TO_LE16(flags); | cmd->promiscuous_flags = CPU_TO_LE16(flags); | ||||
cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); | cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); | ||||
if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || | if (i40e_hw_ver_ge(hw, 1, 5)) | ||||
(hw->aq.api_maj_ver > 1)) | cmd->valid_flags |= | ||||
cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX); | CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); | ||||
cmd->seid = CPU_TO_LE16(seid); | cmd->seid = CPU_TO_LE16(seid); | ||||
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, | ||||
struct i40e_aqc_set_vsi_promiscuous_modes *cmd = | struct i40e_aqc_set_vsi_promiscuous_modes *cmd = | ||||
(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; | (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; | ||||
enum i40e_status_code status; | enum i40e_status_code status; | ||||
u16 flags = 0; | u16 flags = 0; | ||||
i40e_fill_default_direct_cmd_desc(&desc, | i40e_fill_default_direct_cmd_desc(&desc, | ||||
i40e_aqc_opc_set_vsi_promiscuous_modes); | i40e_aqc_opc_set_vsi_promiscuous_modes); | ||||
if (enable) | if (enable) { | ||||
flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; | flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; | ||||
if (i40e_hw_ver_ge(hw, 1, 5)) | |||||
flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; | |||||
} | |||||
cmd->promiscuous_flags = CPU_TO_LE16(flags); | cmd->promiscuous_flags = CPU_TO_LE16(flags); | ||||
cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); | cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); | ||||
if (i40e_hw_ver_ge(hw, 1, 5)) | |||||
cmd->valid_flags |= | |||||
CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); | |||||
cmd->seid = CPU_TO_LE16(seid); | cmd->seid = CPU_TO_LE16(seid); | ||||
cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); | cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); | ||||
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | ||||
return status; | return status; | ||||
} | } | ||||
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, | ||||
cmd->seid = CPU_TO_LE16(seid); | cmd->seid = CPU_TO_LE16(seid); | ||||
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_get_vsi_params - get VSI configuration info | * i40e_aq_get_vsi_params - get VSI configuration info | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @vsi_ctx: pointer to a vsi context struct | * @vsi_ctx: pointer to a vsi context struct | ||||
* @cmd_details: pointer to command details structure or NULL | * @cmd_details: pointer to command details structure or NULL | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, | enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, | ||||
struct i40e_vsi_context *vsi_ctx, | struct i40e_vsi_context *vsi_ctx, | ||||
struct i40e_asq_cmd_details *cmd_details) | struct i40e_asq_cmd_details *cmd_details) | ||||
{ | { | ||||
▲ Show 20 Lines • Show All 243 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up) | ||||
} | } | ||||
*link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; | *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_updatelink_status - update status of the HW network link | * i40e_update_link_info - update status of the HW network link | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw) | enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw) | ||||
{ | { | ||||
struct i40e_aq_get_phy_abilities_resp abilities; | struct i40e_aq_get_phy_abilities_resp abilities; | ||||
enum i40e_status_code status = I40E_SUCCESS; | enum i40e_status_code status = I40E_SUCCESS; | ||||
status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); | status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); | ||||
if (status) | if (status) | ||||
return status; | return status; | ||||
/* extra checking needed to ensure link info to user is timely */ | /* extra checking needed to ensure link info to user is timely */ | ||||
if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && | if (((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && | ||||
((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || | ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || | ||||
!(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { | !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) || | ||||
status = i40e_aq_get_phy_capabilities(hw, FALSE, false, | hw->mac.type == I40E_MAC_X722) { | ||||
status = i40e_aq_get_phy_capabilities(hw, FALSE, | |||||
hw->mac.type == | |||||
I40E_MAC_X722, | |||||
&abilities, NULL); | &abilities, NULL); | ||||
if (status) | if (status) | ||||
return status; | return status; | ||||
if (abilities.fec_cfg_curr_mod_ext_info & | if (abilities.fec_cfg_curr_mod_ext_info & | ||||
I40E_AQ_ENABLE_FEC_AUTO) | I40E_AQ_ENABLE_FEC_AUTO) | ||||
hw->phy.link_info.req_fec_info = | hw->phy.link_info.req_fec_info = | ||||
(I40E_AQ_REQUEST_FEC_KR | | (I40E_AQ_REQUEST_FEC_KR | | ||||
▲ Show 20 Lines • Show All 741 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw, | ||||
cmd->element_count = CPU_TO_LE16(element_count); | cmd->element_count = CPU_TO_LE16(element_count); | ||||
cmd->cmd_flags = CPU_TO_LE16(cmd_flags); | cmd->cmd_flags = CPU_TO_LE16(cmd_flags); | ||||
status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); | status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_aq_nvm_update_in_process | |||||
* @hw: pointer to the hw struct | |||||
* @update_flow_state: True indicates that update flow starts, FALSE that ends | |||||
* @cmd_details: pointer to command details structure or NULL | |||||
* | |||||
* Indicate NVM update in process. | |||||
**/ | |||||
enum i40e_status_code i40e_aq_nvm_update_in_process(struct i40e_hw *hw, | |||||
bool update_flow_state, | |||||
struct i40e_asq_cmd_details *cmd_details) | |||||
{ | |||||
struct i40e_aq_desc desc; | |||||
struct i40e_aqc_nvm_update_in_process *cmd = | |||||
(struct i40e_aqc_nvm_update_in_process *)&desc.params.raw; | |||||
enum i40e_status_code status; | |||||
i40e_fill_default_direct_cmd_desc(&desc, | |||||
i40e_aqc_opc_nvm_update_in_process); | |||||
cmd->command = I40E_AQ_UPDATE_FLOW_END; | |||||
if (update_flow_state) | |||||
cmd->command |= I40E_AQ_UPDATE_FLOW_START; | |||||
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |||||
return status; | |||||
} | |||||
/** | |||||
* i40e_aq_min_rollback_rev_update - triggers an ow after update | |||||
* @hw: pointer to the hw struct | |||||
* @mode: opt-in mode, 1b for single module update, 0b for bulk update | |||||
* @module: module to be updated. Ignored if mode is 0b | |||||
* @min_rrev: value of the new minimal version. Ignored if mode is 0b | |||||
* @cmd_details: pointer to command details structure or NULL | |||||
**/ | |||||
enum i40e_status_code | |||||
i40e_aq_min_rollback_rev_update(struct i40e_hw *hw, u8 mode, u8 module, | |||||
u32 min_rrev, | |||||
struct i40e_asq_cmd_details *cmd_details) | |||||
{ | |||||
struct i40e_aq_desc desc; | |||||
struct i40e_aqc_rollback_revision_update *cmd = | |||||
(struct i40e_aqc_rollback_revision_update *)&desc.params.raw; | |||||
enum i40e_status_code status; | |||||
i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rollback_revision_update); | |||||
cmd->optin_mode = mode; | |||||
cmd->module_selected = module; | |||||
cmd->min_rrev = min_rrev; | |||||
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |||||
return status; | |||||
} | |||||
/** | |||||
* i40e_aq_oem_post_update - triggers an OEM specific flow after update | * i40e_aq_oem_post_update - triggers an OEM specific flow after update | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @buff: buffer for result | * @buff: buffer for result | ||||
* @buff_size: buffer size | * @buff_size: buffer size | ||||
* @cmd_details: pointer to command details structure or NULL | * @cmd_details: pointer to command details structure or NULL | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw, | enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw, | ||||
void *buff, u16 buff_size, | void *buff, u16 buff_size, | ||||
▲ Show 20 Lines • Show All 315 Lines • ▼ Show 20 Lines | case I40E_AQ_CAP_ID_FLOW_DIRECTOR: | ||||
"HW Capability: Guaranteed FD filters = %d\n", | "HW Capability: Guaranteed FD filters = %d\n", | ||||
p->fd_filters_guaranteed); | p->fd_filters_guaranteed); | ||||
break; | break; | ||||
case I40E_AQ_CAP_ID_WSR_PROT: | case I40E_AQ_CAP_ID_WSR_PROT: | ||||
p->wr_csr_prot = (u64)number; | p->wr_csr_prot = (u64)number; | ||||
p->wr_csr_prot |= (u64)logical_id << 32; | p->wr_csr_prot |= (u64)logical_id << 32; | ||||
i40e_debug(hw, I40E_DEBUG_INIT, | i40e_debug(hw, I40E_DEBUG_INIT, | ||||
"HW Capability: wr_csr_prot = 0x%llX\n\n", | "HW Capability: wr_csr_prot = 0x%llX\n\n", | ||||
(p->wr_csr_prot & 0xffff)); | (unsigned long long)(p->wr_csr_prot & 0xffff)); | ||||
break; | break; | ||||
case I40E_AQ_CAP_ID_DIS_UNUSED_PORTS: | |||||
p->dis_unused_ports = (bool)number; | |||||
i40e_debug(hw, I40E_DEBUG_INIT, | |||||
"HW Capability: dis_unused_ports = %d\n\n", | |||||
p->dis_unused_ports); | |||||
break; | |||||
case I40E_AQ_CAP_ID_NVM_MGMT: | case I40E_AQ_CAP_ID_NVM_MGMT: | ||||
if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) | if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) | ||||
p->sec_rev_disabled = TRUE; | p->sec_rev_disabled = TRUE; | ||||
if (number & I40E_NVM_MGMT_UPDATE_DISABLED) | if (number & I40E_NVM_MGMT_UPDATE_DISABLED) | ||||
p->update_disabled = TRUE; | p->update_disabled = TRUE; | ||||
break; | break; | ||||
case I40E_AQ_CAP_ID_WOL_AND_PROXY: | case I40E_AQ_CAP_ID_WOL_AND_PROXY: | ||||
hw->num_wol_proxy_filters = (u16)number; | hw->num_wol_proxy_filters = (u16)number; | ||||
▲ Show 20 Lines • Show All 178 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, | ||||
status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); | status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); | ||||
i40e_aq_update_nvm_exit: | i40e_aq_update_nvm_exit: | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_aq_nvm_progress | |||||
* @hw: pointer to the hw struct | |||||
* @progress: pointer to progress returned from AQ | |||||
* @cmd_details: pointer to command details structure or NULL | |||||
* | |||||
* Gets progress of flash rearrangement process | |||||
**/ | |||||
enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress, | |||||
struct i40e_asq_cmd_details *cmd_details) | |||||
{ | |||||
enum i40e_status_code status; | |||||
struct i40e_aq_desc desc; | |||||
DEBUGFUNC("i40e_aq_nvm_progress"); | |||||
i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress); | |||||
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |||||
*progress = desc.params.raw[0]; | |||||
return status; | |||||
} | |||||
/** | |||||
* i40e_aq_get_lldp_mib | * i40e_aq_get_lldp_mib | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @bridge_type: type of bridge requested | * @bridge_type: type of bridge requested | ||||
* @mib_type: Local, Remote or both Local and Remote MIBs | * @mib_type: Local, Remote or both Local and Remote MIBs | ||||
* @buff: pointer to a user supplied buffer to store the MIB block | * @buff: pointer to a user supplied buffer to store the MIB block | ||||
* @buff_size: size of the buffer (in bytes) | * @buff_size: size of the buffer (in bytes) | ||||
* @local_len : length of the returned Local LLDP MIB | * @local_len : length of the returned Local LLDP MIB | ||||
* @remote_len: length of the returned Remote LLDP MIB | * @remote_len: length of the returned Remote LLDP MIB | ||||
▲ Show 20 Lines • Show All 361 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, | ||||
cmd->index = index; | cmd->index = index; | ||||
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_aq_get_switch_resource_alloc (0x0204) | * i40e_aq_get_switch_resource_alloc - command (0x0204) to get allocations | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @num_entries: pointer to u8 to store the number of resource entries returned | * @num_entries: pointer to u8 to store the number of resource entries returned | ||||
* @buf: pointer to a user supplied buffer. This buffer must be large enough | * @buf: pointer to a user supplied buffer. This buffer must be large enough | ||||
* to store the resource information for all resource types. Each | * to store the resource information for all resource types. Each | ||||
* resource type is a i40e_aqc_switch_resource_alloc_data structure. | * resource type is a i40e_aqc_switch_resource_alloc_data structure. | ||||
* @count: size, in bytes, of the buffer provided | * @count: size, in bytes, of the buffer provided | ||||
* @cmd_details: pointer to command details structure or NULL | * @cmd_details: pointer to command details structure or NULL | ||||
* | * | ||||
▲ Show 20 Lines • Show All 2,095 Lines • ▼ Show 20 Lines | |||||
{ | { | ||||
u8 port_num = (u8)hw->func_caps.mdio_port_num; | u8 port_num = (u8)hw->func_caps.mdio_port_num; | ||||
u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); | u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); | ||||
return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; | return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; | ||||
} | } | ||||
/** | /** | ||||
* i40e_blink_phy_led | * i40e_blink_phy_link_led | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @time: time how long led will blinks in secs | * @time: time how long led will blinks in secs | ||||
* @interval: gap between LED on and off in msecs | * @interval: gap between LED on and off in msecs | ||||
* | * | ||||
* Blinks PHY link LED | * Blinks PHY link LED | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw, | enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw, | ||||
u32 time, u32 interval) | u32 time, u32 interval) | ||||
▲ Show 20 Lines • Show All 220 Lines • ▼ Show 20 Lines | |||||
* | * | ||||
* Read LPI state directly from external PHY register or from MAC | * Read LPI state directly from external PHY register or from MAC | ||||
* register, depending on device ID and current link speed. | * register, depending on device ID and current link speed. | ||||
*/ | */ | ||||
enum i40e_status_code i40e_get_phy_lpi_status(struct i40e_hw *hw, | enum i40e_status_code i40e_get_phy_lpi_status(struct i40e_hw *hw, | ||||
struct i40e_hw_port_stats *stat) | struct i40e_hw_port_stats *stat) | ||||
{ | { | ||||
enum i40e_status_code ret = I40E_SUCCESS; | enum i40e_status_code ret = I40E_SUCCESS; | ||||
bool eee_mrvl_phy; | |||||
bool eee_bcm_phy; | |||||
u32 val; | u32 val; | ||||
stat->rx_lpi_status = 0; | stat->rx_lpi_status = 0; | ||||
stat->tx_lpi_status = 0; | stat->tx_lpi_status = 0; | ||||
if ((hw->device_id == I40E_DEV_ID_10G_BASE_T_BC || | eee_bcm_phy = | ||||
(hw->device_id == I40E_DEV_ID_10G_BASE_T_BC || | |||||
hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) && | hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) && | ||||
(hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB || | (hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB || | ||||
hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB)) { | hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB); | ||||
eee_mrvl_phy = | |||||
hw->device_id == I40E_DEV_ID_1G_BASE_T_X722; | |||||
if (eee_bcm_phy || eee_mrvl_phy) { | |||||
// read Clause 45 PCS Status 1 register | |||||
ret = i40e_aq_get_phy_register(hw, | ret = i40e_aq_get_phy_register(hw, | ||||
I40E_AQ_PHY_REG_ACCESS_EXTERNAL, | I40E_AQ_PHY_REG_ACCESS_EXTERNAL, | ||||
I40E_BCM_PHY_PCS_STATUS1_PAGE, | I40E_BCM_PHY_PCS_STATUS1_PAGE, | ||||
TRUE, | TRUE, | ||||
I40E_BCM_PHY_PCS_STATUS1_REG, | I40E_BCM_PHY_PCS_STATUS1_REG, | ||||
&val, NULL); | &val, NULL); | ||||
if (ret != I40E_SUCCESS) | if (ret != I40E_SUCCESS) | ||||
▲ Show 20 Lines • Show All 575 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw, | ||||
status = i40e_asq_send_command(hw, &desc, proxy_config, | status = i40e_asq_send_command(hw, &desc, proxy_config, | ||||
sizeof(struct i40e_aqc_arp_proxy_data), | sizeof(struct i40e_aqc_arp_proxy_data), | ||||
cmd_details); | cmd_details); | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_aq_opc_set_ns_proxy_table_entry | * i40e_aq_set_ns_proxy_table_entry | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @ns_proxy_table_entry: pointer to NS table entry command struct | * @ns_proxy_table_entry: pointer to NS table entry command struct | ||||
* @cmd_details: pointer to command details | * @cmd_details: pointer to command details | ||||
* | * | ||||
* Set IPv6 Neighbor Solicitation (NS) protocol offload parameters | * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters | ||||
* from pre-populated i40e_aqc_ns_proxy_data struct | * from pre-populated i40e_aqc_ns_proxy_data struct | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw, | enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw, | ||||
▲ Show 20 Lines • Show All 143 Lines • Show Last 20 Lines |