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sys/dev/ixl/i40e_type.h
Show First 20 Lines • Show All 341 Lines • ▼ Show 20 Lines | |||||
#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \ | #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \ | ||||
I40E_PHY_TYPE_OFFSET) | I40E_PHY_TYPE_OFFSET) | ||||
#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \ | #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \ | ||||
I40E_PHY_TYPE_OFFSET) | I40E_PHY_TYPE_OFFSET) | ||||
#define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \ | #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \ | ||||
I40E_PHY_TYPE_OFFSET) | I40E_PHY_TYPE_OFFSET) | ||||
#define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \ | #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \ | ||||
I40E_PHY_TYPE_OFFSET) | I40E_PHY_TYPE_OFFSET) | ||||
/* Offset for 2.5G/5G PHY Types value to bit number conversion */ | #define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | ||||
#define I40E_PHY_TYPE_OFFSET2 (-10) | #define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T) | ||||
#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \ | |||||
I40E_PHY_TYPE_OFFSET2) | |||||
#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \ | |||||
I40E_PHY_TYPE_OFFSET2) | |||||
#define I40E_HW_CAP_MAX_GPIO 30 | #define I40E_HW_CAP_MAX_GPIO 30 | ||||
#define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 | #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 | ||||
#define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 | #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 | ||||
enum i40e_acpi_programming_method { | enum i40e_acpi_programming_method { | ||||
I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0, | I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0, | ||||
I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1 | I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1 | ||||
}; | }; | ||||
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines | #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2 | ||||
u32 led_pin_num; | u32 led_pin_num; | ||||
u32 sdp_pin_num; | u32 sdp_pin_num; | ||||
u32 mdio_port_num; | u32 mdio_port_num; | ||||
u32 mdio_port_mode; | u32 mdio_port_mode; | ||||
u8 rx_buf_chain_len; | u8 rx_buf_chain_len; | ||||
u32 enabled_tcmap; | u32 enabled_tcmap; | ||||
u32 maxtc; | u32 maxtc; | ||||
u64 wr_csr_prot; | u64 wr_csr_prot; | ||||
bool dis_unused_ports; | |||||
bool apm_wol_support; | bool apm_wol_support; | ||||
enum i40e_acpi_programming_method acpi_prog_method; | enum i40e_acpi_programming_method acpi_prog_method; | ||||
bool proxy_support; | bool proxy_support; | ||||
}; | }; | ||||
struct i40e_mac_info { | struct i40e_mac_info { | ||||
enum i40e_mac_type type; | enum i40e_mac_type type; | ||||
u8 addr[ETH_ALEN]; | u8 addr[ETH_ALEN]; | ||||
▲ Show 20 Lines • Show All 516 Lines • ▼ Show 20 Lines | enum i40e_rx_l2_ptype { | ||||
I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, | I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, | ||||
I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, | I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, | ||||
I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, | I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, | ||||
I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, | I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, | ||||
I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, | I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, | ||||
I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, | I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, | ||||
I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, | I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, | ||||
I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, | I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, | ||||
I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153 | I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153, | ||||
I40E_RX_PTYPE_PARSER_ABORTED = 255 | |||||
}; | }; | ||||
struct i40e_rx_ptype_decoded { | struct i40e_rx_ptype_decoded { | ||||
u32 ptype:8; | u32 ptype:8; | ||||
u32 known:1; | u32 known:1; | ||||
u32 outer_ip:1; | u32 outer_ip:1; | ||||
u32 outer_ip_ver:1; | u32 outer_ip_ver:1; | ||||
u32 outer_frag:1; | u32 outer_frag:1; | ||||
▲ Show 20 Lines • Show All 559 Lines • ▼ Show 20 Lines | |||||
#define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 | #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 | ||||
#define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 | #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 | ||||
#define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 | #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 | ||||
#define I40E_SR_EMP_SR_SETTINGS_PTR 0x48 | #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48 | ||||
#define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49 | #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49 | ||||
#define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D | #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D | ||||
#define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E | #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E | ||||
#define I40E_SR_5TH_FREE_PROVISION_AREA_PTR 0x50 | #define I40E_SR_5TH_FREE_PROVISION_AREA_PTR 0x50 | ||||
#define I40E_SR_PRESERVATION_RULES_PTR 0x70 | |||||
#define I40E_FPK_SR_5TH_FREE_PROVISION_AREA_PTR 0x71 | |||||
#define I40E_SR_6TH_FREE_PROVISION_AREA_PTR 0x71 | |||||
/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ | /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ | ||||
#define I40E_SR_VPD_MODULE_MAX_SIZE 1024 | #define I40E_SR_VPD_MODULE_MAX_SIZE 1024 | ||||
#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 | #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 | ||||
#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 | #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 | ||||
#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) | #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) | ||||
#define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5) | #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5) | ||||
#define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) | #define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) | ||||
▲ Show 20 Lines • Show All 153 Lines • ▼ Show 20 Lines | |||||
#define I40E_L3_V6_DST_SHIFT 35 | #define I40E_L3_V6_DST_SHIFT 35 | ||||
#define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT) | #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT) | ||||
#define I40E_L4_SRC_SHIFT 34 | #define I40E_L4_SRC_SHIFT 34 | ||||
#define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT) | #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT) | ||||
#define I40E_L4_DST_SHIFT 33 | #define I40E_L4_DST_SHIFT 33 | ||||
#define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT) | #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT) | ||||
#define I40E_VERIFY_TAG_SHIFT 31 | #define I40E_VERIFY_TAG_SHIFT 31 | ||||
#define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT) | #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT) | ||||
#define I40E_VLAN_SRC_SHIFT 55 | |||||
#define I40E_VLAN_SRC_MASK (0x1ULL << I40E_VLAN_SRC_SHIFT) | |||||
#define I40E_FLEX_50_SHIFT 13 | #define I40E_FLEX_50_SHIFT 13 | ||||
#define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT) | #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT) | ||||
#define I40E_FLEX_51_SHIFT 12 | #define I40E_FLEX_51_SHIFT 12 | ||||
#define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT) | #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT) | ||||
#define I40E_FLEX_52_SHIFT 11 | #define I40E_FLEX_52_SHIFT 11 | ||||
#define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT) | #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT) | ||||
#define I40E_FLEX_53_SHIFT 10 | #define I40E_FLEX_53_SHIFT 10 | ||||
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