Differential D31565 Diff 93767 sys/dev/ixl/i40e_adminq_cmd.h

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sys/dev/ixl/i40e_adminq_cmd.h

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/* This header file defines the i40e Admin Queue commands and is shared between		/* This header file defines the i40e Admin Queue commands and is shared between
* i40e Firmware and Software.		* i40e Firmware and Software.
*		*
* This file needs to comply with the Linux Kernel coding style.		* This file needs to comply with the Linux Kernel coding style.
*/		*/


#define I40E_FW_API_VERSION_MAJOR 0x0001		#define I40E_FW_API_VERSION_MAJOR 0x0001
#define I40E_FW_API_VERSION_MINOR_X722 0x000A		#define I40E_FW_API_VERSION_MINOR_X722 0x000C
#define I40E_FW_API_VERSION_MINOR_X710 0x000A		#define I40E_FW_API_VERSION_MINOR_X710 0x000E

#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \		#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
I40E_FW_API_VERSION_MINOR_X710 : \		I40E_FW_API_VERSION_MINOR_X710 : \
I40E_FW_API_VERSION_MINOR_X722)		I40E_FW_API_VERSION_MINOR_X722)

/* API version 1.7 implements additional link and PHY-specific APIs */		/* API version 1.7 implements additional link and PHY-specific APIs */
#define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007		#define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
/* API version 1.9 for X722 implements additional link and PHY-specific APIs */		/* API version 1.9 for X722 implements additional link and PHY-specific APIs */
▲ Show 20 Lines • Show All 206 Lines • ▼ Show 20 Lines	enum i40e_admin_queue_opc {
i40e_aqc_opc_get_phy_register = 0x0629,		i40e_aqc_opc_get_phy_register = 0x0629,

/* NVM commands */		/* NVM commands */
i40e_aqc_opc_nvm_read = 0x0701,		i40e_aqc_opc_nvm_read = 0x0701,
i40e_aqc_opc_nvm_erase = 0x0702,		i40e_aqc_opc_nvm_erase = 0x0702,
i40e_aqc_opc_nvm_update = 0x0703,		i40e_aqc_opc_nvm_update = 0x0703,
i40e_aqc_opc_nvm_config_read = 0x0704,		i40e_aqc_opc_nvm_config_read = 0x0704,
i40e_aqc_opc_nvm_config_write = 0x0705,		i40e_aqc_opc_nvm_config_write = 0x0705,
i40e_aqc_opc_nvm_progress = 0x0706,		i40e_aqc_opc_nvm_update_in_process = 0x0706,
		i40e_aqc_opc_rollback_revision_update = 0x0707,
i40e_aqc_opc_oem_post_update = 0x0720,		i40e_aqc_opc_oem_post_update = 0x0720,
i40e_aqc_opc_thermal_sensor = 0x0721,		i40e_aqc_opc_thermal_sensor = 0x0721,

/* virtualization commands */		/* virtualization commands */
i40e_aqc_opc_send_msg_to_pf = 0x0801,		i40e_aqc_opc_send_msg_to_pf = 0x0801,
i40e_aqc_opc_send_msg_to_vf = 0x0802,		i40e_aqc_opc_send_msg_to_vf = 0x0802,
i40e_aqc_opc_send_msg_to_peer = 0x0803,		i40e_aqc_opc_send_msg_to_peer = 0x0803,

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#define I40E_AQ_CAP_ID_VF_MSIX 0x0044		#define I40E_AQ_CAP_ID_VF_MSIX 0x0044
#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045		#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
#define I40E_AQ_CAP_ID_1588 0x0046		#define I40E_AQ_CAP_ID_1588 0x0046
#define I40E_AQ_CAP_ID_IWARP 0x0051		#define I40E_AQ_CAP_ID_IWARP 0x0051
#define I40E_AQ_CAP_ID_LED 0x0061		#define I40E_AQ_CAP_ID_LED 0x0061
#define I40E_AQ_CAP_ID_SDP 0x0062		#define I40E_AQ_CAP_ID_SDP 0x0062
#define I40E_AQ_CAP_ID_MDIO 0x0063		#define I40E_AQ_CAP_ID_MDIO 0x0063
#define I40E_AQ_CAP_ID_WSR_PROT 0x0064		#define I40E_AQ_CAP_ID_WSR_PROT 0x0064
		#define I40E_AQ_CAP_ID_DIS_UNUSED_PORTS 0x0067
#define I40E_AQ_CAP_ID_NVM_MGMT 0x0080		#define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
#define I40E_AQ_CAP_ID_FLEX10 0x00F1		#define I40E_AQ_CAP_ID_FLEX10 0x00F1
#define I40E_AQ_CAP_ID_CEM 0x00F2		#define I40E_AQ_CAP_ID_CEM 0x00F2

/* Set CPPM Configuration (direct 0x0103) */		/* Set CPPM Configuration (direct 0x0103) */
struct i40e_aqc_cppm_configuration {		struct i40e_aqc_cppm_configuration {
__le16 command_flags;		__le16 command_flags;
#define I40E_AQ_CPPM_EN_LTRC 0x0800		#define I40E_AQ_CPPM_EN_LTRC 0x0800
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/* Set Switch Configuration (direct 0x0205) */		/* Set Switch Configuration (direct 0x0205) */
struct i40e_aqc_set_switch_config {		struct i40e_aqc_set_switch_config {
__le16 flags;		__le16 flags;
/* flags used for both fields below */		/* flags used for both fields below */
#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001		#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002		#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
#define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004		#define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004
		#define I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN 0x0008
__le16 valid_flags;		__le16 valid_flags;
/* The ethertype in switch_tag is dropped on ingress and used		/* The ethertype in switch_tag is dropped on ingress and used
* internally by the switch. Set this to zero for the default		* internally by the switch. Set this to zero for the default
* of 0x88a8 (802.1ad). Should be zero for firmware API		* of 0x88a8 (802.1ad). Should be zero for firmware API
* versions lower than 1.7.		* versions lower than 1.7.
*/		*/
__le16 switch_tag;		__le16 switch_tag;
/* The ethertypes in first_tag and second_tag are used to		/* The ethertypes in first_tag and second_tag are used to
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines	#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
/* security section */		/* security section */
u8 sec_flags;		u8 sec_flags;
#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01		#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02		#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04		#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
u8 sec_reserved;		u8 sec_reserved;
/* VLAN section */		/* VLAN section */
__le16 pvid; /* VLANS include priority bits */		__le16 pvid; /* VLANS include priority bits */
__le16 fcoe_pvid;		__le16 outer_vlan;
u8 port_vlan_flags;		u8 port_vlan_flags;
#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00		#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \		#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
I40E_AQ_VSI_PVLAN_MODE_SHIFT)		I40E_AQ_VSI_PVLAN_MODE_SHIFT)
#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01		#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02		#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03		#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04		#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03		#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \		#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
I40E_AQ_VSI_PVLAN_EMOD_SHIFT)		I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0		#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08		#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10		#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18		#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
u8 pvlan_reserved[3];		u8 outer_vlan_flags;
		#define I40E_AQ_VSI_OVLAN_MODE_SHIFT 0x00
		#define I40E_AQ_VSI_OVLAN_MODE_MASK (0x03 << \
		I40E_AQ_VSI_OVLAN_MODE_SHIFT)
		#define I40E_AQ_VSI_OVLAN_MODE_UNTAGGED 0x01
		#define I40E_AQ_VSI_OVLAN_MODE_TAGGED 0x02
		#define I40E_AQ_VSI_OVLAN_MODE_ALL 0x03
		#define I40E_AQ_VSI_OVLAN_INSERT_PVID 0x04
		#define I40E_AQ_VSI_OVLAN_EMOD_SHIFT 0x03
		#define I40E_AQ_VSI_OVLAN_EMOD_MASK (0x03 <<\
		I40E_AQ_VSI_OVLAN_EMOD_SHIFT)
		#define I40E_AQ_VSI_OVLAN_EMOD_SHOW_ALL 0x00
		#define I40E_AQ_VSI_OVLAN_EMOD_SHOW_UP 0x01
		#define I40E_AQ_VSI_OVLAN_EMOD_HIDE_ALL 0x02
		#define I40E_AQ_VSI_OVLAN_EMOD_NOTHING 0x03
		#define I40E_AQ_VSI_OVLAN_CTRL_ENA 0x04

		u8 pvlan_reserved[2];
/* ingress egress up sections */		/* ingress egress up sections */
__le32 ingress_table; /* bitmap, 3 bits per up */		__le32 ingress_table; /* bitmap, 3 bits per up */
#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0		#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \		#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)		I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3		#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \		#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)		I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
▲ Show 20 Lines • Show All 285 Lines • ▼ Show 20 Lines	struct i40e_aqc_set_vsi_promiscuous_modes {
__le16 promiscuous_flags;		__le16 promiscuous_flags;
__le16 valid_flags;		__le16 valid_flags;
/* flags used for both fields above */		/* flags used for both fields above */
#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01		#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02		#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04		#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
#define I40E_AQC_SET_VSI_DEFAULT 0x08		#define I40E_AQC_SET_VSI_DEFAULT 0x08
#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10		#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
#define I40E_AQC_SET_VSI_PROMISC_TX 0x8000		#define I40E_AQC_SET_VSI_PROMISC_RX_ONLY 0x8000
__le16 seid;		__le16 seid;
#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF		#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
__le16 vlan_tag;		__le16 vlan_tag;
#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF		#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000		#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
u8 reserved[8];		u8 reserved[8];
};		};

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/* 0x0005 reserved */		/* 0x0005 reserved */
#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006		#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
/* 0x0007 reserved */		/* 0x0007 reserved */
/* 0x0008 reserved */		/* 0x0008 reserved */
#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009		#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A		#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B		#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C		#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
		#define I40E_AQC_ADD_CLOUD_FILTER_OIP1 0x0010
		#define I40E_AQC_ADD_CLOUD_FILTER_OIP2 0x0012
/* 0x000D reserved */		/* 0x000D reserved */
/* 0x000E reserved */		/* 0x000E reserved */
/* 0x000F reserved */		/* 0x000F reserved */
/* 0x0010 to 0x0017 is for custom filters */		/* 0x0010 to 0x0017 is for custom filters */
#define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */		#define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */
#define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */		#define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */
#define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */		#define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */

▲ Show 20 Lines • Show All 491 Lines • ▼ Show 20 Lines	enum i40e_aq_phy_type {
I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,		I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,		I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
I40E_PHY_TYPE_25GBASE_KR = 0x1F,		I40E_PHY_TYPE_25GBASE_KR = 0x1F,
I40E_PHY_TYPE_25GBASE_CR = 0x20,		I40E_PHY_TYPE_25GBASE_CR = 0x20,
I40E_PHY_TYPE_25GBASE_SR = 0x21,		I40E_PHY_TYPE_25GBASE_SR = 0x21,
I40E_PHY_TYPE_25GBASE_LR = 0x22,		I40E_PHY_TYPE_25GBASE_LR = 0x22,
I40E_PHY_TYPE_25GBASE_AOC = 0x23,		I40E_PHY_TYPE_25GBASE_AOC = 0x23,
I40E_PHY_TYPE_25GBASE_ACC = 0x24,		I40E_PHY_TYPE_25GBASE_ACC = 0x24,
I40E_PHY_TYPE_2_5GBASE_T = 0x30,		I40E_PHY_TYPE_2_5GBASE_T = 0x26,
I40E_PHY_TYPE_5GBASE_T = 0x31,		I40E_PHY_TYPE_5GBASE_T = 0x27,
		I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS = 0x30,
		I40E_PHY_TYPE_5GBASE_T_LINK_STATUS = 0x31,
I40E_PHY_TYPE_MAX,		I40E_PHY_TYPE_MAX,
I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,		I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
I40E_PHY_TYPE_EMPTY = 0xFE,		I40E_PHY_TYPE_EMPTY = 0xFE,
I40E_PHY_TYPE_DEFAULT = 0xFF,		I40E_PHY_TYPE_DEFAULT = 0xFF,
};		};

#define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) \| \		#define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) \| \
BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) \| \		BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) \| \
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#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08		#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10		#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
__le16 feature_options;		__le16 feature_options;
__le16 feature_selection;		__le16 feature_selection;
};		};

I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);		I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);

		/* NVM Update in Process (direct 0x0706) */
		struct i40e_aqc_nvm_update_in_process {
		u8 command;
		#define I40E_AQ_UPDATE_FLOW_END 0x0
		#define I40E_AQ_UPDATE_FLOW_START 0x1
		u8 reserved[15];
		};

		I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update_in_process);

struct i40e_aqc_nvm_config_data_immediate_field {		struct i40e_aqc_nvm_config_data_immediate_field {
__le32 field_id;		__le32 field_id;
__le32 field_value;		__le32 field_value;
__le16 field_options;		__le16 field_options;
__le16 reserved;		__le16 reserved;
};		};

I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);		I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);

		/* Minimal Rollback Revision Update (direct 0x0707) */
		struct i40e_aqc_rollback_revision_update {
		u8 optin_mode; /* bool */
		#define I40E_AQ_RREV_OPTIN_MODE 0x01
		u8 module_selected;
		#define I40E_AQ_RREV_MODULE_PCIE_ANALOG 0
		#define I40E_AQ_RREV_MODULE_PHY_ANALOG 1
		#define I40E_AQ_RREV_MODULE_OPTION_ROM 2
		#define I40E_AQ_RREV_MODULE_EMP_IMAGE 3
		#define I40E_AQ_RREV_MODULE_PE_IMAGE 4
		#define I40E_AQ_RREV_MODULE_PHY_PLL_O_CONFIGURATION 5
		#define I40E_AQ_RREV_MODULE_PHY_0_CONFIGURATION 6
		#define I40E_AQ_RREV_MODULE_PHY_PLL_1_CONFIGURATION 7
		#define I40E_AQ_RREV_MODULE_PHY_1_CONFIGURATION 8
		u8 reserved1[2];
		u32 min_rrev;
		u8 reserved2[8];
		};

		I40E_CHECK_CMD_LENGTH(i40e_aqc_rollback_revision_update);

/* OEM Post Update (indirect 0x0720)		/* OEM Post Update (indirect 0x0720)
* no command data struct used		* no command data struct used
*/		*/
struct i40e_aqc_nvm_oem_post_update {		struct i40e_aqc_nvm_oem_post_update {
#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01		#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
u8 sel_data;		u8 sel_data;
u8 reserved[7];		u8 reserved[7];
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