Differential D31261 Diff 93311 sys/arm64/arm64/exception.S

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sys/arm64/arm64/exception.S

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	.if \el == 0			.if \el == 0
	/* Apply the SSBD (CVE-2018-3639) workaround if needed */			/* Apply the SSBD (CVE-2018-3639) workaround if needed */
	ldr x1, [x18, #PC_SSBD]			ldr x1, [x18, #PC_SSBD]
	cbz x1, 1f			cbz x1, 1f
	mov w0, #1			mov w0, #1
	blr x1			blr x1
	1:			1:

				ldr x0, [x18, #PC_CURTHREAD]
				bl ptrauth_exit_el0

	ldr x0, [x18, #(PC_CURTHREAD)]			ldr x0, [x18, #(PC_CURTHREAD)]
	bl dbg_monitor_enter			bl dbg_monitor_enter
	msr daifclr, #8 /* Enable the debug exception */			msr daifclr, #8 /* Enable the debug exception */
	.endif			.endif
	/*			/*
	* For EL1, debug exceptions are conditionally unmasked in			* For EL1, debug exceptions are conditionally unmasked in
	* do_el1h_sync().			* do_el1h_sync().
	*/			*/
	.endm			.endm

	.macro restore_registers el			.macro restore_registers el
	.if \el == 1			.if \el == 1
	/*			/*
	* Disable interrupts and debug exceptions, x18 may change in the			* Disable interrupts and debug exceptions, x18 may change in the
	* interrupt exception handler. For EL0 exceptions, do_ast already			* interrupt exception handler. For EL0 exceptions, do_ast already
	* did this.			* did this.
	*/			*/
	msr daifset, #10			msr daifset, #10
	.endif			.endif
	.if \el == 0			.if \el == 0
	ldr x0, [x18, #PC_CURTHREAD]			ldr x0, [x18, #PC_CURTHREAD]
	mov x1, sp			mov x1, sp
	bl dbg_monitor_exit			bl dbg_monitor_exit

				ldr x0, [x18, #PC_CURTHREAD]
				bl ptrauth_enter_el0

	/* Remove the SSBD (CVE-2018-3639) workaround if needed */			/* Remove the SSBD (CVE-2018-3639) workaround if needed */
	ldr x1, [x18, #PC_SSBD]			ldr x1, [x18, #PC_SSBD]
	cbz x1, 1f			cbz x1, 1f
	mov w0, #0			mov w0, #0
	blr x1			blr x1
	1:			1:
	.endif			.endif
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