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sys/dev/pci/pci_dw.h
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#define DW_MSI_ADDR_HI 0x824 | #define DW_MSI_ADDR_HI 0x824 | ||||
#define DW_MSI_INTR0_ENABLE 0x828 | #define DW_MSI_INTR0_ENABLE 0x828 | ||||
#define DW_MSI_INTR0_MASK 0x82C | #define DW_MSI_INTR0_MASK 0x82C | ||||
#define DW_MSI_INTR0_STATUS 0x830 | #define DW_MSI_INTR0_STATUS 0x830 | ||||
#define DW_MISC_CONTROL_1 0x8BC | #define DW_MISC_CONTROL_1 0x8BC | ||||
#define DBI_RO_WR_EN (1 << 0) | #define DBI_RO_WR_EN (1 << 0) | ||||
/* Legacy (pre-4.80) iATU mode */ | |||||
#define DW_IATU_VIEWPORT 0x900 | #define DW_IATU_VIEWPORT 0x900 | ||||
#define IATU_REGION_INBOUND (1U << 31) | #define IATU_REGION_INBOUND (1U << 31) | ||||
#define IATU_REGION_INDEX(x) ((x) & 0x7) | #define IATU_REGION_INDEX(x) ((x) & 0x7) | ||||
#define DW_IATU_CTRL1 0x904 | #define DW_IATU_CTRL1 0x904 | ||||
#define IATU_CTRL1_TYPE(x) ((x) & 0x1F) | #define IATU_CTRL1_TYPE(x) ((x) & 0x1F) | ||||
#define IATU_CTRL1_TYPE_MEM 0x0 | #define IATU_CTRL1_TYPE_MEM 0x0 | ||||
#define IATU_CTRL1_TYPE_IO 0x2 | #define IATU_CTRL1_TYPE_IO 0x2 | ||||
#define IATU_CTRL1_TYPE_CFG0 0x4 | #define IATU_CTRL1_TYPE_CFG0 0x4 | ||||
#define IATU_CTRL1_TYPE_CFG1 0x5 | #define IATU_CTRL1_TYPE_CFG1 0x5 | ||||
#define DW_IATU_CTRL2 0x908 | #define DW_IATU_CTRL2 0x908 | ||||
#define IATU_CTRL2_REGION_EN (1U << 31) | #define IATU_CTRL2_REGION_EN (1U << 31) | ||||
#define DW_IATU_LWR_BASE_ADDR 0x90C | #define DW_IATU_LWR_BASE_ADDR 0x90C | ||||
#define DW_IATU_UPPER_BASE_ADDR 0x910 | #define DW_IATU_UPPER_BASE_ADDR 0x910 | ||||
#define DW_IATU_LIMIT_ADDR 0x914 | #define DW_IATU_LIMIT_ADDR 0x914 | ||||
#define DW_IATU_LWR_TARGET_ADDR 0x918 | #define DW_IATU_LWR_TARGET_ADDR 0x918 | ||||
#define DW_IATU_UPPER_TARGET_ADDR 0x91C | #define DW_IATU_UPPER_TARGET_ADDR 0x91C | ||||
/* Modern (4.80+) "unroll" iATU mode */ | |||||
#define DW_IATU_UR_STEP 0x200 | |||||
#define DW_IATU_UR_REG(r, n) (r) * DW_IATU_UR_STEP + IATU_UR_##n | |||||
#define IATU_UR_CTRL1 0x00 | |||||
#define IATU_UR_CTRL2 0x04 | |||||
#define IATU_UR_LWR_BASE_ADDR 0x08 | |||||
#define IATU_UR_UPPER_BASE_ADDR 0x0C | |||||
#define IATU_UR_LIMIT_ADDR 0x10 | |||||
#define IATU_UR_LWR_TARGET_ADDR 0x14 | |||||
#define IATU_UR_UPPER_TARGET_ADDR 0x18 | |||||
#define DW_DEFAULT_IATU_UR_DBI_OFFSET 0x300000 | |||||
#define DW_DEFAULT_IATU_UR_DBI_SIZE 0x1000 | |||||
struct pci_dw_softc { | struct pci_dw_softc { | ||||
struct ofw_pci_softc ofw_pci; /* Must be first */ | struct ofw_pci_softc ofw_pci; /* Must be first */ | ||||
/* Filled by attachement stub */ | /* Filled by attachement stub */ | ||||
struct resource *dbi_res; | struct resource *dbi_res; | ||||
/* pci_dw variables */ | /* pci_dw variables */ | ||||
device_t dev; | device_t dev; | ||||
phandle_t node; | phandle_t node; | ||||
struct mtx mtx; | struct mtx mtx; | ||||
struct resource *cfg_res; | struct resource *cfg_res; | ||||
struct ofw_pci_range io_range; | struct ofw_pci_range io_range; | ||||
struct ofw_pci_range *mem_ranges; | struct ofw_pci_range *mem_ranges; | ||||
int num_mem_ranges; | int num_mem_ranges; | ||||
bool coherent; | bool coherent; | ||||
bus_dma_tag_t dmat; | bus_dma_tag_t dmat; | ||||
int num_lanes; | int num_lanes; | ||||
int num_viewport; | int num_viewport; | ||||
struct resource *iatu_ur_res; /* NB: May be dbi_res */ | |||||
bus_addr_t iatu_ur_offset; | |||||
bus_size_t iatu_ur_size; | |||||
bus_addr_t cfg_pa; /* PA of config memoty */ | bus_addr_t cfg_pa; /* PA of config memoty */ | ||||
bus_size_t cfg_size; /* size of config region */ | bus_size_t cfg_size; /* size of config region */ | ||||
u_int bus_start; | u_int bus_start; | ||||
u_int bus_end; | u_int bus_end; | ||||
u_int root_bus; | u_int root_bus; | ||||
u_int sub_bus; | u_int sub_bus; | ||||
}; | }; | ||||
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