Differential D30889 Diff 91988 sys/dev/ice/ice_common.c

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sys/dev/ice/ice_common.c

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#define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M \|\		#define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M \|\
GLNVM_ULD_PCIER_DONE_1_M \|\		GLNVM_ULD_PCIER_DONE_1_M \|\
GLNVM_ULD_CORER_DONE_M \|\		GLNVM_ULD_CORER_DONE_M \|\
GLNVM_ULD_GLOBR_DONE_M \|\		GLNVM_ULD_GLOBR_DONE_M \|\
GLNVM_ULD_POR_DONE_M \|\		GLNVM_ULD_POR_DONE_M \|\
GLNVM_ULD_POR_DONE_1_M \|\		GLNVM_ULD_POR_DONE_1_M \|\
GLNVM_ULD_PCIER_DONE_2_M)		GLNVM_ULD_PCIER_DONE_2_M)

uld_mask = ICE_RESET_DONE_MASK;		uld_mask = ICE_RESET_DONE_MASK \| (hw->func_caps.common_cap.iwarp ?
		GLNVM_ULD_PE_DONE_M : 0);

/* Device is Active; check Global Reset processes are done */		/* Device is Active; check Global Reset processes are done */
for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {		for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
reg = rd32(hw, GLNVM_ULD) & uld_mask;		reg = rd32(hw, GLNVM_ULD) & uld_mask;
if (reg == uld_mask) {		if (reg == uld_mask) {
ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt);		ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt);
break;		break;
}		}
▲ Show 20 Lines • Show All 1,149 Lines • ▼ Show 20 Lines	case ICE_AQC_CAPS_NVM_MGMT:
ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,		ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
caps->nvm_unified_update);		caps->nvm_unified_update);
break;		break;
case ICE_AQC_CAPS_CEM:		case ICE_AQC_CAPS_CEM:
caps->mgmt_cem = (number == 1);		caps->mgmt_cem = (number == 1);
ice_debug(hw, ICE_DBG_INIT, "%s: mgmt_cem = %d\n", prefix,		ice_debug(hw, ICE_DBG_INIT, "%s: mgmt_cem = %d\n", prefix,
caps->mgmt_cem);		caps->mgmt_cem);
break;		break;
		case ICE_AQC_CAPS_IWARP:
		caps->iwarp = (number == 1);
		ice_debug(hw, ICE_DBG_INIT, "%s: iwarp = %d\n", prefix, caps->iwarp);
		break;
case ICE_AQC_CAPS_LED:		case ICE_AQC_CAPS_LED:
if (phys_id < ICE_MAX_SUPPORTED_GPIO_LED) {		if (phys_id < ICE_MAX_SUPPORTED_GPIO_LED) {
caps->led[phys_id] = true;		caps->led[phys_id] = true;
caps->led_pin_num++;		caps->led_pin_num++;
ice_debug(hw, ICE_DBG_INIT, "%s: led[%d] = 1\n", prefix, phys_id);		ice_debug(hw, ICE_DBG_INIT, "%s: led[%d] = 1\n", prefix, phys_id);
}		}
break;		break;
case ICE_AQC_CAPS_SDP:		case ICE_AQC_CAPS_SDP:
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines	ice_recalc_port_limited_caps(struct ice_hw hw, struct ice_hw_common_caps caps)
/* This assumes device capabilities are always scanned before function		/* This assumes device capabilities are always scanned before function
* capabilities during the initialization flow.		* capabilities during the initialization flow.
*/		*/
if (hw->dev_caps.num_funcs > 4) {		if (hw->dev_caps.num_funcs > 4) {
/* Max 4 TCs per port */		/* Max 4 TCs per port */
caps->maxtc = 4;		caps->maxtc = 4;
ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n",		ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n",
caps->maxtc);		caps->maxtc);
		if (caps->iwarp) {
		ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n");
		caps->iwarp = 0;
}		}

		/* print message only when processing device capabilities
		* during initialization.
		*/
		if (caps == &hw->dev_caps.common_cap)
		ice_info(hw, "RDMA functionality is not available with the current device configuration.\n");
}		}
		}

/**		/**
* ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps		* ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps
* @hw: pointer to the HW struct		* @hw: pointer to the HW struct
* @func_p: pointer to function capabilities structure		* @func_p: pointer to function capabilities structure
* @cap: pointer to the capability element to parse		* @cap: pointer to the capability element to parse
*		*
* Extract function capabilities for ICE_AQC_CAPS_VF.		* Extract function capabilities for ICE_AQC_CAPS_VF.
▲ Show 20 Lines • Show All 1,746 Lines • ▼ Show 20 Lines	#define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50

if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&		if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
is_tc_change && !flush_pipe)		is_tc_change && !flush_pipe)
*blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);		*blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);

return status;		return status;
}		}

		/**
		* ice_aq_add_rdma_qsets
		* @hw: pointer to the hardware structure
		* @num_qset_grps: Number of RDMA Qset groups
		* @qset_list: list of qset groups to be added
		* @buf_size: size of buffer for indirect command
		* @cd: pointer to command details structure or NULL
		*
		* Add Tx RDMA Qsets (0x0C33)
		*/
		enum ice_status
		ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps,
		struct ice_aqc_add_rdma_qset_data *qset_list,
		u16 buf_size, struct ice_sq_cd *cd)
		{
		struct ice_aqc_add_rdma_qset_data *list;
		struct ice_aqc_add_rdma_qset *cmd;
		struct ice_aq_desc desc;
		u16 i, sum_size = 0;

		ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);

		cmd = &desc.params.add_rdma_qset;

		ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset);

		if (!qset_list)
		return ICE_ERR_PARAM;

		if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS)
		return ICE_ERR_PARAM;

		for (i = 0, list = qset_list; i < num_qset_grps; i++) {
		u16 num_qsets = LE16_TO_CPU(list->num_qsets);

		sum_size += ice_struct_size(list, rdma_qsets, num_qsets);
		list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets +
		num_qsets);
		}

		if (buf_size != sum_size)
		return ICE_ERR_PARAM;

		desc.flags \|= CPU_TO_LE16(ICE_AQ_FLAG_RD);

		cmd->num_qset_grps = num_qset_grps;

		return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd);
		}

/* End of FW Admin Queue command wrappers */		/* End of FW Admin Queue command wrappers */

/**		/**
* ice_write_byte - write a byte to a packed context structure		* ice_write_byte - write a byte to a packed context structure
* @src_ctx: the context structure to read from		* @src_ctx: the context structure to read from
* @dest_ctx: the context to be written to		* @dest_ctx: the context to be written to
* @ce_info: a description of the struct to be filled		* @ce_info: a description of the struct to be filled
*/		*/
▲ Show 20 Lines • Show All 694 Lines • ▼ Show 20 Lines
* This function adds/updates the VSI LAN queues per TC.		* This function adds/updates the VSI LAN queues per TC.
*/		*/
enum ice_status		enum ice_status
ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,		ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
u16 *max_lanqs)		u16 *max_lanqs)
{		{
return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,		return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
ICE_SCHED_NODE_OWNER_LAN);		ICE_SCHED_NODE_OWNER_LAN);
		}

		/**
		* ice_cfg_vsi_rdma - configure the VSI RDMA queues
		* @pi: port information structure
		* @vsi_handle: software VSI handle
		* @tc_bitmap: TC bitmap
		* @max_rdmaqs: max RDMA queues array per TC
		*
		* This function adds/updates the VSI RDMA queues per TC.
		*/
		enum ice_status
		ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
		u16 *max_rdmaqs)
		{
		return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs,
		ICE_SCHED_NODE_OWNER_RDMA);
		}

		/**
		* ice_ena_vsi_rdma_qset
		* @pi: port information structure
		* @vsi_handle: software VSI handle
		* @tc: TC number
		* @rdma_qset: pointer to RDMA qset
		* @num_qsets: number of RDMA qsets
		* @qset_teid: pointer to qset node teids
		*
		* This function adds RDMA qset
		*/
		enum ice_status
		ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
		u16 rdma_qset, u16 num_qsets, u32 qset_teid)
		{
		struct ice_aqc_txsched_elem_data node = { 0 };
		struct ice_aqc_add_rdma_qset_data *buf;
		struct ice_sched_node *parent;
		enum ice_status status;
		struct ice_hw *hw;
		u16 i, buf_size;

		if (!pi \|\| pi->port_state != ICE_SCHED_PORT_STATE_READY)
		return ICE_ERR_CFG;
		hw = pi->hw;

		if (!ice_is_vsi_valid(hw, vsi_handle))
		return ICE_ERR_PARAM;

		buf_size = ice_struct_size(buf, rdma_qsets, num_qsets);
		buf = (struct ice_aqc_add_rdma_qset_data *)ice_malloc(hw, buf_size);
		if (!buf)
		return ICE_ERR_NO_MEMORY;
		ice_acquire_lock(&pi->sched_lock);

		parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
		ICE_SCHED_NODE_OWNER_RDMA);
		if (!parent) {
		status = ICE_ERR_PARAM;
		goto rdma_error_exit;
		}
		buf->parent_teid = parent->info.node_teid;
		node.parent_teid = parent->info.node_teid;

		buf->num_qsets = CPU_TO_LE16(num_qsets);
		for (i = 0; i < num_qsets; i++) {
		buf->rdma_qsets[i].tx_qset_id = CPU_TO_LE16(rdma_qset[i]);
		buf->rdma_qsets[i].info.valid_sections =
		ICE_AQC_ELEM_VALID_GENERIC \| ICE_AQC_ELEM_VALID_CIR \|
		ICE_AQC_ELEM_VALID_EIR;
		buf->rdma_qsets[i].info.generic = 0;
		buf->rdma_qsets[i].info.cir_bw.bw_profile_idx =
		CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);
		buf->rdma_qsets[i].info.cir_bw.bw_alloc =
		CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);
		buf->rdma_qsets[i].info.eir_bw.bw_profile_idx =
		CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);
		buf->rdma_qsets[i].info.eir_bw.bw_alloc =
		CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);
		}
		status = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL);
		if (status != ICE_SUCCESS) {
		ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n");
		goto rdma_error_exit;
		}
		node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
		for (i = 0; i < num_qsets; i++) {
		node.node_teid = buf->rdma_qsets[i].qset_teid;
		status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1,
		&node);
		if (status)
		break;
		qset_teid[i] = LE32_TO_CPU(node.node_teid);
		}
		rdma_error_exit:
		ice_release_lock(&pi->sched_lock);
		ice_free(hw, buf);
		return status;
		}

		/**
		* ice_dis_vsi_rdma_qset - free RDMA resources
		* @pi: port_info struct
		* @count: number of RDMA qsets to free
		* @qset_teid: TEID of qset node
		* @q_id: list of queue IDs being disabled
		*/
		enum ice_status
		ice_dis_vsi_rdma_qset(struct ice_port_info pi, u16 count, u32 qset_teid,
		u16 *q_id)
		{
		struct ice_aqc_dis_txq_item *qg_list;
		enum ice_status status = ICE_SUCCESS;
		struct ice_hw *hw;
		u16 qg_size;
		int i;

		if (!pi \|\| pi->port_state != ICE_SCHED_PORT_STATE_READY)
		return ICE_ERR_CFG;

		hw = pi->hw;

		qg_size = ice_struct_size(qg_list, q_id, 1);
		qg_list = (struct ice_aqc_dis_txq_item *)ice_malloc(hw, qg_size);
		if (!qg_list)
		return ICE_ERR_NO_MEMORY;

		ice_acquire_lock(&pi->sched_lock);

		for (i = 0; i < count; i++) {
		struct ice_sched_node *node;

		node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]);
		if (!node)
		continue;

		qg_list->parent_teid = node->info.parent_teid;
		qg_list->num_qs = 1;
		qg_list->q_id[0] =
		CPU_TO_LE16(q_id[i] \|
		ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET);

		status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size,
		ICE_NO_RESET, 0, NULL);
		if (status)
		break;

		ice_free_sched_node(pi, node);
		}

		ice_release_lock(&pi->sched_lock);
		ice_free(hw, qg_list);
		return status;
}		}

/**		/**
* ice_is_main_vsi - checks whether the VSI is main VSI		* ice_is_main_vsi - checks whether the VSI is main VSI
* @hw: pointer to the HW struct		* @hw: pointer to the HW struct
* @vsi_handle: VSI handle		* @vsi_handle: VSI handle
*		*
* Checks whether the VSI is the main VSI (the first PF VSI created on		* Checks whether the VSI is the main VSI (the first PF VSI created on
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